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tg3: The case of switches
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
ba5b0bfa 7 * Copyright (C) 2005-2010 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
be7ce530
MC		 70#define DRV_MODULE_VERSION "3.108"
71#define DRV_MODULE_RELDATE "February 17, 2010"
1da177e4
LT		 72
73#define TG3_DEF_MAC_MODE 0
74#define TG3_DEF_RX_MODE 0
75#define TG3_DEF_TX_MODE 0
76#define TG3_DEF_MSG_ENABLE \
77 (NETIF_MSG_DRV | \
78 NETIF_MSG_PROBE | \
79 NETIF_MSG_LINK | \
80 NETIF_MSG_TIMER | \
81 NETIF_MSG_IFDOWN | \
82 NETIF_MSG_IFUP | \
83 NETIF_MSG_RX_ERR | \
84 NETIF_MSG_TX_ERR)
85
86/* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
88 */
89#define TG3_TX_TIMEOUT (5 * HZ)
90
91/* hardware minimum and maximum for a single frame's data payload */
92#define TG3_MIN_MTU 60
93#define TG3_MAX_MTU(tp) \
8f666b07 94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 95
96/* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
99 */
100#define TG3_RX_RING_SIZE 512
101#define TG3_DEF_RX_RING_PENDING 200
102#define TG3_RX_JUMBO_RING_SIZE 256
103#define TG3_DEF_RX_JUMBO_RING_PENDING 100
c6cdf436 104#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 115
116#define TG3_TX_RING_SIZE 512
117#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
79ed5ac7
MC		 121#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
1da177e4 123#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 124 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 125#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
1da177e4
LT		 127#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
287be12e
MC		 129#define TG3_DMA_BYTE_ENAB 64
130
131#define TG3_RX_STD_DMA_SZ 1536
132#define TG3_RX_JMB_DMA_SZ 9046
133
134#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135
136#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 138
2b2cdb65
MC		 139#define TG3_RX_STD_BUFF_RING_SIZE \
140 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
141
142#define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
144
c6cdf436
MC		 145#define TG3_RSS_MIN_NUM_MSIX_VECS 2
146
1da177e4 147/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 148#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 149
ad829268
MC		 150#define TG3_RAW_IP_ALIGN 2
151
1da177e4
LT		 152/* number of ETHTOOL_GSTATS u64's */
153#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
154
4cafd3f5
MC		 155#define TG3_NUM_TEST 6
156
c6cdf436
MC		 157#define TG3_FW_UPDATE_TIMEOUT_SEC 5
158
077f849d
JSR		 159#define FIRMWARE_TG3 "tigon/tg3.bin"
160#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
161#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
162
1da177e4 163static char version[] __devinitdata =
05dbe005 164 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 165
166MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
167MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
168MODULE_LICENSE("GPL");
169MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 170MODULE_FIRMWARE(FIRMWARE_TG3);
171MODULE_FIRMWARE(FIRMWARE_TG3TSO);
172MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
173
1da177e4
LT		 174static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
175module_param(tg3_debug, int, 0);
176MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
177
a3aa1884 178static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
b0f75221
MC		 248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
13185217
HK		 254 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
255 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
258 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
259 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
260 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
261 {}
1da177e4
LT		 262};
263
264MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
265
50da859d 266static const struct {
1da177e4
LT		 267 const char string[ETH_GSTRING_LEN];
268} ethtool_stats_keys[TG3_NUM_STATS] = {
269 { "rx_octets" },
270 { "rx_fragments" },
271 { "rx_ucast_packets" },
272 { "rx_mcast_packets" },
273 { "rx_bcast_packets" },
274 { "rx_fcs_errors" },
275 { "rx_align_errors" },
276 { "rx_xon_pause_rcvd" },
277 { "rx_xoff_pause_rcvd" },
278 { "rx_mac_ctrl_rcvd" },
279 { "rx_xoff_entered" },
280 { "rx_frame_too_long_errors" },
281 { "rx_jabbers" },
282 { "rx_undersize_packets" },
283 { "rx_in_length_errors" },
284 { "rx_out_length_errors" },
285 { "rx_64_or_less_octet_packets" },
286 { "rx_65_to_127_octet_packets" },
287 { "rx_128_to_255_octet_packets" },
288 { "rx_256_to_511_octet_packets" },
289 { "rx_512_to_1023_octet_packets" },
290 { "rx_1024_to_1522_octet_packets" },
291 { "rx_1523_to_2047_octet_packets" },
292 { "rx_2048_to_4095_octet_packets" },
293 { "rx_4096_to_8191_octet_packets" },
294 { "rx_8192_to_9022_octet_packets" },
295
296 { "tx_octets" },
297 { "tx_collisions" },
298
299 { "tx_xon_sent" },
300 { "tx_xoff_sent" },
301 { "tx_flow_control" },
302 { "tx_mac_errors" },
303 { "tx_single_collisions" },
304 { "tx_mult_collisions" },
305 { "tx_deferred" },
306 { "tx_excessive_collisions" },
307 { "tx_late_collisions" },
308 { "tx_collide_2times" },
309 { "tx_collide_3times" },
310 { "tx_collide_4times" },
311 { "tx_collide_5times" },
312 { "tx_collide_6times" },
313 { "tx_collide_7times" },
314 { "tx_collide_8times" },
315 { "tx_collide_9times" },
316 { "tx_collide_10times" },
317 { "tx_collide_11times" },
318 { "tx_collide_12times" },
319 { "tx_collide_13times" },
320 { "tx_collide_14times" },
321 { "tx_collide_15times" },
322 { "tx_ucast_packets" },
323 { "tx_mcast_packets" },
324 { "tx_bcast_packets" },
325 { "tx_carrier_sense_errors" },
326 { "tx_discards" },
327 { "tx_errors" },
328
329 { "dma_writeq_full" },
330 { "dma_write_prioq_full" },
331 { "rxbds_empty" },
332 { "rx_discards" },
333 { "rx_errors" },
334 { "rx_threshold_hit" },
335
336 { "dma_readq_full" },
337 { "dma_read_prioq_full" },
338 { "tx_comp_queue_full" },
339
340 { "ring_set_send_prod_index" },
341 { "ring_status_update" },
342 { "nic_irqs" },
343 { "nic_avoided_irqs" },
344 { "nic_tx_threshold_hit" }
345};
346
50da859d 347static const struct {
4cafd3f5
MC		 348 const char string[ETH_GSTRING_LEN];
349} ethtool_test_keys[TG3_NUM_TEST] = {
350 { "nvram test (online) " },
351 { "link test (online) " },
352 { "register test (offline)" },
353 { "memory test (offline)" },
354 { "loopback test (offline)" },
355 { "interrupt test (offline)" },
356};
357
b401e9e2
MC		 358static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
359{
360 writel(val, tp->regs + off);
361}
362
363static u32 tg3_read32(struct tg3 *tp, u32 off)
364{
6aa20a22 365 return (readl(tp->regs + off));
b401e9e2
MC		 366}
367
0d3031d9
MC		 368static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
369{
370 writel(val, tp->aperegs + off);
371}
372
373static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
374{
375 return (readl(tp->aperegs + off));
376}
377
1da177e4
LT		 378static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
379{
6892914f
MC		 380 unsigned long flags;
381
382 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 383 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 385 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 386}
387
388static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
389{
390 writel(val, tp->regs + off);
391 readl(tp->regs + off);
1da177e4
LT		 392}
393
6892914f 394static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 395{
6892914f
MC		 396 unsigned long flags;
397 u32 val;
398
399 spin_lock_irqsave(&tp->indirect_lock, flags);
400 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
401 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
402 spin_unlock_irqrestore(&tp->indirect_lock, flags);
403 return val;
404}
405
406static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
407{
408 unsigned long flags;
409
410 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
411 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
412 TG3_64BIT_REG_LOW, val);
413 return;
414 }
66711e66 415 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 416 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
417 TG3_64BIT_REG_LOW, val);
418 return;
1da177e4 419 }
6892914f
MC		 420
421 spin_lock_irqsave(&tp->indirect_lock, flags);
422 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
424 spin_unlock_irqrestore(&tp->indirect_lock, flags);
425
426 /* In indirect mode when disabling interrupts, we also need
427 * to clear the interrupt bit in the GRC local ctrl register.
428 */
429 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
430 (val == 0x1)) {
431 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
432 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
433 }
434}
435
436static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
437{
438 unsigned long flags;
439 u32 val;
440
441 spin_lock_irqsave(&tp->indirect_lock, flags);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
443 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
444 spin_unlock_irqrestore(&tp->indirect_lock, flags);
445 return val;
446}
447
b401e9e2
MC		 448/* usec_wait specifies the wait time in usec when writing to certain registers
449 * where it is unsafe to read back the register without some delay.
450 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
451 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
452 */
453static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 454{
b401e9e2
MC		 455 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
456 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
457 /* Non-posted methods */
458 tp->write32(tp, off, val);
459 else {
460 /* Posted method */
461 tg3_write32(tp, off, val);
462 if (usec_wait)
463 udelay(usec_wait);
464 tp->read32(tp, off);
465 }
466 /* Wait again after the read for the posted method to guarantee that
467 * the wait time is met.
468 */
469 if (usec_wait)
470 udelay(usec_wait);
1da177e4
LT		 471}
472
09ee929c
MC		 473static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
474{
475 tp->write32_mbox(tp, off, val);
6892914f
MC		 476 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
477 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
478 tp->read32_mbox(tp, off);
09ee929c
MC		 479}
480
20094930 481static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 482{
483 void __iomem *mbox = tp->regs + off;
484 writel(val, mbox);
485 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
486 writel(val, mbox);
487 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
488 readl(mbox);
489}
490
b5d3772c
MC		 491static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
492{
493 return (readl(tp->regs + off + GRCMBOX_BASE));
494}
495
496static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
497{
498 writel(val, tp->regs + off + GRCMBOX_BASE);
499}
500
c6cdf436 501#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 502#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 503#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
504#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
505#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 506
c6cdf436
MC		 507#define tw32(reg, val) tp->write32(tp, reg, val)
508#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
509#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
510#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 511
512static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
513{
6892914f
MC		 514 unsigned long flags;
515
b5d3772c
MC		 516 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
517 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
518 return;
519
6892914f 520 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 524
bbadf503
MC		 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 530
bbadf503
MC		 531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 535}
536
1da177e4
LT		 537static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
538{
6892914f
MC		 539 unsigned long flags;
540
b5d3772c
MC		 541 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
542 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
543 *val = 0;
544 return;
545 }
546
6892914f 547 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 548 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
549 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
550 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 551
bbadf503
MC		 552 /* Always leave this as zero. */
553 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
554 } else {
555 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
556 *val = tr32(TG3PCI_MEM_WIN_DATA);
557
558 /* Always leave this as zero. */
559 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
560 }
6892914f 561 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 562}
563
0d3031d9
MC		 564static void tg3_ape_lock_init(struct tg3 *tp)
565{
566 int i;
567
568 /* Make sure the driver hasn't any stale locks. */
569 for (i = 0; i < 8; i++)
570 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
571 APE_LOCK_GRANT_DRIVER);
572}
573
574static int tg3_ape_lock(struct tg3 *tp, int locknum)
575{
576 int i, off;
577 int ret = 0;
578 u32 status;
579
580 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
581 return 0;
582
583 switch (locknum) {
33f401ae
MC		 584 case TG3_APE_LOCK_GRC:
585 case TG3_APE_LOCK_MEM:
586 break;
587 default:
588 return -EINVAL;
0d3031d9
MC		 589 }
590
591 off = 4 * locknum;
592
593 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
594
595 /* Wait for up to 1 millisecond to acquire lock. */
596 for (i = 0; i < 100; i++) {
597 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
598 if (status == APE_LOCK_GRANT_DRIVER)
599 break;
600 udelay(10);
601 }
602
603 if (status != APE_LOCK_GRANT_DRIVER) {
604 /* Revoke the lock request. */
605 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
606 APE_LOCK_GRANT_DRIVER);
607
608 ret = -EBUSY;
609 }
610
611 return ret;
612}
613
614static void tg3_ape_unlock(struct tg3 *tp, int locknum)
615{
616 int off;
617
618 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
619 return;
620
621 switch (locknum) {
33f401ae
MC		 622 case TG3_APE_LOCK_GRC:
623 case TG3_APE_LOCK_MEM:
624 break;
625 default:
626 return;
0d3031d9
MC		 627 }
628
629 off = 4 * locknum;
630 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
631}
632
1da177e4
LT		 633static void tg3_disable_ints(struct tg3 *tp)
634{
89aeb3bc
MC		 635 int i;
636
1da177e4
LT		 637 tw32(TG3PCI_MISC_HOST_CTRL,
638 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 639 for (i = 0; i < tp->irq_max; i++)
640 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 641}
642
1da177e4
LT		 643static void tg3_enable_ints(struct tg3 *tp)
644{
89aeb3bc 645 int i;
89aeb3bc 646
bbe832c0
MC		 647 tp->irq_sync = 0;
648 wmb();
649
1da177e4
LT		 650 tw32(TG3PCI_MISC_HOST_CTRL,
651 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 652
f89f38b8 653 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 654 for (i = 0; i < tp->irq_cnt; i++) {
655 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 656
898a56f8 657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 658 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
659 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 660
f89f38b8 661 tp->coal_now |= tnapi->coal_now;
89aeb3bc 662 }
f19af9c2
MC		 663
664 /* Force an initial interrupt */
665 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
666 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
667 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
668 else
f89f38b8
MC		 669 tw32(HOSTCC_MODE, tp->coal_now);
670
671 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 672}
673
17375d25 674static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 675{
17375d25 676 struct tg3 *tp = tnapi->tp;
898a56f8 677 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 678 unsigned int work_exists = 0;
679
680 /* check for phy events */
681 if (!(tp->tg3_flags &
682 (TG3_FLAG_USE_LINKCHG_REG |
683 TG3_FLAG_POLL_SERDES))) {
684 if (sblk->status & SD_STATUS_LINK_CHG)
685 work_exists = 1;
686 }
687 /* check for RX/TX work to do */
f3f3f27e 688 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 689 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 690 work_exists = 1;
691
692 return work_exists;
693}
694
17375d25 695/* tg3_int_reenable
04237ddd
MC		 696 * similar to tg3_enable_ints, but it accurately determines whether there
697 * is new work pending and can return without flushing the PIO write
6aa20a22 698 * which reenables interrupts
1da177e4 699 */
17375d25 700static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 701{
17375d25
MC		 702 struct tg3 *tp = tnapi->tp;
703
898a56f8 704 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 705 mmiowb();
706
fac9b83e
DM		 707 /* When doing tagged status, this work check is unnecessary.
708 * The last_tag we write above tells the chip which piece of
709 * work we've completed.
710 */
711 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 712 tg3_has_work(tnapi))
04237ddd 713 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 714 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 715}
716
fed97810
MC		 717static void tg3_napi_disable(struct tg3 *tp)
718{
719 int i;
720
721 for (i = tp->irq_cnt - 1; i >= 0; i--)
722 napi_disable(&tp->napi[i].napi);
723}
724
725static void tg3_napi_enable(struct tg3 *tp)
726{
727 int i;
728
729 for (i = 0; i < tp->irq_cnt; i++)
730 napi_enable(&tp->napi[i].napi);
731}
732
1da177e4
LT		 733static inline void tg3_netif_stop(struct tg3 *tp)
734{
bbe832c0 735 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 736 tg3_napi_disable(tp);
1da177e4
LT		 737 netif_tx_disable(tp->dev);
738}
739
740static inline void tg3_netif_start(struct tg3 *tp)
741{
fe5f5787
MC		 742 /* NOTE: unconditional netif_tx_wake_all_queues is only
743 * appropriate so long as all callers are assured to
744 * have free tx slots (such as after tg3_init_hw)
1da177e4 745 */
fe5f5787
MC		 746 netif_tx_wake_all_queues(tp->dev);
747
fed97810
MC		 748 tg3_napi_enable(tp);
749 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 750 tg3_enable_ints(tp);
1da177e4
LT		 751}
752
753static void tg3_switch_clocks(struct tg3 *tp)
754{
f6eb9b1f 755 u32 clock_ctrl;
1da177e4
LT		 756 u32 orig_clock_ctrl;
757
795d01c5
MC		 758 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
759 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 760 return;
761
f6eb9b1f
MC		 762 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
763
1da177e4
LT		 764 orig_clock_ctrl = clock_ctrl;
765 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
766 CLOCK_CTRL_CLKRUN_OENABLE |
767 0x1f);
768 tp->pci_clock_ctrl = clock_ctrl;
769
770 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
771 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 772 tw32_wait_f(TG3PCI_CLOCK_CTRL,
773 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 774 }
775 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 776 tw32_wait_f(TG3PCI_CLOCK_CTRL,
777 clock_ctrl |
778 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
779 40);
780 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781 clock_ctrl | (CLOCK_CTRL_ALTCLK),
782 40);
1da177e4 783 }
b401e9e2 784 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 785}
786
787#define PHY_BUSY_LOOPS 5000
788
789static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
790{
791 u32 frame_val;
792 unsigned int loops;
793 int ret;
794
795 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
796 tw32_f(MAC_MI_MODE,
797 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
798 udelay(80);
799 }
800
801 *val = 0x0;
802
882e9793 803 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 804 MI_COM_PHY_ADDR_MASK);
805 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
806 MI_COM_REG_ADDR_MASK);
807 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 808
1da177e4
LT		 809 tw32_f(MAC_MI_COM, frame_val);
810
811 loops = PHY_BUSY_LOOPS;
812 while (loops != 0) {
813 udelay(10);
814 frame_val = tr32(MAC_MI_COM);
815
816 if ((frame_val & MI_COM_BUSY) == 0) {
817 udelay(5);
818 frame_val = tr32(MAC_MI_COM);
819 break;
820 }
821 loops -= 1;
822 }
823
824 ret = -EBUSY;
825 if (loops != 0) {
826 *val = frame_val & MI_COM_DATA_MASK;
827 ret = 0;
828 }
829
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE, tp->mi_mode);
832 udelay(80);
833 }
834
835 return ret;
836}
837
838static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
839{
840 u32 frame_val;
841 unsigned int loops;
842 int ret;
843
7f97a4bd 844 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 845 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
846 return 0;
847
1da177e4
LT		 848 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
849 tw32_f(MAC_MI_MODE,
850 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
851 udelay(80);
852 }
853
882e9793 854 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 855 MI_COM_PHY_ADDR_MASK);
856 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
857 MI_COM_REG_ADDR_MASK);
858 frame_val |= (val & MI_COM_DATA_MASK);
859 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 860
1da177e4
LT		 861 tw32_f(MAC_MI_COM, frame_val);
862
863 loops = PHY_BUSY_LOOPS;
864 while (loops != 0) {
865 udelay(10);
866 frame_val = tr32(MAC_MI_COM);
867 if ((frame_val & MI_COM_BUSY) == 0) {
868 udelay(5);
869 frame_val = tr32(MAC_MI_COM);
870 break;
871 }
872 loops -= 1;
873 }
874
875 ret = -EBUSY;
876 if (loops != 0)
877 ret = 0;
878
879 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
880 tw32_f(MAC_MI_MODE, tp->mi_mode);
881 udelay(80);
882 }
883
884 return ret;
885}
886
95e2869a
MC		 887static int tg3_bmcr_reset(struct tg3 *tp)
888{
889 u32 phy_control;
890 int limit, err;
891
892 /* OK, reset it, and poll the BMCR_RESET bit until it
893 * clears or we time out.
894 */
895 phy_control = BMCR_RESET;
896 err = tg3_writephy(tp, MII_BMCR, phy_control);
897 if (err != 0)
898 return -EBUSY;
899
900 limit = 5000;
901 while (limit--) {
902 err = tg3_readphy(tp, MII_BMCR, &phy_control);
903 if (err != 0)
904 return -EBUSY;
905
906 if ((phy_control & BMCR_RESET) == 0) {
907 udelay(40);
908 break;
909 }
910 udelay(10);
911 }
d4675b52 912 if (limit < 0)
95e2869a
MC		 913 return -EBUSY;
914
915 return 0;
916}
917
158d7abd
MC		 918static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
919{
3d16543d 920 struct tg3 *tp = bp->priv;
158d7abd
MC		 921 u32 val;
922
24bb4fb6 923 spin_lock_bh(&tp->lock);
158d7abd
MC		 924
925 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 926 val = -EIO;
927
928 spin_unlock_bh(&tp->lock);
158d7abd
MC		 929
930 return val;
931}
932
933static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
934{
3d16543d 935 struct tg3 *tp = bp->priv;
24bb4fb6 936 u32 ret = 0;
158d7abd 937
24bb4fb6 938 spin_lock_bh(&tp->lock);
158d7abd
MC		 939
940 if (tg3_writephy(tp, reg, val))
24bb4fb6 941 ret = -EIO;
158d7abd 942
24bb4fb6
MC		 943 spin_unlock_bh(&tp->lock);
944
945 return ret;
158d7abd
MC		 946}
947
948static int tg3_mdio_reset(struct mii_bus *bp)
949{
950 return 0;
951}
952
9c61d6bc 953static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 954{
955 u32 val;
fcb389df 956 struct phy_device *phydev;
a9daf367 957
3f0e3ad7 958 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 959 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 960 case PHY_ID_BCM50610:
961 case PHY_ID_BCM50610M:
fcb389df
MC		 962 val = MAC_PHYCFG2_50610_LED_MODES;
963 break;
6a443a0f 964 case PHY_ID_BCMAC131:
fcb389df
MC		 965 val = MAC_PHYCFG2_AC131_LED_MODES;
966 break;
6a443a0f 967 case PHY_ID_RTL8211C:
fcb389df
MC		 968 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
969 break;
6a443a0f 970 case PHY_ID_RTL8201E:
fcb389df
MC		 971 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
972 break;
973 default:
a9daf367 974 return;
fcb389df
MC		 975 }
976
977 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
978 tw32(MAC_PHYCFG2, val);
979
980 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 981 val &= ~(MAC_PHYCFG1_RGMII_INT |
982 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
983 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 984 tw32(MAC_PHYCFG1, val);
985
986 return;
987 }
988
14417063 989 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
fcb389df
MC		 990 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
991 MAC_PHYCFG2_FMODE_MASK_MASK |
992 MAC_PHYCFG2_GMODE_MASK_MASK |
993 MAC_PHYCFG2_ACT_MASK_MASK |
994 MAC_PHYCFG2_QUAL_MASK_MASK |
995 MAC_PHYCFG2_INBAND_ENABLE;
996
997 tw32(MAC_PHYCFG2, val);
a9daf367 998
bb85fbb6
MC		 999 val = tr32(MAC_PHYCFG1);
1000 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1001 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
14417063 1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1005 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1006 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1007 }
bb85fbb6
MC		 1008 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1009 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1010 tw32(MAC_PHYCFG1, val);
a9daf367 1011
a9daf367
MC		 1012 val = tr32(MAC_EXT_RGMII_MODE);
1013 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET |
1017 MAC_RGMII_MODE_TX_ENABLE |
1018 MAC_RGMII_MODE_TX_LOWPWR |
1019 MAC_RGMII_MODE_TX_RESET);
14417063 1020 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
a9daf367
MC		 1021 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1022 val |= MAC_RGMII_MODE_RX_INT_B |
1023 MAC_RGMII_MODE_RX_QUALITY |
1024 MAC_RGMII_MODE_RX_ACTIVITY |
1025 MAC_RGMII_MODE_RX_ENG_DET;
1026 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1027 val |= MAC_RGMII_MODE_TX_ENABLE |
1028 MAC_RGMII_MODE_TX_LOWPWR |
1029 MAC_RGMII_MODE_TX_RESET;
1030 }
1031 tw32(MAC_EXT_RGMII_MODE, val);
1032}
1033
158d7abd
MC		 1034static void tg3_mdio_start(struct tg3 *tp)
1035{
158d7abd
MC		 1036 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1038 udelay(80);
a9daf367 1039
9ea4818d
MC		 1040 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1042 tg3_mdio_config_5785(tp);
1043}
1044
1045static int tg3_mdio_init(struct tg3 *tp)
1046{
1047 int i;
1048 u32 reg;
1049 struct phy_device *phydev;
1050
882e9793
MC		 1051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1052 u32 funcnum, is_serdes;
1053
1054 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1055 if (funcnum)
1056 tp->phy_addr = 2;
1057 else
1058 tp->phy_addr = 1;
1059
d1ec96af
MC		 1060 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1061 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1062 else
1063 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1064 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1065 if (is_serdes)
1066 tp->phy_addr += 7;
1067 } else
3f0e3ad7 1068 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1069
158d7abd
MC		 1070 tg3_mdio_start(tp);
1071
1072 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1073 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1074 return 0;
1075
298cf9be
LB		 1076 tp->mdio_bus = mdiobus_alloc();
1077 if (tp->mdio_bus == NULL)
1078 return -ENOMEM;
158d7abd 1079
298cf9be
LB		 1080 tp->mdio_bus->name = "tg3 mdio bus";
1081 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1082 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1083 tp->mdio_bus->priv = tp;
1084 tp->mdio_bus->parent = &tp->pdev->dev;
1085 tp->mdio_bus->read = &tg3_mdio_read;
1086 tp->mdio_bus->write = &tg3_mdio_write;
1087 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1088 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1089 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1090
1091 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1092 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1093
1094 /* The bus registration will look for all the PHYs on the mdio bus.
1095 * Unfortunately, it does not ensure the PHY is powered up before
1096 * accessing the PHY ID registers. A chip reset is the
1097 * quickest way to bring the device back to an operational state..
1098 */
1099 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1100 tg3_bmcr_reset(tp);
1101
298cf9be 1102 i = mdiobus_register(tp->mdio_bus);
a9daf367 1103 if (i) {
ab96b241 1104 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1105 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1106 return i;
1107 }
158d7abd 1108
3f0e3ad7 1109 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1110
9c61d6bc 1111 if (!phydev || !phydev->drv) {
ab96b241 1112 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1113 mdiobus_unregister(tp->mdio_bus);
1114 mdiobus_free(tp->mdio_bus);
1115 return -ENODEV;
1116 }
1117
1118 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1119 case PHY_ID_BCM57780:
321d32a0 1120 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1121 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1122 break;
6a443a0f
MC		 1123 case PHY_ID_BCM50610:
1124 case PHY_ID_BCM50610M:
32e5a8d6 1125 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1126 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1127 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1128 PHY_BRCM_AUTO_PWRDWN_ENABLE;
14417063 1129 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
a9daf367
MC		 1130 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1131 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1132 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1133 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1134 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1135 /* fallthru */
6a443a0f 1136 case PHY_ID_RTL8211C:
fcb389df 1137 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1138 break;
6a443a0f
MC		 1139 case PHY_ID_RTL8201E:
1140 case PHY_ID_BCMAC131:
a9daf367 1141 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1142 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1143 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1144 break;
1145 }
1146
9c61d6bc
MC		 1147 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1148
1149 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1150 tg3_mdio_config_5785(tp);
a9daf367
MC		 1151
1152 return 0;
158d7abd
MC		 1153}
1154
1155static void tg3_mdio_fini(struct tg3 *tp)
1156{
1157 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1158 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1159 mdiobus_unregister(tp->mdio_bus);
1160 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1161 }
1162}
1163
4ba526ce
MC		 1164/* tp->lock is held. */
1165static inline void tg3_generate_fw_event(struct tg3 *tp)
1166{
1167 u32 val;
1168
1169 val = tr32(GRC_RX_CPU_EVENT);
1170 val |= GRC_RX_CPU_DRIVER_EVENT;
1171 tw32_f(GRC_RX_CPU_EVENT, val);
1172
1173 tp->last_event_jiffies = jiffies;
1174}
1175
1176#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1177
95e2869a
MC		 1178/* tp->lock is held. */
1179static void tg3_wait_for_event_ack(struct tg3 *tp)
1180{
1181 int i;
4ba526ce
MC		 1182 unsigned int delay_cnt;
1183 long time_remain;
1184
1185 /* If enough time has passed, no wait is necessary. */
1186 time_remain = (long)(tp->last_event_jiffies + 1 +
1187 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1188 (long)jiffies;
1189 if (time_remain < 0)
1190 return;
1191
1192 /* Check if we can shorten the wait time. */
1193 delay_cnt = jiffies_to_usecs(time_remain);
1194 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1195 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1196 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1197
4ba526ce 1198 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1199 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1200 break;
4ba526ce 1201 udelay(8);
95e2869a
MC		 1202 }
1203}
1204
1205/* tp->lock is held. */
1206static void tg3_ump_link_report(struct tg3 *tp)
1207{
1208 u32 reg;
1209 u32 val;
1210
1211 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1212 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1213 return;
1214
1215 tg3_wait_for_event_ack(tp);
1216
1217 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1218
1219 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1220
1221 val = 0;
1222 if (!tg3_readphy(tp, MII_BMCR, &reg))
1223 val = reg << 16;
1224 if (!tg3_readphy(tp, MII_BMSR, &reg))
1225 val |= (reg & 0xffff);
1226 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1227
1228 val = 0;
1229 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1230 val = reg << 16;
1231 if (!tg3_readphy(tp, MII_LPA, &reg))
1232 val |= (reg & 0xffff);
1233 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1234
1235 val = 0;
1236 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1237 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1238 val = reg << 16;
1239 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1240 val |= (reg & 0xffff);
1241 }
1242 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1243
1244 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1245 val = reg << 16;
1246 else
1247 val = 0;
1248 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1249
4ba526ce 1250 tg3_generate_fw_event(tp);
95e2869a
MC		 1251}
1252
1253static void tg3_link_report(struct tg3 *tp)
1254{
1255 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1256 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1257 tg3_ump_link_report(tp);
1258 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1259 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1260 (tp->link_config.active_speed == SPEED_1000 ?
1261 1000 :
1262 (tp->link_config.active_speed == SPEED_100 ?
1263 100 : 10)),
1264 (tp->link_config.active_duplex == DUPLEX_FULL ?
1265 "full" : "half"));
1266
1267 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1268 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1269 "on" : "off",
1270 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1271 "on" : "off");
95e2869a
MC		 1272 tg3_ump_link_report(tp);
1273 }
1274}
1275
1276static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1277{
1278 u16 miireg;
1279
e18ce346 1280 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1281 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1282 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1283 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1284 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1285 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1286 else
1287 miireg = 0;
1288
1289 return miireg;
1290}
1291
1292static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1293{
1294 u16 miireg;
1295
e18ce346 1296 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1297 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1298 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1299 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1300 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1301 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1302 else
1303 miireg = 0;
1304
1305 return miireg;
1306}
1307
95e2869a
MC		 1308static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1309{
1310 u8 cap = 0;
1311
1312 if (lcladv & ADVERTISE_1000XPAUSE) {
1313 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1314 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1315 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1316 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1317 cap = FLOW_CTRL_RX;
95e2869a
MC		 1318 } else {
1319 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1320 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1321 }
1322 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1323 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1324 cap = FLOW_CTRL_TX;
95e2869a
MC		 1325 }
1326
1327 return cap;
1328}
1329
f51f3562 1330static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1331{
b02fd9e3 1332 u8 autoneg;
f51f3562 1333 u8 flowctrl = 0;
95e2869a
MC		 1334 u32 old_rx_mode = tp->rx_mode;
1335 u32 old_tx_mode = tp->tx_mode;
1336
b02fd9e3 1337 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1338 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1339 else
1340 autoneg = tp->link_config.autoneg;
1341
1342 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1343 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1344 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1345 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1346 else
bc02ff95 1347 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1348 } else
1349 flowctrl = tp->link_config.flowctrl;
95e2869a 1350
f51f3562 1351 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1352
e18ce346 1353 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1354 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1355 else
1356 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1357
f51f3562 1358 if (old_rx_mode != tp->rx_mode)
95e2869a 1359 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1360
e18ce346 1361 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1362 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1363 else
1364 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1365
f51f3562 1366 if (old_tx_mode != tp->tx_mode)
95e2869a 1367 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1368}
1369
b02fd9e3
MC		 1370static void tg3_adjust_link(struct net_device *dev)
1371{
1372 u8 oldflowctrl, linkmesg = 0;
1373 u32 mac_mode, lcl_adv, rmt_adv;
1374 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1375 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1376
24bb4fb6 1377 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1378
1379 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1380 MAC_MODE_HALF_DUPLEX);
1381
1382 oldflowctrl = tp->link_config.active_flowctrl;
1383
1384 if (phydev->link) {
1385 lcl_adv = 0;
1386 rmt_adv = 0;
1387
1388 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1389 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1390 else if (phydev->speed == SPEED_1000 ||
1391 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1392 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1393 else
1394 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1395
1396 if (phydev->duplex == DUPLEX_HALF)
1397 mac_mode |= MAC_MODE_HALF_DUPLEX;
1398 else {
1399 lcl_adv = tg3_advert_flowctrl_1000T(
1400 tp->link_config.flowctrl);
1401
1402 if (phydev->pause)
1403 rmt_adv = LPA_PAUSE_CAP;
1404 if (phydev->asym_pause)
1405 rmt_adv |= LPA_PAUSE_ASYM;
1406 }
1407
1408 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1409 } else
1410 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1411
1412 if (mac_mode != tp->mac_mode) {
1413 tp->mac_mode = mac_mode;
1414 tw32_f(MAC_MODE, tp->mac_mode);
1415 udelay(40);
1416 }
1417
fcb389df
MC		 1418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1419 if (phydev->speed == SPEED_10)
1420 tw32(MAC_MI_STAT,
1421 MAC_MI_STAT_10MBPS_MODE |
1422 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1423 else
1424 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1425 }
1426
b02fd9e3
MC		 1427 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1428 tw32(MAC_TX_LENGTHS,
1429 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1430 (6 << TX_LENGTHS_IPG_SHIFT) |
1431 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1432 else
1433 tw32(MAC_TX_LENGTHS,
1434 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1435 (6 << TX_LENGTHS_IPG_SHIFT) |
1436 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1437
1438 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1439 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1440 phydev->speed != tp->link_config.active_speed ||
1441 phydev->duplex != tp->link_config.active_duplex ||
1442 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 1443 linkmesg = 1;
b02fd9e3
MC		 1444
1445 tp->link_config.active_speed = phydev->speed;
1446 tp->link_config.active_duplex = phydev->duplex;
1447
24bb4fb6 1448 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1449
1450 if (linkmesg)
1451 tg3_link_report(tp);
1452}
1453
1454static int tg3_phy_init(struct tg3 *tp)
1455{
1456 struct phy_device *phydev;
1457
1458 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1459 return 0;
1460
1461 /* Bring the PHY back to a known state. */
1462 tg3_bmcr_reset(tp);
1463
3f0e3ad7 1464 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1465
1466 /* Attach the MAC to the PHY. */
fb28ad35 1467 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1468 phydev->dev_flags, phydev->interface);
b02fd9e3 1469 if (IS_ERR(phydev)) {
ab96b241 1470 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 1471 return PTR_ERR(phydev);
1472 }
1473
b02fd9e3 1474 /* Mask with MAC supported features. */
9c61d6bc
MC		 1475 switch (phydev->interface) {
1476 case PHY_INTERFACE_MODE_GMII:
1477 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1478 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1479 phydev->supported &= (PHY_GBIT_FEATURES |
1480 SUPPORTED_Pause |
1481 SUPPORTED_Asym_Pause);
1482 break;
1483 }
1484 /* fallthru */
9c61d6bc
MC		 1485 case PHY_INTERFACE_MODE_MII:
1486 phydev->supported &= (PHY_BASIC_FEATURES |
1487 SUPPORTED_Pause |
1488 SUPPORTED_Asym_Pause);
1489 break;
1490 default:
3f0e3ad7 1491 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1492 return -EINVAL;
1493 }
1494
1495 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1496
1497 phydev->advertising = phydev->supported;
1498
b02fd9e3
MC		 1499 return 0;
1500}
1501
1502static void tg3_phy_start(struct tg3 *tp)
1503{
1504 struct phy_device *phydev;
1505
1506 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1507 return;
1508
3f0e3ad7 1509 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1510
1511 if (tp->link_config.phy_is_low_power) {
1512 tp->link_config.phy_is_low_power = 0;
1513 phydev->speed = tp->link_config.orig_speed;
1514 phydev->duplex = tp->link_config.orig_duplex;
1515 phydev->autoneg = tp->link_config.orig_autoneg;
1516 phydev->advertising = tp->link_config.orig_advertising;
1517 }
1518
1519 phy_start(phydev);
1520
1521 phy_start_aneg(phydev);
1522}
1523
1524static void tg3_phy_stop(struct tg3 *tp)
1525{
1526 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1527 return;
1528
3f0e3ad7 1529 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1530}
1531
1532static void tg3_phy_fini(struct tg3 *tp)
1533{
1534 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1535 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1536 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1537 }
1538}
1539
b2a5c19c
MC		 1540static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1541{
1542 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1543 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1544}
1545
7f97a4bd
MC		 1546static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1547{
1548 u32 phytest;
1549
1550 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1551 u32 phy;
1552
1553 tg3_writephy(tp, MII_TG3_FET_TEST,
1554 phytest | MII_TG3_FET_SHADOW_EN);
1555 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1556 if (enable)
1557 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1558 else
1559 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1560 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1561 }
1562 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1563 }
1564}
1565
6833c043
MC		 1566static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1567{
1568 u32 reg;
1569
ecf1410b
MC		 1570 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1571 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1572 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
6833c043
MC		 1573 return;
1574
7f97a4bd
MC		 1575 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1576 tg3_phy_fet_toggle_apd(tp, enable);
1577 return;
1578 }
1579
6833c043
MC		 1580 reg = MII_TG3_MISC_SHDW_WREN |
1581 MII_TG3_MISC_SHDW_SCR5_SEL |
1582 MII_TG3_MISC_SHDW_SCR5_LPED |
1583 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1584 MII_TG3_MISC_SHDW_SCR5_SDTL |
1585 MII_TG3_MISC_SHDW_SCR5_C125OE;
1586 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1587 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1588
1589 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1590
1591
1592 reg = MII_TG3_MISC_SHDW_WREN |
1593 MII_TG3_MISC_SHDW_APD_SEL |
1594 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1595 if (enable)
1596 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1597
1598 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1599}
1600
9ef8ca99
MC		 1601static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1602{
1603 u32 phy;
1604
1605 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1606 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1607 return;
1608
7f97a4bd 1609 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1610 u32 ephy;
1611
535ef6e1
MC		 1612 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1613 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1614
1615 tg3_writephy(tp, MII_TG3_FET_TEST,
1616 ephy | MII_TG3_FET_SHADOW_EN);
1617 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1618 if (enable)
535ef6e1 1619 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1620 else
535ef6e1
MC		 1621 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1622 tg3_writephy(tp, reg, phy);
9ef8ca99 1623 }
535ef6e1 1624 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1625 }
1626 } else {
1627 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1628 MII_TG3_AUXCTL_SHDWSEL_MISC;
1629 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1630 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1631 if (enable)
1632 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1633 else
1634 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1635 phy |= MII_TG3_AUXCTL_MISC_WREN;
1636 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1637 }
1638 }
1639}
1640
1da177e4
LT		 1641static void tg3_phy_set_wirespeed(struct tg3 *tp)
1642{
1643 u32 val;
1644
1645 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1646 return;
1647
1648 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1649 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1650 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1651 (val | (1 << 15) | (1 << 4)));
1652}
1653
b2a5c19c
MC		 1654static void tg3_phy_apply_otp(struct tg3 *tp)
1655{
1656 u32 otp, phy;
1657
1658 if (!tp->phy_otp)
1659 return;
1660
1661 otp = tp->phy_otp;
1662
1663 /* Enable SM_DSP clock and tx 6dB coding. */
1664 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1665 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1666 MII_TG3_AUXCTL_ACTL_TX_6DB;
1667 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1668
1669 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1670 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1671 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1672
1673 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1674 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1675 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1676
1677 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1678 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1679 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1680
1681 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1683
1684 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1685 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1686
1687 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1688 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1689 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1690
1691 /* Turn off SM_DSP clock. */
1692 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1693 MII_TG3_AUXCTL_ACTL_TX_6DB;
1694 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1695}
1696
1da177e4
LT		 1697static int tg3_wait_macro_done(struct tg3 *tp)
1698{
1699 int limit = 100;
1700
1701 while (limit--) {
1702 u32 tmp32;
1703
1704 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1705 if ((tmp32 & 0x1000) == 0)
1706 break;
1707 }
1708 }
d4675b52 1709 if (limit < 0)
1da177e4
LT		 1710 return -EBUSY;
1711
1712 return 0;
1713}
1714
1715static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1716{
1717 static const u32 test_pat[4][6] = {
1718 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1719 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1720 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1721 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1722 };
1723 int chan;
1724
1725 for (chan = 0; chan < 4; chan++) {
1726 int i;
1727
1728 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1729 (chan * 0x2000) | 0x0200);
1730 tg3_writephy(tp, 0x16, 0x0002);
1731
1732 for (i = 0; i < 6; i++)
1733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1734 test_pat[chan][i]);
1735
1736 tg3_writephy(tp, 0x16, 0x0202);
1737 if (tg3_wait_macro_done(tp)) {
1738 *resetp = 1;
1739 return -EBUSY;
1740 }
1741
1742 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1743 (chan * 0x2000) | 0x0200);
1744 tg3_writephy(tp, 0x16, 0x0082);
1745 if (tg3_wait_macro_done(tp)) {
1746 *resetp = 1;
1747 return -EBUSY;
1748 }
1749
1750 tg3_writephy(tp, 0x16, 0x0802);
1751 if (tg3_wait_macro_done(tp)) {
1752 *resetp = 1;
1753 return -EBUSY;
1754 }
1755
1756 for (i = 0; i < 6; i += 2) {
1757 u32 low, high;
1758
1759 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1760 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1761 tg3_wait_macro_done(tp)) {
1762 *resetp = 1;
1763 return -EBUSY;
1764 }
1765 low &= 0x7fff;
1766 high &= 0x000f;
1767 if (low != test_pat[chan][i] ||
1768 high != test_pat[chan][i+1]) {
1769 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1770 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1771 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1772
1773 return -EBUSY;
1774 }
1775 }
1776 }
1777
1778 return 0;
1779}
1780
1781static int tg3_phy_reset_chanpat(struct tg3 *tp)
1782{
1783 int chan;
1784
1785 for (chan = 0; chan < 4; chan++) {
1786 int i;
1787
1788 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1789 (chan * 0x2000) | 0x0200);
1790 tg3_writephy(tp, 0x16, 0x0002);
1791 for (i = 0; i < 6; i++)
1792 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1793 tg3_writephy(tp, 0x16, 0x0202);
1794 if (tg3_wait_macro_done(tp))
1795 return -EBUSY;
1796 }
1797
1798 return 0;
1799}
1800
1801static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1802{
1803 u32 reg32, phy9_orig;
1804 int retries, do_phy_reset, err;
1805
1806 retries = 10;
1807 do_phy_reset = 1;
1808 do {
1809 if (do_phy_reset) {
1810 err = tg3_bmcr_reset(tp);
1811 if (err)
1812 return err;
1813 do_phy_reset = 0;
1814 }
1815
1816 /* Disable transmitter and interrupt. */
1817 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1818 continue;
1819
1820 reg32 |= 0x3000;
1821 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1822
1823 /* Set full-duplex, 1000 mbps. */
1824 tg3_writephy(tp, MII_BMCR,
1825 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1826
1827 /* Set to master mode. */
1828 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1829 continue;
1830
1831 tg3_writephy(tp, MII_TG3_CTRL,
1832 (MII_TG3_CTRL_AS_MASTER |
1833 MII_TG3_CTRL_ENABLE_AS_MASTER));
1834
1835 /* Enable SM_DSP_CLOCK and 6dB. */
1836 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1837
1838 /* Block the PHY control access. */
1839 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1840 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1841
1842 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1843 if (!err)
1844 break;
1845 } while (--retries);
1846
1847 err = tg3_phy_reset_chanpat(tp);
1848 if (err)
1849 return err;
1850
1851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1852 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1853
1854 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1855 tg3_writephy(tp, 0x16, 0x0000);
1856
1857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1859 /* Set Extended packet length bit for jumbo frames */
1860 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1861 }
1862 else {
1863 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1864 }
1865
1866 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1867
1868 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1869 reg32 &= ~0x3000;
1870 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1871 } else if (!err)
1872 err = -EBUSY;
1873
1874 return err;
1875}
1876
1877/* This will reset the tigon3 PHY if there is no valid
1878 * link unless the FORCE argument is non-zero.
1879 */
1880static int tg3_phy_reset(struct tg3 *tp)
1881{
b2a5c19c 1882 u32 cpmuctrl;
1da177e4
LT		 1883 u32 phy_status;
1884 int err;
1885
60189ddf
MC		 1886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1887 u32 val;
1888
1889 val = tr32(GRC_MISC_CFG);
1890 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1891 udelay(40);
1892 }
1da177e4
LT		 1893 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1894 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1895 if (err != 0)
1896 return -EBUSY;
1897
c8e1e82b
MC		 1898 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1899 netif_carrier_off(tp->dev);
1900 tg3_link_report(tp);
1901 }
1902
1da177e4
LT		 1903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1906 err = tg3_phy_reset_5703_4_5(tp);
1907 if (err)
1908 return err;
1909 goto out;
1910 }
1911
b2a5c19c
MC		 1912 cpmuctrl = 0;
1913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1914 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1915 cpmuctrl = tr32(TG3_CPMU_CTRL);
1916 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1917 tw32(TG3_CPMU_CTRL,
1918 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1919 }
1920
1da177e4
LT		 1921 err = tg3_bmcr_reset(tp);
1922 if (err)
1923 return err;
1924
b2a5c19c
MC		 1925 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1926 u32 phy;
1927
1928 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1929 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1930
1931 tw32(TG3_CPMU_CTRL, cpmuctrl);
1932 }
1933
bcb37f6c
MC		 1934 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1935 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1936 u32 val;
1937
1938 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1939 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1940 CPMU_LSPD_1000MB_MACCLK_12_5) {
1941 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1942 udelay(40);
1943 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1944 }
1945 }
1946
ecf1410b
MC		 1947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1948 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1949 return 0;
1950
b2a5c19c
MC		 1951 tg3_phy_apply_otp(tp);
1952
6833c043
MC		 1953 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1954 tg3_phy_toggle_apd(tp, true);
1955 else
1956 tg3_phy_toggle_apd(tp, false);
1957
1da177e4
LT		 1958out:
1959 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1962 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1963 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1964 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1965 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1966 }
1967 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1968 tg3_writephy(tp, 0x1c, 0x8d68);
1969 tg3_writephy(tp, 0x1c, 0x8d68);
1970 }
1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1973 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1974 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1975 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1976 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1977 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1979 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1980 }
c424cb24
MC		 1981 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1982 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1983 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1984 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1985 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1986 tg3_writephy(tp, MII_TG3_TEST1,
1987 MII_TG3_TEST1_TRIM_EN | 0x4);
1988 } else
1989 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1991 }
1da177e4
LT		 1992 /* Set Extended packet length bit (bit 14) on all chips that */
1993 /* support jumbo frames */
79eb6904 1994 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 1995 /* Cannot do read-modify-write on 5401 */
1996 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1997 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1998 u32 phy_reg;
1999
2000 /* Set bit 14 with read-modify-write to preserve other bits */
2001 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2002 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2003 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2004 }
2005
2006 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2007 * jumbo frames transmission.
2008 */
8f666b07 2009 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2010 u32 phy_reg;
2011
2012 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
c6cdf436
MC		 2013 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2014 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2015 }
2016
715116a1 2017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2018 /* adjust output voltage */
535ef6e1 2019 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2020 }
2021
9ef8ca99 2022 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2023 tg3_phy_set_wirespeed(tp);
2024 return 0;
2025}
2026
2027static void tg3_frob_aux_power(struct tg3 *tp)
2028{
2029 struct tg3 *tp_peer = tp;
2030
334355aa
MC		 2031 /* The GPIOs do something completely different on 57765. */
2032 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
1da177e4
LT		 2034 return;
2035
f6eb9b1f
MC		 2036 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2039 struct net_device *dev_peer;
2040
2041 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2042 /* remove_one() may have been run on the peer. */
8c2dc7e1 2043 if (!dev_peer)
bc1c7567
MC		 2044 tp_peer = tp;
2045 else
2046 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2047 }
2048
1da177e4 2049 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2050 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2051 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2052 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2055 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2056 (GRC_LCLCTRL_GPIO_OE0 |
2057 GRC_LCLCTRL_GPIO_OE1 |
2058 GRC_LCLCTRL_GPIO_OE2 |
2059 GRC_LCLCTRL_GPIO_OUTPUT0 |
2060 GRC_LCLCTRL_GPIO_OUTPUT1),
2061 100);
8d519ab2
MC		 2062 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2063 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2064 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2065 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2066 GRC_LCLCTRL_GPIO_OE1 |
2067 GRC_LCLCTRL_GPIO_OE2 |
2068 GRC_LCLCTRL_GPIO_OUTPUT0 |
2069 GRC_LCLCTRL_GPIO_OUTPUT1 |
2070 tp->grc_local_ctrl;
2071 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2072
2073 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2074 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2075
2076 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2077 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2078 } else {
2079 u32 no_gpio2;
dc56b7d4 2080 u32 grc_local_ctrl = 0;
1da177e4
LT		 2081
2082 if (tp_peer != tp &&
2083 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2084 return;
2085
dc56b7d4
MC		 2086 /* Workaround to prevent overdrawing Amps. */
2087 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2088 ASIC_REV_5714) {
2089 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2090 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2091 grc_local_ctrl, 100);
dc56b7d4
MC		 2092 }
2093
1da177e4
LT		 2094 /* On 5753 and variants, GPIO2 cannot be used. */
2095 no_gpio2 = tp->nic_sram_data_cfg &
2096 NIC_SRAM_DATA_CFG_NO_GPIO2;
2097
dc56b7d4 2098 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2099 GRC_LCLCTRL_GPIO_OE1 |
2100 GRC_LCLCTRL_GPIO_OE2 |
2101 GRC_LCLCTRL_GPIO_OUTPUT1 |
2102 GRC_LCLCTRL_GPIO_OUTPUT2;
2103 if (no_gpio2) {
2104 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2105 GRC_LCLCTRL_GPIO_OUTPUT2);
2106 }
b401e9e2
MC		 2107 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2108 grc_local_ctrl, 100);
1da177e4
LT		 2109
2110 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2111
b401e9e2
MC		 2112 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2113 grc_local_ctrl, 100);
1da177e4
LT		 2114
2115 if (!no_gpio2) {
2116 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2117 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118 grc_local_ctrl, 100);
1da177e4
LT		 2119 }
2120 }
2121 } else {
2122 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2123 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2124 if (tp_peer != tp &&
2125 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2126 return;
2127
b401e9e2
MC		 2128 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2129 (GRC_LCLCTRL_GPIO_OE1 |
2130 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2131
b401e9e2
MC		 2132 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2134
b401e9e2
MC		 2135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2136 (GRC_LCLCTRL_GPIO_OE1 |
2137 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2138 }
2139 }
2140}
2141
e8f3f6ca
MC		 2142static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2143{
2144 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2145 return 1;
79eb6904 2146 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 2147 if (speed != SPEED_10)
2148 return 1;
2149 } else if (speed == SPEED_10)
2150 return 1;
2151
2152 return 0;
2153}
2154
1da177e4
LT		 2155static int tg3_setup_phy(struct tg3 *, int);
2156
2157#define RESET_KIND_SHUTDOWN 0
2158#define RESET_KIND_INIT 1
2159#define RESET_KIND_SUSPEND 2
2160
2161static void tg3_write_sig_post_reset(struct tg3 *, int);
2162static int tg3_halt_cpu(struct tg3 *, u32);
2163
0a459aac 2164static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2165{
ce057f01
MC		 2166 u32 val;
2167
5129724a
MC		 2168 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2169 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2170 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2171 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2172
2173 sg_dig_ctrl |=
2174 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2175 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2176 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2177 }
3f7045c1 2178 return;
5129724a 2179 }
3f7045c1 2180
60189ddf 2181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2182 tg3_bmcr_reset(tp);
2183 val = tr32(GRC_MISC_CFG);
2184 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2185 udelay(40);
2186 return;
0e5f784c
MC		 2187 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2188 u32 phytest;
2189 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2190 u32 phy;
2191
2192 tg3_writephy(tp, MII_ADVERTISE, 0);
2193 tg3_writephy(tp, MII_BMCR,
2194 BMCR_ANENABLE | BMCR_ANRESTART);
2195
2196 tg3_writephy(tp, MII_TG3_FET_TEST,
2197 phytest | MII_TG3_FET_SHADOW_EN);
2198 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2199 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2200 tg3_writephy(tp,
2201 MII_TG3_FET_SHDW_AUXMODE4,
2202 phy);
2203 }
2204 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2205 }
2206 return;
0a459aac 2207 } else if (do_low_power) {
715116a1
MC		 2208 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2209 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2210
2211 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2212 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2213 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2214 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2215 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2216 }
3f7045c1 2217
15c3b696
MC		 2218 /* The PHY should not be powered down on some chips because
2219 * of bugs.
2220 */
2221 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2223 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2224 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2225 return;
ce057f01 2226
bcb37f6c
MC		 2227 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2228 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2229 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2230 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2231 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2232 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2233 }
2234
15c3b696
MC		 2235 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2236}
2237
ffbcfed4
MC		 2238/* tp->lock is held. */
2239static int tg3_nvram_lock(struct tg3 *tp)
2240{
2241 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2242 int i;
2243
2244 if (tp->nvram_lock_cnt == 0) {
2245 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2246 for (i = 0; i < 8000; i++) {
2247 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2248 break;
2249 udelay(20);
2250 }
2251 if (i == 8000) {
2252 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2253 return -ENODEV;
2254 }
2255 }
2256 tp->nvram_lock_cnt++;
2257 }
2258 return 0;
2259}
2260
2261/* tp->lock is held. */
2262static void tg3_nvram_unlock(struct tg3 *tp)
2263{
2264 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2265 if (tp->nvram_lock_cnt > 0)
2266 tp->nvram_lock_cnt--;
2267 if (tp->nvram_lock_cnt == 0)
2268 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2269 }
2270}
2271
2272/* tp->lock is held. */
2273static void tg3_enable_nvram_access(struct tg3 *tp)
2274{
2275 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2276 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2277 u32 nvaccess = tr32(NVRAM_ACCESS);
2278
2279 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2280 }
2281}
2282
2283/* tp->lock is held. */
2284static void tg3_disable_nvram_access(struct tg3 *tp)
2285{
2286 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2287 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2288 u32 nvaccess = tr32(NVRAM_ACCESS);
2289
2290 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2291 }
2292}
2293
2294static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2295 u32 offset, u32 *val)
2296{
2297 u32 tmp;
2298 int i;
2299
2300 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2301 return -EINVAL;
2302
2303 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2304 EEPROM_ADDR_DEVID_MASK |
2305 EEPROM_ADDR_READ);
2306 tw32(GRC_EEPROM_ADDR,
2307 tmp |
2308 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2309 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2310 EEPROM_ADDR_ADDR_MASK) |
2311 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2312
2313 for (i = 0; i < 1000; i++) {
2314 tmp = tr32(GRC_EEPROM_ADDR);
2315
2316 if (tmp & EEPROM_ADDR_COMPLETE)
2317 break;
2318 msleep(1);
2319 }
2320 if (!(tmp & EEPROM_ADDR_COMPLETE))
2321 return -EBUSY;
2322
62cedd11
MC		 2323 tmp = tr32(GRC_EEPROM_DATA);
2324
2325 /*
2326 * The data will always be opposite the native endian
2327 * format. Perform a blind byteswap to compensate.
2328 */
2329 *val = swab32(tmp);
2330
ffbcfed4
MC		 2331 return 0;
2332}
2333
2334#define NVRAM_CMD_TIMEOUT 10000
2335
2336static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2337{
2338 int i;
2339
2340 tw32(NVRAM_CMD, nvram_cmd);
2341 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2342 udelay(10);
2343 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2344 udelay(10);
2345 break;
2346 }
2347 }
2348
2349 if (i == NVRAM_CMD_TIMEOUT)
2350 return -EBUSY;
2351
2352 return 0;
2353}
2354
2355static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2356{
2357 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361 (tp->nvram_jedecnum == JEDEC_ATMEL))
2362
2363 addr = ((addr / tp->nvram_pagesize) <<
2364 ATMEL_AT45DB0X1B_PAGE_POS) +
2365 (addr % tp->nvram_pagesize);
2366
2367 return addr;
2368}
2369
2370static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2371{
2372 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2373 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2374 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2375 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2376 (tp->nvram_jedecnum == JEDEC_ATMEL))
2377
2378 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2379 tp->nvram_pagesize) +
2380 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2381
2382 return addr;
2383}
2384
e4f34110
MC		 2385/* NOTE: Data read in from NVRAM is byteswapped according to
2386 * the byteswapping settings for all other register accesses.
2387 * tg3 devices are BE devices, so on a BE machine, the data
2388 * returned will be exactly as it is seen in NVRAM. On a LE
2389 * machine, the 32-bit value will be byteswapped.
2390 */
ffbcfed4
MC		 2391static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2392{
2393 int ret;
2394
2395 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2396 return tg3_nvram_read_using_eeprom(tp, offset, val);
2397
2398 offset = tg3_nvram_phys_addr(tp, offset);
2399
2400 if (offset > NVRAM_ADDR_MSK)
2401 return -EINVAL;
2402
2403 ret = tg3_nvram_lock(tp);
2404 if (ret)
2405 return ret;
2406
2407 tg3_enable_nvram_access(tp);
2408
2409 tw32(NVRAM_ADDR, offset);
2410 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2411 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2412
2413 if (ret == 0)
e4f34110 2414 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2415
2416 tg3_disable_nvram_access(tp);
2417
2418 tg3_nvram_unlock(tp);
2419
2420 return ret;
2421}
2422
a9dc529d
MC		 2423/* Ensures NVRAM data is in bytestream format. */
2424static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2425{
2426 u32 v;
a9dc529d 2427 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2428 if (!res)
a9dc529d 2429 *val = cpu_to_be32(v);
ffbcfed4
MC		 2430 return res;
2431}
2432
3f007891
MC		 2433/* tp->lock is held. */
2434static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2435{
2436 u32 addr_high, addr_low;
2437 int i;
2438
2439 addr_high = ((tp->dev->dev_addr[0] << 8) |
2440 tp->dev->dev_addr[1]);
2441 addr_low = ((tp->dev->dev_addr[2] << 24) |
2442 (tp->dev->dev_addr[3] << 16) |
2443 (tp->dev->dev_addr[4] << 8) |
2444 (tp->dev->dev_addr[5] << 0));
2445 for (i = 0; i < 4; i++) {
2446 if (i == 1 && skip_mac_1)
2447 continue;
2448 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2449 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2450 }
2451
2452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2453 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2454 for (i = 0; i < 12; i++) {
2455 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2456 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2457 }
2458 }
2459
2460 addr_high = (tp->dev->dev_addr[0] +
2461 tp->dev->dev_addr[1] +
2462 tp->dev->dev_addr[2] +
2463 tp->dev->dev_addr[3] +
2464 tp->dev->dev_addr[4] +
2465 tp->dev->dev_addr[5]) &
2466 TX_BACKOFF_SEED_MASK;
2467 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2468}
2469
bc1c7567 2470static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2471{
2472 u32 misc_host_ctrl;
0a459aac 2473 bool device_should_wake, do_low_power;
1da177e4
LT		 2474
2475 /* Make sure register accesses (indirect or otherwise)
2476 * will function correctly.
2477 */
2478 pci_write_config_dword(tp->pdev,
2479 TG3PCI_MISC_HOST_CTRL,
2480 tp->misc_host_ctrl);
2481
1da177e4 2482 switch (state) {
bc1c7567 2483 case PCI_D0:
12dac075
RW		 2484 pci_enable_wake(tp->pdev, state, false);
2485 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2486
9d26e213
MC		 2487 /* Switch out of Vaux if it is a NIC */
2488 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2489 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2490
2491 return 0;
2492
bc1c7567 2493 case PCI_D1:
bc1c7567 2494 case PCI_D2:
bc1c7567 2495 case PCI_D3hot:
1da177e4
LT		 2496 break;
2497
2498 default:
05dbe005
JP		 2499 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2500 state);
1da177e4 2501 return -EINVAL;
855e1111 2502 }
5e7dfd0f
MC		 2503
2504 /* Restore the CLKREQ setting. */
2505 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2506 u16 lnkctl;
2507
2508 pci_read_config_word(tp->pdev,
2509 tp->pcie_cap + PCI_EXP_LNKCTL,
2510 &lnkctl);
2511 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2512 pci_write_config_word(tp->pdev,
2513 tp->pcie_cap + PCI_EXP_LNKCTL,
2514 lnkctl);
2515 }
2516
1da177e4
LT		 2517 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2518 tw32(TG3PCI_MISC_HOST_CTRL,
2519 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2520
05ac4cb7
MC		 2521 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2522 device_may_wakeup(&tp->pdev->dev) &&
2523 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2524
dd477003 2525 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2526 do_low_power = false;
b02fd9e3
MC		 2527 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2528 !tp->link_config.phy_is_low_power) {
2529 struct phy_device *phydev;
0a459aac 2530 u32 phyid, advertising;
b02fd9e3 2531
3f0e3ad7 2532 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2533
2534 tp->link_config.phy_is_low_power = 1;
2535
2536 tp->link_config.orig_speed = phydev->speed;
2537 tp->link_config.orig_duplex = phydev->duplex;
2538 tp->link_config.orig_autoneg = phydev->autoneg;
2539 tp->link_config.orig_advertising = phydev->advertising;
2540
2541 advertising = ADVERTISED_TP |
2542 ADVERTISED_Pause |
2543 ADVERTISED_Autoneg |
2544 ADVERTISED_10baseT_Half;
2545
2546 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2547 device_should_wake) {
b02fd9e3
MC		 2548 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2549 advertising |=
2550 ADVERTISED_100baseT_Half |
2551 ADVERTISED_100baseT_Full |
2552 ADVERTISED_10baseT_Full;
2553 else
2554 advertising |= ADVERTISED_10baseT_Full;
2555 }
2556
2557 phydev->advertising = advertising;
2558
2559 phy_start_aneg(phydev);
0a459aac
MC		 2560
2561 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 2562 if (phyid != PHY_ID_BCMAC131) {
2563 phyid &= PHY_BCM_OUI_MASK;
2564 if (phyid == PHY_BCM_OUI_1 ||
2565 phyid == PHY_BCM_OUI_2 ||
2566 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 2567 do_low_power = true;
2568 }
b02fd9e3 2569 }
dd477003 2570 } else {
2023276e 2571 do_low_power = true;
0a459aac 2572
dd477003
MC		 2573 if (tp->link_config.phy_is_low_power == 0) {
2574 tp->link_config.phy_is_low_power = 1;
2575 tp->link_config.orig_speed = tp->link_config.speed;
2576 tp->link_config.orig_duplex = tp->link_config.duplex;
2577 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2578 }
1da177e4 2579
dd477003
MC		 2580 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2581 tp->link_config.speed = SPEED_10;
2582 tp->link_config.duplex = DUPLEX_HALF;
2583 tp->link_config.autoneg = AUTONEG_ENABLE;
2584 tg3_setup_phy(tp, 0);
2585 }
1da177e4
LT		 2586 }
2587
b5d3772c
MC		 2588 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2589 u32 val;
2590
2591 val = tr32(GRC_VCPU_EXT_CTRL);
2592 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2593 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2594 int i;
2595 u32 val;
2596
2597 for (i = 0; i < 200; i++) {
2598 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2599 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2600 break;
2601 msleep(1);
2602 }
2603 }
a85feb8c
GZ		 2604 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2605 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2606 WOL_DRV_STATE_SHUTDOWN |
2607 WOL_DRV_WOL |
2608 WOL_SET_MAGIC_PKT);
6921d201 2609
05ac4cb7 2610 if (device_should_wake) {
1da177e4
LT		 2611 u32 mac_mode;
2612
2613 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2614 if (do_low_power) {
dd477003
MC		 2615 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2616 udelay(40);
2617 }
1da177e4 2618
3f7045c1
MC		 2619 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2620 mac_mode = MAC_MODE_PORT_MODE_GMII;
2621 else
2622 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2623
e8f3f6ca
MC		 2624 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2625 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2626 ASIC_REV_5700) {
2627 u32 speed = (tp->tg3_flags &
2628 TG3_FLAG_WOL_SPEED_100MB) ?
2629 SPEED_100 : SPEED_10;
2630 if (tg3_5700_link_polarity(tp, speed))
2631 mac_mode |= MAC_MODE_LINK_POLARITY;
2632 else
2633 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2634 }
1da177e4
LT		 2635 } else {
2636 mac_mode = MAC_MODE_PORT_MODE_TBI;
2637 }
2638
cbf46853 2639 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2640 tw32(MAC_LED_CTRL, tp->led_ctrl);
2641
05ac4cb7
MC		 2642 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2643 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2644 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2645 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2646 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2647 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2648
3bda1258
MC		 2649 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2650 mac_mode |= tp->mac_mode &
2651 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2652 if (mac_mode & MAC_MODE_APE_TX_EN)
2653 mac_mode |= MAC_MODE_TDE_ENABLE;
2654 }
2655
1da177e4
LT		 2656 tw32_f(MAC_MODE, mac_mode);
2657 udelay(100);
2658
2659 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2660 udelay(10);
2661 }
2662
2663 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2664 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2665 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2666 u32 base_val;
2667
2668 base_val = tp->pci_clock_ctrl;
2669 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2670 CLOCK_CTRL_TXCLK_DISABLE);
2671
b401e9e2
MC		 2672 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2673 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2674 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2675 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2676 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2677 /* do nothing */
85e94ced 2678 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2679 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2680 u32 newbits1, newbits2;
2681
2682 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2683 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2684 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2685 CLOCK_CTRL_TXCLK_DISABLE |
2686 CLOCK_CTRL_ALTCLK);
2687 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2688 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2689 newbits1 = CLOCK_CTRL_625_CORE;
2690 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2691 } else {
2692 newbits1 = CLOCK_CTRL_ALTCLK;
2693 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2694 }
2695
b401e9e2
MC		 2696 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2697 40);
1da177e4 2698
b401e9e2
MC		 2699 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2700 40);
1da177e4
LT		 2701
2702 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2703 u32 newbits3;
2704
2705 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2706 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2707 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2708 CLOCK_CTRL_TXCLK_DISABLE |
2709 CLOCK_CTRL_44MHZ_CORE);
2710 } else {
2711 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2712 }
2713
b401e9e2
MC		 2714 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2715 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2716 }
2717 }
2718
05ac4cb7 2719 if (!(device_should_wake) &&
22435849 2720 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2721 tg3_power_down_phy(tp, do_low_power);
6921d201 2722
1da177e4
LT		 2723 tg3_frob_aux_power(tp);
2724
2725 /* Workaround for unstable PLL clock */
2726 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2727 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2728 u32 val = tr32(0x7d00);
2729
2730 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2731 tw32(0x7d00, val);
6921d201 2732 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2733 int err;
2734
2735 err = tg3_nvram_lock(tp);
1da177e4 2736 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2737 if (!err)
2738 tg3_nvram_unlock(tp);
6921d201 2739 }
1da177e4
LT		 2740 }
2741
bbadf503
MC		 2742 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2743
05ac4cb7 2744 if (device_should_wake)
12dac075
RW		 2745 pci_enable_wake(tp->pdev, state, true);
2746
1da177e4 2747 /* Finally, set the new power state. */
12dac075 2748 pci_set_power_state(tp->pdev, state);
1da177e4 2749
1da177e4
LT		 2750 return 0;
2751}
2752
1da177e4
LT		 2753static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2754{
2755 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2756 case MII_TG3_AUX_STAT_10HALF:
2757 *speed = SPEED_10;
2758 *duplex = DUPLEX_HALF;
2759 break;
2760
2761 case MII_TG3_AUX_STAT_10FULL:
2762 *speed = SPEED_10;
2763 *duplex = DUPLEX_FULL;
2764 break;
2765
2766 case MII_TG3_AUX_STAT_100HALF:
2767 *speed = SPEED_100;
2768 *duplex = DUPLEX_HALF;
2769 break;
2770
2771 case MII_TG3_AUX_STAT_100FULL:
2772 *speed = SPEED_100;
2773 *duplex = DUPLEX_FULL;
2774 break;
2775
2776 case MII_TG3_AUX_STAT_1000HALF:
2777 *speed = SPEED_1000;
2778 *duplex = DUPLEX_HALF;
2779 break;
2780
2781 case MII_TG3_AUX_STAT_1000FULL:
2782 *speed = SPEED_1000;
2783 *duplex = DUPLEX_FULL;
2784 break;
2785
2786 default:
7f97a4bd 2787 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2788 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2789 SPEED_10;
2790 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2791 DUPLEX_HALF;
2792 break;
2793 }
1da177e4
LT		 2794 *speed = SPEED_INVALID;
2795 *duplex = DUPLEX_INVALID;
2796 break;
855e1111 2797 }
1da177e4
LT		 2798}
2799
2800static void tg3_phy_copper_begin(struct tg3 *tp)
2801{
2802 u32 new_adv;
2803 int i;
2804
2805 if (tp->link_config.phy_is_low_power) {
2806 /* Entering low power mode. Disable gigabit and
2807 * 100baseT advertisements.
2808 */
2809 tg3_writephy(tp, MII_TG3_CTRL, 0);
2810
2811 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2812 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2813 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2814 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2815
2816 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2817 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2818 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2819 tp->link_config.advertising &=
2820 ~(ADVERTISED_1000baseT_Half |
2821 ADVERTISED_1000baseT_Full);
2822
ba4d07a8 2823 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2824 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2825 new_adv |= ADVERTISE_10HALF;
2826 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2827 new_adv |= ADVERTISE_10FULL;
2828 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2829 new_adv |= ADVERTISE_100HALF;
2830 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2831 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2832
2833 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2834
1da177e4
LT		 2835 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837 if (tp->link_config.advertising &
2838 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2839 new_adv = 0;
2840 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2841 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2842 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2843 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2844 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2845 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2846 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2847 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2848 MII_TG3_CTRL_ENABLE_AS_MASTER);
2849 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2850 } else {
2851 tg3_writephy(tp, MII_TG3_CTRL, 0);
2852 }
2853 } else {
ba4d07a8
MC		 2854 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2855 new_adv |= ADVERTISE_CSMA;
2856
1da177e4
LT		 2857 /* Asking for a specific link mode. */
2858 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2859 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2860
2861 if (tp->link_config.duplex == DUPLEX_FULL)
2862 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2863 else
2864 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2865 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2866 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2867 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2868 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2869 } else {
1da177e4
LT		 2870 if (tp->link_config.speed == SPEED_100) {
2871 if (tp->link_config.duplex == DUPLEX_FULL)
2872 new_adv |= ADVERTISE_100FULL;
2873 else
2874 new_adv |= ADVERTISE_100HALF;
2875 } else {
2876 if (tp->link_config.duplex == DUPLEX_FULL)
2877 new_adv |= ADVERTISE_10FULL;
2878 else
2879 new_adv |= ADVERTISE_10HALF;
2880 }
2881 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2882
2883 new_adv = 0;
1da177e4 2884 }
ba4d07a8
MC		 2885
2886 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2887 }
2888
2889 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2890 tp->link_config.speed != SPEED_INVALID) {
2891 u32 bmcr, orig_bmcr;
2892
2893 tp->link_config.active_speed = tp->link_config.speed;
2894 tp->link_config.active_duplex = tp->link_config.duplex;
2895
2896 bmcr = 0;
2897 switch (tp->link_config.speed) {
2898 default:
2899 case SPEED_10:
2900 break;
2901
2902 case SPEED_100:
2903 bmcr |= BMCR_SPEED100;
2904 break;
2905
2906 case SPEED_1000:
2907 bmcr |= TG3_BMCR_SPEED1000;
2908 break;
855e1111 2909 }
1da177e4
LT		 2910
2911 if (tp->link_config.duplex == DUPLEX_FULL)
2912 bmcr |= BMCR_FULLDPLX;
2913
2914 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2915 (bmcr != orig_bmcr)) {
2916 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2917 for (i = 0; i < 1500; i++) {
2918 u32 tmp;
2919
2920 udelay(10);
2921 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2922 tg3_readphy(tp, MII_BMSR, &tmp))
2923 continue;
2924 if (!(tmp & BMSR_LSTATUS)) {
2925 udelay(40);
2926 break;
2927 }
2928 }
2929 tg3_writephy(tp, MII_BMCR, bmcr);
2930 udelay(40);
2931 }
2932 } else {
2933 tg3_writephy(tp, MII_BMCR,
2934 BMCR_ANENABLE | BMCR_ANRESTART);
2935 }
2936}
2937
2938static int tg3_init_5401phy_dsp(struct tg3 *tp)
2939{
2940 int err;
2941
2942 /* Turn off tap power management. */
2943 /* Set Extended packet length bit */
2944 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2945
2946 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2947 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2948
2949 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2950 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2951
2952 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2953 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2954
2955 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2956 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2957
2958 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2959 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2960
2961 udelay(40);
2962
2963 return err;
2964}
2965
3600d918 2966static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2967{
3600d918
MC		 2968 u32 adv_reg, all_mask = 0;
2969
2970 if (mask & ADVERTISED_10baseT_Half)
2971 all_mask |= ADVERTISE_10HALF;
2972 if (mask & ADVERTISED_10baseT_Full)
2973 all_mask |= ADVERTISE_10FULL;
2974 if (mask & ADVERTISED_100baseT_Half)
2975 all_mask |= ADVERTISE_100HALF;
2976 if (mask & ADVERTISED_100baseT_Full)
2977 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2978
2979 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2980 return 0;
2981
1da177e4
LT		 2982 if ((adv_reg & all_mask) != all_mask)
2983 return 0;
2984 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2985 u32 tg3_ctrl;
2986
3600d918
MC		 2987 all_mask = 0;
2988 if (mask & ADVERTISED_1000baseT_Half)
2989 all_mask |= ADVERTISE_1000HALF;
2990 if (mask & ADVERTISED_1000baseT_Full)
2991 all_mask |= ADVERTISE_1000FULL;
2992
1da177e4
LT		 2993 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2994 return 0;
2995
1da177e4
LT		 2996 if ((tg3_ctrl & all_mask) != all_mask)
2997 return 0;
2998 }
2999 return 1;
3000}
3001
ef167e27
MC		 3002static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3003{
3004 u32 curadv, reqadv;
3005
3006 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3007 return 1;
3008
3009 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3010 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3011
3012 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3013 if (curadv != reqadv)
3014 return 0;
3015
3016 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3017 tg3_readphy(tp, MII_LPA, rmtadv);
3018 } else {
3019 /* Reprogram the advertisement register, even if it
3020 * does not affect the current link. If the link
3021 * gets renegotiated in the future, we can save an
3022 * additional renegotiation cycle by advertising
3023 * it correctly in the first place.
3024 */
3025 if (curadv != reqadv) {
3026 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3027 ADVERTISE_PAUSE_ASYM);
3028 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3029 }
3030 }
3031
3032 return 1;
3033}
3034
1da177e4
LT		 3035static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3036{
3037 int current_link_up;
3038 u32 bmsr, dummy;
ef167e27 3039 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3040 u16 current_speed;
3041 u8 current_duplex;
3042 int i, err;
3043
3044 tw32(MAC_EVENT, 0);
3045
3046 tw32_f(MAC_STATUS,
3047 (MAC_STATUS_SYNC_CHANGED |
3048 MAC_STATUS_CFG_CHANGED |
3049 MAC_STATUS_MI_COMPLETION |
3050 MAC_STATUS_LNKSTATE_CHANGED));
3051 udelay(40);
3052
8ef21428
MC		 3053 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3054 tw32_f(MAC_MI_MODE,
3055 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3056 udelay(80);
3057 }
1da177e4
LT		 3058
3059 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3060
3061 /* Some third-party PHYs need to be reset on link going
3062 * down.
3063 */
3064 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3065 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3067 netif_carrier_ok(tp->dev)) {
3068 tg3_readphy(tp, MII_BMSR, &bmsr);
3069 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3070 !(bmsr & BMSR_LSTATUS))
3071 force_reset = 1;
3072 }
3073 if (force_reset)
3074 tg3_phy_reset(tp);
3075
79eb6904 3076 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 3077 tg3_readphy(tp, MII_BMSR, &bmsr);
3078 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3079 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3080 bmsr = 0;
3081
3082 if (!(bmsr & BMSR_LSTATUS)) {
3083 err = tg3_init_5401phy_dsp(tp);
3084 if (err)
3085 return err;
3086
3087 tg3_readphy(tp, MII_BMSR, &bmsr);
3088 for (i = 0; i < 1000; i++) {
3089 udelay(10);
3090 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3091 (bmsr & BMSR_LSTATUS)) {
3092 udelay(40);
3093 break;
3094 }
3095 }
3096
79eb6904
MC		 3097 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3098 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 3099 !(bmsr & BMSR_LSTATUS) &&
3100 tp->link_config.active_speed == SPEED_1000) {
3101 err = tg3_phy_reset(tp);
3102 if (!err)
3103 err = tg3_init_5401phy_dsp(tp);
3104 if (err)
3105 return err;
3106 }
3107 }
3108 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3109 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3110 /* 5701 {A0,B0} CRC bug workaround */
3111 tg3_writephy(tp, 0x15, 0x0a75);
3112 tg3_writephy(tp, 0x1c, 0x8c68);
3113 tg3_writephy(tp, 0x1c, 0x8d68);
3114 tg3_writephy(tp, 0x1c, 0x8c68);
3115 }
3116
3117 /* Clear pending interrupts... */
3118 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3119 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3120
3121 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3122 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3123 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3124 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3125
3126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3128 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3129 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3130 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3131 else
3132 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3133 }
3134
3135 current_link_up = 0;
3136 current_speed = SPEED_INVALID;
3137 current_duplex = DUPLEX_INVALID;
3138
3139 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3140 u32 val;
3141
3142 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3143 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3144 if (!(val & (1 << 10))) {
3145 val |= (1 << 10);
3146 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3147 goto relink;
3148 }
3149 }
3150
3151 bmsr = 0;
3152 for (i = 0; i < 100; i++) {
3153 tg3_readphy(tp, MII_BMSR, &bmsr);
3154 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3155 (bmsr & BMSR_LSTATUS))
3156 break;
3157 udelay(40);
3158 }
3159
3160 if (bmsr & BMSR_LSTATUS) {
3161 u32 aux_stat, bmcr;
3162
3163 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3164 for (i = 0; i < 2000; i++) {
3165 udelay(10);
3166 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3167 aux_stat)
3168 break;
3169 }
3170
3171 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3172 &current_speed,
3173 &current_duplex);
3174
3175 bmcr = 0;
3176 for (i = 0; i < 200; i++) {
3177 tg3_readphy(tp, MII_BMCR, &bmcr);
3178 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3179 continue;
3180 if (bmcr && bmcr != 0x7fff)
3181 break;
3182 udelay(10);
3183 }
3184
ef167e27
MC		 3185 lcl_adv = 0;
3186 rmt_adv = 0;
1da177e4 3187
ef167e27
MC		 3188 tp->link_config.active_speed = current_speed;
3189 tp->link_config.active_duplex = current_duplex;
3190
3191 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3192 if ((bmcr & BMCR_ANENABLE) &&
3193 tg3_copper_is_advertising_all(tp,
3194 tp->link_config.advertising)) {
3195 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3196 &rmt_adv))
3197 current_link_up = 1;
1da177e4
LT		 3198 }
3199 } else {
3200 if (!(bmcr & BMCR_ANENABLE) &&
3201 tp->link_config.speed == current_speed &&
ef167e27
MC		 3202 tp->link_config.duplex == current_duplex &&
3203 tp->link_config.flowctrl ==
3204 tp->link_config.active_flowctrl) {
1da177e4 3205 current_link_up = 1;
1da177e4
LT		 3206 }
3207 }
3208
ef167e27
MC		 3209 if (current_link_up == 1 &&
3210 tp->link_config.active_duplex == DUPLEX_FULL)
3211 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3212 }
3213
1da177e4 3214relink:
6921d201 3215 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3216 u32 tmp;
3217
3218 tg3_phy_copper_begin(tp);
3219
3220 tg3_readphy(tp, MII_BMSR, &tmp);
3221 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3222 (tmp & BMSR_LSTATUS))
3223 current_link_up = 1;
3224 }
3225
3226 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3227 if (current_link_up == 1) {
3228 if (tp->link_config.active_speed == SPEED_100 ||
3229 tp->link_config.active_speed == SPEED_10)
3230 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3231 else
3232 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3233 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3234 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3235 else
1da177e4
LT		 3236 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3237
3238 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3239 if (tp->link_config.active_duplex == DUPLEX_HALF)
3240 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3241
1da177e4 3242 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3243 if (current_link_up == 1 &&
3244 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3245 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3246 else
3247 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3248 }
3249
3250 /* ??? Without this setting Netgear GA302T PHY does not
3251 * ??? send/receive packets...
3252 */
79eb6904 3253 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
1da177e4
LT		 3254 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3255 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3256 tw32_f(MAC_MI_MODE, tp->mi_mode);
3257 udelay(80);
3258 }
3259
3260 tw32_f(MAC_MODE, tp->mac_mode);
3261 udelay(40);
3262
3263 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3264 /* Polled via timer. */
3265 tw32_f(MAC_EVENT, 0);
3266 } else {
3267 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3268 }
3269 udelay(40);
3270
3271 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3272 current_link_up == 1 &&
3273 tp->link_config.active_speed == SPEED_1000 &&
3274 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3275 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3276 udelay(120);
3277 tw32_f(MAC_STATUS,
3278 (MAC_STATUS_SYNC_CHANGED |
3279 MAC_STATUS_CFG_CHANGED));
3280 udelay(40);
3281 tg3_write_mem(tp,
3282 NIC_SRAM_FIRMWARE_MBOX,
3283 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3284 }
3285
5e7dfd0f
MC		 3286 /* Prevent send BD corruption. */
3287 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3288 u16 oldlnkctl, newlnkctl;
3289
3290 pci_read_config_word(tp->pdev,
3291 tp->pcie_cap + PCI_EXP_LNKCTL,
3292 &oldlnkctl);
3293 if (tp->link_config.active_speed == SPEED_100 ||
3294 tp->link_config.active_speed == SPEED_10)
3295 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3296 else
3297 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3298 if (newlnkctl != oldlnkctl)
3299 pci_write_config_word(tp->pdev,
3300 tp->pcie_cap + PCI_EXP_LNKCTL,
3301 newlnkctl);
3302 }
3303
1da177e4
LT		 3304 if (current_link_up != netif_carrier_ok(tp->dev)) {
3305 if (current_link_up)
3306 netif_carrier_on(tp->dev);
3307 else
3308 netif_carrier_off(tp->dev);
3309 tg3_link_report(tp);
3310 }
3311
3312 return 0;
3313}
3314
3315struct tg3_fiber_aneginfo {
3316 int state;
3317#define ANEG_STATE_UNKNOWN 0
3318#define ANEG_STATE_AN_ENABLE 1
3319#define ANEG_STATE_RESTART_INIT 2
3320#define ANEG_STATE_RESTART 3
3321#define ANEG_STATE_DISABLE_LINK_OK 4
3322#define ANEG_STATE_ABILITY_DETECT_INIT 5
3323#define ANEG_STATE_ABILITY_DETECT 6
3324#define ANEG_STATE_ACK_DETECT_INIT 7
3325#define ANEG_STATE_ACK_DETECT 8
3326#define ANEG_STATE_COMPLETE_ACK_INIT 9
3327#define ANEG_STATE_COMPLETE_ACK 10
3328#define ANEG_STATE_IDLE_DETECT_INIT 11
3329#define ANEG_STATE_IDLE_DETECT 12
3330#define ANEG_STATE_LINK_OK 13
3331#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3332#define ANEG_STATE_NEXT_PAGE_WAIT 15
3333
3334 u32 flags;
3335#define MR_AN_ENABLE 0x00000001
3336#define MR_RESTART_AN 0x00000002
3337#define MR_AN_COMPLETE 0x00000004
3338#define MR_PAGE_RX 0x00000008
3339#define MR_NP_LOADED 0x00000010
3340#define MR_TOGGLE_TX 0x00000020
3341#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3342#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3343#define MR_LP_ADV_SYM_PAUSE 0x00000100
3344#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3345#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3346#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3347#define MR_LP_ADV_NEXT_PAGE 0x00001000
3348#define MR_TOGGLE_RX 0x00002000
3349#define MR_NP_RX 0x00004000
3350
3351#define MR_LINK_OK 0x80000000
3352
3353 unsigned long link_time, cur_time;
3354
3355 u32 ability_match_cfg;
3356 int ability_match_count;
3357
3358 char ability_match, idle_match, ack_match;
3359
3360 u32 txconfig, rxconfig;
3361#define ANEG_CFG_NP 0x00000080
3362#define ANEG_CFG_ACK 0x00000040
3363#define ANEG_CFG_RF2 0x00000020
3364#define ANEG_CFG_RF1 0x00000010
3365#define ANEG_CFG_PS2 0x00000001
3366#define ANEG_CFG_PS1 0x00008000
3367#define ANEG_CFG_HD 0x00004000
3368#define ANEG_CFG_FD 0x00002000
3369#define ANEG_CFG_INVAL 0x00001f06
3370
3371};
3372#define ANEG_OK 0
3373#define ANEG_DONE 1
3374#define ANEG_TIMER_ENAB 2
3375#define ANEG_FAILED -1
3376
3377#define ANEG_STATE_SETTLE_TIME 10000
3378
3379static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3380 struct tg3_fiber_aneginfo *ap)
3381{
5be73b47 3382 u16 flowctrl;
1da177e4
LT		 3383 unsigned long delta;
3384 u32 rx_cfg_reg;
3385 int ret;
3386
3387 if (ap->state == ANEG_STATE_UNKNOWN) {
3388 ap->rxconfig = 0;
3389 ap->link_time = 0;
3390 ap->cur_time = 0;
3391 ap->ability_match_cfg = 0;
3392 ap->ability_match_count = 0;
3393 ap->ability_match = 0;
3394 ap->idle_match = 0;
3395 ap->ack_match = 0;
3396 }
3397 ap->cur_time++;
3398
3399 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3400 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3401
3402 if (rx_cfg_reg != ap->ability_match_cfg) {
3403 ap->ability_match_cfg = rx_cfg_reg;
3404 ap->ability_match = 0;
3405 ap->ability_match_count = 0;
3406 } else {
3407 if (++ap->ability_match_count > 1) {
3408 ap->ability_match = 1;
3409 ap->ability_match_cfg = rx_cfg_reg;
3410 }
3411 }
3412 if (rx_cfg_reg & ANEG_CFG_ACK)
3413 ap->ack_match = 1;
3414 else
3415 ap->ack_match = 0;
3416
3417 ap->idle_match = 0;
3418 } else {
3419 ap->idle_match = 1;
3420 ap->ability_match_cfg = 0;
3421 ap->ability_match_count = 0;
3422 ap->ability_match = 0;
3423 ap->ack_match = 0;
3424
3425 rx_cfg_reg = 0;
3426 }
3427
3428 ap->rxconfig = rx_cfg_reg;
3429 ret = ANEG_OK;
3430
33f401ae 3431 switch (ap->state) {
1da177e4
LT		 3432 case ANEG_STATE_UNKNOWN:
3433 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3434 ap->state = ANEG_STATE_AN_ENABLE;
3435
3436 /* fallthru */
3437 case ANEG_STATE_AN_ENABLE:
3438 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3439 if (ap->flags & MR_AN_ENABLE) {
3440 ap->link_time = 0;
3441 ap->cur_time = 0;
3442 ap->ability_match_cfg = 0;
3443 ap->ability_match_count = 0;
3444 ap->ability_match = 0;
3445 ap->idle_match = 0;
3446 ap->ack_match = 0;
3447
3448 ap->state = ANEG_STATE_RESTART_INIT;
3449 } else {
3450 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3451 }
3452 break;
3453
3454 case ANEG_STATE_RESTART_INIT:
3455 ap->link_time = ap->cur_time;
3456 ap->flags &= ~(MR_NP_LOADED);
3457 ap->txconfig = 0;
3458 tw32(MAC_TX_AUTO_NEG, 0);
3459 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3460 tw32_f(MAC_MODE, tp->mac_mode);
3461 udelay(40);
3462
3463 ret = ANEG_TIMER_ENAB;
3464 ap->state = ANEG_STATE_RESTART;
3465
3466 /* fallthru */
3467 case ANEG_STATE_RESTART:
3468 delta = ap->cur_time - ap->link_time;
3469 if (delta > ANEG_STATE_SETTLE_TIME) {
3470 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3471 } else {
3472 ret = ANEG_TIMER_ENAB;
3473 }
3474 break;
3475
3476 case ANEG_STATE_DISABLE_LINK_OK:
3477 ret = ANEG_DONE;
3478 break;
3479
3480 case ANEG_STATE_ABILITY_DETECT_INIT:
3481 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3482 ap->txconfig = ANEG_CFG_FD;
3483 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3484 if (flowctrl & ADVERTISE_1000XPAUSE)
3485 ap->txconfig |= ANEG_CFG_PS1;
3486 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3487 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3488 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490 tw32_f(MAC_MODE, tp->mac_mode);
3491 udelay(40);
3492
3493 ap->state = ANEG_STATE_ABILITY_DETECT;
3494 break;
3495
3496 case ANEG_STATE_ABILITY_DETECT:
3497 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3498 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3499 }
3500 break;
3501
3502 case ANEG_STATE_ACK_DETECT_INIT:
3503 ap->txconfig |= ANEG_CFG_ACK;
3504 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3505 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3506 tw32_f(MAC_MODE, tp->mac_mode);
3507 udelay(40);
3508
3509 ap->state = ANEG_STATE_ACK_DETECT;
3510
3511 /* fallthru */
3512 case ANEG_STATE_ACK_DETECT:
3513 if (ap->ack_match != 0) {
3514 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3515 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3516 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3517 } else {
3518 ap->state = ANEG_STATE_AN_ENABLE;
3519 }
3520 } else if (ap->ability_match != 0 &&
3521 ap->rxconfig == 0) {
3522 ap->state = ANEG_STATE_AN_ENABLE;
3523 }
3524 break;
3525
3526 case ANEG_STATE_COMPLETE_ACK_INIT:
3527 if (ap->rxconfig & ANEG_CFG_INVAL) {
3528 ret = ANEG_FAILED;
3529 break;
3530 }
3531 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3532 MR_LP_ADV_HALF_DUPLEX |
3533 MR_LP_ADV_SYM_PAUSE |
3534 MR_LP_ADV_ASYM_PAUSE |
3535 MR_LP_ADV_REMOTE_FAULT1 |
3536 MR_LP_ADV_REMOTE_FAULT2 |
3537 MR_LP_ADV_NEXT_PAGE |
3538 MR_TOGGLE_RX |
3539 MR_NP_RX);
3540 if (ap->rxconfig & ANEG_CFG_FD)
3541 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3542 if (ap->rxconfig & ANEG_CFG_HD)
3543 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3544 if (ap->rxconfig & ANEG_CFG_PS1)
3545 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3546 if (ap->rxconfig & ANEG_CFG_PS2)
3547 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3548 if (ap->rxconfig & ANEG_CFG_RF1)
3549 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3550 if (ap->rxconfig & ANEG_CFG_RF2)
3551 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3552 if (ap->rxconfig & ANEG_CFG_NP)
3553 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3554
3555 ap->link_time = ap->cur_time;
3556
3557 ap->flags ^= (MR_TOGGLE_TX);
3558 if (ap->rxconfig & 0x0008)
3559 ap->flags |= MR_TOGGLE_RX;
3560 if (ap->rxconfig & ANEG_CFG_NP)
3561 ap->flags |= MR_NP_RX;
3562 ap->flags |= MR_PAGE_RX;
3563
3564 ap->state = ANEG_STATE_COMPLETE_ACK;
3565 ret = ANEG_TIMER_ENAB;
3566 break;
3567
3568 case ANEG_STATE_COMPLETE_ACK:
3569 if (ap->ability_match != 0 &&
3570 ap->rxconfig == 0) {
3571 ap->state = ANEG_STATE_AN_ENABLE;
3572 break;
3573 }
3574 delta = ap->cur_time - ap->link_time;
3575 if (delta > ANEG_STATE_SETTLE_TIME) {
3576 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3577 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3578 } else {
3579 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3580 !(ap->flags & MR_NP_RX)) {
3581 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3582 } else {
3583 ret = ANEG_FAILED;
3584 }
3585 }
3586 }
3587 break;
3588
3589 case ANEG_STATE_IDLE_DETECT_INIT:
3590 ap->link_time = ap->cur_time;
3591 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3592 tw32_f(MAC_MODE, tp->mac_mode);
3593 udelay(40);
3594
3595 ap->state = ANEG_STATE_IDLE_DETECT;
3596 ret = ANEG_TIMER_ENAB;
3597 break;
3598
3599 case ANEG_STATE_IDLE_DETECT:
3600 if (ap->ability_match != 0 &&
3601 ap->rxconfig == 0) {
3602 ap->state = ANEG_STATE_AN_ENABLE;
3603 break;
3604 }
3605 delta = ap->cur_time - ap->link_time;
3606 if (delta > ANEG_STATE_SETTLE_TIME) {
3607 /* XXX another gem from the Broadcom driver :( */
3608 ap->state = ANEG_STATE_LINK_OK;
3609 }
3610 break;
3611
3612 case ANEG_STATE_LINK_OK:
3613 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3614 ret = ANEG_DONE;
3615 break;
3616
3617 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3618 /* ??? unimplemented */
3619 break;
3620
3621 case ANEG_STATE_NEXT_PAGE_WAIT:
3622 /* ??? unimplemented */
3623 break;
3624
3625 default:
3626 ret = ANEG_FAILED;
3627 break;
855e1111 3628 }
1da177e4
LT		 3629
3630 return ret;
3631}
3632
5be73b47 3633static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3634{
3635 int res = 0;
3636 struct tg3_fiber_aneginfo aninfo;
3637 int status = ANEG_FAILED;
3638 unsigned int tick;
3639 u32 tmp;
3640
3641 tw32_f(MAC_TX_AUTO_NEG, 0);
3642
3643 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3644 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3645 udelay(40);
3646
3647 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3648 udelay(40);
3649
3650 memset(&aninfo, 0, sizeof(aninfo));
3651 aninfo.flags |= MR_AN_ENABLE;
3652 aninfo.state = ANEG_STATE_UNKNOWN;
3653 aninfo.cur_time = 0;
3654 tick = 0;
3655 while (++tick < 195000) {
3656 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3657 if (status == ANEG_DONE || status == ANEG_FAILED)
3658 break;
3659
3660 udelay(1);
3661 }
3662
3663 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3664 tw32_f(MAC_MODE, tp->mac_mode);
3665 udelay(40);
3666
5be73b47
MC		 3667 *txflags = aninfo.txconfig;
3668 *rxflags = aninfo.flags;
1da177e4
LT		 3669
3670 if (status == ANEG_DONE &&
3671 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3672 MR_LP_ADV_FULL_DUPLEX)))
3673 res = 1;
3674
3675 return res;
3676}
3677
3678static void tg3_init_bcm8002(struct tg3 *tp)
3679{
3680 u32 mac_status = tr32(MAC_STATUS);
3681 int i;
3682
3683 /* Reset when initting first time or we have a link. */
3684 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3685 !(mac_status & MAC_STATUS_PCS_SYNCED))
3686 return;
3687
3688 /* Set PLL lock range. */
3689 tg3_writephy(tp, 0x16, 0x8007);
3690
3691 /* SW reset */
3692 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3693
3694 /* Wait for reset to complete. */
3695 /* XXX schedule_timeout() ... */
3696 for (i = 0; i < 500; i++)
3697 udelay(10);
3698
3699 /* Config mode; select PMA/Ch 1 regs. */
3700 tg3_writephy(tp, 0x10, 0x8411);
3701
3702 /* Enable auto-lock and comdet, select txclk for tx. */
3703 tg3_writephy(tp, 0x11, 0x0a10);
3704
3705 tg3_writephy(tp, 0x18, 0x00a0);
3706 tg3_writephy(tp, 0x16, 0x41ff);
3707
3708 /* Assert and deassert POR. */
3709 tg3_writephy(tp, 0x13, 0x0400);
3710 udelay(40);
3711 tg3_writephy(tp, 0x13, 0x0000);
3712
3713 tg3_writephy(tp, 0x11, 0x0a50);
3714 udelay(40);
3715 tg3_writephy(tp, 0x11, 0x0a10);
3716
3717 /* Wait for signal to stabilize */
3718 /* XXX schedule_timeout() ... */
3719 for (i = 0; i < 15000; i++)
3720 udelay(10);
3721
3722 /* Deselect the channel register so we can read the PHYID
3723 * later.
3724 */
3725 tg3_writephy(tp, 0x10, 0x8011);
3726}
3727
3728static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3729{
82cd3d11 3730 u16 flowctrl;
1da177e4
LT		 3731 u32 sg_dig_ctrl, sg_dig_status;
3732 u32 serdes_cfg, expected_sg_dig_ctrl;
3733 int workaround, port_a;
3734 int current_link_up;
3735
3736 serdes_cfg = 0;
3737 expected_sg_dig_ctrl = 0;
3738 workaround = 0;
3739 port_a = 1;
3740 current_link_up = 0;
3741
3742 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3743 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3744 workaround = 1;
3745 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3746 port_a = 0;
3747
3748 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3749 /* preserve bits 20-23 for voltage regulator */
3750 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3751 }
3752
3753 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3754
3755 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3756 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3757 if (workaround) {
3758 u32 val = serdes_cfg;
3759
3760 if (port_a)
3761 val |= 0xc010000;
3762 else
3763 val |= 0x4010000;
3764 tw32_f(MAC_SERDES_CFG, val);
3765 }
c98f6e3b
MC		 3766
3767 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3768 }
3769 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3770 tg3_setup_flow_control(tp, 0, 0);
3771 current_link_up = 1;
3772 }
3773 goto out;
3774 }
3775
3776 /* Want auto-negotiation. */
c98f6e3b 3777 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3778
82cd3d11
MC		 3779 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3780 if (flowctrl & ADVERTISE_1000XPAUSE)
3781 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3782 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3783 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3784
3785 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3786 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3787 tp->serdes_counter &&
3788 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3789 MAC_STATUS_RCVD_CFG)) ==
3790 MAC_STATUS_PCS_SYNCED)) {
3791 tp->serdes_counter--;
3792 current_link_up = 1;
3793 goto out;
3794 }
3795restart_autoneg:
1da177e4
LT		 3796 if (workaround)
3797 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3798 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3799 udelay(5);
3800 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3801
3d3ebe74
MC		 3802 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3803 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3804 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3805 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3806 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3807 mac_status = tr32(MAC_STATUS);
3808
c98f6e3b 3809 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3810 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3811 u32 local_adv = 0, remote_adv = 0;
3812
3813 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3814 local_adv |= ADVERTISE_1000XPAUSE;
3815 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3816 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3817
c98f6e3b 3818 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3819 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3820 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3821 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3822
3823 tg3_setup_flow_control(tp, local_adv, remote_adv);
3824 current_link_up = 1;
3d3ebe74
MC		 3825 tp->serdes_counter = 0;
3826 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3827 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3828 if (tp->serdes_counter)
3829 tp->serdes_counter--;
1da177e4
LT		 3830 else {
3831 if (workaround) {
3832 u32 val = serdes_cfg;
3833
3834 if (port_a)
3835 val |= 0xc010000;
3836 else
3837 val |= 0x4010000;
3838
3839 tw32_f(MAC_SERDES_CFG, val);
3840 }
3841
c98f6e3b 3842 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3843 udelay(40);
3844
3845 /* Link parallel detection - link is up */
3846 /* only if we have PCS_SYNC and not */
3847 /* receiving config code words */
3848 mac_status = tr32(MAC_STATUS);
3849 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3850 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3851 tg3_setup_flow_control(tp, 0, 0);
3852 current_link_up = 1;
3d3ebe74
MC		 3853 tp->tg3_flags2 |=
3854 TG3_FLG2_PARALLEL_DETECT;
3855 tp->serdes_counter =
3856 SERDES_PARALLEL_DET_TIMEOUT;
3857 } else
3858 goto restart_autoneg;
1da177e4
LT		 3859 }
3860 }
3d3ebe74
MC		 3861 } else {
3862 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3863 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3864 }
3865
3866out:
3867 return current_link_up;
3868}
3869
3870static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3871{
3872 int current_link_up = 0;
3873
5cf64b8a 3874 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3875 goto out;
1da177e4
LT		 3876
3877 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3878 u32 txflags, rxflags;
1da177e4 3879 int i;
6aa20a22 3880
5be73b47
MC		 3881 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3882 u32 local_adv = 0, remote_adv = 0;
1da177e4 3883
5be73b47
MC		 3884 if (txflags & ANEG_CFG_PS1)
3885 local_adv |= ADVERTISE_1000XPAUSE;
3886 if (txflags & ANEG_CFG_PS2)
3887 local_adv |= ADVERTISE_1000XPSE_ASYM;
3888
3889 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3890 remote_adv |= LPA_1000XPAUSE;
3891 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3892 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3893
3894 tg3_setup_flow_control(tp, local_adv, remote_adv);
3895
1da177e4
LT		 3896 current_link_up = 1;
3897 }
3898 for (i = 0; i < 30; i++) {
3899 udelay(20);
3900 tw32_f(MAC_STATUS,
3901 (MAC_STATUS_SYNC_CHANGED |
3902 MAC_STATUS_CFG_CHANGED));
3903 udelay(40);
3904 if ((tr32(MAC_STATUS) &
3905 (MAC_STATUS_SYNC_CHANGED |
3906 MAC_STATUS_CFG_CHANGED)) == 0)
3907 break;
3908 }
3909
3910 mac_status = tr32(MAC_STATUS);
3911 if (current_link_up == 0 &&
3912 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3913 !(mac_status & MAC_STATUS_RCVD_CFG))
3914 current_link_up = 1;
3915 } else {
5be73b47
MC		 3916 tg3_setup_flow_control(tp, 0, 0);
3917
1da177e4
LT		 3918 /* Forcing 1000FD link up. */
3919 current_link_up = 1;
1da177e4
LT		 3920
3921 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3922 udelay(40);
e8f3f6ca
MC		 3923
3924 tw32_f(MAC_MODE, tp->mac_mode);
3925 udelay(40);
1da177e4
LT		 3926 }
3927
3928out:
3929 return current_link_up;
3930}
3931
3932static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3933{
3934 u32 orig_pause_cfg;
3935 u16 orig_active_speed;
3936 u8 orig_active_duplex;
3937 u32 mac_status;
3938 int current_link_up;
3939 int i;
3940
8d018621 3941 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3942 orig_active_speed = tp->link_config.active_speed;
3943 orig_active_duplex = tp->link_config.active_duplex;
3944
3945 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3946 netif_carrier_ok(tp->dev) &&
3947 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3948 mac_status = tr32(MAC_STATUS);
3949 mac_status &= (MAC_STATUS_PCS_SYNCED |
3950 MAC_STATUS_SIGNAL_DET |
3951 MAC_STATUS_CFG_CHANGED |
3952 MAC_STATUS_RCVD_CFG);
3953 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3954 MAC_STATUS_SIGNAL_DET)) {
3955 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3956 MAC_STATUS_CFG_CHANGED));
3957 return 0;
3958 }
3959 }
3960
3961 tw32_f(MAC_TX_AUTO_NEG, 0);
3962
3963 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3964 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3965 tw32_f(MAC_MODE, tp->mac_mode);
3966 udelay(40);
3967
79eb6904 3968 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 3969 tg3_init_bcm8002(tp);
3970
3971 /* Enable link change event even when serdes polling. */
3972 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3973 udelay(40);
3974
3975 current_link_up = 0;
3976 mac_status = tr32(MAC_STATUS);
3977
3978 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3979 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3980 else
3981 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3982
898a56f8 3983 tp->napi[0].hw_status->status =
1da177e4 3984 (SD_STATUS_UPDATED |
898a56f8 3985 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3986
3987 for (i = 0; i < 100; i++) {
3988 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3989 MAC_STATUS_CFG_CHANGED));
3990 udelay(5);
3991 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3992 MAC_STATUS_CFG_CHANGED |
3993 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3994 break;
3995 }
3996
3997 mac_status = tr32(MAC_STATUS);
3998 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3999 current_link_up = 0;
3d3ebe74
MC		 4000 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4001 tp->serdes_counter == 0) {
1da177e4
LT		 4002 tw32_f(MAC_MODE, (tp->mac_mode |
4003 MAC_MODE_SEND_CONFIGS));
4004 udelay(1);
4005 tw32_f(MAC_MODE, tp->mac_mode);
4006 }
4007 }
4008
4009 if (current_link_up == 1) {
4010 tp->link_config.active_speed = SPEED_1000;
4011 tp->link_config.active_duplex = DUPLEX_FULL;
4012 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4013 LED_CTRL_LNKLED_OVERRIDE |
4014 LED_CTRL_1000MBPS_ON));
4015 } else {
4016 tp->link_config.active_speed = SPEED_INVALID;
4017 tp->link_config.active_duplex = DUPLEX_INVALID;
4018 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4019 LED_CTRL_LNKLED_OVERRIDE |
4020 LED_CTRL_TRAFFIC_OVERRIDE));
4021 }
4022
4023 if (current_link_up != netif_carrier_ok(tp->dev)) {
4024 if (current_link_up)
4025 netif_carrier_on(tp->dev);
4026 else
4027 netif_carrier_off(tp->dev);
4028 tg3_link_report(tp);
4029 } else {
8d018621 4030 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4031 if (orig_pause_cfg != now_pause_cfg ||
4032 orig_active_speed != tp->link_config.active_speed ||
4033 orig_active_duplex != tp->link_config.active_duplex)
4034 tg3_link_report(tp);
4035 }
4036
4037 return 0;
4038}
4039
747e8f8b
MC		 4040static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4041{
4042 int current_link_up, err = 0;
4043 u32 bmsr, bmcr;
4044 u16 current_speed;
4045 u8 current_duplex;
ef167e27 4046 u32 local_adv, remote_adv;
747e8f8b
MC		 4047
4048 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4049 tw32_f(MAC_MODE, tp->mac_mode);
4050 udelay(40);
4051
4052 tw32(MAC_EVENT, 0);
4053
4054 tw32_f(MAC_STATUS,
4055 (MAC_STATUS_SYNC_CHANGED |
4056 MAC_STATUS_CFG_CHANGED |
4057 MAC_STATUS_MI_COMPLETION |
4058 MAC_STATUS_LNKSTATE_CHANGED));
4059 udelay(40);
4060
4061 if (force_reset)
4062 tg3_phy_reset(tp);
4063
4064 current_link_up = 0;
4065 current_speed = SPEED_INVALID;
4066 current_duplex = DUPLEX_INVALID;
4067
4068 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4069 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4071 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4072 bmsr |= BMSR_LSTATUS;
4073 else
4074 bmsr &= ~BMSR_LSTATUS;
4075 }
747e8f8b
MC		 4076
4077 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4078
4079 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4080 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4081 /* do nothing, just check for link up at the end */
4082 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4083 u32 adv, new_adv;
4084
4085 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4086 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4087 ADVERTISE_1000XPAUSE |
4088 ADVERTISE_1000XPSE_ASYM |
4089 ADVERTISE_SLCT);
4090
ba4d07a8 4091 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4092
4093 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4094 new_adv |= ADVERTISE_1000XHALF;
4095 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4096 new_adv |= ADVERTISE_1000XFULL;
4097
4098 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4099 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4100 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4101 tg3_writephy(tp, MII_BMCR, bmcr);
4102
4103 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4104 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4105 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4106
4107 return err;
4108 }
4109 } else {
4110 u32 new_bmcr;
4111
4112 bmcr &= ~BMCR_SPEED1000;
4113 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4114
4115 if (tp->link_config.duplex == DUPLEX_FULL)
4116 new_bmcr |= BMCR_FULLDPLX;
4117
4118 if (new_bmcr != bmcr) {
4119 /* BMCR_SPEED1000 is a reserved bit that needs
4120 * to be set on write.
4121 */
4122 new_bmcr |= BMCR_SPEED1000;
4123
4124 /* Force a linkdown */
4125 if (netif_carrier_ok(tp->dev)) {
4126 u32 adv;
4127
4128 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4129 adv &= ~(ADVERTISE_1000XFULL |
4130 ADVERTISE_1000XHALF |
4131 ADVERTISE_SLCT);
4132 tg3_writephy(tp, MII_ADVERTISE, adv);
4133 tg3_writephy(tp, MII_BMCR, bmcr |
4134 BMCR_ANRESTART |
4135 BMCR_ANENABLE);
4136 udelay(10);
4137 netif_carrier_off(tp->dev);
4138 }
4139 tg3_writephy(tp, MII_BMCR, new_bmcr);
4140 bmcr = new_bmcr;
4141 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4142 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4143 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4144 ASIC_REV_5714) {
4145 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4146 bmsr |= BMSR_LSTATUS;
4147 else
4148 bmsr &= ~BMSR_LSTATUS;
4149 }
747e8f8b
MC		 4150 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4151 }
4152 }
4153
4154 if (bmsr & BMSR_LSTATUS) {
4155 current_speed = SPEED_1000;
4156 current_link_up = 1;
4157 if (bmcr & BMCR_FULLDPLX)
4158 current_duplex = DUPLEX_FULL;
4159 else
4160 current_duplex = DUPLEX_HALF;
4161
ef167e27
MC		 4162 local_adv = 0;
4163 remote_adv = 0;
4164
747e8f8b 4165 if (bmcr & BMCR_ANENABLE) {
ef167e27 4166 u32 common;
747e8f8b
MC		 4167
4168 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4169 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4170 common = local_adv & remote_adv;
4171 if (common & (ADVERTISE_1000XHALF |
4172 ADVERTISE_1000XFULL)) {
4173 if (common & ADVERTISE_1000XFULL)
4174 current_duplex = DUPLEX_FULL;
4175 else
4176 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4177 }
4178 else
4179 current_link_up = 0;
4180 }
4181 }
4182
ef167e27
MC		 4183 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4184 tg3_setup_flow_control(tp, local_adv, remote_adv);
4185
747e8f8b
MC		 4186 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4187 if (tp->link_config.active_duplex == DUPLEX_HALF)
4188 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4189
4190 tw32_f(MAC_MODE, tp->mac_mode);
4191 udelay(40);
4192
4193 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4194
4195 tp->link_config.active_speed = current_speed;
4196 tp->link_config.active_duplex = current_duplex;
4197
4198 if (current_link_up != netif_carrier_ok(tp->dev)) {
4199 if (current_link_up)
4200 netif_carrier_on(tp->dev);
4201 else {
4202 netif_carrier_off(tp->dev);
4203 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4204 }
4205 tg3_link_report(tp);
4206 }
4207 return err;
4208}
4209
4210static void tg3_serdes_parallel_detect(struct tg3 *tp)
4211{
3d3ebe74 4212 if (tp->serdes_counter) {
747e8f8b 4213 /* Give autoneg time to complete. */
3d3ebe74 4214 tp->serdes_counter--;
747e8f8b
MC		 4215 return;
4216 }
c6cdf436 4217
747e8f8b
MC		 4218 if (!netif_carrier_ok(tp->dev) &&
4219 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4220 u32 bmcr;
4221
4222 tg3_readphy(tp, MII_BMCR, &bmcr);
4223 if (bmcr & BMCR_ANENABLE) {
4224 u32 phy1, phy2;
4225
4226 /* Select shadow register 0x1f */
4227 tg3_writephy(tp, 0x1c, 0x7c00);
4228 tg3_readphy(tp, 0x1c, &phy1);
4229
4230 /* Select expansion interrupt status register */
4231 tg3_writephy(tp, 0x17, 0x0f01);
4232 tg3_readphy(tp, 0x15, &phy2);
4233 tg3_readphy(tp, 0x15, &phy2);
4234
4235 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4236 /* We have signal detect and not receiving
4237 * config code words, link is up by parallel
4238 * detection.
4239 */
4240
4241 bmcr &= ~BMCR_ANENABLE;
4242 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4243 tg3_writephy(tp, MII_BMCR, bmcr);
4244 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4245 }
4246 }
4247 }
4248 else if (netif_carrier_ok(tp->dev) &&
4249 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4250 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4251 u32 phy2;
4252
4253 /* Select expansion interrupt status register */
4254 tg3_writephy(tp, 0x17, 0x0f01);
4255 tg3_readphy(tp, 0x15, &phy2);
4256 if (phy2 & 0x20) {
4257 u32 bmcr;
4258
4259 /* Config code words received, turn on autoneg. */
4260 tg3_readphy(tp, MII_BMCR, &bmcr);
4261 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4262
4263 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4264
4265 }
4266 }
4267}
4268
1da177e4
LT		 4269static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4270{
4271 int err;
4272
4273 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4274 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4275 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4276 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4277 } else {
4278 err = tg3_setup_copper_phy(tp, force_reset);
4279 }
4280
bcb37f6c 4281 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4282 u32 val, scale;
4283
4284 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4285 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4286 scale = 65;
4287 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4288 scale = 6;
4289 else
4290 scale = 12;
4291
4292 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4293 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4294 tw32(GRC_MISC_CFG, val);
4295 }
4296
1da177e4
LT		 4297 if (tp->link_config.active_speed == SPEED_1000 &&
4298 tp->link_config.active_duplex == DUPLEX_HALF)
4299 tw32(MAC_TX_LENGTHS,
4300 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4301 (6 << TX_LENGTHS_IPG_SHIFT) |
4302 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4303 else
4304 tw32(MAC_TX_LENGTHS,
4305 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4306 (6 << TX_LENGTHS_IPG_SHIFT) |
4307 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4308
4309 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4310 if (netif_carrier_ok(tp->dev)) {
4311 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4312 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4313 } else {
4314 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4315 }
4316 }
4317
8ed5d97e
MC		 4318 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4319 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4320 if (!netif_carrier_ok(tp->dev))
4321 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4322 tp->pwrmgmt_thresh;
4323 else
4324 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4325 tw32(PCIE_PWR_MGMT_THRESH, val);
4326 }
4327
1da177e4
LT		 4328 return err;
4329}
4330
df3e6548
MC		 4331/* This is called whenever we suspect that the system chipset is re-
4332 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4333 * is bogus tx completions. We try to recover by setting the
4334 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4335 * in the workqueue.
4336 */
4337static void tg3_tx_recover(struct tg3 *tp)
4338{
4339 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4340 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4341
5129c3a3
MC		 4342 netdev_warn(tp->dev,
4343 "The system may be re-ordering memory-mapped I/O "
4344 "cycles to the network device, attempting to recover. "
4345 "Please report the problem to the driver maintainer "
4346 "and include system chipset information.\n");
df3e6548
MC		 4347
4348 spin_lock(&tp->lock);
df3e6548 4349 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4350 spin_unlock(&tp->lock);
4351}
4352
f3f3f27e 4353static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4354{
4355 smp_mb();
f3f3f27e
MC		 4356 return tnapi->tx_pending -
4357 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4358}
4359
1da177e4
LT		 4360/* Tigon3 never reports partial packet sends. So we do not
4361 * need special logic to handle SKBs that have not had all
4362 * of their frags sent yet, like SunGEM does.
4363 */
17375d25 4364static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4365{
17375d25 4366 struct tg3 *tp = tnapi->tp;
898a56f8 4367 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4368 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4369 struct netdev_queue *txq;
4370 int index = tnapi - tp->napi;
4371
19cfaecc 4372 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4373 index--;
4374
4375 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4376
4377 while (sw_idx != hw_idx) {
f4188d8a 4378 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4379 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4380 int i, tx_bug = 0;
4381
4382 if (unlikely(skb == NULL)) {
4383 tg3_tx_recover(tp);
4384 return;
4385 }
1da177e4 4386
f4188d8a
AD		 4387 pci_unmap_single(tp->pdev,
4388 pci_unmap_addr(ri, mapping),
4389 skb_headlen(skb),
4390 PCI_DMA_TODEVICE);
1da177e4
LT		 4391
4392 ri->skb = NULL;
4393
4394 sw_idx = NEXT_TX(sw_idx);
4395
4396 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4397 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4398 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4399 tx_bug = 1;
f4188d8a
AD		 4400
4401 pci_unmap_page(tp->pdev,
4402 pci_unmap_addr(ri, mapping),
4403 skb_shinfo(skb)->frags[i].size,
4404 PCI_DMA_TODEVICE);
1da177e4
LT		 4405 sw_idx = NEXT_TX(sw_idx);
4406 }
4407
f47c11ee 4408 dev_kfree_skb(skb);
df3e6548
MC		 4409
4410 if (unlikely(tx_bug)) {
4411 tg3_tx_recover(tp);
4412 return;
4413 }
1da177e4
LT		 4414 }
4415
f3f3f27e 4416 tnapi->tx_cons = sw_idx;
1da177e4 4417
1b2a7205
MC		 4418 /* Need to make the tx_cons update visible to tg3_start_xmit()
4419 * before checking for netif_queue_stopped(). Without the
4420 * memory barrier, there is a small possibility that tg3_start_xmit()
4421 * will miss it and cause the queue to be stopped forever.
4422 */
4423 smp_mb();
4424
fe5f5787 4425 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4426 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4427 __netif_tx_lock(txq, smp_processor_id());
4428 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4429 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4430 netif_tx_wake_queue(txq);
4431 __netif_tx_unlock(txq);
51b91468 4432 }
1da177e4
LT		 4433}
4434
2b2cdb65
MC		 4435static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4436{
4437 if (!ri->skb)
4438 return;
4439
4440 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4441 map_sz, PCI_DMA_FROMDEVICE);
4442 dev_kfree_skb_any(ri->skb);
4443 ri->skb = NULL;
4444}
4445
1da177e4
LT		 4446/* Returns size of skb allocated or < 0 on error.
4447 *
4448 * We only need to fill in the address because the other members
4449 * of the RX descriptor are invariant, see tg3_init_rings.
4450 *
4451 * Note the purposeful assymetry of cpu vs. chip accesses. For
4452 * posting buffers we only dirty the first cache line of the RX
4453 * descriptor (containing the address). Whereas for the RX status
4454 * buffers the cpu only reads the last cacheline of the RX descriptor
4455 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4456 */
86b21e59 4457static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4458 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4459{
4460 struct tg3_rx_buffer_desc *desc;
4461 struct ring_info *map, *src_map;
4462 struct sk_buff *skb;
4463 dma_addr_t mapping;
4464 int skb_size, dest_idx;
4465
4466 src_map = NULL;
4467 switch (opaque_key) {
4468 case RXD_OPAQUE_RING_STD:
4469 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4470 desc = &tpr->rx_std[dest_idx];
4471 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4472 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4473 break;
4474
4475 case RXD_OPAQUE_RING_JUMBO:
4476 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4477 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4478 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4479 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4480 break;
4481
4482 default:
4483 return -EINVAL;
855e1111 4484 }
1da177e4
LT		 4485
4486 /* Do not overwrite any of the map or rp information
4487 * until we are sure we can commit to a new buffer.
4488 *
4489 * Callers depend upon this behavior and assume that
4490 * we leave everything unchanged if we fail.
4491 */
287be12e 4492 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4493 if (skb == NULL)
4494 return -ENOMEM;
4495
1da177e4
LT		 4496 skb_reserve(skb, tp->rx_offset);
4497
287be12e 4498 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4499 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4500 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4501 dev_kfree_skb(skb);
4502 return -EIO;
4503 }
1da177e4
LT		 4504
4505 map->skb = skb;
4506 pci_unmap_addr_set(map, mapping, mapping);
4507
1da177e4
LT		 4508 desc->addr_hi = ((u64)mapping >> 32);
4509 desc->addr_lo = ((u64)mapping & 0xffffffff);
4510
4511 return skb_size;
4512}
4513
4514/* We only need to move over in the address because the other
4515 * members of the RX descriptor are invariant. See notes above
4516 * tg3_alloc_rx_skb for full details.
4517 */
a3896167
MC		 4518static void tg3_recycle_rx(struct tg3_napi *tnapi,
4519 struct tg3_rx_prodring_set *dpr,
4520 u32 opaque_key, int src_idx,
4521 u32 dest_idx_unmasked)
1da177e4 4522{
17375d25 4523 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4524 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4525 struct ring_info *src_map, *dest_map;
a3896167 4526 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
c6cdf436 4527 int dest_idx;
1da177e4
LT		 4528
4529 switch (opaque_key) {
4530 case RXD_OPAQUE_RING_STD:
4531 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4532 dest_desc = &dpr->rx_std[dest_idx];
4533 dest_map = &dpr->rx_std_buffers[dest_idx];
4534 src_desc = &spr->rx_std[src_idx];
4535 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4536 break;
4537
4538 case RXD_OPAQUE_RING_JUMBO:
4539 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4540 dest_desc = &dpr->rx_jmb[dest_idx].std;
4541 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4542 src_desc = &spr->rx_jmb[src_idx].std;
4543 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4544 break;
4545
4546 default:
4547 return;
855e1111 4548 }
1da177e4
LT		 4549
4550 dest_map->skb = src_map->skb;
4551 pci_unmap_addr_set(dest_map, mapping,
4552 pci_unmap_addr(src_map, mapping));
4553 dest_desc->addr_hi = src_desc->addr_hi;
4554 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 4555
4556 /* Ensure that the update to the skb happens after the physical
4557 * addresses have been transferred to the new BD location.
4558 */
4559 smp_wmb();
4560
1da177e4
LT		 4561 src_map->skb = NULL;
4562}
4563
1da177e4
LT		 4564/* The RX ring scheme is composed of multiple rings which post fresh
4565 * buffers to the chip, and one special ring the chip uses to report
4566 * status back to the host.
4567 *
4568 * The special ring reports the status of received packets to the
4569 * host. The chip does not write into the original descriptor the
4570 * RX buffer was obtained from. The chip simply takes the original
4571 * descriptor as provided by the host, updates the status and length
4572 * field, then writes this into the next status ring entry.
4573 *
4574 * Each ring the host uses to post buffers to the chip is described
4575 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4576 * it is first placed into the on-chip ram. When the packet's length
4577 * is known, it walks down the TG3_BDINFO entries to select the ring.
4578 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4579 * which is within the range of the new packet's length is chosen.
4580 *
4581 * The "separate ring for rx status" scheme may sound queer, but it makes
4582 * sense from a cache coherency perspective. If only the host writes
4583 * to the buffer post rings, and only the chip writes to the rx status
4584 * rings, then cache lines never move beyond shared-modified state.
4585 * If both the host and chip were to write into the same ring, cache line
4586 * eviction could occur since both entities want it in an exclusive state.
4587 */
17375d25 4588static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4589{
17375d25 4590 struct tg3 *tp = tnapi->tp;
f92905de 4591 u32 work_mask, rx_std_posted = 0;
4361935a 4592 u32 std_prod_idx, jmb_prod_idx;
72334482 4593 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4594 u16 hw_idx;
1da177e4 4595 int received;
b196c7e4 4596 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4597
8d9d7cfc 4598 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4599 /*
4600 * We need to order the read of hw_idx and the read of
4601 * the opaque cookie.
4602 */
4603 rmb();
1da177e4
LT		 4604 work_mask = 0;
4605 received = 0;
4361935a
MC		 4606 std_prod_idx = tpr->rx_std_prod_idx;
4607 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4608 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4609 struct ring_info *ri;
72334482 4610 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4611 unsigned int len;
4612 struct sk_buff *skb;
4613 dma_addr_t dma_addr;
4614 u32 opaque_key, desc_idx, *post_ptr;
4615
4616 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4617 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4618 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4619 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4620 dma_addr = pci_unmap_addr(ri, mapping);
4621 skb = ri->skb;
4361935a 4622 post_ptr = &std_prod_idx;
f92905de 4623 rx_std_posted++;
1da177e4 4624 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4625 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4626 dma_addr = pci_unmap_addr(ri, mapping);
4627 skb = ri->skb;
4361935a 4628 post_ptr = &jmb_prod_idx;
21f581a5 4629 } else
1da177e4 4630 goto next_pkt_nopost;
1da177e4
LT		 4631
4632 work_mask |= opaque_key;
4633
4634 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4635 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4636 drop_it:
a3896167 4637 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4638 desc_idx, *post_ptr);
4639 drop_it_no_recycle:
4640 /* Other statistics kept track of by card. */
4641 tp->net_stats.rx_dropped++;
4642 goto next_pkt;
4643 }
4644
ad829268
MC		 4645 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4646 ETH_FCS_LEN;
1da177e4 4647
8e95a202
JP		 4648 if (len > RX_COPY_THRESHOLD &&
4649 tp->rx_offset == NET_IP_ALIGN) {
4650 /* rx_offset will likely not equal NET_IP_ALIGN
4651 * if this is a 5701 card running in PCI-X mode
4652 * [see tg3_get_invariants()]
4653 */
1da177e4
LT		 4654 int skb_size;
4655
86b21e59 4656 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4657 *post_ptr);
1da177e4
LT		 4658 if (skb_size < 0)
4659 goto drop_it;
4660
287be12e 4661 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4662 PCI_DMA_FROMDEVICE);
4663
61e800cf
MC		 4664 /* Ensure that the update to the skb happens
4665 * after the usage of the old DMA mapping.
4666 */
4667 smp_wmb();
4668
4669 ri->skb = NULL;
4670
1da177e4
LT		 4671 skb_put(skb, len);
4672 } else {
4673 struct sk_buff *copy_skb;
4674
a3896167 4675 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4676 desc_idx, *post_ptr);
4677
ad829268
MC		 4678 copy_skb = netdev_alloc_skb(tp->dev,
4679 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4680 if (copy_skb == NULL)
4681 goto drop_it_no_recycle;
4682
ad829268 4683 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4684 skb_put(copy_skb, len);
4685 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4686 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4687 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4688
4689 /* We'll reuse the original ring buffer. */
4690 skb = copy_skb;
4691 }
4692
4693 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4694 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4695 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4696 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4697 skb->ip_summed = CHECKSUM_UNNECESSARY;
4698 else
4699 skb->ip_summed = CHECKSUM_NONE;
4700
4701 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4702
4703 if (len > (tp->dev->mtu + ETH_HLEN) &&
4704 skb->protocol != htons(ETH_P_8021Q)) {
4705 dev_kfree_skb(skb);
4706 goto next_pkt;
4707 }
4708
1da177e4
LT		 4709#if TG3_VLAN_TAG_USED
4710 if (tp->vlgrp != NULL &&
4711 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4712 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4713 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4714 } else
4715#endif
17375d25 4716 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4717
1da177e4
LT		 4718 received++;
4719 budget--;
4720
4721next_pkt:
4722 (*post_ptr)++;
f92905de
MC		 4723
4724 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
86cfe4ff
MC		 4725 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4726 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4727 tpr->rx_std_prod_idx);
f92905de
MC		 4728 work_mask &= ~RXD_OPAQUE_RING_STD;
4729 rx_std_posted = 0;
4730 }
1da177e4 4731next_pkt_nopost:
483ba50b 4732 sw_idx++;
6b31a515 4733 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4734
4735 /* Refresh hw_idx to see if there is new work */
4736 if (sw_idx == hw_idx) {
8d9d7cfc 4737 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4738 rmb();
4739 }
1da177e4
LT		 4740 }
4741
4742 /* ACK the status ring. */
72334482
MC		 4743 tnapi->rx_rcb_ptr = sw_idx;
4744 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4745
4746 /* Refill RX ring(s). */
e4af1af9 4747 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
b196c7e4
MC		 4748 if (work_mask & RXD_OPAQUE_RING_STD) {
4749 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4750 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4751 tpr->rx_std_prod_idx);
4752 }
4753 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4754 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4755 TG3_RX_JUMBO_RING_SIZE;
4756 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4757 tpr->rx_jmb_prod_idx);
4758 }
4759 mmiowb();
4760 } else if (work_mask) {
4761 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4762 * updated before the producer indices can be updated.
4763 */
4764 smp_wmb();
4765
4361935a 4766 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4767 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4 4768
e4af1af9
MC		 4769 if (tnapi != &tp->napi[1])
4770 napi_schedule(&tp->napi[1].napi);
1da177e4 4771 }
1da177e4
LT		 4772
4773 return received;
4774}
4775
35f2d7d0 4776static void tg3_poll_link(struct tg3 *tp)
1da177e4 4777{
1da177e4
LT		 4778 /* handle link change and other phy events */
4779 if (!(tp->tg3_flags &
4780 (TG3_FLAG_USE_LINKCHG_REG |
4781 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4782 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4783
1da177e4
LT		 4784 if (sblk->status & SD_STATUS_LINK_CHG) {
4785 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4786 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4787 spin_lock(&tp->lock);
dd477003
MC		 4788 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4789 tw32_f(MAC_STATUS,
4790 (MAC_STATUS_SYNC_CHANGED |
4791 MAC_STATUS_CFG_CHANGED |
4792 MAC_STATUS_MI_COMPLETION |
4793 MAC_STATUS_LNKSTATE_CHANGED));
4794 udelay(40);
4795 } else
4796 tg3_setup_phy(tp, 0);
f47c11ee 4797 spin_unlock(&tp->lock);
1da177e4
LT		 4798 }
4799 }
35f2d7d0
MC		 4800}
4801
f89f38b8
MC		 4802static int tg3_rx_prodring_xfer(struct tg3 *tp,
4803 struct tg3_rx_prodring_set *dpr,
4804 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 4805{
4806 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 4807 int i, err = 0;
b196c7e4
MC		 4808
4809 while (1) {
4810 src_prod_idx = spr->rx_std_prod_idx;
4811
4812 /* Make sure updates to the rx_std_buffers[] entries and the
4813 * standard producer index are seen in the correct order.
4814 */
4815 smp_rmb();
4816
4817 if (spr->rx_std_cons_idx == src_prod_idx)
4818 break;
4819
4820 if (spr->rx_std_cons_idx < src_prod_idx)
4821 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4822 else
4823 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4824
4825 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4826
4827 si = spr->rx_std_cons_idx;
4828 di = dpr->rx_std_prod_idx;
4829
e92967bf
MC		 4830 for (i = di; i < di + cpycnt; i++) {
4831 if (dpr->rx_std_buffers[i].skb) {
4832 cpycnt = i - di;
f89f38b8 4833 err = -ENOSPC;
e92967bf
MC		 4834 break;
4835 }
4836 }
4837
4838 if (!cpycnt)
4839 break;
4840
4841 /* Ensure that updates to the rx_std_buffers ring and the
4842 * shadowed hardware producer ring from tg3_recycle_skb() are
4843 * ordered correctly WRT the skb check above.
4844 */
4845 smp_rmb();
4846
b196c7e4
MC		 4847 memcpy(&dpr->rx_std_buffers[di],
4848 &spr->rx_std_buffers[si],
4849 cpycnt * sizeof(struct ring_info));
4850
4851 for (i = 0; i < cpycnt; i++, di++, si++) {
4852 struct tg3_rx_buffer_desc *sbd, *dbd;
4853 sbd = &spr->rx_std[si];
4854 dbd = &dpr->rx_std[di];
4855 dbd->addr_hi = sbd->addr_hi;
4856 dbd->addr_lo = sbd->addr_lo;
4857 }
4858
4859 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4860 TG3_RX_RING_SIZE;
4861 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4862 TG3_RX_RING_SIZE;
4863 }
4864
4865 while (1) {
4866 src_prod_idx = spr->rx_jmb_prod_idx;
4867
4868 /* Make sure updates to the rx_jmb_buffers[] entries and
4869 * the jumbo producer index are seen in the correct order.
4870 */
4871 smp_rmb();
4872
4873 if (spr->rx_jmb_cons_idx == src_prod_idx)
4874 break;
4875
4876 if (spr->rx_jmb_cons_idx < src_prod_idx)
4877 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4878 else
4879 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4880
4881 cpycnt = min(cpycnt,
4882 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4883
4884 si = spr->rx_jmb_cons_idx;
4885 di = dpr->rx_jmb_prod_idx;
4886
e92967bf
MC		 4887 for (i = di; i < di + cpycnt; i++) {
4888 if (dpr->rx_jmb_buffers[i].skb) {
4889 cpycnt = i - di;
f89f38b8 4890 err = -ENOSPC;
e92967bf
MC		 4891 break;
4892 }
4893 }
4894
4895 if (!cpycnt)
4896 break;
4897
4898 /* Ensure that updates to the rx_jmb_buffers ring and the
4899 * shadowed hardware producer ring from tg3_recycle_skb() are
4900 * ordered correctly WRT the skb check above.
4901 */
4902 smp_rmb();
4903
b196c7e4
MC		 4904 memcpy(&dpr->rx_jmb_buffers[di],
4905 &spr->rx_jmb_buffers[si],
4906 cpycnt * sizeof(struct ring_info));
4907
4908 for (i = 0; i < cpycnt; i++, di++, si++) {
4909 struct tg3_rx_buffer_desc *sbd, *dbd;
4910 sbd = &spr->rx_jmb[si].std;
4911 dbd = &dpr->rx_jmb[di].std;
4912 dbd->addr_hi = sbd->addr_hi;
4913 dbd->addr_lo = sbd->addr_lo;
4914 }
4915
4916 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4917 TG3_RX_JUMBO_RING_SIZE;
4918 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4919 TG3_RX_JUMBO_RING_SIZE;
4920 }
f89f38b8
MC		 4921
4922 return err;
b196c7e4
MC		 4923}
4924
35f2d7d0
MC		 4925static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4926{
4927 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4928
4929 /* run TX completion thread */
f3f3f27e 4930 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4931 tg3_tx(tnapi);
6f535763 4932 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4933 return work_done;
1da177e4
LT		 4934 }
4935
1da177e4
LT		 4936 /* run RX thread, within the bounds set by NAPI.
4937 * All RX "locking" is done by ensuring outside
bea3348e 4938 * code synchronizes with tg3->napi.poll()
1da177e4 4939 */
8d9d7cfc 4940 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4941 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4942
b196c7e4 4943 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
e4af1af9 4944 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
f89f38b8 4945 int i, err = 0;
e4af1af9
MC		 4946 u32 std_prod_idx = dpr->rx_std_prod_idx;
4947 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 4948
e4af1af9 4949 for (i = 1; i < tp->irq_cnt; i++)
f89f38b8
MC		 4950 err |= tg3_rx_prodring_xfer(tp, dpr,
4951 tp->napi[i].prodring);
b196c7e4
MC		 4952
4953 wmb();
4954
e4af1af9
MC		 4955 if (std_prod_idx != dpr->rx_std_prod_idx)
4956 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4957 dpr->rx_std_prod_idx);
b196c7e4 4958
e4af1af9
MC		 4959 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4960 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4961 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 4962
4963 mmiowb();
f89f38b8
MC		 4964
4965 if (err)
4966 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 4967 }
4968
6f535763
DM		 4969 return work_done;
4970}
4971
35f2d7d0
MC		 4972static int tg3_poll_msix(struct napi_struct *napi, int budget)
4973{
4974 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4975 struct tg3 *tp = tnapi->tp;
4976 int work_done = 0;
4977 struct tg3_hw_status *sblk = tnapi->hw_status;
4978
4979 while (1) {
4980 work_done = tg3_poll_work(tnapi, work_done, budget);
4981
4982 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4983 goto tx_recovery;
4984
4985 if (unlikely(work_done >= budget))
4986 break;
4987
c6cdf436 4988 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 4989 * to tell the hw how much work has been processed,
4990 * so we must read it before checking for more work.
4991 */
4992 tnapi->last_tag = sblk->status_tag;
4993 tnapi->last_irq_tag = tnapi->last_tag;
4994 rmb();
4995
4996 /* check for RX/TX work to do */
6d40db7b
MC		 4997 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4998 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
35f2d7d0
MC		 4999 napi_complete(napi);
5000 /* Reenable interrupts. */
5001 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5002 mmiowb();
5003 break;
5004 }
5005 }
5006
5007 return work_done;
5008
5009tx_recovery:
5010 /* work_done is guaranteed to be less than budget. */
5011 napi_complete(napi);
5012 schedule_work(&tp->reset_task);
5013 return work_done;
5014}
5015
6f535763
DM		 5016static int tg3_poll(struct napi_struct *napi, int budget)
5017{
8ef0442f
MC		 5018 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5019 struct tg3 *tp = tnapi->tp;
6f535763 5020 int work_done = 0;
898a56f8 5021 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 5022
5023 while (1) {
35f2d7d0
MC		 5024 tg3_poll_link(tp);
5025
17375d25 5026 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 5027
5028 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5029 goto tx_recovery;
5030
5031 if (unlikely(work_done >= budget))
5032 break;
5033
4fd7ab59 5034 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 5035 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 5036 * to tell the hw how much work has been processed,
5037 * so we must read it before checking for more work.
5038 */
898a56f8
MC		 5039 tnapi->last_tag = sblk->status_tag;
5040 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 5041 rmb();
5042 } else
5043 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 5044
17375d25 5045 if (likely(!tg3_has_work(tnapi))) {
288379f0 5046 napi_complete(napi);
17375d25 5047 tg3_int_reenable(tnapi);
6f535763
DM		 5048 break;
5049 }
1da177e4
LT		 5050 }
5051
bea3348e 5052 return work_done;
6f535763
DM		 5053
5054tx_recovery:
4fd7ab59 5055 /* work_done is guaranteed to be less than budget. */
288379f0 5056 napi_complete(napi);
6f535763 5057 schedule_work(&tp->reset_task);
4fd7ab59 5058 return work_done;
1da177e4
LT		 5059}
5060
f47c11ee
DM		 5061static void tg3_irq_quiesce(struct tg3 *tp)
5062{
4f125f42
MC		 5063 int i;
5064
f47c11ee
DM		 5065 BUG_ON(tp->irq_sync);
5066
5067 tp->irq_sync = 1;
5068 smp_mb();
5069
4f125f42
MC		 5070 for (i = 0; i < tp->irq_cnt; i++)
5071 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5072}
5073
5074static inline int tg3_irq_sync(struct tg3 *tp)
5075{
5076 return tp->irq_sync;
5077}
5078
5079/* Fully shutdown all tg3 driver activity elsewhere in the system.
5080 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5081 * with as well. Most of the time, this is not necessary except when
5082 * shutting down the device.
5083 */
5084static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5085{
46966545 5086 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5087 if (irq_sync)
5088 tg3_irq_quiesce(tp);
f47c11ee
DM		 5089}
5090
5091static inline void tg3_full_unlock(struct tg3 *tp)
5092{
f47c11ee
DM		 5093 spin_unlock_bh(&tp->lock);
5094}
5095
fcfa0a32
MC		 5096/* One-shot MSI handler - Chip automatically disables interrupt
5097 * after sending MSI so driver doesn't have to do it.
5098 */
7d12e780 5099static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5100{
09943a18
MC		 5101 struct tg3_napi *tnapi = dev_id;
5102 struct tg3 *tp = tnapi->tp;
fcfa0a32 5103
898a56f8 5104 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5105 if (tnapi->rx_rcb)
5106 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5107
5108 if (likely(!tg3_irq_sync(tp)))
09943a18 5109 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5110
5111 return IRQ_HANDLED;
5112}
5113
88b06bc2
MC		 5114/* MSI ISR - No need to check for interrupt sharing and no need to
5115 * flush status block and interrupt mailbox. PCI ordering rules
5116 * guarantee that MSI will arrive after the status block.
5117 */
7d12e780 5118static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5119{
09943a18
MC		 5120 struct tg3_napi *tnapi = dev_id;
5121 struct tg3 *tp = tnapi->tp;
88b06bc2 5122
898a56f8 5123 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5124 if (tnapi->rx_rcb)
5125 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5126 /*
fac9b83e 5127 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5128 * chip-internal interrupt pending events.
fac9b83e 5129 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5130 * NIC to stop sending us irqs, engaging "in-intr-handler"
5131 * event coalescing.
5132 */
5133 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5134 if (likely(!tg3_irq_sync(tp)))
09943a18 5135 napi_schedule(&tnapi->napi);
61487480 5136
88b06bc2
MC		 5137 return IRQ_RETVAL(1);
5138}
5139
7d12e780 5140static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5141{
09943a18
MC		 5142 struct tg3_napi *tnapi = dev_id;
5143 struct tg3 *tp = tnapi->tp;
898a56f8 5144 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5145 unsigned int handled = 1;
5146
1da177e4
LT		 5147 /* In INTx mode, it is possible for the interrupt to arrive at
5148 * the CPU before the status block posted prior to the interrupt.
5149 * Reading the PCI State register will confirm whether the
5150 * interrupt is ours and will flush the status block.
5151 */
d18edcb2
MC		 5152 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5153 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5154 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5155 handled = 0;
f47c11ee 5156 goto out;
fac9b83e 5157 }
d18edcb2
MC		 5158 }
5159
5160 /*
5161 * Writing any value to intr-mbox-0 clears PCI INTA# and
5162 * chip-internal interrupt pending events.
5163 * Writing non-zero to intr-mbox-0 additional tells the
5164 * NIC to stop sending us irqs, engaging "in-intr-handler"
5165 * event coalescing.
c04cb347
MC		 5166 *
5167 * Flush the mailbox to de-assert the IRQ immediately to prevent
5168 * spurious interrupts. The flush impacts performance but
5169 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5170 */
c04cb347 5171 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5172 if (tg3_irq_sync(tp))
5173 goto out;
5174 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5175 if (likely(tg3_has_work(tnapi))) {
72334482 5176 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5177 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5178 } else {
5179 /* No work, shared interrupt perhaps? re-enable
5180 * interrupts, and flush that PCI write
5181 */
5182 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5183 0x00000000);
fac9b83e 5184 }
f47c11ee 5185out:
fac9b83e
DM		 5186 return IRQ_RETVAL(handled);
5187}
5188
7d12e780 5189static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5190{
09943a18
MC		 5191 struct tg3_napi *tnapi = dev_id;
5192 struct tg3 *tp = tnapi->tp;
898a56f8 5193 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5194 unsigned int handled = 1;
5195
fac9b83e
DM		 5196 /* In INTx mode, it is possible for the interrupt to arrive at
5197 * the CPU before the status block posted prior to the interrupt.
5198 * Reading the PCI State register will confirm whether the
5199 * interrupt is ours and will flush the status block.
5200 */
898a56f8 5201 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5202 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5203 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5204 handled = 0;
f47c11ee 5205 goto out;
1da177e4 5206 }
d18edcb2
MC		 5207 }
5208
5209 /*
5210 * writing any value to intr-mbox-0 clears PCI INTA# and
5211 * chip-internal interrupt pending events.
5212 * writing non-zero to intr-mbox-0 additional tells the
5213 * NIC to stop sending us irqs, engaging "in-intr-handler"
5214 * event coalescing.
c04cb347
MC		 5215 *
5216 * Flush the mailbox to de-assert the IRQ immediately to prevent
5217 * spurious interrupts. The flush impacts performance but
5218 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5219 */
c04cb347 5220 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5221
5222 /*
5223 * In a shared interrupt configuration, sometimes other devices'
5224 * interrupts will scream. We record the current status tag here
5225 * so that the above check can report that the screaming interrupts
5226 * are unhandled. Eventually they will be silenced.
5227 */
898a56f8 5228 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5229
d18edcb2
MC		 5230 if (tg3_irq_sync(tp))
5231 goto out;
624f8e50 5232
72334482 5233 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5234
09943a18 5235 napi_schedule(&tnapi->napi);
624f8e50 5236
f47c11ee 5237out:
1da177e4
LT		 5238 return IRQ_RETVAL(handled);
5239}
5240
7938109f 5241/* ISR for interrupt test */
7d12e780 5242static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5243{
09943a18
MC		 5244 struct tg3_napi *tnapi = dev_id;
5245 struct tg3 *tp = tnapi->tp;
898a56f8 5246 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5247
f9804ddb
MC		 5248 if ((sblk->status & SD_STATUS_UPDATED) ||
5249 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5250 tg3_disable_ints(tp);
7938109f
MC		 5251 return IRQ_RETVAL(1);
5252 }
5253 return IRQ_RETVAL(0);
5254}
5255
8e7a22e3 5256static int tg3_init_hw(struct tg3 *, int);
944d980e 5257static int tg3_halt(struct tg3 *, int, int);
1da177e4 5258
b9ec6c1b
MC		 5259/* Restart hardware after configuration changes, self-test, etc.
5260 * Invoked with tp->lock held.
5261 */
5262static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5263 __releases(tp->lock)
5264 __acquires(tp->lock)
b9ec6c1b
MC		 5265{
5266 int err;
5267
5268 err = tg3_init_hw(tp, reset_phy);
5269 if (err) {
5129c3a3
MC		 5270 netdev_err(tp->dev,
5271 "Failed to re-initialize device, aborting\n");
b9ec6c1b
MC		 5272 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5273 tg3_full_unlock(tp);
5274 del_timer_sync(&tp->timer);
5275 tp->irq_sync = 0;
fed97810 5276 tg3_napi_enable(tp);
b9ec6c1b
MC		 5277 dev_close(tp->dev);
5278 tg3_full_lock(tp, 0);
5279 }
5280 return err;
5281}
5282
1da177e4
LT		 5283#ifdef CONFIG_NET_POLL_CONTROLLER
5284static void tg3_poll_controller(struct net_device *dev)
5285{
4f125f42 5286 int i;
88b06bc2
MC		 5287 struct tg3 *tp = netdev_priv(dev);
5288
4f125f42 5289 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 5290 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 5291}
5292#endif
5293
c4028958 5294static void tg3_reset_task(struct work_struct *work)
1da177e4 5295{
c4028958 5296 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5297 int err;
1da177e4
LT		 5298 unsigned int restart_timer;
5299
7faa006f 5300 tg3_full_lock(tp, 0);
7faa006f
MC		 5301
5302 if (!netif_running(tp->dev)) {
7faa006f
MC		 5303 tg3_full_unlock(tp);
5304 return;
5305 }
5306
5307 tg3_full_unlock(tp);
5308
b02fd9e3
MC		 5309 tg3_phy_stop(tp);
5310
1da177e4
LT		 5311 tg3_netif_stop(tp);
5312
f47c11ee 5313 tg3_full_lock(tp, 1);
1da177e4
LT		 5314
5315 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5316 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5317
df3e6548
MC		 5318 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5319 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5320 tp->write32_rx_mbox = tg3_write_flush_reg32;
5321 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5322 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5323 }
5324
944d980e 5325 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5326 err = tg3_init_hw(tp, 1);
5327 if (err)
b9ec6c1b 5328 goto out;
1da177e4
LT		 5329
5330 tg3_netif_start(tp);
5331
1da177e4
LT		 5332 if (restart_timer)
5333 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5334
b9ec6c1b 5335out:
7faa006f 5336 tg3_full_unlock(tp);
b02fd9e3
MC		 5337
5338 if (!err)
5339 tg3_phy_start(tp);
1da177e4
LT		 5340}
5341
b0408751
MC		 5342static void tg3_dump_short_state(struct tg3 *tp)
5343{
05dbe005
JP		 5344 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5345 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5346 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5347 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
b0408751
MC		 5348}
5349
1da177e4
LT		 5350static void tg3_tx_timeout(struct net_device *dev)
5351{
5352 struct tg3 *tp = netdev_priv(dev);
5353
b0408751 5354 if (netif_msg_tx_err(tp)) {
05dbe005 5355 netdev_err(dev, "transmit timed out, resetting\n");
b0408751
MC		 5356 tg3_dump_short_state(tp);
5357 }
1da177e4
LT		 5358
5359 schedule_work(&tp->reset_task);
5360}
5361
c58ec932
MC		 5362/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5363static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5364{
5365 u32 base = (u32) mapping & 0xffffffff;
5366
5367 return ((base > 0xffffdcc0) &&
5368 (base + len + 8 < base));
5369}
5370
72f2afb8
MC		 5371/* Test for DMA addresses > 40-bit */
5372static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5373 int len)
5374{
5375#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5376 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5377 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5378 return 0;
5379#else
5380 return 0;
5381#endif
5382}
5383
f3f3f27e 5384static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5385
72f2afb8 5386/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5387static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5388 struct sk_buff *skb, u32 last_plus_one,
5389 u32 *start, u32 base_flags, u32 mss)
1da177e4 5390{
24f4efd4 5391 struct tg3 *tp = tnapi->tp;
41588ba1 5392 struct sk_buff *new_skb;
c58ec932 5393 dma_addr_t new_addr = 0;
1da177e4 5394 u32 entry = *start;
c58ec932 5395 int i, ret = 0;
1da177e4 5396
41588ba1
MC		 5397 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5398 new_skb = skb_copy(skb, GFP_ATOMIC);
5399 else {
5400 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5401
5402 new_skb = skb_copy_expand(skb,
5403 skb_headroom(skb) + more_headroom,
5404 skb_tailroom(skb), GFP_ATOMIC);
5405 }
5406
1da177e4 5407 if (!new_skb) {
c58ec932
MC		 5408 ret = -1;
5409 } else {
5410 /* New SKB is guaranteed to be linear. */
5411 entry = *start;
f4188d8a
AD		 5412 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5413 PCI_DMA_TODEVICE);
5414 /* Make sure the mapping succeeded */
5415 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5416 ret = -1;
5417 dev_kfree_skb(new_skb);
5418 new_skb = NULL;
90079ce8 5419
c58ec932
MC		 5420 /* Make sure new skb does not cross any 4G boundaries.
5421 * Drop the packet if it does.
5422 */
f4188d8a
AD		 5423 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5424 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5425 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5426 PCI_DMA_TODEVICE);
c58ec932
MC		 5427 ret = -1;
5428 dev_kfree_skb(new_skb);
5429 new_skb = NULL;
5430 } else {
f3f3f27e 5431 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5432 base_flags, 1 | (mss << 1));
5433 *start = NEXT_TX(entry);
5434 }
1da177e4
LT		 5435 }
5436
1da177e4
LT		 5437 /* Now clean up the sw ring entries. */
5438 i = 0;
5439 while (entry != last_plus_one) {
f4188d8a
AD		 5440 int len;
5441
f3f3f27e 5442 if (i == 0)
f4188d8a 5443 len = skb_headlen(skb);
f3f3f27e 5444 else
f4188d8a
AD		 5445 len = skb_shinfo(skb)->frags[i-1].size;
5446
5447 pci_unmap_single(tp->pdev,
5448 pci_unmap_addr(&tnapi->tx_buffers[entry],
5449 mapping),
5450 len, PCI_DMA_TODEVICE);
5451 if (i == 0) {
5452 tnapi->tx_buffers[entry].skb = new_skb;
5453 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5454 new_addr);
5455 } else {
f3f3f27e 5456 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5457 }
1da177e4
LT		 5458 entry = NEXT_TX(entry);
5459 i++;
5460 }
5461
5462 dev_kfree_skb(skb);
5463
c58ec932 5464 return ret;
1da177e4
LT		 5465}
5466
f3f3f27e 5467static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5468 dma_addr_t mapping, int len, u32 flags,
5469 u32 mss_and_is_end)
5470{
f3f3f27e 5471 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5472 int is_end = (mss_and_is_end & 0x1);
5473 u32 mss = (mss_and_is_end >> 1);
5474 u32 vlan_tag = 0;
5475
5476 if (is_end)
5477 flags |= TXD_FLAG_END;
5478 if (flags & TXD_FLAG_VLAN) {
5479 vlan_tag = flags >> 16;
5480 flags &= 0xffff;
5481 }
5482 vlan_tag |= (mss << TXD_MSS_SHIFT);
5483
5484 txd->addr_hi = ((u64) mapping >> 32);
5485 txd->addr_lo = ((u64) mapping & 0xffffffff);
5486 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5487 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5488}
5489
5a6f3074 5490/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5491 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5492 */
61357325
SH		 5493static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5494 struct net_device *dev)
5a6f3074
MC		 5495{
5496 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5497 u32 len, entry, base_flags, mss;
90079ce8 5498 dma_addr_t mapping;
fe5f5787
MC		 5499 struct tg3_napi *tnapi;
5500 struct netdev_queue *txq;
f4188d8a
AD		 5501 unsigned int i, last;
5502
fe5f5787
MC		 5503 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5504 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5505 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5506 tnapi++;
5a6f3074 5507
00b70504 5508 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5509 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5510 * interrupt. Furthermore, IRQ processing runs lockless so we have
5511 * no IRQ context deadlocks to worry about either. Rejoice!
5512 */
f3f3f27e 5513 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5514 if (!netif_tx_queue_stopped(txq)) {
5515 netif_tx_stop_queue(txq);
5a6f3074
MC		 5516
5517 /* This is a hard error, log it. */
5129c3a3
MC		 5518 netdev_err(dev,
5519 "BUG! Tx Ring full when queue awake!\n");
5a6f3074 5520 }
5a6f3074
MC		 5521 return NETDEV_TX_BUSY;
5522 }
5523
f3f3f27e 5524 entry = tnapi->tx_prod;
5a6f3074 5525 base_flags = 0;
5a6f3074 5526 mss = 0;
c13e3713 5527 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5528 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5529 u32 hdrlen;
5a6f3074
MC		 5530
5531 if (skb_header_cloned(skb) &&
5532 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5533 dev_kfree_skb(skb);
5534 goto out_unlock;
5535 }
5536
b0026624 5537 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5538 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5539 else {
eddc9ec5
ACM		 5540 struct iphdr *iph = ip_hdr(skb);
5541
ab6a5bb6 5542 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5543 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5544
eddc9ec5
ACM		 5545 iph->check = 0;
5546 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5547 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5548 }
5a6f3074 5549
e849cdc3 5550 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5551 mss |= (hdrlen & 0xc) << 12;
5552 if (hdrlen & 0x10)
5553 base_flags |= 0x00000010;
5554 base_flags |= (hdrlen & 0x3e0) << 5;
5555 } else
5556 mss |= hdrlen << 9;
5557
5a6f3074
MC		 5558 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5559 TXD_FLAG_CPU_POST_DMA);
5560
aa8223c7 5561 tcp_hdr(skb)->check = 0;
5a6f3074 5562
5a6f3074 5563 }
84fa7933 5564 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5565 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5566#if TG3_VLAN_TAG_USED
5567 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5568 base_flags |= (TXD_FLAG_VLAN |
5569 (vlan_tx_tag_get(skb) << 16));
5570#endif
5571
f4188d8a
AD		 5572 len = skb_headlen(skb);
5573
5574 /* Queue skb data, a.k.a. the main skb fragment. */
5575 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5576 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5577 dev_kfree_skb(skb);
5578 goto out_unlock;
5579 }
5580
f3f3f27e 5581 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5582 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5583
b703df6f 5584 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5585 !mss && skb->len > ETH_DATA_LEN)
5586 base_flags |= TXD_FLAG_JMB_PKT;
5587
f3f3f27e 5588 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5589 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5590
5591 entry = NEXT_TX(entry);
5592
5593 /* Now loop through additional data fragments, and queue them. */
5594 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5595 last = skb_shinfo(skb)->nr_frags - 1;
5596 for (i = 0; i <= last; i++) {
5597 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5598
5599 len = frag->size;
f4188d8a
AD		 5600 mapping = pci_map_page(tp->pdev,
5601 frag->page,
5602 frag->page_offset,
5603 len, PCI_DMA_TODEVICE);
5604 if (pci_dma_mapping_error(tp->pdev, mapping))
5605 goto dma_error;
5606
f3f3f27e 5607 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5608 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5609 mapping);
5a6f3074 5610
f3f3f27e 5611 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5612 base_flags, (i == last) | (mss << 1));
5613
5614 entry = NEXT_TX(entry);
5615 }
5616 }
5617
5618 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5619 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5620
f3f3f27e
MC		 5621 tnapi->tx_prod = entry;
5622 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5623 netif_tx_stop_queue(txq);
f3f3f27e 5624 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5625 netif_tx_wake_queue(txq);
5a6f3074
MC		 5626 }
5627
5628out_unlock:
cdd0db05 5629 mmiowb();
5a6f3074
MC		 5630
5631 return NETDEV_TX_OK;
f4188d8a
AD		 5632
5633dma_error:
5634 last = i;
5635 entry = tnapi->tx_prod;
5636 tnapi->tx_buffers[entry].skb = NULL;
5637 pci_unmap_single(tp->pdev,
5638 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5639 skb_headlen(skb),
5640 PCI_DMA_TODEVICE);
5641 for (i = 0; i <= last; i++) {
5642 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5643 entry = NEXT_TX(entry);
5644
5645 pci_unmap_page(tp->pdev,
5646 pci_unmap_addr(&tnapi->tx_buffers[entry],
5647 mapping),
5648 frag->size, PCI_DMA_TODEVICE);
5649 }
5650
5651 dev_kfree_skb(skb);
5652 return NETDEV_TX_OK;
5a6f3074
MC		 5653}
5654
61357325
SH		 5655static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5656 struct net_device *);
52c0fd83
MC		 5657
5658/* Use GSO to workaround a rare TSO bug that may be triggered when the
5659 * TSO header is greater than 80 bytes.
5660 */
5661static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5662{
5663 struct sk_buff *segs, *nskb;
f3f3f27e 5664 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5665
5666 /* Estimate the number of fragments in the worst case */
f3f3f27e 5667 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5668 netif_stop_queue(tp->dev);
f3f3f27e 5669 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5670 return NETDEV_TX_BUSY;
5671
5672 netif_wake_queue(tp->dev);
52c0fd83
MC		 5673 }
5674
5675 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5676 if (IS_ERR(segs))
52c0fd83
MC		 5677 goto tg3_tso_bug_end;
5678
5679 do {
5680 nskb = segs;
5681 segs = segs->next;
5682 nskb->next = NULL;
5683 tg3_start_xmit_dma_bug(nskb, tp->dev);
5684 } while (segs);
5685
5686tg3_tso_bug_end:
5687 dev_kfree_skb(skb);
5688
5689 return NETDEV_TX_OK;
5690}
52c0fd83 5691
5a6f3074
MC		 5692/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5693 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5694 */
61357325
SH		 5695static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5696 struct net_device *dev)
1da177e4
LT		 5697{
5698 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5699 u32 len, entry, base_flags, mss;
5700 int would_hit_hwbug;
90079ce8 5701 dma_addr_t mapping;
24f4efd4
MC		 5702 struct tg3_napi *tnapi;
5703 struct netdev_queue *txq;
f4188d8a
AD		 5704 unsigned int i, last;
5705
24f4efd4
MC		 5706 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5707 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5708 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5709 tnapi++;
1da177e4 5710
00b70504 5711 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5712 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5713 * interrupt. Furthermore, IRQ processing runs lockless so we have
5714 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5715 */
f3f3f27e 5716 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5717 if (!netif_tx_queue_stopped(txq)) {
5718 netif_tx_stop_queue(txq);
1f064a87
SH		 5719
5720 /* This is a hard error, log it. */
5129c3a3
MC		 5721 netdev_err(dev,
5722 "BUG! Tx Ring full when queue awake!\n");
1f064a87 5723 }
1da177e4
LT		 5724 return NETDEV_TX_BUSY;
5725 }
5726
f3f3f27e 5727 entry = tnapi->tx_prod;
1da177e4 5728 base_flags = 0;
84fa7933 5729 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5730 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5731
c13e3713 5732 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5733 struct iphdr *iph;
92c6b8d1 5734 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5735
5736 if (skb_header_cloned(skb) &&
5737 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5738 dev_kfree_skb(skb);
5739 goto out_unlock;
5740 }
5741
ab6a5bb6 5742 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5743 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5744
52c0fd83
MC		 5745 hdr_len = ip_tcp_len + tcp_opt_len;
5746 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5747 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5748 return (tg3_tso_bug(tp, skb));
5749
1da177e4
LT		 5750 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5751 TXD_FLAG_CPU_POST_DMA);
5752
eddc9ec5
ACM		 5753 iph = ip_hdr(skb);
5754 iph->check = 0;
5755 iph->tot_len = htons(mss + hdr_len);
1da177e4 5756 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5757 tcp_hdr(skb)->check = 0;
1da177e4 5758 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5759 } else
5760 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5761 iph->daddr, 0,
5762 IPPROTO_TCP,
5763 0);
1da177e4 5764
615774fe
MC		 5765 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5766 mss |= (hdr_len & 0xc) << 12;
5767 if (hdr_len & 0x10)
5768 base_flags |= 0x00000010;
5769 base_flags |= (hdr_len & 0x3e0) << 5;
5770 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5771 mss |= hdr_len << 9;
5772 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5773 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5774 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5775 int tsflags;
5776
eddc9ec5 5777 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5778 mss |= (tsflags << 11);
5779 }
5780 } else {
eddc9ec5 5781 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5782 int tsflags;
5783
eddc9ec5 5784 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5785 base_flags |= tsflags << 12;
5786 }
5787 }
5788 }
1da177e4
LT		 5789#if TG3_VLAN_TAG_USED
5790 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5791 base_flags |= (TXD_FLAG_VLAN |
5792 (vlan_tx_tag_get(skb) << 16));
5793#endif
5794
b703df6f 5795 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5796 !mss && skb->len > ETH_DATA_LEN)
5797 base_flags |= TXD_FLAG_JMB_PKT;
5798
f4188d8a
AD		 5799 len = skb_headlen(skb);
5800
5801 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5802 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5803 dev_kfree_skb(skb);
5804 goto out_unlock;
5805 }
5806
f3f3f27e 5807 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5808 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5809
5810 would_hit_hwbug = 0;
5811
92c6b8d1
MC		 5812 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5813 would_hit_hwbug = 1;
5814
0e1406dd
MC		 5815 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5816 tg3_4g_overflow_test(mapping, len))
5817 would_hit_hwbug = 1;
5818
5819 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5820 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5821 would_hit_hwbug = 1;
0e1406dd
MC		 5822
5823 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5824 would_hit_hwbug = 1;
1da177e4 5825
f3f3f27e 5826 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5827 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5828
5829 entry = NEXT_TX(entry);
5830
5831 /* Now loop through additional data fragments, and queue them. */
5832 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5833 last = skb_shinfo(skb)->nr_frags - 1;
5834 for (i = 0; i <= last; i++) {
5835 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5836
5837 len = frag->size;
f4188d8a
AD		 5838 mapping = pci_map_page(tp->pdev,
5839 frag->page,
5840 frag->page_offset,
5841 len, PCI_DMA_TODEVICE);
1da177e4 5842
f3f3f27e 5843 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5844 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5845 mapping);
5846 if (pci_dma_mapping_error(tp->pdev, mapping))
5847 goto dma_error;
1da177e4 5848
92c6b8d1
MC		 5849 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5850 len <= 8)
5851 would_hit_hwbug = 1;
5852
0e1406dd
MC		 5853 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5854 tg3_4g_overflow_test(mapping, len))
c58ec932 5855 would_hit_hwbug = 1;
1da177e4 5856
0e1406dd
MC		 5857 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5858 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5859 would_hit_hwbug = 1;
5860
1da177e4 5861 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5862 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5863 base_flags, (i == last)|(mss << 1));
5864 else
f3f3f27e 5865 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5866 base_flags, (i == last));
5867
5868 entry = NEXT_TX(entry);
5869 }
5870 }
5871
5872 if (would_hit_hwbug) {
5873 u32 last_plus_one = entry;
5874 u32 start;
1da177e4 5875
c58ec932
MC		 5876 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5877 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5878
5879 /* If the workaround fails due to memory/mapping
5880 * failure, silently drop this packet.
5881 */
24f4efd4 5882 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5883 &start, base_flags, mss))
1da177e4
LT		 5884 goto out_unlock;
5885
5886 entry = start;
5887 }
5888
5889 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5890 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5891
f3f3f27e
MC		 5892 tnapi->tx_prod = entry;
5893 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5894 netif_tx_stop_queue(txq);
f3f3f27e 5895 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5896 netif_tx_wake_queue(txq);
51b91468 5897 }
1da177e4
LT		 5898
5899out_unlock:
cdd0db05 5900 mmiowb();
1da177e4
LT		 5901
5902 return NETDEV_TX_OK;
f4188d8a
AD		 5903
5904dma_error:
5905 last = i;
5906 entry = tnapi->tx_prod;
5907 tnapi->tx_buffers[entry].skb = NULL;
5908 pci_unmap_single(tp->pdev,
5909 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5910 skb_headlen(skb),
5911 PCI_DMA_TODEVICE);
5912 for (i = 0; i <= last; i++) {
5913 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5914 entry = NEXT_TX(entry);
5915
5916 pci_unmap_page(tp->pdev,
5917 pci_unmap_addr(&tnapi->tx_buffers[entry],
5918 mapping),
5919 frag->size, PCI_DMA_TODEVICE);
5920 }
5921
5922 dev_kfree_skb(skb);
5923 return NETDEV_TX_OK;
1da177e4
LT		 5924}
5925
5926static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5927 int new_mtu)
5928{
5929 dev->mtu = new_mtu;
5930
ef7f5ec0 5931 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5932 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5933 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5934 ethtool_op_set_tso(dev, 0);
5935 }
5936 else
5937 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5938 } else {
a4e2b347 5939 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5940 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5941 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5942 }
1da177e4
LT		 5943}
5944
5945static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5946{
5947 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5948 int err;
1da177e4
LT		 5949
5950 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5951 return -EINVAL;
5952
5953 if (!netif_running(dev)) {
5954 /* We'll just catch it later when the
5955 * device is up'd.
5956 */
5957 tg3_set_mtu(dev, tp, new_mtu);
5958 return 0;
5959 }
5960
b02fd9e3
MC		 5961 tg3_phy_stop(tp);
5962
1da177e4 5963 tg3_netif_stop(tp);
f47c11ee
DM		 5964
5965 tg3_full_lock(tp, 1);
1da177e4 5966
944d980e 5967 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5968
5969 tg3_set_mtu(dev, tp, new_mtu);
5970
b9ec6c1b 5971 err = tg3_restart_hw(tp, 0);
1da177e4 5972
b9ec6c1b
MC		 5973 if (!err)
5974 tg3_netif_start(tp);
1da177e4 5975
f47c11ee 5976 tg3_full_unlock(tp);
1da177e4 5977
b02fd9e3
MC		 5978 if (!err)
5979 tg3_phy_start(tp);
5980
b9ec6c1b 5981 return err;
1da177e4
LT		 5982}
5983
21f581a5
MC		 5984static void tg3_rx_prodring_free(struct tg3 *tp,
5985 struct tg3_rx_prodring_set *tpr)
1da177e4 5986{
1da177e4
LT		 5987 int i;
5988
b196c7e4
MC		 5989 if (tpr != &tp->prodring[0]) {
5990 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5991 i = (i + 1) % TG3_RX_RING_SIZE)
5992 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5993 tp->rx_pkt_map_sz);
5994
5995 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5996 for (i = tpr->rx_jmb_cons_idx;
5997 i != tpr->rx_jmb_prod_idx;
5998 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5999 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6000 TG3_RX_JMB_MAP_SZ);
6001 }
6002 }
6003
2b2cdb65 6004 return;
b196c7e4 6005 }
1da177e4 6006
2b2cdb65
MC		 6007 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6008 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6009 tp->rx_pkt_map_sz);
1da177e4 6010
cf7a7298 6011 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 6012 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6013 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6014 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 6015 }
6016}
6017
c6cdf436 6018/* Initialize rx rings for packet processing.
1da177e4
LT		 6019 *
6020 * The chip has been shut down and the driver detached from
6021 * the networking, so no interrupts or new tx packets will
6022 * end up in the driver. tp->{tx,}lock are held and thus
6023 * we may not sleep.
6024 */
21f581a5
MC		 6025static int tg3_rx_prodring_alloc(struct tg3 *tp,
6026 struct tg3_rx_prodring_set *tpr)
1da177e4 6027{
287be12e 6028 u32 i, rx_pkt_dma_sz;
1da177e4 6029
b196c7e4
MC		 6030 tpr->rx_std_cons_idx = 0;
6031 tpr->rx_std_prod_idx = 0;
6032 tpr->rx_jmb_cons_idx = 0;
6033 tpr->rx_jmb_prod_idx = 0;
6034
2b2cdb65
MC		 6035 if (tpr != &tp->prodring[0]) {
6036 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6037 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6038 memset(&tpr->rx_jmb_buffers[0], 0,
6039 TG3_RX_JMB_BUFF_RING_SIZE);
6040 goto done;
6041 }
6042
1da177e4 6043 /* Zero out all descriptors. */
21f581a5 6044 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 6045
287be12e 6046 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 6047 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 6048 tp->dev->mtu > ETH_DATA_LEN)
6049 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6050 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 6051
1da177e4
LT		 6052 /* Initialize invariants of the rings, we only set this
6053 * stuff once. This works because the card does not
6054 * write into the rx buffer posting rings.
6055 */
6056 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6057 struct tg3_rx_buffer_desc *rxd;
6058
21f581a5 6059 rxd = &tpr->rx_std[i];
287be12e 6060 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6061 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6062 rxd->opaque = (RXD_OPAQUE_RING_STD |
6063 (i << RXD_OPAQUE_INDEX_SHIFT));
6064 }
6065
1da177e4
LT		 6066 /* Now allocate fresh SKBs for each rx ring. */
6067 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6068 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
5129c3a3
MC		 6069 netdev_warn(tp->dev,
6070 "Using a smaller RX standard ring. Only "
6071 "%d out of %d buffers were allocated "
6072 "successfully\n", i, tp->rx_pending);
32d8c572 6073 if (i == 0)
cf7a7298 6074 goto initfail;
32d8c572 6075 tp->rx_pending = i;
1da177e4 6076 break;
32d8c572 6077 }
1da177e4
LT		 6078 }
6079
cf7a7298
MC		 6080 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6081 goto done;
6082
21f581a5 6083 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6084
0d86df80
MC		 6085 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6086 goto done;
cf7a7298 6087
0d86df80
MC		 6088 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6089 struct tg3_rx_buffer_desc *rxd;
6090
6091 rxd = &tpr->rx_jmb[i].std;
6092 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6093 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6094 RXD_FLAG_JUMBO;
6095 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6096 (i << RXD_OPAQUE_INDEX_SHIFT));
6097 }
6098
6099 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6100 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
5129c3a3
MC		 6101 netdev_warn(tp->dev,
6102 "Using a smaller RX jumbo ring. Only %d "
6103 "out of %d buffers were allocated "
6104 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 6105 if (i == 0)
6106 goto initfail;
6107 tp->rx_jumbo_pending = i;
6108 break;
1da177e4
LT		 6109 }
6110 }
cf7a7298
MC		 6111
6112done:
32d8c572 6113 return 0;
cf7a7298
MC		 6114
6115initfail:
21f581a5 6116 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6117 return -ENOMEM;
1da177e4
LT		 6118}
6119
21f581a5
MC		 6120static void tg3_rx_prodring_fini(struct tg3 *tp,
6121 struct tg3_rx_prodring_set *tpr)
1da177e4 6122{
21f581a5
MC		 6123 kfree(tpr->rx_std_buffers);
6124 tpr->rx_std_buffers = NULL;
6125 kfree(tpr->rx_jmb_buffers);
6126 tpr->rx_jmb_buffers = NULL;
6127 if (tpr->rx_std) {
1da177e4 6128 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6129 tpr->rx_std, tpr->rx_std_mapping);
6130 tpr->rx_std = NULL;
1da177e4 6131 }
21f581a5 6132 if (tpr->rx_jmb) {
1da177e4 6133 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6134 tpr->rx_jmb, tpr->rx_jmb_mapping);
6135 tpr->rx_jmb = NULL;
1da177e4 6136 }
cf7a7298
MC		 6137}
6138
21f581a5
MC		 6139static int tg3_rx_prodring_init(struct tg3 *tp,
6140 struct tg3_rx_prodring_set *tpr)
cf7a7298 6141{
2b2cdb65 6142 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6143 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6144 return -ENOMEM;
6145
21f581a5
MC		 6146 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6147 &tpr->rx_std_mapping);
6148 if (!tpr->rx_std)
cf7a7298
MC		 6149 goto err_out;
6150
6151 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6152 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6153 GFP_KERNEL);
6154 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6155 goto err_out;
6156
21f581a5
MC		 6157 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6158 TG3_RX_JUMBO_RING_BYTES,
6159 &tpr->rx_jmb_mapping);
6160 if (!tpr->rx_jmb)
cf7a7298
MC		 6161 goto err_out;
6162 }
6163
6164 return 0;
6165
6166err_out:
21f581a5 6167 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6168 return -ENOMEM;
6169}
6170
6171/* Free up pending packets in all rx/tx rings.
6172 *
6173 * The chip has been shut down and the driver detached from
6174 * the networking, so no interrupts or new tx packets will
6175 * end up in the driver. tp->{tx,}lock is not held and we are not
6176 * in an interrupt context and thus may sleep.
6177 */
6178static void tg3_free_rings(struct tg3 *tp)
6179{
f77a6a8e 6180 int i, j;
cf7a7298 6181
f77a6a8e
MC		 6182 for (j = 0; j < tp->irq_cnt; j++) {
6183 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6184
0c1d0e2b
MC		 6185 if (!tnapi->tx_buffers)
6186 continue;
6187
f77a6a8e 6188 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6189 struct ring_info *txp;
f77a6a8e 6190 struct sk_buff *skb;
f4188d8a 6191 unsigned int k;
cf7a7298 6192
f77a6a8e
MC		 6193 txp = &tnapi->tx_buffers[i];
6194 skb = txp->skb;
cf7a7298 6195
f77a6a8e
MC		 6196 if (skb == NULL) {
6197 i++;
6198 continue;
6199 }
cf7a7298 6200
f4188d8a
AD		 6201 pci_unmap_single(tp->pdev,
6202 pci_unmap_addr(txp, mapping),
6203 skb_headlen(skb),
6204 PCI_DMA_TODEVICE);
f77a6a8e 6205 txp->skb = NULL;
cf7a7298 6206
f4188d8a
AD		 6207 i++;
6208
6209 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6210 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6211 pci_unmap_page(tp->pdev,
6212 pci_unmap_addr(txp, mapping),
6213 skb_shinfo(skb)->frags[k].size,
6214 PCI_DMA_TODEVICE);
6215 i++;
6216 }
f77a6a8e
MC		 6217
6218 dev_kfree_skb_any(skb);
6219 }
cf7a7298 6220
e4af1af9 6221 tg3_rx_prodring_free(tp, &tp->prodring[j]);
2b2cdb65 6222 }
cf7a7298
MC		 6223}
6224
6225/* Initialize tx/rx rings for packet processing.
6226 *
6227 * The chip has been shut down and the driver detached from
6228 * the networking, so no interrupts or new tx packets will
6229 * end up in the driver. tp->{tx,}lock are held and thus
6230 * we may not sleep.
6231 */
6232static int tg3_init_rings(struct tg3 *tp)
6233{
f77a6a8e 6234 int i;
72334482 6235
cf7a7298
MC		 6236 /* Free up all the SKBs. */
6237 tg3_free_rings(tp);
6238
f77a6a8e
MC		 6239 for (i = 0; i < tp->irq_cnt; i++) {
6240 struct tg3_napi *tnapi = &tp->napi[i];
6241
6242 tnapi->last_tag = 0;
6243 tnapi->last_irq_tag = 0;
6244 tnapi->hw_status->status = 0;
6245 tnapi->hw_status->status_tag = 0;
6246 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6247
f77a6a8e
MC		 6248 tnapi->tx_prod = 0;
6249 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6250 if (tnapi->tx_ring)
6251 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6252
6253 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6254 if (tnapi->rx_rcb)
6255 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 6256
e4af1af9
MC		 6257 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6258 tg3_free_rings(tp);
2b2cdb65 6259 return -ENOMEM;
e4af1af9 6260 }
f77a6a8e 6261 }
72334482 6262
2b2cdb65 6263 return 0;
cf7a7298
MC		 6264}
6265
6266/*
6267 * Must not be invoked with interrupt sources disabled and
6268 * the hardware shutdown down.
6269 */
6270static void tg3_free_consistent(struct tg3 *tp)
6271{
f77a6a8e 6272 int i;
898a56f8 6273
f77a6a8e
MC		 6274 for (i = 0; i < tp->irq_cnt; i++) {
6275 struct tg3_napi *tnapi = &tp->napi[i];
6276
6277 if (tnapi->tx_ring) {
6278 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6279 tnapi->tx_ring, tnapi->tx_desc_mapping);
6280 tnapi->tx_ring = NULL;
6281 }
6282
6283 kfree(tnapi->tx_buffers);
6284 tnapi->tx_buffers = NULL;
6285
6286 if (tnapi->rx_rcb) {
6287 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6288 tnapi->rx_rcb,
6289 tnapi->rx_rcb_mapping);
6290 tnapi->rx_rcb = NULL;
6291 }
6292
6293 if (tnapi->hw_status) {
6294 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6295 tnapi->hw_status,
6296 tnapi->status_mapping);
6297 tnapi->hw_status = NULL;
6298 }
1da177e4 6299 }
f77a6a8e 6300
1da177e4
LT		 6301 if (tp->hw_stats) {
6302 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6303 tp->hw_stats, tp->stats_mapping);
6304 tp->hw_stats = NULL;
6305 }
f77a6a8e 6306
e4af1af9 6307 for (i = 0; i < tp->irq_cnt; i++)
2b2cdb65 6308 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6309}
6310
6311/*
6312 * Must not be invoked with interrupt sources disabled and
6313 * the hardware shutdown down. Can sleep.
6314 */
6315static int tg3_alloc_consistent(struct tg3 *tp)
6316{
f77a6a8e 6317 int i;
898a56f8 6318
e4af1af9 6319 for (i = 0; i < tp->irq_cnt; i++) {
2b2cdb65
MC		 6320 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6321 goto err_out;
6322 }
1da177e4 6323
f77a6a8e
MC		 6324 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6325 sizeof(struct tg3_hw_stats),
6326 &tp->stats_mapping);
6327 if (!tp->hw_stats)
1da177e4
LT		 6328 goto err_out;
6329
f77a6a8e 6330 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6331
f77a6a8e
MC		 6332 for (i = 0; i < tp->irq_cnt; i++) {
6333 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6334 struct tg3_hw_status *sblk;
1da177e4 6335
f77a6a8e
MC		 6336 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6337 TG3_HW_STATUS_SIZE,
6338 &tnapi->status_mapping);
6339 if (!tnapi->hw_status)
6340 goto err_out;
898a56f8 6341
f77a6a8e 6342 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6343 sblk = tnapi->hw_status;
6344
19cfaecc
MC		 6345 /* If multivector TSS is enabled, vector 0 does not handle
6346 * tx interrupts. Don't allocate any resources for it.
6347 */
6348 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6349 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6350 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6351 TG3_TX_RING_SIZE,
6352 GFP_KERNEL);
6353 if (!tnapi->tx_buffers)
6354 goto err_out;
6355
6356 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6357 TG3_TX_RING_BYTES,
6358 &tnapi->tx_desc_mapping);
6359 if (!tnapi->tx_ring)
6360 goto err_out;
6361 }
6362
8d9d7cfc
MC		 6363 /*
6364 * When RSS is enabled, the status block format changes
6365 * slightly. The "rx_jumbo_consumer", "reserved",
6366 * and "rx_mini_consumer" members get mapped to the
6367 * other three rx return ring producer indexes.
6368 */
6369 switch (i) {
6370 default:
6371 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6372 break;
6373 case 2:
6374 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6375 break;
6376 case 3:
6377 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6378 break;
6379 case 4:
6380 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6381 break;
6382 }
72334482 6383
e4af1af9 6384 tnapi->prodring = &tp->prodring[i];
b196c7e4 6385
0c1d0e2b
MC		 6386 /*
6387 * If multivector RSS is enabled, vector 0 does not handle
6388 * rx or tx interrupts. Don't allocate any resources for it.
6389 */
6390 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6391 continue;
6392
f77a6a8e
MC		 6393 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6394 TG3_RX_RCB_RING_BYTES(tp),
6395 &tnapi->rx_rcb_mapping);
6396 if (!tnapi->rx_rcb)
6397 goto err_out;
72334482 6398
f77a6a8e 6399 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6400 }
1da177e4
LT		 6401
6402 return 0;
6403
6404err_out:
6405 tg3_free_consistent(tp);
6406 return -ENOMEM;
6407}
6408
6409#define MAX_WAIT_CNT 1000
6410
6411/* To stop a block, clear the enable bit and poll till it
6412 * clears. tp->lock is held.
6413 */
b3b7d6be 6414static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6415{
6416 unsigned int i;
6417 u32 val;
6418
6419 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6420 switch (ofs) {
6421 case RCVLSC_MODE:
6422 case DMAC_MODE:
6423 case MBFREE_MODE:
6424 case BUFMGR_MODE:
6425 case MEMARB_MODE:
6426 /* We can't enable/disable these bits of the
6427 * 5705/5750, just say success.
6428 */
6429 return 0;
6430
6431 default:
6432 break;
855e1111 6433 }
1da177e4
LT		 6434 }
6435
6436 val = tr32(ofs);
6437 val &= ~enable_bit;
6438 tw32_f(ofs, val);
6439
6440 for (i = 0; i < MAX_WAIT_CNT; i++) {
6441 udelay(100);
6442 val = tr32(ofs);
6443 if ((val & enable_bit) == 0)
6444 break;
6445 }
6446
b3b7d6be 6447 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 6448 dev_err(&tp->pdev->dev,
6449 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6450 ofs, enable_bit);
1da177e4
LT		 6451 return -ENODEV;
6452 }
6453
6454 return 0;
6455}
6456
6457/* tp->lock is held. */
b3b7d6be 6458static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6459{
6460 int i, err;
6461
6462 tg3_disable_ints(tp);
6463
6464 tp->rx_mode &= ~RX_MODE_ENABLE;
6465 tw32_f(MAC_RX_MODE, tp->rx_mode);
6466 udelay(10);
6467
b3b7d6be
DM		 6468 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6469 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6470 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6471 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6472 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6473 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6474
6475 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6476 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6477 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6478 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6479 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6480 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6481 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6482
6483 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6484 tw32_f(MAC_MODE, tp->mac_mode);
6485 udelay(40);
6486
6487 tp->tx_mode &= ~TX_MODE_ENABLE;
6488 tw32_f(MAC_TX_MODE, tp->tx_mode);
6489
6490 for (i = 0; i < MAX_WAIT_CNT; i++) {
6491 udelay(100);
6492 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6493 break;
6494 }
6495 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 6496 dev_err(&tp->pdev->dev,
6497 "%s timed out, TX_MODE_ENABLE will not clear "
6498 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 6499 err |= -ENODEV;
1da177e4
LT		 6500 }
6501
e6de8ad1 6502 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6503 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6504 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6505
6506 tw32(FTQ_RESET, 0xffffffff);
6507 tw32(FTQ_RESET, 0x00000000);
6508
b3b7d6be
DM		 6509 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6510 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6511
f77a6a8e
MC		 6512 for (i = 0; i < tp->irq_cnt; i++) {
6513 struct tg3_napi *tnapi = &tp->napi[i];
6514 if (tnapi->hw_status)
6515 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6516 }
1da177e4
LT		 6517 if (tp->hw_stats)
6518 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6519
1da177e4
LT		 6520 return err;
6521}
6522
0d3031d9
MC		 6523static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6524{
6525 int i;
6526 u32 apedata;
6527
6528 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6529 if (apedata != APE_SEG_SIG_MAGIC)
6530 return;
6531
6532 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6533 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6534 return;
6535
6536 /* Wait for up to 1 millisecond for APE to service previous event. */
6537 for (i = 0; i < 10; i++) {
6538 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6539 return;
6540
6541 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6542
6543 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6544 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6545 event | APE_EVENT_STATUS_EVENT_PENDING);
6546
6547 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6548
6549 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6550 break;
6551
6552 udelay(100);
6553 }
6554
6555 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6556 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6557}
6558
6559static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6560{
6561 u32 event;
6562 u32 apedata;
6563
6564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6565 return;
6566
6567 switch (kind) {
33f401ae
MC		 6568 case RESET_KIND_INIT:
6569 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6570 APE_HOST_SEG_SIG_MAGIC);
6571 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6572 APE_HOST_SEG_LEN_MAGIC);
6573 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6574 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6575 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6576 APE_HOST_DRIVER_ID_MAGIC);
6577 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6578 APE_HOST_BEHAV_NO_PHYLOCK);
6579
6580 event = APE_EVENT_STATUS_STATE_START;
6581 break;
6582 case RESET_KIND_SHUTDOWN:
6583 /* With the interface we are currently using,
6584 * APE does not track driver state. Wiping
6585 * out the HOST SEGMENT SIGNATURE forces
6586 * the APE to assume OS absent status.
6587 */
6588 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
b2aee154 6589
33f401ae
MC		 6590 event = APE_EVENT_STATUS_STATE_UNLOAD;
6591 break;
6592 case RESET_KIND_SUSPEND:
6593 event = APE_EVENT_STATUS_STATE_SUSPEND;
6594 break;
6595 default:
6596 return;
0d3031d9
MC		 6597 }
6598
6599 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6600
6601 tg3_ape_send_event(tp, event);
6602}
6603
1da177e4
LT		 6604/* tp->lock is held. */
6605static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6606{
f49639e6
DM		 6607 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6608 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6609
6610 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6611 switch (kind) {
6612 case RESET_KIND_INIT:
6613 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6614 DRV_STATE_START);
6615 break;
6616
6617 case RESET_KIND_SHUTDOWN:
6618 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6619 DRV_STATE_UNLOAD);
6620 break;
6621
6622 case RESET_KIND_SUSPEND:
6623 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6624 DRV_STATE_SUSPEND);
6625 break;
6626
6627 default:
6628 break;
855e1111 6629 }
1da177e4 6630 }
0d3031d9
MC		 6631
6632 if (kind == RESET_KIND_INIT ||
6633 kind == RESET_KIND_SUSPEND)
6634 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6635}
6636
6637/* tp->lock is held. */
6638static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6639{
6640 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6641 switch (kind) {
6642 case RESET_KIND_INIT:
6643 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6644 DRV_STATE_START_DONE);
6645 break;
6646
6647 case RESET_KIND_SHUTDOWN:
6648 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6649 DRV_STATE_UNLOAD_DONE);
6650 break;
6651
6652 default:
6653 break;
855e1111 6654 }
1da177e4 6655 }
0d3031d9
MC		 6656
6657 if (kind == RESET_KIND_SHUTDOWN)
6658 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6659}
6660
6661/* tp->lock is held. */
6662static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6663{
6664 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6665 switch (kind) {
6666 case RESET_KIND_INIT:
6667 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6668 DRV_STATE_START);
6669 break;
6670
6671 case RESET_KIND_SHUTDOWN:
6672 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6673 DRV_STATE_UNLOAD);
6674 break;
6675
6676 case RESET_KIND_SUSPEND:
6677 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6678 DRV_STATE_SUSPEND);
6679 break;
6680
6681 default:
6682 break;
855e1111 6683 }
1da177e4
LT		 6684 }
6685}
6686
7a6f4369
MC		 6687static int tg3_poll_fw(struct tg3 *tp)
6688{
6689 int i;
6690 u32 val;
6691
b5d3772c 6692 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6693 /* Wait up to 20ms for init done. */
6694 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6695 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6696 return 0;
0ccead18 6697 udelay(100);
b5d3772c
MC		 6698 }
6699 return -ENODEV;
6700 }
6701
7a6f4369
MC		 6702 /* Wait for firmware initialization to complete. */
6703 for (i = 0; i < 100000; i++) {
6704 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6705 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6706 break;
6707 udelay(10);
6708 }
6709
6710 /* Chip might not be fitted with firmware. Some Sun onboard
6711 * parts are configured like that. So don't signal the timeout
6712 * of the above loop as an error, but do report the lack of
6713 * running firmware once.
6714 */
6715 if (i >= 100000 &&
6716 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6717 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6718
05dbe005 6719 netdev_info(tp->dev, "No firmware running\n");
7a6f4369
MC		 6720 }
6721
6b10c165
MC		 6722 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6723 /* The 57765 A0 needs a little more
6724 * time to do some important work.
6725 */
6726 mdelay(10);
6727 }
6728
7a6f4369
MC		 6729 return 0;
6730}
6731
ee6a99b5
MC		 6732/* Save PCI command register before chip reset */
6733static void tg3_save_pci_state(struct tg3 *tp)
6734{
8a6eac90 6735 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6736}
6737
6738/* Restore PCI state after chip reset */
6739static void tg3_restore_pci_state(struct tg3 *tp)
6740{
6741 u32 val;
6742
6743 /* Re-enable indirect register accesses. */
6744 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6745 tp->misc_host_ctrl);
6746
6747 /* Set MAX PCI retry to zero. */
6748 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6749 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6750 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6751 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6752 /* Allow reads and writes to the APE register and memory space. */
6753 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6754 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6755 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6756 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6757
8a6eac90 6758 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6759
fcb389df
MC		 6760 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6761 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6762 pcie_set_readrq(tp->pdev, 4096);
6763 else {
6764 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6765 tp->pci_cacheline_sz);
6766 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6767 tp->pci_lat_timer);
6768 }
114342f2 6769 }
5f5c51e3 6770
ee6a99b5 6771 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6772 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6773 u16 pcix_cmd;
6774
6775 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6776 &pcix_cmd);
6777 pcix_cmd &= ~PCI_X_CMD_ERO;
6778 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6779 pcix_cmd);
6780 }
ee6a99b5
MC		 6781
6782 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6783
6784 /* Chip reset on 5780 will reset MSI enable bit,
6785 * so need to restore it.
6786 */
6787 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6788 u16 ctrl;
6789
6790 pci_read_config_word(tp->pdev,
6791 tp->msi_cap + PCI_MSI_FLAGS,
6792 &ctrl);
6793 pci_write_config_word(tp->pdev,
6794 tp->msi_cap + PCI_MSI_FLAGS,
6795 ctrl | PCI_MSI_FLAGS_ENABLE);
6796 val = tr32(MSGINT_MODE);
6797 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6798 }
6799 }
6800}
6801
1da177e4
LT		 6802static void tg3_stop_fw(struct tg3 *);
6803
6804/* tp->lock is held. */
6805static int tg3_chip_reset(struct tg3 *tp)
6806{
6807 u32 val;
1ee582d8 6808 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6809 int i, err;
1da177e4 6810
f49639e6
DM		 6811 tg3_nvram_lock(tp);
6812
77b483f1
MC		 6813 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6814
f49639e6
DM		 6815 /* No matching tg3_nvram_unlock() after this because
6816 * chip reset below will undo the nvram lock.
6817 */
6818 tp->nvram_lock_cnt = 0;
1da177e4 6819
ee6a99b5
MC		 6820 /* GRC_MISC_CFG core clock reset will clear the memory
6821 * enable bit in PCI register 4 and the MSI enable bit
6822 * on some chips, so we save relevant registers here.
6823 */
6824 tg3_save_pci_state(tp);
6825
d9ab5ad1 6826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6827 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6828 tw32(GRC_FASTBOOT_PC, 0);
6829
1da177e4
LT		 6830 /*
6831 * We must avoid the readl() that normally takes place.
6832 * It locks machines, causes machine checks, and other
6833 * fun things. So, temporarily disable the 5701
6834 * hardware workaround, while we do the reset.
6835 */
1ee582d8
MC		 6836 write_op = tp->write32;
6837 if (write_op == tg3_write_flush_reg32)
6838 tp->write32 = tg3_write32;
1da177e4 6839
d18edcb2
MC		 6840 /* Prevent the irq handler from reading or writing PCI registers
6841 * during chip reset when the memory enable bit in the PCI command
6842 * register may be cleared. The chip does not generate interrupt
6843 * at this time, but the irq handler may still be called due to irq
6844 * sharing or irqpoll.
6845 */
6846 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6847 for (i = 0; i < tp->irq_cnt; i++) {
6848 struct tg3_napi *tnapi = &tp->napi[i];
6849 if (tnapi->hw_status) {
6850 tnapi->hw_status->status = 0;
6851 tnapi->hw_status->status_tag = 0;
6852 }
6853 tnapi->last_tag = 0;
6854 tnapi->last_irq_tag = 0;
b8fa2f3a 6855 }
d18edcb2 6856 smp_mb();
4f125f42
MC		 6857
6858 for (i = 0; i < tp->irq_cnt; i++)
6859 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6860
255ca311
MC		 6861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6862 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6863 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6864 }
6865
1da177e4
LT		 6866 /* do the reset */
6867 val = GRC_MISC_CFG_CORECLK_RESET;
6868
6869 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6870 if (tr32(0x7e2c) == 0x60) {
6871 tw32(0x7e2c, 0x20);
6872 }
6873 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6874 tw32(GRC_MISC_CFG, (1 << 29));
6875 val |= (1 << 29);
6876 }
6877 }
6878
b5d3772c
MC		 6879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6880 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6881 tw32(GRC_VCPU_EXT_CTRL,
6882 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6883 }
6884
1da177e4
LT		 6885 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6886 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6887 tw32(GRC_MISC_CFG, val);
6888
1ee582d8
MC		 6889 /* restore 5701 hardware bug workaround write method */
6890 tp->write32 = write_op;
1da177e4
LT		 6891
6892 /* Unfortunately, we have to delay before the PCI read back.
6893 * Some 575X chips even will not respond to a PCI cfg access
6894 * when the reset command is given to the chip.
6895 *
6896 * How do these hardware designers expect things to work
6897 * properly if the PCI write is posted for a long period
6898 * of time? It is always necessary to have some method by
6899 * which a register read back can occur to push the write
6900 * out which does the reset.
6901 *
6902 * For most tg3 variants the trick below was working.
6903 * Ho hum...
6904 */
6905 udelay(120);
6906
6907 /* Flush PCI posted writes. The normal MMIO registers
6908 * are inaccessible at this time so this is the only
6909 * way to make this reliably (actually, this is no longer
6910 * the case, see above). I tried to use indirect
6911 * register read/write but this upset some 5701 variants.
6912 */
6913 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6914
6915 udelay(120);
6916
5e7dfd0f 6917 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6918 u16 val16;
6919
1da177e4
LT		 6920 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6921 int i;
6922 u32 cfg_val;
6923
6924 /* Wait for link training to complete. */
6925 for (i = 0; i < 5000; i++)
6926 udelay(100);
6927
6928 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6929 pci_write_config_dword(tp->pdev, 0xc4,
6930 cfg_val | (1 << 15));
6931 }
5e7dfd0f 6932
e7126997
MC		 6933 /* Clear the "no snoop" and "relaxed ordering" bits. */
6934 pci_read_config_word(tp->pdev,
6935 tp->pcie_cap + PCI_EXP_DEVCTL,
6936 &val16);
6937 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6938 PCI_EXP_DEVCTL_NOSNOOP_EN);
6939 /*
6940 * Older PCIe devices only support the 128 byte
6941 * MPS setting. Enforce the restriction.
5e7dfd0f 6942 */
e7126997
MC		 6943 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6944 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6945 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6946 pci_write_config_word(tp->pdev,
6947 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6948 val16);
5e7dfd0f
MC		 6949
6950 pcie_set_readrq(tp->pdev, 4096);
6951
6952 /* Clear error status */
6953 pci_write_config_word(tp->pdev,
6954 tp->pcie_cap + PCI_EXP_DEVSTA,
6955 PCI_EXP_DEVSTA_CED |
6956 PCI_EXP_DEVSTA_NFED |
6957 PCI_EXP_DEVSTA_FED |
6958 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6959 }
6960
ee6a99b5 6961 tg3_restore_pci_state(tp);
1da177e4 6962
d18edcb2
MC		 6963 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6964
ee6a99b5
MC		 6965 val = 0;
6966 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6967 val = tr32(MEMARB_MODE);
ee6a99b5 6968 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6969
6970 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6971 tg3_stop_fw(tp);
6972 tw32(0x5000, 0x400);
6973 }
6974
6975 tw32(GRC_MODE, tp->grc_mode);
6976
6977 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6978 val = tr32(0xc4);
1da177e4
LT		 6979
6980 tw32(0xc4, val | (1 << 15));
6981 }
6982
6983 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6985 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6986 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6987 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6988 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6989 }
6990
6991 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6992 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6993 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6994 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6995 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6996 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6997 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6998 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6999 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7000 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7001 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 7002 } else
7003 tw32_f(MAC_MODE, 0);
7004 udelay(40);
7005
77b483f1
MC		 7006 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7007
7a6f4369
MC		 7008 err = tg3_poll_fw(tp);
7009 if (err)
7010 return err;
1da177e4 7011
0a9140cf
MC		 7012 tg3_mdio_start(tp);
7013
52cdf852
MC		 7014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7015 u8 phy_addr;
7016
7017 phy_addr = tp->phy_addr;
7018 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7019
7020 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7021 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7022 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7023 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7024 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7025 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7026 udelay(10);
7027
7028 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7029 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7030 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7031 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7032 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7033 udelay(10);
7034
7035 tp->phy_addr = phy_addr;
7036 }
7037
1da177e4 7038 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 7039 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7040 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 7041 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7042 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 7043 val = tr32(0x7c00);
1da177e4
LT		 7044
7045 tw32(0x7c00, val | (1 << 25));
7046 }
7047
7048 /* Reprobe ASF enable state. */
7049 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7050 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7051 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7052 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7053 u32 nic_cfg;
7054
7055 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7056 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7057 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 7058 tp->last_event_jiffies = jiffies;
cbf46853 7059 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7060 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7061 }
7062 }
7063
7064 return 0;
7065}
7066
7067/* tp->lock is held. */
7068static void tg3_stop_fw(struct tg3 *tp)
7069{
0d3031d9
MC		 7070 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7071 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7072 /* Wait for RX cpu to ACK the previous event. */
7073 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7074
7075 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7076
7077 tg3_generate_fw_event(tp);
1da177e4 7078
7c5026aa
MC		 7079 /* Wait for RX cpu to ACK this event. */
7080 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7081 }
7082}
7083
7084/* tp->lock is held. */
944d980e 7085static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7086{
7087 int err;
7088
7089 tg3_stop_fw(tp);
7090
944d980e 7091 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7092
b3b7d6be 7093 tg3_abort_hw(tp, silent);
1da177e4
LT		 7094 err = tg3_chip_reset(tp);
7095
daba2a63
MC		 7096 __tg3_set_mac_addr(tp, 0);
7097
944d980e
MC		 7098 tg3_write_sig_legacy(tp, kind);
7099 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7100
7101 if (err)
7102 return err;
7103
7104 return 0;
7105}
7106
1da177e4
LT		 7107#define RX_CPU_SCRATCH_BASE 0x30000
7108#define RX_CPU_SCRATCH_SIZE 0x04000
7109#define TX_CPU_SCRATCH_BASE 0x34000
7110#define TX_CPU_SCRATCH_SIZE 0x04000
7111
7112/* tp->lock is held. */
7113static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7114{
7115 int i;
7116
5d9428de
ES		 7117 BUG_ON(offset == TX_CPU_BASE &&
7118 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7119
b5d3772c
MC		 7120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7121 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7122
7123 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7124 return 0;
7125 }
1da177e4
LT		 7126 if (offset == RX_CPU_BASE) {
7127 for (i = 0; i < 10000; i++) {
7128 tw32(offset + CPU_STATE, 0xffffffff);
7129 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7130 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7131 break;
7132 }
7133
7134 tw32(offset + CPU_STATE, 0xffffffff);
7135 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7136 udelay(10);
7137 } else {
7138 for (i = 0; i < 10000; i++) {
7139 tw32(offset + CPU_STATE, 0xffffffff);
7140 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7141 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7142 break;
7143 }
7144 }
7145
7146 if (i >= 10000) {
05dbe005
JP		 7147 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7148 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
1da177e4
LT		 7149 return -ENODEV;
7150 }
ec41c7df
MC		 7151
7152 /* Clear firmware's nvram arbitration. */
7153 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7154 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7155 return 0;
7156}
7157
7158struct fw_info {
077f849d
JSR		 7159 unsigned int fw_base;
7160 unsigned int fw_len;
7161 const __be32 *fw_data;
1da177e4
LT		 7162};
7163
7164/* tp->lock is held. */
7165static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7166 int cpu_scratch_size, struct fw_info *info)
7167{
ec41c7df 7168 int err, lock_err, i;
1da177e4
LT		 7169 void (*write_op)(struct tg3 *, u32, u32);
7170
7171 if (cpu_base == TX_CPU_BASE &&
7172 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5129c3a3
MC		 7173 netdev_err(tp->dev,
7174 "%s: Trying to load TX cpu firmware which is 5705\n",
05dbe005 7175 __func__);
1da177e4
LT		 7176 return -EINVAL;
7177 }
7178
7179 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7180 write_op = tg3_write_mem;
7181 else
7182 write_op = tg3_write_indirect_reg32;
7183
1b628151
MC		 7184 /* It is possible that bootcode is still loading at this point.
7185 * Get the nvram lock first before halting the cpu.
7186 */
ec41c7df 7187 lock_err = tg3_nvram_lock(tp);
1da177e4 7188 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7189 if (!lock_err)
7190 tg3_nvram_unlock(tp);
1da177e4
LT		 7191 if (err)
7192 goto out;
7193
7194 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7195 write_op(tp, cpu_scratch_base + i, 0);
7196 tw32(cpu_base + CPU_STATE, 0xffffffff);
7197 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7198 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7199 write_op(tp, (cpu_scratch_base +
077f849d 7200 (info->fw_base & 0xffff) +
1da177e4 7201 (i * sizeof(u32))),
077f849d 7202 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7203
7204 err = 0;
7205
7206out:
1da177e4
LT		 7207 return err;
7208}
7209
7210/* tp->lock is held. */
7211static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7212{
7213 struct fw_info info;
077f849d 7214 const __be32 *fw_data;
1da177e4
LT		 7215 int err, i;
7216
077f849d
JSR		 7217 fw_data = (void *)tp->fw->data;
7218
7219 /* Firmware blob starts with version numbers, followed by
7220 start address and length. We are setting complete length.
7221 length = end_address_of_bss - start_address_of_text.
7222 Remainder is the blob to be loaded contiguously
7223 from start address. */
7224
7225 info.fw_base = be32_to_cpu(fw_data[1]);
7226 info.fw_len = tp->fw->size - 12;
7227 info.fw_data = &fw_data[3];
1da177e4
LT		 7228
7229 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7230 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7231 &info);
7232 if (err)
7233 return err;
7234
7235 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7236 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7237 &info);
7238 if (err)
7239 return err;
7240
7241 /* Now startup only the RX cpu. */
7242 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7243 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7244
7245 for (i = 0; i < 5; i++) {
077f849d 7246 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7247 break;
7248 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7249 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7250 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7251 udelay(1000);
7252 }
7253 if (i >= 5) {
5129c3a3
MC		 7254 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7255 "should be %08x\n", __func__,
05dbe005 7256 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
1da177e4
LT		 7257 return -ENODEV;
7258 }
7259 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7260 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7261
7262 return 0;
7263}
7264
1da177e4 7265/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7266
7267/* tp->lock is held. */
7268static int tg3_load_tso_firmware(struct tg3 *tp)
7269{
7270 struct fw_info info;
077f849d 7271 const __be32 *fw_data;
1da177e4
LT		 7272 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7273 int err, i;
7274
7275 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7276 return 0;
7277
077f849d
JSR		 7278 fw_data = (void *)tp->fw->data;
7279
7280 /* Firmware blob starts with version numbers, followed by
7281 start address and length. We are setting complete length.
7282 length = end_address_of_bss - start_address_of_text.
7283 Remainder is the blob to be loaded contiguously
7284 from start address. */
7285
7286 info.fw_base = be32_to_cpu(fw_data[1]);
7287 cpu_scratch_size = tp->fw_len;
7288 info.fw_len = tp->fw->size - 12;
7289 info.fw_data = &fw_data[3];
7290
1da177e4 7291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7292 cpu_base = RX_CPU_BASE;
7293 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7294 } else {
1da177e4
LT		 7295 cpu_base = TX_CPU_BASE;
7296 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7297 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7298 }
7299
7300 err = tg3_load_firmware_cpu(tp, cpu_base,
7301 cpu_scratch_base, cpu_scratch_size,
7302 &info);
7303 if (err)
7304 return err;
7305
7306 /* Now startup the cpu. */
7307 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7308 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7309
7310 for (i = 0; i < 5; i++) {
077f849d 7311 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7312 break;
7313 tw32(cpu_base + CPU_STATE, 0xffffffff);
7314 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7315 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7316 udelay(1000);
7317 }
7318 if (i >= 5) {
5129c3a3
MC		 7319 netdev_err(tp->dev,
7320 "%s fails to set CPU PC, is %08x should be %08x\n",
05dbe005 7321 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
1da177e4
LT		 7322 return -ENODEV;
7323 }
7324 tw32(cpu_base + CPU_STATE, 0xffffffff);
7325 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7326 return 0;
7327}
7328
1da177e4 7329
1da177e4
LT		 7330static int tg3_set_mac_addr(struct net_device *dev, void *p)
7331{
7332 struct tg3 *tp = netdev_priv(dev);
7333 struct sockaddr *addr = p;
986e0aeb 7334 int err = 0, skip_mac_1 = 0;
1da177e4 7335
f9804ddb
MC		 7336 if (!is_valid_ether_addr(addr->sa_data))
7337 return -EINVAL;
7338
1da177e4
LT		 7339 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7340
e75f7c90
MC		 7341 if (!netif_running(dev))
7342 return 0;
7343
58712ef9 7344 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7345 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7346
986e0aeb
MC		 7347 addr0_high = tr32(MAC_ADDR_0_HIGH);
7348 addr0_low = tr32(MAC_ADDR_0_LOW);
7349 addr1_high = tr32(MAC_ADDR_1_HIGH);
7350 addr1_low = tr32(MAC_ADDR_1_LOW);
7351
7352 /* Skip MAC addr 1 if ASF is using it. */
7353 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7354 !(addr1_high == 0 && addr1_low == 0))
7355 skip_mac_1 = 1;
58712ef9 7356 }
986e0aeb
MC		 7357 spin_lock_bh(&tp->lock);
7358 __tg3_set_mac_addr(tp, skip_mac_1);
7359 spin_unlock_bh(&tp->lock);
1da177e4 7360
b9ec6c1b 7361 return err;
1da177e4
LT		 7362}
7363
7364/* tp->lock is held. */
7365static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7366 dma_addr_t mapping, u32 maxlen_flags,
7367 u32 nic_addr)
7368{
7369 tg3_write_mem(tp,
7370 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7371 ((u64) mapping >> 32));
7372 tg3_write_mem(tp,
7373 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7374 ((u64) mapping & 0xffffffff));
7375 tg3_write_mem(tp,
7376 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7377 maxlen_flags);
7378
7379 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7380 tg3_write_mem(tp,
7381 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7382 nic_addr);
7383}
7384
7385static void __tg3_set_rx_mode(struct net_device *);
d244c892 7386static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7387{
b6080e12
MC		 7388 int i;
7389
19cfaecc 7390 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7391 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7392 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7393 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7394 } else {
7395 tw32(HOSTCC_TXCOL_TICKS, 0);
7396 tw32(HOSTCC_TXMAX_FRAMES, 0);
7397 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7398 }
b6080e12 7399
19cfaecc
MC		 7400 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7401 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7402 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7403 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7404 } else {
b6080e12
MC		 7405 tw32(HOSTCC_RXCOL_TICKS, 0);
7406 tw32(HOSTCC_RXMAX_FRAMES, 0);
7407 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7408 }
b6080e12 7409
15f9850d
DM		 7410 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7411 u32 val = ec->stats_block_coalesce_usecs;
7412
b6080e12
MC		 7413 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7414 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7415
15f9850d
DM		 7416 if (!netif_carrier_ok(tp->dev))
7417 val = 0;
7418
7419 tw32(HOSTCC_STAT_COAL_TICKS, val);
7420 }
b6080e12
MC		 7421
7422 for (i = 0; i < tp->irq_cnt - 1; i++) {
7423 u32 reg;
7424
7425 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7426 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7427 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7428 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7429 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7430 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7431
7432 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7433 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7434 tw32(reg, ec->tx_coalesce_usecs);
7435 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7436 tw32(reg, ec->tx_max_coalesced_frames);
7437 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7438 tw32(reg, ec->tx_max_coalesced_frames_irq);
7439 }
b6080e12
MC		 7440 }
7441
7442 for (; i < tp->irq_max - 1; i++) {
7443 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7444 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7445 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7446
7447 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7448 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7449 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7450 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7451 }
b6080e12 7452 }
15f9850d 7453}
1da177e4 7454
2d31ecaf
MC		 7455/* tp->lock is held. */
7456static void tg3_rings_reset(struct tg3 *tp)
7457{
7458 int i;
f77a6a8e 7459 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7460 struct tg3_napi *tnapi = &tp->napi[0];
7461
7462 /* Disable all transmit rings but the first. */
7463 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7464 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7465 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7466 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7467 else
7468 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7469
7470 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7471 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7472 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7473 BDINFO_FLAGS_DISABLED);
7474
7475
7476 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7478 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7479 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7480 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7481 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7482 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7483 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7484 else
7485 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7486
7487 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7488 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7489 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7490 BDINFO_FLAGS_DISABLED);
7491
7492 /* Disable interrupts */
7493 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7494
7495 /* Zero mailbox registers. */
f77a6a8e
MC		 7496 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7497 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7498 tp->napi[i].tx_prod = 0;
7499 tp->napi[i].tx_cons = 0;
c2353a32
MC		 7500 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7501 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 7502 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7503 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7504 }
c2353a32
MC		 7505 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7506 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 7507 } else {
7508 tp->napi[0].tx_prod = 0;
7509 tp->napi[0].tx_cons = 0;
7510 tw32_mailbox(tp->napi[0].prodmbox, 0);
7511 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7512 }
2d31ecaf
MC		 7513
7514 /* Make sure the NIC-based send BD rings are disabled. */
7515 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7516 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7517 for (i = 0; i < 16; i++)
7518 tw32_tx_mbox(mbox + i * 8, 0);
7519 }
7520
7521 txrcb = NIC_SRAM_SEND_RCB;
7522 rxrcb = NIC_SRAM_RCV_RET_RCB;
7523
7524 /* Clear status block in ram. */
7525 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7526
7527 /* Set status block DMA address */
7528 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7529 ((u64) tnapi->status_mapping >> 32));
7530 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7531 ((u64) tnapi->status_mapping & 0xffffffff));
7532
f77a6a8e
MC		 7533 if (tnapi->tx_ring) {
7534 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7535 (TG3_TX_RING_SIZE <<
7536 BDINFO_FLAGS_MAXLEN_SHIFT),
7537 NIC_SRAM_TX_BUFFER_DESC);
7538 txrcb += TG3_BDINFO_SIZE;
7539 }
7540
7541 if (tnapi->rx_rcb) {
7542 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7543 (TG3_RX_RCB_RING_SIZE(tp) <<
7544 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7545 rxrcb += TG3_BDINFO_SIZE;
7546 }
7547
7548 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7549
f77a6a8e
MC		 7550 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7551 u64 mapping = (u64)tnapi->status_mapping;
7552 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7553 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7554
7555 /* Clear status block in ram. */
7556 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7557
19cfaecc
MC		 7558 if (tnapi->tx_ring) {
7559 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7560 (TG3_TX_RING_SIZE <<
7561 BDINFO_FLAGS_MAXLEN_SHIFT),
7562 NIC_SRAM_TX_BUFFER_DESC);
7563 txrcb += TG3_BDINFO_SIZE;
7564 }
f77a6a8e
MC		 7565
7566 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7567 (TG3_RX_RCB_RING_SIZE(tp) <<
7568 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7569
7570 stblk += 8;
f77a6a8e
MC		 7571 rxrcb += TG3_BDINFO_SIZE;
7572 }
2d31ecaf
MC		 7573}
7574
1da177e4 7575/* tp->lock is held. */
8e7a22e3 7576static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7577{
7578 u32 val, rdmac_mode;
7579 int i, err, limit;
21f581a5 7580 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7581
7582 tg3_disable_ints(tp);
7583
7584 tg3_stop_fw(tp);
7585
7586 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7587
7588 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7589 tg3_abort_hw(tp, 1);
1da177e4
LT		 7590 }
7591
603f1173 7592 if (reset_phy)
d4d2c558
MC		 7593 tg3_phy_reset(tp);
7594
1da177e4
LT		 7595 err = tg3_chip_reset(tp);
7596 if (err)
7597 return err;
7598
7599 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7600
bcb37f6c 7601 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7602 val = tr32(TG3_CPMU_CTRL);
7603 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7604 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7605
7606 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7607 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7608 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7609 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7610
7611 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7612 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7613 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7614 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7615
7616 val = tr32(TG3_CPMU_HST_ACC);
7617 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7618 val |= CPMU_HST_ACC_MACCLK_6_25;
7619 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7620 }
7621
33466d93
MC		 7622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7623 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7624 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7625 PCIE_PWR_MGMT_L1_THRESH_4MS;
7626 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7627
7628 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7629 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7630
7631 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7632
f40386c8
MC		 7633 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7634 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7635 }
7636
614b0590
MC		 7637 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7638 u32 grc_mode = tr32(GRC_MODE);
7639
7640 /* Access the lower 1K of PL PCIE block registers. */
7641 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7642 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7643
7644 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7645 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7646 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7647
7648 tw32(GRC_MODE, grc_mode);
7649 }
7650
1da177e4
LT		 7651 /* This works around an issue with Athlon chipsets on
7652 * B3 tigon3 silicon. This bit has no effect on any
7653 * other revision. But do not set this on PCI Express
795d01c5 7654 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7655 */
795d01c5
MC		 7656 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7657 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7658 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7659 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7660 }
1da177e4
LT		 7661
7662 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7663 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7664 val = tr32(TG3PCI_PCISTATE);
7665 val |= PCISTATE_RETRY_SAME_DMA;
7666 tw32(TG3PCI_PCISTATE, val);
7667 }
7668
0d3031d9
MC		 7669 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7670 /* Allow reads and writes to the
7671 * APE register and memory space.
7672 */
7673 val = tr32(TG3PCI_PCISTATE);
7674 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7675 PCISTATE_ALLOW_APE_SHMEM_WR;
7676 tw32(TG3PCI_PCISTATE, val);
7677 }
7678
1da177e4
LT		 7679 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7680 /* Enable some hw fixes. */
7681 val = tr32(TG3PCI_MSI_DATA);
7682 val |= (1 << 26) | (1 << 28) | (1 << 29);
7683 tw32(TG3PCI_MSI_DATA, val);
7684 }
7685
7686 /* Descriptor ring init may make accesses to the
7687 * NIC SRAM area to setup the TX descriptors, so we
7688 * can only do this after the hardware has been
7689 * successfully reset.
7690 */
32d8c572
MC		 7691 err = tg3_init_rings(tp);
7692 if (err)
7693 return err;
1da177e4 7694
b703df6f
MC		 7695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7696 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7697 val = tr32(TG3PCI_DMA_RW_CTRL) &
7698 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7699 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7700 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7701 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7702 /* This value is determined during the probe time DMA
7703 * engine test, tg3_test_dma.
7704 */
7705 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7706 }
1da177e4
LT		 7707
7708 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7709 GRC_MODE_4X_NIC_SEND_RINGS |
7710 GRC_MODE_NO_TX_PHDR_CSUM |
7711 GRC_MODE_NO_RX_PHDR_CSUM);
7712 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7713
7714 /* Pseudo-header checksum is done by hardware logic and not
7715 * the offload processers, so make the chip do the pseudo-
7716 * header checksums on receive. For transmit it is more
7717 * convenient to do the pseudo-header checksum in software
7718 * as Linux does that on transmit for us in all cases.
7719 */
7720 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7721
7722 tw32(GRC_MODE,
7723 tp->grc_mode |
7724 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7725
7726 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7727 val = tr32(GRC_MISC_CFG);
7728 val &= ~0xff;
7729 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7730 tw32(GRC_MISC_CFG, val);
7731
7732 /* Initialize MBUF/DESC pool. */
cbf46853 7733 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7734 /* Do nothing. */
7735 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7736 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7737 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7738 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7739 else
7740 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7741 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7742 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7743 }
1da177e4
LT		 7744 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7745 int fw_len;
7746
077f849d 7747 fw_len = tp->fw_len;
1da177e4
LT		 7748 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7749 tw32(BUFMGR_MB_POOL_ADDR,
7750 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7751 tw32(BUFMGR_MB_POOL_SIZE,
7752 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7753 }
1da177e4 7754
0f893dc6 7755 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7756 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7757 tp->bufmgr_config.mbuf_read_dma_low_water);
7758 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7759 tp->bufmgr_config.mbuf_mac_rx_low_water);
7760 tw32(BUFMGR_MB_HIGH_WATER,
7761 tp->bufmgr_config.mbuf_high_water);
7762 } else {
7763 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7764 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7765 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7766 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7767 tw32(BUFMGR_MB_HIGH_WATER,
7768 tp->bufmgr_config.mbuf_high_water_jumbo);
7769 }
7770 tw32(BUFMGR_DMA_LOW_WATER,
7771 tp->bufmgr_config.dma_low_water);
7772 tw32(BUFMGR_DMA_HIGH_WATER,
7773 tp->bufmgr_config.dma_high_water);
7774
7775 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7776 for (i = 0; i < 2000; i++) {
7777 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7778 break;
7779 udelay(10);
7780 }
7781 if (i >= 2000) {
05dbe005 7782 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 7783 return -ENODEV;
7784 }
7785
7786 /* Setup replenish threshold. */
f92905de
MC		 7787 val = tp->rx_pending / 8;
7788 if (val == 0)
7789 val = 1;
7790 else if (val > tp->rx_std_max_post)
7791 val = tp->rx_std_max_post;
b5d3772c
MC		 7792 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7793 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7794 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7795
7796 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7797 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7798 }
f92905de
MC		 7799
7800 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7801
7802 /* Initialize TG3_BDINFO's at:
7803 * RCVDBDI_STD_BD: standard eth size rx ring
7804 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7805 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7806 *
7807 * like so:
7808 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7809 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7810 * ring attribute flags
7811 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7812 *
7813 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7814 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7815 *
7816 * The size of each ring is fixed in the firmware, but the location is
7817 * configurable.
7818 */
7819 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7820 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7821 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7822 ((u64) tpr->rx_std_mapping & 0xffffffff));
13fa95b0 7823 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7824 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7825 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7826
fdb72b38
MC		 7827 /* Disable the mini ring */
7828 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7829 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7830 BDINFO_FLAGS_DISABLED);
7831
fdb72b38
MC		 7832 /* Program the jumbo buffer descriptor ring control
7833 * blocks on those devices that have them.
7834 */
8f666b07 7835 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7836 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7837 /* Setup replenish threshold. */
7838 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7839
0f893dc6 7840 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7841 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7842 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7843 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7844 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7845 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7846 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7847 BDINFO_FLAGS_USE_EXT_RECV);
5fd68fbd 7848 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7849 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7850 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7851 } else {
7852 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7853 BDINFO_FLAGS_DISABLED);
7854 }
7855
b703df6f
MC		 7856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7858 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7859 (RX_STD_MAX_SIZE << 2);
7860 else
7861 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7862 } else
7863 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7864
7865 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7866
411da640 7867 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7868 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7869
411da640 7870 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7871 tp->rx_jumbo_pending : 0;
66711e66 7872 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7873
b703df6f
MC		 7874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7876 tw32(STD_REPLENISH_LWM, 32);
7877 tw32(JMB_REPLENISH_LWM, 16);
7878 }
7879
2d31ecaf
MC		 7880 tg3_rings_reset(tp);
7881
1da177e4 7882 /* Initialize MAC address and backoff seed. */
986e0aeb 7883 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7884
7885 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7886 tw32(MAC_RX_MTU_SIZE,
7887 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7888
7889 /* The slot time is changed by tg3_setup_phy if we
7890 * run at gigabit with half duplex.
7891 */
7892 tw32(MAC_TX_LENGTHS,
7893 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7894 (6 << TX_LENGTHS_IPG_SHIFT) |
7895 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7896
7897 /* Receive rules. */
7898 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7899 tw32(RCVLPC_CONFIG, 0x0181);
7900
7901 /* Calculate RDMAC_MODE setting early, we need it to determine
7902 * the RCVLPC_STATE_ENABLE mask.
7903 */
7904 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7905 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7906 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7907 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7908 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7909
0339e4e3
MC		 7910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7911 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7912
57e6983c 7913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7916 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7917 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7918 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7919
85e94ced
MC		 7920 /* If statement applies to 5705 and 5750 PCI devices only */
7921 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7922 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7923 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7924 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7926 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7927 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7928 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7929 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7930 }
7931 }
7932
85e94ced
MC		 7933 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7934 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7935
1da177e4 7936 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7937 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7938
e849cdc3
MC		 7939 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7940 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7942 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7943
7944 /* Receive/send statistics. */
1661394e
MC		 7945 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7946 val = tr32(RCVLPC_STATS_ENABLE);
7947 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7948 tw32(RCVLPC_STATS_ENABLE, val);
7949 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7950 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7951 val = tr32(RCVLPC_STATS_ENABLE);
7952 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7953 tw32(RCVLPC_STATS_ENABLE, val);
7954 } else {
7955 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7956 }
7957 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7958 tw32(SNDDATAI_STATSENAB, 0xffffff);
7959 tw32(SNDDATAI_STATSCTRL,
7960 (SNDDATAI_SCTRL_ENABLE |
7961 SNDDATAI_SCTRL_FASTUPD));
7962
7963 /* Setup host coalescing engine. */
7964 tw32(HOSTCC_MODE, 0);
7965 for (i = 0; i < 2000; i++) {
7966 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7967 break;
7968 udelay(10);
7969 }
7970
d244c892 7971 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7972
1da177e4
LT		 7973 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7974 /* Status/statistics block address. See tg3_timer,
7975 * the tg3_periodic_fetch_stats call there, and
7976 * tg3_get_stats to see how this works for 5705/5750 chips.
7977 */
1da177e4
LT		 7978 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7979 ((u64) tp->stats_mapping >> 32));
7980 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7981 ((u64) tp->stats_mapping & 0xffffffff));
7982 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7983
1da177e4 7984 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7985
7986 /* Clear statistics and status block memory areas */
7987 for (i = NIC_SRAM_STATS_BLK;
7988 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7989 i += sizeof(u32)) {
7990 tg3_write_mem(tp, i, 0);
7991 udelay(40);
7992 }
1da177e4
LT		 7993 }
7994
7995 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7996
7997 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7998 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7999 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8000 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8001
c94e3941
MC		 8002 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8003 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8004 /* reset to prevent losing 1st rx packet intermittently */
8005 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8006 udelay(10);
8007 }
8008
3bda1258
MC		 8009 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8010 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8011 else
8012 tp->mac_mode = 0;
8013 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 8014 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 8015 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8016 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8017 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8018 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 8019 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8020 udelay(40);
8021
314fba34 8022 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 8023 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 8024 * register to preserve the GPIO settings for LOMs. The GPIOs,
8025 * whether used as inputs or outputs, are set by boot code after
8026 * reset.
8027 */
9d26e213 8028 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 8029 u32 gpio_mask;
8030
9d26e213
MC		 8031 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8032 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8033 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 8034
8035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8036 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8037 GRC_LCLCTRL_GPIO_OUTPUT3;
8038
af36e6b6
MC		 8039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8040 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8041
aaf84465 8042 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 8043 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8044
8045 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 8046 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8047 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8048 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 8049 }
1da177e4
LT		 8050 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8051 udelay(100);
8052
baf8a94a
MC		 8053 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8054 val = tr32(MSGINT_MODE);
8055 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8056 tw32(MSGINT_MODE, val);
8057 }
8058
1da177e4
LT		 8059 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8060 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8061 udelay(40);
8062 }
8063
8064 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8065 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8066 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8067 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8068 WDMAC_MODE_LNGREAD_ENAB);
8069
85e94ced
MC		 8070 /* If statement applies to 5705 and 5750 PCI devices only */
8071 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8072 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8074 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8075 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8076 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8077 /* nothing */
8078 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8079 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8080 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8081 val |= WDMAC_MODE_RX_ACCEL;
8082 }
8083 }
8084
d9ab5ad1 8085 /* Enable host coalescing bug fix */
321d32a0 8086 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8087 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8088
788a035e
MC		 8089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8090 val |= WDMAC_MODE_BURST_ALL_DATA;
8091
1da177e4
LT		 8092 tw32_f(WDMAC_MODE, val);
8093 udelay(40);
8094
9974a356
MC		 8095 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8096 u16 pcix_cmd;
8097
8098 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8099 &pcix_cmd);
1da177e4 8100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8101 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8102 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8103 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8104 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8105 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8106 }
9974a356
MC		 8107 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8108 pcix_cmd);
1da177e4
LT		 8109 }
8110
8111 tw32_f(RDMAC_MODE, rdmac_mode);
8112 udelay(40);
8113
8114 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8115 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8116 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8117
8118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8119 tw32(SNDDATAC_MODE,
8120 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8121 else
8122 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8123
1da177e4
LT		 8124 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8125 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8126 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8127 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8128 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8129 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8130 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8131 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8132 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8133 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8134 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8135
8136 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8137 err = tg3_load_5701_a0_firmware_fix(tp);
8138 if (err)
8139 return err;
8140 }
8141
1da177e4
LT		 8142 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8143 err = tg3_load_tso_firmware(tp);
8144 if (err)
8145 return err;
8146 }
1da177e4
LT		 8147
8148 tp->tx_mode = TX_MODE_ENABLE;
8149 tw32_f(MAC_TX_MODE, tp->tx_mode);
8150 udelay(100);
8151
baf8a94a
MC		 8152 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8153 u32 reg = MAC_RSS_INDIR_TBL_0;
8154 u8 *ent = (u8 *)&val;
8155
8156 /* Setup the indirection table */
8157 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8158 int idx = i % sizeof(val);
8159
8160 ent[idx] = i % (tp->irq_cnt - 1);
8161 if (idx == sizeof(val) - 1) {
8162 tw32(reg, val);
8163 reg += 4;
8164 }
8165 }
8166
8167 /* Setup the "secret" hash key. */
8168 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8169 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8170 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8171 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8172 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8173 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8174 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8175 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8176 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8177 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8178 }
8179
1da177e4 8180 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8181 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8182 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8183
baf8a94a
MC		 8184 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8185 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8186 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8187 RX_MODE_RSS_IPV6_HASH_EN |
8188 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8189 RX_MODE_RSS_IPV4_HASH_EN |
8190 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8191
1da177e4
LT		 8192 tw32_f(MAC_RX_MODE, tp->rx_mode);
8193 udelay(10);
8194
1da177e4
LT		 8195 tw32(MAC_LED_CTRL, tp->led_ctrl);
8196
8197 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8198 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8199 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8200 udelay(10);
8201 }
8202 tw32_f(MAC_RX_MODE, tp->rx_mode);
8203 udelay(10);
8204
8205 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8206 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8207 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8208 /* Set drive transmission level to 1.2V */
8209 /* only if the signal pre-emphasis bit is not set */
8210 val = tr32(MAC_SERDES_CFG);
8211 val &= 0xfffff000;
8212 val |= 0x880;
8213 tw32(MAC_SERDES_CFG, val);
8214 }
8215 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8216 tw32(MAC_SERDES_CFG, 0x616000);
8217 }
8218
8219 /* Prevent chip from dropping frames when flow control
8220 * is enabled.
8221 */
666bc831
MC		 8222 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8223 val = 1;
8224 else
8225 val = 2;
8226 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 8227
8228 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8229 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8230 /* Use hardware link auto-negotiation */
8231 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8232 }
8233
d4d2c558
MC		 8234 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8235 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8236 u32 tmp;
8237
8238 tmp = tr32(SERDES_RX_CTRL);
8239 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8240 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8241 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8242 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8243 }
8244
dd477003
MC		 8245 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8246 if (tp->link_config.phy_is_low_power) {
8247 tp->link_config.phy_is_low_power = 0;
8248 tp->link_config.speed = tp->link_config.orig_speed;
8249 tp->link_config.duplex = tp->link_config.orig_duplex;
8250 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8251 }
1da177e4 8252
dd477003
MC		 8253 err = tg3_setup_phy(tp, 0);
8254 if (err)
8255 return err;
1da177e4 8256
dd477003 8257 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8258 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8259 u32 tmp;
8260
8261 /* Clear CRC stats. */
8262 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8263 tg3_writephy(tp, MII_TG3_TEST1,
8264 tmp | MII_TG3_TEST1_CRC_EN);
8265 tg3_readphy(tp, 0x14, &tmp);
8266 }
1da177e4
LT		 8267 }
8268 }
8269
8270 __tg3_set_rx_mode(tp->dev);
8271
8272 /* Initialize receive rules. */
8273 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8274 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8275 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8276 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8277
4cf78e4f 8278 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8279 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8280 limit = 8;
8281 else
8282 limit = 16;
8283 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8284 limit -= 4;
8285 switch (limit) {
8286 case 16:
8287 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8288 case 15:
8289 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8290 case 14:
8291 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8292 case 13:
8293 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8294 case 12:
8295 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8296 case 11:
8297 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8298 case 10:
8299 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8300 case 9:
8301 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8302 case 8:
8303 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8304 case 7:
8305 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8306 case 6:
8307 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8308 case 5:
8309 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8310 case 4:
8311 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8312 case 3:
8313 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8314 case 2:
8315 case 1:
8316
8317 default:
8318 break;
855e1111 8319 }
1da177e4 8320
9ce768ea
MC		 8321 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8322 /* Write our heartbeat update interval to APE. */
8323 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8324 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8325
1da177e4
LT		 8326 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8327
1da177e4
LT		 8328 return 0;
8329}
8330
8331/* Called at device open time to get the chip ready for
8332 * packet processing. Invoked with tp->lock held.
8333 */
8e7a22e3 8334static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8335{
1da177e4
LT		 8336 tg3_switch_clocks(tp);
8337
8338 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8339
2f751b67 8340 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8341}
8342
8343#define TG3_STAT_ADD32(PSTAT, REG) \
8344do { u32 __val = tr32(REG); \
8345 (PSTAT)->low += __val; \
8346 if ((PSTAT)->low < __val) \
8347 (PSTAT)->high += 1; \
8348} while (0)
8349
8350static void tg3_periodic_fetch_stats(struct tg3 *tp)
8351{
8352 struct tg3_hw_stats *sp = tp->hw_stats;
8353
8354 if (!netif_carrier_ok(tp->dev))
8355 return;
8356
8357 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8358 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8359 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8360 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8361 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8362 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8363 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8364 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8365 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8366 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8367 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8368 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8369 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8370
8371 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8372 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8373 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8374 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8375 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8376 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8377 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8378 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8379 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8380 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8381 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8382 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8383 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8384 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8385
8386 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8387 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8388 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8389}
8390
8391static void tg3_timer(unsigned long __opaque)
8392{
8393 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8394
f475f163
MC		 8395 if (tp->irq_sync)
8396 goto restart_timer;
8397
f47c11ee 8398 spin_lock(&tp->lock);
1da177e4 8399
fac9b83e
DM		 8400 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8401 /* All of this garbage is because when using non-tagged
8402 * IRQ status the mailbox/status_block protocol the chip
8403 * uses with the cpu is race prone.
8404 */
898a56f8 8405 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8406 tw32(GRC_LOCAL_CTRL,
8407 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8408 } else {
8409 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8410 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8411 }
1da177e4 8412
fac9b83e
DM		 8413 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8414 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8415 spin_unlock(&tp->lock);
fac9b83e
DM		 8416 schedule_work(&tp->reset_task);
8417 return;
8418 }
1da177e4
LT		 8419 }
8420
1da177e4
LT		 8421 /* This part only runs once per second. */
8422 if (!--tp->timer_counter) {
fac9b83e
DM		 8423 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8424 tg3_periodic_fetch_stats(tp);
8425
1da177e4
LT		 8426 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8427 u32 mac_stat;
8428 int phy_event;
8429
8430 mac_stat = tr32(MAC_STATUS);
8431
8432 phy_event = 0;
8433 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8434 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8435 phy_event = 1;
8436 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8437 phy_event = 1;
8438
8439 if (phy_event)
8440 tg3_setup_phy(tp, 0);
8441 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8442 u32 mac_stat = tr32(MAC_STATUS);
8443 int need_setup = 0;
8444
8445 if (netif_carrier_ok(tp->dev) &&
8446 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8447 need_setup = 1;
8448 }
8449 if (! netif_carrier_ok(tp->dev) &&
8450 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8451 MAC_STATUS_SIGNAL_DET))) {
8452 need_setup = 1;
8453 }
8454 if (need_setup) {
3d3ebe74
MC		 8455 if (!tp->serdes_counter) {
8456 tw32_f(MAC_MODE,
8457 (tp->mac_mode &
8458 ~MAC_MODE_PORT_MODE_MASK));
8459 udelay(40);
8460 tw32_f(MAC_MODE, tp->mac_mode);
8461 udelay(40);
8462 }
1da177e4
LT		 8463 tg3_setup_phy(tp, 0);
8464 }
747e8f8b
MC		 8465 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8466 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8467
8468 tp->timer_counter = tp->timer_multiplier;
8469 }
8470
130b8e4d
MC		 8471 /* Heartbeat is only sent once every 2 seconds.
8472 *
8473 * The heartbeat is to tell the ASF firmware that the host
8474 * driver is still alive. In the event that the OS crashes,
8475 * ASF needs to reset the hardware to free up the FIFO space
8476 * that may be filled with rx packets destined for the host.
8477 * If the FIFO is full, ASF will no longer function properly.
8478 *
8479 * Unintended resets have been reported on real time kernels
8480 * where the timer doesn't run on time. Netpoll will also have
8481 * same problem.
8482 *
8483 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8484 * to check the ring condition when the heartbeat is expiring
8485 * before doing the reset. This will prevent most unintended
8486 * resets.
8487 */
1da177e4 8488 if (!--tp->asf_counter) {
bc7959b2
MC		 8489 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8490 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8491 tg3_wait_for_event_ack(tp);
8492
bbadf503 8493 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8494 FWCMD_NICDRV_ALIVE3);
bbadf503 8495 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 8496 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8497 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 8498
8499 tg3_generate_fw_event(tp);
1da177e4
LT		 8500 }
8501 tp->asf_counter = tp->asf_multiplier;
8502 }
8503
f47c11ee 8504 spin_unlock(&tp->lock);
1da177e4 8505
f475f163 8506restart_timer:
1da177e4
LT		 8507 tp->timer.expires = jiffies + tp->timer_offset;
8508 add_timer(&tp->timer);
8509}
8510
4f125f42 8511static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8512{
7d12e780 8513 irq_handler_t fn;
fcfa0a32 8514 unsigned long flags;
4f125f42
MC		 8515 char *name;
8516 struct tg3_napi *tnapi = &tp->napi[irq_num];
8517
8518 if (tp->irq_cnt == 1)
8519 name = tp->dev->name;
8520 else {
8521 name = &tnapi->irq_lbl[0];
8522 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8523 name[IFNAMSIZ-1] = 0;
8524 }
fcfa0a32 8525
679563f4 8526 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8527 fn = tg3_msi;
8528 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8529 fn = tg3_msi_1shot;
1fb9df5d 8530 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8531 } else {
8532 fn = tg3_interrupt;
8533 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8534 fn = tg3_interrupt_tagged;
1fb9df5d 8535 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8536 }
4f125f42
MC		 8537
8538 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8539}
8540
7938109f
MC		 8541static int tg3_test_interrupt(struct tg3 *tp)
8542{
09943a18 8543 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8544 struct net_device *dev = tp->dev;
b16250e3 8545 int err, i, intr_ok = 0;
f6eb9b1f 8546 u32 val;
7938109f 8547
d4bc3927
MC		 8548 if (!netif_running(dev))
8549 return -ENODEV;
8550
7938109f
MC		 8551 tg3_disable_ints(tp);
8552
4f125f42 8553 free_irq(tnapi->irq_vec, tnapi);
7938109f 8554
f6eb9b1f
MC		 8555 /*
8556 * Turn off MSI one shot mode. Otherwise this test has no
8557 * observable way to know whether the interrupt was delivered.
8558 */
b703df6f
MC		 8559 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8560 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8561 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8562 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8563 tw32(MSGINT_MODE, val);
8564 }
8565
4f125f42 8566 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8567 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8568 if (err)
8569 return err;
8570
898a56f8 8571 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8572 tg3_enable_ints(tp);
8573
8574 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8575 tnapi->coal_now);
7938109f
MC		 8576
8577 for (i = 0; i < 5; i++) {
b16250e3
MC		 8578 u32 int_mbox, misc_host_ctrl;
8579
898a56f8 8580 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8581 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8582
8583 if ((int_mbox != 0) ||
8584 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8585 intr_ok = 1;
7938109f 8586 break;
b16250e3
MC		 8587 }
8588
7938109f
MC		 8589 msleep(10);
8590 }
8591
8592 tg3_disable_ints(tp);
8593
4f125f42 8594 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8595
4f125f42 8596 err = tg3_request_irq(tp, 0);
7938109f
MC		 8597
8598 if (err)
8599 return err;
8600
f6eb9b1f
MC		 8601 if (intr_ok) {
8602 /* Reenable MSI one shot mode. */
b703df6f
MC		 8603 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8604 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8605 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8606 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8607 tw32(MSGINT_MODE, val);
8608 }
7938109f 8609 return 0;
f6eb9b1f 8610 }
7938109f
MC		 8611
8612 return -EIO;
8613}
8614
8615/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8616 * successfully restored
8617 */
8618static int tg3_test_msi(struct tg3 *tp)
8619{
7938109f
MC		 8620 int err;
8621 u16 pci_cmd;
8622
8623 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8624 return 0;
8625
8626 /* Turn off SERR reporting in case MSI terminates with Master
8627 * Abort.
8628 */
8629 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8630 pci_write_config_word(tp->pdev, PCI_COMMAND,
8631 pci_cmd & ~PCI_COMMAND_SERR);
8632
8633 err = tg3_test_interrupt(tp);
8634
8635 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8636
8637 if (!err)
8638 return 0;
8639
8640 /* other failures */
8641 if (err != -EIO)
8642 return err;
8643
8644 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 8645 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8646 "to INTx mode. Please report this failure to the PCI "
8647 "maintainer and include system chipset information\n");
7938109f 8648
4f125f42 8649 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8650
7938109f
MC		 8651 pci_disable_msi(tp->pdev);
8652
8653 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8654
4f125f42 8655 err = tg3_request_irq(tp, 0);
7938109f
MC		 8656 if (err)
8657 return err;
8658
8659 /* Need to reset the chip because the MSI cycle may have terminated
8660 * with Master Abort.
8661 */
f47c11ee 8662 tg3_full_lock(tp, 1);
7938109f 8663
944d980e 8664 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8665 err = tg3_init_hw(tp, 1);
7938109f 8666
f47c11ee 8667 tg3_full_unlock(tp);
7938109f
MC		 8668
8669 if (err)
4f125f42 8670 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8671
8672 return err;
8673}
8674
9e9fd12d
MC		 8675static int tg3_request_firmware(struct tg3 *tp)
8676{
8677 const __be32 *fw_data;
8678
8679 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 8680 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8681 tp->fw_needed);
9e9fd12d
MC		 8682 return -ENOENT;
8683 }
8684
8685 fw_data = (void *)tp->fw->data;
8686
8687 /* Firmware blob starts with version numbers, followed by
8688 * start address and _full_ length including BSS sections
8689 * (which must be longer than the actual data, of course
8690 */
8691
8692 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8693 if (tp->fw_len < (tp->fw->size - 12)) {
05dbe005
JP		 8694 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8695 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 8696 release_firmware(tp->fw);
8697 tp->fw = NULL;
8698 return -EINVAL;
8699 }
8700
8701 /* We no longer need firmware; we have it. */
8702 tp->fw_needed = NULL;
8703 return 0;
8704}
8705
679563f4
MC		 8706static bool tg3_enable_msix(struct tg3 *tp)
8707{
8708 int i, rc, cpus = num_online_cpus();
8709 struct msix_entry msix_ent[tp->irq_max];
8710
8711 if (cpus == 1)
8712 /* Just fallback to the simpler MSI mode. */
8713 return false;
8714
8715 /*
8716 * We want as many rx rings enabled as there are cpus.
8717 * The first MSIX vector only deals with link interrupts, etc,
8718 * so we add one to the number of vectors we are requesting.
8719 */
8720 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8721
8722 for (i = 0; i < tp->irq_max; i++) {
8723 msix_ent[i].entry = i;
8724 msix_ent[i].vector = 0;
8725 }
8726
8727 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8728 if (rc != 0) {
8729 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8730 return false;
8731 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8732 return false;
05dbe005
JP		 8733 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8734 tp->irq_cnt, rc);
679563f4
MC		 8735 tp->irq_cnt = rc;
8736 }
8737
baf8a94a
MC		 8738 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8739
679563f4
MC		 8740 for (i = 0; i < tp->irq_max; i++)
8741 tp->napi[i].irq_vec = msix_ent[i].vector;
8742
19cfaecc
MC		 8743 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8744 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8745 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8746 } else
8747 tp->dev->real_num_tx_queues = 1;
fe5f5787 8748
679563f4
MC		 8749 return true;
8750}
8751
07b0173c
MC		 8752static void tg3_ints_init(struct tg3 *tp)
8753{
679563f4
MC		 8754 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8755 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8756 /* All MSI supporting chips should support tagged
8757 * status. Assert that this is the case.
8758 */
5129c3a3
MC		 8759 netdev_warn(tp->dev,
8760 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 8761 goto defcfg;
07b0173c 8762 }
4f125f42 8763
679563f4
MC		 8764 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8765 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8766 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8767 pci_enable_msi(tp->pdev) == 0)
8768 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8769
8770 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8771 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8772 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8773 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8774 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8775 }
8776defcfg:
8777 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8778 tp->irq_cnt = 1;
8779 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8780 tp->dev->real_num_tx_queues = 1;
679563f4 8781 }
07b0173c
MC		 8782}
8783
8784static void tg3_ints_fini(struct tg3 *tp)
8785{
679563f4
MC		 8786 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8787 pci_disable_msix(tp->pdev);
8788 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8789 pci_disable_msi(tp->pdev);
8790 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8791 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8792}
8793
1da177e4
LT		 8794static int tg3_open(struct net_device *dev)
8795{
8796 struct tg3 *tp = netdev_priv(dev);
4f125f42 8797 int i, err;
1da177e4 8798
9e9fd12d
MC		 8799 if (tp->fw_needed) {
8800 err = tg3_request_firmware(tp);
8801 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8802 if (err)
8803 return err;
8804 } else if (err) {
05dbe005 8805 netdev_warn(tp->dev, "TSO capability disabled\n");
9e9fd12d
MC		 8806 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8807 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
05dbe005 8808 netdev_notice(tp->dev, "TSO capability restored\n");
9e9fd12d
MC		 8809 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8810 }
8811 }
8812
c49a1561
MC		 8813 netif_carrier_off(tp->dev);
8814
bc1c7567 8815 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8816 if (err)
bc1c7567 8817 return err;
2f751b67
MC		 8818
8819 tg3_full_lock(tp, 0);
bc1c7567 8820
1da177e4
LT		 8821 tg3_disable_ints(tp);
8822 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8823
f47c11ee 8824 tg3_full_unlock(tp);
1da177e4 8825
679563f4
MC		 8826 /*
8827 * Setup interrupts first so we know how
8828 * many NAPI resources to allocate
8829 */
8830 tg3_ints_init(tp);
8831
1da177e4
LT		 8832 /* The placement of this call is tied
8833 * to the setup and use of Host TX descriptors.
8834 */
8835 err = tg3_alloc_consistent(tp);
8836 if (err)
679563f4 8837 goto err_out1;
88b06bc2 8838
fed97810 8839 tg3_napi_enable(tp);
1da177e4 8840
4f125f42
MC		 8841 for (i = 0; i < tp->irq_cnt; i++) {
8842 struct tg3_napi *tnapi = &tp->napi[i];
8843 err = tg3_request_irq(tp, i);
8844 if (err) {
8845 for (i--; i >= 0; i--)
8846 free_irq(tnapi->irq_vec, tnapi);
8847 break;
8848 }
8849 }
1da177e4 8850
07b0173c 8851 if (err)
679563f4 8852 goto err_out2;
bea3348e 8853
f47c11ee 8854 tg3_full_lock(tp, 0);
1da177e4 8855
8e7a22e3 8856 err = tg3_init_hw(tp, 1);
1da177e4 8857 if (err) {
944d980e 8858 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8859 tg3_free_rings(tp);
8860 } else {
fac9b83e
DM		 8861 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8862 tp->timer_offset = HZ;
8863 else
8864 tp->timer_offset = HZ / 10;
8865
8866 BUG_ON(tp->timer_offset > HZ);
8867 tp->timer_counter = tp->timer_multiplier =
8868 (HZ / tp->timer_offset);
8869 tp->asf_counter = tp->asf_multiplier =
28fbef78 8870 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8871
8872 init_timer(&tp->timer);
8873 tp->timer.expires = jiffies + tp->timer_offset;
8874 tp->timer.data = (unsigned long) tp;
8875 tp->timer.function = tg3_timer;
1da177e4
LT		 8876 }
8877
f47c11ee 8878 tg3_full_unlock(tp);
1da177e4 8879
07b0173c 8880 if (err)
679563f4 8881 goto err_out3;
1da177e4 8882
7938109f
MC		 8883 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8884 err = tg3_test_msi(tp);
fac9b83e 8885
7938109f 8886 if (err) {
f47c11ee 8887 tg3_full_lock(tp, 0);
944d980e 8888 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8889 tg3_free_rings(tp);
f47c11ee 8890 tg3_full_unlock(tp);
7938109f 8891
679563f4 8892 goto err_out2;
7938109f 8893 }
fcfa0a32 8894
f6eb9b1f 8895 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8896 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8897 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8898 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8899 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8900
f6eb9b1f
MC		 8901 tw32(PCIE_TRANSACTION_CFG,
8902 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8903 }
7938109f
MC		 8904 }
8905
b02fd9e3
MC		 8906 tg3_phy_start(tp);
8907
f47c11ee 8908 tg3_full_lock(tp, 0);
1da177e4 8909
7938109f
MC		 8910 add_timer(&tp->timer);
8911 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8912 tg3_enable_ints(tp);
8913
f47c11ee 8914 tg3_full_unlock(tp);
1da177e4 8915
fe5f5787 8916 netif_tx_start_all_queues(dev);
1da177e4
LT		 8917
8918 return 0;
07b0173c 8919
679563f4 8920err_out3:
4f125f42
MC		 8921 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8922 struct tg3_napi *tnapi = &tp->napi[i];
8923 free_irq(tnapi->irq_vec, tnapi);
8924 }
07b0173c 8925
679563f4 8926err_out2:
fed97810 8927 tg3_napi_disable(tp);
07b0173c 8928 tg3_free_consistent(tp);
679563f4
MC		 8929
8930err_out1:
8931 tg3_ints_fini(tp);
07b0173c 8932 return err;
1da177e4
LT		 8933}
8934
8935#if 0
8936/*static*/ void tg3_dump_state(struct tg3 *tp)
8937{
8938 u32 val32, val32_2, val32_3, val32_4, val32_5;
8939 u16 val16;
8940 int i;
898a56f8 8941 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8942
8943 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8944 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8945 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8946 val16, val32);
8947
8948 /* MAC block */
8949 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8950 tr32(MAC_MODE), tr32(MAC_STATUS));
8951 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8952 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8953 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8954 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8955 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8956 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8957
8958 /* Send data initiator control block */
8959 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8960 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8961 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8962 tr32(SNDDATAI_STATSCTRL));
8963
8964 /* Send data completion control block */
8965 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8966
8967 /* Send BD ring selector block */
8968 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8969 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8970
8971 /* Send BD initiator control block */
8972 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8973 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8974
8975 /* Send BD completion control block */
8976 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8977
8978 /* Receive list placement control block */
8979 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8980 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8981 printk(" RCVLPC_STATSCTRL[%08x]\n",
8982 tr32(RCVLPC_STATSCTRL));
8983
8984 /* Receive data and receive BD initiator control block */
8985 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8986 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8987
8988 /* Receive data completion control block */
8989 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8990 tr32(RCVDCC_MODE));
8991
8992 /* Receive BD initiator control block */
8993 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8994 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8995
8996 /* Receive BD completion control block */
8997 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8998 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8999
9000 /* Receive list selector control block */
9001 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
9002 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
9003
9004 /* Mbuf cluster free block */
9005 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
9006 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9007
9008 /* Host coalescing control block */
9009 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9010 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9011 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9012 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9013 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9014 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9015 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9016 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9017 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9018 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9019 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9020 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9021
9022 /* Memory arbiter control block */
9023 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9024 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9025
9026 /* Buffer manager control block */
9027 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9028 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9029 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9030 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9031 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9032 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9033 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9034 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9035
9036 /* Read DMA control block */
9037 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9038 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9039
9040 /* Write DMA control block */
9041 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9042 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9043
9044 /* DMA completion block */
9045 printk("DEBUG: DMAC_MODE[%08x]\n",
9046 tr32(DMAC_MODE));
9047
9048 /* GRC block */
9049 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9050 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9051 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9052 tr32(GRC_LOCAL_CTRL));
9053
9054 /* TG3_BDINFOs */
9055 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9056 tr32(RCVDBDI_JUMBO_BD + 0x0),
9057 tr32(RCVDBDI_JUMBO_BD + 0x4),
9058 tr32(RCVDBDI_JUMBO_BD + 0x8),
9059 tr32(RCVDBDI_JUMBO_BD + 0xc));
9060 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9061 tr32(RCVDBDI_STD_BD + 0x0),
9062 tr32(RCVDBDI_STD_BD + 0x4),
9063 tr32(RCVDBDI_STD_BD + 0x8),
9064 tr32(RCVDBDI_STD_BD + 0xc));
9065 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9066 tr32(RCVDBDI_MINI_BD + 0x0),
9067 tr32(RCVDBDI_MINI_BD + 0x4),
9068 tr32(RCVDBDI_MINI_BD + 0x8),
9069 tr32(RCVDBDI_MINI_BD + 0xc));
9070
9071 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9072 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9073 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9074 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9075 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9076 val32, val32_2, val32_3, val32_4);
9077
9078 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9079 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9080 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9081 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9082 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9083 val32, val32_2, val32_3, val32_4);
9084
9085 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9086 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9087 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9088 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9089 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9090 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9091 val32, val32_2, val32_3, val32_4, val32_5);
9092
9093 /* SW status block */
898a56f8
MC		 9094 printk(KERN_DEBUG
9095 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9096 sblk->status,
9097 sblk->status_tag,
9098 sblk->rx_jumbo_consumer,
9099 sblk->rx_consumer,
9100 sblk->rx_mini_consumer,
9101 sblk->idx[0].rx_producer,
9102 sblk->idx[0].tx_consumer);
1da177e4
LT		 9103
9104 /* SW statistics block */
9105 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9106 ((u32 *)tp->hw_stats)[0],
9107 ((u32 *)tp->hw_stats)[1],
9108 ((u32 *)tp->hw_stats)[2],
9109 ((u32 *)tp->hw_stats)[3]);
9110
9111 /* Mailboxes */
9112 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9113 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9114 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9115 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9116 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9117
9118 /* NIC side send descriptors. */
9119 for (i = 0; i < 6; i++) {
9120 unsigned long txd;
9121
9122 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9123 + (i * sizeof(struct tg3_tx_buffer_desc));
9124 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9125 i,
9126 readl(txd + 0x0), readl(txd + 0x4),
9127 readl(txd + 0x8), readl(txd + 0xc));
9128 }
9129
9130 /* NIC side RX descriptors. */
9131 for (i = 0; i < 6; i++) {
9132 unsigned long rxd;
9133
9134 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9135 + (i * sizeof(struct tg3_rx_buffer_desc));
9136 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9137 i,
9138 readl(rxd + 0x0), readl(rxd + 0x4),
9139 readl(rxd + 0x8), readl(rxd + 0xc));
9140 rxd += (4 * sizeof(u32));
9141 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9142 i,
9143 readl(rxd + 0x0), readl(rxd + 0x4),
9144 readl(rxd + 0x8), readl(rxd + 0xc));
9145 }
9146
9147 for (i = 0; i < 6; i++) {
9148 unsigned long rxd;
9149
9150 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9151 + (i * sizeof(struct tg3_rx_buffer_desc));
9152 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9153 i,
9154 readl(rxd + 0x0), readl(rxd + 0x4),
9155 readl(rxd + 0x8), readl(rxd + 0xc));
9156 rxd += (4 * sizeof(u32));
9157 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9158 i,
9159 readl(rxd + 0x0), readl(rxd + 0x4),
9160 readl(rxd + 0x8), readl(rxd + 0xc));
9161 }
9162}
9163#endif
9164
9165static struct net_device_stats *tg3_get_stats(struct net_device *);
9166static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9167
9168static int tg3_close(struct net_device *dev)
9169{
4f125f42 9170 int i;
1da177e4
LT		 9171 struct tg3 *tp = netdev_priv(dev);
9172
fed97810 9173 tg3_napi_disable(tp);
28e53bdd 9174 cancel_work_sync(&tp->reset_task);
7faa006f 9175
fe5f5787 9176 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9177
9178 del_timer_sync(&tp->timer);
9179
24bb4fb6
MC		 9180 tg3_phy_stop(tp);
9181
f47c11ee 9182 tg3_full_lock(tp, 1);
1da177e4
LT		 9183#if 0
9184 tg3_dump_state(tp);
9185#endif
9186
9187 tg3_disable_ints(tp);
9188
944d980e 9189 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9190 tg3_free_rings(tp);
5cf64b8a 9191 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9192
f47c11ee 9193 tg3_full_unlock(tp);
1da177e4 9194
4f125f42
MC		 9195 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9196 struct tg3_napi *tnapi = &tp->napi[i];
9197 free_irq(tnapi->irq_vec, tnapi);
9198 }
07b0173c
MC		 9199
9200 tg3_ints_fini(tp);
1da177e4
LT		 9201
9202 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9203 sizeof(tp->net_stats_prev));
9204 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9205 sizeof(tp->estats_prev));
9206
9207 tg3_free_consistent(tp);
9208
bc1c7567
MC		 9209 tg3_set_power_state(tp, PCI_D3hot);
9210
9211 netif_carrier_off(tp->dev);
9212
1da177e4
LT		 9213 return 0;
9214}
9215
9216static inline unsigned long get_stat64(tg3_stat64_t *val)
9217{
9218 unsigned long ret;
9219
9220#if (BITS_PER_LONG == 32)
9221 ret = val->low;
9222#else
9223 ret = ((u64)val->high << 32) | ((u64)val->low);
9224#endif
9225 return ret;
9226}
9227
816f8b86
SB		 9228static inline u64 get_estat64(tg3_stat64_t *val)
9229{
9230 return ((u64)val->high << 32) | ((u64)val->low);
9231}
9232
1da177e4
LT		 9233static unsigned long calc_crc_errors(struct tg3 *tp)
9234{
9235 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9236
9237 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9238 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9239 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9240 u32 val;
9241
f47c11ee 9242 spin_lock_bh(&tp->lock);
569a5df8
MC		 9243 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9244 tg3_writephy(tp, MII_TG3_TEST1,
9245 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9246 tg3_readphy(tp, 0x14, &val);
9247 } else
9248 val = 0;
f47c11ee 9249 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9250
9251 tp->phy_crc_errors += val;
9252
9253 return tp->phy_crc_errors;
9254 }
9255
9256 return get_stat64(&hw_stats->rx_fcs_errors);
9257}
9258
9259#define ESTAT_ADD(member) \
9260 estats->member = old_estats->member + \
816f8b86 9261 get_estat64(&hw_stats->member)
1da177e4
LT		 9262
9263static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9264{
9265 struct tg3_ethtool_stats *estats = &tp->estats;
9266 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9267 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9268
9269 if (!hw_stats)
9270 return old_estats;
9271
9272 ESTAT_ADD(rx_octets);
9273 ESTAT_ADD(rx_fragments);
9274 ESTAT_ADD(rx_ucast_packets);
9275 ESTAT_ADD(rx_mcast_packets);
9276 ESTAT_ADD(rx_bcast_packets);
9277 ESTAT_ADD(rx_fcs_errors);
9278 ESTAT_ADD(rx_align_errors);
9279 ESTAT_ADD(rx_xon_pause_rcvd);
9280 ESTAT_ADD(rx_xoff_pause_rcvd);
9281 ESTAT_ADD(rx_mac_ctrl_rcvd);
9282 ESTAT_ADD(rx_xoff_entered);
9283 ESTAT_ADD(rx_frame_too_long_errors);
9284 ESTAT_ADD(rx_jabbers);
9285 ESTAT_ADD(rx_undersize_packets);
9286 ESTAT_ADD(rx_in_length_errors);
9287 ESTAT_ADD(rx_out_length_errors);
9288 ESTAT_ADD(rx_64_or_less_octet_packets);
9289 ESTAT_ADD(rx_65_to_127_octet_packets);
9290 ESTAT_ADD(rx_128_to_255_octet_packets);
9291 ESTAT_ADD(rx_256_to_511_octet_packets);
9292 ESTAT_ADD(rx_512_to_1023_octet_packets);
9293 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9294 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9295 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9296 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9297 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9298
9299 ESTAT_ADD(tx_octets);
9300 ESTAT_ADD(tx_collisions);
9301 ESTAT_ADD(tx_xon_sent);
9302 ESTAT_ADD(tx_xoff_sent);
9303 ESTAT_ADD(tx_flow_control);
9304 ESTAT_ADD(tx_mac_errors);
9305 ESTAT_ADD(tx_single_collisions);
9306 ESTAT_ADD(tx_mult_collisions);
9307 ESTAT_ADD(tx_deferred);
9308 ESTAT_ADD(tx_excessive_collisions);
9309 ESTAT_ADD(tx_late_collisions);
9310 ESTAT_ADD(tx_collide_2times);
9311 ESTAT_ADD(tx_collide_3times);
9312 ESTAT_ADD(tx_collide_4times);
9313 ESTAT_ADD(tx_collide_5times);
9314 ESTAT_ADD(tx_collide_6times);
9315 ESTAT_ADD(tx_collide_7times);
9316 ESTAT_ADD(tx_collide_8times);
9317 ESTAT_ADD(tx_collide_9times);
9318 ESTAT_ADD(tx_collide_10times);
9319 ESTAT_ADD(tx_collide_11times);
9320 ESTAT_ADD(tx_collide_12times);
9321 ESTAT_ADD(tx_collide_13times);
9322 ESTAT_ADD(tx_collide_14times);
9323 ESTAT_ADD(tx_collide_15times);
9324 ESTAT_ADD(tx_ucast_packets);
9325 ESTAT_ADD(tx_mcast_packets);
9326 ESTAT_ADD(tx_bcast_packets);
9327 ESTAT_ADD(tx_carrier_sense_errors);
9328 ESTAT_ADD(tx_discards);
9329 ESTAT_ADD(tx_errors);
9330
9331 ESTAT_ADD(dma_writeq_full);
9332 ESTAT_ADD(dma_write_prioq_full);
9333 ESTAT_ADD(rxbds_empty);
9334 ESTAT_ADD(rx_discards);
9335 ESTAT_ADD(rx_errors);
9336 ESTAT_ADD(rx_threshold_hit);
9337
9338 ESTAT_ADD(dma_readq_full);
9339 ESTAT_ADD(dma_read_prioq_full);
9340 ESTAT_ADD(tx_comp_queue_full);
9341
9342 ESTAT_ADD(ring_set_send_prod_index);
9343 ESTAT_ADD(ring_status_update);
9344 ESTAT_ADD(nic_irqs);
9345 ESTAT_ADD(nic_avoided_irqs);
9346 ESTAT_ADD(nic_tx_threshold_hit);
9347
9348 return estats;
9349}
9350
9351static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9352{
9353 struct tg3 *tp = netdev_priv(dev);
9354 struct net_device_stats *stats = &tp->net_stats;
9355 struct net_device_stats *old_stats = &tp->net_stats_prev;
9356 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9357
9358 if (!hw_stats)
9359 return old_stats;
9360
9361 stats->rx_packets = old_stats->rx_packets +
9362 get_stat64(&hw_stats->rx_ucast_packets) +
9363 get_stat64(&hw_stats->rx_mcast_packets) +
9364 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9365
1da177e4
LT		 9366 stats->tx_packets = old_stats->tx_packets +
9367 get_stat64(&hw_stats->tx_ucast_packets) +
9368 get_stat64(&hw_stats->tx_mcast_packets) +
9369 get_stat64(&hw_stats->tx_bcast_packets);
9370
9371 stats->rx_bytes = old_stats->rx_bytes +
9372 get_stat64(&hw_stats->rx_octets);
9373 stats->tx_bytes = old_stats->tx_bytes +
9374 get_stat64(&hw_stats->tx_octets);
9375
9376 stats->rx_errors = old_stats->rx_errors +
4f63b877 9377 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9378 stats->tx_errors = old_stats->tx_errors +
9379 get_stat64(&hw_stats->tx_errors) +
9380 get_stat64(&hw_stats->tx_mac_errors) +
9381 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9382 get_stat64(&hw_stats->tx_discards);
9383
9384 stats->multicast = old_stats->multicast +
9385 get_stat64(&hw_stats->rx_mcast_packets);
9386 stats->collisions = old_stats->collisions +
9387 get_stat64(&hw_stats->tx_collisions);
9388
9389 stats->rx_length_errors = old_stats->rx_length_errors +
9390 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9391 get_stat64(&hw_stats->rx_undersize_packets);
9392
9393 stats->rx_over_errors = old_stats->rx_over_errors +
9394 get_stat64(&hw_stats->rxbds_empty);
9395 stats->rx_frame_errors = old_stats->rx_frame_errors +
9396 get_stat64(&hw_stats->rx_align_errors);
9397 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9398 get_stat64(&hw_stats->tx_discards);
9399 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9400 get_stat64(&hw_stats->tx_carrier_sense_errors);
9401
9402 stats->rx_crc_errors = old_stats->rx_crc_errors +
9403 calc_crc_errors(tp);
9404
4f63b877
JL		 9405 stats->rx_missed_errors = old_stats->rx_missed_errors +
9406 get_stat64(&hw_stats->rx_discards);
9407
1da177e4
LT		 9408 return stats;
9409}
9410
9411static inline u32 calc_crc(unsigned char *buf, int len)
9412{
9413 u32 reg;
9414 u32 tmp;
9415 int j, k;
9416
9417 reg = 0xffffffff;
9418
9419 for (j = 0; j < len; j++) {
9420 reg ^= buf[j];
9421
9422 for (k = 0; k < 8; k++) {
9423 tmp = reg & 0x01;
9424
9425 reg >>= 1;
9426
9427 if (tmp) {
9428 reg ^= 0xedb88320;
9429 }
9430 }
9431 }
9432
9433 return ~reg;
9434}
9435
9436static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9437{
9438 /* accept or reject all multicast frames */
9439 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9440 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9441 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9442 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9443}
9444
9445static void __tg3_set_rx_mode(struct net_device *dev)
9446{
9447 struct tg3 *tp = netdev_priv(dev);
9448 u32 rx_mode;
9449
9450 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9451 RX_MODE_KEEP_VLAN_TAG);
9452
9453 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9454 * flag clear.
9455 */
9456#if TG3_VLAN_TAG_USED
9457 if (!tp->vlgrp &&
9458 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9459 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9460#else
9461 /* By definition, VLAN is disabled always in this
9462 * case.
9463 */
9464 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9465 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9466#endif
9467
9468 if (dev->flags & IFF_PROMISC) {
9469 /* Promiscuous mode. */
9470 rx_mode |= RX_MODE_PROMISC;
9471 } else if (dev->flags & IFF_ALLMULTI) {
9472 /* Accept all multicast. */
9473 tg3_set_multi (tp, 1);
4cd24eaf 9474 } else if (netdev_mc_empty(dev)) {
1da177e4
LT		 9475 /* Reject all multicast. */
9476 tg3_set_multi (tp, 0);
9477 } else {
9478 /* Accept one or more multicast(s). */
22bedad3 9479 struct netdev_hw_addr *ha;
1da177e4
LT		 9480 u32 mc_filter[4] = { 0, };
9481 u32 regidx;
9482 u32 bit;
9483 u32 crc;
9484
22bedad3
JP		 9485 netdev_for_each_mc_addr(ha, dev) {
9486 crc = calc_crc(ha->addr, ETH_ALEN);
1da177e4
LT		 9487 bit = ~crc & 0x7f;
9488 regidx = (bit & 0x60) >> 5;
9489 bit &= 0x1f;
9490 mc_filter[regidx] |= (1 << bit);
9491 }
9492
9493 tw32(MAC_HASH_REG_0, mc_filter[0]);
9494 tw32(MAC_HASH_REG_1, mc_filter[1]);
9495 tw32(MAC_HASH_REG_2, mc_filter[2]);
9496 tw32(MAC_HASH_REG_3, mc_filter[3]);
9497 }
9498
9499 if (rx_mode != tp->rx_mode) {
9500 tp->rx_mode = rx_mode;
9501 tw32_f(MAC_RX_MODE, rx_mode);
9502 udelay(10);
9503 }
9504}
9505
9506static void tg3_set_rx_mode(struct net_device *dev)
9507{
9508 struct tg3 *tp = netdev_priv(dev);
9509
e75f7c90
MC		 9510 if (!netif_running(dev))
9511 return;
9512
f47c11ee 9513 tg3_full_lock(tp, 0);
1da177e4 9514 __tg3_set_rx_mode(dev);
f47c11ee 9515 tg3_full_unlock(tp);
1da177e4
LT		 9516}
9517
9518#define TG3_REGDUMP_LEN (32 * 1024)
9519
9520static int tg3_get_regs_len(struct net_device *dev)
9521{
9522 return TG3_REGDUMP_LEN;
9523}
9524
9525static void tg3_get_regs(struct net_device *dev,
9526 struct ethtool_regs *regs, void *_p)
9527{
9528 u32 *p = _p;
9529 struct tg3 *tp = netdev_priv(dev);
9530 u8 *orig_p = _p;
9531 int i;
9532
9533 regs->version = 0;
9534
9535 memset(p, 0, TG3_REGDUMP_LEN);
9536
bc1c7567
MC		 9537 if (tp->link_config.phy_is_low_power)
9538 return;
9539
f47c11ee 9540 tg3_full_lock(tp, 0);
1da177e4
LT		 9541
9542#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9543#define GET_REG32_LOOP(base,len) \
9544do { p = (u32 *)(orig_p + (base)); \
9545 for (i = 0; i < len; i += 4) \
9546 __GET_REG32((base) + i); \
9547} while (0)
9548#define GET_REG32_1(reg) \
9549do { p = (u32 *)(orig_p + (reg)); \
9550 __GET_REG32((reg)); \
9551} while (0)
9552
9553 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9554 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9555 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9556 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9557 GET_REG32_1(SNDDATAC_MODE);
9558 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9559 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9560 GET_REG32_1(SNDBDC_MODE);
9561 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9562 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9563 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9564 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9565 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9566 GET_REG32_1(RCVDCC_MODE);
9567 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9568 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9569 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9570 GET_REG32_1(MBFREE_MODE);
9571 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9572 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9573 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9574 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9575 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9576 GET_REG32_1(RX_CPU_MODE);
9577 GET_REG32_1(RX_CPU_STATE);
9578 GET_REG32_1(RX_CPU_PGMCTR);
9579 GET_REG32_1(RX_CPU_HWBKPT);
9580 GET_REG32_1(TX_CPU_MODE);
9581 GET_REG32_1(TX_CPU_STATE);
9582 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9583 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9584 GET_REG32_LOOP(FTQ_RESET, 0x120);
9585 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9586 GET_REG32_1(DMAC_MODE);
9587 GET_REG32_LOOP(GRC_MODE, 0x4c);
9588 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9589 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9590
9591#undef __GET_REG32
9592#undef GET_REG32_LOOP
9593#undef GET_REG32_1
9594
f47c11ee 9595 tg3_full_unlock(tp);
1da177e4
LT		 9596}
9597
9598static int tg3_get_eeprom_len(struct net_device *dev)
9599{
9600 struct tg3 *tp = netdev_priv(dev);
9601
9602 return tp->nvram_size;
9603}
9604
1da177e4
LT		 9605static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9606{
9607 struct tg3 *tp = netdev_priv(dev);
9608 int ret;
9609 u8 *pd;
b9fc7dc5 9610 u32 i, offset, len, b_offset, b_count;
a9dc529d 9611 __be32 val;
1da177e4 9612
df259d8c
MC		 9613 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9614 return -EINVAL;
9615
bc1c7567
MC		 9616 if (tp->link_config.phy_is_low_power)
9617 return -EAGAIN;
9618
1da177e4
LT		 9619 offset = eeprom->offset;
9620 len = eeprom->len;
9621 eeprom->len = 0;
9622
9623 eeprom->magic = TG3_EEPROM_MAGIC;
9624
9625 if (offset & 3) {
9626 /* adjustments to start on required 4 byte boundary */
9627 b_offset = offset & 3;
9628 b_count = 4 - b_offset;
9629 if (b_count > len) {
9630 /* i.e. offset=1 len=2 */
9631 b_count = len;
9632 }
a9dc529d 9633 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9634 if (ret)
9635 return ret;
1da177e4
LT		 9636 memcpy(data, ((char*)&val) + b_offset, b_count);
9637 len -= b_count;
9638 offset += b_count;
c6cdf436 9639 eeprom->len += b_count;
1da177e4
LT		 9640 }
9641
9642 /* read bytes upto the last 4 byte boundary */
9643 pd = &data[eeprom->len];
9644 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9645 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9646 if (ret) {
9647 eeprom->len += i;
9648 return ret;
9649 }
1da177e4
LT		 9650 memcpy(pd + i, &val, 4);
9651 }
9652 eeprom->len += i;
9653
9654 if (len & 3) {
9655 /* read last bytes not ending on 4 byte boundary */
9656 pd = &data[eeprom->len];
9657 b_count = len & 3;
9658 b_offset = offset + len - b_count;
a9dc529d 9659 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9660 if (ret)
9661 return ret;
b9fc7dc5 9662 memcpy(pd, &val, b_count);
1da177e4
LT		 9663 eeprom->len += b_count;
9664 }
9665 return 0;
9666}
9667
6aa20a22 9668static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9669
9670static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9671{
9672 struct tg3 *tp = netdev_priv(dev);
9673 int ret;
b9fc7dc5 9674 u32 offset, len, b_offset, odd_len;
1da177e4 9675 u8 *buf;
a9dc529d 9676 __be32 start, end;
1da177e4 9677
bc1c7567
MC		 9678 if (tp->link_config.phy_is_low_power)
9679 return -EAGAIN;
9680
df259d8c
MC		 9681 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9682 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9683 return -EINVAL;
9684
9685 offset = eeprom->offset;
9686 len = eeprom->len;
9687
9688 if ((b_offset = (offset & 3))) {
9689 /* adjustments to start on required 4 byte boundary */
a9dc529d 9690 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9691 if (ret)
9692 return ret;
1da177e4
LT		 9693 len += b_offset;
9694 offset &= ~3;
1c8594b4
MC		 9695 if (len < 4)
9696 len = 4;
1da177e4
LT		 9697 }
9698
9699 odd_len = 0;
1c8594b4 9700 if (len & 3) {
1da177e4
LT		 9701 /* adjustments to end on required 4 byte boundary */
9702 odd_len = 1;
9703 len = (len + 3) & ~3;
a9dc529d 9704 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9705 if (ret)
9706 return ret;
1da177e4
LT		 9707 }
9708
9709 buf = data;
9710 if (b_offset || odd_len) {
9711 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9712 if (!buf)
1da177e4
LT		 9713 return -ENOMEM;
9714 if (b_offset)
9715 memcpy(buf, &start, 4);
9716 if (odd_len)
9717 memcpy(buf+len-4, &end, 4);
9718 memcpy(buf + b_offset, data, eeprom->len);
9719 }
9720
9721 ret = tg3_nvram_write_block(tp, offset, len, buf);
9722
9723 if (buf != data)
9724 kfree(buf);
9725
9726 return ret;
9727}
9728
9729static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9730{
b02fd9e3
MC		 9731 struct tg3 *tp = netdev_priv(dev);
9732
9733 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9734 struct phy_device *phydev;
b02fd9e3
MC		 9735 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9736 return -EAGAIN;
3f0e3ad7
MC		 9737 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9738 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9739 }
6aa20a22 9740
1da177e4
LT		 9741 cmd->supported = (SUPPORTED_Autoneg);
9742
9743 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9744 cmd->supported |= (SUPPORTED_1000baseT_Half |
9745 SUPPORTED_1000baseT_Full);
9746
ef348144 9747 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9748 cmd->supported |= (SUPPORTED_100baseT_Half |
9749 SUPPORTED_100baseT_Full |
9750 SUPPORTED_10baseT_Half |
9751 SUPPORTED_10baseT_Full |
3bebab59 9752 SUPPORTED_TP);
ef348144
KK		 9753 cmd->port = PORT_TP;
9754 } else {
1da177e4 9755 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9756 cmd->port = PORT_FIBRE;
9757 }
6aa20a22 9758
1da177e4
LT		 9759 cmd->advertising = tp->link_config.advertising;
9760 if (netif_running(dev)) {
9761 cmd->speed = tp->link_config.active_speed;
9762 cmd->duplex = tp->link_config.active_duplex;
9763 }
882e9793 9764 cmd->phy_address = tp->phy_addr;
7e5856bd 9765 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9766 cmd->autoneg = tp->link_config.autoneg;
9767 cmd->maxtxpkt = 0;
9768 cmd->maxrxpkt = 0;
9769 return 0;
9770}
6aa20a22 9771
1da177e4
LT		 9772static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9773{
9774 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9775
b02fd9e3 9776 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9777 struct phy_device *phydev;
b02fd9e3
MC		 9778 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9779 return -EAGAIN;
3f0e3ad7
MC		 9780 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9781 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9782 }
9783
7e5856bd
MC		 9784 if (cmd->autoneg != AUTONEG_ENABLE &&
9785 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9786 return -EINVAL;
7e5856bd
MC		 9787
9788 if (cmd->autoneg == AUTONEG_DISABLE &&
9789 cmd->duplex != DUPLEX_FULL &&
9790 cmd->duplex != DUPLEX_HALF)
37ff238d 9791 return -EINVAL;
1da177e4 9792
7e5856bd
MC		 9793 if (cmd->autoneg == AUTONEG_ENABLE) {
9794 u32 mask = ADVERTISED_Autoneg |
9795 ADVERTISED_Pause |
9796 ADVERTISED_Asym_Pause;
9797
3f07d129 9798 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7e5856bd
MC		 9799 mask |= ADVERTISED_1000baseT_Half |
9800 ADVERTISED_1000baseT_Full;
9801
9802 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9803 mask |= ADVERTISED_100baseT_Half |
9804 ADVERTISED_100baseT_Full |
9805 ADVERTISED_10baseT_Half |
9806 ADVERTISED_10baseT_Full |
9807 ADVERTISED_TP;
9808 else
9809 mask |= ADVERTISED_FIBRE;
9810
9811 if (cmd->advertising & ~mask)
9812 return -EINVAL;
9813
9814 mask &= (ADVERTISED_1000baseT_Half |
9815 ADVERTISED_1000baseT_Full |
9816 ADVERTISED_100baseT_Half |
9817 ADVERTISED_100baseT_Full |
9818 ADVERTISED_10baseT_Half |
9819 ADVERTISED_10baseT_Full);
9820
9821 cmd->advertising &= mask;
9822 } else {
9823 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9824 if (cmd->speed != SPEED_1000)
9825 return -EINVAL;
9826
9827 if (cmd->duplex != DUPLEX_FULL)
9828 return -EINVAL;
9829 } else {
9830 if (cmd->speed != SPEED_100 &&
9831 cmd->speed != SPEED_10)
9832 return -EINVAL;
9833 }
9834 }
9835
f47c11ee 9836 tg3_full_lock(tp, 0);
1da177e4
LT		 9837
9838 tp->link_config.autoneg = cmd->autoneg;
9839 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9840 tp->link_config.advertising = (cmd->advertising |
9841 ADVERTISED_Autoneg);
1da177e4
LT		 9842 tp->link_config.speed = SPEED_INVALID;
9843 tp->link_config.duplex = DUPLEX_INVALID;
9844 } else {
9845 tp->link_config.advertising = 0;
9846 tp->link_config.speed = cmd->speed;
9847 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9848 }
6aa20a22 9849
24fcad6b
MC		 9850 tp->link_config.orig_speed = tp->link_config.speed;
9851 tp->link_config.orig_duplex = tp->link_config.duplex;
9852 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9853
1da177e4
LT		 9854 if (netif_running(dev))
9855 tg3_setup_phy(tp, 1);
9856
f47c11ee 9857 tg3_full_unlock(tp);
6aa20a22 9858
1da177e4
LT		 9859 return 0;
9860}
6aa20a22 9861
1da177e4
LT		 9862static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9863{
9864 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9865
1da177e4
LT		 9866 strcpy(info->driver, DRV_MODULE_NAME);
9867 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9868 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9869 strcpy(info->bus_info, pci_name(tp->pdev));
9870}
6aa20a22 9871
1da177e4
LT		 9872static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9873{
9874 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9875
12dac075
RW		 9876 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9877 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9878 wol->supported = WAKE_MAGIC;
9879 else
9880 wol->supported = 0;
1da177e4 9881 wol->wolopts = 0;
05ac4cb7
MC		 9882 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9883 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9884 wol->wolopts = WAKE_MAGIC;
9885 memset(&wol->sopass, 0, sizeof(wol->sopass));
9886}
6aa20a22 9887
1da177e4
LT		 9888static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9889{
9890 struct tg3 *tp = netdev_priv(dev);
12dac075 9891 struct device *dp = &tp->pdev->dev;
6aa20a22 9892
1da177e4
LT		 9893 if (wol->wolopts & ~WAKE_MAGIC)
9894 return -EINVAL;
9895 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9896 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9897 return -EINVAL;
6aa20a22 9898
f47c11ee 9899 spin_lock_bh(&tp->lock);
12dac075 9900 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9901 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9902 device_set_wakeup_enable(dp, true);
9903 } else {
1da177e4 9904 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9905 device_set_wakeup_enable(dp, false);
9906 }
f47c11ee 9907 spin_unlock_bh(&tp->lock);
6aa20a22 9908
1da177e4
LT		 9909 return 0;
9910}
6aa20a22 9911
1da177e4
LT		 9912static u32 tg3_get_msglevel(struct net_device *dev)
9913{
9914 struct tg3 *tp = netdev_priv(dev);
9915 return tp->msg_enable;
9916}
6aa20a22 9917
1da177e4
LT		 9918static void tg3_set_msglevel(struct net_device *dev, u32 value)
9919{
9920 struct tg3 *tp = netdev_priv(dev);
9921 tp->msg_enable = value;
9922}
6aa20a22 9923
1da177e4
LT		 9924static int tg3_set_tso(struct net_device *dev, u32 value)
9925{
9926 struct tg3 *tp = netdev_priv(dev);
9927
9928 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9929 if (value)
9930 return -EINVAL;
9931 return 0;
9932 }
027455ad 9933 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9934 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9935 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9936 if (value) {
b0026624 9937 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9938 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9940 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9941 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9944 dev->features |= NETIF_F_TSO_ECN;
9945 } else
9946 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9947 }
1da177e4
LT		 9948 return ethtool_op_set_tso(dev, value);
9949}
6aa20a22 9950
1da177e4
LT		 9951static int tg3_nway_reset(struct net_device *dev)
9952{
9953 struct tg3 *tp = netdev_priv(dev);
1da177e4 9954 int r;
6aa20a22 9955
1da177e4
LT		 9956 if (!netif_running(dev))
9957 return -EAGAIN;
9958
c94e3941
MC		 9959 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9960 return -EINVAL;
9961
b02fd9e3
MC		 9962 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9963 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9964 return -EAGAIN;
3f0e3ad7 9965 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9966 } else {
9967 u32 bmcr;
9968
9969 spin_lock_bh(&tp->lock);
9970 r = -EINVAL;
9971 tg3_readphy(tp, MII_BMCR, &bmcr);
9972 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9973 ((bmcr & BMCR_ANENABLE) ||
9974 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9975 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9976 BMCR_ANENABLE);
9977 r = 0;
9978 }
9979 spin_unlock_bh(&tp->lock);
1da177e4 9980 }
6aa20a22 9981
1da177e4
LT		 9982 return r;
9983}
6aa20a22 9984
1da177e4
LT		 9985static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9986{
9987 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9988
1da177e4
LT		 9989 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9990 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9991 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9992 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9993 else
9994 ering->rx_jumbo_max_pending = 0;
9995
9996 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9997
9998 ering->rx_pending = tp->rx_pending;
9999 ering->rx_mini_pending = 0;
4f81c32b
MC		 10000 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10001 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10002 else
10003 ering->rx_jumbo_pending = 0;
10004
f3f3f27e 10005 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 10006}
6aa20a22 10007
1da177e4
LT		 10008static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10009{
10010 struct tg3 *tp = netdev_priv(dev);
646c9edd 10011 int i, irq_sync = 0, err = 0;
6aa20a22 10012
1da177e4
LT		 10013 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10014 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 10015 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10016 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 10017 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 10018 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 10019 return -EINVAL;
6aa20a22 10020
bbe832c0 10021 if (netif_running(dev)) {
b02fd9e3 10022 tg3_phy_stop(tp);
1da177e4 10023 tg3_netif_stop(tp);
bbe832c0
MC		 10024 irq_sync = 1;
10025 }
1da177e4 10026
bbe832c0 10027 tg3_full_lock(tp, irq_sync);
6aa20a22 10028
1da177e4
LT		 10029 tp->rx_pending = ering->rx_pending;
10030
10031 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10032 tp->rx_pending > 63)
10033 tp->rx_pending = 63;
10034 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 10035
10036 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10037 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 10038
10039 if (netif_running(dev)) {
944d980e 10040 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 10041 err = tg3_restart_hw(tp, 1);
10042 if (!err)
10043 tg3_netif_start(tp);
1da177e4
LT		 10044 }
10045
f47c11ee 10046 tg3_full_unlock(tp);
6aa20a22 10047
b02fd9e3
MC		 10048 if (irq_sync && !err)
10049 tg3_phy_start(tp);
10050
b9ec6c1b 10051 return err;
1da177e4 10052}
6aa20a22 10053
1da177e4
LT		 10054static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10055{
10056 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10057
1da177e4 10058 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 10059
e18ce346 10060 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 10061 epause->rx_pause = 1;
10062 else
10063 epause->rx_pause = 0;
10064
e18ce346 10065 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 10066 epause->tx_pause = 1;
10067 else
10068 epause->tx_pause = 0;
1da177e4 10069}
6aa20a22 10070
1da177e4
LT		 10071static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10072{
10073 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 10074 int err = 0;
6aa20a22 10075
b02fd9e3 10076 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2712168f
MC		 10077 u32 newadv;
10078 struct phy_device *phydev;
1da177e4 10079
2712168f 10080 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 10081
2712168f
MC		 10082 if (!(phydev->supported & SUPPORTED_Pause) ||
10083 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10084 ((epause->rx_pause && !epause->tx_pause) ||
10085 (!epause->rx_pause && epause->tx_pause))))
10086 return -EINVAL;
1da177e4 10087
2712168f
MC		 10088 tp->link_config.flowctrl = 0;
10089 if (epause->rx_pause) {
10090 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10091
10092 if (epause->tx_pause) {
10093 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10094 newadv = ADVERTISED_Pause;
b02fd9e3 10095 } else
2712168f
MC		 10096 newadv = ADVERTISED_Pause |
10097 ADVERTISED_Asym_Pause;
10098 } else if (epause->tx_pause) {
10099 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10100 newadv = ADVERTISED_Asym_Pause;
10101 } else
10102 newadv = 0;
10103
10104 if (epause->autoneg)
10105 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10106 else
10107 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10108
10109 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10110 u32 oldadv = phydev->advertising &
10111 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10112 if (oldadv != newadv) {
10113 phydev->advertising &=
10114 ~(ADVERTISED_Pause |
10115 ADVERTISED_Asym_Pause);
10116 phydev->advertising |= newadv;
10117 if (phydev->autoneg) {
10118 /*
10119 * Always renegotiate the link to
10120 * inform our link partner of our
10121 * flow control settings, even if the
10122 * flow control is forced. Let
10123 * tg3_adjust_link() do the final
10124 * flow control setup.
10125 */
10126 return phy_start_aneg(phydev);
b02fd9e3 10127 }
b02fd9e3 10128 }
b02fd9e3 10129
2712168f 10130 if (!epause->autoneg)
b02fd9e3 10131 tg3_setup_flow_control(tp, 0, 0);
2712168f
MC		 10132 } else {
10133 tp->link_config.orig_advertising &=
10134 ~(ADVERTISED_Pause |
10135 ADVERTISED_Asym_Pause);
10136 tp->link_config.orig_advertising |= newadv;
b02fd9e3
MC		 10137 }
10138 } else {
10139 int irq_sync = 0;
10140
10141 if (netif_running(dev)) {
10142 tg3_netif_stop(tp);
10143 irq_sync = 1;
10144 }
10145
10146 tg3_full_lock(tp, irq_sync);
10147
10148 if (epause->autoneg)
10149 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10150 else
10151 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10152 if (epause->rx_pause)
e18ce346 10153 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10154 else
e18ce346 10155 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10156 if (epause->tx_pause)
e18ce346 10157 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10158 else
e18ce346 10159 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10160
10161 if (netif_running(dev)) {
10162 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10163 err = tg3_restart_hw(tp, 1);
10164 if (!err)
10165 tg3_netif_start(tp);
10166 }
10167
10168 tg3_full_unlock(tp);
10169 }
6aa20a22 10170
b9ec6c1b 10171 return err;
1da177e4 10172}
6aa20a22 10173
1da177e4
LT		 10174static u32 tg3_get_rx_csum(struct net_device *dev)
10175{
10176 struct tg3 *tp = netdev_priv(dev);
10177 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10178}
6aa20a22 10179
1da177e4
LT		 10180static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10181{
10182 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10183
1da177e4
LT		 10184 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10185 if (data != 0)
10186 return -EINVAL;
c6cdf436
MC		 10187 return 0;
10188 }
6aa20a22 10189
f47c11ee 10190 spin_lock_bh(&tp->lock);
1da177e4
LT		 10191 if (data)
10192 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10193 else
10194 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10195 spin_unlock_bh(&tp->lock);
6aa20a22 10196
1da177e4
LT		 10197 return 0;
10198}
6aa20a22 10199
1da177e4
LT		 10200static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10201{
10202 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10203
1da177e4
LT		 10204 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10205 if (data != 0)
10206 return -EINVAL;
c6cdf436
MC		 10207 return 0;
10208 }
6aa20a22 10209
321d32a0 10210 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10211 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10212 else
9c27dbdf 10213 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10214
10215 return 0;
10216}
10217
b9f2c044 10218static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10219{
b9f2c044
JG		 10220 switch (sset) {
10221 case ETH_SS_TEST:
10222 return TG3_NUM_TEST;
10223 case ETH_SS_STATS:
10224 return TG3_NUM_STATS;
10225 default:
10226 return -EOPNOTSUPP;
10227 }
4cafd3f5
MC		 10228}
10229
1da177e4
LT		 10230static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10231{
10232 switch (stringset) {
10233 case ETH_SS_STATS:
10234 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10235 break;
4cafd3f5
MC		 10236 case ETH_SS_TEST:
10237 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10238 break;
1da177e4
LT		 10239 default:
10240 WARN_ON(1); /* we need a WARN() */
10241 break;
10242 }
10243}
10244
4009a93d
MC		 10245static int tg3_phys_id(struct net_device *dev, u32 data)
10246{
10247 struct tg3 *tp = netdev_priv(dev);
10248 int i;
10249
10250 if (!netif_running(tp->dev))
10251 return -EAGAIN;
10252
10253 if (data == 0)
759afc31 10254 data = UINT_MAX / 2;
4009a93d
MC		 10255
10256 for (i = 0; i < (data * 2); i++) {
10257 if ((i % 2) == 0)
10258 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10259 LED_CTRL_1000MBPS_ON |
10260 LED_CTRL_100MBPS_ON |
10261 LED_CTRL_10MBPS_ON |
10262 LED_CTRL_TRAFFIC_OVERRIDE |
10263 LED_CTRL_TRAFFIC_BLINK |
10264 LED_CTRL_TRAFFIC_LED);
6aa20a22 10265
4009a93d
MC		 10266 else
10267 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10268 LED_CTRL_TRAFFIC_OVERRIDE);
10269
10270 if (msleep_interruptible(500))
10271 break;
10272 }
10273 tw32(MAC_LED_CTRL, tp->led_ctrl);
10274 return 0;
10275}
10276
1da177e4
LT		 10277static void tg3_get_ethtool_stats (struct net_device *dev,
10278 struct ethtool_stats *estats, u64 *tmp_stats)
10279{
10280 struct tg3 *tp = netdev_priv(dev);
10281 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10282}
10283
566f86ad 10284#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10285#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10286#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10287#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10288#define NVRAM_SELFBOOT_HW_SIZE 0x20
10289#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10290
10291static int tg3_test_nvram(struct tg3 *tp)
10292{
b9fc7dc5 10293 u32 csum, magic;
a9dc529d 10294 __be32 *buf;
ab0049b4 10295 int i, j, k, err = 0, size;
566f86ad 10296
df259d8c
MC		 10297 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10298 return 0;
10299
e4f34110 10300 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10301 return -EIO;
10302
1b27777a
MC		 10303 if (magic == TG3_EEPROM_MAGIC)
10304 size = NVRAM_TEST_SIZE;
b16250e3 10305 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10306 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10307 TG3_EEPROM_SB_FORMAT_1) {
10308 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10309 case TG3_EEPROM_SB_REVISION_0:
10310 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10311 break;
10312 case TG3_EEPROM_SB_REVISION_2:
10313 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10314 break;
10315 case TG3_EEPROM_SB_REVISION_3:
10316 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10317 break;
10318 default:
10319 return 0;
10320 }
10321 } else
1b27777a 10322 return 0;
b16250e3
MC		 10323 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10324 size = NVRAM_SELFBOOT_HW_SIZE;
10325 else
1b27777a
MC		 10326 return -EIO;
10327
10328 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10329 if (buf == NULL)
10330 return -ENOMEM;
10331
1b27777a
MC		 10332 err = -EIO;
10333 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10334 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10335 if (err)
566f86ad 10336 break;
566f86ad 10337 }
1b27777a 10338 if (i < size)
566f86ad
MC		 10339 goto out;
10340
1b27777a 10341 /* Selfboot format */
a9dc529d 10342 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10343 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10344 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10345 u8 *buf8 = (u8 *) buf, csum8 = 0;
10346
b9fc7dc5 10347 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10348 TG3_EEPROM_SB_REVISION_2) {
10349 /* For rev 2, the csum doesn't include the MBA. */
10350 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10351 csum8 += buf8[i];
10352 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10353 csum8 += buf8[i];
10354 } else {
10355 for (i = 0; i < size; i++)
10356 csum8 += buf8[i];
10357 }
1b27777a 10358
ad96b485
AB		 10359 if (csum8 == 0) {
10360 err = 0;
10361 goto out;
10362 }
10363
10364 err = -EIO;
10365 goto out;
1b27777a 10366 }
566f86ad 10367
b9fc7dc5 10368 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10369 TG3_EEPROM_MAGIC_HW) {
10370 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10371 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10372 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10373
10374 /* Separate the parity bits and the data bytes. */
10375 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10376 if ((i == 0) || (i == 8)) {
10377 int l;
10378 u8 msk;
10379
10380 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10381 parity[k++] = buf8[i] & msk;
10382 i++;
10383 }
10384 else if (i == 16) {
10385 int l;
10386 u8 msk;
10387
10388 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10389 parity[k++] = buf8[i] & msk;
10390 i++;
10391
10392 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10393 parity[k++] = buf8[i] & msk;
10394 i++;
10395 }
10396 data[j++] = buf8[i];
10397 }
10398
10399 err = -EIO;
10400 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10401 u8 hw8 = hweight8(data[i]);
10402
10403 if ((hw8 & 0x1) && parity[i])
10404 goto out;
10405 else if (!(hw8 & 0x1) && !parity[i])
10406 goto out;
10407 }
10408 err = 0;
10409 goto out;
10410 }
10411
566f86ad
MC		 10412 /* Bootstrap checksum at offset 0x10 */
10413 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10414 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10415 goto out;
10416
10417 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10418 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10419 if (csum != be32_to_cpu(buf[0xfc/4]))
10420 goto out;
566f86ad
MC		 10421
10422 err = 0;
10423
10424out:
10425 kfree(buf);
10426 return err;
10427}
10428
ca43007a
MC		 10429#define TG3_SERDES_TIMEOUT_SEC 2
10430#define TG3_COPPER_TIMEOUT_SEC 6
10431
10432static int tg3_test_link(struct tg3 *tp)
10433{
10434 int i, max;
10435
10436 if (!netif_running(tp->dev))
10437 return -ENODEV;
10438
4c987487 10439 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10440 max = TG3_SERDES_TIMEOUT_SEC;
10441 else
10442 max = TG3_COPPER_TIMEOUT_SEC;
10443
10444 for (i = 0; i < max; i++) {
10445 if (netif_carrier_ok(tp->dev))
10446 return 0;
10447
10448 if (msleep_interruptible(1000))
10449 break;
10450 }
10451
10452 return -EIO;
10453}
10454
a71116d1 10455/* Only test the commonly used registers */
30ca3e37 10456static int tg3_test_registers(struct tg3 *tp)
a71116d1 10457{
b16250e3 10458 int i, is_5705, is_5750;
a71116d1
MC		 10459 u32 offset, read_mask, write_mask, val, save_val, read_val;
10460 static struct {
10461 u16 offset;
10462 u16 flags;
10463#define TG3_FL_5705 0x1
10464#define TG3_FL_NOT_5705 0x2
10465#define TG3_FL_NOT_5788 0x4
b16250e3 10466#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10467 u32 read_mask;
10468 u32 write_mask;
10469 } reg_tbl[] = {
10470 /* MAC Control Registers */
10471 { MAC_MODE, TG3_FL_NOT_5705,
10472 0x00000000, 0x00ef6f8c },
10473 { MAC_MODE, TG3_FL_5705,
10474 0x00000000, 0x01ef6b8c },
10475 { MAC_STATUS, TG3_FL_NOT_5705,
10476 0x03800107, 0x00000000 },
10477 { MAC_STATUS, TG3_FL_5705,
10478 0x03800100, 0x00000000 },
10479 { MAC_ADDR_0_HIGH, 0x0000,
10480 0x00000000, 0x0000ffff },
10481 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 10482 0x00000000, 0xffffffff },
a71116d1
MC		 10483 { MAC_RX_MTU_SIZE, 0x0000,
10484 0x00000000, 0x0000ffff },
10485 { MAC_TX_MODE, 0x0000,
10486 0x00000000, 0x00000070 },
10487 { MAC_TX_LENGTHS, 0x0000,
10488 0x00000000, 0x00003fff },
10489 { MAC_RX_MODE, TG3_FL_NOT_5705,
10490 0x00000000, 0x000007fc },
10491 { MAC_RX_MODE, TG3_FL_5705,
10492 0x00000000, 0x000007dc },
10493 { MAC_HASH_REG_0, 0x0000,
10494 0x00000000, 0xffffffff },
10495 { MAC_HASH_REG_1, 0x0000,
10496 0x00000000, 0xffffffff },
10497 { MAC_HASH_REG_2, 0x0000,
10498 0x00000000, 0xffffffff },
10499 { MAC_HASH_REG_3, 0x0000,
10500 0x00000000, 0xffffffff },
10501
10502 /* Receive Data and Receive BD Initiator Control Registers. */
10503 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10504 0x00000000, 0xffffffff },
10505 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10506 0x00000000, 0xffffffff },
10507 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10508 0x00000000, 0x00000003 },
10509 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10510 0x00000000, 0xffffffff },
10511 { RCVDBDI_STD_BD+0, 0x0000,
10512 0x00000000, 0xffffffff },
10513 { RCVDBDI_STD_BD+4, 0x0000,
10514 0x00000000, 0xffffffff },
10515 { RCVDBDI_STD_BD+8, 0x0000,
10516 0x00000000, 0xffff0002 },
10517 { RCVDBDI_STD_BD+0xc, 0x0000,
10518 0x00000000, 0xffffffff },
6aa20a22 10519
a71116d1
MC		 10520 /* Receive BD Initiator Control Registers. */
10521 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10522 0x00000000, 0xffffffff },
10523 { RCVBDI_STD_THRESH, TG3_FL_5705,
10524 0x00000000, 0x000003ff },
10525 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10526 0x00000000, 0xffffffff },
6aa20a22 10527
a71116d1
MC		 10528 /* Host Coalescing Control Registers. */
10529 { HOSTCC_MODE, TG3_FL_NOT_5705,
10530 0x00000000, 0x00000004 },
10531 { HOSTCC_MODE, TG3_FL_5705,
10532 0x00000000, 0x000000f6 },
10533 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10534 0x00000000, 0xffffffff },
10535 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10536 0x00000000, 0x000003ff },
10537 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10538 0x00000000, 0xffffffff },
10539 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10540 0x00000000, 0x000003ff },
10541 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10542 0x00000000, 0xffffffff },
10543 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10544 0x00000000, 0x000000ff },
10545 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10546 0x00000000, 0xffffffff },
10547 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10548 0x00000000, 0x000000ff },
10549 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10550 0x00000000, 0xffffffff },
10551 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10552 0x00000000, 0xffffffff },
10553 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10554 0x00000000, 0xffffffff },
10555 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10556 0x00000000, 0x000000ff },
10557 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10558 0x00000000, 0xffffffff },
10559 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10560 0x00000000, 0x000000ff },
10561 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10562 0x00000000, 0xffffffff },
10563 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10564 0x00000000, 0xffffffff },
10565 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10566 0x00000000, 0xffffffff },
10567 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10568 0x00000000, 0xffffffff },
10569 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10570 0x00000000, 0xffffffff },
10571 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10572 0xffffffff, 0x00000000 },
10573 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10574 0xffffffff, 0x00000000 },
10575
10576 /* Buffer Manager Control Registers. */
b16250e3 10577 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10578 0x00000000, 0x007fff80 },
b16250e3 10579 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10580 0x00000000, 0x007fffff },
10581 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10582 0x00000000, 0x0000003f },
10583 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10584 0x00000000, 0x000001ff },
10585 { BUFMGR_MB_HIGH_WATER, 0x0000,
10586 0x00000000, 0x000001ff },
10587 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10588 0xffffffff, 0x00000000 },
10589 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10590 0xffffffff, 0x00000000 },
6aa20a22 10591
a71116d1
MC		 10592 /* Mailbox Registers */
10593 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10594 0x00000000, 0x000001ff },
10595 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10596 0x00000000, 0x000001ff },
10597 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10598 0x00000000, 0x000007ff },
10599 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10600 0x00000000, 0x000001ff },
10601
10602 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10603 };
10604
b16250e3
MC		 10605 is_5705 = is_5750 = 0;
10606 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10607 is_5705 = 1;
b16250e3
MC		 10608 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10609 is_5750 = 1;
10610 }
a71116d1
MC		 10611
10612 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10613 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10614 continue;
10615
10616 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10617 continue;
10618
10619 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10620 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10621 continue;
10622
b16250e3
MC		 10623 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10624 continue;
10625
a71116d1
MC		 10626 offset = (u32) reg_tbl[i].offset;
10627 read_mask = reg_tbl[i].read_mask;
10628 write_mask = reg_tbl[i].write_mask;
10629
10630 /* Save the original register content */
10631 save_val = tr32(offset);
10632
10633 /* Determine the read-only value. */
10634 read_val = save_val & read_mask;
10635
10636 /* Write zero to the register, then make sure the read-only bits
10637 * are not changed and the read/write bits are all zeros.
10638 */
10639 tw32(offset, 0);
10640
10641 val = tr32(offset);
10642
10643 /* Test the read-only and read/write bits. */
10644 if (((val & read_mask) != read_val) || (val & write_mask))
10645 goto out;
10646
10647 /* Write ones to all the bits defined by RdMask and WrMask, then
10648 * make sure the read-only bits are not changed and the
10649 * read/write bits are all ones.
10650 */
10651 tw32(offset, read_mask | write_mask);
10652
10653 val = tr32(offset);
10654
10655 /* Test the read-only bits. */
10656 if ((val & read_mask) != read_val)
10657 goto out;
10658
10659 /* Test the read/write bits. */
10660 if ((val & write_mask) != write_mask)
10661 goto out;
10662
10663 tw32(offset, save_val);
10664 }
10665
10666 return 0;
10667
10668out:
9f88f29f 10669 if (netif_msg_hw(tp))
2445e461
MC		 10670 netdev_err(tp->dev,
10671 "Register test failed at offset %x\n", offset);
a71116d1
MC		 10672 tw32(offset, save_val);
10673 return -EIO;
10674}
10675
7942e1db
MC		 10676static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10677{
f71e1309 10678 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10679 int i;
10680 u32 j;
10681
e9edda69 10682 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10683 for (j = 0; j < len; j += 4) {
10684 u32 val;
10685
10686 tg3_write_mem(tp, offset + j, test_pattern[i]);
10687 tg3_read_mem(tp, offset + j, &val);
10688 if (val != test_pattern[i])
10689 return -EIO;
10690 }
10691 }
10692 return 0;
10693}
10694
10695static int tg3_test_memory(struct tg3 *tp)
10696{
10697 static struct mem_entry {
10698 u32 offset;
10699 u32 len;
10700 } mem_tbl_570x[] = {
38690194 10701 { 0x00000000, 0x00b50},
7942e1db
MC		 10702 { 0x00002000, 0x1c000},
10703 { 0xffffffff, 0x00000}
10704 }, mem_tbl_5705[] = {
10705 { 0x00000100, 0x0000c},
10706 { 0x00000200, 0x00008},
7942e1db
MC		 10707 { 0x00004000, 0x00800},
10708 { 0x00006000, 0x01000},
10709 { 0x00008000, 0x02000},
10710 { 0x00010000, 0x0e000},
10711 { 0xffffffff, 0x00000}
79f4d13a
MC		 10712 }, mem_tbl_5755[] = {
10713 { 0x00000200, 0x00008},
10714 { 0x00004000, 0x00800},
10715 { 0x00006000, 0x00800},
10716 { 0x00008000, 0x02000},
10717 { 0x00010000, 0x0c000},
10718 { 0xffffffff, 0x00000}
b16250e3
MC		 10719 }, mem_tbl_5906[] = {
10720 { 0x00000200, 0x00008},
10721 { 0x00004000, 0x00400},
10722 { 0x00006000, 0x00400},
10723 { 0x00008000, 0x01000},
10724 { 0x00010000, 0x01000},
10725 { 0xffffffff, 0x00000}
8b5a6c42
MC		 10726 }, mem_tbl_5717[] = {
10727 { 0x00000200, 0x00008},
10728 { 0x00010000, 0x0a000},
10729 { 0x00020000, 0x13c00},
10730 { 0xffffffff, 0x00000}
10731 }, mem_tbl_57765[] = {
10732 { 0x00000200, 0x00008},
10733 { 0x00004000, 0x00800},
10734 { 0x00006000, 0x09800},
10735 { 0x00010000, 0x0a000},
10736 { 0xffffffff, 0x00000}
7942e1db
MC		 10737 };
10738 struct mem_entry *mem_tbl;
10739 int err = 0;
10740 int i;
10741
8b5a6c42
MC		 10742 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10743 mem_tbl = mem_tbl_5717;
10744 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10745 mem_tbl = mem_tbl_57765;
10746 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
321d32a0
MC		 10747 mem_tbl = mem_tbl_5755;
10748 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10749 mem_tbl = mem_tbl_5906;
10750 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10751 mem_tbl = mem_tbl_5705;
10752 else
7942e1db
MC		 10753 mem_tbl = mem_tbl_570x;
10754
10755 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10756 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10757 mem_tbl[i].len)) != 0)
10758 break;
10759 }
6aa20a22 10760
7942e1db
MC		 10761 return err;
10762}
10763
9f40dead
MC		 10764#define TG3_MAC_LOOPBACK 0
10765#define TG3_PHY_LOOPBACK 1
10766
10767static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10768{
9f40dead 10769 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10770 u32 desc_idx, coal_now;
c76949a6
MC		 10771 struct sk_buff *skb, *rx_skb;
10772 u8 *tx_data;
10773 dma_addr_t map;
10774 int num_pkts, tx_len, rx_len, i, err;
10775 struct tg3_rx_buffer_desc *desc;
898a56f8 10776 struct tg3_napi *tnapi, *rnapi;
21f581a5 10777 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10778
c8873405
MC		 10779 tnapi = &tp->napi[0];
10780 rnapi = &tp->napi[0];
0c1d0e2b 10781 if (tp->irq_cnt > 1) {
0c1d0e2b 10782 rnapi = &tp->napi[1];
c8873405
MC		 10783 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10784 tnapi = &tp->napi[1];
0c1d0e2b 10785 }
fd2ce37f 10786 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10787
9f40dead 10788 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10789 /* HW errata - mac loopback fails in some cases on 5780.
10790 * Normal traffic and PHY loopback are not affected by
10791 * errata.
10792 */
10793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10794 return 0;
10795
9f40dead 10796 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10797 MAC_MODE_PORT_INT_LPBACK;
10798 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10799 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10800 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10801 mac_mode |= MAC_MODE_PORT_MODE_MII;
10802 else
10803 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10804 tw32(MAC_MODE, mac_mode);
10805 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10806 u32 val;
10807
7f97a4bd
MC		 10808 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10809 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10810 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10811 } else
10812 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10813
9ef8ca99
MC		 10814 tg3_phy_toggle_automdix(tp, 0);
10815
3f7045c1 10816 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10817 udelay(40);
5d64ad34 10818
e8f3f6ca 10819 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd 10820 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1061b7c5
MC		 10821 tg3_writephy(tp, MII_TG3_FET_PTEST,
10822 MII_TG3_FET_PTEST_FRC_TX_LINK |
10823 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10824 /* The write needs to be flushed for the AC131 */
10825 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10826 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
5d64ad34
MC		 10827 mac_mode |= MAC_MODE_PORT_MODE_MII;
10828 } else
10829 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10830
c94e3941
MC		 10831 /* reset to prevent losing 1st rx packet intermittently */
10832 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10833 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10834 udelay(10);
10835 tw32_f(MAC_RX_MODE, tp->rx_mode);
10836 }
e8f3f6ca 10837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
79eb6904
MC		 10838 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10839 if (masked_phy_id == TG3_PHY_ID_BCM5401)
e8f3f6ca 10840 mac_mode &= ~MAC_MODE_LINK_POLARITY;
79eb6904 10841 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
e8f3f6ca 10842 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10843 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10844 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10845 }
9f40dead 10846 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10847 }
10848 else
10849 return -EINVAL;
c76949a6
MC		 10850
10851 err = -EIO;
10852
c76949a6 10853 tx_len = 1514;
a20e9c62 10854 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10855 if (!skb)
10856 return -ENOMEM;
10857
c76949a6
MC		 10858 tx_data = skb_put(skb, tx_len);
10859 memcpy(tx_data, tp->dev->dev_addr, 6);
10860 memset(tx_data + 6, 0x0, 8);
10861
10862 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10863
10864 for (i = 14; i < tx_len; i++)
10865 tx_data[i] = (u8) (i & 0xff);
10866
f4188d8a
AD		 10867 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10868 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10869 dev_kfree_skb(skb);
10870 return -EIO;
10871 }
c76949a6
MC		 10872
10873 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10874 rnapi->coal_now);
c76949a6
MC		 10875
10876 udelay(10);
10877
898a56f8 10878 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10879
c76949a6
MC		 10880 num_pkts = 0;
10881
f4188d8a 10882 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10883
f3f3f27e 10884 tnapi->tx_prod++;
c76949a6
MC		 10885 num_pkts++;
10886
f3f3f27e
MC		 10887 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10888 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10889
10890 udelay(10);
10891
303fc921
MC		 10892 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10893 for (i = 0; i < 35; i++) {
c76949a6 10894 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10895 coal_now);
c76949a6
MC		 10896
10897 udelay(10);
10898
898a56f8
MC		 10899 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10900 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10901 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10902 (rx_idx == (rx_start_idx + num_pkts)))
10903 break;
10904 }
10905
f4188d8a 10906 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10907 dev_kfree_skb(skb);
10908
f3f3f27e 10909 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10910 goto out;
10911
10912 if (rx_idx != rx_start_idx + num_pkts)
10913 goto out;
10914
72334482 10915 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10916 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10917 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10918 if (opaque_key != RXD_OPAQUE_RING_STD)
10919 goto out;
10920
10921 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10922 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10923 goto out;
10924
10925 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10926 if (rx_len != tx_len)
10927 goto out;
10928
21f581a5 10929 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10930
21f581a5 10931 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10932 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10933
10934 for (i = 14; i < tx_len; i++) {
10935 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10936 goto out;
10937 }
10938 err = 0;
6aa20a22 10939
c76949a6
MC		 10940 /* tg3_free_rings will unmap and free the rx_skb */
10941out:
10942 return err;
10943}
10944
9f40dead
MC		 10945#define TG3_MAC_LOOPBACK_FAILED 1
10946#define TG3_PHY_LOOPBACK_FAILED 2
10947#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10948 TG3_PHY_LOOPBACK_FAILED)
10949
10950static int tg3_test_loopback(struct tg3 *tp)
10951{
10952 int err = 0;
9936bcf6 10953 u32 cpmuctrl = 0;
9f40dead
MC		 10954
10955 if (!netif_running(tp->dev))
10956 return TG3_LOOPBACK_FAILED;
10957
b9ec6c1b
MC		 10958 err = tg3_reset_hw(tp, 1);
10959 if (err)
10960 return TG3_LOOPBACK_FAILED;
9f40dead 10961
6833c043
MC		 10962 /* Turn off gphy autopowerdown. */
10963 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10964 tg3_phy_toggle_apd(tp, false);
10965
321d32a0 10966 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10967 int i;
10968 u32 status;
10969
10970 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10971
10972 /* Wait for up to 40 microseconds to acquire lock. */
10973 for (i = 0; i < 4; i++) {
10974 status = tr32(TG3_CPMU_MUTEX_GNT);
10975 if (status == CPMU_MUTEX_GNT_DRIVER)
10976 break;
10977 udelay(10);
10978 }
10979
10980 if (status != CPMU_MUTEX_GNT_DRIVER)
10981 return TG3_LOOPBACK_FAILED;
10982
b2a5c19c 10983 /* Turn off link-based power management. */
e875093c 10984 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10985 tw32(TG3_CPMU_CTRL,
10986 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10987 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10988 }
10989
9f40dead
MC		 10990 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10991 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10992
321d32a0 10993 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10994 tw32(TG3_CPMU_CTRL, cpmuctrl);
10995
10996 /* Release the mutex */
10997 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10998 }
10999
dd477003
MC		 11000 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
11001 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 11002 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11003 err |= TG3_PHY_LOOPBACK_FAILED;
11004 }
11005
6833c043
MC		 11006 /* Re-enable gphy autopowerdown. */
11007 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
11008 tg3_phy_toggle_apd(tp, true);
11009
9f40dead
MC		 11010 return err;
11011}
11012
4cafd3f5
MC		 11013static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11014 u64 *data)
11015{
566f86ad
MC		 11016 struct tg3 *tp = netdev_priv(dev);
11017
bc1c7567
MC		 11018 if (tp->link_config.phy_is_low_power)
11019 tg3_set_power_state(tp, PCI_D0);
11020
566f86ad
MC		 11021 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11022
11023 if (tg3_test_nvram(tp) != 0) {
11024 etest->flags |= ETH_TEST_FL_FAILED;
11025 data[0] = 1;
11026 }
ca43007a
MC		 11027 if (tg3_test_link(tp) != 0) {
11028 etest->flags |= ETH_TEST_FL_FAILED;
11029 data[1] = 1;
11030 }
a71116d1 11031 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 11032 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 11033
11034 if (netif_running(dev)) {
b02fd9e3 11035 tg3_phy_stop(tp);
a71116d1 11036 tg3_netif_stop(tp);
bbe832c0
MC		 11037 irq_sync = 1;
11038 }
a71116d1 11039
bbe832c0 11040 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 11041
11042 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 11043 err = tg3_nvram_lock(tp);
a71116d1
MC		 11044 tg3_halt_cpu(tp, RX_CPU_BASE);
11045 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11046 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 11047 if (!err)
11048 tg3_nvram_unlock(tp);
a71116d1 11049
d9ab5ad1
MC		 11050 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11051 tg3_phy_reset(tp);
11052
a71116d1
MC		 11053 if (tg3_test_registers(tp) != 0) {
11054 etest->flags |= ETH_TEST_FL_FAILED;
11055 data[2] = 1;
11056 }
7942e1db
MC		 11057 if (tg3_test_memory(tp) != 0) {
11058 etest->flags |= ETH_TEST_FL_FAILED;
11059 data[3] = 1;
11060 }
9f40dead 11061 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 11062 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 11063
f47c11ee
DM		 11064 tg3_full_unlock(tp);
11065
d4bc3927
MC		 11066 if (tg3_test_interrupt(tp) != 0) {
11067 etest->flags |= ETH_TEST_FL_FAILED;
11068 data[5] = 1;
11069 }
f47c11ee
DM		 11070
11071 tg3_full_lock(tp, 0);
d4bc3927 11072
a71116d1
MC		 11073 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11074 if (netif_running(dev)) {
11075 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 11076 err2 = tg3_restart_hw(tp, 1);
11077 if (!err2)
b9ec6c1b 11078 tg3_netif_start(tp);
a71116d1 11079 }
f47c11ee
DM		 11080
11081 tg3_full_unlock(tp);
b02fd9e3
MC		 11082
11083 if (irq_sync && !err2)
11084 tg3_phy_start(tp);
a71116d1 11085 }
bc1c7567
MC		 11086 if (tp->link_config.phy_is_low_power)
11087 tg3_set_power_state(tp, PCI_D3hot);
11088
4cafd3f5
MC		 11089}
11090
1da177e4
LT		 11091static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11092{
11093 struct mii_ioctl_data *data = if_mii(ifr);
11094 struct tg3 *tp = netdev_priv(dev);
11095 int err;
11096
b02fd9e3 11097 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 11098 struct phy_device *phydev;
b02fd9e3
MC		 11099 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11100 return -EAGAIN;
3f0e3ad7
MC		 11101 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11102 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 11103 }
11104
33f401ae 11105 switch (cmd) {
1da177e4 11106 case SIOCGMIIPHY:
882e9793 11107 data->phy_id = tp->phy_addr;
1da177e4
LT		 11108
11109 /* fallthru */
11110 case SIOCGMIIREG: {
11111 u32 mii_regval;
11112
11113 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11114 break; /* We have no PHY */
11115
bc1c7567
MC		 11116 if (tp->link_config.phy_is_low_power)
11117 return -EAGAIN;
11118
f47c11ee 11119 spin_lock_bh(&tp->lock);
1da177e4 11120 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11121 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11122
11123 data->val_out = mii_regval;
11124
11125 return err;
11126 }
11127
11128 case SIOCSMIIREG:
11129 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11130 break; /* We have no PHY */
11131
bc1c7567
MC		 11132 if (tp->link_config.phy_is_low_power)
11133 return -EAGAIN;
11134
f47c11ee 11135 spin_lock_bh(&tp->lock);
1da177e4 11136 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11137 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11138
11139 return err;
11140
11141 default:
11142 /* do nothing */
11143 break;
11144 }
11145 return -EOPNOTSUPP;
11146}
11147
11148#if TG3_VLAN_TAG_USED
11149static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11150{
11151 struct tg3 *tp = netdev_priv(dev);
11152
844b3eed
MC		 11153 if (!netif_running(dev)) {
11154 tp->vlgrp = grp;
11155 return;
11156 }
11157
11158 tg3_netif_stop(tp);
29315e87 11159
f47c11ee 11160 tg3_full_lock(tp, 0);
1da177e4
LT		 11161
11162 tp->vlgrp = grp;
11163
11164 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11165 __tg3_set_rx_mode(dev);
11166
844b3eed 11167 tg3_netif_start(tp);
46966545
MC		 11168
11169 tg3_full_unlock(tp);
1da177e4 11170}
1da177e4
LT		 11171#endif
11172
15f9850d
DM		 11173static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11174{
11175 struct tg3 *tp = netdev_priv(dev);
11176
11177 memcpy(ec, &tp->coal, sizeof(*ec));
11178 return 0;
11179}
11180
d244c892
MC		 11181static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11182{
11183 struct tg3 *tp = netdev_priv(dev);
11184 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11185 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11186
11187 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11188 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11189 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11190 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11191 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11192 }
11193
11194 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11195 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11196 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11197 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11198 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11199 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11200 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11201 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11202 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11203 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11204 return -EINVAL;
11205
11206 /* No rx interrupts will be generated if both are zero */
11207 if ((ec->rx_coalesce_usecs == 0) &&
11208 (ec->rx_max_coalesced_frames == 0))
11209 return -EINVAL;
11210
11211 /* No tx interrupts will be generated if both are zero */
11212 if ((ec->tx_coalesce_usecs == 0) &&
11213 (ec->tx_max_coalesced_frames == 0))
11214 return -EINVAL;
11215
11216 /* Only copy relevant parameters, ignore all others. */
11217 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11218 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11219 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11220 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11221 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11222 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11223 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11224 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11225 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11226
11227 if (netif_running(dev)) {
11228 tg3_full_lock(tp, 0);
11229 __tg3_set_coalesce(tp, &tp->coal);
11230 tg3_full_unlock(tp);
11231 }
11232 return 0;
11233}
11234
7282d491 11235static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11236 .get_settings = tg3_get_settings,
11237 .set_settings = tg3_set_settings,
11238 .get_drvinfo = tg3_get_drvinfo,
11239 .get_regs_len = tg3_get_regs_len,
11240 .get_regs = tg3_get_regs,
11241 .get_wol = tg3_get_wol,
11242 .set_wol = tg3_set_wol,
11243 .get_msglevel = tg3_get_msglevel,
11244 .set_msglevel = tg3_set_msglevel,
11245 .nway_reset = tg3_nway_reset,
11246 .get_link = ethtool_op_get_link,
11247 .get_eeprom_len = tg3_get_eeprom_len,
11248 .get_eeprom = tg3_get_eeprom,
11249 .set_eeprom = tg3_set_eeprom,
11250 .get_ringparam = tg3_get_ringparam,
11251 .set_ringparam = tg3_set_ringparam,
11252 .get_pauseparam = tg3_get_pauseparam,
11253 .set_pauseparam = tg3_set_pauseparam,
11254 .get_rx_csum = tg3_get_rx_csum,
11255 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11256 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11257 .set_sg = ethtool_op_set_sg,
1da177e4 11258 .set_tso = tg3_set_tso,
4cafd3f5 11259 .self_test = tg3_self_test,
1da177e4 11260 .get_strings = tg3_get_strings,
4009a93d 11261 .phys_id = tg3_phys_id,
1da177e4 11262 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11263 .get_coalesce = tg3_get_coalesce,
d244c892 11264 .set_coalesce = tg3_set_coalesce,
b9f2c044 11265 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11266};
11267
11268static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11269{
1b27777a 11270 u32 cursize, val, magic;
1da177e4
LT		 11271
11272 tp->nvram_size = EEPROM_CHIP_SIZE;
11273
e4f34110 11274 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11275 return;
11276
b16250e3
MC		 11277 if ((magic != TG3_EEPROM_MAGIC) &&
11278 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11279 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11280 return;
11281
11282 /*
11283 * Size the chip by reading offsets at increasing powers of two.
11284 * When we encounter our validation signature, we know the addressing
11285 * has wrapped around, and thus have our chip size.
11286 */
1b27777a 11287 cursize = 0x10;
1da177e4
LT		 11288
11289 while (cursize < tp->nvram_size) {
e4f34110 11290 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11291 return;
11292
1820180b 11293 if (val == magic)
1da177e4
LT		 11294 break;
11295
11296 cursize <<= 1;
11297 }
11298
11299 tp->nvram_size = cursize;
11300}
6aa20a22 11301
1da177e4
LT		 11302static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11303{
11304 u32 val;
11305
df259d8c
MC		 11306 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11307 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11308 return;
11309
11310 /* Selfboot format */
1820180b 11311 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11312 tg3_get_eeprom_size(tp);
11313 return;
11314 }
11315
6d348f2c 11316 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11317 if (val != 0) {
6d348f2c
MC		 11318 /* This is confusing. We want to operate on the
11319 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11320 * call will read from NVRAM and byteswap the data
11321 * according to the byteswapping settings for all
11322 * other register accesses. This ensures the data we
11323 * want will always reside in the lower 16-bits.
11324 * However, the data in NVRAM is in LE format, which
11325 * means the data from the NVRAM read will always be
11326 * opposite the endianness of the CPU. The 16-bit
11327 * byteswap then brings the data to CPU endianness.
11328 */
11329 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11330 return;
11331 }
11332 }
fd1122a2 11333 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11334}
11335
11336static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11337{
11338 u32 nvcfg1;
11339
11340 nvcfg1 = tr32(NVRAM_CFG1);
11341 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11342 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11343 } else {
1da177e4
LT		 11344 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11345 tw32(NVRAM_CFG1, nvcfg1);
11346 }
11347
4c987487 11348 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11349 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11350 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11351 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11352 tp->nvram_jedecnum = JEDEC_ATMEL;
11353 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11354 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11355 break;
11356 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11357 tp->nvram_jedecnum = JEDEC_ATMEL;
11358 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11359 break;
11360 case FLASH_VENDOR_ATMEL_EEPROM:
11361 tp->nvram_jedecnum = JEDEC_ATMEL;
11362 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11363 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11364 break;
11365 case FLASH_VENDOR_ST:
11366 tp->nvram_jedecnum = JEDEC_ST;
11367 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11368 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11369 break;
11370 case FLASH_VENDOR_SAIFUN:
11371 tp->nvram_jedecnum = JEDEC_SAIFUN;
11372 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11373 break;
11374 case FLASH_VENDOR_SST_SMALL:
11375 case FLASH_VENDOR_SST_LARGE:
11376 tp->nvram_jedecnum = JEDEC_SST;
11377 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11378 break;
1da177e4 11379 }
8590a603 11380 } else {
1da177e4
LT		 11381 tp->nvram_jedecnum = JEDEC_ATMEL;
11382 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11383 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11384 }
11385}
11386
a1b950d5
MC		 11387static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11388{
11389 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11390 case FLASH_5752PAGE_SIZE_256:
11391 tp->nvram_pagesize = 256;
11392 break;
11393 case FLASH_5752PAGE_SIZE_512:
11394 tp->nvram_pagesize = 512;
11395 break;
11396 case FLASH_5752PAGE_SIZE_1K:
11397 tp->nvram_pagesize = 1024;
11398 break;
11399 case FLASH_5752PAGE_SIZE_2K:
11400 tp->nvram_pagesize = 2048;
11401 break;
11402 case FLASH_5752PAGE_SIZE_4K:
11403 tp->nvram_pagesize = 4096;
11404 break;
11405 case FLASH_5752PAGE_SIZE_264:
11406 tp->nvram_pagesize = 264;
11407 break;
11408 case FLASH_5752PAGE_SIZE_528:
11409 tp->nvram_pagesize = 528;
11410 break;
11411 }
11412}
11413
361b4ac2
MC		 11414static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11415{
11416 u32 nvcfg1;
11417
11418 nvcfg1 = tr32(NVRAM_CFG1);
11419
e6af301b
MC		 11420 /* NVRAM protection for TPM */
11421 if (nvcfg1 & (1 << 27))
f66a29b0 11422 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11423
361b4ac2 11424 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11425 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11426 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11427 tp->nvram_jedecnum = JEDEC_ATMEL;
11428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11429 break;
11430 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11431 tp->nvram_jedecnum = JEDEC_ATMEL;
11432 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11433 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11434 break;
11435 case FLASH_5752VENDOR_ST_M45PE10:
11436 case FLASH_5752VENDOR_ST_M45PE20:
11437 case FLASH_5752VENDOR_ST_M45PE40:
11438 tp->nvram_jedecnum = JEDEC_ST;
11439 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11440 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11441 break;
361b4ac2
MC		 11442 }
11443
11444 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11445 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11446 } else {
361b4ac2
MC		 11447 /* For eeprom, set pagesize to maximum eeprom size */
11448 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11449
11450 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11451 tw32(NVRAM_CFG1, nvcfg1);
11452 }
11453}
11454
d3c7b886
MC		 11455static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11456{
989a9d23 11457 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11458
11459 nvcfg1 = tr32(NVRAM_CFG1);
11460
11461 /* NVRAM protection for TPM */
989a9d23 11462 if (nvcfg1 & (1 << 27)) {
f66a29b0 11463 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11464 protect = 1;
11465 }
d3c7b886 11466
989a9d23
MC		 11467 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11468 switch (nvcfg1) {
8590a603
MC		 11469 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11470 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11471 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11472 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11473 tp->nvram_jedecnum = JEDEC_ATMEL;
11474 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11475 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11476 tp->nvram_pagesize = 264;
11477 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11478 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11479 tp->nvram_size = (protect ? 0x3e200 :
11480 TG3_NVRAM_SIZE_512KB);
11481 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11482 tp->nvram_size = (protect ? 0x1f200 :
11483 TG3_NVRAM_SIZE_256KB);
11484 else
11485 tp->nvram_size = (protect ? 0x1f200 :
11486 TG3_NVRAM_SIZE_128KB);
11487 break;
11488 case FLASH_5752VENDOR_ST_M45PE10:
11489 case FLASH_5752VENDOR_ST_M45PE20:
11490 case FLASH_5752VENDOR_ST_M45PE40:
11491 tp->nvram_jedecnum = JEDEC_ST;
11492 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11493 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11494 tp->nvram_pagesize = 256;
11495 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11496 tp->nvram_size = (protect ?
11497 TG3_NVRAM_SIZE_64KB :
11498 TG3_NVRAM_SIZE_128KB);
11499 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11500 tp->nvram_size = (protect ?
11501 TG3_NVRAM_SIZE_64KB :
11502 TG3_NVRAM_SIZE_256KB);
11503 else
11504 tp->nvram_size = (protect ?
11505 TG3_NVRAM_SIZE_128KB :
11506 TG3_NVRAM_SIZE_512KB);
11507 break;
d3c7b886
MC		 11508 }
11509}
11510
1b27777a
MC		 11511static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11512{
11513 u32 nvcfg1;
11514
11515 nvcfg1 = tr32(NVRAM_CFG1);
11516
11517 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11518 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11519 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11520 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11521 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11522 tp->nvram_jedecnum = JEDEC_ATMEL;
11523 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11524 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11525
8590a603
MC		 11526 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11527 tw32(NVRAM_CFG1, nvcfg1);
11528 break;
11529 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11530 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11531 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11532 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11533 tp->nvram_jedecnum = JEDEC_ATMEL;
11534 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11535 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11536 tp->nvram_pagesize = 264;
11537 break;
11538 case FLASH_5752VENDOR_ST_M45PE10:
11539 case FLASH_5752VENDOR_ST_M45PE20:
11540 case FLASH_5752VENDOR_ST_M45PE40:
11541 tp->nvram_jedecnum = JEDEC_ST;
11542 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11543 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11544 tp->nvram_pagesize = 256;
11545 break;
1b27777a
MC		 11546 }
11547}
11548
6b91fa02
MC		 11549static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11550{
11551 u32 nvcfg1, protect = 0;
11552
11553 nvcfg1 = tr32(NVRAM_CFG1);
11554
11555 /* NVRAM protection for TPM */
11556 if (nvcfg1 & (1 << 27)) {
f66a29b0 11557 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11558 protect = 1;
11559 }
11560
11561 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11562 switch (nvcfg1) {
8590a603
MC		 11563 case FLASH_5761VENDOR_ATMEL_ADB021D:
11564 case FLASH_5761VENDOR_ATMEL_ADB041D:
11565 case FLASH_5761VENDOR_ATMEL_ADB081D:
11566 case FLASH_5761VENDOR_ATMEL_ADB161D:
11567 case FLASH_5761VENDOR_ATMEL_MDB021D:
11568 case FLASH_5761VENDOR_ATMEL_MDB041D:
11569 case FLASH_5761VENDOR_ATMEL_MDB081D:
11570 case FLASH_5761VENDOR_ATMEL_MDB161D:
11571 tp->nvram_jedecnum = JEDEC_ATMEL;
11572 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11573 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11574 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11575 tp->nvram_pagesize = 256;
11576 break;
11577 case FLASH_5761VENDOR_ST_A_M45PE20:
11578 case FLASH_5761VENDOR_ST_A_M45PE40:
11579 case FLASH_5761VENDOR_ST_A_M45PE80:
11580 case FLASH_5761VENDOR_ST_A_M45PE16:
11581 case FLASH_5761VENDOR_ST_M_M45PE20:
11582 case FLASH_5761VENDOR_ST_M_M45PE40:
11583 case FLASH_5761VENDOR_ST_M_M45PE80:
11584 case FLASH_5761VENDOR_ST_M_M45PE16:
11585 tp->nvram_jedecnum = JEDEC_ST;
11586 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11587 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11588 tp->nvram_pagesize = 256;
11589 break;
6b91fa02
MC		 11590 }
11591
11592 if (protect) {
11593 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11594 } else {
11595 switch (nvcfg1) {
8590a603
MC		 11596 case FLASH_5761VENDOR_ATMEL_ADB161D:
11597 case FLASH_5761VENDOR_ATMEL_MDB161D:
11598 case FLASH_5761VENDOR_ST_A_M45PE16:
11599 case FLASH_5761VENDOR_ST_M_M45PE16:
11600 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11601 break;
11602 case FLASH_5761VENDOR_ATMEL_ADB081D:
11603 case FLASH_5761VENDOR_ATMEL_MDB081D:
11604 case FLASH_5761VENDOR_ST_A_M45PE80:
11605 case FLASH_5761VENDOR_ST_M_M45PE80:
11606 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11607 break;
11608 case FLASH_5761VENDOR_ATMEL_ADB041D:
11609 case FLASH_5761VENDOR_ATMEL_MDB041D:
11610 case FLASH_5761VENDOR_ST_A_M45PE40:
11611 case FLASH_5761VENDOR_ST_M_M45PE40:
11612 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11613 break;
11614 case FLASH_5761VENDOR_ATMEL_ADB021D:
11615 case FLASH_5761VENDOR_ATMEL_MDB021D:
11616 case FLASH_5761VENDOR_ST_A_M45PE20:
11617 case FLASH_5761VENDOR_ST_M_M45PE20:
11618 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11619 break;
6b91fa02
MC		 11620 }
11621 }
11622}
11623
b5d3772c
MC		 11624static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11625{
11626 tp->nvram_jedecnum = JEDEC_ATMEL;
11627 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11628 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11629}
11630
321d32a0
MC		 11631static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11632{
11633 u32 nvcfg1;
11634
11635 nvcfg1 = tr32(NVRAM_CFG1);
11636
11637 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11638 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11639 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11640 tp->nvram_jedecnum = JEDEC_ATMEL;
11641 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11642 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11643
11644 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11645 tw32(NVRAM_CFG1, nvcfg1);
11646 return;
11647 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11648 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11649 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11650 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11651 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11652 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11653 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11654 tp->nvram_jedecnum = JEDEC_ATMEL;
11655 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11656 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11657
11658 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11659 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11660 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11661 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11662 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11663 break;
11664 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11665 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11666 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11667 break;
11668 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11669 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11670 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11671 break;
11672 }
11673 break;
11674 case FLASH_5752VENDOR_ST_M45PE10:
11675 case FLASH_5752VENDOR_ST_M45PE20:
11676 case FLASH_5752VENDOR_ST_M45PE40:
11677 tp->nvram_jedecnum = JEDEC_ST;
11678 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11679 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11680
11681 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11682 case FLASH_5752VENDOR_ST_M45PE10:
11683 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11684 break;
11685 case FLASH_5752VENDOR_ST_M45PE20:
11686 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11687 break;
11688 case FLASH_5752VENDOR_ST_M45PE40:
11689 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11690 break;
11691 }
11692 break;
11693 default:
df259d8c 11694 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11695 return;
11696 }
11697
a1b950d5
MC		 11698 tg3_nvram_get_pagesize(tp, nvcfg1);
11699 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11700 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11701}
11702
11703
11704static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11705{
11706 u32 nvcfg1;
11707
11708 nvcfg1 = tr32(NVRAM_CFG1);
11709
11710 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11711 case FLASH_5717VENDOR_ATMEL_EEPROM:
11712 case FLASH_5717VENDOR_MICRO_EEPROM:
11713 tp->nvram_jedecnum = JEDEC_ATMEL;
11714 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11715 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11716
11717 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11718 tw32(NVRAM_CFG1, nvcfg1);
11719 return;
11720 case FLASH_5717VENDOR_ATMEL_MDB011D:
11721 case FLASH_5717VENDOR_ATMEL_ADB011B:
11722 case FLASH_5717VENDOR_ATMEL_ADB011D:
11723 case FLASH_5717VENDOR_ATMEL_MDB021D:
11724 case FLASH_5717VENDOR_ATMEL_ADB021B:
11725 case FLASH_5717VENDOR_ATMEL_ADB021D:
11726 case FLASH_5717VENDOR_ATMEL_45USPT:
11727 tp->nvram_jedecnum = JEDEC_ATMEL;
11728 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11729 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11730
11731 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11732 case FLASH_5717VENDOR_ATMEL_MDB021D:
11733 case FLASH_5717VENDOR_ATMEL_ADB021B:
11734 case FLASH_5717VENDOR_ATMEL_ADB021D:
11735 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11736 break;
11737 default:
11738 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11739 break;
11740 }
321d32a0 11741 break;
a1b950d5
MC		 11742 case FLASH_5717VENDOR_ST_M_M25PE10:
11743 case FLASH_5717VENDOR_ST_A_M25PE10:
11744 case FLASH_5717VENDOR_ST_M_M45PE10:
11745 case FLASH_5717VENDOR_ST_A_M45PE10:
11746 case FLASH_5717VENDOR_ST_M_M25PE20:
11747 case FLASH_5717VENDOR_ST_A_M25PE20:
11748 case FLASH_5717VENDOR_ST_M_M45PE20:
11749 case FLASH_5717VENDOR_ST_A_M45PE20:
11750 case FLASH_5717VENDOR_ST_25USPT:
11751 case FLASH_5717VENDOR_ST_45USPT:
11752 tp->nvram_jedecnum = JEDEC_ST;
11753 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11754 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11755
11756 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11757 case FLASH_5717VENDOR_ST_M_M25PE20:
11758 case FLASH_5717VENDOR_ST_A_M25PE20:
11759 case FLASH_5717VENDOR_ST_M_M45PE20:
11760 case FLASH_5717VENDOR_ST_A_M45PE20:
11761 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11762 break;
11763 default:
11764 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11765 break;
11766 }
321d32a0 11767 break;
a1b950d5
MC		 11768 default:
11769 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11770 return;
321d32a0 11771 }
a1b950d5
MC		 11772
11773 tg3_nvram_get_pagesize(tp, nvcfg1);
11774 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11775 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11776}
11777
1da177e4
LT		 11778/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11779static void __devinit tg3_nvram_init(struct tg3 *tp)
11780{
1da177e4
LT		 11781 tw32_f(GRC_EEPROM_ADDR,
11782 (EEPROM_ADDR_FSM_RESET |
11783 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11784 EEPROM_ADDR_CLKPERD_SHIFT)));
11785
9d57f01c 11786 msleep(1);
1da177e4
LT		 11787
11788 /* Enable seeprom accesses. */
11789 tw32_f(GRC_LOCAL_CTRL,
11790 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11791 udelay(100);
11792
11793 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11794 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11795 tp->tg3_flags |= TG3_FLAG_NVRAM;
11796
ec41c7df 11797 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 11798 netdev_warn(tp->dev,
11799 "Cannot get nvram lock, %s failed\n",
05dbe005 11800 __func__);
ec41c7df
MC		 11801 return;
11802 }
e6af301b 11803 tg3_enable_nvram_access(tp);
1da177e4 11804
989a9d23
MC		 11805 tp->nvram_size = 0;
11806
361b4ac2
MC		 11807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11808 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11809 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11810 tg3_get_5755_nvram_info(tp);
d30cdd28 11811 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11812 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11813 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11814 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11815 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11816 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11817 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11818 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11819 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11821 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11822 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11823 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11824 else
11825 tg3_get_nvram_info(tp);
11826
989a9d23
MC		 11827 if (tp->nvram_size == 0)
11828 tg3_get_nvram_size(tp);
1da177e4 11829
e6af301b 11830 tg3_disable_nvram_access(tp);
381291b7 11831 tg3_nvram_unlock(tp);
1da177e4
LT		 11832
11833 } else {
11834 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11835
11836 tg3_get_eeprom_size(tp);
11837 }
11838}
11839
1da177e4
LT		 11840static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11841 u32 offset, u32 len, u8 *buf)
11842{
11843 int i, j, rc = 0;
11844 u32 val;
11845
11846 for (i = 0; i < len; i += 4) {
b9fc7dc5 11847 u32 addr;
a9dc529d 11848 __be32 data;
1da177e4
LT		 11849
11850 addr = offset + i;
11851
11852 memcpy(&data, buf + i, 4);
11853
62cedd11
MC		 11854 /*
11855 * The SEEPROM interface expects the data to always be opposite
11856 * the native endian format. We accomplish this by reversing
11857 * all the operations that would have been performed on the
11858 * data from a call to tg3_nvram_read_be32().
11859 */
11860 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11861
11862 val = tr32(GRC_EEPROM_ADDR);
11863 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11864
11865 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11866 EEPROM_ADDR_READ);
11867 tw32(GRC_EEPROM_ADDR, val |
11868 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11869 (addr & EEPROM_ADDR_ADDR_MASK) |
11870 EEPROM_ADDR_START |
11871 EEPROM_ADDR_WRITE);
6aa20a22 11872
9d57f01c 11873 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11874 val = tr32(GRC_EEPROM_ADDR);
11875
11876 if (val & EEPROM_ADDR_COMPLETE)
11877 break;
9d57f01c 11878 msleep(1);
1da177e4
LT		 11879 }
11880 if (!(val & EEPROM_ADDR_COMPLETE)) {
11881 rc = -EBUSY;
11882 break;
11883 }
11884 }
11885
11886 return rc;
11887}
11888
11889/* offset and length are dword aligned */
11890static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11891 u8 *buf)
11892{
11893 int ret = 0;
11894 u32 pagesize = tp->nvram_pagesize;
11895 u32 pagemask = pagesize - 1;
11896 u32 nvram_cmd;
11897 u8 *tmp;
11898
11899 tmp = kmalloc(pagesize, GFP_KERNEL);
11900 if (tmp == NULL)
11901 return -ENOMEM;
11902
11903 while (len) {
11904 int j;
e6af301b 11905 u32 phy_addr, page_off, size;
1da177e4
LT		 11906
11907 phy_addr = offset & ~pagemask;
6aa20a22 11908
1da177e4 11909 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11910 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11911 (__be32 *) (tmp + j));
11912 if (ret)
1da177e4
LT		 11913 break;
11914 }
11915 if (ret)
11916 break;
11917
c6cdf436 11918 page_off = offset & pagemask;
1da177e4
LT		 11919 size = pagesize;
11920 if (len < size)
11921 size = len;
11922
11923 len -= size;
11924
11925 memcpy(tmp + page_off, buf, size);
11926
11927 offset = offset + (pagesize - page_off);
11928
e6af301b 11929 tg3_enable_nvram_access(tp);
1da177e4
LT		 11930
11931 /*
11932 * Before we can erase the flash page, we need
11933 * to issue a special "write enable" command.
11934 */
11935 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11936
11937 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11938 break;
11939
11940 /* Erase the target page */
11941 tw32(NVRAM_ADDR, phy_addr);
11942
11943 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11944 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11945
c6cdf436 11946 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
1da177e4
LT		 11947 break;
11948
11949 /* Issue another write enable to start the write. */
11950 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11951
11952 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11953 break;
11954
11955 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11956 __be32 data;
1da177e4 11957
b9fc7dc5 11958 data = *((__be32 *) (tmp + j));
a9dc529d 11959
b9fc7dc5 11960 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11961
11962 tw32(NVRAM_ADDR, phy_addr + j);
11963
11964 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11965 NVRAM_CMD_WR;
11966
11967 if (j == 0)
11968 nvram_cmd |= NVRAM_CMD_FIRST;
11969 else if (j == (pagesize - 4))
11970 nvram_cmd |= NVRAM_CMD_LAST;
11971
11972 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11973 break;
11974 }
11975 if (ret)
11976 break;
11977 }
11978
11979 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11980 tg3_nvram_exec_cmd(tp, nvram_cmd);
11981
11982 kfree(tmp);
11983
11984 return ret;
11985}
11986
11987/* offset and length are dword aligned */
11988static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11989 u8 *buf)
11990{
11991 int i, ret = 0;
11992
11993 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11994 u32 page_off, phy_addr, nvram_cmd;
11995 __be32 data;
1da177e4
LT		 11996
11997 memcpy(&data, buf + i, 4);
b9fc7dc5 11998 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4 11999
c6cdf436 12000 page_off = offset % tp->nvram_pagesize;
1da177e4 12001
1820180b 12002 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 12003
12004 tw32(NVRAM_ADDR, phy_addr);
12005
12006 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12007
c6cdf436 12008 if (page_off == 0 || i == 0)
1da177e4 12009 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 12010 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 12011 nvram_cmd |= NVRAM_CMD_LAST;
12012
12013 if (i == (len - 4))
12014 nvram_cmd |= NVRAM_CMD_LAST;
12015
321d32a0
MC		 12016 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12017 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 12018 (tp->nvram_jedecnum == JEDEC_ST) &&
12019 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 12020
12021 if ((ret = tg3_nvram_exec_cmd(tp,
12022 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12023 NVRAM_CMD_DONE)))
12024
12025 break;
12026 }
12027 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12028 /* We always do complete word writes to eeprom. */
12029 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12030 }
12031
12032 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12033 break;
12034 }
12035 return ret;
12036}
12037
12038/* offset and length are dword aligned */
12039static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12040{
12041 int ret;
12042
1da177e4 12043 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 12044 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12045 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 12046 udelay(40);
12047 }
12048
12049 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12050 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12051 }
12052 else {
12053 u32 grc_mode;
12054
ec41c7df
MC		 12055 ret = tg3_nvram_lock(tp);
12056 if (ret)
12057 return ret;
1da177e4 12058
e6af301b
MC		 12059 tg3_enable_nvram_access(tp);
12060 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 12061 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 12062 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 12063
12064 grc_mode = tr32(GRC_MODE);
12065 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12066
12067 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12068 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12069
12070 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12071 buf);
12072 }
12073 else {
12074 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12075 buf);
12076 }
12077
12078 grc_mode = tr32(GRC_MODE);
12079 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12080
e6af301b 12081 tg3_disable_nvram_access(tp);
1da177e4
LT		 12082 tg3_nvram_unlock(tp);
12083 }
12084
12085 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 12086 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 12087 udelay(40);
12088 }
12089
12090 return ret;
12091}
12092
12093struct subsys_tbl_ent {
12094 u16 subsys_vendor, subsys_devid;
12095 u32 phy_id;
12096};
12097
24daf2b0 12098static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
1da177e4 12099 /* Broadcom boards. */
24daf2b0 12100 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12101 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 12102 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12103 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 12104 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12105 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 12106 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12107 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12108 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12109 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 12110 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12111 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12112 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12113 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12114 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12115 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 12116 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12117 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 12118 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12119 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 12120 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 12121 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 12122
12123 /* 3com boards. */
24daf2b0 12124 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12125 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 12126 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12127 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12128 { TG3PCI_SUBVENDOR_ID_3COM,
12129 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12130 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12131 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 12132 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 12133 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 12134
12135 /* DELL boards. */
24daf2b0 12136 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12137 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 12138 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12139 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 12140 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12141 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 12142 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 12143 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 12144
12145 /* Compaq boards. */
24daf2b0 12146 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12147 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 12148 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12149 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 12150 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12151 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12152 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12153 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 12154 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 12155 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 12156
12157 /* IBM boards. */
24daf2b0
MC		 12158 { TG3PCI_SUBVENDOR_ID_IBM,
12159 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 12160};
12161
24daf2b0 12162static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 12163{
12164 int i;
12165
12166 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12167 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12168 tp->pdev->subsystem_vendor) &&
12169 (subsys_id_to_phy_id[i].subsys_devid ==
12170 tp->pdev->subsystem_device))
12171 return &subsys_id_to_phy_id[i];
12172 }
12173 return NULL;
12174}
12175
7d0c41ef 12176static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12177{
1da177e4 12178 u32 val;
caf636c7
MC		 12179 u16 pmcsr;
12180
12181 /* On some early chips the SRAM cannot be accessed in D3hot state,
12182 * so need make sure we're in D0.
12183 */
12184 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12185 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12186 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12187 msleep(1);
7d0c41ef
MC		 12188
12189 /* Make sure register accesses (indirect or otherwise)
12190 * will function correctly.
12191 */
12192 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12193 tp->misc_host_ctrl);
1da177e4 12194
f49639e6
DM		 12195 /* The memory arbiter has to be enabled in order for SRAM accesses
12196 * to succeed. Normally on powerup the tg3 chip firmware will make
12197 * sure it is enabled, but other entities such as system netboot
12198 * code might disable it.
12199 */
12200 val = tr32(MEMARB_MODE);
12201 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12202
79eb6904 12203 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 12204 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12205
a85feb8c
GZ		 12206 /* Assume an onboard device and WOL capable by default. */
12207 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12208
b5d3772c 12209 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12210 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12211 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12212 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12213 }
0527ba35
MC		 12214 val = tr32(VCPU_CFGSHDW);
12215 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12216 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12217 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12218 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12219 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12220 goto done;
b5d3772c
MC		 12221 }
12222
1da177e4
LT		 12223 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12224 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12225 u32 nic_cfg, led_cfg;
a9daf367 12226 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12227 int eeprom_phy_serdes = 0;
1da177e4
LT		 12228
12229 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12230 tp->nic_sram_data_cfg = nic_cfg;
12231
12232 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12233 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12234 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12235 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12236 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12237 (ver > 0) && (ver < 0x100))
12238 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12239
a9daf367
MC		 12240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12241 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12242
1da177e4
LT		 12243 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12244 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12245 eeprom_phy_serdes = 1;
12246
12247 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12248 if (nic_phy_id != 0) {
12249 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12250 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12251
12252 eeprom_phy_id = (id1 >> 16) << 10;
12253 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12254 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12255 } else
12256 eeprom_phy_id = 0;
12257
7d0c41ef 12258 tp->phy_id = eeprom_phy_id;
747e8f8b 12259 if (eeprom_phy_serdes) {
d1ec96af
MC		 12260 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12261 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
747e8f8b
MC		 12262 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12263 else
12264 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12265 }
7d0c41ef 12266
cbf46853 12267 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12268 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12269 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12270 else
1da177e4
LT		 12271 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12272
12273 switch (led_cfg) {
12274 default:
12275 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12276 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12277 break;
12278
12279 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12280 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12281 break;
12282
12283 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12284 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12285
12286 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12287 * read on some older 5700/5701 bootcode.
12288 */
12289 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12290 ASIC_REV_5700 ||
12291 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12292 ASIC_REV_5701)
12293 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12294
1da177e4
LT		 12295 break;
12296
12297 case SHASTA_EXT_LED_SHARED:
12298 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12299 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12300 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12301 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12302 LED_CTRL_MODE_PHY_2);
12303 break;
12304
12305 case SHASTA_EXT_LED_MAC:
12306 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12307 break;
12308
12309 case SHASTA_EXT_LED_COMBO:
12310 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12311 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12312 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12313 LED_CTRL_MODE_PHY_2);
12314 break;
12315
855e1111 12316 }
1da177e4
LT		 12317
12318 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12319 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12320 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12321 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12322
b2a5c19c
MC		 12323 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12324 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12325
9d26e213 12326 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12327 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12328 if ((tp->pdev->subsystem_vendor ==
12329 PCI_VENDOR_ID_ARIMA) &&
12330 (tp->pdev->subsystem_device == 0x205a ||
12331 tp->pdev->subsystem_device == 0x2063))
12332 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12333 } else {
f49639e6 12334 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12335 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12336 }
1da177e4
LT		 12337
12338 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12339 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12340 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12341 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12342 }
b2b98d4a
MC		 12343
12344 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12345 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12346 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12347
a85feb8c
GZ		 12348 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12349 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12350 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12351
12dac075 12352 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12353 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12354 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12355
1da177e4
LT		 12356 if (cfg2 & (1 << 17))
12357 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12358
12359 /* serdes signal pre-emphasis in register 0x590 set by */
12360 /* bootcode if bit 18 is set */
12361 if (cfg2 & (1 << 18))
12362 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12363
321d32a0
MC		 12364 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12365 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12366 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12367 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12368
8ed5d97e
MC		 12369 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12370 u32 cfg3;
12371
12372 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12373 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12374 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12375 }
a9daf367 12376
14417063
MC		 12377 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12378 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
a9daf367
MC		 12379 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12380 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12381 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12382 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12383 }
05ac4cb7
MC		 12384done:
12385 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12386 device_set_wakeup_enable(&tp->pdev->dev,
12387 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12388}
12389
b2a5c19c
MC		 12390static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12391{
12392 int i;
12393 u32 val;
12394
12395 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12396 tw32(OTP_CTRL, cmd);
12397
12398 /* Wait for up to 1 ms for command to execute. */
12399 for (i = 0; i < 100; i++) {
12400 val = tr32(OTP_STATUS);
12401 if (val & OTP_STATUS_CMD_DONE)
12402 break;
12403 udelay(10);
12404 }
12405
12406 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12407}
12408
12409/* Read the gphy configuration from the OTP region of the chip. The gphy
12410 * configuration is a 32-bit value that straddles the alignment boundary.
12411 * We do two 32-bit reads and then shift and merge the results.
12412 */
12413static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12414{
12415 u32 bhalf_otp, thalf_otp;
12416
12417 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12418
12419 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12420 return 0;
12421
12422 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12423
12424 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12425 return 0;
12426
12427 thalf_otp = tr32(OTP_READ_DATA);
12428
12429 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12430
12431 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12432 return 0;
12433
12434 bhalf_otp = tr32(OTP_READ_DATA);
12435
12436 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12437}
12438
7d0c41ef
MC		 12439static int __devinit tg3_phy_probe(struct tg3 *tp)
12440{
12441 u32 hw_phy_id_1, hw_phy_id_2;
12442 u32 hw_phy_id, hw_phy_id_masked;
12443 int err;
1da177e4 12444
b02fd9e3
MC		 12445 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12446 return tg3_phy_init(tp);
12447
1da177e4 12448 /* Reading the PHY ID register can conflict with ASF
877d0310 12449 * firmware access to the PHY hardware.
1da177e4
LT		 12450 */
12451 err = 0;
0d3031d9
MC		 12452 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12453 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
79eb6904 12454 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 12455 } else {
12456 /* Now read the physical PHY_ID from the chip and verify
12457 * that it is sane. If it doesn't look good, we fall back
12458 * to either the hard-coded table based PHY_ID and failing
12459 * that the value found in the eeprom area.
12460 */
12461 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12462 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12463
12464 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12465 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12466 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12467
79eb6904 12468 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 12469 }
12470
79eb6904 12471 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 12472 tp->phy_id = hw_phy_id;
79eb6904 12473 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
1da177e4 12474 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12475 else
12476 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12477 } else {
79eb6904 12478 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 12479 /* Do nothing, phy ID already set up in
12480 * tg3_get_eeprom_hw_cfg().
12481 */
1da177e4
LT		 12482 } else {
12483 struct subsys_tbl_ent *p;
12484
12485 /* No eeprom signature? Try the hardcoded
12486 * subsys device table.
12487 */
24daf2b0 12488 p = tg3_lookup_by_subsys(tp);
1da177e4
LT		 12489 if (!p)
12490 return -ENODEV;
12491
12492 tp->phy_id = p->phy_id;
12493 if (!tp->phy_id ||
79eb6904 12494 tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 12495 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12496 }
12497 }
12498
747e8f8b 12499 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12500 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12501 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12502 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12503
12504 tg3_readphy(tp, MII_BMSR, &bmsr);
12505 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12506 (bmsr & BMSR_LSTATUS))
12507 goto skip_phy_reset;
6aa20a22 12508
1da177e4
LT		 12509 err = tg3_phy_reset(tp);
12510 if (err)
12511 return err;
12512
12513 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12514 ADVERTISE_100HALF | ADVERTISE_100FULL |
12515 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12516 tg3_ctrl = 0;
12517 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12518 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12519 MII_TG3_CTRL_ADV_1000_FULL);
12520 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12521 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12522 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12523 MII_TG3_CTRL_ENABLE_AS_MASTER);
12524 }
12525
3600d918
MC		 12526 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12527 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12528 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12529 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12530 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12531
12532 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12533 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12534
12535 tg3_writephy(tp, MII_BMCR,
12536 BMCR_ANENABLE | BMCR_ANRESTART);
12537 }
12538 tg3_phy_set_wirespeed(tp);
12539
12540 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12541 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12542 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12543 }
12544
12545skip_phy_reset:
79eb6904 12546 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 12547 err = tg3_init_5401phy_dsp(tp);
12548 if (err)
12549 return err;
1da177e4 12550
1da177e4
LT		 12551 err = tg3_init_5401phy_dsp(tp);
12552 }
12553
747e8f8b 12554 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12555 tp->link_config.advertising =
12556 (ADVERTISED_1000baseT_Half |
12557 ADVERTISED_1000baseT_Full |
12558 ADVERTISED_Autoneg |
12559 ADVERTISED_FIBRE);
12560 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12561 tp->link_config.advertising &=
12562 ~(ADVERTISED_1000baseT_Half |
12563 ADVERTISED_1000baseT_Full);
12564
12565 return err;
12566}
12567
184b8904 12568static void __devinit tg3_read_vpd(struct tg3 *tp)
1da177e4 12569{
184b8904 12570 u8 vpd_data[TG3_NVM_VPD_LEN];
4181b2c8 12571 unsigned int block_end, rosize, len;
184b8904 12572 int j, i = 0;
1b27777a 12573 u32 magic;
1da177e4 12574
df259d8c
MC		 12575 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12576 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12577 goto out_not_found;
1da177e4 12578
1820180b 12579 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12580 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12581 u32 tmp;
1da177e4 12582
6d348f2c
MC		 12583 /* The data is in little-endian format in NVRAM.
12584 * Use the big-endian read routines to preserve
12585 * the byte order as it exists in NVRAM.
12586 */
141518c9 12587 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12588 goto out_not_found;
12589
6d348f2c 12590 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12591 }
12592 } else {
94c982bd 12593 ssize_t cnt;
4181b2c8 12594 unsigned int pos = 0;
94c982bd
MC		 12595
12596 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12597 cnt = pci_read_vpd(tp->pdev, pos,
12598 TG3_NVM_VPD_LEN - pos,
12599 &vpd_data[pos]);
12600 if (cnt == -ETIMEDOUT || -EINTR)
12601 cnt = 0;
12602 else if (cnt < 0)
f49639e6 12603 goto out_not_found;
1b27777a 12604 }
94c982bd
MC		 12605 if (pos != TG3_NVM_VPD_LEN)
12606 goto out_not_found;
1da177e4
LT		 12607 }
12608
4181b2c8
MC		 12609 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12610 PCI_VPD_LRDT_RO_DATA);
12611 if (i < 0)
12612 goto out_not_found;
1da177e4 12613
4181b2c8
MC		 12614 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12615 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12616 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 12617
4181b2c8
MC		 12618 if (block_end > TG3_NVM_VPD_LEN)
12619 goto out_not_found;
af2c6a4a 12620
184b8904
MC		 12621 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12622 PCI_VPD_RO_KEYWORD_MFR_ID);
12623 if (j > 0) {
12624 len = pci_vpd_info_field_size(&vpd_data[j]);
12625
12626 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12627 if (j + len > block_end || len != 4 ||
12628 memcmp(&vpd_data[j], "1028", 4))
12629 goto partno;
12630
12631 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12632 PCI_VPD_RO_KEYWORD_VENDOR0);
12633 if (j < 0)
12634 goto partno;
12635
12636 len = pci_vpd_info_field_size(&vpd_data[j]);
12637
12638 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12639 if (j + len > block_end)
12640 goto partno;
12641
12642 memcpy(tp->fw_ver, &vpd_data[j], len);
12643 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12644 }
12645
12646partno:
4181b2c8
MC		 12647 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12648 PCI_VPD_RO_KEYWORD_PARTNO);
12649 if (i < 0)
12650 goto out_not_found;
af2c6a4a 12651
4181b2c8 12652 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 12653
4181b2c8
MC		 12654 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12655 if (len > TG3_BPN_SIZE ||
12656 (len + i) > TG3_NVM_VPD_LEN)
12657 goto out_not_found;
1da177e4 12658
4181b2c8 12659 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 12660
4181b2c8 12661 return;
1da177e4
LT		 12662
12663out_not_found:
b5d3772c
MC		 12664 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12665 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12666 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12667 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12668 strcpy(tp->board_part_number, "BCM57780");
12669 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12670 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12671 strcpy(tp->board_part_number, "BCM57760");
12672 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12673 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12674 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12675 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12676 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12677 strcpy(tp->board_part_number, "BCM57788");
b474eca7
MC		 12678 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12679 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12680 strcpy(tp->board_part_number, "BCM57761");
12681 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12682 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
b703df6f 12683 strcpy(tp->board_part_number, "BCM57765");
b474eca7
MC		 12684 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12685 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12686 strcpy(tp->board_part_number, "BCM57781");
12687 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12688 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12689 strcpy(tp->board_part_number, "BCM57785");
12690 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12691 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12692 strcpy(tp->board_part_number, "BCM57791");
12693 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12694 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12695 strcpy(tp->board_part_number, "BCM57795");
b5d3772c
MC		 12696 else
12697 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12698}
12699
9c8a620e
MC		 12700static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12701{
12702 u32 val;
12703
e4f34110 12704 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12705 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12706 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12707 val != 0)
12708 return 0;
12709
12710 return 1;
12711}
12712
acd9c119
MC		 12713static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12714{
ff3a7cb2 12715 u32 val, offset, start, ver_offset;
75f9936e 12716 int i, dst_off;
ff3a7cb2 12717 bool newver = false;
acd9c119
MC		 12718
12719 if (tg3_nvram_read(tp, 0xc, &offset) ||
12720 tg3_nvram_read(tp, 0x4, &start))
12721 return;
12722
12723 offset = tg3_nvram_logical_addr(tp, offset);
12724
ff3a7cb2 12725 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12726 return;
12727
ff3a7cb2
MC		 12728 if ((val & 0xfc000000) == 0x0c000000) {
12729 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12730 return;
12731
ff3a7cb2
MC		 12732 if (val == 0)
12733 newver = true;
12734 }
12735
75f9936e
MC		 12736 dst_off = strlen(tp->fw_ver);
12737
ff3a7cb2 12738 if (newver) {
75f9936e
MC		 12739 if (TG3_VER_SIZE - dst_off < 16 ||
12740 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 12741 return;
12742
12743 offset = offset + ver_offset - start;
12744 for (i = 0; i < 16; i += 4) {
12745 __be32 v;
12746 if (tg3_nvram_read_be32(tp, offset + i, &v))
12747 return;
12748
75f9936e 12749 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 12750 }
12751 } else {
12752 u32 major, minor;
12753
12754 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12755 return;
12756
12757 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12758 TG3_NVM_BCVER_MAJSFT;
12759 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 12760 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12761 "v%d.%02d", major, minor);
acd9c119
MC		 12762 }
12763}
12764
a6f6cb1c
MC		 12765static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12766{
12767 u32 val, major, minor;
12768
12769 /* Use native endian representation */
12770 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12771 return;
12772
12773 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12774 TG3_NVM_HWSB_CFG1_MAJSFT;
12775 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12776 TG3_NVM_HWSB_CFG1_MINSFT;
12777
12778 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12779}
12780
dfe00d7d
MC		 12781static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12782{
12783 u32 offset, major, minor, build;
12784
75f9936e 12785 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 12786
12787 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12788 return;
12789
12790 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12791 case TG3_EEPROM_SB_REVISION_0:
12792 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12793 break;
12794 case TG3_EEPROM_SB_REVISION_2:
12795 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12796 break;
12797 case TG3_EEPROM_SB_REVISION_3:
12798 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12799 break;
a4153d40
MC		 12800 case TG3_EEPROM_SB_REVISION_4:
12801 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12802 break;
12803 case TG3_EEPROM_SB_REVISION_5:
12804 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12805 break;
dfe00d7d
MC		 12806 default:
12807 return;
12808 }
12809
e4f34110 12810 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12811 return;
12812
12813 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12814 TG3_EEPROM_SB_EDH_BLD_SHFT;
12815 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12816 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12817 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12818
12819 if (minor > 99 || build > 26)
12820 return;
12821
75f9936e
MC		 12822 offset = strlen(tp->fw_ver);
12823 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12824 " v%d.%02d", major, minor);
dfe00d7d
MC		 12825
12826 if (build > 0) {
75f9936e
MC		 12827 offset = strlen(tp->fw_ver);
12828 if (offset < TG3_VER_SIZE - 1)
12829 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 12830 }
12831}
12832
acd9c119 12833static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12834{
12835 u32 val, offset, start;
acd9c119 12836 int i, vlen;
9c8a620e
MC		 12837
12838 for (offset = TG3_NVM_DIR_START;
12839 offset < TG3_NVM_DIR_END;
12840 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12841 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12842 return;
12843
9c8a620e
MC		 12844 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12845 break;
12846 }
12847
12848 if (offset == TG3_NVM_DIR_END)
12849 return;
12850
12851 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12852 start = 0x08000000;
e4f34110 12853 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12854 return;
12855
e4f34110 12856 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12857 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12858 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12859 return;
12860
12861 offset += val - start;
12862
acd9c119 12863 vlen = strlen(tp->fw_ver);
9c8a620e 12864
acd9c119
MC		 12865 tp->fw_ver[vlen++] = ',';
12866 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12867
12868 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12869 __be32 v;
12870 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12871 return;
12872
b9fc7dc5 12873 offset += sizeof(v);
c4e6575c 12874
acd9c119
MC		 12875 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12876 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12877 break;
c4e6575c 12878 }
9c8a620e 12879
acd9c119
MC		 12880 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12881 vlen += sizeof(v);
c4e6575c 12882 }
acd9c119
MC		 12883}
12884
7fd76445
MC		 12885static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12886{
12887 int vlen;
12888 u32 apedata;
12889
12890 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12891 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12892 return;
12893
12894 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12895 if (apedata != APE_SEG_SIG_MAGIC)
12896 return;
12897
12898 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12899 if (!(apedata & APE_FW_STATUS_READY))
12900 return;
12901
12902 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12903
12904 vlen = strlen(tp->fw_ver);
12905
12906 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12907 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12908 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12909 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12910 (apedata & APE_FW_VERSION_BLDMSK));
12911}
12912
acd9c119
MC		 12913static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12914{
12915 u32 val;
75f9936e 12916 bool vpd_vers = false;
acd9c119 12917
75f9936e
MC		 12918 if (tp->fw_ver[0] != 0)
12919 vpd_vers = true;
df259d8c 12920
75f9936e
MC		 12921 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12922 strcat(tp->fw_ver, "sb");
df259d8c
MC		 12923 return;
12924 }
12925
acd9c119
MC		 12926 if (tg3_nvram_read(tp, 0, &val))
12927 return;
12928
12929 if (val == TG3_EEPROM_MAGIC)
12930 tg3_read_bc_ver(tp);
12931 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12932 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12933 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12934 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12935 else
12936 return;
12937
12938 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
75f9936e
MC		 12939 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12940 goto done;
acd9c119
MC		 12941
12942 tg3_read_mgmtfw_ver(tp);
9c8a620e 12943
75f9936e 12944done:
9c8a620e 12945 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12946}
12947
7544b097
MC		 12948static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12949
1da177e4
LT		 12950static int __devinit tg3_get_invariants(struct tg3 *tp)
12951{
12952 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4 12953 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
c6cdf436 12954 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004 12955 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
c6cdf436 12956 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12957 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12958 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12959 { },
12960 };
12961 u32 misc_ctrl_reg;
1da177e4
LT		 12962 u32 pci_state_reg, grc_misc_cfg;
12963 u32 val;
12964 u16 pci_cmd;
5e7dfd0f 12965 int err;
1da177e4 12966
1da177e4
LT		 12967 /* Force memory write invalidate off. If we leave it on,
12968 * then on 5700_BX chips we have to enable a workaround.
12969 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12970 * to match the cacheline size. The Broadcom driver have this
12971 * workaround but turns MWI off all the times so never uses
12972 * it. This seems to suggest that the workaround is insufficient.
12973 */
12974 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12975 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12976 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12977
12978 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12979 * has the register indirect write enable bit set before
12980 * we try to access any of the MMIO registers. It is also
12981 * critical that the PCI-X hw workaround situation is decided
12982 * before that as well.
12983 */
12984 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12985 &misc_ctrl_reg);
12986
12987 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12988 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12990 u32 prod_id_asic_rev;
12991
5001e2f6
MC		 12992 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12993 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12994 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12995 pci_read_config_dword(tp->pdev,
12996 TG3PCI_GEN2_PRODID_ASICREV,
12997 &prod_id_asic_rev);
b703df6f
MC		 12998 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12999 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13000 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13001 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13002 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13003 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13004 pci_read_config_dword(tp->pdev,
13005 TG3PCI_GEN15_PRODID_ASICREV,
13006 &prod_id_asic_rev);
f6eb9b1f
MC		 13007 else
13008 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13009 &prod_id_asic_rev);
13010
321d32a0 13011 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 13012 }
1da177e4 13013
ff645bec
MC		 13014 /* Wrong chip ID in 5752 A0. This code can be removed later
13015 * as A0 is not in production.
13016 */
13017 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13018 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13019
6892914f
MC		 13020 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13021 * we need to disable memory and use config. cycles
13022 * only to access all registers. The 5702/03 chips
13023 * can mistakenly decode the special cycles from the
13024 * ICH chipsets as memory write cycles, causing corruption
13025 * of register and memory space. Only certain ICH bridges
13026 * will drive special cycles with non-zero data during the
13027 * address phase which can fall within the 5703's address
13028 * range. This is not an ICH bug as the PCI spec allows
13029 * non-zero address during special cycles. However, only
13030 * these ICH bridges are known to drive non-zero addresses
13031 * during special cycles.
13032 *
13033 * Since special cycles do not cross PCI bridges, we only
13034 * enable this workaround if the 5703 is on the secondary
13035 * bus of these ICH bridges.
13036 */
13037 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13038 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13039 static struct tg3_dev_id {
13040 u32 vendor;
13041 u32 device;
13042 u32 rev;
13043 } ich_chipsets[] = {
13044 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13045 PCI_ANY_ID },
13046 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13047 PCI_ANY_ID },
13048 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13049 0xa },
13050 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13051 PCI_ANY_ID },
13052 { },
13053 };
13054 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13055 struct pci_dev *bridge = NULL;
13056
13057 while (pci_id->vendor != 0) {
13058 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13059 bridge);
13060 if (!bridge) {
13061 pci_id++;
13062 continue;
13063 }
13064 if (pci_id->rev != PCI_ANY_ID) {
44c10138 13065 if (bridge->revision > pci_id->rev)
6892914f
MC		 13066 continue;
13067 }
13068 if (bridge->subordinate &&
13069 (bridge->subordinate->number ==
13070 tp->pdev->bus->number)) {
13071
13072 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13073 pci_dev_put(bridge);
13074 break;
13075 }
13076 }
13077 }
13078
41588ba1
MC		 13079 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13080 static struct tg3_dev_id {
13081 u32 vendor;
13082 u32 device;
13083 } bridge_chipsets[] = {
13084 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13085 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13086 { },
13087 };
13088 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13089 struct pci_dev *bridge = NULL;
13090
13091 while (pci_id->vendor != 0) {
13092 bridge = pci_get_device(pci_id->vendor,
13093 pci_id->device,
13094 bridge);
13095 if (!bridge) {
13096 pci_id++;
13097 continue;
13098 }
13099 if (bridge->subordinate &&
13100 (bridge->subordinate->number <=
13101 tp->pdev->bus->number) &&
13102 (bridge->subordinate->subordinate >=
13103 tp->pdev->bus->number)) {
13104 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13105 pci_dev_put(bridge);
13106 break;
13107 }
13108 }
13109 }
13110
4a29cc2e
MC		 13111 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13112 * DMA addresses > 40-bit. This bridge may have other additional
13113 * 57xx devices behind it in some 4-port NIC designs for example.
13114 * Any tg3 device found behind the bridge will also need the 40-bit
13115 * DMA workaround.
13116 */
a4e2b347
MC		 13117 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13118 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13119 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 13120 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 13121 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 13122 }
4a29cc2e
MC		 13123 else {
13124 struct pci_dev *bridge = NULL;
13125
13126 do {
13127 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13128 PCI_DEVICE_ID_SERVERWORKS_EPB,
13129 bridge);
13130 if (bridge && bridge->subordinate &&
13131 (bridge->subordinate->number <=
13132 tp->pdev->bus->number) &&
13133 (bridge->subordinate->subordinate >=
13134 tp->pdev->bus->number)) {
13135 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13136 pci_dev_put(bridge);
13137 break;
13138 }
13139 } while (bridge);
13140 }
4cf78e4f 13141
1da177e4
LT		 13142 /* Initialize misc host control in PCI block. */
13143 tp->misc_host_ctrl |= (misc_ctrl_reg &
13144 MISC_HOST_CTRL_CHIPREV);
13145 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13146 tp->misc_host_ctrl);
13147
f6eb9b1f
MC		 13148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 13151 tp->pdev_peer = tg3_find_peer(tp);
13152
321d32a0
MC		 13153 /* Intentionally exclude ASIC_REV_5906 */
13154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 13155 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 13156 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 13157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 13158 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13159 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 13162 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13163
13164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13165 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 13166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 13167 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 13168 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 13169 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13170
1b440c56
JL		 13171 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13172 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13173 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13174
027455ad
MC		 13175 /* 5700 B0 chips do not support checksumming correctly due
13176 * to hardware bugs.
13177 */
13178 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13179 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13180 else {
13181 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13182 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13183 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13184 tp->dev->features |= NETIF_F_IPV6_CSUM;
13185 }
13186
507399f1 13187 /* Determine TSO capabilities */
b703df6f
MC		 13188 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13190 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13191 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13193 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13194 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13195 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13196 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13197 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13198 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13199 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13200 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13201 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13202 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13203 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13204 tp->fw_needed = FIRMWARE_TG3TSO5;
13205 else
13206 tp->fw_needed = FIRMWARE_TG3TSO;
13207 }
13208
13209 tp->irq_max = 1;
13210
5a6f3074 13211 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13212 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13213 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13214 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13215 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13216 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13217 tp->pdev_peer == tp->pdev))
13218 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13219
321d32a0 13220 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13222 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13223 }
4f125f42 13224
b703df6f
MC		 13225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13227 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13228 tp->irq_max = TG3_IRQ_MAX_VECS;
13229 }
f6eb9b1f 13230 }
0e1406dd 13231
615774fe
MC		 13232 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13233 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13234 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13235 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13236 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13237 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13238 }
f6eb9b1f 13239
b703df6f
MC		 13240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13242 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13243
f51f3562 13244 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
c6cdf436
MC		 13245 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13246 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13247 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13248
52f4490c
MC		 13249 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13250 &pci_state_reg);
13251
5e7dfd0f
MC		 13252 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13253 if (tp->pcie_cap != 0) {
13254 u16 lnkctl;
13255
1da177e4 13256 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13257
13258 pcie_set_readrq(tp->pdev, 4096);
13259
5e7dfd0f
MC		 13260 pci_read_config_word(tp->pdev,
13261 tp->pcie_cap + PCI_EXP_LNKCTL,
13262 &lnkctl);
13263 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13264 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13265 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13267 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13268 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13269 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13270 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13271 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13272 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13273 }
52f4490c 13274 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13275 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13276 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13277 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13278 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13279 if (!tp->pcix_cap) {
2445e461
MC		 13280 dev_err(&tp->pdev->dev,
13281 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 13282 return -EIO;
13283 }
13284
13285 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13286 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13287 }
1da177e4 13288
399de50b
MC		 13289 /* If we have an AMD 762 or VIA K8T800 chipset, write
13290 * reordering to the mailbox registers done by the host
13291 * controller can cause major troubles. We read back from
13292 * every mailbox register write to force the writes to be
13293 * posted to the chip in order.
13294 */
13295 if (pci_dev_present(write_reorder_chipsets) &&
13296 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13297 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13298
69fc4053
MC		 13299 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13300 &tp->pci_cacheline_sz);
13301 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13302 &tp->pci_lat_timer);
1da177e4
LT		 13303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13304 tp->pci_lat_timer < 64) {
13305 tp->pci_lat_timer = 64;
69fc4053
MC		 13306 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13307 tp->pci_lat_timer);
1da177e4
LT		 13308 }
13309
52f4490c
MC		 13310 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13311 /* 5700 BX chips need to have their TX producer index
13312 * mailboxes written twice to workaround a bug.
13313 */
13314 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13315
52f4490c 13316 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13317 *
13318 * The workaround is to use indirect register accesses
13319 * for all chip writes not to mailbox registers.
13320 */
52f4490c 13321 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13322 u32 pm_reg;
1da177e4
LT		 13323
13324 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13325
13326 /* The chip can have it's power management PCI config
13327 * space registers clobbered due to this bug.
13328 * So explicitly force the chip into D0 here.
13329 */
9974a356
MC		 13330 pci_read_config_dword(tp->pdev,
13331 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13332 &pm_reg);
13333 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13334 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13335 pci_write_config_dword(tp->pdev,
13336 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13337 pm_reg);
13338
13339 /* Also, force SERR#/PERR# in PCI command. */
13340 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13341 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13342 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13343 }
13344 }
13345
1da177e4
LT		 13346 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13347 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13348 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13349 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13350
13351 /* Chip-specific fixup from Broadcom driver */
13352 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13353 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13354 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13355 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13356 }
13357
1ee582d8 13358 /* Default fast path register access methods */
20094930 13359 tp->read32 = tg3_read32;
1ee582d8 13360 tp->write32 = tg3_write32;
09ee929c 13361 tp->read32_mbox = tg3_read32;
20094930 13362 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13363 tp->write32_tx_mbox = tg3_write32;
13364 tp->write32_rx_mbox = tg3_write32;
13365
13366 /* Various workaround register access methods */
13367 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13368 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13369 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13370 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13371 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13372 /*
13373 * Back to back register writes can cause problems on these
13374 * chips, the workaround is to read back all reg writes
13375 * except those to mailbox regs.
13376 *
13377 * See tg3_write_indirect_reg32().
13378 */
1ee582d8 13379 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13380 }
13381
1ee582d8
MC		 13382 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13383 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13384 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13385 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13386 tp->write32_rx_mbox = tg3_write_flush_reg32;
13387 }
20094930 13388
6892914f
MC		 13389 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13390 tp->read32 = tg3_read_indirect_reg32;
13391 tp->write32 = tg3_write_indirect_reg32;
13392 tp->read32_mbox = tg3_read_indirect_mbox;
13393 tp->write32_mbox = tg3_write_indirect_mbox;
13394 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13395 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13396
13397 iounmap(tp->regs);
22abe310 13398 tp->regs = NULL;
6892914f
MC		 13399
13400 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13401 pci_cmd &= ~PCI_COMMAND_MEMORY;
13402 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13403 }
b5d3772c
MC		 13404 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13405 tp->read32_mbox = tg3_read32_mbox_5906;
13406 tp->write32_mbox = tg3_write32_mbox_5906;
13407 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13408 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13409 }
6892914f 13410
bbadf503
MC		 13411 if (tp->write32 == tg3_write_indirect_reg32 ||
13412 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13413 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13414 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13415 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13416
7d0c41ef 13417 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13418 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13419 * determined before calling tg3_set_power_state() so that
13420 * we know whether or not to switch out of Vaux power.
13421 * When the flag is set, it means that GPIO1 is used for eeprom
13422 * write protect and also implies that it is a LOM where GPIOs
13423 * are not used to switch power.
6aa20a22 13424 */
7d0c41ef
MC		 13425 tg3_get_eeprom_hw_cfg(tp);
13426
0d3031d9
MC		 13427 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13428 /* Allow reads and writes to the
13429 * APE register and memory space.
13430 */
13431 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13432 PCISTATE_ALLOW_APE_SHMEM_WR;
13433 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13434 pci_state_reg);
13435 }
13436
9936bcf6 13437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13439 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13440 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13441 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13443 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13444
314fba34
MC		 13445 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13446 * GPIO1 driven high will bring 5700's external PHY out of reset.
13447 * It is also used as eeprom write protect on LOMs.
13448 */
13449 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13450 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13451 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13452 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13453 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13454 /* Unused GPIO3 must be driven as output on 5752 because there
13455 * are no pull-up resistors on unused GPIO pins.
13456 */
13457 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13458 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13459
321d32a0 13460 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd
MC		 13461 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13462 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
af36e6b6
MC		 13463 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13464
8d519ab2
MC		 13465 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13466 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13467 /* Turn off the debug UART. */
13468 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13469 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13470 /* Keep VMain power. */
13471 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13472 GRC_LCLCTRL_GPIO_OUTPUT0;
13473 }
13474
1da177e4 13475 /* Force the chip into D0. */
bc1c7567 13476 err = tg3_set_power_state(tp, PCI_D0);
1da177e4 13477 if (err) {
2445e461 13478 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
1da177e4
LT		 13479 return err;
13480 }
13481
1da177e4
LT		 13482 /* Derive initial jumbo mode from MTU assigned in
13483 * ether_setup() via the alloc_etherdev() call
13484 */
0f893dc6 13485 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13486 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13487 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13488
13489 /* Determine WakeOnLan speed to use. */
13490 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13491 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13492 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13493 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13494 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13495 } else {
13496 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13497 }
13498
7f97a4bd
MC		 13499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13500 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13501
1da177e4
LT		 13502 /* A few boards don't want Ethernet@WireSpeed phy feature */
13503 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13504 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13505 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13506 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13507 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13508 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13509 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13510
13511 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13512 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13513 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13514 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13515 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13516
321d32a0 13517 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13518 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13519 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13520 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13521 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13522 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13523 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13525 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13526 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13527 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13528 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13529 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13530 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13531 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13532 } else
c424cb24
MC		 13533 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13534 }
1da177e4 13535
b2a5c19c
MC		 13536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13537 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13538 tp->phy_otp = tg3_read_otp_phycfg(tp);
13539 if (tp->phy_otp == 0)
13540 tp->phy_otp = TG3_OTP_DEFAULT;
13541 }
13542
f51f3562 13543 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13544 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13545 else
13546 tp->mi_mode = MAC_MI_MODE_BASE;
13547
1da177e4 13548 tp->coalesce_mode = 0;
1da177e4
LT		 13549 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13550 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13551 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13552
321d32a0
MC		 13553 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13554 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13555 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13556
158d7abd
MC		 13557 err = tg3_mdio_init(tp);
13558 if (err)
13559 return err;
1da177e4 13560
55dffe79
MC		 13561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13562 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13563 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13564 return -ENOTSUPP;
13565
1da177e4
LT		 13566 /* Initialize data/descriptor byte/word swapping. */
13567 val = tr32(GRC_MODE);
13568 val &= GRC_MODE_HOST_STACKUP;
13569 tw32(GRC_MODE, val | tp->grc_mode);
13570
13571 tg3_switch_clocks(tp);
13572
13573 /* Clear this out for sanity. */
13574 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13575
13576 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13577 &pci_state_reg);
13578 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13579 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13580 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13581
13582 if (chiprevid == CHIPREV_ID_5701_A0 ||
13583 chiprevid == CHIPREV_ID_5701_B0 ||
13584 chiprevid == CHIPREV_ID_5701_B2 ||
13585 chiprevid == CHIPREV_ID_5701_B5) {
13586 void __iomem *sram_base;
13587
13588 /* Write some dummy words into the SRAM status block
13589 * area, see if it reads back correctly. If the return
13590 * value is bad, force enable the PCIX workaround.
13591 */
13592 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13593
13594 writel(0x00000000, sram_base);
13595 writel(0x00000000, sram_base + 4);
13596 writel(0xffffffff, sram_base + 4);
13597 if (readl(sram_base) != 0x00000000)
13598 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13599 }
13600 }
13601
13602 udelay(50);
13603 tg3_nvram_init(tp);
13604
13605 grc_misc_cfg = tr32(GRC_MISC_CFG);
13606 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13607
1da177e4
LT		 13608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13609 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13610 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13611 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13612
fac9b83e
DM		 13613 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13614 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13615 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13616 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13617 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13618 HOSTCC_MODE_CLRTICK_TXBD);
13619
13620 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13621 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13622 tp->misc_host_ctrl);
13623 }
13624
3bda1258
MC		 13625 /* Preserve the APE MAC_MODE bits */
13626 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13627 tp->mac_mode = tr32(MAC_MODE) |
13628 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13629 else
13630 tp->mac_mode = TG3_DEF_MAC_MODE;
13631
1da177e4
LT		 13632 /* these are limited to 10/100 only */
13633 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13634 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13635 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13636 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13637 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13638 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13639 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13640 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13641 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13642 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13643 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13644 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
d1101142
MC		 13645 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13646 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
7f97a4bd 13647 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13648 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13649
13650 err = tg3_phy_probe(tp);
13651 if (err) {
2445e461 13652 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 13653 /* ... but do not return immediately ... */
b02fd9e3 13654 tg3_mdio_fini(tp);
1da177e4
LT		 13655 }
13656
184b8904 13657 tg3_read_vpd(tp);
c4e6575c 13658 tg3_read_fw_ver(tp);
1da177e4
LT		 13659
13660 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13661 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13662 } else {
13663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13664 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13665 else
13666 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13667 }
13668
13669 /* 5700 {AX,BX} chips have a broken status block link
13670 * change bit implementation, so we must use the
13671 * status register in those cases.
13672 */
13673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13674 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13675 else
13676 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13677
13678 /* The led_ctrl is set during tg3_phy_probe, here we might
13679 * have to force the link status polling mechanism based
13680 * upon subsystem IDs.
13681 */
13682 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13683 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13684 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13685 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13686 TG3_FLAG_USE_LINKCHG_REG);
13687 }
13688
13689 /* For all SERDES we poll the MAC status register. */
13690 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13691 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13692 else
13693 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13694
ad829268 13695 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13696 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13697 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13698 tp->rx_offset = 0;
13699
f92905de
MC		 13700 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13701
13702 /* Increment the rx prod index on the rx std ring by at most
13703 * 8 for these chips to workaround hw errata.
13704 */
13705 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13706 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13707 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13708 tp->rx_std_max_post = 8;
13709
8ed5d97e
MC		 13710 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13711 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13712 PCIE_PWR_MGMT_L1_THRESH_MSK;
13713
1da177e4
LT		 13714 return err;
13715}
13716
49b6e95f 13717#ifdef CONFIG_SPARC
1da177e4
LT		 13718static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13719{
13720 struct net_device *dev = tp->dev;
13721 struct pci_dev *pdev = tp->pdev;
49b6e95f 13722 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13723 const unsigned char *addr;
49b6e95f
DM		 13724 int len;
13725
13726 addr = of_get_property(dp, "local-mac-address", &len);
13727 if (addr && len == 6) {
13728 memcpy(dev->dev_addr, addr, 6);
13729 memcpy(dev->perm_addr, dev->dev_addr, 6);
13730 return 0;
1da177e4
LT		 13731 }
13732 return -ENODEV;
13733}
13734
13735static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13736{
13737 struct net_device *dev = tp->dev;
13738
13739 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13740 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13741 return 0;
13742}
13743#endif
13744
13745static int __devinit tg3_get_device_address(struct tg3 *tp)
13746{
13747 struct net_device *dev = tp->dev;
13748 u32 hi, lo, mac_offset;
008652b3 13749 int addr_ok = 0;
1da177e4 13750
49b6e95f 13751#ifdef CONFIG_SPARC
1da177e4
LT		 13752 if (!tg3_get_macaddr_sparc(tp))
13753 return 0;
13754#endif
13755
13756 mac_offset = 0x7c;
f49639e6 13757 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13758 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13759 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13760 mac_offset = 0xcc;
13761 if (tg3_nvram_lock(tp))
13762 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13763 else
13764 tg3_nvram_unlock(tp);
a1b950d5
MC		 13765 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13766 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13767 mac_offset = 0xcc;
13768 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13769 mac_offset = 0x10;
1da177e4
LT		 13770
13771 /* First try to get it from MAC address mailbox. */
13772 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13773 if ((hi >> 16) == 0x484b) {
13774 dev->dev_addr[0] = (hi >> 8) & 0xff;
13775 dev->dev_addr[1] = (hi >> 0) & 0xff;
13776
13777 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13778 dev->dev_addr[2] = (lo >> 24) & 0xff;
13779 dev->dev_addr[3] = (lo >> 16) & 0xff;
13780 dev->dev_addr[4] = (lo >> 8) & 0xff;
13781 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13782
008652b3
MC		 13783 /* Some old bootcode may report a 0 MAC address in SRAM */
13784 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13785 }
13786 if (!addr_ok) {
13787 /* Next, try NVRAM. */
df259d8c
MC		 13788 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13789 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13790 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13791 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13792 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13793 }
13794 /* Finally just fetch it out of the MAC control regs. */
13795 else {
13796 hi = tr32(MAC_ADDR_0_HIGH);
13797 lo = tr32(MAC_ADDR_0_LOW);
13798
13799 dev->dev_addr[5] = lo & 0xff;
13800 dev->dev_addr[4] = (lo >> 8) & 0xff;
13801 dev->dev_addr[3] = (lo >> 16) & 0xff;
13802 dev->dev_addr[2] = (lo >> 24) & 0xff;
13803 dev->dev_addr[1] = hi & 0xff;
13804 dev->dev_addr[0] = (hi >> 8) & 0xff;
13805 }
1da177e4
LT		 13806 }
13807
13808 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13809#ifdef CONFIG_SPARC
1da177e4
LT		 13810 if (!tg3_get_default_macaddr_sparc(tp))
13811 return 0;
13812#endif
13813 return -EINVAL;
13814 }
2ff43697 13815 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13816 return 0;
13817}
13818
59e6b434
DM		 13819#define BOUNDARY_SINGLE_CACHELINE 1
13820#define BOUNDARY_MULTI_CACHELINE 2
13821
13822static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13823{
13824 int cacheline_size;
13825 u8 byte;
13826 int goal;
13827
13828 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13829 if (byte == 0)
13830 cacheline_size = 1024;
13831 else
13832 cacheline_size = (int) byte * 4;
13833
13834 /* On 5703 and later chips, the boundary bits have no
13835 * effect.
13836 */
13837 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13838 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13839 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13840 goto out;
13841
13842#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13843 goal = BOUNDARY_MULTI_CACHELINE;
13844#else
13845#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13846 goal = BOUNDARY_SINGLE_CACHELINE;
13847#else
13848 goal = 0;
13849#endif
13850#endif
13851
b703df6f
MC		 13852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13853 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13854 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13855 goto out;
13856 }
13857
59e6b434
DM		 13858 if (!goal)
13859 goto out;
13860
13861 /* PCI controllers on most RISC systems tend to disconnect
13862 * when a device tries to burst across a cache-line boundary.
13863 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13864 *
13865 * Unfortunately, for PCI-E there are only limited
13866 * write-side controls for this, and thus for reads
13867 * we will still get the disconnects. We'll also waste
13868 * these PCI cycles for both read and write for chips
13869 * other than 5700 and 5701 which do not implement the
13870 * boundary bits.
13871 */
13872 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13873 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13874 switch (cacheline_size) {
13875 case 16:
13876 case 32:
13877 case 64:
13878 case 128:
13879 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13880 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13881 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13882 } else {
13883 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13884 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13885 }
13886 break;
13887
13888 case 256:
13889 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13890 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13891 break;
13892
13893 default:
13894 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13895 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13896 break;
855e1111 13897 }
59e6b434
DM		 13898 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13899 switch (cacheline_size) {
13900 case 16:
13901 case 32:
13902 case 64:
13903 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13904 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13905 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13906 break;
13907 }
13908 /* fallthrough */
13909 case 128:
13910 default:
13911 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13912 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13913 break;
855e1111 13914 }
59e6b434
DM		 13915 } else {
13916 switch (cacheline_size) {
13917 case 16:
13918 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13919 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13920 DMA_RWCTRL_WRITE_BNDRY_16);
13921 break;
13922 }
13923 /* fallthrough */
13924 case 32:
13925 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13926 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13927 DMA_RWCTRL_WRITE_BNDRY_32);
13928 break;
13929 }
13930 /* fallthrough */
13931 case 64:
13932 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13933 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13934 DMA_RWCTRL_WRITE_BNDRY_64);
13935 break;
13936 }
13937 /* fallthrough */
13938 case 128:
13939 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13940 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13941 DMA_RWCTRL_WRITE_BNDRY_128);
13942 break;
13943 }
13944 /* fallthrough */
13945 case 256:
13946 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13947 DMA_RWCTRL_WRITE_BNDRY_256);
13948 break;
13949 case 512:
13950 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13951 DMA_RWCTRL_WRITE_BNDRY_512);
13952 break;
13953 case 1024:
13954 default:
13955 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13956 DMA_RWCTRL_WRITE_BNDRY_1024);
13957 break;
855e1111 13958 }
59e6b434
DM		 13959 }
13960
13961out:
13962 return val;
13963}
13964
1da177e4
LT		 13965static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13966{
13967 struct tg3_internal_buffer_desc test_desc;
13968 u32 sram_dma_descs;
13969 int i, ret;
13970
13971 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13972
13973 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13974 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13975 tw32(RDMAC_STATUS, 0);
13976 tw32(WDMAC_STATUS, 0);
13977
13978 tw32(BUFMGR_MODE, 0);
13979 tw32(FTQ_RESET, 0);
13980
13981 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13982 test_desc.addr_lo = buf_dma & 0xffffffff;
13983 test_desc.nic_mbuf = 0x00002100;
13984 test_desc.len = size;
13985
13986 /*
13987 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13988 * the *second* time the tg3 driver was getting loaded after an
13989 * initial scan.
13990 *
13991 * Broadcom tells me:
13992 * ...the DMA engine is connected to the GRC block and a DMA
13993 * reset may affect the GRC block in some unpredictable way...
13994 * The behavior of resets to individual blocks has not been tested.
13995 *
13996 * Broadcom noted the GRC reset will also reset all sub-components.
13997 */
13998 if (to_device) {
13999 test_desc.cqid_sqid = (13 << 8) | 2;
14000
14001 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14002 udelay(40);
14003 } else {
14004 test_desc.cqid_sqid = (16 << 8) | 7;
14005
14006 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14007 udelay(40);
14008 }
14009 test_desc.flags = 0x00000005;
14010
14011 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14012 u32 val;
14013
14014 val = *(((u32 *)&test_desc) + i);
14015 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14016 sram_dma_descs + (i * sizeof(u32)));
14017 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14018 }
14019 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14020
14021 if (to_device) {
14022 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14023 } else {
14024 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14025 }
14026
14027 ret = -ENODEV;
14028 for (i = 0; i < 40; i++) {
14029 u32 val;
14030
14031 if (to_device)
14032 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14033 else
14034 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14035 if ((val & 0xffff) == sram_dma_descs) {
14036 ret = 0;
14037 break;
14038 }
14039
14040 udelay(100);
14041 }
14042
14043 return ret;
14044}
14045
ded7340d 14046#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 14047
14048static int __devinit tg3_test_dma(struct tg3 *tp)
14049{
14050 dma_addr_t buf_dma;
59e6b434 14051 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 14052 int ret = 0;
1da177e4
LT		 14053
14054 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14055 if (!buf) {
14056 ret = -ENOMEM;
14057 goto out_nofree;
14058 }
14059
14060 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14061 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14062
59e6b434 14063 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 14064
b703df6f
MC		 14065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 14067 goto out;
14068
1da177e4
LT		 14069 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14070 /* DMA read watermark not used on PCIE */
14071 tp->dma_rwctrl |= 0x00180000;
14072 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 14073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14074 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 14075 tp->dma_rwctrl |= 0x003f0000;
14076 else
14077 tp->dma_rwctrl |= 0x003f000f;
14078 } else {
14079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14081 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 14082 u32 read_water = 0x7;
1da177e4 14083
4a29cc2e
MC		 14084 /* If the 5704 is behind the EPB bridge, we can
14085 * do the less restrictive ONE_DMA workaround for
14086 * better performance.
14087 */
14088 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14089 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14090 tp->dma_rwctrl |= 0x8000;
14091 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 14092 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14093
49afdeb6
MC		 14094 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14095 read_water = 4;
59e6b434 14096 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 14097 tp->dma_rwctrl |=
14098 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14099 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14100 (1 << 23);
4cf78e4f
MC		 14101 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14102 /* 5780 always in PCIX mode */
14103 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 14104 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14105 /* 5714 always in PCIX mode */
14106 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 14107 } else {
14108 tp->dma_rwctrl |= 0x001b000f;
14109 }
14110 }
14111
14112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14113 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14114 tp->dma_rwctrl &= 0xfffffff0;
14115
14116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14117 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14118 /* Remove this if it causes problems for some boards. */
14119 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14120
14121 /* On 5700/5701 chips, we need to set this bit.
14122 * Otherwise the chip will issue cacheline transactions
14123 * to streamable DMA memory with not all the byte
14124 * enables turned on. This is an error on several
14125 * RISC PCI controllers, in particular sparc64.
14126 *
14127 * On 5703/5704 chips, this bit has been reassigned
14128 * a different meaning. In particular, it is used
14129 * on those chips to enable a PCI-X workaround.
14130 */
14131 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14132 }
14133
14134 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14135
14136#if 0
14137 /* Unneeded, already done by tg3_get_invariants. */
14138 tg3_switch_clocks(tp);
14139#endif
14140
1da177e4
LT		 14141 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14142 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14143 goto out;
14144
59e6b434
DM		 14145 /* It is best to perform DMA test with maximum write burst size
14146 * to expose the 5700/5701 write DMA bug.
14147 */
14148 saved_dma_rwctrl = tp->dma_rwctrl;
14149 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14150 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14151
1da177e4
LT		 14152 while (1) {
14153 u32 *p = buf, i;
14154
14155 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14156 p[i] = i;
14157
14158 /* Send the buffer to the chip. */
14159 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14160 if (ret) {
2445e461
MC		 14161 dev_err(&tp->pdev->dev,
14162 "%s: Buffer write failed. err = %d\n",
14163 __func__, ret);
1da177e4
LT		 14164 break;
14165 }
14166
14167#if 0
14168 /* validate data reached card RAM correctly. */
14169 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14170 u32 val;
14171 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14172 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 14173 dev_err(&tp->pdev->dev,
14174 "%s: Buffer corrupted on device! "
14175 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 14176 /* ret = -ENODEV here? */
14177 }
14178 p[i] = 0;
14179 }
14180#endif
14181 /* Now read it back. */
14182 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14183 if (ret) {
5129c3a3
MC		 14184 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14185 "err = %d\n", __func__, ret);
1da177e4
LT		 14186 break;
14187 }
14188
14189 /* Verify it. */
14190 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14191 if (p[i] == i)
14192 continue;
14193
59e6b434
DM		 14194 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14195 DMA_RWCTRL_WRITE_BNDRY_16) {
14196 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14197 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14198 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14199 break;
14200 } else {
2445e461
MC		 14201 dev_err(&tp->pdev->dev,
14202 "%s: Buffer corrupted on read back! "
14203 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 14204 ret = -ENODEV;
14205 goto out;
14206 }
14207 }
14208
14209 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14210 /* Success. */
14211 ret = 0;
14212 break;
14213 }
14214 }
59e6b434
DM		 14215 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14216 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14217 static struct pci_device_id dma_wait_state_chipsets[] = {
14218 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14219 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14220 { },
14221 };
14222
59e6b434 14223 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14224 * now look for chipsets that are known to expose the
14225 * DMA bug without failing the test.
59e6b434 14226 */
6d1cfbab
MC		 14227 if (pci_dev_present(dma_wait_state_chipsets)) {
14228 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14229 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14230 }
14231 else
14232 /* Safe to use the calculated DMA boundary. */
14233 tp->dma_rwctrl = saved_dma_rwctrl;
14234
59e6b434
DM		 14235 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14236 }
1da177e4
LT		 14237
14238out:
14239 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14240out_nofree:
14241 return ret;
14242}
14243
14244static void __devinit tg3_init_link_config(struct tg3 *tp)
14245{
14246 tp->link_config.advertising =
14247 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14248 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14249 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14250 ADVERTISED_Autoneg | ADVERTISED_MII);
14251 tp->link_config.speed = SPEED_INVALID;
14252 tp->link_config.duplex = DUPLEX_INVALID;
14253 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14254 tp->link_config.active_speed = SPEED_INVALID;
14255 tp->link_config.active_duplex = DUPLEX_INVALID;
14256 tp->link_config.phy_is_low_power = 0;
14257 tp->link_config.orig_speed = SPEED_INVALID;
14258 tp->link_config.orig_duplex = DUPLEX_INVALID;
14259 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14260}
14261
14262static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14263{
666bc831
MC		 14264 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14265 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14266 tp->bufmgr_config.mbuf_read_dma_low_water =
14267 DEFAULT_MB_RDMA_LOW_WATER_5705;
14268 tp->bufmgr_config.mbuf_mac_rx_low_water =
14269 DEFAULT_MB_MACRX_LOW_WATER_57765;
14270 tp->bufmgr_config.mbuf_high_water =
14271 DEFAULT_MB_HIGH_WATER_57765;
14272
14273 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14274 DEFAULT_MB_RDMA_LOW_WATER_5705;
14275 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14276 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14277 tp->bufmgr_config.mbuf_high_water_jumbo =
14278 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14279 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
fdfec172
MC		 14280 tp->bufmgr_config.mbuf_read_dma_low_water =
14281 DEFAULT_MB_RDMA_LOW_WATER_5705;
14282 tp->bufmgr_config.mbuf_mac_rx_low_water =
14283 DEFAULT_MB_MACRX_LOW_WATER_5705;
14284 tp->bufmgr_config.mbuf_high_water =
14285 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14286 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14287 tp->bufmgr_config.mbuf_mac_rx_low_water =
14288 DEFAULT_MB_MACRX_LOW_WATER_5906;
14289 tp->bufmgr_config.mbuf_high_water =
14290 DEFAULT_MB_HIGH_WATER_5906;
14291 }
fdfec172
MC		 14292
14293 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14294 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14295 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14296 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14297 tp->bufmgr_config.mbuf_high_water_jumbo =
14298 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14299 } else {
14300 tp->bufmgr_config.mbuf_read_dma_low_water =
14301 DEFAULT_MB_RDMA_LOW_WATER;
14302 tp->bufmgr_config.mbuf_mac_rx_low_water =
14303 DEFAULT_MB_MACRX_LOW_WATER;
14304 tp->bufmgr_config.mbuf_high_water =
14305 DEFAULT_MB_HIGH_WATER;
14306
14307 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14308 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14309 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14310 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14311 tp->bufmgr_config.mbuf_high_water_jumbo =
14312 DEFAULT_MB_HIGH_WATER_JUMBO;
14313 }
1da177e4
LT		 14314
14315 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14316 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14317}
14318
14319static char * __devinit tg3_phy_string(struct tg3 *tp)
14320{
79eb6904
MC		 14321 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14322 case TG3_PHY_ID_BCM5400: return "5400";
14323 case TG3_PHY_ID_BCM5401: return "5401";
14324 case TG3_PHY_ID_BCM5411: return "5411";
14325 case TG3_PHY_ID_BCM5701: return "5701";
14326 case TG3_PHY_ID_BCM5703: return "5703";
14327 case TG3_PHY_ID_BCM5704: return "5704";
14328 case TG3_PHY_ID_BCM5705: return "5705";
14329 case TG3_PHY_ID_BCM5750: return "5750";
14330 case TG3_PHY_ID_BCM5752: return "5752";
14331 case TG3_PHY_ID_BCM5714: return "5714";
14332 case TG3_PHY_ID_BCM5780: return "5780";
14333 case TG3_PHY_ID_BCM5755: return "5755";
14334 case TG3_PHY_ID_BCM5787: return "5787";
14335 case TG3_PHY_ID_BCM5784: return "5784";
14336 case TG3_PHY_ID_BCM5756: return "5722/5756";
14337 case TG3_PHY_ID_BCM5906: return "5906";
14338 case TG3_PHY_ID_BCM5761: return "5761";
14339 case TG3_PHY_ID_BCM5718C: return "5718C";
14340 case TG3_PHY_ID_BCM5718S: return "5718S";
14341 case TG3_PHY_ID_BCM57765: return "57765";
14342 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 14343 case 0: return "serdes";
14344 default: return "unknown";
855e1111 14345 }
1da177e4
LT		 14346}
14347
f9804ddb
MC		 14348static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14349{
14350 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14351 strcpy(str, "PCI Express");
14352 return str;
14353 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14354 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14355
14356 strcpy(str, "PCIX:");
14357
14358 if ((clock_ctrl == 7) ||
14359 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14360 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14361 strcat(str, "133MHz");
14362 else if (clock_ctrl == 0)
14363 strcat(str, "33MHz");
14364 else if (clock_ctrl == 2)
14365 strcat(str, "50MHz");
14366 else if (clock_ctrl == 4)
14367 strcat(str, "66MHz");
14368 else if (clock_ctrl == 6)
14369 strcat(str, "100MHz");
f9804ddb
MC		 14370 } else {
14371 strcpy(str, "PCI:");
14372 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14373 strcat(str, "66MHz");
14374 else
14375 strcat(str, "33MHz");
14376 }
14377 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14378 strcat(str, ":32-bit");
14379 else
14380 strcat(str, ":64-bit");
14381 return str;
14382}
14383
8c2dc7e1 14384static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14385{
14386 struct pci_dev *peer;
14387 unsigned int func, devnr = tp->pdev->devfn & ~7;
14388
14389 for (func = 0; func < 8; func++) {
14390 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14391 if (peer && peer != tp->pdev)
14392 break;
14393 pci_dev_put(peer);
14394 }
16fe9d74
MC		 14395 /* 5704 can be configured in single-port mode, set peer to
14396 * tp->pdev in that case.
14397 */
14398 if (!peer) {
14399 peer = tp->pdev;
14400 return peer;
14401 }
1da177e4
LT		 14402
14403 /*
14404 * We don't need to keep the refcount elevated; there's no way
14405 * to remove one half of this device without removing the other
14406 */
14407 pci_dev_put(peer);
14408
14409 return peer;
14410}
14411
15f9850d
DM		 14412static void __devinit tg3_init_coal(struct tg3 *tp)
14413{
14414 struct ethtool_coalesce *ec = &tp->coal;
14415
14416 memset(ec, 0, sizeof(*ec));
14417 ec->cmd = ETHTOOL_GCOALESCE;
14418 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14419 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14420 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14421 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14422 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14423 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14424 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14425 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14426 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14427
14428 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14429 HOSTCC_MODE_CLRTICK_TXBD)) {
14430 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14431 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14432 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14433 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14434 }
d244c892
MC		 14435
14436 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14437 ec->rx_coalesce_usecs_irq = 0;
14438 ec->tx_coalesce_usecs_irq = 0;
14439 ec->stats_block_coalesce_usecs = 0;
14440 }
15f9850d
DM		 14441}
14442
7c7d64b8
SH		 14443static const struct net_device_ops tg3_netdev_ops = {
14444 .ndo_open = tg3_open,
14445 .ndo_stop = tg3_close,
00829823
SH		 14446 .ndo_start_xmit = tg3_start_xmit,
14447 .ndo_get_stats = tg3_get_stats,
14448 .ndo_validate_addr = eth_validate_addr,
14449 .ndo_set_multicast_list = tg3_set_rx_mode,
14450 .ndo_set_mac_address = tg3_set_mac_addr,
14451 .ndo_do_ioctl = tg3_ioctl,
14452 .ndo_tx_timeout = tg3_tx_timeout,
14453 .ndo_change_mtu = tg3_change_mtu,
14454#if TG3_VLAN_TAG_USED
14455 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14456#endif
14457#ifdef CONFIG_NET_POLL_CONTROLLER
14458 .ndo_poll_controller = tg3_poll_controller,
14459#endif
14460};
14461
14462static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14463 .ndo_open = tg3_open,
14464 .ndo_stop = tg3_close,
14465 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14466 .ndo_get_stats = tg3_get_stats,
14467 .ndo_validate_addr = eth_validate_addr,
14468 .ndo_set_multicast_list = tg3_set_rx_mode,
14469 .ndo_set_mac_address = tg3_set_mac_addr,
14470 .ndo_do_ioctl = tg3_ioctl,
14471 .ndo_tx_timeout = tg3_tx_timeout,
14472 .ndo_change_mtu = tg3_change_mtu,
14473#if TG3_VLAN_TAG_USED
14474 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14475#endif
14476#ifdef CONFIG_NET_POLL_CONTROLLER
14477 .ndo_poll_controller = tg3_poll_controller,
14478#endif
14479};
14480
1da177e4
LT		 14481static int __devinit tg3_init_one(struct pci_dev *pdev,
14482 const struct pci_device_id *ent)
14483{
1da177e4
LT		 14484 struct net_device *dev;
14485 struct tg3 *tp;
646c9edd
MC		 14486 int i, err, pm_cap;
14487 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14488 char str[40];
72f2afb8 14489 u64 dma_mask, persist_dma_mask;
1da177e4 14490
05dbe005 14491 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 14492
14493 err = pci_enable_device(pdev);
14494 if (err) {
2445e461 14495 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 14496 return err;
14497 }
14498
1da177e4
LT		 14499 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14500 if (err) {
2445e461 14501 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 14502 goto err_out_disable_pdev;
14503 }
14504
14505 pci_set_master(pdev);
14506
14507 /* Find power-management capability. */
14508 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14509 if (pm_cap == 0) {
2445e461
MC		 14510 dev_err(&pdev->dev,
14511 "Cannot find Power Management capability, aborting\n");
1da177e4
LT		 14512 err = -EIO;
14513 goto err_out_free_res;
14514 }
14515
fe5f5787 14516 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 14517 if (!dev) {
2445e461 14518 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
1da177e4
LT		 14519 err = -ENOMEM;
14520 goto err_out_free_res;
14521 }
14522
1da177e4
LT		 14523 SET_NETDEV_DEV(dev, &pdev->dev);
14524
1da177e4
LT		 14525#if TG3_VLAN_TAG_USED
14526 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14527#endif
14528
14529 tp = netdev_priv(dev);
14530 tp->pdev = pdev;
14531 tp->dev = dev;
14532 tp->pm_cap = pm_cap;
1da177e4
LT		 14533 tp->rx_mode = TG3_DEF_RX_MODE;
14534 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14535
1da177e4
LT		 14536 if (tg3_debug > 0)
14537 tp->msg_enable = tg3_debug;
14538 else
14539 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14540
14541 /* The word/byte swap controls here control register access byte
14542 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14543 * setting below.
14544 */
14545 tp->misc_host_ctrl =
14546 MISC_HOST_CTRL_MASK_PCI_INT |
14547 MISC_HOST_CTRL_WORD_SWAP |
14548 MISC_HOST_CTRL_INDIR_ACCESS |
14549 MISC_HOST_CTRL_PCISTATE_RW;
14550
14551 /* The NONFRM (non-frame) byte/word swap controls take effect
14552 * on descriptor entries, anything which isn't packet data.
14553 *
14554 * The StrongARM chips on the board (one for tx, one for rx)
14555 * are running in big-endian mode.
14556 */
14557 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14558 GRC_MODE_WSWAP_NONFRM_DATA);
14559#ifdef __BIG_ENDIAN
14560 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14561#endif
14562 spin_lock_init(&tp->lock);
1da177e4 14563 spin_lock_init(&tp->indirect_lock);
c4028958 14564 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14565
d5fe488a 14566 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14567 if (!tp->regs) {
ab96b241 14568 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 14569 err = -ENOMEM;
14570 goto err_out_free_dev;
14571 }
14572
14573 tg3_init_link_config(tp);
14574
1da177e4
LT		 14575 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14576 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14577
1da177e4 14578 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14579 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14580 dev->irq = pdev->irq;
1da177e4
LT		 14581
14582 err = tg3_get_invariants(tp);
14583 if (err) {
ab96b241
MC		 14584 dev_err(&pdev->dev,
14585 "Problem fetching invariants of chip, aborting\n");
1da177e4
LT		 14586 goto err_out_iounmap;
14587 }
14588
615774fe
MC		 14589 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14590 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14591 dev->netdev_ops = &tg3_netdev_ops;
14592 else
14593 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14594
14595
4a29cc2e
MC		 14596 /* The EPB bridge inside 5714, 5715, and 5780 and any
14597 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14598 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14599 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14600 * do DMA address check in tg3_start_xmit().
14601 */
4a29cc2e 14602 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14603 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14604 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14605 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14606#ifdef CONFIG_HIGHMEM
6a35528a 14607 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14608#endif
4a29cc2e 14609 } else
6a35528a 14610 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14611
14612 /* Configure DMA attributes. */
284901a9 14613 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14614 err = pci_set_dma_mask(pdev, dma_mask);
14615 if (!err) {
14616 dev->features |= NETIF_F_HIGHDMA;
14617 err = pci_set_consistent_dma_mask(pdev,
14618 persist_dma_mask);
14619 if (err < 0) {
ab96b241
MC		 14620 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14621 "DMA for consistent allocations\n");
72f2afb8
MC		 14622 goto err_out_iounmap;
14623 }
14624 }
14625 }
284901a9
YH		 14626 if (err || dma_mask == DMA_BIT_MASK(32)) {
14627 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 14628 if (err) {
ab96b241
MC		 14629 dev_err(&pdev->dev,
14630 "No usable DMA configuration, aborting\n");
72f2afb8
MC		 14631 goto err_out_iounmap;
14632 }
14633 }
14634
fdfec172 14635 tg3_init_bufmgr_config(tp);
1da177e4 14636
507399f1
MC		 14637 /* Selectively allow TSO based on operating conditions */
14638 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14639 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14640 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14641 else {
14642 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14643 tp->fw_needed = NULL;
1da177e4 14644 }
507399f1
MC		 14645
14646 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14647 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14648
4e3a7aaa
MC		 14649 /* TSO is on by default on chips that support hardware TSO.
14650 * Firmware TSO on older chips gives lower performance, so it
14651 * is off by default, but can be enabled using ethtool.
14652 */
e849cdc3
MC		 14653 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14654 (dev->features & NETIF_F_IP_CSUM))
14655 dev->features |= NETIF_F_TSO;
14656
14657 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14658 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14659 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14660 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14661 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14663 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14664 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14665 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14666 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14667 dev->features |= NETIF_F_TSO_ECN;
b0026624 14668 }
1da177e4 14669
1da177e4
LT		 14670 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14671 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14672 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14673 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14674 tp->rx_pending = 63;
14675 }
14676
1da177e4
LT		 14677 err = tg3_get_device_address(tp);
14678 if (err) {
ab96b241
MC		 14679 dev_err(&pdev->dev,
14680 "Could not obtain valid ethernet address, aborting\n");
026a6c21 14681 goto err_out_iounmap;
1da177e4
LT		 14682 }
14683
c88864df 14684 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14685 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14686 if (!tp->aperegs) {
ab96b241
MC		 14687 dev_err(&pdev->dev,
14688 "Cannot map APE registers, aborting\n");
c88864df 14689 err = -ENOMEM;
026a6c21 14690 goto err_out_iounmap;
c88864df
MC		 14691 }
14692
14693 tg3_ape_lock_init(tp);
7fd76445
MC		 14694
14695 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14696 tg3_read_dash_ver(tp);
c88864df
MC		 14697 }
14698
1da177e4
LT		 14699 /*
14700 * Reset chip in case UNDI or EFI driver did not shutdown
14701 * DMA self test will enable WDMAC and we'll see (spurious)
14702 * pending DMA on the PCI bus at that point.
14703 */
14704 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14705 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14706 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14707 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14708 }
14709
14710 err = tg3_test_dma(tp);
14711 if (err) {
ab96b241 14712 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 14713 goto err_out_apeunmap;
1da177e4
LT		 14714 }
14715
1da177e4
LT		 14716 /* flow control autonegotiation is default behavior */
14717 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14718 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14719
78f90dcf
MC		 14720 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14721 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14722 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14723 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14724 struct tg3_napi *tnapi = &tp->napi[i];
14725
14726 tnapi->tp = tp;
14727 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14728
14729 tnapi->int_mbox = intmbx;
14730 if (i < 4)
14731 intmbx += 0x8;
14732 else
14733 intmbx += 0x4;
14734
14735 tnapi->consmbox = rcvmbx;
14736 tnapi->prodmbox = sndmbx;
14737
14738 if (i) {
14739 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14740 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14741 } else {
14742 tnapi->coal_now = HOSTCC_MODE_NOW;
14743 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14744 }
14745
14746 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14747 break;
14748
14749 /*
14750 * If we support MSIX, we'll be using RSS. If we're using
14751 * RSS, the first vector only handles link interrupts and the
14752 * remaining vectors handle rx and tx interrupts. Reuse the
14753 * mailbox values for the next iteration. The values we setup
14754 * above are still useful for the single vectored mode.
14755 */
14756 if (!i)
14757 continue;
14758
14759 rcvmbx += 0x8;
14760
14761 if (sndmbx & 0x4)
14762 sndmbx -= 0x4;
14763 else
14764 sndmbx += 0xc;
14765 }
14766
15f9850d
DM		 14767 tg3_init_coal(tp);
14768
c49a1561
MC		 14769 pci_set_drvdata(pdev, dev);
14770
1da177e4
LT		 14771 err = register_netdev(dev);
14772 if (err) {
ab96b241 14773 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 14774 goto err_out_apeunmap;
1da177e4
LT		 14775 }
14776
05dbe005
JP		 14777 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14778 tp->board_part_number,
14779 tp->pci_chip_rev_id,
14780 tg3_bus_string(tp, str),
14781 dev->dev_addr);
1da177e4 14782
3f0e3ad7
MC		 14783 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14784 struct phy_device *phydev;
14785 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 14786 netdev_info(dev,
14787 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 14788 phydev->drv->name, dev_name(&phydev->dev));
3f0e3ad7 14789 } else
5129c3a3
MC		 14790 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14791 "(WireSpeed[%d])\n", tg3_phy_string(tp),
05dbe005
JP		 14792 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14793 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14794 "10/100/1000Base-T")),
14795 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14796
14797 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14798 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14799 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14800 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14801 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14802 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14803 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14804 tp->dma_rwctrl,
14805 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14806 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4
LT		 14807
14808 return 0;
14809
0d3031d9
MC		 14810err_out_apeunmap:
14811 if (tp->aperegs) {
14812 iounmap(tp->aperegs);
14813 tp->aperegs = NULL;
14814 }
14815
1da177e4 14816err_out_iounmap:
6892914f
MC		 14817 if (tp->regs) {
14818 iounmap(tp->regs);
22abe310 14819 tp->regs = NULL;
6892914f 14820 }
1da177e4
LT		 14821
14822err_out_free_dev:
14823 free_netdev(dev);
14824
14825err_out_free_res:
14826 pci_release_regions(pdev);
14827
14828err_out_disable_pdev:
14829 pci_disable_device(pdev);
14830 pci_set_drvdata(pdev, NULL);
14831 return err;
14832}
14833
14834static void __devexit tg3_remove_one(struct pci_dev *pdev)
14835{
14836 struct net_device *dev = pci_get_drvdata(pdev);
14837
14838 if (dev) {
14839 struct tg3 *tp = netdev_priv(dev);
14840
077f849d
JSR		 14841 if (tp->fw)
14842 release_firmware(tp->fw);
14843
7faa006f 14844 flush_scheduled_work();
158d7abd 14845
b02fd9e3
MC		 14846 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14847 tg3_phy_fini(tp);
158d7abd 14848 tg3_mdio_fini(tp);
b02fd9e3 14849 }
158d7abd 14850
1da177e4 14851 unregister_netdev(dev);
0d3031d9
MC		 14852 if (tp->aperegs) {
14853 iounmap(tp->aperegs);
14854 tp->aperegs = NULL;
14855 }
6892914f
MC		 14856 if (tp->regs) {
14857 iounmap(tp->regs);
22abe310 14858 tp->regs = NULL;
6892914f 14859 }
1da177e4
LT		 14860 free_netdev(dev);
14861 pci_release_regions(pdev);
14862 pci_disable_device(pdev);
14863 pci_set_drvdata(pdev, NULL);
14864 }
14865}
14866
14867static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14868{
14869 struct net_device *dev = pci_get_drvdata(pdev);
14870 struct tg3 *tp = netdev_priv(dev);
12dac075 14871 pci_power_t target_state;
1da177e4
LT		 14872 int err;
14873
3e0c95fd
MC		 14874 /* PCI register 4 needs to be saved whether netif_running() or not.
14875 * MSI address and data need to be saved if using MSI and
14876 * netif_running().
14877 */
14878 pci_save_state(pdev);
14879
1da177e4
LT		 14880 if (!netif_running(dev))
14881 return 0;
14882
7faa006f 14883 flush_scheduled_work();
b02fd9e3 14884 tg3_phy_stop(tp);
1da177e4
LT		 14885 tg3_netif_stop(tp);
14886
14887 del_timer_sync(&tp->timer);
14888
f47c11ee 14889 tg3_full_lock(tp, 1);
1da177e4 14890 tg3_disable_ints(tp);
f47c11ee 14891 tg3_full_unlock(tp);
1da177e4
LT		 14892
14893 netif_device_detach(dev);
14894
f47c11ee 14895 tg3_full_lock(tp, 0);
944d980e 14896 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14897 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14898 tg3_full_unlock(tp);
1da177e4 14899
12dac075
RW		 14900 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14901
14902 err = tg3_set_power_state(tp, target_state);
1da177e4 14903 if (err) {
b02fd9e3
MC		 14904 int err2;
14905
f47c11ee 14906 tg3_full_lock(tp, 0);
1da177e4 14907
6a9eba15 14908 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14909 err2 = tg3_restart_hw(tp, 1);
14910 if (err2)
b9ec6c1b 14911 goto out;
1da177e4
LT		 14912
14913 tp->timer.expires = jiffies + tp->timer_offset;
14914 add_timer(&tp->timer);
14915
14916 netif_device_attach(dev);
14917 tg3_netif_start(tp);
14918
b9ec6c1b 14919out:
f47c11ee 14920 tg3_full_unlock(tp);
b02fd9e3
MC		 14921
14922 if (!err2)
14923 tg3_phy_start(tp);
1da177e4
LT		 14924 }
14925
14926 return err;
14927}
14928
14929static int tg3_resume(struct pci_dev *pdev)
14930{
14931 struct net_device *dev = pci_get_drvdata(pdev);
14932 struct tg3 *tp = netdev_priv(dev);
14933 int err;
14934
3e0c95fd
MC		 14935 pci_restore_state(tp->pdev);
14936
1da177e4
LT		 14937 if (!netif_running(dev))
14938 return 0;
14939
bc1c7567 14940 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14941 if (err)
14942 return err;
14943
14944 netif_device_attach(dev);
14945
f47c11ee 14946 tg3_full_lock(tp, 0);
1da177e4 14947
6a9eba15 14948 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14949 err = tg3_restart_hw(tp, 1);
14950 if (err)
14951 goto out;
1da177e4
LT		 14952
14953 tp->timer.expires = jiffies + tp->timer_offset;
14954 add_timer(&tp->timer);
14955
1da177e4
LT		 14956 tg3_netif_start(tp);
14957
b9ec6c1b 14958out:
f47c11ee 14959 tg3_full_unlock(tp);
1da177e4 14960
b02fd9e3
MC		 14961 if (!err)
14962 tg3_phy_start(tp);
14963
b9ec6c1b 14964 return err;
1da177e4
LT		 14965}
14966
14967static struct pci_driver tg3_driver = {
14968 .name = DRV_MODULE_NAME,
14969 .id_table = tg3_pci_tbl,
14970 .probe = tg3_init_one,
14971 .remove = __devexit_p(tg3_remove_one),
14972 .suspend = tg3_suspend,
14973 .resume = tg3_resume
14974};
14975
14976static int __init tg3_init(void)
14977{
29917620 14978 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14979}
14980
14981static void __exit tg3_cleanup(void)
14982{
14983 pci_unregister_driver(&tg3_driver);
14984}
14985
14986module_init(tg3_init);
14987module_exit(tg3_cleanup);
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