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tg3: Improve 5785 PCIe performance
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
daf09de8
MC		 71#define DRV_MODULE_VERSION "3.102"
72#define DRV_MODULE_RELDATE "September 1, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 139
140/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 141#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 142
ad829268
MC		 143#define TG3_RAW_IP_ALIGN 2
144
1da177e4
LT		 145/* number of ETHTOOL_GSTATS u64's */
146#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
4cafd3f5
MC		 148#define TG3_NUM_TEST 6
149
077f849d
JSR		 150#define FIRMWARE_TG3 "tigon/tg3.bin"
151#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
1da177e4
LT		 154static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 161MODULE_FIRMWARE(FIRMWARE_TG3);
162MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
679563f4 165#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 166
167static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168module_param(tg3_debug, int, 0);
169MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
1da177e4
LT		 246};
247
248MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
50da859d 250static const struct {
1da177e4
LT		 251 const char string[ETH_GSTRING_LEN];
252} ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329};
330
50da859d 331static const struct {
4cafd3f5
MC		 332 const char string[ETH_GSTRING_LEN];
333} ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340};
341
b401e9e2
MC		 342static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345}
346
347static u32 tg3_read32(struct tg3 *tp, u32 off)
348{
6aa20a22 349 return (readl(tp->regs + off));
b401e9e2
MC		 350}
351
0d3031d9
MC		 352static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353{
354 writel(val, tp->aperegs + off);
355}
356
357static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358{
359 return (readl(tp->aperegs + off));
360}
361
1da177e4
LT		 362static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363{
6892914f
MC		 364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 370}
371
372static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373{
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
1da177e4
LT		 376}
377
6892914f 378static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 379{
6892914f
MC		 380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388}
389
390static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391{
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
1da177e4 403 }
6892914f
MC		 404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418}
419
420static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421{
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430}
431
b401e9e2
MC		 432/* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 438{
b401e9e2
MC		 439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
1da177e4
LT		 455}
456
09ee929c
MC		 457static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458{
459 tp->write32_mbox(tp, off, val);
6892914f
MC		 460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
09ee929c
MC		 463}
464
20094930 465static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 466{
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473}
474
b5d3772c
MC		 475static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476{
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478}
479
480static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481{
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483}
484
20094930 485#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 486#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 487#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 489#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 490
491#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 492#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 494#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 495
496static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497{
6892914f
MC		 498 unsigned long flags;
499
b5d3772c
MC		 500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
6892914f 504 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 508
bbadf503
MC		 509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 519}
520
1da177e4
LT		 521static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522{
6892914f
MC		 523 unsigned long flags;
524
b5d3772c
MC		 525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
6892914f 531 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 535
bbadf503
MC		 536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
6892914f 545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 546}
547
0d3031d9
MC		 548static void tg3_ape_lock_init(struct tg3 *tp)
549{
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556}
557
558static int tg3_ape_lock(struct tg3 *tp, int locknum)
559{
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
77b483f1 568 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596}
597
598static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599{
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
77b483f1 606 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615}
616
1da177e4
LT		 617static void tg3_disable_ints(struct tg3 *tp)
618{
89aeb3bc
MC		 619 int i;
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 625}
626
1da177e4
LT		 627static void tg3_enable_ints(struct tg3 *tp)
628{
89aeb3bc
MC		 629 int i;
630 u32 coal_now = 0;
631
bbe832c0
MC		 632 tp->irq_sync = 0;
633 wmb();
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 643
89aeb3bc
MC		 644 coal_now |= tnapi->coal_now;
645 }
f19af9c2
MC		 646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 654}
655
17375d25 656static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 657{
17375d25 658 struct tg3 *tp = tnapi->tp;
898a56f8 659 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
f3f3f27e 670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 672 work_exists = 1;
673
674 return work_exists;
675}
676
17375d25 677/* tg3_int_reenable
04237ddd
MC		 678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
6aa20a22 680 * which reenables interrupts
1da177e4 681 */
17375d25 682static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 683{
17375d25
MC		 684 struct tg3 *tp = tnapi->tp;
685
898a56f8 686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 687 mmiowb();
688
fac9b83e
DM		 689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 694 tg3_has_work(tnapi))
04237ddd 695 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 697}
698
fed97810
MC		 699static void tg3_napi_disable(struct tg3 *tp)
700{
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705}
706
707static void tg3_napi_enable(struct tg3 *tp)
708{
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713}
714
1da177e4
LT		 715static inline void tg3_netif_stop(struct tg3 *tp)
716{
bbe832c0 717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 718 tg3_napi_disable(tp);
1da177e4
LT		 719 netif_tx_disable(tp->dev);
720}
721
722static inline void tg3_netif_start(struct tg3 *tp)
723{
fe5f5787
MC		 724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
1da177e4 727 */
fe5f5787
MC		 728 netif_tx_wake_all_queues(tp->dev);
729
fed97810
MC		 730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 732 tg3_enable_ints(tp);
1da177e4
LT		 733}
734
735static void tg3_switch_clocks(struct tg3 *tp)
736{
f6eb9b1f 737 u32 clock_ctrl;
1da177e4
LT		 738 u32 orig_clock_ctrl;
739
795d01c5
MC		 740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 742 return;
743
f6eb9b1f
MC		 744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
1da177e4
LT		 746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
1da177e4 765 }
b401e9e2 766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 767}
768
769#define PHY_BUSY_LOOPS 5000
770
771static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772{
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
882e9793 785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 790
1da177e4
LT		 791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818}
819
820static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821{
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
7f97a4bd 826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
1da177e4
LT		 830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
882e9793 836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 842
1da177e4
LT		 843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867}
868
95e2869a
MC		 869static int tg3_bmcr_reset(struct tg3 *tp)
870{
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
d4675b52 894 if (limit < 0)
95e2869a
MC		 895 return -EBUSY;
896
897 return 0;
898}
899
158d7abd
MC		 900static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901{
3d16543d 902 struct tg3 *tp = bp->priv;
158d7abd
MC		 903 u32 val;
904
24bb4fb6 905 spin_lock_bh(&tp->lock);
158d7abd
MC		 906
907 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
158d7abd
MC		 911
912 return val;
913}
914
915static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
24bb4fb6 918 u32 ret = 0;
158d7abd 919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_writephy(tp, reg, val))
24bb4fb6 923 ret = -EIO;
158d7abd 924
24bb4fb6
MC		 925 spin_unlock_bh(&tp->lock);
926
927 return ret;
158d7abd
MC		 928}
929
930static int tg3_mdio_reset(struct mii_bus *bp)
931{
932 return 0;
933}
934
9c61d6bc 935static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 936{
937 u32 val;
fcb389df 938 struct phy_device *phydev;
a9daf367 939
3f0e3ad7 940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
943 val = MAC_PHYCFG2_50610_LED_MODES;
944 break;
945 case TG3_PHY_ID_BCMAC131:
946 val = MAC_PHYCFG2_AC131_LED_MODES;
947 break;
948 case TG3_PHY_ID_RTL8211C:
949 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
950 break;
951 case TG3_PHY_ID_RTL8201E:
952 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
953 break;
954 default:
a9daf367 955 return;
fcb389df
MC		 956 }
957
958 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
959 tw32(MAC_PHYCFG2, val);
960
961 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 962 val &= ~(MAC_PHYCFG1_RGMII_INT |
963 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
964 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 965 tw32(MAC_PHYCFG1, val);
966
967 return;
968 }
969
970 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
971 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
972 MAC_PHYCFG2_FMODE_MASK_MASK |
973 MAC_PHYCFG2_GMODE_MASK_MASK |
974 MAC_PHYCFG2_ACT_MASK_MASK |
975 MAC_PHYCFG2_QUAL_MASK_MASK |
976 MAC_PHYCFG2_INBAND_ENABLE;
977
978 tw32(MAC_PHYCFG2, val);
a9daf367 979
bb85fbb6
MC		 980 val = tr32(MAC_PHYCFG1);
981 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
982 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
983 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 984 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
985 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
986 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
987 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
988 }
bb85fbb6
MC		 989 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
990 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
991 tw32(MAC_PHYCFG1, val);
a9daf367 992
a9daf367
MC		 993 val = tr32(MAC_EXT_RGMII_MODE);
994 val &= ~(MAC_RGMII_MODE_RX_INT_B |
995 MAC_RGMII_MODE_RX_QUALITY |
996 MAC_RGMII_MODE_RX_ACTIVITY |
997 MAC_RGMII_MODE_RX_ENG_DET |
998 MAC_RGMII_MODE_TX_ENABLE |
999 MAC_RGMII_MODE_TX_LOWPWR |
1000 MAC_RGMII_MODE_TX_RESET);
fcb389df 1001 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1002 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1003 val |= MAC_RGMII_MODE_RX_INT_B |
1004 MAC_RGMII_MODE_RX_QUALITY |
1005 MAC_RGMII_MODE_RX_ACTIVITY |
1006 MAC_RGMII_MODE_RX_ENG_DET;
1007 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1008 val |= MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET;
1011 }
1012 tw32(MAC_EXT_RGMII_MODE, val);
1013}
1014
158d7abd
MC		 1015static void tg3_mdio_start(struct tg3 *tp)
1016{
158d7abd
MC		 1017 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1018 tw32_f(MAC_MI_MODE, tp->mi_mode);
1019 udelay(80);
a9daf367 1020
882e9793
MC		 1021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1022 u32 funcnum, is_serdes;
1023
1024 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1025 if (funcnum)
1026 tp->phy_addr = 2;
1027 else
1028 tp->phy_addr = 1;
1029
1030 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1031 if (is_serdes)
1032 tp->phy_addr += 7;
1033 } else
3f0e3ad7 1034 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1035
9c61d6bc
MC		 1036 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038 tg3_mdio_config_5785(tp);
158d7abd
MC		 1039}
1040
158d7abd
MC		 1041static int tg3_mdio_init(struct tg3 *tp)
1042{
1043 int i;
1044 u32 reg;
a9daf367 1045 struct phy_device *phydev;
158d7abd
MC		 1046
1047 tg3_mdio_start(tp);
1048
1049 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1050 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1051 return 0;
1052
298cf9be
LB		 1053 tp->mdio_bus = mdiobus_alloc();
1054 if (tp->mdio_bus == NULL)
1055 return -ENOMEM;
158d7abd 1056
298cf9be
LB		 1057 tp->mdio_bus->name = "tg3 mdio bus";
1058 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1059 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1060 tp->mdio_bus->priv = tp;
1061 tp->mdio_bus->parent = &tp->pdev->dev;
1062 tp->mdio_bus->read = &tg3_mdio_read;
1063 tp->mdio_bus->write = &tg3_mdio_write;
1064 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1065 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1066 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1067
1068 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1069 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1070
1071 /* The bus registration will look for all the PHYs on the mdio bus.
1072 * Unfortunately, it does not ensure the PHY is powered up before
1073 * accessing the PHY ID registers. A chip reset is the
1074 * quickest way to bring the device back to an operational state..
1075 */
1076 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1077 tg3_bmcr_reset(tp);
1078
298cf9be 1079 i = mdiobus_register(tp->mdio_bus);
a9daf367 1080 if (i) {
158d7abd
MC		 1081 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1082 tp->dev->name, i);
9c61d6bc 1083 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1084 return i;
1085 }
158d7abd 1086
3f0e3ad7 1087 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1088
9c61d6bc
MC		 1089 if (!phydev || !phydev->drv) {
1090 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1091 mdiobus_unregister(tp->mdio_bus);
1092 mdiobus_free(tp->mdio_bus);
1093 return -ENODEV;
1094 }
1095
1096 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1097 case TG3_PHY_ID_BCM57780:
1098 phydev->interface = PHY_INTERFACE_MODE_GMII;
1099 break;
a9daf367 1100 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1101 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1102 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1103 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1104 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1105 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1106 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1107 /* fallthru */
1108 case TG3_PHY_ID_RTL8211C:
1109 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1110 break;
fcb389df 1111 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1112 case TG3_PHY_ID_BCMAC131:
1113 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1114 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1115 break;
1116 }
1117
9c61d6bc
MC		 1118 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1119
1120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1121 tg3_mdio_config_5785(tp);
a9daf367
MC		 1122
1123 return 0;
158d7abd
MC		 1124}
1125
1126static void tg3_mdio_fini(struct tg3 *tp)
1127{
1128 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1129 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1130 mdiobus_unregister(tp->mdio_bus);
1131 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1132 }
1133}
1134
4ba526ce
MC		 1135/* tp->lock is held. */
1136static inline void tg3_generate_fw_event(struct tg3 *tp)
1137{
1138 u32 val;
1139
1140 val = tr32(GRC_RX_CPU_EVENT);
1141 val |= GRC_RX_CPU_DRIVER_EVENT;
1142 tw32_f(GRC_RX_CPU_EVENT, val);
1143
1144 tp->last_event_jiffies = jiffies;
1145}
1146
1147#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1148
95e2869a
MC		 1149/* tp->lock is held. */
1150static void tg3_wait_for_event_ack(struct tg3 *tp)
1151{
1152 int i;
4ba526ce
MC		 1153 unsigned int delay_cnt;
1154 long time_remain;
1155
1156 /* If enough time has passed, no wait is necessary. */
1157 time_remain = (long)(tp->last_event_jiffies + 1 +
1158 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1159 (long)jiffies;
1160 if (time_remain < 0)
1161 return;
1162
1163 /* Check if we can shorten the wait time. */
1164 delay_cnt = jiffies_to_usecs(time_remain);
1165 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1166 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1167 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1168
4ba526ce 1169 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1170 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1171 break;
4ba526ce 1172 udelay(8);
95e2869a
MC		 1173 }
1174}
1175
1176/* tp->lock is held. */
1177static void tg3_ump_link_report(struct tg3 *tp)
1178{
1179 u32 reg;
1180 u32 val;
1181
1182 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1183 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1184 return;
1185
1186 tg3_wait_for_event_ack(tp);
1187
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1189
1190 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1191
1192 val = 0;
1193 if (!tg3_readphy(tp, MII_BMCR, &reg))
1194 val = reg << 16;
1195 if (!tg3_readphy(tp, MII_BMSR, &reg))
1196 val |= (reg & 0xffff);
1197 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1198
1199 val = 0;
1200 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1201 val = reg << 16;
1202 if (!tg3_readphy(tp, MII_LPA, &reg))
1203 val |= (reg & 0xffff);
1204 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1205
1206 val = 0;
1207 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1208 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1209 val = reg << 16;
1210 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1211 val |= (reg & 0xffff);
1212 }
1213 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1214
1215 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1216 val = reg << 16;
1217 else
1218 val = 0;
1219 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1220
4ba526ce 1221 tg3_generate_fw_event(tp);
95e2869a
MC		 1222}
1223
1224static void tg3_link_report(struct tg3 *tp)
1225{
1226 if (!netif_carrier_ok(tp->dev)) {
1227 if (netif_msg_link(tp))
1228 printk(KERN_INFO PFX "%s: Link is down.\n",
1229 tp->dev->name);
1230 tg3_ump_link_report(tp);
1231 } else if (netif_msg_link(tp)) {
1232 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1233 tp->dev->name,
1234 (tp->link_config.active_speed == SPEED_1000 ?
1235 1000 :
1236 (tp->link_config.active_speed == SPEED_100 ?
1237 100 : 10)),
1238 (tp->link_config.active_duplex == DUPLEX_FULL ?
1239 "full" : "half"));
1240
1241 printk(KERN_INFO PFX
1242 "%s: Flow control is %s for TX and %s for RX.\n",
1243 tp->dev->name,
e18ce346 1244 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1245 "on" : "off",
e18ce346 1246 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1247 "on" : "off");
1248 tg3_ump_link_report(tp);
1249 }
1250}
1251
1252static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1253{
1254 u16 miireg;
1255
e18ce346 1256 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1257 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1258 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1259 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1260 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1261 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1262 else
1263 miireg = 0;
1264
1265 return miireg;
1266}
1267
1268static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1269{
1270 u16 miireg;
1271
e18ce346 1272 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1273 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1274 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1275 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1276 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1277 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1278 else
1279 miireg = 0;
1280
1281 return miireg;
1282}
1283
95e2869a
MC		 1284static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1285{
1286 u8 cap = 0;
1287
1288 if (lcladv & ADVERTISE_1000XPAUSE) {
1289 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1290 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1291 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1292 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1293 cap = FLOW_CTRL_RX;
95e2869a
MC		 1294 } else {
1295 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1296 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1297 }
1298 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1299 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1300 cap = FLOW_CTRL_TX;
95e2869a
MC		 1301 }
1302
1303 return cap;
1304}
1305
f51f3562 1306static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1307{
b02fd9e3 1308 u8 autoneg;
f51f3562 1309 u8 flowctrl = 0;
95e2869a
MC		 1310 u32 old_rx_mode = tp->rx_mode;
1311 u32 old_tx_mode = tp->tx_mode;
1312
b02fd9e3 1313 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1314 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1315 else
1316 autoneg = tp->link_config.autoneg;
1317
1318 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1319 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1320 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1321 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1322 else
bc02ff95 1323 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1324 } else
1325 flowctrl = tp->link_config.flowctrl;
95e2869a 1326
f51f3562 1327 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1328
e18ce346 1329 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1330 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1331 else
1332 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1333
f51f3562 1334 if (old_rx_mode != tp->rx_mode)
95e2869a 1335 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1336
e18ce346 1337 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1338 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1339 else
1340 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1341
f51f3562 1342 if (old_tx_mode != tp->tx_mode)
95e2869a 1343 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1344}
1345
b02fd9e3
MC		 1346static void tg3_adjust_link(struct net_device *dev)
1347{
1348 u8 oldflowctrl, linkmesg = 0;
1349 u32 mac_mode, lcl_adv, rmt_adv;
1350 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1351 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1352
24bb4fb6 1353 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1354
1355 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1356 MAC_MODE_HALF_DUPLEX);
1357
1358 oldflowctrl = tp->link_config.active_flowctrl;
1359
1360 if (phydev->link) {
1361 lcl_adv = 0;
1362 rmt_adv = 0;
1363
1364 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1365 mac_mode |= MAC_MODE_PORT_MODE_MII;
1366 else
1367 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1368
1369 if (phydev->duplex == DUPLEX_HALF)
1370 mac_mode |= MAC_MODE_HALF_DUPLEX;
1371 else {
1372 lcl_adv = tg3_advert_flowctrl_1000T(
1373 tp->link_config.flowctrl);
1374
1375 if (phydev->pause)
1376 rmt_adv = LPA_PAUSE_CAP;
1377 if (phydev->asym_pause)
1378 rmt_adv |= LPA_PAUSE_ASYM;
1379 }
1380
1381 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1382 } else
1383 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1384
1385 if (mac_mode != tp->mac_mode) {
1386 tp->mac_mode = mac_mode;
1387 tw32_f(MAC_MODE, tp->mac_mode);
1388 udelay(40);
1389 }
1390
fcb389df
MC		 1391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1392 if (phydev->speed == SPEED_10)
1393 tw32(MAC_MI_STAT,
1394 MAC_MI_STAT_10MBPS_MODE |
1395 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1396 else
1397 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1398 }
1399
b02fd9e3
MC		 1400 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1401 tw32(MAC_TX_LENGTHS,
1402 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1403 (6 << TX_LENGTHS_IPG_SHIFT) |
1404 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1405 else
1406 tw32(MAC_TX_LENGTHS,
1407 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1408 (6 << TX_LENGTHS_IPG_SHIFT) |
1409 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1410
1411 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1412 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1413 phydev->speed != tp->link_config.active_speed ||
1414 phydev->duplex != tp->link_config.active_duplex ||
1415 oldflowctrl != tp->link_config.active_flowctrl)
1416 linkmesg = 1;
1417
1418 tp->link_config.active_speed = phydev->speed;
1419 tp->link_config.active_duplex = phydev->duplex;
1420
24bb4fb6 1421 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1422
1423 if (linkmesg)
1424 tg3_link_report(tp);
1425}
1426
1427static int tg3_phy_init(struct tg3 *tp)
1428{
1429 struct phy_device *phydev;
1430
1431 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1432 return 0;
1433
1434 /* Bring the PHY back to a known state. */
1435 tg3_bmcr_reset(tp);
1436
3f0e3ad7 1437 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1438
1439 /* Attach the MAC to the PHY. */
fb28ad35 1440 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1441 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1442 if (IS_ERR(phydev)) {
1443 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1444 return PTR_ERR(phydev);
1445 }
1446
b02fd9e3 1447 /* Mask with MAC supported features. */
9c61d6bc
MC		 1448 switch (phydev->interface) {
1449 case PHY_INTERFACE_MODE_GMII:
1450 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1451 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1452 phydev->supported &= (PHY_GBIT_FEATURES |
1453 SUPPORTED_Pause |
1454 SUPPORTED_Asym_Pause);
1455 break;
1456 }
1457 /* fallthru */
9c61d6bc
MC		 1458 case PHY_INTERFACE_MODE_MII:
1459 phydev->supported &= (PHY_BASIC_FEATURES |
1460 SUPPORTED_Pause |
1461 SUPPORTED_Asym_Pause);
1462 break;
1463 default:
3f0e3ad7 1464 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1465 return -EINVAL;
1466 }
1467
1468 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1469
1470 phydev->advertising = phydev->supported;
1471
b02fd9e3
MC		 1472 return 0;
1473}
1474
1475static void tg3_phy_start(struct tg3 *tp)
1476{
1477 struct phy_device *phydev;
1478
1479 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1480 return;
1481
3f0e3ad7 1482 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1483
1484 if (tp->link_config.phy_is_low_power) {
1485 tp->link_config.phy_is_low_power = 0;
1486 phydev->speed = tp->link_config.orig_speed;
1487 phydev->duplex = tp->link_config.orig_duplex;
1488 phydev->autoneg = tp->link_config.orig_autoneg;
1489 phydev->advertising = tp->link_config.orig_advertising;
1490 }
1491
1492 phy_start(phydev);
1493
1494 phy_start_aneg(phydev);
1495}
1496
1497static void tg3_phy_stop(struct tg3 *tp)
1498{
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
3f0e3ad7 1502 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1503}
1504
1505static void tg3_phy_fini(struct tg3 *tp)
1506{
1507 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1508 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1509 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1510 }
1511}
1512
b2a5c19c
MC		 1513static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1514{
1515 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1516 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1517}
1518
7f97a4bd
MC		 1519static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1520{
1521 u32 phytest;
1522
1523 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1524 u32 phy;
1525
1526 tg3_writephy(tp, MII_TG3_FET_TEST,
1527 phytest | MII_TG3_FET_SHADOW_EN);
1528 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1531 else
1532 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1533 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1534 }
1535 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1536 }
1537}
1538
6833c043
MC		 1539static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1540{
1541 u32 reg;
1542
7f97a4bd 1543 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1544 return;
1545
7f97a4bd
MC		 1546 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1547 tg3_phy_fet_toggle_apd(tp, enable);
1548 return;
1549 }
1550
6833c043
MC		 1551 reg = MII_TG3_MISC_SHDW_WREN |
1552 MII_TG3_MISC_SHDW_SCR5_SEL |
1553 MII_TG3_MISC_SHDW_SCR5_LPED |
1554 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1555 MII_TG3_MISC_SHDW_SCR5_SDTL |
1556 MII_TG3_MISC_SHDW_SCR5_C125OE;
1557 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1558 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1559
1560 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1561
1562
1563 reg = MII_TG3_MISC_SHDW_WREN |
1564 MII_TG3_MISC_SHDW_APD_SEL |
1565 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1566 if (enable)
1567 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1568
1569 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1570}
1571
9ef8ca99
MC		 1572static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1573{
1574 u32 phy;
1575
1576 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1577 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1578 return;
1579
7f97a4bd 1580 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1581 u32 ephy;
1582
535ef6e1
MC		 1583 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1584 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1585
1586 tg3_writephy(tp, MII_TG3_FET_TEST,
1587 ephy | MII_TG3_FET_SHADOW_EN);
1588 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1589 if (enable)
535ef6e1 1590 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1591 else
535ef6e1
MC		 1592 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1593 tg3_writephy(tp, reg, phy);
9ef8ca99 1594 }
535ef6e1 1595 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1596 }
1597 } else {
1598 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1599 MII_TG3_AUXCTL_SHDWSEL_MISC;
1600 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1601 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1602 if (enable)
1603 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1604 else
1605 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1606 phy |= MII_TG3_AUXCTL_MISC_WREN;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608 }
1609 }
1610}
1611
1da177e4
LT		 1612static void tg3_phy_set_wirespeed(struct tg3 *tp)
1613{
1614 u32 val;
1615
1616 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1617 return;
1618
1619 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1620 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1621 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1622 (val | (1 << 15) | (1 << 4)));
1623}
1624
b2a5c19c
MC		 1625static void tg3_phy_apply_otp(struct tg3 *tp)
1626{
1627 u32 otp, phy;
1628
1629 if (!tp->phy_otp)
1630 return;
1631
1632 otp = tp->phy_otp;
1633
1634 /* Enable SM_DSP clock and tx 6dB coding. */
1635 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1636 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1637 MII_TG3_AUXCTL_ACTL_TX_6DB;
1638 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1639
1640 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1641 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1642 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1643
1644 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1645 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1646 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1647
1648 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1649 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1650 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1651
1652 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1653 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1654
1655 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1656 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1657
1658 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1659 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1660 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1661
1662 /* Turn off SM_DSP clock. */
1663 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1664 MII_TG3_AUXCTL_ACTL_TX_6DB;
1665 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1666}
1667
1da177e4
LT		 1668static int tg3_wait_macro_done(struct tg3 *tp)
1669{
1670 int limit = 100;
1671
1672 while (limit--) {
1673 u32 tmp32;
1674
1675 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1676 if ((tmp32 & 0x1000) == 0)
1677 break;
1678 }
1679 }
d4675b52 1680 if (limit < 0)
1da177e4
LT		 1681 return -EBUSY;
1682
1683 return 0;
1684}
1685
1686static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1687{
1688 static const u32 test_pat[4][6] = {
1689 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1690 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1691 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1692 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1693 };
1694 int chan;
1695
1696 for (chan = 0; chan < 4; chan++) {
1697 int i;
1698
1699 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1700 (chan * 0x2000) | 0x0200);
1701 tg3_writephy(tp, 0x16, 0x0002);
1702
1703 for (i = 0; i < 6; i++)
1704 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1705 test_pat[chan][i]);
1706
1707 tg3_writephy(tp, 0x16, 0x0202);
1708 if (tg3_wait_macro_done(tp)) {
1709 *resetp = 1;
1710 return -EBUSY;
1711 }
1712
1713 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1714 (chan * 0x2000) | 0x0200);
1715 tg3_writephy(tp, 0x16, 0x0082);
1716 if (tg3_wait_macro_done(tp)) {
1717 *resetp = 1;
1718 return -EBUSY;
1719 }
1720
1721 tg3_writephy(tp, 0x16, 0x0802);
1722 if (tg3_wait_macro_done(tp)) {
1723 *resetp = 1;
1724 return -EBUSY;
1725 }
1726
1727 for (i = 0; i < 6; i += 2) {
1728 u32 low, high;
1729
1730 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1731 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1732 tg3_wait_macro_done(tp)) {
1733 *resetp = 1;
1734 return -EBUSY;
1735 }
1736 low &= 0x7fff;
1737 high &= 0x000f;
1738 if (low != test_pat[chan][i] ||
1739 high != test_pat[chan][i+1]) {
1740 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1741 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1742 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1743
1744 return -EBUSY;
1745 }
1746 }
1747 }
1748
1749 return 0;
1750}
1751
1752static int tg3_phy_reset_chanpat(struct tg3 *tp)
1753{
1754 int chan;
1755
1756 for (chan = 0; chan < 4; chan++) {
1757 int i;
1758
1759 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1760 (chan * 0x2000) | 0x0200);
1761 tg3_writephy(tp, 0x16, 0x0002);
1762 for (i = 0; i < 6; i++)
1763 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1764 tg3_writephy(tp, 0x16, 0x0202);
1765 if (tg3_wait_macro_done(tp))
1766 return -EBUSY;
1767 }
1768
1769 return 0;
1770}
1771
1772static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1773{
1774 u32 reg32, phy9_orig;
1775 int retries, do_phy_reset, err;
1776
1777 retries = 10;
1778 do_phy_reset = 1;
1779 do {
1780 if (do_phy_reset) {
1781 err = tg3_bmcr_reset(tp);
1782 if (err)
1783 return err;
1784 do_phy_reset = 0;
1785 }
1786
1787 /* Disable transmitter and interrupt. */
1788 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1789 continue;
1790
1791 reg32 |= 0x3000;
1792 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1793
1794 /* Set full-duplex, 1000 mbps. */
1795 tg3_writephy(tp, MII_BMCR,
1796 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1797
1798 /* Set to master mode. */
1799 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1800 continue;
1801
1802 tg3_writephy(tp, MII_TG3_CTRL,
1803 (MII_TG3_CTRL_AS_MASTER |
1804 MII_TG3_CTRL_ENABLE_AS_MASTER));
1805
1806 /* Enable SM_DSP_CLOCK and 6dB. */
1807 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1808
1809 /* Block the PHY control access. */
1810 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1811 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1812
1813 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1814 if (!err)
1815 break;
1816 } while (--retries);
1817
1818 err = tg3_phy_reset_chanpat(tp);
1819 if (err)
1820 return err;
1821
1822 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1823 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1824
1825 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1826 tg3_writephy(tp, 0x16, 0x0000);
1827
1828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1829 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1830 /* Set Extended packet length bit for jumbo frames */
1831 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1832 }
1833 else {
1834 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1835 }
1836
1837 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1838
1839 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1840 reg32 &= ~0x3000;
1841 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1842 } else if (!err)
1843 err = -EBUSY;
1844
1845 return err;
1846}
1847
1848/* This will reset the tigon3 PHY if there is no valid
1849 * link unless the FORCE argument is non-zero.
1850 */
1851static int tg3_phy_reset(struct tg3 *tp)
1852{
b2a5c19c 1853 u32 cpmuctrl;
1da177e4
LT		 1854 u32 phy_status;
1855 int err;
1856
60189ddf
MC		 1857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1858 u32 val;
1859
1860 val = tr32(GRC_MISC_CFG);
1861 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1862 udelay(40);
1863 }
1da177e4
LT		 1864 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1865 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1866 if (err != 0)
1867 return -EBUSY;
1868
c8e1e82b
MC		 1869 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1870 netif_carrier_off(tp->dev);
1871 tg3_link_report(tp);
1872 }
1873
1da177e4
LT		 1874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1877 err = tg3_phy_reset_5703_4_5(tp);
1878 if (err)
1879 return err;
1880 goto out;
1881 }
1882
b2a5c19c
MC		 1883 cpmuctrl = 0;
1884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1885 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1886 cpmuctrl = tr32(TG3_CPMU_CTRL);
1887 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1888 tw32(TG3_CPMU_CTRL,
1889 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1890 }
1891
1da177e4
LT		 1892 err = tg3_bmcr_reset(tp);
1893 if (err)
1894 return err;
1895
b2a5c19c
MC		 1896 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1897 u32 phy;
1898
1899 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1900 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1901
1902 tw32(TG3_CPMU_CTRL, cpmuctrl);
1903 }
1904
bcb37f6c
MC		 1905 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1906 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1907 u32 val;
1908
1909 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1910 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1911 CPMU_LSPD_1000MB_MACCLK_12_5) {
1912 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1913 udelay(40);
1914 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1915 }
1916 }
1917
b2a5c19c
MC		 1918 tg3_phy_apply_otp(tp);
1919
6833c043
MC		 1920 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1921 tg3_phy_toggle_apd(tp, true);
1922 else
1923 tg3_phy_toggle_apd(tp, false);
1924
1da177e4
LT		 1925out:
1926 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1927 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1928 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1929 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1930 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1931 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1933 }
1934 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1935 tg3_writephy(tp, 0x1c, 0x8d68);
1936 tg3_writephy(tp, 0x1c, 0x8d68);
1937 }
1938 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1940 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1941 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1942 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1943 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1944 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1945 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1946 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1947 }
c424cb24
MC		 1948 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1949 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1951 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1953 tg3_writephy(tp, MII_TG3_TEST1,
1954 MII_TG3_TEST1_TRIM_EN | 0x4);
1955 } else
1956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958 }
1da177e4
LT		 1959 /* Set Extended packet length bit (bit 14) on all chips that */
1960 /* support jumbo frames */
1961 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1962 /* Cannot do read-modify-write on 5401 */
1963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1964 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1965 u32 phy_reg;
1966
1967 /* Set bit 14 with read-modify-write to preserve other bits */
1968 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1969 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1970 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1971 }
1972
1973 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1974 * jumbo frames transmission.
1975 */
8f666b07 1976 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1977 u32 phy_reg;
1978
1979 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1980 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1981 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1982 }
1983
715116a1 1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1985 /* adjust output voltage */
535ef6e1 1986 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1987 }
1988
9ef8ca99 1989 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1990 tg3_phy_set_wirespeed(tp);
1991 return 0;
1992}
1993
1994static void tg3_frob_aux_power(struct tg3 *tp)
1995{
1996 struct tg3 *tp_peer = tp;
1997
9d26e213 1998 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1999 return;
2000
f6eb9b1f
MC		 2001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2004 struct net_device *dev_peer;
2005
2006 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2007 /* remove_one() may have been run on the peer. */
8c2dc7e1 2008 if (!dev_peer)
bc1c7567
MC		 2009 tp_peer = tp;
2010 else
2011 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2012 }
2013
1da177e4 2014 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2015 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2016 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2017 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2020 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2021 (GRC_LCLCTRL_GPIO_OE0 |
2022 GRC_LCLCTRL_GPIO_OE1 |
2023 GRC_LCLCTRL_GPIO_OE2 |
2024 GRC_LCLCTRL_GPIO_OUTPUT0 |
2025 GRC_LCLCTRL_GPIO_OUTPUT1),
2026 100);
8d519ab2
MC		 2027 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2029 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2030 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2031 GRC_LCLCTRL_GPIO_OE1 |
2032 GRC_LCLCTRL_GPIO_OE2 |
2033 GRC_LCLCTRL_GPIO_OUTPUT0 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 tp->grc_local_ctrl;
2036 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2037
2038 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2039 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2040
2041 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2042 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2043 } else {
2044 u32 no_gpio2;
dc56b7d4 2045 u32 grc_local_ctrl = 0;
1da177e4
LT		 2046
2047 if (tp_peer != tp &&
2048 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2049 return;
2050
dc56b7d4
MC		 2051 /* Workaround to prevent overdrawing Amps. */
2052 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2053 ASIC_REV_5714) {
2054 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2055 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2056 grc_local_ctrl, 100);
dc56b7d4
MC		 2057 }
2058
1da177e4
LT		 2059 /* On 5753 and variants, GPIO2 cannot be used. */
2060 no_gpio2 = tp->nic_sram_data_cfg &
2061 NIC_SRAM_DATA_CFG_NO_GPIO2;
2062
dc56b7d4 2063 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2064 GRC_LCLCTRL_GPIO_OE1 |
2065 GRC_LCLCTRL_GPIO_OE2 |
2066 GRC_LCLCTRL_GPIO_OUTPUT1 |
2067 GRC_LCLCTRL_GPIO_OUTPUT2;
2068 if (no_gpio2) {
2069 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2070 GRC_LCLCTRL_GPIO_OUTPUT2);
2071 }
b401e9e2
MC		 2072 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2073 grc_local_ctrl, 100);
1da177e4
LT		 2074
2075 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2076
b401e9e2
MC		 2077 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2078 grc_local_ctrl, 100);
1da177e4
LT		 2079
2080 if (!no_gpio2) {
2081 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2082 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2083 grc_local_ctrl, 100);
1da177e4
LT		 2084 }
2085 }
2086 } else {
2087 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2088 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2089 if (tp_peer != tp &&
2090 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2091 return;
2092
b401e9e2
MC		 2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 (GRC_LCLCTRL_GPIO_OE1 |
2095 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2096
b401e9e2
MC		 2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2099
b401e9e2
MC		 2100 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2101 (GRC_LCLCTRL_GPIO_OE1 |
2102 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2103 }
2104 }
2105}
2106
e8f3f6ca
MC		 2107static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2108{
2109 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2110 return 1;
2111 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2112 if (speed != SPEED_10)
2113 return 1;
2114 } else if (speed == SPEED_10)
2115 return 1;
2116
2117 return 0;
2118}
2119
1da177e4
LT		 2120static int tg3_setup_phy(struct tg3 *, int);
2121
2122#define RESET_KIND_SHUTDOWN 0
2123#define RESET_KIND_INIT 1
2124#define RESET_KIND_SUSPEND 2
2125
2126static void tg3_write_sig_post_reset(struct tg3 *, int);
2127static int tg3_halt_cpu(struct tg3 *, u32);
2128
0a459aac 2129static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2130{
ce057f01
MC		 2131 u32 val;
2132
5129724a
MC		 2133 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2135 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2136 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2137
2138 sg_dig_ctrl |=
2139 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2140 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2141 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2142 }
3f7045c1 2143 return;
5129724a 2144 }
3f7045c1 2145
60189ddf 2146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2147 tg3_bmcr_reset(tp);
2148 val = tr32(GRC_MISC_CFG);
2149 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2150 udelay(40);
2151 return;
0a459aac 2152 } else if (do_low_power) {
715116a1
MC		 2153 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2154 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2155
2156 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2157 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2158 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2159 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2160 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2161 }
3f7045c1 2162
15c3b696
MC		 2163 /* The PHY should not be powered down on some chips because
2164 * of bugs.
2165 */
2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2167 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2168 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2169 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2170 return;
ce057f01 2171
bcb37f6c
MC		 2172 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2173 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2174 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2175 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2176 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2177 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2178 }
2179
15c3b696
MC		 2180 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2181}
2182
ffbcfed4
MC		 2183/* tp->lock is held. */
2184static int tg3_nvram_lock(struct tg3 *tp)
2185{
2186 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2187 int i;
2188
2189 if (tp->nvram_lock_cnt == 0) {
2190 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2191 for (i = 0; i < 8000; i++) {
2192 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2193 break;
2194 udelay(20);
2195 }
2196 if (i == 8000) {
2197 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2198 return -ENODEV;
2199 }
2200 }
2201 tp->nvram_lock_cnt++;
2202 }
2203 return 0;
2204}
2205
2206/* tp->lock is held. */
2207static void tg3_nvram_unlock(struct tg3 *tp)
2208{
2209 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2210 if (tp->nvram_lock_cnt > 0)
2211 tp->nvram_lock_cnt--;
2212 if (tp->nvram_lock_cnt == 0)
2213 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2214 }
2215}
2216
2217/* tp->lock is held. */
2218static void tg3_enable_nvram_access(struct tg3 *tp)
2219{
2220 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2221 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2222 u32 nvaccess = tr32(NVRAM_ACCESS);
2223
2224 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2225 }
2226}
2227
2228/* tp->lock is held. */
2229static void tg3_disable_nvram_access(struct tg3 *tp)
2230{
2231 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2232 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2233 u32 nvaccess = tr32(NVRAM_ACCESS);
2234
2235 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2236 }
2237}
2238
2239static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2240 u32 offset, u32 *val)
2241{
2242 u32 tmp;
2243 int i;
2244
2245 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2246 return -EINVAL;
2247
2248 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2249 EEPROM_ADDR_DEVID_MASK |
2250 EEPROM_ADDR_READ);
2251 tw32(GRC_EEPROM_ADDR,
2252 tmp |
2253 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2254 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2255 EEPROM_ADDR_ADDR_MASK) |
2256 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2257
2258 for (i = 0; i < 1000; i++) {
2259 tmp = tr32(GRC_EEPROM_ADDR);
2260
2261 if (tmp & EEPROM_ADDR_COMPLETE)
2262 break;
2263 msleep(1);
2264 }
2265 if (!(tmp & EEPROM_ADDR_COMPLETE))
2266 return -EBUSY;
2267
62cedd11
MC		 2268 tmp = tr32(GRC_EEPROM_DATA);
2269
2270 /*
2271 * The data will always be opposite the native endian
2272 * format. Perform a blind byteswap to compensate.
2273 */
2274 *val = swab32(tmp);
2275
ffbcfed4
MC		 2276 return 0;
2277}
2278
2279#define NVRAM_CMD_TIMEOUT 10000
2280
2281static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2282{
2283 int i;
2284
2285 tw32(NVRAM_CMD, nvram_cmd);
2286 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2287 udelay(10);
2288 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2289 udelay(10);
2290 break;
2291 }
2292 }
2293
2294 if (i == NVRAM_CMD_TIMEOUT)
2295 return -EBUSY;
2296
2297 return 0;
2298}
2299
2300static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2301{
2302 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2303 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2304 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2305 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2306 (tp->nvram_jedecnum == JEDEC_ATMEL))
2307
2308 addr = ((addr / tp->nvram_pagesize) <<
2309 ATMEL_AT45DB0X1B_PAGE_POS) +
2310 (addr % tp->nvram_pagesize);
2311
2312 return addr;
2313}
2314
2315static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2316{
2317 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2318 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2319 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2320 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2321 (tp->nvram_jedecnum == JEDEC_ATMEL))
2322
2323 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2324 tp->nvram_pagesize) +
2325 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2326
2327 return addr;
2328}
2329
e4f34110
MC		 2330/* NOTE: Data read in from NVRAM is byteswapped according to
2331 * the byteswapping settings for all other register accesses.
2332 * tg3 devices are BE devices, so on a BE machine, the data
2333 * returned will be exactly as it is seen in NVRAM. On a LE
2334 * machine, the 32-bit value will be byteswapped.
2335 */
ffbcfed4
MC		 2336static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2337{
2338 int ret;
2339
2340 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2341 return tg3_nvram_read_using_eeprom(tp, offset, val);
2342
2343 offset = tg3_nvram_phys_addr(tp, offset);
2344
2345 if (offset > NVRAM_ADDR_MSK)
2346 return -EINVAL;
2347
2348 ret = tg3_nvram_lock(tp);
2349 if (ret)
2350 return ret;
2351
2352 tg3_enable_nvram_access(tp);
2353
2354 tw32(NVRAM_ADDR, offset);
2355 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2356 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2357
2358 if (ret == 0)
e4f34110 2359 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2360
2361 tg3_disable_nvram_access(tp);
2362
2363 tg3_nvram_unlock(tp);
2364
2365 return ret;
2366}
2367
a9dc529d
MC		 2368/* Ensures NVRAM data is in bytestream format. */
2369static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2370{
2371 u32 v;
a9dc529d 2372 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2373 if (!res)
a9dc529d 2374 *val = cpu_to_be32(v);
ffbcfed4
MC		 2375 return res;
2376}
2377
3f007891
MC		 2378/* tp->lock is held. */
2379static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2380{
2381 u32 addr_high, addr_low;
2382 int i;
2383
2384 addr_high = ((tp->dev->dev_addr[0] << 8) |
2385 tp->dev->dev_addr[1]);
2386 addr_low = ((tp->dev->dev_addr[2] << 24) |
2387 (tp->dev->dev_addr[3] << 16) |
2388 (tp->dev->dev_addr[4] << 8) |
2389 (tp->dev->dev_addr[5] << 0));
2390 for (i = 0; i < 4; i++) {
2391 if (i == 1 && skip_mac_1)
2392 continue;
2393 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2394 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2395 }
2396
2397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2399 for (i = 0; i < 12; i++) {
2400 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2401 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2402 }
2403 }
2404
2405 addr_high = (tp->dev->dev_addr[0] +
2406 tp->dev->dev_addr[1] +
2407 tp->dev->dev_addr[2] +
2408 tp->dev->dev_addr[3] +
2409 tp->dev->dev_addr[4] +
2410 tp->dev->dev_addr[5]) &
2411 TX_BACKOFF_SEED_MASK;
2412 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2413}
2414
bc1c7567 2415static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2416{
2417 u32 misc_host_ctrl;
0a459aac 2418 bool device_should_wake, do_low_power;
1da177e4
LT		 2419
2420 /* Make sure register accesses (indirect or otherwise)
2421 * will function correctly.
2422 */
2423 pci_write_config_dword(tp->pdev,
2424 TG3PCI_MISC_HOST_CTRL,
2425 tp->misc_host_ctrl);
2426
1da177e4 2427 switch (state) {
bc1c7567 2428 case PCI_D0:
12dac075
RW		 2429 pci_enable_wake(tp->pdev, state, false);
2430 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2431
9d26e213
MC		 2432 /* Switch out of Vaux if it is a NIC */
2433 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2434 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2435
2436 return 0;
2437
bc1c7567 2438 case PCI_D1:
bc1c7567 2439 case PCI_D2:
bc1c7567 2440 case PCI_D3hot:
1da177e4
LT		 2441 break;
2442
2443 default:
12dac075
RW		 2444 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2445 tp->dev->name, state);
1da177e4 2446 return -EINVAL;
855e1111 2447 }
5e7dfd0f
MC		 2448
2449 /* Restore the CLKREQ setting. */
2450 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2451 u16 lnkctl;
2452
2453 pci_read_config_word(tp->pdev,
2454 tp->pcie_cap + PCI_EXP_LNKCTL,
2455 &lnkctl);
2456 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2457 pci_write_config_word(tp->pdev,
2458 tp->pcie_cap + PCI_EXP_LNKCTL,
2459 lnkctl);
2460 }
2461
1da177e4
LT		 2462 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2463 tw32(TG3PCI_MISC_HOST_CTRL,
2464 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2465
05ac4cb7
MC		 2466 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2467 device_may_wakeup(&tp->pdev->dev) &&
2468 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2469
dd477003 2470 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2471 do_low_power = false;
b02fd9e3
MC		 2472 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2473 !tp->link_config.phy_is_low_power) {
2474 struct phy_device *phydev;
0a459aac 2475 u32 phyid, advertising;
b02fd9e3 2476
3f0e3ad7 2477 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2478
2479 tp->link_config.phy_is_low_power = 1;
2480
2481 tp->link_config.orig_speed = phydev->speed;
2482 tp->link_config.orig_duplex = phydev->duplex;
2483 tp->link_config.orig_autoneg = phydev->autoneg;
2484 tp->link_config.orig_advertising = phydev->advertising;
2485
2486 advertising = ADVERTISED_TP |
2487 ADVERTISED_Pause |
2488 ADVERTISED_Autoneg |
2489 ADVERTISED_10baseT_Half;
2490
2491 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2492 device_should_wake) {
b02fd9e3
MC		 2493 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2494 advertising |=
2495 ADVERTISED_100baseT_Half |
2496 ADVERTISED_100baseT_Full |
2497 ADVERTISED_10baseT_Full;
2498 else
2499 advertising |= ADVERTISED_10baseT_Full;
2500 }
2501
2502 phydev->advertising = advertising;
2503
2504 phy_start_aneg(phydev);
0a459aac
MC		 2505
2506 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2507 if (phyid != TG3_PHY_ID_BCMAC131) {
2508 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2509 if (phyid == TG3_PHY_OUI_1 ||
2510 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2511 phyid == TG3_PHY_OUI_3)
2512 do_low_power = true;
2513 }
b02fd9e3 2514 }
dd477003 2515 } else {
2023276e 2516 do_low_power = true;
0a459aac 2517
dd477003
MC		 2518 if (tp->link_config.phy_is_low_power == 0) {
2519 tp->link_config.phy_is_low_power = 1;
2520 tp->link_config.orig_speed = tp->link_config.speed;
2521 tp->link_config.orig_duplex = tp->link_config.duplex;
2522 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2523 }
1da177e4 2524
dd477003
MC		 2525 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2526 tp->link_config.speed = SPEED_10;
2527 tp->link_config.duplex = DUPLEX_HALF;
2528 tp->link_config.autoneg = AUTONEG_ENABLE;
2529 tg3_setup_phy(tp, 0);
2530 }
1da177e4
LT		 2531 }
2532
b5d3772c
MC		 2533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2534 u32 val;
2535
2536 val = tr32(GRC_VCPU_EXT_CTRL);
2537 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2538 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2539 int i;
2540 u32 val;
2541
2542 for (i = 0; i < 200; i++) {
2543 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2544 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2545 break;
2546 msleep(1);
2547 }
2548 }
a85feb8c
GZ		 2549 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2550 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2551 WOL_DRV_STATE_SHUTDOWN |
2552 WOL_DRV_WOL |
2553 WOL_SET_MAGIC_PKT);
6921d201 2554
05ac4cb7 2555 if (device_should_wake) {
1da177e4
LT		 2556 u32 mac_mode;
2557
2558 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2559 if (do_low_power) {
dd477003
MC		 2560 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2561 udelay(40);
2562 }
1da177e4 2563
3f7045c1
MC		 2564 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2565 mac_mode = MAC_MODE_PORT_MODE_GMII;
2566 else
2567 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2568
e8f3f6ca
MC		 2569 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2570 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2571 ASIC_REV_5700) {
2572 u32 speed = (tp->tg3_flags &
2573 TG3_FLAG_WOL_SPEED_100MB) ?
2574 SPEED_100 : SPEED_10;
2575 if (tg3_5700_link_polarity(tp, speed))
2576 mac_mode |= MAC_MODE_LINK_POLARITY;
2577 else
2578 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2579 }
1da177e4
LT		 2580 } else {
2581 mac_mode = MAC_MODE_PORT_MODE_TBI;
2582 }
2583
cbf46853 2584 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2585 tw32(MAC_LED_CTRL, tp->led_ctrl);
2586
05ac4cb7
MC		 2587 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2588 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2589 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2590 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2591 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2592 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2593
3bda1258
MC		 2594 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2595 mac_mode |= tp->mac_mode &
2596 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2597 if (mac_mode & MAC_MODE_APE_TX_EN)
2598 mac_mode |= MAC_MODE_TDE_ENABLE;
2599 }
2600
1da177e4
LT		 2601 tw32_f(MAC_MODE, mac_mode);
2602 udelay(100);
2603
2604 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2605 udelay(10);
2606 }
2607
2608 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2609 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2611 u32 base_val;
2612
2613 base_val = tp->pci_clock_ctrl;
2614 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2615 CLOCK_CTRL_TXCLK_DISABLE);
2616
b401e9e2
MC		 2617 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2618 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2619 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2620 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2621 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2622 /* do nothing */
85e94ced 2623 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2624 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2625 u32 newbits1, newbits2;
2626
2627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2629 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2630 CLOCK_CTRL_TXCLK_DISABLE |
2631 CLOCK_CTRL_ALTCLK);
2632 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2633 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2634 newbits1 = CLOCK_CTRL_625_CORE;
2635 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2636 } else {
2637 newbits1 = CLOCK_CTRL_ALTCLK;
2638 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2639 }
2640
b401e9e2
MC		 2641 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2642 40);
1da177e4 2643
b401e9e2
MC		 2644 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2645 40);
1da177e4
LT		 2646
2647 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2648 u32 newbits3;
2649
2650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2652 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2653 CLOCK_CTRL_TXCLK_DISABLE |
2654 CLOCK_CTRL_44MHZ_CORE);
2655 } else {
2656 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2657 }
2658
b401e9e2
MC		 2659 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2660 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2661 }
2662 }
2663
05ac4cb7 2664 if (!(device_should_wake) &&
22435849 2665 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2666 tg3_power_down_phy(tp, do_low_power);
6921d201 2667
1da177e4
LT		 2668 tg3_frob_aux_power(tp);
2669
2670 /* Workaround for unstable PLL clock */
2671 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2672 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2673 u32 val = tr32(0x7d00);
2674
2675 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2676 tw32(0x7d00, val);
6921d201 2677 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2678 int err;
2679
2680 err = tg3_nvram_lock(tp);
1da177e4 2681 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2682 if (!err)
2683 tg3_nvram_unlock(tp);
6921d201 2684 }
1da177e4
LT		 2685 }
2686
bbadf503
MC		 2687 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2688
05ac4cb7 2689 if (device_should_wake)
12dac075
RW		 2690 pci_enable_wake(tp->pdev, state, true);
2691
1da177e4 2692 /* Finally, set the new power state. */
12dac075 2693 pci_set_power_state(tp->pdev, state);
1da177e4 2694
1da177e4
LT		 2695 return 0;
2696}
2697
1da177e4
LT		 2698static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2699{
2700 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2701 case MII_TG3_AUX_STAT_10HALF:
2702 *speed = SPEED_10;
2703 *duplex = DUPLEX_HALF;
2704 break;
2705
2706 case MII_TG3_AUX_STAT_10FULL:
2707 *speed = SPEED_10;
2708 *duplex = DUPLEX_FULL;
2709 break;
2710
2711 case MII_TG3_AUX_STAT_100HALF:
2712 *speed = SPEED_100;
2713 *duplex = DUPLEX_HALF;
2714 break;
2715
2716 case MII_TG3_AUX_STAT_100FULL:
2717 *speed = SPEED_100;
2718 *duplex = DUPLEX_FULL;
2719 break;
2720
2721 case MII_TG3_AUX_STAT_1000HALF:
2722 *speed = SPEED_1000;
2723 *duplex = DUPLEX_HALF;
2724 break;
2725
2726 case MII_TG3_AUX_STAT_1000FULL:
2727 *speed = SPEED_1000;
2728 *duplex = DUPLEX_FULL;
2729 break;
2730
2731 default:
7f97a4bd 2732 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2733 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2734 SPEED_10;
2735 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2736 DUPLEX_HALF;
2737 break;
2738 }
1da177e4
LT		 2739 *speed = SPEED_INVALID;
2740 *duplex = DUPLEX_INVALID;
2741 break;
855e1111 2742 }
1da177e4
LT		 2743}
2744
2745static void tg3_phy_copper_begin(struct tg3 *tp)
2746{
2747 u32 new_adv;
2748 int i;
2749
2750 if (tp->link_config.phy_is_low_power) {
2751 /* Entering low power mode. Disable gigabit and
2752 * 100baseT advertisements.
2753 */
2754 tg3_writephy(tp, MII_TG3_CTRL, 0);
2755
2756 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2757 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2758 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2759 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2760
2761 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2762 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2763 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2764 tp->link_config.advertising &=
2765 ~(ADVERTISED_1000baseT_Half |
2766 ADVERTISED_1000baseT_Full);
2767
ba4d07a8 2768 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2769 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2770 new_adv |= ADVERTISE_10HALF;
2771 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2772 new_adv |= ADVERTISE_10FULL;
2773 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2774 new_adv |= ADVERTISE_100HALF;
2775 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2776 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2777
2778 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2779
1da177e4
LT		 2780 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2781
2782 if (tp->link_config.advertising &
2783 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2784 new_adv = 0;
2785 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2786 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2787 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2788 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2789 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2790 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2791 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2792 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2793 MII_TG3_CTRL_ENABLE_AS_MASTER);
2794 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2795 } else {
2796 tg3_writephy(tp, MII_TG3_CTRL, 0);
2797 }
2798 } else {
ba4d07a8
MC		 2799 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2800 new_adv |= ADVERTISE_CSMA;
2801
1da177e4
LT		 2802 /* Asking for a specific link mode. */
2803 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2804 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2805
2806 if (tp->link_config.duplex == DUPLEX_FULL)
2807 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2808 else
2809 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2810 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2811 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2812 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2813 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2814 } else {
1da177e4
LT		 2815 if (tp->link_config.speed == SPEED_100) {
2816 if (tp->link_config.duplex == DUPLEX_FULL)
2817 new_adv |= ADVERTISE_100FULL;
2818 else
2819 new_adv |= ADVERTISE_100HALF;
2820 } else {
2821 if (tp->link_config.duplex == DUPLEX_FULL)
2822 new_adv |= ADVERTISE_10FULL;
2823 else
2824 new_adv |= ADVERTISE_10HALF;
2825 }
2826 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2827
2828 new_adv = 0;
1da177e4 2829 }
ba4d07a8
MC		 2830
2831 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2832 }
2833
2834 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2835 tp->link_config.speed != SPEED_INVALID) {
2836 u32 bmcr, orig_bmcr;
2837
2838 tp->link_config.active_speed = tp->link_config.speed;
2839 tp->link_config.active_duplex = tp->link_config.duplex;
2840
2841 bmcr = 0;
2842 switch (tp->link_config.speed) {
2843 default:
2844 case SPEED_10:
2845 break;
2846
2847 case SPEED_100:
2848 bmcr |= BMCR_SPEED100;
2849 break;
2850
2851 case SPEED_1000:
2852 bmcr |= TG3_BMCR_SPEED1000;
2853 break;
855e1111 2854 }
1da177e4
LT		 2855
2856 if (tp->link_config.duplex == DUPLEX_FULL)
2857 bmcr |= BMCR_FULLDPLX;
2858
2859 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2860 (bmcr != orig_bmcr)) {
2861 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2862 for (i = 0; i < 1500; i++) {
2863 u32 tmp;
2864
2865 udelay(10);
2866 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2867 tg3_readphy(tp, MII_BMSR, &tmp))
2868 continue;
2869 if (!(tmp & BMSR_LSTATUS)) {
2870 udelay(40);
2871 break;
2872 }
2873 }
2874 tg3_writephy(tp, MII_BMCR, bmcr);
2875 udelay(40);
2876 }
2877 } else {
2878 tg3_writephy(tp, MII_BMCR,
2879 BMCR_ANENABLE | BMCR_ANRESTART);
2880 }
2881}
2882
2883static int tg3_init_5401phy_dsp(struct tg3 *tp)
2884{
2885 int err;
2886
2887 /* Turn off tap power management. */
2888 /* Set Extended packet length bit */
2889 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2890
2891 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2892 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2893
2894 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2895 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2896
2897 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2898 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2899
2900 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2901 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2902
2903 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2904 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2905
2906 udelay(40);
2907
2908 return err;
2909}
2910
3600d918 2911static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2912{
3600d918
MC		 2913 u32 adv_reg, all_mask = 0;
2914
2915 if (mask & ADVERTISED_10baseT_Half)
2916 all_mask |= ADVERTISE_10HALF;
2917 if (mask & ADVERTISED_10baseT_Full)
2918 all_mask |= ADVERTISE_10FULL;
2919 if (mask & ADVERTISED_100baseT_Half)
2920 all_mask |= ADVERTISE_100HALF;
2921 if (mask & ADVERTISED_100baseT_Full)
2922 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2923
2924 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2925 return 0;
2926
1da177e4
LT		 2927 if ((adv_reg & all_mask) != all_mask)
2928 return 0;
2929 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2930 u32 tg3_ctrl;
2931
3600d918
MC		 2932 all_mask = 0;
2933 if (mask & ADVERTISED_1000baseT_Half)
2934 all_mask |= ADVERTISE_1000HALF;
2935 if (mask & ADVERTISED_1000baseT_Full)
2936 all_mask |= ADVERTISE_1000FULL;
2937
1da177e4
LT		 2938 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2939 return 0;
2940
1da177e4
LT		 2941 if ((tg3_ctrl & all_mask) != all_mask)
2942 return 0;
2943 }
2944 return 1;
2945}
2946
ef167e27
MC		 2947static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2948{
2949 u32 curadv, reqadv;
2950
2951 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2952 return 1;
2953
2954 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2955 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2956
2957 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2958 if (curadv != reqadv)
2959 return 0;
2960
2961 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2962 tg3_readphy(tp, MII_LPA, rmtadv);
2963 } else {
2964 /* Reprogram the advertisement register, even if it
2965 * does not affect the current link. If the link
2966 * gets renegotiated in the future, we can save an
2967 * additional renegotiation cycle by advertising
2968 * it correctly in the first place.
2969 */
2970 if (curadv != reqadv) {
2971 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2972 ADVERTISE_PAUSE_ASYM);
2973 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2974 }
2975 }
2976
2977 return 1;
2978}
2979
1da177e4
LT		 2980static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2981{
2982 int current_link_up;
2983 u32 bmsr, dummy;
ef167e27 2984 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2985 u16 current_speed;
2986 u8 current_duplex;
2987 int i, err;
2988
2989 tw32(MAC_EVENT, 0);
2990
2991 tw32_f(MAC_STATUS,
2992 (MAC_STATUS_SYNC_CHANGED |
2993 MAC_STATUS_CFG_CHANGED |
2994 MAC_STATUS_MI_COMPLETION |
2995 MAC_STATUS_LNKSTATE_CHANGED));
2996 udelay(40);
2997
8ef21428
MC		 2998 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2999 tw32_f(MAC_MI_MODE,
3000 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3001 udelay(80);
3002 }
1da177e4
LT		 3003
3004 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3005
3006 /* Some third-party PHYs need to be reset on link going
3007 * down.
3008 */
3009 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3012 netif_carrier_ok(tp->dev)) {
3013 tg3_readphy(tp, MII_BMSR, &bmsr);
3014 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3015 !(bmsr & BMSR_LSTATUS))
3016 force_reset = 1;
3017 }
3018 if (force_reset)
3019 tg3_phy_reset(tp);
3020
3021 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3022 tg3_readphy(tp, MII_BMSR, &bmsr);
3023 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3024 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3025 bmsr = 0;
3026
3027 if (!(bmsr & BMSR_LSTATUS)) {
3028 err = tg3_init_5401phy_dsp(tp);
3029 if (err)
3030 return err;
3031
3032 tg3_readphy(tp, MII_BMSR, &bmsr);
3033 for (i = 0; i < 1000; i++) {
3034 udelay(10);
3035 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3036 (bmsr & BMSR_LSTATUS)) {
3037 udelay(40);
3038 break;
3039 }
3040 }
3041
3042 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3043 !(bmsr & BMSR_LSTATUS) &&
3044 tp->link_config.active_speed == SPEED_1000) {
3045 err = tg3_phy_reset(tp);
3046 if (!err)
3047 err = tg3_init_5401phy_dsp(tp);
3048 if (err)
3049 return err;
3050 }
3051 }
3052 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3053 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3054 /* 5701 {A0,B0} CRC bug workaround */
3055 tg3_writephy(tp, 0x15, 0x0a75);
3056 tg3_writephy(tp, 0x1c, 0x8c68);
3057 tg3_writephy(tp, 0x1c, 0x8d68);
3058 tg3_writephy(tp, 0x1c, 0x8c68);
3059 }
3060
3061 /* Clear pending interrupts... */
3062 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3063 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3064
3065 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3066 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3067 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3068 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3069
3070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3072 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3073 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3074 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3075 else
3076 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3077 }
3078
3079 current_link_up = 0;
3080 current_speed = SPEED_INVALID;
3081 current_duplex = DUPLEX_INVALID;
3082
3083 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3084 u32 val;
3085
3086 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3087 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3088 if (!(val & (1 << 10))) {
3089 val |= (1 << 10);
3090 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3091 goto relink;
3092 }
3093 }
3094
3095 bmsr = 0;
3096 for (i = 0; i < 100; i++) {
3097 tg3_readphy(tp, MII_BMSR, &bmsr);
3098 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3099 (bmsr & BMSR_LSTATUS))
3100 break;
3101 udelay(40);
3102 }
3103
3104 if (bmsr & BMSR_LSTATUS) {
3105 u32 aux_stat, bmcr;
3106
3107 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3108 for (i = 0; i < 2000; i++) {
3109 udelay(10);
3110 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3111 aux_stat)
3112 break;
3113 }
3114
3115 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3116 &current_speed,
3117 &current_duplex);
3118
3119 bmcr = 0;
3120 for (i = 0; i < 200; i++) {
3121 tg3_readphy(tp, MII_BMCR, &bmcr);
3122 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3123 continue;
3124 if (bmcr && bmcr != 0x7fff)
3125 break;
3126 udelay(10);
3127 }
3128
ef167e27
MC		 3129 lcl_adv = 0;
3130 rmt_adv = 0;
1da177e4 3131
ef167e27
MC		 3132 tp->link_config.active_speed = current_speed;
3133 tp->link_config.active_duplex = current_duplex;
3134
3135 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3136 if ((bmcr & BMCR_ANENABLE) &&
3137 tg3_copper_is_advertising_all(tp,
3138 tp->link_config.advertising)) {
3139 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3140 &rmt_adv))
3141 current_link_up = 1;
1da177e4
LT		 3142 }
3143 } else {
3144 if (!(bmcr & BMCR_ANENABLE) &&
3145 tp->link_config.speed == current_speed &&
ef167e27
MC		 3146 tp->link_config.duplex == current_duplex &&
3147 tp->link_config.flowctrl ==
3148 tp->link_config.active_flowctrl) {
1da177e4 3149 current_link_up = 1;
1da177e4
LT		 3150 }
3151 }
3152
ef167e27
MC		 3153 if (current_link_up == 1 &&
3154 tp->link_config.active_duplex == DUPLEX_FULL)
3155 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3156 }
3157
1da177e4 3158relink:
6921d201 3159 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3160 u32 tmp;
3161
3162 tg3_phy_copper_begin(tp);
3163
3164 tg3_readphy(tp, MII_BMSR, &tmp);
3165 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3166 (tmp & BMSR_LSTATUS))
3167 current_link_up = 1;
3168 }
3169
3170 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3171 if (current_link_up == 1) {
3172 if (tp->link_config.active_speed == SPEED_100 ||
3173 tp->link_config.active_speed == SPEED_10)
3174 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3175 else
3176 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3177 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3178 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3179 else
1da177e4
LT		 3180 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3181
3182 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3183 if (tp->link_config.active_duplex == DUPLEX_HALF)
3184 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3185
1da177e4 3186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3187 if (current_link_up == 1 &&
3188 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3189 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3190 else
3191 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3192 }
3193
3194 /* ??? Without this setting Netgear GA302T PHY does not
3195 * ??? send/receive packets...
3196 */
3197 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3198 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3199 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3200 tw32_f(MAC_MI_MODE, tp->mi_mode);
3201 udelay(80);
3202 }
3203
3204 tw32_f(MAC_MODE, tp->mac_mode);
3205 udelay(40);
3206
3207 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3208 /* Polled via timer. */
3209 tw32_f(MAC_EVENT, 0);
3210 } else {
3211 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3212 }
3213 udelay(40);
3214
3215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3216 current_link_up == 1 &&
3217 tp->link_config.active_speed == SPEED_1000 &&
3218 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3219 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3220 udelay(120);
3221 tw32_f(MAC_STATUS,
3222 (MAC_STATUS_SYNC_CHANGED |
3223 MAC_STATUS_CFG_CHANGED));
3224 udelay(40);
3225 tg3_write_mem(tp,
3226 NIC_SRAM_FIRMWARE_MBOX,
3227 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3228 }
3229
5e7dfd0f
MC		 3230 /* Prevent send BD corruption. */
3231 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3232 u16 oldlnkctl, newlnkctl;
3233
3234 pci_read_config_word(tp->pdev,
3235 tp->pcie_cap + PCI_EXP_LNKCTL,
3236 &oldlnkctl);
3237 if (tp->link_config.active_speed == SPEED_100 ||
3238 tp->link_config.active_speed == SPEED_10)
3239 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3240 else
3241 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3242 if (newlnkctl != oldlnkctl)
3243 pci_write_config_word(tp->pdev,
3244 tp->pcie_cap + PCI_EXP_LNKCTL,
3245 newlnkctl);
3246 }
3247
1da177e4
LT		 3248 if (current_link_up != netif_carrier_ok(tp->dev)) {
3249 if (current_link_up)
3250 netif_carrier_on(tp->dev);
3251 else
3252 netif_carrier_off(tp->dev);
3253 tg3_link_report(tp);
3254 }
3255
3256 return 0;
3257}
3258
3259struct tg3_fiber_aneginfo {
3260 int state;
3261#define ANEG_STATE_UNKNOWN 0
3262#define ANEG_STATE_AN_ENABLE 1
3263#define ANEG_STATE_RESTART_INIT 2
3264#define ANEG_STATE_RESTART 3
3265#define ANEG_STATE_DISABLE_LINK_OK 4
3266#define ANEG_STATE_ABILITY_DETECT_INIT 5
3267#define ANEG_STATE_ABILITY_DETECT 6
3268#define ANEG_STATE_ACK_DETECT_INIT 7
3269#define ANEG_STATE_ACK_DETECT 8
3270#define ANEG_STATE_COMPLETE_ACK_INIT 9
3271#define ANEG_STATE_COMPLETE_ACK 10
3272#define ANEG_STATE_IDLE_DETECT_INIT 11
3273#define ANEG_STATE_IDLE_DETECT 12
3274#define ANEG_STATE_LINK_OK 13
3275#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3276#define ANEG_STATE_NEXT_PAGE_WAIT 15
3277
3278 u32 flags;
3279#define MR_AN_ENABLE 0x00000001
3280#define MR_RESTART_AN 0x00000002
3281#define MR_AN_COMPLETE 0x00000004
3282#define MR_PAGE_RX 0x00000008
3283#define MR_NP_LOADED 0x00000010
3284#define MR_TOGGLE_TX 0x00000020
3285#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3286#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3287#define MR_LP_ADV_SYM_PAUSE 0x00000100
3288#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3289#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3290#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3291#define MR_LP_ADV_NEXT_PAGE 0x00001000
3292#define MR_TOGGLE_RX 0x00002000
3293#define MR_NP_RX 0x00004000
3294
3295#define MR_LINK_OK 0x80000000
3296
3297 unsigned long link_time, cur_time;
3298
3299 u32 ability_match_cfg;
3300 int ability_match_count;
3301
3302 char ability_match, idle_match, ack_match;
3303
3304 u32 txconfig, rxconfig;
3305#define ANEG_CFG_NP 0x00000080
3306#define ANEG_CFG_ACK 0x00000040
3307#define ANEG_CFG_RF2 0x00000020
3308#define ANEG_CFG_RF1 0x00000010
3309#define ANEG_CFG_PS2 0x00000001
3310#define ANEG_CFG_PS1 0x00008000
3311#define ANEG_CFG_HD 0x00004000
3312#define ANEG_CFG_FD 0x00002000
3313#define ANEG_CFG_INVAL 0x00001f06
3314
3315};
3316#define ANEG_OK 0
3317#define ANEG_DONE 1
3318#define ANEG_TIMER_ENAB 2
3319#define ANEG_FAILED -1
3320
3321#define ANEG_STATE_SETTLE_TIME 10000
3322
3323static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3324 struct tg3_fiber_aneginfo *ap)
3325{
5be73b47 3326 u16 flowctrl;
1da177e4
LT		 3327 unsigned long delta;
3328 u32 rx_cfg_reg;
3329 int ret;
3330
3331 if (ap->state == ANEG_STATE_UNKNOWN) {
3332 ap->rxconfig = 0;
3333 ap->link_time = 0;
3334 ap->cur_time = 0;
3335 ap->ability_match_cfg = 0;
3336 ap->ability_match_count = 0;
3337 ap->ability_match = 0;
3338 ap->idle_match = 0;
3339 ap->ack_match = 0;
3340 }
3341 ap->cur_time++;
3342
3343 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3344 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3345
3346 if (rx_cfg_reg != ap->ability_match_cfg) {
3347 ap->ability_match_cfg = rx_cfg_reg;
3348 ap->ability_match = 0;
3349 ap->ability_match_count = 0;
3350 } else {
3351 if (++ap->ability_match_count > 1) {
3352 ap->ability_match = 1;
3353 ap->ability_match_cfg = rx_cfg_reg;
3354 }
3355 }
3356 if (rx_cfg_reg & ANEG_CFG_ACK)
3357 ap->ack_match = 1;
3358 else
3359 ap->ack_match = 0;
3360
3361 ap->idle_match = 0;
3362 } else {
3363 ap->idle_match = 1;
3364 ap->ability_match_cfg = 0;
3365 ap->ability_match_count = 0;
3366 ap->ability_match = 0;
3367 ap->ack_match = 0;
3368
3369 rx_cfg_reg = 0;
3370 }
3371
3372 ap->rxconfig = rx_cfg_reg;
3373 ret = ANEG_OK;
3374
3375 switch(ap->state) {
3376 case ANEG_STATE_UNKNOWN:
3377 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3378 ap->state = ANEG_STATE_AN_ENABLE;
3379
3380 /* fallthru */
3381 case ANEG_STATE_AN_ENABLE:
3382 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3383 if (ap->flags & MR_AN_ENABLE) {
3384 ap->link_time = 0;
3385 ap->cur_time = 0;
3386 ap->ability_match_cfg = 0;
3387 ap->ability_match_count = 0;
3388 ap->ability_match = 0;
3389 ap->idle_match = 0;
3390 ap->ack_match = 0;
3391
3392 ap->state = ANEG_STATE_RESTART_INIT;
3393 } else {
3394 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3395 }
3396 break;
3397
3398 case ANEG_STATE_RESTART_INIT:
3399 ap->link_time = ap->cur_time;
3400 ap->flags &= ~(MR_NP_LOADED);
3401 ap->txconfig = 0;
3402 tw32(MAC_TX_AUTO_NEG, 0);
3403 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3404 tw32_f(MAC_MODE, tp->mac_mode);
3405 udelay(40);
3406
3407 ret = ANEG_TIMER_ENAB;
3408 ap->state = ANEG_STATE_RESTART;
3409
3410 /* fallthru */
3411 case ANEG_STATE_RESTART:
3412 delta = ap->cur_time - ap->link_time;
3413 if (delta > ANEG_STATE_SETTLE_TIME) {
3414 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3415 } else {
3416 ret = ANEG_TIMER_ENAB;
3417 }
3418 break;
3419
3420 case ANEG_STATE_DISABLE_LINK_OK:
3421 ret = ANEG_DONE;
3422 break;
3423
3424 case ANEG_STATE_ABILITY_DETECT_INIT:
3425 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3426 ap->txconfig = ANEG_CFG_FD;
3427 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3428 if (flowctrl & ADVERTISE_1000XPAUSE)
3429 ap->txconfig |= ANEG_CFG_PS1;
3430 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3431 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3432 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3433 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3434 tw32_f(MAC_MODE, tp->mac_mode);
3435 udelay(40);
3436
3437 ap->state = ANEG_STATE_ABILITY_DETECT;
3438 break;
3439
3440 case ANEG_STATE_ABILITY_DETECT:
3441 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3442 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3443 }
3444 break;
3445
3446 case ANEG_STATE_ACK_DETECT_INIT:
3447 ap->txconfig |= ANEG_CFG_ACK;
3448 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3449 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3450 tw32_f(MAC_MODE, tp->mac_mode);
3451 udelay(40);
3452
3453 ap->state = ANEG_STATE_ACK_DETECT;
3454
3455 /* fallthru */
3456 case ANEG_STATE_ACK_DETECT:
3457 if (ap->ack_match != 0) {
3458 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3459 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3460 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3461 } else {
3462 ap->state = ANEG_STATE_AN_ENABLE;
3463 }
3464 } else if (ap->ability_match != 0 &&
3465 ap->rxconfig == 0) {
3466 ap->state = ANEG_STATE_AN_ENABLE;
3467 }
3468 break;
3469
3470 case ANEG_STATE_COMPLETE_ACK_INIT:
3471 if (ap->rxconfig & ANEG_CFG_INVAL) {
3472 ret = ANEG_FAILED;
3473 break;
3474 }
3475 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3476 MR_LP_ADV_HALF_DUPLEX |
3477 MR_LP_ADV_SYM_PAUSE |
3478 MR_LP_ADV_ASYM_PAUSE |
3479 MR_LP_ADV_REMOTE_FAULT1 |
3480 MR_LP_ADV_REMOTE_FAULT2 |
3481 MR_LP_ADV_NEXT_PAGE |
3482 MR_TOGGLE_RX |
3483 MR_NP_RX);
3484 if (ap->rxconfig & ANEG_CFG_FD)
3485 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3486 if (ap->rxconfig & ANEG_CFG_HD)
3487 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3488 if (ap->rxconfig & ANEG_CFG_PS1)
3489 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3490 if (ap->rxconfig & ANEG_CFG_PS2)
3491 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3492 if (ap->rxconfig & ANEG_CFG_RF1)
3493 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3494 if (ap->rxconfig & ANEG_CFG_RF2)
3495 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3496 if (ap->rxconfig & ANEG_CFG_NP)
3497 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3498
3499 ap->link_time = ap->cur_time;
3500
3501 ap->flags ^= (MR_TOGGLE_TX);
3502 if (ap->rxconfig & 0x0008)
3503 ap->flags |= MR_TOGGLE_RX;
3504 if (ap->rxconfig & ANEG_CFG_NP)
3505 ap->flags |= MR_NP_RX;
3506 ap->flags |= MR_PAGE_RX;
3507
3508 ap->state = ANEG_STATE_COMPLETE_ACK;
3509 ret = ANEG_TIMER_ENAB;
3510 break;
3511
3512 case ANEG_STATE_COMPLETE_ACK:
3513 if (ap->ability_match != 0 &&
3514 ap->rxconfig == 0) {
3515 ap->state = ANEG_STATE_AN_ENABLE;
3516 break;
3517 }
3518 delta = ap->cur_time - ap->link_time;
3519 if (delta > ANEG_STATE_SETTLE_TIME) {
3520 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3521 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3522 } else {
3523 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3524 !(ap->flags & MR_NP_RX)) {
3525 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3526 } else {
3527 ret = ANEG_FAILED;
3528 }
3529 }
3530 }
3531 break;
3532
3533 case ANEG_STATE_IDLE_DETECT_INIT:
3534 ap->link_time = ap->cur_time;
3535 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3536 tw32_f(MAC_MODE, tp->mac_mode);
3537 udelay(40);
3538
3539 ap->state = ANEG_STATE_IDLE_DETECT;
3540 ret = ANEG_TIMER_ENAB;
3541 break;
3542
3543 case ANEG_STATE_IDLE_DETECT:
3544 if (ap->ability_match != 0 &&
3545 ap->rxconfig == 0) {
3546 ap->state = ANEG_STATE_AN_ENABLE;
3547 break;
3548 }
3549 delta = ap->cur_time - ap->link_time;
3550 if (delta > ANEG_STATE_SETTLE_TIME) {
3551 /* XXX another gem from the Broadcom driver :( */
3552 ap->state = ANEG_STATE_LINK_OK;
3553 }
3554 break;
3555
3556 case ANEG_STATE_LINK_OK:
3557 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3558 ret = ANEG_DONE;
3559 break;
3560
3561 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3562 /* ??? unimplemented */
3563 break;
3564
3565 case ANEG_STATE_NEXT_PAGE_WAIT:
3566 /* ??? unimplemented */
3567 break;
3568
3569 default:
3570 ret = ANEG_FAILED;
3571 break;
855e1111 3572 }
1da177e4
LT		 3573
3574 return ret;
3575}
3576
5be73b47 3577static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3578{
3579 int res = 0;
3580 struct tg3_fiber_aneginfo aninfo;
3581 int status = ANEG_FAILED;
3582 unsigned int tick;
3583 u32 tmp;
3584
3585 tw32_f(MAC_TX_AUTO_NEG, 0);
3586
3587 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3588 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3589 udelay(40);
3590
3591 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3592 udelay(40);
3593
3594 memset(&aninfo, 0, sizeof(aninfo));
3595 aninfo.flags |= MR_AN_ENABLE;
3596 aninfo.state = ANEG_STATE_UNKNOWN;
3597 aninfo.cur_time = 0;
3598 tick = 0;
3599 while (++tick < 195000) {
3600 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3601 if (status == ANEG_DONE || status == ANEG_FAILED)
3602 break;
3603
3604 udelay(1);
3605 }
3606
3607 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3608 tw32_f(MAC_MODE, tp->mac_mode);
3609 udelay(40);
3610
5be73b47
MC		 3611 *txflags = aninfo.txconfig;
3612 *rxflags = aninfo.flags;
1da177e4
LT		 3613
3614 if (status == ANEG_DONE &&
3615 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3616 MR_LP_ADV_FULL_DUPLEX)))
3617 res = 1;
3618
3619 return res;
3620}
3621
3622static void tg3_init_bcm8002(struct tg3 *tp)
3623{
3624 u32 mac_status = tr32(MAC_STATUS);
3625 int i;
3626
3627 /* Reset when initting first time or we have a link. */
3628 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3629 !(mac_status & MAC_STATUS_PCS_SYNCED))
3630 return;
3631
3632 /* Set PLL lock range. */
3633 tg3_writephy(tp, 0x16, 0x8007);
3634
3635 /* SW reset */
3636 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3637
3638 /* Wait for reset to complete. */
3639 /* XXX schedule_timeout() ... */
3640 for (i = 0; i < 500; i++)
3641 udelay(10);
3642
3643 /* Config mode; select PMA/Ch 1 regs. */
3644 tg3_writephy(tp, 0x10, 0x8411);
3645
3646 /* Enable auto-lock and comdet, select txclk for tx. */
3647 tg3_writephy(tp, 0x11, 0x0a10);
3648
3649 tg3_writephy(tp, 0x18, 0x00a0);
3650 tg3_writephy(tp, 0x16, 0x41ff);
3651
3652 /* Assert and deassert POR. */
3653 tg3_writephy(tp, 0x13, 0x0400);
3654 udelay(40);
3655 tg3_writephy(tp, 0x13, 0x0000);
3656
3657 tg3_writephy(tp, 0x11, 0x0a50);
3658 udelay(40);
3659 tg3_writephy(tp, 0x11, 0x0a10);
3660
3661 /* Wait for signal to stabilize */
3662 /* XXX schedule_timeout() ... */
3663 for (i = 0; i < 15000; i++)
3664 udelay(10);
3665
3666 /* Deselect the channel register so we can read the PHYID
3667 * later.
3668 */
3669 tg3_writephy(tp, 0x10, 0x8011);
3670}
3671
3672static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3673{
82cd3d11 3674 u16 flowctrl;
1da177e4
LT		 3675 u32 sg_dig_ctrl, sg_dig_status;
3676 u32 serdes_cfg, expected_sg_dig_ctrl;
3677 int workaround, port_a;
3678 int current_link_up;
3679
3680 serdes_cfg = 0;
3681 expected_sg_dig_ctrl = 0;
3682 workaround = 0;
3683 port_a = 1;
3684 current_link_up = 0;
3685
3686 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3687 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3688 workaround = 1;
3689 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3690 port_a = 0;
3691
3692 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3693 /* preserve bits 20-23 for voltage regulator */
3694 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3695 }
3696
3697 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3698
3699 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3700 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3701 if (workaround) {
3702 u32 val = serdes_cfg;
3703
3704 if (port_a)
3705 val |= 0xc010000;
3706 else
3707 val |= 0x4010000;
3708 tw32_f(MAC_SERDES_CFG, val);
3709 }
c98f6e3b
MC		 3710
3711 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3712 }
3713 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3714 tg3_setup_flow_control(tp, 0, 0);
3715 current_link_up = 1;
3716 }
3717 goto out;
3718 }
3719
3720 /* Want auto-negotiation. */
c98f6e3b 3721 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3722
82cd3d11
MC		 3723 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3724 if (flowctrl & ADVERTISE_1000XPAUSE)
3725 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3726 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3727 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3728
3729 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3730 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3731 tp->serdes_counter &&
3732 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3733 MAC_STATUS_RCVD_CFG)) ==
3734 MAC_STATUS_PCS_SYNCED)) {
3735 tp->serdes_counter--;
3736 current_link_up = 1;
3737 goto out;
3738 }
3739restart_autoneg:
1da177e4
LT		 3740 if (workaround)
3741 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3742 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3743 udelay(5);
3744 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3745
3d3ebe74
MC		 3746 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3747 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3748 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3749 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3750 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3751 mac_status = tr32(MAC_STATUS);
3752
c98f6e3b 3753 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3754 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3755 u32 local_adv = 0, remote_adv = 0;
3756
3757 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3758 local_adv |= ADVERTISE_1000XPAUSE;
3759 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3760 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3761
c98f6e3b 3762 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3763 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3764 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3765 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3766
3767 tg3_setup_flow_control(tp, local_adv, remote_adv);
3768 current_link_up = 1;
3d3ebe74
MC		 3769 tp->serdes_counter = 0;
3770 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3771 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3772 if (tp->serdes_counter)
3773 tp->serdes_counter--;
1da177e4
LT		 3774 else {
3775 if (workaround) {
3776 u32 val = serdes_cfg;
3777
3778 if (port_a)
3779 val |= 0xc010000;
3780 else
3781 val |= 0x4010000;
3782
3783 tw32_f(MAC_SERDES_CFG, val);
3784 }
3785
c98f6e3b 3786 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3787 udelay(40);
3788
3789 /* Link parallel detection - link is up */
3790 /* only if we have PCS_SYNC and not */
3791 /* receiving config code words */
3792 mac_status = tr32(MAC_STATUS);
3793 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3794 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3795 tg3_setup_flow_control(tp, 0, 0);
3796 current_link_up = 1;
3d3ebe74
MC		 3797 tp->tg3_flags2 |=
3798 TG3_FLG2_PARALLEL_DETECT;
3799 tp->serdes_counter =
3800 SERDES_PARALLEL_DET_TIMEOUT;
3801 } else
3802 goto restart_autoneg;
1da177e4
LT		 3803 }
3804 }
3d3ebe74
MC		 3805 } else {
3806 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3807 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3808 }
3809
3810out:
3811 return current_link_up;
3812}
3813
3814static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3815{
3816 int current_link_up = 0;
3817
5cf64b8a 3818 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3819 goto out;
1da177e4
LT		 3820
3821 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3822 u32 txflags, rxflags;
1da177e4 3823 int i;
6aa20a22 3824
5be73b47
MC		 3825 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3826 u32 local_adv = 0, remote_adv = 0;
1da177e4 3827
5be73b47
MC		 3828 if (txflags & ANEG_CFG_PS1)
3829 local_adv |= ADVERTISE_1000XPAUSE;
3830 if (txflags & ANEG_CFG_PS2)
3831 local_adv |= ADVERTISE_1000XPSE_ASYM;
3832
3833 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3834 remote_adv |= LPA_1000XPAUSE;
3835 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3836 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3837
3838 tg3_setup_flow_control(tp, local_adv, remote_adv);
3839
1da177e4
LT		 3840 current_link_up = 1;
3841 }
3842 for (i = 0; i < 30; i++) {
3843 udelay(20);
3844 tw32_f(MAC_STATUS,
3845 (MAC_STATUS_SYNC_CHANGED |
3846 MAC_STATUS_CFG_CHANGED));
3847 udelay(40);
3848 if ((tr32(MAC_STATUS) &
3849 (MAC_STATUS_SYNC_CHANGED |
3850 MAC_STATUS_CFG_CHANGED)) == 0)
3851 break;
3852 }
3853
3854 mac_status = tr32(MAC_STATUS);
3855 if (current_link_up == 0 &&
3856 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3857 !(mac_status & MAC_STATUS_RCVD_CFG))
3858 current_link_up = 1;
3859 } else {
5be73b47
MC		 3860 tg3_setup_flow_control(tp, 0, 0);
3861
1da177e4
LT		 3862 /* Forcing 1000FD link up. */
3863 current_link_up = 1;
1da177e4
LT		 3864
3865 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3866 udelay(40);
e8f3f6ca
MC		 3867
3868 tw32_f(MAC_MODE, tp->mac_mode);
3869 udelay(40);
1da177e4
LT		 3870 }
3871
3872out:
3873 return current_link_up;
3874}
3875
3876static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3877{
3878 u32 orig_pause_cfg;
3879 u16 orig_active_speed;
3880 u8 orig_active_duplex;
3881 u32 mac_status;
3882 int current_link_up;
3883 int i;
3884
8d018621 3885 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3886 orig_active_speed = tp->link_config.active_speed;
3887 orig_active_duplex = tp->link_config.active_duplex;
3888
3889 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3890 netif_carrier_ok(tp->dev) &&
3891 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3892 mac_status = tr32(MAC_STATUS);
3893 mac_status &= (MAC_STATUS_PCS_SYNCED |
3894 MAC_STATUS_SIGNAL_DET |
3895 MAC_STATUS_CFG_CHANGED |
3896 MAC_STATUS_RCVD_CFG);
3897 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3898 MAC_STATUS_SIGNAL_DET)) {
3899 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3900 MAC_STATUS_CFG_CHANGED));
3901 return 0;
3902 }
3903 }
3904
3905 tw32_f(MAC_TX_AUTO_NEG, 0);
3906
3907 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3908 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3909 tw32_f(MAC_MODE, tp->mac_mode);
3910 udelay(40);
3911
3912 if (tp->phy_id == PHY_ID_BCM8002)
3913 tg3_init_bcm8002(tp);
3914
3915 /* Enable link change event even when serdes polling. */
3916 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3917 udelay(40);
3918
3919 current_link_up = 0;
3920 mac_status = tr32(MAC_STATUS);
3921
3922 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3923 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3924 else
3925 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3926
898a56f8 3927 tp->napi[0].hw_status->status =
1da177e4 3928 (SD_STATUS_UPDATED |
898a56f8 3929 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3930
3931 for (i = 0; i < 100; i++) {
3932 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3933 MAC_STATUS_CFG_CHANGED));
3934 udelay(5);
3935 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3936 MAC_STATUS_CFG_CHANGED |
3937 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3938 break;
3939 }
3940
3941 mac_status = tr32(MAC_STATUS);
3942 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3943 current_link_up = 0;
3d3ebe74
MC		 3944 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3945 tp->serdes_counter == 0) {
1da177e4
LT		 3946 tw32_f(MAC_MODE, (tp->mac_mode |
3947 MAC_MODE_SEND_CONFIGS));
3948 udelay(1);
3949 tw32_f(MAC_MODE, tp->mac_mode);
3950 }
3951 }
3952
3953 if (current_link_up == 1) {
3954 tp->link_config.active_speed = SPEED_1000;
3955 tp->link_config.active_duplex = DUPLEX_FULL;
3956 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3957 LED_CTRL_LNKLED_OVERRIDE |
3958 LED_CTRL_1000MBPS_ON));
3959 } else {
3960 tp->link_config.active_speed = SPEED_INVALID;
3961 tp->link_config.active_duplex = DUPLEX_INVALID;
3962 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3963 LED_CTRL_LNKLED_OVERRIDE |
3964 LED_CTRL_TRAFFIC_OVERRIDE));
3965 }
3966
3967 if (current_link_up != netif_carrier_ok(tp->dev)) {
3968 if (current_link_up)
3969 netif_carrier_on(tp->dev);
3970 else
3971 netif_carrier_off(tp->dev);
3972 tg3_link_report(tp);
3973 } else {
8d018621 3974 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3975 if (orig_pause_cfg != now_pause_cfg ||
3976 orig_active_speed != tp->link_config.active_speed ||
3977 orig_active_duplex != tp->link_config.active_duplex)
3978 tg3_link_report(tp);
3979 }
3980
3981 return 0;
3982}
3983
747e8f8b
MC		 3984static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3985{
3986 int current_link_up, err = 0;
3987 u32 bmsr, bmcr;
3988 u16 current_speed;
3989 u8 current_duplex;
ef167e27 3990 u32 local_adv, remote_adv;
747e8f8b
MC		 3991
3992 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3993 tw32_f(MAC_MODE, tp->mac_mode);
3994 udelay(40);
3995
3996 tw32(MAC_EVENT, 0);
3997
3998 tw32_f(MAC_STATUS,
3999 (MAC_STATUS_SYNC_CHANGED |
4000 MAC_STATUS_CFG_CHANGED |
4001 MAC_STATUS_MI_COMPLETION |
4002 MAC_STATUS_LNKSTATE_CHANGED));
4003 udelay(40);
4004
4005 if (force_reset)
4006 tg3_phy_reset(tp);
4007
4008 current_link_up = 0;
4009 current_speed = SPEED_INVALID;
4010 current_duplex = DUPLEX_INVALID;
4011
4012 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4013 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4015 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4016 bmsr |= BMSR_LSTATUS;
4017 else
4018 bmsr &= ~BMSR_LSTATUS;
4019 }
747e8f8b
MC		 4020
4021 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4022
4023 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4024 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4025 /* do nothing, just check for link up at the end */
4026 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4027 u32 adv, new_adv;
4028
4029 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4030 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4031 ADVERTISE_1000XPAUSE |
4032 ADVERTISE_1000XPSE_ASYM |
4033 ADVERTISE_SLCT);
4034
ba4d07a8 4035 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4036
4037 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4038 new_adv |= ADVERTISE_1000XHALF;
4039 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4040 new_adv |= ADVERTISE_1000XFULL;
4041
4042 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4043 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4044 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4045 tg3_writephy(tp, MII_BMCR, bmcr);
4046
4047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4048 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4049 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4050
4051 return err;
4052 }
4053 } else {
4054 u32 new_bmcr;
4055
4056 bmcr &= ~BMCR_SPEED1000;
4057 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4058
4059 if (tp->link_config.duplex == DUPLEX_FULL)
4060 new_bmcr |= BMCR_FULLDPLX;
4061
4062 if (new_bmcr != bmcr) {
4063 /* BMCR_SPEED1000 is a reserved bit that needs
4064 * to be set on write.
4065 */
4066 new_bmcr |= BMCR_SPEED1000;
4067
4068 /* Force a linkdown */
4069 if (netif_carrier_ok(tp->dev)) {
4070 u32 adv;
4071
4072 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4073 adv &= ~(ADVERTISE_1000XFULL |
4074 ADVERTISE_1000XHALF |
4075 ADVERTISE_SLCT);
4076 tg3_writephy(tp, MII_ADVERTISE, adv);
4077 tg3_writephy(tp, MII_BMCR, bmcr |
4078 BMCR_ANRESTART |
4079 BMCR_ANENABLE);
4080 udelay(10);
4081 netif_carrier_off(tp->dev);
4082 }
4083 tg3_writephy(tp, MII_BMCR, new_bmcr);
4084 bmcr = new_bmcr;
4085 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4086 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4087 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4088 ASIC_REV_5714) {
4089 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4090 bmsr |= BMSR_LSTATUS;
4091 else
4092 bmsr &= ~BMSR_LSTATUS;
4093 }
747e8f8b
MC		 4094 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4095 }
4096 }
4097
4098 if (bmsr & BMSR_LSTATUS) {
4099 current_speed = SPEED_1000;
4100 current_link_up = 1;
4101 if (bmcr & BMCR_FULLDPLX)
4102 current_duplex = DUPLEX_FULL;
4103 else
4104 current_duplex = DUPLEX_HALF;
4105
ef167e27
MC		 4106 local_adv = 0;
4107 remote_adv = 0;
4108
747e8f8b 4109 if (bmcr & BMCR_ANENABLE) {
ef167e27 4110 u32 common;
747e8f8b
MC		 4111
4112 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4113 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4114 common = local_adv & remote_adv;
4115 if (common & (ADVERTISE_1000XHALF |
4116 ADVERTISE_1000XFULL)) {
4117 if (common & ADVERTISE_1000XFULL)
4118 current_duplex = DUPLEX_FULL;
4119 else
4120 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4121 }
4122 else
4123 current_link_up = 0;
4124 }
4125 }
4126
ef167e27
MC		 4127 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4128 tg3_setup_flow_control(tp, local_adv, remote_adv);
4129
747e8f8b
MC		 4130 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4131 if (tp->link_config.active_duplex == DUPLEX_HALF)
4132 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4133
4134 tw32_f(MAC_MODE, tp->mac_mode);
4135 udelay(40);
4136
4137 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4138
4139 tp->link_config.active_speed = current_speed;
4140 tp->link_config.active_duplex = current_duplex;
4141
4142 if (current_link_up != netif_carrier_ok(tp->dev)) {
4143 if (current_link_up)
4144 netif_carrier_on(tp->dev);
4145 else {
4146 netif_carrier_off(tp->dev);
4147 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4148 }
4149 tg3_link_report(tp);
4150 }
4151 return err;
4152}
4153
4154static void tg3_serdes_parallel_detect(struct tg3 *tp)
4155{
3d3ebe74 4156 if (tp->serdes_counter) {
747e8f8b 4157 /* Give autoneg time to complete. */
3d3ebe74 4158 tp->serdes_counter--;
747e8f8b
MC		 4159 return;
4160 }
4161 if (!netif_carrier_ok(tp->dev) &&
4162 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4163 u32 bmcr;
4164
4165 tg3_readphy(tp, MII_BMCR, &bmcr);
4166 if (bmcr & BMCR_ANENABLE) {
4167 u32 phy1, phy2;
4168
4169 /* Select shadow register 0x1f */
4170 tg3_writephy(tp, 0x1c, 0x7c00);
4171 tg3_readphy(tp, 0x1c, &phy1);
4172
4173 /* Select expansion interrupt status register */
4174 tg3_writephy(tp, 0x17, 0x0f01);
4175 tg3_readphy(tp, 0x15, &phy2);
4176 tg3_readphy(tp, 0x15, &phy2);
4177
4178 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4179 /* We have signal detect and not receiving
4180 * config code words, link is up by parallel
4181 * detection.
4182 */
4183
4184 bmcr &= ~BMCR_ANENABLE;
4185 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4186 tg3_writephy(tp, MII_BMCR, bmcr);
4187 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4188 }
4189 }
4190 }
4191 else if (netif_carrier_ok(tp->dev) &&
4192 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4193 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4194 u32 phy2;
4195
4196 /* Select expansion interrupt status register */
4197 tg3_writephy(tp, 0x17, 0x0f01);
4198 tg3_readphy(tp, 0x15, &phy2);
4199 if (phy2 & 0x20) {
4200 u32 bmcr;
4201
4202 /* Config code words received, turn on autoneg. */
4203 tg3_readphy(tp, MII_BMCR, &bmcr);
4204 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4205
4206 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4207
4208 }
4209 }
4210}
4211
1da177e4
LT		 4212static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4213{
4214 int err;
4215
4216 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4217 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4218 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4219 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4220 } else {
4221 err = tg3_setup_copper_phy(tp, force_reset);
4222 }
4223
bcb37f6c 4224 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4225 u32 val, scale;
4226
4227 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4228 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4229 scale = 65;
4230 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4231 scale = 6;
4232 else
4233 scale = 12;
4234
4235 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4236 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4237 tw32(GRC_MISC_CFG, val);
4238 }
4239
1da177e4
LT		 4240 if (tp->link_config.active_speed == SPEED_1000 &&
4241 tp->link_config.active_duplex == DUPLEX_HALF)
4242 tw32(MAC_TX_LENGTHS,
4243 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4244 (6 << TX_LENGTHS_IPG_SHIFT) |
4245 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4246 else
4247 tw32(MAC_TX_LENGTHS,
4248 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4249 (6 << TX_LENGTHS_IPG_SHIFT) |
4250 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4251
4252 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4253 if (netif_carrier_ok(tp->dev)) {
4254 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4255 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4256 } else {
4257 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4258 }
4259 }
4260
8ed5d97e
MC		 4261 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4262 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4263 if (!netif_carrier_ok(tp->dev))
4264 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4265 tp->pwrmgmt_thresh;
4266 else
4267 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4268 tw32(PCIE_PWR_MGMT_THRESH, val);
4269 }
4270
1da177e4
LT		 4271 return err;
4272}
4273
df3e6548
MC		 4274/* This is called whenever we suspect that the system chipset is re-
4275 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4276 * is bogus tx completions. We try to recover by setting the
4277 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4278 * in the workqueue.
4279 */
4280static void tg3_tx_recover(struct tg3 *tp)
4281{
4282 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4283 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4284
4285 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4286 "mapped I/O cycles to the network device, attempting to "
4287 "recover. Please report the problem to the driver maintainer "
4288 "and include system chipset information.\n", tp->dev->name);
4289
4290 spin_lock(&tp->lock);
df3e6548 4291 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4292 spin_unlock(&tp->lock);
4293}
4294
f3f3f27e 4295static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4296{
4297 smp_mb();
f3f3f27e
MC		 4298 return tnapi->tx_pending -
4299 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4300}
4301
1da177e4
LT		 4302/* Tigon3 never reports partial packet sends. So we do not
4303 * need special logic to handle SKBs that have not had all
4304 * of their frags sent yet, like SunGEM does.
4305 */
17375d25 4306static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4307{
17375d25 4308 struct tg3 *tp = tnapi->tp;
898a56f8 4309 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4310 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4311 struct netdev_queue *txq;
4312 int index = tnapi - tp->napi;
4313
4314 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4315 index--;
4316
4317 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4318
4319 while (sw_idx != hw_idx) {
f3f3f27e 4320 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4321 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4322 int i, tx_bug = 0;
4323
4324 if (unlikely(skb == NULL)) {
4325 tg3_tx_recover(tp);
4326 return;
4327 }
1da177e4 4328
90079ce8 4329 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4330
4331 ri->skb = NULL;
4332
4333 sw_idx = NEXT_TX(sw_idx);
4334
4335 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4336 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4337 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4338 tx_bug = 1;
1da177e4
LT		 4339 sw_idx = NEXT_TX(sw_idx);
4340 }
4341
f47c11ee 4342 dev_kfree_skb(skb);
df3e6548
MC		 4343
4344 if (unlikely(tx_bug)) {
4345 tg3_tx_recover(tp);
4346 return;
4347 }
1da177e4
LT		 4348 }
4349
f3f3f27e 4350 tnapi->tx_cons = sw_idx;
1da177e4 4351
1b2a7205
MC		 4352 /* Need to make the tx_cons update visible to tg3_start_xmit()
4353 * before checking for netif_queue_stopped(). Without the
4354 * memory barrier, there is a small possibility that tg3_start_xmit()
4355 * will miss it and cause the queue to be stopped forever.
4356 */
4357 smp_mb();
4358
fe5f5787 4359 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4360 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4361 __netif_tx_lock(txq, smp_processor_id());
4362 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4363 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4364 netif_tx_wake_queue(txq);
4365 __netif_tx_unlock(txq);
51b91468 4366 }
1da177e4
LT		 4367}
4368
4369/* Returns size of skb allocated or < 0 on error.
4370 *
4371 * We only need to fill in the address because the other members
4372 * of the RX descriptor are invariant, see tg3_init_rings.
4373 *
4374 * Note the purposeful assymetry of cpu vs. chip accesses. For
4375 * posting buffers we only dirty the first cache line of the RX
4376 * descriptor (containing the address). Whereas for the RX status
4377 * buffers the cpu only reads the last cacheline of the RX descriptor
4378 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4379 */
17375d25 4380static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4381 int src_idx, u32 dest_idx_unmasked)
4382{
17375d25 4383 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4384 struct tg3_rx_buffer_desc *desc;
4385 struct ring_info *map, *src_map;
4386 struct sk_buff *skb;
4387 dma_addr_t mapping;
4388 int skb_size, dest_idx;
21f581a5 4389 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4390
4391 src_map = NULL;
4392 switch (opaque_key) {
4393 case RXD_OPAQUE_RING_STD:
4394 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4395 desc = &tpr->rx_std[dest_idx];
4396 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4397 if (src_idx >= 0)
21f581a5 4398 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4399 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4400 break;
4401
4402 case RXD_OPAQUE_RING_JUMBO:
4403 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4404 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4405 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4406 if (src_idx >= 0)
21f581a5 4407 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4408 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4409 break;
4410
4411 default:
4412 return -EINVAL;
855e1111 4413 }
1da177e4
LT		 4414
4415 /* Do not overwrite any of the map or rp information
4416 * until we are sure we can commit to a new buffer.
4417 *
4418 * Callers depend upon this behavior and assume that
4419 * we leave everything unchanged if we fail.
4420 */
287be12e 4421 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4422 if (skb == NULL)
4423 return -ENOMEM;
4424
1da177e4
LT		 4425 skb_reserve(skb, tp->rx_offset);
4426
287be12e 4427 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4428 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4429 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4430 dev_kfree_skb(skb);
4431 return -EIO;
4432 }
1da177e4
LT		 4433
4434 map->skb = skb;
4435 pci_unmap_addr_set(map, mapping, mapping);
4436
4437 if (src_map != NULL)
4438 src_map->skb = NULL;
4439
4440 desc->addr_hi = ((u64)mapping >> 32);
4441 desc->addr_lo = ((u64)mapping & 0xffffffff);
4442
4443 return skb_size;
4444}
4445
4446/* We only need to move over in the address because the other
4447 * members of the RX descriptor are invariant. See notes above
4448 * tg3_alloc_rx_skb for full details.
4449 */
17375d25 4450static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4451 int src_idx, u32 dest_idx_unmasked)
4452{
17375d25 4453 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4454 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4455 struct ring_info *src_map, *dest_map;
4456 int dest_idx;
21f581a5 4457 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4458
4459 switch (opaque_key) {
4460 case RXD_OPAQUE_RING_STD:
4461 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4462 dest_desc = &tpr->rx_std[dest_idx];
4463 dest_map = &tpr->rx_std_buffers[dest_idx];
4464 src_desc = &tpr->rx_std[src_idx];
4465 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4466 break;
4467
4468 case RXD_OPAQUE_RING_JUMBO:
4469 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4470 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4471 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4472 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4473 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4474 break;
4475
4476 default:
4477 return;
855e1111 4478 }
1da177e4
LT		 4479
4480 dest_map->skb = src_map->skb;
4481 pci_unmap_addr_set(dest_map, mapping,
4482 pci_unmap_addr(src_map, mapping));
4483 dest_desc->addr_hi = src_desc->addr_hi;
4484 dest_desc->addr_lo = src_desc->addr_lo;
4485
4486 src_map->skb = NULL;
4487}
4488
1da177e4
LT		 4489/* The RX ring scheme is composed of multiple rings which post fresh
4490 * buffers to the chip, and one special ring the chip uses to report
4491 * status back to the host.
4492 *
4493 * The special ring reports the status of received packets to the
4494 * host. The chip does not write into the original descriptor the
4495 * RX buffer was obtained from. The chip simply takes the original
4496 * descriptor as provided by the host, updates the status and length
4497 * field, then writes this into the next status ring entry.
4498 *
4499 * Each ring the host uses to post buffers to the chip is described
4500 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4501 * it is first placed into the on-chip ram. When the packet's length
4502 * is known, it walks down the TG3_BDINFO entries to select the ring.
4503 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4504 * which is within the range of the new packet's length is chosen.
4505 *
4506 * The "separate ring for rx status" scheme may sound queer, but it makes
4507 * sense from a cache coherency perspective. If only the host writes
4508 * to the buffer post rings, and only the chip writes to the rx status
4509 * rings, then cache lines never move beyond shared-modified state.
4510 * If both the host and chip were to write into the same ring, cache line
4511 * eviction could occur since both entities want it in an exclusive state.
4512 */
17375d25 4513static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4514{
17375d25 4515 struct tg3 *tp = tnapi->tp;
f92905de 4516 u32 work_mask, rx_std_posted = 0;
72334482 4517 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4518 u16 hw_idx;
1da177e4 4519 int received;
21f581a5 4520 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4521
8d9d7cfc 4522 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4523 /*
4524 * We need to order the read of hw_idx and the read of
4525 * the opaque cookie.
4526 */
4527 rmb();
1da177e4
LT		 4528 work_mask = 0;
4529 received = 0;
4530 while (sw_idx != hw_idx && budget > 0) {
72334482 4531 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4532 unsigned int len;
4533 struct sk_buff *skb;
4534 dma_addr_t dma_addr;
4535 u32 opaque_key, desc_idx, *post_ptr;
4536
4537 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4538 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4539 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4540 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4541 dma_addr = pci_unmap_addr(ri, mapping);
4542 skb = ri->skb;
4543 post_ptr = &tpr->rx_std_ptr;
f92905de 4544 rx_std_posted++;
1da177e4 4545 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4546 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4547 dma_addr = pci_unmap_addr(ri, mapping);
4548 skb = ri->skb;
4549 post_ptr = &tpr->rx_jmb_ptr;
4550 } else
1da177e4 4551 goto next_pkt_nopost;
1da177e4
LT		 4552
4553 work_mask |= opaque_key;
4554
4555 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4556 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4557 drop_it:
17375d25 4558 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4559 desc_idx, *post_ptr);
4560 drop_it_no_recycle:
4561 /* Other statistics kept track of by card. */
4562 tp->net_stats.rx_dropped++;
4563 goto next_pkt;
4564 }
4565
ad829268
MC		 4566 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4567 ETH_FCS_LEN;
1da177e4 4568
6aa20a22 4569 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4570 && tp->rx_offset == NET_IP_ALIGN
4571 /* rx_offset will likely not equal NET_IP_ALIGN
4572 * if this is a 5701 card running in PCI-X mode
4573 * [see tg3_get_invariants()]
4574 */
1da177e4
LT		 4575 ) {
4576 int skb_size;
4577
17375d25 4578 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4579 desc_idx, *post_ptr);
4580 if (skb_size < 0)
4581 goto drop_it;
4582
287be12e 4583 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4584 PCI_DMA_FROMDEVICE);
4585
4586 skb_put(skb, len);
4587 } else {
4588 struct sk_buff *copy_skb;
4589
17375d25 4590 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4591 desc_idx, *post_ptr);
4592
ad829268
MC		 4593 copy_skb = netdev_alloc_skb(tp->dev,
4594 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4595 if (copy_skb == NULL)
4596 goto drop_it_no_recycle;
4597
ad829268 4598 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4599 skb_put(copy_skb, len);
4600 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4601 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4602 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4603
4604 /* We'll reuse the original ring buffer. */
4605 skb = copy_skb;
4606 }
4607
4608 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4609 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4610 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4611 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4612 skb->ip_summed = CHECKSUM_UNNECESSARY;
4613 else
4614 skb->ip_summed = CHECKSUM_NONE;
4615
4616 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4617
4618 if (len > (tp->dev->mtu + ETH_HLEN) &&
4619 skb->protocol != htons(ETH_P_8021Q)) {
4620 dev_kfree_skb(skb);
4621 goto next_pkt;
4622 }
4623
1da177e4
LT		 4624#if TG3_VLAN_TAG_USED
4625 if (tp->vlgrp != NULL &&
4626 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4627 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4628 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4629 } else
4630#endif
17375d25 4631 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4632
1da177e4
LT		 4633 received++;
4634 budget--;
4635
4636next_pkt:
4637 (*post_ptr)++;
f92905de
MC		 4638
4639 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4640 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4641
4642 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4643 TG3_64BIT_REG_LOW, idx);
4644 work_mask &= ~RXD_OPAQUE_RING_STD;
4645 rx_std_posted = 0;
4646 }
1da177e4 4647next_pkt_nopost:
483ba50b 4648 sw_idx++;
6b31a515 4649 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4650
4651 /* Refresh hw_idx to see if there is new work */
4652 if (sw_idx == hw_idx) {
8d9d7cfc 4653 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4654 rmb();
4655 }
1da177e4
LT		 4656 }
4657
4658 /* ACK the status ring. */
72334482
MC		 4659 tnapi->rx_rcb_ptr = sw_idx;
4660 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4661
4662 /* Refill RX ring(s). */
4663 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4664 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4665 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4666 sw_idx);
4667 }
4668 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4669 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4670 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4671 sw_idx);
4672 }
4673 mmiowb();
4674
4675 return received;
4676}
4677
17375d25 4678static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4679{
17375d25 4680 struct tg3 *tp = tnapi->tp;
898a56f8 4681 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4682
1da177e4
LT		 4683 /* handle link change and other phy events */
4684 if (!(tp->tg3_flags &
4685 (TG3_FLAG_USE_LINKCHG_REG |
4686 TG3_FLAG_POLL_SERDES))) {
4687 if (sblk->status & SD_STATUS_LINK_CHG) {
4688 sblk->status = SD_STATUS_UPDATED |
4689 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4690 spin_lock(&tp->lock);
dd477003
MC		 4691 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4692 tw32_f(MAC_STATUS,
4693 (MAC_STATUS_SYNC_CHANGED |
4694 MAC_STATUS_CFG_CHANGED |
4695 MAC_STATUS_MI_COMPLETION |
4696 MAC_STATUS_LNKSTATE_CHANGED));
4697 udelay(40);
4698 } else
4699 tg3_setup_phy(tp, 0);
f47c11ee 4700 spin_unlock(&tp->lock);
1da177e4
LT		 4701 }
4702 }
4703
4704 /* run TX completion thread */
f3f3f27e 4705 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4706 tg3_tx(tnapi);
6f535763 4707 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4708 return work_done;
1da177e4
LT		 4709 }
4710
1da177e4
LT		 4711 /* run RX thread, within the bounds set by NAPI.
4712 * All RX "locking" is done by ensuring outside
bea3348e 4713 * code synchronizes with tg3->napi.poll()
1da177e4 4714 */
8d9d7cfc 4715 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4716 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4717
6f535763
DM		 4718 return work_done;
4719}
4720
4721static int tg3_poll(struct napi_struct *napi, int budget)
4722{
8ef0442f
MC		 4723 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4724 struct tg3 *tp = tnapi->tp;
6f535763 4725 int work_done = 0;
898a56f8 4726 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4727
4728 while (1) {
17375d25 4729 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4730
4731 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4732 goto tx_recovery;
4733
4734 if (unlikely(work_done >= budget))
4735 break;
4736
4fd7ab59 4737 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4738 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4739 * to tell the hw how much work has been processed,
4740 * so we must read it before checking for more work.
4741 */
898a56f8
MC		 4742 tnapi->last_tag = sblk->status_tag;
4743 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4744 rmb();
4745 } else
4746 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4747
17375d25 4748 if (likely(!tg3_has_work(tnapi))) {
288379f0 4749 napi_complete(napi);
17375d25 4750 tg3_int_reenable(tnapi);
6f535763
DM		 4751 break;
4752 }
1da177e4
LT		 4753 }
4754
bea3348e 4755 return work_done;
6f535763
DM		 4756
4757tx_recovery:
4fd7ab59 4758 /* work_done is guaranteed to be less than budget. */
288379f0 4759 napi_complete(napi);
6f535763 4760 schedule_work(&tp->reset_task);
4fd7ab59 4761 return work_done;
1da177e4
LT		 4762}
4763
f47c11ee
DM		 4764static void tg3_irq_quiesce(struct tg3 *tp)
4765{
4f125f42
MC		 4766 int i;
4767
f47c11ee
DM		 4768 BUG_ON(tp->irq_sync);
4769
4770 tp->irq_sync = 1;
4771 smp_mb();
4772
4f125f42
MC		 4773 for (i = 0; i < tp->irq_cnt; i++)
4774 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4775}
4776
4777static inline int tg3_irq_sync(struct tg3 *tp)
4778{
4779 return tp->irq_sync;
4780}
4781
4782/* Fully shutdown all tg3 driver activity elsewhere in the system.
4783 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4784 * with as well. Most of the time, this is not necessary except when
4785 * shutting down the device.
4786 */
4787static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4788{
46966545 4789 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4790 if (irq_sync)
4791 tg3_irq_quiesce(tp);
f47c11ee
DM		 4792}
4793
4794static inline void tg3_full_unlock(struct tg3 *tp)
4795{
f47c11ee
DM		 4796 spin_unlock_bh(&tp->lock);
4797}
4798
fcfa0a32
MC		 4799/* One-shot MSI handler - Chip automatically disables interrupt
4800 * after sending MSI so driver doesn't have to do it.
4801 */
7d12e780 4802static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4803{
09943a18
MC		 4804 struct tg3_napi *tnapi = dev_id;
4805 struct tg3 *tp = tnapi->tp;
fcfa0a32 4806
898a56f8 4807 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4808 if (tnapi->rx_rcb)
4809 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4810
4811 if (likely(!tg3_irq_sync(tp)))
09943a18 4812 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4813
4814 return IRQ_HANDLED;
4815}
4816
88b06bc2
MC		 4817/* MSI ISR - No need to check for interrupt sharing and no need to
4818 * flush status block and interrupt mailbox. PCI ordering rules
4819 * guarantee that MSI will arrive after the status block.
4820 */
7d12e780 4821static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4822{
09943a18
MC		 4823 struct tg3_napi *tnapi = dev_id;
4824 struct tg3 *tp = tnapi->tp;
88b06bc2 4825
898a56f8 4826 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4827 if (tnapi->rx_rcb)
4828 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4829 /*
fac9b83e 4830 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4831 * chip-internal interrupt pending events.
fac9b83e 4832 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4833 * NIC to stop sending us irqs, engaging "in-intr-handler"
4834 * event coalescing.
4835 */
4836 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4837 if (likely(!tg3_irq_sync(tp)))
09943a18 4838 napi_schedule(&tnapi->napi);
61487480 4839
88b06bc2
MC		 4840 return IRQ_RETVAL(1);
4841}
4842
7d12e780 4843static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4844{
09943a18
MC		 4845 struct tg3_napi *tnapi = dev_id;
4846 struct tg3 *tp = tnapi->tp;
898a56f8 4847 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4848 unsigned int handled = 1;
4849
1da177e4
LT		 4850 /* In INTx mode, it is possible for the interrupt to arrive at
4851 * the CPU before the status block posted prior to the interrupt.
4852 * Reading the PCI State register will confirm whether the
4853 * interrupt is ours and will flush the status block.
4854 */
d18edcb2
MC		 4855 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4856 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4857 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4858 handled = 0;
f47c11ee 4859 goto out;
fac9b83e 4860 }
d18edcb2
MC		 4861 }
4862
4863 /*
4864 * Writing any value to intr-mbox-0 clears PCI INTA# and
4865 * chip-internal interrupt pending events.
4866 * Writing non-zero to intr-mbox-0 additional tells the
4867 * NIC to stop sending us irqs, engaging "in-intr-handler"
4868 * event coalescing.
c04cb347
MC		 4869 *
4870 * Flush the mailbox to de-assert the IRQ immediately to prevent
4871 * spurious interrupts. The flush impacts performance but
4872 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4873 */
c04cb347 4874 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4875 if (tg3_irq_sync(tp))
4876 goto out;
4877 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4878 if (likely(tg3_has_work(tnapi))) {
72334482 4879 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4880 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4881 } else {
4882 /* No work, shared interrupt perhaps? re-enable
4883 * interrupts, and flush that PCI write
4884 */
4885 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4886 0x00000000);
fac9b83e 4887 }
f47c11ee 4888out:
fac9b83e
DM		 4889 return IRQ_RETVAL(handled);
4890}
4891
7d12e780 4892static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4893{
09943a18
MC		 4894 struct tg3_napi *tnapi = dev_id;
4895 struct tg3 *tp = tnapi->tp;
898a56f8 4896 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4897 unsigned int handled = 1;
4898
fac9b83e
DM		 4899 /* In INTx mode, it is possible for the interrupt to arrive at
4900 * the CPU before the status block posted prior to the interrupt.
4901 * Reading the PCI State register will confirm whether the
4902 * interrupt is ours and will flush the status block.
4903 */
898a56f8 4904 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4905 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4906 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4907 handled = 0;
f47c11ee 4908 goto out;
1da177e4 4909 }
d18edcb2
MC		 4910 }
4911
4912 /*
4913 * writing any value to intr-mbox-0 clears PCI INTA# and
4914 * chip-internal interrupt pending events.
4915 * writing non-zero to intr-mbox-0 additional tells the
4916 * NIC to stop sending us irqs, engaging "in-intr-handler"
4917 * event coalescing.
c04cb347
MC		 4918 *
4919 * Flush the mailbox to de-assert the IRQ immediately to prevent
4920 * spurious interrupts. The flush impacts performance but
4921 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4922 */
c04cb347 4923 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4924
4925 /*
4926 * In a shared interrupt configuration, sometimes other devices'
4927 * interrupts will scream. We record the current status tag here
4928 * so that the above check can report that the screaming interrupts
4929 * are unhandled. Eventually they will be silenced.
4930 */
898a56f8 4931 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4932
d18edcb2
MC		 4933 if (tg3_irq_sync(tp))
4934 goto out;
624f8e50 4935
72334482 4936 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4937
09943a18 4938 napi_schedule(&tnapi->napi);
624f8e50 4939
f47c11ee 4940out:
1da177e4
LT		 4941 return IRQ_RETVAL(handled);
4942}
4943
7938109f 4944/* ISR for interrupt test */
7d12e780 4945static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4946{
09943a18
MC		 4947 struct tg3_napi *tnapi = dev_id;
4948 struct tg3 *tp = tnapi->tp;
898a56f8 4949 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4950
f9804ddb
MC		 4951 if ((sblk->status & SD_STATUS_UPDATED) ||
4952 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4953 tg3_disable_ints(tp);
7938109f
MC		 4954 return IRQ_RETVAL(1);
4955 }
4956 return IRQ_RETVAL(0);
4957}
4958
8e7a22e3 4959static int tg3_init_hw(struct tg3 *, int);
944d980e 4960static int tg3_halt(struct tg3 *, int, int);
1da177e4 4961
b9ec6c1b
MC		 4962/* Restart hardware after configuration changes, self-test, etc.
4963 * Invoked with tp->lock held.
4964 */
4965static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4966 __releases(tp->lock)
4967 __acquires(tp->lock)
b9ec6c1b
MC		 4968{
4969 int err;
4970
4971 err = tg3_init_hw(tp, reset_phy);
4972 if (err) {
4973 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4974 "aborting.\n", tp->dev->name);
4975 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4976 tg3_full_unlock(tp);
4977 del_timer_sync(&tp->timer);
4978 tp->irq_sync = 0;
fed97810 4979 tg3_napi_enable(tp);
b9ec6c1b
MC		 4980 dev_close(tp->dev);
4981 tg3_full_lock(tp, 0);
4982 }
4983 return err;
4984}
4985
1da177e4
LT		 4986#ifdef CONFIG_NET_POLL_CONTROLLER
4987static void tg3_poll_controller(struct net_device *dev)
4988{
4f125f42 4989 int i;
88b06bc2
MC		 4990 struct tg3 *tp = netdev_priv(dev);
4991
4f125f42
MC		 4992 for (i = 0; i < tp->irq_cnt; i++)
4993 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 4994}
4995#endif
4996
c4028958 4997static void tg3_reset_task(struct work_struct *work)
1da177e4 4998{
c4028958 4999 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5000 int err;
1da177e4
LT		 5001 unsigned int restart_timer;
5002
7faa006f 5003 tg3_full_lock(tp, 0);
7faa006f
MC		 5004
5005 if (!netif_running(tp->dev)) {
7faa006f
MC		 5006 tg3_full_unlock(tp);
5007 return;
5008 }
5009
5010 tg3_full_unlock(tp);
5011
b02fd9e3
MC		 5012 tg3_phy_stop(tp);
5013
1da177e4
LT		 5014 tg3_netif_stop(tp);
5015
f47c11ee 5016 tg3_full_lock(tp, 1);
1da177e4
LT		 5017
5018 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5019 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5020
df3e6548
MC		 5021 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5022 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5023 tp->write32_rx_mbox = tg3_write_flush_reg32;
5024 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5025 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5026 }
5027
944d980e 5028 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5029 err = tg3_init_hw(tp, 1);
5030 if (err)
b9ec6c1b 5031 goto out;
1da177e4
LT		 5032
5033 tg3_netif_start(tp);
5034
1da177e4
LT		 5035 if (restart_timer)
5036 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5037
b9ec6c1b 5038out:
7faa006f 5039 tg3_full_unlock(tp);
b02fd9e3
MC		 5040
5041 if (!err)
5042 tg3_phy_start(tp);
1da177e4
LT		 5043}
5044
b0408751
MC		 5045static void tg3_dump_short_state(struct tg3 *tp)
5046{
5047 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5048 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5049 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5050 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5051}
5052
1da177e4
LT		 5053static void tg3_tx_timeout(struct net_device *dev)
5054{
5055 struct tg3 *tp = netdev_priv(dev);
5056
b0408751 5057 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5058 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5059 dev->name);
b0408751
MC		 5060 tg3_dump_short_state(tp);
5061 }
1da177e4
LT		 5062
5063 schedule_work(&tp->reset_task);
5064}
5065
c58ec932
MC		 5066/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5067static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5068{
5069 u32 base = (u32) mapping & 0xffffffff;
5070
5071 return ((base > 0xffffdcc0) &&
5072 (base + len + 8 < base));
5073}
5074
72f2afb8
MC		 5075/* Test for DMA addresses > 40-bit */
5076static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5077 int len)
5078{
5079#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5080 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5081 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5082 return 0;
5083#else
5084 return 0;
5085#endif
5086}
5087
f3f3f27e 5088static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5089
72f2afb8
MC		 5090/* Workaround 4GB and 40-bit hardware DMA bugs. */
5091static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5092 u32 last_plus_one, u32 *start,
5093 u32 base_flags, u32 mss)
1da177e4 5094{
f3f3f27e 5095 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5096 struct sk_buff *new_skb;
c58ec932 5097 dma_addr_t new_addr = 0;
1da177e4 5098 u32 entry = *start;
c58ec932 5099 int i, ret = 0;
1da177e4 5100
41588ba1
MC		 5101 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5102 new_skb = skb_copy(skb, GFP_ATOMIC);
5103 else {
5104 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5105
5106 new_skb = skb_copy_expand(skb,
5107 skb_headroom(skb) + more_headroom,
5108 skb_tailroom(skb), GFP_ATOMIC);
5109 }
5110
1da177e4 5111 if (!new_skb) {
c58ec932
MC		 5112 ret = -1;
5113 } else {
5114 /* New SKB is guaranteed to be linear. */
5115 entry = *start;
90079ce8 5116 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5117 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5118
c58ec932
MC		 5119 /* Make sure new skb does not cross any 4G boundaries.
5120 * Drop the packet if it does.
5121 */
0e1406dd
MC		 5122 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5123 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5124 if (!ret)
5125 skb_dma_unmap(&tp->pdev->dev, new_skb,
5126 DMA_TO_DEVICE);
c58ec932
MC		 5127 ret = -1;
5128 dev_kfree_skb(new_skb);
5129 new_skb = NULL;
5130 } else {
f3f3f27e 5131 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5132 base_flags, 1 | (mss << 1));
5133 *start = NEXT_TX(entry);
5134 }
1da177e4
LT		 5135 }
5136
1da177e4
LT		 5137 /* Now clean up the sw ring entries. */
5138 i = 0;
5139 while (entry != last_plus_one) {
f3f3f27e
MC		 5140 if (i == 0)
5141 tnapi->tx_buffers[entry].skb = new_skb;
5142 else
5143 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5144 entry = NEXT_TX(entry);
5145 i++;
5146 }
5147
90079ce8 5148 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5149 dev_kfree_skb(skb);
5150
c58ec932 5151 return ret;
1da177e4
LT		 5152}
5153
f3f3f27e 5154static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5155 dma_addr_t mapping, int len, u32 flags,
5156 u32 mss_and_is_end)
5157{
f3f3f27e 5158 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5159 int is_end = (mss_and_is_end & 0x1);
5160 u32 mss = (mss_and_is_end >> 1);
5161 u32 vlan_tag = 0;
5162
5163 if (is_end)
5164 flags |= TXD_FLAG_END;
5165 if (flags & TXD_FLAG_VLAN) {
5166 vlan_tag = flags >> 16;
5167 flags &= 0xffff;
5168 }
5169 vlan_tag |= (mss << TXD_MSS_SHIFT);
5170
5171 txd->addr_hi = ((u64) mapping >> 32);
5172 txd->addr_lo = ((u64) mapping & 0xffffffff);
5173 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5174 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5175}
5176
5a6f3074
MC		 5177/* hard_start_xmit for devices that don't have any bugs and
5178 * support TG3_FLG2_HW_TSO_2 only.
5179 */
61357325
SH		 5180static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5181 struct net_device *dev)
5a6f3074
MC		 5182{
5183 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5184 u32 len, entry, base_flags, mss;
90079ce8
DM		 5185 struct skb_shared_info *sp;
5186 dma_addr_t mapping;
fe5f5787
MC		 5187 struct tg3_napi *tnapi;
5188 struct netdev_queue *txq;
5a6f3074 5189
fe5f5787
MC		 5190 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5191 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5192 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5193 tnapi++;
5a6f3074 5194
00b70504 5195 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5196 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5197 * interrupt. Furthermore, IRQ processing runs lockless so we have
5198 * no IRQ context deadlocks to worry about either. Rejoice!
5199 */
f3f3f27e 5200 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5201 if (!netif_tx_queue_stopped(txq)) {
5202 netif_tx_stop_queue(txq);
5a6f3074
MC		 5203
5204 /* This is a hard error, log it. */
5205 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5206 "queue awake!\n", dev->name);
5207 }
5a6f3074
MC		 5208 return NETDEV_TX_BUSY;
5209 }
5210
f3f3f27e 5211 entry = tnapi->tx_prod;
5a6f3074 5212 base_flags = 0;
5a6f3074 5213 mss = 0;
c13e3713 5214 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5215 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5216 u32 hdrlen;
5a6f3074
MC		 5217
5218 if (skb_header_cloned(skb) &&
5219 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5220 dev_kfree_skb(skb);
5221 goto out_unlock;
5222 }
5223
b0026624 5224 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5225 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5226 else {
eddc9ec5
ACM		 5227 struct iphdr *iph = ip_hdr(skb);
5228
ab6a5bb6 5229 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5230 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5231
eddc9ec5
ACM		 5232 iph->check = 0;
5233 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5234 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5235 }
5a6f3074 5236
f6eb9b1f
MC		 5237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5238 mss |= (hdrlen & 0xc) << 12;
5239 if (hdrlen & 0x10)
5240 base_flags |= 0x00000010;
5241 base_flags |= (hdrlen & 0x3e0) << 5;
5242 } else
5243 mss |= hdrlen << 9;
5244
5a6f3074
MC		 5245 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5246 TXD_FLAG_CPU_POST_DMA);
5247
aa8223c7 5248 tcp_hdr(skb)->check = 0;
5a6f3074 5249
5a6f3074 5250 }
84fa7933 5251 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5252 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5253#if TG3_VLAN_TAG_USED
5254 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5255 base_flags |= (TXD_FLAG_VLAN |
5256 (vlan_tx_tag_get(skb) << 16));
5257#endif
5258
90079ce8
DM		 5259 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5260 dev_kfree_skb(skb);
5261 goto out_unlock;
5262 }
5263
5264 sp = skb_shinfo(skb);
5265
042a53a9 5266 mapping = sp->dma_head;
5a6f3074 5267
f3f3f27e 5268 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5269
fe5f5787
MC		 5270 len = skb_headlen(skb);
5271
f6eb9b1f
MC		 5272 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5273 !mss && skb->len > ETH_DATA_LEN)
5274 base_flags |= TXD_FLAG_JMB_PKT;
5275
f3f3f27e 5276 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5277 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5278
5279 entry = NEXT_TX(entry);
5280
5281 /* Now loop through additional data fragments, and queue them. */
5282 if (skb_shinfo(skb)->nr_frags > 0) {
5283 unsigned int i, last;
5284
5285 last = skb_shinfo(skb)->nr_frags - 1;
5286 for (i = 0; i <= last; i++) {
5287 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5288
5289 len = frag->size;
042a53a9 5290 mapping = sp->dma_maps[i];
f3f3f27e 5291 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5292
f3f3f27e 5293 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5294 base_flags, (i == last) | (mss << 1));
5295
5296 entry = NEXT_TX(entry);
5297 }
5298 }
5299
5300 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5301 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5302
f3f3f27e
MC		 5303 tnapi->tx_prod = entry;
5304 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5305 netif_tx_stop_queue(txq);
f3f3f27e 5306 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5307 netif_tx_wake_queue(txq);
5a6f3074
MC		 5308 }
5309
5310out_unlock:
cdd0db05 5311 mmiowb();
5a6f3074
MC		 5312
5313 return NETDEV_TX_OK;
5314}
5315
61357325
SH		 5316static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5317 struct net_device *);
52c0fd83
MC		 5318
5319/* Use GSO to workaround a rare TSO bug that may be triggered when the
5320 * TSO header is greater than 80 bytes.
5321 */
5322static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5323{
5324 struct sk_buff *segs, *nskb;
f3f3f27e 5325 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5326
5327 /* Estimate the number of fragments in the worst case */
f3f3f27e 5328 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5329 netif_stop_queue(tp->dev);
f3f3f27e 5330 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5331 return NETDEV_TX_BUSY;
5332
5333 netif_wake_queue(tp->dev);
52c0fd83
MC		 5334 }
5335
5336 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5337 if (IS_ERR(segs))
52c0fd83
MC		 5338 goto tg3_tso_bug_end;
5339
5340 do {
5341 nskb = segs;
5342 segs = segs->next;
5343 nskb->next = NULL;
5344 tg3_start_xmit_dma_bug(nskb, tp->dev);
5345 } while (segs);
5346
5347tg3_tso_bug_end:
5348 dev_kfree_skb(skb);
5349
5350 return NETDEV_TX_OK;
5351}
52c0fd83 5352
5a6f3074
MC		 5353/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5354 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5355 */
61357325
SH		 5356static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5357 struct net_device *dev)
1da177e4
LT		 5358{
5359 struct tg3 *tp = netdev_priv(dev);
1da177e4 5360 u32 len, entry, base_flags, mss;
90079ce8 5361 struct skb_shared_info *sp;
1da177e4 5362 int would_hit_hwbug;
90079ce8 5363 dma_addr_t mapping;
f3f3f27e 5364 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5365
5366 len = skb_headlen(skb);
5367
00b70504 5368 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5369 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5370 * interrupt. Furthermore, IRQ processing runs lockless so we have
5371 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5372 */
f3f3f27e 5373 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5374 if (!netif_queue_stopped(dev)) {
5375 netif_stop_queue(dev);
5376
5377 /* This is a hard error, log it. */
5378 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5379 "queue awake!\n", dev->name);
5380 }
1da177e4
LT		 5381 return NETDEV_TX_BUSY;
5382 }
5383
f3f3f27e 5384 entry = tnapi->tx_prod;
1da177e4 5385 base_flags = 0;
84fa7933 5386 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5387 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5388 mss = 0;
c13e3713 5389 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5390 struct iphdr *iph;
92c6b8d1 5391 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5392
5393 if (skb_header_cloned(skb) &&
5394 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5395 dev_kfree_skb(skb);
5396 goto out_unlock;
5397 }
5398
ab6a5bb6 5399 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5400 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5401
52c0fd83
MC		 5402 hdr_len = ip_tcp_len + tcp_opt_len;
5403 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5404 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5405 return (tg3_tso_bug(tp, skb));
5406
1da177e4
LT		 5407 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5408 TXD_FLAG_CPU_POST_DMA);
5409
eddc9ec5
ACM		 5410 iph = ip_hdr(skb);
5411 iph->check = 0;
5412 iph->tot_len = htons(mss + hdr_len);
1da177e4 5413 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5414 tcp_hdr(skb)->check = 0;
1da177e4 5415 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5416 } else
5417 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5418 iph->daddr, 0,
5419 IPPROTO_TCP,
5420 0);
1da177e4 5421
92c6b8d1
MC		 5422 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5423 mss |= hdr_len << 9;
5424 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5426 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5427 int tsflags;
5428
eddc9ec5 5429 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5430 mss |= (tsflags << 11);
5431 }
5432 } else {
eddc9ec5 5433 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5434 int tsflags;
5435
eddc9ec5 5436 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5437 base_flags |= tsflags << 12;
5438 }
5439 }
5440 }
1da177e4
LT		 5441#if TG3_VLAN_TAG_USED
5442 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5443 base_flags |= (TXD_FLAG_VLAN |
5444 (vlan_tx_tag_get(skb) << 16));
5445#endif
5446
90079ce8
DM		 5447 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5448 dev_kfree_skb(skb);
5449 goto out_unlock;
5450 }
5451
5452 sp = skb_shinfo(skb);
5453
042a53a9 5454 mapping = sp->dma_head;
1da177e4 5455
f3f3f27e 5456 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5457
5458 would_hit_hwbug = 0;
5459
92c6b8d1
MC		 5460 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5461 would_hit_hwbug = 1;
5462
0e1406dd
MC		 5463 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5464 tg3_4g_overflow_test(mapping, len))
5465 would_hit_hwbug = 1;
5466
5467 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5468 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5469 would_hit_hwbug = 1;
0e1406dd
MC		 5470
5471 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5472 would_hit_hwbug = 1;
1da177e4 5473
f3f3f27e 5474 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5475 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5476
5477 entry = NEXT_TX(entry);
5478
5479 /* Now loop through additional data fragments, and queue them. */
5480 if (skb_shinfo(skb)->nr_frags > 0) {
5481 unsigned int i, last;
5482
5483 last = skb_shinfo(skb)->nr_frags - 1;
5484 for (i = 0; i <= last; i++) {
5485 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5486
5487 len = frag->size;
042a53a9 5488 mapping = sp->dma_maps[i];
1da177e4 5489
f3f3f27e 5490 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5491
92c6b8d1
MC		 5492 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5493 len <= 8)
5494 would_hit_hwbug = 1;
5495
0e1406dd
MC		 5496 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5497 tg3_4g_overflow_test(mapping, len))
c58ec932 5498 would_hit_hwbug = 1;
1da177e4 5499
0e1406dd
MC		 5500 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5501 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5502 would_hit_hwbug = 1;
5503
1da177e4 5504 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5505 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5506 base_flags, (i == last)|(mss << 1));
5507 else
f3f3f27e 5508 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5509 base_flags, (i == last));
5510
5511 entry = NEXT_TX(entry);
5512 }
5513 }
5514
5515 if (would_hit_hwbug) {
5516 u32 last_plus_one = entry;
5517 u32 start;
1da177e4 5518
c58ec932
MC		 5519 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5520 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5521
5522 /* If the workaround fails due to memory/mapping
5523 * failure, silently drop this packet.
5524 */
72f2afb8 5525 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5526 &start, base_flags, mss))
1da177e4
LT		 5527 goto out_unlock;
5528
5529 entry = start;
5530 }
5531
5532 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5533 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5534
f3f3f27e
MC		 5535 tnapi->tx_prod = entry;
5536 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5537 netif_stop_queue(dev);
f3f3f27e 5538 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5539 netif_wake_queue(tp->dev);
5540 }
1da177e4
LT		 5541
5542out_unlock:
cdd0db05 5543 mmiowb();
1da177e4
LT		 5544
5545 return NETDEV_TX_OK;
5546}
5547
5548static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5549 int new_mtu)
5550{
5551 dev->mtu = new_mtu;
5552
ef7f5ec0 5553 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5554 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5555 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5556 ethtool_op_set_tso(dev, 0);
5557 }
5558 else
5559 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5560 } else {
a4e2b347 5561 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5562 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5563 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5564 }
1da177e4
LT		 5565}
5566
5567static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5568{
5569 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5570 int err;
1da177e4
LT		 5571
5572 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5573 return -EINVAL;
5574
5575 if (!netif_running(dev)) {
5576 /* We'll just catch it later when the
5577 * device is up'd.
5578 */
5579 tg3_set_mtu(dev, tp, new_mtu);
5580 return 0;
5581 }
5582
b02fd9e3
MC		 5583 tg3_phy_stop(tp);
5584
1da177e4 5585 tg3_netif_stop(tp);
f47c11ee
DM		 5586
5587 tg3_full_lock(tp, 1);
1da177e4 5588
944d980e 5589 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5590
5591 tg3_set_mtu(dev, tp, new_mtu);
5592
b9ec6c1b 5593 err = tg3_restart_hw(tp, 0);
1da177e4 5594
b9ec6c1b
MC		 5595 if (!err)
5596 tg3_netif_start(tp);
1da177e4 5597
f47c11ee 5598 tg3_full_unlock(tp);
1da177e4 5599
b02fd9e3
MC		 5600 if (!err)
5601 tg3_phy_start(tp);
5602
b9ec6c1b 5603 return err;
1da177e4
LT		 5604}
5605
21f581a5
MC		 5606static void tg3_rx_prodring_free(struct tg3 *tp,
5607 struct tg3_rx_prodring_set *tpr)
1da177e4 5608{
1da177e4 5609 int i;
f3f3f27e 5610 struct ring_info *rxp;
1da177e4
LT		 5611
5612 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5613 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5614
5615 if (rxp->skb == NULL)
5616 continue;
1da177e4 5617
1da177e4
LT		 5618 pci_unmap_single(tp->pdev,
5619 pci_unmap_addr(rxp, mapping),
cf7a7298 5620 tp->rx_pkt_map_sz,
1da177e4
LT		 5621 PCI_DMA_FROMDEVICE);
5622 dev_kfree_skb_any(rxp->skb);
5623 rxp->skb = NULL;
5624 }
5625
cf7a7298
MC		 5626 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5627 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5628 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5629
cf7a7298
MC		 5630 if (rxp->skb == NULL)
5631 continue;
1da177e4 5632
cf7a7298
MC		 5633 pci_unmap_single(tp->pdev,
5634 pci_unmap_addr(rxp, mapping),
5635 TG3_RX_JMB_MAP_SZ,
5636 PCI_DMA_FROMDEVICE);
5637 dev_kfree_skb_any(rxp->skb);
5638 rxp->skb = NULL;
1da177e4 5639 }
1da177e4
LT		 5640 }
5641}
5642
5643/* Initialize tx/rx rings for packet processing.
5644 *
5645 * The chip has been shut down and the driver detached from
5646 * the networking, so no interrupts or new tx packets will
5647 * end up in the driver. tp->{tx,}lock are held and thus
5648 * we may not sleep.
5649 */
21f581a5
MC		 5650static int tg3_rx_prodring_alloc(struct tg3 *tp,
5651 struct tg3_rx_prodring_set *tpr)
1da177e4 5652{
287be12e 5653 u32 i, rx_pkt_dma_sz;
17375d25 5654 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5655
1da177e4 5656 /* Zero out all descriptors. */
21f581a5 5657 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5658
287be12e 5659 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5660 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5661 tp->dev->mtu > ETH_DATA_LEN)
5662 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5663 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5664
1da177e4
LT		 5665 /* Initialize invariants of the rings, we only set this
5666 * stuff once. This works because the card does not
5667 * write into the rx buffer posting rings.
5668 */
5669 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5670 struct tg3_rx_buffer_desc *rxd;
5671
21f581a5 5672 rxd = &tpr->rx_std[i];
287be12e 5673 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5674 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5675 rxd->opaque = (RXD_OPAQUE_RING_STD |
5676 (i << RXD_OPAQUE_INDEX_SHIFT));
5677 }
5678
1da177e4
LT		 5679 /* Now allocate fresh SKBs for each rx ring. */
5680 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5681 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5682 printk(KERN_WARNING PFX
5683 "%s: Using a smaller RX standard ring, "
5684 "only %d out of %d buffers were allocated "
5685 "successfully.\n",
5686 tp->dev->name, i, tp->rx_pending);
5687 if (i == 0)
cf7a7298 5688 goto initfail;
32d8c572 5689 tp->rx_pending = i;
1da177e4 5690 break;
32d8c572 5691 }
1da177e4
LT		 5692 }
5693
cf7a7298
MC		 5694 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5695 goto done;
5696
21f581a5 5697 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5698
0f893dc6 5699 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5700 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5701 struct tg3_rx_buffer_desc *rxd;
5702
79ed5ac7 5703 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5704 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5705 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5706 RXD_FLAG_JUMBO;
5707 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5708 (i << RXD_OPAQUE_INDEX_SHIFT));
5709 }
5710
1da177e4 5711 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5712 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5713 -1, i) < 0) {
5714 printk(KERN_WARNING PFX
5715 "%s: Using a smaller RX jumbo ring, "
5716 "only %d out of %d buffers were "
5717 "allocated successfully.\n",
5718 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5719 if (i == 0)
5720 goto initfail;
32d8c572 5721 tp->rx_jumbo_pending = i;
1da177e4 5722 break;
32d8c572 5723 }
1da177e4
LT		 5724 }
5725 }
cf7a7298
MC		 5726
5727done:
32d8c572 5728 return 0;
cf7a7298
MC		 5729
5730initfail:
21f581a5 5731 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5732 return -ENOMEM;
1da177e4
LT		 5733}
5734
21f581a5
MC		 5735static void tg3_rx_prodring_fini(struct tg3 *tp,
5736 struct tg3_rx_prodring_set *tpr)
1da177e4 5737{
21f581a5
MC		 5738 kfree(tpr->rx_std_buffers);
5739 tpr->rx_std_buffers = NULL;
5740 kfree(tpr->rx_jmb_buffers);
5741 tpr->rx_jmb_buffers = NULL;
5742 if (tpr->rx_std) {
1da177e4 5743 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5744 tpr->rx_std, tpr->rx_std_mapping);
5745 tpr->rx_std = NULL;
1da177e4 5746 }
21f581a5 5747 if (tpr->rx_jmb) {
1da177e4 5748 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5749 tpr->rx_jmb, tpr->rx_jmb_mapping);
5750 tpr->rx_jmb = NULL;
1da177e4 5751 }
cf7a7298
MC		 5752}
5753
21f581a5
MC		 5754static int tg3_rx_prodring_init(struct tg3 *tp,
5755 struct tg3_rx_prodring_set *tpr)
cf7a7298 5756{
21f581a5
MC		 5757 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5758 TG3_RX_RING_SIZE, GFP_KERNEL);
5759 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5760 return -ENOMEM;
5761
21f581a5
MC		 5762 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5763 &tpr->rx_std_mapping);
5764 if (!tpr->rx_std)
cf7a7298
MC		 5765 goto err_out;
5766
5767 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5768 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5769 TG3_RX_JUMBO_RING_SIZE,
5770 GFP_KERNEL);
5771 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5772 goto err_out;
5773
21f581a5
MC		 5774 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5775 TG3_RX_JUMBO_RING_BYTES,
5776 &tpr->rx_jmb_mapping);
5777 if (!tpr->rx_jmb)
cf7a7298
MC		 5778 goto err_out;
5779 }
5780
5781 return 0;
5782
5783err_out:
21f581a5 5784 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5785 return -ENOMEM;
5786}
5787
5788/* Free up pending packets in all rx/tx rings.
5789 *
5790 * The chip has been shut down and the driver detached from
5791 * the networking, so no interrupts or new tx packets will
5792 * end up in the driver. tp->{tx,}lock is not held and we are not
5793 * in an interrupt context and thus may sleep.
5794 */
5795static void tg3_free_rings(struct tg3 *tp)
5796{
f77a6a8e 5797 int i, j;
cf7a7298 5798
f77a6a8e
MC		 5799 for (j = 0; j < tp->irq_cnt; j++) {
5800 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5801
0c1d0e2b
MC		 5802 if (!tnapi->tx_buffers)
5803 continue;
5804
f77a6a8e
MC		 5805 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5806 struct tx_ring_info *txp;
5807 struct sk_buff *skb;
cf7a7298 5808
f77a6a8e
MC		 5809 txp = &tnapi->tx_buffers[i];
5810 skb = txp->skb;
cf7a7298 5811
f77a6a8e
MC		 5812 if (skb == NULL) {
5813 i++;
5814 continue;
5815 }
cf7a7298 5816
f77a6a8e 5817 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5818
f77a6a8e 5819 txp->skb = NULL;
cf7a7298 5820
f77a6a8e
MC		 5821 i += skb_shinfo(skb)->nr_frags + 1;
5822
5823 dev_kfree_skb_any(skb);
5824 }
cf7a7298
MC		 5825 }
5826
21f581a5 5827 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5828}
5829
5830/* Initialize tx/rx rings for packet processing.
5831 *
5832 * The chip has been shut down and the driver detached from
5833 * the networking, so no interrupts or new tx packets will
5834 * end up in the driver. tp->{tx,}lock are held and thus
5835 * we may not sleep.
5836 */
5837static int tg3_init_rings(struct tg3 *tp)
5838{
f77a6a8e 5839 int i;
72334482 5840
cf7a7298
MC		 5841 /* Free up all the SKBs. */
5842 tg3_free_rings(tp);
5843
f77a6a8e
MC		 5844 for (i = 0; i < tp->irq_cnt; i++) {
5845 struct tg3_napi *tnapi = &tp->napi[i];
5846
5847 tnapi->last_tag = 0;
5848 tnapi->last_irq_tag = 0;
5849 tnapi->hw_status->status = 0;
5850 tnapi->hw_status->status_tag = 0;
5851 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5852
f77a6a8e
MC		 5853 tnapi->tx_prod = 0;
5854 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5855 if (tnapi->tx_ring)
5856 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5857
5858 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5859 if (tnapi->rx_rcb)
5860 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 5861 }
72334482 5862
21f581a5 5863 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5864}
5865
5866/*
5867 * Must not be invoked with interrupt sources disabled and
5868 * the hardware shutdown down.
5869 */
5870static void tg3_free_consistent(struct tg3 *tp)
5871{
f77a6a8e 5872 int i;
898a56f8 5873
f77a6a8e
MC		 5874 for (i = 0; i < tp->irq_cnt; i++) {
5875 struct tg3_napi *tnapi = &tp->napi[i];
5876
5877 if (tnapi->tx_ring) {
5878 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5879 tnapi->tx_ring, tnapi->tx_desc_mapping);
5880 tnapi->tx_ring = NULL;
5881 }
5882
5883 kfree(tnapi->tx_buffers);
5884 tnapi->tx_buffers = NULL;
5885
5886 if (tnapi->rx_rcb) {
5887 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5888 tnapi->rx_rcb,
5889 tnapi->rx_rcb_mapping);
5890 tnapi->rx_rcb = NULL;
5891 }
5892
5893 if (tnapi->hw_status) {
5894 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5895 tnapi->hw_status,
5896 tnapi->status_mapping);
5897 tnapi->hw_status = NULL;
5898 }
1da177e4 5899 }
f77a6a8e 5900
1da177e4
LT		 5901 if (tp->hw_stats) {
5902 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5903 tp->hw_stats, tp->stats_mapping);
5904 tp->hw_stats = NULL;
5905 }
f77a6a8e 5906
21f581a5 5907 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5908}
5909
5910/*
5911 * Must not be invoked with interrupt sources disabled and
5912 * the hardware shutdown down. Can sleep.
5913 */
5914static int tg3_alloc_consistent(struct tg3 *tp)
5915{
f77a6a8e 5916 int i;
898a56f8 5917
21f581a5 5918 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5919 return -ENOMEM;
5920
f77a6a8e
MC		 5921 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5922 sizeof(struct tg3_hw_stats),
5923 &tp->stats_mapping);
5924 if (!tp->hw_stats)
1da177e4
LT		 5925 goto err_out;
5926
f77a6a8e 5927 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 5928
f77a6a8e
MC		 5929 for (i = 0; i < tp->irq_cnt; i++) {
5930 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 5931 struct tg3_hw_status *sblk;
1da177e4 5932
f77a6a8e
MC		 5933 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5934 TG3_HW_STATUS_SIZE,
5935 &tnapi->status_mapping);
5936 if (!tnapi->hw_status)
5937 goto err_out;
898a56f8 5938
f77a6a8e 5939 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 5940 sblk = tnapi->hw_status;
5941
5942 /*
5943 * When RSS is enabled, the status block format changes
5944 * slightly. The "rx_jumbo_consumer", "reserved",
5945 * and "rx_mini_consumer" members get mapped to the
5946 * other three rx return ring producer indexes.
5947 */
5948 switch (i) {
5949 default:
5950 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5951 break;
5952 case 2:
5953 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5954 break;
5955 case 3:
5956 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5957 break;
5958 case 4:
5959 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5960 break;
5961 }
72334482 5962
0c1d0e2b
MC		 5963 /*
5964 * If multivector RSS is enabled, vector 0 does not handle
5965 * rx or tx interrupts. Don't allocate any resources for it.
5966 */
5967 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5968 continue;
5969
f77a6a8e
MC		 5970 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5971 TG3_RX_RCB_RING_BYTES(tp),
5972 &tnapi->rx_rcb_mapping);
5973 if (!tnapi->rx_rcb)
5974 goto err_out;
72334482 5975
f77a6a8e 5976 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 5977
f77a6a8e
MC		 5978 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5979 TG3_TX_RING_SIZE, GFP_KERNEL);
5980 if (!tnapi->tx_buffers)
5981 goto err_out;
5982
5983 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
5984 TG3_TX_RING_BYTES,
5985 &tnapi->tx_desc_mapping);
5986 if (!tnapi->tx_ring)
5987 goto err_out;
5988 }
1da177e4
LT		 5989
5990 return 0;
5991
5992err_out:
5993 tg3_free_consistent(tp);
5994 return -ENOMEM;
5995}
5996
5997#define MAX_WAIT_CNT 1000
5998
5999/* To stop a block, clear the enable bit and poll till it
6000 * clears. tp->lock is held.
6001 */
b3b7d6be 6002static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6003{
6004 unsigned int i;
6005 u32 val;
6006
6007 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6008 switch (ofs) {
6009 case RCVLSC_MODE:
6010 case DMAC_MODE:
6011 case MBFREE_MODE:
6012 case BUFMGR_MODE:
6013 case MEMARB_MODE:
6014 /* We can't enable/disable these bits of the
6015 * 5705/5750, just say success.
6016 */
6017 return 0;
6018
6019 default:
6020 break;
855e1111 6021 }
1da177e4
LT		 6022 }
6023
6024 val = tr32(ofs);
6025 val &= ~enable_bit;
6026 tw32_f(ofs, val);
6027
6028 for (i = 0; i < MAX_WAIT_CNT; i++) {
6029 udelay(100);
6030 val = tr32(ofs);
6031 if ((val & enable_bit) == 0)
6032 break;
6033 }
6034
b3b7d6be 6035 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6036 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6037 "ofs=%lx enable_bit=%x\n",
6038 ofs, enable_bit);
6039 return -ENODEV;
6040 }
6041
6042 return 0;
6043}
6044
6045/* tp->lock is held. */
b3b7d6be 6046static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6047{
6048 int i, err;
6049
6050 tg3_disable_ints(tp);
6051
6052 tp->rx_mode &= ~RX_MODE_ENABLE;
6053 tw32_f(MAC_RX_MODE, tp->rx_mode);
6054 udelay(10);
6055
b3b7d6be
DM		 6056 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6057 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6058 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6059 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6060 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6061 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6062
6063 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6064 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6065 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6066 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6067 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6068 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6069 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6070
6071 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6072 tw32_f(MAC_MODE, tp->mac_mode);
6073 udelay(40);
6074
6075 tp->tx_mode &= ~TX_MODE_ENABLE;
6076 tw32_f(MAC_TX_MODE, tp->tx_mode);
6077
6078 for (i = 0; i < MAX_WAIT_CNT; i++) {
6079 udelay(100);
6080 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6081 break;
6082 }
6083 if (i >= MAX_WAIT_CNT) {
6084 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6085 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6086 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6087 err |= -ENODEV;
1da177e4
LT		 6088 }
6089
e6de8ad1 6090 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6091 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6092 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6093
6094 tw32(FTQ_RESET, 0xffffffff);
6095 tw32(FTQ_RESET, 0x00000000);
6096
b3b7d6be
DM		 6097 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6098 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6099
f77a6a8e
MC		 6100 for (i = 0; i < tp->irq_cnt; i++) {
6101 struct tg3_napi *tnapi = &tp->napi[i];
6102 if (tnapi->hw_status)
6103 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6104 }
1da177e4
LT		 6105 if (tp->hw_stats)
6106 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6107
1da177e4
LT		 6108 return err;
6109}
6110
0d3031d9
MC		 6111static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6112{
6113 int i;
6114 u32 apedata;
6115
6116 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6117 if (apedata != APE_SEG_SIG_MAGIC)
6118 return;
6119
6120 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6121 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6122 return;
6123
6124 /* Wait for up to 1 millisecond for APE to service previous event. */
6125 for (i = 0; i < 10; i++) {
6126 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6127 return;
6128
6129 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6130
6131 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6132 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6133 event | APE_EVENT_STATUS_EVENT_PENDING);
6134
6135 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6136
6137 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6138 break;
6139
6140 udelay(100);
6141 }
6142
6143 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6144 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6145}
6146
6147static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6148{
6149 u32 event;
6150 u32 apedata;
6151
6152 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6153 return;
6154
6155 switch (kind) {
6156 case RESET_KIND_INIT:
6157 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6158 APE_HOST_SEG_SIG_MAGIC);
6159 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6160 APE_HOST_SEG_LEN_MAGIC);
6161 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6162 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6163 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6164 APE_HOST_DRIVER_ID_MAGIC);
6165 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6166 APE_HOST_BEHAV_NO_PHYLOCK);
6167
6168 event = APE_EVENT_STATUS_STATE_START;
6169 break;
6170 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6171 /* With the interface we are currently using,
6172 * APE does not track driver state. Wiping
6173 * out the HOST SEGMENT SIGNATURE forces
6174 * the APE to assume OS absent status.
6175 */
6176 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6177
0d3031d9
MC		 6178 event = APE_EVENT_STATUS_STATE_UNLOAD;
6179 break;
6180 case RESET_KIND_SUSPEND:
6181 event = APE_EVENT_STATUS_STATE_SUSPEND;
6182 break;
6183 default:
6184 return;
6185 }
6186
6187 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6188
6189 tg3_ape_send_event(tp, event);
6190}
6191
1da177e4
LT		 6192/* tp->lock is held. */
6193static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6194{
f49639e6
DM		 6195 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6196 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6197
6198 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6199 switch (kind) {
6200 case RESET_KIND_INIT:
6201 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6202 DRV_STATE_START);
6203 break;
6204
6205 case RESET_KIND_SHUTDOWN:
6206 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6207 DRV_STATE_UNLOAD);
6208 break;
6209
6210 case RESET_KIND_SUSPEND:
6211 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6212 DRV_STATE_SUSPEND);
6213 break;
6214
6215 default:
6216 break;
855e1111 6217 }
1da177e4 6218 }
0d3031d9
MC		 6219
6220 if (kind == RESET_KIND_INIT ||
6221 kind == RESET_KIND_SUSPEND)
6222 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6223}
6224
6225/* tp->lock is held. */
6226static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6227{
6228 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6229 switch (kind) {
6230 case RESET_KIND_INIT:
6231 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6232 DRV_STATE_START_DONE);
6233 break;
6234
6235 case RESET_KIND_SHUTDOWN:
6236 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6237 DRV_STATE_UNLOAD_DONE);
6238 break;
6239
6240 default:
6241 break;
855e1111 6242 }
1da177e4 6243 }
0d3031d9
MC		 6244
6245 if (kind == RESET_KIND_SHUTDOWN)
6246 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6247}
6248
6249/* tp->lock is held. */
6250static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6251{
6252 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6253 switch (kind) {
6254 case RESET_KIND_INIT:
6255 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6256 DRV_STATE_START);
6257 break;
6258
6259 case RESET_KIND_SHUTDOWN:
6260 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6261 DRV_STATE_UNLOAD);
6262 break;
6263
6264 case RESET_KIND_SUSPEND:
6265 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6266 DRV_STATE_SUSPEND);
6267 break;
6268
6269 default:
6270 break;
855e1111 6271 }
1da177e4
LT		 6272 }
6273}
6274
7a6f4369
MC		 6275static int tg3_poll_fw(struct tg3 *tp)
6276{
6277 int i;
6278 u32 val;
6279
b5d3772c 6280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6281 /* Wait up to 20ms for init done. */
6282 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6283 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6284 return 0;
0ccead18 6285 udelay(100);
b5d3772c
MC		 6286 }
6287 return -ENODEV;
6288 }
6289
7a6f4369
MC		 6290 /* Wait for firmware initialization to complete. */
6291 for (i = 0; i < 100000; i++) {
6292 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6293 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6294 break;
6295 udelay(10);
6296 }
6297
6298 /* Chip might not be fitted with firmware. Some Sun onboard
6299 * parts are configured like that. So don't signal the timeout
6300 * of the above loop as an error, but do report the lack of
6301 * running firmware once.
6302 */
6303 if (i >= 100000 &&
6304 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6305 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6306
6307 printk(KERN_INFO PFX "%s: No firmware running.\n",
6308 tp->dev->name);
6309 }
6310
6311 return 0;
6312}
6313
ee6a99b5
MC		 6314/* Save PCI command register before chip reset */
6315static void tg3_save_pci_state(struct tg3 *tp)
6316{
8a6eac90 6317 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6318}
6319
6320/* Restore PCI state after chip reset */
6321static void tg3_restore_pci_state(struct tg3 *tp)
6322{
6323 u32 val;
6324
6325 /* Re-enable indirect register accesses. */
6326 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6327 tp->misc_host_ctrl);
6328
6329 /* Set MAX PCI retry to zero. */
6330 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6331 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6332 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6333 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6334 /* Allow reads and writes to the APE register and memory space. */
6335 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6336 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6337 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6338 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6339
8a6eac90 6340 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6341
fcb389df
MC		 6342 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6343 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6344 pcie_set_readrq(tp->pdev, 4096);
6345 else {
6346 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6347 tp->pci_cacheline_sz);
6348 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6349 tp->pci_lat_timer);
6350 }
114342f2 6351 }
5f5c51e3 6352
ee6a99b5 6353 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6354 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6355 u16 pcix_cmd;
6356
6357 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6358 &pcix_cmd);
6359 pcix_cmd &= ~PCI_X_CMD_ERO;
6360 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6361 pcix_cmd);
6362 }
ee6a99b5
MC		 6363
6364 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6365
6366 /* Chip reset on 5780 will reset MSI enable bit,
6367 * so need to restore it.
6368 */
6369 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6370 u16 ctrl;
6371
6372 pci_read_config_word(tp->pdev,
6373 tp->msi_cap + PCI_MSI_FLAGS,
6374 &ctrl);
6375 pci_write_config_word(tp->pdev,
6376 tp->msi_cap + PCI_MSI_FLAGS,
6377 ctrl | PCI_MSI_FLAGS_ENABLE);
6378 val = tr32(MSGINT_MODE);
6379 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6380 }
6381 }
6382}
6383
1da177e4
LT		 6384static void tg3_stop_fw(struct tg3 *);
6385
6386/* tp->lock is held. */
6387static int tg3_chip_reset(struct tg3 *tp)
6388{
6389 u32 val;
1ee582d8 6390 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6391 int i, err;
1da177e4 6392
f49639e6
DM		 6393 tg3_nvram_lock(tp);
6394
77b483f1
MC		 6395 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6396
f49639e6
DM		 6397 /* No matching tg3_nvram_unlock() after this because
6398 * chip reset below will undo the nvram lock.
6399 */
6400 tp->nvram_lock_cnt = 0;
1da177e4 6401
ee6a99b5
MC		 6402 /* GRC_MISC_CFG core clock reset will clear the memory
6403 * enable bit in PCI register 4 and the MSI enable bit
6404 * on some chips, so we save relevant registers here.
6405 */
6406 tg3_save_pci_state(tp);
6407
d9ab5ad1 6408 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6409 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6410 tw32(GRC_FASTBOOT_PC, 0);
6411
1da177e4
LT		 6412 /*
6413 * We must avoid the readl() that normally takes place.
6414 * It locks machines, causes machine checks, and other
6415 * fun things. So, temporarily disable the 5701
6416 * hardware workaround, while we do the reset.
6417 */
1ee582d8
MC		 6418 write_op = tp->write32;
6419 if (write_op == tg3_write_flush_reg32)
6420 tp->write32 = tg3_write32;
1da177e4 6421
d18edcb2
MC		 6422 /* Prevent the irq handler from reading or writing PCI registers
6423 * during chip reset when the memory enable bit in the PCI command
6424 * register may be cleared. The chip does not generate interrupt
6425 * at this time, but the irq handler may still be called due to irq
6426 * sharing or irqpoll.
6427 */
6428 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6429 for (i = 0; i < tp->irq_cnt; i++) {
6430 struct tg3_napi *tnapi = &tp->napi[i];
6431 if (tnapi->hw_status) {
6432 tnapi->hw_status->status = 0;
6433 tnapi->hw_status->status_tag = 0;
6434 }
6435 tnapi->last_tag = 0;
6436 tnapi->last_irq_tag = 0;
b8fa2f3a 6437 }
d18edcb2 6438 smp_mb();
4f125f42
MC		 6439
6440 for (i = 0; i < tp->irq_cnt; i++)
6441 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6442
255ca311
MC		 6443 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6444 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6445 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6446 }
6447
1da177e4
LT		 6448 /* do the reset */
6449 val = GRC_MISC_CFG_CORECLK_RESET;
6450
6451 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6452 if (tr32(0x7e2c) == 0x60) {
6453 tw32(0x7e2c, 0x20);
6454 }
6455 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6456 tw32(GRC_MISC_CFG, (1 << 29));
6457 val |= (1 << 29);
6458 }
6459 }
6460
b5d3772c
MC		 6461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6462 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6463 tw32(GRC_VCPU_EXT_CTRL,
6464 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6465 }
6466
1da177e4
LT		 6467 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6468 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6469 tw32(GRC_MISC_CFG, val);
6470
1ee582d8
MC		 6471 /* restore 5701 hardware bug workaround write method */
6472 tp->write32 = write_op;
1da177e4
LT		 6473
6474 /* Unfortunately, we have to delay before the PCI read back.
6475 * Some 575X chips even will not respond to a PCI cfg access
6476 * when the reset command is given to the chip.
6477 *
6478 * How do these hardware designers expect things to work
6479 * properly if the PCI write is posted for a long period
6480 * of time? It is always necessary to have some method by
6481 * which a register read back can occur to push the write
6482 * out which does the reset.
6483 *
6484 * For most tg3 variants the trick below was working.
6485 * Ho hum...
6486 */
6487 udelay(120);
6488
6489 /* Flush PCI posted writes. The normal MMIO registers
6490 * are inaccessible at this time so this is the only
6491 * way to make this reliably (actually, this is no longer
6492 * the case, see above). I tried to use indirect
6493 * register read/write but this upset some 5701 variants.
6494 */
6495 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6496
6497 udelay(120);
6498
5e7dfd0f 6499 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6500 u16 val16;
6501
1da177e4
LT		 6502 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6503 int i;
6504 u32 cfg_val;
6505
6506 /* Wait for link training to complete. */
6507 for (i = 0; i < 5000; i++)
6508 udelay(100);
6509
6510 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6511 pci_write_config_dword(tp->pdev, 0xc4,
6512 cfg_val | (1 << 15));
6513 }
5e7dfd0f 6514
e7126997
MC		 6515 /* Clear the "no snoop" and "relaxed ordering" bits. */
6516 pci_read_config_word(tp->pdev,
6517 tp->pcie_cap + PCI_EXP_DEVCTL,
6518 &val16);
6519 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6520 PCI_EXP_DEVCTL_NOSNOOP_EN);
6521 /*
6522 * Older PCIe devices only support the 128 byte
6523 * MPS setting. Enforce the restriction.
5e7dfd0f 6524 */
e7126997
MC		 6525 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6526 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6527 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6528 pci_write_config_word(tp->pdev,
6529 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6530 val16);
5e7dfd0f
MC		 6531
6532 pcie_set_readrq(tp->pdev, 4096);
6533
6534 /* Clear error status */
6535 pci_write_config_word(tp->pdev,
6536 tp->pcie_cap + PCI_EXP_DEVSTA,
6537 PCI_EXP_DEVSTA_CED |
6538 PCI_EXP_DEVSTA_NFED |
6539 PCI_EXP_DEVSTA_FED |
6540 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6541 }
6542
ee6a99b5 6543 tg3_restore_pci_state(tp);
1da177e4 6544
d18edcb2
MC		 6545 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6546
ee6a99b5
MC		 6547 val = 0;
6548 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6549 val = tr32(MEMARB_MODE);
ee6a99b5 6550 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6551
6552 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6553 tg3_stop_fw(tp);
6554 tw32(0x5000, 0x400);
6555 }
6556
6557 tw32(GRC_MODE, tp->grc_mode);
6558
6559 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6560 val = tr32(0xc4);
1da177e4
LT		 6561
6562 tw32(0xc4, val | (1 << 15));
6563 }
6564
6565 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6566 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6567 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6568 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6569 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6570 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6571 }
6572
6573 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6574 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6575 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6576 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6577 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6578 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6579 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6580 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6581 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6582 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6583 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6584 } else
6585 tw32_f(MAC_MODE, 0);
6586 udelay(40);
6587
77b483f1
MC		 6588 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6589
7a6f4369
MC		 6590 err = tg3_poll_fw(tp);
6591 if (err)
6592 return err;
1da177e4 6593
0a9140cf
MC		 6594 tg3_mdio_start(tp);
6595
52cdf852
MC		 6596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6597 u8 phy_addr;
6598
6599 phy_addr = tp->phy_addr;
6600 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6601
6602 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6603 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6604 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6605 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6606 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6607 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6608 udelay(10);
6609
6610 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6611 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6612 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6613 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6614 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6615 udelay(10);
6616
6617 tp->phy_addr = phy_addr;
6618 }
6619
1da177e4 6620 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6621 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6622 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6623 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6624 val = tr32(0x7c00);
1da177e4
LT		 6625
6626 tw32(0x7c00, val | (1 << 25));
6627 }
6628
6629 /* Reprobe ASF enable state. */
6630 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6631 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6632 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6633 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6634 u32 nic_cfg;
6635
6636 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6637 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6638 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6639 tp->last_event_jiffies = jiffies;
cbf46853 6640 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6641 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6642 }
6643 }
6644
6645 return 0;
6646}
6647
6648/* tp->lock is held. */
6649static void tg3_stop_fw(struct tg3 *tp)
6650{
0d3031d9
MC		 6651 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6652 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6653 /* Wait for RX cpu to ACK the previous event. */
6654 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6655
6656 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6657
6658 tg3_generate_fw_event(tp);
1da177e4 6659
7c5026aa
MC		 6660 /* Wait for RX cpu to ACK this event. */
6661 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6662 }
6663}
6664
6665/* tp->lock is held. */
944d980e 6666static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6667{
6668 int err;
6669
6670 tg3_stop_fw(tp);
6671
944d980e 6672 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6673
b3b7d6be 6674 tg3_abort_hw(tp, silent);
1da177e4
LT		 6675 err = tg3_chip_reset(tp);
6676
daba2a63
MC		 6677 __tg3_set_mac_addr(tp, 0);
6678
944d980e
MC		 6679 tg3_write_sig_legacy(tp, kind);
6680 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6681
6682 if (err)
6683 return err;
6684
6685 return 0;
6686}
6687
1da177e4
LT		 6688#define RX_CPU_SCRATCH_BASE 0x30000
6689#define RX_CPU_SCRATCH_SIZE 0x04000
6690#define TX_CPU_SCRATCH_BASE 0x34000
6691#define TX_CPU_SCRATCH_SIZE 0x04000
6692
6693/* tp->lock is held. */
6694static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6695{
6696 int i;
6697
5d9428de
ES		 6698 BUG_ON(offset == TX_CPU_BASE &&
6699 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6700
b5d3772c
MC		 6701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6702 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6703
6704 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6705 return 0;
6706 }
1da177e4
LT		 6707 if (offset == RX_CPU_BASE) {
6708 for (i = 0; i < 10000; i++) {
6709 tw32(offset + CPU_STATE, 0xffffffff);
6710 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6711 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6712 break;
6713 }
6714
6715 tw32(offset + CPU_STATE, 0xffffffff);
6716 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6717 udelay(10);
6718 } else {
6719 for (i = 0; i < 10000; i++) {
6720 tw32(offset + CPU_STATE, 0xffffffff);
6721 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6722 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6723 break;
6724 }
6725 }
6726
6727 if (i >= 10000) {
6728 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6729 "and %s CPU\n",
6730 tp->dev->name,
6731 (offset == RX_CPU_BASE ? "RX" : "TX"));
6732 return -ENODEV;
6733 }
ec41c7df
MC		 6734
6735 /* Clear firmware's nvram arbitration. */
6736 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6737 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6738 return 0;
6739}
6740
6741struct fw_info {
077f849d
JSR		 6742 unsigned int fw_base;
6743 unsigned int fw_len;
6744 const __be32 *fw_data;
1da177e4
LT		 6745};
6746
6747/* tp->lock is held. */
6748static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6749 int cpu_scratch_size, struct fw_info *info)
6750{
ec41c7df 6751 int err, lock_err, i;
1da177e4
LT		 6752 void (*write_op)(struct tg3 *, u32, u32);
6753
6754 if (cpu_base == TX_CPU_BASE &&
6755 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6756 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6757 "TX cpu firmware on %s which is 5705.\n",
6758 tp->dev->name);
6759 return -EINVAL;
6760 }
6761
6762 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6763 write_op = tg3_write_mem;
6764 else
6765 write_op = tg3_write_indirect_reg32;
6766
1b628151
MC		 6767 /* It is possible that bootcode is still loading at this point.
6768 * Get the nvram lock first before halting the cpu.
6769 */
ec41c7df 6770 lock_err = tg3_nvram_lock(tp);
1da177e4 6771 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6772 if (!lock_err)
6773 tg3_nvram_unlock(tp);
1da177e4
LT		 6774 if (err)
6775 goto out;
6776
6777 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6778 write_op(tp, cpu_scratch_base + i, 0);
6779 tw32(cpu_base + CPU_STATE, 0xffffffff);
6780 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6781 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6782 write_op(tp, (cpu_scratch_base +
077f849d 6783 (info->fw_base & 0xffff) +
1da177e4 6784 (i * sizeof(u32))),
077f849d 6785 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6786
6787 err = 0;
6788
6789out:
1da177e4
LT		 6790 return err;
6791}
6792
6793/* tp->lock is held. */
6794static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6795{
6796 struct fw_info info;
077f849d 6797 const __be32 *fw_data;
1da177e4
LT		 6798 int err, i;
6799
077f849d
JSR		 6800 fw_data = (void *)tp->fw->data;
6801
6802 /* Firmware blob starts with version numbers, followed by
6803 start address and length. We are setting complete length.
6804 length = end_address_of_bss - start_address_of_text.
6805 Remainder is the blob to be loaded contiguously
6806 from start address. */
6807
6808 info.fw_base = be32_to_cpu(fw_data[1]);
6809 info.fw_len = tp->fw->size - 12;
6810 info.fw_data = &fw_data[3];
1da177e4
LT		 6811
6812 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6813 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6814 &info);
6815 if (err)
6816 return err;
6817
6818 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6819 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6820 &info);
6821 if (err)
6822 return err;
6823
6824 /* Now startup only the RX cpu. */
6825 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6826 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6827
6828 for (i = 0; i < 5; i++) {
077f849d 6829 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6830 break;
6831 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6832 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6833 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6834 udelay(1000);
6835 }
6836 if (i >= 5) {
6837 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6838 "to set RX CPU PC, is %08x should be %08x\n",
6839 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6840 info.fw_base);
1da177e4
LT		 6841 return -ENODEV;
6842 }
6843 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6844 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6845
6846 return 0;
6847}
6848
1da177e4 6849/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6850
6851/* tp->lock is held. */
6852static int tg3_load_tso_firmware(struct tg3 *tp)
6853{
6854 struct fw_info info;
077f849d 6855 const __be32 *fw_data;
1da177e4
LT		 6856 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6857 int err, i;
6858
6859 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6860 return 0;
6861
077f849d
JSR		 6862 fw_data = (void *)tp->fw->data;
6863
6864 /* Firmware blob starts with version numbers, followed by
6865 start address and length. We are setting complete length.
6866 length = end_address_of_bss - start_address_of_text.
6867 Remainder is the blob to be loaded contiguously
6868 from start address. */
6869
6870 info.fw_base = be32_to_cpu(fw_data[1]);
6871 cpu_scratch_size = tp->fw_len;
6872 info.fw_len = tp->fw->size - 12;
6873 info.fw_data = &fw_data[3];
6874
1da177e4 6875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6876 cpu_base = RX_CPU_BASE;
6877 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6878 } else {
1da177e4
LT		 6879 cpu_base = TX_CPU_BASE;
6880 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6881 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6882 }
6883
6884 err = tg3_load_firmware_cpu(tp, cpu_base,
6885 cpu_scratch_base, cpu_scratch_size,
6886 &info);
6887 if (err)
6888 return err;
6889
6890 /* Now startup the cpu. */
6891 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6892 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6893
6894 for (i = 0; i < 5; i++) {
077f849d 6895 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6896 break;
6897 tw32(cpu_base + CPU_STATE, 0xffffffff);
6898 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6899 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6900 udelay(1000);
6901 }
6902 if (i >= 5) {
6903 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6904 "to set CPU PC, is %08x should be %08x\n",
6905 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6906 info.fw_base);
1da177e4
LT		 6907 return -ENODEV;
6908 }
6909 tw32(cpu_base + CPU_STATE, 0xffffffff);
6910 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6911 return 0;
6912}
6913
1da177e4 6914
1da177e4
LT		 6915static int tg3_set_mac_addr(struct net_device *dev, void *p)
6916{
6917 struct tg3 *tp = netdev_priv(dev);
6918 struct sockaddr *addr = p;
986e0aeb 6919 int err = 0, skip_mac_1 = 0;
1da177e4 6920
f9804ddb
MC		 6921 if (!is_valid_ether_addr(addr->sa_data))
6922 return -EINVAL;
6923
1da177e4
LT		 6924 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6925
e75f7c90
MC		 6926 if (!netif_running(dev))
6927 return 0;
6928
58712ef9 6929 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6930 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6931
986e0aeb
MC		 6932 addr0_high = tr32(MAC_ADDR_0_HIGH);
6933 addr0_low = tr32(MAC_ADDR_0_LOW);
6934 addr1_high = tr32(MAC_ADDR_1_HIGH);
6935 addr1_low = tr32(MAC_ADDR_1_LOW);
6936
6937 /* Skip MAC addr 1 if ASF is using it. */
6938 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6939 !(addr1_high == 0 && addr1_low == 0))
6940 skip_mac_1 = 1;
58712ef9 6941 }
986e0aeb
MC		 6942 spin_lock_bh(&tp->lock);
6943 __tg3_set_mac_addr(tp, skip_mac_1);
6944 spin_unlock_bh(&tp->lock);
1da177e4 6945
b9ec6c1b 6946 return err;
1da177e4
LT		 6947}
6948
6949/* tp->lock is held. */
6950static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6951 dma_addr_t mapping, u32 maxlen_flags,
6952 u32 nic_addr)
6953{
6954 tg3_write_mem(tp,
6955 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6956 ((u64) mapping >> 32));
6957 tg3_write_mem(tp,
6958 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6959 ((u64) mapping & 0xffffffff));
6960 tg3_write_mem(tp,
6961 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6962 maxlen_flags);
6963
6964 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6965 tg3_write_mem(tp,
6966 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6967 nic_addr);
6968}
6969
6970static void __tg3_set_rx_mode(struct net_device *);
d244c892 6971static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 6972{
b6080e12
MC		 6973 int i;
6974
6975 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6976 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6977 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6978 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6979
6980 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6981 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6982 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6983 } else {
6984 tw32(HOSTCC_TXCOL_TICKS, 0);
6985 tw32(HOSTCC_TXMAX_FRAMES, 0);
6986 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
6987
6988 tw32(HOSTCC_RXCOL_TICKS, 0);
6989 tw32(HOSTCC_RXMAX_FRAMES, 0);
6990 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 6991 }
b6080e12 6992
15f9850d
DM		 6993 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6994 u32 val = ec->stats_block_coalesce_usecs;
6995
b6080e12
MC		 6996 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6997 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6998
15f9850d
DM		 6999 if (!netif_carrier_ok(tp->dev))
7000 val = 0;
7001
7002 tw32(HOSTCC_STAT_COAL_TICKS, val);
7003 }
b6080e12
MC		 7004
7005 for (i = 0; i < tp->irq_cnt - 1; i++) {
7006 u32 reg;
7007
7008 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7009 tw32(reg, ec->rx_coalesce_usecs);
7010 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7011 tw32(reg, ec->tx_coalesce_usecs);
7012 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7013 tw32(reg, ec->rx_max_coalesced_frames);
7014 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7015 tw32(reg, ec->tx_max_coalesced_frames);
7016 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7017 tw32(reg, ec->rx_max_coalesced_frames_irq);
7018 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7019 tw32(reg, ec->tx_max_coalesced_frames_irq);
7020 }
7021
7022 for (; i < tp->irq_max - 1; i++) {
7023 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7024 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7025 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7026 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7027 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7028 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7029 }
15f9850d 7030}
1da177e4 7031
2d31ecaf
MC		 7032/* tp->lock is held. */
7033static void tg3_rings_reset(struct tg3 *tp)
7034{
7035 int i;
f77a6a8e 7036 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7037 struct tg3_napi *tnapi = &tp->napi[0];
7038
7039 /* Disable all transmit rings but the first. */
7040 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7041 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7042 else
7043 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7044
7045 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7046 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7047 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7048 BDINFO_FLAGS_DISABLED);
7049
7050
7051 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7053 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7054 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7055 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7056 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7057 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7058 else
7059 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7060
7061 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7062 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7063 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7064 BDINFO_FLAGS_DISABLED);
7065
7066 /* Disable interrupts */
7067 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7068
7069 /* Zero mailbox registers. */
f77a6a8e
MC		 7070 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7071 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7072 tp->napi[i].tx_prod = 0;
7073 tp->napi[i].tx_cons = 0;
7074 tw32_mailbox(tp->napi[i].prodmbox, 0);
7075 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7076 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7077 }
7078 } else {
7079 tp->napi[0].tx_prod = 0;
7080 tp->napi[0].tx_cons = 0;
7081 tw32_mailbox(tp->napi[0].prodmbox, 0);
7082 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7083 }
2d31ecaf
MC		 7084
7085 /* Make sure the NIC-based send BD rings are disabled. */
7086 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7087 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7088 for (i = 0; i < 16; i++)
7089 tw32_tx_mbox(mbox + i * 8, 0);
7090 }
7091
7092 txrcb = NIC_SRAM_SEND_RCB;
7093 rxrcb = NIC_SRAM_RCV_RET_RCB;
7094
7095 /* Clear status block in ram. */
7096 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7097
7098 /* Set status block DMA address */
7099 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7100 ((u64) tnapi->status_mapping >> 32));
7101 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7102 ((u64) tnapi->status_mapping & 0xffffffff));
7103
f77a6a8e
MC		 7104 if (tnapi->tx_ring) {
7105 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7106 (TG3_TX_RING_SIZE <<
7107 BDINFO_FLAGS_MAXLEN_SHIFT),
7108 NIC_SRAM_TX_BUFFER_DESC);
7109 txrcb += TG3_BDINFO_SIZE;
7110 }
7111
7112 if (tnapi->rx_rcb) {
7113 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7114 (TG3_RX_RCB_RING_SIZE(tp) <<
7115 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7116 rxrcb += TG3_BDINFO_SIZE;
7117 }
7118
7119 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7120
f77a6a8e
MC		 7121 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7122 u64 mapping = (u64)tnapi->status_mapping;
7123 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7124 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7125
7126 /* Clear status block in ram. */
7127 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7128
7129 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7130 (TG3_TX_RING_SIZE <<
7131 BDINFO_FLAGS_MAXLEN_SHIFT),
7132 NIC_SRAM_TX_BUFFER_DESC);
7133
7134 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7135 (TG3_RX_RCB_RING_SIZE(tp) <<
7136 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7137
7138 stblk += 8;
7139 txrcb += TG3_BDINFO_SIZE;
7140 rxrcb += TG3_BDINFO_SIZE;
7141 }
2d31ecaf
MC		 7142}
7143
1da177e4 7144/* tp->lock is held. */
8e7a22e3 7145static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7146{
7147 u32 val, rdmac_mode;
7148 int i, err, limit;
21f581a5 7149 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7150
7151 tg3_disable_ints(tp);
7152
7153 tg3_stop_fw(tp);
7154
7155 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7156
7157 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7158 tg3_abort_hw(tp, 1);
1da177e4
LT		 7159 }
7160
dd477003
MC		 7161 if (reset_phy &&
7162 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7163 tg3_phy_reset(tp);
7164
1da177e4
LT		 7165 err = tg3_chip_reset(tp);
7166 if (err)
7167 return err;
7168
7169 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7170
bcb37f6c 7171 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7172 val = tr32(TG3_CPMU_CTRL);
7173 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7174 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7175
7176 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7177 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7178 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7179 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7180
7181 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7182 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7183 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7184 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7185
7186 val = tr32(TG3_CPMU_HST_ACC);
7187 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7188 val |= CPMU_HST_ACC_MACCLK_6_25;
7189 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7190 }
7191
33466d93
MC		 7192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7193 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7194 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7195 PCIE_PWR_MGMT_L1_THRESH_4MS;
7196 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7197
7198 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7199 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7200
7201 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7202
f40386c8
MC		 7203 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7204 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7205 }
7206
1da177e4
LT		 7207 /* This works around an issue with Athlon chipsets on
7208 * B3 tigon3 silicon. This bit has no effect on any
7209 * other revision. But do not set this on PCI Express
795d01c5 7210 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7211 */
795d01c5
MC		 7212 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7213 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7214 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7215 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7216 }
1da177e4
LT		 7217
7218 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7219 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7220 val = tr32(TG3PCI_PCISTATE);
7221 val |= PCISTATE_RETRY_SAME_DMA;
7222 tw32(TG3PCI_PCISTATE, val);
7223 }
7224
0d3031d9
MC		 7225 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7226 /* Allow reads and writes to the
7227 * APE register and memory space.
7228 */
7229 val = tr32(TG3PCI_PCISTATE);
7230 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7231 PCISTATE_ALLOW_APE_SHMEM_WR;
7232 tw32(TG3PCI_PCISTATE, val);
7233 }
7234
1da177e4
LT		 7235 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7236 /* Enable some hw fixes. */
7237 val = tr32(TG3PCI_MSI_DATA);
7238 val |= (1 << 26) | (1 << 28) | (1 << 29);
7239 tw32(TG3PCI_MSI_DATA, val);
7240 }
7241
7242 /* Descriptor ring init may make accesses to the
7243 * NIC SRAM area to setup the TX descriptors, so we
7244 * can only do this after the hardware has been
7245 * successfully reset.
7246 */
32d8c572
MC		 7247 err = tg3_init_rings(tp);
7248 if (err)
7249 return err;
1da177e4 7250
9936bcf6 7251 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
f6eb9b1f
MC		 7252 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7253 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
d30cdd28
MC		 7254 /* This value is determined during the probe time DMA
7255 * engine test, tg3_test_dma.
7256 */
7257 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7258 }
1da177e4
LT		 7259
7260 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7261 GRC_MODE_4X_NIC_SEND_RINGS |
7262 GRC_MODE_NO_TX_PHDR_CSUM |
7263 GRC_MODE_NO_RX_PHDR_CSUM);
7264 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7265
7266 /* Pseudo-header checksum is done by hardware logic and not
7267 * the offload processers, so make the chip do the pseudo-
7268 * header checksums on receive. For transmit it is more
7269 * convenient to do the pseudo-header checksum in software
7270 * as Linux does that on transmit for us in all cases.
7271 */
7272 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7273
7274 tw32(GRC_MODE,
7275 tp->grc_mode |
7276 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7277
7278 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7279 val = tr32(GRC_MISC_CFG);
7280 val &= ~0xff;
7281 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7282 tw32(GRC_MISC_CFG, val);
7283
7284 /* Initialize MBUF/DESC pool. */
cbf46853 7285 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7286 /* Do nothing. */
7287 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7288 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7290 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7291 else
7292 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7293 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7294 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7295 }
1da177e4
LT		 7296 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7297 int fw_len;
7298
077f849d 7299 fw_len = tp->fw_len;
1da177e4
LT		 7300 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7301 tw32(BUFMGR_MB_POOL_ADDR,
7302 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7303 tw32(BUFMGR_MB_POOL_SIZE,
7304 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7305 }
1da177e4 7306
0f893dc6 7307 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7308 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7309 tp->bufmgr_config.mbuf_read_dma_low_water);
7310 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7311 tp->bufmgr_config.mbuf_mac_rx_low_water);
7312 tw32(BUFMGR_MB_HIGH_WATER,
7313 tp->bufmgr_config.mbuf_high_water);
7314 } else {
7315 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7316 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7317 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7318 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7319 tw32(BUFMGR_MB_HIGH_WATER,
7320 tp->bufmgr_config.mbuf_high_water_jumbo);
7321 }
7322 tw32(BUFMGR_DMA_LOW_WATER,
7323 tp->bufmgr_config.dma_low_water);
7324 tw32(BUFMGR_DMA_HIGH_WATER,
7325 tp->bufmgr_config.dma_high_water);
7326
7327 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7328 for (i = 0; i < 2000; i++) {
7329 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7330 break;
7331 udelay(10);
7332 }
7333 if (i >= 2000) {
7334 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7335 tp->dev->name);
7336 return -ENODEV;
7337 }
7338
7339 /* Setup replenish threshold. */
f92905de
MC		 7340 val = tp->rx_pending / 8;
7341 if (val == 0)
7342 val = 1;
7343 else if (val > tp->rx_std_max_post)
7344 val = tp->rx_std_max_post;
b5d3772c
MC		 7345 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7346 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7347 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7348
7349 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7350 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7351 }
f92905de
MC		 7352
7353 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7354
7355 /* Initialize TG3_BDINFO's at:
7356 * RCVDBDI_STD_BD: standard eth size rx ring
7357 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7358 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7359 *
7360 * like so:
7361 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7362 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7363 * ring attribute flags
7364 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7365 *
7366 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7367 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7368 *
7369 * The size of each ring is fixed in the firmware, but the location is
7370 * configurable.
7371 */
7372 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7373 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7374 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7375 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7376 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7377 NIC_SRAM_RX_BUFFER_DESC);
7378
fdb72b38
MC		 7379 /* Disable the mini ring */
7380 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7381 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7382 BDINFO_FLAGS_DISABLED);
7383
fdb72b38
MC		 7384 /* Program the jumbo buffer descriptor ring control
7385 * blocks on those devices that have them.
7386 */
8f666b07 7387 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7388 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7389 /* Setup replenish threshold. */
7390 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7391
0f893dc6 7392 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7393 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7394 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7395 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7396 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7397 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7398 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7399 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7400 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7401 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7402 } else {
7403 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7404 BDINFO_FLAGS_DISABLED);
7405 }
7406
f6eb9b1f
MC		 7407 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7408 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7409 (RX_STD_MAX_SIZE << 2);
7410 else
7411 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7412 } else
7413 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7414
7415 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7416
21f581a5 7417 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7418 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7419 tpr->rx_std_ptr);
1da177e4 7420
21f581a5
MC		 7421 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7422 tp->rx_jumbo_pending : 0;
1da177e4 7423 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7424 tpr->rx_jmb_ptr);
1da177e4 7425
f6eb9b1f
MC		 7426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7427 tw32(STD_REPLENISH_LWM, 32);
7428 tw32(JMB_REPLENISH_LWM, 16);
7429 }
7430
2d31ecaf
MC		 7431 tg3_rings_reset(tp);
7432
1da177e4 7433 /* Initialize MAC address and backoff seed. */
986e0aeb 7434 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7435
7436 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7437 tw32(MAC_RX_MTU_SIZE,
7438 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7439
7440 /* The slot time is changed by tg3_setup_phy if we
7441 * run at gigabit with half duplex.
7442 */
7443 tw32(MAC_TX_LENGTHS,
7444 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7445 (6 << TX_LENGTHS_IPG_SHIFT) |
7446 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7447
7448 /* Receive rules. */
7449 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7450 tw32(RCVLPC_CONFIG, 0x0181);
7451
7452 /* Calculate RDMAC_MODE setting early, we need it to determine
7453 * the RCVLPC_STATE_ENABLE mask.
7454 */
7455 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7456 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7457 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7458 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7459 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7460
57e6983c 7461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7462 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7463 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7464 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7465 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7466 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7467
85e94ced
MC		 7468 /* If statement applies to 5705 and 5750 PCI devices only */
7469 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7470 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7471 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7472 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7474 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7475 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7476 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7477 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7478 }
7479 }
7480
85e94ced
MC		 7481 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7482 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7483
1da177e4 7484 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7485 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7486
7487 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7488 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7489 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7490
7491 /* Receive/send statistics. */
1661394e
MC		 7492 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7493 val = tr32(RCVLPC_STATS_ENABLE);
7494 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7495 tw32(RCVLPC_STATS_ENABLE, val);
7496 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7497 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7498 val = tr32(RCVLPC_STATS_ENABLE);
7499 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7500 tw32(RCVLPC_STATS_ENABLE, val);
7501 } else {
7502 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7503 }
7504 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7505 tw32(SNDDATAI_STATSENAB, 0xffffff);
7506 tw32(SNDDATAI_STATSCTRL,
7507 (SNDDATAI_SCTRL_ENABLE |
7508 SNDDATAI_SCTRL_FASTUPD));
7509
7510 /* Setup host coalescing engine. */
7511 tw32(HOSTCC_MODE, 0);
7512 for (i = 0; i < 2000; i++) {
7513 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7514 break;
7515 udelay(10);
7516 }
7517
d244c892 7518 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7519
1da177e4
LT		 7520 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7521 /* Status/statistics block address. See tg3_timer,
7522 * the tg3_periodic_fetch_stats call there, and
7523 * tg3_get_stats to see how this works for 5705/5750 chips.
7524 */
1da177e4
LT		 7525 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7526 ((u64) tp->stats_mapping >> 32));
7527 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7528 ((u64) tp->stats_mapping & 0xffffffff));
7529 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7530
1da177e4 7531 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7532
7533 /* Clear statistics and status block memory areas */
7534 for (i = NIC_SRAM_STATS_BLK;
7535 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7536 i += sizeof(u32)) {
7537 tg3_write_mem(tp, i, 0);
7538 udelay(40);
7539 }
1da177e4
LT		 7540 }
7541
7542 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7543
7544 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7545 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7546 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7547 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7548
c94e3941
MC		 7549 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7550 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7551 /* reset to prevent losing 1st rx packet intermittently */
7552 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7553 udelay(10);
7554 }
7555
3bda1258
MC		 7556 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7557 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7558 else
7559 tp->mac_mode = 0;
7560 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7561 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7562 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7563 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7564 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7565 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7566 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7567 udelay(40);
7568
314fba34 7569 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7570 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7571 * register to preserve the GPIO settings for LOMs. The GPIOs,
7572 * whether used as inputs or outputs, are set by boot code after
7573 * reset.
7574 */
9d26e213 7575 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7576 u32 gpio_mask;
7577
9d26e213
MC		 7578 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7579 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7580 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7581
7582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7583 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7584 GRC_LCLCTRL_GPIO_OUTPUT3;
7585
af36e6b6
MC		 7586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7587 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7588
aaf84465 7589 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7590 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7591
7592 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7593 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7594 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7595 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7596 }
1da177e4
LT		 7597 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7598 udelay(100);
7599
baf8a94a
MC		 7600 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7601 val = tr32(MSGINT_MODE);
7602 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7603 tw32(MSGINT_MODE, val);
7604 }
7605
1da177e4
LT		 7606 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7607 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7608 udelay(40);
7609 }
7610
7611 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7612 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7613 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7614 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7615 WDMAC_MODE_LNGREAD_ENAB);
7616
85e94ced
MC		 7617 /* If statement applies to 5705 and 5750 PCI devices only */
7618 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7619 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7621 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7622 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7623 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7624 /* nothing */
7625 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7626 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7627 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7628 val |= WDMAC_MODE_RX_ACCEL;
7629 }
7630 }
7631
d9ab5ad1 7632 /* Enable host coalescing bug fix */
321d32a0 7633 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7634 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7635
788a035e
MC		 7636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7637 val |= WDMAC_MODE_BURST_ALL_DATA;
7638
1da177e4
LT		 7639 tw32_f(WDMAC_MODE, val);
7640 udelay(40);
7641
9974a356
MC		 7642 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7643 u16 pcix_cmd;
7644
7645 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7646 &pcix_cmd);
1da177e4 7647 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7648 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7649 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7650 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7651 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7652 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7653 }
9974a356
MC		 7654 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7655 pcix_cmd);
1da177e4
LT		 7656 }
7657
7658 tw32_f(RDMAC_MODE, rdmac_mode);
7659 udelay(40);
7660
7661 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7662 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7663 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7664
7665 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7666 tw32(SNDDATAC_MODE,
7667 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7668 else
7669 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7670
1da177e4
LT		 7671 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7672 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7673 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7674 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7675 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7676 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7677 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7678 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7679 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7680 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7681 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7682
7683 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7684 err = tg3_load_5701_a0_firmware_fix(tp);
7685 if (err)
7686 return err;
7687 }
7688
1da177e4
LT		 7689 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7690 err = tg3_load_tso_firmware(tp);
7691 if (err)
7692 return err;
7693 }
1da177e4
LT		 7694
7695 tp->tx_mode = TX_MODE_ENABLE;
7696 tw32_f(MAC_TX_MODE, tp->tx_mode);
7697 udelay(100);
7698
baf8a94a
MC		 7699 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7700 u32 reg = MAC_RSS_INDIR_TBL_0;
7701 u8 *ent = (u8 *)&val;
7702
7703 /* Setup the indirection table */
7704 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7705 int idx = i % sizeof(val);
7706
7707 ent[idx] = i % (tp->irq_cnt - 1);
7708 if (idx == sizeof(val) - 1) {
7709 tw32(reg, val);
7710 reg += 4;
7711 }
7712 }
7713
7714 /* Setup the "secret" hash key. */
7715 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7716 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7717 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7718 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7719 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7720 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7721 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7722 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7723 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7724 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7725 }
7726
1da177e4 7727 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7728 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7729 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7730
baf8a94a
MC		 7731 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7732 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7733 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7734 RX_MODE_RSS_IPV6_HASH_EN |
7735 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7736 RX_MODE_RSS_IPV4_HASH_EN |
7737 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7738
1da177e4
LT		 7739 tw32_f(MAC_RX_MODE, tp->rx_mode);
7740 udelay(10);
7741
1da177e4
LT		 7742 tw32(MAC_LED_CTRL, tp->led_ctrl);
7743
7744 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7745 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7746 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7747 udelay(10);
7748 }
7749 tw32_f(MAC_RX_MODE, tp->rx_mode);
7750 udelay(10);
7751
7752 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7753 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7754 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7755 /* Set drive transmission level to 1.2V */
7756 /* only if the signal pre-emphasis bit is not set */
7757 val = tr32(MAC_SERDES_CFG);
7758 val &= 0xfffff000;
7759 val |= 0x880;
7760 tw32(MAC_SERDES_CFG, val);
7761 }
7762 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7763 tw32(MAC_SERDES_CFG, 0x616000);
7764 }
7765
7766 /* Prevent chip from dropping frames when flow control
7767 * is enabled.
7768 */
7769 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7770
7771 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7772 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7773 /* Use hardware link auto-negotiation */
7774 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7775 }
7776
d4d2c558
MC		 7777 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7778 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7779 u32 tmp;
7780
7781 tmp = tr32(SERDES_RX_CTRL);
7782 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7783 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7784 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7785 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7786 }
7787
dd477003
MC		 7788 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7789 if (tp->link_config.phy_is_low_power) {
7790 tp->link_config.phy_is_low_power = 0;
7791 tp->link_config.speed = tp->link_config.orig_speed;
7792 tp->link_config.duplex = tp->link_config.orig_duplex;
7793 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7794 }
1da177e4 7795
dd477003
MC		 7796 err = tg3_setup_phy(tp, 0);
7797 if (err)
7798 return err;
1da177e4 7799
dd477003 7800 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7801 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7802 u32 tmp;
7803
7804 /* Clear CRC stats. */
7805 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7806 tg3_writephy(tp, MII_TG3_TEST1,
7807 tmp | MII_TG3_TEST1_CRC_EN);
7808 tg3_readphy(tp, 0x14, &tmp);
7809 }
1da177e4
LT		 7810 }
7811 }
7812
7813 __tg3_set_rx_mode(tp->dev);
7814
7815 /* Initialize receive rules. */
7816 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7817 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7818 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7819 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7820
4cf78e4f 7821 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7822 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7823 limit = 8;
7824 else
7825 limit = 16;
7826 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7827 limit -= 4;
7828 switch (limit) {
7829 case 16:
7830 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7831 case 15:
7832 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7833 case 14:
7834 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7835 case 13:
7836 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7837 case 12:
7838 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7839 case 11:
7840 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7841 case 10:
7842 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7843 case 9:
7844 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7845 case 8:
7846 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7847 case 7:
7848 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7849 case 6:
7850 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7851 case 5:
7852 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7853 case 4:
7854 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7855 case 3:
7856 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7857 case 2:
7858 case 1:
7859
7860 default:
7861 break;
855e1111 7862 }
1da177e4 7863
9ce768ea
MC		 7864 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7865 /* Write our heartbeat update interval to APE. */
7866 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7867 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7868
1da177e4
LT		 7869 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7870
1da177e4
LT		 7871 return 0;
7872}
7873
7874/* Called at device open time to get the chip ready for
7875 * packet processing. Invoked with tp->lock held.
7876 */
8e7a22e3 7877static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7878{
1da177e4
LT		 7879 tg3_switch_clocks(tp);
7880
7881 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7882
2f751b67 7883 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7884}
7885
7886#define TG3_STAT_ADD32(PSTAT, REG) \
7887do { u32 __val = tr32(REG); \
7888 (PSTAT)->low += __val; \
7889 if ((PSTAT)->low < __val) \
7890 (PSTAT)->high += 1; \
7891} while (0)
7892
7893static void tg3_periodic_fetch_stats(struct tg3 *tp)
7894{
7895 struct tg3_hw_stats *sp = tp->hw_stats;
7896
7897 if (!netif_carrier_ok(tp->dev))
7898 return;
7899
7900 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7901 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7902 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7903 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7904 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7905 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7906 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7907 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7908 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7909 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7910 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7911 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7912 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7913
7914 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7915 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7916 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7917 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7918 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7919 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7920 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7921 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7922 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7923 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7924 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7925 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7926 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7927 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7928
7929 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7930 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7931 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7932}
7933
7934static void tg3_timer(unsigned long __opaque)
7935{
7936 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7937
f475f163
MC		 7938 if (tp->irq_sync)
7939 goto restart_timer;
7940
f47c11ee 7941 spin_lock(&tp->lock);
1da177e4 7942
fac9b83e
DM		 7943 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7944 /* All of this garbage is because when using non-tagged
7945 * IRQ status the mailbox/status_block protocol the chip
7946 * uses with the cpu is race prone.
7947 */
898a56f8 7948 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7949 tw32(GRC_LOCAL_CTRL,
7950 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7951 } else {
7952 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7953 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7954 }
1da177e4 7955
fac9b83e
DM		 7956 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7957 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7958 spin_unlock(&tp->lock);
fac9b83e
DM		 7959 schedule_work(&tp->reset_task);
7960 return;
7961 }
1da177e4
LT		 7962 }
7963
1da177e4
LT		 7964 /* This part only runs once per second. */
7965 if (!--tp->timer_counter) {
fac9b83e
DM		 7966 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7967 tg3_periodic_fetch_stats(tp);
7968
1da177e4
LT		 7969 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7970 u32 mac_stat;
7971 int phy_event;
7972
7973 mac_stat = tr32(MAC_STATUS);
7974
7975 phy_event = 0;
7976 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7977 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7978 phy_event = 1;
7979 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7980 phy_event = 1;
7981
7982 if (phy_event)
7983 tg3_setup_phy(tp, 0);
7984 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7985 u32 mac_stat = tr32(MAC_STATUS);
7986 int need_setup = 0;
7987
7988 if (netif_carrier_ok(tp->dev) &&
7989 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7990 need_setup = 1;
7991 }
7992 if (! netif_carrier_ok(tp->dev) &&
7993 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7994 MAC_STATUS_SIGNAL_DET))) {
7995 need_setup = 1;
7996 }
7997 if (need_setup) {
3d3ebe74
MC		 7998 if (!tp->serdes_counter) {
7999 tw32_f(MAC_MODE,
8000 (tp->mac_mode &
8001 ~MAC_MODE_PORT_MODE_MASK));
8002 udelay(40);
8003 tw32_f(MAC_MODE, tp->mac_mode);
8004 udelay(40);
8005 }
1da177e4
LT		 8006 tg3_setup_phy(tp, 0);
8007 }
747e8f8b
MC		 8008 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8009 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8010
8011 tp->timer_counter = tp->timer_multiplier;
8012 }
8013
130b8e4d
MC		 8014 /* Heartbeat is only sent once every 2 seconds.
8015 *
8016 * The heartbeat is to tell the ASF firmware that the host
8017 * driver is still alive. In the event that the OS crashes,
8018 * ASF needs to reset the hardware to free up the FIFO space
8019 * that may be filled with rx packets destined for the host.
8020 * If the FIFO is full, ASF will no longer function properly.
8021 *
8022 * Unintended resets have been reported on real time kernels
8023 * where the timer doesn't run on time. Netpoll will also have
8024 * same problem.
8025 *
8026 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8027 * to check the ring condition when the heartbeat is expiring
8028 * before doing the reset. This will prevent most unintended
8029 * resets.
8030 */
1da177e4 8031 if (!--tp->asf_counter) {
bc7959b2
MC		 8032 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8033 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8034 tg3_wait_for_event_ack(tp);
8035
bbadf503 8036 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8037 FWCMD_NICDRV_ALIVE3);
bbadf503 8038 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8039 /* 5 seconds timeout */
bbadf503 8040 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8041
8042 tg3_generate_fw_event(tp);
1da177e4
LT		 8043 }
8044 tp->asf_counter = tp->asf_multiplier;
8045 }
8046
f47c11ee 8047 spin_unlock(&tp->lock);
1da177e4 8048
f475f163 8049restart_timer:
1da177e4
LT		 8050 tp->timer.expires = jiffies + tp->timer_offset;
8051 add_timer(&tp->timer);
8052}
8053
4f125f42 8054static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8055{
7d12e780 8056 irq_handler_t fn;
fcfa0a32 8057 unsigned long flags;
4f125f42
MC		 8058 char *name;
8059 struct tg3_napi *tnapi = &tp->napi[irq_num];
8060
8061 if (tp->irq_cnt == 1)
8062 name = tp->dev->name;
8063 else {
8064 name = &tnapi->irq_lbl[0];
8065 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8066 name[IFNAMSIZ-1] = 0;
8067 }
fcfa0a32 8068
679563f4 8069 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8070 fn = tg3_msi;
8071 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8072 fn = tg3_msi_1shot;
1fb9df5d 8073 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8074 } else {
8075 fn = tg3_interrupt;
8076 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8077 fn = tg3_interrupt_tagged;
1fb9df5d 8078 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8079 }
4f125f42
MC		 8080
8081 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8082}
8083
7938109f
MC		 8084static int tg3_test_interrupt(struct tg3 *tp)
8085{
09943a18 8086 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8087 struct net_device *dev = tp->dev;
b16250e3 8088 int err, i, intr_ok = 0;
f6eb9b1f 8089 u32 val;
7938109f 8090
d4bc3927
MC		 8091 if (!netif_running(dev))
8092 return -ENODEV;
8093
7938109f
MC		 8094 tg3_disable_ints(tp);
8095
4f125f42 8096 free_irq(tnapi->irq_vec, tnapi);
7938109f 8097
f6eb9b1f
MC		 8098 /*
8099 * Turn off MSI one shot mode. Otherwise this test has no
8100 * observable way to know whether the interrupt was delivered.
8101 */
8102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8103 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8104 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8105 tw32(MSGINT_MODE, val);
8106 }
8107
4f125f42 8108 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8109 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8110 if (err)
8111 return err;
8112
898a56f8 8113 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8114 tg3_enable_ints(tp);
8115
8116 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8117 tnapi->coal_now);
7938109f
MC		 8118
8119 for (i = 0; i < 5; i++) {
b16250e3
MC		 8120 u32 int_mbox, misc_host_ctrl;
8121
898a56f8 8122 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8123 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8124
8125 if ((int_mbox != 0) ||
8126 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8127 intr_ok = 1;
7938109f 8128 break;
b16250e3
MC		 8129 }
8130
7938109f
MC		 8131 msleep(10);
8132 }
8133
8134 tg3_disable_ints(tp);
8135
4f125f42 8136 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8137
4f125f42 8138 err = tg3_request_irq(tp, 0);
7938109f
MC		 8139
8140 if (err)
8141 return err;
8142
f6eb9b1f
MC		 8143 if (intr_ok) {
8144 /* Reenable MSI one shot mode. */
8145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8146 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8147 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8148 tw32(MSGINT_MODE, val);
8149 }
7938109f 8150 return 0;
f6eb9b1f 8151 }
7938109f
MC		 8152
8153 return -EIO;
8154}
8155
8156/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8157 * successfully restored
8158 */
8159static int tg3_test_msi(struct tg3 *tp)
8160{
7938109f
MC		 8161 int err;
8162 u16 pci_cmd;
8163
8164 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8165 return 0;
8166
8167 /* Turn off SERR reporting in case MSI terminates with Master
8168 * Abort.
8169 */
8170 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8171 pci_write_config_word(tp->pdev, PCI_COMMAND,
8172 pci_cmd & ~PCI_COMMAND_SERR);
8173
8174 err = tg3_test_interrupt(tp);
8175
8176 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8177
8178 if (!err)
8179 return 0;
8180
8181 /* other failures */
8182 if (err != -EIO)
8183 return err;
8184
8185 /* MSI test failed, go back to INTx mode */
8186 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8187 "switching to INTx mode. Please report this failure to "
8188 "the PCI maintainer and include system chipset information.\n",
8189 tp->dev->name);
8190
4f125f42 8191 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8192
7938109f
MC		 8193 pci_disable_msi(tp->pdev);
8194
8195 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8196
4f125f42 8197 err = tg3_request_irq(tp, 0);
7938109f
MC		 8198 if (err)
8199 return err;
8200
8201 /* Need to reset the chip because the MSI cycle may have terminated
8202 * with Master Abort.
8203 */
f47c11ee 8204 tg3_full_lock(tp, 1);
7938109f 8205
944d980e 8206 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8207 err = tg3_init_hw(tp, 1);
7938109f 8208
f47c11ee 8209 tg3_full_unlock(tp);
7938109f
MC		 8210
8211 if (err)
4f125f42 8212 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8213
8214 return err;
8215}
8216
9e9fd12d
MC		 8217static int tg3_request_firmware(struct tg3 *tp)
8218{
8219 const __be32 *fw_data;
8220
8221 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8222 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8223 tp->dev->name, tp->fw_needed);
8224 return -ENOENT;
8225 }
8226
8227 fw_data = (void *)tp->fw->data;
8228
8229 /* Firmware blob starts with version numbers, followed by
8230 * start address and _full_ length including BSS sections
8231 * (which must be longer than the actual data, of course
8232 */
8233
8234 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8235 if (tp->fw_len < (tp->fw->size - 12)) {
8236 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8237 tp->dev->name, tp->fw_len, tp->fw_needed);
8238 release_firmware(tp->fw);
8239 tp->fw = NULL;
8240 return -EINVAL;
8241 }
8242
8243 /* We no longer need firmware; we have it. */
8244 tp->fw_needed = NULL;
8245 return 0;
8246}
8247
679563f4
MC		 8248static bool tg3_enable_msix(struct tg3 *tp)
8249{
8250 int i, rc, cpus = num_online_cpus();
8251 struct msix_entry msix_ent[tp->irq_max];
8252
8253 if (cpus == 1)
8254 /* Just fallback to the simpler MSI mode. */
8255 return false;
8256
8257 /*
8258 * We want as many rx rings enabled as there are cpus.
8259 * The first MSIX vector only deals with link interrupts, etc,
8260 * so we add one to the number of vectors we are requesting.
8261 */
8262 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8263
8264 for (i = 0; i < tp->irq_max; i++) {
8265 msix_ent[i].entry = i;
8266 msix_ent[i].vector = 0;
8267 }
8268
8269 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8270 if (rc != 0) {
8271 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8272 return false;
8273 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8274 return false;
8275 printk(KERN_NOTICE
8276 "%s: Requested %d MSI-X vectors, received %d\n",
8277 tp->dev->name, tp->irq_cnt, rc);
8278 tp->irq_cnt = rc;
8279 }
8280
baf8a94a
MC		 8281 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8282
679563f4
MC		 8283 for (i = 0; i < tp->irq_max; i++)
8284 tp->napi[i].irq_vec = msix_ent[i].vector;
8285
fe5f5787
MC		 8286 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8287
679563f4
MC		 8288 return true;
8289}
8290
07b0173c
MC		 8291static void tg3_ints_init(struct tg3 *tp)
8292{
679563f4
MC		 8293 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8294 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8295 /* All MSI supporting chips should support tagged
8296 * status. Assert that this is the case.
8297 */
679563f4
MC		 8298 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8299 "Not using MSI.\n", tp->dev->name);
8300 goto defcfg;
07b0173c 8301 }
4f125f42 8302
679563f4
MC		 8303 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8304 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8305 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8306 pci_enable_msi(tp->pdev) == 0)
8307 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8308
8309 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8310 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8311 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8312 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8313 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8314 }
8315defcfg:
8316 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8317 tp->irq_cnt = 1;
8318 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8319 tp->dev->real_num_tx_queues = 1;
679563f4 8320 }
07b0173c
MC		 8321}
8322
8323static void tg3_ints_fini(struct tg3 *tp)
8324{
679563f4
MC		 8325 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8326 pci_disable_msix(tp->pdev);
8327 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8328 pci_disable_msi(tp->pdev);
8329 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8330 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8331}
8332
1da177e4
LT		 8333static int tg3_open(struct net_device *dev)
8334{
8335 struct tg3 *tp = netdev_priv(dev);
4f125f42 8336 int i, err;
1da177e4 8337
9e9fd12d
MC		 8338 if (tp->fw_needed) {
8339 err = tg3_request_firmware(tp);
8340 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8341 if (err)
8342 return err;
8343 } else if (err) {
8344 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8345 tp->dev->name);
8346 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8347 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8348 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8349 tp->dev->name);
8350 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8351 }
8352 }
8353
c49a1561
MC		 8354 netif_carrier_off(tp->dev);
8355
bc1c7567 8356 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8357 if (err)
bc1c7567 8358 return err;
2f751b67
MC		 8359
8360 tg3_full_lock(tp, 0);
bc1c7567 8361
1da177e4
LT		 8362 tg3_disable_ints(tp);
8363 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8364
f47c11ee 8365 tg3_full_unlock(tp);
1da177e4 8366
679563f4
MC		 8367 /*
8368 * Setup interrupts first so we know how
8369 * many NAPI resources to allocate
8370 */
8371 tg3_ints_init(tp);
8372
1da177e4
LT		 8373 /* The placement of this call is tied
8374 * to the setup and use of Host TX descriptors.
8375 */
8376 err = tg3_alloc_consistent(tp);
8377 if (err)
679563f4 8378 goto err_out1;
88b06bc2 8379
fed97810 8380 tg3_napi_enable(tp);
1da177e4 8381
4f125f42
MC		 8382 for (i = 0; i < tp->irq_cnt; i++) {
8383 struct tg3_napi *tnapi = &tp->napi[i];
8384 err = tg3_request_irq(tp, i);
8385 if (err) {
8386 for (i--; i >= 0; i--)
8387 free_irq(tnapi->irq_vec, tnapi);
8388 break;
8389 }
8390 }
1da177e4 8391
07b0173c 8392 if (err)
679563f4 8393 goto err_out2;
bea3348e 8394
f47c11ee 8395 tg3_full_lock(tp, 0);
1da177e4 8396
8e7a22e3 8397 err = tg3_init_hw(tp, 1);
1da177e4 8398 if (err) {
944d980e 8399 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8400 tg3_free_rings(tp);
8401 } else {
fac9b83e
DM		 8402 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8403 tp->timer_offset = HZ;
8404 else
8405 tp->timer_offset = HZ / 10;
8406
8407 BUG_ON(tp->timer_offset > HZ);
8408 tp->timer_counter = tp->timer_multiplier =
8409 (HZ / tp->timer_offset);
8410 tp->asf_counter = tp->asf_multiplier =
28fbef78 8411 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8412
8413 init_timer(&tp->timer);
8414 tp->timer.expires = jiffies + tp->timer_offset;
8415 tp->timer.data = (unsigned long) tp;
8416 tp->timer.function = tg3_timer;
1da177e4
LT		 8417 }
8418
f47c11ee 8419 tg3_full_unlock(tp);
1da177e4 8420
07b0173c 8421 if (err)
679563f4 8422 goto err_out3;
1da177e4 8423
7938109f
MC		 8424 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8425 err = tg3_test_msi(tp);
fac9b83e 8426
7938109f 8427 if (err) {
f47c11ee 8428 tg3_full_lock(tp, 0);
944d980e 8429 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8430 tg3_free_rings(tp);
f47c11ee 8431 tg3_full_unlock(tp);
7938109f 8432
679563f4 8433 goto err_out2;
7938109f 8434 }
fcfa0a32 8435
f6eb9b1f
MC		 8436 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8437 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8438 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8439 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8440
f6eb9b1f
MC		 8441 tw32(PCIE_TRANSACTION_CFG,
8442 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8443 }
7938109f
MC		 8444 }
8445
b02fd9e3
MC		 8446 tg3_phy_start(tp);
8447
f47c11ee 8448 tg3_full_lock(tp, 0);
1da177e4 8449
7938109f
MC		 8450 add_timer(&tp->timer);
8451 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8452 tg3_enable_ints(tp);
8453
f47c11ee 8454 tg3_full_unlock(tp);
1da177e4 8455
fe5f5787 8456 netif_tx_start_all_queues(dev);
1da177e4
LT		 8457
8458 return 0;
07b0173c 8459
679563f4 8460err_out3:
4f125f42
MC		 8461 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8462 struct tg3_napi *tnapi = &tp->napi[i];
8463 free_irq(tnapi->irq_vec, tnapi);
8464 }
07b0173c 8465
679563f4 8466err_out2:
fed97810 8467 tg3_napi_disable(tp);
07b0173c 8468 tg3_free_consistent(tp);
679563f4
MC		 8469
8470err_out1:
8471 tg3_ints_fini(tp);
07b0173c 8472 return err;
1da177e4
LT		 8473}
8474
8475#if 0
8476/*static*/ void tg3_dump_state(struct tg3 *tp)
8477{
8478 u32 val32, val32_2, val32_3, val32_4, val32_5;
8479 u16 val16;
8480 int i;
898a56f8 8481 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8482
8483 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8484 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8485 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8486 val16, val32);
8487
8488 /* MAC block */
8489 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8490 tr32(MAC_MODE), tr32(MAC_STATUS));
8491 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8492 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8493 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8494 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8495 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8496 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8497
8498 /* Send data initiator control block */
8499 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8500 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8501 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8502 tr32(SNDDATAI_STATSCTRL));
8503
8504 /* Send data completion control block */
8505 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8506
8507 /* Send BD ring selector block */
8508 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8509 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8510
8511 /* Send BD initiator control block */
8512 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8513 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8514
8515 /* Send BD completion control block */
8516 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8517
8518 /* Receive list placement control block */
8519 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8520 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8521 printk(" RCVLPC_STATSCTRL[%08x]\n",
8522 tr32(RCVLPC_STATSCTRL));
8523
8524 /* Receive data and receive BD initiator control block */
8525 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8526 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8527
8528 /* Receive data completion control block */
8529 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8530 tr32(RCVDCC_MODE));
8531
8532 /* Receive BD initiator control block */
8533 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8534 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8535
8536 /* Receive BD completion control block */
8537 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8538 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8539
8540 /* Receive list selector control block */
8541 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8542 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8543
8544 /* Mbuf cluster free block */
8545 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8546 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8547
8548 /* Host coalescing control block */
8549 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8550 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8551 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8552 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8553 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8554 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8555 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8556 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8557 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8558 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8559 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8560 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8561
8562 /* Memory arbiter control block */
8563 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8564 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8565
8566 /* Buffer manager control block */
8567 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8568 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8569 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8570 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8571 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8572 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8573 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8574 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8575
8576 /* Read DMA control block */
8577 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8578 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8579
8580 /* Write DMA control block */
8581 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8582 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8583
8584 /* DMA completion block */
8585 printk("DEBUG: DMAC_MODE[%08x]\n",
8586 tr32(DMAC_MODE));
8587
8588 /* GRC block */
8589 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8590 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8591 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8592 tr32(GRC_LOCAL_CTRL));
8593
8594 /* TG3_BDINFOs */
8595 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8596 tr32(RCVDBDI_JUMBO_BD + 0x0),
8597 tr32(RCVDBDI_JUMBO_BD + 0x4),
8598 tr32(RCVDBDI_JUMBO_BD + 0x8),
8599 tr32(RCVDBDI_JUMBO_BD + 0xc));
8600 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8601 tr32(RCVDBDI_STD_BD + 0x0),
8602 tr32(RCVDBDI_STD_BD + 0x4),
8603 tr32(RCVDBDI_STD_BD + 0x8),
8604 tr32(RCVDBDI_STD_BD + 0xc));
8605 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8606 tr32(RCVDBDI_MINI_BD + 0x0),
8607 tr32(RCVDBDI_MINI_BD + 0x4),
8608 tr32(RCVDBDI_MINI_BD + 0x8),
8609 tr32(RCVDBDI_MINI_BD + 0xc));
8610
8611 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8612 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8613 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8614 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8615 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8616 val32, val32_2, val32_3, val32_4);
8617
8618 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8619 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8620 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8621 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8622 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8623 val32, val32_2, val32_3, val32_4);
8624
8625 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8626 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8627 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8628 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8629 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8630 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8631 val32, val32_2, val32_3, val32_4, val32_5);
8632
8633 /* SW status block */
898a56f8
MC		 8634 printk(KERN_DEBUG
8635 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8636 sblk->status,
8637 sblk->status_tag,
8638 sblk->rx_jumbo_consumer,
8639 sblk->rx_consumer,
8640 sblk->rx_mini_consumer,
8641 sblk->idx[0].rx_producer,
8642 sblk->idx[0].tx_consumer);
1da177e4
LT		 8643
8644 /* SW statistics block */
8645 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8646 ((u32 *)tp->hw_stats)[0],
8647 ((u32 *)tp->hw_stats)[1],
8648 ((u32 *)tp->hw_stats)[2],
8649 ((u32 *)tp->hw_stats)[3]);
8650
8651 /* Mailboxes */
8652 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8653 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8654 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8655 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8656 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8657
8658 /* NIC side send descriptors. */
8659 for (i = 0; i < 6; i++) {
8660 unsigned long txd;
8661
8662 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8663 + (i * sizeof(struct tg3_tx_buffer_desc));
8664 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8665 i,
8666 readl(txd + 0x0), readl(txd + 0x4),
8667 readl(txd + 0x8), readl(txd + 0xc));
8668 }
8669
8670 /* NIC side RX descriptors. */
8671 for (i = 0; i < 6; i++) {
8672 unsigned long rxd;
8673
8674 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8675 + (i * sizeof(struct tg3_rx_buffer_desc));
8676 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8677 i,
8678 readl(rxd + 0x0), readl(rxd + 0x4),
8679 readl(rxd + 0x8), readl(rxd + 0xc));
8680 rxd += (4 * sizeof(u32));
8681 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8682 i,
8683 readl(rxd + 0x0), readl(rxd + 0x4),
8684 readl(rxd + 0x8), readl(rxd + 0xc));
8685 }
8686
8687 for (i = 0; i < 6; i++) {
8688 unsigned long rxd;
8689
8690 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8691 + (i * sizeof(struct tg3_rx_buffer_desc));
8692 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8693 i,
8694 readl(rxd + 0x0), readl(rxd + 0x4),
8695 readl(rxd + 0x8), readl(rxd + 0xc));
8696 rxd += (4 * sizeof(u32));
8697 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8698 i,
8699 readl(rxd + 0x0), readl(rxd + 0x4),
8700 readl(rxd + 0x8), readl(rxd + 0xc));
8701 }
8702}
8703#endif
8704
8705static struct net_device_stats *tg3_get_stats(struct net_device *);
8706static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8707
8708static int tg3_close(struct net_device *dev)
8709{
4f125f42 8710 int i;
1da177e4
LT		 8711 struct tg3 *tp = netdev_priv(dev);
8712
fed97810 8713 tg3_napi_disable(tp);
28e53bdd 8714 cancel_work_sync(&tp->reset_task);
7faa006f 8715
fe5f5787 8716 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8717
8718 del_timer_sync(&tp->timer);
8719
24bb4fb6
MC		 8720 tg3_phy_stop(tp);
8721
f47c11ee 8722 tg3_full_lock(tp, 1);
1da177e4
LT		 8723#if 0
8724 tg3_dump_state(tp);
8725#endif
8726
8727 tg3_disable_ints(tp);
8728
944d980e 8729 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8730 tg3_free_rings(tp);
5cf64b8a 8731 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8732
f47c11ee 8733 tg3_full_unlock(tp);
1da177e4 8734
4f125f42
MC		 8735 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8736 struct tg3_napi *tnapi = &tp->napi[i];
8737 free_irq(tnapi->irq_vec, tnapi);
8738 }
07b0173c
MC		 8739
8740 tg3_ints_fini(tp);
1da177e4
LT		 8741
8742 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8743 sizeof(tp->net_stats_prev));
8744 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8745 sizeof(tp->estats_prev));
8746
8747 tg3_free_consistent(tp);
8748
bc1c7567
MC		 8749 tg3_set_power_state(tp, PCI_D3hot);
8750
8751 netif_carrier_off(tp->dev);
8752
1da177e4
LT		 8753 return 0;
8754}
8755
8756static inline unsigned long get_stat64(tg3_stat64_t *val)
8757{
8758 unsigned long ret;
8759
8760#if (BITS_PER_LONG == 32)
8761 ret = val->low;
8762#else
8763 ret = ((u64)val->high << 32) | ((u64)val->low);
8764#endif
8765 return ret;
8766}
8767
816f8b86
SB		 8768static inline u64 get_estat64(tg3_stat64_t *val)
8769{
8770 return ((u64)val->high << 32) | ((u64)val->low);
8771}
8772
1da177e4
LT		 8773static unsigned long calc_crc_errors(struct tg3 *tp)
8774{
8775 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8776
8777 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8778 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8779 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8780 u32 val;
8781
f47c11ee 8782 spin_lock_bh(&tp->lock);
569a5df8
MC		 8783 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8784 tg3_writephy(tp, MII_TG3_TEST1,
8785 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8786 tg3_readphy(tp, 0x14, &val);
8787 } else
8788 val = 0;
f47c11ee 8789 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8790
8791 tp->phy_crc_errors += val;
8792
8793 return tp->phy_crc_errors;
8794 }
8795
8796 return get_stat64(&hw_stats->rx_fcs_errors);
8797}
8798
8799#define ESTAT_ADD(member) \
8800 estats->member = old_estats->member + \
816f8b86 8801 get_estat64(&hw_stats->member)
1da177e4
LT		 8802
8803static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8804{
8805 struct tg3_ethtool_stats *estats = &tp->estats;
8806 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8807 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8808
8809 if (!hw_stats)
8810 return old_estats;
8811
8812 ESTAT_ADD(rx_octets);
8813 ESTAT_ADD(rx_fragments);
8814 ESTAT_ADD(rx_ucast_packets);
8815 ESTAT_ADD(rx_mcast_packets);
8816 ESTAT_ADD(rx_bcast_packets);
8817 ESTAT_ADD(rx_fcs_errors);
8818 ESTAT_ADD(rx_align_errors);
8819 ESTAT_ADD(rx_xon_pause_rcvd);
8820 ESTAT_ADD(rx_xoff_pause_rcvd);
8821 ESTAT_ADD(rx_mac_ctrl_rcvd);
8822 ESTAT_ADD(rx_xoff_entered);
8823 ESTAT_ADD(rx_frame_too_long_errors);
8824 ESTAT_ADD(rx_jabbers);
8825 ESTAT_ADD(rx_undersize_packets);
8826 ESTAT_ADD(rx_in_length_errors);
8827 ESTAT_ADD(rx_out_length_errors);
8828 ESTAT_ADD(rx_64_or_less_octet_packets);
8829 ESTAT_ADD(rx_65_to_127_octet_packets);
8830 ESTAT_ADD(rx_128_to_255_octet_packets);
8831 ESTAT_ADD(rx_256_to_511_octet_packets);
8832 ESTAT_ADD(rx_512_to_1023_octet_packets);
8833 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8834 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8835 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8836 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8837 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8838
8839 ESTAT_ADD(tx_octets);
8840 ESTAT_ADD(tx_collisions);
8841 ESTAT_ADD(tx_xon_sent);
8842 ESTAT_ADD(tx_xoff_sent);
8843 ESTAT_ADD(tx_flow_control);
8844 ESTAT_ADD(tx_mac_errors);
8845 ESTAT_ADD(tx_single_collisions);
8846 ESTAT_ADD(tx_mult_collisions);
8847 ESTAT_ADD(tx_deferred);
8848 ESTAT_ADD(tx_excessive_collisions);
8849 ESTAT_ADD(tx_late_collisions);
8850 ESTAT_ADD(tx_collide_2times);
8851 ESTAT_ADD(tx_collide_3times);
8852 ESTAT_ADD(tx_collide_4times);
8853 ESTAT_ADD(tx_collide_5times);
8854 ESTAT_ADD(tx_collide_6times);
8855 ESTAT_ADD(tx_collide_7times);
8856 ESTAT_ADD(tx_collide_8times);
8857 ESTAT_ADD(tx_collide_9times);
8858 ESTAT_ADD(tx_collide_10times);
8859 ESTAT_ADD(tx_collide_11times);
8860 ESTAT_ADD(tx_collide_12times);
8861 ESTAT_ADD(tx_collide_13times);
8862 ESTAT_ADD(tx_collide_14times);
8863 ESTAT_ADD(tx_collide_15times);
8864 ESTAT_ADD(tx_ucast_packets);
8865 ESTAT_ADD(tx_mcast_packets);
8866 ESTAT_ADD(tx_bcast_packets);
8867 ESTAT_ADD(tx_carrier_sense_errors);
8868 ESTAT_ADD(tx_discards);
8869 ESTAT_ADD(tx_errors);
8870
8871 ESTAT_ADD(dma_writeq_full);
8872 ESTAT_ADD(dma_write_prioq_full);
8873 ESTAT_ADD(rxbds_empty);
8874 ESTAT_ADD(rx_discards);
8875 ESTAT_ADD(rx_errors);
8876 ESTAT_ADD(rx_threshold_hit);
8877
8878 ESTAT_ADD(dma_readq_full);
8879 ESTAT_ADD(dma_read_prioq_full);
8880 ESTAT_ADD(tx_comp_queue_full);
8881
8882 ESTAT_ADD(ring_set_send_prod_index);
8883 ESTAT_ADD(ring_status_update);
8884 ESTAT_ADD(nic_irqs);
8885 ESTAT_ADD(nic_avoided_irqs);
8886 ESTAT_ADD(nic_tx_threshold_hit);
8887
8888 return estats;
8889}
8890
8891static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8892{
8893 struct tg3 *tp = netdev_priv(dev);
8894 struct net_device_stats *stats = &tp->net_stats;
8895 struct net_device_stats *old_stats = &tp->net_stats_prev;
8896 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8897
8898 if (!hw_stats)
8899 return old_stats;
8900
8901 stats->rx_packets = old_stats->rx_packets +
8902 get_stat64(&hw_stats->rx_ucast_packets) +
8903 get_stat64(&hw_stats->rx_mcast_packets) +
8904 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8905
1da177e4
LT		 8906 stats->tx_packets = old_stats->tx_packets +
8907 get_stat64(&hw_stats->tx_ucast_packets) +
8908 get_stat64(&hw_stats->tx_mcast_packets) +
8909 get_stat64(&hw_stats->tx_bcast_packets);
8910
8911 stats->rx_bytes = old_stats->rx_bytes +
8912 get_stat64(&hw_stats->rx_octets);
8913 stats->tx_bytes = old_stats->tx_bytes +
8914 get_stat64(&hw_stats->tx_octets);
8915
8916 stats->rx_errors = old_stats->rx_errors +
4f63b877 8917 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8918 stats->tx_errors = old_stats->tx_errors +
8919 get_stat64(&hw_stats->tx_errors) +
8920 get_stat64(&hw_stats->tx_mac_errors) +
8921 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8922 get_stat64(&hw_stats->tx_discards);
8923
8924 stats->multicast = old_stats->multicast +
8925 get_stat64(&hw_stats->rx_mcast_packets);
8926 stats->collisions = old_stats->collisions +
8927 get_stat64(&hw_stats->tx_collisions);
8928
8929 stats->rx_length_errors = old_stats->rx_length_errors +
8930 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8931 get_stat64(&hw_stats->rx_undersize_packets);
8932
8933 stats->rx_over_errors = old_stats->rx_over_errors +
8934 get_stat64(&hw_stats->rxbds_empty);
8935 stats->rx_frame_errors = old_stats->rx_frame_errors +
8936 get_stat64(&hw_stats->rx_align_errors);
8937 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8938 get_stat64(&hw_stats->tx_discards);
8939 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8940 get_stat64(&hw_stats->tx_carrier_sense_errors);
8941
8942 stats->rx_crc_errors = old_stats->rx_crc_errors +
8943 calc_crc_errors(tp);
8944
4f63b877
JL		 8945 stats->rx_missed_errors = old_stats->rx_missed_errors +
8946 get_stat64(&hw_stats->rx_discards);
8947
1da177e4
LT		 8948 return stats;
8949}
8950
8951static inline u32 calc_crc(unsigned char *buf, int len)
8952{
8953 u32 reg;
8954 u32 tmp;
8955 int j, k;
8956
8957 reg = 0xffffffff;
8958
8959 for (j = 0; j < len; j++) {
8960 reg ^= buf[j];
8961
8962 for (k = 0; k < 8; k++) {
8963 tmp = reg & 0x01;
8964
8965 reg >>= 1;
8966
8967 if (tmp) {
8968 reg ^= 0xedb88320;
8969 }
8970 }
8971 }
8972
8973 return ~reg;
8974}
8975
8976static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8977{
8978 /* accept or reject all multicast frames */
8979 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8980 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8981 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8982 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8983}
8984
8985static void __tg3_set_rx_mode(struct net_device *dev)
8986{
8987 struct tg3 *tp = netdev_priv(dev);
8988 u32 rx_mode;
8989
8990 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8991 RX_MODE_KEEP_VLAN_TAG);
8992
8993 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8994 * flag clear.
8995 */
8996#if TG3_VLAN_TAG_USED
8997 if (!tp->vlgrp &&
8998 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8999 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9000#else
9001 /* By definition, VLAN is disabled always in this
9002 * case.
9003 */
9004 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9005 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9006#endif
9007
9008 if (dev->flags & IFF_PROMISC) {
9009 /* Promiscuous mode. */
9010 rx_mode |= RX_MODE_PROMISC;
9011 } else if (dev->flags & IFF_ALLMULTI) {
9012 /* Accept all multicast. */
9013 tg3_set_multi (tp, 1);
9014 } else if (dev->mc_count < 1) {
9015 /* Reject all multicast. */
9016 tg3_set_multi (tp, 0);
9017 } else {
9018 /* Accept one or more multicast(s). */
9019 struct dev_mc_list *mclist;
9020 unsigned int i;
9021 u32 mc_filter[4] = { 0, };
9022 u32 regidx;
9023 u32 bit;
9024 u32 crc;
9025
9026 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9027 i++, mclist = mclist->next) {
9028
9029 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9030 bit = ~crc & 0x7f;
9031 regidx = (bit & 0x60) >> 5;
9032 bit &= 0x1f;
9033 mc_filter[regidx] |= (1 << bit);
9034 }
9035
9036 tw32(MAC_HASH_REG_0, mc_filter[0]);
9037 tw32(MAC_HASH_REG_1, mc_filter[1]);
9038 tw32(MAC_HASH_REG_2, mc_filter[2]);
9039 tw32(MAC_HASH_REG_3, mc_filter[3]);
9040 }
9041
9042 if (rx_mode != tp->rx_mode) {
9043 tp->rx_mode = rx_mode;
9044 tw32_f(MAC_RX_MODE, rx_mode);
9045 udelay(10);
9046 }
9047}
9048
9049static void tg3_set_rx_mode(struct net_device *dev)
9050{
9051 struct tg3 *tp = netdev_priv(dev);
9052
e75f7c90
MC		 9053 if (!netif_running(dev))
9054 return;
9055
f47c11ee 9056 tg3_full_lock(tp, 0);
1da177e4 9057 __tg3_set_rx_mode(dev);
f47c11ee 9058 tg3_full_unlock(tp);
1da177e4
LT		 9059}
9060
9061#define TG3_REGDUMP_LEN (32 * 1024)
9062
9063static int tg3_get_regs_len(struct net_device *dev)
9064{
9065 return TG3_REGDUMP_LEN;
9066}
9067
9068static void tg3_get_regs(struct net_device *dev,
9069 struct ethtool_regs *regs, void *_p)
9070{
9071 u32 *p = _p;
9072 struct tg3 *tp = netdev_priv(dev);
9073 u8 *orig_p = _p;
9074 int i;
9075
9076 regs->version = 0;
9077
9078 memset(p, 0, TG3_REGDUMP_LEN);
9079
bc1c7567
MC		 9080 if (tp->link_config.phy_is_low_power)
9081 return;
9082
f47c11ee 9083 tg3_full_lock(tp, 0);
1da177e4
LT		 9084
9085#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9086#define GET_REG32_LOOP(base,len) \
9087do { p = (u32 *)(orig_p + (base)); \
9088 for (i = 0; i < len; i += 4) \
9089 __GET_REG32((base) + i); \
9090} while (0)
9091#define GET_REG32_1(reg) \
9092do { p = (u32 *)(orig_p + (reg)); \
9093 __GET_REG32((reg)); \
9094} while (0)
9095
9096 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9097 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9098 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9099 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9100 GET_REG32_1(SNDDATAC_MODE);
9101 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9102 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9103 GET_REG32_1(SNDBDC_MODE);
9104 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9105 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9106 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9107 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9108 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9109 GET_REG32_1(RCVDCC_MODE);
9110 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9111 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9112 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9113 GET_REG32_1(MBFREE_MODE);
9114 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9115 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9116 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9117 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9118 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9119 GET_REG32_1(RX_CPU_MODE);
9120 GET_REG32_1(RX_CPU_STATE);
9121 GET_REG32_1(RX_CPU_PGMCTR);
9122 GET_REG32_1(RX_CPU_HWBKPT);
9123 GET_REG32_1(TX_CPU_MODE);
9124 GET_REG32_1(TX_CPU_STATE);
9125 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9126 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9127 GET_REG32_LOOP(FTQ_RESET, 0x120);
9128 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9129 GET_REG32_1(DMAC_MODE);
9130 GET_REG32_LOOP(GRC_MODE, 0x4c);
9131 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9132 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9133
9134#undef __GET_REG32
9135#undef GET_REG32_LOOP
9136#undef GET_REG32_1
9137
f47c11ee 9138 tg3_full_unlock(tp);
1da177e4
LT		 9139}
9140
9141static int tg3_get_eeprom_len(struct net_device *dev)
9142{
9143 struct tg3 *tp = netdev_priv(dev);
9144
9145 return tp->nvram_size;
9146}
9147
1da177e4
LT		 9148static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9149{
9150 struct tg3 *tp = netdev_priv(dev);
9151 int ret;
9152 u8 *pd;
b9fc7dc5 9153 u32 i, offset, len, b_offset, b_count;
a9dc529d 9154 __be32 val;
1da177e4 9155
df259d8c
MC		 9156 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9157 return -EINVAL;
9158
bc1c7567
MC		 9159 if (tp->link_config.phy_is_low_power)
9160 return -EAGAIN;
9161
1da177e4
LT		 9162 offset = eeprom->offset;
9163 len = eeprom->len;
9164 eeprom->len = 0;
9165
9166 eeprom->magic = TG3_EEPROM_MAGIC;
9167
9168 if (offset & 3) {
9169 /* adjustments to start on required 4 byte boundary */
9170 b_offset = offset & 3;
9171 b_count = 4 - b_offset;
9172 if (b_count > len) {
9173 /* i.e. offset=1 len=2 */
9174 b_count = len;
9175 }
a9dc529d 9176 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9177 if (ret)
9178 return ret;
1da177e4
LT		 9179 memcpy(data, ((char*)&val) + b_offset, b_count);
9180 len -= b_count;
9181 offset += b_count;
9182 eeprom->len += b_count;
9183 }
9184
9185 /* read bytes upto the last 4 byte boundary */
9186 pd = &data[eeprom->len];
9187 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9188 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9189 if (ret) {
9190 eeprom->len += i;
9191 return ret;
9192 }
1da177e4
LT		 9193 memcpy(pd + i, &val, 4);
9194 }
9195 eeprom->len += i;
9196
9197 if (len & 3) {
9198 /* read last bytes not ending on 4 byte boundary */
9199 pd = &data[eeprom->len];
9200 b_count = len & 3;
9201 b_offset = offset + len - b_count;
a9dc529d 9202 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9203 if (ret)
9204 return ret;
b9fc7dc5 9205 memcpy(pd, &val, b_count);
1da177e4
LT		 9206 eeprom->len += b_count;
9207 }
9208 return 0;
9209}
9210
6aa20a22 9211static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9212
9213static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9214{
9215 struct tg3 *tp = netdev_priv(dev);
9216 int ret;
b9fc7dc5 9217 u32 offset, len, b_offset, odd_len;
1da177e4 9218 u8 *buf;
a9dc529d 9219 __be32 start, end;
1da177e4 9220
bc1c7567
MC		 9221 if (tp->link_config.phy_is_low_power)
9222 return -EAGAIN;
9223
df259d8c
MC		 9224 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9225 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9226 return -EINVAL;
9227
9228 offset = eeprom->offset;
9229 len = eeprom->len;
9230
9231 if ((b_offset = (offset & 3))) {
9232 /* adjustments to start on required 4 byte boundary */
a9dc529d 9233 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9234 if (ret)
9235 return ret;
1da177e4
LT		 9236 len += b_offset;
9237 offset &= ~3;
1c8594b4
MC		 9238 if (len < 4)
9239 len = 4;
1da177e4
LT		 9240 }
9241
9242 odd_len = 0;
1c8594b4 9243 if (len & 3) {
1da177e4
LT		 9244 /* adjustments to end on required 4 byte boundary */
9245 odd_len = 1;
9246 len = (len + 3) & ~3;
a9dc529d 9247 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9248 if (ret)
9249 return ret;
1da177e4
LT		 9250 }
9251
9252 buf = data;
9253 if (b_offset || odd_len) {
9254 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9255 if (!buf)
1da177e4
LT		 9256 return -ENOMEM;
9257 if (b_offset)
9258 memcpy(buf, &start, 4);
9259 if (odd_len)
9260 memcpy(buf+len-4, &end, 4);
9261 memcpy(buf + b_offset, data, eeprom->len);
9262 }
9263
9264 ret = tg3_nvram_write_block(tp, offset, len, buf);
9265
9266 if (buf != data)
9267 kfree(buf);
9268
9269 return ret;
9270}
9271
9272static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9273{
b02fd9e3
MC		 9274 struct tg3 *tp = netdev_priv(dev);
9275
9276 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9277 struct phy_device *phydev;
b02fd9e3
MC		 9278 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9279 return -EAGAIN;
3f0e3ad7
MC		 9280 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9281 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9282 }
6aa20a22 9283
1da177e4
LT		 9284 cmd->supported = (SUPPORTED_Autoneg);
9285
9286 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9287 cmd->supported |= (SUPPORTED_1000baseT_Half |
9288 SUPPORTED_1000baseT_Full);
9289
ef348144 9290 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9291 cmd->supported |= (SUPPORTED_100baseT_Half |
9292 SUPPORTED_100baseT_Full |
9293 SUPPORTED_10baseT_Half |
9294 SUPPORTED_10baseT_Full |
3bebab59 9295 SUPPORTED_TP);
ef348144
KK		 9296 cmd->port = PORT_TP;
9297 } else {
1da177e4 9298 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9299 cmd->port = PORT_FIBRE;
9300 }
6aa20a22 9301
1da177e4
LT		 9302 cmd->advertising = tp->link_config.advertising;
9303 if (netif_running(dev)) {
9304 cmd->speed = tp->link_config.active_speed;
9305 cmd->duplex = tp->link_config.active_duplex;
9306 }
882e9793 9307 cmd->phy_address = tp->phy_addr;
7e5856bd 9308 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9309 cmd->autoneg = tp->link_config.autoneg;
9310 cmd->maxtxpkt = 0;
9311 cmd->maxrxpkt = 0;
9312 return 0;
9313}
6aa20a22 9314
1da177e4
LT		 9315static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9316{
9317 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9318
b02fd9e3 9319 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9320 struct phy_device *phydev;
b02fd9e3
MC		 9321 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9322 return -EAGAIN;
3f0e3ad7
MC		 9323 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9324 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9325 }
9326
7e5856bd
MC		 9327 if (cmd->autoneg != AUTONEG_ENABLE &&
9328 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9329 return -EINVAL;
7e5856bd
MC		 9330
9331 if (cmd->autoneg == AUTONEG_DISABLE &&
9332 cmd->duplex != DUPLEX_FULL &&
9333 cmd->duplex != DUPLEX_HALF)
37ff238d 9334 return -EINVAL;
1da177e4 9335
7e5856bd
MC		 9336 if (cmd->autoneg == AUTONEG_ENABLE) {
9337 u32 mask = ADVERTISED_Autoneg |
9338 ADVERTISED_Pause |
9339 ADVERTISED_Asym_Pause;
9340
9341 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9342 mask |= ADVERTISED_1000baseT_Half |
9343 ADVERTISED_1000baseT_Full;
9344
9345 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9346 mask |= ADVERTISED_100baseT_Half |
9347 ADVERTISED_100baseT_Full |
9348 ADVERTISED_10baseT_Half |
9349 ADVERTISED_10baseT_Full |
9350 ADVERTISED_TP;
9351 else
9352 mask |= ADVERTISED_FIBRE;
9353
9354 if (cmd->advertising & ~mask)
9355 return -EINVAL;
9356
9357 mask &= (ADVERTISED_1000baseT_Half |
9358 ADVERTISED_1000baseT_Full |
9359 ADVERTISED_100baseT_Half |
9360 ADVERTISED_100baseT_Full |
9361 ADVERTISED_10baseT_Half |
9362 ADVERTISED_10baseT_Full);
9363
9364 cmd->advertising &= mask;
9365 } else {
9366 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9367 if (cmd->speed != SPEED_1000)
9368 return -EINVAL;
9369
9370 if (cmd->duplex != DUPLEX_FULL)
9371 return -EINVAL;
9372 } else {
9373 if (cmd->speed != SPEED_100 &&
9374 cmd->speed != SPEED_10)
9375 return -EINVAL;
9376 }
9377 }
9378
f47c11ee 9379 tg3_full_lock(tp, 0);
1da177e4
LT		 9380
9381 tp->link_config.autoneg = cmd->autoneg;
9382 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9383 tp->link_config.advertising = (cmd->advertising |
9384 ADVERTISED_Autoneg);
1da177e4
LT		 9385 tp->link_config.speed = SPEED_INVALID;
9386 tp->link_config.duplex = DUPLEX_INVALID;
9387 } else {
9388 tp->link_config.advertising = 0;
9389 tp->link_config.speed = cmd->speed;
9390 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9391 }
6aa20a22 9392
24fcad6b
MC		 9393 tp->link_config.orig_speed = tp->link_config.speed;
9394 tp->link_config.orig_duplex = tp->link_config.duplex;
9395 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9396
1da177e4
LT		 9397 if (netif_running(dev))
9398 tg3_setup_phy(tp, 1);
9399
f47c11ee 9400 tg3_full_unlock(tp);
6aa20a22 9401
1da177e4
LT		 9402 return 0;
9403}
6aa20a22 9404
1da177e4
LT		 9405static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9406{
9407 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9408
1da177e4
LT		 9409 strcpy(info->driver, DRV_MODULE_NAME);
9410 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9411 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9412 strcpy(info->bus_info, pci_name(tp->pdev));
9413}
6aa20a22 9414
1da177e4
LT		 9415static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9416{
9417 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9418
12dac075
RW		 9419 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9420 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9421 wol->supported = WAKE_MAGIC;
9422 else
9423 wol->supported = 0;
1da177e4 9424 wol->wolopts = 0;
05ac4cb7
MC		 9425 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9426 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9427 wol->wolopts = WAKE_MAGIC;
9428 memset(&wol->sopass, 0, sizeof(wol->sopass));
9429}
6aa20a22 9430
1da177e4
LT		 9431static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9432{
9433 struct tg3 *tp = netdev_priv(dev);
12dac075 9434 struct device *dp = &tp->pdev->dev;
6aa20a22 9435
1da177e4
LT		 9436 if (wol->wolopts & ~WAKE_MAGIC)
9437 return -EINVAL;
9438 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9439 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9440 return -EINVAL;
6aa20a22 9441
f47c11ee 9442 spin_lock_bh(&tp->lock);
12dac075 9443 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9444 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9445 device_set_wakeup_enable(dp, true);
9446 } else {
1da177e4 9447 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9448 device_set_wakeup_enable(dp, false);
9449 }
f47c11ee 9450 spin_unlock_bh(&tp->lock);
6aa20a22 9451
1da177e4
LT		 9452 return 0;
9453}
6aa20a22 9454
1da177e4
LT		 9455static u32 tg3_get_msglevel(struct net_device *dev)
9456{
9457 struct tg3 *tp = netdev_priv(dev);
9458 return tp->msg_enable;
9459}
6aa20a22 9460
1da177e4
LT		 9461static void tg3_set_msglevel(struct net_device *dev, u32 value)
9462{
9463 struct tg3 *tp = netdev_priv(dev);
9464 tp->msg_enable = value;
9465}
6aa20a22 9466
1da177e4
LT		 9467static int tg3_set_tso(struct net_device *dev, u32 value)
9468{
9469 struct tg3 *tp = netdev_priv(dev);
9470
9471 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9472 if (value)
9473 return -EINVAL;
9474 return 0;
9475 }
027455ad
MC		 9476 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9477 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9478 if (value) {
b0026624 9479 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9481 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9482 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9483 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 9484 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6
MC		 9486 dev->features |= NETIF_F_TSO_ECN;
9487 } else
9488 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9489 }
1da177e4
LT		 9490 return ethtool_op_set_tso(dev, value);
9491}
6aa20a22 9492
1da177e4
LT		 9493static int tg3_nway_reset(struct net_device *dev)
9494{
9495 struct tg3 *tp = netdev_priv(dev);
1da177e4 9496 int r;
6aa20a22 9497
1da177e4
LT		 9498 if (!netif_running(dev))
9499 return -EAGAIN;
9500
c94e3941
MC		 9501 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9502 return -EINVAL;
9503
b02fd9e3
MC		 9504 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9505 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9506 return -EAGAIN;
3f0e3ad7 9507 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9508 } else {
9509 u32 bmcr;
9510
9511 spin_lock_bh(&tp->lock);
9512 r = -EINVAL;
9513 tg3_readphy(tp, MII_BMCR, &bmcr);
9514 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9515 ((bmcr & BMCR_ANENABLE) ||
9516 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9517 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9518 BMCR_ANENABLE);
9519 r = 0;
9520 }
9521 spin_unlock_bh(&tp->lock);
1da177e4 9522 }
6aa20a22 9523
1da177e4
LT		 9524 return r;
9525}
6aa20a22 9526
1da177e4
LT		 9527static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9528{
9529 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9530
1da177e4
LT		 9531 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9532 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9533 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9534 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9535 else
9536 ering->rx_jumbo_max_pending = 0;
9537
9538 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9539
9540 ering->rx_pending = tp->rx_pending;
9541 ering->rx_mini_pending = 0;
4f81c32b
MC		 9542 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9543 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9544 else
9545 ering->rx_jumbo_pending = 0;
9546
f3f3f27e 9547 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9548}
6aa20a22 9549
1da177e4
LT		 9550static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9551{
9552 struct tg3 *tp = netdev_priv(dev);
646c9edd 9553 int i, irq_sync = 0, err = 0;
6aa20a22 9554
1da177e4
LT		 9555 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9556 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9557 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9558 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9559 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9560 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9561 return -EINVAL;
6aa20a22 9562
bbe832c0 9563 if (netif_running(dev)) {
b02fd9e3 9564 tg3_phy_stop(tp);
1da177e4 9565 tg3_netif_stop(tp);
bbe832c0
MC		 9566 irq_sync = 1;
9567 }
1da177e4 9568
bbe832c0 9569 tg3_full_lock(tp, irq_sync);
6aa20a22 9570
1da177e4
LT		 9571 tp->rx_pending = ering->rx_pending;
9572
9573 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9574 tp->rx_pending > 63)
9575 tp->rx_pending = 63;
9576 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9577
9578 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9579 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9580
9581 if (netif_running(dev)) {
944d980e 9582 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9583 err = tg3_restart_hw(tp, 1);
9584 if (!err)
9585 tg3_netif_start(tp);
1da177e4
LT		 9586 }
9587
f47c11ee 9588 tg3_full_unlock(tp);
6aa20a22 9589
b02fd9e3
MC		 9590 if (irq_sync && !err)
9591 tg3_phy_start(tp);
9592
b9ec6c1b 9593 return err;
1da177e4 9594}
6aa20a22 9595
1da177e4
LT		 9596static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9597{
9598 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9599
1da177e4 9600 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9601
e18ce346 9602 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9603 epause->rx_pause = 1;
9604 else
9605 epause->rx_pause = 0;
9606
e18ce346 9607 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9608 epause->tx_pause = 1;
9609 else
9610 epause->tx_pause = 0;
1da177e4 9611}
6aa20a22 9612
1da177e4
LT		 9613static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9614{
9615 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9616 int err = 0;
6aa20a22 9617
b02fd9e3
MC		 9618 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9619 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9620 return -EAGAIN;
1da177e4 9621
b02fd9e3
MC		 9622 if (epause->autoneg) {
9623 u32 newadv;
9624 struct phy_device *phydev;
f47c11ee 9625
3f0e3ad7 9626 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9627
b02fd9e3
MC		 9628 if (epause->rx_pause) {
9629 if (epause->tx_pause)
9630 newadv = ADVERTISED_Pause;
9631 else
9632 newadv = ADVERTISED_Pause |
9633 ADVERTISED_Asym_Pause;
9634 } else if (epause->tx_pause) {
9635 newadv = ADVERTISED_Asym_Pause;
9636 } else
9637 newadv = 0;
9638
9639 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9640 u32 oldadv = phydev->advertising &
9641 (ADVERTISED_Pause |
9642 ADVERTISED_Asym_Pause);
9643 if (oldadv != newadv) {
9644 phydev->advertising &=
9645 ~(ADVERTISED_Pause |
9646 ADVERTISED_Asym_Pause);
9647 phydev->advertising |= newadv;
9648 err = phy_start_aneg(phydev);
9649 }
9650 } else {
9651 tp->link_config.advertising &=
9652 ~(ADVERTISED_Pause |
9653 ADVERTISED_Asym_Pause);
9654 tp->link_config.advertising |= newadv;
9655 }
9656 } else {
9657 if (epause->rx_pause)
e18ce346 9658 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9659 else
e18ce346 9660 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9661
b02fd9e3 9662 if (epause->tx_pause)
e18ce346 9663 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9664 else
e18ce346 9665 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9666
9667 if (netif_running(dev))
9668 tg3_setup_flow_control(tp, 0, 0);
9669 }
9670 } else {
9671 int irq_sync = 0;
9672
9673 if (netif_running(dev)) {
9674 tg3_netif_stop(tp);
9675 irq_sync = 1;
9676 }
9677
9678 tg3_full_lock(tp, irq_sync);
9679
9680 if (epause->autoneg)
9681 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9682 else
9683 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9684 if (epause->rx_pause)
e18ce346 9685 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9686 else
e18ce346 9687 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9688 if (epause->tx_pause)
e18ce346 9689 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9690 else
e18ce346 9691 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9692
9693 if (netif_running(dev)) {
9694 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9695 err = tg3_restart_hw(tp, 1);
9696 if (!err)
9697 tg3_netif_start(tp);
9698 }
9699
9700 tg3_full_unlock(tp);
9701 }
6aa20a22 9702
b9ec6c1b 9703 return err;
1da177e4 9704}
6aa20a22 9705
1da177e4
LT		 9706static u32 tg3_get_rx_csum(struct net_device *dev)
9707{
9708 struct tg3 *tp = netdev_priv(dev);
9709 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9710}
6aa20a22 9711
1da177e4
LT		 9712static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9713{
9714 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9715
1da177e4
LT		 9716 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9717 if (data != 0)
9718 return -EINVAL;
9719 return 0;
9720 }
6aa20a22 9721
f47c11ee 9722 spin_lock_bh(&tp->lock);
1da177e4
LT		 9723 if (data)
9724 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9725 else
9726 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9727 spin_unlock_bh(&tp->lock);
6aa20a22 9728
1da177e4
LT		 9729 return 0;
9730}
6aa20a22 9731
1da177e4
LT		 9732static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9733{
9734 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9735
1da177e4
LT		 9736 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9737 if (data != 0)
9738 return -EINVAL;
9739 return 0;
9740 }
6aa20a22 9741
321d32a0 9742 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9743 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9744 else
9c27dbdf 9745 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9746
9747 return 0;
9748}
9749
b9f2c044 9750static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9751{
b9f2c044
JG		 9752 switch (sset) {
9753 case ETH_SS_TEST:
9754 return TG3_NUM_TEST;
9755 case ETH_SS_STATS:
9756 return TG3_NUM_STATS;
9757 default:
9758 return -EOPNOTSUPP;
9759 }
4cafd3f5
MC		 9760}
9761
1da177e4
LT		 9762static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9763{
9764 switch (stringset) {
9765 case ETH_SS_STATS:
9766 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9767 break;
4cafd3f5
MC		 9768 case ETH_SS_TEST:
9769 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9770 break;
1da177e4
LT		 9771 default:
9772 WARN_ON(1); /* we need a WARN() */
9773 break;
9774 }
9775}
9776
4009a93d
MC		 9777static int tg3_phys_id(struct net_device *dev, u32 data)
9778{
9779 struct tg3 *tp = netdev_priv(dev);
9780 int i;
9781
9782 if (!netif_running(tp->dev))
9783 return -EAGAIN;
9784
9785 if (data == 0)
759afc31 9786 data = UINT_MAX / 2;
4009a93d
MC		 9787
9788 for (i = 0; i < (data * 2); i++) {
9789 if ((i % 2) == 0)
9790 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9791 LED_CTRL_1000MBPS_ON |
9792 LED_CTRL_100MBPS_ON |
9793 LED_CTRL_10MBPS_ON |
9794 LED_CTRL_TRAFFIC_OVERRIDE |
9795 LED_CTRL_TRAFFIC_BLINK |
9796 LED_CTRL_TRAFFIC_LED);
6aa20a22 9797
4009a93d
MC		 9798 else
9799 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9800 LED_CTRL_TRAFFIC_OVERRIDE);
9801
9802 if (msleep_interruptible(500))
9803 break;
9804 }
9805 tw32(MAC_LED_CTRL, tp->led_ctrl);
9806 return 0;
9807}
9808
1da177e4
LT		 9809static void tg3_get_ethtool_stats (struct net_device *dev,
9810 struct ethtool_stats *estats, u64 *tmp_stats)
9811{
9812 struct tg3 *tp = netdev_priv(dev);
9813 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9814}
9815
566f86ad 9816#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9817#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9818#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9819#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9820#define NVRAM_SELFBOOT_HW_SIZE 0x20
9821#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9822
9823static int tg3_test_nvram(struct tg3 *tp)
9824{
b9fc7dc5 9825 u32 csum, magic;
a9dc529d 9826 __be32 *buf;
ab0049b4 9827 int i, j, k, err = 0, size;
566f86ad 9828
df259d8c
MC		 9829 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9830 return 0;
9831
e4f34110 9832 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9833 return -EIO;
9834
1b27777a
MC		 9835 if (magic == TG3_EEPROM_MAGIC)
9836 size = NVRAM_TEST_SIZE;
b16250e3 9837 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9838 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9839 TG3_EEPROM_SB_FORMAT_1) {
9840 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9841 case TG3_EEPROM_SB_REVISION_0:
9842 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9843 break;
9844 case TG3_EEPROM_SB_REVISION_2:
9845 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9846 break;
9847 case TG3_EEPROM_SB_REVISION_3:
9848 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9849 break;
9850 default:
9851 return 0;
9852 }
9853 } else
1b27777a 9854 return 0;
b16250e3
MC		 9855 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9856 size = NVRAM_SELFBOOT_HW_SIZE;
9857 else
1b27777a
MC		 9858 return -EIO;
9859
9860 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9861 if (buf == NULL)
9862 return -ENOMEM;
9863
1b27777a
MC		 9864 err = -EIO;
9865 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9866 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9867 if (err)
566f86ad 9868 break;
566f86ad 9869 }
1b27777a 9870 if (i < size)
566f86ad
MC		 9871 goto out;
9872
1b27777a 9873 /* Selfboot format */
a9dc529d 9874 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9875 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9876 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9877 u8 *buf8 = (u8 *) buf, csum8 = 0;
9878
b9fc7dc5 9879 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9880 TG3_EEPROM_SB_REVISION_2) {
9881 /* For rev 2, the csum doesn't include the MBA. */
9882 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9883 csum8 += buf8[i];
9884 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9885 csum8 += buf8[i];
9886 } else {
9887 for (i = 0; i < size; i++)
9888 csum8 += buf8[i];
9889 }
1b27777a 9890
ad96b485
AB		 9891 if (csum8 == 0) {
9892 err = 0;
9893 goto out;
9894 }
9895
9896 err = -EIO;
9897 goto out;
1b27777a 9898 }
566f86ad 9899
b9fc7dc5 9900 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9901 TG3_EEPROM_MAGIC_HW) {
9902 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9903 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9904 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9905
9906 /* Separate the parity bits and the data bytes. */
9907 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9908 if ((i == 0) || (i == 8)) {
9909 int l;
9910 u8 msk;
9911
9912 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9913 parity[k++] = buf8[i] & msk;
9914 i++;
9915 }
9916 else if (i == 16) {
9917 int l;
9918 u8 msk;
9919
9920 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9921 parity[k++] = buf8[i] & msk;
9922 i++;
9923
9924 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9925 parity[k++] = buf8[i] & msk;
9926 i++;
9927 }
9928 data[j++] = buf8[i];
9929 }
9930
9931 err = -EIO;
9932 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9933 u8 hw8 = hweight8(data[i]);
9934
9935 if ((hw8 & 0x1) && parity[i])
9936 goto out;
9937 else if (!(hw8 & 0x1) && !parity[i])
9938 goto out;
9939 }
9940 err = 0;
9941 goto out;
9942 }
9943
566f86ad
MC		 9944 /* Bootstrap checksum at offset 0x10 */
9945 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9946 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9947 goto out;
9948
9949 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9950 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9951 if (csum != be32_to_cpu(buf[0xfc/4]))
9952 goto out;
566f86ad
MC		 9953
9954 err = 0;
9955
9956out:
9957 kfree(buf);
9958 return err;
9959}
9960
ca43007a
MC		 9961#define TG3_SERDES_TIMEOUT_SEC 2
9962#define TG3_COPPER_TIMEOUT_SEC 6
9963
9964static int tg3_test_link(struct tg3 *tp)
9965{
9966 int i, max;
9967
9968 if (!netif_running(tp->dev))
9969 return -ENODEV;
9970
4c987487 9971 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9972 max = TG3_SERDES_TIMEOUT_SEC;
9973 else
9974 max = TG3_COPPER_TIMEOUT_SEC;
9975
9976 for (i = 0; i < max; i++) {
9977 if (netif_carrier_ok(tp->dev))
9978 return 0;
9979
9980 if (msleep_interruptible(1000))
9981 break;
9982 }
9983
9984 return -EIO;
9985}
9986
a71116d1 9987/* Only test the commonly used registers */
30ca3e37 9988static int tg3_test_registers(struct tg3 *tp)
a71116d1 9989{
b16250e3 9990 int i, is_5705, is_5750;
a71116d1
MC		 9991 u32 offset, read_mask, write_mask, val, save_val, read_val;
9992 static struct {
9993 u16 offset;
9994 u16 flags;
9995#define TG3_FL_5705 0x1
9996#define TG3_FL_NOT_5705 0x2
9997#define TG3_FL_NOT_5788 0x4
b16250e3 9998#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9999 u32 read_mask;
10000 u32 write_mask;
10001 } reg_tbl[] = {
10002 /* MAC Control Registers */
10003 { MAC_MODE, TG3_FL_NOT_5705,
10004 0x00000000, 0x00ef6f8c },
10005 { MAC_MODE, TG3_FL_5705,
10006 0x00000000, 0x01ef6b8c },
10007 { MAC_STATUS, TG3_FL_NOT_5705,
10008 0x03800107, 0x00000000 },
10009 { MAC_STATUS, TG3_FL_5705,
10010 0x03800100, 0x00000000 },
10011 { MAC_ADDR_0_HIGH, 0x0000,
10012 0x00000000, 0x0000ffff },
10013 { MAC_ADDR_0_LOW, 0x0000,
10014 0x00000000, 0xffffffff },
10015 { MAC_RX_MTU_SIZE, 0x0000,
10016 0x00000000, 0x0000ffff },
10017 { MAC_TX_MODE, 0x0000,
10018 0x00000000, 0x00000070 },
10019 { MAC_TX_LENGTHS, 0x0000,
10020 0x00000000, 0x00003fff },
10021 { MAC_RX_MODE, TG3_FL_NOT_5705,
10022 0x00000000, 0x000007fc },
10023 { MAC_RX_MODE, TG3_FL_5705,
10024 0x00000000, 0x000007dc },
10025 { MAC_HASH_REG_0, 0x0000,
10026 0x00000000, 0xffffffff },
10027 { MAC_HASH_REG_1, 0x0000,
10028 0x00000000, 0xffffffff },
10029 { MAC_HASH_REG_2, 0x0000,
10030 0x00000000, 0xffffffff },
10031 { MAC_HASH_REG_3, 0x0000,
10032 0x00000000, 0xffffffff },
10033
10034 /* Receive Data and Receive BD Initiator Control Registers. */
10035 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10036 0x00000000, 0xffffffff },
10037 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10038 0x00000000, 0xffffffff },
10039 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10040 0x00000000, 0x00000003 },
10041 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10042 0x00000000, 0xffffffff },
10043 { RCVDBDI_STD_BD+0, 0x0000,
10044 0x00000000, 0xffffffff },
10045 { RCVDBDI_STD_BD+4, 0x0000,
10046 0x00000000, 0xffffffff },
10047 { RCVDBDI_STD_BD+8, 0x0000,
10048 0x00000000, 0xffff0002 },
10049 { RCVDBDI_STD_BD+0xc, 0x0000,
10050 0x00000000, 0xffffffff },
6aa20a22 10051
a71116d1
MC		 10052 /* Receive BD Initiator Control Registers. */
10053 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10054 0x00000000, 0xffffffff },
10055 { RCVBDI_STD_THRESH, TG3_FL_5705,
10056 0x00000000, 0x000003ff },
10057 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10058 0x00000000, 0xffffffff },
6aa20a22 10059
a71116d1
MC		 10060 /* Host Coalescing Control Registers. */
10061 { HOSTCC_MODE, TG3_FL_NOT_5705,
10062 0x00000000, 0x00000004 },
10063 { HOSTCC_MODE, TG3_FL_5705,
10064 0x00000000, 0x000000f6 },
10065 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10066 0x00000000, 0xffffffff },
10067 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10068 0x00000000, 0x000003ff },
10069 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10070 0x00000000, 0xffffffff },
10071 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10072 0x00000000, 0x000003ff },
10073 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10074 0x00000000, 0xffffffff },
10075 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10076 0x00000000, 0x000000ff },
10077 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10078 0x00000000, 0xffffffff },
10079 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10080 0x00000000, 0x000000ff },
10081 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10082 0x00000000, 0xffffffff },
10083 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10084 0x00000000, 0xffffffff },
10085 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10086 0x00000000, 0xffffffff },
10087 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10088 0x00000000, 0x000000ff },
10089 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10090 0x00000000, 0xffffffff },
10091 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10092 0x00000000, 0x000000ff },
10093 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10094 0x00000000, 0xffffffff },
10095 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10096 0x00000000, 0xffffffff },
10097 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10098 0x00000000, 0xffffffff },
10099 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10100 0x00000000, 0xffffffff },
10101 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10102 0x00000000, 0xffffffff },
10103 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10104 0xffffffff, 0x00000000 },
10105 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10106 0xffffffff, 0x00000000 },
10107
10108 /* Buffer Manager Control Registers. */
b16250e3 10109 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10110 0x00000000, 0x007fff80 },
b16250e3 10111 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10112 0x00000000, 0x007fffff },
10113 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10114 0x00000000, 0x0000003f },
10115 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10116 0x00000000, 0x000001ff },
10117 { BUFMGR_MB_HIGH_WATER, 0x0000,
10118 0x00000000, 0x000001ff },
10119 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10120 0xffffffff, 0x00000000 },
10121 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10122 0xffffffff, 0x00000000 },
6aa20a22 10123
a71116d1
MC		 10124 /* Mailbox Registers */
10125 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10126 0x00000000, 0x000001ff },
10127 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10128 0x00000000, 0x000001ff },
10129 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10130 0x00000000, 0x000007ff },
10131 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10132 0x00000000, 0x000001ff },
10133
10134 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10135 };
10136
b16250e3
MC		 10137 is_5705 = is_5750 = 0;
10138 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10139 is_5705 = 1;
b16250e3
MC		 10140 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10141 is_5750 = 1;
10142 }
a71116d1
MC		 10143
10144 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10145 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10146 continue;
10147
10148 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10149 continue;
10150
10151 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10152 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10153 continue;
10154
b16250e3
MC		 10155 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10156 continue;
10157
a71116d1
MC		 10158 offset = (u32) reg_tbl[i].offset;
10159 read_mask = reg_tbl[i].read_mask;
10160 write_mask = reg_tbl[i].write_mask;
10161
10162 /* Save the original register content */
10163 save_val = tr32(offset);
10164
10165 /* Determine the read-only value. */
10166 read_val = save_val & read_mask;
10167
10168 /* Write zero to the register, then make sure the read-only bits
10169 * are not changed and the read/write bits are all zeros.
10170 */
10171 tw32(offset, 0);
10172
10173 val = tr32(offset);
10174
10175 /* Test the read-only and read/write bits. */
10176 if (((val & read_mask) != read_val) || (val & write_mask))
10177 goto out;
10178
10179 /* Write ones to all the bits defined by RdMask and WrMask, then
10180 * make sure the read-only bits are not changed and the
10181 * read/write bits are all ones.
10182 */
10183 tw32(offset, read_mask | write_mask);
10184
10185 val = tr32(offset);
10186
10187 /* Test the read-only bits. */
10188 if ((val & read_mask) != read_val)
10189 goto out;
10190
10191 /* Test the read/write bits. */
10192 if ((val & write_mask) != write_mask)
10193 goto out;
10194
10195 tw32(offset, save_val);
10196 }
10197
10198 return 0;
10199
10200out:
9f88f29f
MC		 10201 if (netif_msg_hw(tp))
10202 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10203 offset);
a71116d1
MC		 10204 tw32(offset, save_val);
10205 return -EIO;
10206}
10207
7942e1db
MC		 10208static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10209{
f71e1309 10210 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10211 int i;
10212 u32 j;
10213
e9edda69 10214 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10215 for (j = 0; j < len; j += 4) {
10216 u32 val;
10217
10218 tg3_write_mem(tp, offset + j, test_pattern[i]);
10219 tg3_read_mem(tp, offset + j, &val);
10220 if (val != test_pattern[i])
10221 return -EIO;
10222 }
10223 }
10224 return 0;
10225}
10226
10227static int tg3_test_memory(struct tg3 *tp)
10228{
10229 static struct mem_entry {
10230 u32 offset;
10231 u32 len;
10232 } mem_tbl_570x[] = {
38690194 10233 { 0x00000000, 0x00b50},
7942e1db
MC		 10234 { 0x00002000, 0x1c000},
10235 { 0xffffffff, 0x00000}
10236 }, mem_tbl_5705[] = {
10237 { 0x00000100, 0x0000c},
10238 { 0x00000200, 0x00008},
7942e1db
MC		 10239 { 0x00004000, 0x00800},
10240 { 0x00006000, 0x01000},
10241 { 0x00008000, 0x02000},
10242 { 0x00010000, 0x0e000},
10243 { 0xffffffff, 0x00000}
79f4d13a
MC		 10244 }, mem_tbl_5755[] = {
10245 { 0x00000200, 0x00008},
10246 { 0x00004000, 0x00800},
10247 { 0x00006000, 0x00800},
10248 { 0x00008000, 0x02000},
10249 { 0x00010000, 0x0c000},
10250 { 0xffffffff, 0x00000}
b16250e3
MC		 10251 }, mem_tbl_5906[] = {
10252 { 0x00000200, 0x00008},
10253 { 0x00004000, 0x00400},
10254 { 0x00006000, 0x00400},
10255 { 0x00008000, 0x01000},
10256 { 0x00010000, 0x01000},
10257 { 0xffffffff, 0x00000}
7942e1db
MC		 10258 };
10259 struct mem_entry *mem_tbl;
10260 int err = 0;
10261 int i;
10262
321d32a0
MC		 10263 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10264 mem_tbl = mem_tbl_5755;
10265 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10266 mem_tbl = mem_tbl_5906;
10267 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10268 mem_tbl = mem_tbl_5705;
10269 else
7942e1db
MC		 10270 mem_tbl = mem_tbl_570x;
10271
10272 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10273 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10274 mem_tbl[i].len)) != 0)
10275 break;
10276 }
6aa20a22 10277
7942e1db
MC		 10278 return err;
10279}
10280
9f40dead
MC		 10281#define TG3_MAC_LOOPBACK 0
10282#define TG3_PHY_LOOPBACK 1
10283
10284static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10285{
9f40dead 10286 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10287 u32 desc_idx, coal_now;
c76949a6
MC		 10288 struct sk_buff *skb, *rx_skb;
10289 u8 *tx_data;
10290 dma_addr_t map;
10291 int num_pkts, tx_len, rx_len, i, err;
10292 struct tg3_rx_buffer_desc *desc;
898a56f8 10293 struct tg3_napi *tnapi, *rnapi;
21f581a5 10294 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10295
0c1d0e2b
MC		 10296 if (tp->irq_cnt > 1) {
10297 tnapi = &tp->napi[1];
10298 rnapi = &tp->napi[1];
10299 } else {
10300 tnapi = &tp->napi[0];
10301 rnapi = &tp->napi[0];
10302 }
fd2ce37f 10303 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10304
9f40dead 10305 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10306 /* HW errata - mac loopback fails in some cases on 5780.
10307 * Normal traffic and PHY loopback are not affected by
10308 * errata.
10309 */
10310 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10311 return 0;
10312
9f40dead 10313 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10314 MAC_MODE_PORT_INT_LPBACK;
10315 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10316 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10317 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10318 mac_mode |= MAC_MODE_PORT_MODE_MII;
10319 else
10320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10321 tw32(MAC_MODE, mac_mode);
10322 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10323 u32 val;
10324
7f97a4bd
MC		 10325 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10326 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10327 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10328 } else
10329 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10330
9ef8ca99
MC		 10331 tg3_phy_toggle_automdix(tp, 0);
10332
3f7045c1 10333 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10334 udelay(40);
5d64ad34 10335
e8f3f6ca 10336 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10337 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10339 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10340 mac_mode |= MAC_MODE_PORT_MODE_MII;
10341 } else
10342 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10343
c94e3941
MC		 10344 /* reset to prevent losing 1st rx packet intermittently */
10345 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10346 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10347 udelay(10);
10348 tw32_f(MAC_RX_MODE, tp->rx_mode);
10349 }
e8f3f6ca
MC		 10350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10351 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10352 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10353 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10354 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10355 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10356 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10357 }
9f40dead 10358 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10359 }
10360 else
10361 return -EINVAL;
c76949a6
MC		 10362
10363 err = -EIO;
10364
c76949a6 10365 tx_len = 1514;
a20e9c62 10366 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10367 if (!skb)
10368 return -ENOMEM;
10369
c76949a6
MC		 10370 tx_data = skb_put(skb, tx_len);
10371 memcpy(tx_data, tp->dev->dev_addr, 6);
10372 memset(tx_data + 6, 0x0, 8);
10373
10374 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10375
10376 for (i = 14; i < tx_len; i++)
10377 tx_data[i] = (u8) (i & 0xff);
10378
a21771dd
MC		 10379 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10380 dev_kfree_skb(skb);
10381 return -EIO;
10382 }
c76949a6
MC		 10383
10384 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10385 rnapi->coal_now);
c76949a6
MC		 10386
10387 udelay(10);
10388
898a56f8 10389 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10390
c76949a6
MC		 10391 num_pkts = 0;
10392
a21771dd
MC		 10393 tg3_set_txd(tnapi, tnapi->tx_prod,
10394 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
c76949a6 10395
f3f3f27e 10396 tnapi->tx_prod++;
c76949a6
MC		 10397 num_pkts++;
10398
f3f3f27e
MC		 10399 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10400 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10401
10402 udelay(10);
10403
3f7045c1
MC		 10404 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10405 for (i = 0; i < 25; i++) {
c76949a6 10406 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10407 coal_now);
c76949a6
MC		 10408
10409 udelay(10);
10410
898a56f8
MC		 10411 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10412 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10413 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10414 (rx_idx == (rx_start_idx + num_pkts)))
10415 break;
10416 }
10417
a21771dd 10418 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
c76949a6
MC		 10419 dev_kfree_skb(skb);
10420
f3f3f27e 10421 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10422 goto out;
10423
10424 if (rx_idx != rx_start_idx + num_pkts)
10425 goto out;
10426
72334482 10427 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10428 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10429 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10430 if (opaque_key != RXD_OPAQUE_RING_STD)
10431 goto out;
10432
10433 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10434 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10435 goto out;
10436
10437 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10438 if (rx_len != tx_len)
10439 goto out;
10440
21f581a5 10441 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10442
21f581a5 10443 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10444 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10445
10446 for (i = 14; i < tx_len; i++) {
10447 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10448 goto out;
10449 }
10450 err = 0;
6aa20a22 10451
c76949a6
MC		 10452 /* tg3_free_rings will unmap and free the rx_skb */
10453out:
10454 return err;
10455}
10456
9f40dead
MC		 10457#define TG3_MAC_LOOPBACK_FAILED 1
10458#define TG3_PHY_LOOPBACK_FAILED 2
10459#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10460 TG3_PHY_LOOPBACK_FAILED)
10461
10462static int tg3_test_loopback(struct tg3 *tp)
10463{
10464 int err = 0;
9936bcf6 10465 u32 cpmuctrl = 0;
9f40dead
MC		 10466
10467 if (!netif_running(tp->dev))
10468 return TG3_LOOPBACK_FAILED;
10469
b9ec6c1b
MC		 10470 err = tg3_reset_hw(tp, 1);
10471 if (err)
10472 return TG3_LOOPBACK_FAILED;
9f40dead 10473
6833c043
MC		 10474 /* Turn off gphy autopowerdown. */
10475 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10476 tg3_phy_toggle_apd(tp, false);
10477
321d32a0 10478 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10479 int i;
10480 u32 status;
10481
10482 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10483
10484 /* Wait for up to 40 microseconds to acquire lock. */
10485 for (i = 0; i < 4; i++) {
10486 status = tr32(TG3_CPMU_MUTEX_GNT);
10487 if (status == CPMU_MUTEX_GNT_DRIVER)
10488 break;
10489 udelay(10);
10490 }
10491
10492 if (status != CPMU_MUTEX_GNT_DRIVER)
10493 return TG3_LOOPBACK_FAILED;
10494
b2a5c19c 10495 /* Turn off link-based power management. */
e875093c 10496 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10497 tw32(TG3_CPMU_CTRL,
10498 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10499 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10500 }
10501
9f40dead
MC		 10502 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10503 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10504
321d32a0 10505 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10506 tw32(TG3_CPMU_CTRL, cpmuctrl);
10507
10508 /* Release the mutex */
10509 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10510 }
10511
dd477003
MC		 10512 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10513 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10514 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10515 err |= TG3_PHY_LOOPBACK_FAILED;
10516 }
10517
6833c043
MC		 10518 /* Re-enable gphy autopowerdown. */
10519 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10520 tg3_phy_toggle_apd(tp, true);
10521
9f40dead
MC		 10522 return err;
10523}
10524
4cafd3f5
MC		 10525static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10526 u64 *data)
10527{
566f86ad
MC		 10528 struct tg3 *tp = netdev_priv(dev);
10529
bc1c7567
MC		 10530 if (tp->link_config.phy_is_low_power)
10531 tg3_set_power_state(tp, PCI_D0);
10532
566f86ad
MC		 10533 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10534
10535 if (tg3_test_nvram(tp) != 0) {
10536 etest->flags |= ETH_TEST_FL_FAILED;
10537 data[0] = 1;
10538 }
ca43007a
MC		 10539 if (tg3_test_link(tp) != 0) {
10540 etest->flags |= ETH_TEST_FL_FAILED;
10541 data[1] = 1;
10542 }
a71116d1 10543 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10544 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10545
10546 if (netif_running(dev)) {
b02fd9e3 10547 tg3_phy_stop(tp);
a71116d1 10548 tg3_netif_stop(tp);
bbe832c0
MC		 10549 irq_sync = 1;
10550 }
a71116d1 10551
bbe832c0 10552 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10553
10554 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10555 err = tg3_nvram_lock(tp);
a71116d1
MC		 10556 tg3_halt_cpu(tp, RX_CPU_BASE);
10557 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10558 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10559 if (!err)
10560 tg3_nvram_unlock(tp);
a71116d1 10561
d9ab5ad1
MC		 10562 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10563 tg3_phy_reset(tp);
10564
a71116d1
MC		 10565 if (tg3_test_registers(tp) != 0) {
10566 etest->flags |= ETH_TEST_FL_FAILED;
10567 data[2] = 1;
10568 }
7942e1db
MC		 10569 if (tg3_test_memory(tp) != 0) {
10570 etest->flags |= ETH_TEST_FL_FAILED;
10571 data[3] = 1;
10572 }
9f40dead 10573 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10574 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10575
f47c11ee
DM		 10576 tg3_full_unlock(tp);
10577
d4bc3927
MC		 10578 if (tg3_test_interrupt(tp) != 0) {
10579 etest->flags |= ETH_TEST_FL_FAILED;
10580 data[5] = 1;
10581 }
f47c11ee
DM		 10582
10583 tg3_full_lock(tp, 0);
d4bc3927 10584
a71116d1
MC		 10585 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10586 if (netif_running(dev)) {
10587 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10588 err2 = tg3_restart_hw(tp, 1);
10589 if (!err2)
b9ec6c1b 10590 tg3_netif_start(tp);
a71116d1 10591 }
f47c11ee
DM		 10592
10593 tg3_full_unlock(tp);
b02fd9e3
MC		 10594
10595 if (irq_sync && !err2)
10596 tg3_phy_start(tp);
a71116d1 10597 }
bc1c7567
MC		 10598 if (tp->link_config.phy_is_low_power)
10599 tg3_set_power_state(tp, PCI_D3hot);
10600
4cafd3f5
MC		 10601}
10602
1da177e4
LT		 10603static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10604{
10605 struct mii_ioctl_data *data = if_mii(ifr);
10606 struct tg3 *tp = netdev_priv(dev);
10607 int err;
10608
b02fd9e3 10609 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10610 struct phy_device *phydev;
b02fd9e3
MC		 10611 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10612 return -EAGAIN;
3f0e3ad7
MC		 10613 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10614 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10615 }
10616
1da177e4
LT		 10617 switch(cmd) {
10618 case SIOCGMIIPHY:
882e9793 10619 data->phy_id = tp->phy_addr;
1da177e4
LT		 10620
10621 /* fallthru */
10622 case SIOCGMIIREG: {
10623 u32 mii_regval;
10624
10625 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10626 break; /* We have no PHY */
10627
bc1c7567
MC		 10628 if (tp->link_config.phy_is_low_power)
10629 return -EAGAIN;
10630
f47c11ee 10631 spin_lock_bh(&tp->lock);
1da177e4 10632 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10633 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10634
10635 data->val_out = mii_regval;
10636
10637 return err;
10638 }
10639
10640 case SIOCSMIIREG:
10641 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10642 break; /* We have no PHY */
10643
bc1c7567
MC		 10644 if (tp->link_config.phy_is_low_power)
10645 return -EAGAIN;
10646
f47c11ee 10647 spin_lock_bh(&tp->lock);
1da177e4 10648 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10649 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10650
10651 return err;
10652
10653 default:
10654 /* do nothing */
10655 break;
10656 }
10657 return -EOPNOTSUPP;
10658}
10659
10660#if TG3_VLAN_TAG_USED
10661static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10662{
10663 struct tg3 *tp = netdev_priv(dev);
10664
844b3eed
MC		 10665 if (!netif_running(dev)) {
10666 tp->vlgrp = grp;
10667 return;
10668 }
10669
10670 tg3_netif_stop(tp);
29315e87 10671
f47c11ee 10672 tg3_full_lock(tp, 0);
1da177e4
LT		 10673
10674 tp->vlgrp = grp;
10675
10676 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10677 __tg3_set_rx_mode(dev);
10678
844b3eed 10679 tg3_netif_start(tp);
46966545
MC		 10680
10681 tg3_full_unlock(tp);
1da177e4 10682}
1da177e4
LT		 10683#endif
10684
15f9850d
DM		 10685static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10686{
10687 struct tg3 *tp = netdev_priv(dev);
10688
10689 memcpy(ec, &tp->coal, sizeof(*ec));
10690 return 0;
10691}
10692
d244c892
MC		 10693static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10694{
10695 struct tg3 *tp = netdev_priv(dev);
10696 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10697 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10698
10699 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10700 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10701 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10702 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10703 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10704 }
10705
10706 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10707 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10708 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10709 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10710 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10711 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10712 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10713 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10714 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10715 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10716 return -EINVAL;
10717
10718 /* No rx interrupts will be generated if both are zero */
10719 if ((ec->rx_coalesce_usecs == 0) &&
10720 (ec->rx_max_coalesced_frames == 0))
10721 return -EINVAL;
10722
10723 /* No tx interrupts will be generated if both are zero */
10724 if ((ec->tx_coalesce_usecs == 0) &&
10725 (ec->tx_max_coalesced_frames == 0))
10726 return -EINVAL;
10727
10728 /* Only copy relevant parameters, ignore all others. */
10729 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10730 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10731 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10732 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10733 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10734 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10735 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10736 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10737 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10738
10739 if (netif_running(dev)) {
10740 tg3_full_lock(tp, 0);
10741 __tg3_set_coalesce(tp, &tp->coal);
10742 tg3_full_unlock(tp);
10743 }
10744 return 0;
10745}
10746
7282d491 10747static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10748 .get_settings = tg3_get_settings,
10749 .set_settings = tg3_set_settings,
10750 .get_drvinfo = tg3_get_drvinfo,
10751 .get_regs_len = tg3_get_regs_len,
10752 .get_regs = tg3_get_regs,
10753 .get_wol = tg3_get_wol,
10754 .set_wol = tg3_set_wol,
10755 .get_msglevel = tg3_get_msglevel,
10756 .set_msglevel = tg3_set_msglevel,
10757 .nway_reset = tg3_nway_reset,
10758 .get_link = ethtool_op_get_link,
10759 .get_eeprom_len = tg3_get_eeprom_len,
10760 .get_eeprom = tg3_get_eeprom,
10761 .set_eeprom = tg3_set_eeprom,
10762 .get_ringparam = tg3_get_ringparam,
10763 .set_ringparam = tg3_set_ringparam,
10764 .get_pauseparam = tg3_get_pauseparam,
10765 .set_pauseparam = tg3_set_pauseparam,
10766 .get_rx_csum = tg3_get_rx_csum,
10767 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10768 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10769 .set_sg = ethtool_op_set_sg,
1da177e4 10770 .set_tso = tg3_set_tso,
4cafd3f5 10771 .self_test = tg3_self_test,
1da177e4 10772 .get_strings = tg3_get_strings,
4009a93d 10773 .phys_id = tg3_phys_id,
1da177e4 10774 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10775 .get_coalesce = tg3_get_coalesce,
d244c892 10776 .set_coalesce = tg3_set_coalesce,
b9f2c044 10777 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10778};
10779
10780static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10781{
1b27777a 10782 u32 cursize, val, magic;
1da177e4
LT		 10783
10784 tp->nvram_size = EEPROM_CHIP_SIZE;
10785
e4f34110 10786 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10787 return;
10788
b16250e3
MC		 10789 if ((magic != TG3_EEPROM_MAGIC) &&
10790 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10791 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10792 return;
10793
10794 /*
10795 * Size the chip by reading offsets at increasing powers of two.
10796 * When we encounter our validation signature, we know the addressing
10797 * has wrapped around, and thus have our chip size.
10798 */
1b27777a 10799 cursize = 0x10;
1da177e4
LT		 10800
10801 while (cursize < tp->nvram_size) {
e4f34110 10802 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10803 return;
10804
1820180b 10805 if (val == magic)
1da177e4
LT		 10806 break;
10807
10808 cursize <<= 1;
10809 }
10810
10811 tp->nvram_size = cursize;
10812}
6aa20a22 10813
1da177e4
LT		 10814static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10815{
10816 u32 val;
10817
df259d8c
MC		 10818 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10819 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10820 return;
10821
10822 /* Selfboot format */
1820180b 10823 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10824 tg3_get_eeprom_size(tp);
10825 return;
10826 }
10827
6d348f2c 10828 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10829 if (val != 0) {
6d348f2c
MC		 10830 /* This is confusing. We want to operate on the
10831 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10832 * call will read from NVRAM and byteswap the data
10833 * according to the byteswapping settings for all
10834 * other register accesses. This ensures the data we
10835 * want will always reside in the lower 16-bits.
10836 * However, the data in NVRAM is in LE format, which
10837 * means the data from the NVRAM read will always be
10838 * opposite the endianness of the CPU. The 16-bit
10839 * byteswap then brings the data to CPU endianness.
10840 */
10841 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10842 return;
10843 }
10844 }
fd1122a2 10845 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10846}
10847
10848static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10849{
10850 u32 nvcfg1;
10851
10852 nvcfg1 = tr32(NVRAM_CFG1);
10853 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10854 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10855 } else {
1da177e4
LT		 10856 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10857 tw32(NVRAM_CFG1, nvcfg1);
10858 }
10859
4c987487 10860 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10861 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10862 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10863 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10864 tp->nvram_jedecnum = JEDEC_ATMEL;
10865 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10866 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10867 break;
10868 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10869 tp->nvram_jedecnum = JEDEC_ATMEL;
10870 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10871 break;
10872 case FLASH_VENDOR_ATMEL_EEPROM:
10873 tp->nvram_jedecnum = JEDEC_ATMEL;
10874 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10875 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10876 break;
10877 case FLASH_VENDOR_ST:
10878 tp->nvram_jedecnum = JEDEC_ST;
10879 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10880 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10881 break;
10882 case FLASH_VENDOR_SAIFUN:
10883 tp->nvram_jedecnum = JEDEC_SAIFUN;
10884 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10885 break;
10886 case FLASH_VENDOR_SST_SMALL:
10887 case FLASH_VENDOR_SST_LARGE:
10888 tp->nvram_jedecnum = JEDEC_SST;
10889 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10890 break;
1da177e4 10891 }
8590a603 10892 } else {
1da177e4
LT		 10893 tp->nvram_jedecnum = JEDEC_ATMEL;
10894 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10895 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10896 }
10897}
10898
a1b950d5
MC		 10899static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10900{
10901 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10902 case FLASH_5752PAGE_SIZE_256:
10903 tp->nvram_pagesize = 256;
10904 break;
10905 case FLASH_5752PAGE_SIZE_512:
10906 tp->nvram_pagesize = 512;
10907 break;
10908 case FLASH_5752PAGE_SIZE_1K:
10909 tp->nvram_pagesize = 1024;
10910 break;
10911 case FLASH_5752PAGE_SIZE_2K:
10912 tp->nvram_pagesize = 2048;
10913 break;
10914 case FLASH_5752PAGE_SIZE_4K:
10915 tp->nvram_pagesize = 4096;
10916 break;
10917 case FLASH_5752PAGE_SIZE_264:
10918 tp->nvram_pagesize = 264;
10919 break;
10920 case FLASH_5752PAGE_SIZE_528:
10921 tp->nvram_pagesize = 528;
10922 break;
10923 }
10924}
10925
361b4ac2
MC		 10926static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10927{
10928 u32 nvcfg1;
10929
10930 nvcfg1 = tr32(NVRAM_CFG1);
10931
e6af301b
MC		 10932 /* NVRAM protection for TPM */
10933 if (nvcfg1 & (1 << 27))
10934 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10935
361b4ac2 10936 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10937 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10938 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10939 tp->nvram_jedecnum = JEDEC_ATMEL;
10940 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10941 break;
10942 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10943 tp->nvram_jedecnum = JEDEC_ATMEL;
10944 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10945 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10946 break;
10947 case FLASH_5752VENDOR_ST_M45PE10:
10948 case FLASH_5752VENDOR_ST_M45PE20:
10949 case FLASH_5752VENDOR_ST_M45PE40:
10950 tp->nvram_jedecnum = JEDEC_ST;
10951 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10952 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10953 break;
361b4ac2
MC		 10954 }
10955
10956 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 10957 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 10958 } else {
361b4ac2
MC		 10959 /* For eeprom, set pagesize to maximum eeprom size */
10960 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10961
10962 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10963 tw32(NVRAM_CFG1, nvcfg1);
10964 }
10965}
10966
d3c7b886
MC		 10967static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10968{
989a9d23 10969 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10970
10971 nvcfg1 = tr32(NVRAM_CFG1);
10972
10973 /* NVRAM protection for TPM */
989a9d23 10974 if (nvcfg1 & (1 << 27)) {
d3c7b886 10975 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10976 protect = 1;
10977 }
d3c7b886 10978
989a9d23
MC		 10979 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10980 switch (nvcfg1) {
8590a603
MC		 10981 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10982 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10983 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10984 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10985 tp->nvram_jedecnum = JEDEC_ATMEL;
10986 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10987 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10988 tp->nvram_pagesize = 264;
10989 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10990 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10991 tp->nvram_size = (protect ? 0x3e200 :
10992 TG3_NVRAM_SIZE_512KB);
10993 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10994 tp->nvram_size = (protect ? 0x1f200 :
10995 TG3_NVRAM_SIZE_256KB);
10996 else
10997 tp->nvram_size = (protect ? 0x1f200 :
10998 TG3_NVRAM_SIZE_128KB);
10999 break;
11000 case FLASH_5752VENDOR_ST_M45PE10:
11001 case FLASH_5752VENDOR_ST_M45PE20:
11002 case FLASH_5752VENDOR_ST_M45PE40:
11003 tp->nvram_jedecnum = JEDEC_ST;
11004 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11005 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11006 tp->nvram_pagesize = 256;
11007 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11008 tp->nvram_size = (protect ?
11009 TG3_NVRAM_SIZE_64KB :
11010 TG3_NVRAM_SIZE_128KB);
11011 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11012 tp->nvram_size = (protect ?
11013 TG3_NVRAM_SIZE_64KB :
11014 TG3_NVRAM_SIZE_256KB);
11015 else
11016 tp->nvram_size = (protect ?
11017 TG3_NVRAM_SIZE_128KB :
11018 TG3_NVRAM_SIZE_512KB);
11019 break;
d3c7b886
MC		 11020 }
11021}
11022
1b27777a
MC		 11023static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11024{
11025 u32 nvcfg1;
11026
11027 nvcfg1 = tr32(NVRAM_CFG1);
11028
11029 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11030 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11031 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11032 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11033 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11034 tp->nvram_jedecnum = JEDEC_ATMEL;
11035 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11036 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11037
8590a603
MC		 11038 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11039 tw32(NVRAM_CFG1, nvcfg1);
11040 break;
11041 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11042 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11043 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11044 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11045 tp->nvram_jedecnum = JEDEC_ATMEL;
11046 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11047 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11048 tp->nvram_pagesize = 264;
11049 break;
11050 case FLASH_5752VENDOR_ST_M45PE10:
11051 case FLASH_5752VENDOR_ST_M45PE20:
11052 case FLASH_5752VENDOR_ST_M45PE40:
11053 tp->nvram_jedecnum = JEDEC_ST;
11054 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11055 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11056 tp->nvram_pagesize = 256;
11057 break;
1b27777a
MC		 11058 }
11059}
11060
6b91fa02
MC		 11061static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11062{
11063 u32 nvcfg1, protect = 0;
11064
11065 nvcfg1 = tr32(NVRAM_CFG1);
11066
11067 /* NVRAM protection for TPM */
11068 if (nvcfg1 & (1 << 27)) {
11069 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11070 protect = 1;
11071 }
11072
11073 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11074 switch (nvcfg1) {
8590a603
MC		 11075 case FLASH_5761VENDOR_ATMEL_ADB021D:
11076 case FLASH_5761VENDOR_ATMEL_ADB041D:
11077 case FLASH_5761VENDOR_ATMEL_ADB081D:
11078 case FLASH_5761VENDOR_ATMEL_ADB161D:
11079 case FLASH_5761VENDOR_ATMEL_MDB021D:
11080 case FLASH_5761VENDOR_ATMEL_MDB041D:
11081 case FLASH_5761VENDOR_ATMEL_MDB081D:
11082 case FLASH_5761VENDOR_ATMEL_MDB161D:
11083 tp->nvram_jedecnum = JEDEC_ATMEL;
11084 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11085 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11086 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11087 tp->nvram_pagesize = 256;
11088 break;
11089 case FLASH_5761VENDOR_ST_A_M45PE20:
11090 case FLASH_5761VENDOR_ST_A_M45PE40:
11091 case FLASH_5761VENDOR_ST_A_M45PE80:
11092 case FLASH_5761VENDOR_ST_A_M45PE16:
11093 case FLASH_5761VENDOR_ST_M_M45PE20:
11094 case FLASH_5761VENDOR_ST_M_M45PE40:
11095 case FLASH_5761VENDOR_ST_M_M45PE80:
11096 case FLASH_5761VENDOR_ST_M_M45PE16:
11097 tp->nvram_jedecnum = JEDEC_ST;
11098 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11099 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11100 tp->nvram_pagesize = 256;
11101 break;
6b91fa02
MC		 11102 }
11103
11104 if (protect) {
11105 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11106 } else {
11107 switch (nvcfg1) {
8590a603
MC		 11108 case FLASH_5761VENDOR_ATMEL_ADB161D:
11109 case FLASH_5761VENDOR_ATMEL_MDB161D:
11110 case FLASH_5761VENDOR_ST_A_M45PE16:
11111 case FLASH_5761VENDOR_ST_M_M45PE16:
11112 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11113 break;
11114 case FLASH_5761VENDOR_ATMEL_ADB081D:
11115 case FLASH_5761VENDOR_ATMEL_MDB081D:
11116 case FLASH_5761VENDOR_ST_A_M45PE80:
11117 case FLASH_5761VENDOR_ST_M_M45PE80:
11118 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11119 break;
11120 case FLASH_5761VENDOR_ATMEL_ADB041D:
11121 case FLASH_5761VENDOR_ATMEL_MDB041D:
11122 case FLASH_5761VENDOR_ST_A_M45PE40:
11123 case FLASH_5761VENDOR_ST_M_M45PE40:
11124 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11125 break;
11126 case FLASH_5761VENDOR_ATMEL_ADB021D:
11127 case FLASH_5761VENDOR_ATMEL_MDB021D:
11128 case FLASH_5761VENDOR_ST_A_M45PE20:
11129 case FLASH_5761VENDOR_ST_M_M45PE20:
11130 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11131 break;
6b91fa02
MC		 11132 }
11133 }
11134}
11135
b5d3772c
MC		 11136static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11137{
11138 tp->nvram_jedecnum = JEDEC_ATMEL;
11139 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11140 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11141}
11142
321d32a0
MC		 11143static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11144{
11145 u32 nvcfg1;
11146
11147 nvcfg1 = tr32(NVRAM_CFG1);
11148
11149 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11150 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11151 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11152 tp->nvram_jedecnum = JEDEC_ATMEL;
11153 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11154 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11155
11156 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11157 tw32(NVRAM_CFG1, nvcfg1);
11158 return;
11159 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11160 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11161 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11162 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11163 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11164 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11165 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11166 tp->nvram_jedecnum = JEDEC_ATMEL;
11167 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11168 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11169
11170 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11171 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11172 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11173 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11174 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11175 break;
11176 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11177 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11178 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11179 break;
11180 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11181 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11182 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11183 break;
11184 }
11185 break;
11186 case FLASH_5752VENDOR_ST_M45PE10:
11187 case FLASH_5752VENDOR_ST_M45PE20:
11188 case FLASH_5752VENDOR_ST_M45PE40:
11189 tp->nvram_jedecnum = JEDEC_ST;
11190 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11191 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11192
11193 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11194 case FLASH_5752VENDOR_ST_M45PE10:
11195 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11196 break;
11197 case FLASH_5752VENDOR_ST_M45PE20:
11198 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11199 break;
11200 case FLASH_5752VENDOR_ST_M45PE40:
11201 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11202 break;
11203 }
11204 break;
11205 default:
df259d8c 11206 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11207 return;
11208 }
11209
a1b950d5
MC		 11210 tg3_nvram_get_pagesize(tp, nvcfg1);
11211 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11212 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11213}
11214
11215
11216static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11217{
11218 u32 nvcfg1;
11219
11220 nvcfg1 = tr32(NVRAM_CFG1);
11221
11222 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11223 case FLASH_5717VENDOR_ATMEL_EEPROM:
11224 case FLASH_5717VENDOR_MICRO_EEPROM:
11225 tp->nvram_jedecnum = JEDEC_ATMEL;
11226 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11227 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11228
11229 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11230 tw32(NVRAM_CFG1, nvcfg1);
11231 return;
11232 case FLASH_5717VENDOR_ATMEL_MDB011D:
11233 case FLASH_5717VENDOR_ATMEL_ADB011B:
11234 case FLASH_5717VENDOR_ATMEL_ADB011D:
11235 case FLASH_5717VENDOR_ATMEL_MDB021D:
11236 case FLASH_5717VENDOR_ATMEL_ADB021B:
11237 case FLASH_5717VENDOR_ATMEL_ADB021D:
11238 case FLASH_5717VENDOR_ATMEL_45USPT:
11239 tp->nvram_jedecnum = JEDEC_ATMEL;
11240 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11241 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11242
11243 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11244 case FLASH_5717VENDOR_ATMEL_MDB021D:
11245 case FLASH_5717VENDOR_ATMEL_ADB021B:
11246 case FLASH_5717VENDOR_ATMEL_ADB021D:
11247 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11248 break;
11249 default:
11250 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11251 break;
11252 }
321d32a0 11253 break;
a1b950d5
MC		 11254 case FLASH_5717VENDOR_ST_M_M25PE10:
11255 case FLASH_5717VENDOR_ST_A_M25PE10:
11256 case FLASH_5717VENDOR_ST_M_M45PE10:
11257 case FLASH_5717VENDOR_ST_A_M45PE10:
11258 case FLASH_5717VENDOR_ST_M_M25PE20:
11259 case FLASH_5717VENDOR_ST_A_M25PE20:
11260 case FLASH_5717VENDOR_ST_M_M45PE20:
11261 case FLASH_5717VENDOR_ST_A_M45PE20:
11262 case FLASH_5717VENDOR_ST_25USPT:
11263 case FLASH_5717VENDOR_ST_45USPT:
11264 tp->nvram_jedecnum = JEDEC_ST;
11265 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11266 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11267
11268 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11269 case FLASH_5717VENDOR_ST_M_M25PE20:
11270 case FLASH_5717VENDOR_ST_A_M25PE20:
11271 case FLASH_5717VENDOR_ST_M_M45PE20:
11272 case FLASH_5717VENDOR_ST_A_M45PE20:
11273 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11274 break;
11275 default:
11276 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11277 break;
11278 }
321d32a0 11279 break;
a1b950d5
MC		 11280 default:
11281 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11282 return;
321d32a0 11283 }
a1b950d5
MC		 11284
11285 tg3_nvram_get_pagesize(tp, nvcfg1);
11286 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11287 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11288}
11289
1da177e4
LT		 11290/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11291static void __devinit tg3_nvram_init(struct tg3 *tp)
11292{
1da177e4
LT		 11293 tw32_f(GRC_EEPROM_ADDR,
11294 (EEPROM_ADDR_FSM_RESET |
11295 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11296 EEPROM_ADDR_CLKPERD_SHIFT)));
11297
9d57f01c 11298 msleep(1);
1da177e4
LT		 11299
11300 /* Enable seeprom accesses. */
11301 tw32_f(GRC_LOCAL_CTRL,
11302 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11303 udelay(100);
11304
11305 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11306 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11307 tp->tg3_flags |= TG3_FLAG_NVRAM;
11308
ec41c7df
MC		 11309 if (tg3_nvram_lock(tp)) {
11310 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11311 "tg3_nvram_init failed.\n", tp->dev->name);
11312 return;
11313 }
e6af301b 11314 tg3_enable_nvram_access(tp);
1da177e4 11315
989a9d23
MC		 11316 tp->nvram_size = 0;
11317
361b4ac2
MC		 11318 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11319 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11320 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11321 tg3_get_5755_nvram_info(tp);
d30cdd28 11322 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11323 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11325 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11326 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11327 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11328 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11329 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11330 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11331 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11332 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11333 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11334 else
11335 tg3_get_nvram_info(tp);
11336
989a9d23
MC		 11337 if (tp->nvram_size == 0)
11338 tg3_get_nvram_size(tp);
1da177e4 11339
e6af301b 11340 tg3_disable_nvram_access(tp);
381291b7 11341 tg3_nvram_unlock(tp);
1da177e4
LT		 11342
11343 } else {
11344 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11345
11346 tg3_get_eeprom_size(tp);
11347 }
11348}
11349
1da177e4
LT		 11350static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11351 u32 offset, u32 len, u8 *buf)
11352{
11353 int i, j, rc = 0;
11354 u32 val;
11355
11356 for (i = 0; i < len; i += 4) {
b9fc7dc5 11357 u32 addr;
a9dc529d 11358 __be32 data;
1da177e4
LT		 11359
11360 addr = offset + i;
11361
11362 memcpy(&data, buf + i, 4);
11363
62cedd11
MC		 11364 /*
11365 * The SEEPROM interface expects the data to always be opposite
11366 * the native endian format. We accomplish this by reversing
11367 * all the operations that would have been performed on the
11368 * data from a call to tg3_nvram_read_be32().
11369 */
11370 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11371
11372 val = tr32(GRC_EEPROM_ADDR);
11373 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11374
11375 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11376 EEPROM_ADDR_READ);
11377 tw32(GRC_EEPROM_ADDR, val |
11378 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11379 (addr & EEPROM_ADDR_ADDR_MASK) |
11380 EEPROM_ADDR_START |
11381 EEPROM_ADDR_WRITE);
6aa20a22 11382
9d57f01c 11383 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11384 val = tr32(GRC_EEPROM_ADDR);
11385
11386 if (val & EEPROM_ADDR_COMPLETE)
11387 break;
9d57f01c 11388 msleep(1);
1da177e4
LT		 11389 }
11390 if (!(val & EEPROM_ADDR_COMPLETE)) {
11391 rc = -EBUSY;
11392 break;
11393 }
11394 }
11395
11396 return rc;
11397}
11398
11399/* offset and length are dword aligned */
11400static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11401 u8 *buf)
11402{
11403 int ret = 0;
11404 u32 pagesize = tp->nvram_pagesize;
11405 u32 pagemask = pagesize - 1;
11406 u32 nvram_cmd;
11407 u8 *tmp;
11408
11409 tmp = kmalloc(pagesize, GFP_KERNEL);
11410 if (tmp == NULL)
11411 return -ENOMEM;
11412
11413 while (len) {
11414 int j;
e6af301b 11415 u32 phy_addr, page_off, size;
1da177e4
LT		 11416
11417 phy_addr = offset & ~pagemask;
6aa20a22 11418
1da177e4 11419 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11420 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11421 (__be32 *) (tmp + j));
11422 if (ret)
1da177e4
LT		 11423 break;
11424 }
11425 if (ret)
11426 break;
11427
11428 page_off = offset & pagemask;
11429 size = pagesize;
11430 if (len < size)
11431 size = len;
11432
11433 len -= size;
11434
11435 memcpy(tmp + page_off, buf, size);
11436
11437 offset = offset + (pagesize - page_off);
11438
e6af301b 11439 tg3_enable_nvram_access(tp);
1da177e4
LT		 11440
11441 /*
11442 * Before we can erase the flash page, we need
11443 * to issue a special "write enable" command.
11444 */
11445 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11446
11447 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11448 break;
11449
11450 /* Erase the target page */
11451 tw32(NVRAM_ADDR, phy_addr);
11452
11453 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11454 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11455
11456 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11457 break;
11458
11459 /* Issue another write enable to start the write. */
11460 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11461
11462 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11463 break;
11464
11465 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11466 __be32 data;
1da177e4 11467
b9fc7dc5 11468 data = *((__be32 *) (tmp + j));
a9dc529d 11469
b9fc7dc5 11470 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11471
11472 tw32(NVRAM_ADDR, phy_addr + j);
11473
11474 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11475 NVRAM_CMD_WR;
11476
11477 if (j == 0)
11478 nvram_cmd |= NVRAM_CMD_FIRST;
11479 else if (j == (pagesize - 4))
11480 nvram_cmd |= NVRAM_CMD_LAST;
11481
11482 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11483 break;
11484 }
11485 if (ret)
11486 break;
11487 }
11488
11489 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11490 tg3_nvram_exec_cmd(tp, nvram_cmd);
11491
11492 kfree(tmp);
11493
11494 return ret;
11495}
11496
11497/* offset and length are dword aligned */
11498static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11499 u8 *buf)
11500{
11501 int i, ret = 0;
11502
11503 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11504 u32 page_off, phy_addr, nvram_cmd;
11505 __be32 data;
1da177e4
LT		 11506
11507 memcpy(&data, buf + i, 4);
b9fc7dc5 11508 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11509
11510 page_off = offset % tp->nvram_pagesize;
11511
1820180b 11512 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11513
11514 tw32(NVRAM_ADDR, phy_addr);
11515
11516 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11517
11518 if ((page_off == 0) || (i == 0))
11519 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11520 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11521 nvram_cmd |= NVRAM_CMD_LAST;
11522
11523 if (i == (len - 4))
11524 nvram_cmd |= NVRAM_CMD_LAST;
11525
321d32a0
MC		 11526 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11527 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11528 (tp->nvram_jedecnum == JEDEC_ST) &&
11529 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11530
11531 if ((ret = tg3_nvram_exec_cmd(tp,
11532 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11533 NVRAM_CMD_DONE)))
11534
11535 break;
11536 }
11537 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11538 /* We always do complete word writes to eeprom. */
11539 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11540 }
11541
11542 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11543 break;
11544 }
11545 return ret;
11546}
11547
11548/* offset and length are dword aligned */
11549static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11550{
11551 int ret;
11552
1da177e4 11553 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11554 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11555 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11556 udelay(40);
11557 }
11558
11559 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11560 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11561 }
11562 else {
11563 u32 grc_mode;
11564
ec41c7df
MC		 11565 ret = tg3_nvram_lock(tp);
11566 if (ret)
11567 return ret;
1da177e4 11568
e6af301b
MC		 11569 tg3_enable_nvram_access(tp);
11570 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11571 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11572 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11573
11574 grc_mode = tr32(GRC_MODE);
11575 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11576
11577 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11578 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11579
11580 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11581 buf);
11582 }
11583 else {
11584 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11585 buf);
11586 }
11587
11588 grc_mode = tr32(GRC_MODE);
11589 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11590
e6af301b 11591 tg3_disable_nvram_access(tp);
1da177e4
LT		 11592 tg3_nvram_unlock(tp);
11593 }
11594
11595 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11596 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11597 udelay(40);
11598 }
11599
11600 return ret;
11601}
11602
11603struct subsys_tbl_ent {
11604 u16 subsys_vendor, subsys_devid;
11605 u32 phy_id;
11606};
11607
11608static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11609 /* Broadcom boards. */
11610 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11611 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11612 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11613 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11614 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11615 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11616 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11617 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11618 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11619 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11620 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11621
11622 /* 3com boards. */
11623 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11624 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11625 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11626 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11627 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11628
11629 /* DELL boards. */
11630 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11631 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11632 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11633 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11634
11635 /* Compaq boards. */
11636 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11637 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11638 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11639 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11640 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11641
11642 /* IBM boards. */
11643 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11644};
11645
11646static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11647{
11648 int i;
11649
11650 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11651 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11652 tp->pdev->subsystem_vendor) &&
11653 (subsys_id_to_phy_id[i].subsys_devid ==
11654 tp->pdev->subsystem_device))
11655 return &subsys_id_to_phy_id[i];
11656 }
11657 return NULL;
11658}
11659
7d0c41ef 11660static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11661{
1da177e4 11662 u32 val;
caf636c7
MC		 11663 u16 pmcsr;
11664
11665 /* On some early chips the SRAM cannot be accessed in D3hot state,
11666 * so need make sure we're in D0.
11667 */
11668 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11669 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11670 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11671 msleep(1);
7d0c41ef
MC		 11672
11673 /* Make sure register accesses (indirect or otherwise)
11674 * will function correctly.
11675 */
11676 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11677 tp->misc_host_ctrl);
1da177e4 11678
f49639e6
DM		 11679 /* The memory arbiter has to be enabled in order for SRAM accesses
11680 * to succeed. Normally on powerup the tg3 chip firmware will make
11681 * sure it is enabled, but other entities such as system netboot
11682 * code might disable it.
11683 */
11684 val = tr32(MEMARB_MODE);
11685 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11686
1da177e4 11687 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11688 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11689
a85feb8c
GZ		 11690 /* Assume an onboard device and WOL capable by default. */
11691 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11692
b5d3772c 11693 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11694 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11695 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11696 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11697 }
0527ba35
MC		 11698 val = tr32(VCPU_CFGSHDW);
11699 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11700 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11701 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11702 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11703 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11704 goto done;
b5d3772c
MC		 11705 }
11706
1da177e4
LT		 11707 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11708 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11709 u32 nic_cfg, led_cfg;
a9daf367 11710 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11711 int eeprom_phy_serdes = 0;
1da177e4
LT		 11712
11713 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11714 tp->nic_sram_data_cfg = nic_cfg;
11715
11716 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11717 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11718 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11719 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11720 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11721 (ver > 0) && (ver < 0x100))
11722 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11723
a9daf367
MC		 11724 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11725 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11726
1da177e4
LT		 11727 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11728 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11729 eeprom_phy_serdes = 1;
11730
11731 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11732 if (nic_phy_id != 0) {
11733 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11734 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11735
11736 eeprom_phy_id = (id1 >> 16) << 10;
11737 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11738 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11739 } else
11740 eeprom_phy_id = 0;
11741
7d0c41ef 11742 tp->phy_id = eeprom_phy_id;
747e8f8b 11743 if (eeprom_phy_serdes) {
a4e2b347 11744 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11745 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11746 else
11747 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11748 }
7d0c41ef 11749
cbf46853 11750 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11751 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11752 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11753 else
1da177e4
LT		 11754 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11755
11756 switch (led_cfg) {
11757 default:
11758 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11759 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11760 break;
11761
11762 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11763 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11764 break;
11765
11766 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11767 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11768
11769 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11770 * read on some older 5700/5701 bootcode.
11771 */
11772 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11773 ASIC_REV_5700 ||
11774 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11775 ASIC_REV_5701)
11776 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11777
1da177e4
LT		 11778 break;
11779
11780 case SHASTA_EXT_LED_SHARED:
11781 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11782 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11783 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11784 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11785 LED_CTRL_MODE_PHY_2);
11786 break;
11787
11788 case SHASTA_EXT_LED_MAC:
11789 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11790 break;
11791
11792 case SHASTA_EXT_LED_COMBO:
11793 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11794 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11795 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11796 LED_CTRL_MODE_PHY_2);
11797 break;
11798
855e1111 11799 }
1da177e4
LT		 11800
11801 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11803 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11804 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11805
b2a5c19c
MC		 11806 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11807 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11808
9d26e213 11809 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11810 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11811 if ((tp->pdev->subsystem_vendor ==
11812 PCI_VENDOR_ID_ARIMA) &&
11813 (tp->pdev->subsystem_device == 0x205a ||
11814 tp->pdev->subsystem_device == 0x2063))
11815 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11816 } else {
f49639e6 11817 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11818 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11819 }
1da177e4
LT		 11820
11821 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11822 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11823 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11824 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11825 }
b2b98d4a
MC		 11826
11827 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11828 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11829 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11830
a85feb8c
GZ		 11831 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11832 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11833 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11834
12dac075 11835 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11836 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11837 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11838
1da177e4
LT		 11839 if (cfg2 & (1 << 17))
11840 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11841
11842 /* serdes signal pre-emphasis in register 0x590 set by */
11843 /* bootcode if bit 18 is set */
11844 if (cfg2 & (1 << 18))
11845 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11846
321d32a0
MC		 11847 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11848 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11849 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11850 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11851
8ed5d97e
MC		 11852 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11853 u32 cfg3;
11854
11855 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11856 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11857 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11858 }
a9daf367
MC		 11859
11860 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11861 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11862 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11863 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11864 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11865 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11866 }
05ac4cb7
MC		 11867done:
11868 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11869 device_set_wakeup_enable(&tp->pdev->dev,
11870 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11871}
11872
b2a5c19c
MC		 11873static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11874{
11875 int i;
11876 u32 val;
11877
11878 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11879 tw32(OTP_CTRL, cmd);
11880
11881 /* Wait for up to 1 ms for command to execute. */
11882 for (i = 0; i < 100; i++) {
11883 val = tr32(OTP_STATUS);
11884 if (val & OTP_STATUS_CMD_DONE)
11885 break;
11886 udelay(10);
11887 }
11888
11889 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11890}
11891
11892/* Read the gphy configuration from the OTP region of the chip. The gphy
11893 * configuration is a 32-bit value that straddles the alignment boundary.
11894 * We do two 32-bit reads and then shift and merge the results.
11895 */
11896static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11897{
11898 u32 bhalf_otp, thalf_otp;
11899
11900 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11901
11902 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11903 return 0;
11904
11905 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11906
11907 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11908 return 0;
11909
11910 thalf_otp = tr32(OTP_READ_DATA);
11911
11912 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11913
11914 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11915 return 0;
11916
11917 bhalf_otp = tr32(OTP_READ_DATA);
11918
11919 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11920}
11921
7d0c41ef
MC		 11922static int __devinit tg3_phy_probe(struct tg3 *tp)
11923{
11924 u32 hw_phy_id_1, hw_phy_id_2;
11925 u32 hw_phy_id, hw_phy_id_masked;
11926 int err;
1da177e4 11927
b02fd9e3
MC		 11928 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11929 return tg3_phy_init(tp);
11930
1da177e4 11931 /* Reading the PHY ID register can conflict with ASF
877d0310 11932 * firmware access to the PHY hardware.
1da177e4
LT		 11933 */
11934 err = 0;
0d3031d9
MC		 11935 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11936 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11937 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11938 } else {
11939 /* Now read the physical PHY_ID from the chip and verify
11940 * that it is sane. If it doesn't look good, we fall back
11941 * to either the hard-coded table based PHY_ID and failing
11942 * that the value found in the eeprom area.
11943 */
11944 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11945 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11946
11947 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11948 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11949 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11950
11951 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11952 }
11953
11954 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11955 tp->phy_id = hw_phy_id;
11956 if (hw_phy_id_masked == PHY_ID_BCM8002)
11957 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11958 else
11959 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11960 } else {
7d0c41ef
MC		 11961 if (tp->phy_id != PHY_ID_INVALID) {
11962 /* Do nothing, phy ID already set up in
11963 * tg3_get_eeprom_hw_cfg().
11964 */
1da177e4
LT		 11965 } else {
11966 struct subsys_tbl_ent *p;
11967
11968 /* No eeprom signature? Try the hardcoded
11969 * subsys device table.
11970 */
11971 p = lookup_by_subsys(tp);
11972 if (!p)
11973 return -ENODEV;
11974
11975 tp->phy_id = p->phy_id;
11976 if (!tp->phy_id ||
11977 tp->phy_id == PHY_ID_BCM8002)
11978 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11979 }
11980 }
11981
747e8f8b 11982 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11983 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11984 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11985 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11986
11987 tg3_readphy(tp, MII_BMSR, &bmsr);
11988 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11989 (bmsr & BMSR_LSTATUS))
11990 goto skip_phy_reset;
6aa20a22 11991
1da177e4
LT		 11992 err = tg3_phy_reset(tp);
11993 if (err)
11994 return err;
11995
11996 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11997 ADVERTISE_100HALF | ADVERTISE_100FULL |
11998 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11999 tg3_ctrl = 0;
12000 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12001 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12002 MII_TG3_CTRL_ADV_1000_FULL);
12003 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12004 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12005 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12006 MII_TG3_CTRL_ENABLE_AS_MASTER);
12007 }
12008
3600d918
MC		 12009 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12010 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12011 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12012 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12013 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12014
12015 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12016 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12017
12018 tg3_writephy(tp, MII_BMCR,
12019 BMCR_ANENABLE | BMCR_ANRESTART);
12020 }
12021 tg3_phy_set_wirespeed(tp);
12022
12023 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12024 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12025 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12026 }
12027
12028skip_phy_reset:
12029 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12030 err = tg3_init_5401phy_dsp(tp);
12031 if (err)
12032 return err;
12033 }
12034
12035 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12036 err = tg3_init_5401phy_dsp(tp);
12037 }
12038
747e8f8b 12039 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12040 tp->link_config.advertising =
12041 (ADVERTISED_1000baseT_Half |
12042 ADVERTISED_1000baseT_Full |
12043 ADVERTISED_Autoneg |
12044 ADVERTISED_FIBRE);
12045 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12046 tp->link_config.advertising &=
12047 ~(ADVERTISED_1000baseT_Half |
12048 ADVERTISED_1000baseT_Full);
12049
12050 return err;
12051}
12052
12053static void __devinit tg3_read_partno(struct tg3 *tp)
12054{
6d348f2c 12055 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12056 unsigned int i;
1b27777a 12057 u32 magic;
1da177e4 12058
df259d8c
MC		 12059 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12060 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12061 goto out_not_found;
1da177e4 12062
1820180b 12063 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12064 for (i = 0; i < 256; i += 4) {
12065 u32 tmp;
1da177e4 12066
6d348f2c
MC		 12067 /* The data is in little-endian format in NVRAM.
12068 * Use the big-endian read routines to preserve
12069 * the byte order as it exists in NVRAM.
12070 */
12071 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12072 goto out_not_found;
12073
6d348f2c 12074 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12075 }
12076 } else {
12077 int vpd_cap;
12078
12079 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12080 for (i = 0; i < 256; i += 4) {
12081 u32 tmp, j = 0;
b9fc7dc5 12082 __le32 v;
1b27777a
MC		 12083 u16 tmp16;
12084
12085 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12086 i);
12087 while (j++ < 100) {
12088 pci_read_config_word(tp->pdev, vpd_cap +
12089 PCI_VPD_ADDR, &tmp16);
12090 if (tmp16 & 0x8000)
12091 break;
12092 msleep(1);
12093 }
f49639e6
DM		 12094 if (!(tmp16 & 0x8000))
12095 goto out_not_found;
12096
1b27777a
MC		 12097 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12098 &tmp);
b9fc7dc5 12099 v = cpu_to_le32(tmp);
6d348f2c 12100 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12101 }
1da177e4
LT		 12102 }
12103
12104 /* Now parse and find the part number. */
af2c6a4a 12105 for (i = 0; i < 254; ) {
1da177e4 12106 unsigned char val = vpd_data[i];
af2c6a4a 12107 unsigned int block_end;
1da177e4
LT		 12108
12109 if (val == 0x82 || val == 0x91) {
12110 i = (i + 3 +
12111 (vpd_data[i + 1] +
12112 (vpd_data[i + 2] << 8)));
12113 continue;
12114 }
12115
12116 if (val != 0x90)
12117 goto out_not_found;
12118
12119 block_end = (i + 3 +
12120 (vpd_data[i + 1] +
12121 (vpd_data[i + 2] << 8)));
12122 i += 3;
af2c6a4a
MC		 12123
12124 if (block_end > 256)
12125 goto out_not_found;
12126
12127 while (i < (block_end - 2)) {
1da177e4
LT		 12128 if (vpd_data[i + 0] == 'P' &&
12129 vpd_data[i + 1] == 'N') {
12130 int partno_len = vpd_data[i + 2];
12131
af2c6a4a
MC		 12132 i += 3;
12133 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12134 goto out_not_found;
12135
12136 memcpy(tp->board_part_number,
af2c6a4a 12137 &vpd_data[i], partno_len);
1da177e4
LT		 12138
12139 /* Success. */
12140 return;
12141 }
af2c6a4a 12142 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12143 }
12144
12145 /* Part number not found. */
12146 goto out_not_found;
12147 }
12148
12149out_not_found:
b5d3772c
MC		 12150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12151 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12152 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12153 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12154 strcpy(tp->board_part_number, "BCM57780");
12155 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12156 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12157 strcpy(tp->board_part_number, "BCM57760");
12158 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12159 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12160 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12161 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12162 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12163 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12164 else
12165 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12166}
12167
9c8a620e
MC		 12168static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12169{
12170 u32 val;
12171
e4f34110 12172 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12173 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12174 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12175 val != 0)
12176 return 0;
12177
12178 return 1;
12179}
12180
acd9c119
MC		 12181static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12182{
ff3a7cb2 12183 u32 val, offset, start, ver_offset;
acd9c119 12184 int i;
ff3a7cb2 12185 bool newver = false;
acd9c119
MC		 12186
12187 if (tg3_nvram_read(tp, 0xc, &offset) ||
12188 tg3_nvram_read(tp, 0x4, &start))
12189 return;
12190
12191 offset = tg3_nvram_logical_addr(tp, offset);
12192
ff3a7cb2 12193 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12194 return;
12195
ff3a7cb2
MC		 12196 if ((val & 0xfc000000) == 0x0c000000) {
12197 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12198 return;
12199
ff3a7cb2
MC		 12200 if (val == 0)
12201 newver = true;
12202 }
12203
12204 if (newver) {
12205 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12206 return;
12207
12208 offset = offset + ver_offset - start;
12209 for (i = 0; i < 16; i += 4) {
12210 __be32 v;
12211 if (tg3_nvram_read_be32(tp, offset + i, &v))
12212 return;
12213
12214 memcpy(tp->fw_ver + i, &v, sizeof(v));
12215 }
12216 } else {
12217 u32 major, minor;
12218
12219 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12220 return;
12221
12222 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12223 TG3_NVM_BCVER_MAJSFT;
12224 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12225 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12226 }
12227}
12228
a6f6cb1c
MC		 12229static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12230{
12231 u32 val, major, minor;
12232
12233 /* Use native endian representation */
12234 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12235 return;
12236
12237 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12238 TG3_NVM_HWSB_CFG1_MAJSFT;
12239 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12240 TG3_NVM_HWSB_CFG1_MINSFT;
12241
12242 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12243}
12244
dfe00d7d
MC		 12245static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12246{
12247 u32 offset, major, minor, build;
12248
12249 tp->fw_ver[0] = 's';
12250 tp->fw_ver[1] = 'b';
12251 tp->fw_ver[2] = '\0';
12252
12253 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12254 return;
12255
12256 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12257 case TG3_EEPROM_SB_REVISION_0:
12258 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12259 break;
12260 case TG3_EEPROM_SB_REVISION_2:
12261 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12262 break;
12263 case TG3_EEPROM_SB_REVISION_3:
12264 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12265 break;
12266 default:
12267 return;
12268 }
12269
e4f34110 12270 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12271 return;
12272
12273 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12274 TG3_EEPROM_SB_EDH_BLD_SHFT;
12275 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12276 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12277 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12278
12279 if (minor > 99 || build > 26)
12280 return;
12281
12282 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12283
12284 if (build > 0) {
12285 tp->fw_ver[8] = 'a' + build - 1;
12286 tp->fw_ver[9] = '\0';
12287 }
12288}
12289
acd9c119 12290static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12291{
12292 u32 val, offset, start;
acd9c119 12293 int i, vlen;
9c8a620e
MC		 12294
12295 for (offset = TG3_NVM_DIR_START;
12296 offset < TG3_NVM_DIR_END;
12297 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12298 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12299 return;
12300
9c8a620e
MC		 12301 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12302 break;
12303 }
12304
12305 if (offset == TG3_NVM_DIR_END)
12306 return;
12307
12308 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12309 start = 0x08000000;
e4f34110 12310 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12311 return;
12312
e4f34110 12313 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12314 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12315 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12316 return;
12317
12318 offset += val - start;
12319
acd9c119 12320 vlen = strlen(tp->fw_ver);
9c8a620e 12321
acd9c119
MC		 12322 tp->fw_ver[vlen++] = ',';
12323 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12324
12325 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12326 __be32 v;
12327 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12328 return;
12329
b9fc7dc5 12330 offset += sizeof(v);
c4e6575c 12331
acd9c119
MC		 12332 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12333 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12334 break;
c4e6575c 12335 }
9c8a620e 12336
acd9c119
MC		 12337 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12338 vlen += sizeof(v);
c4e6575c 12339 }
acd9c119
MC		 12340}
12341
7fd76445
MC		 12342static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12343{
12344 int vlen;
12345 u32 apedata;
12346
12347 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12348 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12349 return;
12350
12351 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12352 if (apedata != APE_SEG_SIG_MAGIC)
12353 return;
12354
12355 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12356 if (!(apedata & APE_FW_STATUS_READY))
12357 return;
12358
12359 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12360
12361 vlen = strlen(tp->fw_ver);
12362
12363 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12364 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12365 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12366 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12367 (apedata & APE_FW_VERSION_BLDMSK));
12368}
12369
acd9c119
MC		 12370static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12371{
12372 u32 val;
12373
df259d8c
MC		 12374 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12375 tp->fw_ver[0] = 's';
12376 tp->fw_ver[1] = 'b';
12377 tp->fw_ver[2] = '\0';
12378
12379 return;
12380 }
12381
acd9c119
MC		 12382 if (tg3_nvram_read(tp, 0, &val))
12383 return;
12384
12385 if (val == TG3_EEPROM_MAGIC)
12386 tg3_read_bc_ver(tp);
12387 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12388 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12389 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12390 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12391 else
12392 return;
12393
12394 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12395 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12396 return;
12397
12398 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12399
12400 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12401}
12402
7544b097
MC		 12403static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12404
1da177e4
LT		 12405static int __devinit tg3_get_invariants(struct tg3 *tp)
12406{
12407 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12408 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12409 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12410 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12411 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12412 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12413 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12414 { },
12415 };
12416 u32 misc_ctrl_reg;
1da177e4
LT		 12417 u32 pci_state_reg, grc_misc_cfg;
12418 u32 val;
12419 u16 pci_cmd;
5e7dfd0f 12420 int err;
1da177e4 12421
1da177e4
LT		 12422 /* Force memory write invalidate off. If we leave it on,
12423 * then on 5700_BX chips we have to enable a workaround.
12424 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12425 * to match the cacheline size. The Broadcom driver have this
12426 * workaround but turns MWI off all the times so never uses
12427 * it. This seems to suggest that the workaround is insufficient.
12428 */
12429 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12430 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12431 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12432
12433 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12434 * has the register indirect write enable bit set before
12435 * we try to access any of the MMIO registers. It is also
12436 * critical that the PCI-X hw workaround situation is decided
12437 * before that as well.
12438 */
12439 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12440 &misc_ctrl_reg);
12441
12442 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12443 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12444 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12445 u32 prod_id_asic_rev;
12446
f6eb9b1f
MC		 12447 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12448 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12449 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12450 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12451 pci_read_config_dword(tp->pdev,
12452 TG3PCI_GEN2_PRODID_ASICREV,
12453 &prod_id_asic_rev);
12454 else
12455 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12456 &prod_id_asic_rev);
12457
321d32a0 12458 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12459 }
1da177e4 12460
ff645bec
MC		 12461 /* Wrong chip ID in 5752 A0. This code can be removed later
12462 * as A0 is not in production.
12463 */
12464 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12465 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12466
6892914f
MC		 12467 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12468 * we need to disable memory and use config. cycles
12469 * only to access all registers. The 5702/03 chips
12470 * can mistakenly decode the special cycles from the
12471 * ICH chipsets as memory write cycles, causing corruption
12472 * of register and memory space. Only certain ICH bridges
12473 * will drive special cycles with non-zero data during the
12474 * address phase which can fall within the 5703's address
12475 * range. This is not an ICH bug as the PCI spec allows
12476 * non-zero address during special cycles. However, only
12477 * these ICH bridges are known to drive non-zero addresses
12478 * during special cycles.
12479 *
12480 * Since special cycles do not cross PCI bridges, we only
12481 * enable this workaround if the 5703 is on the secondary
12482 * bus of these ICH bridges.
12483 */
12484 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12485 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12486 static struct tg3_dev_id {
12487 u32 vendor;
12488 u32 device;
12489 u32 rev;
12490 } ich_chipsets[] = {
12491 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12492 PCI_ANY_ID },
12493 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12494 PCI_ANY_ID },
12495 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12496 0xa },
12497 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12498 PCI_ANY_ID },
12499 { },
12500 };
12501 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12502 struct pci_dev *bridge = NULL;
12503
12504 while (pci_id->vendor != 0) {
12505 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12506 bridge);
12507 if (!bridge) {
12508 pci_id++;
12509 continue;
12510 }
12511 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12512 if (bridge->revision > pci_id->rev)
6892914f
MC		 12513 continue;
12514 }
12515 if (bridge->subordinate &&
12516 (bridge->subordinate->number ==
12517 tp->pdev->bus->number)) {
12518
12519 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12520 pci_dev_put(bridge);
12521 break;
12522 }
12523 }
12524 }
12525
41588ba1
MC		 12526 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12527 static struct tg3_dev_id {
12528 u32 vendor;
12529 u32 device;
12530 } bridge_chipsets[] = {
12531 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12532 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12533 { },
12534 };
12535 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12536 struct pci_dev *bridge = NULL;
12537
12538 while (pci_id->vendor != 0) {
12539 bridge = pci_get_device(pci_id->vendor,
12540 pci_id->device,
12541 bridge);
12542 if (!bridge) {
12543 pci_id++;
12544 continue;
12545 }
12546 if (bridge->subordinate &&
12547 (bridge->subordinate->number <=
12548 tp->pdev->bus->number) &&
12549 (bridge->subordinate->subordinate >=
12550 tp->pdev->bus->number)) {
12551 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12552 pci_dev_put(bridge);
12553 break;
12554 }
12555 }
12556 }
12557
4a29cc2e
MC		 12558 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12559 * DMA addresses > 40-bit. This bridge may have other additional
12560 * 57xx devices behind it in some 4-port NIC designs for example.
12561 * Any tg3 device found behind the bridge will also need the 40-bit
12562 * DMA workaround.
12563 */
a4e2b347
MC		 12564 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12565 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12566 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12567 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12568 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12569 }
4a29cc2e
MC		 12570 else {
12571 struct pci_dev *bridge = NULL;
12572
12573 do {
12574 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12575 PCI_DEVICE_ID_SERVERWORKS_EPB,
12576 bridge);
12577 if (bridge && bridge->subordinate &&
12578 (bridge->subordinate->number <=
12579 tp->pdev->bus->number) &&
12580 (bridge->subordinate->subordinate >=
12581 tp->pdev->bus->number)) {
12582 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12583 pci_dev_put(bridge);
12584 break;
12585 }
12586 } while (bridge);
12587 }
4cf78e4f 12588
1da177e4
LT		 12589 /* Initialize misc host control in PCI block. */
12590 tp->misc_host_ctrl |= (misc_ctrl_reg &
12591 MISC_HOST_CTRL_CHIPREV);
12592 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12593 tp->misc_host_ctrl);
12594
f6eb9b1f
MC		 12595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12597 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12598 tp->pdev_peer = tg3_find_peer(tp);
12599
321d32a0
MC		 12600 /* Intentionally exclude ASIC_REV_5906 */
12601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12602 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12603 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12604 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12605 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12606 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12607 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12608 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12609
12610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12611 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12612 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12613 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12614 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12615 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12616
1b440c56
JL		 12617 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12618 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12619 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12620
027455ad
MC		 12621 /* 5700 B0 chips do not support checksumming correctly due
12622 * to hardware bugs.
12623 */
12624 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12625 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12626 else {
12627 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12628 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12629 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12630 tp->dev->features |= NETIF_F_IPV6_CSUM;
12631 }
12632
5a6f3074 12633 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12634 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12635 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12636 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12637 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12638 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12639 tp->pdev_peer == tp->pdev))
12640 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12641
321d32a0 12642 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12643 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12644 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12645 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12646 } else {
7f62ad5d 12647 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12648 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12649 ASIC_REV_5750 &&
12650 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12651 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12652 }
5a6f3074 12653 }
1da177e4 12654
4f125f42
MC		 12655 tp->irq_max = 1;
12656
f6eb9b1f
MC		 12657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12658 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12659 tp->irq_max = TG3_IRQ_MAX_VECS;
12660 }
0e1406dd
MC		 12661
12662 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
92c6b8d1
MC		 12663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12664 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12665 else {
12666 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12667 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12668 }
0e1406dd 12669 }
f6eb9b1f 12670
f51f3562 12671 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12672 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12673 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12674 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12675
52f4490c
MC		 12676 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12677 &pci_state_reg);
12678
5e7dfd0f
MC		 12679 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12680 if (tp->pcie_cap != 0) {
12681 u16 lnkctl;
12682
1da177e4 12683 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12684
12685 pcie_set_readrq(tp->pdev, 4096);
12686
5e7dfd0f
MC		 12687 pci_read_config_word(tp->pdev,
12688 tp->pcie_cap + PCI_EXP_LNKCTL,
12689 &lnkctl);
12690 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12692 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12693 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12694 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12695 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12696 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12697 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12698 }
52f4490c 12699 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12700 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12701 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12702 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12703 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12704 if (!tp->pcix_cap) {
12705 printk(KERN_ERR PFX "Cannot find PCI-X "
12706 "capability, aborting.\n");
12707 return -EIO;
12708 }
12709
12710 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12711 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12712 }
1da177e4 12713
399de50b
MC		 12714 /* If we have an AMD 762 or VIA K8T800 chipset, write
12715 * reordering to the mailbox registers done by the host
12716 * controller can cause major troubles. We read back from
12717 * every mailbox register write to force the writes to be
12718 * posted to the chip in order.
12719 */
12720 if (pci_dev_present(write_reorder_chipsets) &&
12721 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12722 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12723
69fc4053
MC		 12724 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12725 &tp->pci_cacheline_sz);
12726 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12727 &tp->pci_lat_timer);
1da177e4
LT		 12728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12729 tp->pci_lat_timer < 64) {
12730 tp->pci_lat_timer = 64;
69fc4053
MC		 12731 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12732 tp->pci_lat_timer);
1da177e4
LT		 12733 }
12734
52f4490c
MC		 12735 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12736 /* 5700 BX chips need to have their TX producer index
12737 * mailboxes written twice to workaround a bug.
12738 */
12739 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12740
52f4490c 12741 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12742 *
12743 * The workaround is to use indirect register accesses
12744 * for all chip writes not to mailbox registers.
12745 */
52f4490c 12746 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12747 u32 pm_reg;
1da177e4
LT		 12748
12749 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12750
12751 /* The chip can have it's power management PCI config
12752 * space registers clobbered due to this bug.
12753 * So explicitly force the chip into D0 here.
12754 */
9974a356
MC		 12755 pci_read_config_dword(tp->pdev,
12756 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12757 &pm_reg);
12758 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12759 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12760 pci_write_config_dword(tp->pdev,
12761 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12762 pm_reg);
12763
12764 /* Also, force SERR#/PERR# in PCI command. */
12765 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12766 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12767 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12768 }
12769 }
12770
1da177e4
LT		 12771 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12772 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12773 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12774 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12775
12776 /* Chip-specific fixup from Broadcom driver */
12777 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12778 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12779 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12780 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12781 }
12782
1ee582d8 12783 /* Default fast path register access methods */
20094930 12784 tp->read32 = tg3_read32;
1ee582d8 12785 tp->write32 = tg3_write32;
09ee929c 12786 tp->read32_mbox = tg3_read32;
20094930 12787 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12788 tp->write32_tx_mbox = tg3_write32;
12789 tp->write32_rx_mbox = tg3_write32;
12790
12791 /* Various workaround register access methods */
12792 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12793 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12794 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12795 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12796 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12797 /*
12798 * Back to back register writes can cause problems on these
12799 * chips, the workaround is to read back all reg writes
12800 * except those to mailbox regs.
12801 *
12802 * See tg3_write_indirect_reg32().
12803 */
1ee582d8 12804 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12805 }
12806
1ee582d8
MC		 12807 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12808 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12809 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12810 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12811 tp->write32_rx_mbox = tg3_write_flush_reg32;
12812 }
20094930 12813
6892914f
MC		 12814 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12815 tp->read32 = tg3_read_indirect_reg32;
12816 tp->write32 = tg3_write_indirect_reg32;
12817 tp->read32_mbox = tg3_read_indirect_mbox;
12818 tp->write32_mbox = tg3_write_indirect_mbox;
12819 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12820 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12821
12822 iounmap(tp->regs);
22abe310 12823 tp->regs = NULL;
6892914f
MC		 12824
12825 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12826 pci_cmd &= ~PCI_COMMAND_MEMORY;
12827 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12828 }
b5d3772c
MC		 12829 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12830 tp->read32_mbox = tg3_read32_mbox_5906;
12831 tp->write32_mbox = tg3_write32_mbox_5906;
12832 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12833 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12834 }
6892914f 12835
bbadf503
MC		 12836 if (tp->write32 == tg3_write_indirect_reg32 ||
12837 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12838 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12839 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12840 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12841
7d0c41ef 12842 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12843 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12844 * determined before calling tg3_set_power_state() so that
12845 * we know whether or not to switch out of Vaux power.
12846 * When the flag is set, it means that GPIO1 is used for eeprom
12847 * write protect and also implies that it is a LOM where GPIOs
12848 * are not used to switch power.
6aa20a22 12849 */
7d0c41ef
MC		 12850 tg3_get_eeprom_hw_cfg(tp);
12851
0d3031d9
MC		 12852 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12853 /* Allow reads and writes to the
12854 * APE register and memory space.
12855 */
12856 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12857 PCISTATE_ALLOW_APE_SHMEM_WR;
12858 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12859 pci_state_reg);
12860 }
12861
9936bcf6 12862 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12863 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12864 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12865 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12867 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12868
314fba34
MC		 12869 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12870 * GPIO1 driven high will bring 5700's external PHY out of reset.
12871 * It is also used as eeprom write protect on LOMs.
12872 */
12873 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12874 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12875 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12876 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12877 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12878 /* Unused GPIO3 must be driven as output on 5752 because there
12879 * are no pull-up resistors on unused GPIO pins.
12880 */
12881 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12882 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12883
321d32a0
MC		 12884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12886 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12887
8d519ab2
MC		 12888 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12889 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12890 /* Turn off the debug UART. */
12891 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12892 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12893 /* Keep VMain power. */
12894 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12895 GRC_LCLCTRL_GPIO_OUTPUT0;
12896 }
12897
1da177e4 12898 /* Force the chip into D0. */
bc1c7567 12899 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12900 if (err) {
12901 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12902 pci_name(tp->pdev));
12903 return err;
12904 }
12905
1da177e4
LT		 12906 /* Derive initial jumbo mode from MTU assigned in
12907 * ether_setup() via the alloc_etherdev() call
12908 */
0f893dc6 12909 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12910 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12911 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12912
12913 /* Determine WakeOnLan speed to use. */
12914 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12915 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12916 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12917 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12918 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12919 } else {
12920 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12921 }
12922
7f97a4bd
MC		 12923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12924 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12925
1da177e4
LT		 12926 /* A few boards don't want Ethernet@WireSpeed phy feature */
12927 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12928 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12929 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12930 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12931 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12932 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12933 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12934
12935 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12936 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12937 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12938 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12939 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12940
321d32a0 12941 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12942 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 12943 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 12944 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12945 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 12946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12950 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12951 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12952 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12953 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12954 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12955 } else
c424cb24
MC		 12956 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12957 }
1da177e4 12958
b2a5c19c
MC		 12959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12960 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12961 tp->phy_otp = tg3_read_otp_phycfg(tp);
12962 if (tp->phy_otp == 0)
12963 tp->phy_otp = TG3_OTP_DEFAULT;
12964 }
12965
f51f3562 12966 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12967 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12968 else
12969 tp->mi_mode = MAC_MI_MODE_BASE;
12970
1da177e4 12971 tp->coalesce_mode = 0;
1da177e4
LT		 12972 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12973 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12974 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12975
321d32a0
MC		 12976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12978 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12979
158d7abd
MC		 12980 err = tg3_mdio_init(tp);
12981 if (err)
12982 return err;
1da177e4
LT		 12983
12984 /* Initialize data/descriptor byte/word swapping. */
12985 val = tr32(GRC_MODE);
12986 val &= GRC_MODE_HOST_STACKUP;
12987 tw32(GRC_MODE, val | tp->grc_mode);
12988
12989 tg3_switch_clocks(tp);
12990
12991 /* Clear this out for sanity. */
12992 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12993
12994 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12995 &pci_state_reg);
12996 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12997 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12998 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12999
13000 if (chiprevid == CHIPREV_ID_5701_A0 ||
13001 chiprevid == CHIPREV_ID_5701_B0 ||
13002 chiprevid == CHIPREV_ID_5701_B2 ||
13003 chiprevid == CHIPREV_ID_5701_B5) {
13004 void __iomem *sram_base;
13005
13006 /* Write some dummy words into the SRAM status block
13007 * area, see if it reads back correctly. If the return
13008 * value is bad, force enable the PCIX workaround.
13009 */
13010 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13011
13012 writel(0x00000000, sram_base);
13013 writel(0x00000000, sram_base + 4);
13014 writel(0xffffffff, sram_base + 4);
13015 if (readl(sram_base) != 0x00000000)
13016 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13017 }
13018 }
13019
13020 udelay(50);
13021 tg3_nvram_init(tp);
13022
13023 grc_misc_cfg = tr32(GRC_MISC_CFG);
13024 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13025
1da177e4
LT		 13026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13027 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13028 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13029 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13030
fac9b83e
DM		 13031 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13032 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13033 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13034 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13035 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13036 HOSTCC_MODE_CLRTICK_TXBD);
13037
13038 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13039 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13040 tp->misc_host_ctrl);
13041 }
13042
3bda1258
MC		 13043 /* Preserve the APE MAC_MODE bits */
13044 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13045 tp->mac_mode = tr32(MAC_MODE) |
13046 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13047 else
13048 tp->mac_mode = TG3_DEF_MAC_MODE;
13049
1da177e4
LT		 13050 /* these are limited to 10/100 only */
13051 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13052 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13053 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13054 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13055 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13056 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13057 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13058 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13059 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13060 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13061 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13062 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13063 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13064 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13065
13066 err = tg3_phy_probe(tp);
13067 if (err) {
13068 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13069 pci_name(tp->pdev), err);
13070 /* ... but do not return immediately ... */
b02fd9e3 13071 tg3_mdio_fini(tp);
1da177e4
LT		 13072 }
13073
13074 tg3_read_partno(tp);
c4e6575c 13075 tg3_read_fw_ver(tp);
1da177e4
LT		 13076
13077 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13078 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13079 } else {
13080 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13081 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13082 else
13083 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13084 }
13085
13086 /* 5700 {AX,BX} chips have a broken status block link
13087 * change bit implementation, so we must use the
13088 * status register in those cases.
13089 */
13090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13091 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13092 else
13093 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13094
13095 /* The led_ctrl is set during tg3_phy_probe, here we might
13096 * have to force the link status polling mechanism based
13097 * upon subsystem IDs.
13098 */
13099 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13101 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13102 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13103 TG3_FLAG_USE_LINKCHG_REG);
13104 }
13105
13106 /* For all SERDES we poll the MAC status register. */
13107 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13108 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13109 else
13110 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13111
ad829268 13112 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13114 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13115 tp->rx_offset = 0;
13116
f92905de
MC		 13117 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13118
13119 /* Increment the rx prod index on the rx std ring by at most
13120 * 8 for these chips to workaround hw errata.
13121 */
13122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13123 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13125 tp->rx_std_max_post = 8;
13126
8ed5d97e
MC		 13127 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13128 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13129 PCIE_PWR_MGMT_L1_THRESH_MSK;
13130
1da177e4
LT		 13131 return err;
13132}
13133
49b6e95f 13134#ifdef CONFIG_SPARC
1da177e4
LT		 13135static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13136{
13137 struct net_device *dev = tp->dev;
13138 struct pci_dev *pdev = tp->pdev;
49b6e95f 13139 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13140 const unsigned char *addr;
49b6e95f
DM		 13141 int len;
13142
13143 addr = of_get_property(dp, "local-mac-address", &len);
13144 if (addr && len == 6) {
13145 memcpy(dev->dev_addr, addr, 6);
13146 memcpy(dev->perm_addr, dev->dev_addr, 6);
13147 return 0;
1da177e4
LT		 13148 }
13149 return -ENODEV;
13150}
13151
13152static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13153{
13154 struct net_device *dev = tp->dev;
13155
13156 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13157 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13158 return 0;
13159}
13160#endif
13161
13162static int __devinit tg3_get_device_address(struct tg3 *tp)
13163{
13164 struct net_device *dev = tp->dev;
13165 u32 hi, lo, mac_offset;
008652b3 13166 int addr_ok = 0;
1da177e4 13167
49b6e95f 13168#ifdef CONFIG_SPARC
1da177e4
LT		 13169 if (!tg3_get_macaddr_sparc(tp))
13170 return 0;
13171#endif
13172
13173 mac_offset = 0x7c;
f49639e6 13174 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13175 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13176 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13177 mac_offset = 0xcc;
13178 if (tg3_nvram_lock(tp))
13179 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13180 else
13181 tg3_nvram_unlock(tp);
a1b950d5
MC		 13182 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13183 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13184 mac_offset = 0xcc;
13185 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13186 mac_offset = 0x10;
1da177e4
LT		 13187
13188 /* First try to get it from MAC address mailbox. */
13189 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13190 if ((hi >> 16) == 0x484b) {
13191 dev->dev_addr[0] = (hi >> 8) & 0xff;
13192 dev->dev_addr[1] = (hi >> 0) & 0xff;
13193
13194 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13195 dev->dev_addr[2] = (lo >> 24) & 0xff;
13196 dev->dev_addr[3] = (lo >> 16) & 0xff;
13197 dev->dev_addr[4] = (lo >> 8) & 0xff;
13198 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13199
008652b3
MC		 13200 /* Some old bootcode may report a 0 MAC address in SRAM */
13201 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13202 }
13203 if (!addr_ok) {
13204 /* Next, try NVRAM. */
df259d8c
MC		 13205 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13206 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13207 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13208 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13209 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13210 }
13211 /* Finally just fetch it out of the MAC control regs. */
13212 else {
13213 hi = tr32(MAC_ADDR_0_HIGH);
13214 lo = tr32(MAC_ADDR_0_LOW);
13215
13216 dev->dev_addr[5] = lo & 0xff;
13217 dev->dev_addr[4] = (lo >> 8) & 0xff;
13218 dev->dev_addr[3] = (lo >> 16) & 0xff;
13219 dev->dev_addr[2] = (lo >> 24) & 0xff;
13220 dev->dev_addr[1] = hi & 0xff;
13221 dev->dev_addr[0] = (hi >> 8) & 0xff;
13222 }
1da177e4
LT		 13223 }
13224
13225 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13226#ifdef CONFIG_SPARC
1da177e4
LT		 13227 if (!tg3_get_default_macaddr_sparc(tp))
13228 return 0;
13229#endif
13230 return -EINVAL;
13231 }
2ff43697 13232 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13233 return 0;
13234}
13235
59e6b434
DM		 13236#define BOUNDARY_SINGLE_CACHELINE 1
13237#define BOUNDARY_MULTI_CACHELINE 2
13238
13239static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13240{
13241 int cacheline_size;
13242 u8 byte;
13243 int goal;
13244
13245 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13246 if (byte == 0)
13247 cacheline_size = 1024;
13248 else
13249 cacheline_size = (int) byte * 4;
13250
13251 /* On 5703 and later chips, the boundary bits have no
13252 * effect.
13253 */
13254 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13255 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13256 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13257 goto out;
13258
13259#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13260 goal = BOUNDARY_MULTI_CACHELINE;
13261#else
13262#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13263 goal = BOUNDARY_SINGLE_CACHELINE;
13264#else
13265 goal = 0;
13266#endif
13267#endif
13268
13269 if (!goal)
13270 goto out;
13271
13272 /* PCI controllers on most RISC systems tend to disconnect
13273 * when a device tries to burst across a cache-line boundary.
13274 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13275 *
13276 * Unfortunately, for PCI-E there are only limited
13277 * write-side controls for this, and thus for reads
13278 * we will still get the disconnects. We'll also waste
13279 * these PCI cycles for both read and write for chips
13280 * other than 5700 and 5701 which do not implement the
13281 * boundary bits.
13282 */
13283 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13284 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13285 switch (cacheline_size) {
13286 case 16:
13287 case 32:
13288 case 64:
13289 case 128:
13290 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13291 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13292 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13293 } else {
13294 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13295 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13296 }
13297 break;
13298
13299 case 256:
13300 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13301 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13302 break;
13303
13304 default:
13305 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13306 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13307 break;
855e1111 13308 }
59e6b434
DM		 13309 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13310 switch (cacheline_size) {
13311 case 16:
13312 case 32:
13313 case 64:
13314 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13315 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13316 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13317 break;
13318 }
13319 /* fallthrough */
13320 case 128:
13321 default:
13322 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13323 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13324 break;
855e1111 13325 }
59e6b434
DM		 13326 } else {
13327 switch (cacheline_size) {
13328 case 16:
13329 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13330 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13331 DMA_RWCTRL_WRITE_BNDRY_16);
13332 break;
13333 }
13334 /* fallthrough */
13335 case 32:
13336 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13337 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13338 DMA_RWCTRL_WRITE_BNDRY_32);
13339 break;
13340 }
13341 /* fallthrough */
13342 case 64:
13343 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13344 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13345 DMA_RWCTRL_WRITE_BNDRY_64);
13346 break;
13347 }
13348 /* fallthrough */
13349 case 128:
13350 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13351 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13352 DMA_RWCTRL_WRITE_BNDRY_128);
13353 break;
13354 }
13355 /* fallthrough */
13356 case 256:
13357 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13358 DMA_RWCTRL_WRITE_BNDRY_256);
13359 break;
13360 case 512:
13361 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13362 DMA_RWCTRL_WRITE_BNDRY_512);
13363 break;
13364 case 1024:
13365 default:
13366 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13367 DMA_RWCTRL_WRITE_BNDRY_1024);
13368 break;
855e1111 13369 }
59e6b434
DM		 13370 }
13371
13372out:
13373 return val;
13374}
13375
1da177e4
LT		 13376static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13377{
13378 struct tg3_internal_buffer_desc test_desc;
13379 u32 sram_dma_descs;
13380 int i, ret;
13381
13382 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13383
13384 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13385 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13386 tw32(RDMAC_STATUS, 0);
13387 tw32(WDMAC_STATUS, 0);
13388
13389 tw32(BUFMGR_MODE, 0);
13390 tw32(FTQ_RESET, 0);
13391
13392 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13393 test_desc.addr_lo = buf_dma & 0xffffffff;
13394 test_desc.nic_mbuf = 0x00002100;
13395 test_desc.len = size;
13396
13397 /*
13398 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13399 * the *second* time the tg3 driver was getting loaded after an
13400 * initial scan.
13401 *
13402 * Broadcom tells me:
13403 * ...the DMA engine is connected to the GRC block and a DMA
13404 * reset may affect the GRC block in some unpredictable way...
13405 * The behavior of resets to individual blocks has not been tested.
13406 *
13407 * Broadcom noted the GRC reset will also reset all sub-components.
13408 */
13409 if (to_device) {
13410 test_desc.cqid_sqid = (13 << 8) | 2;
13411
13412 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13413 udelay(40);
13414 } else {
13415 test_desc.cqid_sqid = (16 << 8) | 7;
13416
13417 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13418 udelay(40);
13419 }
13420 test_desc.flags = 0x00000005;
13421
13422 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13423 u32 val;
13424
13425 val = *(((u32 *)&test_desc) + i);
13426 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13427 sram_dma_descs + (i * sizeof(u32)));
13428 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13429 }
13430 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13431
13432 if (to_device) {
13433 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13434 } else {
13435 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13436 }
13437
13438 ret = -ENODEV;
13439 for (i = 0; i < 40; i++) {
13440 u32 val;
13441
13442 if (to_device)
13443 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13444 else
13445 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13446 if ((val & 0xffff) == sram_dma_descs) {
13447 ret = 0;
13448 break;
13449 }
13450
13451 udelay(100);
13452 }
13453
13454 return ret;
13455}
13456
ded7340d 13457#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13458
13459static int __devinit tg3_test_dma(struct tg3 *tp)
13460{
13461 dma_addr_t buf_dma;
59e6b434 13462 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 13463 int ret;
13464
13465 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13466 if (!buf) {
13467 ret = -ENOMEM;
13468 goto out_nofree;
13469 }
13470
13471 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13472 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13473
59e6b434 13474 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 13475
13476 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13477 /* DMA read watermark not used on PCIE */
13478 tp->dma_rwctrl |= 0x00180000;
13479 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13481 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13482 tp->dma_rwctrl |= 0x003f0000;
13483 else
13484 tp->dma_rwctrl |= 0x003f000f;
13485 } else {
13486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13487 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13488 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13489 u32 read_water = 0x7;
1da177e4 13490
4a29cc2e
MC		 13491 /* If the 5704 is behind the EPB bridge, we can
13492 * do the less restrictive ONE_DMA workaround for
13493 * better performance.
13494 */
13495 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13497 tp->dma_rwctrl |= 0x8000;
13498 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13499 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13500
49afdeb6
MC		 13501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13502 read_water = 4;
59e6b434 13503 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13504 tp->dma_rwctrl |=
13505 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13506 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13507 (1 << 23);
4cf78e4f
MC		 13508 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13509 /* 5780 always in PCIX mode */
13510 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13511 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13512 /* 5714 always in PCIX mode */
13513 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13514 } else {
13515 tp->dma_rwctrl |= 0x001b000f;
13516 }
13517 }
13518
13519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13521 tp->dma_rwctrl &= 0xfffffff0;
13522
13523 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13525 /* Remove this if it causes problems for some boards. */
13526 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13527
13528 /* On 5700/5701 chips, we need to set this bit.
13529 * Otherwise the chip will issue cacheline transactions
13530 * to streamable DMA memory with not all the byte
13531 * enables turned on. This is an error on several
13532 * RISC PCI controllers, in particular sparc64.
13533 *
13534 * On 5703/5704 chips, this bit has been reassigned
13535 * a different meaning. In particular, it is used
13536 * on those chips to enable a PCI-X workaround.
13537 */
13538 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13539 }
13540
13541 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13542
13543#if 0
13544 /* Unneeded, already done by tg3_get_invariants. */
13545 tg3_switch_clocks(tp);
13546#endif
13547
13548 ret = 0;
13549 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13550 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13551 goto out;
13552
59e6b434
DM		 13553 /* It is best to perform DMA test with maximum write burst size
13554 * to expose the 5700/5701 write DMA bug.
13555 */
13556 saved_dma_rwctrl = tp->dma_rwctrl;
13557 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13558 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13559
1da177e4
LT		 13560 while (1) {
13561 u32 *p = buf, i;
13562
13563 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13564 p[i] = i;
13565
13566 /* Send the buffer to the chip. */
13567 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13568 if (ret) {
13569 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13570 break;
13571 }
13572
13573#if 0
13574 /* validate data reached card RAM correctly. */
13575 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13576 u32 val;
13577 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13578 if (le32_to_cpu(val) != p[i]) {
13579 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13580 /* ret = -ENODEV here? */
13581 }
13582 p[i] = 0;
13583 }
13584#endif
13585 /* Now read it back. */
13586 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13587 if (ret) {
13588 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13589
13590 break;
13591 }
13592
13593 /* Verify it. */
13594 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13595 if (p[i] == i)
13596 continue;
13597
59e6b434
DM		 13598 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13599 DMA_RWCTRL_WRITE_BNDRY_16) {
13600 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13601 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13602 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13603 break;
13604 } else {
13605 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13606 ret = -ENODEV;
13607 goto out;
13608 }
13609 }
13610
13611 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13612 /* Success. */
13613 ret = 0;
13614 break;
13615 }
13616 }
59e6b434
DM		 13617 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13618 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13619 static struct pci_device_id dma_wait_state_chipsets[] = {
13620 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13621 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13622 { },
13623 };
13624
59e6b434 13625 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13626 * now look for chipsets that are known to expose the
13627 * DMA bug without failing the test.
59e6b434 13628 */
6d1cfbab
MC		 13629 if (pci_dev_present(dma_wait_state_chipsets)) {
13630 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13631 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13632 }
13633 else
13634 /* Safe to use the calculated DMA boundary. */
13635 tp->dma_rwctrl = saved_dma_rwctrl;
13636
59e6b434
DM		 13637 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13638 }
1da177e4
LT		 13639
13640out:
13641 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13642out_nofree:
13643 return ret;
13644}
13645
13646static void __devinit tg3_init_link_config(struct tg3 *tp)
13647{
13648 tp->link_config.advertising =
13649 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13650 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13651 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13652 ADVERTISED_Autoneg | ADVERTISED_MII);
13653 tp->link_config.speed = SPEED_INVALID;
13654 tp->link_config.duplex = DUPLEX_INVALID;
13655 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13656 tp->link_config.active_speed = SPEED_INVALID;
13657 tp->link_config.active_duplex = DUPLEX_INVALID;
13658 tp->link_config.phy_is_low_power = 0;
13659 tp->link_config.orig_speed = SPEED_INVALID;
13660 tp->link_config.orig_duplex = DUPLEX_INVALID;
13661 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13662}
13663
13664static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13665{
f6eb9b1f
MC		 13666 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13667 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13668 tp->bufmgr_config.mbuf_read_dma_low_water =
13669 DEFAULT_MB_RDMA_LOW_WATER_5705;
13670 tp->bufmgr_config.mbuf_mac_rx_low_water =
13671 DEFAULT_MB_MACRX_LOW_WATER_5705;
13672 tp->bufmgr_config.mbuf_high_water =
13673 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13675 tp->bufmgr_config.mbuf_mac_rx_low_water =
13676 DEFAULT_MB_MACRX_LOW_WATER_5906;
13677 tp->bufmgr_config.mbuf_high_water =
13678 DEFAULT_MB_HIGH_WATER_5906;
13679 }
fdfec172
MC		 13680
13681 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13682 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13683 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13684 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13685 tp->bufmgr_config.mbuf_high_water_jumbo =
13686 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13687 } else {
13688 tp->bufmgr_config.mbuf_read_dma_low_water =
13689 DEFAULT_MB_RDMA_LOW_WATER;
13690 tp->bufmgr_config.mbuf_mac_rx_low_water =
13691 DEFAULT_MB_MACRX_LOW_WATER;
13692 tp->bufmgr_config.mbuf_high_water =
13693 DEFAULT_MB_HIGH_WATER;
13694
13695 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13696 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13697 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13698 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13699 tp->bufmgr_config.mbuf_high_water_jumbo =
13700 DEFAULT_MB_HIGH_WATER_JUMBO;
13701 }
1da177e4
LT		 13702
13703 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13704 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13705}
13706
13707static char * __devinit tg3_phy_string(struct tg3 *tp)
13708{
13709 switch (tp->phy_id & PHY_ID_MASK) {
13710 case PHY_ID_BCM5400: return "5400";
13711 case PHY_ID_BCM5401: return "5401";
13712 case PHY_ID_BCM5411: return "5411";
13713 case PHY_ID_BCM5701: return "5701";
13714 case PHY_ID_BCM5703: return "5703";
13715 case PHY_ID_BCM5704: return "5704";
13716 case PHY_ID_BCM5705: return "5705";
13717 case PHY_ID_BCM5750: return "5750";
85e94ced 13718 case PHY_ID_BCM5752: return "5752";
a4e2b347 13719 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13720 case PHY_ID_BCM5780: return "5780";
af36e6b6 13721 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13722 case PHY_ID_BCM5787: return "5787";
d30cdd28 13723 case PHY_ID_BCM5784: return "5784";
126a3368 13724 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13725 case PHY_ID_BCM5906: return "5906";
9936bcf6 13726 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13727 case PHY_ID_BCM8002: return "8002/serdes";
13728 case 0: return "serdes";
13729 default: return "unknown";
855e1111 13730 }
1da177e4
LT		 13731}
13732
f9804ddb
MC		 13733static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13734{
13735 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13736 strcpy(str, "PCI Express");
13737 return str;
13738 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13739 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13740
13741 strcpy(str, "PCIX:");
13742
13743 if ((clock_ctrl == 7) ||
13744 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13745 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13746 strcat(str, "133MHz");
13747 else if (clock_ctrl == 0)
13748 strcat(str, "33MHz");
13749 else if (clock_ctrl == 2)
13750 strcat(str, "50MHz");
13751 else if (clock_ctrl == 4)
13752 strcat(str, "66MHz");
13753 else if (clock_ctrl == 6)
13754 strcat(str, "100MHz");
f9804ddb
MC		 13755 } else {
13756 strcpy(str, "PCI:");
13757 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13758 strcat(str, "66MHz");
13759 else
13760 strcat(str, "33MHz");
13761 }
13762 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13763 strcat(str, ":32-bit");
13764 else
13765 strcat(str, ":64-bit");
13766 return str;
13767}
13768
8c2dc7e1 13769static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13770{
13771 struct pci_dev *peer;
13772 unsigned int func, devnr = tp->pdev->devfn & ~7;
13773
13774 for (func = 0; func < 8; func++) {
13775 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13776 if (peer && peer != tp->pdev)
13777 break;
13778 pci_dev_put(peer);
13779 }
16fe9d74
MC		 13780 /* 5704 can be configured in single-port mode, set peer to
13781 * tp->pdev in that case.
13782 */
13783 if (!peer) {
13784 peer = tp->pdev;
13785 return peer;
13786 }
1da177e4
LT		 13787
13788 /*
13789 * We don't need to keep the refcount elevated; there's no way
13790 * to remove one half of this device without removing the other
13791 */
13792 pci_dev_put(peer);
13793
13794 return peer;
13795}
13796
15f9850d
DM		 13797static void __devinit tg3_init_coal(struct tg3 *tp)
13798{
13799 struct ethtool_coalesce *ec = &tp->coal;
13800
13801 memset(ec, 0, sizeof(*ec));
13802 ec->cmd = ETHTOOL_GCOALESCE;
13803 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13804 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13805 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13806 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13807 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13808 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13809 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13810 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13811 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13812
13813 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13814 HOSTCC_MODE_CLRTICK_TXBD)) {
13815 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13816 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13817 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13818 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13819 }
d244c892
MC		 13820
13821 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13822 ec->rx_coalesce_usecs_irq = 0;
13823 ec->tx_coalesce_usecs_irq = 0;
13824 ec->stats_block_coalesce_usecs = 0;
13825 }
15f9850d
DM		 13826}
13827
7c7d64b8
SH		 13828static const struct net_device_ops tg3_netdev_ops = {
13829 .ndo_open = tg3_open,
13830 .ndo_stop = tg3_close,
00829823
SH		 13831 .ndo_start_xmit = tg3_start_xmit,
13832 .ndo_get_stats = tg3_get_stats,
13833 .ndo_validate_addr = eth_validate_addr,
13834 .ndo_set_multicast_list = tg3_set_rx_mode,
13835 .ndo_set_mac_address = tg3_set_mac_addr,
13836 .ndo_do_ioctl = tg3_ioctl,
13837 .ndo_tx_timeout = tg3_tx_timeout,
13838 .ndo_change_mtu = tg3_change_mtu,
13839#if TG3_VLAN_TAG_USED
13840 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13841#endif
13842#ifdef CONFIG_NET_POLL_CONTROLLER
13843 .ndo_poll_controller = tg3_poll_controller,
13844#endif
13845};
13846
13847static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13848 .ndo_open = tg3_open,
13849 .ndo_stop = tg3_close,
13850 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13851 .ndo_get_stats = tg3_get_stats,
13852 .ndo_validate_addr = eth_validate_addr,
13853 .ndo_set_multicast_list = tg3_set_rx_mode,
13854 .ndo_set_mac_address = tg3_set_mac_addr,
13855 .ndo_do_ioctl = tg3_ioctl,
13856 .ndo_tx_timeout = tg3_tx_timeout,
13857 .ndo_change_mtu = tg3_change_mtu,
13858#if TG3_VLAN_TAG_USED
13859 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13860#endif
13861#ifdef CONFIG_NET_POLL_CONTROLLER
13862 .ndo_poll_controller = tg3_poll_controller,
13863#endif
13864};
13865
1da177e4
LT		 13866static int __devinit tg3_init_one(struct pci_dev *pdev,
13867 const struct pci_device_id *ent)
13868{
13869 static int tg3_version_printed = 0;
1da177e4
LT		 13870 struct net_device *dev;
13871 struct tg3 *tp;
646c9edd
MC		 13872 int i, err, pm_cap;
13873 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13874 char str[40];
72f2afb8 13875 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13876
13877 if (tg3_version_printed++ == 0)
13878 printk(KERN_INFO "%s", version);
13879
13880 err = pci_enable_device(pdev);
13881 if (err) {
13882 printk(KERN_ERR PFX "Cannot enable PCI device, "
13883 "aborting.\n");
13884 return err;
13885 }
13886
1da177e4
LT		 13887 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13888 if (err) {
13889 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13890 "aborting.\n");
13891 goto err_out_disable_pdev;
13892 }
13893
13894 pci_set_master(pdev);
13895
13896 /* Find power-management capability. */
13897 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13898 if (pm_cap == 0) {
13899 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13900 "aborting.\n");
13901 err = -EIO;
13902 goto err_out_free_res;
13903 }
13904
fe5f5787 13905 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 13906 if (!dev) {
13907 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13908 err = -ENOMEM;
13909 goto err_out_free_res;
13910 }
13911
1da177e4
LT		 13912 SET_NETDEV_DEV(dev, &pdev->dev);
13913
1da177e4
LT		 13914#if TG3_VLAN_TAG_USED
13915 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13916#endif
13917
13918 tp = netdev_priv(dev);
13919 tp->pdev = pdev;
13920 tp->dev = dev;
13921 tp->pm_cap = pm_cap;
1da177e4
LT		 13922 tp->rx_mode = TG3_DEF_RX_MODE;
13923 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13924
1da177e4
LT		 13925 if (tg3_debug > 0)
13926 tp->msg_enable = tg3_debug;
13927 else
13928 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13929
13930 /* The word/byte swap controls here control register access byte
13931 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13932 * setting below.
13933 */
13934 tp->misc_host_ctrl =
13935 MISC_HOST_CTRL_MASK_PCI_INT |
13936 MISC_HOST_CTRL_WORD_SWAP |
13937 MISC_HOST_CTRL_INDIR_ACCESS |
13938 MISC_HOST_CTRL_PCISTATE_RW;
13939
13940 /* The NONFRM (non-frame) byte/word swap controls take effect
13941 * on descriptor entries, anything which isn't packet data.
13942 *
13943 * The StrongARM chips on the board (one for tx, one for rx)
13944 * are running in big-endian mode.
13945 */
13946 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13947 GRC_MODE_WSWAP_NONFRM_DATA);
13948#ifdef __BIG_ENDIAN
13949 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13950#endif
13951 spin_lock_init(&tp->lock);
1da177e4 13952 spin_lock_init(&tp->indirect_lock);
c4028958 13953 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13954
d5fe488a 13955 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13956 if (!tp->regs) {
1da177e4
LT		 13957 printk(KERN_ERR PFX "Cannot map device registers, "
13958 "aborting.\n");
13959 err = -ENOMEM;
13960 goto err_out_free_dev;
13961 }
13962
13963 tg3_init_link_config(tp);
13964
1da177e4
LT		 13965 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13966 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 13967
646c9edd
MC		 13968 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13969 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13970 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13971 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13972 struct tg3_napi *tnapi = &tp->napi[i];
13973
13974 tnapi->tp = tp;
13975 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13976
13977 tnapi->int_mbox = intmbx;
13978 if (i < 4)
13979 intmbx += 0x8;
13980 else
13981 intmbx += 0x4;
13982
13983 tnapi->consmbox = rcvmbx;
13984 tnapi->prodmbox = sndmbx;
13985
13986 if (i)
13987 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13988 else
13989 tnapi->coal_now = HOSTCC_MODE_NOW;
13990
13991 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13992 break;
13993
13994 /*
13995 * If we support MSIX, we'll be using RSS. If we're using
13996 * RSS, the first vector only handles link interrupts and the
13997 * remaining vectors handle rx and tx interrupts. Reuse the
13998 * mailbox values for the next iteration. The values we setup
13999 * above are still useful for the single vectored mode.
14000 */
14001 if (!i)
14002 continue;
14003
14004 rcvmbx += 0x8;
14005
14006 if (sndmbx & 0x4)
14007 sndmbx -= 0x4;
14008 else
14009 sndmbx += 0xc;
14010 }
14011
8ef0442f 14012 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 14013 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14014 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14015 dev->irq = pdev->irq;
1da177e4
LT		 14016
14017 err = tg3_get_invariants(tp);
14018 if (err) {
14019 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14020 "aborting.\n");
14021 goto err_out_iounmap;
14022 }
14023
92c6b8d1 14024 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
00829823
SH		 14025 dev->netdev_ops = &tg3_netdev_ops;
14026 else
14027 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14028
14029
4a29cc2e
MC		 14030 /* The EPB bridge inside 5714, 5715, and 5780 and any
14031 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14032 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14033 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14034 * do DMA address check in tg3_start_xmit().
14035 */
4a29cc2e 14036 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14037 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14038 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14039 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14040#ifdef CONFIG_HIGHMEM
6a35528a 14041 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14042#endif
4a29cc2e 14043 } else
6a35528a 14044 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14045
14046 /* Configure DMA attributes. */
284901a9 14047 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14048 err = pci_set_dma_mask(pdev, dma_mask);
14049 if (!err) {
14050 dev->features |= NETIF_F_HIGHDMA;
14051 err = pci_set_consistent_dma_mask(pdev,
14052 persist_dma_mask);
14053 if (err < 0) {
14054 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14055 "DMA for consistent allocations\n");
14056 goto err_out_iounmap;
14057 }
14058 }
14059 }
284901a9
YH		 14060 if (err || dma_mask == DMA_BIT_MASK(32)) {
14061 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14062 if (err) {
14063 printk(KERN_ERR PFX "No usable DMA configuration, "
14064 "aborting.\n");
14065 goto err_out_iounmap;
14066 }
14067 }
14068
fdfec172 14069 tg3_init_bufmgr_config(tp);
1da177e4 14070
077f849d 14071 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 14072 tp->fw_needed = FIRMWARE_TG3;
077f849d 14073
1da177e4
LT		 14074 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14075 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14076 }
14077 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14079 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 14080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 14081 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14082 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14083 } else {
7f62ad5d 14084 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 14085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 14086 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 14087 else
9e9fd12d 14088 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 14089 }
1da177e4 14090
4e3a7aaa
MC		 14091 /* TSO is on by default on chips that support hardware TSO.
14092 * Firmware TSO on older chips gives lower performance, so it
14093 * is off by default, but can be enabled using ethtool.
14094 */
b0026624 14095 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 14096 if (dev->features & NETIF_F_IP_CSUM)
14097 dev->features |= NETIF_F_TSO;
14098 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14099 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 14100 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 14101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14102 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14103 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 14105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6 14107 dev->features |= NETIF_F_TSO_ECN;
b0026624 14108 }
1da177e4 14109
1da177e4
LT		 14110
14111 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14112 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14113 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14114 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14115 tp->rx_pending = 63;
14116 }
14117
1da177e4
LT		 14118 err = tg3_get_device_address(tp);
14119 if (err) {
14120 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14121 "aborting.\n");
077f849d 14122 goto err_out_fw;
1da177e4
LT		 14123 }
14124
c88864df 14125 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14126 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14127 if (!tp->aperegs) {
c88864df
MC		 14128 printk(KERN_ERR PFX "Cannot map APE registers, "
14129 "aborting.\n");
14130 err = -ENOMEM;
077f849d 14131 goto err_out_fw;
c88864df
MC		 14132 }
14133
14134 tg3_ape_lock_init(tp);
7fd76445
MC		 14135
14136 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14137 tg3_read_dash_ver(tp);
c88864df
MC		 14138 }
14139
1da177e4
LT		 14140 /*
14141 * Reset chip in case UNDI or EFI driver did not shutdown
14142 * DMA self test will enable WDMAC and we'll see (spurious)
14143 * pending DMA on the PCI bus at that point.
14144 */
14145 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14146 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14147 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14148 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14149 }
14150
14151 err = tg3_test_dma(tp);
14152 if (err) {
14153 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14154 goto err_out_apeunmap;
1da177e4
LT		 14155 }
14156
1da177e4
LT		 14157 /* flow control autonegotiation is default behavior */
14158 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14159 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14160
15f9850d
DM		 14161 tg3_init_coal(tp);
14162
c49a1561
MC		 14163 pci_set_drvdata(pdev, dev);
14164
1da177e4
LT		 14165 err = register_netdev(dev);
14166 if (err) {
14167 printk(KERN_ERR PFX "Cannot register net device, "
14168 "aborting.\n");
0d3031d9 14169 goto err_out_apeunmap;
1da177e4
LT		 14170 }
14171
df59c940 14172 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14173 dev->name,
14174 tp->board_part_number,
14175 tp->pci_chip_rev_id,
f9804ddb 14176 tg3_bus_string(tp, str),
e174961c 14177 dev->dev_addr);
1da177e4 14178
3f0e3ad7
MC		 14179 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14180 struct phy_device *phydev;
14181 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14182 printk(KERN_INFO
14183 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14184 tp->dev->name, phydev->drv->name,
14185 dev_name(&phydev->dev));
14186 } else
df59c940
MC		 14187 printk(KERN_INFO
14188 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14189 tp->dev->name, tg3_phy_string(tp),
14190 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14191 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14192 "10/100/1000Base-T")),
14193 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14194
14195 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14196 dev->name,
14197 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14198 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14199 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14200 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14201 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14202 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14203 dev->name, tp->dma_rwctrl,
284901a9 14204 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14205 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14206
14207 return 0;
14208
0d3031d9
MC		 14209err_out_apeunmap:
14210 if (tp->aperegs) {
14211 iounmap(tp->aperegs);
14212 tp->aperegs = NULL;
14213 }
14214
077f849d
JSR		 14215err_out_fw:
14216 if (tp->fw)
14217 release_firmware(tp->fw);
14218
1da177e4 14219err_out_iounmap:
6892914f
MC		 14220 if (tp->regs) {
14221 iounmap(tp->regs);
22abe310 14222 tp->regs = NULL;
6892914f 14223 }
1da177e4
LT		 14224
14225err_out_free_dev:
14226 free_netdev(dev);
14227
14228err_out_free_res:
14229 pci_release_regions(pdev);
14230
14231err_out_disable_pdev:
14232 pci_disable_device(pdev);
14233 pci_set_drvdata(pdev, NULL);
14234 return err;
14235}
14236
14237static void __devexit tg3_remove_one(struct pci_dev *pdev)
14238{
14239 struct net_device *dev = pci_get_drvdata(pdev);
14240
14241 if (dev) {
14242 struct tg3 *tp = netdev_priv(dev);
14243
077f849d
JSR		 14244 if (tp->fw)
14245 release_firmware(tp->fw);
14246
7faa006f 14247 flush_scheduled_work();
158d7abd 14248
b02fd9e3
MC		 14249 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14250 tg3_phy_fini(tp);
158d7abd 14251 tg3_mdio_fini(tp);
b02fd9e3 14252 }
158d7abd 14253
1da177e4 14254 unregister_netdev(dev);
0d3031d9
MC		 14255 if (tp->aperegs) {
14256 iounmap(tp->aperegs);
14257 tp->aperegs = NULL;
14258 }
6892914f
MC		 14259 if (tp->regs) {
14260 iounmap(tp->regs);
22abe310 14261 tp->regs = NULL;
6892914f 14262 }
1da177e4
LT		 14263 free_netdev(dev);
14264 pci_release_regions(pdev);
14265 pci_disable_device(pdev);
14266 pci_set_drvdata(pdev, NULL);
14267 }
14268}
14269
14270static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14271{
14272 struct net_device *dev = pci_get_drvdata(pdev);
14273 struct tg3 *tp = netdev_priv(dev);
12dac075 14274 pci_power_t target_state;
1da177e4
LT		 14275 int err;
14276
3e0c95fd
MC		 14277 /* PCI register 4 needs to be saved whether netif_running() or not.
14278 * MSI address and data need to be saved if using MSI and
14279 * netif_running().
14280 */
14281 pci_save_state(pdev);
14282
1da177e4
LT		 14283 if (!netif_running(dev))
14284 return 0;
14285
7faa006f 14286 flush_scheduled_work();
b02fd9e3 14287 tg3_phy_stop(tp);
1da177e4
LT		 14288 tg3_netif_stop(tp);
14289
14290 del_timer_sync(&tp->timer);
14291
f47c11ee 14292 tg3_full_lock(tp, 1);
1da177e4 14293 tg3_disable_ints(tp);
f47c11ee 14294 tg3_full_unlock(tp);
1da177e4
LT		 14295
14296 netif_device_detach(dev);
14297
f47c11ee 14298 tg3_full_lock(tp, 0);
944d980e 14299 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14300 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14301 tg3_full_unlock(tp);
1da177e4 14302
12dac075
RW		 14303 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14304
14305 err = tg3_set_power_state(tp, target_state);
1da177e4 14306 if (err) {
b02fd9e3
MC		 14307 int err2;
14308
f47c11ee 14309 tg3_full_lock(tp, 0);
1da177e4 14310
6a9eba15 14311 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14312 err2 = tg3_restart_hw(tp, 1);
14313 if (err2)
b9ec6c1b 14314 goto out;
1da177e4
LT		 14315
14316 tp->timer.expires = jiffies + tp->timer_offset;
14317 add_timer(&tp->timer);
14318
14319 netif_device_attach(dev);
14320 tg3_netif_start(tp);
14321
b9ec6c1b 14322out:
f47c11ee 14323 tg3_full_unlock(tp);
b02fd9e3
MC		 14324
14325 if (!err2)
14326 tg3_phy_start(tp);
1da177e4
LT		 14327 }
14328
14329 return err;
14330}
14331
14332static int tg3_resume(struct pci_dev *pdev)
14333{
14334 struct net_device *dev = pci_get_drvdata(pdev);
14335 struct tg3 *tp = netdev_priv(dev);
14336 int err;
14337
3e0c95fd
MC		 14338 pci_restore_state(tp->pdev);
14339
1da177e4
LT		 14340 if (!netif_running(dev))
14341 return 0;
14342
bc1c7567 14343 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14344 if (err)
14345 return err;
14346
14347 netif_device_attach(dev);
14348
f47c11ee 14349 tg3_full_lock(tp, 0);
1da177e4 14350
6a9eba15 14351 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14352 err = tg3_restart_hw(tp, 1);
14353 if (err)
14354 goto out;
1da177e4
LT		 14355
14356 tp->timer.expires = jiffies + tp->timer_offset;
14357 add_timer(&tp->timer);
14358
1da177e4
LT		 14359 tg3_netif_start(tp);
14360
b9ec6c1b 14361out:
f47c11ee 14362 tg3_full_unlock(tp);
1da177e4 14363
b02fd9e3
MC		 14364 if (!err)
14365 tg3_phy_start(tp);
14366
b9ec6c1b 14367 return err;
1da177e4
LT		 14368}
14369
14370static struct pci_driver tg3_driver = {
14371 .name = DRV_MODULE_NAME,
14372 .id_table = tg3_pci_tbl,
14373 .probe = tg3_init_one,
14374 .remove = __devexit_p(tg3_remove_one),
14375 .suspend = tg3_suspend,
14376 .resume = tg3_resume
14377};
14378
14379static int __init tg3_init(void)
14380{
29917620 14381 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14382}
14383
14384static void __exit tg3_cleanup(void)
14385{
14386 pci_unregister_driver(&tg3_driver);
14387}
14388
14389module_init(tg3_init);
14390module_exit(tg3_cleanup);
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