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tg3: Allow screaming interrupt detection
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
0d2a5068
MC		 71#define DRV_MODULE_VERSION "3.98"
72#define DRV_MODULE_RELDATE "February 25, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
0f893dc6 95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131/* minimum number of free TX descriptors required to wake up TX process */
42952231 132#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 133
ad829268
MC		 134#define TG3_RAW_IP_ALIGN 2
135
1da177e4
LT		 136/* number of ETHTOOL_GSTATS u64's */
137#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
4cafd3f5
MC		 139#define TG3_NUM_TEST 6
140
077f849d
JSR		 141#define FIRMWARE_TG3 "tigon/tg3.bin"
142#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
1da177e4
LT		 145static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150MODULE_LICENSE("GPL");
151MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 152MODULE_FIRMWARE(FIRMWARE_TG3);
153MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
1da177e4
LT		 156
157static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158module_param(tg3_debug, int, 0);
159MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
57e6983c 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
321d32a0
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
13185217
HK		 227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
1da177e4
LT		 235};
236
237MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
50da859d 239static const struct {
1da177e4
LT		 240 const char string[ETH_GSTRING_LEN];
241} ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318};
319
50da859d 320static const struct {
4cafd3f5
MC		 321 const char string[ETH_GSTRING_LEN];
322} ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329};
330
b401e9e2
MC		 331static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332{
333 writel(val, tp->regs + off);
334}
335
336static u32 tg3_read32(struct tg3 *tp, u32 off)
337{
6aa20a22 338 return (readl(tp->regs + off));
b401e9e2
MC		 339}
340
0d3031d9
MC		 341static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342{
343 writel(val, tp->aperegs + off);
344}
345
346static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347{
348 return (readl(tp->aperegs + off));
349}
350
1da177e4
LT		 351static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352{
6892914f
MC		 353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 359}
360
361static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
1da177e4
LT		 365}
366
6892914f 367static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 368{
6892914f
MC		 369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377}
378
379static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380{
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
1da177e4 392 }
6892914f
MC		 393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407}
408
409static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410{
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419}
420
b401e9e2
MC		 421/* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 427{
b401e9e2
MC		 428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
1da177e4
LT		 444}
445
09ee929c
MC		 446static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447{
448 tp->write32_mbox(tp, off, val);
6892914f
MC		 449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
09ee929c
MC		 452}
453
20094930 454static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 455{
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462}
463
b5d3772c
MC		 464static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465{
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467}
468
469static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470{
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472}
473
20094930 474#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 475#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 476#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 478#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 479
480#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 481#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 483#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 484
485static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486{
6892914f
MC		 487 unsigned long flags;
488
b5d3772c
MC		 489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
6892914f 493 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 497
bbadf503
MC		 498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 503
bbadf503
MC		 504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 508}
509
1da177e4
LT		 510static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511{
6892914f
MC		 512 unsigned long flags;
513
b5d3772c
MC		 514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
6892914f 520 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 524
bbadf503
MC		 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
6892914f 534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 535}
536
0d3031d9
MC		 537static void tg3_ape_lock_init(struct tg3 *tp)
538{
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545}
546
547static int tg3_ape_lock(struct tg3 *tp, int locknum)
548{
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
77b483f1 557 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585}
586
587static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588{
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
77b483f1 595 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604}
605
1da177e4
LT		 606static void tg3_disable_ints(struct tg3 *tp)
607{
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 611}
612
613static inline void tg3_cond_int(struct tg3 *tp)
614{
38f3843e
MC		 615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 621}
622
623static void tg3_enable_ints(struct tg3 *tp)
624{
bbe832c0
MC		 625 tp->irq_sync = 0;
626 wmb();
627
1da177e4
LT		 628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
fcfa0a32
MC		 632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
1da177e4
LT		 635 tg3_cond_int(tp);
636}
637
04237ddd
MC		 638static inline unsigned int tg3_has_work(struct tg3 *tp)
639{
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656}
657
1da177e4 658/* tg3_restart_ints
04237ddd
MC		 659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
6aa20a22 661 * which reenables interrupts
1da177e4
LT		 662 */
663static void tg3_restart_ints(struct tg3 *tp)
664{
fac9b83e
DM		 665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
1da177e4
LT		 667 mmiowb();
668
fac9b83e
DM		 669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
04237ddd
MC		 675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 677}
678
679static inline void tg3_netif_stop(struct tg3 *tp)
680{
bbe832c0 681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 682 napi_disable(&tp->napi);
1da177e4
LT		 683 netif_tx_disable(tp->dev);
684}
685
686static inline void tg3_netif_start(struct tg3 *tp)
687{
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
bea3348e 693 napi_enable(&tp->napi);
f47c11ee
DM		 694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
1da177e4
LT		 696}
697
698static void tg3_switch_clocks(struct tg3 *tp)
699{
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
795d01c5
MC		 703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 705 return;
706
1da177e4
LT		 707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
1da177e4 726 }
b401e9e2 727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 728}
729
730#define PHY_BUSY_LOOPS 5000
731
732static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733{
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 751
1da177e4
LT		 752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779}
780
781static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782{
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
b5d3772c
MC		 787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
1da177e4
LT		 791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 803
1da177e4
LT		 804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828}
829
95e2869a
MC		 830static int tg3_bmcr_reset(struct tg3 *tp)
831{
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
d4675b52 855 if (limit < 0)
95e2869a
MC		 856 return -EBUSY;
857
858 return 0;
859}
860
158d7abd
MC		 861static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862{
3d16543d 863 struct tg3 *tp = bp->priv;
158d7abd
MC		 864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873}
874
875static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876{
3d16543d 877 struct tg3 *tp = bp->priv;
158d7abd
MC		 878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886}
887
888static int tg3_mdio_reset(struct mii_bus *bp)
889{
890 return 0;
891}
892
9c61d6bc 893static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 894{
895 u32 val;
fcb389df 896 struct phy_device *phydev;
a9daf367 897
fcb389df
MC		 898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
a9daf367 913 return;
fcb389df
MC		 914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
a9daf367
MC		 935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
a9daf367
MC		 946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
fcb389df 954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966}
967
158d7abd
MC		 968static void tg3_mdio_start(struct tg3 *tp)
969{
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 971 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 973 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
a9daf367 979
9c61d6bc
MC		 980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
158d7abd
MC		 983}
984
985static void tg3_mdio_stop(struct tg3 *tp)
986{
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 988 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 990 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 991 }
992}
993
994static int tg3_mdio_init(struct tg3 *tp)
995{
996 int i;
997 u32 reg;
a9daf367 998 struct phy_device *phydev;
158d7abd
MC		 999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
298cf9be
LB		 1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
158d7abd 1009
298cf9be
LB		 1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1022 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
298cf9be 1032 i = mdiobus_register(tp->mdio_bus);
a9daf367 1033 if (i) {
158d7abd
MC		 1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
9c61d6bc 1036 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1037 return i;
1038 }
158d7abd 1039
298cf9be 1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1041
9c61d6bc
MC		 1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
a9daf367 1053 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1063 break;
fcb389df 1064 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
9c61d6bc
MC		 1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
a9daf367
MC		 1074
1075 return 0;
158d7abd
MC		 1076}
1077
1078static void tg3_mdio_fini(struct tg3 *tp)
1079{
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086}
1087
4ba526ce
MC		 1088/* tp->lock is held. */
1089static inline void tg3_generate_fw_event(struct tg3 *tp)
1090{
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098}
1099
1100#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
95e2869a
MC		 1102/* tp->lock is held. */
1103static void tg3_wait_for_event_ack(struct tg3 *tp)
1104{
1105 int i;
4ba526ce
MC		 1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1121
4ba526ce 1122 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
4ba526ce 1125 udelay(8);
95e2869a
MC		 1126 }
1127}
1128
1129/* tp->lock is held. */
1130static void tg3_ump_link_report(struct tg3 *tp)
1131{
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
4ba526ce 1174 tg3_generate_fw_event(tp);
95e2869a
MC		 1175}
1176
1177static void tg3_link_report(struct tg3 *tp)
1178{
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
e18ce346 1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1198 "on" : "off",
e18ce346 1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203}
1204
1205static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206{
1207 u16 miireg;
1208
e18ce346 1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1210 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1211 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1212 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1213 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219}
1220
1221static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
95e2869a
MC		 1237static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238{
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1246 cap = FLOW_CTRL_RX;
95e2869a
MC		 1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1253 cap = FLOW_CTRL_TX;
95e2869a
MC		 1254 }
1255
1256 return cap;
1257}
1258
f51f3562 1259static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1260{
b02fd9e3 1261 u8 autoneg;
f51f3562 1262 u8 flowctrl = 0;
95e2869a
MC		 1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
b02fd9e3 1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1275 else
bc02ff95 1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1277 } else
1278 flowctrl = tp->link_config.flowctrl;
95e2869a 1279
f51f3562 1280 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1281
e18ce346 1282 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
f51f3562 1287 if (old_rx_mode != tp->rx_mode)
95e2869a 1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1289
e18ce346 1290 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
f51f3562 1295 if (old_tx_mode != tp->tx_mode)
95e2869a 1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1297}
1298
b02fd9e3
MC		 1299static void tg3_adjust_link(struct net_device *dev)
1300{
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
298cf9be 1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
fcb389df
MC		 1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
b02fd9e3
MC		 1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378}
1379
1380static int tg3_phy_init(struct tg3 *tp)
1381{
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
298cf9be 1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1391
1392 /* Attach the MAC to the PHY. */
fb28ad35 1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1394 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
b02fd9e3 1400 /* Mask with MAC supported features. */
9c61d6bc
MC		 1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
9c61d6bc
MC		 1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1422
1423 phydev->advertising = phydev->supported;
1424
b02fd9e3
MC		 1425 return 0;
1426}
1427
1428static void tg3_phy_start(struct tg3 *tp)
1429{
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
298cf9be 1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448}
1449
1450static void tg3_phy_stop(struct tg3 *tp)
1451{
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
298cf9be 1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1456}
1457
1458static void tg3_phy_fini(struct tg3 *tp)
1459{
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464}
1465
b2a5c19c
MC		 1466static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467{
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470}
1471
6833c043
MC		 1472static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473{
1474 u32 reg;
1475
a6435f3a
MC		 1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6833c043
MC		 1478 return;
1479
1480 reg = MII_TG3_MISC_SHDW_WREN |
1481 MII_TG3_MISC_SHDW_SCR5_SEL |
1482 MII_TG3_MISC_SHDW_SCR5_LPED |
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484 MII_TG3_MISC_SHDW_SCR5_SDTL |
1485 MII_TG3_MISC_SHDW_SCR5_C125OE;
1486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492 reg = MII_TG3_MISC_SHDW_WREN |
1493 MII_TG3_MISC_SHDW_APD_SEL |
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495 if (enable)
1496 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499}
1500
9ef8ca99
MC		 1501static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502{
1503 u32 phy;
1504
1505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507 return;
1508
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510 u32 ephy;
1511
1512 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514 ephy | MII_TG3_EPHY_SHADOW_EN);
1515 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516 if (enable)
1517 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518 else
1519 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521 }
1522 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523 }
1524 } else {
1525 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526 MII_TG3_AUXCTL_SHDWSEL_MISC;
1527 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531 else
1532 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533 phy |= MII_TG3_AUXCTL_MISC_WREN;
1534 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535 }
1536 }
1537}
1538
1da177e4
LT		 1539static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540{
1541 u32 val;
1542
1543 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544 return;
1545
1546 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549 (val | (1 << 15) | (1 << 4)));
1550}
1551
b2a5c19c
MC		 1552static void tg3_phy_apply_otp(struct tg3 *tp)
1553{
1554 u32 otp, phy;
1555
1556 if (!tp->phy_otp)
1557 return;
1558
1559 otp = tp->phy_otp;
1560
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564 MII_TG3_AUXCTL_ACTL_TX_6DB;
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589 /* Turn off SM_DSP clock. */
1590 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591 MII_TG3_AUXCTL_ACTL_TX_6DB;
1592 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593}
1594
1da177e4
LT		 1595static int tg3_wait_macro_done(struct tg3 *tp)
1596{
1597 int limit = 100;
1598
1599 while (limit--) {
1600 u32 tmp32;
1601
1602 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603 if ((tmp32 & 0x1000) == 0)
1604 break;
1605 }
1606 }
d4675b52 1607 if (limit < 0)
1da177e4
LT		 1608 return -EBUSY;
1609
1610 return 0;
1611}
1612
1613static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614{
1615 static const u32 test_pat[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620 };
1621 int chan;
1622
1623 for (chan = 0; chan < 4; chan++) {
1624 int i;
1625
1626 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627 (chan * 0x2000) | 0x0200);
1628 tg3_writephy(tp, 0x16, 0x0002);
1629
1630 for (i = 0; i < 6; i++)
1631 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632 test_pat[chan][i]);
1633
1634 tg3_writephy(tp, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641 (chan * 0x2000) | 0x0200);
1642 tg3_writephy(tp, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp)) {
1644 *resetp = 1;
1645 return -EBUSY;
1646 }
1647
1648 tg3_writephy(tp, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp)) {
1650 *resetp = 1;
1651 return -EBUSY;
1652 }
1653
1654 for (i = 0; i < 6; i += 2) {
1655 u32 low, high;
1656
1657 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659 tg3_wait_macro_done(tp)) {
1660 *resetp = 1;
1661 return -EBUSY;
1662 }
1663 low &= 0x7fff;
1664 high &= 0x000f;
1665 if (low != test_pat[chan][i] ||
1666 high != test_pat[chan][i+1]) {
1667 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671 return -EBUSY;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677}
1678
1679static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680{
1681 int chan;
1682
1683 for (chan = 0; chan < 4; chan++) {
1684 int i;
1685
1686 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687 (chan * 0x2000) | 0x0200);
1688 tg3_writephy(tp, 0x16, 0x0002);
1689 for (i = 0; i < 6; i++)
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691 tg3_writephy(tp, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp))
1693 return -EBUSY;
1694 }
1695
1696 return 0;
1697}
1698
1699static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700{
1701 u32 reg32, phy9_orig;
1702 int retries, do_phy_reset, err;
1703
1704 retries = 10;
1705 do_phy_reset = 1;
1706 do {
1707 if (do_phy_reset) {
1708 err = tg3_bmcr_reset(tp);
1709 if (err)
1710 return err;
1711 do_phy_reset = 0;
1712 }
1713
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716 continue;
1717
1718 reg32 |= 0x3000;
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp, MII_BMCR,
1723 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727 continue;
1728
1729 tg3_writephy(tp, MII_TG3_CTRL,
1730 (MII_TG3_CTRL_AS_MASTER |
1731 MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741 if (!err)
1742 break;
1743 } while (--retries);
1744
1745 err = tg3_phy_reset_chanpat(tp);
1746 if (err)
1747 return err;
1748
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753 tg3_writephy(tp, 0x16, 0x0000);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759 }
1760 else {
1761 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762 }
1763
1764 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767 reg32 &= ~0x3000;
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769 } else if (!err)
1770 err = -EBUSY;
1771
1772 return err;
1773}
1774
1775/* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1777 */
1778static int tg3_phy_reset(struct tg3 *tp)
1779{
b2a5c19c 1780 u32 cpmuctrl;
1da177e4
LT		 1781 u32 phy_status;
1782 int err;
1783
60189ddf
MC		 1784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785 u32 val;
1786
1787 val = tr32(GRC_MISC_CFG);
1788 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789 udelay(40);
1790 }
1da177e4
LT		 1791 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1792 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793 if (err != 0)
1794 return -EBUSY;
1795
c8e1e82b
MC		 1796 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797 netif_carrier_off(tp->dev);
1798 tg3_link_report(tp);
1799 }
1800
1da177e4
LT		 1801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804 err = tg3_phy_reset_5703_4_5(tp);
1805 if (err)
1806 return err;
1807 goto out;
1808 }
1809
b2a5c19c
MC		 1810 cpmuctrl = 0;
1811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815 tw32(TG3_CPMU_CTRL,
1816 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817 }
1818
1da177e4
LT		 1819 err = tg3_bmcr_reset(tp);
1820 if (err)
1821 return err;
1822
b2a5c19c
MC		 1823 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824 u32 phy;
1825
1826 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830 }
1831
bcb37f6c
MC		 1832 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1834 u32 val;
1835
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5) {
1839 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840 udelay(40);
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842 }
1843 }
1844
b2a5c19c
MC		 1845 tg3_phy_apply_otp(tp);
1846
6833c043
MC		 1847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848 tg3_phy_toggle_apd(tp, true);
1849 else
1850 tg3_phy_toggle_apd(tp, false);
1851
1da177e4
LT		 1852out:
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860 }
1861 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 tg3_writephy(tp, 0x1c, 0x8d68);
1864 }
1865 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874 }
c424cb24
MC		 1875 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1878 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880 tg3_writephy(tp, MII_TG3_TEST1,
1881 MII_TG3_TEST1_TRIM_EN | 0x4);
1882 } else
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1884 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885 }
1da177e4
LT		 1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1891 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1892 u32 phy_reg;
1893
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898 }
1899
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1902 */
0f893dc6 1903 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1904 u32 phy_reg;
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909 }
1910
715116a1 1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1912 /* adjust output voltage */
1913 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1914 }
1915
9ef8ca99 1916 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1917 tg3_phy_set_wirespeed(tp);
1918 return 0;
1919}
1920
1921static void tg3_frob_aux_power(struct tg3 *tp)
1922{
1923 struct tg3 *tp_peer = tp;
1924
9d26e213 1925 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1926 return;
1927
8c2dc7e1
MC		 1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930 struct net_device *dev_peer;
1931
1932 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1933 /* remove_one() may have been run on the peer. */
8c2dc7e1 1934 if (!dev_peer)
bc1c7567
MC		 1935 tp_peer = tp;
1936 else
1937 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1938 }
1939
1da177e4 1940 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1941 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1946 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947 (GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1),
1952 100);
5f0c4a3c
MC		 1953 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1954 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1956 GRC_LCLCTRL_GPIO_OE1 |
1957 GRC_LCLCTRL_GPIO_OE2 |
1958 GRC_LCLCTRL_GPIO_OUTPUT0 |
1959 GRC_LCLCTRL_GPIO_OUTPUT1 |
1960 tp->grc_local_ctrl;
1961 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1962
1963 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1964 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1965
1966 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1967 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 1968 } else {
1969 u32 no_gpio2;
dc56b7d4 1970 u32 grc_local_ctrl = 0;
1da177e4
LT		 1971
1972 if (tp_peer != tp &&
1973 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1974 return;
1975
dc56b7d4
MC		 1976 /* Workaround to prevent overdrawing Amps. */
1977 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1978 ASIC_REV_5714) {
1979 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1980 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1981 grc_local_ctrl, 100);
dc56b7d4
MC		 1982 }
1983
1da177e4
LT		 1984 /* On 5753 and variants, GPIO2 cannot be used. */
1985 no_gpio2 = tp->nic_sram_data_cfg &
1986 NIC_SRAM_DATA_CFG_NO_GPIO2;
1987
dc56b7d4 1988 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1989 GRC_LCLCTRL_GPIO_OE1 |
1990 GRC_LCLCTRL_GPIO_OE2 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1 |
1992 GRC_LCLCTRL_GPIO_OUTPUT2;
1993 if (no_gpio2) {
1994 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1995 GRC_LCLCTRL_GPIO_OUTPUT2);
1996 }
b401e9e2
MC		 1997 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1998 grc_local_ctrl, 100);
1da177e4
LT		 1999
2000 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2001
b401e9e2
MC		 2002 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2003 grc_local_ctrl, 100);
1da177e4
LT		 2004
2005 if (!no_gpio2) {
2006 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2007 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2008 grc_local_ctrl, 100);
1da177e4
LT		 2009 }
2010 }
2011 } else {
2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2013 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2014 if (tp_peer != tp &&
2015 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2016 return;
2017
b401e9e2
MC		 2018 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019 (GRC_LCLCTRL_GPIO_OE1 |
2020 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2021
b401e9e2
MC		 2022 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2023 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2024
b401e9e2
MC		 2025 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026 (GRC_LCLCTRL_GPIO_OE1 |
2027 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2028 }
2029 }
2030}
2031
e8f3f6ca
MC		 2032static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2033{
2034 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2035 return 1;
2036 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2037 if (speed != SPEED_10)
2038 return 1;
2039 } else if (speed == SPEED_10)
2040 return 1;
2041
2042 return 0;
2043}
2044
1da177e4
LT		 2045static int tg3_setup_phy(struct tg3 *, int);
2046
2047#define RESET_KIND_SHUTDOWN 0
2048#define RESET_KIND_INIT 1
2049#define RESET_KIND_SUSPEND 2
2050
2051static void tg3_write_sig_post_reset(struct tg3 *, int);
2052static int tg3_halt_cpu(struct tg3 *, u32);
2053
0a459aac 2054static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2055{
ce057f01
MC		 2056 u32 val;
2057
5129724a
MC		 2058 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2060 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2061 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2062
2063 sg_dig_ctrl |=
2064 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2065 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2066 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2067 }
3f7045c1 2068 return;
5129724a 2069 }
3f7045c1 2070
60189ddf 2071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2072 tg3_bmcr_reset(tp);
2073 val = tr32(GRC_MISC_CFG);
2074 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2075 udelay(40);
2076 return;
0a459aac 2077 } else if (do_low_power) {
715116a1
MC		 2078 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2079 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2080
2081 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2082 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2083 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2084 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2085 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2086 }
3f7045c1 2087
15c3b696
MC		 2088 /* The PHY should not be powered down on some chips because
2089 * of bugs.
2090 */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2093 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2094 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2095 return;
ce057f01 2096
bcb37f6c
MC		 2097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2098 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2099 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2100 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2101 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2102 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2103 }
2104
15c3b696
MC		 2105 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2106}
2107
ffbcfed4
MC		 2108/* tp->lock is held. */
2109static int tg3_nvram_lock(struct tg3 *tp)
2110{
2111 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2112 int i;
2113
2114 if (tp->nvram_lock_cnt == 0) {
2115 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2116 for (i = 0; i < 8000; i++) {
2117 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2118 break;
2119 udelay(20);
2120 }
2121 if (i == 8000) {
2122 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2123 return -ENODEV;
2124 }
2125 }
2126 tp->nvram_lock_cnt++;
2127 }
2128 return 0;
2129}
2130
2131/* tp->lock is held. */
2132static void tg3_nvram_unlock(struct tg3 *tp)
2133{
2134 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2135 if (tp->nvram_lock_cnt > 0)
2136 tp->nvram_lock_cnt--;
2137 if (tp->nvram_lock_cnt == 0)
2138 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2139 }
2140}
2141
2142/* tp->lock is held. */
2143static void tg3_enable_nvram_access(struct tg3 *tp)
2144{
2145 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2146 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2147 u32 nvaccess = tr32(NVRAM_ACCESS);
2148
2149 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2150 }
2151}
2152
2153/* tp->lock is held. */
2154static void tg3_disable_nvram_access(struct tg3 *tp)
2155{
2156 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2157 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2158 u32 nvaccess = tr32(NVRAM_ACCESS);
2159
2160 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2161 }
2162}
2163
2164static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2165 u32 offset, u32 *val)
2166{
2167 u32 tmp;
2168 int i;
2169
2170 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2171 return -EINVAL;
2172
2173 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2174 EEPROM_ADDR_DEVID_MASK |
2175 EEPROM_ADDR_READ);
2176 tw32(GRC_EEPROM_ADDR,
2177 tmp |
2178 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2179 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2180 EEPROM_ADDR_ADDR_MASK) |
2181 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2182
2183 for (i = 0; i < 1000; i++) {
2184 tmp = tr32(GRC_EEPROM_ADDR);
2185
2186 if (tmp & EEPROM_ADDR_COMPLETE)
2187 break;
2188 msleep(1);
2189 }
2190 if (!(tmp & EEPROM_ADDR_COMPLETE))
2191 return -EBUSY;
2192
62cedd11
MC		 2193 tmp = tr32(GRC_EEPROM_DATA);
2194
2195 /*
2196 * The data will always be opposite the native endian
2197 * format. Perform a blind byteswap to compensate.
2198 */
2199 *val = swab32(tmp);
2200
ffbcfed4
MC		 2201 return 0;
2202}
2203
2204#define NVRAM_CMD_TIMEOUT 10000
2205
2206static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2207{
2208 int i;
2209
2210 tw32(NVRAM_CMD, nvram_cmd);
2211 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2212 udelay(10);
2213 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2214 udelay(10);
2215 break;
2216 }
2217 }
2218
2219 if (i == NVRAM_CMD_TIMEOUT)
2220 return -EBUSY;
2221
2222 return 0;
2223}
2224
2225static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2226{
2227 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2228 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2229 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2230 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2231 (tp->nvram_jedecnum == JEDEC_ATMEL))
2232
2233 addr = ((addr / tp->nvram_pagesize) <<
2234 ATMEL_AT45DB0X1B_PAGE_POS) +
2235 (addr % tp->nvram_pagesize);
2236
2237 return addr;
2238}
2239
2240static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2241{
2242 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2243 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2244 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2245 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2246 (tp->nvram_jedecnum == JEDEC_ATMEL))
2247
2248 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2249 tp->nvram_pagesize) +
2250 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2251
2252 return addr;
2253}
2254
e4f34110
MC		 2255/* NOTE: Data read in from NVRAM is byteswapped according to
2256 * the byteswapping settings for all other register accesses.
2257 * tg3 devices are BE devices, so on a BE machine, the data
2258 * returned will be exactly as it is seen in NVRAM. On a LE
2259 * machine, the 32-bit value will be byteswapped.
2260 */
ffbcfed4
MC		 2261static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2262{
2263 int ret;
2264
2265 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2266 return tg3_nvram_read_using_eeprom(tp, offset, val);
2267
2268 offset = tg3_nvram_phys_addr(tp, offset);
2269
2270 if (offset > NVRAM_ADDR_MSK)
2271 return -EINVAL;
2272
2273 ret = tg3_nvram_lock(tp);
2274 if (ret)
2275 return ret;
2276
2277 tg3_enable_nvram_access(tp);
2278
2279 tw32(NVRAM_ADDR, offset);
2280 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2281 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2282
2283 if (ret == 0)
e4f34110 2284 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2285
2286 tg3_disable_nvram_access(tp);
2287
2288 tg3_nvram_unlock(tp);
2289
2290 return ret;
2291}
2292
a9dc529d
MC		 2293/* Ensures NVRAM data is in bytestream format. */
2294static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2295{
2296 u32 v;
a9dc529d 2297 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2298 if (!res)
a9dc529d 2299 *val = cpu_to_be32(v);
ffbcfed4
MC		 2300 return res;
2301}
2302
3f007891
MC		 2303/* tp->lock is held. */
2304static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2305{
2306 u32 addr_high, addr_low;
2307 int i;
2308
2309 addr_high = ((tp->dev->dev_addr[0] << 8) |
2310 tp->dev->dev_addr[1]);
2311 addr_low = ((tp->dev->dev_addr[2] << 24) |
2312 (tp->dev->dev_addr[3] << 16) |
2313 (tp->dev->dev_addr[4] << 8) |
2314 (tp->dev->dev_addr[5] << 0));
2315 for (i = 0; i < 4; i++) {
2316 if (i == 1 && skip_mac_1)
2317 continue;
2318 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2319 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2320 }
2321
2322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2323 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2324 for (i = 0; i < 12; i++) {
2325 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2326 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2327 }
2328 }
2329
2330 addr_high = (tp->dev->dev_addr[0] +
2331 tp->dev->dev_addr[1] +
2332 tp->dev->dev_addr[2] +
2333 tp->dev->dev_addr[3] +
2334 tp->dev->dev_addr[4] +
2335 tp->dev->dev_addr[5]) &
2336 TX_BACKOFF_SEED_MASK;
2337 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2338}
2339
bc1c7567 2340static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2341{
2342 u32 misc_host_ctrl;
0a459aac 2343 bool device_should_wake, do_low_power;
1da177e4
LT		 2344
2345 /* Make sure register accesses (indirect or otherwise)
2346 * will function correctly.
2347 */
2348 pci_write_config_dword(tp->pdev,
2349 TG3PCI_MISC_HOST_CTRL,
2350 tp->misc_host_ctrl);
2351
1da177e4 2352 switch (state) {
bc1c7567 2353 case PCI_D0:
12dac075
RW		 2354 pci_enable_wake(tp->pdev, state, false);
2355 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2356
9d26e213
MC		 2357 /* Switch out of Vaux if it is a NIC */
2358 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2359 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2360
2361 return 0;
2362
bc1c7567 2363 case PCI_D1:
bc1c7567 2364 case PCI_D2:
bc1c7567 2365 case PCI_D3hot:
1da177e4
LT		 2366 break;
2367
2368 default:
12dac075
RW		 2369 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2370 tp->dev->name, state);
1da177e4 2371 return -EINVAL;
855e1111 2372 }
5e7dfd0f
MC		 2373
2374 /* Restore the CLKREQ setting. */
2375 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2376 u16 lnkctl;
2377
2378 pci_read_config_word(tp->pdev,
2379 tp->pcie_cap + PCI_EXP_LNKCTL,
2380 &lnkctl);
2381 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2382 pci_write_config_word(tp->pdev,
2383 tp->pcie_cap + PCI_EXP_LNKCTL,
2384 lnkctl);
2385 }
2386
1da177e4
LT		 2387 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2388 tw32(TG3PCI_MISC_HOST_CTRL,
2389 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2390
05ac4cb7
MC		 2391 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2392 device_may_wakeup(&tp->pdev->dev) &&
2393 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2394
dd477003 2395 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2396 do_low_power = false;
b02fd9e3
MC		 2397 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2398 !tp->link_config.phy_is_low_power) {
2399 struct phy_device *phydev;
0a459aac 2400 u32 phyid, advertising;
b02fd9e3 2401
298cf9be 2402 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2403
2404 tp->link_config.phy_is_low_power = 1;
2405
2406 tp->link_config.orig_speed = phydev->speed;
2407 tp->link_config.orig_duplex = phydev->duplex;
2408 tp->link_config.orig_autoneg = phydev->autoneg;
2409 tp->link_config.orig_advertising = phydev->advertising;
2410
2411 advertising = ADVERTISED_TP |
2412 ADVERTISED_Pause |
2413 ADVERTISED_Autoneg |
2414 ADVERTISED_10baseT_Half;
2415
2416 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2417 device_should_wake) {
b02fd9e3
MC		 2418 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2419 advertising |=
2420 ADVERTISED_100baseT_Half |
2421 ADVERTISED_100baseT_Full |
2422 ADVERTISED_10baseT_Full;
2423 else
2424 advertising |= ADVERTISED_10baseT_Full;
2425 }
2426
2427 phydev->advertising = advertising;
2428
2429 phy_start_aneg(phydev);
0a459aac
MC		 2430
2431 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2432 if (phyid != TG3_PHY_ID_BCMAC131) {
2433 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2434 if (phyid == TG3_PHY_OUI_1 ||
2435 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2436 phyid == TG3_PHY_OUI_3)
2437 do_low_power = true;
2438 }
b02fd9e3 2439 }
dd477003 2440 } else {
2023276e 2441 do_low_power = true;
0a459aac 2442
dd477003
MC		 2443 if (tp->link_config.phy_is_low_power == 0) {
2444 tp->link_config.phy_is_low_power = 1;
2445 tp->link_config.orig_speed = tp->link_config.speed;
2446 tp->link_config.orig_duplex = tp->link_config.duplex;
2447 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2448 }
1da177e4 2449
dd477003
MC		 2450 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2451 tp->link_config.speed = SPEED_10;
2452 tp->link_config.duplex = DUPLEX_HALF;
2453 tp->link_config.autoneg = AUTONEG_ENABLE;
2454 tg3_setup_phy(tp, 0);
2455 }
1da177e4
LT		 2456 }
2457
3f007891
MC		 2458 __tg3_set_mac_addr(tp, 0);
2459
b5d3772c
MC		 2460 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2461 u32 val;
2462
2463 val = tr32(GRC_VCPU_EXT_CTRL);
2464 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2465 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2466 int i;
2467 u32 val;
2468
2469 for (i = 0; i < 200; i++) {
2470 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2471 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2472 break;
2473 msleep(1);
2474 }
2475 }
a85feb8c
GZ		 2476 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2477 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2478 WOL_DRV_STATE_SHUTDOWN |
2479 WOL_DRV_WOL |
2480 WOL_SET_MAGIC_PKT);
6921d201 2481
05ac4cb7 2482 if (device_should_wake) {
1da177e4
LT		 2483 u32 mac_mode;
2484
2485 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2486 if (do_low_power) {
dd477003
MC		 2487 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2488 udelay(40);
2489 }
1da177e4 2490
3f7045c1
MC		 2491 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2492 mac_mode = MAC_MODE_PORT_MODE_GMII;
2493 else
2494 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2495
e8f3f6ca
MC		 2496 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2497 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2498 ASIC_REV_5700) {
2499 u32 speed = (tp->tg3_flags &
2500 TG3_FLAG_WOL_SPEED_100MB) ?
2501 SPEED_100 : SPEED_10;
2502 if (tg3_5700_link_polarity(tp, speed))
2503 mac_mode |= MAC_MODE_LINK_POLARITY;
2504 else
2505 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2506 }
1da177e4
LT		 2507 } else {
2508 mac_mode = MAC_MODE_PORT_MODE_TBI;
2509 }
2510
cbf46853 2511 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2512 tw32(MAC_LED_CTRL, tp->led_ctrl);
2513
05ac4cb7
MC		 2514 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2515 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2516 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2517 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2518 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2519 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2520
3bda1258
MC		 2521 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2522 mac_mode |= tp->mac_mode &
2523 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2524 if (mac_mode & MAC_MODE_APE_TX_EN)
2525 mac_mode |= MAC_MODE_TDE_ENABLE;
2526 }
2527
1da177e4
LT		 2528 tw32_f(MAC_MODE, mac_mode);
2529 udelay(100);
2530
2531 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2532 udelay(10);
2533 }
2534
2535 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2536 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2538 u32 base_val;
2539
2540 base_val = tp->pci_clock_ctrl;
2541 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2542 CLOCK_CTRL_TXCLK_DISABLE);
2543
b401e9e2
MC		 2544 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2545 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2546 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2547 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2548 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2549 /* do nothing */
85e94ced 2550 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2551 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2552 u32 newbits1, newbits2;
2553
2554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2555 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2556 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2557 CLOCK_CTRL_TXCLK_DISABLE |
2558 CLOCK_CTRL_ALTCLK);
2559 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2560 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2561 newbits1 = CLOCK_CTRL_625_CORE;
2562 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2563 } else {
2564 newbits1 = CLOCK_CTRL_ALTCLK;
2565 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2566 }
2567
b401e9e2
MC		 2568 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2569 40);
1da177e4 2570
b401e9e2
MC		 2571 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2572 40);
1da177e4
LT		 2573
2574 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2575 u32 newbits3;
2576
2577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2579 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2580 CLOCK_CTRL_TXCLK_DISABLE |
2581 CLOCK_CTRL_44MHZ_CORE);
2582 } else {
2583 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2584 }
2585
b401e9e2
MC		 2586 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2587 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2588 }
2589 }
2590
05ac4cb7 2591 if (!(device_should_wake) &&
22435849 2592 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2593 tg3_power_down_phy(tp, do_low_power);
6921d201 2594
1da177e4
LT		 2595 tg3_frob_aux_power(tp);
2596
2597 /* Workaround for unstable PLL clock */
2598 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2599 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2600 u32 val = tr32(0x7d00);
2601
2602 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2603 tw32(0x7d00, val);
6921d201 2604 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2605 int err;
2606
2607 err = tg3_nvram_lock(tp);
1da177e4 2608 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2609 if (!err)
2610 tg3_nvram_unlock(tp);
6921d201 2611 }
1da177e4
LT		 2612 }
2613
bbadf503
MC		 2614 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2615
05ac4cb7 2616 if (device_should_wake)
12dac075
RW		 2617 pci_enable_wake(tp->pdev, state, true);
2618
1da177e4 2619 /* Finally, set the new power state. */
12dac075 2620 pci_set_power_state(tp->pdev, state);
1da177e4 2621
1da177e4
LT		 2622 return 0;
2623}
2624
1da177e4
LT		 2625static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2626{
2627 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2628 case MII_TG3_AUX_STAT_10HALF:
2629 *speed = SPEED_10;
2630 *duplex = DUPLEX_HALF;
2631 break;
2632
2633 case MII_TG3_AUX_STAT_10FULL:
2634 *speed = SPEED_10;
2635 *duplex = DUPLEX_FULL;
2636 break;
2637
2638 case MII_TG3_AUX_STAT_100HALF:
2639 *speed = SPEED_100;
2640 *duplex = DUPLEX_HALF;
2641 break;
2642
2643 case MII_TG3_AUX_STAT_100FULL:
2644 *speed = SPEED_100;
2645 *duplex = DUPLEX_FULL;
2646 break;
2647
2648 case MII_TG3_AUX_STAT_1000HALF:
2649 *speed = SPEED_1000;
2650 *duplex = DUPLEX_HALF;
2651 break;
2652
2653 case MII_TG3_AUX_STAT_1000FULL:
2654 *speed = SPEED_1000;
2655 *duplex = DUPLEX_FULL;
2656 break;
2657
2658 default:
715116a1
MC		 2659 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2660 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2661 SPEED_10;
2662 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2663 DUPLEX_HALF;
2664 break;
2665 }
1da177e4
LT		 2666 *speed = SPEED_INVALID;
2667 *duplex = DUPLEX_INVALID;
2668 break;
855e1111 2669 }
1da177e4
LT		 2670}
2671
2672static void tg3_phy_copper_begin(struct tg3 *tp)
2673{
2674 u32 new_adv;
2675 int i;
2676
2677 if (tp->link_config.phy_is_low_power) {
2678 /* Entering low power mode. Disable gigabit and
2679 * 100baseT advertisements.
2680 */
2681 tg3_writephy(tp, MII_TG3_CTRL, 0);
2682
2683 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2684 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2685 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2686 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2687
2688 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2689 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2690 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2691 tp->link_config.advertising &=
2692 ~(ADVERTISED_1000baseT_Half |
2693 ADVERTISED_1000baseT_Full);
2694
ba4d07a8 2695 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2696 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2697 new_adv |= ADVERTISE_10HALF;
2698 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2699 new_adv |= ADVERTISE_10FULL;
2700 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2701 new_adv |= ADVERTISE_100HALF;
2702 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2703 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2704
2705 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2706
1da177e4
LT		 2707 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2708
2709 if (tp->link_config.advertising &
2710 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2711 new_adv = 0;
2712 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2713 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2714 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2715 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2716 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2717 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2718 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2719 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2720 MII_TG3_CTRL_ENABLE_AS_MASTER);
2721 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2722 } else {
2723 tg3_writephy(tp, MII_TG3_CTRL, 0);
2724 }
2725 } else {
ba4d07a8
MC		 2726 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2727 new_adv |= ADVERTISE_CSMA;
2728
1da177e4
LT		 2729 /* Asking for a specific link mode. */
2730 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2731 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2732
2733 if (tp->link_config.duplex == DUPLEX_FULL)
2734 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2735 else
2736 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2737 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2738 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2739 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2740 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2741 } else {
1da177e4
LT		 2742 if (tp->link_config.speed == SPEED_100) {
2743 if (tp->link_config.duplex == DUPLEX_FULL)
2744 new_adv |= ADVERTISE_100FULL;
2745 else
2746 new_adv |= ADVERTISE_100HALF;
2747 } else {
2748 if (tp->link_config.duplex == DUPLEX_FULL)
2749 new_adv |= ADVERTISE_10FULL;
2750 else
2751 new_adv |= ADVERTISE_10HALF;
2752 }
2753 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2754
2755 new_adv = 0;
1da177e4 2756 }
ba4d07a8
MC		 2757
2758 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2759 }
2760
2761 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2762 tp->link_config.speed != SPEED_INVALID) {
2763 u32 bmcr, orig_bmcr;
2764
2765 tp->link_config.active_speed = tp->link_config.speed;
2766 tp->link_config.active_duplex = tp->link_config.duplex;
2767
2768 bmcr = 0;
2769 switch (tp->link_config.speed) {
2770 default:
2771 case SPEED_10:
2772 break;
2773
2774 case SPEED_100:
2775 bmcr |= BMCR_SPEED100;
2776 break;
2777
2778 case SPEED_1000:
2779 bmcr |= TG3_BMCR_SPEED1000;
2780 break;
855e1111 2781 }
1da177e4
LT		 2782
2783 if (tp->link_config.duplex == DUPLEX_FULL)
2784 bmcr |= BMCR_FULLDPLX;
2785
2786 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2787 (bmcr != orig_bmcr)) {
2788 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2789 for (i = 0; i < 1500; i++) {
2790 u32 tmp;
2791
2792 udelay(10);
2793 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2794 tg3_readphy(tp, MII_BMSR, &tmp))
2795 continue;
2796 if (!(tmp & BMSR_LSTATUS)) {
2797 udelay(40);
2798 break;
2799 }
2800 }
2801 tg3_writephy(tp, MII_BMCR, bmcr);
2802 udelay(40);
2803 }
2804 } else {
2805 tg3_writephy(tp, MII_BMCR,
2806 BMCR_ANENABLE | BMCR_ANRESTART);
2807 }
2808}
2809
2810static int tg3_init_5401phy_dsp(struct tg3 *tp)
2811{
2812 int err;
2813
2814 /* Turn off tap power management. */
2815 /* Set Extended packet length bit */
2816 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2817
2818 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2819 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2820
2821 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2822 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2823
2824 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2825 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2826
2827 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2828 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2829
2830 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2831 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2832
2833 udelay(40);
2834
2835 return err;
2836}
2837
3600d918 2838static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2839{
3600d918
MC		 2840 u32 adv_reg, all_mask = 0;
2841
2842 if (mask & ADVERTISED_10baseT_Half)
2843 all_mask |= ADVERTISE_10HALF;
2844 if (mask & ADVERTISED_10baseT_Full)
2845 all_mask |= ADVERTISE_10FULL;
2846 if (mask & ADVERTISED_100baseT_Half)
2847 all_mask |= ADVERTISE_100HALF;
2848 if (mask & ADVERTISED_100baseT_Full)
2849 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2850
2851 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2852 return 0;
2853
1da177e4
LT		 2854 if ((adv_reg & all_mask) != all_mask)
2855 return 0;
2856 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2857 u32 tg3_ctrl;
2858
3600d918
MC		 2859 all_mask = 0;
2860 if (mask & ADVERTISED_1000baseT_Half)
2861 all_mask |= ADVERTISE_1000HALF;
2862 if (mask & ADVERTISED_1000baseT_Full)
2863 all_mask |= ADVERTISE_1000FULL;
2864
1da177e4
LT		 2865 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2866 return 0;
2867
1da177e4
LT		 2868 if ((tg3_ctrl & all_mask) != all_mask)
2869 return 0;
2870 }
2871 return 1;
2872}
2873
ef167e27
MC		 2874static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2875{
2876 u32 curadv, reqadv;
2877
2878 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2879 return 1;
2880
2881 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2882 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2883
2884 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2885 if (curadv != reqadv)
2886 return 0;
2887
2888 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2889 tg3_readphy(tp, MII_LPA, rmtadv);
2890 } else {
2891 /* Reprogram the advertisement register, even if it
2892 * does not affect the current link. If the link
2893 * gets renegotiated in the future, we can save an
2894 * additional renegotiation cycle by advertising
2895 * it correctly in the first place.
2896 */
2897 if (curadv != reqadv) {
2898 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2899 ADVERTISE_PAUSE_ASYM);
2900 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2901 }
2902 }
2903
2904 return 1;
2905}
2906
1da177e4
LT		 2907static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2908{
2909 int current_link_up;
2910 u32 bmsr, dummy;
ef167e27 2911 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2912 u16 current_speed;
2913 u8 current_duplex;
2914 int i, err;
2915
2916 tw32(MAC_EVENT, 0);
2917
2918 tw32_f(MAC_STATUS,
2919 (MAC_STATUS_SYNC_CHANGED |
2920 MAC_STATUS_CFG_CHANGED |
2921 MAC_STATUS_MI_COMPLETION |
2922 MAC_STATUS_LNKSTATE_CHANGED));
2923 udelay(40);
2924
8ef21428
MC		 2925 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2926 tw32_f(MAC_MI_MODE,
2927 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2928 udelay(80);
2929 }
1da177e4
LT		 2930
2931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2932
2933 /* Some third-party PHYs need to be reset on link going
2934 * down.
2935 */
2936 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2939 netif_carrier_ok(tp->dev)) {
2940 tg3_readphy(tp, MII_BMSR, &bmsr);
2941 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2942 !(bmsr & BMSR_LSTATUS))
2943 force_reset = 1;
2944 }
2945 if (force_reset)
2946 tg3_phy_reset(tp);
2947
2948 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2949 tg3_readphy(tp, MII_BMSR, &bmsr);
2950 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2951 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2952 bmsr = 0;
2953
2954 if (!(bmsr & BMSR_LSTATUS)) {
2955 err = tg3_init_5401phy_dsp(tp);
2956 if (err)
2957 return err;
2958
2959 tg3_readphy(tp, MII_BMSR, &bmsr);
2960 for (i = 0; i < 1000; i++) {
2961 udelay(10);
2962 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2963 (bmsr & BMSR_LSTATUS)) {
2964 udelay(40);
2965 break;
2966 }
2967 }
2968
2969 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2970 !(bmsr & BMSR_LSTATUS) &&
2971 tp->link_config.active_speed == SPEED_1000) {
2972 err = tg3_phy_reset(tp);
2973 if (!err)
2974 err = tg3_init_5401phy_dsp(tp);
2975 if (err)
2976 return err;
2977 }
2978 }
2979 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2980 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2981 /* 5701 {A0,B0} CRC bug workaround */
2982 tg3_writephy(tp, 0x15, 0x0a75);
2983 tg3_writephy(tp, 0x1c, 0x8c68);
2984 tg3_writephy(tp, 0x1c, 0x8d68);
2985 tg3_writephy(tp, 0x1c, 0x8c68);
2986 }
2987
2988 /* Clear pending interrupts... */
2989 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2990 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2991
2992 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2993 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2994 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2995 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2996
2997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2999 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3000 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3001 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3002 else
3003 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3004 }
3005
3006 current_link_up = 0;
3007 current_speed = SPEED_INVALID;
3008 current_duplex = DUPLEX_INVALID;
3009
3010 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3011 u32 val;
3012
3013 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3014 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3015 if (!(val & (1 << 10))) {
3016 val |= (1 << 10);
3017 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3018 goto relink;
3019 }
3020 }
3021
3022 bmsr = 0;
3023 for (i = 0; i < 100; i++) {
3024 tg3_readphy(tp, MII_BMSR, &bmsr);
3025 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3026 (bmsr & BMSR_LSTATUS))
3027 break;
3028 udelay(40);
3029 }
3030
3031 if (bmsr & BMSR_LSTATUS) {
3032 u32 aux_stat, bmcr;
3033
3034 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3035 for (i = 0; i < 2000; i++) {
3036 udelay(10);
3037 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3038 aux_stat)
3039 break;
3040 }
3041
3042 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3043 &current_speed,
3044 &current_duplex);
3045
3046 bmcr = 0;
3047 for (i = 0; i < 200; i++) {
3048 tg3_readphy(tp, MII_BMCR, &bmcr);
3049 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3050 continue;
3051 if (bmcr && bmcr != 0x7fff)
3052 break;
3053 udelay(10);
3054 }
3055
ef167e27
MC		 3056 lcl_adv = 0;
3057 rmt_adv = 0;
1da177e4 3058
ef167e27
MC		 3059 tp->link_config.active_speed = current_speed;
3060 tp->link_config.active_duplex = current_duplex;
3061
3062 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3063 if ((bmcr & BMCR_ANENABLE) &&
3064 tg3_copper_is_advertising_all(tp,
3065 tp->link_config.advertising)) {
3066 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3067 &rmt_adv))
3068 current_link_up = 1;
1da177e4
LT		 3069 }
3070 } else {
3071 if (!(bmcr & BMCR_ANENABLE) &&
3072 tp->link_config.speed == current_speed &&
ef167e27
MC		 3073 tp->link_config.duplex == current_duplex &&
3074 tp->link_config.flowctrl ==
3075 tp->link_config.active_flowctrl) {
1da177e4 3076 current_link_up = 1;
1da177e4
LT		 3077 }
3078 }
3079
ef167e27
MC		 3080 if (current_link_up == 1 &&
3081 tp->link_config.active_duplex == DUPLEX_FULL)
3082 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3083 }
3084
1da177e4 3085relink:
6921d201 3086 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3087 u32 tmp;
3088
3089 tg3_phy_copper_begin(tp);
3090
3091 tg3_readphy(tp, MII_BMSR, &tmp);
3092 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3093 (tmp & BMSR_LSTATUS))
3094 current_link_up = 1;
3095 }
3096
3097 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3098 if (current_link_up == 1) {
3099 if (tp->link_config.active_speed == SPEED_100 ||
3100 tp->link_config.active_speed == SPEED_10)
3101 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3102 else
3103 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3104 } else
3105 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3106
3107 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3108 if (tp->link_config.active_duplex == DUPLEX_HALF)
3109 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3110
1da177e4 3111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3112 if (current_link_up == 1 &&
3113 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3114 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3115 else
3116 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3117 }
3118
3119 /* ??? Without this setting Netgear GA302T PHY does not
3120 * ??? send/receive packets...
3121 */
3122 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3123 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3124 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3125 tw32_f(MAC_MI_MODE, tp->mi_mode);
3126 udelay(80);
3127 }
3128
3129 tw32_f(MAC_MODE, tp->mac_mode);
3130 udelay(40);
3131
3132 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3133 /* Polled via timer. */
3134 tw32_f(MAC_EVENT, 0);
3135 } else {
3136 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3137 }
3138 udelay(40);
3139
3140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3141 current_link_up == 1 &&
3142 tp->link_config.active_speed == SPEED_1000 &&
3143 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3144 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3145 udelay(120);
3146 tw32_f(MAC_STATUS,
3147 (MAC_STATUS_SYNC_CHANGED |
3148 MAC_STATUS_CFG_CHANGED));
3149 udelay(40);
3150 tg3_write_mem(tp,
3151 NIC_SRAM_FIRMWARE_MBOX,
3152 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3153 }
3154
5e7dfd0f
MC		 3155 /* Prevent send BD corruption. */
3156 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3157 u16 oldlnkctl, newlnkctl;
3158
3159 pci_read_config_word(tp->pdev,
3160 tp->pcie_cap + PCI_EXP_LNKCTL,
3161 &oldlnkctl);
3162 if (tp->link_config.active_speed == SPEED_100 ||
3163 tp->link_config.active_speed == SPEED_10)
3164 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3165 else
3166 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3167 if (newlnkctl != oldlnkctl)
3168 pci_write_config_word(tp->pdev,
3169 tp->pcie_cap + PCI_EXP_LNKCTL,
3170 newlnkctl);
3171 }
3172
1da177e4
LT		 3173 if (current_link_up != netif_carrier_ok(tp->dev)) {
3174 if (current_link_up)
3175 netif_carrier_on(tp->dev);
3176 else
3177 netif_carrier_off(tp->dev);
3178 tg3_link_report(tp);
3179 }
3180
3181 return 0;
3182}
3183
3184struct tg3_fiber_aneginfo {
3185 int state;
3186#define ANEG_STATE_UNKNOWN 0
3187#define ANEG_STATE_AN_ENABLE 1
3188#define ANEG_STATE_RESTART_INIT 2
3189#define ANEG_STATE_RESTART 3
3190#define ANEG_STATE_DISABLE_LINK_OK 4
3191#define ANEG_STATE_ABILITY_DETECT_INIT 5
3192#define ANEG_STATE_ABILITY_DETECT 6
3193#define ANEG_STATE_ACK_DETECT_INIT 7
3194#define ANEG_STATE_ACK_DETECT 8
3195#define ANEG_STATE_COMPLETE_ACK_INIT 9
3196#define ANEG_STATE_COMPLETE_ACK 10
3197#define ANEG_STATE_IDLE_DETECT_INIT 11
3198#define ANEG_STATE_IDLE_DETECT 12
3199#define ANEG_STATE_LINK_OK 13
3200#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3201#define ANEG_STATE_NEXT_PAGE_WAIT 15
3202
3203 u32 flags;
3204#define MR_AN_ENABLE 0x00000001
3205#define MR_RESTART_AN 0x00000002
3206#define MR_AN_COMPLETE 0x00000004
3207#define MR_PAGE_RX 0x00000008
3208#define MR_NP_LOADED 0x00000010
3209#define MR_TOGGLE_TX 0x00000020
3210#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3211#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3212#define MR_LP_ADV_SYM_PAUSE 0x00000100
3213#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3214#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3215#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3216#define MR_LP_ADV_NEXT_PAGE 0x00001000
3217#define MR_TOGGLE_RX 0x00002000
3218#define MR_NP_RX 0x00004000
3219
3220#define MR_LINK_OK 0x80000000
3221
3222 unsigned long link_time, cur_time;
3223
3224 u32 ability_match_cfg;
3225 int ability_match_count;
3226
3227 char ability_match, idle_match, ack_match;
3228
3229 u32 txconfig, rxconfig;
3230#define ANEG_CFG_NP 0x00000080
3231#define ANEG_CFG_ACK 0x00000040
3232#define ANEG_CFG_RF2 0x00000020
3233#define ANEG_CFG_RF1 0x00000010
3234#define ANEG_CFG_PS2 0x00000001
3235#define ANEG_CFG_PS1 0x00008000
3236#define ANEG_CFG_HD 0x00004000
3237#define ANEG_CFG_FD 0x00002000
3238#define ANEG_CFG_INVAL 0x00001f06
3239
3240};
3241#define ANEG_OK 0
3242#define ANEG_DONE 1
3243#define ANEG_TIMER_ENAB 2
3244#define ANEG_FAILED -1
3245
3246#define ANEG_STATE_SETTLE_TIME 10000
3247
3248static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3249 struct tg3_fiber_aneginfo *ap)
3250{
5be73b47 3251 u16 flowctrl;
1da177e4
LT		 3252 unsigned long delta;
3253 u32 rx_cfg_reg;
3254 int ret;
3255
3256 if (ap->state == ANEG_STATE_UNKNOWN) {
3257 ap->rxconfig = 0;
3258 ap->link_time = 0;
3259 ap->cur_time = 0;
3260 ap->ability_match_cfg = 0;
3261 ap->ability_match_count = 0;
3262 ap->ability_match = 0;
3263 ap->idle_match = 0;
3264 ap->ack_match = 0;
3265 }
3266 ap->cur_time++;
3267
3268 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3269 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3270
3271 if (rx_cfg_reg != ap->ability_match_cfg) {
3272 ap->ability_match_cfg = rx_cfg_reg;
3273 ap->ability_match = 0;
3274 ap->ability_match_count = 0;
3275 } else {
3276 if (++ap->ability_match_count > 1) {
3277 ap->ability_match = 1;
3278 ap->ability_match_cfg = rx_cfg_reg;
3279 }
3280 }
3281 if (rx_cfg_reg & ANEG_CFG_ACK)
3282 ap->ack_match = 1;
3283 else
3284 ap->ack_match = 0;
3285
3286 ap->idle_match = 0;
3287 } else {
3288 ap->idle_match = 1;
3289 ap->ability_match_cfg = 0;
3290 ap->ability_match_count = 0;
3291 ap->ability_match = 0;
3292 ap->ack_match = 0;
3293
3294 rx_cfg_reg = 0;
3295 }
3296
3297 ap->rxconfig = rx_cfg_reg;
3298 ret = ANEG_OK;
3299
3300 switch(ap->state) {
3301 case ANEG_STATE_UNKNOWN:
3302 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3303 ap->state = ANEG_STATE_AN_ENABLE;
3304
3305 /* fallthru */
3306 case ANEG_STATE_AN_ENABLE:
3307 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3308 if (ap->flags & MR_AN_ENABLE) {
3309 ap->link_time = 0;
3310 ap->cur_time = 0;
3311 ap->ability_match_cfg = 0;
3312 ap->ability_match_count = 0;
3313 ap->ability_match = 0;
3314 ap->idle_match = 0;
3315 ap->ack_match = 0;
3316
3317 ap->state = ANEG_STATE_RESTART_INIT;
3318 } else {
3319 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3320 }
3321 break;
3322
3323 case ANEG_STATE_RESTART_INIT:
3324 ap->link_time = ap->cur_time;
3325 ap->flags &= ~(MR_NP_LOADED);
3326 ap->txconfig = 0;
3327 tw32(MAC_TX_AUTO_NEG, 0);
3328 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3329 tw32_f(MAC_MODE, tp->mac_mode);
3330 udelay(40);
3331
3332 ret = ANEG_TIMER_ENAB;
3333 ap->state = ANEG_STATE_RESTART;
3334
3335 /* fallthru */
3336 case ANEG_STATE_RESTART:
3337 delta = ap->cur_time - ap->link_time;
3338 if (delta > ANEG_STATE_SETTLE_TIME) {
3339 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3340 } else {
3341 ret = ANEG_TIMER_ENAB;
3342 }
3343 break;
3344
3345 case ANEG_STATE_DISABLE_LINK_OK:
3346 ret = ANEG_DONE;
3347 break;
3348
3349 case ANEG_STATE_ABILITY_DETECT_INIT:
3350 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3351 ap->txconfig = ANEG_CFG_FD;
3352 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3353 if (flowctrl & ADVERTISE_1000XPAUSE)
3354 ap->txconfig |= ANEG_CFG_PS1;
3355 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3356 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3357 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3358 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3359 tw32_f(MAC_MODE, tp->mac_mode);
3360 udelay(40);
3361
3362 ap->state = ANEG_STATE_ABILITY_DETECT;
3363 break;
3364
3365 case ANEG_STATE_ABILITY_DETECT:
3366 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3367 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3368 }
3369 break;
3370
3371 case ANEG_STATE_ACK_DETECT_INIT:
3372 ap->txconfig |= ANEG_CFG_ACK;
3373 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3374 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3375 tw32_f(MAC_MODE, tp->mac_mode);
3376 udelay(40);
3377
3378 ap->state = ANEG_STATE_ACK_DETECT;
3379
3380 /* fallthru */
3381 case ANEG_STATE_ACK_DETECT:
3382 if (ap->ack_match != 0) {
3383 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3384 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3385 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3386 } else {
3387 ap->state = ANEG_STATE_AN_ENABLE;
3388 }
3389 } else if (ap->ability_match != 0 &&
3390 ap->rxconfig == 0) {
3391 ap->state = ANEG_STATE_AN_ENABLE;
3392 }
3393 break;
3394
3395 case ANEG_STATE_COMPLETE_ACK_INIT:
3396 if (ap->rxconfig & ANEG_CFG_INVAL) {
3397 ret = ANEG_FAILED;
3398 break;
3399 }
3400 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3401 MR_LP_ADV_HALF_DUPLEX |
3402 MR_LP_ADV_SYM_PAUSE |
3403 MR_LP_ADV_ASYM_PAUSE |
3404 MR_LP_ADV_REMOTE_FAULT1 |
3405 MR_LP_ADV_REMOTE_FAULT2 |
3406 MR_LP_ADV_NEXT_PAGE |
3407 MR_TOGGLE_RX |
3408 MR_NP_RX);
3409 if (ap->rxconfig & ANEG_CFG_FD)
3410 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3411 if (ap->rxconfig & ANEG_CFG_HD)
3412 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3413 if (ap->rxconfig & ANEG_CFG_PS1)
3414 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3415 if (ap->rxconfig & ANEG_CFG_PS2)
3416 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3417 if (ap->rxconfig & ANEG_CFG_RF1)
3418 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3419 if (ap->rxconfig & ANEG_CFG_RF2)
3420 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3421 if (ap->rxconfig & ANEG_CFG_NP)
3422 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3423
3424 ap->link_time = ap->cur_time;
3425
3426 ap->flags ^= (MR_TOGGLE_TX);
3427 if (ap->rxconfig & 0x0008)
3428 ap->flags |= MR_TOGGLE_RX;
3429 if (ap->rxconfig & ANEG_CFG_NP)
3430 ap->flags |= MR_NP_RX;
3431 ap->flags |= MR_PAGE_RX;
3432
3433 ap->state = ANEG_STATE_COMPLETE_ACK;
3434 ret = ANEG_TIMER_ENAB;
3435 break;
3436
3437 case ANEG_STATE_COMPLETE_ACK:
3438 if (ap->ability_match != 0 &&
3439 ap->rxconfig == 0) {
3440 ap->state = ANEG_STATE_AN_ENABLE;
3441 break;
3442 }
3443 delta = ap->cur_time - ap->link_time;
3444 if (delta > ANEG_STATE_SETTLE_TIME) {
3445 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3446 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3447 } else {
3448 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3449 !(ap->flags & MR_NP_RX)) {
3450 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3451 } else {
3452 ret = ANEG_FAILED;
3453 }
3454 }
3455 }
3456 break;
3457
3458 case ANEG_STATE_IDLE_DETECT_INIT:
3459 ap->link_time = ap->cur_time;
3460 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3461 tw32_f(MAC_MODE, tp->mac_mode);
3462 udelay(40);
3463
3464 ap->state = ANEG_STATE_IDLE_DETECT;
3465 ret = ANEG_TIMER_ENAB;
3466 break;
3467
3468 case ANEG_STATE_IDLE_DETECT:
3469 if (ap->ability_match != 0 &&
3470 ap->rxconfig == 0) {
3471 ap->state = ANEG_STATE_AN_ENABLE;
3472 break;
3473 }
3474 delta = ap->cur_time - ap->link_time;
3475 if (delta > ANEG_STATE_SETTLE_TIME) {
3476 /* XXX another gem from the Broadcom driver :( */
3477 ap->state = ANEG_STATE_LINK_OK;
3478 }
3479 break;
3480
3481 case ANEG_STATE_LINK_OK:
3482 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3483 ret = ANEG_DONE;
3484 break;
3485
3486 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3487 /* ??? unimplemented */
3488 break;
3489
3490 case ANEG_STATE_NEXT_PAGE_WAIT:
3491 /* ??? unimplemented */
3492 break;
3493
3494 default:
3495 ret = ANEG_FAILED;
3496 break;
855e1111 3497 }
1da177e4
LT		 3498
3499 return ret;
3500}
3501
5be73b47 3502static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3503{
3504 int res = 0;
3505 struct tg3_fiber_aneginfo aninfo;
3506 int status = ANEG_FAILED;
3507 unsigned int tick;
3508 u32 tmp;
3509
3510 tw32_f(MAC_TX_AUTO_NEG, 0);
3511
3512 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3513 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3514 udelay(40);
3515
3516 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3517 udelay(40);
3518
3519 memset(&aninfo, 0, sizeof(aninfo));
3520 aninfo.flags |= MR_AN_ENABLE;
3521 aninfo.state = ANEG_STATE_UNKNOWN;
3522 aninfo.cur_time = 0;
3523 tick = 0;
3524 while (++tick < 195000) {
3525 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3526 if (status == ANEG_DONE || status == ANEG_FAILED)
3527 break;
3528
3529 udelay(1);
3530 }
3531
3532 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3533 tw32_f(MAC_MODE, tp->mac_mode);
3534 udelay(40);
3535
5be73b47
MC		 3536 *txflags = aninfo.txconfig;
3537 *rxflags = aninfo.flags;
1da177e4
LT		 3538
3539 if (status == ANEG_DONE &&
3540 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3541 MR_LP_ADV_FULL_DUPLEX)))
3542 res = 1;
3543
3544 return res;
3545}
3546
3547static void tg3_init_bcm8002(struct tg3 *tp)
3548{
3549 u32 mac_status = tr32(MAC_STATUS);
3550 int i;
3551
3552 /* Reset when initting first time or we have a link. */
3553 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3554 !(mac_status & MAC_STATUS_PCS_SYNCED))
3555 return;
3556
3557 /* Set PLL lock range. */
3558 tg3_writephy(tp, 0x16, 0x8007);
3559
3560 /* SW reset */
3561 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3562
3563 /* Wait for reset to complete. */
3564 /* XXX schedule_timeout() ... */
3565 for (i = 0; i < 500; i++)
3566 udelay(10);
3567
3568 /* Config mode; select PMA/Ch 1 regs. */
3569 tg3_writephy(tp, 0x10, 0x8411);
3570
3571 /* Enable auto-lock and comdet, select txclk for tx. */
3572 tg3_writephy(tp, 0x11, 0x0a10);
3573
3574 tg3_writephy(tp, 0x18, 0x00a0);
3575 tg3_writephy(tp, 0x16, 0x41ff);
3576
3577 /* Assert and deassert POR. */
3578 tg3_writephy(tp, 0x13, 0x0400);
3579 udelay(40);
3580 tg3_writephy(tp, 0x13, 0x0000);
3581
3582 tg3_writephy(tp, 0x11, 0x0a50);
3583 udelay(40);
3584 tg3_writephy(tp, 0x11, 0x0a10);
3585
3586 /* Wait for signal to stabilize */
3587 /* XXX schedule_timeout() ... */
3588 for (i = 0; i < 15000; i++)
3589 udelay(10);
3590
3591 /* Deselect the channel register so we can read the PHYID
3592 * later.
3593 */
3594 tg3_writephy(tp, 0x10, 0x8011);
3595}
3596
3597static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3598{
82cd3d11 3599 u16 flowctrl;
1da177e4
LT		 3600 u32 sg_dig_ctrl, sg_dig_status;
3601 u32 serdes_cfg, expected_sg_dig_ctrl;
3602 int workaround, port_a;
3603 int current_link_up;
3604
3605 serdes_cfg = 0;
3606 expected_sg_dig_ctrl = 0;
3607 workaround = 0;
3608 port_a = 1;
3609 current_link_up = 0;
3610
3611 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3612 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3613 workaround = 1;
3614 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3615 port_a = 0;
3616
3617 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3618 /* preserve bits 20-23 for voltage regulator */
3619 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3620 }
3621
3622 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3623
3624 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3625 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3626 if (workaround) {
3627 u32 val = serdes_cfg;
3628
3629 if (port_a)
3630 val |= 0xc010000;
3631 else
3632 val |= 0x4010000;
3633 tw32_f(MAC_SERDES_CFG, val);
3634 }
c98f6e3b
MC		 3635
3636 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3637 }
3638 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3639 tg3_setup_flow_control(tp, 0, 0);
3640 current_link_up = 1;
3641 }
3642 goto out;
3643 }
3644
3645 /* Want auto-negotiation. */
c98f6e3b 3646 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3647
82cd3d11
MC		 3648 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3649 if (flowctrl & ADVERTISE_1000XPAUSE)
3650 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3651 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3652 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3653
3654 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3655 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3656 tp->serdes_counter &&
3657 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3658 MAC_STATUS_RCVD_CFG)) ==
3659 MAC_STATUS_PCS_SYNCED)) {
3660 tp->serdes_counter--;
3661 current_link_up = 1;
3662 goto out;
3663 }
3664restart_autoneg:
1da177e4
LT		 3665 if (workaround)
3666 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3667 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3668 udelay(5);
3669 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3670
3d3ebe74
MC		 3671 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3672 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3673 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3674 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3675 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3676 mac_status = tr32(MAC_STATUS);
3677
c98f6e3b 3678 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3679 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3680 u32 local_adv = 0, remote_adv = 0;
3681
3682 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3683 local_adv |= ADVERTISE_1000XPAUSE;
3684 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3685 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3686
c98f6e3b 3687 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3688 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3689 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3690 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3691
3692 tg3_setup_flow_control(tp, local_adv, remote_adv);
3693 current_link_up = 1;
3d3ebe74
MC		 3694 tp->serdes_counter = 0;
3695 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3696 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3697 if (tp->serdes_counter)
3698 tp->serdes_counter--;
1da177e4
LT		 3699 else {
3700 if (workaround) {
3701 u32 val = serdes_cfg;
3702
3703 if (port_a)
3704 val |= 0xc010000;
3705 else
3706 val |= 0x4010000;
3707
3708 tw32_f(MAC_SERDES_CFG, val);
3709 }
3710
c98f6e3b 3711 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3712 udelay(40);
3713
3714 /* Link parallel detection - link is up */
3715 /* only if we have PCS_SYNC and not */
3716 /* receiving config code words */
3717 mac_status = tr32(MAC_STATUS);
3718 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3719 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3720 tg3_setup_flow_control(tp, 0, 0);
3721 current_link_up = 1;
3d3ebe74
MC		 3722 tp->tg3_flags2 |=
3723 TG3_FLG2_PARALLEL_DETECT;
3724 tp->serdes_counter =
3725 SERDES_PARALLEL_DET_TIMEOUT;
3726 } else
3727 goto restart_autoneg;
1da177e4
LT		 3728 }
3729 }
3d3ebe74
MC		 3730 } else {
3731 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3732 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3733 }
3734
3735out:
3736 return current_link_up;
3737}
3738
3739static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3740{
3741 int current_link_up = 0;
3742
5cf64b8a 3743 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3744 goto out;
1da177e4
LT		 3745
3746 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3747 u32 txflags, rxflags;
1da177e4 3748 int i;
6aa20a22 3749
5be73b47
MC		 3750 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3751 u32 local_adv = 0, remote_adv = 0;
1da177e4 3752
5be73b47
MC		 3753 if (txflags & ANEG_CFG_PS1)
3754 local_adv |= ADVERTISE_1000XPAUSE;
3755 if (txflags & ANEG_CFG_PS2)
3756 local_adv |= ADVERTISE_1000XPSE_ASYM;
3757
3758 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3759 remote_adv |= LPA_1000XPAUSE;
3760 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3761 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3762
3763 tg3_setup_flow_control(tp, local_adv, remote_adv);
3764
1da177e4
LT		 3765 current_link_up = 1;
3766 }
3767 for (i = 0; i < 30; i++) {
3768 udelay(20);
3769 tw32_f(MAC_STATUS,
3770 (MAC_STATUS_SYNC_CHANGED |
3771 MAC_STATUS_CFG_CHANGED));
3772 udelay(40);
3773 if ((tr32(MAC_STATUS) &
3774 (MAC_STATUS_SYNC_CHANGED |
3775 MAC_STATUS_CFG_CHANGED)) == 0)
3776 break;
3777 }
3778
3779 mac_status = tr32(MAC_STATUS);
3780 if (current_link_up == 0 &&
3781 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3782 !(mac_status & MAC_STATUS_RCVD_CFG))
3783 current_link_up = 1;
3784 } else {
5be73b47
MC		 3785 tg3_setup_flow_control(tp, 0, 0);
3786
1da177e4
LT		 3787 /* Forcing 1000FD link up. */
3788 current_link_up = 1;
1da177e4
LT		 3789
3790 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3791 udelay(40);
e8f3f6ca
MC		 3792
3793 tw32_f(MAC_MODE, tp->mac_mode);
3794 udelay(40);
1da177e4
LT		 3795 }
3796
3797out:
3798 return current_link_up;
3799}
3800
3801static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3802{
3803 u32 orig_pause_cfg;
3804 u16 orig_active_speed;
3805 u8 orig_active_duplex;
3806 u32 mac_status;
3807 int current_link_up;
3808 int i;
3809
8d018621 3810 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3811 orig_active_speed = tp->link_config.active_speed;
3812 orig_active_duplex = tp->link_config.active_duplex;
3813
3814 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3815 netif_carrier_ok(tp->dev) &&
3816 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3817 mac_status = tr32(MAC_STATUS);
3818 mac_status &= (MAC_STATUS_PCS_SYNCED |
3819 MAC_STATUS_SIGNAL_DET |
3820 MAC_STATUS_CFG_CHANGED |
3821 MAC_STATUS_RCVD_CFG);
3822 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3823 MAC_STATUS_SIGNAL_DET)) {
3824 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3825 MAC_STATUS_CFG_CHANGED));
3826 return 0;
3827 }
3828 }
3829
3830 tw32_f(MAC_TX_AUTO_NEG, 0);
3831
3832 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3833 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3834 tw32_f(MAC_MODE, tp->mac_mode);
3835 udelay(40);
3836
3837 if (tp->phy_id == PHY_ID_BCM8002)
3838 tg3_init_bcm8002(tp);
3839
3840 /* Enable link change event even when serdes polling. */
3841 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3842 udelay(40);
3843
3844 current_link_up = 0;
3845 mac_status = tr32(MAC_STATUS);
3846
3847 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3848 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3849 else
3850 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3851
1da177e4
LT		 3852 tp->hw_status->status =
3853 (SD_STATUS_UPDATED |
3854 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3855
3856 for (i = 0; i < 100; i++) {
3857 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3858 MAC_STATUS_CFG_CHANGED));
3859 udelay(5);
3860 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3861 MAC_STATUS_CFG_CHANGED |
3862 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3863 break;
3864 }
3865
3866 mac_status = tr32(MAC_STATUS);
3867 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3868 current_link_up = 0;
3d3ebe74
MC		 3869 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3870 tp->serdes_counter == 0) {
1da177e4
LT		 3871 tw32_f(MAC_MODE, (tp->mac_mode |
3872 MAC_MODE_SEND_CONFIGS));
3873 udelay(1);
3874 tw32_f(MAC_MODE, tp->mac_mode);
3875 }
3876 }
3877
3878 if (current_link_up == 1) {
3879 tp->link_config.active_speed = SPEED_1000;
3880 tp->link_config.active_duplex = DUPLEX_FULL;
3881 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3882 LED_CTRL_LNKLED_OVERRIDE |
3883 LED_CTRL_1000MBPS_ON));
3884 } else {
3885 tp->link_config.active_speed = SPEED_INVALID;
3886 tp->link_config.active_duplex = DUPLEX_INVALID;
3887 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3888 LED_CTRL_LNKLED_OVERRIDE |
3889 LED_CTRL_TRAFFIC_OVERRIDE));
3890 }
3891
3892 if (current_link_up != netif_carrier_ok(tp->dev)) {
3893 if (current_link_up)
3894 netif_carrier_on(tp->dev);
3895 else
3896 netif_carrier_off(tp->dev);
3897 tg3_link_report(tp);
3898 } else {
8d018621 3899 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3900 if (orig_pause_cfg != now_pause_cfg ||
3901 orig_active_speed != tp->link_config.active_speed ||
3902 orig_active_duplex != tp->link_config.active_duplex)
3903 tg3_link_report(tp);
3904 }
3905
3906 return 0;
3907}
3908
747e8f8b
MC		 3909static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3910{
3911 int current_link_up, err = 0;
3912 u32 bmsr, bmcr;
3913 u16 current_speed;
3914 u8 current_duplex;
ef167e27 3915 u32 local_adv, remote_adv;
747e8f8b
MC		 3916
3917 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3918 tw32_f(MAC_MODE, tp->mac_mode);
3919 udelay(40);
3920
3921 tw32(MAC_EVENT, 0);
3922
3923 tw32_f(MAC_STATUS,
3924 (MAC_STATUS_SYNC_CHANGED |
3925 MAC_STATUS_CFG_CHANGED |
3926 MAC_STATUS_MI_COMPLETION |
3927 MAC_STATUS_LNKSTATE_CHANGED));
3928 udelay(40);
3929
3930 if (force_reset)
3931 tg3_phy_reset(tp);
3932
3933 current_link_up = 0;
3934 current_speed = SPEED_INVALID;
3935 current_duplex = DUPLEX_INVALID;
3936
3937 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3938 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3940 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3941 bmsr |= BMSR_LSTATUS;
3942 else
3943 bmsr &= ~BMSR_LSTATUS;
3944 }
747e8f8b
MC		 3945
3946 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3947
3948 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3949 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 3950 /* do nothing, just check for link up at the end */
3951 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3952 u32 adv, new_adv;
3953
3954 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3955 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3956 ADVERTISE_1000XPAUSE |
3957 ADVERTISE_1000XPSE_ASYM |
3958 ADVERTISE_SLCT);
3959
ba4d07a8 3960 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 3961
3962 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3963 new_adv |= ADVERTISE_1000XHALF;
3964 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3965 new_adv |= ADVERTISE_1000XFULL;
3966
3967 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3968 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3969 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3970 tg3_writephy(tp, MII_BMCR, bmcr);
3971
3972 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 3973 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 3974 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3975
3976 return err;
3977 }
3978 } else {
3979 u32 new_bmcr;
3980
3981 bmcr &= ~BMCR_SPEED1000;
3982 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3983
3984 if (tp->link_config.duplex == DUPLEX_FULL)
3985 new_bmcr |= BMCR_FULLDPLX;
3986
3987 if (new_bmcr != bmcr) {
3988 /* BMCR_SPEED1000 is a reserved bit that needs
3989 * to be set on write.
3990 */
3991 new_bmcr |= BMCR_SPEED1000;
3992
3993 /* Force a linkdown */
3994 if (netif_carrier_ok(tp->dev)) {
3995 u32 adv;
3996
3997 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3998 adv &= ~(ADVERTISE_1000XFULL |
3999 ADVERTISE_1000XHALF |
4000 ADVERTISE_SLCT);
4001 tg3_writephy(tp, MII_ADVERTISE, adv);
4002 tg3_writephy(tp, MII_BMCR, bmcr |
4003 BMCR_ANRESTART |
4004 BMCR_ANENABLE);
4005 udelay(10);
4006 netif_carrier_off(tp->dev);
4007 }
4008 tg3_writephy(tp, MII_BMCR, new_bmcr);
4009 bmcr = new_bmcr;
4010 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4011 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4012 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4013 ASIC_REV_5714) {
4014 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4015 bmsr |= BMSR_LSTATUS;
4016 else
4017 bmsr &= ~BMSR_LSTATUS;
4018 }
747e8f8b
MC		 4019 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4020 }
4021 }
4022
4023 if (bmsr & BMSR_LSTATUS) {
4024 current_speed = SPEED_1000;
4025 current_link_up = 1;
4026 if (bmcr & BMCR_FULLDPLX)
4027 current_duplex = DUPLEX_FULL;
4028 else
4029 current_duplex = DUPLEX_HALF;
4030
ef167e27
MC		 4031 local_adv = 0;
4032 remote_adv = 0;
4033
747e8f8b 4034 if (bmcr & BMCR_ANENABLE) {
ef167e27 4035 u32 common;
747e8f8b
MC		 4036
4037 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4038 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4039 common = local_adv & remote_adv;
4040 if (common & (ADVERTISE_1000XHALF |
4041 ADVERTISE_1000XFULL)) {
4042 if (common & ADVERTISE_1000XFULL)
4043 current_duplex = DUPLEX_FULL;
4044 else
4045 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4046 }
4047 else
4048 current_link_up = 0;
4049 }
4050 }
4051
ef167e27
MC		 4052 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4053 tg3_setup_flow_control(tp, local_adv, remote_adv);
4054
747e8f8b
MC		 4055 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4056 if (tp->link_config.active_duplex == DUPLEX_HALF)
4057 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4058
4059 tw32_f(MAC_MODE, tp->mac_mode);
4060 udelay(40);
4061
4062 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4063
4064 tp->link_config.active_speed = current_speed;
4065 tp->link_config.active_duplex = current_duplex;
4066
4067 if (current_link_up != netif_carrier_ok(tp->dev)) {
4068 if (current_link_up)
4069 netif_carrier_on(tp->dev);
4070 else {
4071 netif_carrier_off(tp->dev);
4072 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4073 }
4074 tg3_link_report(tp);
4075 }
4076 return err;
4077}
4078
4079static void tg3_serdes_parallel_detect(struct tg3 *tp)
4080{
3d3ebe74 4081 if (tp->serdes_counter) {
747e8f8b 4082 /* Give autoneg time to complete. */
3d3ebe74 4083 tp->serdes_counter--;
747e8f8b
MC		 4084 return;
4085 }
4086 if (!netif_carrier_ok(tp->dev) &&
4087 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4088 u32 bmcr;
4089
4090 tg3_readphy(tp, MII_BMCR, &bmcr);
4091 if (bmcr & BMCR_ANENABLE) {
4092 u32 phy1, phy2;
4093
4094 /* Select shadow register 0x1f */
4095 tg3_writephy(tp, 0x1c, 0x7c00);
4096 tg3_readphy(tp, 0x1c, &phy1);
4097
4098 /* Select expansion interrupt status register */
4099 tg3_writephy(tp, 0x17, 0x0f01);
4100 tg3_readphy(tp, 0x15, &phy2);
4101 tg3_readphy(tp, 0x15, &phy2);
4102
4103 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4104 /* We have signal detect and not receiving
4105 * config code words, link is up by parallel
4106 * detection.
4107 */
4108
4109 bmcr &= ~BMCR_ANENABLE;
4110 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4111 tg3_writephy(tp, MII_BMCR, bmcr);
4112 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4113 }
4114 }
4115 }
4116 else if (netif_carrier_ok(tp->dev) &&
4117 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4118 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4119 u32 phy2;
4120
4121 /* Select expansion interrupt status register */
4122 tg3_writephy(tp, 0x17, 0x0f01);
4123 tg3_readphy(tp, 0x15, &phy2);
4124 if (phy2 & 0x20) {
4125 u32 bmcr;
4126
4127 /* Config code words received, turn on autoneg. */
4128 tg3_readphy(tp, MII_BMCR, &bmcr);
4129 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4130
4131 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4132
4133 }
4134 }
4135}
4136
1da177e4
LT		 4137static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4138{
4139 int err;
4140
4141 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4142 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4143 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4144 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4145 } else {
4146 err = tg3_setup_copper_phy(tp, force_reset);
4147 }
4148
bcb37f6c 4149 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4150 u32 val, scale;
4151
4152 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4153 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4154 scale = 65;
4155 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4156 scale = 6;
4157 else
4158 scale = 12;
4159
4160 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4161 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4162 tw32(GRC_MISC_CFG, val);
4163 }
4164
1da177e4
LT		 4165 if (tp->link_config.active_speed == SPEED_1000 &&
4166 tp->link_config.active_duplex == DUPLEX_HALF)
4167 tw32(MAC_TX_LENGTHS,
4168 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4169 (6 << TX_LENGTHS_IPG_SHIFT) |
4170 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4171 else
4172 tw32(MAC_TX_LENGTHS,
4173 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4174 (6 << TX_LENGTHS_IPG_SHIFT) |
4175 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4176
4177 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4178 if (netif_carrier_ok(tp->dev)) {
4179 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4180 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4181 } else {
4182 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4183 }
4184 }
4185
8ed5d97e
MC		 4186 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4187 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4188 if (!netif_carrier_ok(tp->dev))
4189 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4190 tp->pwrmgmt_thresh;
4191 else
4192 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4193 tw32(PCIE_PWR_MGMT_THRESH, val);
4194 }
4195
1da177e4
LT		 4196 return err;
4197}
4198
df3e6548
MC		 4199/* This is called whenever we suspect that the system chipset is re-
4200 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4201 * is bogus tx completions. We try to recover by setting the
4202 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4203 * in the workqueue.
4204 */
4205static void tg3_tx_recover(struct tg3 *tp)
4206{
4207 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4208 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4209
4210 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4211 "mapped I/O cycles to the network device, attempting to "
4212 "recover. Please report the problem to the driver maintainer "
4213 "and include system chipset information.\n", tp->dev->name);
4214
4215 spin_lock(&tp->lock);
df3e6548 4216 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4217 spin_unlock(&tp->lock);
4218}
4219
1b2a7205
MC		 4220static inline u32 tg3_tx_avail(struct tg3 *tp)
4221{
4222 smp_mb();
4223 return (tp->tx_pending -
4224 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4225}
4226
1da177e4
LT		 4227/* Tigon3 never reports partial packet sends. So we do not
4228 * need special logic to handle SKBs that have not had all
4229 * of their frags sent yet, like SunGEM does.
4230 */
4231static void tg3_tx(struct tg3 *tp)
4232{
4233 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4234 u32 sw_idx = tp->tx_cons;
4235
4236 while (sw_idx != hw_idx) {
4237 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4238 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4239 int i, tx_bug = 0;
4240
4241 if (unlikely(skb == NULL)) {
4242 tg3_tx_recover(tp);
4243 return;
4244 }
1da177e4 4245
90079ce8 4246 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4247
4248 ri->skb = NULL;
4249
4250 sw_idx = NEXT_TX(sw_idx);
4251
4252 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4253 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4254 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4255 tx_bug = 1;
1da177e4
LT		 4256 sw_idx = NEXT_TX(sw_idx);
4257 }
4258
f47c11ee 4259 dev_kfree_skb(skb);
df3e6548
MC		 4260
4261 if (unlikely(tx_bug)) {
4262 tg3_tx_recover(tp);
4263 return;
4264 }
1da177e4
LT		 4265 }
4266
4267 tp->tx_cons = sw_idx;
4268
1b2a7205
MC		 4269 /* Need to make the tx_cons update visible to tg3_start_xmit()
4270 * before checking for netif_queue_stopped(). Without the
4271 * memory barrier, there is a small possibility that tg3_start_xmit()
4272 * will miss it and cause the queue to be stopped forever.
4273 */
4274 smp_mb();
4275
4276 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4277 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4278 netif_tx_lock(tp->dev);
51b91468 4279 if (netif_queue_stopped(tp->dev) &&
42952231 4280 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4281 netif_wake_queue(tp->dev);
1b2a7205 4282 netif_tx_unlock(tp->dev);
51b91468 4283 }
1da177e4
LT		 4284}
4285
4286/* Returns size of skb allocated or < 0 on error.
4287 *
4288 * We only need to fill in the address because the other members
4289 * of the RX descriptor are invariant, see tg3_init_rings.
4290 *
4291 * Note the purposeful assymetry of cpu vs. chip accesses. For
4292 * posting buffers we only dirty the first cache line of the RX
4293 * descriptor (containing the address). Whereas for the RX status
4294 * buffers the cpu only reads the last cacheline of the RX descriptor
4295 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4296 */
4297static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4298 int src_idx, u32 dest_idx_unmasked)
4299{
4300 struct tg3_rx_buffer_desc *desc;
4301 struct ring_info *map, *src_map;
4302 struct sk_buff *skb;
4303 dma_addr_t mapping;
4304 int skb_size, dest_idx;
4305
4306 src_map = NULL;
4307 switch (opaque_key) {
4308 case RXD_OPAQUE_RING_STD:
4309 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4310 desc = &tp->rx_std[dest_idx];
4311 map = &tp->rx_std_buffers[dest_idx];
4312 if (src_idx >= 0)
4313 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 4314 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 4315 break;
4316
4317 case RXD_OPAQUE_RING_JUMBO:
4318 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4319 desc = &tp->rx_jumbo[dest_idx];
4320 map = &tp->rx_jumbo_buffers[dest_idx];
4321 if (src_idx >= 0)
4322 src_map = &tp->rx_jumbo_buffers[src_idx];
4323 skb_size = RX_JUMBO_PKT_BUF_SZ;
4324 break;
4325
4326 default:
4327 return -EINVAL;
855e1111 4328 }
1da177e4
LT		 4329
4330 /* Do not overwrite any of the map or rp information
4331 * until we are sure we can commit to a new buffer.
4332 *
4333 * Callers depend upon this behavior and assume that
4334 * we leave everything unchanged if we fail.
4335 */
a20e9c62 4336 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 4337 if (skb == NULL)
4338 return -ENOMEM;
4339
1da177e4
LT		 4340 skb_reserve(skb, tp->rx_offset);
4341
4342 mapping = pci_map_single(tp->pdev, skb->data,
4343 skb_size - tp->rx_offset,
4344 PCI_DMA_FROMDEVICE);
4345
4346 map->skb = skb;
4347 pci_unmap_addr_set(map, mapping, mapping);
4348
4349 if (src_map != NULL)
4350 src_map->skb = NULL;
4351
4352 desc->addr_hi = ((u64)mapping >> 32);
4353 desc->addr_lo = ((u64)mapping & 0xffffffff);
4354
4355 return skb_size;
4356}
4357
4358/* We only need to move over in the address because the other
4359 * members of the RX descriptor are invariant. See notes above
4360 * tg3_alloc_rx_skb for full details.
4361 */
4362static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4363 int src_idx, u32 dest_idx_unmasked)
4364{
4365 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4366 struct ring_info *src_map, *dest_map;
4367 int dest_idx;
4368
4369 switch (opaque_key) {
4370 case RXD_OPAQUE_RING_STD:
4371 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4372 dest_desc = &tp->rx_std[dest_idx];
4373 dest_map = &tp->rx_std_buffers[dest_idx];
4374 src_desc = &tp->rx_std[src_idx];
4375 src_map = &tp->rx_std_buffers[src_idx];
4376 break;
4377
4378 case RXD_OPAQUE_RING_JUMBO:
4379 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4380 dest_desc = &tp->rx_jumbo[dest_idx];
4381 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4382 src_desc = &tp->rx_jumbo[src_idx];
4383 src_map = &tp->rx_jumbo_buffers[src_idx];
4384 break;
4385
4386 default:
4387 return;
855e1111 4388 }
1da177e4
LT		 4389
4390 dest_map->skb = src_map->skb;
4391 pci_unmap_addr_set(dest_map, mapping,
4392 pci_unmap_addr(src_map, mapping));
4393 dest_desc->addr_hi = src_desc->addr_hi;
4394 dest_desc->addr_lo = src_desc->addr_lo;
4395
4396 src_map->skb = NULL;
4397}
4398
4399#if TG3_VLAN_TAG_USED
4400static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4401{
1383bdb9 4402 return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
1da177e4
LT		 4403}
4404#endif
4405
4406/* The RX ring scheme is composed of multiple rings which post fresh
4407 * buffers to the chip, and one special ring the chip uses to report
4408 * status back to the host.
4409 *
4410 * The special ring reports the status of received packets to the
4411 * host. The chip does not write into the original descriptor the
4412 * RX buffer was obtained from. The chip simply takes the original
4413 * descriptor as provided by the host, updates the status and length
4414 * field, then writes this into the next status ring entry.
4415 *
4416 * Each ring the host uses to post buffers to the chip is described
4417 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4418 * it is first placed into the on-chip ram. When the packet's length
4419 * is known, it walks down the TG3_BDINFO entries to select the ring.
4420 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4421 * which is within the range of the new packet's length is chosen.
4422 *
4423 * The "separate ring for rx status" scheme may sound queer, but it makes
4424 * sense from a cache coherency perspective. If only the host writes
4425 * to the buffer post rings, and only the chip writes to the rx status
4426 * rings, then cache lines never move beyond shared-modified state.
4427 * If both the host and chip were to write into the same ring, cache line
4428 * eviction could occur since both entities want it in an exclusive state.
4429 */
4430static int tg3_rx(struct tg3 *tp, int budget)
4431{
f92905de 4432 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4433 u32 sw_idx = tp->rx_rcb_ptr;
4434 u16 hw_idx;
1da177e4
LT		 4435 int received;
4436
4437 hw_idx = tp->hw_status->idx[0].rx_producer;
4438 /*
4439 * We need to order the read of hw_idx and the read of
4440 * the opaque cookie.
4441 */
4442 rmb();
1da177e4
LT		 4443 work_mask = 0;
4444 received = 0;
4445 while (sw_idx != hw_idx && budget > 0) {
4446 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4447 unsigned int len;
4448 struct sk_buff *skb;
4449 dma_addr_t dma_addr;
4450 u32 opaque_key, desc_idx, *post_ptr;
4451
4452 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4453 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4454 if (opaque_key == RXD_OPAQUE_RING_STD) {
4455 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4456 mapping);
4457 skb = tp->rx_std_buffers[desc_idx].skb;
4458 post_ptr = &tp->rx_std_ptr;
f92905de 4459 rx_std_posted++;
1da177e4
LT		 4460 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4461 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4462 mapping);
4463 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4464 post_ptr = &tp->rx_jumbo_ptr;
4465 }
4466 else {
4467 goto next_pkt_nopost;
4468 }
4469
4470 work_mask |= opaque_key;
4471
4472 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4473 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4474 drop_it:
4475 tg3_recycle_rx(tp, opaque_key,
4476 desc_idx, *post_ptr);
4477 drop_it_no_recycle:
4478 /* Other statistics kept track of by card. */
4479 tp->net_stats.rx_dropped++;
4480 goto next_pkt;
4481 }
4482
ad829268
MC		 4483 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4484 ETH_FCS_LEN;
1da177e4 4485
6aa20a22 4486 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4487 && tp->rx_offset == NET_IP_ALIGN
4488 /* rx_offset will likely not equal NET_IP_ALIGN
4489 * if this is a 5701 card running in PCI-X mode
4490 * [see tg3_get_invariants()]
4491 */
1da177e4
LT		 4492 ) {
4493 int skb_size;
4494
4495 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4496 desc_idx, *post_ptr);
4497 if (skb_size < 0)
4498 goto drop_it;
4499
4500 pci_unmap_single(tp->pdev, dma_addr,
4501 skb_size - tp->rx_offset,
4502 PCI_DMA_FROMDEVICE);
4503
4504 skb_put(skb, len);
4505 } else {
4506 struct sk_buff *copy_skb;
4507
4508 tg3_recycle_rx(tp, opaque_key,
4509 desc_idx, *post_ptr);
4510
ad829268
MC		 4511 copy_skb = netdev_alloc_skb(tp->dev,
4512 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4513 if (copy_skb == NULL)
4514 goto drop_it_no_recycle;
4515
ad829268 4516 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4517 skb_put(copy_skb, len);
4518 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4519 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4520 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4521
4522 /* We'll reuse the original ring buffer. */
4523 skb = copy_skb;
4524 }
4525
4526 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4527 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4528 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4529 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4530 skb->ip_summed = CHECKSUM_UNNECESSARY;
4531 else
4532 skb->ip_summed = CHECKSUM_NONE;
4533
4534 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4535
4536 if (len > (tp->dev->mtu + ETH_HLEN) &&
4537 skb->protocol != htons(ETH_P_8021Q)) {
4538 dev_kfree_skb(skb);
4539 goto next_pkt;
4540 }
4541
1da177e4
LT		 4542#if TG3_VLAN_TAG_USED
4543 if (tp->vlgrp != NULL &&
4544 desc->type_flags & RXD_FLAG_VLAN) {
4545 tg3_vlan_rx(tp, skb,
4546 desc->err_vlan & RXD_VLAN_MASK);
4547 } else
4548#endif
1383bdb9 4549 napi_gro_receive(&tp->napi, skb);
1da177e4 4550
1da177e4
LT		 4551 received++;
4552 budget--;
4553
4554next_pkt:
4555 (*post_ptr)++;
f92905de
MC		 4556
4557 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4558 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4559
4560 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4561 TG3_64BIT_REG_LOW, idx);
4562 work_mask &= ~RXD_OPAQUE_RING_STD;
4563 rx_std_posted = 0;
4564 }
1da177e4 4565next_pkt_nopost:
483ba50b 4566 sw_idx++;
6b31a515 4567 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4568
4569 /* Refresh hw_idx to see if there is new work */
4570 if (sw_idx == hw_idx) {
4571 hw_idx = tp->hw_status->idx[0].rx_producer;
4572 rmb();
4573 }
1da177e4
LT		 4574 }
4575
4576 /* ACK the status ring. */
483ba50b
MC		 4577 tp->rx_rcb_ptr = sw_idx;
4578 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4579
4580 /* Refill RX ring(s). */
4581 if (work_mask & RXD_OPAQUE_RING_STD) {
4582 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4583 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4584 sw_idx);
4585 }
4586 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4587 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4588 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4589 sw_idx);
4590 }
4591 mmiowb();
4592
4593 return received;
4594}
4595
6f535763 4596static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4597{
1da177e4 4598 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4599
1da177e4
LT		 4600 /* handle link change and other phy events */
4601 if (!(tp->tg3_flags &
4602 (TG3_FLAG_USE_LINKCHG_REG |
4603 TG3_FLAG_POLL_SERDES))) {
4604 if (sblk->status & SD_STATUS_LINK_CHG) {
4605 sblk->status = SD_STATUS_UPDATED |
4606 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4607 spin_lock(&tp->lock);
dd477003
MC		 4608 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4609 tw32_f(MAC_STATUS,
4610 (MAC_STATUS_SYNC_CHANGED |
4611 MAC_STATUS_CFG_CHANGED |
4612 MAC_STATUS_MI_COMPLETION |
4613 MAC_STATUS_LNKSTATE_CHANGED));
4614 udelay(40);
4615 } else
4616 tg3_setup_phy(tp, 0);
f47c11ee 4617 spin_unlock(&tp->lock);
1da177e4
LT		 4618 }
4619 }
4620
4621 /* run TX completion thread */
4622 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4623 tg3_tx(tp);
6f535763 4624 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4625 return work_done;
1da177e4
LT		 4626 }
4627
1da177e4
LT		 4628 /* run RX thread, within the bounds set by NAPI.
4629 * All RX "locking" is done by ensuring outside
bea3348e 4630 * code synchronizes with tg3->napi.poll()
1da177e4 4631 */
bea3348e 4632 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4633 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4634
6f535763
DM		 4635 return work_done;
4636}
4637
4638static int tg3_poll(struct napi_struct *napi, int budget)
4639{
4640 struct tg3 *tp = container_of(napi, struct tg3, napi);
4641 int work_done = 0;
4fd7ab59 4642 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4643
4644 while (1) {
4645 work_done = tg3_poll_work(tp, work_done, budget);
4646
4647 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4648 goto tx_recovery;
4649
4650 if (unlikely(work_done >= budget))
4651 break;
4652
4fd7ab59
MC		 4653 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4654 /* tp->last_tag is used in tg3_restart_ints() below
4655 * to tell the hw how much work has been processed,
4656 * so we must read it before checking for more work.
4657 */
4658 tp->last_tag = sblk->status_tag;
624f8e50 4659 tp->last_irq_tag = tp->last_tag;
4fd7ab59
MC		 4660 rmb();
4661 } else
4662 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4663
4fd7ab59 4664 if (likely(!tg3_has_work(tp))) {
288379f0 4665 napi_complete(napi);
6f535763
DM		 4666 tg3_restart_ints(tp);
4667 break;
4668 }
1da177e4
LT		 4669 }
4670
bea3348e 4671 return work_done;
6f535763
DM		 4672
4673tx_recovery:
4fd7ab59 4674 /* work_done is guaranteed to be less than budget. */
288379f0 4675 napi_complete(napi);
6f535763 4676 schedule_work(&tp->reset_task);
4fd7ab59 4677 return work_done;
1da177e4
LT		 4678}
4679
f47c11ee
DM		 4680static void tg3_irq_quiesce(struct tg3 *tp)
4681{
4682 BUG_ON(tp->irq_sync);
4683
4684 tp->irq_sync = 1;
4685 smp_mb();
4686
4687 synchronize_irq(tp->pdev->irq);
4688}
4689
4690static inline int tg3_irq_sync(struct tg3 *tp)
4691{
4692 return tp->irq_sync;
4693}
4694
4695/* Fully shutdown all tg3 driver activity elsewhere in the system.
4696 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4697 * with as well. Most of the time, this is not necessary except when
4698 * shutting down the device.
4699 */
4700static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4701{
46966545 4702 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4703 if (irq_sync)
4704 tg3_irq_quiesce(tp);
f47c11ee
DM		 4705}
4706
4707static inline void tg3_full_unlock(struct tg3 *tp)
4708{
f47c11ee
DM		 4709 spin_unlock_bh(&tp->lock);
4710}
4711
fcfa0a32
MC		 4712/* One-shot MSI handler - Chip automatically disables interrupt
4713 * after sending MSI so driver doesn't have to do it.
4714 */
7d12e780 4715static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4716{
4717 struct net_device *dev = dev_id;
4718 struct tg3 *tp = netdev_priv(dev);
4719
4720 prefetch(tp->hw_status);
4721 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4722
4723 if (likely(!tg3_irq_sync(tp)))
288379f0 4724 napi_schedule(&tp->napi);
fcfa0a32
MC		 4725
4726 return IRQ_HANDLED;
4727}
4728
88b06bc2
MC		 4729/* MSI ISR - No need to check for interrupt sharing and no need to
4730 * flush status block and interrupt mailbox. PCI ordering rules
4731 * guarantee that MSI will arrive after the status block.
4732 */
7d12e780 4733static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4734{
4735 struct net_device *dev = dev_id;
4736 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4737
61487480
MC		 4738 prefetch(tp->hw_status);
4739 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4740 /*
fac9b83e 4741 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4742 * chip-internal interrupt pending events.
fac9b83e 4743 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4744 * NIC to stop sending us irqs, engaging "in-intr-handler"
4745 * event coalescing.
4746 */
4747 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4748 if (likely(!tg3_irq_sync(tp)))
288379f0 4749 napi_schedule(&tp->napi);
61487480 4750
88b06bc2
MC		 4751 return IRQ_RETVAL(1);
4752}
4753
7d12e780 4754static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4755{
4756 struct net_device *dev = dev_id;
4757 struct tg3 *tp = netdev_priv(dev);
4758 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4759 unsigned int handled = 1;
4760
1da177e4
LT		 4761 /* In INTx mode, it is possible for the interrupt to arrive at
4762 * the CPU before the status block posted prior to the interrupt.
4763 * Reading the PCI State register will confirm whether the
4764 * interrupt is ours and will flush the status block.
4765 */
d18edcb2
MC		 4766 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4767 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4768 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4769 handled = 0;
f47c11ee 4770 goto out;
fac9b83e 4771 }
d18edcb2
MC		 4772 }
4773
4774 /*
4775 * Writing any value to intr-mbox-0 clears PCI INTA# and
4776 * chip-internal interrupt pending events.
4777 * Writing non-zero to intr-mbox-0 additional tells the
4778 * NIC to stop sending us irqs, engaging "in-intr-handler"
4779 * event coalescing.
c04cb347
MC		 4780 *
4781 * Flush the mailbox to de-assert the IRQ immediately to prevent
4782 * spurious interrupts. The flush impacts performance but
4783 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4784 */
c04cb347 4785 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4786 if (tg3_irq_sync(tp))
4787 goto out;
4788 sblk->status &= ~SD_STATUS_UPDATED;
4789 if (likely(tg3_has_work(tp))) {
4790 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4791 napi_schedule(&tp->napi);
d18edcb2
MC		 4792 } else {
4793 /* No work, shared interrupt perhaps? re-enable
4794 * interrupts, and flush that PCI write
4795 */
4796 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4797 0x00000000);
fac9b83e 4798 }
f47c11ee 4799out:
fac9b83e
DM		 4800 return IRQ_RETVAL(handled);
4801}
4802
7d12e780 4803static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4804{
4805 struct net_device *dev = dev_id;
4806 struct tg3 *tp = netdev_priv(dev);
4807 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4808 unsigned int handled = 1;
4809
fac9b83e
DM		 4810 /* In INTx mode, it is possible for the interrupt to arrive at
4811 * the CPU before the status block posted prior to the interrupt.
4812 * Reading the PCI State register will confirm whether the
4813 * interrupt is ours and will flush the status block.
4814 */
624f8e50 4815 if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
d18edcb2
MC		 4816 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4817 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4818 handled = 0;
f47c11ee 4819 goto out;
1da177e4 4820 }
d18edcb2
MC		 4821 }
4822
4823 /*
4824 * writing any value to intr-mbox-0 clears PCI INTA# and
4825 * chip-internal interrupt pending events.
4826 * writing non-zero to intr-mbox-0 additional tells the
4827 * NIC to stop sending us irqs, engaging "in-intr-handler"
4828 * event coalescing.
c04cb347
MC		 4829 *
4830 * Flush the mailbox to de-assert the IRQ immediately to prevent
4831 * spurious interrupts. The flush impacts performance but
4832 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4833 */
c04cb347 4834 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4835
4836 /*
4837 * In a shared interrupt configuration, sometimes other devices'
4838 * interrupts will scream. We record the current status tag here
4839 * so that the above check can report that the screaming interrupts
4840 * are unhandled. Eventually they will be silenced.
4841 */
4842 tp->last_irq_tag = sblk->status_tag;
4843
d18edcb2
MC		 4844 if (tg3_irq_sync(tp))
4845 goto out;
624f8e50
MC		 4846
4847 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4848
4849 napi_schedule(&tp->napi);
4850
f47c11ee 4851out:
1da177e4
LT		 4852 return IRQ_RETVAL(handled);
4853}
4854
7938109f 4855/* ISR for interrupt test */
7d12e780 4856static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4857{
4858 struct net_device *dev = dev_id;
4859 struct tg3 *tp = netdev_priv(dev);
4860 struct tg3_hw_status *sblk = tp->hw_status;
4861
f9804ddb
MC		 4862 if ((sblk->status & SD_STATUS_UPDATED) ||
4863 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4864 tg3_disable_ints(tp);
7938109f
MC		 4865 return IRQ_RETVAL(1);
4866 }
4867 return IRQ_RETVAL(0);
4868}
4869
8e7a22e3 4870static int tg3_init_hw(struct tg3 *, int);
944d980e 4871static int tg3_halt(struct tg3 *, int, int);
1da177e4 4872
b9ec6c1b
MC		 4873/* Restart hardware after configuration changes, self-test, etc.
4874 * Invoked with tp->lock held.
4875 */
4876static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4877 __releases(tp->lock)
4878 __acquires(tp->lock)
b9ec6c1b
MC		 4879{
4880 int err;
4881
4882 err = tg3_init_hw(tp, reset_phy);
4883 if (err) {
4884 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4885 "aborting.\n", tp->dev->name);
4886 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4887 tg3_full_unlock(tp);
4888 del_timer_sync(&tp->timer);
4889 tp->irq_sync = 0;
bea3348e 4890 napi_enable(&tp->napi);
b9ec6c1b
MC		 4891 dev_close(tp->dev);
4892 tg3_full_lock(tp, 0);
4893 }
4894 return err;
4895}
4896
1da177e4
LT		 4897#ifdef CONFIG_NET_POLL_CONTROLLER
4898static void tg3_poll_controller(struct net_device *dev)
4899{
88b06bc2
MC		 4900 struct tg3 *tp = netdev_priv(dev);
4901
7d12e780 4902 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4903}
4904#endif
4905
c4028958 4906static void tg3_reset_task(struct work_struct *work)
1da177e4 4907{
c4028958 4908 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4909 int err;
1da177e4
LT		 4910 unsigned int restart_timer;
4911
7faa006f 4912 tg3_full_lock(tp, 0);
7faa006f
MC		 4913
4914 if (!netif_running(tp->dev)) {
7faa006f
MC		 4915 tg3_full_unlock(tp);
4916 return;
4917 }
4918
4919 tg3_full_unlock(tp);
4920
b02fd9e3
MC		 4921 tg3_phy_stop(tp);
4922
1da177e4
LT		 4923 tg3_netif_stop(tp);
4924
f47c11ee 4925 tg3_full_lock(tp, 1);
1da177e4
LT		 4926
4927 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4928 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4929
df3e6548
MC		 4930 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4931 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4932 tp->write32_rx_mbox = tg3_write_flush_reg32;
4933 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4934 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4935 }
4936
944d980e 4937 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4938 err = tg3_init_hw(tp, 1);
4939 if (err)
b9ec6c1b 4940 goto out;
1da177e4
LT		 4941
4942 tg3_netif_start(tp);
4943
1da177e4
LT		 4944 if (restart_timer)
4945 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4946
b9ec6c1b 4947out:
7faa006f 4948 tg3_full_unlock(tp);
b02fd9e3
MC		 4949
4950 if (!err)
4951 tg3_phy_start(tp);
1da177e4
LT		 4952}
4953
b0408751
MC		 4954static void tg3_dump_short_state(struct tg3 *tp)
4955{
4956 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4957 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4958 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4959 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4960}
4961
1da177e4
LT		 4962static void tg3_tx_timeout(struct net_device *dev)
4963{
4964 struct tg3 *tp = netdev_priv(dev);
4965
b0408751 4966 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 4967 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4968 dev->name);
b0408751
MC		 4969 tg3_dump_short_state(tp);
4970 }
1da177e4
LT		 4971
4972 schedule_work(&tp->reset_task);
4973}
4974
c58ec932
MC		 4975/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4976static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4977{
4978 u32 base = (u32) mapping & 0xffffffff;
4979
4980 return ((base > 0xffffdcc0) &&
4981 (base + len + 8 < base));
4982}
4983
72f2afb8
MC		 4984/* Test for DMA addresses > 40-bit */
4985static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4986 int len)
4987{
4988#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 4989 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 4990 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 4991 return 0;
4992#else
4993 return 0;
4994#endif
4995}
4996
1da177e4
LT		 4997static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4998
72f2afb8
MC		 4999/* Workaround 4GB and 40-bit hardware DMA bugs. */
5000static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5001 u32 last_plus_one, u32 *start,
5002 u32 base_flags, u32 mss)
1da177e4 5003{
41588ba1 5004 struct sk_buff *new_skb;
c58ec932 5005 dma_addr_t new_addr = 0;
1da177e4 5006 u32 entry = *start;
c58ec932 5007 int i, ret = 0;
1da177e4 5008
41588ba1
MC		 5009 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5010 new_skb = skb_copy(skb, GFP_ATOMIC);
5011 else {
5012 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5013
5014 new_skb = skb_copy_expand(skb,
5015 skb_headroom(skb) + more_headroom,
5016 skb_tailroom(skb), GFP_ATOMIC);
5017 }
5018
1da177e4 5019 if (!new_skb) {
c58ec932
MC		 5020 ret = -1;
5021 } else {
5022 /* New SKB is guaranteed to be linear. */
5023 entry = *start;
90079ce8
DM		 5024 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5025 new_addr = skb_shinfo(new_skb)->dma_maps[0];
5026
c58ec932
MC		 5027 /* Make sure new skb does not cross any 4G boundaries.
5028 * Drop the packet if it does.
5029 */
90079ce8 5030 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5031 if (!ret)
5032 skb_dma_unmap(&tp->pdev->dev, new_skb,
5033 DMA_TO_DEVICE);
c58ec932
MC		 5034 ret = -1;
5035 dev_kfree_skb(new_skb);
5036 new_skb = NULL;
5037 } else {
5038 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5039 base_flags, 1 | (mss << 1));
5040 *start = NEXT_TX(entry);
5041 }
1da177e4
LT		 5042 }
5043
1da177e4
LT		 5044 /* Now clean up the sw ring entries. */
5045 i = 0;
5046 while (entry != last_plus_one) {
1da177e4
LT		 5047 if (i == 0) {
5048 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5049 } else {
5050 tp->tx_buffers[entry].skb = NULL;
5051 }
5052 entry = NEXT_TX(entry);
5053 i++;
5054 }
5055
90079ce8 5056 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5057 dev_kfree_skb(skb);
5058
c58ec932 5059 return ret;
1da177e4
LT		 5060}
5061
5062static void tg3_set_txd(struct tg3 *tp, int entry,
5063 dma_addr_t mapping, int len, u32 flags,
5064 u32 mss_and_is_end)
5065{
5066 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5067 int is_end = (mss_and_is_end & 0x1);
5068 u32 mss = (mss_and_is_end >> 1);
5069 u32 vlan_tag = 0;
5070
5071 if (is_end)
5072 flags |= TXD_FLAG_END;
5073 if (flags & TXD_FLAG_VLAN) {
5074 vlan_tag = flags >> 16;
5075 flags &= 0xffff;
5076 }
5077 vlan_tag |= (mss << TXD_MSS_SHIFT);
5078
5079 txd->addr_hi = ((u64) mapping >> 32);
5080 txd->addr_lo = ((u64) mapping & 0xffffffff);
5081 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5082 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5083}
5084
5a6f3074
MC		 5085/* hard_start_xmit for devices that don't have any bugs and
5086 * support TG3_FLG2_HW_TSO_2 only.
5087 */
1da177e4 5088static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5089{
5090 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5091 u32 len, entry, base_flags, mss;
90079ce8
DM		 5092 struct skb_shared_info *sp;
5093 dma_addr_t mapping;
5a6f3074
MC		 5094
5095 len = skb_headlen(skb);
5096
00b70504 5097 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5098 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5099 * interrupt. Furthermore, IRQ processing runs lockless so we have
5100 * no IRQ context deadlocks to worry about either. Rejoice!
5101 */
1b2a7205 5102 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5103 if (!netif_queue_stopped(dev)) {
5104 netif_stop_queue(dev);
5105
5106 /* This is a hard error, log it. */
5107 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5108 "queue awake!\n", dev->name);
5109 }
5a6f3074
MC		 5110 return NETDEV_TX_BUSY;
5111 }
5112
5113 entry = tp->tx_prod;
5114 base_flags = 0;
5a6f3074 5115 mss = 0;
c13e3713 5116 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5117 int tcp_opt_len, ip_tcp_len;
5118
5119 if (skb_header_cloned(skb) &&
5120 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5121 dev_kfree_skb(skb);
5122 goto out_unlock;
5123 }
5124
b0026624
MC		 5125 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5126 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5127 else {
eddc9ec5
ACM		 5128 struct iphdr *iph = ip_hdr(skb);
5129
ab6a5bb6 5130 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5131 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5132
eddc9ec5
ACM		 5133 iph->check = 0;
5134 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5135 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5136 }
5a6f3074
MC		 5137
5138 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5139 TXD_FLAG_CPU_POST_DMA);
5140
aa8223c7 5141 tcp_hdr(skb)->check = 0;
5a6f3074 5142
5a6f3074 5143 }
84fa7933 5144 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5145 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5146#if TG3_VLAN_TAG_USED
5147 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5148 base_flags |= (TXD_FLAG_VLAN |
5149 (vlan_tx_tag_get(skb) << 16));
5150#endif
5151
90079ce8
DM		 5152 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5153 dev_kfree_skb(skb);
5154 goto out_unlock;
5155 }
5156
5157 sp = skb_shinfo(skb);
5158
5159 mapping = sp->dma_maps[0];
5a6f3074
MC		 5160
5161 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5162
5163 tg3_set_txd(tp, entry, mapping, len, base_flags,
5164 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5165
5166 entry = NEXT_TX(entry);
5167
5168 /* Now loop through additional data fragments, and queue them. */
5169 if (skb_shinfo(skb)->nr_frags > 0) {
5170 unsigned int i, last;
5171
5172 last = skb_shinfo(skb)->nr_frags - 1;
5173 for (i = 0; i <= last; i++) {
5174 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5175
5176 len = frag->size;
90079ce8 5177 mapping = sp->dma_maps[i + 1];
5a6f3074 5178 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5179
5180 tg3_set_txd(tp, entry, mapping, len,
5181 base_flags, (i == last) | (mss << 1));
5182
5183 entry = NEXT_TX(entry);
5184 }
5185 }
5186
5187 /* Packets are ready, update Tx producer idx local and on card. */
5188 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5189
5190 tp->tx_prod = entry;
1b2a7205 5191 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5192 netif_stop_queue(dev);
42952231 5193 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5194 netif_wake_queue(tp->dev);
5195 }
5196
5197out_unlock:
5198 mmiowb();
5a6f3074
MC		 5199
5200 dev->trans_start = jiffies;
5201
5202 return NETDEV_TX_OK;
5203}
5204
52c0fd83
MC		 5205static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5206
5207/* Use GSO to workaround a rare TSO bug that may be triggered when the
5208 * TSO header is greater than 80 bytes.
5209 */
5210static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5211{
5212 struct sk_buff *segs, *nskb;
5213
5214 /* Estimate the number of fragments in the worst case */
1b2a7205 5215 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5216 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5217 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5218 return NETDEV_TX_BUSY;
5219
5220 netif_wake_queue(tp->dev);
52c0fd83
MC		 5221 }
5222
5223 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5224 if (IS_ERR(segs))
52c0fd83
MC		 5225 goto tg3_tso_bug_end;
5226
5227 do {
5228 nskb = segs;
5229 segs = segs->next;
5230 nskb->next = NULL;
5231 tg3_start_xmit_dma_bug(nskb, tp->dev);
5232 } while (segs);
5233
5234tg3_tso_bug_end:
5235 dev_kfree_skb(skb);
5236
5237 return NETDEV_TX_OK;
5238}
52c0fd83 5239
5a6f3074
MC		 5240/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5241 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5242 */
5243static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5244{
5245 struct tg3 *tp = netdev_priv(dev);
1da177e4 5246 u32 len, entry, base_flags, mss;
90079ce8 5247 struct skb_shared_info *sp;
1da177e4 5248 int would_hit_hwbug;
90079ce8 5249 dma_addr_t mapping;
1da177e4
LT		 5250
5251 len = skb_headlen(skb);
5252
00b70504 5253 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5254 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5255 * interrupt. Furthermore, IRQ processing runs lockless so we have
5256 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5257 */
1b2a7205 5258 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5259 if (!netif_queue_stopped(dev)) {
5260 netif_stop_queue(dev);
5261
5262 /* This is a hard error, log it. */
5263 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5264 "queue awake!\n", dev->name);
5265 }
1da177e4
LT		 5266 return NETDEV_TX_BUSY;
5267 }
5268
5269 entry = tp->tx_prod;
5270 base_flags = 0;
84fa7933 5271 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5272 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5273 mss = 0;
c13e3713 5274 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5275 struct iphdr *iph;
52c0fd83 5276 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5277
5278 if (skb_header_cloned(skb) &&
5279 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5280 dev_kfree_skb(skb);
5281 goto out_unlock;
5282 }
5283
ab6a5bb6 5284 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5285 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5286
52c0fd83
MC		 5287 hdr_len = ip_tcp_len + tcp_opt_len;
5288 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5289 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5290 return (tg3_tso_bug(tp, skb));
5291
1da177e4
LT		 5292 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5293 TXD_FLAG_CPU_POST_DMA);
5294
eddc9ec5
ACM		 5295 iph = ip_hdr(skb);
5296 iph->check = 0;
5297 iph->tot_len = htons(mss + hdr_len);
1da177e4 5298 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5299 tcp_hdr(skb)->check = 0;
1da177e4 5300 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5301 } else
5302 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5303 iph->daddr, 0,
5304 IPPROTO_TCP,
5305 0);
1da177e4
LT		 5306
5307 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5308 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5309 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5310 int tsflags;
5311
eddc9ec5 5312 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5313 mss |= (tsflags << 11);
5314 }
5315 } else {
eddc9ec5 5316 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5317 int tsflags;
5318
eddc9ec5 5319 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5320 base_flags |= tsflags << 12;
5321 }
5322 }
5323 }
1da177e4
LT		 5324#if TG3_VLAN_TAG_USED
5325 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5326 base_flags |= (TXD_FLAG_VLAN |
5327 (vlan_tx_tag_get(skb) << 16));
5328#endif
5329
90079ce8
DM		 5330 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5331 dev_kfree_skb(skb);
5332 goto out_unlock;
5333 }
5334
5335 sp = skb_shinfo(skb);
5336
5337 mapping = sp->dma_maps[0];
1da177e4
LT		 5338
5339 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5340
5341 would_hit_hwbug = 0;
5342
41588ba1
MC		 5343 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5344 would_hit_hwbug = 1;
5345 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5346 would_hit_hwbug = 1;
1da177e4
LT		 5347
5348 tg3_set_txd(tp, entry, mapping, len, base_flags,
5349 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5350
5351 entry = NEXT_TX(entry);
5352
5353 /* Now loop through additional data fragments, and queue them. */
5354 if (skb_shinfo(skb)->nr_frags > 0) {
5355 unsigned int i, last;
5356
5357 last = skb_shinfo(skb)->nr_frags - 1;
5358 for (i = 0; i <= last; i++) {
5359 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5360
5361 len = frag->size;
90079ce8 5362 mapping = sp->dma_maps[i + 1];
1da177e4
LT		 5363
5364 tp->tx_buffers[entry].skb = NULL;
1da177e4 5365
c58ec932
MC		 5366 if (tg3_4g_overflow_test(mapping, len))
5367 would_hit_hwbug = 1;
1da177e4 5368
72f2afb8
MC		 5369 if (tg3_40bit_overflow_test(tp, mapping, len))
5370 would_hit_hwbug = 1;
5371
1da177e4
LT		 5372 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5373 tg3_set_txd(tp, entry, mapping, len,
5374 base_flags, (i == last)|(mss << 1));
5375 else
5376 tg3_set_txd(tp, entry, mapping, len,
5377 base_flags, (i == last));
5378
5379 entry = NEXT_TX(entry);
5380 }
5381 }
5382
5383 if (would_hit_hwbug) {
5384 u32 last_plus_one = entry;
5385 u32 start;
1da177e4 5386
c58ec932
MC		 5387 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5388 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5389
5390 /* If the workaround fails due to memory/mapping
5391 * failure, silently drop this packet.
5392 */
72f2afb8 5393 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5394 &start, base_flags, mss))
1da177e4
LT		 5395 goto out_unlock;
5396
5397 entry = start;
5398 }
5399
5400 /* Packets are ready, update Tx producer idx local and on card. */
5401 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5402
5403 tp->tx_prod = entry;
1b2a7205 5404 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5405 netif_stop_queue(dev);
42952231 5406 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5407 netif_wake_queue(tp->dev);
5408 }
1da177e4
LT		 5409
5410out_unlock:
5411 mmiowb();
1da177e4
LT		 5412
5413 dev->trans_start = jiffies;
5414
5415 return NETDEV_TX_OK;
5416}
5417
5418static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5419 int new_mtu)
5420{
5421 dev->mtu = new_mtu;
5422
ef7f5ec0 5423 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5424 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5425 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5426 ethtool_op_set_tso(dev, 0);
5427 }
5428 else
5429 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5430 } else {
a4e2b347 5431 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5432 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5433 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5434 }
1da177e4
LT		 5435}
5436
5437static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5438{
5439 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5440 int err;
1da177e4
LT		 5441
5442 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5443 return -EINVAL;
5444
5445 if (!netif_running(dev)) {
5446 /* We'll just catch it later when the
5447 * device is up'd.
5448 */
5449 tg3_set_mtu(dev, tp, new_mtu);
5450 return 0;
5451 }
5452
b02fd9e3
MC		 5453 tg3_phy_stop(tp);
5454
1da177e4 5455 tg3_netif_stop(tp);
f47c11ee
DM		 5456
5457 tg3_full_lock(tp, 1);
1da177e4 5458
944d980e 5459 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5460
5461 tg3_set_mtu(dev, tp, new_mtu);
5462
b9ec6c1b 5463 err = tg3_restart_hw(tp, 0);
1da177e4 5464
b9ec6c1b
MC		 5465 if (!err)
5466 tg3_netif_start(tp);
1da177e4 5467
f47c11ee 5468 tg3_full_unlock(tp);
1da177e4 5469
b02fd9e3
MC		 5470 if (!err)
5471 tg3_phy_start(tp);
5472
b9ec6c1b 5473 return err;
1da177e4
LT		 5474}
5475
5476/* Free up pending packets in all rx/tx rings.
5477 *
5478 * The chip has been shut down and the driver detached from
5479 * the networking, so no interrupts or new tx packets will
5480 * end up in the driver. tp->{tx,}lock is not held and we are not
5481 * in an interrupt context and thus may sleep.
5482 */
5483static void tg3_free_rings(struct tg3 *tp)
5484{
5485 struct ring_info *rxp;
5486 int i;
5487
5488 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5489 rxp = &tp->rx_std_buffers[i];
5490
5491 if (rxp->skb == NULL)
5492 continue;
5493 pci_unmap_single(tp->pdev,
5494 pci_unmap_addr(rxp, mapping),
7e72aad4 5495 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 5496 PCI_DMA_FROMDEVICE);
5497 dev_kfree_skb_any(rxp->skb);
5498 rxp->skb = NULL;
5499 }
5500
5501 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5502 rxp = &tp->rx_jumbo_buffers[i];
5503
5504 if (rxp->skb == NULL)
5505 continue;
5506 pci_unmap_single(tp->pdev,
5507 pci_unmap_addr(rxp, mapping),
5508 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5509 PCI_DMA_FROMDEVICE);
5510 dev_kfree_skb_any(rxp->skb);
5511 rxp->skb = NULL;
5512 }
5513
5514 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5515 struct tx_ring_info *txp;
5516 struct sk_buff *skb;
1da177e4
LT		 5517
5518 txp = &tp->tx_buffers[i];
5519 skb = txp->skb;
5520
5521 if (skb == NULL) {
5522 i++;
5523 continue;
5524 }
5525
90079ce8 5526 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5527
90079ce8 5528 txp->skb = NULL;
1da177e4 5529
90079ce8 5530 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5531
5532 dev_kfree_skb_any(skb);
5533 }
5534}
5535
5536/* Initialize tx/rx rings for packet processing.
5537 *
5538 * The chip has been shut down and the driver detached from
5539 * the networking, so no interrupts or new tx packets will
5540 * end up in the driver. tp->{tx,}lock are held and thus
5541 * we may not sleep.
5542 */
32d8c572 5543static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 5544{
5545 u32 i;
5546
5547 /* Free up all the SKBs. */
5548 tg3_free_rings(tp);
5549
5550 /* Zero out all descriptors. */
5551 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5552 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5553 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5554 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5555
7e72aad4 5556 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 5557 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 5558 (tp->dev->mtu > ETH_DATA_LEN))
5559 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5560
1da177e4
LT		 5561 /* Initialize invariants of the rings, we only set this
5562 * stuff once. This works because the card does not
5563 * write into the rx buffer posting rings.
5564 */
5565 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5566 struct tg3_rx_buffer_desc *rxd;
5567
5568 rxd = &tp->rx_std[i];
7e72aad4 5569 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 5570 << RXD_LEN_SHIFT;
5571 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5572 rxd->opaque = (RXD_OPAQUE_RING_STD |
5573 (i << RXD_OPAQUE_INDEX_SHIFT));
5574 }
5575
0f893dc6 5576 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5577 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5578 struct tg3_rx_buffer_desc *rxd;
5579
5580 rxd = &tp->rx_jumbo[i];
5581 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5582 << RXD_LEN_SHIFT;
5583 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5584 RXD_FLAG_JUMBO;
5585 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5586 (i << RXD_OPAQUE_INDEX_SHIFT));
5587 }
5588 }
5589
5590 /* Now allocate fresh SKBs for each rx ring. */
5591 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5592 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5593 printk(KERN_WARNING PFX
5594 "%s: Using a smaller RX standard ring, "
5595 "only %d out of %d buffers were allocated "
5596 "successfully.\n",
5597 tp->dev->name, i, tp->rx_pending);
5598 if (i == 0)
5599 return -ENOMEM;
5600 tp->rx_pending = i;
1da177e4 5601 break;
32d8c572 5602 }
1da177e4
LT		 5603 }
5604
0f893dc6 5605 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5606 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5607 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5608 -1, i) < 0) {
5609 printk(KERN_WARNING PFX
5610 "%s: Using a smaller RX jumbo ring, "
5611 "only %d out of %d buffers were "
5612 "allocated successfully.\n",
5613 tp->dev->name, i, tp->rx_jumbo_pending);
5614 if (i == 0) {
5615 tg3_free_rings(tp);
5616 return -ENOMEM;
5617 }
5618 tp->rx_jumbo_pending = i;
1da177e4 5619 break;
32d8c572 5620 }
1da177e4
LT		 5621 }
5622 }
32d8c572 5623 return 0;
1da177e4
LT		 5624}
5625
5626/*
5627 * Must not be invoked with interrupt sources disabled and
5628 * the hardware shutdown down.
5629 */
5630static void tg3_free_consistent(struct tg3 *tp)
5631{
b4558ea9
JJ		 5632 kfree(tp->rx_std_buffers);
5633 tp->rx_std_buffers = NULL;
1da177e4
LT		 5634 if (tp->rx_std) {
5635 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5636 tp->rx_std, tp->rx_std_mapping);
5637 tp->rx_std = NULL;
5638 }
5639 if (tp->rx_jumbo) {
5640 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5641 tp->rx_jumbo, tp->rx_jumbo_mapping);
5642 tp->rx_jumbo = NULL;
5643 }
5644 if (tp->rx_rcb) {
5645 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5646 tp->rx_rcb, tp->rx_rcb_mapping);
5647 tp->rx_rcb = NULL;
5648 }
5649 if (tp->tx_ring) {
5650 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5651 tp->tx_ring, tp->tx_desc_mapping);
5652 tp->tx_ring = NULL;
5653 }
5654 if (tp->hw_status) {
5655 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5656 tp->hw_status, tp->status_mapping);
5657 tp->hw_status = NULL;
5658 }
5659 if (tp->hw_stats) {
5660 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5661 tp->hw_stats, tp->stats_mapping);
5662 tp->hw_stats = NULL;
5663 }
5664}
5665
5666/*
5667 * Must not be invoked with interrupt sources disabled and
5668 * the hardware shutdown down. Can sleep.
5669 */
5670static int tg3_alloc_consistent(struct tg3 *tp)
5671{
bd2b3343 5672 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5673 (TG3_RX_RING_SIZE +
5674 TG3_RX_JUMBO_RING_SIZE)) +
5675 (sizeof(struct tx_ring_info) *
5676 TG3_TX_RING_SIZE),
5677 GFP_KERNEL);
5678 if (!tp->rx_std_buffers)
5679 return -ENOMEM;
5680
1da177e4
LT		 5681 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5682 tp->tx_buffers = (struct tx_ring_info *)
5683 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5684
5685 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5686 &tp->rx_std_mapping);
5687 if (!tp->rx_std)
5688 goto err_out;
5689
5690 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5691 &tp->rx_jumbo_mapping);
5692
5693 if (!tp->rx_jumbo)
5694 goto err_out;
5695
5696 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5697 &tp->rx_rcb_mapping);
5698 if (!tp->rx_rcb)
5699 goto err_out;
5700
5701 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5702 &tp->tx_desc_mapping);
5703 if (!tp->tx_ring)
5704 goto err_out;
5705
5706 tp->hw_status = pci_alloc_consistent(tp->pdev,
5707 TG3_HW_STATUS_SIZE,
5708 &tp->status_mapping);
5709 if (!tp->hw_status)
5710 goto err_out;
5711
5712 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5713 sizeof(struct tg3_hw_stats),
5714 &tp->stats_mapping);
5715 if (!tp->hw_stats)
5716 goto err_out;
5717
5718 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5719 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5720
5721 return 0;
5722
5723err_out:
5724 tg3_free_consistent(tp);
5725 return -ENOMEM;
5726}
5727
5728#define MAX_WAIT_CNT 1000
5729
5730/* To stop a block, clear the enable bit and poll till it
5731 * clears. tp->lock is held.
5732 */
b3b7d6be 5733static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5734{
5735 unsigned int i;
5736 u32 val;
5737
5738 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5739 switch (ofs) {
5740 case RCVLSC_MODE:
5741 case DMAC_MODE:
5742 case MBFREE_MODE:
5743 case BUFMGR_MODE:
5744 case MEMARB_MODE:
5745 /* We can't enable/disable these bits of the
5746 * 5705/5750, just say success.
5747 */
5748 return 0;
5749
5750 default:
5751 break;
855e1111 5752 }
1da177e4
LT		 5753 }
5754
5755 val = tr32(ofs);
5756 val &= ~enable_bit;
5757 tw32_f(ofs, val);
5758
5759 for (i = 0; i < MAX_WAIT_CNT; i++) {
5760 udelay(100);
5761 val = tr32(ofs);
5762 if ((val & enable_bit) == 0)
5763 break;
5764 }
5765
b3b7d6be 5766 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5767 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5768 "ofs=%lx enable_bit=%x\n",
5769 ofs, enable_bit);
5770 return -ENODEV;
5771 }
5772
5773 return 0;
5774}
5775
5776/* tp->lock is held. */
b3b7d6be 5777static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5778{
5779 int i, err;
5780
5781 tg3_disable_ints(tp);
5782
5783 tp->rx_mode &= ~RX_MODE_ENABLE;
5784 tw32_f(MAC_RX_MODE, tp->rx_mode);
5785 udelay(10);
5786
b3b7d6be
DM		 5787 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5788 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5789 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5790 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5791 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5792 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5793
5794 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5795 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5796 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5797 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5798 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5799 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5800 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5801
5802 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5803 tw32_f(MAC_MODE, tp->mac_mode);
5804 udelay(40);
5805
5806 tp->tx_mode &= ~TX_MODE_ENABLE;
5807 tw32_f(MAC_TX_MODE, tp->tx_mode);
5808
5809 for (i = 0; i < MAX_WAIT_CNT; i++) {
5810 udelay(100);
5811 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5812 break;
5813 }
5814 if (i >= MAX_WAIT_CNT) {
5815 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5816 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5817 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5818 err |= -ENODEV;
1da177e4
LT		 5819 }
5820
e6de8ad1 5821 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5822 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5823 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5824
5825 tw32(FTQ_RESET, 0xffffffff);
5826 tw32(FTQ_RESET, 0x00000000);
5827
b3b7d6be
DM		 5828 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5829 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5830
5831 if (tp->hw_status)
5832 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5833 if (tp->hw_stats)
5834 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5835
1da177e4
LT		 5836 return err;
5837}
5838
0d3031d9
MC		 5839static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5840{
5841 int i;
5842 u32 apedata;
5843
5844 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5845 if (apedata != APE_SEG_SIG_MAGIC)
5846 return;
5847
5848 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5849 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5850 return;
5851
5852 /* Wait for up to 1 millisecond for APE to service previous event. */
5853 for (i = 0; i < 10; i++) {
5854 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5855 return;
5856
5857 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5858
5859 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5860 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5861 event | APE_EVENT_STATUS_EVENT_PENDING);
5862
5863 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5864
5865 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5866 break;
5867
5868 udelay(100);
5869 }
5870
5871 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5872 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5873}
5874
5875static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5876{
5877 u32 event;
5878 u32 apedata;
5879
5880 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5881 return;
5882
5883 switch (kind) {
5884 case RESET_KIND_INIT:
5885 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5886 APE_HOST_SEG_SIG_MAGIC);
5887 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5888 APE_HOST_SEG_LEN_MAGIC);
5889 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5890 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5891 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5892 APE_HOST_DRIVER_ID_MAGIC);
5893 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5894 APE_HOST_BEHAV_NO_PHYLOCK);
5895
5896 event = APE_EVENT_STATUS_STATE_START;
5897 break;
5898 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5899 /* With the interface we are currently using,
5900 * APE does not track driver state. Wiping
5901 * out the HOST SEGMENT SIGNATURE forces
5902 * the APE to assume OS absent status.
5903 */
5904 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5905
0d3031d9
MC		 5906 event = APE_EVENT_STATUS_STATE_UNLOAD;
5907 break;
5908 case RESET_KIND_SUSPEND:
5909 event = APE_EVENT_STATUS_STATE_SUSPEND;
5910 break;
5911 default:
5912 return;
5913 }
5914
5915 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5916
5917 tg3_ape_send_event(tp, event);
5918}
5919
1da177e4
LT		 5920/* tp->lock is held. */
5921static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5922{
f49639e6
DM		 5923 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5924 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5925
5926 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5927 switch (kind) {
5928 case RESET_KIND_INIT:
5929 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5930 DRV_STATE_START);
5931 break;
5932
5933 case RESET_KIND_SHUTDOWN:
5934 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5935 DRV_STATE_UNLOAD);
5936 break;
5937
5938 case RESET_KIND_SUSPEND:
5939 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5940 DRV_STATE_SUSPEND);
5941 break;
5942
5943 default:
5944 break;
855e1111 5945 }
1da177e4 5946 }
0d3031d9
MC		 5947
5948 if (kind == RESET_KIND_INIT ||
5949 kind == RESET_KIND_SUSPEND)
5950 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5951}
5952
5953/* tp->lock is held. */
5954static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5955{
5956 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5957 switch (kind) {
5958 case RESET_KIND_INIT:
5959 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5960 DRV_STATE_START_DONE);
5961 break;
5962
5963 case RESET_KIND_SHUTDOWN:
5964 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5965 DRV_STATE_UNLOAD_DONE);
5966 break;
5967
5968 default:
5969 break;
855e1111 5970 }
1da177e4 5971 }
0d3031d9
MC		 5972
5973 if (kind == RESET_KIND_SHUTDOWN)
5974 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5975}
5976
5977/* tp->lock is held. */
5978static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5979{
5980 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5981 switch (kind) {
5982 case RESET_KIND_INIT:
5983 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5984 DRV_STATE_START);
5985 break;
5986
5987 case RESET_KIND_SHUTDOWN:
5988 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5989 DRV_STATE_UNLOAD);
5990 break;
5991
5992 case RESET_KIND_SUSPEND:
5993 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5994 DRV_STATE_SUSPEND);
5995 break;
5996
5997 default:
5998 break;
855e1111 5999 }
1da177e4
LT		 6000 }
6001}
6002
7a6f4369
MC		 6003static int tg3_poll_fw(struct tg3 *tp)
6004{
6005 int i;
6006 u32 val;
6007
b5d3772c 6008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6009 /* Wait up to 20ms for init done. */
6010 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6011 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6012 return 0;
0ccead18 6013 udelay(100);
b5d3772c
MC		 6014 }
6015 return -ENODEV;
6016 }
6017
7a6f4369
MC		 6018 /* Wait for firmware initialization to complete. */
6019 for (i = 0; i < 100000; i++) {
6020 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6021 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6022 break;
6023 udelay(10);
6024 }
6025
6026 /* Chip might not be fitted with firmware. Some Sun onboard
6027 * parts are configured like that. So don't signal the timeout
6028 * of the above loop as an error, but do report the lack of
6029 * running firmware once.
6030 */
6031 if (i >= 100000 &&
6032 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6033 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6034
6035 printk(KERN_INFO PFX "%s: No firmware running.\n",
6036 tp->dev->name);
6037 }
6038
6039 return 0;
6040}
6041
ee6a99b5
MC		 6042/* Save PCI command register before chip reset */
6043static void tg3_save_pci_state(struct tg3 *tp)
6044{
8a6eac90 6045 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6046}
6047
6048/* Restore PCI state after chip reset */
6049static void tg3_restore_pci_state(struct tg3 *tp)
6050{
6051 u32 val;
6052
6053 /* Re-enable indirect register accesses. */
6054 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6055 tp->misc_host_ctrl);
6056
6057 /* Set MAX PCI retry to zero. */
6058 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6059 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6060 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6061 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6062 /* Allow reads and writes to the APE register and memory space. */
6063 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6064 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6065 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6066 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6067
8a6eac90 6068 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6069
fcb389df
MC		 6070 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6071 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6072 pcie_set_readrq(tp->pdev, 4096);
6073 else {
6074 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6075 tp->pci_cacheline_sz);
6076 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6077 tp->pci_lat_timer);
6078 }
114342f2 6079 }
5f5c51e3 6080
ee6a99b5 6081 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6082 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6083 u16 pcix_cmd;
6084
6085 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6086 &pcix_cmd);
6087 pcix_cmd &= ~PCI_X_CMD_ERO;
6088 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6089 pcix_cmd);
6090 }
ee6a99b5
MC		 6091
6092 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6093
6094 /* Chip reset on 5780 will reset MSI enable bit,
6095 * so need to restore it.
6096 */
6097 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6098 u16 ctrl;
6099
6100 pci_read_config_word(tp->pdev,
6101 tp->msi_cap + PCI_MSI_FLAGS,
6102 &ctrl);
6103 pci_write_config_word(tp->pdev,
6104 tp->msi_cap + PCI_MSI_FLAGS,
6105 ctrl | PCI_MSI_FLAGS_ENABLE);
6106 val = tr32(MSGINT_MODE);
6107 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6108 }
6109 }
6110}
6111
1da177e4
LT		 6112static void tg3_stop_fw(struct tg3 *);
6113
6114/* tp->lock is held. */
6115static int tg3_chip_reset(struct tg3 *tp)
6116{
6117 u32 val;
1ee582d8 6118 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6119 int err;
1da177e4 6120
f49639e6
DM		 6121 tg3_nvram_lock(tp);
6122
158d7abd
MC		 6123 tg3_mdio_stop(tp);
6124
77b483f1
MC		 6125 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6126
f49639e6
DM		 6127 /* No matching tg3_nvram_unlock() after this because
6128 * chip reset below will undo the nvram lock.
6129 */
6130 tp->nvram_lock_cnt = 0;
1da177e4 6131
ee6a99b5
MC		 6132 /* GRC_MISC_CFG core clock reset will clear the memory
6133 * enable bit in PCI register 4 and the MSI enable bit
6134 * on some chips, so we save relevant registers here.
6135 */
6136 tg3_save_pci_state(tp);
6137
d9ab5ad1 6138 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6139 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6140 tw32(GRC_FASTBOOT_PC, 0);
6141
1da177e4
LT		 6142 /*
6143 * We must avoid the readl() that normally takes place.
6144 * It locks machines, causes machine checks, and other
6145 * fun things. So, temporarily disable the 5701
6146 * hardware workaround, while we do the reset.
6147 */
1ee582d8
MC		 6148 write_op = tp->write32;
6149 if (write_op == tg3_write_flush_reg32)
6150 tp->write32 = tg3_write32;
1da177e4 6151
d18edcb2
MC		 6152 /* Prevent the irq handler from reading or writing PCI registers
6153 * during chip reset when the memory enable bit in the PCI command
6154 * register may be cleared. The chip does not generate interrupt
6155 * at this time, but the irq handler may still be called due to irq
6156 * sharing or irqpoll.
6157 */
6158 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6159 if (tp->hw_status) {
6160 tp->hw_status->status = 0;
6161 tp->hw_status->status_tag = 0;
6162 }
d18edcb2 6163 tp->last_tag = 0;
624f8e50 6164 tp->last_irq_tag = 0;
d18edcb2
MC		 6165 smp_mb();
6166 synchronize_irq(tp->pdev->irq);
6167
1da177e4
LT		 6168 /* do the reset */
6169 val = GRC_MISC_CFG_CORECLK_RESET;
6170
6171 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6172 if (tr32(0x7e2c) == 0x60) {
6173 tw32(0x7e2c, 0x20);
6174 }
6175 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6176 tw32(GRC_MISC_CFG, (1 << 29));
6177 val |= (1 << 29);
6178 }
6179 }
6180
b5d3772c
MC		 6181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6182 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6183 tw32(GRC_VCPU_EXT_CTRL,
6184 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6185 }
6186
1da177e4
LT		 6187 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6188 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6189 tw32(GRC_MISC_CFG, val);
6190
1ee582d8
MC		 6191 /* restore 5701 hardware bug workaround write method */
6192 tp->write32 = write_op;
1da177e4
LT		 6193
6194 /* Unfortunately, we have to delay before the PCI read back.
6195 * Some 575X chips even will not respond to a PCI cfg access
6196 * when the reset command is given to the chip.
6197 *
6198 * How do these hardware designers expect things to work
6199 * properly if the PCI write is posted for a long period
6200 * of time? It is always necessary to have some method by
6201 * which a register read back can occur to push the write
6202 * out which does the reset.
6203 *
6204 * For most tg3 variants the trick below was working.
6205 * Ho hum...
6206 */
6207 udelay(120);
6208
6209 /* Flush PCI posted writes. The normal MMIO registers
6210 * are inaccessible at this time so this is the only
6211 * way to make this reliably (actually, this is no longer
6212 * the case, see above). I tried to use indirect
6213 * register read/write but this upset some 5701 variants.
6214 */
6215 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6216
6217 udelay(120);
6218
5e7dfd0f 6219 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
1da177e4
LT		 6220 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6221 int i;
6222 u32 cfg_val;
6223
6224 /* Wait for link training to complete. */
6225 for (i = 0; i < 5000; i++)
6226 udelay(100);
6227
6228 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6229 pci_write_config_dword(tp->pdev, 0xc4,
6230 cfg_val | (1 << 15));
6231 }
5e7dfd0f
MC		 6232
6233 /* Set PCIE max payload size to 128 bytes and
6234 * clear the "no snoop" and "relaxed ordering" bits.
6235 */
6236 pci_write_config_word(tp->pdev,
6237 tp->pcie_cap + PCI_EXP_DEVCTL,
6238 0);
6239
6240 pcie_set_readrq(tp->pdev, 4096);
6241
6242 /* Clear error status */
6243 pci_write_config_word(tp->pdev,
6244 tp->pcie_cap + PCI_EXP_DEVSTA,
6245 PCI_EXP_DEVSTA_CED |
6246 PCI_EXP_DEVSTA_NFED |
6247 PCI_EXP_DEVSTA_FED |
6248 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6249 }
6250
ee6a99b5 6251 tg3_restore_pci_state(tp);
1da177e4 6252
d18edcb2
MC		 6253 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6254
ee6a99b5
MC		 6255 val = 0;
6256 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6257 val = tr32(MEMARB_MODE);
ee6a99b5 6258 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6259
6260 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6261 tg3_stop_fw(tp);
6262 tw32(0x5000, 0x400);
6263 }
6264
6265 tw32(GRC_MODE, tp->grc_mode);
6266
6267 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6268 val = tr32(0xc4);
1da177e4
LT		 6269
6270 tw32(0xc4, val | (1 << 15));
6271 }
6272
6273 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6274 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6275 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6276 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6277 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6278 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6279 }
6280
6281 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6282 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6283 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6284 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6285 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6286 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6287 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6288 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6289 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6290 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6291 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6292 } else
6293 tw32_f(MAC_MODE, 0);
6294 udelay(40);
6295
158d7abd
MC		 6296 tg3_mdio_start(tp);
6297
77b483f1
MC		 6298 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6299
7a6f4369
MC		 6300 err = tg3_poll_fw(tp);
6301 if (err)
6302 return err;
1da177e4
LT		 6303
6304 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6305 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6306 val = tr32(0x7c00);
1da177e4
LT		 6307
6308 tw32(0x7c00, val | (1 << 25));
6309 }
6310
6311 /* Reprobe ASF enable state. */
6312 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6313 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6314 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6315 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6316 u32 nic_cfg;
6317
6318 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6319 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6320 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6321 tp->last_event_jiffies = jiffies;
cbf46853 6322 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6323 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6324 }
6325 }
6326
6327 return 0;
6328}
6329
6330/* tp->lock is held. */
6331static void tg3_stop_fw(struct tg3 *tp)
6332{
0d3031d9
MC		 6333 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6334 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6335 /* Wait for RX cpu to ACK the previous event. */
6336 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6337
6338 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6339
6340 tg3_generate_fw_event(tp);
1da177e4 6341
7c5026aa
MC		 6342 /* Wait for RX cpu to ACK this event. */
6343 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6344 }
6345}
6346
6347/* tp->lock is held. */
944d980e 6348static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6349{
6350 int err;
6351
6352 tg3_stop_fw(tp);
6353
944d980e 6354 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6355
b3b7d6be 6356 tg3_abort_hw(tp, silent);
1da177e4
LT		 6357 err = tg3_chip_reset(tp);
6358
944d980e
MC		 6359 tg3_write_sig_legacy(tp, kind);
6360 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6361
6362 if (err)
6363 return err;
6364
6365 return 0;
6366}
6367
1da177e4
LT		 6368#define RX_CPU_SCRATCH_BASE 0x30000
6369#define RX_CPU_SCRATCH_SIZE 0x04000
6370#define TX_CPU_SCRATCH_BASE 0x34000
6371#define TX_CPU_SCRATCH_SIZE 0x04000
6372
6373/* tp->lock is held. */
6374static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6375{
6376 int i;
6377
5d9428de
ES		 6378 BUG_ON(offset == TX_CPU_BASE &&
6379 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6380
b5d3772c
MC		 6381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6382 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6383
6384 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6385 return 0;
6386 }
1da177e4
LT		 6387 if (offset == RX_CPU_BASE) {
6388 for (i = 0; i < 10000; i++) {
6389 tw32(offset + CPU_STATE, 0xffffffff);
6390 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6391 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6392 break;
6393 }
6394
6395 tw32(offset + CPU_STATE, 0xffffffff);
6396 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6397 udelay(10);
6398 } else {
6399 for (i = 0; i < 10000; i++) {
6400 tw32(offset + CPU_STATE, 0xffffffff);
6401 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6402 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6403 break;
6404 }
6405 }
6406
6407 if (i >= 10000) {
6408 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6409 "and %s CPU\n",
6410 tp->dev->name,
6411 (offset == RX_CPU_BASE ? "RX" : "TX"));
6412 return -ENODEV;
6413 }
ec41c7df
MC		 6414
6415 /* Clear firmware's nvram arbitration. */
6416 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6417 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6418 return 0;
6419}
6420
6421struct fw_info {
077f849d
JSR		 6422 unsigned int fw_base;
6423 unsigned int fw_len;
6424 const __be32 *fw_data;
1da177e4
LT		 6425};
6426
6427/* tp->lock is held. */
6428static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6429 int cpu_scratch_size, struct fw_info *info)
6430{
ec41c7df 6431 int err, lock_err, i;
1da177e4
LT		 6432 void (*write_op)(struct tg3 *, u32, u32);
6433
6434 if (cpu_base == TX_CPU_BASE &&
6435 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6436 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6437 "TX cpu firmware on %s which is 5705.\n",
6438 tp->dev->name);
6439 return -EINVAL;
6440 }
6441
6442 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6443 write_op = tg3_write_mem;
6444 else
6445 write_op = tg3_write_indirect_reg32;
6446
1b628151
MC		 6447 /* It is possible that bootcode is still loading at this point.
6448 * Get the nvram lock first before halting the cpu.
6449 */
ec41c7df 6450 lock_err = tg3_nvram_lock(tp);
1da177e4 6451 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6452 if (!lock_err)
6453 tg3_nvram_unlock(tp);
1da177e4
LT		 6454 if (err)
6455 goto out;
6456
6457 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6458 write_op(tp, cpu_scratch_base + i, 0);
6459 tw32(cpu_base + CPU_STATE, 0xffffffff);
6460 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6461 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6462 write_op(tp, (cpu_scratch_base +
077f849d 6463 (info->fw_base & 0xffff) +
1da177e4 6464 (i * sizeof(u32))),
077f849d 6465 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6466
6467 err = 0;
6468
6469out:
1da177e4
LT		 6470 return err;
6471}
6472
6473/* tp->lock is held. */
6474static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6475{
6476 struct fw_info info;
077f849d 6477 const __be32 *fw_data;
1da177e4
LT		 6478 int err, i;
6479
077f849d
JSR		 6480 fw_data = (void *)tp->fw->data;
6481
6482 /* Firmware blob starts with version numbers, followed by
6483 start address and length. We are setting complete length.
6484 length = end_address_of_bss - start_address_of_text.
6485 Remainder is the blob to be loaded contiguously
6486 from start address. */
6487
6488 info.fw_base = be32_to_cpu(fw_data[1]);
6489 info.fw_len = tp->fw->size - 12;
6490 info.fw_data = &fw_data[3];
1da177e4
LT		 6491
6492 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6493 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6494 &info);
6495 if (err)
6496 return err;
6497
6498 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6499 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6500 &info);
6501 if (err)
6502 return err;
6503
6504 /* Now startup only the RX cpu. */
6505 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6506 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6507
6508 for (i = 0; i < 5; i++) {
077f849d 6509 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6510 break;
6511 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6512 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6513 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6514 udelay(1000);
6515 }
6516 if (i >= 5) {
6517 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6518 "to set RX CPU PC, is %08x should be %08x\n",
6519 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6520 info.fw_base);
1da177e4
LT		 6521 return -ENODEV;
6522 }
6523 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6524 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6525
6526 return 0;
6527}
6528
1da177e4 6529/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6530
6531/* tp->lock is held. */
6532static int tg3_load_tso_firmware(struct tg3 *tp)
6533{
6534 struct fw_info info;
077f849d 6535 const __be32 *fw_data;
1da177e4
LT		 6536 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6537 int err, i;
6538
6539 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6540 return 0;
6541
077f849d
JSR		 6542 fw_data = (void *)tp->fw->data;
6543
6544 /* Firmware blob starts with version numbers, followed by
6545 start address and length. We are setting complete length.
6546 length = end_address_of_bss - start_address_of_text.
6547 Remainder is the blob to be loaded contiguously
6548 from start address. */
6549
6550 info.fw_base = be32_to_cpu(fw_data[1]);
6551 cpu_scratch_size = tp->fw_len;
6552 info.fw_len = tp->fw->size - 12;
6553 info.fw_data = &fw_data[3];
6554
1da177e4 6555 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6556 cpu_base = RX_CPU_BASE;
6557 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6558 } else {
1da177e4
LT		 6559 cpu_base = TX_CPU_BASE;
6560 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6561 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6562 }
6563
6564 err = tg3_load_firmware_cpu(tp, cpu_base,
6565 cpu_scratch_base, cpu_scratch_size,
6566 &info);
6567 if (err)
6568 return err;
6569
6570 /* Now startup the cpu. */
6571 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6572 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6573
6574 for (i = 0; i < 5; i++) {
077f849d 6575 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6576 break;
6577 tw32(cpu_base + CPU_STATE, 0xffffffff);
6578 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6579 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6580 udelay(1000);
6581 }
6582 if (i >= 5) {
6583 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6584 "to set CPU PC, is %08x should be %08x\n",
6585 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6586 info.fw_base);
1da177e4
LT		 6587 return -ENODEV;
6588 }
6589 tw32(cpu_base + CPU_STATE, 0xffffffff);
6590 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6591 return 0;
6592}
6593
1da177e4 6594
1da177e4
LT		 6595static int tg3_set_mac_addr(struct net_device *dev, void *p)
6596{
6597 struct tg3 *tp = netdev_priv(dev);
6598 struct sockaddr *addr = p;
986e0aeb 6599 int err = 0, skip_mac_1 = 0;
1da177e4 6600
f9804ddb
MC		 6601 if (!is_valid_ether_addr(addr->sa_data))
6602 return -EINVAL;
6603
1da177e4
LT		 6604 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6605
e75f7c90
MC		 6606 if (!netif_running(dev))
6607 return 0;
6608
58712ef9 6609 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6610 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6611
986e0aeb
MC		 6612 addr0_high = tr32(MAC_ADDR_0_HIGH);
6613 addr0_low = tr32(MAC_ADDR_0_LOW);
6614 addr1_high = tr32(MAC_ADDR_1_HIGH);
6615 addr1_low = tr32(MAC_ADDR_1_LOW);
6616
6617 /* Skip MAC addr 1 if ASF is using it. */
6618 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6619 !(addr1_high == 0 && addr1_low == 0))
6620 skip_mac_1 = 1;
58712ef9 6621 }
986e0aeb
MC		 6622 spin_lock_bh(&tp->lock);
6623 __tg3_set_mac_addr(tp, skip_mac_1);
6624 spin_unlock_bh(&tp->lock);
1da177e4 6625
b9ec6c1b 6626 return err;
1da177e4
LT		 6627}
6628
6629/* tp->lock is held. */
6630static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6631 dma_addr_t mapping, u32 maxlen_flags,
6632 u32 nic_addr)
6633{
6634 tg3_write_mem(tp,
6635 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6636 ((u64) mapping >> 32));
6637 tg3_write_mem(tp,
6638 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6639 ((u64) mapping & 0xffffffff));
6640 tg3_write_mem(tp,
6641 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6642 maxlen_flags);
6643
6644 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6645 tg3_write_mem(tp,
6646 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6647 nic_addr);
6648}
6649
6650static void __tg3_set_rx_mode(struct net_device *);
d244c892 6651static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6652{
6653 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6654 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6655 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6656 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6657 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6658 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6659 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6660 }
6661 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6662 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6663 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6664 u32 val = ec->stats_block_coalesce_usecs;
6665
6666 if (!netif_carrier_ok(tp->dev))
6667 val = 0;
6668
6669 tw32(HOSTCC_STAT_COAL_TICKS, val);
6670 }
6671}
1da177e4
LT		 6672
6673/* tp->lock is held. */
8e7a22e3 6674static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6675{
6676 u32 val, rdmac_mode;
6677 int i, err, limit;
6678
6679 tg3_disable_ints(tp);
6680
6681 tg3_stop_fw(tp);
6682
6683 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6684
6685 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6686 tg3_abort_hw(tp, 1);
1da177e4
LT		 6687 }
6688
dd477003
MC		 6689 if (reset_phy &&
6690 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6691 tg3_phy_reset(tp);
6692
1da177e4
LT		 6693 err = tg3_chip_reset(tp);
6694 if (err)
6695 return err;
6696
6697 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6698
bcb37f6c 6699 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6700 val = tr32(TG3_CPMU_CTRL);
6701 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6702 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6703
6704 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6705 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6706 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6707 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6708
6709 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6710 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6711 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6712 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6713
6714 val = tr32(TG3_CPMU_HST_ACC);
6715 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6716 val |= CPMU_HST_ACC_MACCLK_6_25;
6717 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6718 }
6719
1da177e4
LT		 6720 /* This works around an issue with Athlon chipsets on
6721 * B3 tigon3 silicon. This bit has no effect on any
6722 * other revision. But do not set this on PCI Express
795d01c5 6723 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6724 */
795d01c5
MC		 6725 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6726 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6727 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6728 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6729 }
1da177e4
LT		 6730
6731 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6732 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6733 val = tr32(TG3PCI_PCISTATE);
6734 val |= PCISTATE_RETRY_SAME_DMA;
6735 tw32(TG3PCI_PCISTATE, val);
6736 }
6737
0d3031d9
MC		 6738 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6739 /* Allow reads and writes to the
6740 * APE register and memory space.
6741 */
6742 val = tr32(TG3PCI_PCISTATE);
6743 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6744 PCISTATE_ALLOW_APE_SHMEM_WR;
6745 tw32(TG3PCI_PCISTATE, val);
6746 }
6747
1da177e4
LT		 6748 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6749 /* Enable some hw fixes. */
6750 val = tr32(TG3PCI_MSI_DATA);
6751 val |= (1 << 26) | (1 << 28) | (1 << 29);
6752 tw32(TG3PCI_MSI_DATA, val);
6753 }
6754
6755 /* Descriptor ring init may make accesses to the
6756 * NIC SRAM area to setup the TX descriptors, so we
6757 * can only do this after the hardware has been
6758 * successfully reset.
6759 */
32d8c572
MC		 6760 err = tg3_init_rings(tp);
6761 if (err)
6762 return err;
1da177e4 6763
9936bcf6 6764 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6765 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6766 /* This value is determined during the probe time DMA
6767 * engine test, tg3_test_dma.
6768 */
6769 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6770 }
1da177e4
LT		 6771
6772 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6773 GRC_MODE_4X_NIC_SEND_RINGS |
6774 GRC_MODE_NO_TX_PHDR_CSUM |
6775 GRC_MODE_NO_RX_PHDR_CSUM);
6776 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6777
6778 /* Pseudo-header checksum is done by hardware logic and not
6779 * the offload processers, so make the chip do the pseudo-
6780 * header checksums on receive. For transmit it is more
6781 * convenient to do the pseudo-header checksum in software
6782 * as Linux does that on transmit for us in all cases.
6783 */
6784 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6785
6786 tw32(GRC_MODE,
6787 tp->grc_mode |
6788 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6789
6790 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6791 val = tr32(GRC_MISC_CFG);
6792 val &= ~0xff;
6793 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6794 tw32(GRC_MISC_CFG, val);
6795
6796 /* Initialize MBUF/DESC pool. */
cbf46853 6797 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6798 /* Do nothing. */
6799 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6800 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6802 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6803 else
6804 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6805 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6806 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6807 }
1da177e4
LT		 6808 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6809 int fw_len;
6810
077f849d 6811 fw_len = tp->fw_len;
1da177e4
LT		 6812 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6813 tw32(BUFMGR_MB_POOL_ADDR,
6814 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6815 tw32(BUFMGR_MB_POOL_SIZE,
6816 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6817 }
1da177e4 6818
0f893dc6 6819 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6820 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6821 tp->bufmgr_config.mbuf_read_dma_low_water);
6822 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6823 tp->bufmgr_config.mbuf_mac_rx_low_water);
6824 tw32(BUFMGR_MB_HIGH_WATER,
6825 tp->bufmgr_config.mbuf_high_water);
6826 } else {
6827 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6828 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6829 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6830 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6831 tw32(BUFMGR_MB_HIGH_WATER,
6832 tp->bufmgr_config.mbuf_high_water_jumbo);
6833 }
6834 tw32(BUFMGR_DMA_LOW_WATER,
6835 tp->bufmgr_config.dma_low_water);
6836 tw32(BUFMGR_DMA_HIGH_WATER,
6837 tp->bufmgr_config.dma_high_water);
6838
6839 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6840 for (i = 0; i < 2000; i++) {
6841 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6842 break;
6843 udelay(10);
6844 }
6845 if (i >= 2000) {
6846 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6847 tp->dev->name);
6848 return -ENODEV;
6849 }
6850
6851 /* Setup replenish threshold. */
f92905de
MC		 6852 val = tp->rx_pending / 8;
6853 if (val == 0)
6854 val = 1;
6855 else if (val > tp->rx_std_max_post)
6856 val = tp->rx_std_max_post;
b5d3772c
MC		 6857 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6858 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6859 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6860
6861 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6862 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6863 }
f92905de
MC		 6864
6865 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6866
6867 /* Initialize TG3_BDINFO's at:
6868 * RCVDBDI_STD_BD: standard eth size rx ring
6869 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6870 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6871 *
6872 * like so:
6873 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6874 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6875 * ring attribute flags
6876 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6877 *
6878 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6879 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6880 *
6881 * The size of each ring is fixed in the firmware, but the location is
6882 * configurable.
6883 */
6884 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6885 ((u64) tp->rx_std_mapping >> 32));
6886 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6887 ((u64) tp->rx_std_mapping & 0xffffffff));
6888 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6889 NIC_SRAM_RX_BUFFER_DESC);
6890
6891 /* Don't even try to program the JUMBO/MINI buffer descriptor
6892 * configs on 5705.
6893 */
6894 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6895 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6896 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6897 } else {
6898 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6899 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6900
6901 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6902 BDINFO_FLAGS_DISABLED);
6903
6904 /* Setup replenish threshold. */
6905 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6906
0f893dc6 6907 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6908 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6909 ((u64) tp->rx_jumbo_mapping >> 32));
6910 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6911 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6912 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6913 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6914 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6915 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6916 } else {
6917 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6918 BDINFO_FLAGS_DISABLED);
6919 }
6920
6921 }
6922
6923 /* There is only one send ring on 5705/5750, no need to explicitly
6924 * disable the others.
6925 */
6926 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6927 /* Clear out send RCB ring in SRAM. */
6928 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6929 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6930 BDINFO_FLAGS_DISABLED);
6931 }
6932
6933 tp->tx_prod = 0;
6934 tp->tx_cons = 0;
6935 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6936 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6937
6938 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6939 tp->tx_desc_mapping,
6940 (TG3_TX_RING_SIZE <<
6941 BDINFO_FLAGS_MAXLEN_SHIFT),
6942 NIC_SRAM_TX_BUFFER_DESC);
6943
6944 /* There is only one receive return ring on 5705/5750, no need
6945 * to explicitly disable the others.
6946 */
6947 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6948 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6949 i += TG3_BDINFO_SIZE) {
6950 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6951 BDINFO_FLAGS_DISABLED);
6952 }
6953 }
6954
6955 tp->rx_rcb_ptr = 0;
6956 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6957
6958 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6959 tp->rx_rcb_mapping,
6960 (TG3_RX_RCB_RING_SIZE(tp) <<
6961 BDINFO_FLAGS_MAXLEN_SHIFT),
6962 0);
6963
6964 tp->rx_std_ptr = tp->rx_pending;
6965 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6966 tp->rx_std_ptr);
6967
0f893dc6 6968 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6969 tp->rx_jumbo_pending : 0;
6970 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6971 tp->rx_jumbo_ptr);
6972
6973 /* Initialize MAC address and backoff seed. */
986e0aeb 6974 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6975
6976 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 6977 tw32(MAC_RX_MTU_SIZE,
6978 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 6979
6980 /* The slot time is changed by tg3_setup_phy if we
6981 * run at gigabit with half duplex.
6982 */
6983 tw32(MAC_TX_LENGTHS,
6984 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6985 (6 << TX_LENGTHS_IPG_SHIFT) |
6986 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6987
6988 /* Receive rules. */
6989 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6990 tw32(RCVLPC_CONFIG, 0x0181);
6991
6992 /* Calculate RDMAC_MODE setting early, we need it to determine
6993 * the RCVLPC_STATE_ENABLE mask.
6994 */
6995 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6996 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6997 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6998 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6999 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7000
57e6983c 7001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7004 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7005 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7006 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7007
85e94ced
MC		 7008 /* If statement applies to 5705 and 5750 PCI devices only */
7009 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7010 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7011 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7012 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7014 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7015 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7016 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7017 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7018 }
7019 }
7020
85e94ced
MC		 7021 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7022 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7023
1da177e4 7024 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7025 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7026
7027 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7029 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7030
7031 /* Receive/send statistics. */
1661394e
MC		 7032 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7033 val = tr32(RCVLPC_STATS_ENABLE);
7034 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7035 tw32(RCVLPC_STATS_ENABLE, val);
7036 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7037 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7038 val = tr32(RCVLPC_STATS_ENABLE);
7039 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7040 tw32(RCVLPC_STATS_ENABLE, val);
7041 } else {
7042 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7043 }
7044 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7045 tw32(SNDDATAI_STATSENAB, 0xffffff);
7046 tw32(SNDDATAI_STATSCTRL,
7047 (SNDDATAI_SCTRL_ENABLE |
7048 SNDDATAI_SCTRL_FASTUPD));
7049
7050 /* Setup host coalescing engine. */
7051 tw32(HOSTCC_MODE, 0);
7052 for (i = 0; i < 2000; i++) {
7053 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7054 break;
7055 udelay(10);
7056 }
7057
d244c892 7058 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7059
7060 /* set status block DMA address */
7061 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7062 ((u64) tp->status_mapping >> 32));
7063 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7064 ((u64) tp->status_mapping & 0xffffffff));
7065
7066 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7067 /* Status/statistics block address. See tg3_timer,
7068 * the tg3_periodic_fetch_stats call there, and
7069 * tg3_get_stats to see how this works for 5705/5750 chips.
7070 */
1da177e4
LT		 7071 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7072 ((u64) tp->stats_mapping >> 32));
7073 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7074 ((u64) tp->stats_mapping & 0xffffffff));
7075 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7076 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7077 }
7078
7079 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7080
7081 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7082 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7083 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7084 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7085
7086 /* Clear statistics/status block in chip, and status block in ram. */
7087 for (i = NIC_SRAM_STATS_BLK;
7088 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7089 i += sizeof(u32)) {
7090 tg3_write_mem(tp, i, 0);
7091 udelay(40);
7092 }
7093 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7094
c94e3941
MC		 7095 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7096 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7097 /* reset to prevent losing 1st rx packet intermittently */
7098 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7099 udelay(10);
7100 }
7101
3bda1258
MC		 7102 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7103 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7104 else
7105 tp->mac_mode = 0;
7106 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7107 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7108 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7109 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7110 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7111 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7112 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7113 udelay(40);
7114
314fba34 7115 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7116 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7117 * register to preserve the GPIO settings for LOMs. The GPIOs,
7118 * whether used as inputs or outputs, are set by boot code after
7119 * reset.
7120 */
9d26e213 7121 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7122 u32 gpio_mask;
7123
9d26e213
MC		 7124 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7125 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7126 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7127
7128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7129 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7130 GRC_LCLCTRL_GPIO_OUTPUT3;
7131
af36e6b6
MC		 7132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7133 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7134
aaf84465 7135 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7136 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7137
7138 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7139 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7140 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7141 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7142 }
1da177e4
LT		 7143 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7144 udelay(100);
7145
09ee929c 7146 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
1da177e4
LT		 7147
7148 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7149 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7150 udelay(40);
7151 }
7152
7153 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7154 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7155 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7156 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7157 WDMAC_MODE_LNGREAD_ENAB);
7158
85e94ced
MC		 7159 /* If statement applies to 5705 and 5750 PCI devices only */
7160 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7161 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7162 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7163 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7164 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7165 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7166 /* nothing */
7167 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7168 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7169 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7170 val |= WDMAC_MODE_RX_ACCEL;
7171 }
7172 }
7173
d9ab5ad1 7174 /* Enable host coalescing bug fix */
321d32a0 7175 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7176 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7177
1da177e4
LT		 7178 tw32_f(WDMAC_MODE, val);
7179 udelay(40);
7180
9974a356
MC		 7181 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7182 u16 pcix_cmd;
7183
7184 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7185 &pcix_cmd);
1da177e4 7186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7187 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7188 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7189 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7190 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7191 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7192 }
9974a356
MC		 7193 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7194 pcix_cmd);
1da177e4
LT		 7195 }
7196
7197 tw32_f(RDMAC_MODE, rdmac_mode);
7198 udelay(40);
7199
7200 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7201 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7202 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7203
7204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7205 tw32(SNDDATAC_MODE,
7206 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7207 else
7208 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7209
1da177e4
LT		 7210 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7211 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7212 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7213 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7214 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7215 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7216 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7217 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7218
7219 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7220 err = tg3_load_5701_a0_firmware_fix(tp);
7221 if (err)
7222 return err;
7223 }
7224
1da177e4
LT		 7225 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7226 err = tg3_load_tso_firmware(tp);
7227 if (err)
7228 return err;
7229 }
1da177e4
LT		 7230
7231 tp->tx_mode = TX_MODE_ENABLE;
7232 tw32_f(MAC_TX_MODE, tp->tx_mode);
7233 udelay(100);
7234
7235 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7236 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7237 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7238
1da177e4
LT		 7239 tw32_f(MAC_RX_MODE, tp->rx_mode);
7240 udelay(10);
7241
1da177e4
LT		 7242 tw32(MAC_LED_CTRL, tp->led_ctrl);
7243
7244 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7245 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7246 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7247 udelay(10);
7248 }
7249 tw32_f(MAC_RX_MODE, tp->rx_mode);
7250 udelay(10);
7251
7252 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7253 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7254 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7255 /* Set drive transmission level to 1.2V */
7256 /* only if the signal pre-emphasis bit is not set */
7257 val = tr32(MAC_SERDES_CFG);
7258 val &= 0xfffff000;
7259 val |= 0x880;
7260 tw32(MAC_SERDES_CFG, val);
7261 }
7262 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7263 tw32(MAC_SERDES_CFG, 0x616000);
7264 }
7265
7266 /* Prevent chip from dropping frames when flow control
7267 * is enabled.
7268 */
7269 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7270
7271 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7272 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7273 /* Use hardware link auto-negotiation */
7274 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7275 }
7276
d4d2c558
MC		 7277 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7278 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7279 u32 tmp;
7280
7281 tmp = tr32(SERDES_RX_CTRL);
7282 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7283 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7284 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7285 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7286 }
7287
dd477003
MC		 7288 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7289 if (tp->link_config.phy_is_low_power) {
7290 tp->link_config.phy_is_low_power = 0;
7291 tp->link_config.speed = tp->link_config.orig_speed;
7292 tp->link_config.duplex = tp->link_config.orig_duplex;
7293 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7294 }
1da177e4 7295
dd477003
MC		 7296 err = tg3_setup_phy(tp, 0);
7297 if (err)
7298 return err;
1da177e4 7299
dd477003
MC		 7300 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7301 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7302 u32 tmp;
7303
7304 /* Clear CRC stats. */
7305 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7306 tg3_writephy(tp, MII_TG3_TEST1,
7307 tmp | MII_TG3_TEST1_CRC_EN);
7308 tg3_readphy(tp, 0x14, &tmp);
7309 }
1da177e4
LT		 7310 }
7311 }
7312
7313 __tg3_set_rx_mode(tp->dev);
7314
7315 /* Initialize receive rules. */
7316 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7317 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7318 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7319 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7320
4cf78e4f 7321 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7322 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7323 limit = 8;
7324 else
7325 limit = 16;
7326 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7327 limit -= 4;
7328 switch (limit) {
7329 case 16:
7330 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7331 case 15:
7332 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7333 case 14:
7334 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7335 case 13:
7336 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7337 case 12:
7338 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7339 case 11:
7340 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7341 case 10:
7342 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7343 case 9:
7344 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7345 case 8:
7346 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7347 case 7:
7348 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7349 case 6:
7350 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7351 case 5:
7352 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7353 case 4:
7354 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7355 case 3:
7356 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7357 case 2:
7358 case 1:
7359
7360 default:
7361 break;
855e1111 7362 }
1da177e4 7363
9ce768ea
MC		 7364 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7365 /* Write our heartbeat update interval to APE. */
7366 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7367 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7368
1da177e4
LT		 7369 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7370
1da177e4
LT		 7371 return 0;
7372}
7373
7374/* Called at device open time to get the chip ready for
7375 * packet processing. Invoked with tp->lock held.
7376 */
8e7a22e3 7377static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7378{
1da177e4
LT		 7379 tg3_switch_clocks(tp);
7380
7381 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7382
2f751b67 7383 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7384}
7385
7386#define TG3_STAT_ADD32(PSTAT, REG) \
7387do { u32 __val = tr32(REG); \
7388 (PSTAT)->low += __val; \
7389 if ((PSTAT)->low < __val) \
7390 (PSTAT)->high += 1; \
7391} while (0)
7392
7393static void tg3_periodic_fetch_stats(struct tg3 *tp)
7394{
7395 struct tg3_hw_stats *sp = tp->hw_stats;
7396
7397 if (!netif_carrier_ok(tp->dev))
7398 return;
7399
7400 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7401 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7402 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7403 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7404 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7405 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7406 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7407 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7408 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7409 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7410 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7411 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7412 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7413
7414 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7415 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7416 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7417 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7418 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7419 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7420 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7421 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7422 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7423 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7424 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7425 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7426 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7427 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7428
7429 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7430 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7431 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7432}
7433
7434static void tg3_timer(unsigned long __opaque)
7435{
7436 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7437
f475f163
MC		 7438 if (tp->irq_sync)
7439 goto restart_timer;
7440
f47c11ee 7441 spin_lock(&tp->lock);
1da177e4 7442
fac9b83e
DM		 7443 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7444 /* All of this garbage is because when using non-tagged
7445 * IRQ status the mailbox/status_block protocol the chip
7446 * uses with the cpu is race prone.
7447 */
7448 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7449 tw32(GRC_LOCAL_CTRL,
7450 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7451 } else {
7452 tw32(HOSTCC_MODE, tp->coalesce_mode |
7453 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7454 }
1da177e4 7455
fac9b83e
DM		 7456 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7457 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7458 spin_unlock(&tp->lock);
fac9b83e
DM		 7459 schedule_work(&tp->reset_task);
7460 return;
7461 }
1da177e4
LT		 7462 }
7463
1da177e4
LT		 7464 /* This part only runs once per second. */
7465 if (!--tp->timer_counter) {
fac9b83e
DM		 7466 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7467 tg3_periodic_fetch_stats(tp);
7468
1da177e4
LT		 7469 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7470 u32 mac_stat;
7471 int phy_event;
7472
7473 mac_stat = tr32(MAC_STATUS);
7474
7475 phy_event = 0;
7476 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7477 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7478 phy_event = 1;
7479 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7480 phy_event = 1;
7481
7482 if (phy_event)
7483 tg3_setup_phy(tp, 0);
7484 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7485 u32 mac_stat = tr32(MAC_STATUS);
7486 int need_setup = 0;
7487
7488 if (netif_carrier_ok(tp->dev) &&
7489 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7490 need_setup = 1;
7491 }
7492 if (! netif_carrier_ok(tp->dev) &&
7493 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7494 MAC_STATUS_SIGNAL_DET))) {
7495 need_setup = 1;
7496 }
7497 if (need_setup) {
3d3ebe74
MC		 7498 if (!tp->serdes_counter) {
7499 tw32_f(MAC_MODE,
7500 (tp->mac_mode &
7501 ~MAC_MODE_PORT_MODE_MASK));
7502 udelay(40);
7503 tw32_f(MAC_MODE, tp->mac_mode);
7504 udelay(40);
7505 }
1da177e4
LT		 7506 tg3_setup_phy(tp, 0);
7507 }
747e8f8b
MC		 7508 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7509 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7510
7511 tp->timer_counter = tp->timer_multiplier;
7512 }
7513
130b8e4d
MC		 7514 /* Heartbeat is only sent once every 2 seconds.
7515 *
7516 * The heartbeat is to tell the ASF firmware that the host
7517 * driver is still alive. In the event that the OS crashes,
7518 * ASF needs to reset the hardware to free up the FIFO space
7519 * that may be filled with rx packets destined for the host.
7520 * If the FIFO is full, ASF will no longer function properly.
7521 *
7522 * Unintended resets have been reported on real time kernels
7523 * where the timer doesn't run on time. Netpoll will also have
7524 * same problem.
7525 *
7526 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7527 * to check the ring condition when the heartbeat is expiring
7528 * before doing the reset. This will prevent most unintended
7529 * resets.
7530 */
1da177e4 7531 if (!--tp->asf_counter) {
bc7959b2
MC		 7532 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7533 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7534 tg3_wait_for_event_ack(tp);
7535
bbadf503 7536 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7537 FWCMD_NICDRV_ALIVE3);
bbadf503 7538 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7539 /* 5 seconds timeout */
bbadf503 7540 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7541
7542 tg3_generate_fw_event(tp);
1da177e4
LT		 7543 }
7544 tp->asf_counter = tp->asf_multiplier;
7545 }
7546
f47c11ee 7547 spin_unlock(&tp->lock);
1da177e4 7548
f475f163 7549restart_timer:
1da177e4
LT		 7550 tp->timer.expires = jiffies + tp->timer_offset;
7551 add_timer(&tp->timer);
7552}
7553
81789ef5 7554static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7555{
7d12e780 7556 irq_handler_t fn;
fcfa0a32
MC		 7557 unsigned long flags;
7558 struct net_device *dev = tp->dev;
7559
7560 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7561 fn = tg3_msi;
7562 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7563 fn = tg3_msi_1shot;
1fb9df5d 7564 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7565 } else {
7566 fn = tg3_interrupt;
7567 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7568 fn = tg3_interrupt_tagged;
1fb9df5d 7569 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7570 }
7571 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7572}
7573
7938109f
MC		 7574static int tg3_test_interrupt(struct tg3 *tp)
7575{
7576 struct net_device *dev = tp->dev;
b16250e3 7577 int err, i, intr_ok = 0;
7938109f 7578
d4bc3927
MC		 7579 if (!netif_running(dev))
7580 return -ENODEV;
7581
7938109f
MC		 7582 tg3_disable_ints(tp);
7583
7584 free_irq(tp->pdev->irq, dev);
7585
7586 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7587 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7588 if (err)
7589 return err;
7590
38f3843e 7591 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7592 tg3_enable_ints(tp);
7593
7594 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7595 HOSTCC_MODE_NOW);
7596
7597 for (i = 0; i < 5; i++) {
b16250e3
MC		 7598 u32 int_mbox, misc_host_ctrl;
7599
09ee929c
MC		 7600 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7601 TG3_64BIT_REG_LOW);
b16250e3
MC		 7602 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7603
7604 if ((int_mbox != 0) ||
7605 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7606 intr_ok = 1;
7938109f 7607 break;
b16250e3
MC		 7608 }
7609
7938109f
MC		 7610 msleep(10);
7611 }
7612
7613 tg3_disable_ints(tp);
7614
7615 free_irq(tp->pdev->irq, dev);
6aa20a22 7616
fcfa0a32 7617 err = tg3_request_irq(tp);
7938109f
MC		 7618
7619 if (err)
7620 return err;
7621
b16250e3 7622 if (intr_ok)
7938109f
MC		 7623 return 0;
7624
7625 return -EIO;
7626}
7627
7628/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7629 * successfully restored
7630 */
7631static int tg3_test_msi(struct tg3 *tp)
7632{
7633 struct net_device *dev = tp->dev;
7634 int err;
7635 u16 pci_cmd;
7636
7637 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7638 return 0;
7639
7640 /* Turn off SERR reporting in case MSI terminates with Master
7641 * Abort.
7642 */
7643 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7644 pci_write_config_word(tp->pdev, PCI_COMMAND,
7645 pci_cmd & ~PCI_COMMAND_SERR);
7646
7647 err = tg3_test_interrupt(tp);
7648
7649 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7650
7651 if (!err)
7652 return 0;
7653
7654 /* other failures */
7655 if (err != -EIO)
7656 return err;
7657
7658 /* MSI test failed, go back to INTx mode */
7659 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7660 "switching to INTx mode. Please report this failure to "
7661 "the PCI maintainer and include system chipset information.\n",
7662 tp->dev->name);
7663
7664 free_irq(tp->pdev->irq, dev);
7665 pci_disable_msi(tp->pdev);
7666
7667 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7668
fcfa0a32 7669 err = tg3_request_irq(tp);
7938109f
MC		 7670 if (err)
7671 return err;
7672
7673 /* Need to reset the chip because the MSI cycle may have terminated
7674 * with Master Abort.
7675 */
f47c11ee 7676 tg3_full_lock(tp, 1);
7938109f 7677
944d980e 7678 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7679 err = tg3_init_hw(tp, 1);
7938109f 7680
f47c11ee 7681 tg3_full_unlock(tp);
7938109f
MC		 7682
7683 if (err)
7684 free_irq(tp->pdev->irq, dev);
7685
7686 return err;
7687}
7688
9e9fd12d
MC		 7689static int tg3_request_firmware(struct tg3 *tp)
7690{
7691 const __be32 *fw_data;
7692
7693 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7694 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7695 tp->dev->name, tp->fw_needed);
7696 return -ENOENT;
7697 }
7698
7699 fw_data = (void *)tp->fw->data;
7700
7701 /* Firmware blob starts with version numbers, followed by
7702 * start address and _full_ length including BSS sections
7703 * (which must be longer than the actual data, of course
7704 */
7705
7706 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7707 if (tp->fw_len < (tp->fw->size - 12)) {
7708 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7709 tp->dev->name, tp->fw_len, tp->fw_needed);
7710 release_firmware(tp->fw);
7711 tp->fw = NULL;
7712 return -EINVAL;
7713 }
7714
7715 /* We no longer need firmware; we have it. */
7716 tp->fw_needed = NULL;
7717 return 0;
7718}
7719
1da177e4
LT		 7720static int tg3_open(struct net_device *dev)
7721{
7722 struct tg3 *tp = netdev_priv(dev);
7723 int err;
7724
9e9fd12d
MC		 7725 if (tp->fw_needed) {
7726 err = tg3_request_firmware(tp);
7727 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7728 if (err)
7729 return err;
7730 } else if (err) {
7731 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7732 tp->dev->name);
7733 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7734 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7735 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7736 tp->dev->name);
7737 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7738 }
7739 }
7740
c49a1561
MC		 7741 netif_carrier_off(tp->dev);
7742
bc1c7567 7743 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7744 if (err)
bc1c7567 7745 return err;
2f751b67
MC		 7746
7747 tg3_full_lock(tp, 0);
bc1c7567 7748
1da177e4
LT		 7749 tg3_disable_ints(tp);
7750 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7751
f47c11ee 7752 tg3_full_unlock(tp);
1da177e4
LT		 7753
7754 /* The placement of this call is tied
7755 * to the setup and use of Host TX descriptors.
7756 */
7757 err = tg3_alloc_consistent(tp);
7758 if (err)
7759 return err;
7760
7544b097 7761 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7762 /* All MSI supporting chips should support tagged
7763 * status. Assert that this is the case.
7764 */
7765 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7766 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7767 "Not using MSI.\n", tp->dev->name);
7768 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7769 u32 msi_mode;
7770
7771 msi_mode = tr32(MSGINT_MODE);
7772 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7773 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7774 }
7775 }
fcfa0a32 7776 err = tg3_request_irq(tp);
1da177e4
LT		 7777
7778 if (err) {
88b06bc2
MC		 7779 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7780 pci_disable_msi(tp->pdev);
7781 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7782 }
1da177e4
LT		 7783 tg3_free_consistent(tp);
7784 return err;
7785 }
7786
bea3348e
SH		 7787 napi_enable(&tp->napi);
7788
f47c11ee 7789 tg3_full_lock(tp, 0);
1da177e4 7790
8e7a22e3 7791 err = tg3_init_hw(tp, 1);
1da177e4 7792 if (err) {
944d980e 7793 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7794 tg3_free_rings(tp);
7795 } else {
fac9b83e
DM		 7796 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7797 tp->timer_offset = HZ;
7798 else
7799 tp->timer_offset = HZ / 10;
7800
7801 BUG_ON(tp->timer_offset > HZ);
7802 tp->timer_counter = tp->timer_multiplier =
7803 (HZ / tp->timer_offset);
7804 tp->asf_counter = tp->asf_multiplier =
28fbef78 7805 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7806
7807 init_timer(&tp->timer);
7808 tp->timer.expires = jiffies + tp->timer_offset;
7809 tp->timer.data = (unsigned long) tp;
7810 tp->timer.function = tg3_timer;
1da177e4
LT		 7811 }
7812
f47c11ee 7813 tg3_full_unlock(tp);
1da177e4
LT		 7814
7815 if (err) {
bea3348e 7816 napi_disable(&tp->napi);
88b06bc2
MC		 7817 free_irq(tp->pdev->irq, dev);
7818 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7819 pci_disable_msi(tp->pdev);
7820 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7821 }
1da177e4
LT		 7822 tg3_free_consistent(tp);
7823 return err;
7824 }
7825
7938109f
MC		 7826 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7827 err = tg3_test_msi(tp);
fac9b83e 7828
7938109f 7829 if (err) {
f47c11ee 7830 tg3_full_lock(tp, 0);
7938109f
MC		 7831
7832 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7833 pci_disable_msi(tp->pdev);
7834 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7835 }
944d980e 7836 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7837 tg3_free_rings(tp);
7838 tg3_free_consistent(tp);
7839
f47c11ee 7840 tg3_full_unlock(tp);
7938109f 7841
bea3348e
SH		 7842 napi_disable(&tp->napi);
7843
7938109f
MC		 7844 return err;
7845 }
fcfa0a32
MC		 7846
7847 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7848 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7849 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7850
b5d3772c
MC		 7851 tw32(PCIE_TRANSACTION_CFG,
7852 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7853 }
7854 }
7938109f
MC		 7855 }
7856
b02fd9e3
MC		 7857 tg3_phy_start(tp);
7858
f47c11ee 7859 tg3_full_lock(tp, 0);
1da177e4 7860
7938109f
MC		 7861 add_timer(&tp->timer);
7862 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7863 tg3_enable_ints(tp);
7864
f47c11ee 7865 tg3_full_unlock(tp);
1da177e4
LT		 7866
7867 netif_start_queue(dev);
7868
7869 return 0;
7870}
7871
7872#if 0
7873/*static*/ void tg3_dump_state(struct tg3 *tp)
7874{
7875 u32 val32, val32_2, val32_3, val32_4, val32_5;
7876 u16 val16;
7877 int i;
7878
7879 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7880 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7881 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7882 val16, val32);
7883
7884 /* MAC block */
7885 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7886 tr32(MAC_MODE), tr32(MAC_STATUS));
7887 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7888 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7889 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7890 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7891 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7892 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7893
7894 /* Send data initiator control block */
7895 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7896 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7897 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7898 tr32(SNDDATAI_STATSCTRL));
7899
7900 /* Send data completion control block */
7901 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7902
7903 /* Send BD ring selector block */
7904 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7905 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7906
7907 /* Send BD initiator control block */
7908 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7909 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7910
7911 /* Send BD completion control block */
7912 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7913
7914 /* Receive list placement control block */
7915 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7916 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7917 printk(" RCVLPC_STATSCTRL[%08x]\n",
7918 tr32(RCVLPC_STATSCTRL));
7919
7920 /* Receive data and receive BD initiator control block */
7921 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7922 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7923
7924 /* Receive data completion control block */
7925 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7926 tr32(RCVDCC_MODE));
7927
7928 /* Receive BD initiator control block */
7929 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7930 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7931
7932 /* Receive BD completion control block */
7933 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7934 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7935
7936 /* Receive list selector control block */
7937 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7938 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7939
7940 /* Mbuf cluster free block */
7941 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7942 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7943
7944 /* Host coalescing control block */
7945 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7946 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7947 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7948 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7949 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7950 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7951 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7952 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7953 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7954 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7955 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7956 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7957
7958 /* Memory arbiter control block */
7959 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7960 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7961
7962 /* Buffer manager control block */
7963 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7964 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7965 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7966 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7967 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7968 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7969 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7970 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7971
7972 /* Read DMA control block */
7973 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7974 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7975
7976 /* Write DMA control block */
7977 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7978 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7979
7980 /* DMA completion block */
7981 printk("DEBUG: DMAC_MODE[%08x]\n",
7982 tr32(DMAC_MODE));
7983
7984 /* GRC block */
7985 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7986 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7987 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7988 tr32(GRC_LOCAL_CTRL));
7989
7990 /* TG3_BDINFOs */
7991 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7992 tr32(RCVDBDI_JUMBO_BD + 0x0),
7993 tr32(RCVDBDI_JUMBO_BD + 0x4),
7994 tr32(RCVDBDI_JUMBO_BD + 0x8),
7995 tr32(RCVDBDI_JUMBO_BD + 0xc));
7996 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7997 tr32(RCVDBDI_STD_BD + 0x0),
7998 tr32(RCVDBDI_STD_BD + 0x4),
7999 tr32(RCVDBDI_STD_BD + 0x8),
8000 tr32(RCVDBDI_STD_BD + 0xc));
8001 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8002 tr32(RCVDBDI_MINI_BD + 0x0),
8003 tr32(RCVDBDI_MINI_BD + 0x4),
8004 tr32(RCVDBDI_MINI_BD + 0x8),
8005 tr32(RCVDBDI_MINI_BD + 0xc));
8006
8007 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8008 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8009 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8010 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8011 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8012 val32, val32_2, val32_3, val32_4);
8013
8014 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8015 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8016 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8017 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8018 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8019 val32, val32_2, val32_3, val32_4);
8020
8021 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8022 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8023 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8024 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8025 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8026 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8027 val32, val32_2, val32_3, val32_4, val32_5);
8028
8029 /* SW status block */
8030 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8031 tp->hw_status->status,
8032 tp->hw_status->status_tag,
8033 tp->hw_status->rx_jumbo_consumer,
8034 tp->hw_status->rx_consumer,
8035 tp->hw_status->rx_mini_consumer,
8036 tp->hw_status->idx[0].rx_producer,
8037 tp->hw_status->idx[0].tx_consumer);
8038
8039 /* SW statistics block */
8040 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8041 ((u32 *)tp->hw_stats)[0],
8042 ((u32 *)tp->hw_stats)[1],
8043 ((u32 *)tp->hw_stats)[2],
8044 ((u32 *)tp->hw_stats)[3]);
8045
8046 /* Mailboxes */
8047 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8048 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8049 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8050 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8051 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8052
8053 /* NIC side send descriptors. */
8054 for (i = 0; i < 6; i++) {
8055 unsigned long txd;
8056
8057 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8058 + (i * sizeof(struct tg3_tx_buffer_desc));
8059 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8060 i,
8061 readl(txd + 0x0), readl(txd + 0x4),
8062 readl(txd + 0x8), readl(txd + 0xc));
8063 }
8064
8065 /* NIC side RX descriptors. */
8066 for (i = 0; i < 6; i++) {
8067 unsigned long rxd;
8068
8069 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8070 + (i * sizeof(struct tg3_rx_buffer_desc));
8071 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8072 i,
8073 readl(rxd + 0x0), readl(rxd + 0x4),
8074 readl(rxd + 0x8), readl(rxd + 0xc));
8075 rxd += (4 * sizeof(u32));
8076 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8077 i,
8078 readl(rxd + 0x0), readl(rxd + 0x4),
8079 readl(rxd + 0x8), readl(rxd + 0xc));
8080 }
8081
8082 for (i = 0; i < 6; i++) {
8083 unsigned long rxd;
8084
8085 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8086 + (i * sizeof(struct tg3_rx_buffer_desc));
8087 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8088 i,
8089 readl(rxd + 0x0), readl(rxd + 0x4),
8090 readl(rxd + 0x8), readl(rxd + 0xc));
8091 rxd += (4 * sizeof(u32));
8092 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8093 i,
8094 readl(rxd + 0x0), readl(rxd + 0x4),
8095 readl(rxd + 0x8), readl(rxd + 0xc));
8096 }
8097}
8098#endif
8099
8100static struct net_device_stats *tg3_get_stats(struct net_device *);
8101static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8102
8103static int tg3_close(struct net_device *dev)
8104{
8105 struct tg3 *tp = netdev_priv(dev);
8106
bea3348e 8107 napi_disable(&tp->napi);
28e53bdd 8108 cancel_work_sync(&tp->reset_task);
7faa006f 8109
1da177e4
LT		 8110 netif_stop_queue(dev);
8111
8112 del_timer_sync(&tp->timer);
8113
f47c11ee 8114 tg3_full_lock(tp, 1);
1da177e4
LT		 8115#if 0
8116 tg3_dump_state(tp);
8117#endif
8118
8119 tg3_disable_ints(tp);
8120
944d980e 8121 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8122 tg3_free_rings(tp);
5cf64b8a 8123 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8124
f47c11ee 8125 tg3_full_unlock(tp);
1da177e4 8126
88b06bc2
MC		 8127 free_irq(tp->pdev->irq, dev);
8128 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8129 pci_disable_msi(tp->pdev);
8130 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8131 }
1da177e4
LT		 8132
8133 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8134 sizeof(tp->net_stats_prev));
8135 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8136 sizeof(tp->estats_prev));
8137
8138 tg3_free_consistent(tp);
8139
bc1c7567
MC		 8140 tg3_set_power_state(tp, PCI_D3hot);
8141
8142 netif_carrier_off(tp->dev);
8143
1da177e4
LT		 8144 return 0;
8145}
8146
8147static inline unsigned long get_stat64(tg3_stat64_t *val)
8148{
8149 unsigned long ret;
8150
8151#if (BITS_PER_LONG == 32)
8152 ret = val->low;
8153#else
8154 ret = ((u64)val->high << 32) | ((u64)val->low);
8155#endif
8156 return ret;
8157}
8158
816f8b86
SB		 8159static inline u64 get_estat64(tg3_stat64_t *val)
8160{
8161 return ((u64)val->high << 32) | ((u64)val->low);
8162}
8163
1da177e4
LT		 8164static unsigned long calc_crc_errors(struct tg3 *tp)
8165{
8166 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8167
8168 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8169 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8171 u32 val;
8172
f47c11ee 8173 spin_lock_bh(&tp->lock);
569a5df8
MC		 8174 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8175 tg3_writephy(tp, MII_TG3_TEST1,
8176 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8177 tg3_readphy(tp, 0x14, &val);
8178 } else
8179 val = 0;
f47c11ee 8180 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8181
8182 tp->phy_crc_errors += val;
8183
8184 return tp->phy_crc_errors;
8185 }
8186
8187 return get_stat64(&hw_stats->rx_fcs_errors);
8188}
8189
8190#define ESTAT_ADD(member) \
8191 estats->member = old_estats->member + \
816f8b86 8192 get_estat64(&hw_stats->member)
1da177e4
LT		 8193
8194static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8195{
8196 struct tg3_ethtool_stats *estats = &tp->estats;
8197 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8198 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8199
8200 if (!hw_stats)
8201 return old_estats;
8202
8203 ESTAT_ADD(rx_octets);
8204 ESTAT_ADD(rx_fragments);
8205 ESTAT_ADD(rx_ucast_packets);
8206 ESTAT_ADD(rx_mcast_packets);
8207 ESTAT_ADD(rx_bcast_packets);
8208 ESTAT_ADD(rx_fcs_errors);
8209 ESTAT_ADD(rx_align_errors);
8210 ESTAT_ADD(rx_xon_pause_rcvd);
8211 ESTAT_ADD(rx_xoff_pause_rcvd);
8212 ESTAT_ADD(rx_mac_ctrl_rcvd);
8213 ESTAT_ADD(rx_xoff_entered);
8214 ESTAT_ADD(rx_frame_too_long_errors);
8215 ESTAT_ADD(rx_jabbers);
8216 ESTAT_ADD(rx_undersize_packets);
8217 ESTAT_ADD(rx_in_length_errors);
8218 ESTAT_ADD(rx_out_length_errors);
8219 ESTAT_ADD(rx_64_or_less_octet_packets);
8220 ESTAT_ADD(rx_65_to_127_octet_packets);
8221 ESTAT_ADD(rx_128_to_255_octet_packets);
8222 ESTAT_ADD(rx_256_to_511_octet_packets);
8223 ESTAT_ADD(rx_512_to_1023_octet_packets);
8224 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8225 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8226 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8227 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8228 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8229
8230 ESTAT_ADD(tx_octets);
8231 ESTAT_ADD(tx_collisions);
8232 ESTAT_ADD(tx_xon_sent);
8233 ESTAT_ADD(tx_xoff_sent);
8234 ESTAT_ADD(tx_flow_control);
8235 ESTAT_ADD(tx_mac_errors);
8236 ESTAT_ADD(tx_single_collisions);
8237 ESTAT_ADD(tx_mult_collisions);
8238 ESTAT_ADD(tx_deferred);
8239 ESTAT_ADD(tx_excessive_collisions);
8240 ESTAT_ADD(tx_late_collisions);
8241 ESTAT_ADD(tx_collide_2times);
8242 ESTAT_ADD(tx_collide_3times);
8243 ESTAT_ADD(tx_collide_4times);
8244 ESTAT_ADD(tx_collide_5times);
8245 ESTAT_ADD(tx_collide_6times);
8246 ESTAT_ADD(tx_collide_7times);
8247 ESTAT_ADD(tx_collide_8times);
8248 ESTAT_ADD(tx_collide_9times);
8249 ESTAT_ADD(tx_collide_10times);
8250 ESTAT_ADD(tx_collide_11times);
8251 ESTAT_ADD(tx_collide_12times);
8252 ESTAT_ADD(tx_collide_13times);
8253 ESTAT_ADD(tx_collide_14times);
8254 ESTAT_ADD(tx_collide_15times);
8255 ESTAT_ADD(tx_ucast_packets);
8256 ESTAT_ADD(tx_mcast_packets);
8257 ESTAT_ADD(tx_bcast_packets);
8258 ESTAT_ADD(tx_carrier_sense_errors);
8259 ESTAT_ADD(tx_discards);
8260 ESTAT_ADD(tx_errors);
8261
8262 ESTAT_ADD(dma_writeq_full);
8263 ESTAT_ADD(dma_write_prioq_full);
8264 ESTAT_ADD(rxbds_empty);
8265 ESTAT_ADD(rx_discards);
8266 ESTAT_ADD(rx_errors);
8267 ESTAT_ADD(rx_threshold_hit);
8268
8269 ESTAT_ADD(dma_readq_full);
8270 ESTAT_ADD(dma_read_prioq_full);
8271 ESTAT_ADD(tx_comp_queue_full);
8272
8273 ESTAT_ADD(ring_set_send_prod_index);
8274 ESTAT_ADD(ring_status_update);
8275 ESTAT_ADD(nic_irqs);
8276 ESTAT_ADD(nic_avoided_irqs);
8277 ESTAT_ADD(nic_tx_threshold_hit);
8278
8279 return estats;
8280}
8281
8282static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8283{
8284 struct tg3 *tp = netdev_priv(dev);
8285 struct net_device_stats *stats = &tp->net_stats;
8286 struct net_device_stats *old_stats = &tp->net_stats_prev;
8287 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8288
8289 if (!hw_stats)
8290 return old_stats;
8291
8292 stats->rx_packets = old_stats->rx_packets +
8293 get_stat64(&hw_stats->rx_ucast_packets) +
8294 get_stat64(&hw_stats->rx_mcast_packets) +
8295 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8296
1da177e4
LT		 8297 stats->tx_packets = old_stats->tx_packets +
8298 get_stat64(&hw_stats->tx_ucast_packets) +
8299 get_stat64(&hw_stats->tx_mcast_packets) +
8300 get_stat64(&hw_stats->tx_bcast_packets);
8301
8302 stats->rx_bytes = old_stats->rx_bytes +
8303 get_stat64(&hw_stats->rx_octets);
8304 stats->tx_bytes = old_stats->tx_bytes +
8305 get_stat64(&hw_stats->tx_octets);
8306
8307 stats->rx_errors = old_stats->rx_errors +
4f63b877 8308 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8309 stats->tx_errors = old_stats->tx_errors +
8310 get_stat64(&hw_stats->tx_errors) +
8311 get_stat64(&hw_stats->tx_mac_errors) +
8312 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8313 get_stat64(&hw_stats->tx_discards);
8314
8315 stats->multicast = old_stats->multicast +
8316 get_stat64(&hw_stats->rx_mcast_packets);
8317 stats->collisions = old_stats->collisions +
8318 get_stat64(&hw_stats->tx_collisions);
8319
8320 stats->rx_length_errors = old_stats->rx_length_errors +
8321 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8322 get_stat64(&hw_stats->rx_undersize_packets);
8323
8324 stats->rx_over_errors = old_stats->rx_over_errors +
8325 get_stat64(&hw_stats->rxbds_empty);
8326 stats->rx_frame_errors = old_stats->rx_frame_errors +
8327 get_stat64(&hw_stats->rx_align_errors);
8328 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8329 get_stat64(&hw_stats->tx_discards);
8330 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8331 get_stat64(&hw_stats->tx_carrier_sense_errors);
8332
8333 stats->rx_crc_errors = old_stats->rx_crc_errors +
8334 calc_crc_errors(tp);
8335
4f63b877
JL		 8336 stats->rx_missed_errors = old_stats->rx_missed_errors +
8337 get_stat64(&hw_stats->rx_discards);
8338
1da177e4
LT		 8339 return stats;
8340}
8341
8342static inline u32 calc_crc(unsigned char *buf, int len)
8343{
8344 u32 reg;
8345 u32 tmp;
8346 int j, k;
8347
8348 reg = 0xffffffff;
8349
8350 for (j = 0; j < len; j++) {
8351 reg ^= buf[j];
8352
8353 for (k = 0; k < 8; k++) {
8354 tmp = reg & 0x01;
8355
8356 reg >>= 1;
8357
8358 if (tmp) {
8359 reg ^= 0xedb88320;
8360 }
8361 }
8362 }
8363
8364 return ~reg;
8365}
8366
8367static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8368{
8369 /* accept or reject all multicast frames */
8370 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8371 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8372 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8373 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8374}
8375
8376static void __tg3_set_rx_mode(struct net_device *dev)
8377{
8378 struct tg3 *tp = netdev_priv(dev);
8379 u32 rx_mode;
8380
8381 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8382 RX_MODE_KEEP_VLAN_TAG);
8383
8384 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8385 * flag clear.
8386 */
8387#if TG3_VLAN_TAG_USED
8388 if (!tp->vlgrp &&
8389 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8390 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8391#else
8392 /* By definition, VLAN is disabled always in this
8393 * case.
8394 */
8395 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8396 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8397#endif
8398
8399 if (dev->flags & IFF_PROMISC) {
8400 /* Promiscuous mode. */
8401 rx_mode |= RX_MODE_PROMISC;
8402 } else if (dev->flags & IFF_ALLMULTI) {
8403 /* Accept all multicast. */
8404 tg3_set_multi (tp, 1);
8405 } else if (dev->mc_count < 1) {
8406 /* Reject all multicast. */
8407 tg3_set_multi (tp, 0);
8408 } else {
8409 /* Accept one or more multicast(s). */
8410 struct dev_mc_list *mclist;
8411 unsigned int i;
8412 u32 mc_filter[4] = { 0, };
8413 u32 regidx;
8414 u32 bit;
8415 u32 crc;
8416
8417 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8418 i++, mclist = mclist->next) {
8419
8420 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8421 bit = ~crc & 0x7f;
8422 regidx = (bit & 0x60) >> 5;
8423 bit &= 0x1f;
8424 mc_filter[regidx] |= (1 << bit);
8425 }
8426
8427 tw32(MAC_HASH_REG_0, mc_filter[0]);
8428 tw32(MAC_HASH_REG_1, mc_filter[1]);
8429 tw32(MAC_HASH_REG_2, mc_filter[2]);
8430 tw32(MAC_HASH_REG_3, mc_filter[3]);
8431 }
8432
8433 if (rx_mode != tp->rx_mode) {
8434 tp->rx_mode = rx_mode;
8435 tw32_f(MAC_RX_MODE, rx_mode);
8436 udelay(10);
8437 }
8438}
8439
8440static void tg3_set_rx_mode(struct net_device *dev)
8441{
8442 struct tg3 *tp = netdev_priv(dev);
8443
e75f7c90
MC		 8444 if (!netif_running(dev))
8445 return;
8446
f47c11ee 8447 tg3_full_lock(tp, 0);
1da177e4 8448 __tg3_set_rx_mode(dev);
f47c11ee 8449 tg3_full_unlock(tp);
1da177e4
LT		 8450}
8451
8452#define TG3_REGDUMP_LEN (32 * 1024)
8453
8454static int tg3_get_regs_len(struct net_device *dev)
8455{
8456 return TG3_REGDUMP_LEN;
8457}
8458
8459static void tg3_get_regs(struct net_device *dev,
8460 struct ethtool_regs *regs, void *_p)
8461{
8462 u32 *p = _p;
8463 struct tg3 *tp = netdev_priv(dev);
8464 u8 *orig_p = _p;
8465 int i;
8466
8467 regs->version = 0;
8468
8469 memset(p, 0, TG3_REGDUMP_LEN);
8470
bc1c7567
MC		 8471 if (tp->link_config.phy_is_low_power)
8472 return;
8473
f47c11ee 8474 tg3_full_lock(tp, 0);
1da177e4
LT		 8475
8476#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8477#define GET_REG32_LOOP(base,len) \
8478do { p = (u32 *)(orig_p + (base)); \
8479 for (i = 0; i < len; i += 4) \
8480 __GET_REG32((base) + i); \
8481} while (0)
8482#define GET_REG32_1(reg) \
8483do { p = (u32 *)(orig_p + (reg)); \
8484 __GET_REG32((reg)); \
8485} while (0)
8486
8487 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8488 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8489 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8490 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8491 GET_REG32_1(SNDDATAC_MODE);
8492 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8493 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8494 GET_REG32_1(SNDBDC_MODE);
8495 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8496 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8497 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8498 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8499 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8500 GET_REG32_1(RCVDCC_MODE);
8501 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8502 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8503 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8504 GET_REG32_1(MBFREE_MODE);
8505 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8506 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8507 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8508 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8509 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8510 GET_REG32_1(RX_CPU_MODE);
8511 GET_REG32_1(RX_CPU_STATE);
8512 GET_REG32_1(RX_CPU_PGMCTR);
8513 GET_REG32_1(RX_CPU_HWBKPT);
8514 GET_REG32_1(TX_CPU_MODE);
8515 GET_REG32_1(TX_CPU_STATE);
8516 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8517 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8518 GET_REG32_LOOP(FTQ_RESET, 0x120);
8519 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8520 GET_REG32_1(DMAC_MODE);
8521 GET_REG32_LOOP(GRC_MODE, 0x4c);
8522 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8523 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8524
8525#undef __GET_REG32
8526#undef GET_REG32_LOOP
8527#undef GET_REG32_1
8528
f47c11ee 8529 tg3_full_unlock(tp);
1da177e4
LT		 8530}
8531
8532static int tg3_get_eeprom_len(struct net_device *dev)
8533{
8534 struct tg3 *tp = netdev_priv(dev);
8535
8536 return tp->nvram_size;
8537}
8538
1da177e4
LT		 8539static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8540{
8541 struct tg3 *tp = netdev_priv(dev);
8542 int ret;
8543 u8 *pd;
b9fc7dc5 8544 u32 i, offset, len, b_offset, b_count;
a9dc529d 8545 __be32 val;
1da177e4 8546
bc1c7567
MC		 8547 if (tp->link_config.phy_is_low_power)
8548 return -EAGAIN;
8549
1da177e4
LT		 8550 offset = eeprom->offset;
8551 len = eeprom->len;
8552 eeprom->len = 0;
8553
8554 eeprom->magic = TG3_EEPROM_MAGIC;
8555
8556 if (offset & 3) {
8557 /* adjustments to start on required 4 byte boundary */
8558 b_offset = offset & 3;
8559 b_count = 4 - b_offset;
8560 if (b_count > len) {
8561 /* i.e. offset=1 len=2 */
8562 b_count = len;
8563 }
a9dc529d 8564 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8565 if (ret)
8566 return ret;
1da177e4
LT		 8567 memcpy(data, ((char*)&val) + b_offset, b_count);
8568 len -= b_count;
8569 offset += b_count;
8570 eeprom->len += b_count;
8571 }
8572
8573 /* read bytes upto the last 4 byte boundary */
8574 pd = &data[eeprom->len];
8575 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8576 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8577 if (ret) {
8578 eeprom->len += i;
8579 return ret;
8580 }
1da177e4
LT		 8581 memcpy(pd + i, &val, 4);
8582 }
8583 eeprom->len += i;
8584
8585 if (len & 3) {
8586 /* read last bytes not ending on 4 byte boundary */
8587 pd = &data[eeprom->len];
8588 b_count = len & 3;
8589 b_offset = offset + len - b_count;
a9dc529d 8590 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8591 if (ret)
8592 return ret;
b9fc7dc5 8593 memcpy(pd, &val, b_count);
1da177e4
LT		 8594 eeprom->len += b_count;
8595 }
8596 return 0;
8597}
8598
6aa20a22 8599static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8600
8601static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8602{
8603 struct tg3 *tp = netdev_priv(dev);
8604 int ret;
b9fc7dc5 8605 u32 offset, len, b_offset, odd_len;
1da177e4 8606 u8 *buf;
a9dc529d 8607 __be32 start, end;
1da177e4 8608
bc1c7567
MC		 8609 if (tp->link_config.phy_is_low_power)
8610 return -EAGAIN;
8611
1da177e4
LT		 8612 if (eeprom->magic != TG3_EEPROM_MAGIC)
8613 return -EINVAL;
8614
8615 offset = eeprom->offset;
8616 len = eeprom->len;
8617
8618 if ((b_offset = (offset & 3))) {
8619 /* adjustments to start on required 4 byte boundary */
a9dc529d 8620 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8621 if (ret)
8622 return ret;
1da177e4
LT		 8623 len += b_offset;
8624 offset &= ~3;
1c8594b4
MC		 8625 if (len < 4)
8626 len = 4;
1da177e4
LT		 8627 }
8628
8629 odd_len = 0;
1c8594b4 8630 if (len & 3) {
1da177e4
LT		 8631 /* adjustments to end on required 4 byte boundary */
8632 odd_len = 1;
8633 len = (len + 3) & ~3;
a9dc529d 8634 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8635 if (ret)
8636 return ret;
1da177e4
LT		 8637 }
8638
8639 buf = data;
8640 if (b_offset || odd_len) {
8641 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8642 if (!buf)
1da177e4
LT		 8643 return -ENOMEM;
8644 if (b_offset)
8645 memcpy(buf, &start, 4);
8646 if (odd_len)
8647 memcpy(buf+len-4, &end, 4);
8648 memcpy(buf + b_offset, data, eeprom->len);
8649 }
8650
8651 ret = tg3_nvram_write_block(tp, offset, len, buf);
8652
8653 if (buf != data)
8654 kfree(buf);
8655
8656 return ret;
8657}
8658
8659static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8660{
b02fd9e3
MC		 8661 struct tg3 *tp = netdev_priv(dev);
8662
8663 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8664 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8665 return -EAGAIN;
298cf9be 8666 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8667 }
6aa20a22 8668
1da177e4
LT		 8669 cmd->supported = (SUPPORTED_Autoneg);
8670
8671 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8672 cmd->supported |= (SUPPORTED_1000baseT_Half |
8673 SUPPORTED_1000baseT_Full);
8674
ef348144 8675 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8676 cmd->supported |= (SUPPORTED_100baseT_Half |
8677 SUPPORTED_100baseT_Full |
8678 SUPPORTED_10baseT_Half |
8679 SUPPORTED_10baseT_Full |
3bebab59 8680 SUPPORTED_TP);
ef348144
KK		 8681 cmd->port = PORT_TP;
8682 } else {
1da177e4 8683 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8684 cmd->port = PORT_FIBRE;
8685 }
6aa20a22 8686
1da177e4
LT		 8687 cmd->advertising = tp->link_config.advertising;
8688 if (netif_running(dev)) {
8689 cmd->speed = tp->link_config.active_speed;
8690 cmd->duplex = tp->link_config.active_duplex;
8691 }
1da177e4 8692 cmd->phy_address = PHY_ADDR;
7e5856bd 8693 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8694 cmd->autoneg = tp->link_config.autoneg;
8695 cmd->maxtxpkt = 0;
8696 cmd->maxrxpkt = 0;
8697 return 0;
8698}
6aa20a22 8699
1da177e4
LT		 8700static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8701{
8702 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8703
b02fd9e3
MC		 8704 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8705 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8706 return -EAGAIN;
298cf9be 8707 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8708 }
8709
7e5856bd
MC		 8710 if (cmd->autoneg != AUTONEG_ENABLE &&
8711 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8712 return -EINVAL;
7e5856bd
MC		 8713
8714 if (cmd->autoneg == AUTONEG_DISABLE &&
8715 cmd->duplex != DUPLEX_FULL &&
8716 cmd->duplex != DUPLEX_HALF)
37ff238d 8717 return -EINVAL;
1da177e4 8718
7e5856bd
MC		 8719 if (cmd->autoneg == AUTONEG_ENABLE) {
8720 u32 mask = ADVERTISED_Autoneg |
8721 ADVERTISED_Pause |
8722 ADVERTISED_Asym_Pause;
8723
8724 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8725 mask |= ADVERTISED_1000baseT_Half |
8726 ADVERTISED_1000baseT_Full;
8727
8728 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8729 mask |= ADVERTISED_100baseT_Half |
8730 ADVERTISED_100baseT_Full |
8731 ADVERTISED_10baseT_Half |
8732 ADVERTISED_10baseT_Full |
8733 ADVERTISED_TP;
8734 else
8735 mask |= ADVERTISED_FIBRE;
8736
8737 if (cmd->advertising & ~mask)
8738 return -EINVAL;
8739
8740 mask &= (ADVERTISED_1000baseT_Half |
8741 ADVERTISED_1000baseT_Full |
8742 ADVERTISED_100baseT_Half |
8743 ADVERTISED_100baseT_Full |
8744 ADVERTISED_10baseT_Half |
8745 ADVERTISED_10baseT_Full);
8746
8747 cmd->advertising &= mask;
8748 } else {
8749 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8750 if (cmd->speed != SPEED_1000)
8751 return -EINVAL;
8752
8753 if (cmd->duplex != DUPLEX_FULL)
8754 return -EINVAL;
8755 } else {
8756 if (cmd->speed != SPEED_100 &&
8757 cmd->speed != SPEED_10)
8758 return -EINVAL;
8759 }
8760 }
8761
f47c11ee 8762 tg3_full_lock(tp, 0);
1da177e4
LT		 8763
8764 tp->link_config.autoneg = cmd->autoneg;
8765 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8766 tp->link_config.advertising = (cmd->advertising |
8767 ADVERTISED_Autoneg);
1da177e4
LT		 8768 tp->link_config.speed = SPEED_INVALID;
8769 tp->link_config.duplex = DUPLEX_INVALID;
8770 } else {
8771 tp->link_config.advertising = 0;
8772 tp->link_config.speed = cmd->speed;
8773 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8774 }
6aa20a22 8775
24fcad6b
MC		 8776 tp->link_config.orig_speed = tp->link_config.speed;
8777 tp->link_config.orig_duplex = tp->link_config.duplex;
8778 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8779
1da177e4
LT		 8780 if (netif_running(dev))
8781 tg3_setup_phy(tp, 1);
8782
f47c11ee 8783 tg3_full_unlock(tp);
6aa20a22 8784
1da177e4
LT		 8785 return 0;
8786}
6aa20a22 8787
1da177e4
LT		 8788static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8789{
8790 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8791
1da177e4
LT		 8792 strcpy(info->driver, DRV_MODULE_NAME);
8793 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8794 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8795 strcpy(info->bus_info, pci_name(tp->pdev));
8796}
6aa20a22 8797
1da177e4
LT		 8798static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8799{
8800 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8801
12dac075
RW		 8802 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8803 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8804 wol->supported = WAKE_MAGIC;
8805 else
8806 wol->supported = 0;
1da177e4 8807 wol->wolopts = 0;
05ac4cb7
MC		 8808 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8809 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8810 wol->wolopts = WAKE_MAGIC;
8811 memset(&wol->sopass, 0, sizeof(wol->sopass));
8812}
6aa20a22 8813
1da177e4
LT		 8814static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8815{
8816 struct tg3 *tp = netdev_priv(dev);
12dac075 8817 struct device *dp = &tp->pdev->dev;
6aa20a22 8818
1da177e4
LT		 8819 if (wol->wolopts & ~WAKE_MAGIC)
8820 return -EINVAL;
8821 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8822 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8823 return -EINVAL;
6aa20a22 8824
f47c11ee 8825 spin_lock_bh(&tp->lock);
12dac075 8826 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8827 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8828 device_set_wakeup_enable(dp, true);
8829 } else {
1da177e4 8830 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8831 device_set_wakeup_enable(dp, false);
8832 }
f47c11ee 8833 spin_unlock_bh(&tp->lock);
6aa20a22 8834
1da177e4
LT		 8835 return 0;
8836}
6aa20a22 8837
1da177e4
LT		 8838static u32 tg3_get_msglevel(struct net_device *dev)
8839{
8840 struct tg3 *tp = netdev_priv(dev);
8841 return tp->msg_enable;
8842}
6aa20a22 8843
1da177e4
LT		 8844static void tg3_set_msglevel(struct net_device *dev, u32 value)
8845{
8846 struct tg3 *tp = netdev_priv(dev);
8847 tp->msg_enable = value;
8848}
6aa20a22 8849
1da177e4
LT		 8850static int tg3_set_tso(struct net_device *dev, u32 value)
8851{
8852 struct tg3 *tp = netdev_priv(dev);
8853
8854 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8855 if (value)
8856 return -EINVAL;
8857 return 0;
8858 }
027455ad
MC		 8859 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8860 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 8861 if (value) {
b0026624 8862 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 8863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8864 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8865 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 8866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 8868 dev->features |= NETIF_F_TSO_ECN;
8869 } else
8870 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8871 }
1da177e4
LT		 8872 return ethtool_op_set_tso(dev, value);
8873}
6aa20a22 8874
1da177e4
LT		 8875static int tg3_nway_reset(struct net_device *dev)
8876{
8877 struct tg3 *tp = netdev_priv(dev);
1da177e4 8878 int r;
6aa20a22 8879
1da177e4
LT		 8880 if (!netif_running(dev))
8881 return -EAGAIN;
8882
c94e3941
MC		 8883 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8884 return -EINVAL;
8885
b02fd9e3
MC		 8886 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8887 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8888 return -EAGAIN;
298cf9be 8889 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 8890 } else {
8891 u32 bmcr;
8892
8893 spin_lock_bh(&tp->lock);
8894 r = -EINVAL;
8895 tg3_readphy(tp, MII_BMCR, &bmcr);
8896 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8897 ((bmcr & BMCR_ANENABLE) ||
8898 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8899 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8900 BMCR_ANENABLE);
8901 r = 0;
8902 }
8903 spin_unlock_bh(&tp->lock);
1da177e4 8904 }
6aa20a22 8905
1da177e4
LT		 8906 return r;
8907}
6aa20a22 8908
1da177e4
LT		 8909static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8910{
8911 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8912
1da177e4
LT		 8913 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8914 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8915 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8916 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8917 else
8918 ering->rx_jumbo_max_pending = 0;
8919
8920 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8921
8922 ering->rx_pending = tp->rx_pending;
8923 ering->rx_mini_pending = 0;
4f81c32b
MC		 8924 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8925 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8926 else
8927 ering->rx_jumbo_pending = 0;
8928
1da177e4
LT		 8929 ering->tx_pending = tp->tx_pending;
8930}
6aa20a22 8931
1da177e4
LT		 8932static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8933{
8934 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8935 int irq_sync = 0, err = 0;
6aa20a22 8936
1da177e4
LT		 8937 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8938 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8939 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8940 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8941 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8942 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8943 return -EINVAL;
6aa20a22 8944
bbe832c0 8945 if (netif_running(dev)) {
b02fd9e3 8946 tg3_phy_stop(tp);
1da177e4 8947 tg3_netif_stop(tp);
bbe832c0
MC		 8948 irq_sync = 1;
8949 }
1da177e4 8950
bbe832c0 8951 tg3_full_lock(tp, irq_sync);
6aa20a22 8952
1da177e4
LT		 8953 tp->rx_pending = ering->rx_pending;
8954
8955 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8956 tp->rx_pending > 63)
8957 tp->rx_pending = 63;
8958 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8959 tp->tx_pending = ering->tx_pending;
8960
8961 if (netif_running(dev)) {
944d980e 8962 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8963 err = tg3_restart_hw(tp, 1);
8964 if (!err)
8965 tg3_netif_start(tp);
1da177e4
LT		 8966 }
8967
f47c11ee 8968 tg3_full_unlock(tp);
6aa20a22 8969
b02fd9e3
MC		 8970 if (irq_sync && !err)
8971 tg3_phy_start(tp);
8972
b9ec6c1b 8973 return err;
1da177e4 8974}
6aa20a22 8975
1da177e4
LT		 8976static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8977{
8978 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8979
1da177e4 8980 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 8981
e18ce346 8982 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 8983 epause->rx_pause = 1;
8984 else
8985 epause->rx_pause = 0;
8986
e18ce346 8987 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 8988 epause->tx_pause = 1;
8989 else
8990 epause->tx_pause = 0;
1da177e4 8991}
6aa20a22 8992
1da177e4
LT		 8993static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8994{
8995 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 8996 int err = 0;
6aa20a22 8997
b02fd9e3
MC		 8998 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8999 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9000 return -EAGAIN;
1da177e4 9001
b02fd9e3
MC		 9002 if (epause->autoneg) {
9003 u32 newadv;
9004 struct phy_device *phydev;
f47c11ee 9005
298cf9be 9006 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9007
b02fd9e3
MC		 9008 if (epause->rx_pause) {
9009 if (epause->tx_pause)
9010 newadv = ADVERTISED_Pause;
9011 else
9012 newadv = ADVERTISED_Pause |
9013 ADVERTISED_Asym_Pause;
9014 } else if (epause->tx_pause) {
9015 newadv = ADVERTISED_Asym_Pause;
9016 } else
9017 newadv = 0;
9018
9019 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9020 u32 oldadv = phydev->advertising &
9021 (ADVERTISED_Pause |
9022 ADVERTISED_Asym_Pause);
9023 if (oldadv != newadv) {
9024 phydev->advertising &=
9025 ~(ADVERTISED_Pause |
9026 ADVERTISED_Asym_Pause);
9027 phydev->advertising |= newadv;
9028 err = phy_start_aneg(phydev);
9029 }
9030 } else {
9031 tp->link_config.advertising &=
9032 ~(ADVERTISED_Pause |
9033 ADVERTISED_Asym_Pause);
9034 tp->link_config.advertising |= newadv;
9035 }
9036 } else {
9037 if (epause->rx_pause)
e18ce346 9038 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9039 else
e18ce346 9040 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9041
b02fd9e3 9042 if (epause->tx_pause)
e18ce346 9043 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9044 else
e18ce346 9045 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9046
9047 if (netif_running(dev))
9048 tg3_setup_flow_control(tp, 0, 0);
9049 }
9050 } else {
9051 int irq_sync = 0;
9052
9053 if (netif_running(dev)) {
9054 tg3_netif_stop(tp);
9055 irq_sync = 1;
9056 }
9057
9058 tg3_full_lock(tp, irq_sync);
9059
9060 if (epause->autoneg)
9061 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9062 else
9063 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9064 if (epause->rx_pause)
e18ce346 9065 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9066 else
e18ce346 9067 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9068 if (epause->tx_pause)
e18ce346 9069 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9070 else
e18ce346 9071 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9072
9073 if (netif_running(dev)) {
9074 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9075 err = tg3_restart_hw(tp, 1);
9076 if (!err)
9077 tg3_netif_start(tp);
9078 }
9079
9080 tg3_full_unlock(tp);
9081 }
6aa20a22 9082
b9ec6c1b 9083 return err;
1da177e4 9084}
6aa20a22 9085
1da177e4
LT		 9086static u32 tg3_get_rx_csum(struct net_device *dev)
9087{
9088 struct tg3 *tp = netdev_priv(dev);
9089 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9090}
6aa20a22 9091
1da177e4
LT		 9092static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9093{
9094 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9095
1da177e4
LT		 9096 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9097 if (data != 0)
9098 return -EINVAL;
9099 return 0;
9100 }
6aa20a22 9101
f47c11ee 9102 spin_lock_bh(&tp->lock);
1da177e4
LT		 9103 if (data)
9104 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9105 else
9106 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9107 spin_unlock_bh(&tp->lock);
6aa20a22 9108
1da177e4
LT		 9109 return 0;
9110}
6aa20a22 9111
1da177e4
LT		 9112static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9113{
9114 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9115
1da177e4
LT		 9116 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9117 if (data != 0)
9118 return -EINVAL;
9119 return 0;
9120 }
6aa20a22 9121
321d32a0 9122 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9123 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9124 else
9c27dbdf 9125 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9126
9127 return 0;
9128}
9129
b9f2c044 9130static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9131{
b9f2c044
JG		 9132 switch (sset) {
9133 case ETH_SS_TEST:
9134 return TG3_NUM_TEST;
9135 case ETH_SS_STATS:
9136 return TG3_NUM_STATS;
9137 default:
9138 return -EOPNOTSUPP;
9139 }
4cafd3f5
MC		 9140}
9141
1da177e4
LT		 9142static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9143{
9144 switch (stringset) {
9145 case ETH_SS_STATS:
9146 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9147 break;
4cafd3f5
MC		 9148 case ETH_SS_TEST:
9149 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9150 break;
1da177e4
LT		 9151 default:
9152 WARN_ON(1); /* we need a WARN() */
9153 break;
9154 }
9155}
9156
4009a93d
MC		 9157static int tg3_phys_id(struct net_device *dev, u32 data)
9158{
9159 struct tg3 *tp = netdev_priv(dev);
9160 int i;
9161
9162 if (!netif_running(tp->dev))
9163 return -EAGAIN;
9164
9165 if (data == 0)
759afc31 9166 data = UINT_MAX / 2;
4009a93d
MC		 9167
9168 for (i = 0; i < (data * 2); i++) {
9169 if ((i % 2) == 0)
9170 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9171 LED_CTRL_1000MBPS_ON |
9172 LED_CTRL_100MBPS_ON |
9173 LED_CTRL_10MBPS_ON |
9174 LED_CTRL_TRAFFIC_OVERRIDE |
9175 LED_CTRL_TRAFFIC_BLINK |
9176 LED_CTRL_TRAFFIC_LED);
6aa20a22 9177
4009a93d
MC		 9178 else
9179 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9180 LED_CTRL_TRAFFIC_OVERRIDE);
9181
9182 if (msleep_interruptible(500))
9183 break;
9184 }
9185 tw32(MAC_LED_CTRL, tp->led_ctrl);
9186 return 0;
9187}
9188
1da177e4
LT		 9189static void tg3_get_ethtool_stats (struct net_device *dev,
9190 struct ethtool_stats *estats, u64 *tmp_stats)
9191{
9192 struct tg3 *tp = netdev_priv(dev);
9193 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9194}
9195
566f86ad 9196#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9197#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9198#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9199#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9200#define NVRAM_SELFBOOT_HW_SIZE 0x20
9201#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9202
9203static int tg3_test_nvram(struct tg3 *tp)
9204{
b9fc7dc5 9205 u32 csum, magic;
a9dc529d 9206 __be32 *buf;
ab0049b4 9207 int i, j, k, err = 0, size;
566f86ad 9208
e4f34110 9209 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9210 return -EIO;
9211
1b27777a
MC		 9212 if (magic == TG3_EEPROM_MAGIC)
9213 size = NVRAM_TEST_SIZE;
b16250e3 9214 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9215 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9216 TG3_EEPROM_SB_FORMAT_1) {
9217 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9218 case TG3_EEPROM_SB_REVISION_0:
9219 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9220 break;
9221 case TG3_EEPROM_SB_REVISION_2:
9222 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9223 break;
9224 case TG3_EEPROM_SB_REVISION_3:
9225 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9226 break;
9227 default:
9228 return 0;
9229 }
9230 } else
1b27777a 9231 return 0;
b16250e3
MC		 9232 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9233 size = NVRAM_SELFBOOT_HW_SIZE;
9234 else
1b27777a
MC		 9235 return -EIO;
9236
9237 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9238 if (buf == NULL)
9239 return -ENOMEM;
9240
1b27777a
MC		 9241 err = -EIO;
9242 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9243 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9244 if (err)
566f86ad 9245 break;
566f86ad 9246 }
1b27777a 9247 if (i < size)
566f86ad
MC		 9248 goto out;
9249
1b27777a 9250 /* Selfboot format */
a9dc529d 9251 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9252 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9253 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9254 u8 *buf8 = (u8 *) buf, csum8 = 0;
9255
b9fc7dc5 9256 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9257 TG3_EEPROM_SB_REVISION_2) {
9258 /* For rev 2, the csum doesn't include the MBA. */
9259 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9260 csum8 += buf8[i];
9261 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9262 csum8 += buf8[i];
9263 } else {
9264 for (i = 0; i < size; i++)
9265 csum8 += buf8[i];
9266 }
1b27777a 9267
ad96b485
AB		 9268 if (csum8 == 0) {
9269 err = 0;
9270 goto out;
9271 }
9272
9273 err = -EIO;
9274 goto out;
1b27777a 9275 }
566f86ad 9276
b9fc7dc5 9277 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9278 TG3_EEPROM_MAGIC_HW) {
9279 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9280 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9281 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9282
9283 /* Separate the parity bits and the data bytes. */
9284 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9285 if ((i == 0) || (i == 8)) {
9286 int l;
9287 u8 msk;
9288
9289 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9290 parity[k++] = buf8[i] & msk;
9291 i++;
9292 }
9293 else if (i == 16) {
9294 int l;
9295 u8 msk;
9296
9297 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9298 parity[k++] = buf8[i] & msk;
9299 i++;
9300
9301 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9302 parity[k++] = buf8[i] & msk;
9303 i++;
9304 }
9305 data[j++] = buf8[i];
9306 }
9307
9308 err = -EIO;
9309 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9310 u8 hw8 = hweight8(data[i]);
9311
9312 if ((hw8 & 0x1) && parity[i])
9313 goto out;
9314 else if (!(hw8 & 0x1) && !parity[i])
9315 goto out;
9316 }
9317 err = 0;
9318 goto out;
9319 }
9320
566f86ad
MC		 9321 /* Bootstrap checksum at offset 0x10 */
9322 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9323 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9324 goto out;
9325
9326 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9327 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9328 if (csum != be32_to_cpu(buf[0xfc/4]))
9329 goto out;
566f86ad
MC		 9330
9331 err = 0;
9332
9333out:
9334 kfree(buf);
9335 return err;
9336}
9337
ca43007a
MC		 9338#define TG3_SERDES_TIMEOUT_SEC 2
9339#define TG3_COPPER_TIMEOUT_SEC 6
9340
9341static int tg3_test_link(struct tg3 *tp)
9342{
9343 int i, max;
9344
9345 if (!netif_running(tp->dev))
9346 return -ENODEV;
9347
4c987487 9348 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9349 max = TG3_SERDES_TIMEOUT_SEC;
9350 else
9351 max = TG3_COPPER_TIMEOUT_SEC;
9352
9353 for (i = 0; i < max; i++) {
9354 if (netif_carrier_ok(tp->dev))
9355 return 0;
9356
9357 if (msleep_interruptible(1000))
9358 break;
9359 }
9360
9361 return -EIO;
9362}
9363
a71116d1 9364/* Only test the commonly used registers */
30ca3e37 9365static int tg3_test_registers(struct tg3 *tp)
a71116d1 9366{
b16250e3 9367 int i, is_5705, is_5750;
a71116d1
MC		 9368 u32 offset, read_mask, write_mask, val, save_val, read_val;
9369 static struct {
9370 u16 offset;
9371 u16 flags;
9372#define TG3_FL_5705 0x1
9373#define TG3_FL_NOT_5705 0x2
9374#define TG3_FL_NOT_5788 0x4
b16250e3 9375#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9376 u32 read_mask;
9377 u32 write_mask;
9378 } reg_tbl[] = {
9379 /* MAC Control Registers */
9380 { MAC_MODE, TG3_FL_NOT_5705,
9381 0x00000000, 0x00ef6f8c },
9382 { MAC_MODE, TG3_FL_5705,
9383 0x00000000, 0x01ef6b8c },
9384 { MAC_STATUS, TG3_FL_NOT_5705,
9385 0x03800107, 0x00000000 },
9386 { MAC_STATUS, TG3_FL_5705,
9387 0x03800100, 0x00000000 },
9388 { MAC_ADDR_0_HIGH, 0x0000,
9389 0x00000000, 0x0000ffff },
9390 { MAC_ADDR_0_LOW, 0x0000,
9391 0x00000000, 0xffffffff },
9392 { MAC_RX_MTU_SIZE, 0x0000,
9393 0x00000000, 0x0000ffff },
9394 { MAC_TX_MODE, 0x0000,
9395 0x00000000, 0x00000070 },
9396 { MAC_TX_LENGTHS, 0x0000,
9397 0x00000000, 0x00003fff },
9398 { MAC_RX_MODE, TG3_FL_NOT_5705,
9399 0x00000000, 0x000007fc },
9400 { MAC_RX_MODE, TG3_FL_5705,
9401 0x00000000, 0x000007dc },
9402 { MAC_HASH_REG_0, 0x0000,
9403 0x00000000, 0xffffffff },
9404 { MAC_HASH_REG_1, 0x0000,
9405 0x00000000, 0xffffffff },
9406 { MAC_HASH_REG_2, 0x0000,
9407 0x00000000, 0xffffffff },
9408 { MAC_HASH_REG_3, 0x0000,
9409 0x00000000, 0xffffffff },
9410
9411 /* Receive Data and Receive BD Initiator Control Registers. */
9412 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9413 0x00000000, 0xffffffff },
9414 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9415 0x00000000, 0xffffffff },
9416 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9417 0x00000000, 0x00000003 },
9418 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9419 0x00000000, 0xffffffff },
9420 { RCVDBDI_STD_BD+0, 0x0000,
9421 0x00000000, 0xffffffff },
9422 { RCVDBDI_STD_BD+4, 0x0000,
9423 0x00000000, 0xffffffff },
9424 { RCVDBDI_STD_BD+8, 0x0000,
9425 0x00000000, 0xffff0002 },
9426 { RCVDBDI_STD_BD+0xc, 0x0000,
9427 0x00000000, 0xffffffff },
6aa20a22 9428
a71116d1
MC		 9429 /* Receive BD Initiator Control Registers. */
9430 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9431 0x00000000, 0xffffffff },
9432 { RCVBDI_STD_THRESH, TG3_FL_5705,
9433 0x00000000, 0x000003ff },
9434 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9435 0x00000000, 0xffffffff },
6aa20a22 9436
a71116d1
MC		 9437 /* Host Coalescing Control Registers. */
9438 { HOSTCC_MODE, TG3_FL_NOT_5705,
9439 0x00000000, 0x00000004 },
9440 { HOSTCC_MODE, TG3_FL_5705,
9441 0x00000000, 0x000000f6 },
9442 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9443 0x00000000, 0xffffffff },
9444 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9445 0x00000000, 0x000003ff },
9446 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9447 0x00000000, 0xffffffff },
9448 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9449 0x00000000, 0x000003ff },
9450 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9451 0x00000000, 0xffffffff },
9452 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9453 0x00000000, 0x000000ff },
9454 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9455 0x00000000, 0xffffffff },
9456 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9457 0x00000000, 0x000000ff },
9458 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9459 0x00000000, 0xffffffff },
9460 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9461 0x00000000, 0xffffffff },
9462 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9463 0x00000000, 0xffffffff },
9464 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9465 0x00000000, 0x000000ff },
9466 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9467 0x00000000, 0xffffffff },
9468 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9469 0x00000000, 0x000000ff },
9470 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9471 0x00000000, 0xffffffff },
9472 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9473 0x00000000, 0xffffffff },
9474 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9475 0x00000000, 0xffffffff },
9476 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9477 0x00000000, 0xffffffff },
9478 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9479 0x00000000, 0xffffffff },
9480 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9481 0xffffffff, 0x00000000 },
9482 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9483 0xffffffff, 0x00000000 },
9484
9485 /* Buffer Manager Control Registers. */
b16250e3 9486 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9487 0x00000000, 0x007fff80 },
b16250e3 9488 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9489 0x00000000, 0x007fffff },
9490 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9491 0x00000000, 0x0000003f },
9492 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9493 0x00000000, 0x000001ff },
9494 { BUFMGR_MB_HIGH_WATER, 0x0000,
9495 0x00000000, 0x000001ff },
9496 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9497 0xffffffff, 0x00000000 },
9498 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9499 0xffffffff, 0x00000000 },
6aa20a22 9500
a71116d1
MC		 9501 /* Mailbox Registers */
9502 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9503 0x00000000, 0x000001ff },
9504 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9505 0x00000000, 0x000001ff },
9506 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9507 0x00000000, 0x000007ff },
9508 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9509 0x00000000, 0x000001ff },
9510
9511 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9512 };
9513
b16250e3
MC		 9514 is_5705 = is_5750 = 0;
9515 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9516 is_5705 = 1;
b16250e3
MC		 9517 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9518 is_5750 = 1;
9519 }
a71116d1
MC		 9520
9521 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9522 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9523 continue;
9524
9525 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9526 continue;
9527
9528 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9529 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9530 continue;
9531
b16250e3
MC		 9532 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9533 continue;
9534
a71116d1
MC		 9535 offset = (u32) reg_tbl[i].offset;
9536 read_mask = reg_tbl[i].read_mask;
9537 write_mask = reg_tbl[i].write_mask;
9538
9539 /* Save the original register content */
9540 save_val = tr32(offset);
9541
9542 /* Determine the read-only value. */
9543 read_val = save_val & read_mask;
9544
9545 /* Write zero to the register, then make sure the read-only bits
9546 * are not changed and the read/write bits are all zeros.
9547 */
9548 tw32(offset, 0);
9549
9550 val = tr32(offset);
9551
9552 /* Test the read-only and read/write bits. */
9553 if (((val & read_mask) != read_val) || (val & write_mask))
9554 goto out;
9555
9556 /* Write ones to all the bits defined by RdMask and WrMask, then
9557 * make sure the read-only bits are not changed and the
9558 * read/write bits are all ones.
9559 */
9560 tw32(offset, read_mask | write_mask);
9561
9562 val = tr32(offset);
9563
9564 /* Test the read-only bits. */
9565 if ((val & read_mask) != read_val)
9566 goto out;
9567
9568 /* Test the read/write bits. */
9569 if ((val & write_mask) != write_mask)
9570 goto out;
9571
9572 tw32(offset, save_val);
9573 }
9574
9575 return 0;
9576
9577out:
9f88f29f
MC		 9578 if (netif_msg_hw(tp))
9579 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9580 offset);
a71116d1
MC		 9581 tw32(offset, save_val);
9582 return -EIO;
9583}
9584
7942e1db
MC		 9585static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9586{
f71e1309 9587 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9588 int i;
9589 u32 j;
9590
e9edda69 9591 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9592 for (j = 0; j < len; j += 4) {
9593 u32 val;
9594
9595 tg3_write_mem(tp, offset + j, test_pattern[i]);
9596 tg3_read_mem(tp, offset + j, &val);
9597 if (val != test_pattern[i])
9598 return -EIO;
9599 }
9600 }
9601 return 0;
9602}
9603
9604static int tg3_test_memory(struct tg3 *tp)
9605{
9606 static struct mem_entry {
9607 u32 offset;
9608 u32 len;
9609 } mem_tbl_570x[] = {
38690194 9610 { 0x00000000, 0x00b50},
7942e1db
MC		 9611 { 0x00002000, 0x1c000},
9612 { 0xffffffff, 0x00000}
9613 }, mem_tbl_5705[] = {
9614 { 0x00000100, 0x0000c},
9615 { 0x00000200, 0x00008},
7942e1db
MC		 9616 { 0x00004000, 0x00800},
9617 { 0x00006000, 0x01000},
9618 { 0x00008000, 0x02000},
9619 { 0x00010000, 0x0e000},
9620 { 0xffffffff, 0x00000}
79f4d13a
MC		 9621 }, mem_tbl_5755[] = {
9622 { 0x00000200, 0x00008},
9623 { 0x00004000, 0x00800},
9624 { 0x00006000, 0x00800},
9625 { 0x00008000, 0x02000},
9626 { 0x00010000, 0x0c000},
9627 { 0xffffffff, 0x00000}
b16250e3
MC		 9628 }, mem_tbl_5906[] = {
9629 { 0x00000200, 0x00008},
9630 { 0x00004000, 0x00400},
9631 { 0x00006000, 0x00400},
9632 { 0x00008000, 0x01000},
9633 { 0x00010000, 0x01000},
9634 { 0xffffffff, 0x00000}
7942e1db
MC		 9635 };
9636 struct mem_entry *mem_tbl;
9637 int err = 0;
9638 int i;
9639
321d32a0
MC		 9640 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9641 mem_tbl = mem_tbl_5755;
9642 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9643 mem_tbl = mem_tbl_5906;
9644 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9645 mem_tbl = mem_tbl_5705;
9646 else
7942e1db
MC		 9647 mem_tbl = mem_tbl_570x;
9648
9649 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9650 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9651 mem_tbl[i].len)) != 0)
9652 break;
9653 }
6aa20a22 9654
7942e1db
MC		 9655 return err;
9656}
9657
9f40dead
MC		 9658#define TG3_MAC_LOOPBACK 0
9659#define TG3_PHY_LOOPBACK 1
9660
9661static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9662{
9f40dead 9663 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9664 u32 desc_idx;
9665 struct sk_buff *skb, *rx_skb;
9666 u8 *tx_data;
9667 dma_addr_t map;
9668 int num_pkts, tx_len, rx_len, i, err;
9669 struct tg3_rx_buffer_desc *desc;
9670
9f40dead 9671 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9672 /* HW errata - mac loopback fails in some cases on 5780.
9673 * Normal traffic and PHY loopback are not affected by
9674 * errata.
9675 */
9676 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9677 return 0;
9678
9f40dead 9679 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9680 MAC_MODE_PORT_INT_LPBACK;
9681 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9682 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9683 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9684 mac_mode |= MAC_MODE_PORT_MODE_MII;
9685 else
9686 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9687 tw32(MAC_MODE, mac_mode);
9688 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9689 u32 val;
9690
b16250e3
MC		 9691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9692 u32 phytest;
9693
9694 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9695 u32 phy;
9696
9697 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9698 phytest | MII_TG3_EPHY_SHADOW_EN);
9699 if (!tg3_readphy(tp, 0x1b, &phy))
9700 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9701 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9702 }
5d64ad34
MC		 9703 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9704 } else
9705 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9706
9ef8ca99
MC		 9707 tg3_phy_toggle_automdix(tp, 0);
9708
3f7045c1 9709 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9710 udelay(40);
5d64ad34 9711
e8f3f6ca 9712 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9713 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9714 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9715 mac_mode |= MAC_MODE_PORT_MODE_MII;
9716 } else
9717 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9718
c94e3941
MC		 9719 /* reset to prevent losing 1st rx packet intermittently */
9720 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9721 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9722 udelay(10);
9723 tw32_f(MAC_RX_MODE, tp->rx_mode);
9724 }
e8f3f6ca
MC		 9725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9726 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9727 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9728 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9729 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9730 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9731 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9732 }
9f40dead 9733 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9734 }
9735 else
9736 return -EINVAL;
c76949a6
MC		 9737
9738 err = -EIO;
9739
c76949a6 9740 tx_len = 1514;
a20e9c62 9741 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9742 if (!skb)
9743 return -ENOMEM;
9744
c76949a6
MC		 9745 tx_data = skb_put(skb, tx_len);
9746 memcpy(tx_data, tp->dev->dev_addr, 6);
9747 memset(tx_data + 6, 0x0, 8);
9748
9749 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9750
9751 for (i = 14; i < tx_len; i++)
9752 tx_data[i] = (u8) (i & 0xff);
9753
9754 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9755
9756 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9757 HOSTCC_MODE_NOW);
9758
9759 udelay(10);
9760
9761 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9762
c76949a6
MC		 9763 num_pkts = 0;
9764
9f40dead 9765 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9766
9f40dead 9767 tp->tx_prod++;
c76949a6
MC		 9768 num_pkts++;
9769
9f40dead
MC		 9770 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9771 tp->tx_prod);
09ee929c 9772 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9773
9774 udelay(10);
9775
3f7045c1
MC		 9776 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9777 for (i = 0; i < 25; i++) {
c76949a6
MC		 9778 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9779 HOSTCC_MODE_NOW);
9780
9781 udelay(10);
9782
9783 tx_idx = tp->hw_status->idx[0].tx_consumer;
9784 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9785 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9786 (rx_idx == (rx_start_idx + num_pkts)))
9787 break;
9788 }
9789
9790 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9791 dev_kfree_skb(skb);
9792
9f40dead 9793 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9794 goto out;
9795
9796 if (rx_idx != rx_start_idx + num_pkts)
9797 goto out;
9798
9799 desc = &tp->rx_rcb[rx_start_idx];
9800 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9801 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9802 if (opaque_key != RXD_OPAQUE_RING_STD)
9803 goto out;
9804
9805 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9806 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9807 goto out;
9808
9809 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9810 if (rx_len != tx_len)
9811 goto out;
9812
9813 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9814
9815 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9816 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9817
9818 for (i = 14; i < tx_len; i++) {
9819 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9820 goto out;
9821 }
9822 err = 0;
6aa20a22 9823
c76949a6
MC		 9824 /* tg3_free_rings will unmap and free the rx_skb */
9825out:
9826 return err;
9827}
9828
9f40dead
MC		 9829#define TG3_MAC_LOOPBACK_FAILED 1
9830#define TG3_PHY_LOOPBACK_FAILED 2
9831#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9832 TG3_PHY_LOOPBACK_FAILED)
9833
9834static int tg3_test_loopback(struct tg3 *tp)
9835{
9836 int err = 0;
9936bcf6 9837 u32 cpmuctrl = 0;
9f40dead
MC		 9838
9839 if (!netif_running(tp->dev))
9840 return TG3_LOOPBACK_FAILED;
9841
b9ec6c1b
MC		 9842 err = tg3_reset_hw(tp, 1);
9843 if (err)
9844 return TG3_LOOPBACK_FAILED;
9f40dead 9845
6833c043
MC		 9846 /* Turn off gphy autopowerdown. */
9847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9848 tg3_phy_toggle_apd(tp, false);
9849
321d32a0 9850 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9851 int i;
9852 u32 status;
9853
9854 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9855
9856 /* Wait for up to 40 microseconds to acquire lock. */
9857 for (i = 0; i < 4; i++) {
9858 status = tr32(TG3_CPMU_MUTEX_GNT);
9859 if (status == CPMU_MUTEX_GNT_DRIVER)
9860 break;
9861 udelay(10);
9862 }
9863
9864 if (status != CPMU_MUTEX_GNT_DRIVER)
9865 return TG3_LOOPBACK_FAILED;
9866
b2a5c19c 9867 /* Turn off link-based power management. */
e875093c 9868 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 9869 tw32(TG3_CPMU_CTRL,
9870 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9871 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9872 }
9873
9f40dead
MC		 9874 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9875 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9876
321d32a0 9877 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9878 tw32(TG3_CPMU_CTRL, cpmuctrl);
9879
9880 /* Release the mutex */
9881 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9882 }
9883
dd477003
MC		 9884 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9885 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 9886 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9887 err |= TG3_PHY_LOOPBACK_FAILED;
9888 }
9889
6833c043
MC		 9890 /* Re-enable gphy autopowerdown. */
9891 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9892 tg3_phy_toggle_apd(tp, true);
9893
9f40dead
MC		 9894 return err;
9895}
9896
4cafd3f5
MC		 9897static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9898 u64 *data)
9899{
566f86ad
MC		 9900 struct tg3 *tp = netdev_priv(dev);
9901
bc1c7567
MC		 9902 if (tp->link_config.phy_is_low_power)
9903 tg3_set_power_state(tp, PCI_D0);
9904
566f86ad
MC		 9905 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9906
9907 if (tg3_test_nvram(tp) != 0) {
9908 etest->flags |= ETH_TEST_FL_FAILED;
9909 data[0] = 1;
9910 }
ca43007a
MC		 9911 if (tg3_test_link(tp) != 0) {
9912 etest->flags |= ETH_TEST_FL_FAILED;
9913 data[1] = 1;
9914 }
a71116d1 9915 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 9916 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 9917
9918 if (netif_running(dev)) {
b02fd9e3 9919 tg3_phy_stop(tp);
a71116d1 9920 tg3_netif_stop(tp);
bbe832c0
MC		 9921 irq_sync = 1;
9922 }
a71116d1 9923
bbe832c0 9924 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9925
9926 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9927 err = tg3_nvram_lock(tp);
a71116d1
MC		 9928 tg3_halt_cpu(tp, RX_CPU_BASE);
9929 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9930 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9931 if (!err)
9932 tg3_nvram_unlock(tp);
a71116d1 9933
d9ab5ad1
MC		 9934 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9935 tg3_phy_reset(tp);
9936
a71116d1
MC		 9937 if (tg3_test_registers(tp) != 0) {
9938 etest->flags |= ETH_TEST_FL_FAILED;
9939 data[2] = 1;
9940 }
7942e1db
MC		 9941 if (tg3_test_memory(tp) != 0) {
9942 etest->flags |= ETH_TEST_FL_FAILED;
9943 data[3] = 1;
9944 }
9f40dead 9945 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9946 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9947
f47c11ee
DM		 9948 tg3_full_unlock(tp);
9949
d4bc3927
MC		 9950 if (tg3_test_interrupt(tp) != 0) {
9951 etest->flags |= ETH_TEST_FL_FAILED;
9952 data[5] = 1;
9953 }
f47c11ee
DM		 9954
9955 tg3_full_lock(tp, 0);
d4bc3927 9956
a71116d1
MC		 9957 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9958 if (netif_running(dev)) {
9959 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 9960 err2 = tg3_restart_hw(tp, 1);
9961 if (!err2)
b9ec6c1b 9962 tg3_netif_start(tp);
a71116d1 9963 }
f47c11ee
DM		 9964
9965 tg3_full_unlock(tp);
b02fd9e3
MC		 9966
9967 if (irq_sync && !err2)
9968 tg3_phy_start(tp);
a71116d1 9969 }
bc1c7567
MC		 9970 if (tp->link_config.phy_is_low_power)
9971 tg3_set_power_state(tp, PCI_D3hot);
9972
4cafd3f5
MC		 9973}
9974
1da177e4
LT		 9975static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9976{
9977 struct mii_ioctl_data *data = if_mii(ifr);
9978 struct tg3 *tp = netdev_priv(dev);
9979 int err;
9980
b02fd9e3
MC		 9981 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9982 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9983 return -EAGAIN;
298cf9be 9984 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 9985 }
9986
1da177e4
LT		 9987 switch(cmd) {
9988 case SIOCGMIIPHY:
9989 data->phy_id = PHY_ADDR;
9990
9991 /* fallthru */
9992 case SIOCGMIIREG: {
9993 u32 mii_regval;
9994
9995 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9996 break; /* We have no PHY */
9997
bc1c7567
MC		 9998 if (tp->link_config.phy_is_low_power)
9999 return -EAGAIN;
10000
f47c11ee 10001 spin_lock_bh(&tp->lock);
1da177e4 10002 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10003 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10004
10005 data->val_out = mii_regval;
10006
10007 return err;
10008 }
10009
10010 case SIOCSMIIREG:
10011 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10012 break; /* We have no PHY */
10013
10014 if (!capable(CAP_NET_ADMIN))
10015 return -EPERM;
10016
bc1c7567
MC		 10017 if (tp->link_config.phy_is_low_power)
10018 return -EAGAIN;
10019
f47c11ee 10020 spin_lock_bh(&tp->lock);
1da177e4 10021 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10022 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10023
10024 return err;
10025
10026 default:
10027 /* do nothing */
10028 break;
10029 }
10030 return -EOPNOTSUPP;
10031}
10032
10033#if TG3_VLAN_TAG_USED
10034static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10035{
10036 struct tg3 *tp = netdev_priv(dev);
10037
844b3eed
MC		 10038 if (!netif_running(dev)) {
10039 tp->vlgrp = grp;
10040 return;
10041 }
10042
10043 tg3_netif_stop(tp);
29315e87 10044
f47c11ee 10045 tg3_full_lock(tp, 0);
1da177e4
LT		 10046
10047 tp->vlgrp = grp;
10048
10049 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10050 __tg3_set_rx_mode(dev);
10051
844b3eed 10052 tg3_netif_start(tp);
46966545
MC		 10053
10054 tg3_full_unlock(tp);
1da177e4 10055}
1da177e4
LT		 10056#endif
10057
15f9850d
DM		 10058static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10059{
10060 struct tg3 *tp = netdev_priv(dev);
10061
10062 memcpy(ec, &tp->coal, sizeof(*ec));
10063 return 0;
10064}
10065
d244c892
MC		 10066static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10067{
10068 struct tg3 *tp = netdev_priv(dev);
10069 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10070 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10071
10072 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10073 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10074 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10075 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10076 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10077 }
10078
10079 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10080 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10081 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10082 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10083 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10084 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10085 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10086 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10087 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10088 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10089 return -EINVAL;
10090
10091 /* No rx interrupts will be generated if both are zero */
10092 if ((ec->rx_coalesce_usecs == 0) &&
10093 (ec->rx_max_coalesced_frames == 0))
10094 return -EINVAL;
10095
10096 /* No tx interrupts will be generated if both are zero */
10097 if ((ec->tx_coalesce_usecs == 0) &&
10098 (ec->tx_max_coalesced_frames == 0))
10099 return -EINVAL;
10100
10101 /* Only copy relevant parameters, ignore all others. */
10102 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10103 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10104 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10105 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10106 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10107 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10108 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10109 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10110 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10111
10112 if (netif_running(dev)) {
10113 tg3_full_lock(tp, 0);
10114 __tg3_set_coalesce(tp, &tp->coal);
10115 tg3_full_unlock(tp);
10116 }
10117 return 0;
10118}
10119
7282d491 10120static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10121 .get_settings = tg3_get_settings,
10122 .set_settings = tg3_set_settings,
10123 .get_drvinfo = tg3_get_drvinfo,
10124 .get_regs_len = tg3_get_regs_len,
10125 .get_regs = tg3_get_regs,
10126 .get_wol = tg3_get_wol,
10127 .set_wol = tg3_set_wol,
10128 .get_msglevel = tg3_get_msglevel,
10129 .set_msglevel = tg3_set_msglevel,
10130 .nway_reset = tg3_nway_reset,
10131 .get_link = ethtool_op_get_link,
10132 .get_eeprom_len = tg3_get_eeprom_len,
10133 .get_eeprom = tg3_get_eeprom,
10134 .set_eeprom = tg3_set_eeprom,
10135 .get_ringparam = tg3_get_ringparam,
10136 .set_ringparam = tg3_set_ringparam,
10137 .get_pauseparam = tg3_get_pauseparam,
10138 .set_pauseparam = tg3_set_pauseparam,
10139 .get_rx_csum = tg3_get_rx_csum,
10140 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10141 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10142 .set_sg = ethtool_op_set_sg,
1da177e4 10143 .set_tso = tg3_set_tso,
4cafd3f5 10144 .self_test = tg3_self_test,
1da177e4 10145 .get_strings = tg3_get_strings,
4009a93d 10146 .phys_id = tg3_phys_id,
1da177e4 10147 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10148 .get_coalesce = tg3_get_coalesce,
d244c892 10149 .set_coalesce = tg3_set_coalesce,
b9f2c044 10150 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10151};
10152
10153static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10154{
1b27777a 10155 u32 cursize, val, magic;
1da177e4
LT		 10156
10157 tp->nvram_size = EEPROM_CHIP_SIZE;
10158
e4f34110 10159 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10160 return;
10161
b16250e3
MC		 10162 if ((magic != TG3_EEPROM_MAGIC) &&
10163 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10164 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10165 return;
10166
10167 /*
10168 * Size the chip by reading offsets at increasing powers of two.
10169 * When we encounter our validation signature, we know the addressing
10170 * has wrapped around, and thus have our chip size.
10171 */
1b27777a 10172 cursize = 0x10;
1da177e4
LT		 10173
10174 while (cursize < tp->nvram_size) {
e4f34110 10175 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10176 return;
10177
1820180b 10178 if (val == magic)
1da177e4
LT		 10179 break;
10180
10181 cursize <<= 1;
10182 }
10183
10184 tp->nvram_size = cursize;
10185}
6aa20a22 10186
1da177e4
LT		 10187static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10188{
10189 u32 val;
10190
e4f34110 10191 if (tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10192 return;
10193
10194 /* Selfboot format */
1820180b 10195 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10196 tg3_get_eeprom_size(tp);
10197 return;
10198 }
10199
6d348f2c 10200 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10201 if (val != 0) {
6d348f2c
MC		 10202 /* This is confusing. We want to operate on the
10203 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10204 * call will read from NVRAM and byteswap the data
10205 * according to the byteswapping settings for all
10206 * other register accesses. This ensures the data we
10207 * want will always reside in the lower 16-bits.
10208 * However, the data in NVRAM is in LE format, which
10209 * means the data from the NVRAM read will always be
10210 * opposite the endianness of the CPU. The 16-bit
10211 * byteswap then brings the data to CPU endianness.
10212 */
10213 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10214 return;
10215 }
10216 }
fd1122a2 10217 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10218}
10219
10220static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10221{
10222 u32 nvcfg1;
10223
10224 nvcfg1 = tr32(NVRAM_CFG1);
10225 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10226 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10227 }
10228 else {
10229 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10230 tw32(NVRAM_CFG1, nvcfg1);
10231 }
10232
4c987487 10233 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10234 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 10235 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10236 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10237 tp->nvram_jedecnum = JEDEC_ATMEL;
10238 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10239 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10240 break;
10241 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10242 tp->nvram_jedecnum = JEDEC_ATMEL;
10243 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10244 break;
10245 case FLASH_VENDOR_ATMEL_EEPROM:
10246 tp->nvram_jedecnum = JEDEC_ATMEL;
10247 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10248 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10249 break;
10250 case FLASH_VENDOR_ST:
10251 tp->nvram_jedecnum = JEDEC_ST;
10252 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10253 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10254 break;
10255 case FLASH_VENDOR_SAIFUN:
10256 tp->nvram_jedecnum = JEDEC_SAIFUN;
10257 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10258 break;
10259 case FLASH_VENDOR_SST_SMALL:
10260 case FLASH_VENDOR_SST_LARGE:
10261 tp->nvram_jedecnum = JEDEC_SST;
10262 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10263 break;
10264 }
10265 }
10266 else {
10267 tp->nvram_jedecnum = JEDEC_ATMEL;
10268 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10269 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10270 }
10271}
10272
361b4ac2
MC		 10273static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10274{
10275 u32 nvcfg1;
10276
10277 nvcfg1 = tr32(NVRAM_CFG1);
10278
e6af301b
MC		 10279 /* NVRAM protection for TPM */
10280 if (nvcfg1 & (1 << 27))
10281 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10282
361b4ac2
MC		 10283 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10284 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10285 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10286 tp->nvram_jedecnum = JEDEC_ATMEL;
10287 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10288 break;
10289 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10290 tp->nvram_jedecnum = JEDEC_ATMEL;
10291 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10292 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10293 break;
10294 case FLASH_5752VENDOR_ST_M45PE10:
10295 case FLASH_5752VENDOR_ST_M45PE20:
10296 case FLASH_5752VENDOR_ST_M45PE40:
10297 tp->nvram_jedecnum = JEDEC_ST;
10298 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10299 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10300 break;
10301 }
10302
10303 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10304 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10305 case FLASH_5752PAGE_SIZE_256:
10306 tp->nvram_pagesize = 256;
10307 break;
10308 case FLASH_5752PAGE_SIZE_512:
10309 tp->nvram_pagesize = 512;
10310 break;
10311 case FLASH_5752PAGE_SIZE_1K:
10312 tp->nvram_pagesize = 1024;
10313 break;
10314 case FLASH_5752PAGE_SIZE_2K:
10315 tp->nvram_pagesize = 2048;
10316 break;
10317 case FLASH_5752PAGE_SIZE_4K:
10318 tp->nvram_pagesize = 4096;
10319 break;
10320 case FLASH_5752PAGE_SIZE_264:
10321 tp->nvram_pagesize = 264;
10322 break;
10323 }
10324 }
10325 else {
10326 /* For eeprom, set pagesize to maximum eeprom size */
10327 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10328
10329 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10330 tw32(NVRAM_CFG1, nvcfg1);
10331 }
10332}
10333
d3c7b886
MC		 10334static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10335{
989a9d23 10336 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10337
10338 nvcfg1 = tr32(NVRAM_CFG1);
10339
10340 /* NVRAM protection for TPM */
989a9d23 10341 if (nvcfg1 & (1 << 27)) {
d3c7b886 10342 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10343 protect = 1;
10344 }
d3c7b886 10345
989a9d23
MC		 10346 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10347 switch (nvcfg1) {
d3c7b886
MC		 10348 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10349 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10350 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 10351 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 10352 tp->nvram_jedecnum = JEDEC_ATMEL;
10353 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10354 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10355 tp->nvram_pagesize = 264;
70b65a2d
MC		 10356 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10357 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
fd1122a2
MC		 10358 tp->nvram_size = (protect ? 0x3e200 :
10359 TG3_NVRAM_SIZE_512KB);
989a9d23 10360 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
fd1122a2
MC		 10361 tp->nvram_size = (protect ? 0x1f200 :
10362 TG3_NVRAM_SIZE_256KB);
989a9d23 10363 else
fd1122a2
MC		 10364 tp->nvram_size = (protect ? 0x1f200 :
10365 TG3_NVRAM_SIZE_128KB);
d3c7b886
MC		 10366 break;
10367 case FLASH_5752VENDOR_ST_M45PE10:
10368 case FLASH_5752VENDOR_ST_M45PE20:
10369 case FLASH_5752VENDOR_ST_M45PE40:
10370 tp->nvram_jedecnum = JEDEC_ST;
10371 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10372 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10373 tp->nvram_pagesize = 256;
989a9d23 10374 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
fd1122a2
MC		 10375 tp->nvram_size = (protect ?
10376 TG3_NVRAM_SIZE_64KB :
10377 TG3_NVRAM_SIZE_128KB);
989a9d23 10378 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
fd1122a2
MC		 10379 tp->nvram_size = (protect ?
10380 TG3_NVRAM_SIZE_64KB :
10381 TG3_NVRAM_SIZE_256KB);
989a9d23 10382 else
fd1122a2
MC		 10383 tp->nvram_size = (protect ?
10384 TG3_NVRAM_SIZE_128KB :
10385 TG3_NVRAM_SIZE_512KB);
d3c7b886
MC		 10386 break;
10387 }
10388}
10389
1b27777a
MC		 10390static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10391{
10392 u32 nvcfg1;
10393
10394 nvcfg1 = tr32(NVRAM_CFG1);
10395
10396 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10397 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10398 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10399 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10400 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10401 tp->nvram_jedecnum = JEDEC_ATMEL;
10402 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10403 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10404
10405 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10406 tw32(NVRAM_CFG1, nvcfg1);
10407 break;
10408 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10409 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10410 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10411 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10412 tp->nvram_jedecnum = JEDEC_ATMEL;
10413 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10414 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10415 tp->nvram_pagesize = 264;
10416 break;
10417 case FLASH_5752VENDOR_ST_M45PE10:
10418 case FLASH_5752VENDOR_ST_M45PE20:
10419 case FLASH_5752VENDOR_ST_M45PE40:
10420 tp->nvram_jedecnum = JEDEC_ST;
10421 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10422 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10423 tp->nvram_pagesize = 256;
10424 break;
10425 }
10426}
10427
6b91fa02
MC		 10428static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10429{
10430 u32 nvcfg1, protect = 0;
10431
10432 nvcfg1 = tr32(NVRAM_CFG1);
10433
10434 /* NVRAM protection for TPM */
10435 if (nvcfg1 & (1 << 27)) {
10436 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10437 protect = 1;
10438 }
10439
10440 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10441 switch (nvcfg1) {
10442 case FLASH_5761VENDOR_ATMEL_ADB021D:
10443 case FLASH_5761VENDOR_ATMEL_ADB041D:
10444 case FLASH_5761VENDOR_ATMEL_ADB081D:
10445 case FLASH_5761VENDOR_ATMEL_ADB161D:
10446 case FLASH_5761VENDOR_ATMEL_MDB021D:
10447 case FLASH_5761VENDOR_ATMEL_MDB041D:
10448 case FLASH_5761VENDOR_ATMEL_MDB081D:
10449 case FLASH_5761VENDOR_ATMEL_MDB161D:
10450 tp->nvram_jedecnum = JEDEC_ATMEL;
10451 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10452 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10453 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10454 tp->nvram_pagesize = 256;
10455 break;
10456 case FLASH_5761VENDOR_ST_A_M45PE20:
10457 case FLASH_5761VENDOR_ST_A_M45PE40:
10458 case FLASH_5761VENDOR_ST_A_M45PE80:
10459 case FLASH_5761VENDOR_ST_A_M45PE16:
10460 case FLASH_5761VENDOR_ST_M_M45PE20:
10461 case FLASH_5761VENDOR_ST_M_M45PE40:
10462 case FLASH_5761VENDOR_ST_M_M45PE80:
10463 case FLASH_5761VENDOR_ST_M_M45PE16:
10464 tp->nvram_jedecnum = JEDEC_ST;
10465 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10466 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10467 tp->nvram_pagesize = 256;
10468 break;
10469 }
10470
10471 if (protect) {
10472 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10473 } else {
10474 switch (nvcfg1) {
10475 case FLASH_5761VENDOR_ATMEL_ADB161D:
10476 case FLASH_5761VENDOR_ATMEL_MDB161D:
10477 case FLASH_5761VENDOR_ST_A_M45PE16:
10478 case FLASH_5761VENDOR_ST_M_M45PE16:
fd1122a2 10479 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
6b91fa02
MC		 10480 break;
10481 case FLASH_5761VENDOR_ATMEL_ADB081D:
10482 case FLASH_5761VENDOR_ATMEL_MDB081D:
10483 case FLASH_5761VENDOR_ST_A_M45PE80:
10484 case FLASH_5761VENDOR_ST_M_M45PE80:
fd1122a2 10485 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
6b91fa02
MC		 10486 break;
10487 case FLASH_5761VENDOR_ATMEL_ADB041D:
10488 case FLASH_5761VENDOR_ATMEL_MDB041D:
10489 case FLASH_5761VENDOR_ST_A_M45PE40:
10490 case FLASH_5761VENDOR_ST_M_M45PE40:
fd1122a2 10491 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
6b91fa02
MC		 10492 break;
10493 case FLASH_5761VENDOR_ATMEL_ADB021D:
10494 case FLASH_5761VENDOR_ATMEL_MDB021D:
10495 case FLASH_5761VENDOR_ST_A_M45PE20:
10496 case FLASH_5761VENDOR_ST_M_M45PE20:
fd1122a2 10497 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
6b91fa02
MC		 10498 break;
10499 }
10500 }
10501}
10502
b5d3772c
MC		 10503static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10504{
10505 tp->nvram_jedecnum = JEDEC_ATMEL;
10506 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10507 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10508}
10509
321d32a0
MC		 10510static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10511{
10512 u32 nvcfg1;
10513
10514 nvcfg1 = tr32(NVRAM_CFG1);
10515
10516 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10517 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10518 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10519 tp->nvram_jedecnum = JEDEC_ATMEL;
10520 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10521 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10522
10523 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10524 tw32(NVRAM_CFG1, nvcfg1);
10525 return;
10526 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10527 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10528 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10529 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10530 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10531 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10532 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10533 tp->nvram_jedecnum = JEDEC_ATMEL;
10534 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10535 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10536
10537 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10538 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10539 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10540 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10541 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10542 break;
10543 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10544 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10545 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10546 break;
10547 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10548 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10549 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10550 break;
10551 }
10552 break;
10553 case FLASH_5752VENDOR_ST_M45PE10:
10554 case FLASH_5752VENDOR_ST_M45PE20:
10555 case FLASH_5752VENDOR_ST_M45PE40:
10556 tp->nvram_jedecnum = JEDEC_ST;
10557 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10558 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10559
10560 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10561 case FLASH_5752VENDOR_ST_M45PE10:
10562 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10563 break;
10564 case FLASH_5752VENDOR_ST_M45PE20:
10565 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10566 break;
10567 case FLASH_5752VENDOR_ST_M45PE40:
10568 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10569 break;
10570 }
10571 break;
10572 default:
10573 return;
10574 }
10575
10576 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10577 case FLASH_5752PAGE_SIZE_256:
10578 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10579 tp->nvram_pagesize = 256;
10580 break;
10581 case FLASH_5752PAGE_SIZE_512:
10582 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10583 tp->nvram_pagesize = 512;
10584 break;
10585 case FLASH_5752PAGE_SIZE_1K:
10586 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10587 tp->nvram_pagesize = 1024;
10588 break;
10589 case FLASH_5752PAGE_SIZE_2K:
10590 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10591 tp->nvram_pagesize = 2048;
10592 break;
10593 case FLASH_5752PAGE_SIZE_4K:
10594 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10595 tp->nvram_pagesize = 4096;
10596 break;
10597 case FLASH_5752PAGE_SIZE_264:
10598 tp->nvram_pagesize = 264;
10599 break;
10600 case FLASH_5752PAGE_SIZE_528:
10601 tp->nvram_pagesize = 528;
10602 break;
10603 }
10604}
10605
1da177e4
LT		 10606/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10607static void __devinit tg3_nvram_init(struct tg3 *tp)
10608{
1da177e4
LT		 10609 tw32_f(GRC_EEPROM_ADDR,
10610 (EEPROM_ADDR_FSM_RESET |
10611 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10612 EEPROM_ADDR_CLKPERD_SHIFT)));
10613
9d57f01c 10614 msleep(1);
1da177e4
LT		 10615
10616 /* Enable seeprom accesses. */
10617 tw32_f(GRC_LOCAL_CTRL,
10618 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10619 udelay(100);
10620
10621 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10622 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10623 tp->tg3_flags |= TG3_FLAG_NVRAM;
10624
ec41c7df
MC		 10625 if (tg3_nvram_lock(tp)) {
10626 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10627 "tg3_nvram_init failed.\n", tp->dev->name);
10628 return;
10629 }
e6af301b 10630 tg3_enable_nvram_access(tp);
1da177e4 10631
989a9d23
MC		 10632 tp->nvram_size = 0;
10633
361b4ac2
MC		 10634 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10635 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10636 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10637 tg3_get_5755_nvram_info(tp);
d30cdd28 10638 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10639 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10641 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10642 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10643 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10644 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10645 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10646 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10647 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10648 else
10649 tg3_get_nvram_info(tp);
10650
989a9d23
MC		 10651 if (tp->nvram_size == 0)
10652 tg3_get_nvram_size(tp);
1da177e4 10653
e6af301b 10654 tg3_disable_nvram_access(tp);
381291b7 10655 tg3_nvram_unlock(tp);
1da177e4
LT		 10656
10657 } else {
10658 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10659
10660 tg3_get_eeprom_size(tp);
10661 }
10662}
10663
1da177e4
LT		 10664static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10665 u32 offset, u32 len, u8 *buf)
10666{
10667 int i, j, rc = 0;
10668 u32 val;
10669
10670 for (i = 0; i < len; i += 4) {
b9fc7dc5 10671 u32 addr;
a9dc529d 10672 __be32 data;
1da177e4
LT		 10673
10674 addr = offset + i;
10675
10676 memcpy(&data, buf + i, 4);
10677
62cedd11
MC		 10678 /*
10679 * The SEEPROM interface expects the data to always be opposite
10680 * the native endian format. We accomplish this by reversing
10681 * all the operations that would have been performed on the
10682 * data from a call to tg3_nvram_read_be32().
10683 */
10684 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10685
10686 val = tr32(GRC_EEPROM_ADDR);
10687 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10688
10689 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10690 EEPROM_ADDR_READ);
10691 tw32(GRC_EEPROM_ADDR, val |
10692 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10693 (addr & EEPROM_ADDR_ADDR_MASK) |
10694 EEPROM_ADDR_START |
10695 EEPROM_ADDR_WRITE);
6aa20a22 10696
9d57f01c 10697 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10698 val = tr32(GRC_EEPROM_ADDR);
10699
10700 if (val & EEPROM_ADDR_COMPLETE)
10701 break;
9d57f01c 10702 msleep(1);
1da177e4
LT		 10703 }
10704 if (!(val & EEPROM_ADDR_COMPLETE)) {
10705 rc = -EBUSY;
10706 break;
10707 }
10708 }
10709
10710 return rc;
10711}
10712
10713/* offset and length are dword aligned */
10714static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10715 u8 *buf)
10716{
10717 int ret = 0;
10718 u32 pagesize = tp->nvram_pagesize;
10719 u32 pagemask = pagesize - 1;
10720 u32 nvram_cmd;
10721 u8 *tmp;
10722
10723 tmp = kmalloc(pagesize, GFP_KERNEL);
10724 if (tmp == NULL)
10725 return -ENOMEM;
10726
10727 while (len) {
10728 int j;
e6af301b 10729 u32 phy_addr, page_off, size;
1da177e4
LT		 10730
10731 phy_addr = offset & ~pagemask;
6aa20a22 10732
1da177e4 10733 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10734 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10735 (__be32 *) (tmp + j));
10736 if (ret)
1da177e4
LT		 10737 break;
10738 }
10739 if (ret)
10740 break;
10741
10742 page_off = offset & pagemask;
10743 size = pagesize;
10744 if (len < size)
10745 size = len;
10746
10747 len -= size;
10748
10749 memcpy(tmp + page_off, buf, size);
10750
10751 offset = offset + (pagesize - page_off);
10752
e6af301b 10753 tg3_enable_nvram_access(tp);
1da177e4
LT		 10754
10755 /*
10756 * Before we can erase the flash page, we need
10757 * to issue a special "write enable" command.
10758 */
10759 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10760
10761 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10762 break;
10763
10764 /* Erase the target page */
10765 tw32(NVRAM_ADDR, phy_addr);
10766
10767 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10768 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10769
10770 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10771 break;
10772
10773 /* Issue another write enable to start the write. */
10774 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10775
10776 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10777 break;
10778
10779 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10780 __be32 data;
1da177e4 10781
b9fc7dc5 10782 data = *((__be32 *) (tmp + j));
a9dc529d 10783
b9fc7dc5 10784 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10785
10786 tw32(NVRAM_ADDR, phy_addr + j);
10787
10788 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10789 NVRAM_CMD_WR;
10790
10791 if (j == 0)
10792 nvram_cmd |= NVRAM_CMD_FIRST;
10793 else if (j == (pagesize - 4))
10794 nvram_cmd |= NVRAM_CMD_LAST;
10795
10796 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10797 break;
10798 }
10799 if (ret)
10800 break;
10801 }
10802
10803 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10804 tg3_nvram_exec_cmd(tp, nvram_cmd);
10805
10806 kfree(tmp);
10807
10808 return ret;
10809}
10810
10811/* offset and length are dword aligned */
10812static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10813 u8 *buf)
10814{
10815 int i, ret = 0;
10816
10817 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10818 u32 page_off, phy_addr, nvram_cmd;
10819 __be32 data;
1da177e4
LT		 10820
10821 memcpy(&data, buf + i, 4);
b9fc7dc5 10822 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10823
10824 page_off = offset % tp->nvram_pagesize;
10825
1820180b 10826 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10827
10828 tw32(NVRAM_ADDR, phy_addr);
10829
10830 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10831
10832 if ((page_off == 0) || (i == 0))
10833 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10834 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10835 nvram_cmd |= NVRAM_CMD_LAST;
10836
10837 if (i == (len - 4))
10838 nvram_cmd |= NVRAM_CMD_LAST;
10839
321d32a0
MC		 10840 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10841 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10842 (tp->nvram_jedecnum == JEDEC_ST) &&
10843 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10844
10845 if ((ret = tg3_nvram_exec_cmd(tp,
10846 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10847 NVRAM_CMD_DONE)))
10848
10849 break;
10850 }
10851 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10852 /* We always do complete word writes to eeprom. */
10853 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10854 }
10855
10856 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10857 break;
10858 }
10859 return ret;
10860}
10861
10862/* offset and length are dword aligned */
10863static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10864{
10865 int ret;
10866
1da177e4 10867 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10868 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10869 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10870 udelay(40);
10871 }
10872
10873 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10874 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10875 }
10876 else {
10877 u32 grc_mode;
10878
ec41c7df
MC		 10879 ret = tg3_nvram_lock(tp);
10880 if (ret)
10881 return ret;
1da177e4 10882
e6af301b
MC		 10883 tg3_enable_nvram_access(tp);
10884 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10885 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10886 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10887
10888 grc_mode = tr32(GRC_MODE);
10889 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10890
10891 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10892 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10893
10894 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10895 buf);
10896 }
10897 else {
10898 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10899 buf);
10900 }
10901
10902 grc_mode = tr32(GRC_MODE);
10903 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10904
e6af301b 10905 tg3_disable_nvram_access(tp);
1da177e4
LT		 10906 tg3_nvram_unlock(tp);
10907 }
10908
10909 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10910 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10911 udelay(40);
10912 }
10913
10914 return ret;
10915}
10916
10917struct subsys_tbl_ent {
10918 u16 subsys_vendor, subsys_devid;
10919 u32 phy_id;
10920};
10921
10922static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10923 /* Broadcom boards. */
10924 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10925 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10926 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10927 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10928 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10929 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10930 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10931 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10932 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10933 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10934 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10935
10936 /* 3com boards. */
10937 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10938 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10939 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10940 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10941 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10942
10943 /* DELL boards. */
10944 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10945 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10946 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10947 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10948
10949 /* Compaq boards. */
10950 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10951 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10952 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10953 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10954 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10955
10956 /* IBM boards. */
10957 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10958};
10959
10960static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10961{
10962 int i;
10963
10964 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10965 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10966 tp->pdev->subsystem_vendor) &&
10967 (subsys_id_to_phy_id[i].subsys_devid ==
10968 tp->pdev->subsystem_device))
10969 return &subsys_id_to_phy_id[i];
10970 }
10971 return NULL;
10972}
10973
7d0c41ef 10974static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10975{
1da177e4 10976 u32 val;
caf636c7
MC		 10977 u16 pmcsr;
10978
10979 /* On some early chips the SRAM cannot be accessed in D3hot state,
10980 * so need make sure we're in D0.
10981 */
10982 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10983 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10984 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10985 msleep(1);
7d0c41ef
MC		 10986
10987 /* Make sure register accesses (indirect or otherwise)
10988 * will function correctly.
10989 */
10990 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10991 tp->misc_host_ctrl);
1da177e4 10992
f49639e6
DM		 10993 /* The memory arbiter has to be enabled in order for SRAM accesses
10994 * to succeed. Normally on powerup the tg3 chip firmware will make
10995 * sure it is enabled, but other entities such as system netboot
10996 * code might disable it.
10997 */
10998 val = tr32(MEMARB_MODE);
10999 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11000
1da177e4 11001 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11002 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11003
a85feb8c
GZ		 11004 /* Assume an onboard device and WOL capable by default. */
11005 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11006
b5d3772c 11007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11008 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11009 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11010 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11011 }
0527ba35
MC		 11012 val = tr32(VCPU_CFGSHDW);
11013 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11014 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11015 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11016 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11017 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11018 goto done;
b5d3772c
MC		 11019 }
11020
1da177e4
LT		 11021 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11022 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11023 u32 nic_cfg, led_cfg;
a9daf367 11024 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11025 int eeprom_phy_serdes = 0;
1da177e4
LT		 11026
11027 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11028 tp->nic_sram_data_cfg = nic_cfg;
11029
11030 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11031 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11032 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11033 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11034 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11035 (ver > 0) && (ver < 0x100))
11036 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11037
a9daf367
MC		 11038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11039 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11040
1da177e4
LT		 11041 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11042 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11043 eeprom_phy_serdes = 1;
11044
11045 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11046 if (nic_phy_id != 0) {
11047 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11048 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11049
11050 eeprom_phy_id = (id1 >> 16) << 10;
11051 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11052 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11053 } else
11054 eeprom_phy_id = 0;
11055
7d0c41ef 11056 tp->phy_id = eeprom_phy_id;
747e8f8b 11057 if (eeprom_phy_serdes) {
a4e2b347 11058 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11059 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11060 else
11061 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11062 }
7d0c41ef 11063
cbf46853 11064 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11065 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11066 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11067 else
1da177e4
LT		 11068 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11069
11070 switch (led_cfg) {
11071 default:
11072 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11073 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11074 break;
11075
11076 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11077 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11078 break;
11079
11080 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11081 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11082
11083 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11084 * read on some older 5700/5701 bootcode.
11085 */
11086 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11087 ASIC_REV_5700 ||
11088 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11089 ASIC_REV_5701)
11090 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11091
1da177e4
LT		 11092 break;
11093
11094 case SHASTA_EXT_LED_SHARED:
11095 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11096 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11097 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11098 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11099 LED_CTRL_MODE_PHY_2);
11100 break;
11101
11102 case SHASTA_EXT_LED_MAC:
11103 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11104 break;
11105
11106 case SHASTA_EXT_LED_COMBO:
11107 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11108 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11109 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11110 LED_CTRL_MODE_PHY_2);
11111 break;
11112
855e1111 11113 }
1da177e4
LT		 11114
11115 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11116 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11117 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11118 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11119
b2a5c19c
MC		 11120 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11121 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11122
9d26e213 11123 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11124 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11125 if ((tp->pdev->subsystem_vendor ==
11126 PCI_VENDOR_ID_ARIMA) &&
11127 (tp->pdev->subsystem_device == 0x205a ||
11128 tp->pdev->subsystem_device == 0x2063))
11129 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11130 } else {
f49639e6 11131 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11132 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11133 }
1da177e4
LT		 11134
11135 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11136 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11137 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11138 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11139 }
b2b98d4a
MC		 11140
11141 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11142 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11143 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11144
a85feb8c
GZ		 11145 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11146 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11147 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11148
12dac075 11149 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11150 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11151 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11152
1da177e4
LT		 11153 if (cfg2 & (1 << 17))
11154 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11155
11156 /* serdes signal pre-emphasis in register 0x590 set by */
11157 /* bootcode if bit 18 is set */
11158 if (cfg2 & (1 << 18))
11159 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11160
321d32a0
MC		 11161 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11162 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11163 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11164 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11165
8ed5d97e
MC		 11166 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11167 u32 cfg3;
11168
11169 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11170 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11171 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11172 }
a9daf367
MC		 11173
11174 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11175 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11176 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11177 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11178 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11179 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11180 }
05ac4cb7
MC		 11181done:
11182 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11183 device_set_wakeup_enable(&tp->pdev->dev,
11184 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11185}
11186
b2a5c19c
MC		 11187static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11188{
11189 int i;
11190 u32 val;
11191
11192 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11193 tw32(OTP_CTRL, cmd);
11194
11195 /* Wait for up to 1 ms for command to execute. */
11196 for (i = 0; i < 100; i++) {
11197 val = tr32(OTP_STATUS);
11198 if (val & OTP_STATUS_CMD_DONE)
11199 break;
11200 udelay(10);
11201 }
11202
11203 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11204}
11205
11206/* Read the gphy configuration from the OTP region of the chip. The gphy
11207 * configuration is a 32-bit value that straddles the alignment boundary.
11208 * We do two 32-bit reads and then shift and merge the results.
11209 */
11210static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11211{
11212 u32 bhalf_otp, thalf_otp;
11213
11214 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11215
11216 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11217 return 0;
11218
11219 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11220
11221 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11222 return 0;
11223
11224 thalf_otp = tr32(OTP_READ_DATA);
11225
11226 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11227
11228 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11229 return 0;
11230
11231 bhalf_otp = tr32(OTP_READ_DATA);
11232
11233 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11234}
11235
7d0c41ef
MC		 11236static int __devinit tg3_phy_probe(struct tg3 *tp)
11237{
11238 u32 hw_phy_id_1, hw_phy_id_2;
11239 u32 hw_phy_id, hw_phy_id_masked;
11240 int err;
1da177e4 11241
b02fd9e3
MC		 11242 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11243 return tg3_phy_init(tp);
11244
1da177e4 11245 /* Reading the PHY ID register can conflict with ASF
877d0310 11246 * firmware access to the PHY hardware.
1da177e4
LT		 11247 */
11248 err = 0;
0d3031d9
MC		 11249 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11250 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11251 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11252 } else {
11253 /* Now read the physical PHY_ID from the chip and verify
11254 * that it is sane. If it doesn't look good, we fall back
11255 * to either the hard-coded table based PHY_ID and failing
11256 * that the value found in the eeprom area.
11257 */
11258 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11259 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11260
11261 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11262 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11263 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11264
11265 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11266 }
11267
11268 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11269 tp->phy_id = hw_phy_id;
11270 if (hw_phy_id_masked == PHY_ID_BCM8002)
11271 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11272 else
11273 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11274 } else {
7d0c41ef
MC		 11275 if (tp->phy_id != PHY_ID_INVALID) {
11276 /* Do nothing, phy ID already set up in
11277 * tg3_get_eeprom_hw_cfg().
11278 */
1da177e4
LT		 11279 } else {
11280 struct subsys_tbl_ent *p;
11281
11282 /* No eeprom signature? Try the hardcoded
11283 * subsys device table.
11284 */
11285 p = lookup_by_subsys(tp);
11286 if (!p)
11287 return -ENODEV;
11288
11289 tp->phy_id = p->phy_id;
11290 if (!tp->phy_id ||
11291 tp->phy_id == PHY_ID_BCM8002)
11292 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11293 }
11294 }
11295
747e8f8b 11296 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11297 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11298 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11299 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11300
11301 tg3_readphy(tp, MII_BMSR, &bmsr);
11302 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11303 (bmsr & BMSR_LSTATUS))
11304 goto skip_phy_reset;
6aa20a22 11305
1da177e4
LT		 11306 err = tg3_phy_reset(tp);
11307 if (err)
11308 return err;
11309
11310 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11311 ADVERTISE_100HALF | ADVERTISE_100FULL |
11312 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11313 tg3_ctrl = 0;
11314 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11315 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11316 MII_TG3_CTRL_ADV_1000_FULL);
11317 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11318 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11319 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11320 MII_TG3_CTRL_ENABLE_AS_MASTER);
11321 }
11322
3600d918
MC		 11323 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11324 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11325 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11326 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11327 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11328
11329 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11330 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11331
11332 tg3_writephy(tp, MII_BMCR,
11333 BMCR_ANENABLE | BMCR_ANRESTART);
11334 }
11335 tg3_phy_set_wirespeed(tp);
11336
11337 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11338 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11339 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11340 }
11341
11342skip_phy_reset:
11343 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11344 err = tg3_init_5401phy_dsp(tp);
11345 if (err)
11346 return err;
11347 }
11348
11349 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11350 err = tg3_init_5401phy_dsp(tp);
11351 }
11352
747e8f8b 11353 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11354 tp->link_config.advertising =
11355 (ADVERTISED_1000baseT_Half |
11356 ADVERTISED_1000baseT_Full |
11357 ADVERTISED_Autoneg |
11358 ADVERTISED_FIBRE);
11359 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11360 tp->link_config.advertising &=
11361 ~(ADVERTISED_1000baseT_Half |
11362 ADVERTISED_1000baseT_Full);
11363
11364 return err;
11365}
11366
11367static void __devinit tg3_read_partno(struct tg3 *tp)
11368{
6d348f2c 11369 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11370 unsigned int i;
1b27777a 11371 u32 magic;
1da177e4 11372
e4f34110 11373 if (tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11374 goto out_not_found;
1da177e4 11375
1820180b 11376 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11377 for (i = 0; i < 256; i += 4) {
11378 u32 tmp;
1da177e4 11379
6d348f2c
MC		 11380 /* The data is in little-endian format in NVRAM.
11381 * Use the big-endian read routines to preserve
11382 * the byte order as it exists in NVRAM.
11383 */
11384 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11385 goto out_not_found;
11386
6d348f2c 11387 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11388 }
11389 } else {
11390 int vpd_cap;
11391
11392 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11393 for (i = 0; i < 256; i += 4) {
11394 u32 tmp, j = 0;
b9fc7dc5 11395 __le32 v;
1b27777a
MC		 11396 u16 tmp16;
11397
11398 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11399 i);
11400 while (j++ < 100) {
11401 pci_read_config_word(tp->pdev, vpd_cap +
11402 PCI_VPD_ADDR, &tmp16);
11403 if (tmp16 & 0x8000)
11404 break;
11405 msleep(1);
11406 }
f49639e6
DM		 11407 if (!(tmp16 & 0x8000))
11408 goto out_not_found;
11409
1b27777a
MC		 11410 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11411 &tmp);
b9fc7dc5 11412 v = cpu_to_le32(tmp);
6d348f2c 11413 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11414 }
1da177e4
LT		 11415 }
11416
11417 /* Now parse and find the part number. */
af2c6a4a 11418 for (i = 0; i < 254; ) {
1da177e4 11419 unsigned char val = vpd_data[i];
af2c6a4a 11420 unsigned int block_end;
1da177e4
LT		 11421
11422 if (val == 0x82 || val == 0x91) {
11423 i = (i + 3 +
11424 (vpd_data[i + 1] +
11425 (vpd_data[i + 2] << 8)));
11426 continue;
11427 }
11428
11429 if (val != 0x90)
11430 goto out_not_found;
11431
11432 block_end = (i + 3 +
11433 (vpd_data[i + 1] +
11434 (vpd_data[i + 2] << 8)));
11435 i += 3;
af2c6a4a
MC		 11436
11437 if (block_end > 256)
11438 goto out_not_found;
11439
11440 while (i < (block_end - 2)) {
1da177e4
LT		 11441 if (vpd_data[i + 0] == 'P' &&
11442 vpd_data[i + 1] == 'N') {
11443 int partno_len = vpd_data[i + 2];
11444
af2c6a4a
MC		 11445 i += 3;
11446 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11447 goto out_not_found;
11448
11449 memcpy(tp->board_part_number,
af2c6a4a 11450 &vpd_data[i], partno_len);
1da177e4
LT		 11451
11452 /* Success. */
11453 return;
11454 }
af2c6a4a 11455 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11456 }
11457
11458 /* Part number not found. */
11459 goto out_not_found;
11460 }
11461
11462out_not_found:
b5d3772c
MC		 11463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11464 strcpy(tp->board_part_number, "BCM95906");
11465 else
11466 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11467}
11468
9c8a620e
MC		 11469static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11470{
11471 u32 val;
11472
e4f34110 11473 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11474 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11475 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11476 val != 0)
11477 return 0;
11478
11479 return 1;
11480}
11481
acd9c119
MC		 11482static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11483{
ff3a7cb2 11484 u32 val, offset, start, ver_offset;
acd9c119 11485 int i;
ff3a7cb2 11486 bool newver = false;
acd9c119
MC		 11487
11488 if (tg3_nvram_read(tp, 0xc, &offset) ||
11489 tg3_nvram_read(tp, 0x4, &start))
11490 return;
11491
11492 offset = tg3_nvram_logical_addr(tp, offset);
11493
ff3a7cb2 11494 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11495 return;
11496
ff3a7cb2
MC		 11497 if ((val & 0xfc000000) == 0x0c000000) {
11498 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11499 return;
11500
ff3a7cb2
MC		 11501 if (val == 0)
11502 newver = true;
11503 }
11504
11505 if (newver) {
11506 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11507 return;
11508
11509 offset = offset + ver_offset - start;
11510 for (i = 0; i < 16; i += 4) {
11511 __be32 v;
11512 if (tg3_nvram_read_be32(tp, offset + i, &v))
11513 return;
11514
11515 memcpy(tp->fw_ver + i, &v, sizeof(v));
11516 }
11517 } else {
11518 u32 major, minor;
11519
11520 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11521 return;
11522
11523 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11524 TG3_NVM_BCVER_MAJSFT;
11525 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11526 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11527 }
11528}
11529
a6f6cb1c
MC		 11530static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11531{
11532 u32 val, major, minor;
11533
11534 /* Use native endian representation */
11535 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11536 return;
11537
11538 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11539 TG3_NVM_HWSB_CFG1_MAJSFT;
11540 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11541 TG3_NVM_HWSB_CFG1_MINSFT;
11542
11543 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11544}
11545
dfe00d7d
MC		 11546static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11547{
11548 u32 offset, major, minor, build;
11549
11550 tp->fw_ver[0] = 's';
11551 tp->fw_ver[1] = 'b';
11552 tp->fw_ver[2] = '\0';
11553
11554 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11555 return;
11556
11557 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11558 case TG3_EEPROM_SB_REVISION_0:
11559 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11560 break;
11561 case TG3_EEPROM_SB_REVISION_2:
11562 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11563 break;
11564 case TG3_EEPROM_SB_REVISION_3:
11565 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11566 break;
11567 default:
11568 return;
11569 }
11570
e4f34110 11571 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11572 return;
11573
11574 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11575 TG3_EEPROM_SB_EDH_BLD_SHFT;
11576 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11577 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11578 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11579
11580 if (minor > 99 || build > 26)
11581 return;
11582
11583 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11584
11585 if (build > 0) {
11586 tp->fw_ver[8] = 'a' + build - 1;
11587 tp->fw_ver[9] = '\0';
11588 }
11589}
11590
acd9c119 11591static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11592{
11593 u32 val, offset, start;
acd9c119 11594 int i, vlen;
9c8a620e
MC		 11595
11596 for (offset = TG3_NVM_DIR_START;
11597 offset < TG3_NVM_DIR_END;
11598 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11599 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11600 return;
11601
9c8a620e
MC		 11602 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11603 break;
11604 }
11605
11606 if (offset == TG3_NVM_DIR_END)
11607 return;
11608
11609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11610 start = 0x08000000;
e4f34110 11611 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11612 return;
11613
e4f34110 11614 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11615 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11616 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11617 return;
11618
11619 offset += val - start;
11620
acd9c119 11621 vlen = strlen(tp->fw_ver);
9c8a620e 11622
acd9c119
MC		 11623 tp->fw_ver[vlen++] = ',';
11624 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11625
11626 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11627 __be32 v;
11628 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11629 return;
11630
b9fc7dc5 11631 offset += sizeof(v);
c4e6575c 11632
acd9c119
MC		 11633 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11634 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11635 break;
c4e6575c 11636 }
9c8a620e 11637
acd9c119
MC		 11638 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11639 vlen += sizeof(v);
c4e6575c 11640 }
acd9c119
MC		 11641}
11642
7fd76445
MC		 11643static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11644{
11645 int vlen;
11646 u32 apedata;
11647
11648 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11649 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11650 return;
11651
11652 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11653 if (apedata != APE_SEG_SIG_MAGIC)
11654 return;
11655
11656 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11657 if (!(apedata & APE_FW_STATUS_READY))
11658 return;
11659
11660 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11661
11662 vlen = strlen(tp->fw_ver);
11663
11664 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11665 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11666 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11667 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11668 (apedata & APE_FW_VERSION_BLDMSK));
11669}
11670
acd9c119
MC		 11671static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11672{
11673 u32 val;
11674
11675 if (tg3_nvram_read(tp, 0, &val))
11676 return;
11677
11678 if (val == TG3_EEPROM_MAGIC)
11679 tg3_read_bc_ver(tp);
11680 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11681 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11682 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11683 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11684 else
11685 return;
11686
11687 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11688 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11689 return;
11690
11691 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11692
11693 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11694}
11695
7544b097
MC		 11696static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11697
1da177e4
LT		 11698static int __devinit tg3_get_invariants(struct tg3 *tp)
11699{
11700 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11701 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11702 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11703 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11704 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11705 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11706 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11707 { },
11708 };
11709 u32 misc_ctrl_reg;
1da177e4
LT		 11710 u32 pci_state_reg, grc_misc_cfg;
11711 u32 val;
11712 u16 pci_cmd;
5e7dfd0f 11713 int err;
1da177e4 11714
1da177e4
LT		 11715 /* Force memory write invalidate off. If we leave it on,
11716 * then on 5700_BX chips we have to enable a workaround.
11717 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11718 * to match the cacheline size. The Broadcom driver have this
11719 * workaround but turns MWI off all the times so never uses
11720 * it. This seems to suggest that the workaround is insufficient.
11721 */
11722 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11723 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11724 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11725
11726 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11727 * has the register indirect write enable bit set before
11728 * we try to access any of the MMIO registers. It is also
11729 * critical that the PCI-X hw workaround situation is decided
11730 * before that as well.
11731 */
11732 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11733 &misc_ctrl_reg);
11734
11735 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11736 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11737 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11738 u32 prod_id_asic_rev;
11739
11740 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11741 &prod_id_asic_rev);
321d32a0 11742 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11743 }
1da177e4 11744
ff645bec
MC		 11745 /* Wrong chip ID in 5752 A0. This code can be removed later
11746 * as A0 is not in production.
11747 */
11748 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11749 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11750
6892914f
MC		 11751 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11752 * we need to disable memory and use config. cycles
11753 * only to access all registers. The 5702/03 chips
11754 * can mistakenly decode the special cycles from the
11755 * ICH chipsets as memory write cycles, causing corruption
11756 * of register and memory space. Only certain ICH bridges
11757 * will drive special cycles with non-zero data during the
11758 * address phase which can fall within the 5703's address
11759 * range. This is not an ICH bug as the PCI spec allows
11760 * non-zero address during special cycles. However, only
11761 * these ICH bridges are known to drive non-zero addresses
11762 * during special cycles.
11763 *
11764 * Since special cycles do not cross PCI bridges, we only
11765 * enable this workaround if the 5703 is on the secondary
11766 * bus of these ICH bridges.
11767 */
11768 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11769 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11770 static struct tg3_dev_id {
11771 u32 vendor;
11772 u32 device;
11773 u32 rev;
11774 } ich_chipsets[] = {
11775 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11776 PCI_ANY_ID },
11777 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11778 PCI_ANY_ID },
11779 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11780 0xa },
11781 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11782 PCI_ANY_ID },
11783 { },
11784 };
11785 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11786 struct pci_dev *bridge = NULL;
11787
11788 while (pci_id->vendor != 0) {
11789 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11790 bridge);
11791 if (!bridge) {
11792 pci_id++;
11793 continue;
11794 }
11795 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11796 if (bridge->revision > pci_id->rev)
6892914f
MC		 11797 continue;
11798 }
11799 if (bridge->subordinate &&
11800 (bridge->subordinate->number ==
11801 tp->pdev->bus->number)) {
11802
11803 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11804 pci_dev_put(bridge);
11805 break;
11806 }
11807 }
11808 }
11809
41588ba1
MC		 11810 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11811 static struct tg3_dev_id {
11812 u32 vendor;
11813 u32 device;
11814 } bridge_chipsets[] = {
11815 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11816 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11817 { },
11818 };
11819 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11820 struct pci_dev *bridge = NULL;
11821
11822 while (pci_id->vendor != 0) {
11823 bridge = pci_get_device(pci_id->vendor,
11824 pci_id->device,
11825 bridge);
11826 if (!bridge) {
11827 pci_id++;
11828 continue;
11829 }
11830 if (bridge->subordinate &&
11831 (bridge->subordinate->number <=
11832 tp->pdev->bus->number) &&
11833 (bridge->subordinate->subordinate >=
11834 tp->pdev->bus->number)) {
11835 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11836 pci_dev_put(bridge);
11837 break;
11838 }
11839 }
11840 }
11841
4a29cc2e
MC		 11842 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11843 * DMA addresses > 40-bit. This bridge may have other additional
11844 * 57xx devices behind it in some 4-port NIC designs for example.
11845 * Any tg3 device found behind the bridge will also need the 40-bit
11846 * DMA workaround.
11847 */
a4e2b347
MC		 11848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11850 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11851 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11852 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11853 }
4a29cc2e
MC		 11854 else {
11855 struct pci_dev *bridge = NULL;
11856
11857 do {
11858 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11859 PCI_DEVICE_ID_SERVERWORKS_EPB,
11860 bridge);
11861 if (bridge && bridge->subordinate &&
11862 (bridge->subordinate->number <=
11863 tp->pdev->bus->number) &&
11864 (bridge->subordinate->subordinate >=
11865 tp->pdev->bus->number)) {
11866 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11867 pci_dev_put(bridge);
11868 break;
11869 }
11870 } while (bridge);
11871 }
4cf78e4f 11872
1da177e4
LT		 11873 /* Initialize misc host control in PCI block. */
11874 tp->misc_host_ctrl |= (misc_ctrl_reg &
11875 MISC_HOST_CTRL_CHIPREV);
11876 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11877 tp->misc_host_ctrl);
11878
7544b097
MC		 11879 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11880 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11881 tp->pdev_peer = tg3_find_peer(tp);
11882
321d32a0
MC		 11883 /* Intentionally exclude ASIC_REV_5906 */
11884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 11888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 11889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11890 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11891
11892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 11894 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 11895 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 11896 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11897 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11898
1b440c56
JL		 11899 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11900 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11901 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11902
027455ad
MC		 11903 /* 5700 B0 chips do not support checksumming correctly due
11904 * to hardware bugs.
11905 */
11906 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11907 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11908 else {
11909 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11910 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11911 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11912 tp->dev->features |= NETIF_F_IPV6_CSUM;
11913 }
11914
5a6f3074 11915 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11916 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11917 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11918 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11919 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11920 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11921 tp->pdev_peer == tp->pdev))
11922 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11923
321d32a0 11924 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 11925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11926 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11927 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11928 } else {
7f62ad5d 11929 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11930 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11931 ASIC_REV_5750 &&
11932 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11933 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11934 }
5a6f3074 11935 }
1da177e4 11936
f51f3562
MC		 11937 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11938 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6
MC		 11939 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11940
52f4490c
MC		 11941 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11942 &pci_state_reg);
11943
5e7dfd0f
MC		 11944 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11945 if (tp->pcie_cap != 0) {
11946 u16 lnkctl;
11947
1da177e4 11948 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 11949
11950 pcie_set_readrq(tp->pdev, 4096);
11951
5e7dfd0f
MC		 11952 pci_read_config_word(tp->pdev,
11953 tp->pcie_cap + PCI_EXP_LNKCTL,
11954 &lnkctl);
11955 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11956 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 11957 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 11958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 11959 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11960 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
5e7dfd0f 11961 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 11962 }
52f4490c 11963 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 11964 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 11965 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11966 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11967 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11968 if (!tp->pcix_cap) {
11969 printk(KERN_ERR PFX "Cannot find PCI-X "
11970 "capability, aborting.\n");
11971 return -EIO;
11972 }
11973
11974 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
11975 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11976 }
1da177e4 11977
399de50b
MC		 11978 /* If we have an AMD 762 or VIA K8T800 chipset, write
11979 * reordering to the mailbox registers done by the host
11980 * controller can cause major troubles. We read back from
11981 * every mailbox register write to force the writes to be
11982 * posted to the chip in order.
11983 */
11984 if (pci_dev_present(write_reorder_chipsets) &&
11985 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11986 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11987
69fc4053
MC		 11988 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
11989 &tp->pci_cacheline_sz);
11990 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11991 &tp->pci_lat_timer);
1da177e4
LT		 11992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11993 tp->pci_lat_timer < 64) {
11994 tp->pci_lat_timer = 64;
69fc4053
MC		 11995 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11996 tp->pci_lat_timer);
1da177e4
LT		 11997 }
11998
52f4490c
MC		 11999 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12000 /* 5700 BX chips need to have their TX producer index
12001 * mailboxes written twice to workaround a bug.
12002 */
12003 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12004
52f4490c 12005 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12006 *
12007 * The workaround is to use indirect register accesses
12008 * for all chip writes not to mailbox registers.
12009 */
52f4490c 12010 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12011 u32 pm_reg;
1da177e4
LT		 12012
12013 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12014
12015 /* The chip can have it's power management PCI config
12016 * space registers clobbered due to this bug.
12017 * So explicitly force the chip into D0 here.
12018 */
9974a356
MC		 12019 pci_read_config_dword(tp->pdev,
12020 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12021 &pm_reg);
12022 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12023 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12024 pci_write_config_dword(tp->pdev,
12025 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12026 pm_reg);
12027
12028 /* Also, force SERR#/PERR# in PCI command. */
12029 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12030 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12031 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12032 }
12033 }
12034
1da177e4
LT		 12035 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12036 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12037 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12038 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12039
12040 /* Chip-specific fixup from Broadcom driver */
12041 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12042 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12043 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12044 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12045 }
12046
1ee582d8 12047 /* Default fast path register access methods */
20094930 12048 tp->read32 = tg3_read32;
1ee582d8 12049 tp->write32 = tg3_write32;
09ee929c 12050 tp->read32_mbox = tg3_read32;
20094930 12051 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12052 tp->write32_tx_mbox = tg3_write32;
12053 tp->write32_rx_mbox = tg3_write32;
12054
12055 /* Various workaround register access methods */
12056 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12057 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12058 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12059 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12060 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12061 /*
12062 * Back to back register writes can cause problems on these
12063 * chips, the workaround is to read back all reg writes
12064 * except those to mailbox regs.
12065 *
12066 * See tg3_write_indirect_reg32().
12067 */
1ee582d8 12068 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12069 }
12070
1ee582d8
MC		 12071
12072 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12073 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12074 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12075 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12076 tp->write32_rx_mbox = tg3_write_flush_reg32;
12077 }
20094930 12078
6892914f
MC		 12079 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12080 tp->read32 = tg3_read_indirect_reg32;
12081 tp->write32 = tg3_write_indirect_reg32;
12082 tp->read32_mbox = tg3_read_indirect_mbox;
12083 tp->write32_mbox = tg3_write_indirect_mbox;
12084 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12085 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12086
12087 iounmap(tp->regs);
22abe310 12088 tp->regs = NULL;
6892914f
MC		 12089
12090 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12091 pci_cmd &= ~PCI_COMMAND_MEMORY;
12092 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12093 }
b5d3772c
MC		 12094 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12095 tp->read32_mbox = tg3_read32_mbox_5906;
12096 tp->write32_mbox = tg3_write32_mbox_5906;
12097 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12098 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12099 }
6892914f 12100
bbadf503
MC		 12101 if (tp->write32 == tg3_write_indirect_reg32 ||
12102 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12103 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12105 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12106
7d0c41ef 12107 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12108 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12109 * determined before calling tg3_set_power_state() so that
12110 * we know whether or not to switch out of Vaux power.
12111 * When the flag is set, it means that GPIO1 is used for eeprom
12112 * write protect and also implies that it is a LOM where GPIOs
12113 * are not used to switch power.
6aa20a22 12114 */
7d0c41ef
MC		 12115 tg3_get_eeprom_hw_cfg(tp);
12116
0d3031d9
MC		 12117 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12118 /* Allow reads and writes to the
12119 * APE register and memory space.
12120 */
12121 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12122 PCISTATE_ALLOW_APE_SHMEM_WR;
12123 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12124 pci_state_reg);
12125 }
12126
9936bcf6 12127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12129 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12131 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12132
314fba34
MC		 12133 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12134 * GPIO1 driven high will bring 5700's external PHY out of reset.
12135 * It is also used as eeprom write protect on LOMs.
12136 */
12137 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12138 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12139 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12140 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12141 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12142 /* Unused GPIO3 must be driven as output on 5752 because there
12143 * are no pull-up resistors on unused GPIO pins.
12144 */
12145 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12146 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12147
321d32a0
MC		 12148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12150 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12151
5f0c4a3c
MC		 12152 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12153 /* Turn off the debug UART. */
12154 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12155 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12156 /* Keep VMain power. */
12157 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12158 GRC_LCLCTRL_GPIO_OUTPUT0;
12159 }
12160
1da177e4 12161 /* Force the chip into D0. */
bc1c7567 12162 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12163 if (err) {
12164 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12165 pci_name(tp->pdev));
12166 return err;
12167 }
12168
1da177e4
LT		 12169 /* Derive initial jumbo mode from MTU assigned in
12170 * ether_setup() via the alloc_etherdev() call
12171 */
0f893dc6 12172 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12173 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12174 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12175
12176 /* Determine WakeOnLan speed to use. */
12177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12178 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12179 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12180 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12181 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12182 } else {
12183 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12184 }
12185
12186 /* A few boards don't want Ethernet@WireSpeed phy feature */
12187 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12188 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12189 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12190 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 12191 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 12192 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12193 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12194
12195 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12196 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12197 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12198 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12199 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12200
321d32a0
MC		 12201 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12202 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12203 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12204 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12205 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12206 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12208 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12209 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12210 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12211 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12212 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12213 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12214 } else
c424cb24
MC		 12215 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12216 }
1da177e4 12217
b2a5c19c
MC		 12218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12219 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12220 tp->phy_otp = tg3_read_otp_phycfg(tp);
12221 if (tp->phy_otp == 0)
12222 tp->phy_otp = TG3_OTP_DEFAULT;
12223 }
12224
f51f3562 12225 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12226 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12227 else
12228 tp->mi_mode = MAC_MI_MODE_BASE;
12229
1da177e4 12230 tp->coalesce_mode = 0;
1da177e4
LT		 12231 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12232 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12233 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12234
321d32a0
MC		 12235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12236 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12237 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12238
158d7abd
MC		 12239 err = tg3_mdio_init(tp);
12240 if (err)
12241 return err;
1da177e4
LT		 12242
12243 /* Initialize data/descriptor byte/word swapping. */
12244 val = tr32(GRC_MODE);
12245 val &= GRC_MODE_HOST_STACKUP;
12246 tw32(GRC_MODE, val | tp->grc_mode);
12247
12248 tg3_switch_clocks(tp);
12249
12250 /* Clear this out for sanity. */
12251 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12252
12253 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12254 &pci_state_reg);
12255 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12256 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12257 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12258
12259 if (chiprevid == CHIPREV_ID_5701_A0 ||
12260 chiprevid == CHIPREV_ID_5701_B0 ||
12261 chiprevid == CHIPREV_ID_5701_B2 ||
12262 chiprevid == CHIPREV_ID_5701_B5) {
12263 void __iomem *sram_base;
12264
12265 /* Write some dummy words into the SRAM status block
12266 * area, see if it reads back correctly. If the return
12267 * value is bad, force enable the PCIX workaround.
12268 */
12269 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12270
12271 writel(0x00000000, sram_base);
12272 writel(0x00000000, sram_base + 4);
12273 writel(0xffffffff, sram_base + 4);
12274 if (readl(sram_base) != 0x00000000)
12275 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12276 }
12277 }
12278
12279 udelay(50);
12280 tg3_nvram_init(tp);
12281
12282 grc_misc_cfg = tr32(GRC_MISC_CFG);
12283 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12284
1da177e4
LT		 12285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12286 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12287 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12288 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12289
fac9b83e
DM		 12290 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12291 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12292 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12293 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12294 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12295 HOSTCC_MODE_CLRTICK_TXBD);
12296
12297 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12298 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12299 tp->misc_host_ctrl);
12300 }
12301
3bda1258
MC		 12302 /* Preserve the APE MAC_MODE bits */
12303 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12304 tp->mac_mode = tr32(MAC_MODE) |
12305 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12306 else
12307 tp->mac_mode = TG3_DEF_MAC_MODE;
12308
1da177e4
LT		 12309 /* these are limited to 10/100 only */
12310 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12311 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12312 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12313 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12314 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12315 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12316 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12317 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12318 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12319 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12320 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12321 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
b5d3772c 12322 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 12323 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12324
12325 err = tg3_phy_probe(tp);
12326 if (err) {
12327 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12328 pci_name(tp->pdev), err);
12329 /* ... but do not return immediately ... */
b02fd9e3 12330 tg3_mdio_fini(tp);
1da177e4
LT		 12331 }
12332
12333 tg3_read_partno(tp);
c4e6575c 12334 tg3_read_fw_ver(tp);
1da177e4
LT		 12335
12336 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12337 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12338 } else {
12339 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12340 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12341 else
12342 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12343 }
12344
12345 /* 5700 {AX,BX} chips have a broken status block link
12346 * change bit implementation, so we must use the
12347 * status register in those cases.
12348 */
12349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12350 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12351 else
12352 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12353
12354 /* The led_ctrl is set during tg3_phy_probe, here we might
12355 * have to force the link status polling mechanism based
12356 * upon subsystem IDs.
12357 */
12358 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12359 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12360 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12361 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12362 TG3_FLAG_USE_LINKCHG_REG);
12363 }
12364
12365 /* For all SERDES we poll the MAC status register. */
12366 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12367 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12368 else
12369 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12370
ad829268 12371 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12373 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12374 tp->rx_offset = 0;
12375
f92905de
MC		 12376 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12377
12378 /* Increment the rx prod index on the rx std ring by at most
12379 * 8 for these chips to workaround hw errata.
12380 */
12381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12382 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12383 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12384 tp->rx_std_max_post = 8;
12385
8ed5d97e
MC		 12386 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12387 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12388 PCIE_PWR_MGMT_L1_THRESH_MSK;
12389
1da177e4
LT		 12390 return err;
12391}
12392
49b6e95f 12393#ifdef CONFIG_SPARC
1da177e4
LT		 12394static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12395{
12396 struct net_device *dev = tp->dev;
12397 struct pci_dev *pdev = tp->pdev;
49b6e95f 12398 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12399 const unsigned char *addr;
49b6e95f
DM		 12400 int len;
12401
12402 addr = of_get_property(dp, "local-mac-address", &len);
12403 if (addr && len == 6) {
12404 memcpy(dev->dev_addr, addr, 6);
12405 memcpy(dev->perm_addr, dev->dev_addr, 6);
12406 return 0;
1da177e4
LT		 12407 }
12408 return -ENODEV;
12409}
12410
12411static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12412{
12413 struct net_device *dev = tp->dev;
12414
12415 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12416 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12417 return 0;
12418}
12419#endif
12420
12421static int __devinit tg3_get_device_address(struct tg3 *tp)
12422{
12423 struct net_device *dev = tp->dev;
12424 u32 hi, lo, mac_offset;
008652b3 12425 int addr_ok = 0;
1da177e4 12426
49b6e95f 12427#ifdef CONFIG_SPARC
1da177e4
LT		 12428 if (!tg3_get_macaddr_sparc(tp))
12429 return 0;
12430#endif
12431
12432 mac_offset = 0x7c;
f49639e6 12433 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12434 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12435 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12436 mac_offset = 0xcc;
12437 if (tg3_nvram_lock(tp))
12438 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12439 else
12440 tg3_nvram_unlock(tp);
12441 }
b5d3772c
MC		 12442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12443 mac_offset = 0x10;
1da177e4
LT		 12444
12445 /* First try to get it from MAC address mailbox. */
12446 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12447 if ((hi >> 16) == 0x484b) {
12448 dev->dev_addr[0] = (hi >> 8) & 0xff;
12449 dev->dev_addr[1] = (hi >> 0) & 0xff;
12450
12451 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12452 dev->dev_addr[2] = (lo >> 24) & 0xff;
12453 dev->dev_addr[3] = (lo >> 16) & 0xff;
12454 dev->dev_addr[4] = (lo >> 8) & 0xff;
12455 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12456
008652b3
MC		 12457 /* Some old bootcode may report a 0 MAC address in SRAM */
12458 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12459 }
12460 if (!addr_ok) {
12461 /* Next, try NVRAM. */
6d348f2c
MC		 12462 if (!tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12463 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12464 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12465 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12466 }
12467 /* Finally just fetch it out of the MAC control regs. */
12468 else {
12469 hi = tr32(MAC_ADDR_0_HIGH);
12470 lo = tr32(MAC_ADDR_0_LOW);
12471
12472 dev->dev_addr[5] = lo & 0xff;
12473 dev->dev_addr[4] = (lo >> 8) & 0xff;
12474 dev->dev_addr[3] = (lo >> 16) & 0xff;
12475 dev->dev_addr[2] = (lo >> 24) & 0xff;
12476 dev->dev_addr[1] = hi & 0xff;
12477 dev->dev_addr[0] = (hi >> 8) & 0xff;
12478 }
1da177e4
LT		 12479 }
12480
12481 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12482#ifdef CONFIG_SPARC
1da177e4
LT		 12483 if (!tg3_get_default_macaddr_sparc(tp))
12484 return 0;
12485#endif
12486 return -EINVAL;
12487 }
2ff43697 12488 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12489 return 0;
12490}
12491
59e6b434
DM		 12492#define BOUNDARY_SINGLE_CACHELINE 1
12493#define BOUNDARY_MULTI_CACHELINE 2
12494
12495static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12496{
12497 int cacheline_size;
12498 u8 byte;
12499 int goal;
12500
12501 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12502 if (byte == 0)
12503 cacheline_size = 1024;
12504 else
12505 cacheline_size = (int) byte * 4;
12506
12507 /* On 5703 and later chips, the boundary bits have no
12508 * effect.
12509 */
12510 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12511 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12512 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12513 goto out;
12514
12515#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12516 goal = BOUNDARY_MULTI_CACHELINE;
12517#else
12518#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12519 goal = BOUNDARY_SINGLE_CACHELINE;
12520#else
12521 goal = 0;
12522#endif
12523#endif
12524
12525 if (!goal)
12526 goto out;
12527
12528 /* PCI controllers on most RISC systems tend to disconnect
12529 * when a device tries to burst across a cache-line boundary.
12530 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12531 *
12532 * Unfortunately, for PCI-E there are only limited
12533 * write-side controls for this, and thus for reads
12534 * we will still get the disconnects. We'll also waste
12535 * these PCI cycles for both read and write for chips
12536 * other than 5700 and 5701 which do not implement the
12537 * boundary bits.
12538 */
12539 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12540 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12541 switch (cacheline_size) {
12542 case 16:
12543 case 32:
12544 case 64:
12545 case 128:
12546 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12547 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12548 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12549 } else {
12550 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12551 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12552 }
12553 break;
12554
12555 case 256:
12556 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12557 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12558 break;
12559
12560 default:
12561 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12562 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12563 break;
855e1111 12564 }
59e6b434
DM		 12565 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12566 switch (cacheline_size) {
12567 case 16:
12568 case 32:
12569 case 64:
12570 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12571 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12572 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12573 break;
12574 }
12575 /* fallthrough */
12576 case 128:
12577 default:
12578 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12579 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12580 break;
855e1111 12581 }
59e6b434
DM		 12582 } else {
12583 switch (cacheline_size) {
12584 case 16:
12585 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12586 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12587 DMA_RWCTRL_WRITE_BNDRY_16);
12588 break;
12589 }
12590 /* fallthrough */
12591 case 32:
12592 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12593 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12594 DMA_RWCTRL_WRITE_BNDRY_32);
12595 break;
12596 }
12597 /* fallthrough */
12598 case 64:
12599 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12600 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12601 DMA_RWCTRL_WRITE_BNDRY_64);
12602 break;
12603 }
12604 /* fallthrough */
12605 case 128:
12606 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12607 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12608 DMA_RWCTRL_WRITE_BNDRY_128);
12609 break;
12610 }
12611 /* fallthrough */
12612 case 256:
12613 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12614 DMA_RWCTRL_WRITE_BNDRY_256);
12615 break;
12616 case 512:
12617 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12618 DMA_RWCTRL_WRITE_BNDRY_512);
12619 break;
12620 case 1024:
12621 default:
12622 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12623 DMA_RWCTRL_WRITE_BNDRY_1024);
12624 break;
855e1111 12625 }
59e6b434
DM		 12626 }
12627
12628out:
12629 return val;
12630}
12631
1da177e4
LT		 12632static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12633{
12634 struct tg3_internal_buffer_desc test_desc;
12635 u32 sram_dma_descs;
12636 int i, ret;
12637
12638 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12639
12640 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12641 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12642 tw32(RDMAC_STATUS, 0);
12643 tw32(WDMAC_STATUS, 0);
12644
12645 tw32(BUFMGR_MODE, 0);
12646 tw32(FTQ_RESET, 0);
12647
12648 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12649 test_desc.addr_lo = buf_dma & 0xffffffff;
12650 test_desc.nic_mbuf = 0x00002100;
12651 test_desc.len = size;
12652
12653 /*
12654 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12655 * the *second* time the tg3 driver was getting loaded after an
12656 * initial scan.
12657 *
12658 * Broadcom tells me:
12659 * ...the DMA engine is connected to the GRC block and a DMA
12660 * reset may affect the GRC block in some unpredictable way...
12661 * The behavior of resets to individual blocks has not been tested.
12662 *
12663 * Broadcom noted the GRC reset will also reset all sub-components.
12664 */
12665 if (to_device) {
12666 test_desc.cqid_sqid = (13 << 8) | 2;
12667
12668 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12669 udelay(40);
12670 } else {
12671 test_desc.cqid_sqid = (16 << 8) | 7;
12672
12673 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12674 udelay(40);
12675 }
12676 test_desc.flags = 0x00000005;
12677
12678 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12679 u32 val;
12680
12681 val = *(((u32 *)&test_desc) + i);
12682 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12683 sram_dma_descs + (i * sizeof(u32)));
12684 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12685 }
12686 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12687
12688 if (to_device) {
12689 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12690 } else {
12691 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12692 }
12693
12694 ret = -ENODEV;
12695 for (i = 0; i < 40; i++) {
12696 u32 val;
12697
12698 if (to_device)
12699 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12700 else
12701 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12702 if ((val & 0xffff) == sram_dma_descs) {
12703 ret = 0;
12704 break;
12705 }
12706
12707 udelay(100);
12708 }
12709
12710 return ret;
12711}
12712
ded7340d 12713#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12714
12715static int __devinit tg3_test_dma(struct tg3 *tp)
12716{
12717 dma_addr_t buf_dma;
59e6b434 12718 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12719 int ret;
12720
12721 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12722 if (!buf) {
12723 ret = -ENOMEM;
12724 goto out_nofree;
12725 }
12726
12727 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12728 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12729
59e6b434 12730 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12731
12732 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12733 /* DMA read watermark not used on PCIE */
12734 tp->dma_rwctrl |= 0x00180000;
12735 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12736 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12737 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12738 tp->dma_rwctrl |= 0x003f0000;
12739 else
12740 tp->dma_rwctrl |= 0x003f000f;
12741 } else {
12742 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12743 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12744 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12745 u32 read_water = 0x7;
1da177e4 12746
4a29cc2e
MC		 12747 /* If the 5704 is behind the EPB bridge, we can
12748 * do the less restrictive ONE_DMA workaround for
12749 * better performance.
12750 */
12751 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12752 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12753 tp->dma_rwctrl |= 0x8000;
12754 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12755 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12756
49afdeb6
MC		 12757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12758 read_water = 4;
59e6b434 12759 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12760 tp->dma_rwctrl |=
12761 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12762 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12763 (1 << 23);
4cf78e4f
MC		 12764 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12765 /* 5780 always in PCIX mode */
12766 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12767 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12768 /* 5714 always in PCIX mode */
12769 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12770 } else {
12771 tp->dma_rwctrl |= 0x001b000f;
12772 }
12773 }
12774
12775 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12776 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12777 tp->dma_rwctrl &= 0xfffffff0;
12778
12779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12780 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12781 /* Remove this if it causes problems for some boards. */
12782 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12783
12784 /* On 5700/5701 chips, we need to set this bit.
12785 * Otherwise the chip will issue cacheline transactions
12786 * to streamable DMA memory with not all the byte
12787 * enables turned on. This is an error on several
12788 * RISC PCI controllers, in particular sparc64.
12789 *
12790 * On 5703/5704 chips, this bit has been reassigned
12791 * a different meaning. In particular, it is used
12792 * on those chips to enable a PCI-X workaround.
12793 */
12794 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12795 }
12796
12797 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12798
12799#if 0
12800 /* Unneeded, already done by tg3_get_invariants. */
12801 tg3_switch_clocks(tp);
12802#endif
12803
12804 ret = 0;
12805 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12806 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12807 goto out;
12808
59e6b434
DM		 12809 /* It is best to perform DMA test with maximum write burst size
12810 * to expose the 5700/5701 write DMA bug.
12811 */
12812 saved_dma_rwctrl = tp->dma_rwctrl;
12813 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12814 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12815
1da177e4
LT		 12816 while (1) {
12817 u32 *p = buf, i;
12818
12819 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12820 p[i] = i;
12821
12822 /* Send the buffer to the chip. */
12823 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12824 if (ret) {
12825 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12826 break;
12827 }
12828
12829#if 0
12830 /* validate data reached card RAM correctly. */
12831 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12832 u32 val;
12833 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12834 if (le32_to_cpu(val) != p[i]) {
12835 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12836 /* ret = -ENODEV here? */
12837 }
12838 p[i] = 0;
12839 }
12840#endif
12841 /* Now read it back. */
12842 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12843 if (ret) {
12844 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12845
12846 break;
12847 }
12848
12849 /* Verify it. */
12850 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12851 if (p[i] == i)
12852 continue;
12853
59e6b434
DM		 12854 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12855 DMA_RWCTRL_WRITE_BNDRY_16) {
12856 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12857 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12858 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12859 break;
12860 } else {
12861 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12862 ret = -ENODEV;
12863 goto out;
12864 }
12865 }
12866
12867 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12868 /* Success. */
12869 ret = 0;
12870 break;
12871 }
12872 }
59e6b434
DM		 12873 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12874 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12875 static struct pci_device_id dma_wait_state_chipsets[] = {
12876 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12877 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12878 { },
12879 };
12880
59e6b434 12881 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12882 * now look for chipsets that are known to expose the
12883 * DMA bug without failing the test.
59e6b434 12884 */
6d1cfbab
MC		 12885 if (pci_dev_present(dma_wait_state_chipsets)) {
12886 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12887 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12888 }
12889 else
12890 /* Safe to use the calculated DMA boundary. */
12891 tp->dma_rwctrl = saved_dma_rwctrl;
12892
59e6b434
DM		 12893 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12894 }
1da177e4
LT		 12895
12896out:
12897 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12898out_nofree:
12899 return ret;
12900}
12901
12902static void __devinit tg3_init_link_config(struct tg3 *tp)
12903{
12904 tp->link_config.advertising =
12905 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12906 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12907 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12908 ADVERTISED_Autoneg | ADVERTISED_MII);
12909 tp->link_config.speed = SPEED_INVALID;
12910 tp->link_config.duplex = DUPLEX_INVALID;
12911 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12912 tp->link_config.active_speed = SPEED_INVALID;
12913 tp->link_config.active_duplex = DUPLEX_INVALID;
12914 tp->link_config.phy_is_low_power = 0;
12915 tp->link_config.orig_speed = SPEED_INVALID;
12916 tp->link_config.orig_duplex = DUPLEX_INVALID;
12917 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12918}
12919
12920static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12921{
fdfec172
MC		 12922 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12923 tp->bufmgr_config.mbuf_read_dma_low_water =
12924 DEFAULT_MB_RDMA_LOW_WATER_5705;
12925 tp->bufmgr_config.mbuf_mac_rx_low_water =
12926 DEFAULT_MB_MACRX_LOW_WATER_5705;
12927 tp->bufmgr_config.mbuf_high_water =
12928 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12929 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12930 tp->bufmgr_config.mbuf_mac_rx_low_water =
12931 DEFAULT_MB_MACRX_LOW_WATER_5906;
12932 tp->bufmgr_config.mbuf_high_water =
12933 DEFAULT_MB_HIGH_WATER_5906;
12934 }
fdfec172
MC		 12935
12936 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12937 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12938 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12939 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12940 tp->bufmgr_config.mbuf_high_water_jumbo =
12941 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12942 } else {
12943 tp->bufmgr_config.mbuf_read_dma_low_water =
12944 DEFAULT_MB_RDMA_LOW_WATER;
12945 tp->bufmgr_config.mbuf_mac_rx_low_water =
12946 DEFAULT_MB_MACRX_LOW_WATER;
12947 tp->bufmgr_config.mbuf_high_water =
12948 DEFAULT_MB_HIGH_WATER;
12949
12950 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12951 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12952 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12953 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12954 tp->bufmgr_config.mbuf_high_water_jumbo =
12955 DEFAULT_MB_HIGH_WATER_JUMBO;
12956 }
1da177e4
LT		 12957
12958 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12959 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12960}
12961
12962static char * __devinit tg3_phy_string(struct tg3 *tp)
12963{
12964 switch (tp->phy_id & PHY_ID_MASK) {
12965 case PHY_ID_BCM5400: return "5400";
12966 case PHY_ID_BCM5401: return "5401";
12967 case PHY_ID_BCM5411: return "5411";
12968 case PHY_ID_BCM5701: return "5701";
12969 case PHY_ID_BCM5703: return "5703";
12970 case PHY_ID_BCM5704: return "5704";
12971 case PHY_ID_BCM5705: return "5705";
12972 case PHY_ID_BCM5750: return "5750";
85e94ced 12973 case PHY_ID_BCM5752: return "5752";
a4e2b347 12974 case PHY_ID_BCM5714: return "5714";
4cf78e4f 12975 case PHY_ID_BCM5780: return "5780";
af36e6b6 12976 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 12977 case PHY_ID_BCM5787: return "5787";
d30cdd28 12978 case PHY_ID_BCM5784: return "5784";
126a3368 12979 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 12980 case PHY_ID_BCM5906: return "5906";
9936bcf6 12981 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 12982 case PHY_ID_BCM8002: return "8002/serdes";
12983 case 0: return "serdes";
12984 default: return "unknown";
855e1111 12985 }
1da177e4
LT		 12986}
12987
f9804ddb
MC		 12988static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12989{
12990 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12991 strcpy(str, "PCI Express");
12992 return str;
12993 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12994 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12995
12996 strcpy(str, "PCIX:");
12997
12998 if ((clock_ctrl == 7) ||
12999 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13000 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13001 strcat(str, "133MHz");
13002 else if (clock_ctrl == 0)
13003 strcat(str, "33MHz");
13004 else if (clock_ctrl == 2)
13005 strcat(str, "50MHz");
13006 else if (clock_ctrl == 4)
13007 strcat(str, "66MHz");
13008 else if (clock_ctrl == 6)
13009 strcat(str, "100MHz");
f9804ddb
MC		 13010 } else {
13011 strcpy(str, "PCI:");
13012 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13013 strcat(str, "66MHz");
13014 else
13015 strcat(str, "33MHz");
13016 }
13017 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13018 strcat(str, ":32-bit");
13019 else
13020 strcat(str, ":64-bit");
13021 return str;
13022}
13023
8c2dc7e1 13024static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13025{
13026 struct pci_dev *peer;
13027 unsigned int func, devnr = tp->pdev->devfn & ~7;
13028
13029 for (func = 0; func < 8; func++) {
13030 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13031 if (peer && peer != tp->pdev)
13032 break;
13033 pci_dev_put(peer);
13034 }
16fe9d74
MC		 13035 /* 5704 can be configured in single-port mode, set peer to
13036 * tp->pdev in that case.
13037 */
13038 if (!peer) {
13039 peer = tp->pdev;
13040 return peer;
13041 }
1da177e4
LT		 13042
13043 /*
13044 * We don't need to keep the refcount elevated; there's no way
13045 * to remove one half of this device without removing the other
13046 */
13047 pci_dev_put(peer);
13048
13049 return peer;
13050}
13051
15f9850d
DM		 13052static void __devinit tg3_init_coal(struct tg3 *tp)
13053{
13054 struct ethtool_coalesce *ec = &tp->coal;
13055
13056 memset(ec, 0, sizeof(*ec));
13057 ec->cmd = ETHTOOL_GCOALESCE;
13058 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13059 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13060 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13061 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13062 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13063 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13064 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13065 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13066 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13067
13068 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13069 HOSTCC_MODE_CLRTICK_TXBD)) {
13070 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13071 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13072 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13073 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13074 }
d244c892
MC		 13075
13076 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13077 ec->rx_coalesce_usecs_irq = 0;
13078 ec->tx_coalesce_usecs_irq = 0;
13079 ec->stats_block_coalesce_usecs = 0;
13080 }
15f9850d
DM		 13081}
13082
7c7d64b8
SH		 13083static const struct net_device_ops tg3_netdev_ops = {
13084 .ndo_open = tg3_open,
13085 .ndo_stop = tg3_close,
00829823
SH		 13086 .ndo_start_xmit = tg3_start_xmit,
13087 .ndo_get_stats = tg3_get_stats,
13088 .ndo_validate_addr = eth_validate_addr,
13089 .ndo_set_multicast_list = tg3_set_rx_mode,
13090 .ndo_set_mac_address = tg3_set_mac_addr,
13091 .ndo_do_ioctl = tg3_ioctl,
13092 .ndo_tx_timeout = tg3_tx_timeout,
13093 .ndo_change_mtu = tg3_change_mtu,
13094#if TG3_VLAN_TAG_USED
13095 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13096#endif
13097#ifdef CONFIG_NET_POLL_CONTROLLER
13098 .ndo_poll_controller = tg3_poll_controller,
13099#endif
13100};
13101
13102static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13103 .ndo_open = tg3_open,
13104 .ndo_stop = tg3_close,
13105 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13106 .ndo_get_stats = tg3_get_stats,
13107 .ndo_validate_addr = eth_validate_addr,
13108 .ndo_set_multicast_list = tg3_set_rx_mode,
13109 .ndo_set_mac_address = tg3_set_mac_addr,
13110 .ndo_do_ioctl = tg3_ioctl,
13111 .ndo_tx_timeout = tg3_tx_timeout,
13112 .ndo_change_mtu = tg3_change_mtu,
13113#if TG3_VLAN_TAG_USED
13114 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13115#endif
13116#ifdef CONFIG_NET_POLL_CONTROLLER
13117 .ndo_poll_controller = tg3_poll_controller,
13118#endif
13119};
13120
1da177e4
LT		 13121static int __devinit tg3_init_one(struct pci_dev *pdev,
13122 const struct pci_device_id *ent)
13123{
13124 static int tg3_version_printed = 0;
1da177e4
LT		 13125 struct net_device *dev;
13126 struct tg3 *tp;
d6645372 13127 int err, pm_cap;
f9804ddb 13128 char str[40];
72f2afb8 13129 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13130
13131 if (tg3_version_printed++ == 0)
13132 printk(KERN_INFO "%s", version);
13133
13134 err = pci_enable_device(pdev);
13135 if (err) {
13136 printk(KERN_ERR PFX "Cannot enable PCI device, "
13137 "aborting.\n");
13138 return err;
13139 }
13140
1da177e4
LT		 13141 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13142 if (err) {
13143 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13144 "aborting.\n");
13145 goto err_out_disable_pdev;
13146 }
13147
13148 pci_set_master(pdev);
13149
13150 /* Find power-management capability. */
13151 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13152 if (pm_cap == 0) {
13153 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13154 "aborting.\n");
13155 err = -EIO;
13156 goto err_out_free_res;
13157 }
13158
1da177e4
LT		 13159 dev = alloc_etherdev(sizeof(*tp));
13160 if (!dev) {
13161 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13162 err = -ENOMEM;
13163 goto err_out_free_res;
13164 }
13165
1da177e4
LT		 13166 SET_NETDEV_DEV(dev, &pdev->dev);
13167
1da177e4
LT		 13168#if TG3_VLAN_TAG_USED
13169 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13170#endif
13171
13172 tp = netdev_priv(dev);
13173 tp->pdev = pdev;
13174 tp->dev = dev;
13175 tp->pm_cap = pm_cap;
1da177e4
LT		 13176 tp->rx_mode = TG3_DEF_RX_MODE;
13177 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13178
1da177e4
LT		 13179 if (tg3_debug > 0)
13180 tp->msg_enable = tg3_debug;
13181 else
13182 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13183
13184 /* The word/byte swap controls here control register access byte
13185 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13186 * setting below.
13187 */
13188 tp->misc_host_ctrl =
13189 MISC_HOST_CTRL_MASK_PCI_INT |
13190 MISC_HOST_CTRL_WORD_SWAP |
13191 MISC_HOST_CTRL_INDIR_ACCESS |
13192 MISC_HOST_CTRL_PCISTATE_RW;
13193
13194 /* The NONFRM (non-frame) byte/word swap controls take effect
13195 * on descriptor entries, anything which isn't packet data.
13196 *
13197 * The StrongARM chips on the board (one for tx, one for rx)
13198 * are running in big-endian mode.
13199 */
13200 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13201 GRC_MODE_WSWAP_NONFRM_DATA);
13202#ifdef __BIG_ENDIAN
13203 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13204#endif
13205 spin_lock_init(&tp->lock);
1da177e4 13206 spin_lock_init(&tp->indirect_lock);
c4028958 13207 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13208
d5fe488a 13209 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13210 if (!tp->regs) {
1da177e4
LT		 13211 printk(KERN_ERR PFX "Cannot map device registers, "
13212 "aborting.\n");
13213 err = -ENOMEM;
13214 goto err_out_free_dev;
13215 }
13216
13217 tg3_init_link_config(tp);
13218
1da177e4
LT		 13219 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13220 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13221 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13222
bea3348e 13223 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13224 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13225 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13226 dev->irq = pdev->irq;
1da177e4
LT		 13227
13228 err = tg3_get_invariants(tp);
13229 if (err) {
13230 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13231 "aborting.\n");
13232 goto err_out_iounmap;
13233 }
13234
321d32a0 13235 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13236 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13237 dev->netdev_ops = &tg3_netdev_ops;
13238 else
13239 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13240
13241
4a29cc2e
MC		 13242 /* The EPB bridge inside 5714, 5715, and 5780 and any
13243 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13244 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13245 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13246 * do DMA address check in tg3_start_xmit().
13247 */
4a29cc2e 13248 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13249 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13250 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13251 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13252#ifdef CONFIG_HIGHMEM
6a35528a 13253 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13254#endif
4a29cc2e 13255 } else
6a35528a 13256 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13257
13258 /* Configure DMA attributes. */
284901a9 13259 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13260 err = pci_set_dma_mask(pdev, dma_mask);
13261 if (!err) {
13262 dev->features |= NETIF_F_HIGHDMA;
13263 err = pci_set_consistent_dma_mask(pdev,
13264 persist_dma_mask);
13265 if (err < 0) {
13266 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13267 "DMA for consistent allocations\n");
13268 goto err_out_iounmap;
13269 }
13270 }
13271 }
284901a9
YH		 13272 if (err || dma_mask == DMA_BIT_MASK(32)) {
13273 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13274 if (err) {
13275 printk(KERN_ERR PFX "No usable DMA configuration, "
13276 "aborting.\n");
13277 goto err_out_iounmap;
13278 }
13279 }
13280
fdfec172 13281 tg3_init_bufmgr_config(tp);
1da177e4 13282
077f849d 13283 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13284 tp->fw_needed = FIRMWARE_TG3;
077f849d 13285
1da177e4
LT		 13286 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13287 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13288 }
13289 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13291 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13292 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13293 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13294 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13295 } else {
7f62ad5d 13296 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13297 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13298 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13299 else
9e9fd12d 13300 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13301 }
1da177e4 13302
4e3a7aaa
MC		 13303 /* TSO is on by default on chips that support hardware TSO.
13304 * Firmware TSO on older chips gives lower performance, so it
13305 * is off by default, but can be enabled using ethtool.
13306 */
b0026624 13307 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13308 if (dev->features & NETIF_F_IP_CSUM)
13309 dev->features |= NETIF_F_TSO;
13310 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13311 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13312 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13313 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13314 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13315 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13318 dev->features |= NETIF_F_TSO_ECN;
b0026624 13319 }
1da177e4 13320
1da177e4
LT		 13321
13322 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13323 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13324 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13325 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13326 tp->rx_pending = 63;
13327 }
13328
1da177e4
LT		 13329 err = tg3_get_device_address(tp);
13330 if (err) {
13331 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13332 "aborting.\n");
077f849d 13333 goto err_out_fw;
1da177e4
LT		 13334 }
13335
c88864df 13336 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13337 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13338 if (!tp->aperegs) {
c88864df
MC		 13339 printk(KERN_ERR PFX "Cannot map APE registers, "
13340 "aborting.\n");
13341 err = -ENOMEM;
077f849d 13342 goto err_out_fw;
c88864df
MC		 13343 }
13344
13345 tg3_ape_lock_init(tp);
7fd76445
MC		 13346
13347 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13348 tg3_read_dash_ver(tp);
c88864df
MC		 13349 }
13350
1da177e4
LT		 13351 /*
13352 * Reset chip in case UNDI or EFI driver did not shutdown
13353 * DMA self test will enable WDMAC and we'll see (spurious)
13354 * pending DMA on the PCI bus at that point.
13355 */
13356 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13357 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13358 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13359 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13360 }
13361
13362 err = tg3_test_dma(tp);
13363 if (err) {
13364 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13365 goto err_out_apeunmap;
1da177e4
LT		 13366 }
13367
1da177e4
LT		 13368 /* flow control autonegotiation is default behavior */
13369 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13370 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13371
15f9850d
DM		 13372 tg3_init_coal(tp);
13373
c49a1561
MC		 13374 pci_set_drvdata(pdev, dev);
13375
1da177e4
LT		 13376 err = register_netdev(dev);
13377 if (err) {
13378 printk(KERN_ERR PFX "Cannot register net device, "
13379 "aborting.\n");
0d3031d9 13380 goto err_out_apeunmap;
1da177e4
LT		 13381 }
13382
df59c940 13383 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13384 dev->name,
13385 tp->board_part_number,
13386 tp->pci_chip_rev_id,
f9804ddb 13387 tg3_bus_string(tp, str),
e174961c 13388 dev->dev_addr);
1da177e4 13389
df59c940
MC		 13390 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13391 printk(KERN_INFO
13392 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13393 tp->dev->name,
13394 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13395 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13396 else
13397 printk(KERN_INFO
13398 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13399 tp->dev->name, tg3_phy_string(tp),
13400 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13401 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13402 "10/100/1000Base-T")),
13403 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13404
13405 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13406 dev->name,
13407 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13408 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13409 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13410 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13411 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13412 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13413 dev->name, tp->dma_rwctrl,
284901a9 13414 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13415 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13416
13417 return 0;
13418
0d3031d9
MC		 13419err_out_apeunmap:
13420 if (tp->aperegs) {
13421 iounmap(tp->aperegs);
13422 tp->aperegs = NULL;
13423 }
13424
077f849d
JSR		 13425err_out_fw:
13426 if (tp->fw)
13427 release_firmware(tp->fw);
13428
1da177e4 13429err_out_iounmap:
6892914f
MC		 13430 if (tp->regs) {
13431 iounmap(tp->regs);
22abe310 13432 tp->regs = NULL;
6892914f 13433 }
1da177e4
LT		 13434
13435err_out_free_dev:
13436 free_netdev(dev);
13437
13438err_out_free_res:
13439 pci_release_regions(pdev);
13440
13441err_out_disable_pdev:
13442 pci_disable_device(pdev);
13443 pci_set_drvdata(pdev, NULL);
13444 return err;
13445}
13446
13447static void __devexit tg3_remove_one(struct pci_dev *pdev)
13448{
13449 struct net_device *dev = pci_get_drvdata(pdev);
13450
13451 if (dev) {
13452 struct tg3 *tp = netdev_priv(dev);
13453
077f849d
JSR		 13454 if (tp->fw)
13455 release_firmware(tp->fw);
13456
7faa006f 13457 flush_scheduled_work();
158d7abd 13458
b02fd9e3
MC		 13459 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13460 tg3_phy_fini(tp);
158d7abd 13461 tg3_mdio_fini(tp);
b02fd9e3 13462 }
158d7abd 13463
1da177e4 13464 unregister_netdev(dev);
0d3031d9
MC		 13465 if (tp->aperegs) {
13466 iounmap(tp->aperegs);
13467 tp->aperegs = NULL;
13468 }
6892914f
MC		 13469 if (tp->regs) {
13470 iounmap(tp->regs);
22abe310 13471 tp->regs = NULL;
6892914f 13472 }
1da177e4
LT		 13473 free_netdev(dev);
13474 pci_release_regions(pdev);
13475 pci_disable_device(pdev);
13476 pci_set_drvdata(pdev, NULL);
13477 }
13478}
13479
13480static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13481{
13482 struct net_device *dev = pci_get_drvdata(pdev);
13483 struct tg3 *tp = netdev_priv(dev);
12dac075 13484 pci_power_t target_state;
1da177e4
LT		 13485 int err;
13486
3e0c95fd
MC		 13487 /* PCI register 4 needs to be saved whether netif_running() or not.
13488 * MSI address and data need to be saved if using MSI and
13489 * netif_running().
13490 */
13491 pci_save_state(pdev);
13492
1da177e4
LT		 13493 if (!netif_running(dev))
13494 return 0;
13495
7faa006f 13496 flush_scheduled_work();
b02fd9e3 13497 tg3_phy_stop(tp);
1da177e4
LT		 13498 tg3_netif_stop(tp);
13499
13500 del_timer_sync(&tp->timer);
13501
f47c11ee 13502 tg3_full_lock(tp, 1);
1da177e4 13503 tg3_disable_ints(tp);
f47c11ee 13504 tg3_full_unlock(tp);
1da177e4
LT		 13505
13506 netif_device_detach(dev);
13507
f47c11ee 13508 tg3_full_lock(tp, 0);
944d980e 13509 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13510 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13511 tg3_full_unlock(tp);
1da177e4 13512
12dac075
RW		 13513 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13514
13515 err = tg3_set_power_state(tp, target_state);
1da177e4 13516 if (err) {
b02fd9e3
MC		 13517 int err2;
13518
f47c11ee 13519 tg3_full_lock(tp, 0);
1da177e4 13520
6a9eba15 13521 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13522 err2 = tg3_restart_hw(tp, 1);
13523 if (err2)
b9ec6c1b 13524 goto out;
1da177e4
LT		 13525
13526 tp->timer.expires = jiffies + tp->timer_offset;
13527 add_timer(&tp->timer);
13528
13529 netif_device_attach(dev);
13530 tg3_netif_start(tp);
13531
b9ec6c1b 13532out:
f47c11ee 13533 tg3_full_unlock(tp);
b02fd9e3
MC		 13534
13535 if (!err2)
13536 tg3_phy_start(tp);
1da177e4
LT		 13537 }
13538
13539 return err;
13540}
13541
13542static int tg3_resume(struct pci_dev *pdev)
13543{
13544 struct net_device *dev = pci_get_drvdata(pdev);
13545 struct tg3 *tp = netdev_priv(dev);
13546 int err;
13547
3e0c95fd
MC		 13548 pci_restore_state(tp->pdev);
13549
1da177e4
LT		 13550 if (!netif_running(dev))
13551 return 0;
13552
bc1c7567 13553 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13554 if (err)
13555 return err;
13556
13557 netif_device_attach(dev);
13558
f47c11ee 13559 tg3_full_lock(tp, 0);
1da177e4 13560
6a9eba15 13561 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13562 err = tg3_restart_hw(tp, 1);
13563 if (err)
13564 goto out;
1da177e4
LT		 13565
13566 tp->timer.expires = jiffies + tp->timer_offset;
13567 add_timer(&tp->timer);
13568
1da177e4
LT		 13569 tg3_netif_start(tp);
13570
b9ec6c1b 13571out:
f47c11ee 13572 tg3_full_unlock(tp);
1da177e4 13573
b02fd9e3
MC		 13574 if (!err)
13575 tg3_phy_start(tp);
13576
b9ec6c1b 13577 return err;
1da177e4
LT		 13578}
13579
13580static struct pci_driver tg3_driver = {
13581 .name = DRV_MODULE_NAME,
13582 .id_table = tg3_pci_tbl,
13583 .probe = tg3_init_one,
13584 .remove = __devexit_p(tg3_remove_one),
13585 .suspend = tg3_suspend,
13586 .resume = tg3_resume
13587};
13588
13589static int __init tg3_init(void)
13590{
29917620 13591 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13592}
13593
13594static void __exit tg3_cleanup(void)
13595{
13596 pci_unregister_driver(&tg3_driver);
13597}
13598
13599module_init(tg3_init);
13600module_exit(tg3_cleanup);
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