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[TG3]: 5722/5756 don't need PHY jitter workaround.
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
43
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/byteorder.h>
47#include <asm/uaccess.h>
48
49#ifdef CONFIG_SPARC64
50#include <asm/idprom.h>
51#include <asm/oplib.h>
52#include <asm/pbm.h>
53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
1da177e4 61#define TG3_TSO_SUPPORT 1
1da177e4
LT		 62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
c1d2a196
MC		 67#define DRV_MODULE_VERSION "3.72"
68#define DRV_MODULE_RELDATE "January 8, 2007"
1da177e4
LT		 69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83/* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88/* hardware minimum and maximum for a single frame's data payload */
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
0f893dc6 91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 92
93/* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102/* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
1da177e4
LT		 122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127/* minimum number of free TX descriptors required to wake up TX process */
42952231 128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4
LT		 129
130/* number of ETHTOOL_GSTATS u64's */
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
4cafd3f5
MC		 133#define TG3_NUM_TEST 6
134
1da177e4
LT		 135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
13185217
HK		 201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
1da177e4
LT		 209};
210
211MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
50da859d 213static const struct {
1da177e4
LT		 214 const char string[ETH_GSTRING_LEN];
215} ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292};
293
50da859d 294static const struct {
4cafd3f5
MC		 295 const char string[ETH_GSTRING_LEN];
296} ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303};
304
b401e9e2
MC		 305static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306{
307 writel(val, tp->regs + off);
308}
309
310static u32 tg3_read32(struct tg3 *tp, u32 off)
311{
6aa20a22 312 return (readl(tp->regs + off));
b401e9e2
MC		 313}
314
1da177e4
LT		 315static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316{
6892914f
MC		 317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 323}
324
325static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326{
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
1da177e4
LT		 329}
330
6892914f 331static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 332{
6892914f
MC		 333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341}
342
343static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344{
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
1da177e4 356 }
6892914f
MC		 357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371}
372
373static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374{
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383}
384
b401e9e2
MC		 385/* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 391{
b401e9e2
MC		 392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
1da177e4
LT		 408}
409
09ee929c
MC		 410static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411{
412 tp->write32_mbox(tp, off, val);
6892914f
MC		 413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
09ee929c
MC		 416}
417
20094930 418static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 419{
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426}
427
b5d3772c
MC		 428static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429{
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431}
432
433static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434{
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436}
437
20094930 438#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 439#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 440#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 442#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 443
444#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 445#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 447#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 448
449static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450{
6892914f
MC		 451 unsigned long flags;
452
b5d3772c
MC		 453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
6892914f 457 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 461
bbadf503
MC		 462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 467
bbadf503
MC		 468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 472}
473
1da177e4
LT		 474static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475{
6892914f
MC		 476 unsigned long flags;
477
b5d3772c
MC		 478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
6892914f 484 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 488
bbadf503
MC		 489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 499}
500
501static void tg3_disable_ints(struct tg3 *tp)
502{
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 506}
507
508static inline void tg3_cond_int(struct tg3 *tp)
509{
38f3843e
MC		 510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 516}
517
518static void tg3_enable_ints(struct tg3 *tp)
519{
bbe832c0
MC		 520 tp->irq_sync = 0;
521 wmb();
522
1da177e4
LT		 523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
fcfa0a32
MC		 527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
1da177e4
LT		 530 tg3_cond_int(tp);
531}
532
04237ddd
MC		 533static inline unsigned int tg3_has_work(struct tg3 *tp)
534{
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551}
552
1da177e4 553/* tg3_restart_ints
04237ddd
MC		 554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
6aa20a22 556 * which reenables interrupts
1da177e4
LT		 557 */
558static void tg3_restart_ints(struct tg3 *tp)
559{
fac9b83e
DM		 560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
1da177e4
LT		 562 mmiowb();
563
fac9b83e
DM		 564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
04237ddd
MC		 570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 572}
573
574static inline void tg3_netif_stop(struct tg3 *tp)
575{
bbe832c0 576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579}
580
581static inline void tg3_netif_start(struct tg3 *tp)
582{
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
f47c11ee
DM		 589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
1da177e4
LT		 591}
592
593static void tg3_switch_clocks(struct tg3 *tp)
594{
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
a4e2b347 598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f
MC		 599 return;
600
1da177e4
LT		 601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
1da177e4 620 }
b401e9e2 621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 622}
623
624#define PHY_BUSY_LOOPS 5000
625
626static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627{
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 645
1da177e4
LT		 646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673}
674
675static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676{
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
b5d3772c
MC		 681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
1da177e4
LT		 685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 697
1da177e4
LT		 698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722}
723
724static void tg3_phy_set_wirespeed(struct tg3 *tp)
725{
726 u32 val;
727
728 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
729 return;
730
731 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
732 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
733 tg3_writephy(tp, MII_TG3_AUX_CTRL,
734 (val | (1 << 15) | (1 << 4)));
735}
736
737static int tg3_bmcr_reset(struct tg3 *tp)
738{
739 u32 phy_control;
740 int limit, err;
741
742 /* OK, reset it, and poll the BMCR_RESET bit until it
743 * clears or we time out.
744 */
745 phy_control = BMCR_RESET;
746 err = tg3_writephy(tp, MII_BMCR, phy_control);
747 if (err != 0)
748 return -EBUSY;
749
750 limit = 5000;
751 while (limit--) {
752 err = tg3_readphy(tp, MII_BMCR, &phy_control);
753 if (err != 0)
754 return -EBUSY;
755
756 if ((phy_control & BMCR_RESET) == 0) {
757 udelay(40);
758 break;
759 }
760 udelay(10);
761 }
762 if (limit <= 0)
763 return -EBUSY;
764
765 return 0;
766}
767
768static int tg3_wait_macro_done(struct tg3 *tp)
769{
770 int limit = 100;
771
772 while (limit--) {
773 u32 tmp32;
774
775 if (!tg3_readphy(tp, 0x16, &tmp32)) {
776 if ((tmp32 & 0x1000) == 0)
777 break;
778 }
779 }
780 if (limit <= 0)
781 return -EBUSY;
782
783 return 0;
784}
785
786static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
787{
788 static const u32 test_pat[4][6] = {
789 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
790 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
791 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
792 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
793 };
794 int chan;
795
796 for (chan = 0; chan < 4; chan++) {
797 int i;
798
799 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
800 (chan * 0x2000) | 0x0200);
801 tg3_writephy(tp, 0x16, 0x0002);
802
803 for (i = 0; i < 6; i++)
804 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
805 test_pat[chan][i]);
806
807 tg3_writephy(tp, 0x16, 0x0202);
808 if (tg3_wait_macro_done(tp)) {
809 *resetp = 1;
810 return -EBUSY;
811 }
812
813 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
814 (chan * 0x2000) | 0x0200);
815 tg3_writephy(tp, 0x16, 0x0082);
816 if (tg3_wait_macro_done(tp)) {
817 *resetp = 1;
818 return -EBUSY;
819 }
820
821 tg3_writephy(tp, 0x16, 0x0802);
822 if (tg3_wait_macro_done(tp)) {
823 *resetp = 1;
824 return -EBUSY;
825 }
826
827 for (i = 0; i < 6; i += 2) {
828 u32 low, high;
829
830 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
831 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
832 tg3_wait_macro_done(tp)) {
833 *resetp = 1;
834 return -EBUSY;
835 }
836 low &= 0x7fff;
837 high &= 0x000f;
838 if (low != test_pat[chan][i] ||
839 high != test_pat[chan][i+1]) {
840 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
841 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
843
844 return -EBUSY;
845 }
846 }
847 }
848
849 return 0;
850}
851
852static int tg3_phy_reset_chanpat(struct tg3 *tp)
853{
854 int chan;
855
856 for (chan = 0; chan < 4; chan++) {
857 int i;
858
859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
860 (chan * 0x2000) | 0x0200);
861 tg3_writephy(tp, 0x16, 0x0002);
862 for (i = 0; i < 6; i++)
863 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
864 tg3_writephy(tp, 0x16, 0x0202);
865 if (tg3_wait_macro_done(tp))
866 return -EBUSY;
867 }
868
869 return 0;
870}
871
872static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
873{
874 u32 reg32, phy9_orig;
875 int retries, do_phy_reset, err;
876
877 retries = 10;
878 do_phy_reset = 1;
879 do {
880 if (do_phy_reset) {
881 err = tg3_bmcr_reset(tp);
882 if (err)
883 return err;
884 do_phy_reset = 0;
885 }
886
887 /* Disable transmitter and interrupt. */
888 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
889 continue;
890
891 reg32 |= 0x3000;
892 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
893
894 /* Set full-duplex, 1000 mbps. */
895 tg3_writephy(tp, MII_BMCR,
896 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
897
898 /* Set to master mode. */
899 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
900 continue;
901
902 tg3_writephy(tp, MII_TG3_CTRL,
903 (MII_TG3_CTRL_AS_MASTER |
904 MII_TG3_CTRL_ENABLE_AS_MASTER));
905
906 /* Enable SM_DSP_CLOCK and 6dB. */
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
908
909 /* Block the PHY control access. */
910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
912
913 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
914 if (!err)
915 break;
916 } while (--retries);
917
918 err = tg3_phy_reset_chanpat(tp);
919 if (err)
920 return err;
921
922 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
926 tg3_writephy(tp, 0x16, 0x0000);
927
928 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
930 /* Set Extended packet length bit for jumbo frames */
931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
932 }
933 else {
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
935 }
936
937 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
938
939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940 reg32 &= ~0x3000;
941 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
942 } else if (!err)
943 err = -EBUSY;
944
945 return err;
946}
947
c8e1e82b
MC		 948static void tg3_link_report(struct tg3 *);
949
1da177e4
LT		 950/* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
952 */
953static int tg3_phy_reset(struct tg3 *tp)
954{
955 u32 phy_status;
956 int err;
957
60189ddf
MC		 958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
959 u32 val;
960
961 val = tr32(GRC_MISC_CFG);
962 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
963 udelay(40);
964 }
1da177e4
LT		 965 err = tg3_readphy(tp, MII_BMSR, &phy_status);
966 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
967 if (err != 0)
968 return -EBUSY;
969
c8e1e82b
MC		 970 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
971 netif_carrier_off(tp->dev);
972 tg3_link_report(tp);
973 }
974
1da177e4
LT		 975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
978 err = tg3_phy_reset_5703_4_5(tp);
979 if (err)
980 return err;
981 goto out;
982 }
983
984 err = tg3_bmcr_reset(tp);
985 if (err)
986 return err;
987
988out:
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
995 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
996 }
997 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
998 tg3_writephy(tp, 0x1c, 0x8d68);
999 tg3_writephy(tp, 0x1c, 0x8d68);
1000 }
1001 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010 }
c424cb24
MC		 1011 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1014 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016 tg3_writephy(tp, MII_TG3_TEST1,
1017 MII_TG3_TEST1_TRIM_EN | 0x4);
1018 } else
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1020 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021 }
1da177e4
LT		 1022 /* Set Extended packet length bit (bit 14) on all chips that */
1023 /* support jumbo frames */
1024 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025 /* Cannot do read-modify-write on 5401 */
1026 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1027 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1028 u32 phy_reg;
1029
1030 /* Set bit 14 with read-modify-write to preserve other bits */
1031 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034 }
1035
1036 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037 * jumbo frames transmission.
1038 */
0f893dc6 1039 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1040 u32 phy_reg;
1041
1042 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045 }
1046
715116a1
MC		 1047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048 u32 phy_reg;
1049
1050 /* adjust output voltage */
1051 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054 u32 phy_reg2;
1055
1056 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057 phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058 /* Enable auto-MDIX */
1059 if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061 tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062 }
1063 }
1064
1da177e4
LT		 1065 tg3_phy_set_wirespeed(tp);
1066 return 0;
1067}
1068
1069static void tg3_frob_aux_power(struct tg3 *tp)
1070{
1071 struct tg3 *tp_peer = tp;
1072
9d26e213 1073 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1074 return;
1075
8c2dc7e1
MC		 1076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078 struct net_device *dev_peer;
1079
1080 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1081 /* remove_one() may have been run on the peer. */
8c2dc7e1 1082 if (!dev_peer)
bc1c7567
MC		 1083 tp_peer = tp;
1084 else
1085 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1086 }
1087
1da177e4 1088 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1089 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095 (GRC_LCLCTRL_GPIO_OE0 |
1096 GRC_LCLCTRL_GPIO_OE1 |
1097 GRC_LCLCTRL_GPIO_OE2 |
1098 GRC_LCLCTRL_GPIO_OUTPUT0 |
1099 GRC_LCLCTRL_GPIO_OUTPUT1),
1100 100);
1da177e4
LT		 1101 } else {
1102 u32 no_gpio2;
dc56b7d4 1103 u32 grc_local_ctrl = 0;
1da177e4
LT		 1104
1105 if (tp_peer != tp &&
1106 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107 return;
1108
dc56b7d4
MC		 1109 /* Workaround to prevent overdrawing Amps. */
1110 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111 ASIC_REV_5714) {
1112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 grc_local_ctrl, 100);
dc56b7d4
MC		 1115 }
1116
1da177e4
LT		 1117 /* On 5753 and variants, GPIO2 cannot be used. */
1118 no_gpio2 = tp->nic_sram_data_cfg &
1119 NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
dc56b7d4 1121 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT1 |
1125 GRC_LCLCTRL_GPIO_OUTPUT2;
1126 if (no_gpio2) {
1127 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128 GRC_LCLCTRL_GPIO_OUTPUT2);
1129 }
b401e9e2
MC		 1130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131 grc_local_ctrl, 100);
1da177e4
LT		 1132
1133 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
b401e9e2
MC		 1135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136 grc_local_ctrl, 100);
1da177e4
LT		 1137
1138 if (!no_gpio2) {
1139 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1140 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141 grc_local_ctrl, 100);
1da177e4
LT		 1142 }
1143 }
1144 } else {
1145 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147 if (tp_peer != tp &&
1148 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149 return;
1150
b401e9e2
MC		 1151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152 (GRC_LCLCTRL_GPIO_OE1 |
1153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1154
b401e9e2
MC		 1155 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1157
b401e9e2
MC		 1158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159 (GRC_LCLCTRL_GPIO_OE1 |
1160 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1161 }
1162 }
1163}
1164
1165static int tg3_setup_phy(struct tg3 *, int);
1166
1167#define RESET_KIND_SHUTDOWN 0
1168#define RESET_KIND_INIT 1
1169#define RESET_KIND_SUSPEND 2
1170
1171static void tg3_write_sig_post_reset(struct tg3 *, int);
1172static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1173static int tg3_nvram_lock(struct tg3 *);
1174static void tg3_nvram_unlock(struct tg3 *);
1da177e4 1175
15c3b696
MC		 1176static void tg3_power_down_phy(struct tg3 *tp)
1177{
3f7045c1
MC		 1178 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1179 return;
1180
60189ddf
MC		 1181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1182 u32 val;
1183
1184 tg3_bmcr_reset(tp);
1185 val = tr32(GRC_MISC_CFG);
1186 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1187 udelay(40);
1188 return;
1189 } else {
715116a1
MC		 1190 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1191 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1192 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1193 }
3f7045c1 1194
15c3b696
MC		 1195 /* The PHY should not be powered down on some chips because
1196 * of bugs.
1197 */
1198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1199 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1200 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1201 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1202 return;
1203 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1204}
1205
bc1c7567 1206static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 1207{
1208 u32 misc_host_ctrl;
1209 u16 power_control, power_caps;
1210 int pm = tp->pm_cap;
1211
1212 /* Make sure register accesses (indirect or otherwise)
1213 * will function correctly.
1214 */
1215 pci_write_config_dword(tp->pdev,
1216 TG3PCI_MISC_HOST_CTRL,
1217 tp->misc_host_ctrl);
1218
1219 pci_read_config_word(tp->pdev,
1220 pm + PCI_PM_CTRL,
1221 &power_control);
1222 power_control |= PCI_PM_CTRL_PME_STATUS;
1223 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1224 switch (state) {
bc1c7567 1225 case PCI_D0:
1da177e4
LT		 1226 power_control |= 0;
1227 pci_write_config_word(tp->pdev,
1228 pm + PCI_PM_CTRL,
1229 power_control);
8c6bda1a
MC		 1230 udelay(100); /* Delay after power state change */
1231
9d26e213
MC		 1232 /* Switch out of Vaux if it is a NIC */
1233 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 1234 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1235
1236 return 0;
1237
bc1c7567 1238 case PCI_D1:
1da177e4
LT		 1239 power_control |= 1;
1240 break;
1241
bc1c7567 1242 case PCI_D2:
1da177e4
LT		 1243 power_control |= 2;
1244 break;
1245
bc1c7567 1246 case PCI_D3hot:
1da177e4
LT		 1247 power_control |= 3;
1248 break;
1249
1250 default:
1251 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1252 "requested.\n",
1253 tp->dev->name, state);
1254 return -EINVAL;
1255 };
1256
1257 power_control |= PCI_PM_CTRL_PME_ENABLE;
1258
1259 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1260 tw32(TG3PCI_MISC_HOST_CTRL,
1261 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1262
1263 if (tp->link_config.phy_is_low_power == 0) {
1264 tp->link_config.phy_is_low_power = 1;
1265 tp->link_config.orig_speed = tp->link_config.speed;
1266 tp->link_config.orig_duplex = tp->link_config.duplex;
1267 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1268 }
1269
747e8f8b 1270 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1271 tp->link_config.speed = SPEED_10;
1272 tp->link_config.duplex = DUPLEX_HALF;
1273 tp->link_config.autoneg = AUTONEG_ENABLE;
1274 tg3_setup_phy(tp, 0);
1275 }
1276
b5d3772c
MC		 1277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1278 u32 val;
1279
1280 val = tr32(GRC_VCPU_EXT_CTRL);
1281 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1282 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 1283 int i;
1284 u32 val;
1285
1286 for (i = 0; i < 200; i++) {
1287 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1288 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1289 break;
1290 msleep(1);
1291 }
1292 }
1293 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1294 WOL_DRV_STATE_SHUTDOWN |
1295 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1296
1da177e4
LT		 1297 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1298
1299 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1300 u32 mac_mode;
1301
1302 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1303 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1304 udelay(40);
1305
3f7045c1
MC		 1306 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1307 mac_mode = MAC_MODE_PORT_MODE_GMII;
1308 else
1309 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4
LT		 1310
1311 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1312 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1313 mac_mode |= MAC_MODE_LINK_POLARITY;
1314 } else {
1315 mac_mode = MAC_MODE_PORT_MODE_TBI;
1316 }
1317
cbf46853 1318 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1319 tw32(MAC_LED_CTRL, tp->led_ctrl);
1320
1321 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1322 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1323 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1324
1325 tw32_f(MAC_MODE, mac_mode);
1326 udelay(100);
1327
1328 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1329 udelay(10);
1330 }
1331
1332 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1333 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1334 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1335 u32 base_val;
1336
1337 base_val = tp->pci_clock_ctrl;
1338 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1339 CLOCK_CTRL_TXCLK_DISABLE);
1340
b401e9e2
MC		 1341 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1342 CLOCK_CTRL_PWRDOWN_PLL133, 40);
a4e2b347 1343 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f 1344 /* do nothing */
85e94ced 1345 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1346 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1347 u32 newbits1, newbits2;
1348
1349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1350 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1351 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1352 CLOCK_CTRL_TXCLK_DISABLE |
1353 CLOCK_CTRL_ALTCLK);
1354 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1355 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1356 newbits1 = CLOCK_CTRL_625_CORE;
1357 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1358 } else {
1359 newbits1 = CLOCK_CTRL_ALTCLK;
1360 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1361 }
1362
b401e9e2
MC		 1363 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1364 40);
1da177e4 1365
b401e9e2
MC		 1366 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1367 40);
1da177e4
LT		 1368
1369 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1370 u32 newbits3;
1371
1372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1373 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1374 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1375 CLOCK_CTRL_TXCLK_DISABLE |
1376 CLOCK_CTRL_44MHZ_CORE);
1377 } else {
1378 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1379 }
1380
b401e9e2
MC		 1381 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1382 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1383 }
1384 }
1385
6921d201 1386 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
3f7045c1
MC		 1387 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1388 tg3_power_down_phy(tp);
6921d201 1389
1da177e4
LT		 1390 tg3_frob_aux_power(tp);
1391
1392 /* Workaround for unstable PLL clock */
1393 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1394 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1395 u32 val = tr32(0x7d00);
1396
1397 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1398 tw32(0x7d00, val);
6921d201 1399 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1400 int err;
1401
1402 err = tg3_nvram_lock(tp);
1da177e4 1403 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1404 if (!err)
1405 tg3_nvram_unlock(tp);
6921d201 1406 }
1da177e4
LT		 1407 }
1408
bbadf503
MC		 1409 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1410
1da177e4
LT		 1411 /* Finally, set the new power state. */
1412 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1413 udelay(100); /* Delay after power state change */
1da177e4 1414
1da177e4
LT		 1415 return 0;
1416}
1417
1418static void tg3_link_report(struct tg3 *tp)
1419{
1420 if (!netif_carrier_ok(tp->dev)) {
9f88f29f
MC		 1421 if (netif_msg_link(tp))
1422 printk(KERN_INFO PFX "%s: Link is down.\n",
1423 tp->dev->name);
1424 } else if (netif_msg_link(tp)) {
1da177e4
LT		 1425 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1426 tp->dev->name,
1427 (tp->link_config.active_speed == SPEED_1000 ?
1428 1000 :
1429 (tp->link_config.active_speed == SPEED_100 ?
1430 100 : 10)),
1431 (tp->link_config.active_duplex == DUPLEX_FULL ?
1432 "full" : "half"));
1433
1434 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1435 "%s for RX.\n",
1436 tp->dev->name,
1437 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1438 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1439 }
1440}
1441
1442static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1443{
1444 u32 new_tg3_flags = 0;
1445 u32 old_rx_mode = tp->rx_mode;
1446 u32 old_tx_mode = tp->tx_mode;
1447
1448 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1449
1450 /* Convert 1000BaseX flow control bits to 1000BaseT
1451 * bits before resolving flow control.
1452 */
1453 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1454 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1455 ADVERTISE_PAUSE_ASYM);
1456 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1457
1458 if (local_adv & ADVERTISE_1000XPAUSE)
1459 local_adv |= ADVERTISE_PAUSE_CAP;
1460 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1461 local_adv |= ADVERTISE_PAUSE_ASYM;
1462 if (remote_adv & LPA_1000XPAUSE)
1463 remote_adv |= LPA_PAUSE_CAP;
1464 if (remote_adv & LPA_1000XPAUSE_ASYM)
1465 remote_adv |= LPA_PAUSE_ASYM;
1466 }
1467
1da177e4
LT		 1468 if (local_adv & ADVERTISE_PAUSE_CAP) {
1469 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1470 if (remote_adv & LPA_PAUSE_CAP)
1471 new_tg3_flags |=
1472 (TG3_FLAG_RX_PAUSE |
1473 TG3_FLAG_TX_PAUSE);
1474 else if (remote_adv & LPA_PAUSE_ASYM)
1475 new_tg3_flags |=
1476 (TG3_FLAG_RX_PAUSE);
1477 } else {
1478 if (remote_adv & LPA_PAUSE_CAP)
1479 new_tg3_flags |=
1480 (TG3_FLAG_RX_PAUSE |
1481 TG3_FLAG_TX_PAUSE);
1482 }
1483 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1484 if ((remote_adv & LPA_PAUSE_CAP) &&
1485 (remote_adv & LPA_PAUSE_ASYM))
1486 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1487 }
1488
1489 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1490 tp->tg3_flags |= new_tg3_flags;
1491 } else {
1492 new_tg3_flags = tp->tg3_flags;
1493 }
1494
1495 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1496 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1497 else
1498 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1499
1500 if (old_rx_mode != tp->rx_mode) {
1501 tw32_f(MAC_RX_MODE, tp->rx_mode);
1502 }
6aa20a22 1503
1da177e4
LT		 1504 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1505 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1506 else
1507 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1508
1509 if (old_tx_mode != tp->tx_mode) {
1510 tw32_f(MAC_TX_MODE, tp->tx_mode);
1511 }
1512}
1513
1514static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1515{
1516 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1517 case MII_TG3_AUX_STAT_10HALF:
1518 *speed = SPEED_10;
1519 *duplex = DUPLEX_HALF;
1520 break;
1521
1522 case MII_TG3_AUX_STAT_10FULL:
1523 *speed = SPEED_10;
1524 *duplex = DUPLEX_FULL;
1525 break;
1526
1527 case MII_TG3_AUX_STAT_100HALF:
1528 *speed = SPEED_100;
1529 *duplex = DUPLEX_HALF;
1530 break;
1531
1532 case MII_TG3_AUX_STAT_100FULL:
1533 *speed = SPEED_100;
1534 *duplex = DUPLEX_FULL;
1535 break;
1536
1537 case MII_TG3_AUX_STAT_1000HALF:
1538 *speed = SPEED_1000;
1539 *duplex = DUPLEX_HALF;
1540 break;
1541
1542 case MII_TG3_AUX_STAT_1000FULL:
1543 *speed = SPEED_1000;
1544 *duplex = DUPLEX_FULL;
1545 break;
1546
1547 default:
715116a1
MC		 1548 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1549 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1550 SPEED_10;
1551 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1552 DUPLEX_HALF;
1553 break;
1554 }
1da177e4
LT		 1555 *speed = SPEED_INVALID;
1556 *duplex = DUPLEX_INVALID;
1557 break;
1558 };
1559}
1560
1561static void tg3_phy_copper_begin(struct tg3 *tp)
1562{
1563 u32 new_adv;
1564 int i;
1565
1566 if (tp->link_config.phy_is_low_power) {
1567 /* Entering low power mode. Disable gigabit and
1568 * 100baseT advertisements.
1569 */
1570 tg3_writephy(tp, MII_TG3_CTRL, 0);
1571
1572 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1573 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1574 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1575 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1576
1577 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1578 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 1579 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1580 tp->link_config.advertising &=
1581 ~(ADVERTISED_1000baseT_Half |
1582 ADVERTISED_1000baseT_Full);
1583
1584 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1585 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1586 new_adv |= ADVERTISE_10HALF;
1587 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1588 new_adv |= ADVERTISE_10FULL;
1589 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1590 new_adv |= ADVERTISE_100HALF;
1591 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1592 new_adv |= ADVERTISE_100FULL;
1593 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1594
1595 if (tp->link_config.advertising &
1596 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1597 new_adv = 0;
1598 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1599 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1600 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1601 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1602 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1603 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1604 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1605 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1606 MII_TG3_CTRL_ENABLE_AS_MASTER);
1607 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1608 } else {
1609 tg3_writephy(tp, MII_TG3_CTRL, 0);
1610 }
1611 } else {
1612 /* Asking for a specific link mode. */
1613 if (tp->link_config.speed == SPEED_1000) {
1614 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1615 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1616
1617 if (tp->link_config.duplex == DUPLEX_FULL)
1618 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1619 else
1620 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1621 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1622 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1623 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1624 MII_TG3_CTRL_ENABLE_AS_MASTER);
1625 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1626 } else {
1627 tg3_writephy(tp, MII_TG3_CTRL, 0);
1628
1629 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1630 if (tp->link_config.speed == SPEED_100) {
1631 if (tp->link_config.duplex == DUPLEX_FULL)
1632 new_adv |= ADVERTISE_100FULL;
1633 else
1634 new_adv |= ADVERTISE_100HALF;
1635 } else {
1636 if (tp->link_config.duplex == DUPLEX_FULL)
1637 new_adv |= ADVERTISE_10FULL;
1638 else
1639 new_adv |= ADVERTISE_10HALF;
1640 }
1641 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1642 }
1643 }
1644
1645 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1646 tp->link_config.speed != SPEED_INVALID) {
1647 u32 bmcr, orig_bmcr;
1648
1649 tp->link_config.active_speed = tp->link_config.speed;
1650 tp->link_config.active_duplex = tp->link_config.duplex;
1651
1652 bmcr = 0;
1653 switch (tp->link_config.speed) {
1654 default:
1655 case SPEED_10:
1656 break;
1657
1658 case SPEED_100:
1659 bmcr |= BMCR_SPEED100;
1660 break;
1661
1662 case SPEED_1000:
1663 bmcr |= TG3_BMCR_SPEED1000;
1664 break;
1665 };
1666
1667 if (tp->link_config.duplex == DUPLEX_FULL)
1668 bmcr |= BMCR_FULLDPLX;
1669
1670 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1671 (bmcr != orig_bmcr)) {
1672 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1673 for (i = 0; i < 1500; i++) {
1674 u32 tmp;
1675
1676 udelay(10);
1677 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1678 tg3_readphy(tp, MII_BMSR, &tmp))
1679 continue;
1680 if (!(tmp & BMSR_LSTATUS)) {
1681 udelay(40);
1682 break;
1683 }
1684 }
1685 tg3_writephy(tp, MII_BMCR, bmcr);
1686 udelay(40);
1687 }
1688 } else {
1689 tg3_writephy(tp, MII_BMCR,
1690 BMCR_ANENABLE | BMCR_ANRESTART);
1691 }
1692}
1693
1694static int tg3_init_5401phy_dsp(struct tg3 *tp)
1695{
1696 int err;
1697
1698 /* Turn off tap power management. */
1699 /* Set Extended packet length bit */
1700 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1701
1702 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1703 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1704
1705 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1706 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1707
1708 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1709 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1710
1711 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1712 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1713
1714 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1715 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1716
1717 udelay(40);
1718
1719 return err;
1720}
1721
3600d918 1722static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 1723{
3600d918
MC		 1724 u32 adv_reg, all_mask = 0;
1725
1726 if (mask & ADVERTISED_10baseT_Half)
1727 all_mask |= ADVERTISE_10HALF;
1728 if (mask & ADVERTISED_10baseT_Full)
1729 all_mask |= ADVERTISE_10FULL;
1730 if (mask & ADVERTISED_100baseT_Half)
1731 all_mask |= ADVERTISE_100HALF;
1732 if (mask & ADVERTISED_100baseT_Full)
1733 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 1734
1735 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1736 return 0;
1737
1da177e4
LT		 1738 if ((adv_reg & all_mask) != all_mask)
1739 return 0;
1740 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1741 u32 tg3_ctrl;
1742
3600d918
MC		 1743 all_mask = 0;
1744 if (mask & ADVERTISED_1000baseT_Half)
1745 all_mask |= ADVERTISE_1000HALF;
1746 if (mask & ADVERTISED_1000baseT_Full)
1747 all_mask |= ADVERTISE_1000FULL;
1748
1da177e4
LT		 1749 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1750 return 0;
1751
1da177e4
LT		 1752 if ((tg3_ctrl & all_mask) != all_mask)
1753 return 0;
1754 }
1755 return 1;
1756}
1757
1758static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1759{
1760 int current_link_up;
1761 u32 bmsr, dummy;
1762 u16 current_speed;
1763 u8 current_duplex;
1764 int i, err;
1765
1766 tw32(MAC_EVENT, 0);
1767
1768 tw32_f(MAC_STATUS,
1769 (MAC_STATUS_SYNC_CHANGED |
1770 MAC_STATUS_CFG_CHANGED |
1771 MAC_STATUS_MI_COMPLETION |
1772 MAC_STATUS_LNKSTATE_CHANGED));
1773 udelay(40);
1774
1775 tp->mi_mode = MAC_MI_MODE_BASE;
1776 tw32_f(MAC_MI_MODE, tp->mi_mode);
1777 udelay(80);
1778
1779 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1780
1781 /* Some third-party PHYs need to be reset on link going
1782 * down.
1783 */
1784 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1785 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1786 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1787 netif_carrier_ok(tp->dev)) {
1788 tg3_readphy(tp, MII_BMSR, &bmsr);
1789 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1790 !(bmsr & BMSR_LSTATUS))
1791 force_reset = 1;
1792 }
1793 if (force_reset)
1794 tg3_phy_reset(tp);
1795
1796 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1797 tg3_readphy(tp, MII_BMSR, &bmsr);
1798 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1799 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1800 bmsr = 0;
1801
1802 if (!(bmsr & BMSR_LSTATUS)) {
1803 err = tg3_init_5401phy_dsp(tp);
1804 if (err)
1805 return err;
1806
1807 tg3_readphy(tp, MII_BMSR, &bmsr);
1808 for (i = 0; i < 1000; i++) {
1809 udelay(10);
1810 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1811 (bmsr & BMSR_LSTATUS)) {
1812 udelay(40);
1813 break;
1814 }
1815 }
1816
1817 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1818 !(bmsr & BMSR_LSTATUS) &&
1819 tp->link_config.active_speed == SPEED_1000) {
1820 err = tg3_phy_reset(tp);
1821 if (!err)
1822 err = tg3_init_5401phy_dsp(tp);
1823 if (err)
1824 return err;
1825 }
1826 }
1827 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1828 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1829 /* 5701 {A0,B0} CRC bug workaround */
1830 tg3_writephy(tp, 0x15, 0x0a75);
1831 tg3_writephy(tp, 0x1c, 0x8c68);
1832 tg3_writephy(tp, 0x1c, 0x8d68);
1833 tg3_writephy(tp, 0x1c, 0x8c68);
1834 }
1835
1836 /* Clear pending interrupts... */
1837 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1838 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1839
1840 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1841 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 1842 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 1843 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1844
1845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1847 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1848 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1849 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1850 else
1851 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1852 }
1853
1854 current_link_up = 0;
1855 current_speed = SPEED_INVALID;
1856 current_duplex = DUPLEX_INVALID;
1857
1858 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1859 u32 val;
1860
1861 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1862 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1863 if (!(val & (1 << 10))) {
1864 val |= (1 << 10);
1865 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1866 goto relink;
1867 }
1868 }
1869
1870 bmsr = 0;
1871 for (i = 0; i < 100; i++) {
1872 tg3_readphy(tp, MII_BMSR, &bmsr);
1873 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1874 (bmsr & BMSR_LSTATUS))
1875 break;
1876 udelay(40);
1877 }
1878
1879 if (bmsr & BMSR_LSTATUS) {
1880 u32 aux_stat, bmcr;
1881
1882 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1883 for (i = 0; i < 2000; i++) {
1884 udelay(10);
1885 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1886 aux_stat)
1887 break;
1888 }
1889
1890 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1891 &current_speed,
1892 &current_duplex);
1893
1894 bmcr = 0;
1895 for (i = 0; i < 200; i++) {
1896 tg3_readphy(tp, MII_BMCR, &bmcr);
1897 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1898 continue;
1899 if (bmcr && bmcr != 0x7fff)
1900 break;
1901 udelay(10);
1902 }
1903
1904 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1905 if (bmcr & BMCR_ANENABLE) {
1906 current_link_up = 1;
1907
1908 /* Force autoneg restart if we are exiting
1909 * low power mode.
1910 */
3600d918
MC		 1911 if (!tg3_copper_is_advertising_all(tp,
1912 tp->link_config.advertising))
1da177e4
LT		 1913 current_link_up = 0;
1914 } else {
1915 current_link_up = 0;
1916 }
1917 } else {
1918 if (!(bmcr & BMCR_ANENABLE) &&
1919 tp->link_config.speed == current_speed &&
1920 tp->link_config.duplex == current_duplex) {
1921 current_link_up = 1;
1922 } else {
1923 current_link_up = 0;
1924 }
1925 }
1926
1927 tp->link_config.active_speed = current_speed;
1928 tp->link_config.active_duplex = current_duplex;
1929 }
1930
1931 if (current_link_up == 1 &&
1932 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1933 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1934 u32 local_adv, remote_adv;
1935
1936 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1937 local_adv = 0;
1938 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1939
1940 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1941 remote_adv = 0;
1942
1943 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1944
1945 /* If we are not advertising full pause capability,
1946 * something is wrong. Bring the link down and reconfigure.
1947 */
1948 if (local_adv != ADVERTISE_PAUSE_CAP) {
1949 current_link_up = 0;
1950 } else {
1951 tg3_setup_flow_control(tp, local_adv, remote_adv);
1952 }
1953 }
1954relink:
6921d201 1955 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 1956 u32 tmp;
1957
1958 tg3_phy_copper_begin(tp);
1959
1960 tg3_readphy(tp, MII_BMSR, &tmp);
1961 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1962 (tmp & BMSR_LSTATUS))
1963 current_link_up = 1;
1964 }
1965
1966 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1967 if (current_link_up == 1) {
1968 if (tp->link_config.active_speed == SPEED_100 ||
1969 tp->link_config.active_speed == SPEED_10)
1970 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1971 else
1972 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1973 } else
1974 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1975
1976 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1977 if (tp->link_config.active_duplex == DUPLEX_HALF)
1978 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1979
1980 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1982 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1983 (current_link_up == 1 &&
1984 tp->link_config.active_speed == SPEED_10))
1985 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1986 } else {
1987 if (current_link_up == 1)
1988 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1989 }
1990
1991 /* ??? Without this setting Netgear GA302T PHY does not
1992 * ??? send/receive packets...
1993 */
1994 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1995 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1996 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1997 tw32_f(MAC_MI_MODE, tp->mi_mode);
1998 udelay(80);
1999 }
2000
2001 tw32_f(MAC_MODE, tp->mac_mode);
2002 udelay(40);
2003
2004 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2005 /* Polled via timer. */
2006 tw32_f(MAC_EVENT, 0);
2007 } else {
2008 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2009 }
2010 udelay(40);
2011
2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2013 current_link_up == 1 &&
2014 tp->link_config.active_speed == SPEED_1000 &&
2015 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2016 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2017 udelay(120);
2018 tw32_f(MAC_STATUS,
2019 (MAC_STATUS_SYNC_CHANGED |
2020 MAC_STATUS_CFG_CHANGED));
2021 udelay(40);
2022 tg3_write_mem(tp,
2023 NIC_SRAM_FIRMWARE_MBOX,
2024 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2025 }
2026
2027 if (current_link_up != netif_carrier_ok(tp->dev)) {
2028 if (current_link_up)
2029 netif_carrier_on(tp->dev);
2030 else
2031 netif_carrier_off(tp->dev);
2032 tg3_link_report(tp);
2033 }
2034
2035 return 0;
2036}
2037
2038struct tg3_fiber_aneginfo {
2039 int state;
2040#define ANEG_STATE_UNKNOWN 0
2041#define ANEG_STATE_AN_ENABLE 1
2042#define ANEG_STATE_RESTART_INIT 2
2043#define ANEG_STATE_RESTART 3
2044#define ANEG_STATE_DISABLE_LINK_OK 4
2045#define ANEG_STATE_ABILITY_DETECT_INIT 5
2046#define ANEG_STATE_ABILITY_DETECT 6
2047#define ANEG_STATE_ACK_DETECT_INIT 7
2048#define ANEG_STATE_ACK_DETECT 8
2049#define ANEG_STATE_COMPLETE_ACK_INIT 9
2050#define ANEG_STATE_COMPLETE_ACK 10
2051#define ANEG_STATE_IDLE_DETECT_INIT 11
2052#define ANEG_STATE_IDLE_DETECT 12
2053#define ANEG_STATE_LINK_OK 13
2054#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2055#define ANEG_STATE_NEXT_PAGE_WAIT 15
2056
2057 u32 flags;
2058#define MR_AN_ENABLE 0x00000001
2059#define MR_RESTART_AN 0x00000002
2060#define MR_AN_COMPLETE 0x00000004
2061#define MR_PAGE_RX 0x00000008
2062#define MR_NP_LOADED 0x00000010
2063#define MR_TOGGLE_TX 0x00000020
2064#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2065#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2066#define MR_LP_ADV_SYM_PAUSE 0x00000100
2067#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2068#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2069#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2070#define MR_LP_ADV_NEXT_PAGE 0x00001000
2071#define MR_TOGGLE_RX 0x00002000
2072#define MR_NP_RX 0x00004000
2073
2074#define MR_LINK_OK 0x80000000
2075
2076 unsigned long link_time, cur_time;
2077
2078 u32 ability_match_cfg;
2079 int ability_match_count;
2080
2081 char ability_match, idle_match, ack_match;
2082
2083 u32 txconfig, rxconfig;
2084#define ANEG_CFG_NP 0x00000080
2085#define ANEG_CFG_ACK 0x00000040
2086#define ANEG_CFG_RF2 0x00000020
2087#define ANEG_CFG_RF1 0x00000010
2088#define ANEG_CFG_PS2 0x00000001
2089#define ANEG_CFG_PS1 0x00008000
2090#define ANEG_CFG_HD 0x00004000
2091#define ANEG_CFG_FD 0x00002000
2092#define ANEG_CFG_INVAL 0x00001f06
2093
2094};
2095#define ANEG_OK 0
2096#define ANEG_DONE 1
2097#define ANEG_TIMER_ENAB 2
2098#define ANEG_FAILED -1
2099
2100#define ANEG_STATE_SETTLE_TIME 10000
2101
2102static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2103 struct tg3_fiber_aneginfo *ap)
2104{
2105 unsigned long delta;
2106 u32 rx_cfg_reg;
2107 int ret;
2108
2109 if (ap->state == ANEG_STATE_UNKNOWN) {
2110 ap->rxconfig = 0;
2111 ap->link_time = 0;
2112 ap->cur_time = 0;
2113 ap->ability_match_cfg = 0;
2114 ap->ability_match_count = 0;
2115 ap->ability_match = 0;
2116 ap->idle_match = 0;
2117 ap->ack_match = 0;
2118 }
2119 ap->cur_time++;
2120
2121 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2122 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2123
2124 if (rx_cfg_reg != ap->ability_match_cfg) {
2125 ap->ability_match_cfg = rx_cfg_reg;
2126 ap->ability_match = 0;
2127 ap->ability_match_count = 0;
2128 } else {
2129 if (++ap->ability_match_count > 1) {
2130 ap->ability_match = 1;
2131 ap->ability_match_cfg = rx_cfg_reg;
2132 }
2133 }
2134 if (rx_cfg_reg & ANEG_CFG_ACK)
2135 ap->ack_match = 1;
2136 else
2137 ap->ack_match = 0;
2138
2139 ap->idle_match = 0;
2140 } else {
2141 ap->idle_match = 1;
2142 ap->ability_match_cfg = 0;
2143 ap->ability_match_count = 0;
2144 ap->ability_match = 0;
2145 ap->ack_match = 0;
2146
2147 rx_cfg_reg = 0;
2148 }
2149
2150 ap->rxconfig = rx_cfg_reg;
2151 ret = ANEG_OK;
2152
2153 switch(ap->state) {
2154 case ANEG_STATE_UNKNOWN:
2155 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2156 ap->state = ANEG_STATE_AN_ENABLE;
2157
2158 /* fallthru */
2159 case ANEG_STATE_AN_ENABLE:
2160 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2161 if (ap->flags & MR_AN_ENABLE) {
2162 ap->link_time = 0;
2163 ap->cur_time = 0;
2164 ap->ability_match_cfg = 0;
2165 ap->ability_match_count = 0;
2166 ap->ability_match = 0;
2167 ap->idle_match = 0;
2168 ap->ack_match = 0;
2169
2170 ap->state = ANEG_STATE_RESTART_INIT;
2171 } else {
2172 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2173 }
2174 break;
2175
2176 case ANEG_STATE_RESTART_INIT:
2177 ap->link_time = ap->cur_time;
2178 ap->flags &= ~(MR_NP_LOADED);
2179 ap->txconfig = 0;
2180 tw32(MAC_TX_AUTO_NEG, 0);
2181 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2182 tw32_f(MAC_MODE, tp->mac_mode);
2183 udelay(40);
2184
2185 ret = ANEG_TIMER_ENAB;
2186 ap->state = ANEG_STATE_RESTART;
2187
2188 /* fallthru */
2189 case ANEG_STATE_RESTART:
2190 delta = ap->cur_time - ap->link_time;
2191 if (delta > ANEG_STATE_SETTLE_TIME) {
2192 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2193 } else {
2194 ret = ANEG_TIMER_ENAB;
2195 }
2196 break;
2197
2198 case ANEG_STATE_DISABLE_LINK_OK:
2199 ret = ANEG_DONE;
2200 break;
2201
2202 case ANEG_STATE_ABILITY_DETECT_INIT:
2203 ap->flags &= ~(MR_TOGGLE_TX);
2204 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2205 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2206 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2207 tw32_f(MAC_MODE, tp->mac_mode);
2208 udelay(40);
2209
2210 ap->state = ANEG_STATE_ABILITY_DETECT;
2211 break;
2212
2213 case ANEG_STATE_ABILITY_DETECT:
2214 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2215 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2216 }
2217 break;
2218
2219 case ANEG_STATE_ACK_DETECT_INIT:
2220 ap->txconfig |= ANEG_CFG_ACK;
2221 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2222 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2223 tw32_f(MAC_MODE, tp->mac_mode);
2224 udelay(40);
2225
2226 ap->state = ANEG_STATE_ACK_DETECT;
2227
2228 /* fallthru */
2229 case ANEG_STATE_ACK_DETECT:
2230 if (ap->ack_match != 0) {
2231 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2232 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2233 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2234 } else {
2235 ap->state = ANEG_STATE_AN_ENABLE;
2236 }
2237 } else if (ap->ability_match != 0 &&
2238 ap->rxconfig == 0) {
2239 ap->state = ANEG_STATE_AN_ENABLE;
2240 }
2241 break;
2242
2243 case ANEG_STATE_COMPLETE_ACK_INIT:
2244 if (ap->rxconfig & ANEG_CFG_INVAL) {
2245 ret = ANEG_FAILED;
2246 break;
2247 }
2248 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2249 MR_LP_ADV_HALF_DUPLEX |
2250 MR_LP_ADV_SYM_PAUSE |
2251 MR_LP_ADV_ASYM_PAUSE |
2252 MR_LP_ADV_REMOTE_FAULT1 |
2253 MR_LP_ADV_REMOTE_FAULT2 |
2254 MR_LP_ADV_NEXT_PAGE |
2255 MR_TOGGLE_RX |
2256 MR_NP_RX);
2257 if (ap->rxconfig & ANEG_CFG_FD)
2258 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2259 if (ap->rxconfig & ANEG_CFG_HD)
2260 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2261 if (ap->rxconfig & ANEG_CFG_PS1)
2262 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2263 if (ap->rxconfig & ANEG_CFG_PS2)
2264 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2265 if (ap->rxconfig & ANEG_CFG_RF1)
2266 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2267 if (ap->rxconfig & ANEG_CFG_RF2)
2268 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2269 if (ap->rxconfig & ANEG_CFG_NP)
2270 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2271
2272 ap->link_time = ap->cur_time;
2273
2274 ap->flags ^= (MR_TOGGLE_TX);
2275 if (ap->rxconfig & 0x0008)
2276 ap->flags |= MR_TOGGLE_RX;
2277 if (ap->rxconfig & ANEG_CFG_NP)
2278 ap->flags |= MR_NP_RX;
2279 ap->flags |= MR_PAGE_RX;
2280
2281 ap->state = ANEG_STATE_COMPLETE_ACK;
2282 ret = ANEG_TIMER_ENAB;
2283 break;
2284
2285 case ANEG_STATE_COMPLETE_ACK:
2286 if (ap->ability_match != 0 &&
2287 ap->rxconfig == 0) {
2288 ap->state = ANEG_STATE_AN_ENABLE;
2289 break;
2290 }
2291 delta = ap->cur_time - ap->link_time;
2292 if (delta > ANEG_STATE_SETTLE_TIME) {
2293 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2294 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2295 } else {
2296 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2297 !(ap->flags & MR_NP_RX)) {
2298 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2299 } else {
2300 ret = ANEG_FAILED;
2301 }
2302 }
2303 }
2304 break;
2305
2306 case ANEG_STATE_IDLE_DETECT_INIT:
2307 ap->link_time = ap->cur_time;
2308 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2309 tw32_f(MAC_MODE, tp->mac_mode);
2310 udelay(40);
2311
2312 ap->state = ANEG_STATE_IDLE_DETECT;
2313 ret = ANEG_TIMER_ENAB;
2314 break;
2315
2316 case ANEG_STATE_IDLE_DETECT:
2317 if (ap->ability_match != 0 &&
2318 ap->rxconfig == 0) {
2319 ap->state = ANEG_STATE_AN_ENABLE;
2320 break;
2321 }
2322 delta = ap->cur_time - ap->link_time;
2323 if (delta > ANEG_STATE_SETTLE_TIME) {
2324 /* XXX another gem from the Broadcom driver :( */
2325 ap->state = ANEG_STATE_LINK_OK;
2326 }
2327 break;
2328
2329 case ANEG_STATE_LINK_OK:
2330 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2331 ret = ANEG_DONE;
2332 break;
2333
2334 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2335 /* ??? unimplemented */
2336 break;
2337
2338 case ANEG_STATE_NEXT_PAGE_WAIT:
2339 /* ??? unimplemented */
2340 break;
2341
2342 default:
2343 ret = ANEG_FAILED;
2344 break;
2345 };
2346
2347 return ret;
2348}
2349
2350static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2351{
2352 int res = 0;
2353 struct tg3_fiber_aneginfo aninfo;
2354 int status = ANEG_FAILED;
2355 unsigned int tick;
2356 u32 tmp;
2357
2358 tw32_f(MAC_TX_AUTO_NEG, 0);
2359
2360 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2361 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2362 udelay(40);
2363
2364 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2365 udelay(40);
2366
2367 memset(&aninfo, 0, sizeof(aninfo));
2368 aninfo.flags |= MR_AN_ENABLE;
2369 aninfo.state = ANEG_STATE_UNKNOWN;
2370 aninfo.cur_time = 0;
2371 tick = 0;
2372 while (++tick < 195000) {
2373 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2374 if (status == ANEG_DONE || status == ANEG_FAILED)
2375 break;
2376
2377 udelay(1);
2378 }
2379
2380 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2381 tw32_f(MAC_MODE, tp->mac_mode);
2382 udelay(40);
2383
2384 *flags = aninfo.flags;
2385
2386 if (status == ANEG_DONE &&
2387 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2388 MR_LP_ADV_FULL_DUPLEX)))
2389 res = 1;
2390
2391 return res;
2392}
2393
2394static void tg3_init_bcm8002(struct tg3 *tp)
2395{
2396 u32 mac_status = tr32(MAC_STATUS);
2397 int i;
2398
2399 /* Reset when initting first time or we have a link. */
2400 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2401 !(mac_status & MAC_STATUS_PCS_SYNCED))
2402 return;
2403
2404 /* Set PLL lock range. */
2405 tg3_writephy(tp, 0x16, 0x8007);
2406
2407 /* SW reset */
2408 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2409
2410 /* Wait for reset to complete. */
2411 /* XXX schedule_timeout() ... */
2412 for (i = 0; i < 500; i++)
2413 udelay(10);
2414
2415 /* Config mode; select PMA/Ch 1 regs. */
2416 tg3_writephy(tp, 0x10, 0x8411);
2417
2418 /* Enable auto-lock and comdet, select txclk for tx. */
2419 tg3_writephy(tp, 0x11, 0x0a10);
2420
2421 tg3_writephy(tp, 0x18, 0x00a0);
2422 tg3_writephy(tp, 0x16, 0x41ff);
2423
2424 /* Assert and deassert POR. */
2425 tg3_writephy(tp, 0x13, 0x0400);
2426 udelay(40);
2427 tg3_writephy(tp, 0x13, 0x0000);
2428
2429 tg3_writephy(tp, 0x11, 0x0a50);
2430 udelay(40);
2431 tg3_writephy(tp, 0x11, 0x0a10);
2432
2433 /* Wait for signal to stabilize */
2434 /* XXX schedule_timeout() ... */
2435 for (i = 0; i < 15000; i++)
2436 udelay(10);
2437
2438 /* Deselect the channel register so we can read the PHYID
2439 * later.
2440 */
2441 tg3_writephy(tp, 0x10, 0x8011);
2442}
2443
2444static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2445{
2446 u32 sg_dig_ctrl, sg_dig_status;
2447 u32 serdes_cfg, expected_sg_dig_ctrl;
2448 int workaround, port_a;
2449 int current_link_up;
2450
2451 serdes_cfg = 0;
2452 expected_sg_dig_ctrl = 0;
2453 workaround = 0;
2454 port_a = 1;
2455 current_link_up = 0;
2456
2457 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2458 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2459 workaround = 1;
2460 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2461 port_a = 0;
2462
2463 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2464 /* preserve bits 20-23 for voltage regulator */
2465 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2466 }
2467
2468 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2469
2470 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2471 if (sg_dig_ctrl & (1 << 31)) {
2472 if (workaround) {
2473 u32 val = serdes_cfg;
2474
2475 if (port_a)
2476 val |= 0xc010000;
2477 else
2478 val |= 0x4010000;
2479 tw32_f(MAC_SERDES_CFG, val);
2480 }
2481 tw32_f(SG_DIG_CTRL, 0x01388400);
2482 }
2483 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2484 tg3_setup_flow_control(tp, 0, 0);
2485 current_link_up = 1;
2486 }
2487 goto out;
2488 }
2489
2490 /* Want auto-negotiation. */
2491 expected_sg_dig_ctrl = 0x81388400;
2492
2493 /* Pause capability */
2494 expected_sg_dig_ctrl |= (1 << 11);
2495
2496 /* Asymettric pause */
2497 expected_sg_dig_ctrl |= (1 << 12);
2498
2499 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 2500 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2501 tp->serdes_counter &&
2502 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2503 MAC_STATUS_RCVD_CFG)) ==
2504 MAC_STATUS_PCS_SYNCED)) {
2505 tp->serdes_counter--;
2506 current_link_up = 1;
2507 goto out;
2508 }
2509restart_autoneg:
1da177e4
LT		 2510 if (workaround)
2511 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2512 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2513 udelay(5);
2514 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2515
3d3ebe74
MC		 2516 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2517 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2518 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2519 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 2520 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 2521 mac_status = tr32(MAC_STATUS);
2522
2523 if ((sg_dig_status & (1 << 1)) &&
2524 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2525 u32 local_adv, remote_adv;
2526
2527 local_adv = ADVERTISE_PAUSE_CAP;
2528 remote_adv = 0;
2529 if (sg_dig_status & (1 << 19))
2530 remote_adv |= LPA_PAUSE_CAP;
2531 if (sg_dig_status & (1 << 20))
2532 remote_adv |= LPA_PAUSE_ASYM;
2533
2534 tg3_setup_flow_control(tp, local_adv, remote_adv);
2535 current_link_up = 1;
3d3ebe74
MC		 2536 tp->serdes_counter = 0;
2537 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4 2538 } else if (!(sg_dig_status & (1 << 1))) {
3d3ebe74
MC		 2539 if (tp->serdes_counter)
2540 tp->serdes_counter--;
1da177e4
LT		 2541 else {
2542 if (workaround) {
2543 u32 val = serdes_cfg;
2544
2545 if (port_a)
2546 val |= 0xc010000;
2547 else
2548 val |= 0x4010000;
2549
2550 tw32_f(MAC_SERDES_CFG, val);
2551 }
2552
2553 tw32_f(SG_DIG_CTRL, 0x01388400);
2554 udelay(40);
2555
2556 /* Link parallel detection - link is up */
2557 /* only if we have PCS_SYNC and not */
2558 /* receiving config code words */
2559 mac_status = tr32(MAC_STATUS);
2560 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2561 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2562 tg3_setup_flow_control(tp, 0, 0);
2563 current_link_up = 1;
3d3ebe74
MC		 2564 tp->tg3_flags2 |=
2565 TG3_FLG2_PARALLEL_DETECT;
2566 tp->serdes_counter =
2567 SERDES_PARALLEL_DET_TIMEOUT;
2568 } else
2569 goto restart_autoneg;
1da177e4
LT		 2570 }
2571 }
3d3ebe74
MC		 2572 } else {
2573 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2574 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2575 }
2576
2577out:
2578 return current_link_up;
2579}
2580
2581static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2582{
2583 int current_link_up = 0;
2584
2585 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2586 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2587 goto out;
2588 }
2589
2590 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2591 u32 flags;
2592 int i;
6aa20a22 2593
1da177e4
LT		 2594 if (fiber_autoneg(tp, &flags)) {
2595 u32 local_adv, remote_adv;
2596
2597 local_adv = ADVERTISE_PAUSE_CAP;
2598 remote_adv = 0;
2599 if (flags & MR_LP_ADV_SYM_PAUSE)
2600 remote_adv |= LPA_PAUSE_CAP;
2601 if (flags & MR_LP_ADV_ASYM_PAUSE)
2602 remote_adv |= LPA_PAUSE_ASYM;
2603
2604 tg3_setup_flow_control(tp, local_adv, remote_adv);
2605
2606 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2607 current_link_up = 1;
2608 }
2609 for (i = 0; i < 30; i++) {
2610 udelay(20);
2611 tw32_f(MAC_STATUS,
2612 (MAC_STATUS_SYNC_CHANGED |
2613 MAC_STATUS_CFG_CHANGED));
2614 udelay(40);
2615 if ((tr32(MAC_STATUS) &
2616 (MAC_STATUS_SYNC_CHANGED |
2617 MAC_STATUS_CFG_CHANGED)) == 0)
2618 break;
2619 }
2620
2621 mac_status = tr32(MAC_STATUS);
2622 if (current_link_up == 0 &&
2623 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2624 !(mac_status & MAC_STATUS_RCVD_CFG))
2625 current_link_up = 1;
2626 } else {
2627 /* Forcing 1000FD link up. */
2628 current_link_up = 1;
2629 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2630
2631 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2632 udelay(40);
2633 }
2634
2635out:
2636 return current_link_up;
2637}
2638
2639static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2640{
2641 u32 orig_pause_cfg;
2642 u16 orig_active_speed;
2643 u8 orig_active_duplex;
2644 u32 mac_status;
2645 int current_link_up;
2646 int i;
2647
2648 orig_pause_cfg =
2649 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2650 TG3_FLAG_TX_PAUSE));
2651 orig_active_speed = tp->link_config.active_speed;
2652 orig_active_duplex = tp->link_config.active_duplex;
2653
2654 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2655 netif_carrier_ok(tp->dev) &&
2656 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2657 mac_status = tr32(MAC_STATUS);
2658 mac_status &= (MAC_STATUS_PCS_SYNCED |
2659 MAC_STATUS_SIGNAL_DET |
2660 MAC_STATUS_CFG_CHANGED |
2661 MAC_STATUS_RCVD_CFG);
2662 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2663 MAC_STATUS_SIGNAL_DET)) {
2664 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2665 MAC_STATUS_CFG_CHANGED));
2666 return 0;
2667 }
2668 }
2669
2670 tw32_f(MAC_TX_AUTO_NEG, 0);
2671
2672 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2673 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2674 tw32_f(MAC_MODE, tp->mac_mode);
2675 udelay(40);
2676
2677 if (tp->phy_id == PHY_ID_BCM8002)
2678 tg3_init_bcm8002(tp);
2679
2680 /* Enable link change event even when serdes polling. */
2681 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2682 udelay(40);
2683
2684 current_link_up = 0;
2685 mac_status = tr32(MAC_STATUS);
2686
2687 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2688 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2689 else
2690 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2691
2692 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2693 tw32_f(MAC_MODE, tp->mac_mode);
2694 udelay(40);
2695
2696 tp->hw_status->status =
2697 (SD_STATUS_UPDATED |
2698 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2699
2700 for (i = 0; i < 100; i++) {
2701 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2702 MAC_STATUS_CFG_CHANGED));
2703 udelay(5);
2704 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 2705 MAC_STATUS_CFG_CHANGED |
2706 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 2707 break;
2708 }
2709
2710 mac_status = tr32(MAC_STATUS);
2711 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2712 current_link_up = 0;
3d3ebe74
MC		 2713 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2714 tp->serdes_counter == 0) {
1da177e4
LT		 2715 tw32_f(MAC_MODE, (tp->mac_mode |
2716 MAC_MODE_SEND_CONFIGS));
2717 udelay(1);
2718 tw32_f(MAC_MODE, tp->mac_mode);
2719 }
2720 }
2721
2722 if (current_link_up == 1) {
2723 tp->link_config.active_speed = SPEED_1000;
2724 tp->link_config.active_duplex = DUPLEX_FULL;
2725 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2726 LED_CTRL_LNKLED_OVERRIDE |
2727 LED_CTRL_1000MBPS_ON));
2728 } else {
2729 tp->link_config.active_speed = SPEED_INVALID;
2730 tp->link_config.active_duplex = DUPLEX_INVALID;
2731 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2732 LED_CTRL_LNKLED_OVERRIDE |
2733 LED_CTRL_TRAFFIC_OVERRIDE));
2734 }
2735
2736 if (current_link_up != netif_carrier_ok(tp->dev)) {
2737 if (current_link_up)
2738 netif_carrier_on(tp->dev);
2739 else
2740 netif_carrier_off(tp->dev);
2741 tg3_link_report(tp);
2742 } else {
2743 u32 now_pause_cfg =
2744 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2745 TG3_FLAG_TX_PAUSE);
2746 if (orig_pause_cfg != now_pause_cfg ||
2747 orig_active_speed != tp->link_config.active_speed ||
2748 orig_active_duplex != tp->link_config.active_duplex)
2749 tg3_link_report(tp);
2750 }
2751
2752 return 0;
2753}
2754
747e8f8b
MC		 2755static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2756{
2757 int current_link_up, err = 0;
2758 u32 bmsr, bmcr;
2759 u16 current_speed;
2760 u8 current_duplex;
2761
2762 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2763 tw32_f(MAC_MODE, tp->mac_mode);
2764 udelay(40);
2765
2766 tw32(MAC_EVENT, 0);
2767
2768 tw32_f(MAC_STATUS,
2769 (MAC_STATUS_SYNC_CHANGED |
2770 MAC_STATUS_CFG_CHANGED |
2771 MAC_STATUS_MI_COMPLETION |
2772 MAC_STATUS_LNKSTATE_CHANGED));
2773 udelay(40);
2774
2775 if (force_reset)
2776 tg3_phy_reset(tp);
2777
2778 current_link_up = 0;
2779 current_speed = SPEED_INVALID;
2780 current_duplex = DUPLEX_INVALID;
2781
2782 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2783 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2785 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2786 bmsr |= BMSR_LSTATUS;
2787 else
2788 bmsr &= ~BMSR_LSTATUS;
2789 }
747e8f8b
MC		 2790
2791 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2792
2793 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2794 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2795 /* do nothing, just check for link up at the end */
2796 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2797 u32 adv, new_adv;
2798
2799 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2800 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2801 ADVERTISE_1000XPAUSE |
2802 ADVERTISE_1000XPSE_ASYM |
2803 ADVERTISE_SLCT);
2804
2805 /* Always advertise symmetric PAUSE just like copper */
2806 new_adv |= ADVERTISE_1000XPAUSE;
2807
2808 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2809 new_adv |= ADVERTISE_1000XHALF;
2810 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2811 new_adv |= ADVERTISE_1000XFULL;
2812
2813 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2814 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2815 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2816 tg3_writephy(tp, MII_BMCR, bmcr);
2817
2818 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 2819 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 2820 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2821
2822 return err;
2823 }
2824 } else {
2825 u32 new_bmcr;
2826
2827 bmcr &= ~BMCR_SPEED1000;
2828 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2829
2830 if (tp->link_config.duplex == DUPLEX_FULL)
2831 new_bmcr |= BMCR_FULLDPLX;
2832
2833 if (new_bmcr != bmcr) {
2834 /* BMCR_SPEED1000 is a reserved bit that needs
2835 * to be set on write.
2836 */
2837 new_bmcr |= BMCR_SPEED1000;
2838
2839 /* Force a linkdown */
2840 if (netif_carrier_ok(tp->dev)) {
2841 u32 adv;
2842
2843 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2844 adv &= ~(ADVERTISE_1000XFULL |
2845 ADVERTISE_1000XHALF |
2846 ADVERTISE_SLCT);
2847 tg3_writephy(tp, MII_ADVERTISE, adv);
2848 tg3_writephy(tp, MII_BMCR, bmcr |
2849 BMCR_ANRESTART |
2850 BMCR_ANENABLE);
2851 udelay(10);
2852 netif_carrier_off(tp->dev);
2853 }
2854 tg3_writephy(tp, MII_BMCR, new_bmcr);
2855 bmcr = new_bmcr;
2856 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2857 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2858 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2859 ASIC_REV_5714) {
2860 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2861 bmsr |= BMSR_LSTATUS;
2862 else
2863 bmsr &= ~BMSR_LSTATUS;
2864 }
747e8f8b
MC		 2865 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2866 }
2867 }
2868
2869 if (bmsr & BMSR_LSTATUS) {
2870 current_speed = SPEED_1000;
2871 current_link_up = 1;
2872 if (bmcr & BMCR_FULLDPLX)
2873 current_duplex = DUPLEX_FULL;
2874 else
2875 current_duplex = DUPLEX_HALF;
2876
2877 if (bmcr & BMCR_ANENABLE) {
2878 u32 local_adv, remote_adv, common;
2879
2880 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2881 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2882 common = local_adv & remote_adv;
2883 if (common & (ADVERTISE_1000XHALF |
2884 ADVERTISE_1000XFULL)) {
2885 if (common & ADVERTISE_1000XFULL)
2886 current_duplex = DUPLEX_FULL;
2887 else
2888 current_duplex = DUPLEX_HALF;
2889
2890 tg3_setup_flow_control(tp, local_adv,
2891 remote_adv);
2892 }
2893 else
2894 current_link_up = 0;
2895 }
2896 }
2897
2898 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2899 if (tp->link_config.active_duplex == DUPLEX_HALF)
2900 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2901
2902 tw32_f(MAC_MODE, tp->mac_mode);
2903 udelay(40);
2904
2905 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2906
2907 tp->link_config.active_speed = current_speed;
2908 tp->link_config.active_duplex = current_duplex;
2909
2910 if (current_link_up != netif_carrier_ok(tp->dev)) {
2911 if (current_link_up)
2912 netif_carrier_on(tp->dev);
2913 else {
2914 netif_carrier_off(tp->dev);
2915 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2916 }
2917 tg3_link_report(tp);
2918 }
2919 return err;
2920}
2921
2922static void tg3_serdes_parallel_detect(struct tg3 *tp)
2923{
3d3ebe74 2924 if (tp->serdes_counter) {
747e8f8b 2925 /* Give autoneg time to complete. */
3d3ebe74 2926 tp->serdes_counter--;
747e8f8b
MC		 2927 return;
2928 }
2929 if (!netif_carrier_ok(tp->dev) &&
2930 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2931 u32 bmcr;
2932
2933 tg3_readphy(tp, MII_BMCR, &bmcr);
2934 if (bmcr & BMCR_ANENABLE) {
2935 u32 phy1, phy2;
2936
2937 /* Select shadow register 0x1f */
2938 tg3_writephy(tp, 0x1c, 0x7c00);
2939 tg3_readphy(tp, 0x1c, &phy1);
2940
2941 /* Select expansion interrupt status register */
2942 tg3_writephy(tp, 0x17, 0x0f01);
2943 tg3_readphy(tp, 0x15, &phy2);
2944 tg3_readphy(tp, 0x15, &phy2);
2945
2946 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2947 /* We have signal detect and not receiving
2948 * config code words, link is up by parallel
2949 * detection.
2950 */
2951
2952 bmcr &= ~BMCR_ANENABLE;
2953 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2954 tg3_writephy(tp, MII_BMCR, bmcr);
2955 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2956 }
2957 }
2958 }
2959 else if (netif_carrier_ok(tp->dev) &&
2960 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2961 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2962 u32 phy2;
2963
2964 /* Select expansion interrupt status register */
2965 tg3_writephy(tp, 0x17, 0x0f01);
2966 tg3_readphy(tp, 0x15, &phy2);
2967 if (phy2 & 0x20) {
2968 u32 bmcr;
2969
2970 /* Config code words received, turn on autoneg. */
2971 tg3_readphy(tp, MII_BMCR, &bmcr);
2972 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2973
2974 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2975
2976 }
2977 }
2978}
2979
1da177e4
LT		 2980static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2981{
2982 int err;
2983
2984 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2985 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2986 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2987 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2988 } else {
2989 err = tg3_setup_copper_phy(tp, force_reset);
2990 }
2991
2992 if (tp->link_config.active_speed == SPEED_1000 &&
2993 tp->link_config.active_duplex == DUPLEX_HALF)
2994 tw32(MAC_TX_LENGTHS,
2995 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2996 (6 << TX_LENGTHS_IPG_SHIFT) |
2997 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2998 else
2999 tw32(MAC_TX_LENGTHS,
3000 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3001 (6 << TX_LENGTHS_IPG_SHIFT) |
3002 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3003
3004 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3005 if (netif_carrier_ok(tp->dev)) {
3006 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3007 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3008 } else {
3009 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3010 }
3011 }
3012
3013 return err;
3014}
3015
df3e6548
MC		 3016/* This is called whenever we suspect that the system chipset is re-
3017 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3018 * is bogus tx completions. We try to recover by setting the
3019 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3020 * in the workqueue.
3021 */
3022static void tg3_tx_recover(struct tg3 *tp)
3023{
3024 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3025 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3026
3027 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3028 "mapped I/O cycles to the network device, attempting to "
3029 "recover. Please report the problem to the driver maintainer "
3030 "and include system chipset information.\n", tp->dev->name);
3031
3032 spin_lock(&tp->lock);
df3e6548 3033 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 3034 spin_unlock(&tp->lock);
3035}
3036
1b2a7205
MC		 3037static inline u32 tg3_tx_avail(struct tg3 *tp)
3038{
3039 smp_mb();
3040 return (tp->tx_pending -
3041 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3042}
3043
1da177e4
LT		 3044/* Tigon3 never reports partial packet sends. So we do not
3045 * need special logic to handle SKBs that have not had all
3046 * of their frags sent yet, like SunGEM does.
3047 */
3048static void tg3_tx(struct tg3 *tp)
3049{
3050 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3051 u32 sw_idx = tp->tx_cons;
3052
3053 while (sw_idx != hw_idx) {
3054 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3055 struct sk_buff *skb = ri->skb;
df3e6548
MC		 3056 int i, tx_bug = 0;
3057
3058 if (unlikely(skb == NULL)) {
3059 tg3_tx_recover(tp);
3060 return;
3061 }
1da177e4 3062
1da177e4
LT		 3063 pci_unmap_single(tp->pdev,
3064 pci_unmap_addr(ri, mapping),
3065 skb_headlen(skb),
3066 PCI_DMA_TODEVICE);
3067
3068 ri->skb = NULL;
3069
3070 sw_idx = NEXT_TX(sw_idx);
3071
3072 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 3073 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 3074 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3075 tx_bug = 1;
1da177e4
LT		 3076
3077 pci_unmap_page(tp->pdev,
3078 pci_unmap_addr(ri, mapping),
3079 skb_shinfo(skb)->frags[i].size,
3080 PCI_DMA_TODEVICE);
3081
3082 sw_idx = NEXT_TX(sw_idx);
3083 }
3084
f47c11ee 3085 dev_kfree_skb(skb);
df3e6548
MC		 3086
3087 if (unlikely(tx_bug)) {
3088 tg3_tx_recover(tp);
3089 return;
3090 }
1da177e4
LT		 3091 }
3092
3093 tp->tx_cons = sw_idx;
3094
1b2a7205
MC		 3095 /* Need to make the tx_cons update visible to tg3_start_xmit()
3096 * before checking for netif_queue_stopped(). Without the
3097 * memory barrier, there is a small possibility that tg3_start_xmit()
3098 * will miss it and cause the queue to be stopped forever.
3099 */
3100 smp_mb();
3101
3102 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 3103 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 3104 netif_tx_lock(tp->dev);
51b91468 3105 if (netif_queue_stopped(tp->dev) &&
42952231 3106 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 3107 netif_wake_queue(tp->dev);
1b2a7205 3108 netif_tx_unlock(tp->dev);
51b91468 3109 }
1da177e4
LT		 3110}
3111
3112/* Returns size of skb allocated or < 0 on error.
3113 *
3114 * We only need to fill in the address because the other members
3115 * of the RX descriptor are invariant, see tg3_init_rings.
3116 *
3117 * Note the purposeful assymetry of cpu vs. chip accesses. For
3118 * posting buffers we only dirty the first cache line of the RX
3119 * descriptor (containing the address). Whereas for the RX status
3120 * buffers the cpu only reads the last cacheline of the RX descriptor
3121 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3122 */
3123static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3124 int src_idx, u32 dest_idx_unmasked)
3125{
3126 struct tg3_rx_buffer_desc *desc;
3127 struct ring_info *map, *src_map;
3128 struct sk_buff *skb;
3129 dma_addr_t mapping;
3130 int skb_size, dest_idx;
3131
3132 src_map = NULL;
3133 switch (opaque_key) {
3134 case RXD_OPAQUE_RING_STD:
3135 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3136 desc = &tp->rx_std[dest_idx];
3137 map = &tp->rx_std_buffers[dest_idx];
3138 if (src_idx >= 0)
3139 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 3140 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 3141 break;
3142
3143 case RXD_OPAQUE_RING_JUMBO:
3144 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3145 desc = &tp->rx_jumbo[dest_idx];
3146 map = &tp->rx_jumbo_buffers[dest_idx];
3147 if (src_idx >= 0)
3148 src_map = &tp->rx_jumbo_buffers[src_idx];
3149 skb_size = RX_JUMBO_PKT_BUF_SZ;
3150 break;
3151
3152 default:
3153 return -EINVAL;
3154 };
3155
3156 /* Do not overwrite any of the map or rp information
3157 * until we are sure we can commit to a new buffer.
3158 *
3159 * Callers depend upon this behavior and assume that
3160 * we leave everything unchanged if we fail.
3161 */
a20e9c62 3162 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 3163 if (skb == NULL)
3164 return -ENOMEM;
3165
1da177e4
LT		 3166 skb_reserve(skb, tp->rx_offset);
3167
3168 mapping = pci_map_single(tp->pdev, skb->data,
3169 skb_size - tp->rx_offset,
3170 PCI_DMA_FROMDEVICE);
3171
3172 map->skb = skb;
3173 pci_unmap_addr_set(map, mapping, mapping);
3174
3175 if (src_map != NULL)
3176 src_map->skb = NULL;
3177
3178 desc->addr_hi = ((u64)mapping >> 32);
3179 desc->addr_lo = ((u64)mapping & 0xffffffff);
3180
3181 return skb_size;
3182}
3183
3184/* We only need to move over in the address because the other
3185 * members of the RX descriptor are invariant. See notes above
3186 * tg3_alloc_rx_skb for full details.
3187 */
3188static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3189 int src_idx, u32 dest_idx_unmasked)
3190{
3191 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3192 struct ring_info *src_map, *dest_map;
3193 int dest_idx;
3194
3195 switch (opaque_key) {
3196 case RXD_OPAQUE_RING_STD:
3197 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3198 dest_desc = &tp->rx_std[dest_idx];
3199 dest_map = &tp->rx_std_buffers[dest_idx];
3200 src_desc = &tp->rx_std[src_idx];
3201 src_map = &tp->rx_std_buffers[src_idx];
3202 break;
3203
3204 case RXD_OPAQUE_RING_JUMBO:
3205 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3206 dest_desc = &tp->rx_jumbo[dest_idx];
3207 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3208 src_desc = &tp->rx_jumbo[src_idx];
3209 src_map = &tp->rx_jumbo_buffers[src_idx];
3210 break;
3211
3212 default:
3213 return;
3214 };
3215
3216 dest_map->skb = src_map->skb;
3217 pci_unmap_addr_set(dest_map, mapping,
3218 pci_unmap_addr(src_map, mapping));
3219 dest_desc->addr_hi = src_desc->addr_hi;
3220 dest_desc->addr_lo = src_desc->addr_lo;
3221
3222 src_map->skb = NULL;
3223}
3224
3225#if TG3_VLAN_TAG_USED
3226static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3227{
3228 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3229}
3230#endif
3231
3232/* The RX ring scheme is composed of multiple rings which post fresh
3233 * buffers to the chip, and one special ring the chip uses to report
3234 * status back to the host.
3235 *
3236 * The special ring reports the status of received packets to the
3237 * host. The chip does not write into the original descriptor the
3238 * RX buffer was obtained from. The chip simply takes the original
3239 * descriptor as provided by the host, updates the status and length
3240 * field, then writes this into the next status ring entry.
3241 *
3242 * Each ring the host uses to post buffers to the chip is described
3243 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3244 * it is first placed into the on-chip ram. When the packet's length
3245 * is known, it walks down the TG3_BDINFO entries to select the ring.
3246 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3247 * which is within the range of the new packet's length is chosen.
3248 *
3249 * The "separate ring for rx status" scheme may sound queer, but it makes
3250 * sense from a cache coherency perspective. If only the host writes
3251 * to the buffer post rings, and only the chip writes to the rx status
3252 * rings, then cache lines never move beyond shared-modified state.
3253 * If both the host and chip were to write into the same ring, cache line
3254 * eviction could occur since both entities want it in an exclusive state.
3255 */
3256static int tg3_rx(struct tg3 *tp, int budget)
3257{
f92905de 3258 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 3259 u32 sw_idx = tp->rx_rcb_ptr;
3260 u16 hw_idx;
1da177e4
LT		 3261 int received;
3262
3263 hw_idx = tp->hw_status->idx[0].rx_producer;
3264 /*
3265 * We need to order the read of hw_idx and the read of
3266 * the opaque cookie.
3267 */
3268 rmb();
1da177e4
LT		 3269 work_mask = 0;
3270 received = 0;
3271 while (sw_idx != hw_idx && budget > 0) {
3272 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3273 unsigned int len;
3274 struct sk_buff *skb;
3275 dma_addr_t dma_addr;
3276 u32 opaque_key, desc_idx, *post_ptr;
3277
3278 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3279 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3280 if (opaque_key == RXD_OPAQUE_RING_STD) {
3281 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3282 mapping);
3283 skb = tp->rx_std_buffers[desc_idx].skb;
3284 post_ptr = &tp->rx_std_ptr;
f92905de 3285 rx_std_posted++;
1da177e4
LT		 3286 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3287 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3288 mapping);
3289 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3290 post_ptr = &tp->rx_jumbo_ptr;
3291 }
3292 else {
3293 goto next_pkt_nopost;
3294 }
3295
3296 work_mask |= opaque_key;
3297
3298 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3299 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3300 drop_it:
3301 tg3_recycle_rx(tp, opaque_key,
3302 desc_idx, *post_ptr);
3303 drop_it_no_recycle:
3304 /* Other statistics kept track of by card. */
3305 tp->net_stats.rx_dropped++;
3306 goto next_pkt;
3307 }
3308
3309 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3310
6aa20a22 3311 if (len > RX_COPY_THRESHOLD
1da177e4
LT		 3312 && tp->rx_offset == 2
3313 /* rx_offset != 2 iff this is a 5701 card running
3314 * in PCI-X mode [see tg3_get_invariants()] */
3315 ) {
3316 int skb_size;
3317
3318 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3319 desc_idx, *post_ptr);
3320 if (skb_size < 0)
3321 goto drop_it;
3322
3323 pci_unmap_single(tp->pdev, dma_addr,
3324 skb_size - tp->rx_offset,
3325 PCI_DMA_FROMDEVICE);
3326
3327 skb_put(skb, len);
3328 } else {
3329 struct sk_buff *copy_skb;
3330
3331 tg3_recycle_rx(tp, opaque_key,
3332 desc_idx, *post_ptr);
3333
a20e9c62 3334 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
1da177e4
LT		 3335 if (copy_skb == NULL)
3336 goto drop_it_no_recycle;
3337
1da177e4
LT		 3338 skb_reserve(copy_skb, 2);
3339 skb_put(copy_skb, len);
3340 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3341 memcpy(copy_skb->data, skb->data, len);
3342 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3343
3344 /* We'll reuse the original ring buffer. */
3345 skb = copy_skb;
3346 }
3347
3348 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3349 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3350 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3351 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3352 skb->ip_summed = CHECKSUM_UNNECESSARY;
3353 else
3354 skb->ip_summed = CHECKSUM_NONE;
3355
3356 skb->protocol = eth_type_trans(skb, tp->dev);
3357#if TG3_VLAN_TAG_USED
3358 if (tp->vlgrp != NULL &&
3359 desc->type_flags & RXD_FLAG_VLAN) {
3360 tg3_vlan_rx(tp, skb,
3361 desc->err_vlan & RXD_VLAN_MASK);
3362 } else
3363#endif
3364 netif_receive_skb(skb);
3365
3366 tp->dev->last_rx = jiffies;
3367 received++;
3368 budget--;
3369
3370next_pkt:
3371 (*post_ptr)++;
f92905de
MC		 3372
3373 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3374 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3375
3376 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3377 TG3_64BIT_REG_LOW, idx);
3378 work_mask &= ~RXD_OPAQUE_RING_STD;
3379 rx_std_posted = 0;
3380 }
1da177e4 3381next_pkt_nopost:
483ba50b 3382 sw_idx++;
6b31a515 3383 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 3384
3385 /* Refresh hw_idx to see if there is new work */
3386 if (sw_idx == hw_idx) {
3387 hw_idx = tp->hw_status->idx[0].rx_producer;
3388 rmb();
3389 }
1da177e4
LT		 3390 }
3391
3392 /* ACK the status ring. */
483ba50b
MC		 3393 tp->rx_rcb_ptr = sw_idx;
3394 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3395
3396 /* Refill RX ring(s). */
3397 if (work_mask & RXD_OPAQUE_RING_STD) {
3398 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3399 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3400 sw_idx);
3401 }
3402 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3403 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3404 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3405 sw_idx);
3406 }
3407 mmiowb();
3408
3409 return received;
3410}
3411
3412static int tg3_poll(struct net_device *netdev, int *budget)
3413{
3414 struct tg3 *tp = netdev_priv(netdev);
3415 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3416 int done;
3417
1da177e4
LT		 3418 /* handle link change and other phy events */
3419 if (!(tp->tg3_flags &
3420 (TG3_FLAG_USE_LINKCHG_REG |
3421 TG3_FLAG_POLL_SERDES))) {
3422 if (sblk->status & SD_STATUS_LINK_CHG) {
3423 sblk->status = SD_STATUS_UPDATED |
3424 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3425 spin_lock(&tp->lock);
1da177e4 3426 tg3_setup_phy(tp, 0);
f47c11ee 3427 spin_unlock(&tp->lock);
1da177e4
LT		 3428 }
3429 }
3430
3431 /* run TX completion thread */
3432 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3433 tg3_tx(tp);
df3e6548
MC		 3434 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3435 netif_rx_complete(netdev);
3436 schedule_work(&tp->reset_task);
3437 return 0;
3438 }
1da177e4
LT		 3439 }
3440
1da177e4
LT		 3441 /* run RX thread, within the bounds set by NAPI.
3442 * All RX "locking" is done by ensuring outside
3443 * code synchronizes with dev->poll()
3444 */
1da177e4
LT		 3445 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3446 int orig_budget = *budget;
3447 int work_done;
3448
3449 if (orig_budget > netdev->quota)
3450 orig_budget = netdev->quota;
3451
3452 work_done = tg3_rx(tp, orig_budget);
3453
3454 *budget -= work_done;
3455 netdev->quota -= work_done;
1da177e4
LT		 3456 }
3457
38f3843e 3458 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
f7383c22 3459 tp->last_tag = sblk->status_tag;
38f3843e
MC		 3460 rmb();
3461 } else
3462 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3463
1da177e4 3464 /* if no more work, tell net stack and NIC we're done */
f7383c22 3465 done = !tg3_has_work(tp);
1da177e4 3466 if (done) {
f47c11ee 3467 netif_rx_complete(netdev);
1da177e4 3468 tg3_restart_ints(tp);
1da177e4
LT		 3469 }
3470
3471 return (done ? 0 : 1);
3472}
3473
f47c11ee
DM		 3474static void tg3_irq_quiesce(struct tg3 *tp)
3475{
3476 BUG_ON(tp->irq_sync);
3477
3478 tp->irq_sync = 1;
3479 smp_mb();
3480
3481 synchronize_irq(tp->pdev->irq);
3482}
3483
3484static inline int tg3_irq_sync(struct tg3 *tp)
3485{
3486 return tp->irq_sync;
3487}
3488
3489/* Fully shutdown all tg3 driver activity elsewhere in the system.
3490 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3491 * with as well. Most of the time, this is not necessary except when
3492 * shutting down the device.
3493 */
3494static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3495{
3496 if (irq_sync)
3497 tg3_irq_quiesce(tp);
3498 spin_lock_bh(&tp->lock);
f47c11ee
DM		 3499}
3500
3501static inline void tg3_full_unlock(struct tg3 *tp)
3502{
f47c11ee
DM		 3503 spin_unlock_bh(&tp->lock);
3504}
3505
fcfa0a32
MC		 3506/* One-shot MSI handler - Chip automatically disables interrupt
3507 * after sending MSI so driver doesn't have to do it.
3508 */
7d12e780 3509static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 3510{
3511 struct net_device *dev = dev_id;
3512 struct tg3 *tp = netdev_priv(dev);
3513
3514 prefetch(tp->hw_status);
3515 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3516
3517 if (likely(!tg3_irq_sync(tp)))
3518 netif_rx_schedule(dev); /* schedule NAPI poll */
3519
3520 return IRQ_HANDLED;
3521}
3522
88b06bc2
MC		 3523/* MSI ISR - No need to check for interrupt sharing and no need to
3524 * flush status block and interrupt mailbox. PCI ordering rules
3525 * guarantee that MSI will arrive after the status block.
3526 */
7d12e780 3527static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 3528{
3529 struct net_device *dev = dev_id;
3530 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3531
61487480
MC		 3532 prefetch(tp->hw_status);
3533 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3534 /*
fac9b83e 3535 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3536 * chip-internal interrupt pending events.
fac9b83e 3537 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3538 * NIC to stop sending us irqs, engaging "in-intr-handler"
3539 * event coalescing.
3540 */
3541 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3542 if (likely(!tg3_irq_sync(tp)))
88b06bc2 3543 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3544
88b06bc2
MC		 3545 return IRQ_RETVAL(1);
3546}
3547
7d12e780 3548static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 3549{
3550 struct net_device *dev = dev_id;
3551 struct tg3 *tp = netdev_priv(dev);
3552 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3553 unsigned int handled = 1;
3554
1da177e4
LT		 3555 /* In INTx mode, it is possible for the interrupt to arrive at
3556 * the CPU before the status block posted prior to the interrupt.
3557 * Reading the PCI State register will confirm whether the
3558 * interrupt is ours and will flush the status block.
3559 */
3560 if ((sblk->status & SD_STATUS_UPDATED) ||
3561 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3562 /*
fac9b83e 3563 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 3564 * chip-internal interrupt pending events.
fac9b83e 3565 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 3566 * NIC to stop sending us irqs, engaging "in-intr-handler"
3567 * event coalescing.
3568 */
3569 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3570 0x00000001);
f47c11ee
DM		 3571 if (tg3_irq_sync(tp))
3572 goto out;
fac9b83e 3573 sblk->status &= ~SD_STATUS_UPDATED;
61487480
MC		 3574 if (likely(tg3_has_work(tp))) {
3575 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
fac9b83e 3576 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3577 } else {
fac9b83e
DM		 3578 /* No work, shared interrupt perhaps? re-enable
3579 * interrupts, and flush that PCI write
3580 */
09ee929c 3581 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3582 0x00000000);
fac9b83e
DM		 3583 }
3584 } else { /* shared interrupt */
3585 handled = 0;
3586 }
f47c11ee 3587out:
fac9b83e
DM		 3588 return IRQ_RETVAL(handled);
3589}
3590
7d12e780 3591static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 3592{
3593 struct net_device *dev = dev_id;
3594 struct tg3 *tp = netdev_priv(dev);
3595 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3596 unsigned int handled = 1;
3597
fac9b83e
DM		 3598 /* In INTx mode, it is possible for the interrupt to arrive at
3599 * the CPU before the status block posted prior to the interrupt.
3600 * Reading the PCI State register will confirm whether the
3601 * interrupt is ours and will flush the status block.
3602 */
38f3843e 3603 if ((sblk->status_tag != tp->last_tag) ||
fac9b83e 3604 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3605 /*
fac9b83e
DM		 3606 * writing any value to intr-mbox-0 clears PCI INTA# and
3607 * chip-internal interrupt pending events.
3608 * writing non-zero to intr-mbox-0 additional tells the
3609 * NIC to stop sending us irqs, engaging "in-intr-handler"
3610 * event coalescing.
1da177e4 3611 */
fac9b83e
DM		 3612 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3613 0x00000001);
f47c11ee
DM		 3614 if (tg3_irq_sync(tp))
3615 goto out;
38f3843e 3616 if (netif_rx_schedule_prep(dev)) {
61487480 3617 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
38f3843e
MC		 3618 /* Update last_tag to mark that this status has been
3619 * seen. Because interrupt may be shared, we may be
3620 * racing with tg3_poll(), so only update last_tag
3621 * if tg3_poll() is not scheduled.
1da177e4 3622 */
38f3843e
MC		 3623 tp->last_tag = sblk->status_tag;
3624 __netif_rx_schedule(dev);
1da177e4
LT		 3625 }
3626 } else { /* shared interrupt */
3627 handled = 0;
3628 }
f47c11ee 3629out:
1da177e4
LT		 3630 return IRQ_RETVAL(handled);
3631}
3632
7938109f 3633/* ISR for interrupt test */
7d12e780 3634static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 3635{
3636 struct net_device *dev = dev_id;
3637 struct tg3 *tp = netdev_priv(dev);
3638 struct tg3_hw_status *sblk = tp->hw_status;
3639
f9804ddb
MC		 3640 if ((sblk->status & SD_STATUS_UPDATED) ||
3641 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 3642 tg3_disable_ints(tp);
7938109f
MC		 3643 return IRQ_RETVAL(1);
3644 }
3645 return IRQ_RETVAL(0);
3646}
3647
8e7a22e3 3648static int tg3_init_hw(struct tg3 *, int);
944d980e 3649static int tg3_halt(struct tg3 *, int, int);
1da177e4 3650
b9ec6c1b
MC		 3651/* Restart hardware after configuration changes, self-test, etc.
3652 * Invoked with tp->lock held.
3653 */
3654static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3655{
3656 int err;
3657
3658 err = tg3_init_hw(tp, reset_phy);
3659 if (err) {
3660 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3661 "aborting.\n", tp->dev->name);
3662 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3663 tg3_full_unlock(tp);
3664 del_timer_sync(&tp->timer);
3665 tp->irq_sync = 0;
3666 netif_poll_enable(tp->dev);
3667 dev_close(tp->dev);
3668 tg3_full_lock(tp, 0);
3669 }
3670 return err;
3671}
3672
1da177e4
LT		 3673#ifdef CONFIG_NET_POLL_CONTROLLER
3674static void tg3_poll_controller(struct net_device *dev)
3675{
88b06bc2
MC		 3676 struct tg3 *tp = netdev_priv(dev);
3677
7d12e780 3678 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 3679}
3680#endif
3681
c4028958 3682static void tg3_reset_task(struct work_struct *work)
1da177e4 3683{
c4028958 3684 struct tg3 *tp = container_of(work, struct tg3, reset_task);
1da177e4
LT		 3685 unsigned int restart_timer;
3686
7faa006f
MC		 3687 tg3_full_lock(tp, 0);
3688 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3689
3690 if (!netif_running(tp->dev)) {
3691 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3692 tg3_full_unlock(tp);
3693 return;
3694 }
3695
3696 tg3_full_unlock(tp);
3697
1da177e4
LT		 3698 tg3_netif_stop(tp);
3699
f47c11ee 3700 tg3_full_lock(tp, 1);
1da177e4
LT		 3701
3702 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3703 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3704
df3e6548
MC		 3705 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3706 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3707 tp->write32_rx_mbox = tg3_write_flush_reg32;
3708 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3709 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3710 }
3711
944d980e 3712 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b9ec6c1b
MC		 3713 if (tg3_init_hw(tp, 1))
3714 goto out;
1da177e4
LT		 3715
3716 tg3_netif_start(tp);
3717
1da177e4
LT		 3718 if (restart_timer)
3719 mod_timer(&tp->timer, jiffies + 1);
7faa006f 3720
b9ec6c1b 3721out:
7faa006f
MC		 3722 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3723
3724 tg3_full_unlock(tp);
1da177e4
LT		 3725}
3726
3727static void tg3_tx_timeout(struct net_device *dev)
3728{
3729 struct tg3 *tp = netdev_priv(dev);
3730
9f88f29f
MC		 3731 if (netif_msg_tx_err(tp))
3732 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3733 dev->name);
1da177e4
LT		 3734
3735 schedule_work(&tp->reset_task);
3736}
3737
c58ec932
MC		 3738/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3739static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3740{
3741 u32 base = (u32) mapping & 0xffffffff;
3742
3743 return ((base > 0xffffdcc0) &&
3744 (base + len + 8 < base));
3745}
3746
72f2afb8
MC		 3747/* Test for DMA addresses > 40-bit */
3748static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3749 int len)
3750{
3751#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 3752 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 3753 return (((u64) mapping + len) > DMA_40BIT_MASK);
3754 return 0;
3755#else
3756 return 0;
3757#endif
3758}
3759
1da177e4
LT		 3760static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3761
72f2afb8
MC		 3762/* Workaround 4GB and 40-bit hardware DMA bugs. */
3763static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3764 u32 last_plus_one, u32 *start,
3765 u32 base_flags, u32 mss)
1da177e4
LT		 3766{
3767 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3768 dma_addr_t new_addr = 0;
1da177e4 3769 u32 entry = *start;
c58ec932 3770 int i, ret = 0;
1da177e4
LT		 3771
3772 if (!new_skb) {
c58ec932
MC		 3773 ret = -1;
3774 } else {
3775 /* New SKB is guaranteed to be linear. */
3776 entry = *start;
3777 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3778 PCI_DMA_TODEVICE);
3779 /* Make sure new skb does not cross any 4G boundaries.
3780 * Drop the packet if it does.
3781 */
3782 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3783 ret = -1;
3784 dev_kfree_skb(new_skb);
3785 new_skb = NULL;
3786 } else {
3787 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3788 base_flags, 1 | (mss << 1));
3789 *start = NEXT_TX(entry);
3790 }
1da177e4
LT		 3791 }
3792
1da177e4
LT		 3793 /* Now clean up the sw ring entries. */
3794 i = 0;
3795 while (entry != last_plus_one) {
3796 int len;
3797
3798 if (i == 0)
3799 len = skb_headlen(skb);
3800 else
3801 len = skb_shinfo(skb)->frags[i-1].size;
3802 pci_unmap_single(tp->pdev,
3803 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3804 len, PCI_DMA_TODEVICE);
3805 if (i == 0) {
3806 tp->tx_buffers[entry].skb = new_skb;
3807 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3808 } else {
3809 tp->tx_buffers[entry].skb = NULL;
3810 }
3811 entry = NEXT_TX(entry);
3812 i++;
3813 }
3814
3815 dev_kfree_skb(skb);
3816
c58ec932 3817 return ret;
1da177e4
LT		 3818}
3819
3820static void tg3_set_txd(struct tg3 *tp, int entry,
3821 dma_addr_t mapping, int len, u32 flags,
3822 u32 mss_and_is_end)
3823{
3824 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3825 int is_end = (mss_and_is_end & 0x1);
3826 u32 mss = (mss_and_is_end >> 1);
3827 u32 vlan_tag = 0;
3828
3829 if (is_end)
3830 flags |= TXD_FLAG_END;
3831 if (flags & TXD_FLAG_VLAN) {
3832 vlan_tag = flags >> 16;
3833 flags &= 0xffff;
3834 }
3835 vlan_tag |= (mss << TXD_MSS_SHIFT);
3836
3837 txd->addr_hi = ((u64) mapping >> 32);
3838 txd->addr_lo = ((u64) mapping & 0xffffffff);
3839 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3840 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3841}
3842
5a6f3074
MC		 3843/* hard_start_xmit for devices that don't have any bugs and
3844 * support TG3_FLG2_HW_TSO_2 only.
3845 */
1da177e4 3846static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 3847{
3848 struct tg3 *tp = netdev_priv(dev);
3849 dma_addr_t mapping;
3850 u32 len, entry, base_flags, mss;
3851
3852 len = skb_headlen(skb);
3853
00b70504
MC		 3854 /* We are running in BH disabled context with netif_tx_lock
3855 * and TX reclaim runs via tp->poll inside of a software
5a6f3074
MC		 3856 * interrupt. Furthermore, IRQ processing runs lockless so we have
3857 * no IRQ context deadlocks to worry about either. Rejoice!
3858 */
1b2a7205 3859 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 3860 if (!netif_queue_stopped(dev)) {
3861 netif_stop_queue(dev);
3862
3863 /* This is a hard error, log it. */
3864 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3865 "queue awake!\n", dev->name);
3866 }
5a6f3074
MC		 3867 return NETDEV_TX_BUSY;
3868 }
3869
3870 entry = tp->tx_prod;
3871 base_flags = 0;
5a6f3074
MC		 3872 mss = 0;
3873 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
7967168c 3874 (mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 3875 int tcp_opt_len, ip_tcp_len;
3876
3877 if (skb_header_cloned(skb) &&
3878 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3879 dev_kfree_skb(skb);
3880 goto out_unlock;
3881 }
3882
b0026624
MC		 3883 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3884 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3885 else {
3886 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3887 ip_tcp_len = (skb->nh.iph->ihl * 4) +
3888 sizeof(struct tcphdr);
3889
3890 skb->nh.iph->check = 0;
3891 skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3892 tcp_opt_len);
3893 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3894 }
5a6f3074
MC		 3895
3896 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3897 TXD_FLAG_CPU_POST_DMA);
3898
5a6f3074
MC		 3899 skb->h.th->check = 0;
3900
5a6f3074 3901 }
84fa7933 3902 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 3903 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 3904#if TG3_VLAN_TAG_USED
3905 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3906 base_flags |= (TXD_FLAG_VLAN |
3907 (vlan_tx_tag_get(skb) << 16));
3908#endif
3909
3910 /* Queue skb data, a.k.a. the main skb fragment. */
3911 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3912
3913 tp->tx_buffers[entry].skb = skb;
3914 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3915
3916 tg3_set_txd(tp, entry, mapping, len, base_flags,
3917 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3918
3919 entry = NEXT_TX(entry);
3920
3921 /* Now loop through additional data fragments, and queue them. */
3922 if (skb_shinfo(skb)->nr_frags > 0) {
3923 unsigned int i, last;
3924
3925 last = skb_shinfo(skb)->nr_frags - 1;
3926 for (i = 0; i <= last; i++) {
3927 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3928
3929 len = frag->size;
3930 mapping = pci_map_page(tp->pdev,
3931 frag->page,
3932 frag->page_offset,
3933 len, PCI_DMA_TODEVICE);
3934
3935 tp->tx_buffers[entry].skb = NULL;
3936 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3937
3938 tg3_set_txd(tp, entry, mapping, len,
3939 base_flags, (i == last) | (mss << 1));
3940
3941 entry = NEXT_TX(entry);
3942 }
3943 }
3944
3945 /* Packets are ready, update Tx producer idx local and on card. */
3946 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3947
3948 tp->tx_prod = entry;
1b2a7205 3949 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 3950 netif_stop_queue(dev);
42952231 3951 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 3952 netif_wake_queue(tp->dev);
3953 }
3954
3955out_unlock:
3956 mmiowb();
5a6f3074
MC		 3957
3958 dev->trans_start = jiffies;
3959
3960 return NETDEV_TX_OK;
3961}
3962
52c0fd83
MC		 3963static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3964
3965/* Use GSO to workaround a rare TSO bug that may be triggered when the
3966 * TSO header is greater than 80 bytes.
3967 */
3968static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3969{
3970 struct sk_buff *segs, *nskb;
3971
3972 /* Estimate the number of fragments in the worst case */
1b2a7205 3973 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83
MC		 3974 netif_stop_queue(tp->dev);
3975 return NETDEV_TX_BUSY;
3976 }
3977
3978 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3979 if (unlikely(IS_ERR(segs)))
3980 goto tg3_tso_bug_end;
3981
3982 do {
3983 nskb = segs;
3984 segs = segs->next;
3985 nskb->next = NULL;
3986 tg3_start_xmit_dma_bug(nskb, tp->dev);
3987 } while (segs);
3988
3989tg3_tso_bug_end:
3990 dev_kfree_skb(skb);
3991
3992 return NETDEV_TX_OK;
3993}
52c0fd83 3994
5a6f3074
MC		 3995/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3996 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3997 */
3998static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 3999{
4000 struct tg3 *tp = netdev_priv(dev);
4001 dma_addr_t mapping;
1da177e4
LT		 4002 u32 len, entry, base_flags, mss;
4003 int would_hit_hwbug;
1da177e4
LT		 4004
4005 len = skb_headlen(skb);
4006
00b70504
MC		 4007 /* We are running in BH disabled context with netif_tx_lock
4008 * and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 4009 * interrupt. Furthermore, IRQ processing runs lockless so we have
4010 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 4011 */
1b2a7205 4012 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 4013 if (!netif_queue_stopped(dev)) {
4014 netif_stop_queue(dev);
4015
4016 /* This is a hard error, log it. */
4017 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4018 "queue awake!\n", dev->name);
4019 }
1da177e4
LT		 4020 return NETDEV_TX_BUSY;
4021 }
4022
4023 entry = tp->tx_prod;
4024 base_flags = 0;
84fa7933 4025 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 4026 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4
LT		 4027 mss = 0;
4028 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
7967168c 4029 (mss = skb_shinfo(skb)->gso_size) != 0) {
52c0fd83 4030 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 4031
4032 if (skb_header_cloned(skb) &&
4033 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4034 dev_kfree_skb(skb);
4035 goto out_unlock;
4036 }
4037
4038 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4039 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4040
52c0fd83
MC		 4041 hdr_len = ip_tcp_len + tcp_opt_len;
4042 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4043 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4044 return (tg3_tso_bug(tp, skb));
4045
1da177e4
LT		 4046 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4047 TXD_FLAG_CPU_POST_DMA);
4048
4049 skb->nh.iph->check = 0;
52c0fd83 4050 skb->nh.iph->tot_len = htons(mss + hdr_len);
1da177e4
LT		 4051 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4052 skb->h.th->check = 0;
4053 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4054 }
4055 else {
4056 skb->h.th->check =
4057 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4058 skb->nh.iph->daddr,
4059 0, IPPROTO_TCP, 0);
4060 }
4061
4062 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4063 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4064 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4065 int tsflags;
4066
4067 tsflags = ((skb->nh.iph->ihl - 5) +
4068 (tcp_opt_len >> 2));
4069 mss |= (tsflags << 11);
4070 }
4071 } else {
4072 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4073 int tsflags;
4074
4075 tsflags = ((skb->nh.iph->ihl - 5) +
4076 (tcp_opt_len >> 2));
4077 base_flags |= tsflags << 12;
4078 }
4079 }
4080 }
1da177e4
LT		 4081#if TG3_VLAN_TAG_USED
4082 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4083 base_flags |= (TXD_FLAG_VLAN |
4084 (vlan_tx_tag_get(skb) << 16));
4085#endif
4086
4087 /* Queue skb data, a.k.a. the main skb fragment. */
4088 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4089
4090 tp->tx_buffers[entry].skb = skb;
4091 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4092
4093 would_hit_hwbug = 0;
4094
4095 if (tg3_4g_overflow_test(mapping, len))
c58ec932 4096 would_hit_hwbug = 1;
1da177e4
LT		 4097
4098 tg3_set_txd(tp, entry, mapping, len, base_flags,
4099 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4100
4101 entry = NEXT_TX(entry);
4102
4103 /* Now loop through additional data fragments, and queue them. */
4104 if (skb_shinfo(skb)->nr_frags > 0) {
4105 unsigned int i, last;
4106
4107 last = skb_shinfo(skb)->nr_frags - 1;
4108 for (i = 0; i <= last; i++) {
4109 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4110
4111 len = frag->size;
4112 mapping = pci_map_page(tp->pdev,
4113 frag->page,
4114 frag->page_offset,
4115 len, PCI_DMA_TODEVICE);
4116
4117 tp->tx_buffers[entry].skb = NULL;
4118 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4119
c58ec932
MC		 4120 if (tg3_4g_overflow_test(mapping, len))
4121 would_hit_hwbug = 1;
1da177e4 4122
72f2afb8
MC		 4123 if (tg3_40bit_overflow_test(tp, mapping, len))
4124 would_hit_hwbug = 1;
4125
1da177e4
LT		 4126 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4127 tg3_set_txd(tp, entry, mapping, len,
4128 base_flags, (i == last)|(mss << 1));
4129 else
4130 tg3_set_txd(tp, entry, mapping, len,
4131 base_flags, (i == last));
4132
4133 entry = NEXT_TX(entry);
4134 }
4135 }
4136
4137 if (would_hit_hwbug) {
4138 u32 last_plus_one = entry;
4139 u32 start;
1da177e4 4140
c58ec932
MC		 4141 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4142 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 4143
4144 /* If the workaround fails due to memory/mapping
4145 * failure, silently drop this packet.
4146 */
72f2afb8 4147 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 4148 &start, base_flags, mss))
1da177e4
LT		 4149 goto out_unlock;
4150
4151 entry = start;
4152 }
4153
4154 /* Packets are ready, update Tx producer idx local and on card. */
4155 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4156
4157 tp->tx_prod = entry;
1b2a7205 4158 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 4159 netif_stop_queue(dev);
42952231 4160 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 4161 netif_wake_queue(tp->dev);
4162 }
1da177e4
LT		 4163
4164out_unlock:
4165 mmiowb();
1da177e4
LT		 4166
4167 dev->trans_start = jiffies;
4168
4169 return NETDEV_TX_OK;
4170}
4171
4172static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4173 int new_mtu)
4174{
4175 dev->mtu = new_mtu;
4176
ef7f5ec0 4177 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 4178 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 4179 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4180 ethtool_op_set_tso(dev, 0);
4181 }
4182 else
4183 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4184 } else {
a4e2b347 4185 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 4186 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 4187 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 4188 }
1da177e4
LT		 4189}
4190
4191static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4192{
4193 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 4194 int err;
1da177e4
LT		 4195
4196 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4197 return -EINVAL;
4198
4199 if (!netif_running(dev)) {
4200 /* We'll just catch it later when the
4201 * device is up'd.
4202 */
4203 tg3_set_mtu(dev, tp, new_mtu);
4204 return 0;
4205 }
4206
4207 tg3_netif_stop(tp);
f47c11ee
DM		 4208
4209 tg3_full_lock(tp, 1);
1da177e4 4210
944d980e 4211 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 4212
4213 tg3_set_mtu(dev, tp, new_mtu);
4214
b9ec6c1b 4215 err = tg3_restart_hw(tp, 0);
1da177e4 4216
b9ec6c1b
MC		 4217 if (!err)
4218 tg3_netif_start(tp);
1da177e4 4219
f47c11ee 4220 tg3_full_unlock(tp);
1da177e4 4221
b9ec6c1b 4222 return err;
1da177e4
LT		 4223}
4224
4225/* Free up pending packets in all rx/tx rings.
4226 *
4227 * The chip has been shut down and the driver detached from
4228 * the networking, so no interrupts or new tx packets will
4229 * end up in the driver. tp->{tx,}lock is not held and we are not
4230 * in an interrupt context and thus may sleep.
4231 */
4232static void tg3_free_rings(struct tg3 *tp)
4233{
4234 struct ring_info *rxp;
4235 int i;
4236
4237 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4238 rxp = &tp->rx_std_buffers[i];
4239
4240 if (rxp->skb == NULL)
4241 continue;
4242 pci_unmap_single(tp->pdev,
4243 pci_unmap_addr(rxp, mapping),
7e72aad4 4244 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 4245 PCI_DMA_FROMDEVICE);
4246 dev_kfree_skb_any(rxp->skb);
4247 rxp->skb = NULL;
4248 }
4249
4250 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4251 rxp = &tp->rx_jumbo_buffers[i];
4252
4253 if (rxp->skb == NULL)
4254 continue;
4255 pci_unmap_single(tp->pdev,
4256 pci_unmap_addr(rxp, mapping),
4257 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4258 PCI_DMA_FROMDEVICE);
4259 dev_kfree_skb_any(rxp->skb);
4260 rxp->skb = NULL;
4261 }
4262
4263 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4264 struct tx_ring_info *txp;
4265 struct sk_buff *skb;
4266 int j;
4267
4268 txp = &tp->tx_buffers[i];
4269 skb = txp->skb;
4270
4271 if (skb == NULL) {
4272 i++;
4273 continue;
4274 }
4275
4276 pci_unmap_single(tp->pdev,
4277 pci_unmap_addr(txp, mapping),
4278 skb_headlen(skb),
4279 PCI_DMA_TODEVICE);
4280 txp->skb = NULL;
4281
4282 i++;
4283
4284 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4285 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4286 pci_unmap_page(tp->pdev,
4287 pci_unmap_addr(txp, mapping),
4288 skb_shinfo(skb)->frags[j].size,
4289 PCI_DMA_TODEVICE);
4290 i++;
4291 }
4292
4293 dev_kfree_skb_any(skb);
4294 }
4295}
4296
4297/* Initialize tx/rx rings for packet processing.
4298 *
4299 * The chip has been shut down and the driver detached from
4300 * the networking, so no interrupts or new tx packets will
4301 * end up in the driver. tp->{tx,}lock are held and thus
4302 * we may not sleep.
4303 */
32d8c572 4304static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 4305{
4306 u32 i;
4307
4308 /* Free up all the SKBs. */
4309 tg3_free_rings(tp);
4310
4311 /* Zero out all descriptors. */
4312 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4313 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4314 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4315 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4316
7e72aad4 4317 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 4318 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 4319 (tp->dev->mtu > ETH_DATA_LEN))
4320 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4321
1da177e4
LT		 4322 /* Initialize invariants of the rings, we only set this
4323 * stuff once. This works because the card does not
4324 * write into the rx buffer posting rings.
4325 */
4326 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4327 struct tg3_rx_buffer_desc *rxd;
4328
4329 rxd = &tp->rx_std[i];
7e72aad4 4330 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 4331 << RXD_LEN_SHIFT;
4332 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4333 rxd->opaque = (RXD_OPAQUE_RING_STD |
4334 (i << RXD_OPAQUE_INDEX_SHIFT));
4335 }
4336
0f893dc6 4337 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4338 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4339 struct tg3_rx_buffer_desc *rxd;
4340
4341 rxd = &tp->rx_jumbo[i];
4342 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4343 << RXD_LEN_SHIFT;
4344 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4345 RXD_FLAG_JUMBO;
4346 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4347 (i << RXD_OPAQUE_INDEX_SHIFT));
4348 }
4349 }
4350
4351 /* Now allocate fresh SKBs for each rx ring. */
4352 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 4353 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4354 printk(KERN_WARNING PFX
4355 "%s: Using a smaller RX standard ring, "
4356 "only %d out of %d buffers were allocated "
4357 "successfully.\n",
4358 tp->dev->name, i, tp->rx_pending);
4359 if (i == 0)
4360 return -ENOMEM;
4361 tp->rx_pending = i;
1da177e4 4362 break;
32d8c572 4363 }
1da177e4
LT		 4364 }
4365
0f893dc6 4366 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4367 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4368 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 4369 -1, i) < 0) {
4370 printk(KERN_WARNING PFX
4371 "%s: Using a smaller RX jumbo ring, "
4372 "only %d out of %d buffers were "
4373 "allocated successfully.\n",
4374 tp->dev->name, i, tp->rx_jumbo_pending);
4375 if (i == 0) {
4376 tg3_free_rings(tp);
4377 return -ENOMEM;
4378 }
4379 tp->rx_jumbo_pending = i;
1da177e4 4380 break;
32d8c572 4381 }
1da177e4
LT		 4382 }
4383 }
32d8c572 4384 return 0;
1da177e4
LT		 4385}
4386
4387/*
4388 * Must not be invoked with interrupt sources disabled and
4389 * the hardware shutdown down.
4390 */
4391static void tg3_free_consistent(struct tg3 *tp)
4392{
b4558ea9
JJ		 4393 kfree(tp->rx_std_buffers);
4394 tp->rx_std_buffers = NULL;
1da177e4
LT		 4395 if (tp->rx_std) {
4396 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4397 tp->rx_std, tp->rx_std_mapping);
4398 tp->rx_std = NULL;
4399 }
4400 if (tp->rx_jumbo) {
4401 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4402 tp->rx_jumbo, tp->rx_jumbo_mapping);
4403 tp->rx_jumbo = NULL;
4404 }
4405 if (tp->rx_rcb) {
4406 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4407 tp->rx_rcb, tp->rx_rcb_mapping);
4408 tp->rx_rcb = NULL;
4409 }
4410 if (tp->tx_ring) {
4411 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4412 tp->tx_ring, tp->tx_desc_mapping);
4413 tp->tx_ring = NULL;
4414 }
4415 if (tp->hw_status) {
4416 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4417 tp->hw_status, tp->status_mapping);
4418 tp->hw_status = NULL;
4419 }
4420 if (tp->hw_stats) {
4421 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4422 tp->hw_stats, tp->stats_mapping);
4423 tp->hw_stats = NULL;
4424 }
4425}
4426
4427/*
4428 * Must not be invoked with interrupt sources disabled and
4429 * the hardware shutdown down. Can sleep.
4430 */
4431static int tg3_alloc_consistent(struct tg3 *tp)
4432{
bd2b3343 4433 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 4434 (TG3_RX_RING_SIZE +
4435 TG3_RX_JUMBO_RING_SIZE)) +
4436 (sizeof(struct tx_ring_info) *
4437 TG3_TX_RING_SIZE),
4438 GFP_KERNEL);
4439 if (!tp->rx_std_buffers)
4440 return -ENOMEM;
4441
1da177e4
LT		 4442 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4443 tp->tx_buffers = (struct tx_ring_info *)
4444 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4445
4446 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4447 &tp->rx_std_mapping);
4448 if (!tp->rx_std)
4449 goto err_out;
4450
4451 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4452 &tp->rx_jumbo_mapping);
4453
4454 if (!tp->rx_jumbo)
4455 goto err_out;
4456
4457 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4458 &tp->rx_rcb_mapping);
4459 if (!tp->rx_rcb)
4460 goto err_out;
4461
4462 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4463 &tp->tx_desc_mapping);
4464 if (!tp->tx_ring)
4465 goto err_out;
4466
4467 tp->hw_status = pci_alloc_consistent(tp->pdev,
4468 TG3_HW_STATUS_SIZE,
4469 &tp->status_mapping);
4470 if (!tp->hw_status)
4471 goto err_out;
4472
4473 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4474 sizeof(struct tg3_hw_stats),
4475 &tp->stats_mapping);
4476 if (!tp->hw_stats)
4477 goto err_out;
4478
4479 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4480 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4481
4482 return 0;
4483
4484err_out:
4485 tg3_free_consistent(tp);
4486 return -ENOMEM;
4487}
4488
4489#define MAX_WAIT_CNT 1000
4490
4491/* To stop a block, clear the enable bit and poll till it
4492 * clears. tp->lock is held.
4493 */
b3b7d6be 4494static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4495{
4496 unsigned int i;
4497 u32 val;
4498
4499 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4500 switch (ofs) {
4501 case RCVLSC_MODE:
4502 case DMAC_MODE:
4503 case MBFREE_MODE:
4504 case BUFMGR_MODE:
4505 case MEMARB_MODE:
4506 /* We can't enable/disable these bits of the
4507 * 5705/5750, just say success.
4508 */
4509 return 0;
4510
4511 default:
4512 break;
4513 };
4514 }
4515
4516 val = tr32(ofs);
4517 val &= ~enable_bit;
4518 tw32_f(ofs, val);
4519
4520 for (i = 0; i < MAX_WAIT_CNT; i++) {
4521 udelay(100);
4522 val = tr32(ofs);
4523 if ((val & enable_bit) == 0)
4524 break;
4525 }
4526
b3b7d6be 4527 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4528 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4529 "ofs=%lx enable_bit=%x\n",
4530 ofs, enable_bit);
4531 return -ENODEV;
4532 }
4533
4534 return 0;
4535}
4536
4537/* tp->lock is held. */
b3b7d6be 4538static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4539{
4540 int i, err;
4541
4542 tg3_disable_ints(tp);
4543
4544 tp->rx_mode &= ~RX_MODE_ENABLE;
4545 tw32_f(MAC_RX_MODE, tp->rx_mode);
4546 udelay(10);
4547
b3b7d6be
DM		 4548 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4549 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4550 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4551 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4552 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4553 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4554
4555 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4556 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4557 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4558 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4559 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4560 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4561 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4562
4563 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4564 tw32_f(MAC_MODE, tp->mac_mode);
4565 udelay(40);
4566
4567 tp->tx_mode &= ~TX_MODE_ENABLE;
4568 tw32_f(MAC_TX_MODE, tp->tx_mode);
4569
4570 for (i = 0; i < MAX_WAIT_CNT; i++) {
4571 udelay(100);
4572 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4573 break;
4574 }
4575 if (i >= MAX_WAIT_CNT) {
4576 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4577 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4578 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4579 err |= -ENODEV;
1da177e4
LT		 4580 }
4581
e6de8ad1 4582 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4583 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4584 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4585
4586 tw32(FTQ_RESET, 0xffffffff);
4587 tw32(FTQ_RESET, 0x00000000);
4588
b3b7d6be
DM		 4589 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4590 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4591
4592 if (tp->hw_status)
4593 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4594 if (tp->hw_stats)
4595 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4596
1da177e4
LT		 4597 return err;
4598}
4599
4600/* tp->lock is held. */
4601static int tg3_nvram_lock(struct tg3 *tp)
4602{
4603 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4604 int i;
4605
ec41c7df
MC		 4606 if (tp->nvram_lock_cnt == 0) {
4607 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4608 for (i = 0; i < 8000; i++) {
4609 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4610 break;
4611 udelay(20);
4612 }
4613 if (i == 8000) {
4614 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4615 return -ENODEV;
4616 }
1da177e4 4617 }
ec41c7df 4618 tp->nvram_lock_cnt++;
1da177e4
LT		 4619 }
4620 return 0;
4621}
4622
4623/* tp->lock is held. */
4624static void tg3_nvram_unlock(struct tg3 *tp)
4625{
ec41c7df
MC		 4626 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4627 if (tp->nvram_lock_cnt > 0)
4628 tp->nvram_lock_cnt--;
4629 if (tp->nvram_lock_cnt == 0)
4630 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4631 }
1da177e4
LT		 4632}
4633
e6af301b
MC		 4634/* tp->lock is held. */
4635static void tg3_enable_nvram_access(struct tg3 *tp)
4636{
4637 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4638 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4639 u32 nvaccess = tr32(NVRAM_ACCESS);
4640
4641 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4642 }
4643}
4644
4645/* tp->lock is held. */
4646static void tg3_disable_nvram_access(struct tg3 *tp)
4647{
4648 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4649 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4650 u32 nvaccess = tr32(NVRAM_ACCESS);
4651
4652 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4653 }
4654}
4655
1da177e4
LT		 4656/* tp->lock is held. */
4657static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4658{
f49639e6
DM		 4659 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4660 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 4661
4662 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4663 switch (kind) {
4664 case RESET_KIND_INIT:
4665 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4666 DRV_STATE_START);
4667 break;
4668
4669 case RESET_KIND_SHUTDOWN:
4670 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4671 DRV_STATE_UNLOAD);
4672 break;
4673
4674 case RESET_KIND_SUSPEND:
4675 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4676 DRV_STATE_SUSPEND);
4677 break;
4678
4679 default:
4680 break;
4681 };
4682 }
4683}
4684
4685/* tp->lock is held. */
4686static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4687{
4688 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4689 switch (kind) {
4690 case RESET_KIND_INIT:
4691 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4692 DRV_STATE_START_DONE);
4693 break;
4694
4695 case RESET_KIND_SHUTDOWN:
4696 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4697 DRV_STATE_UNLOAD_DONE);
4698 break;
4699
4700 default:
4701 break;
4702 };
4703 }
4704}
4705
4706/* tp->lock is held. */
4707static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4708{
4709 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4710 switch (kind) {
4711 case RESET_KIND_INIT:
4712 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4713 DRV_STATE_START);
4714 break;
4715
4716 case RESET_KIND_SHUTDOWN:
4717 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4718 DRV_STATE_UNLOAD);
4719 break;
4720
4721 case RESET_KIND_SUSPEND:
4722 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4723 DRV_STATE_SUSPEND);
4724 break;
4725
4726 default:
4727 break;
4728 };
4729 }
4730}
4731
7a6f4369
MC		 4732static int tg3_poll_fw(struct tg3 *tp)
4733{
4734 int i;
4735 u32 val;
4736
b5d3772c 4737 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 4738 /* Wait up to 20ms for init done. */
4739 for (i = 0; i < 200; i++) {
b5d3772c
MC		 4740 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4741 return 0;
0ccead18 4742 udelay(100);
b5d3772c
MC		 4743 }
4744 return -ENODEV;
4745 }
4746
7a6f4369
MC		 4747 /* Wait for firmware initialization to complete. */
4748 for (i = 0; i < 100000; i++) {
4749 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4750 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4751 break;
4752 udelay(10);
4753 }
4754
4755 /* Chip might not be fitted with firmware. Some Sun onboard
4756 * parts are configured like that. So don't signal the timeout
4757 * of the above loop as an error, but do report the lack of
4758 * running firmware once.
4759 */
4760 if (i >= 100000 &&
4761 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4762 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4763
4764 printk(KERN_INFO PFX "%s: No firmware running.\n",
4765 tp->dev->name);
4766 }
4767
4768 return 0;
4769}
4770
1da177e4
LT		 4771static void tg3_stop_fw(struct tg3 *);
4772
4773/* tp->lock is held. */
4774static int tg3_chip_reset(struct tg3 *tp)
4775{
4776 u32 val;
1ee582d8 4777 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 4778 int err;
1da177e4 4779
f49639e6
DM		 4780 tg3_nvram_lock(tp);
4781
4782 /* No matching tg3_nvram_unlock() after this because
4783 * chip reset below will undo the nvram lock.
4784 */
4785 tp->nvram_lock_cnt = 0;
1da177e4 4786
d9ab5ad1 4787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 4788 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1
MC		 4789 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4790 tw32(GRC_FASTBOOT_PC, 0);
4791
1da177e4
LT		 4792 /*
4793 * We must avoid the readl() that normally takes place.
4794 * It locks machines, causes machine checks, and other
4795 * fun things. So, temporarily disable the 5701
4796 * hardware workaround, while we do the reset.
4797 */
1ee582d8
MC		 4798 write_op = tp->write32;
4799 if (write_op == tg3_write_flush_reg32)
4800 tp->write32 = tg3_write32;
1da177e4
LT		 4801
4802 /* do the reset */
4803 val = GRC_MISC_CFG_CORECLK_RESET;
4804
4805 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4806 if (tr32(0x7e2c) == 0x60) {
4807 tw32(0x7e2c, 0x20);
4808 }
4809 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4810 tw32(GRC_MISC_CFG, (1 << 29));
4811 val |= (1 << 29);
4812 }
4813 }
4814
b5d3772c
MC		 4815 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4816 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4817 tw32(GRC_VCPU_EXT_CTRL,
4818 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4819 }
4820
1da177e4
LT		 4821 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4822 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4823 tw32(GRC_MISC_CFG, val);
4824
1ee582d8
MC		 4825 /* restore 5701 hardware bug workaround write method */
4826 tp->write32 = write_op;
1da177e4
LT		 4827
4828 /* Unfortunately, we have to delay before the PCI read back.
4829 * Some 575X chips even will not respond to a PCI cfg access
4830 * when the reset command is given to the chip.
4831 *
4832 * How do these hardware designers expect things to work
4833 * properly if the PCI write is posted for a long period
4834 * of time? It is always necessary to have some method by
4835 * which a register read back can occur to push the write
4836 * out which does the reset.
4837 *
4838 * For most tg3 variants the trick below was working.
4839 * Ho hum...
4840 */
4841 udelay(120);
4842
4843 /* Flush PCI posted writes. The normal MMIO registers
4844 * are inaccessible at this time so this is the only
4845 * way to make this reliably (actually, this is no longer
4846 * the case, see above). I tried to use indirect
4847 * register read/write but this upset some 5701 variants.
4848 */
4849 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4850
4851 udelay(120);
4852
4853 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4854 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4855 int i;
4856 u32 cfg_val;
4857
4858 /* Wait for link training to complete. */
4859 for (i = 0; i < 5000; i++)
4860 udelay(100);
4861
4862 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4863 pci_write_config_dword(tp->pdev, 0xc4,
4864 cfg_val | (1 << 15));
4865 }
4866 /* Set PCIE max payload size and clear error status. */
4867 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4868 }
4869
4870 /* Re-enable indirect register accesses. */
4871 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4872 tp->misc_host_ctrl);
4873
4874 /* Set MAX PCI retry to zero. */
4875 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4876 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4877 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4878 val |= PCISTATE_RETRY_SAME_DMA;
4879 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4880
4881 pci_restore_state(tp->pdev);
4882
4883 /* Make sure PCI-X relaxed ordering bit is clear. */
4884 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4885 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4886 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4887
a4e2b347 4888 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f
MC		 4889 u32 val;
4890
4891 /* Chip reset on 5780 will reset MSI enable bit,
4892 * so need to restore it.
4893 */
4894 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4895 u16 ctrl;
4896
4897 pci_read_config_word(tp->pdev,
4898 tp->msi_cap + PCI_MSI_FLAGS,
4899 &ctrl);
4900 pci_write_config_word(tp->pdev,
4901 tp->msi_cap + PCI_MSI_FLAGS,
4902 ctrl | PCI_MSI_FLAGS_ENABLE);
4903 val = tr32(MSGINT_MODE);
4904 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4905 }
4906
4907 val = tr32(MEMARB_MODE);
4908 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4909
4910 } else
4911 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4912
4913 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4914 tg3_stop_fw(tp);
4915 tw32(0x5000, 0x400);
4916 }
4917
4918 tw32(GRC_MODE, tp->grc_mode);
4919
4920 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4921 u32 val = tr32(0xc4);
4922
4923 tw32(0xc4, val | (1 << 15));
4924 }
4925
4926 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4928 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4929 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4930 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4931 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4932 }
4933
4934 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4935 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4936 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4937 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4938 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4939 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4940 } else
4941 tw32_f(MAC_MODE, 0);
4942 udelay(40);
4943
7a6f4369
MC		 4944 err = tg3_poll_fw(tp);
4945 if (err)
4946 return err;
1da177e4
LT		 4947
4948 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4949 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4950 u32 val = tr32(0x7c00);
4951
4952 tw32(0x7c00, val | (1 << 25));
4953 }
4954
4955 /* Reprobe ASF enable state. */
4956 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4957 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4958 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4959 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4960 u32 nic_cfg;
4961
4962 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4963 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4964 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4965 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4966 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4967 }
4968 }
4969
4970 return 0;
4971}
4972
4973/* tp->lock is held. */
4974static void tg3_stop_fw(struct tg3 *tp)
4975{
4976 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4977 u32 val;
4978 int i;
4979
4980 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4981 val = tr32(GRC_RX_CPU_EVENT);
4982 val |= (1 << 14);
4983 tw32(GRC_RX_CPU_EVENT, val);
4984
4985 /* Wait for RX cpu to ACK the event. */
4986 for (i = 0; i < 100; i++) {
4987 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4988 break;
4989 udelay(1);
4990 }
4991 }
4992}
4993
4994/* tp->lock is held. */
944d980e 4995static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 4996{
4997 int err;
4998
4999 tg3_stop_fw(tp);
5000
944d980e 5001 tg3_write_sig_pre_reset(tp, kind);
1da177e4 5002
b3b7d6be 5003 tg3_abort_hw(tp, silent);
1da177e4
LT		 5004 err = tg3_chip_reset(tp);
5005
944d980e
MC		 5006 tg3_write_sig_legacy(tp, kind);
5007 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 5008
5009 if (err)
5010 return err;
5011
5012 return 0;
5013}
5014
5015#define TG3_FW_RELEASE_MAJOR 0x0
5016#define TG3_FW_RELASE_MINOR 0x0
5017#define TG3_FW_RELEASE_FIX 0x0
5018#define TG3_FW_START_ADDR 0x08000000
5019#define TG3_FW_TEXT_ADDR 0x08000000
5020#define TG3_FW_TEXT_LEN 0x9c0
5021#define TG3_FW_RODATA_ADDR 0x080009c0
5022#define TG3_FW_RODATA_LEN 0x60
5023#define TG3_FW_DATA_ADDR 0x08000a40
5024#define TG3_FW_DATA_LEN 0x20
5025#define TG3_FW_SBSS_ADDR 0x08000a60
5026#define TG3_FW_SBSS_LEN 0xc
5027#define TG3_FW_BSS_ADDR 0x08000a70
5028#define TG3_FW_BSS_LEN 0x10
5029
50da859d 5030static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5031 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5032 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5033 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5034 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5035 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5036 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5037 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5038 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5039 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5040 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5041 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5042 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5043 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5044 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5045 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5046 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5047 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5048 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5049 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5050 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5051 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5052 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5053 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5054 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5055 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5056 0, 0, 0, 0, 0, 0,
5057 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5058 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5059 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5060 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5061 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5062 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5063 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5064 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5065 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5066 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5067 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5068 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5069 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5070 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5071 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5072 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5073 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5074 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5075 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5076 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5077 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5078 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5079 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5080 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5081 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5082 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5083 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5084 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5085 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5086 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5087 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5088 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5089 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5090 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5091 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5092 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5093 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5094 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5095 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5096 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5097 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5098 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5099 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5100 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5101 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5102 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5103 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5104 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5105 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5106 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5107 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5108 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5109 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5110 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5111 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5112 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5113 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5114 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5115 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5116 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5117 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5118 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5119 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5120 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5121 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5122};
5123
50da859d 5124static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5125 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5126 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5127 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5128 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5129 0x00000000
5130};
5131
5132#if 0 /* All zeros, don't eat up space with it. */
5133u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5134 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5135 0x00000000, 0x00000000, 0x00000000, 0x00000000
5136};
5137#endif
5138
5139#define RX_CPU_SCRATCH_BASE 0x30000
5140#define RX_CPU_SCRATCH_SIZE 0x04000
5141#define TX_CPU_SCRATCH_BASE 0x34000
5142#define TX_CPU_SCRATCH_SIZE 0x04000
5143
5144/* tp->lock is held. */
5145static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5146{
5147 int i;
5148
5d9428de
ES		 5149 BUG_ON(offset == TX_CPU_BASE &&
5150 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 5151
b5d3772c
MC		 5152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5153 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5154
5155 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5156 return 0;
5157 }
1da177e4
LT		 5158 if (offset == RX_CPU_BASE) {
5159 for (i = 0; i < 10000; i++) {
5160 tw32(offset + CPU_STATE, 0xffffffff);
5161 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5162 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5163 break;
5164 }
5165
5166 tw32(offset + CPU_STATE, 0xffffffff);
5167 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5168 udelay(10);
5169 } else {
5170 for (i = 0; i < 10000; i++) {
5171 tw32(offset + CPU_STATE, 0xffffffff);
5172 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5173 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5174 break;
5175 }
5176 }
5177
5178 if (i >= 10000) {
5179 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5180 "and %s CPU\n",
5181 tp->dev->name,
5182 (offset == RX_CPU_BASE ? "RX" : "TX"));
5183 return -ENODEV;
5184 }
ec41c7df
MC		 5185
5186 /* Clear firmware's nvram arbitration. */
5187 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5188 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 5189 return 0;
5190}
5191
5192struct fw_info {
5193 unsigned int text_base;
5194 unsigned int text_len;
50da859d 5195 const u32 *text_data;
1da177e4
LT		 5196 unsigned int rodata_base;
5197 unsigned int rodata_len;
50da859d 5198 const u32 *rodata_data;
1da177e4
LT		 5199 unsigned int data_base;
5200 unsigned int data_len;
50da859d 5201 const u32 *data_data;
1da177e4
LT		 5202};
5203
5204/* tp->lock is held. */
5205static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5206 int cpu_scratch_size, struct fw_info *info)
5207{
ec41c7df 5208 int err, lock_err, i;
1da177e4
LT		 5209 void (*write_op)(struct tg3 *, u32, u32);
5210
5211 if (cpu_base == TX_CPU_BASE &&
5212 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5213 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5214 "TX cpu firmware on %s which is 5705.\n",
5215 tp->dev->name);
5216 return -EINVAL;
5217 }
5218
5219 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5220 write_op = tg3_write_mem;
5221 else
5222 write_op = tg3_write_indirect_reg32;
5223
1b628151
MC		 5224 /* It is possible that bootcode is still loading at this point.
5225 * Get the nvram lock first before halting the cpu.
5226 */
ec41c7df 5227 lock_err = tg3_nvram_lock(tp);
1da177e4 5228 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 5229 if (!lock_err)
5230 tg3_nvram_unlock(tp);
1da177e4
LT		 5231 if (err)
5232 goto out;
5233
5234 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5235 write_op(tp, cpu_scratch_base + i, 0);
5236 tw32(cpu_base + CPU_STATE, 0xffffffff);
5237 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5238 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5239 write_op(tp, (cpu_scratch_base +
5240 (info->text_base & 0xffff) +
5241 (i * sizeof(u32))),
5242 (info->text_data ?
5243 info->text_data[i] : 0));
5244 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5245 write_op(tp, (cpu_scratch_base +
5246 (info->rodata_base & 0xffff) +
5247 (i * sizeof(u32))),
5248 (info->rodata_data ?
5249 info->rodata_data[i] : 0));
5250 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5251 write_op(tp, (cpu_scratch_base +
5252 (info->data_base & 0xffff) +
5253 (i * sizeof(u32))),
5254 (info->data_data ?
5255 info->data_data[i] : 0));
5256
5257 err = 0;
5258
5259out:
1da177e4
LT		 5260 return err;
5261}
5262
5263/* tp->lock is held. */
5264static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5265{
5266 struct fw_info info;
5267 int err, i;
5268
5269 info.text_base = TG3_FW_TEXT_ADDR;
5270 info.text_len = TG3_FW_TEXT_LEN;
5271 info.text_data = &tg3FwText[0];
5272 info.rodata_base = TG3_FW_RODATA_ADDR;
5273 info.rodata_len = TG3_FW_RODATA_LEN;
5274 info.rodata_data = &tg3FwRodata[0];
5275 info.data_base = TG3_FW_DATA_ADDR;
5276 info.data_len = TG3_FW_DATA_LEN;
5277 info.data_data = NULL;
5278
5279 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5280 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5281 &info);
5282 if (err)
5283 return err;
5284
5285 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5286 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5287 &info);
5288 if (err)
5289 return err;
5290
5291 /* Now startup only the RX cpu. */
5292 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5293 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5294
5295 for (i = 0; i < 5; i++) {
5296 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5297 break;
5298 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5299 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5300 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5301 udelay(1000);
5302 }
5303 if (i >= 5) {
5304 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5305 "to set RX CPU PC, is %08x should be %08x\n",
5306 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5307 TG3_FW_TEXT_ADDR);
5308 return -ENODEV;
5309 }
5310 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5311 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5312
5313 return 0;
5314}
5315
1da177e4
LT		 5316
5317#define TG3_TSO_FW_RELEASE_MAJOR 0x1
5318#define TG3_TSO_FW_RELASE_MINOR 0x6
5319#define TG3_TSO_FW_RELEASE_FIX 0x0
5320#define TG3_TSO_FW_START_ADDR 0x08000000
5321#define TG3_TSO_FW_TEXT_ADDR 0x08000000
5322#define TG3_TSO_FW_TEXT_LEN 0x1aa0
5323#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5324#define TG3_TSO_FW_RODATA_LEN 0x60
5325#define TG3_TSO_FW_DATA_ADDR 0x08001b20
5326#define TG3_TSO_FW_DATA_LEN 0x30
5327#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5328#define TG3_TSO_FW_SBSS_LEN 0x2c
5329#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5330#define TG3_TSO_FW_BSS_LEN 0x894
5331
50da859d 5332static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5333 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5334 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5335 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5336 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5337 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5338 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5339 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5340 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5341 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5342 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5343 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5344 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5345 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5346 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5347 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5348 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5349 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5350 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5351 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5352 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5353 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5354 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5355 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5356 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5357 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5358 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5359 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5360 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5361 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5362 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5363 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5364 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5365 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5366 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5367 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5368 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5369 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5370 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5371 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5372 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5373 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5374 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5375 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5376 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5377 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5378 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5379 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5380 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5381 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5382 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5383 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5384 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5385 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5386 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5387 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5388 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5389 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5390 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5391 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5392 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5393 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5394 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5395 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5396 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5397 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5398 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5399 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5400 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5401 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5402 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5403 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5404 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5405 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5406 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5407 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5408 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5409 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5410 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5411 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5412 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5413 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5414 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5415 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5416 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5417 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5418 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5419 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5420 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5421 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5422 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5423 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5424 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5425 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5426 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5427 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5428 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5429 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5430 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5431 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5432 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5433 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5434 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5435 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5436 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5437 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5438 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5439 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5440 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5441 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5442 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5443 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5444 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5445 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5446 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5447 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5448 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5449 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5450 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5451 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5452 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5453 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5454 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5455 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5456 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5457 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5458 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5459 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5460 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5461 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5462 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5463 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5464 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5465 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5466 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5467 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5468 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5469 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5470 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5471 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5472 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5473 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5474 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5475 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5476 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5477 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5478 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5479 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5480 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5481 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5482 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5483 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5484 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5485 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5486 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5487 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5488 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5489 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5490 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5491 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5492 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5493 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5494 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5495 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5496 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5497 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5498 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5499 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5500 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5501 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5502 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5503 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5504 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5505 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5506 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5507 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5508 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5509 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5510 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5511 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5512 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5513 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5514 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5515 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5516 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5517 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5518 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5519 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5520 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5521 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5522 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5523 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5524 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5525 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5526 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5527 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5528 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5529 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5530 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5531 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5532 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5533 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5534 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5535 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5536 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5537 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5538 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5539 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5540 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5541 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5542 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5543 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5544 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5545 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5546 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5547 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5548 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5549 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5550 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5551 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5552 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5553 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5554 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5555 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5556 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5557 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5558 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5559 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5560 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5561 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5562 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5563 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5564 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5565 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5566 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5567 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5568 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5569 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5570 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5571 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5572 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5573 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5574 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5575 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5576 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5577 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5578 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5579 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5580 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5581 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5582 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5583 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5584 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5585 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5586 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5587 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5588 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5589 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5590 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5591 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5592 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5593 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5594 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5595 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5596 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5597 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5598 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5599 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5600 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5601 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5602 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5603 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5604 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5605 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5606 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5607 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5608 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5609 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5610 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5611 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5612 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5613 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5614 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5615 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5616 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5617};
5618
50da859d 5619static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 5620 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5621 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5622 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5623 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5624 0x00000000,
5625};
5626
50da859d 5627static const u32 tg3TsoFwData[] = {
1da177e4
LT		 5628 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5629 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5630 0x00000000,
5631};
5632
5633/* 5705 needs a special version of the TSO firmware. */
5634#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5635#define TG3_TSO5_FW_RELASE_MINOR 0x2
5636#define TG3_TSO5_FW_RELEASE_FIX 0x0
5637#define TG3_TSO5_FW_START_ADDR 0x00010000
5638#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5639#define TG3_TSO5_FW_TEXT_LEN 0xe90
5640#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5641#define TG3_TSO5_FW_RODATA_LEN 0x50
5642#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5643#define TG3_TSO5_FW_DATA_LEN 0x20
5644#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5645#define TG3_TSO5_FW_SBSS_LEN 0x28
5646#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5647#define TG3_TSO5_FW_BSS_LEN 0x88
5648
50da859d 5649static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5650 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5651 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5652 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5653 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5654 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5655 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5656 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5657 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5658 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5659 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5660 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5661 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5662 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5663 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5664 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5665 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5666 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5667 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5668 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5669 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5670 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5671 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5672 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5673 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5674 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5675 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5676 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5677 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5678 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5679 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5680 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5681 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5682 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5683 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5684 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5685 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5686 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5687 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5688 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5689 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5690 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5691 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5692 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5693 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5694 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5695 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5696 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5697 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5698 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5699 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5700 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5701 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5702 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5703 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5704 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5705 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5706 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5707 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5708 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5709 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5710 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5711 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5712 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5713 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5714 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5715 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5716 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5717 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5718 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5719 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5720 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5721 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5722 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5723 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5724 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5725 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5726 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5727 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5728 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5729 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5730 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5731 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5732 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5733 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5734 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5735 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5736 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5737 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5738 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5739 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5740 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5741 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5742 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5743 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5744 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5745 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5746 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5747 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5748 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5749 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5750 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5751 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5752 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5753 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5754 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5755 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5756 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5757 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5758 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5759 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5760 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5761 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5762 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5763 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5764 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5765 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5766 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5767 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5768 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5769 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5770 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5771 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5772 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5773 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5774 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5775 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5776 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5777 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5778 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5779 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5780 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5781 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5782 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5783 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5784 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5785 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5786 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5787 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5788 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5789 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5790 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5791 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5792 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5793 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5794 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5795 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5796 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5797 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5798 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5799 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5800 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5801 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5802 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5803 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5804 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5805 0x00000000, 0x00000000, 0x00000000,
5806};
5807
50da859d 5808static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 5809 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5810 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5811 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5812 0x00000000, 0x00000000, 0x00000000,
5813};
5814
50da859d 5815static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 5816 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5817 0x00000000, 0x00000000, 0x00000000,
5818};
5819
5820/* tp->lock is held. */
5821static int tg3_load_tso_firmware(struct tg3 *tp)
5822{
5823 struct fw_info info;
5824 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5825 int err, i;
5826
5827 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5828 return 0;
5829
5830 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5831 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5832 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5833 info.text_data = &tg3Tso5FwText[0];
5834 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5835 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5836 info.rodata_data = &tg3Tso5FwRodata[0];
5837 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5838 info.data_len = TG3_TSO5_FW_DATA_LEN;
5839 info.data_data = &tg3Tso5FwData[0];
5840 cpu_base = RX_CPU_BASE;
5841 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5842 cpu_scratch_size = (info.text_len +
5843 info.rodata_len +
5844 info.data_len +
5845 TG3_TSO5_FW_SBSS_LEN +
5846 TG3_TSO5_FW_BSS_LEN);
5847 } else {
5848 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5849 info.text_len = TG3_TSO_FW_TEXT_LEN;
5850 info.text_data = &tg3TsoFwText[0];
5851 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5852 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5853 info.rodata_data = &tg3TsoFwRodata[0];
5854 info.data_base = TG3_TSO_FW_DATA_ADDR;
5855 info.data_len = TG3_TSO_FW_DATA_LEN;
5856 info.data_data = &tg3TsoFwData[0];
5857 cpu_base = TX_CPU_BASE;
5858 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5859 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5860 }
5861
5862 err = tg3_load_firmware_cpu(tp, cpu_base,
5863 cpu_scratch_base, cpu_scratch_size,
5864 &info);
5865 if (err)
5866 return err;
5867
5868 /* Now startup the cpu. */
5869 tw32(cpu_base + CPU_STATE, 0xffffffff);
5870 tw32_f(cpu_base + CPU_PC, info.text_base);
5871
5872 for (i = 0; i < 5; i++) {
5873 if (tr32(cpu_base + CPU_PC) == info.text_base)
5874 break;
5875 tw32(cpu_base + CPU_STATE, 0xffffffff);
5876 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5877 tw32_f(cpu_base + CPU_PC, info.text_base);
5878 udelay(1000);
5879 }
5880 if (i >= 5) {
5881 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5882 "to set CPU PC, is %08x should be %08x\n",
5883 tp->dev->name, tr32(cpu_base + CPU_PC),
5884 info.text_base);
5885 return -ENODEV;
5886 }
5887 tw32(cpu_base + CPU_STATE, 0xffffffff);
5888 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5889 return 0;
5890}
5891
1da177e4
LT		 5892
5893/* tp->lock is held. */
5894static void __tg3_set_mac_addr(struct tg3 *tp)
5895{
5896 u32 addr_high, addr_low;
5897 int i;
5898
5899 addr_high = ((tp->dev->dev_addr[0] << 8) |
5900 tp->dev->dev_addr[1]);
5901 addr_low = ((tp->dev->dev_addr[2] << 24) |
5902 (tp->dev->dev_addr[3] << 16) |
5903 (tp->dev->dev_addr[4] << 8) |
5904 (tp->dev->dev_addr[5] << 0));
5905 for (i = 0; i < 4; i++) {
5906 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5907 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5908 }
5909
5910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5911 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5912 for (i = 0; i < 12; i++) {
5913 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5914 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5915 }
5916 }
5917
5918 addr_high = (tp->dev->dev_addr[0] +
5919 tp->dev->dev_addr[1] +
5920 tp->dev->dev_addr[2] +
5921 tp->dev->dev_addr[3] +
5922 tp->dev->dev_addr[4] +
5923 tp->dev->dev_addr[5]) &
5924 TX_BACKOFF_SEED_MASK;
5925 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5926}
5927
5928static int tg3_set_mac_addr(struct net_device *dev, void *p)
5929{
5930 struct tg3 *tp = netdev_priv(dev);
5931 struct sockaddr *addr = p;
b9ec6c1b 5932 int err = 0;
1da177e4 5933
f9804ddb
MC		 5934 if (!is_valid_ether_addr(addr->sa_data))
5935 return -EINVAL;
5936
1da177e4
LT		 5937 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5938
e75f7c90
MC		 5939 if (!netif_running(dev))
5940 return 0;
5941
58712ef9
MC		 5942 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5943 /* Reset chip so that ASF can re-init any MAC addresses it
5944 * needs.
5945 */
5946 tg3_netif_stop(tp);
5947 tg3_full_lock(tp, 1);
5948
5949 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 5950 err = tg3_restart_hw(tp, 0);
5951 if (!err)
5952 tg3_netif_start(tp);
58712ef9
MC		 5953 tg3_full_unlock(tp);
5954 } else {
5955 spin_lock_bh(&tp->lock);
5956 __tg3_set_mac_addr(tp);
5957 spin_unlock_bh(&tp->lock);
5958 }
1da177e4 5959
b9ec6c1b 5960 return err;
1da177e4
LT		 5961}
5962
5963/* tp->lock is held. */
5964static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5965 dma_addr_t mapping, u32 maxlen_flags,
5966 u32 nic_addr)
5967{
5968 tg3_write_mem(tp,
5969 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5970 ((u64) mapping >> 32));
5971 tg3_write_mem(tp,
5972 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5973 ((u64) mapping & 0xffffffff));
5974 tg3_write_mem(tp,
5975 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5976 maxlen_flags);
5977
5978 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5979 tg3_write_mem(tp,
5980 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5981 nic_addr);
5982}
5983
5984static void __tg3_set_rx_mode(struct net_device *);
d244c892 5985static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 5986{
5987 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5988 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5989 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5990 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5991 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5992 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5993 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5994 }
5995 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5996 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5997 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5998 u32 val = ec->stats_block_coalesce_usecs;
5999
6000 if (!netif_carrier_ok(tp->dev))
6001 val = 0;
6002
6003 tw32(HOSTCC_STAT_COAL_TICKS, val);
6004 }
6005}
1da177e4
LT		 6006
6007/* tp->lock is held. */
8e7a22e3 6008static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6009{
6010 u32 val, rdmac_mode;
6011 int i, err, limit;
6012
6013 tg3_disable_ints(tp);
6014
6015 tg3_stop_fw(tp);
6016
6017 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6018
6019 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6020 tg3_abort_hw(tp, 1);
1da177e4
LT		 6021 }
6022
36da4d86 6023 if (reset_phy)
d4d2c558
MC		 6024 tg3_phy_reset(tp);
6025
1da177e4
LT		 6026 err = tg3_chip_reset(tp);
6027 if (err)
6028 return err;
6029
6030 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6031
6032 /* This works around an issue with Athlon chipsets on
6033 * B3 tigon3 silicon. This bit has no effect on any
6034 * other revision. But do not set this on PCI Express
6035 * chips.
6036 */
6037 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6038 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6039 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6040
6041 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6042 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6043 val = tr32(TG3PCI_PCISTATE);
6044 val |= PCISTATE_RETRY_SAME_DMA;
6045 tw32(TG3PCI_PCISTATE, val);
6046 }
6047
6048 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6049 /* Enable some hw fixes. */
6050 val = tr32(TG3PCI_MSI_DATA);
6051 val |= (1 << 26) | (1 << 28) | (1 << 29);
6052 tw32(TG3PCI_MSI_DATA, val);
6053 }
6054
6055 /* Descriptor ring init may make accesses to the
6056 * NIC SRAM area to setup the TX descriptors, so we
6057 * can only do this after the hardware has been
6058 * successfully reset.
6059 */
32d8c572
MC		 6060 err = tg3_init_rings(tp);
6061 if (err)
6062 return err;
1da177e4
LT		 6063
6064 /* This value is determined during the probe time DMA
6065 * engine test, tg3_test_dma.
6066 */
6067 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6068
6069 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6070 GRC_MODE_4X_NIC_SEND_RINGS |
6071 GRC_MODE_NO_TX_PHDR_CSUM |
6072 GRC_MODE_NO_RX_PHDR_CSUM);
6073 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6074
6075 /* Pseudo-header checksum is done by hardware logic and not
6076 * the offload processers, so make the chip do the pseudo-
6077 * header checksums on receive. For transmit it is more
6078 * convenient to do the pseudo-header checksum in software
6079 * as Linux does that on transmit for us in all cases.
6080 */
6081 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6082
6083 tw32(GRC_MODE,
6084 tp->grc_mode |
6085 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6086
6087 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6088 val = tr32(GRC_MISC_CFG);
6089 val &= ~0xff;
6090 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6091 tw32(GRC_MISC_CFG, val);
6092
6093 /* Initialize MBUF/DESC pool. */
cbf46853 6094 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6095 /* Do nothing. */
6096 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6097 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6099 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6100 else
6101 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6102 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6103 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6104 }
1da177e4
LT		 6105 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6106 int fw_len;
6107
6108 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6109 TG3_TSO5_FW_RODATA_LEN +
6110 TG3_TSO5_FW_DATA_LEN +
6111 TG3_TSO5_FW_SBSS_LEN +
6112 TG3_TSO5_FW_BSS_LEN);
6113 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6114 tw32(BUFMGR_MB_POOL_ADDR,
6115 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6116 tw32(BUFMGR_MB_POOL_SIZE,
6117 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6118 }
1da177e4 6119
0f893dc6 6120 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6121 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6122 tp->bufmgr_config.mbuf_read_dma_low_water);
6123 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6124 tp->bufmgr_config.mbuf_mac_rx_low_water);
6125 tw32(BUFMGR_MB_HIGH_WATER,
6126 tp->bufmgr_config.mbuf_high_water);
6127 } else {
6128 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6129 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6130 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6131 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6132 tw32(BUFMGR_MB_HIGH_WATER,
6133 tp->bufmgr_config.mbuf_high_water_jumbo);
6134 }
6135 tw32(BUFMGR_DMA_LOW_WATER,
6136 tp->bufmgr_config.dma_low_water);
6137 tw32(BUFMGR_DMA_HIGH_WATER,
6138 tp->bufmgr_config.dma_high_water);
6139
6140 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6141 for (i = 0; i < 2000; i++) {
6142 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6143 break;
6144 udelay(10);
6145 }
6146 if (i >= 2000) {
6147 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6148 tp->dev->name);
6149 return -ENODEV;
6150 }
6151
6152 /* Setup replenish threshold. */
f92905de
MC		 6153 val = tp->rx_pending / 8;
6154 if (val == 0)
6155 val = 1;
6156 else if (val > tp->rx_std_max_post)
6157 val = tp->rx_std_max_post;
b5d3772c
MC		 6158 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6159 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6160 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6161
6162 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6163 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6164 }
f92905de
MC		 6165
6166 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6167
6168 /* Initialize TG3_BDINFO's at:
6169 * RCVDBDI_STD_BD: standard eth size rx ring
6170 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6171 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6172 *
6173 * like so:
6174 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6175 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6176 * ring attribute flags
6177 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6178 *
6179 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6180 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6181 *
6182 * The size of each ring is fixed in the firmware, but the location is
6183 * configurable.
6184 */
6185 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6186 ((u64) tp->rx_std_mapping >> 32));
6187 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6188 ((u64) tp->rx_std_mapping & 0xffffffff));
6189 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6190 NIC_SRAM_RX_BUFFER_DESC);
6191
6192 /* Don't even try to program the JUMBO/MINI buffer descriptor
6193 * configs on 5705.
6194 */
6195 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6196 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6197 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6198 } else {
6199 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6200 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6201
6202 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6203 BDINFO_FLAGS_DISABLED);
6204
6205 /* Setup replenish threshold. */
6206 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6207
0f893dc6 6208 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6209 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6210 ((u64) tp->rx_jumbo_mapping >> 32));
6211 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6212 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6213 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6214 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6215 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6216 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6217 } else {
6218 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6219 BDINFO_FLAGS_DISABLED);
6220 }
6221
6222 }
6223
6224 /* There is only one send ring on 5705/5750, no need to explicitly
6225 * disable the others.
6226 */
6227 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6228 /* Clear out send RCB ring in SRAM. */
6229 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6230 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6231 BDINFO_FLAGS_DISABLED);
6232 }
6233
6234 tp->tx_prod = 0;
6235 tp->tx_cons = 0;
6236 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6237 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6238
6239 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6240 tp->tx_desc_mapping,
6241 (TG3_TX_RING_SIZE <<
6242 BDINFO_FLAGS_MAXLEN_SHIFT),
6243 NIC_SRAM_TX_BUFFER_DESC);
6244
6245 /* There is only one receive return ring on 5705/5750, no need
6246 * to explicitly disable the others.
6247 */
6248 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6249 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6250 i += TG3_BDINFO_SIZE) {
6251 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6252 BDINFO_FLAGS_DISABLED);
6253 }
6254 }
6255
6256 tp->rx_rcb_ptr = 0;
6257 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6258
6259 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6260 tp->rx_rcb_mapping,
6261 (TG3_RX_RCB_RING_SIZE(tp) <<
6262 BDINFO_FLAGS_MAXLEN_SHIFT),
6263 0);
6264
6265 tp->rx_std_ptr = tp->rx_pending;
6266 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6267 tp->rx_std_ptr);
6268
0f893dc6 6269 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6270 tp->rx_jumbo_pending : 0;
6271 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6272 tp->rx_jumbo_ptr);
6273
6274 /* Initialize MAC address and backoff seed. */
6275 __tg3_set_mac_addr(tp);
6276
6277 /* MTU + ethernet header + FCS + optional VLAN tag */
6278 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6279
6280 /* The slot time is changed by tg3_setup_phy if we
6281 * run at gigabit with half duplex.
6282 */
6283 tw32(MAC_TX_LENGTHS,
6284 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6285 (6 << TX_LENGTHS_IPG_SHIFT) |
6286 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6287
6288 /* Receive rules. */
6289 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6290 tw32(RCVLPC_CONFIG, 0x0181);
6291
6292 /* Calculate RDMAC_MODE setting early, we need it to determine
6293 * the RCVLPC_STATE_ENABLE mask.
6294 */
6295 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6296 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6297 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6298 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6299 RDMAC_MODE_LNGREAD_ENAB);
6300 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6301 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 6302
6303 /* If statement applies to 5705 and 5750 PCI devices only */
6304 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6305 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6306 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 6307 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6308 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6309 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6310 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6311 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6312 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6313 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6314 }
6315 }
6316
85e94ced
MC		 6317 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6318 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6319
1da177e4
LT		 6320 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6321 rdmac_mode |= (1 << 27);
1da177e4
LT		 6322
6323 /* Receive/send statistics. */
1661394e
MC		 6324 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6325 val = tr32(RCVLPC_STATS_ENABLE);
6326 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6327 tw32(RCVLPC_STATS_ENABLE, val);
6328 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6329 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6330 val = tr32(RCVLPC_STATS_ENABLE);
6331 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6332 tw32(RCVLPC_STATS_ENABLE, val);
6333 } else {
6334 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6335 }
6336 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6337 tw32(SNDDATAI_STATSENAB, 0xffffff);
6338 tw32(SNDDATAI_STATSCTRL,
6339 (SNDDATAI_SCTRL_ENABLE |
6340 SNDDATAI_SCTRL_FASTUPD));
6341
6342 /* Setup host coalescing engine. */
6343 tw32(HOSTCC_MODE, 0);
6344 for (i = 0; i < 2000; i++) {
6345 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6346 break;
6347 udelay(10);
6348 }
6349
d244c892 6350 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6351
6352 /* set status block DMA address */
6353 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6354 ((u64) tp->status_mapping >> 32));
6355 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6356 ((u64) tp->status_mapping & 0xffffffff));
6357
6358 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6359 /* Status/statistics block address. See tg3_timer,
6360 * the tg3_periodic_fetch_stats call there, and
6361 * tg3_get_stats to see how this works for 5705/5750 chips.
6362 */
1da177e4
LT		 6363 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6364 ((u64) tp->stats_mapping >> 32));
6365 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6366 ((u64) tp->stats_mapping & 0xffffffff));
6367 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6368 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6369 }
6370
6371 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6372
6373 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6374 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6375 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6376 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6377
6378 /* Clear statistics/status block in chip, and status block in ram. */
6379 for (i = NIC_SRAM_STATS_BLK;
6380 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6381 i += sizeof(u32)) {
6382 tg3_write_mem(tp, i, 0);
6383 udelay(40);
6384 }
6385 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6386
c94e3941
MC		 6387 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6388 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6389 /* reset to prevent losing 1st rx packet intermittently */
6390 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6391 udelay(10);
6392 }
6393
1da177e4
LT		 6394 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6395 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6396 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6397 udelay(40);
6398
314fba34 6399 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6400 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6401 * register to preserve the GPIO settings for LOMs. The GPIOs,
6402 * whether used as inputs or outputs, are set by boot code after
6403 * reset.
6404 */
9d26e213 6405 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6406 u32 gpio_mask;
6407
9d26e213
MC		 6408 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6409 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6410 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6411
6412 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6413 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6414 GRC_LCLCTRL_GPIO_OUTPUT3;
6415
af36e6b6
MC		 6416 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6417 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6418
314fba34
MC		 6419 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6420
6421 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6422 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6423 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6424 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6425 }
1da177e4
LT		 6426 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6427 udelay(100);
6428
09ee929c 6429 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 6430 tp->last_tag = 0;
1da177e4
LT		 6431
6432 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6433 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6434 udelay(40);
6435 }
6436
6437 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6438 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6439 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6440 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6441 WDMAC_MODE_LNGREAD_ENAB);
6442
85e94ced
MC		 6443 /* If statement applies to 5705 and 5750 PCI devices only */
6444 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6445 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6446 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 6447 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6448 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6449 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6450 /* nothing */
6451 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6452 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6453 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6454 val |= WDMAC_MODE_RX_ACCEL;
6455 }
6456 }
6457
d9ab5ad1 6458 /* Enable host coalescing bug fix */
af36e6b6
MC		 6459 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6460 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
d9ab5ad1
MC		 6461 val |= (1 << 29);
6462
1da177e4
LT		 6463 tw32_f(WDMAC_MODE, val);
6464 udelay(40);
6465
6466 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6467 val = tr32(TG3PCI_X_CAPS);
6468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6469 val &= ~PCIX_CAPS_BURST_MASK;
6470 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6471 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6472 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6473 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6474 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6475 val |= (tp->split_mode_max_reqs <<
6476 PCIX_CAPS_SPLIT_SHIFT);
6477 }
6478 tw32(TG3PCI_X_CAPS, val);
6479 }
6480
6481 tw32_f(RDMAC_MODE, rdmac_mode);
6482 udelay(40);
6483
6484 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6485 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6486 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6487 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6488 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6489 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6490 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6491 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 6492 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6493 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 6494 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6495 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6496
6497 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6498 err = tg3_load_5701_a0_firmware_fix(tp);
6499 if (err)
6500 return err;
6501 }
6502
1da177e4
LT		 6503 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6504 err = tg3_load_tso_firmware(tp);
6505 if (err)
6506 return err;
6507 }
1da177e4
LT		 6508
6509 tp->tx_mode = TX_MODE_ENABLE;
6510 tw32_f(MAC_TX_MODE, tp->tx_mode);
6511 udelay(100);
6512
6513 tp->rx_mode = RX_MODE_ENABLE;
af36e6b6
MC		 6514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6515 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6516
1da177e4
LT		 6517 tw32_f(MAC_RX_MODE, tp->rx_mode);
6518 udelay(10);
6519
6520 if (tp->link_config.phy_is_low_power) {
6521 tp->link_config.phy_is_low_power = 0;
6522 tp->link_config.speed = tp->link_config.orig_speed;
6523 tp->link_config.duplex = tp->link_config.orig_duplex;
6524 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6525 }
6526
6527 tp->mi_mode = MAC_MI_MODE_BASE;
6528 tw32_f(MAC_MI_MODE, tp->mi_mode);
6529 udelay(80);
6530
6531 tw32(MAC_LED_CTRL, tp->led_ctrl);
6532
6533 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6534 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6535 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6536 udelay(10);
6537 }
6538 tw32_f(MAC_RX_MODE, tp->rx_mode);
6539 udelay(10);
6540
6541 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6542 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6543 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6544 /* Set drive transmission level to 1.2V */
6545 /* only if the signal pre-emphasis bit is not set */
6546 val = tr32(MAC_SERDES_CFG);
6547 val &= 0xfffff000;
6548 val |= 0x880;
6549 tw32(MAC_SERDES_CFG, val);
6550 }
6551 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6552 tw32(MAC_SERDES_CFG, 0x616000);
6553 }
6554
6555 /* Prevent chip from dropping frames when flow control
6556 * is enabled.
6557 */
6558 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6559
6560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6561 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6562 /* Use hardware link auto-negotiation */
6563 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6564 }
6565
d4d2c558
MC		 6566 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6567 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6568 u32 tmp;
6569
6570 tmp = tr32(SERDES_RX_CTRL);
6571 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6572 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6573 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6574 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6575 }
6576
36da4d86 6577 err = tg3_setup_phy(tp, 0);
1da177e4
LT		 6578 if (err)
6579 return err;
6580
715116a1
MC		 6581 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6582 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1da177e4
LT		 6583 u32 tmp;
6584
6585 /* Clear CRC stats. */
6586 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6587 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6588 tg3_readphy(tp, 0x14, &tmp);
6589 }
6590 }
6591
6592 __tg3_set_rx_mode(tp->dev);
6593
6594 /* Initialize receive rules. */
6595 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6596 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6597 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6598 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6599
4cf78e4f 6600 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 6601 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 6602 limit = 8;
6603 else
6604 limit = 16;
6605 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6606 limit -= 4;
6607 switch (limit) {
6608 case 16:
6609 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6610 case 15:
6611 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6612 case 14:
6613 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6614 case 13:
6615 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6616 case 12:
6617 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6618 case 11:
6619 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6620 case 10:
6621 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6622 case 9:
6623 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6624 case 8:
6625 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6626 case 7:
6627 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6628 case 6:
6629 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6630 case 5:
6631 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6632 case 4:
6633 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6634 case 3:
6635 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6636 case 2:
6637 case 1:
6638
6639 default:
6640 break;
6641 };
6642
6643 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6644
1da177e4
LT		 6645 return 0;
6646}
6647
6648/* Called at device open time to get the chip ready for
6649 * packet processing. Invoked with tp->lock held.
6650 */
8e7a22e3 6651static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6652{
6653 int err;
6654
6655 /* Force the chip into D0. */
bc1c7567 6656 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 6657 if (err)
6658 goto out;
6659
6660 tg3_switch_clocks(tp);
6661
6662 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6663
8e7a22e3 6664 err = tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 6665
6666out:
6667 return err;
6668}
6669
6670#define TG3_STAT_ADD32(PSTAT, REG) \
6671do { u32 __val = tr32(REG); \
6672 (PSTAT)->low += __val; \
6673 if ((PSTAT)->low < __val) \
6674 (PSTAT)->high += 1; \
6675} while (0)
6676
6677static void tg3_periodic_fetch_stats(struct tg3 *tp)
6678{
6679 struct tg3_hw_stats *sp = tp->hw_stats;
6680
6681 if (!netif_carrier_ok(tp->dev))
6682 return;
6683
6684 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6685 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6686 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6687 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6688 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6689 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6690 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6691 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6692 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6693 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6694 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6695 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6696 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6697
6698 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6699 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6700 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6701 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6702 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6703 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6704 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6705 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6706 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6707 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6708 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6709 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6710 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6711 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 6712
6713 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6714 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6715 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 6716}
6717
6718static void tg3_timer(unsigned long __opaque)
6719{
6720 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6721
f475f163
MC		 6722 if (tp->irq_sync)
6723 goto restart_timer;
6724
f47c11ee 6725 spin_lock(&tp->lock);
1da177e4 6726
fac9b83e
DM		 6727 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6728 /* All of this garbage is because when using non-tagged
6729 * IRQ status the mailbox/status_block protocol the chip
6730 * uses with the cpu is race prone.
6731 */
6732 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6733 tw32(GRC_LOCAL_CTRL,
6734 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6735 } else {
6736 tw32(HOSTCC_MODE, tp->coalesce_mode |
6737 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6738 }
1da177e4 6739
fac9b83e
DM		 6740 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6741 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6742 spin_unlock(&tp->lock);
fac9b83e
DM		 6743 schedule_work(&tp->reset_task);
6744 return;
6745 }
1da177e4
LT		 6746 }
6747
1da177e4
LT		 6748 /* This part only runs once per second. */
6749 if (!--tp->timer_counter) {
fac9b83e
DM		 6750 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6751 tg3_periodic_fetch_stats(tp);
6752
1da177e4
LT		 6753 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6754 u32 mac_stat;
6755 int phy_event;
6756
6757 mac_stat = tr32(MAC_STATUS);
6758
6759 phy_event = 0;
6760 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6761 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6762 phy_event = 1;
6763 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6764 phy_event = 1;
6765
6766 if (phy_event)
6767 tg3_setup_phy(tp, 0);
6768 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6769 u32 mac_stat = tr32(MAC_STATUS);
6770 int need_setup = 0;
6771
6772 if (netif_carrier_ok(tp->dev) &&
6773 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6774 need_setup = 1;
6775 }
6776 if (! netif_carrier_ok(tp->dev) &&
6777 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6778 MAC_STATUS_SIGNAL_DET))) {
6779 need_setup = 1;
6780 }
6781 if (need_setup) {
3d3ebe74
MC		 6782 if (!tp->serdes_counter) {
6783 tw32_f(MAC_MODE,
6784 (tp->mac_mode &
6785 ~MAC_MODE_PORT_MODE_MASK));
6786 udelay(40);
6787 tw32_f(MAC_MODE, tp->mac_mode);
6788 udelay(40);
6789 }
1da177e4
LT		 6790 tg3_setup_phy(tp, 0);
6791 }
747e8f8b
MC		 6792 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6793 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6794
6795 tp->timer_counter = tp->timer_multiplier;
6796 }
6797
130b8e4d
MC		 6798 /* Heartbeat is only sent once every 2 seconds.
6799 *
6800 * The heartbeat is to tell the ASF firmware that the host
6801 * driver is still alive. In the event that the OS crashes,
6802 * ASF needs to reset the hardware to free up the FIFO space
6803 * that may be filled with rx packets destined for the host.
6804 * If the FIFO is full, ASF will no longer function properly.
6805 *
6806 * Unintended resets have been reported on real time kernels
6807 * where the timer doesn't run on time. Netpoll will also have
6808 * same problem.
6809 *
6810 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6811 * to check the ring condition when the heartbeat is expiring
6812 * before doing the reset. This will prevent most unintended
6813 * resets.
6814 */
1da177e4
LT		 6815 if (!--tp->asf_counter) {
6816 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6817 u32 val;
6818
bbadf503 6819 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 6820 FWCMD_NICDRV_ALIVE3);
bbadf503 6821 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 6822 /* 5 seconds timeout */
bbadf503 6823 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 6824 val = tr32(GRC_RX_CPU_EVENT);
6825 val |= (1 << 14);
6826 tw32(GRC_RX_CPU_EVENT, val);
6827 }
6828 tp->asf_counter = tp->asf_multiplier;
6829 }
6830
f47c11ee 6831 spin_unlock(&tp->lock);
1da177e4 6832
f475f163 6833restart_timer:
1da177e4
LT		 6834 tp->timer.expires = jiffies + tp->timer_offset;
6835 add_timer(&tp->timer);
6836}
6837
81789ef5 6838static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 6839{
7d12e780 6840 irq_handler_t fn;
fcfa0a32
MC		 6841 unsigned long flags;
6842 struct net_device *dev = tp->dev;
6843
6844 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6845 fn = tg3_msi;
6846 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6847 fn = tg3_msi_1shot;
1fb9df5d 6848 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6849 } else {
6850 fn = tg3_interrupt;
6851 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6852 fn = tg3_interrupt_tagged;
1fb9df5d 6853 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6854 }
6855 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6856}
6857
7938109f
MC		 6858static int tg3_test_interrupt(struct tg3 *tp)
6859{
6860 struct net_device *dev = tp->dev;
b16250e3 6861 int err, i, intr_ok = 0;
7938109f 6862
d4bc3927
MC		 6863 if (!netif_running(dev))
6864 return -ENODEV;
6865
7938109f
MC		 6866 tg3_disable_ints(tp);
6867
6868 free_irq(tp->pdev->irq, dev);
6869
6870 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 6871 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6872 if (err)
6873 return err;
6874
38f3843e 6875 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 6876 tg3_enable_ints(tp);
6877
6878 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6879 HOSTCC_MODE_NOW);
6880
6881 for (i = 0; i < 5; i++) {
b16250e3
MC		 6882 u32 int_mbox, misc_host_ctrl;
6883
09ee929c
MC		 6884 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6885 TG3_64BIT_REG_LOW);
b16250e3
MC		 6886 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6887
6888 if ((int_mbox != 0) ||
6889 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6890 intr_ok = 1;
7938109f 6891 break;
b16250e3
MC		 6892 }
6893
7938109f
MC		 6894 msleep(10);
6895 }
6896
6897 tg3_disable_ints(tp);
6898
6899 free_irq(tp->pdev->irq, dev);
6aa20a22 6900
fcfa0a32 6901 err = tg3_request_irq(tp);
7938109f
MC		 6902
6903 if (err)
6904 return err;
6905
b16250e3 6906 if (intr_ok)
7938109f
MC		 6907 return 0;
6908
6909 return -EIO;
6910}
6911
6912/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6913 * successfully restored
6914 */
6915static int tg3_test_msi(struct tg3 *tp)
6916{
6917 struct net_device *dev = tp->dev;
6918 int err;
6919 u16 pci_cmd;
6920
6921 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6922 return 0;
6923
6924 /* Turn off SERR reporting in case MSI terminates with Master
6925 * Abort.
6926 */
6927 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6928 pci_write_config_word(tp->pdev, PCI_COMMAND,
6929 pci_cmd & ~PCI_COMMAND_SERR);
6930
6931 err = tg3_test_interrupt(tp);
6932
6933 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6934
6935 if (!err)
6936 return 0;
6937
6938 /* other failures */
6939 if (err != -EIO)
6940 return err;
6941
6942 /* MSI test failed, go back to INTx mode */
6943 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6944 "switching to INTx mode. Please report this failure to "
6945 "the PCI maintainer and include system chipset information.\n",
6946 tp->dev->name);
6947
6948 free_irq(tp->pdev->irq, dev);
6949 pci_disable_msi(tp->pdev);
6950
6951 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6952
fcfa0a32 6953 err = tg3_request_irq(tp);
7938109f
MC		 6954 if (err)
6955 return err;
6956
6957 /* Need to reset the chip because the MSI cycle may have terminated
6958 * with Master Abort.
6959 */
f47c11ee 6960 tg3_full_lock(tp, 1);
7938109f 6961
944d980e 6962 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 6963 err = tg3_init_hw(tp, 1);
7938109f 6964
f47c11ee 6965 tg3_full_unlock(tp);
7938109f
MC		 6966
6967 if (err)
6968 free_irq(tp->pdev->irq, dev);
6969
6970 return err;
6971}
6972
1da177e4
LT		 6973static int tg3_open(struct net_device *dev)
6974{
6975 struct tg3 *tp = netdev_priv(dev);
6976 int err;
6977
c49a1561
MC		 6978 netif_carrier_off(tp->dev);
6979
f47c11ee 6980 tg3_full_lock(tp, 0);
1da177e4 6981
bc1c7567 6982 err = tg3_set_power_state(tp, PCI_D0);
12862086
IS		 6983 if (err) {
6984 tg3_full_unlock(tp);
bc1c7567 6985 return err;
12862086 6986 }
bc1c7567 6987
1da177e4
LT		 6988 tg3_disable_ints(tp);
6989 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6990
f47c11ee 6991 tg3_full_unlock(tp);
1da177e4
LT		 6992
6993 /* The placement of this call is tied
6994 * to the setup and use of Host TX descriptors.
6995 */
6996 err = tg3_alloc_consistent(tp);
6997 if (err)
6998 return err;
6999
88b06bc2
MC		 7000 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7001 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
d4d2c558
MC		 7002 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7003 !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7004 (tp->pdev_peer == tp->pdev))) {
fac9b83e
DM		 7005 /* All MSI supporting chips should support tagged
7006 * status. Assert that this is the case.
7007 */
7008 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7009 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7010 "Not using MSI.\n", tp->dev->name);
7011 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7012 u32 msi_mode;
7013
7014 msi_mode = tr32(MSGINT_MODE);
7015 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7016 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7017 }
7018 }
fcfa0a32 7019 err = tg3_request_irq(tp);
1da177e4
LT		 7020
7021 if (err) {
88b06bc2
MC		 7022 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7023 pci_disable_msi(tp->pdev);
7024 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7025 }
1da177e4
LT		 7026 tg3_free_consistent(tp);
7027 return err;
7028 }
7029
f47c11ee 7030 tg3_full_lock(tp, 0);
1da177e4 7031
8e7a22e3 7032 err = tg3_init_hw(tp, 1);
1da177e4 7033 if (err) {
944d980e 7034 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7035 tg3_free_rings(tp);
7036 } else {
fac9b83e
DM		 7037 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7038 tp->timer_offset = HZ;
7039 else
7040 tp->timer_offset = HZ / 10;
7041
7042 BUG_ON(tp->timer_offset > HZ);
7043 tp->timer_counter = tp->timer_multiplier =
7044 (HZ / tp->timer_offset);
7045 tp->asf_counter = tp->asf_multiplier =
28fbef78 7046 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7047
7048 init_timer(&tp->timer);
7049 tp->timer.expires = jiffies + tp->timer_offset;
7050 tp->timer.data = (unsigned long) tp;
7051 tp->timer.function = tg3_timer;
1da177e4
LT		 7052 }
7053
f47c11ee 7054 tg3_full_unlock(tp);
1da177e4
LT		 7055
7056 if (err) {
88b06bc2
MC		 7057 free_irq(tp->pdev->irq, dev);
7058 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7059 pci_disable_msi(tp->pdev);
7060 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7061 }
1da177e4
LT		 7062 tg3_free_consistent(tp);
7063 return err;
7064 }
7065
7938109f
MC		 7066 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7067 err = tg3_test_msi(tp);
fac9b83e 7068
7938109f 7069 if (err) {
f47c11ee 7070 tg3_full_lock(tp, 0);
7938109f
MC		 7071
7072 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7073 pci_disable_msi(tp->pdev);
7074 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7075 }
944d980e 7076 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7077 tg3_free_rings(tp);
7078 tg3_free_consistent(tp);
7079
f47c11ee 7080 tg3_full_unlock(tp);
7938109f
MC		 7081
7082 return err;
7083 }
fcfa0a32
MC		 7084
7085 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7086 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7087 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7088
b5d3772c
MC		 7089 tw32(PCIE_TRANSACTION_CFG,
7090 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7091 }
7092 }
7938109f
MC		 7093 }
7094
f47c11ee 7095 tg3_full_lock(tp, 0);
1da177e4 7096
7938109f
MC		 7097 add_timer(&tp->timer);
7098 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7099 tg3_enable_ints(tp);
7100
f47c11ee 7101 tg3_full_unlock(tp);
1da177e4
LT		 7102
7103 netif_start_queue(dev);
7104
7105 return 0;
7106}
7107
7108#if 0
7109/*static*/ void tg3_dump_state(struct tg3 *tp)
7110{
7111 u32 val32, val32_2, val32_3, val32_4, val32_5;
7112 u16 val16;
7113 int i;
7114
7115 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7116 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7117 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7118 val16, val32);
7119
7120 /* MAC block */
7121 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7122 tr32(MAC_MODE), tr32(MAC_STATUS));
7123 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7124 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7125 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7126 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7127 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7128 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7129
7130 /* Send data initiator control block */
7131 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7132 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7133 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7134 tr32(SNDDATAI_STATSCTRL));
7135
7136 /* Send data completion control block */
7137 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7138
7139 /* Send BD ring selector block */
7140 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7141 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7142
7143 /* Send BD initiator control block */
7144 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7145 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7146
7147 /* Send BD completion control block */
7148 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7149
7150 /* Receive list placement control block */
7151 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7152 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7153 printk(" RCVLPC_STATSCTRL[%08x]\n",
7154 tr32(RCVLPC_STATSCTRL));
7155
7156 /* Receive data and receive BD initiator control block */
7157 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7158 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7159
7160 /* Receive data completion control block */
7161 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7162 tr32(RCVDCC_MODE));
7163
7164 /* Receive BD initiator control block */
7165 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7166 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7167
7168 /* Receive BD completion control block */
7169 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7170 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7171
7172 /* Receive list selector control block */
7173 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7174 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7175
7176 /* Mbuf cluster free block */
7177 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7178 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7179
7180 /* Host coalescing control block */
7181 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7182 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7183 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7184 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7185 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7186 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7187 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7188 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7189 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7190 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7191 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7192 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7193
7194 /* Memory arbiter control block */
7195 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7196 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7197
7198 /* Buffer manager control block */
7199 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7200 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7201 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7202 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7203 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7204 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7205 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7206 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7207
7208 /* Read DMA control block */
7209 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7210 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7211
7212 /* Write DMA control block */
7213 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7214 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7215
7216 /* DMA completion block */
7217 printk("DEBUG: DMAC_MODE[%08x]\n",
7218 tr32(DMAC_MODE));
7219
7220 /* GRC block */
7221 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7222 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7223 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7224 tr32(GRC_LOCAL_CTRL));
7225
7226 /* TG3_BDINFOs */
7227 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7228 tr32(RCVDBDI_JUMBO_BD + 0x0),
7229 tr32(RCVDBDI_JUMBO_BD + 0x4),
7230 tr32(RCVDBDI_JUMBO_BD + 0x8),
7231 tr32(RCVDBDI_JUMBO_BD + 0xc));
7232 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7233 tr32(RCVDBDI_STD_BD + 0x0),
7234 tr32(RCVDBDI_STD_BD + 0x4),
7235 tr32(RCVDBDI_STD_BD + 0x8),
7236 tr32(RCVDBDI_STD_BD + 0xc));
7237 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7238 tr32(RCVDBDI_MINI_BD + 0x0),
7239 tr32(RCVDBDI_MINI_BD + 0x4),
7240 tr32(RCVDBDI_MINI_BD + 0x8),
7241 tr32(RCVDBDI_MINI_BD + 0xc));
7242
7243 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7244 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7245 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7246 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7247 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7248 val32, val32_2, val32_3, val32_4);
7249
7250 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7251 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7252 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7253 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7254 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7255 val32, val32_2, val32_3, val32_4);
7256
7257 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7258 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7259 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7260 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7261 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7262 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7263 val32, val32_2, val32_3, val32_4, val32_5);
7264
7265 /* SW status block */
7266 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7267 tp->hw_status->status,
7268 tp->hw_status->status_tag,
7269 tp->hw_status->rx_jumbo_consumer,
7270 tp->hw_status->rx_consumer,
7271 tp->hw_status->rx_mini_consumer,
7272 tp->hw_status->idx[0].rx_producer,
7273 tp->hw_status->idx[0].tx_consumer);
7274
7275 /* SW statistics block */
7276 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7277 ((u32 *)tp->hw_stats)[0],
7278 ((u32 *)tp->hw_stats)[1],
7279 ((u32 *)tp->hw_stats)[2],
7280 ((u32 *)tp->hw_stats)[3]);
7281
7282 /* Mailboxes */
7283 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7284 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7285 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7286 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7287 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7288
7289 /* NIC side send descriptors. */
7290 for (i = 0; i < 6; i++) {
7291 unsigned long txd;
7292
7293 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7294 + (i * sizeof(struct tg3_tx_buffer_desc));
7295 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7296 i,
7297 readl(txd + 0x0), readl(txd + 0x4),
7298 readl(txd + 0x8), readl(txd + 0xc));
7299 }
7300
7301 /* NIC side RX descriptors. */
7302 for (i = 0; i < 6; i++) {
7303 unsigned long rxd;
7304
7305 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7306 + (i * sizeof(struct tg3_rx_buffer_desc));
7307 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7308 i,
7309 readl(rxd + 0x0), readl(rxd + 0x4),
7310 readl(rxd + 0x8), readl(rxd + 0xc));
7311 rxd += (4 * sizeof(u32));
7312 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7313 i,
7314 readl(rxd + 0x0), readl(rxd + 0x4),
7315 readl(rxd + 0x8), readl(rxd + 0xc));
7316 }
7317
7318 for (i = 0; i < 6; i++) {
7319 unsigned long rxd;
7320
7321 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7322 + (i * sizeof(struct tg3_rx_buffer_desc));
7323 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7324 i,
7325 readl(rxd + 0x0), readl(rxd + 0x4),
7326 readl(rxd + 0x8), readl(rxd + 0xc));
7327 rxd += (4 * sizeof(u32));
7328 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7329 i,
7330 readl(rxd + 0x0), readl(rxd + 0x4),
7331 readl(rxd + 0x8), readl(rxd + 0xc));
7332 }
7333}
7334#endif
7335
7336static struct net_device_stats *tg3_get_stats(struct net_device *);
7337static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7338
7339static int tg3_close(struct net_device *dev)
7340{
7341 struct tg3 *tp = netdev_priv(dev);
7342
7faa006f
MC		 7343 /* Calling flush_scheduled_work() may deadlock because
7344 * linkwatch_event() may be on the workqueue and it will try to get
7345 * the rtnl_lock which we are holding.
7346 */
7347 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7348 msleep(1);
7349
1da177e4
LT		 7350 netif_stop_queue(dev);
7351
7352 del_timer_sync(&tp->timer);
7353
f47c11ee 7354 tg3_full_lock(tp, 1);
1da177e4
LT		 7355#if 0
7356 tg3_dump_state(tp);
7357#endif
7358
7359 tg3_disable_ints(tp);
7360
944d980e 7361 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7362 tg3_free_rings(tp);
7363 tp->tg3_flags &=
7364 ~(TG3_FLAG_INIT_COMPLETE |
7365 TG3_FLAG_GOT_SERDES_FLOWCTL);
1da177e4 7366
f47c11ee 7367 tg3_full_unlock(tp);
1da177e4 7368
88b06bc2
MC		 7369 free_irq(tp->pdev->irq, dev);
7370 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7371 pci_disable_msi(tp->pdev);
7372 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7373 }
1da177e4
LT		 7374
7375 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7376 sizeof(tp->net_stats_prev));
7377 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7378 sizeof(tp->estats_prev));
7379
7380 tg3_free_consistent(tp);
7381
bc1c7567
MC		 7382 tg3_set_power_state(tp, PCI_D3hot);
7383
7384 netif_carrier_off(tp->dev);
7385
1da177e4
LT		 7386 return 0;
7387}
7388
7389static inline unsigned long get_stat64(tg3_stat64_t *val)
7390{
7391 unsigned long ret;
7392
7393#if (BITS_PER_LONG == 32)
7394 ret = val->low;
7395#else
7396 ret = ((u64)val->high << 32) | ((u64)val->low);
7397#endif
7398 return ret;
7399}
7400
7401static unsigned long calc_crc_errors(struct tg3 *tp)
7402{
7403 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7404
7405 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7406 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7407 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 7408 u32 val;
7409
f47c11ee 7410 spin_lock_bh(&tp->lock);
1da177e4
LT		 7411 if (!tg3_readphy(tp, 0x1e, &val)) {
7412 tg3_writephy(tp, 0x1e, val | 0x8000);
7413 tg3_readphy(tp, 0x14, &val);
7414 } else
7415 val = 0;
f47c11ee 7416 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7417
7418 tp->phy_crc_errors += val;
7419
7420 return tp->phy_crc_errors;
7421 }
7422
7423 return get_stat64(&hw_stats->rx_fcs_errors);
7424}
7425
7426#define ESTAT_ADD(member) \
7427 estats->member = old_estats->member + \
7428 get_stat64(&hw_stats->member)
7429
7430static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7431{
7432 struct tg3_ethtool_stats *estats = &tp->estats;
7433 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7434 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7435
7436 if (!hw_stats)
7437 return old_estats;
7438
7439 ESTAT_ADD(rx_octets);
7440 ESTAT_ADD(rx_fragments);
7441 ESTAT_ADD(rx_ucast_packets);
7442 ESTAT_ADD(rx_mcast_packets);
7443 ESTAT_ADD(rx_bcast_packets);
7444 ESTAT_ADD(rx_fcs_errors);
7445 ESTAT_ADD(rx_align_errors);
7446 ESTAT_ADD(rx_xon_pause_rcvd);
7447 ESTAT_ADD(rx_xoff_pause_rcvd);
7448 ESTAT_ADD(rx_mac_ctrl_rcvd);
7449 ESTAT_ADD(rx_xoff_entered);
7450 ESTAT_ADD(rx_frame_too_long_errors);
7451 ESTAT_ADD(rx_jabbers);
7452 ESTAT_ADD(rx_undersize_packets);
7453 ESTAT_ADD(rx_in_length_errors);
7454 ESTAT_ADD(rx_out_length_errors);
7455 ESTAT_ADD(rx_64_or_less_octet_packets);
7456 ESTAT_ADD(rx_65_to_127_octet_packets);
7457 ESTAT_ADD(rx_128_to_255_octet_packets);
7458 ESTAT_ADD(rx_256_to_511_octet_packets);
7459 ESTAT_ADD(rx_512_to_1023_octet_packets);
7460 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7461 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7462 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7463 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7464 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7465
7466 ESTAT_ADD(tx_octets);
7467 ESTAT_ADD(tx_collisions);
7468 ESTAT_ADD(tx_xon_sent);
7469 ESTAT_ADD(tx_xoff_sent);
7470 ESTAT_ADD(tx_flow_control);
7471 ESTAT_ADD(tx_mac_errors);
7472 ESTAT_ADD(tx_single_collisions);
7473 ESTAT_ADD(tx_mult_collisions);
7474 ESTAT_ADD(tx_deferred);
7475 ESTAT_ADD(tx_excessive_collisions);
7476 ESTAT_ADD(tx_late_collisions);
7477 ESTAT_ADD(tx_collide_2times);
7478 ESTAT_ADD(tx_collide_3times);
7479 ESTAT_ADD(tx_collide_4times);
7480 ESTAT_ADD(tx_collide_5times);
7481 ESTAT_ADD(tx_collide_6times);
7482 ESTAT_ADD(tx_collide_7times);
7483 ESTAT_ADD(tx_collide_8times);
7484 ESTAT_ADD(tx_collide_9times);
7485 ESTAT_ADD(tx_collide_10times);
7486 ESTAT_ADD(tx_collide_11times);
7487 ESTAT_ADD(tx_collide_12times);
7488 ESTAT_ADD(tx_collide_13times);
7489 ESTAT_ADD(tx_collide_14times);
7490 ESTAT_ADD(tx_collide_15times);
7491 ESTAT_ADD(tx_ucast_packets);
7492 ESTAT_ADD(tx_mcast_packets);
7493 ESTAT_ADD(tx_bcast_packets);
7494 ESTAT_ADD(tx_carrier_sense_errors);
7495 ESTAT_ADD(tx_discards);
7496 ESTAT_ADD(tx_errors);
7497
7498 ESTAT_ADD(dma_writeq_full);
7499 ESTAT_ADD(dma_write_prioq_full);
7500 ESTAT_ADD(rxbds_empty);
7501 ESTAT_ADD(rx_discards);
7502 ESTAT_ADD(rx_errors);
7503 ESTAT_ADD(rx_threshold_hit);
7504
7505 ESTAT_ADD(dma_readq_full);
7506 ESTAT_ADD(dma_read_prioq_full);
7507 ESTAT_ADD(tx_comp_queue_full);
7508
7509 ESTAT_ADD(ring_set_send_prod_index);
7510 ESTAT_ADD(ring_status_update);
7511 ESTAT_ADD(nic_irqs);
7512 ESTAT_ADD(nic_avoided_irqs);
7513 ESTAT_ADD(nic_tx_threshold_hit);
7514
7515 return estats;
7516}
7517
7518static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7519{
7520 struct tg3 *tp = netdev_priv(dev);
7521 struct net_device_stats *stats = &tp->net_stats;
7522 struct net_device_stats *old_stats = &tp->net_stats_prev;
7523 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7524
7525 if (!hw_stats)
7526 return old_stats;
7527
7528 stats->rx_packets = old_stats->rx_packets +
7529 get_stat64(&hw_stats->rx_ucast_packets) +
7530 get_stat64(&hw_stats->rx_mcast_packets) +
7531 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 7532
1da177e4
LT		 7533 stats->tx_packets = old_stats->tx_packets +
7534 get_stat64(&hw_stats->tx_ucast_packets) +
7535 get_stat64(&hw_stats->tx_mcast_packets) +
7536 get_stat64(&hw_stats->tx_bcast_packets);
7537
7538 stats->rx_bytes = old_stats->rx_bytes +
7539 get_stat64(&hw_stats->rx_octets);
7540 stats->tx_bytes = old_stats->tx_bytes +
7541 get_stat64(&hw_stats->tx_octets);
7542
7543 stats->rx_errors = old_stats->rx_errors +
4f63b877 7544 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 7545 stats->tx_errors = old_stats->tx_errors +
7546 get_stat64(&hw_stats->tx_errors) +
7547 get_stat64(&hw_stats->tx_mac_errors) +
7548 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7549 get_stat64(&hw_stats->tx_discards);
7550
7551 stats->multicast = old_stats->multicast +
7552 get_stat64(&hw_stats->rx_mcast_packets);
7553 stats->collisions = old_stats->collisions +
7554 get_stat64(&hw_stats->tx_collisions);
7555
7556 stats->rx_length_errors = old_stats->rx_length_errors +
7557 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7558 get_stat64(&hw_stats->rx_undersize_packets);
7559
7560 stats->rx_over_errors = old_stats->rx_over_errors +
7561 get_stat64(&hw_stats->rxbds_empty);
7562 stats->rx_frame_errors = old_stats->rx_frame_errors +
7563 get_stat64(&hw_stats->rx_align_errors);
7564 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7565 get_stat64(&hw_stats->tx_discards);
7566 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7567 get_stat64(&hw_stats->tx_carrier_sense_errors);
7568
7569 stats->rx_crc_errors = old_stats->rx_crc_errors +
7570 calc_crc_errors(tp);
7571
4f63b877
JL		 7572 stats->rx_missed_errors = old_stats->rx_missed_errors +
7573 get_stat64(&hw_stats->rx_discards);
7574
1da177e4
LT		 7575 return stats;
7576}
7577
7578static inline u32 calc_crc(unsigned char *buf, int len)
7579{
7580 u32 reg;
7581 u32 tmp;
7582 int j, k;
7583
7584 reg = 0xffffffff;
7585
7586 for (j = 0; j < len; j++) {
7587 reg ^= buf[j];
7588
7589 for (k = 0; k < 8; k++) {
7590 tmp = reg & 0x01;
7591
7592 reg >>= 1;
7593
7594 if (tmp) {
7595 reg ^= 0xedb88320;
7596 }
7597 }
7598 }
7599
7600 return ~reg;
7601}
7602
7603static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7604{
7605 /* accept or reject all multicast frames */
7606 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7607 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7608 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7609 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7610}
7611
7612static void __tg3_set_rx_mode(struct net_device *dev)
7613{
7614 struct tg3 *tp = netdev_priv(dev);
7615 u32 rx_mode;
7616
7617 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7618 RX_MODE_KEEP_VLAN_TAG);
7619
7620 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7621 * flag clear.
7622 */
7623#if TG3_VLAN_TAG_USED
7624 if (!tp->vlgrp &&
7625 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7626 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7627#else
7628 /* By definition, VLAN is disabled always in this
7629 * case.
7630 */
7631 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7632 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7633#endif
7634
7635 if (dev->flags & IFF_PROMISC) {
7636 /* Promiscuous mode. */
7637 rx_mode |= RX_MODE_PROMISC;
7638 } else if (dev->flags & IFF_ALLMULTI) {
7639 /* Accept all multicast. */
7640 tg3_set_multi (tp, 1);
7641 } else if (dev->mc_count < 1) {
7642 /* Reject all multicast. */
7643 tg3_set_multi (tp, 0);
7644 } else {
7645 /* Accept one or more multicast(s). */
7646 struct dev_mc_list *mclist;
7647 unsigned int i;
7648 u32 mc_filter[4] = { 0, };
7649 u32 regidx;
7650 u32 bit;
7651 u32 crc;
7652
7653 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7654 i++, mclist = mclist->next) {
7655
7656 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7657 bit = ~crc & 0x7f;
7658 regidx = (bit & 0x60) >> 5;
7659 bit &= 0x1f;
7660 mc_filter[regidx] |= (1 << bit);
7661 }
7662
7663 tw32(MAC_HASH_REG_0, mc_filter[0]);
7664 tw32(MAC_HASH_REG_1, mc_filter[1]);
7665 tw32(MAC_HASH_REG_2, mc_filter[2]);
7666 tw32(MAC_HASH_REG_3, mc_filter[3]);
7667 }
7668
7669 if (rx_mode != tp->rx_mode) {
7670 tp->rx_mode = rx_mode;
7671 tw32_f(MAC_RX_MODE, rx_mode);
7672 udelay(10);
7673 }
7674}
7675
7676static void tg3_set_rx_mode(struct net_device *dev)
7677{
7678 struct tg3 *tp = netdev_priv(dev);
7679
e75f7c90
MC		 7680 if (!netif_running(dev))
7681 return;
7682
f47c11ee 7683 tg3_full_lock(tp, 0);
1da177e4 7684 __tg3_set_rx_mode(dev);
f47c11ee 7685 tg3_full_unlock(tp);
1da177e4
LT		 7686}
7687
7688#define TG3_REGDUMP_LEN (32 * 1024)
7689
7690static int tg3_get_regs_len(struct net_device *dev)
7691{
7692 return TG3_REGDUMP_LEN;
7693}
7694
7695static void tg3_get_regs(struct net_device *dev,
7696 struct ethtool_regs *regs, void *_p)
7697{
7698 u32 *p = _p;
7699 struct tg3 *tp = netdev_priv(dev);
7700 u8 *orig_p = _p;
7701 int i;
7702
7703 regs->version = 0;
7704
7705 memset(p, 0, TG3_REGDUMP_LEN);
7706
bc1c7567
MC		 7707 if (tp->link_config.phy_is_low_power)
7708 return;
7709
f47c11ee 7710 tg3_full_lock(tp, 0);
1da177e4
LT		 7711
7712#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7713#define GET_REG32_LOOP(base,len) \
7714do { p = (u32 *)(orig_p + (base)); \
7715 for (i = 0; i < len; i += 4) \
7716 __GET_REG32((base) + i); \
7717} while (0)
7718#define GET_REG32_1(reg) \
7719do { p = (u32 *)(orig_p + (reg)); \
7720 __GET_REG32((reg)); \
7721} while (0)
7722
7723 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7724 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7725 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7726 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7727 GET_REG32_1(SNDDATAC_MODE);
7728 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7729 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7730 GET_REG32_1(SNDBDC_MODE);
7731 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7732 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7733 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7734 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7735 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7736 GET_REG32_1(RCVDCC_MODE);
7737 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7738 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7739 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7740 GET_REG32_1(MBFREE_MODE);
7741 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7742 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7743 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7744 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7745 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 7746 GET_REG32_1(RX_CPU_MODE);
7747 GET_REG32_1(RX_CPU_STATE);
7748 GET_REG32_1(RX_CPU_PGMCTR);
7749 GET_REG32_1(RX_CPU_HWBKPT);
7750 GET_REG32_1(TX_CPU_MODE);
7751 GET_REG32_1(TX_CPU_STATE);
7752 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 7753 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7754 GET_REG32_LOOP(FTQ_RESET, 0x120);
7755 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7756 GET_REG32_1(DMAC_MODE);
7757 GET_REG32_LOOP(GRC_MODE, 0x4c);
7758 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7759 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7760
7761#undef __GET_REG32
7762#undef GET_REG32_LOOP
7763#undef GET_REG32_1
7764
f47c11ee 7765 tg3_full_unlock(tp);
1da177e4
LT		 7766}
7767
7768static int tg3_get_eeprom_len(struct net_device *dev)
7769{
7770 struct tg3 *tp = netdev_priv(dev);
7771
7772 return tp->nvram_size;
7773}
7774
7775static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
1820180b 7776static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 7777
7778static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7779{
7780 struct tg3 *tp = netdev_priv(dev);
7781 int ret;
7782 u8 *pd;
7783 u32 i, offset, len, val, b_offset, b_count;
7784
bc1c7567
MC		 7785 if (tp->link_config.phy_is_low_power)
7786 return -EAGAIN;
7787
1da177e4
LT		 7788 offset = eeprom->offset;
7789 len = eeprom->len;
7790 eeprom->len = 0;
7791
7792 eeprom->magic = TG3_EEPROM_MAGIC;
7793
7794 if (offset & 3) {
7795 /* adjustments to start on required 4 byte boundary */
7796 b_offset = offset & 3;
7797 b_count = 4 - b_offset;
7798 if (b_count > len) {
7799 /* i.e. offset=1 len=2 */
7800 b_count = len;
7801 }
7802 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7803 if (ret)
7804 return ret;
7805 val = cpu_to_le32(val);
7806 memcpy(data, ((char*)&val) + b_offset, b_count);
7807 len -= b_count;
7808 offset += b_count;
7809 eeprom->len += b_count;
7810 }
7811
7812 /* read bytes upto the last 4 byte boundary */
7813 pd = &data[eeprom->len];
7814 for (i = 0; i < (len - (len & 3)); i += 4) {
7815 ret = tg3_nvram_read(tp, offset + i, &val);
7816 if (ret) {
7817 eeprom->len += i;
7818 return ret;
7819 }
7820 val = cpu_to_le32(val);
7821 memcpy(pd + i, &val, 4);
7822 }
7823 eeprom->len += i;
7824
7825 if (len & 3) {
7826 /* read last bytes not ending on 4 byte boundary */
7827 pd = &data[eeprom->len];
7828 b_count = len & 3;
7829 b_offset = offset + len - b_count;
7830 ret = tg3_nvram_read(tp, b_offset, &val);
7831 if (ret)
7832 return ret;
7833 val = cpu_to_le32(val);
7834 memcpy(pd, ((char*)&val), b_count);
7835 eeprom->len += b_count;
7836 }
7837 return 0;
7838}
7839
6aa20a22 7840static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 7841
7842static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7843{
7844 struct tg3 *tp = netdev_priv(dev);
7845 int ret;
7846 u32 offset, len, b_offset, odd_len, start, end;
7847 u8 *buf;
7848
bc1c7567
MC		 7849 if (tp->link_config.phy_is_low_power)
7850 return -EAGAIN;
7851
1da177e4
LT		 7852 if (eeprom->magic != TG3_EEPROM_MAGIC)
7853 return -EINVAL;
7854
7855 offset = eeprom->offset;
7856 len = eeprom->len;
7857
7858 if ((b_offset = (offset & 3))) {
7859 /* adjustments to start on required 4 byte boundary */
7860 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7861 if (ret)
7862 return ret;
7863 start = cpu_to_le32(start);
7864 len += b_offset;
7865 offset &= ~3;
1c8594b4
MC		 7866 if (len < 4)
7867 len = 4;
1da177e4
LT		 7868 }
7869
7870 odd_len = 0;
1c8594b4 7871 if (len & 3) {
1da177e4
LT		 7872 /* adjustments to end on required 4 byte boundary */
7873 odd_len = 1;
7874 len = (len + 3) & ~3;
7875 ret = tg3_nvram_read(tp, offset+len-4, &end);
7876 if (ret)
7877 return ret;
7878 end = cpu_to_le32(end);
7879 }
7880
7881 buf = data;
7882 if (b_offset || odd_len) {
7883 buf = kmalloc(len, GFP_KERNEL);
7884 if (buf == 0)
7885 return -ENOMEM;
7886 if (b_offset)
7887 memcpy(buf, &start, 4);
7888 if (odd_len)
7889 memcpy(buf+len-4, &end, 4);
7890 memcpy(buf + b_offset, data, eeprom->len);
7891 }
7892
7893 ret = tg3_nvram_write_block(tp, offset, len, buf);
7894
7895 if (buf != data)
7896 kfree(buf);
7897
7898 return ret;
7899}
7900
7901static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7902{
7903 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7904
1da177e4
LT		 7905 cmd->supported = (SUPPORTED_Autoneg);
7906
7907 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7908 cmd->supported |= (SUPPORTED_1000baseT_Half |
7909 SUPPORTED_1000baseT_Full);
7910
ef348144 7911 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 7912 cmd->supported |= (SUPPORTED_100baseT_Half |
7913 SUPPORTED_100baseT_Full |
7914 SUPPORTED_10baseT_Half |
7915 SUPPORTED_10baseT_Full |
7916 SUPPORTED_MII);
ef348144
KK		 7917 cmd->port = PORT_TP;
7918 } else {
1da177e4 7919 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 7920 cmd->port = PORT_FIBRE;
7921 }
6aa20a22 7922
1da177e4
LT		 7923 cmd->advertising = tp->link_config.advertising;
7924 if (netif_running(dev)) {
7925 cmd->speed = tp->link_config.active_speed;
7926 cmd->duplex = tp->link_config.active_duplex;
7927 }
1da177e4
LT		 7928 cmd->phy_address = PHY_ADDR;
7929 cmd->transceiver = 0;
7930 cmd->autoneg = tp->link_config.autoneg;
7931 cmd->maxtxpkt = 0;
7932 cmd->maxrxpkt = 0;
7933 return 0;
7934}
6aa20a22 7935
1da177e4
LT		 7936static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7937{
7938 struct tg3 *tp = netdev_priv(dev);
6aa20a22
JG		 7939
7940 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 7941 /* These are the only valid advertisement bits allowed. */
7942 if (cmd->autoneg == AUTONEG_ENABLE &&
7943 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7944 ADVERTISED_1000baseT_Full |
7945 ADVERTISED_Autoneg |
7946 ADVERTISED_FIBRE)))
7947 return -EINVAL;
37ff238d
MC		 7948 /* Fiber can only do SPEED_1000. */
7949 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7950 (cmd->speed != SPEED_1000))
7951 return -EINVAL;
7952 /* Copper cannot force SPEED_1000. */
7953 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7954 (cmd->speed == SPEED_1000))
7955 return -EINVAL;
7956 else if ((cmd->speed == SPEED_1000) &&
7957 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7958 return -EINVAL;
1da177e4 7959
f47c11ee 7960 tg3_full_lock(tp, 0);
1da177e4
LT		 7961
7962 tp->link_config.autoneg = cmd->autoneg;
7963 if (cmd->autoneg == AUTONEG_ENABLE) {
7964 tp->link_config.advertising = cmd->advertising;
7965 tp->link_config.speed = SPEED_INVALID;
7966 tp->link_config.duplex = DUPLEX_INVALID;
7967 } else {
7968 tp->link_config.advertising = 0;
7969 tp->link_config.speed = cmd->speed;
7970 tp->link_config.duplex = cmd->duplex;
7971 }
6aa20a22 7972
24fcad6b
MC		 7973 tp->link_config.orig_speed = tp->link_config.speed;
7974 tp->link_config.orig_duplex = tp->link_config.duplex;
7975 tp->link_config.orig_autoneg = tp->link_config.autoneg;
7976
1da177e4
LT		 7977 if (netif_running(dev))
7978 tg3_setup_phy(tp, 1);
7979
f47c11ee 7980 tg3_full_unlock(tp);
6aa20a22 7981
1da177e4
LT		 7982 return 0;
7983}
6aa20a22 7984
1da177e4
LT		 7985static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7986{
7987 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7988
1da177e4
LT		 7989 strcpy(info->driver, DRV_MODULE_NAME);
7990 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 7991 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 7992 strcpy(info->bus_info, pci_name(tp->pdev));
7993}
6aa20a22 7994
1da177e4
LT		 7995static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7996{
7997 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7998
1da177e4
LT		 7999 wol->supported = WAKE_MAGIC;
8000 wol->wolopts = 0;
8001 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8002 wol->wolopts = WAKE_MAGIC;
8003 memset(&wol->sopass, 0, sizeof(wol->sopass));
8004}
6aa20a22 8005
1da177e4
LT		 8006static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8007{
8008 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8009
1da177e4
LT		 8010 if (wol->wolopts & ~WAKE_MAGIC)
8011 return -EINVAL;
8012 if ((wol->wolopts & WAKE_MAGIC) &&
3f7045c1 8013 tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
1da177e4
LT		 8014 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8015 return -EINVAL;
6aa20a22 8016
f47c11ee 8017 spin_lock_bh(&tp->lock);
1da177e4
LT		 8018 if (wol->wolopts & WAKE_MAGIC)
8019 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8020 else
8021 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 8022 spin_unlock_bh(&tp->lock);
6aa20a22 8023
1da177e4
LT		 8024 return 0;
8025}
6aa20a22 8026
1da177e4
LT		 8027static u32 tg3_get_msglevel(struct net_device *dev)
8028{
8029 struct tg3 *tp = netdev_priv(dev);
8030 return tp->msg_enable;
8031}
6aa20a22 8032
1da177e4
LT		 8033static void tg3_set_msglevel(struct net_device *dev, u32 value)
8034{
8035 struct tg3 *tp = netdev_priv(dev);
8036 tp->msg_enable = value;
8037}
6aa20a22 8038
1da177e4
LT		 8039static int tg3_set_tso(struct net_device *dev, u32 value)
8040{
8041 struct tg3 *tp = netdev_priv(dev);
8042
8043 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8044 if (value)
8045 return -EINVAL;
8046 return 0;
8047 }
b5d3772c
MC		 8048 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8049 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
b0026624
MC		 8050 if (value)
8051 dev->features |= NETIF_F_TSO6;
8052 else
8053 dev->features &= ~NETIF_F_TSO6;
8054 }
1da177e4
LT		 8055 return ethtool_op_set_tso(dev, value);
8056}
6aa20a22 8057
1da177e4
LT		 8058static int tg3_nway_reset(struct net_device *dev)
8059{
8060 struct tg3 *tp = netdev_priv(dev);
8061 u32 bmcr;
8062 int r;
6aa20a22 8063
1da177e4
LT		 8064 if (!netif_running(dev))
8065 return -EAGAIN;
8066
c94e3941
MC		 8067 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8068 return -EINVAL;
8069
f47c11ee 8070 spin_lock_bh(&tp->lock);
1da177e4
LT		 8071 r = -EINVAL;
8072 tg3_readphy(tp, MII_BMCR, &bmcr);
8073 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 8074 ((bmcr & BMCR_ANENABLE) ||
8075 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8076 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8077 BMCR_ANENABLE);
1da177e4
LT		 8078 r = 0;
8079 }
f47c11ee 8080 spin_unlock_bh(&tp->lock);
6aa20a22 8081
1da177e4
LT		 8082 return r;
8083}
6aa20a22 8084
1da177e4
LT		 8085static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8086{
8087 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8088
1da177e4
LT		 8089 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8090 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8091 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8092 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8093 else
8094 ering->rx_jumbo_max_pending = 0;
8095
8096 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8097
8098 ering->rx_pending = tp->rx_pending;
8099 ering->rx_mini_pending = 0;
4f81c32b
MC		 8100 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8101 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8102 else
8103 ering->rx_jumbo_pending = 0;
8104
1da177e4
LT		 8105 ering->tx_pending = tp->tx_pending;
8106}
6aa20a22 8107
1da177e4
LT		 8108static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8109{
8110 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8111 int irq_sync = 0, err = 0;
6aa20a22 8112
1da177e4
LT		 8113 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8114 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8115 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8116 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8117 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8118 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8119 return -EINVAL;
6aa20a22 8120
bbe832c0 8121 if (netif_running(dev)) {
1da177e4 8122 tg3_netif_stop(tp);
bbe832c0
MC		 8123 irq_sync = 1;
8124 }
1da177e4 8125
bbe832c0 8126 tg3_full_lock(tp, irq_sync);
6aa20a22 8127
1da177e4
LT		 8128 tp->rx_pending = ering->rx_pending;
8129
8130 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8131 tp->rx_pending > 63)
8132 tp->rx_pending = 63;
8133 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8134 tp->tx_pending = ering->tx_pending;
8135
8136 if (netif_running(dev)) {
944d980e 8137 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8138 err = tg3_restart_hw(tp, 1);
8139 if (!err)
8140 tg3_netif_start(tp);
1da177e4
LT		 8141 }
8142
f47c11ee 8143 tg3_full_unlock(tp);
6aa20a22 8144
b9ec6c1b 8145 return err;
1da177e4 8146}
6aa20a22 8147
1da177e4
LT		 8148static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8149{
8150 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8151
1da177e4
LT		 8152 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8153 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8154 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8155}
6aa20a22 8156
1da177e4
LT		 8157static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8158{
8159 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8160 int irq_sync = 0, err = 0;
6aa20a22 8161
bbe832c0 8162 if (netif_running(dev)) {
1da177e4 8163 tg3_netif_stop(tp);
bbe832c0
MC		 8164 irq_sync = 1;
8165 }
1da177e4 8166
bbe832c0 8167 tg3_full_lock(tp, irq_sync);
f47c11ee 8168
1da177e4
LT		 8169 if (epause->autoneg)
8170 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8171 else
8172 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8173 if (epause->rx_pause)
8174 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8175 else
8176 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8177 if (epause->tx_pause)
8178 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8179 else
8180 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8181
8182 if (netif_running(dev)) {
944d980e 8183 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8184 err = tg3_restart_hw(tp, 1);
8185 if (!err)
8186 tg3_netif_start(tp);
1da177e4 8187 }
f47c11ee
DM		 8188
8189 tg3_full_unlock(tp);
6aa20a22 8190
b9ec6c1b 8191 return err;
1da177e4 8192}
6aa20a22 8193
1da177e4
LT		 8194static u32 tg3_get_rx_csum(struct net_device *dev)
8195{
8196 struct tg3 *tp = netdev_priv(dev);
8197 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8198}
6aa20a22 8199
1da177e4
LT		 8200static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8201{
8202 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8203
1da177e4
LT		 8204 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8205 if (data != 0)
8206 return -EINVAL;
8207 return 0;
8208 }
6aa20a22 8209
f47c11ee 8210 spin_lock_bh(&tp->lock);
1da177e4
LT		 8211 if (data)
8212 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8213 else
8214 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8215 spin_unlock_bh(&tp->lock);
6aa20a22 8216
1da177e4
LT		 8217 return 0;
8218}
6aa20a22 8219
1da177e4
LT		 8220static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8221{
8222 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8223
1da177e4
LT		 8224 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8225 if (data != 0)
8226 return -EINVAL;
8227 return 0;
8228 }
6aa20a22 8229
af36e6b6
MC		 8230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf 8232 ethtool_op_set_tx_hw_csum(dev, data);
1da177e4 8233 else
9c27dbdf 8234 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8235
8236 return 0;
8237}
8238
8239static int tg3_get_stats_count (struct net_device *dev)
8240{
8241 return TG3_NUM_STATS;
8242}
8243
4cafd3f5
MC		 8244static int tg3_get_test_count (struct net_device *dev)
8245{
8246 return TG3_NUM_TEST;
8247}
8248
1da177e4
LT		 8249static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8250{
8251 switch (stringset) {
8252 case ETH_SS_STATS:
8253 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8254 break;
4cafd3f5
MC		 8255 case ETH_SS_TEST:
8256 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8257 break;
1da177e4
LT		 8258 default:
8259 WARN_ON(1); /* we need a WARN() */
8260 break;
8261 }
8262}
8263
4009a93d
MC		 8264static int tg3_phys_id(struct net_device *dev, u32 data)
8265{
8266 struct tg3 *tp = netdev_priv(dev);
8267 int i;
8268
8269 if (!netif_running(tp->dev))
8270 return -EAGAIN;
8271
8272 if (data == 0)
8273 data = 2;
8274
8275 for (i = 0; i < (data * 2); i++) {
8276 if ((i % 2) == 0)
8277 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8278 LED_CTRL_1000MBPS_ON |
8279 LED_CTRL_100MBPS_ON |
8280 LED_CTRL_10MBPS_ON |
8281 LED_CTRL_TRAFFIC_OVERRIDE |
8282 LED_CTRL_TRAFFIC_BLINK |
8283 LED_CTRL_TRAFFIC_LED);
6aa20a22 8284
4009a93d
MC		 8285 else
8286 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8287 LED_CTRL_TRAFFIC_OVERRIDE);
8288
8289 if (msleep_interruptible(500))
8290 break;
8291 }
8292 tw32(MAC_LED_CTRL, tp->led_ctrl);
8293 return 0;
8294}
8295
1da177e4
LT		 8296static void tg3_get_ethtool_stats (struct net_device *dev,
8297 struct ethtool_stats *estats, u64 *tmp_stats)
8298{
8299 struct tg3 *tp = netdev_priv(dev);
8300 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8301}
8302
566f86ad 8303#define NVRAM_TEST_SIZE 0x100
1b27777a 8304#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
b16250e3
MC		 8305#define NVRAM_SELFBOOT_HW_SIZE 0x20
8306#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 8307
8308static int tg3_test_nvram(struct tg3 *tp)
8309{
1b27777a
MC		 8310 u32 *buf, csum, magic;
8311 int i, j, err = 0, size;
566f86ad 8312
1820180b 8313 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 8314 return -EIO;
8315
1b27777a
MC		 8316 if (magic == TG3_EEPROM_MAGIC)
8317 size = NVRAM_TEST_SIZE;
b16250e3 8318 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8319 if ((magic & 0xe00000) == 0x200000)
8320 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8321 else
8322 return 0;
b16250e3
MC		 8323 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8324 size = NVRAM_SELFBOOT_HW_SIZE;
8325 else
1b27777a
MC		 8326 return -EIO;
8327
8328 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 8329 if (buf == NULL)
8330 return -ENOMEM;
8331
1b27777a
MC		 8332 err = -EIO;
8333 for (i = 0, j = 0; i < size; i += 4, j++) {
566f86ad
MC		 8334 u32 val;
8335
8336 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8337 break;
8338 buf[j] = cpu_to_le32(val);
8339 }
1b27777a 8340 if (i < size)
566f86ad
MC		 8341 goto out;
8342
1b27777a 8343 /* Selfboot format */
b16250e3
MC		 8344 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8345 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8346 u8 *buf8 = (u8 *) buf, csum8 = 0;
8347
8348 for (i = 0; i < size; i++)
8349 csum8 += buf8[i];
8350
ad96b485
AB		 8351 if (csum8 == 0) {
8352 err = 0;
8353 goto out;
8354 }
8355
8356 err = -EIO;
8357 goto out;
1b27777a 8358 }
566f86ad 8359
b16250e3
MC		 8360 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8361 TG3_EEPROM_MAGIC_HW) {
8362 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8363 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8364 u8 *buf8 = (u8 *) buf;
8365 int j, k;
8366
8367 /* Separate the parity bits and the data bytes. */
8368 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8369 if ((i == 0) || (i == 8)) {
8370 int l;
8371 u8 msk;
8372
8373 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8374 parity[k++] = buf8[i] & msk;
8375 i++;
8376 }
8377 else if (i == 16) {
8378 int l;
8379 u8 msk;
8380
8381 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8382 parity[k++] = buf8[i] & msk;
8383 i++;
8384
8385 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8386 parity[k++] = buf8[i] & msk;
8387 i++;
8388 }
8389 data[j++] = buf8[i];
8390 }
8391
8392 err = -EIO;
8393 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8394 u8 hw8 = hweight8(data[i]);
8395
8396 if ((hw8 & 0x1) && parity[i])
8397 goto out;
8398 else if (!(hw8 & 0x1) && !parity[i])
8399 goto out;
8400 }
8401 err = 0;
8402 goto out;
8403 }
8404
566f86ad
MC		 8405 /* Bootstrap checksum at offset 0x10 */
8406 csum = calc_crc((unsigned char *) buf, 0x10);
8407 if(csum != cpu_to_le32(buf[0x10/4]))
8408 goto out;
8409
8410 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8411 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8412 if (csum != cpu_to_le32(buf[0xfc/4]))
8413 goto out;
8414
8415 err = 0;
8416
8417out:
8418 kfree(buf);
8419 return err;
8420}
8421
ca43007a
MC		 8422#define TG3_SERDES_TIMEOUT_SEC 2
8423#define TG3_COPPER_TIMEOUT_SEC 6
8424
8425static int tg3_test_link(struct tg3 *tp)
8426{
8427 int i, max;
8428
8429 if (!netif_running(tp->dev))
8430 return -ENODEV;
8431
4c987487 8432 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 8433 max = TG3_SERDES_TIMEOUT_SEC;
8434 else
8435 max = TG3_COPPER_TIMEOUT_SEC;
8436
8437 for (i = 0; i < max; i++) {
8438 if (netif_carrier_ok(tp->dev))
8439 return 0;
8440
8441 if (msleep_interruptible(1000))
8442 break;
8443 }
8444
8445 return -EIO;
8446}
8447
a71116d1 8448/* Only test the commonly used registers */
30ca3e37 8449static int tg3_test_registers(struct tg3 *tp)
a71116d1 8450{
b16250e3 8451 int i, is_5705, is_5750;
a71116d1
MC		 8452 u32 offset, read_mask, write_mask, val, save_val, read_val;
8453 static struct {
8454 u16 offset;
8455 u16 flags;
8456#define TG3_FL_5705 0x1
8457#define TG3_FL_NOT_5705 0x2
8458#define TG3_FL_NOT_5788 0x4
b16250e3 8459#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 8460 u32 read_mask;
8461 u32 write_mask;
8462 } reg_tbl[] = {
8463 /* MAC Control Registers */
8464 { MAC_MODE, TG3_FL_NOT_5705,
8465 0x00000000, 0x00ef6f8c },
8466 { MAC_MODE, TG3_FL_5705,
8467 0x00000000, 0x01ef6b8c },
8468 { MAC_STATUS, TG3_FL_NOT_5705,
8469 0x03800107, 0x00000000 },
8470 { MAC_STATUS, TG3_FL_5705,
8471 0x03800100, 0x00000000 },
8472 { MAC_ADDR_0_HIGH, 0x0000,
8473 0x00000000, 0x0000ffff },
8474 { MAC_ADDR_0_LOW, 0x0000,
8475 0x00000000, 0xffffffff },
8476 { MAC_RX_MTU_SIZE, 0x0000,
8477 0x00000000, 0x0000ffff },
8478 { MAC_TX_MODE, 0x0000,
8479 0x00000000, 0x00000070 },
8480 { MAC_TX_LENGTHS, 0x0000,
8481 0x00000000, 0x00003fff },
8482 { MAC_RX_MODE, TG3_FL_NOT_5705,
8483 0x00000000, 0x000007fc },
8484 { MAC_RX_MODE, TG3_FL_5705,
8485 0x00000000, 0x000007dc },
8486 { MAC_HASH_REG_0, 0x0000,
8487 0x00000000, 0xffffffff },
8488 { MAC_HASH_REG_1, 0x0000,
8489 0x00000000, 0xffffffff },
8490 { MAC_HASH_REG_2, 0x0000,
8491 0x00000000, 0xffffffff },
8492 { MAC_HASH_REG_3, 0x0000,
8493 0x00000000, 0xffffffff },
8494
8495 /* Receive Data and Receive BD Initiator Control Registers. */
8496 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8497 0x00000000, 0xffffffff },
8498 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8499 0x00000000, 0xffffffff },
8500 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8501 0x00000000, 0x00000003 },
8502 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8503 0x00000000, 0xffffffff },
8504 { RCVDBDI_STD_BD+0, 0x0000,
8505 0x00000000, 0xffffffff },
8506 { RCVDBDI_STD_BD+4, 0x0000,
8507 0x00000000, 0xffffffff },
8508 { RCVDBDI_STD_BD+8, 0x0000,
8509 0x00000000, 0xffff0002 },
8510 { RCVDBDI_STD_BD+0xc, 0x0000,
8511 0x00000000, 0xffffffff },
6aa20a22 8512
a71116d1
MC		 8513 /* Receive BD Initiator Control Registers. */
8514 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8515 0x00000000, 0xffffffff },
8516 { RCVBDI_STD_THRESH, TG3_FL_5705,
8517 0x00000000, 0x000003ff },
8518 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8519 0x00000000, 0xffffffff },
6aa20a22 8520
a71116d1
MC		 8521 /* Host Coalescing Control Registers. */
8522 { HOSTCC_MODE, TG3_FL_NOT_5705,
8523 0x00000000, 0x00000004 },
8524 { HOSTCC_MODE, TG3_FL_5705,
8525 0x00000000, 0x000000f6 },
8526 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8527 0x00000000, 0xffffffff },
8528 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8529 0x00000000, 0x000003ff },
8530 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8531 0x00000000, 0xffffffff },
8532 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8533 0x00000000, 0x000003ff },
8534 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8535 0x00000000, 0xffffffff },
8536 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8537 0x00000000, 0x000000ff },
8538 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8539 0x00000000, 0xffffffff },
8540 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8541 0x00000000, 0x000000ff },
8542 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8543 0x00000000, 0xffffffff },
8544 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8545 0x00000000, 0xffffffff },
8546 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8547 0x00000000, 0xffffffff },
8548 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8549 0x00000000, 0x000000ff },
8550 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8551 0x00000000, 0xffffffff },
8552 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8553 0x00000000, 0x000000ff },
8554 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8555 0x00000000, 0xffffffff },
8556 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8557 0x00000000, 0xffffffff },
8558 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8559 0x00000000, 0xffffffff },
8560 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8561 0x00000000, 0xffffffff },
8562 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8563 0x00000000, 0xffffffff },
8564 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8565 0xffffffff, 0x00000000 },
8566 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8567 0xffffffff, 0x00000000 },
8568
8569 /* Buffer Manager Control Registers. */
b16250e3 8570 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 8571 0x00000000, 0x007fff80 },
b16250e3 8572 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 8573 0x00000000, 0x007fffff },
8574 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8575 0x00000000, 0x0000003f },
8576 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8577 0x00000000, 0x000001ff },
8578 { BUFMGR_MB_HIGH_WATER, 0x0000,
8579 0x00000000, 0x000001ff },
8580 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8581 0xffffffff, 0x00000000 },
8582 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8583 0xffffffff, 0x00000000 },
6aa20a22 8584
a71116d1
MC		 8585 /* Mailbox Registers */
8586 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8587 0x00000000, 0x000001ff },
8588 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8589 0x00000000, 0x000001ff },
8590 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8591 0x00000000, 0x000007ff },
8592 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8593 0x00000000, 0x000001ff },
8594
8595 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8596 };
8597
b16250e3
MC		 8598 is_5705 = is_5750 = 0;
8599 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 8600 is_5705 = 1;
b16250e3
MC		 8601 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8602 is_5750 = 1;
8603 }
a71116d1
MC		 8604
8605 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8606 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8607 continue;
8608
8609 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8610 continue;
8611
8612 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8613 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8614 continue;
8615
b16250e3
MC		 8616 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8617 continue;
8618
a71116d1
MC		 8619 offset = (u32) reg_tbl[i].offset;
8620 read_mask = reg_tbl[i].read_mask;
8621 write_mask = reg_tbl[i].write_mask;
8622
8623 /* Save the original register content */
8624 save_val = tr32(offset);
8625
8626 /* Determine the read-only value. */
8627 read_val = save_val & read_mask;
8628
8629 /* Write zero to the register, then make sure the read-only bits
8630 * are not changed and the read/write bits are all zeros.
8631 */
8632 tw32(offset, 0);
8633
8634 val = tr32(offset);
8635
8636 /* Test the read-only and read/write bits. */
8637 if (((val & read_mask) != read_val) || (val & write_mask))
8638 goto out;
8639
8640 /* Write ones to all the bits defined by RdMask and WrMask, then
8641 * make sure the read-only bits are not changed and the
8642 * read/write bits are all ones.
8643 */
8644 tw32(offset, read_mask | write_mask);
8645
8646 val = tr32(offset);
8647
8648 /* Test the read-only bits. */
8649 if ((val & read_mask) != read_val)
8650 goto out;
8651
8652 /* Test the read/write bits. */
8653 if ((val & write_mask) != write_mask)
8654 goto out;
8655
8656 tw32(offset, save_val);
8657 }
8658
8659 return 0;
8660
8661out:
9f88f29f
MC		 8662 if (netif_msg_hw(tp))
8663 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8664 offset);
a71116d1
MC		 8665 tw32(offset, save_val);
8666 return -EIO;
8667}
8668
7942e1db
MC		 8669static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8670{
f71e1309 8671 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 8672 int i;
8673 u32 j;
8674
8675 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8676 for (j = 0; j < len; j += 4) {
8677 u32 val;
8678
8679 tg3_write_mem(tp, offset + j, test_pattern[i]);
8680 tg3_read_mem(tp, offset + j, &val);
8681 if (val != test_pattern[i])
8682 return -EIO;
8683 }
8684 }
8685 return 0;
8686}
8687
8688static int tg3_test_memory(struct tg3 *tp)
8689{
8690 static struct mem_entry {
8691 u32 offset;
8692 u32 len;
8693 } mem_tbl_570x[] = {
38690194 8694 { 0x00000000, 0x00b50},
7942e1db
MC		 8695 { 0x00002000, 0x1c000},
8696 { 0xffffffff, 0x00000}
8697 }, mem_tbl_5705[] = {
8698 { 0x00000100, 0x0000c},
8699 { 0x00000200, 0x00008},
7942e1db
MC		 8700 { 0x00004000, 0x00800},
8701 { 0x00006000, 0x01000},
8702 { 0x00008000, 0x02000},
8703 { 0x00010000, 0x0e000},
8704 { 0xffffffff, 0x00000}
79f4d13a
MC		 8705 }, mem_tbl_5755[] = {
8706 { 0x00000200, 0x00008},
8707 { 0x00004000, 0x00800},
8708 { 0x00006000, 0x00800},
8709 { 0x00008000, 0x02000},
8710 { 0x00010000, 0x0c000},
8711 { 0xffffffff, 0x00000}
b16250e3
MC		 8712 }, mem_tbl_5906[] = {
8713 { 0x00000200, 0x00008},
8714 { 0x00004000, 0x00400},
8715 { 0x00006000, 0x00400},
8716 { 0x00008000, 0x01000},
8717 { 0x00010000, 0x01000},
8718 { 0xffffffff, 0x00000}
7942e1db
MC		 8719 };
8720 struct mem_entry *mem_tbl;
8721 int err = 0;
8722 int i;
8723
79f4d13a 8724 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
af36e6b6
MC		 8725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8726 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
79f4d13a 8727 mem_tbl = mem_tbl_5755;
b16250e3
MC		 8728 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8729 mem_tbl = mem_tbl_5906;
79f4d13a
MC		 8730 else
8731 mem_tbl = mem_tbl_5705;
8732 } else
7942e1db
MC		 8733 mem_tbl = mem_tbl_570x;
8734
8735 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8736 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8737 mem_tbl[i].len)) != 0)
8738 break;
8739 }
6aa20a22 8740
7942e1db
MC		 8741 return err;
8742}
8743
9f40dead
MC		 8744#define TG3_MAC_LOOPBACK 0
8745#define TG3_PHY_LOOPBACK 1
8746
8747static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 8748{
9f40dead 8749 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 8750 u32 desc_idx;
8751 struct sk_buff *skb, *rx_skb;
8752 u8 *tx_data;
8753 dma_addr_t map;
8754 int num_pkts, tx_len, rx_len, i, err;
8755 struct tg3_rx_buffer_desc *desc;
8756
9f40dead 8757 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 8758 /* HW errata - mac loopback fails in some cases on 5780.
8759 * Normal traffic and PHY loopback are not affected by
8760 * errata.
8761 */
8762 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8763 return 0;
8764
9f40dead 8765 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
3f7045c1
MC		 8766 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8767 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8768 mac_mode |= MAC_MODE_PORT_MODE_MII;
8769 else
8770 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 8771 tw32(MAC_MODE, mac_mode);
8772 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 8773 u32 val;
8774
b16250e3
MC		 8775 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8776 u32 phytest;
8777
8778 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8779 u32 phy;
8780
8781 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8782 phytest | MII_TG3_EPHY_SHADOW_EN);
8783 if (!tg3_readphy(tp, 0x1b, &phy))
8784 tg3_writephy(tp, 0x1b, phy & ~0x20);
8785 if (!tg3_readphy(tp, 0x10, &phy))
8786 tg3_writephy(tp, 0x10, phy & ~0x4000);
8787 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8788 }
5d64ad34
MC		 8789 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8790 } else
8791 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1
MC		 8792
8793 tg3_writephy(tp, MII_BMCR, val);
c94e3941 8794 udelay(40);
5d64ad34
MC		 8795
8796 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8797 MAC_MODE_LINK_POLARITY;
8798 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 8799 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 8800 mac_mode |= MAC_MODE_PORT_MODE_MII;
8801 } else
8802 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 8803
c94e3941
MC		 8804 /* reset to prevent losing 1st rx packet intermittently */
8805 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8806 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8807 udelay(10);
8808 tw32_f(MAC_RX_MODE, tp->rx_mode);
8809 }
ff18ff02 8810 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9f40dead 8811 mac_mode &= ~MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 8812 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8813 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8814 }
9f40dead 8815 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 8816 }
8817 else
8818 return -EINVAL;
c76949a6
MC		 8819
8820 err = -EIO;
8821
c76949a6 8822 tx_len = 1514;
a20e9c62 8823 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 8824 if (!skb)
8825 return -ENOMEM;
8826
c76949a6
MC		 8827 tx_data = skb_put(skb, tx_len);
8828 memcpy(tx_data, tp->dev->dev_addr, 6);
8829 memset(tx_data + 6, 0x0, 8);
8830
8831 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8832
8833 for (i = 14; i < tx_len; i++)
8834 tx_data[i] = (u8) (i & 0xff);
8835
8836 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8837
8838 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8839 HOSTCC_MODE_NOW);
8840
8841 udelay(10);
8842
8843 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8844
c76949a6
MC		 8845 num_pkts = 0;
8846
9f40dead 8847 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 8848
9f40dead 8849 tp->tx_prod++;
c76949a6
MC		 8850 num_pkts++;
8851
9f40dead
MC		 8852 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8853 tp->tx_prod);
09ee929c 8854 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 8855
8856 udelay(10);
8857
3f7045c1
MC		 8858 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8859 for (i = 0; i < 25; i++) {
c76949a6
MC		 8860 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8861 HOSTCC_MODE_NOW);
8862
8863 udelay(10);
8864
8865 tx_idx = tp->hw_status->idx[0].tx_consumer;
8866 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 8867 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 8868 (rx_idx == (rx_start_idx + num_pkts)))
8869 break;
8870 }
8871
8872 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8873 dev_kfree_skb(skb);
8874
9f40dead 8875 if (tx_idx != tp->tx_prod)
c76949a6
MC		 8876 goto out;
8877
8878 if (rx_idx != rx_start_idx + num_pkts)
8879 goto out;
8880
8881 desc = &tp->rx_rcb[rx_start_idx];
8882 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8883 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8884 if (opaque_key != RXD_OPAQUE_RING_STD)
8885 goto out;
8886
8887 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8888 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8889 goto out;
8890
8891 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8892 if (rx_len != tx_len)
8893 goto out;
8894
8895 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8896
8897 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8898 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8899
8900 for (i = 14; i < tx_len; i++) {
8901 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8902 goto out;
8903 }
8904 err = 0;
6aa20a22 8905
c76949a6
MC		 8906 /* tg3_free_rings will unmap and free the rx_skb */
8907out:
8908 return err;
8909}
8910
9f40dead
MC		 8911#define TG3_MAC_LOOPBACK_FAILED 1
8912#define TG3_PHY_LOOPBACK_FAILED 2
8913#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8914 TG3_PHY_LOOPBACK_FAILED)
8915
8916static int tg3_test_loopback(struct tg3 *tp)
8917{
8918 int err = 0;
8919
8920 if (!netif_running(tp->dev))
8921 return TG3_LOOPBACK_FAILED;
8922
b9ec6c1b
MC		 8923 err = tg3_reset_hw(tp, 1);
8924 if (err)
8925 return TG3_LOOPBACK_FAILED;
9f40dead
MC		 8926
8927 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8928 err |= TG3_MAC_LOOPBACK_FAILED;
8929 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8930 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8931 err |= TG3_PHY_LOOPBACK_FAILED;
8932 }
8933
8934 return err;
8935}
8936
4cafd3f5
MC		 8937static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8938 u64 *data)
8939{
566f86ad
MC		 8940 struct tg3 *tp = netdev_priv(dev);
8941
bc1c7567
MC		 8942 if (tp->link_config.phy_is_low_power)
8943 tg3_set_power_state(tp, PCI_D0);
8944
566f86ad
MC		 8945 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8946
8947 if (tg3_test_nvram(tp) != 0) {
8948 etest->flags |= ETH_TEST_FL_FAILED;
8949 data[0] = 1;
8950 }
ca43007a
MC		 8951 if (tg3_test_link(tp) != 0) {
8952 etest->flags |= ETH_TEST_FL_FAILED;
8953 data[1] = 1;
8954 }
a71116d1 8955 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 8956 int err, irq_sync = 0;
bbe832c0
MC		 8957
8958 if (netif_running(dev)) {
a71116d1 8959 tg3_netif_stop(tp);
bbe832c0
MC		 8960 irq_sync = 1;
8961 }
a71116d1 8962
bbe832c0 8963 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 8964
8965 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 8966 err = tg3_nvram_lock(tp);
a71116d1
MC		 8967 tg3_halt_cpu(tp, RX_CPU_BASE);
8968 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8969 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 8970 if (!err)
8971 tg3_nvram_unlock(tp);
a71116d1 8972
d9ab5ad1
MC		 8973 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8974 tg3_phy_reset(tp);
8975
a71116d1
MC		 8976 if (tg3_test_registers(tp) != 0) {
8977 etest->flags |= ETH_TEST_FL_FAILED;
8978 data[2] = 1;
8979 }
7942e1db
MC		 8980 if (tg3_test_memory(tp) != 0) {
8981 etest->flags |= ETH_TEST_FL_FAILED;
8982 data[3] = 1;
8983 }
9f40dead 8984 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 8985 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 8986
f47c11ee
DM		 8987 tg3_full_unlock(tp);
8988
d4bc3927
MC		 8989 if (tg3_test_interrupt(tp) != 0) {
8990 etest->flags |= ETH_TEST_FL_FAILED;
8991 data[5] = 1;
8992 }
f47c11ee
DM		 8993
8994 tg3_full_lock(tp, 0);
d4bc3927 8995
a71116d1
MC		 8996 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8997 if (netif_running(dev)) {
8998 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 8999 if (!tg3_restart_hw(tp, 1))
9000 tg3_netif_start(tp);
a71116d1 9001 }
f47c11ee
DM		 9002
9003 tg3_full_unlock(tp);
a71116d1 9004 }
bc1c7567
MC		 9005 if (tp->link_config.phy_is_low_power)
9006 tg3_set_power_state(tp, PCI_D3hot);
9007
4cafd3f5
MC		 9008}
9009
1da177e4
LT		 9010static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9011{
9012 struct mii_ioctl_data *data = if_mii(ifr);
9013 struct tg3 *tp = netdev_priv(dev);
9014 int err;
9015
9016 switch(cmd) {
9017 case SIOCGMIIPHY:
9018 data->phy_id = PHY_ADDR;
9019
9020 /* fallthru */
9021 case SIOCGMIIREG: {
9022 u32 mii_regval;
9023
9024 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9025 break; /* We have no PHY */
9026
bc1c7567
MC		 9027 if (tp->link_config.phy_is_low_power)
9028 return -EAGAIN;
9029
f47c11ee 9030 spin_lock_bh(&tp->lock);
1da177e4 9031 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9032 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9033
9034 data->val_out = mii_regval;
9035
9036 return err;
9037 }
9038
9039 case SIOCSMIIREG:
9040 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9041 break; /* We have no PHY */
9042
9043 if (!capable(CAP_NET_ADMIN))
9044 return -EPERM;
9045
bc1c7567
MC		 9046 if (tp->link_config.phy_is_low_power)
9047 return -EAGAIN;
9048
f47c11ee 9049 spin_lock_bh(&tp->lock);
1da177e4 9050 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9051 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9052
9053 return err;
9054
9055 default:
9056 /* do nothing */
9057 break;
9058 }
9059 return -EOPNOTSUPP;
9060}
9061
9062#if TG3_VLAN_TAG_USED
9063static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9064{
9065 struct tg3 *tp = netdev_priv(dev);
9066
29315e87
MC		 9067 if (netif_running(dev))
9068 tg3_netif_stop(tp);
9069
f47c11ee 9070 tg3_full_lock(tp, 0);
1da177e4
LT		 9071
9072 tp->vlgrp = grp;
9073
9074 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9075 __tg3_set_rx_mode(dev);
9076
f47c11ee 9077 tg3_full_unlock(tp);
29315e87
MC		 9078
9079 if (netif_running(dev))
9080 tg3_netif_start(tp);
1da177e4
LT		 9081}
9082
9083static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9084{
9085 struct tg3 *tp = netdev_priv(dev);
9086
29315e87
MC		 9087 if (netif_running(dev))
9088 tg3_netif_stop(tp);
9089
f47c11ee 9090 tg3_full_lock(tp, 0);
1da177e4
LT		 9091 if (tp->vlgrp)
9092 tp->vlgrp->vlan_devices[vid] = NULL;
f47c11ee 9093 tg3_full_unlock(tp);
29315e87
MC		 9094
9095 if (netif_running(dev))
9096 tg3_netif_start(tp);
1da177e4
LT		 9097}
9098#endif
9099
15f9850d
DM		 9100static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9101{
9102 struct tg3 *tp = netdev_priv(dev);
9103
9104 memcpy(ec, &tp->coal, sizeof(*ec));
9105 return 0;
9106}
9107
d244c892
MC		 9108static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9109{
9110 struct tg3 *tp = netdev_priv(dev);
9111 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9112 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9113
9114 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9115 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9116 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9117 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9118 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9119 }
9120
9121 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9122 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9123 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9124 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9125 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9126 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9127 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9128 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9129 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9130 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9131 return -EINVAL;
9132
9133 /* No rx interrupts will be generated if both are zero */
9134 if ((ec->rx_coalesce_usecs == 0) &&
9135 (ec->rx_max_coalesced_frames == 0))
9136 return -EINVAL;
9137
9138 /* No tx interrupts will be generated if both are zero */
9139 if ((ec->tx_coalesce_usecs == 0) &&
9140 (ec->tx_max_coalesced_frames == 0))
9141 return -EINVAL;
9142
9143 /* Only copy relevant parameters, ignore all others. */
9144 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9145 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9146 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9147 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9148 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9149 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9150 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9151 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9152 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9153
9154 if (netif_running(dev)) {
9155 tg3_full_lock(tp, 0);
9156 __tg3_set_coalesce(tp, &tp->coal);
9157 tg3_full_unlock(tp);
9158 }
9159 return 0;
9160}
9161
7282d491 9162static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9163 .get_settings = tg3_get_settings,
9164 .set_settings = tg3_set_settings,
9165 .get_drvinfo = tg3_get_drvinfo,
9166 .get_regs_len = tg3_get_regs_len,
9167 .get_regs = tg3_get_regs,
9168 .get_wol = tg3_get_wol,
9169 .set_wol = tg3_set_wol,
9170 .get_msglevel = tg3_get_msglevel,
9171 .set_msglevel = tg3_set_msglevel,
9172 .nway_reset = tg3_nway_reset,
9173 .get_link = ethtool_op_get_link,
9174 .get_eeprom_len = tg3_get_eeprom_len,
9175 .get_eeprom = tg3_get_eeprom,
9176 .set_eeprom = tg3_set_eeprom,
9177 .get_ringparam = tg3_get_ringparam,
9178 .set_ringparam = tg3_set_ringparam,
9179 .get_pauseparam = tg3_get_pauseparam,
9180 .set_pauseparam = tg3_set_pauseparam,
9181 .get_rx_csum = tg3_get_rx_csum,
9182 .set_rx_csum = tg3_set_rx_csum,
9183 .get_tx_csum = ethtool_op_get_tx_csum,
9184 .set_tx_csum = tg3_set_tx_csum,
9185 .get_sg = ethtool_op_get_sg,
9186 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 9187 .get_tso = ethtool_op_get_tso,
9188 .set_tso = tg3_set_tso,
4cafd3f5
MC		 9189 .self_test_count = tg3_get_test_count,
9190 .self_test = tg3_self_test,
1da177e4 9191 .get_strings = tg3_get_strings,
4009a93d 9192 .phys_id = tg3_phys_id,
1da177e4
LT		 9193 .get_stats_count = tg3_get_stats_count,
9194 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 9195 .get_coalesce = tg3_get_coalesce,
d244c892 9196 .set_coalesce = tg3_set_coalesce,
2ff43697 9197 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 9198};
9199
9200static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9201{
1b27777a 9202 u32 cursize, val, magic;
1da177e4
LT		 9203
9204 tp->nvram_size = EEPROM_CHIP_SIZE;
9205
1820180b 9206 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 9207 return;
9208
b16250e3
MC		 9209 if ((magic != TG3_EEPROM_MAGIC) &&
9210 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9211 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 9212 return;
9213
9214 /*
9215 * Size the chip by reading offsets at increasing powers of two.
9216 * When we encounter our validation signature, we know the addressing
9217 * has wrapped around, and thus have our chip size.
9218 */
1b27777a 9219 cursize = 0x10;
1da177e4
LT		 9220
9221 while (cursize < tp->nvram_size) {
1820180b 9222 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 9223 return;
9224
1820180b 9225 if (val == magic)
1da177e4
LT		 9226 break;
9227
9228 cursize <<= 1;
9229 }
9230
9231 tp->nvram_size = cursize;
9232}
6aa20a22 9233
1da177e4
LT		 9234static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9235{
9236 u32 val;
9237
1820180b 9238 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 9239 return;
9240
9241 /* Selfboot format */
1820180b 9242 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 9243 tg3_get_eeprom_size(tp);
9244 return;
9245 }
9246
1da177e4
LT		 9247 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9248 if (val != 0) {
9249 tp->nvram_size = (val >> 16) * 1024;
9250 return;
9251 }
9252 }
9253 tp->nvram_size = 0x20000;
9254}
9255
9256static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9257{
9258 u32 nvcfg1;
9259
9260 nvcfg1 = tr32(NVRAM_CFG1);
9261 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9262 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9263 }
9264 else {
9265 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9266 tw32(NVRAM_CFG1, nvcfg1);
9267 }
9268
4c987487 9269 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 9270 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9271 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9272 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9273 tp->nvram_jedecnum = JEDEC_ATMEL;
9274 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9275 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9276 break;
9277 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9278 tp->nvram_jedecnum = JEDEC_ATMEL;
9279 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9280 break;
9281 case FLASH_VENDOR_ATMEL_EEPROM:
9282 tp->nvram_jedecnum = JEDEC_ATMEL;
9283 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9284 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9285 break;
9286 case FLASH_VENDOR_ST:
9287 tp->nvram_jedecnum = JEDEC_ST;
9288 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9289 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9290 break;
9291 case FLASH_VENDOR_SAIFUN:
9292 tp->nvram_jedecnum = JEDEC_SAIFUN;
9293 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9294 break;
9295 case FLASH_VENDOR_SST_SMALL:
9296 case FLASH_VENDOR_SST_LARGE:
9297 tp->nvram_jedecnum = JEDEC_SST;
9298 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9299 break;
9300 }
9301 }
9302 else {
9303 tp->nvram_jedecnum = JEDEC_ATMEL;
9304 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9305 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9306 }
9307}
9308
361b4ac2
MC		 9309static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9310{
9311 u32 nvcfg1;
9312
9313 nvcfg1 = tr32(NVRAM_CFG1);
9314
e6af301b
MC		 9315 /* NVRAM protection for TPM */
9316 if (nvcfg1 & (1 << 27))
9317 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9318
361b4ac2
MC		 9319 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9320 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9321 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9322 tp->nvram_jedecnum = JEDEC_ATMEL;
9323 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9324 break;
9325 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9326 tp->nvram_jedecnum = JEDEC_ATMEL;
9327 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9328 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9329 break;
9330 case FLASH_5752VENDOR_ST_M45PE10:
9331 case FLASH_5752VENDOR_ST_M45PE20:
9332 case FLASH_5752VENDOR_ST_M45PE40:
9333 tp->nvram_jedecnum = JEDEC_ST;
9334 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9335 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9336 break;
9337 }
9338
9339 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9340 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9341 case FLASH_5752PAGE_SIZE_256:
9342 tp->nvram_pagesize = 256;
9343 break;
9344 case FLASH_5752PAGE_SIZE_512:
9345 tp->nvram_pagesize = 512;
9346 break;
9347 case FLASH_5752PAGE_SIZE_1K:
9348 tp->nvram_pagesize = 1024;
9349 break;
9350 case FLASH_5752PAGE_SIZE_2K:
9351 tp->nvram_pagesize = 2048;
9352 break;
9353 case FLASH_5752PAGE_SIZE_4K:
9354 tp->nvram_pagesize = 4096;
9355 break;
9356 case FLASH_5752PAGE_SIZE_264:
9357 tp->nvram_pagesize = 264;
9358 break;
9359 }
9360 }
9361 else {
9362 /* For eeprom, set pagesize to maximum eeprom size */
9363 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9364
9365 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9366 tw32(NVRAM_CFG1, nvcfg1);
9367 }
9368}
9369
d3c7b886
MC		 9370static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9371{
9372 u32 nvcfg1;
9373
9374 nvcfg1 = tr32(NVRAM_CFG1);
9375
9376 /* NVRAM protection for TPM */
9377 if (nvcfg1 & (1 << 27))
9378 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9379
9380 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9381 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9382 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9383 tp->nvram_jedecnum = JEDEC_ATMEL;
9384 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9385 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9386
9387 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9388 tw32(NVRAM_CFG1, nvcfg1);
9389 break;
9390 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9391 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9392 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9393 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9394 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9395 tp->nvram_jedecnum = JEDEC_ATMEL;
9396 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9397 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9398 tp->nvram_pagesize = 264;
9399 break;
9400 case FLASH_5752VENDOR_ST_M45PE10:
9401 case FLASH_5752VENDOR_ST_M45PE20:
9402 case FLASH_5752VENDOR_ST_M45PE40:
9403 tp->nvram_jedecnum = JEDEC_ST;
9404 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9405 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9406 tp->nvram_pagesize = 256;
9407 break;
9408 }
9409}
9410
1b27777a
MC		 9411static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9412{
9413 u32 nvcfg1;
9414
9415 nvcfg1 = tr32(NVRAM_CFG1);
9416
9417 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9418 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9419 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9420 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9421 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9422 tp->nvram_jedecnum = JEDEC_ATMEL;
9423 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9424 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9425
9426 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9427 tw32(NVRAM_CFG1, nvcfg1);
9428 break;
9429 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9430 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9431 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9432 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9433 tp->nvram_jedecnum = JEDEC_ATMEL;
9434 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9435 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9436 tp->nvram_pagesize = 264;
9437 break;
9438 case FLASH_5752VENDOR_ST_M45PE10:
9439 case FLASH_5752VENDOR_ST_M45PE20:
9440 case FLASH_5752VENDOR_ST_M45PE40:
9441 tp->nvram_jedecnum = JEDEC_ST;
9442 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9443 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9444 tp->nvram_pagesize = 256;
9445 break;
9446 }
9447}
9448
b5d3772c
MC		 9449static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9450{
9451 tp->nvram_jedecnum = JEDEC_ATMEL;
9452 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9453 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9454}
9455
1da177e4
LT		 9456/* Chips other than 5700/5701 use the NVRAM for fetching info. */
9457static void __devinit tg3_nvram_init(struct tg3 *tp)
9458{
1da177e4
LT		 9459 tw32_f(GRC_EEPROM_ADDR,
9460 (EEPROM_ADDR_FSM_RESET |
9461 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9462 EEPROM_ADDR_CLKPERD_SHIFT)));
9463
9d57f01c 9464 msleep(1);
1da177e4
LT		 9465
9466 /* Enable seeprom accesses. */
9467 tw32_f(GRC_LOCAL_CTRL,
9468 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9469 udelay(100);
9470
9471 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9472 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9473 tp->tg3_flags |= TG3_FLAG_NVRAM;
9474
ec41c7df
MC		 9475 if (tg3_nvram_lock(tp)) {
9476 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9477 "tg3_nvram_init failed.\n", tp->dev->name);
9478 return;
9479 }
e6af301b 9480 tg3_enable_nvram_access(tp);
1da177e4 9481
361b4ac2
MC		 9482 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9483 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 9484 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9485 tg3_get_5755_nvram_info(tp);
1b27777a
MC		 9486 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9487 tg3_get_5787_nvram_info(tp);
b5d3772c
MC		 9488 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9489 tg3_get_5906_nvram_info(tp);
361b4ac2
MC		 9490 else
9491 tg3_get_nvram_info(tp);
9492
1da177e4
LT		 9493 tg3_get_nvram_size(tp);
9494
e6af301b 9495 tg3_disable_nvram_access(tp);
381291b7 9496 tg3_nvram_unlock(tp);
1da177e4
LT		 9497
9498 } else {
9499 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9500
9501 tg3_get_eeprom_size(tp);
9502 }
9503}
9504
9505static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9506 u32 offset, u32 *val)
9507{
9508 u32 tmp;
9509 int i;
9510
9511 if (offset > EEPROM_ADDR_ADDR_MASK ||
9512 (offset % 4) != 0)
9513 return -EINVAL;
9514
9515 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9516 EEPROM_ADDR_DEVID_MASK |
9517 EEPROM_ADDR_READ);
9518 tw32(GRC_EEPROM_ADDR,
9519 tmp |
9520 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9521 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9522 EEPROM_ADDR_ADDR_MASK) |
9523 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9524
9d57f01c 9525 for (i = 0; i < 1000; i++) {
1da177e4
LT		 9526 tmp = tr32(GRC_EEPROM_ADDR);
9527
9528 if (tmp & EEPROM_ADDR_COMPLETE)
9529 break;
9d57f01c 9530 msleep(1);
1da177e4
LT		 9531 }
9532 if (!(tmp & EEPROM_ADDR_COMPLETE))
9533 return -EBUSY;
9534
9535 *val = tr32(GRC_EEPROM_DATA);
9536 return 0;
9537}
9538
9539#define NVRAM_CMD_TIMEOUT 10000
9540
9541static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9542{
9543 int i;
9544
9545 tw32(NVRAM_CMD, nvram_cmd);
9546 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9547 udelay(10);
9548 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9549 udelay(10);
9550 break;
9551 }
9552 }
9553 if (i == NVRAM_CMD_TIMEOUT) {
9554 return -EBUSY;
9555 }
9556 return 0;
9557}
9558
1820180b
MC		 9559static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9560{
9561 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9562 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9563 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9564 (tp->nvram_jedecnum == JEDEC_ATMEL))
9565
9566 addr = ((addr / tp->nvram_pagesize) <<
9567 ATMEL_AT45DB0X1B_PAGE_POS) +
9568 (addr % tp->nvram_pagesize);
9569
9570 return addr;
9571}
9572
c4e6575c
MC		 9573static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9574{
9575 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9576 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9577 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9578 (tp->nvram_jedecnum == JEDEC_ATMEL))
9579
9580 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9581 tp->nvram_pagesize) +
9582 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9583
9584 return addr;
9585}
9586
1da177e4
LT		 9587static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9588{
9589 int ret;
9590
1da177e4
LT		 9591 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9592 return tg3_nvram_read_using_eeprom(tp, offset, val);
9593
1820180b 9594 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9595
9596 if (offset > NVRAM_ADDR_MSK)
9597 return -EINVAL;
9598
ec41c7df
MC		 9599 ret = tg3_nvram_lock(tp);
9600 if (ret)
9601 return ret;
1da177e4 9602
e6af301b 9603 tg3_enable_nvram_access(tp);
1da177e4
LT		 9604
9605 tw32(NVRAM_ADDR, offset);
9606 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9607 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9608
9609 if (ret == 0)
9610 *val = swab32(tr32(NVRAM_RDDATA));
9611
e6af301b 9612 tg3_disable_nvram_access(tp);
1da177e4 9613
381291b7
MC		 9614 tg3_nvram_unlock(tp);
9615
1da177e4
LT		 9616 return ret;
9617}
9618
1820180b
MC		 9619static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9620{
9621 int err;
9622 u32 tmp;
9623
9624 err = tg3_nvram_read(tp, offset, &tmp);
9625 *val = swab32(tmp);
9626 return err;
9627}
9628
1da177e4
LT		 9629static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9630 u32 offset, u32 len, u8 *buf)
9631{
9632 int i, j, rc = 0;
9633 u32 val;
9634
9635 for (i = 0; i < len; i += 4) {
9636 u32 addr, data;
9637
9638 addr = offset + i;
9639
9640 memcpy(&data, buf + i, 4);
9641
9642 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9643
9644 val = tr32(GRC_EEPROM_ADDR);
9645 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9646
9647 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9648 EEPROM_ADDR_READ);
9649 tw32(GRC_EEPROM_ADDR, val |
9650 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9651 (addr & EEPROM_ADDR_ADDR_MASK) |
9652 EEPROM_ADDR_START |
9653 EEPROM_ADDR_WRITE);
6aa20a22 9654
9d57f01c 9655 for (j = 0; j < 1000; j++) {
1da177e4
LT		 9656 val = tr32(GRC_EEPROM_ADDR);
9657
9658 if (val & EEPROM_ADDR_COMPLETE)
9659 break;
9d57f01c 9660 msleep(1);
1da177e4
LT		 9661 }
9662 if (!(val & EEPROM_ADDR_COMPLETE)) {
9663 rc = -EBUSY;
9664 break;
9665 }
9666 }
9667
9668 return rc;
9669}
9670
9671/* offset and length are dword aligned */
9672static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9673 u8 *buf)
9674{
9675 int ret = 0;
9676 u32 pagesize = tp->nvram_pagesize;
9677 u32 pagemask = pagesize - 1;
9678 u32 nvram_cmd;
9679 u8 *tmp;
9680
9681 tmp = kmalloc(pagesize, GFP_KERNEL);
9682 if (tmp == NULL)
9683 return -ENOMEM;
9684
9685 while (len) {
9686 int j;
e6af301b 9687 u32 phy_addr, page_off, size;
1da177e4
LT		 9688
9689 phy_addr = offset & ~pagemask;
6aa20a22 9690
1da177e4
LT		 9691 for (j = 0; j < pagesize; j += 4) {
9692 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9693 (u32 *) (tmp + j))))
9694 break;
9695 }
9696 if (ret)
9697 break;
9698
9699 page_off = offset & pagemask;
9700 size = pagesize;
9701 if (len < size)
9702 size = len;
9703
9704 len -= size;
9705
9706 memcpy(tmp + page_off, buf, size);
9707
9708 offset = offset + (pagesize - page_off);
9709
e6af301b 9710 tg3_enable_nvram_access(tp);
1da177e4
LT		 9711
9712 /*
9713 * Before we can erase the flash page, we need
9714 * to issue a special "write enable" command.
9715 */
9716 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9717
9718 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9719 break;
9720
9721 /* Erase the target page */
9722 tw32(NVRAM_ADDR, phy_addr);
9723
9724 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9725 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9726
9727 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9728 break;
9729
9730 /* Issue another write enable to start the write. */
9731 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9732
9733 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9734 break;
9735
9736 for (j = 0; j < pagesize; j += 4) {
9737 u32 data;
9738
9739 data = *((u32 *) (tmp + j));
9740 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9741
9742 tw32(NVRAM_ADDR, phy_addr + j);
9743
9744 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9745 NVRAM_CMD_WR;
9746
9747 if (j == 0)
9748 nvram_cmd |= NVRAM_CMD_FIRST;
9749 else if (j == (pagesize - 4))
9750 nvram_cmd |= NVRAM_CMD_LAST;
9751
9752 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9753 break;
9754 }
9755 if (ret)
9756 break;
9757 }
9758
9759 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9760 tg3_nvram_exec_cmd(tp, nvram_cmd);
9761
9762 kfree(tmp);
9763
9764 return ret;
9765}
9766
9767/* offset and length are dword aligned */
9768static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9769 u8 *buf)
9770{
9771 int i, ret = 0;
9772
9773 for (i = 0; i < len; i += 4, offset += 4) {
9774 u32 data, page_off, phy_addr, nvram_cmd;
9775
9776 memcpy(&data, buf + i, 4);
9777 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9778
9779 page_off = offset % tp->nvram_pagesize;
9780
1820180b 9781 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9782
9783 tw32(NVRAM_ADDR, phy_addr);
9784
9785 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9786
9787 if ((page_off == 0) || (i == 0))
9788 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 9789 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 9790 nvram_cmd |= NVRAM_CMD_LAST;
9791
9792 if (i == (len - 4))
9793 nvram_cmd |= NVRAM_CMD_LAST;
9794
4c987487 9795 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
af36e6b6 9796 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
1b27777a 9797 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
4c987487
MC		 9798 (tp->nvram_jedecnum == JEDEC_ST) &&
9799 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 9800
9801 if ((ret = tg3_nvram_exec_cmd(tp,
9802 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9803 NVRAM_CMD_DONE)))
9804
9805 break;
9806 }
9807 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9808 /* We always do complete word writes to eeprom. */
9809 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9810 }
9811
9812 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9813 break;
9814 }
9815 return ret;
9816}
9817
9818/* offset and length are dword aligned */
9819static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9820{
9821 int ret;
9822
1da177e4 9823 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 9824 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9825 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 9826 udelay(40);
9827 }
9828
9829 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9830 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9831 }
9832 else {
9833 u32 grc_mode;
9834
ec41c7df
MC		 9835 ret = tg3_nvram_lock(tp);
9836 if (ret)
9837 return ret;
1da177e4 9838
e6af301b
MC		 9839 tg3_enable_nvram_access(tp);
9840 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9841 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 9842 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 9843
9844 grc_mode = tr32(GRC_MODE);
9845 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9846
9847 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9848 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9849
9850 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9851 buf);
9852 }
9853 else {
9854 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9855 buf);
9856 }
9857
9858 grc_mode = tr32(GRC_MODE);
9859 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9860
e6af301b 9861 tg3_disable_nvram_access(tp);
1da177e4
LT		 9862 tg3_nvram_unlock(tp);
9863 }
9864
9865 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 9866 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 9867 udelay(40);
9868 }
9869
9870 return ret;
9871}
9872
9873struct subsys_tbl_ent {
9874 u16 subsys_vendor, subsys_devid;
9875 u32 phy_id;
9876};
9877
9878static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9879 /* Broadcom boards. */
9880 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9881 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9882 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9883 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9884 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9885 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9886 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9887 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9888 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9889 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9890 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9891
9892 /* 3com boards. */
9893 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9894 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9895 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9896 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9897 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9898
9899 /* DELL boards. */
9900 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9901 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9902 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9903 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9904
9905 /* Compaq boards. */
9906 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9907 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9908 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9909 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9910 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9911
9912 /* IBM boards. */
9913 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9914};
9915
9916static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9917{
9918 int i;
9919
9920 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9921 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9922 tp->pdev->subsystem_vendor) &&
9923 (subsys_id_to_phy_id[i].subsys_devid ==
9924 tp->pdev->subsystem_device))
9925 return &subsys_id_to_phy_id[i];
9926 }
9927 return NULL;
9928}
9929
7d0c41ef 9930static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 9931{
1da177e4 9932 u32 val;
caf636c7
MC		 9933 u16 pmcsr;
9934
9935 /* On some early chips the SRAM cannot be accessed in D3hot state,
9936 * so need make sure we're in D0.
9937 */
9938 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9939 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9940 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9941 msleep(1);
7d0c41ef
MC		 9942
9943 /* Make sure register accesses (indirect or otherwise)
9944 * will function correctly.
9945 */
9946 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9947 tp->misc_host_ctrl);
1da177e4 9948
f49639e6
DM		 9949 /* The memory arbiter has to be enabled in order for SRAM accesses
9950 * to succeed. Normally on powerup the tg3 chip firmware will make
9951 * sure it is enabled, but other entities such as system netboot
9952 * code might disable it.
9953 */
9954 val = tr32(MEMARB_MODE);
9955 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9956
1da177e4 9957 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 9958 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9959
f49639e6
DM		 9960 /* Assume an onboard device by default. */
9961 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
72b845e0 9962
b5d3772c 9963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 9964 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 9965 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 9966 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9967 }
b5d3772c
MC		 9968 return;
9969 }
9970
1da177e4
LT		 9971 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9972 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9973 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 9974 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9975 int eeprom_phy_serdes = 0;
1da177e4
LT		 9976
9977 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9978 tp->nic_sram_data_cfg = nic_cfg;
9979
9980 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9981 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9982 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9983 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9984 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9985 (ver > 0) && (ver < 0x100))
9986 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9987
1da177e4
LT		 9988 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9989 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9990 eeprom_phy_serdes = 1;
9991
9992 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9993 if (nic_phy_id != 0) {
9994 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9995 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9996
9997 eeprom_phy_id = (id1 >> 16) << 10;
9998 eeprom_phy_id |= (id2 & 0xfc00) << 16;
9999 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10000 } else
10001 eeprom_phy_id = 0;
10002
7d0c41ef 10003 tp->phy_id = eeprom_phy_id;
747e8f8b 10004 if (eeprom_phy_serdes) {
a4e2b347 10005 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 10006 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10007 else
10008 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10009 }
7d0c41ef 10010
cbf46853 10011 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10012 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10013 SHASTA_EXT_LED_MODE_MASK);
cbf46853 10014 else
1da177e4
LT		 10015 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10016
10017 switch (led_cfg) {
10018 default:
10019 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10020 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10021 break;
10022
10023 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10024 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10025 break;
10026
10027 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10028 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 10029
10030 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10031 * read on some older 5700/5701 bootcode.
10032 */
10033 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10034 ASIC_REV_5700 ||
10035 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10036 ASIC_REV_5701)
10037 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10038
1da177e4
LT		 10039 break;
10040
10041 case SHASTA_EXT_LED_SHARED:
10042 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10043 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10044 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10045 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10046 LED_CTRL_MODE_PHY_2);
10047 break;
10048
10049 case SHASTA_EXT_LED_MAC:
10050 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10051 break;
10052
10053 case SHASTA_EXT_LED_COMBO:
10054 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10055 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10056 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10057 LED_CTRL_MODE_PHY_2);
10058 break;
10059
10060 };
10061
10062 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10064 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10065 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10066
9d26e213 10067 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 10068 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10069 if ((tp->pdev->subsystem_vendor ==
10070 PCI_VENDOR_ID_ARIMA) &&
10071 (tp->pdev->subsystem_device == 0x205a ||
10072 tp->pdev->subsystem_device == 0x2063))
10073 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10074 } else {
f49639e6 10075 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10076 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10077 }
1da177e4
LT		 10078
10079 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10080 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 10081 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10082 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10083 }
10084 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10085 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10086
10087 if (cfg2 & (1 << 17))
10088 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10089
10090 /* serdes signal pre-emphasis in register 0x590 set by */
10091 /* bootcode if bit 18 is set */
10092 if (cfg2 & (1 << 18))
10093 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10094 }
7d0c41ef
MC		 10095}
10096
10097static int __devinit tg3_phy_probe(struct tg3 *tp)
10098{
10099 u32 hw_phy_id_1, hw_phy_id_2;
10100 u32 hw_phy_id, hw_phy_id_masked;
10101 int err;
1da177e4
LT		 10102
10103 /* Reading the PHY ID register can conflict with ASF
10104 * firwmare access to the PHY hardware.
10105 */
10106 err = 0;
10107 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10108 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10109 } else {
10110 /* Now read the physical PHY_ID from the chip and verify
10111 * that it is sane. If it doesn't look good, we fall back
10112 * to either the hard-coded table based PHY_ID and failing
10113 * that the value found in the eeprom area.
10114 */
10115 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10116 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10117
10118 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10119 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10120 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10121
10122 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10123 }
10124
10125 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10126 tp->phy_id = hw_phy_id;
10127 if (hw_phy_id_masked == PHY_ID_BCM8002)
10128 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 10129 else
10130 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 10131 } else {
7d0c41ef
MC		 10132 if (tp->phy_id != PHY_ID_INVALID) {
10133 /* Do nothing, phy ID already set up in
10134 * tg3_get_eeprom_hw_cfg().
10135 */
1da177e4
LT		 10136 } else {
10137 struct subsys_tbl_ent *p;
10138
10139 /* No eeprom signature? Try the hardcoded
10140 * subsys device table.
10141 */
10142 p = lookup_by_subsys(tp);
10143 if (!p)
10144 return -ENODEV;
10145
10146 tp->phy_id = p->phy_id;
10147 if (!tp->phy_id ||
10148 tp->phy_id == PHY_ID_BCM8002)
10149 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10150 }
10151 }
10152
747e8f8b 10153 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4 10154 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 10155 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 10156
10157 tg3_readphy(tp, MII_BMSR, &bmsr);
10158 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10159 (bmsr & BMSR_LSTATUS))
10160 goto skip_phy_reset;
6aa20a22 10161
1da177e4
LT		 10162 err = tg3_phy_reset(tp);
10163 if (err)
10164 return err;
10165
10166 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10167 ADVERTISE_100HALF | ADVERTISE_100FULL |
10168 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10169 tg3_ctrl = 0;
10170 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10171 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10172 MII_TG3_CTRL_ADV_1000_FULL);
10173 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10174 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10175 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10176 MII_TG3_CTRL_ENABLE_AS_MASTER);
10177 }
10178
3600d918
MC		 10179 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10180 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10181 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10182 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 10183 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10184
10185 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10186 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10187
10188 tg3_writephy(tp, MII_BMCR,
10189 BMCR_ANENABLE | BMCR_ANRESTART);
10190 }
10191 tg3_phy_set_wirespeed(tp);
10192
10193 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10194 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10195 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10196 }
10197
10198skip_phy_reset:
10199 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10200 err = tg3_init_5401phy_dsp(tp);
10201 if (err)
10202 return err;
10203 }
10204
10205 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10206 err = tg3_init_5401phy_dsp(tp);
10207 }
10208
747e8f8b 10209 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 10210 tp->link_config.advertising =
10211 (ADVERTISED_1000baseT_Half |
10212 ADVERTISED_1000baseT_Full |
10213 ADVERTISED_Autoneg |
10214 ADVERTISED_FIBRE);
10215 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10216 tp->link_config.advertising &=
10217 ~(ADVERTISED_1000baseT_Half |
10218 ADVERTISED_1000baseT_Full);
10219
10220 return err;
10221}
10222
10223static void __devinit tg3_read_partno(struct tg3 *tp)
10224{
10225 unsigned char vpd_data[256];
af2c6a4a 10226 unsigned int i;
1b27777a 10227 u32 magic;
1da177e4 10228
1820180b 10229 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 10230 goto out_not_found;
1da177e4 10231
1820180b 10232 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 10233 for (i = 0; i < 256; i += 4) {
10234 u32 tmp;
1da177e4 10235
1b27777a
MC		 10236 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10237 goto out_not_found;
10238
10239 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10240 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10241 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10242 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10243 }
10244 } else {
10245 int vpd_cap;
10246
10247 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10248 for (i = 0; i < 256; i += 4) {
10249 u32 tmp, j = 0;
10250 u16 tmp16;
10251
10252 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10253 i);
10254 while (j++ < 100) {
10255 pci_read_config_word(tp->pdev, vpd_cap +
10256 PCI_VPD_ADDR, &tmp16);
10257 if (tmp16 & 0x8000)
10258 break;
10259 msleep(1);
10260 }
f49639e6
DM		 10261 if (!(tmp16 & 0x8000))
10262 goto out_not_found;
10263
1b27777a
MC		 10264 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10265 &tmp);
10266 tmp = cpu_to_le32(tmp);
10267 memcpy(&vpd_data[i], &tmp, 4);
10268 }
1da177e4
LT		 10269 }
10270
10271 /* Now parse and find the part number. */
af2c6a4a 10272 for (i = 0; i < 254; ) {
1da177e4 10273 unsigned char val = vpd_data[i];
af2c6a4a 10274 unsigned int block_end;
1da177e4
LT		 10275
10276 if (val == 0x82 || val == 0x91) {
10277 i = (i + 3 +
10278 (vpd_data[i + 1] +
10279 (vpd_data[i + 2] << 8)));
10280 continue;
10281 }
10282
10283 if (val != 0x90)
10284 goto out_not_found;
10285
10286 block_end = (i + 3 +
10287 (vpd_data[i + 1] +
10288 (vpd_data[i + 2] << 8)));
10289 i += 3;
af2c6a4a
MC		 10290
10291 if (block_end > 256)
10292 goto out_not_found;
10293
10294 while (i < (block_end - 2)) {
1da177e4
LT		 10295 if (vpd_data[i + 0] == 'P' &&
10296 vpd_data[i + 1] == 'N') {
10297 int partno_len = vpd_data[i + 2];
10298
af2c6a4a
MC		 10299 i += 3;
10300 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 10301 goto out_not_found;
10302
10303 memcpy(tp->board_part_number,
af2c6a4a 10304 &vpd_data[i], partno_len);
1da177e4
LT		 10305
10306 /* Success. */
10307 return;
10308 }
af2c6a4a 10309 i += 3 + vpd_data[i + 2];
1da177e4
LT		 10310 }
10311
10312 /* Part number not found. */
10313 goto out_not_found;
10314 }
10315
10316out_not_found:
b5d3772c
MC		 10317 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10318 strcpy(tp->board_part_number, "BCM95906");
10319 else
10320 strcpy(tp->board_part_number, "none");
1da177e4
LT		 10321}
10322
c4e6575c
MC		 10323static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10324{
10325 u32 val, offset, start;
10326
10327 if (tg3_nvram_read_swab(tp, 0, &val))
10328 return;
10329
10330 if (val != TG3_EEPROM_MAGIC)
10331 return;
10332
10333 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10334 tg3_nvram_read_swab(tp, 0x4, &start))
10335 return;
10336
10337 offset = tg3_nvram_logical_addr(tp, offset);
10338 if (tg3_nvram_read_swab(tp, offset, &val))
10339 return;
10340
10341 if ((val & 0xfc000000) == 0x0c000000) {
10342 u32 ver_offset, addr;
10343 int i;
10344
10345 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10346 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10347 return;
10348
10349 if (val != 0)
10350 return;
10351
10352 addr = offset + ver_offset - start;
10353 for (i = 0; i < 16; i += 4) {
10354 if (tg3_nvram_read(tp, addr + i, &val))
10355 return;
10356
10357 val = cpu_to_le32(val);
10358 memcpy(tp->fw_ver + i, &val, 4);
10359 }
10360 }
10361}
10362
1da177e4
LT		 10363static int __devinit tg3_get_invariants(struct tg3 *tp)
10364{
10365 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 10366 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10367 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 10368 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10369 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 10370 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10371 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 10372 { },
10373 };
10374 u32 misc_ctrl_reg;
10375 u32 cacheline_sz_reg;
10376 u32 pci_state_reg, grc_misc_cfg;
10377 u32 val;
10378 u16 pci_cmd;
c7835a77 10379 int err, pcie_cap;
1da177e4 10380
1da177e4
LT		 10381 /* Force memory write invalidate off. If we leave it on,
10382 * then on 5700_BX chips we have to enable a workaround.
10383 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10384 * to match the cacheline size. The Broadcom driver have this
10385 * workaround but turns MWI off all the times so never uses
10386 * it. This seems to suggest that the workaround is insufficient.
10387 */
10388 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10389 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10390 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10391
10392 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10393 * has the register indirect write enable bit set before
10394 * we try to access any of the MMIO registers. It is also
10395 * critical that the PCI-X hw workaround situation is decided
10396 * before that as well.
10397 */
10398 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10399 &misc_ctrl_reg);
10400
10401 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10402 MISC_HOST_CTRL_CHIPREV_SHIFT);
10403
ff645bec
MC		 10404 /* Wrong chip ID in 5752 A0. This code can be removed later
10405 * as A0 is not in production.
10406 */
10407 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10408 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10409
6892914f
MC		 10410 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10411 * we need to disable memory and use config. cycles
10412 * only to access all registers. The 5702/03 chips
10413 * can mistakenly decode the special cycles from the
10414 * ICH chipsets as memory write cycles, causing corruption
10415 * of register and memory space. Only certain ICH bridges
10416 * will drive special cycles with non-zero data during the
10417 * address phase which can fall within the 5703's address
10418 * range. This is not an ICH bug as the PCI spec allows
10419 * non-zero address during special cycles. However, only
10420 * these ICH bridges are known to drive non-zero addresses
10421 * during special cycles.
10422 *
10423 * Since special cycles do not cross PCI bridges, we only
10424 * enable this workaround if the 5703 is on the secondary
10425 * bus of these ICH bridges.
10426 */
10427 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10428 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10429 static struct tg3_dev_id {
10430 u32 vendor;
10431 u32 device;
10432 u32 rev;
10433 } ich_chipsets[] = {
10434 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10435 PCI_ANY_ID },
10436 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10437 PCI_ANY_ID },
10438 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10439 0xa },
10440 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10441 PCI_ANY_ID },
10442 { },
10443 };
10444 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10445 struct pci_dev *bridge = NULL;
10446
10447 while (pci_id->vendor != 0) {
10448 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10449 bridge);
10450 if (!bridge) {
10451 pci_id++;
10452 continue;
10453 }
10454 if (pci_id->rev != PCI_ANY_ID) {
10455 u8 rev;
10456
10457 pci_read_config_byte(bridge, PCI_REVISION_ID,
10458 &rev);
10459 if (rev > pci_id->rev)
10460 continue;
10461 }
10462 if (bridge->subordinate &&
10463 (bridge->subordinate->number ==
10464 tp->pdev->bus->number)) {
10465
10466 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10467 pci_dev_put(bridge);
10468 break;
10469 }
10470 }
10471 }
10472
4a29cc2e
MC		 10473 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10474 * DMA addresses > 40-bit. This bridge may have other additional
10475 * 57xx devices behind it in some 4-port NIC designs for example.
10476 * Any tg3 device found behind the bridge will also need the 40-bit
10477 * DMA workaround.
10478 */
a4e2b347
MC		 10479 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10480 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10481 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 10482 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 10483 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 10484 }
4a29cc2e
MC		 10485 else {
10486 struct pci_dev *bridge = NULL;
10487
10488 do {
10489 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10490 PCI_DEVICE_ID_SERVERWORKS_EPB,
10491 bridge);
10492 if (bridge && bridge->subordinate &&
10493 (bridge->subordinate->number <=
10494 tp->pdev->bus->number) &&
10495 (bridge->subordinate->subordinate >=
10496 tp->pdev->bus->number)) {
10497 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10498 pci_dev_put(bridge);
10499 break;
10500 }
10501 } while (bridge);
10502 }
4cf78e4f 10503
1da177e4
LT		 10504 /* Initialize misc host control in PCI block. */
10505 tp->misc_host_ctrl |= (misc_ctrl_reg &
10506 MISC_HOST_CTRL_CHIPREV);
10507 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10508 tp->misc_host_ctrl);
10509
10510 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10511 &cacheline_sz_reg);
10512
10513 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10514 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10515 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10516 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10517
6708e5cc 10518 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 10519 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 10520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 10521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
b5d3772c 10522 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
a4e2b347 10523 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 10524 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10525
1b440c56
JL		 10526 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10527 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10528 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10529
5a6f3074 10530 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
af36e6b6 10531 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 10534 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 10535 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83
MC		 10536 } else {
10537 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10538 TG3_FLG2_HW_TSO_1_BUG;
10539 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10540 ASIC_REV_5750 &&
10541 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10542 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10543 }
5a6f3074 10544 }
1da177e4 10545
0f893dc6
MC		 10546 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10547 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
d9ab5ad1 10548 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
af36e6b6 10549 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
b5d3772c
MC		 10550 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10551 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
0f893dc6
MC		 10552 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10553
c7835a77
MC		 10554 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10555 if (pcie_cap != 0) {
1da177e4 10556 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
c7835a77
MC		 10557 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10558 u16 lnkctl;
10559
10560 pci_read_config_word(tp->pdev,
10561 pcie_cap + PCI_EXP_LNKCTL,
10562 &lnkctl);
10563 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10564 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10565 }
10566 }
1da177e4 10567
399de50b
MC		 10568 /* If we have an AMD 762 or VIA K8T800 chipset, write
10569 * reordering to the mailbox registers done by the host
10570 * controller can cause major troubles. We read back from
10571 * every mailbox register write to force the writes to be
10572 * posted to the chip in order.
10573 */
10574 if (pci_dev_present(write_reorder_chipsets) &&
10575 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10576 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10577
1da177e4
LT		 10578 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10579 tp->pci_lat_timer < 64) {
10580 tp->pci_lat_timer = 64;
10581
10582 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10583 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10584 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10585 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10586
10587 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10588 cacheline_sz_reg);
10589 }
10590
10591 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10592 &pci_state_reg);
10593
10594 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10595 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10596
10597 /* If this is a 5700 BX chipset, and we are in PCI-X
10598 * mode, enable register write workaround.
10599 *
10600 * The workaround is to use indirect register accesses
10601 * for all chip writes not to mailbox registers.
10602 */
10603 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10604 u32 pm_reg;
10605 u16 pci_cmd;
10606
10607 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10608
10609 /* The chip can have it's power management PCI config
10610 * space registers clobbered due to this bug.
10611 * So explicitly force the chip into D0 here.
10612 */
10613 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10614 &pm_reg);
10615 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10616 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10617 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10618 pm_reg);
10619
10620 /* Also, force SERR#/PERR# in PCI command. */
10621 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10622 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10623 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10624 }
10625 }
10626
087fe256
MC		 10627 /* 5700 BX chips need to have their TX producer index mailboxes
10628 * written twice to workaround a bug.
10629 */
10630 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10631 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10632
1da177e4
LT		 10633 /* Back to back register writes can cause problems on this chip,
10634 * the workaround is to read back all reg writes except those to
10635 * mailbox regs. See tg3_write_indirect_reg32().
10636 *
10637 * PCI Express 5750_A0 rev chips need this workaround too.
10638 */
10639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10640 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10641 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10642 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10643
10644 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10645 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10646 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10647 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10648
10649 /* Chip-specific fixup from Broadcom driver */
10650 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10651 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10652 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10653 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10654 }
10655
1ee582d8 10656 /* Default fast path register access methods */
20094930 10657 tp->read32 = tg3_read32;
1ee582d8 10658 tp->write32 = tg3_write32;
09ee929c 10659 tp->read32_mbox = tg3_read32;
20094930 10660 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 10661 tp->write32_tx_mbox = tg3_write32;
10662 tp->write32_rx_mbox = tg3_write32;
10663
10664 /* Various workaround register access methods */
10665 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10666 tp->write32 = tg3_write_indirect_reg32;
10667 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10668 tp->write32 = tg3_write_flush_reg32;
10669
10670 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10671 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10672 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10673 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10674 tp->write32_rx_mbox = tg3_write_flush_reg32;
10675 }
20094930 10676
6892914f
MC		 10677 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10678 tp->read32 = tg3_read_indirect_reg32;
10679 tp->write32 = tg3_write_indirect_reg32;
10680 tp->read32_mbox = tg3_read_indirect_mbox;
10681 tp->write32_mbox = tg3_write_indirect_mbox;
10682 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10683 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10684
10685 iounmap(tp->regs);
22abe310 10686 tp->regs = NULL;
6892914f
MC		 10687
10688 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10689 pci_cmd &= ~PCI_COMMAND_MEMORY;
10690 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10691 }
b5d3772c
MC		 10692 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10693 tp->read32_mbox = tg3_read32_mbox_5906;
10694 tp->write32_mbox = tg3_write32_mbox_5906;
10695 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10696 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10697 }
6892914f 10698
bbadf503
MC		 10699 if (tp->write32 == tg3_write_indirect_reg32 ||
10700 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10701 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 10702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 10703 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10704
7d0c41ef 10705 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 10706 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 10707 * determined before calling tg3_set_power_state() so that
10708 * we know whether or not to switch out of Vaux power.
10709 * When the flag is set, it means that GPIO1 is used for eeprom
10710 * write protect and also implies that it is a LOM where GPIOs
10711 * are not used to switch power.
6aa20a22 10712 */
7d0c41ef
MC		 10713 tg3_get_eeprom_hw_cfg(tp);
10714
314fba34
MC		 10715 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10716 * GPIO1 driven high will bring 5700's external PHY out of reset.
10717 * It is also used as eeprom write protect on LOMs.
10718 */
10719 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10720 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10721 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10722 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10723 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 10724 /* Unused GPIO3 must be driven as output on 5752 because there
10725 * are no pull-up resistors on unused GPIO pins.
10726 */
10727 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10728 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 10729
af36e6b6
MC		 10730 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10731 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10732
1da177e4 10733 /* Force the chip into D0. */
bc1c7567 10734 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 10735 if (err) {
10736 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10737 pci_name(tp->pdev));
10738 return err;
10739 }
10740
10741 /* 5700 B0 chips do not support checksumming correctly due
10742 * to hardware bugs.
10743 */
10744 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10745 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10746
1da177e4
LT		 10747 /* Derive initial jumbo mode from MTU assigned in
10748 * ether_setup() via the alloc_etherdev() call
10749 */
0f893dc6 10750 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 10751 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 10752 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 10753
10754 /* Determine WakeOnLan speed to use. */
10755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10756 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10757 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10758 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10759 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10760 } else {
10761 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10762 }
10763
10764 /* A few boards don't want Ethernet@WireSpeed phy feature */
10765 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10766 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10767 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 10768 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 10769 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 10770 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 10771 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10772
10773 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10774 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10775 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10776 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10777 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10778
c424cb24
MC		 10779 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
c1d2a196 10781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
d4011ada
MC		 10782 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10783 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10784 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 10785 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10786 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10787 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
c424cb24
MC		 10788 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10789 }
1da177e4 10790
1da177e4 10791 tp->coalesce_mode = 0;
1da177e4
LT		 10792 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10793 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10794 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10795
10796 /* Initialize MAC MI mode, polling disabled. */
10797 tw32_f(MAC_MI_MODE, tp->mi_mode);
10798 udelay(80);
10799
10800 /* Initialize data/descriptor byte/word swapping. */
10801 val = tr32(GRC_MODE);
10802 val &= GRC_MODE_HOST_STACKUP;
10803 tw32(GRC_MODE, val | tp->grc_mode);
10804
10805 tg3_switch_clocks(tp);
10806
10807 /* Clear this out for sanity. */
10808 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10809
10810 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10811 &pci_state_reg);
10812 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10813 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10814 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10815
10816 if (chiprevid == CHIPREV_ID_5701_A0 ||
10817 chiprevid == CHIPREV_ID_5701_B0 ||
10818 chiprevid == CHIPREV_ID_5701_B2 ||
10819 chiprevid == CHIPREV_ID_5701_B5) {
10820 void __iomem *sram_base;
10821
10822 /* Write some dummy words into the SRAM status block
10823 * area, see if it reads back correctly. If the return
10824 * value is bad, force enable the PCIX workaround.
10825 */
10826 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10827
10828 writel(0x00000000, sram_base);
10829 writel(0x00000000, sram_base + 4);
10830 writel(0xffffffff, sram_base + 4);
10831 if (readl(sram_base) != 0x00000000)
10832 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10833 }
10834 }
10835
10836 udelay(50);
10837 tg3_nvram_init(tp);
10838
10839 grc_misc_cfg = tr32(GRC_MISC_CFG);
10840 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10841
10842 /* Broadcom's driver says that CIOBE multisplit has a bug */
10843#if 0
10844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10845 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10846 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10847 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10848 }
10849#endif
10850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10851 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10852 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10853 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10854
fac9b83e
DM		 10855 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10856 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10857 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10858 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10859 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10860 HOSTCC_MODE_CLRTICK_TXBD);
10861
10862 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10863 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10864 tp->misc_host_ctrl);
10865 }
10866
1da177e4
LT		 10867 /* these are limited to 10/100 only */
10868 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10869 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10870 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10871 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10872 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10873 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10874 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10875 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10876 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 10877 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10878 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
b5d3772c 10879 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 10880 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10881
10882 err = tg3_phy_probe(tp);
10883 if (err) {
10884 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10885 pci_name(tp->pdev), err);
10886 /* ... but do not return immediately ... */
10887 }
10888
10889 tg3_read_partno(tp);
c4e6575c 10890 tg3_read_fw_ver(tp);
1da177e4
LT		 10891
10892 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10893 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10894 } else {
10895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10896 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10897 else
10898 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10899 }
10900
10901 /* 5700 {AX,BX} chips have a broken status block link
10902 * change bit implementation, so we must use the
10903 * status register in those cases.
10904 */
10905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10906 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10907 else
10908 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10909
10910 /* The led_ctrl is set during tg3_phy_probe, here we might
10911 * have to force the link status polling mechanism based
10912 * upon subsystem IDs.
10913 */
10914 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10915 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10916 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10917 TG3_FLAG_USE_LINKCHG_REG);
10918 }
10919
10920 /* For all SERDES we poll the MAC status register. */
10921 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10922 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10923 else
10924 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10925
5a6f3074 10926 /* All chips before 5787 can get confused if TX buffers
1da177e4
LT		 10927 * straddle the 4GB address boundary in some cases.
10928 */
af36e6b6 10929 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5a6f3074
MC		 10932 tp->dev->hard_start_xmit = tg3_start_xmit;
10933 else
10934 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
1da177e4
LT		 10935
10936 tp->rx_offset = 2;
10937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10938 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10939 tp->rx_offset = 0;
10940
f92905de
MC		 10941 tp->rx_std_max_post = TG3_RX_RING_SIZE;
10942
10943 /* Increment the rx prod index on the rx std ring by at most
10944 * 8 for these chips to workaround hw errata.
10945 */
10946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10949 tp->rx_std_max_post = 8;
10950
1da177e4
LT		 10951 /* By default, disable wake-on-lan. User can change this
10952 * using ETHTOOL_SWOL.
10953 */
10954 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10955
10956 return err;
10957}
10958
10959#ifdef CONFIG_SPARC64
10960static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10961{
10962 struct net_device *dev = tp->dev;
10963 struct pci_dev *pdev = tp->pdev;
10964 struct pcidev_cookie *pcp = pdev->sysdata;
10965
10966 if (pcp != NULL) {
de8d28b1
DM		 10967 unsigned char *addr;
10968 int len;
1da177e4 10969
de8d28b1
DM		 10970 addr = of_get_property(pcp->prom_node, "local-mac-address",
10971 &len);
10972 if (addr && len == 6) {
10973 memcpy(dev->dev_addr, addr, 6);
2ff43697 10974 memcpy(dev->perm_addr, dev->dev_addr, 6);
1da177e4
LT		 10975 return 0;
10976 }
10977 }
10978 return -ENODEV;
10979}
10980
10981static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10982{
10983 struct net_device *dev = tp->dev;
10984
10985 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 10986 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 10987 return 0;
10988}
10989#endif
10990
10991static int __devinit tg3_get_device_address(struct tg3 *tp)
10992{
10993 struct net_device *dev = tp->dev;
10994 u32 hi, lo, mac_offset;
008652b3 10995 int addr_ok = 0;
1da177e4
LT		 10996
10997#ifdef CONFIG_SPARC64
10998 if (!tg3_get_macaddr_sparc(tp))
10999 return 0;
11000#endif
11001
11002 mac_offset = 0x7c;
f49639e6 11003 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 11004 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 11005 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11006 mac_offset = 0xcc;
11007 if (tg3_nvram_lock(tp))
11008 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11009 else
11010 tg3_nvram_unlock(tp);
11011 }
b5d3772c
MC		 11012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11013 mac_offset = 0x10;
1da177e4
LT		 11014
11015 /* First try to get it from MAC address mailbox. */
11016 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11017 if ((hi >> 16) == 0x484b) {
11018 dev->dev_addr[0] = (hi >> 8) & 0xff;
11019 dev->dev_addr[1] = (hi >> 0) & 0xff;
11020
11021 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11022 dev->dev_addr[2] = (lo >> 24) & 0xff;
11023 dev->dev_addr[3] = (lo >> 16) & 0xff;
11024 dev->dev_addr[4] = (lo >> 8) & 0xff;
11025 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 11026
008652b3
MC		 11027 /* Some old bootcode may report a 0 MAC address in SRAM */
11028 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11029 }
11030 if (!addr_ok) {
11031 /* Next, try NVRAM. */
f49639e6 11032 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 11033 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11034 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11035 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11036 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11037 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11038 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11039 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11040 }
11041 /* Finally just fetch it out of the MAC control regs. */
11042 else {
11043 hi = tr32(MAC_ADDR_0_HIGH);
11044 lo = tr32(MAC_ADDR_0_LOW);
11045
11046 dev->dev_addr[5] = lo & 0xff;
11047 dev->dev_addr[4] = (lo >> 8) & 0xff;
11048 dev->dev_addr[3] = (lo >> 16) & 0xff;
11049 dev->dev_addr[2] = (lo >> 24) & 0xff;
11050 dev->dev_addr[1] = hi & 0xff;
11051 dev->dev_addr[0] = (hi >> 8) & 0xff;
11052 }
1da177e4
LT		 11053 }
11054
11055 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11056#ifdef CONFIG_SPARC64
11057 if (!tg3_get_default_macaddr_sparc(tp))
11058 return 0;
11059#endif
11060 return -EINVAL;
11061 }
2ff43697 11062 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 11063 return 0;
11064}
11065
59e6b434
DM		 11066#define BOUNDARY_SINGLE_CACHELINE 1
11067#define BOUNDARY_MULTI_CACHELINE 2
11068
11069static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11070{
11071 int cacheline_size;
11072 u8 byte;
11073 int goal;
11074
11075 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11076 if (byte == 0)
11077 cacheline_size = 1024;
11078 else
11079 cacheline_size = (int) byte * 4;
11080
11081 /* On 5703 and later chips, the boundary bits have no
11082 * effect.
11083 */
11084 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11085 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11086 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11087 goto out;
11088
11089#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11090 goal = BOUNDARY_MULTI_CACHELINE;
11091#else
11092#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11093 goal = BOUNDARY_SINGLE_CACHELINE;
11094#else
11095 goal = 0;
11096#endif
11097#endif
11098
11099 if (!goal)
11100 goto out;
11101
11102 /* PCI controllers on most RISC systems tend to disconnect
11103 * when a device tries to burst across a cache-line boundary.
11104 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11105 *
11106 * Unfortunately, for PCI-E there are only limited
11107 * write-side controls for this, and thus for reads
11108 * we will still get the disconnects. We'll also waste
11109 * these PCI cycles for both read and write for chips
11110 * other than 5700 and 5701 which do not implement the
11111 * boundary bits.
11112 */
11113 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11114 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11115 switch (cacheline_size) {
11116 case 16:
11117 case 32:
11118 case 64:
11119 case 128:
11120 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11121 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11122 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11123 } else {
11124 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11125 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11126 }
11127 break;
11128
11129 case 256:
11130 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11131 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11132 break;
11133
11134 default:
11135 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11136 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11137 break;
11138 };
11139 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11140 switch (cacheline_size) {
11141 case 16:
11142 case 32:
11143 case 64:
11144 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11145 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11146 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11147 break;
11148 }
11149 /* fallthrough */
11150 case 128:
11151 default:
11152 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11153 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11154 break;
11155 };
11156 } else {
11157 switch (cacheline_size) {
11158 case 16:
11159 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11160 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11161 DMA_RWCTRL_WRITE_BNDRY_16);
11162 break;
11163 }
11164 /* fallthrough */
11165 case 32:
11166 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11167 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11168 DMA_RWCTRL_WRITE_BNDRY_32);
11169 break;
11170 }
11171 /* fallthrough */
11172 case 64:
11173 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11174 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11175 DMA_RWCTRL_WRITE_BNDRY_64);
11176 break;
11177 }
11178 /* fallthrough */
11179 case 128:
11180 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11181 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11182 DMA_RWCTRL_WRITE_BNDRY_128);
11183 break;
11184 }
11185 /* fallthrough */
11186 case 256:
11187 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11188 DMA_RWCTRL_WRITE_BNDRY_256);
11189 break;
11190 case 512:
11191 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11192 DMA_RWCTRL_WRITE_BNDRY_512);
11193 break;
11194 case 1024:
11195 default:
11196 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11197 DMA_RWCTRL_WRITE_BNDRY_1024);
11198 break;
11199 };
11200 }
11201
11202out:
11203 return val;
11204}
11205
1da177e4
LT		 11206static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11207{
11208 struct tg3_internal_buffer_desc test_desc;
11209 u32 sram_dma_descs;
11210 int i, ret;
11211
11212 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11213
11214 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11215 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11216 tw32(RDMAC_STATUS, 0);
11217 tw32(WDMAC_STATUS, 0);
11218
11219 tw32(BUFMGR_MODE, 0);
11220 tw32(FTQ_RESET, 0);
11221
11222 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11223 test_desc.addr_lo = buf_dma & 0xffffffff;
11224 test_desc.nic_mbuf = 0x00002100;
11225 test_desc.len = size;
11226
11227 /*
11228 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11229 * the *second* time the tg3 driver was getting loaded after an
11230 * initial scan.
11231 *
11232 * Broadcom tells me:
11233 * ...the DMA engine is connected to the GRC block and a DMA
11234 * reset may affect the GRC block in some unpredictable way...
11235 * The behavior of resets to individual blocks has not been tested.
11236 *
11237 * Broadcom noted the GRC reset will also reset all sub-components.
11238 */
11239 if (to_device) {
11240 test_desc.cqid_sqid = (13 << 8) | 2;
11241
11242 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11243 udelay(40);
11244 } else {
11245 test_desc.cqid_sqid = (16 << 8) | 7;
11246
11247 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11248 udelay(40);
11249 }
11250 test_desc.flags = 0x00000005;
11251
11252 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11253 u32 val;
11254
11255 val = *(((u32 *)&test_desc) + i);
11256 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11257 sram_dma_descs + (i * sizeof(u32)));
11258 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11259 }
11260 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11261
11262 if (to_device) {
11263 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11264 } else {
11265 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11266 }
11267
11268 ret = -ENODEV;
11269 for (i = 0; i < 40; i++) {
11270 u32 val;
11271
11272 if (to_device)
11273 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11274 else
11275 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11276 if ((val & 0xffff) == sram_dma_descs) {
11277 ret = 0;
11278 break;
11279 }
11280
11281 udelay(100);
11282 }
11283
11284 return ret;
11285}
11286
ded7340d 11287#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 11288
11289static int __devinit tg3_test_dma(struct tg3 *tp)
11290{
11291 dma_addr_t buf_dma;
59e6b434 11292 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 11293 int ret;
11294
11295 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11296 if (!buf) {
11297 ret = -ENOMEM;
11298 goto out_nofree;
11299 }
11300
11301 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11302 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11303
59e6b434 11304 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 11305
11306 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11307 /* DMA read watermark not used on PCIE */
11308 tp->dma_rwctrl |= 0x00180000;
11309 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 11310 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 11312 tp->dma_rwctrl |= 0x003f0000;
11313 else
11314 tp->dma_rwctrl |= 0x003f000f;
11315 } else {
11316 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11318 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 11319 u32 read_water = 0x7;
1da177e4 11320
4a29cc2e
MC		 11321 /* If the 5704 is behind the EPB bridge, we can
11322 * do the less restrictive ONE_DMA workaround for
11323 * better performance.
11324 */
11325 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11326 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11327 tp->dma_rwctrl |= 0x8000;
11328 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 11329 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11330
49afdeb6
MC		 11331 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11332 read_water = 4;
59e6b434 11333 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 11334 tp->dma_rwctrl |=
11335 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11336 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11337 (1 << 23);
4cf78e4f
MC		 11338 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11339 /* 5780 always in PCIX mode */
11340 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 11341 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11342 /* 5714 always in PCIX mode */
11343 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 11344 } else {
11345 tp->dma_rwctrl |= 0x001b000f;
11346 }
11347 }
11348
11349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11350 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11351 tp->dma_rwctrl &= 0xfffffff0;
11352
11353 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11355 /* Remove this if it causes problems for some boards. */
11356 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11357
11358 /* On 5700/5701 chips, we need to set this bit.
11359 * Otherwise the chip will issue cacheline transactions
11360 * to streamable DMA memory with not all the byte
11361 * enables turned on. This is an error on several
11362 * RISC PCI controllers, in particular sparc64.
11363 *
11364 * On 5703/5704 chips, this bit has been reassigned
11365 * a different meaning. In particular, it is used
11366 * on those chips to enable a PCI-X workaround.
11367 */
11368 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11369 }
11370
11371 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11372
11373#if 0
11374 /* Unneeded, already done by tg3_get_invariants. */
11375 tg3_switch_clocks(tp);
11376#endif
11377
11378 ret = 0;
11379 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11380 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11381 goto out;
11382
59e6b434
DM		 11383 /* It is best to perform DMA test with maximum write burst size
11384 * to expose the 5700/5701 write DMA bug.
11385 */
11386 saved_dma_rwctrl = tp->dma_rwctrl;
11387 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11388 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11389
1da177e4
LT		 11390 while (1) {
11391 u32 *p = buf, i;
11392
11393 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11394 p[i] = i;
11395
11396 /* Send the buffer to the chip. */
11397 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11398 if (ret) {
11399 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11400 break;
11401 }
11402
11403#if 0
11404 /* validate data reached card RAM correctly. */
11405 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11406 u32 val;
11407 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11408 if (le32_to_cpu(val) != p[i]) {
11409 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11410 /* ret = -ENODEV here? */
11411 }
11412 p[i] = 0;
11413 }
11414#endif
11415 /* Now read it back. */
11416 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11417 if (ret) {
11418 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11419
11420 break;
11421 }
11422
11423 /* Verify it. */
11424 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11425 if (p[i] == i)
11426 continue;
11427
59e6b434
DM		 11428 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11429 DMA_RWCTRL_WRITE_BNDRY_16) {
11430 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 11431 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11432 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11433 break;
11434 } else {
11435 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11436 ret = -ENODEV;
11437 goto out;
11438 }
11439 }
11440
11441 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11442 /* Success. */
11443 ret = 0;
11444 break;
11445 }
11446 }
59e6b434
DM		 11447 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11448 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 11449 static struct pci_device_id dma_wait_state_chipsets[] = {
11450 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11451 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11452 { },
11453 };
11454
59e6b434 11455 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 11456 * now look for chipsets that are known to expose the
11457 * DMA bug without failing the test.
59e6b434 11458 */
6d1cfbab
MC		 11459 if (pci_dev_present(dma_wait_state_chipsets)) {
11460 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11461 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11462 }
11463 else
11464 /* Safe to use the calculated DMA boundary. */
11465 tp->dma_rwctrl = saved_dma_rwctrl;
11466
59e6b434
DM		 11467 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11468 }
1da177e4
LT		 11469
11470out:
11471 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11472out_nofree:
11473 return ret;
11474}
11475
11476static void __devinit tg3_init_link_config(struct tg3 *tp)
11477{
11478 tp->link_config.advertising =
11479 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11480 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11481 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11482 ADVERTISED_Autoneg | ADVERTISED_MII);
11483 tp->link_config.speed = SPEED_INVALID;
11484 tp->link_config.duplex = DUPLEX_INVALID;
11485 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 11486 tp->link_config.active_speed = SPEED_INVALID;
11487 tp->link_config.active_duplex = DUPLEX_INVALID;
11488 tp->link_config.phy_is_low_power = 0;
11489 tp->link_config.orig_speed = SPEED_INVALID;
11490 tp->link_config.orig_duplex = DUPLEX_INVALID;
11491 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11492}
11493
11494static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11495{
fdfec172
MC		 11496 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11497 tp->bufmgr_config.mbuf_read_dma_low_water =
11498 DEFAULT_MB_RDMA_LOW_WATER_5705;
11499 tp->bufmgr_config.mbuf_mac_rx_low_water =
11500 DEFAULT_MB_MACRX_LOW_WATER_5705;
11501 tp->bufmgr_config.mbuf_high_water =
11502 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 11503 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11504 tp->bufmgr_config.mbuf_mac_rx_low_water =
11505 DEFAULT_MB_MACRX_LOW_WATER_5906;
11506 tp->bufmgr_config.mbuf_high_water =
11507 DEFAULT_MB_HIGH_WATER_5906;
11508 }
fdfec172
MC		 11509
11510 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11511 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11512 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11513 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11514 tp->bufmgr_config.mbuf_high_water_jumbo =
11515 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11516 } else {
11517 tp->bufmgr_config.mbuf_read_dma_low_water =
11518 DEFAULT_MB_RDMA_LOW_WATER;
11519 tp->bufmgr_config.mbuf_mac_rx_low_water =
11520 DEFAULT_MB_MACRX_LOW_WATER;
11521 tp->bufmgr_config.mbuf_high_water =
11522 DEFAULT_MB_HIGH_WATER;
11523
11524 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11525 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11526 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11527 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11528 tp->bufmgr_config.mbuf_high_water_jumbo =
11529 DEFAULT_MB_HIGH_WATER_JUMBO;
11530 }
1da177e4
LT		 11531
11532 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11533 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11534}
11535
11536static char * __devinit tg3_phy_string(struct tg3 *tp)
11537{
11538 switch (tp->phy_id & PHY_ID_MASK) {
11539 case PHY_ID_BCM5400: return "5400";
11540 case PHY_ID_BCM5401: return "5401";
11541 case PHY_ID_BCM5411: return "5411";
11542 case PHY_ID_BCM5701: return "5701";
11543 case PHY_ID_BCM5703: return "5703";
11544 case PHY_ID_BCM5704: return "5704";
11545 case PHY_ID_BCM5705: return "5705";
11546 case PHY_ID_BCM5750: return "5750";
85e94ced 11547 case PHY_ID_BCM5752: return "5752";
a4e2b347 11548 case PHY_ID_BCM5714: return "5714";
4cf78e4f 11549 case PHY_ID_BCM5780: return "5780";
af36e6b6 11550 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 11551 case PHY_ID_BCM5787: return "5787";
126a3368 11552 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 11553 case PHY_ID_BCM5906: return "5906";
1da177e4
LT		 11554 case PHY_ID_BCM8002: return "8002/serdes";
11555 case 0: return "serdes";
11556 default: return "unknown";
11557 };
11558}
11559
f9804ddb
MC		 11560static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11561{
11562 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11563 strcpy(str, "PCI Express");
11564 return str;
11565 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11566 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11567
11568 strcpy(str, "PCIX:");
11569
11570 if ((clock_ctrl == 7) ||
11571 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11572 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11573 strcat(str, "133MHz");
11574 else if (clock_ctrl == 0)
11575 strcat(str, "33MHz");
11576 else if (clock_ctrl == 2)
11577 strcat(str, "50MHz");
11578 else if (clock_ctrl == 4)
11579 strcat(str, "66MHz");
11580 else if (clock_ctrl == 6)
11581 strcat(str, "100MHz");
f9804ddb
MC		 11582 } else {
11583 strcpy(str, "PCI:");
11584 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11585 strcat(str, "66MHz");
11586 else
11587 strcat(str, "33MHz");
11588 }
11589 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11590 strcat(str, ":32-bit");
11591 else
11592 strcat(str, ":64-bit");
11593 return str;
11594}
11595
8c2dc7e1 11596static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 11597{
11598 struct pci_dev *peer;
11599 unsigned int func, devnr = tp->pdev->devfn & ~7;
11600
11601 for (func = 0; func < 8; func++) {
11602 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11603 if (peer && peer != tp->pdev)
11604 break;
11605 pci_dev_put(peer);
11606 }
16fe9d74
MC		 11607 /* 5704 can be configured in single-port mode, set peer to
11608 * tp->pdev in that case.
11609 */
11610 if (!peer) {
11611 peer = tp->pdev;
11612 return peer;
11613 }
1da177e4
LT		 11614
11615 /*
11616 * We don't need to keep the refcount elevated; there's no way
11617 * to remove one half of this device without removing the other
11618 */
11619 pci_dev_put(peer);
11620
11621 return peer;
11622}
11623
15f9850d
DM		 11624static void __devinit tg3_init_coal(struct tg3 *tp)
11625{
11626 struct ethtool_coalesce *ec = &tp->coal;
11627
11628 memset(ec, 0, sizeof(*ec));
11629 ec->cmd = ETHTOOL_GCOALESCE;
11630 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11631 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11632 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11633 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11634 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11635 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11636 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11637 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11638 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11639
11640 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11641 HOSTCC_MODE_CLRTICK_TXBD)) {
11642 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11643 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11644 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11645 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11646 }
d244c892
MC		 11647
11648 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11649 ec->rx_coalesce_usecs_irq = 0;
11650 ec->tx_coalesce_usecs_irq = 0;
11651 ec->stats_block_coalesce_usecs = 0;
11652 }
15f9850d
DM		 11653}
11654
1da177e4
LT		 11655static int __devinit tg3_init_one(struct pci_dev *pdev,
11656 const struct pci_device_id *ent)
11657{
11658 static int tg3_version_printed = 0;
11659 unsigned long tg3reg_base, tg3reg_len;
11660 struct net_device *dev;
11661 struct tg3 *tp;
72f2afb8 11662 int i, err, pm_cap;
f9804ddb 11663 char str[40];
72f2afb8 11664 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 11665
11666 if (tg3_version_printed++ == 0)
11667 printk(KERN_INFO "%s", version);
11668
11669 err = pci_enable_device(pdev);
11670 if (err) {
11671 printk(KERN_ERR PFX "Cannot enable PCI device, "
11672 "aborting.\n");
11673 return err;
11674 }
11675
11676 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11677 printk(KERN_ERR PFX "Cannot find proper PCI device "
11678 "base address, aborting.\n");
11679 err = -ENODEV;
11680 goto err_out_disable_pdev;
11681 }
11682
11683 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11684 if (err) {
11685 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11686 "aborting.\n");
11687 goto err_out_disable_pdev;
11688 }
11689
11690 pci_set_master(pdev);
11691
11692 /* Find power-management capability. */
11693 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11694 if (pm_cap == 0) {
11695 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11696 "aborting.\n");
11697 err = -EIO;
11698 goto err_out_free_res;
11699 }
11700
1da177e4
LT		 11701 tg3reg_base = pci_resource_start(pdev, 0);
11702 tg3reg_len = pci_resource_len(pdev, 0);
11703
11704 dev = alloc_etherdev(sizeof(*tp));
11705 if (!dev) {
11706 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11707 err = -ENOMEM;
11708 goto err_out_free_res;
11709 }
11710
11711 SET_MODULE_OWNER(dev);
11712 SET_NETDEV_DEV(dev, &pdev->dev);
11713
1da177e4
LT		 11714#if TG3_VLAN_TAG_USED
11715 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11716 dev->vlan_rx_register = tg3_vlan_rx_register;
11717 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11718#endif
11719
11720 tp = netdev_priv(dev);
11721 tp->pdev = pdev;
11722 tp->dev = dev;
11723 tp->pm_cap = pm_cap;
11724 tp->mac_mode = TG3_DEF_MAC_MODE;
11725 tp->rx_mode = TG3_DEF_RX_MODE;
11726 tp->tx_mode = TG3_DEF_TX_MODE;
11727 tp->mi_mode = MAC_MI_MODE_BASE;
11728 if (tg3_debug > 0)
11729 tp->msg_enable = tg3_debug;
11730 else
11731 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11732
11733 /* The word/byte swap controls here control register access byte
11734 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11735 * setting below.
11736 */
11737 tp->misc_host_ctrl =
11738 MISC_HOST_CTRL_MASK_PCI_INT |
11739 MISC_HOST_CTRL_WORD_SWAP |
11740 MISC_HOST_CTRL_INDIR_ACCESS |
11741 MISC_HOST_CTRL_PCISTATE_RW;
11742
11743 /* The NONFRM (non-frame) byte/word swap controls take effect
11744 * on descriptor entries, anything which isn't packet data.
11745 *
11746 * The StrongARM chips on the board (one for tx, one for rx)
11747 * are running in big-endian mode.
11748 */
11749 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11750 GRC_MODE_WSWAP_NONFRM_DATA);
11751#ifdef __BIG_ENDIAN
11752 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11753#endif
11754 spin_lock_init(&tp->lock);
1da177e4 11755 spin_lock_init(&tp->indirect_lock);
c4028958 11756 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4
LT		 11757
11758 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11759 if (tp->regs == 0UL) {
11760 printk(KERN_ERR PFX "Cannot map device registers, "
11761 "aborting.\n");
11762 err = -ENOMEM;
11763 goto err_out_free_dev;
11764 }
11765
11766 tg3_init_link_config(tp);
11767
1da177e4
LT		 11768 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11769 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11770 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11771
11772 dev->open = tg3_open;
11773 dev->stop = tg3_close;
11774 dev->get_stats = tg3_get_stats;
11775 dev->set_multicast_list = tg3_set_rx_mode;
11776 dev->set_mac_address = tg3_set_mac_addr;
11777 dev->do_ioctl = tg3_ioctl;
11778 dev->tx_timeout = tg3_tx_timeout;
11779 dev->poll = tg3_poll;
11780 dev->ethtool_ops = &tg3_ethtool_ops;
11781 dev->weight = 64;
11782 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11783 dev->change_mtu = tg3_change_mtu;
11784 dev->irq = pdev->irq;
11785#ifdef CONFIG_NET_POLL_CONTROLLER
11786 dev->poll_controller = tg3_poll_controller;
11787#endif
11788
11789 err = tg3_get_invariants(tp);
11790 if (err) {
11791 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11792 "aborting.\n");
11793 goto err_out_iounmap;
11794 }
11795
4a29cc2e
MC		 11796 /* The EPB bridge inside 5714, 5715, and 5780 and any
11797 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 11798 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11799 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11800 * do DMA address check in tg3_start_xmit().
11801 */
4a29cc2e
MC		 11802 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11803 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11804 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 11805 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11806#ifdef CONFIG_HIGHMEM
11807 dma_mask = DMA_64BIT_MASK;
11808#endif
4a29cc2e 11809 } else
72f2afb8
MC		 11810 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11811
11812 /* Configure DMA attributes. */
11813 if (dma_mask > DMA_32BIT_MASK) {
11814 err = pci_set_dma_mask(pdev, dma_mask);
11815 if (!err) {
11816 dev->features |= NETIF_F_HIGHDMA;
11817 err = pci_set_consistent_dma_mask(pdev,
11818 persist_dma_mask);
11819 if (err < 0) {
11820 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11821 "DMA for consistent allocations\n");
11822 goto err_out_iounmap;
11823 }
11824 }
11825 }
11826 if (err || dma_mask == DMA_32BIT_MASK) {
11827 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11828 if (err) {
11829 printk(KERN_ERR PFX "No usable DMA configuration, "
11830 "aborting.\n");
11831 goto err_out_iounmap;
11832 }
11833 }
11834
fdfec172 11835 tg3_init_bufmgr_config(tp);
1da177e4 11836
1da177e4
LT		 11837 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11838 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11839 }
11840 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11841 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11842 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 11843 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 11844 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11845 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11846 } else {
11847 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11848 }
11849
4e3a7aaa
MC		 11850 /* TSO is on by default on chips that support hardware TSO.
11851 * Firmware TSO on older chips gives lower performance, so it
11852 * is off by default, but can be enabled using ethtool.
11853 */
b0026624 11854 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 11855 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 11856 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11857 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624
MC		 11858 dev->features |= NETIF_F_TSO6;
11859 }
1da177e4 11860
1da177e4
LT		 11861
11862 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11863 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11864 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11865 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11866 tp->rx_pending = 63;
11867 }
11868
8c2dc7e1
MC		 11869 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11870 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11871 tp->pdev_peer = tg3_find_peer(tp);
1da177e4
LT		 11872
11873 err = tg3_get_device_address(tp);
11874 if (err) {
11875 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11876 "aborting.\n");
11877 goto err_out_iounmap;
11878 }
11879
11880 /*
11881 * Reset chip in case UNDI or EFI driver did not shutdown
11882 * DMA self test will enable WDMAC and we'll see (spurious)
11883 * pending DMA on the PCI bus at that point.
11884 */
11885 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11886 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11887 pci_save_state(tp->pdev);
11888 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 11889 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 11890 }
11891
11892 err = tg3_test_dma(tp);
11893 if (err) {
11894 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11895 goto err_out_iounmap;
11896 }
11897
11898 /* Tigon3 can do ipv4 only... and some chips have buggy
11899 * checksumming.
11900 */
11901 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
af36e6b6
MC		 11902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf
MC		 11904 dev->features |= NETIF_F_HW_CSUM;
11905 else
11906 dev->features |= NETIF_F_IP_CSUM;
11907 dev->features |= NETIF_F_SG;
1da177e4
LT		 11908 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11909 } else
11910 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11911
1da177e4
LT		 11912 /* flow control autonegotiation is default behavior */
11913 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11914
15f9850d
DM		 11915 tg3_init_coal(tp);
11916
7d3f4c97
DM		 11917 /* Now that we have fully setup the chip, save away a snapshot
11918 * of the PCI config space. We need to restore this after
11919 * GRC_MISC_CFG core clock resets and some resume events.
11920 */
11921 pci_save_state(tp->pdev);
11922
c49a1561
MC		 11923 pci_set_drvdata(pdev, dev);
11924
1da177e4
LT		 11925 err = register_netdev(dev);
11926 if (err) {
11927 printk(KERN_ERR PFX "Cannot register net device, "
11928 "aborting.\n");
11929 goto err_out_iounmap;
11930 }
11931
cbb45d21 11932 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
1da177e4
LT		 11933 dev->name,
11934 tp->board_part_number,
11935 tp->pci_chip_rev_id,
11936 tg3_phy_string(tp),
f9804ddb 11937 tg3_bus_string(tp, str),
cbb45d21
MC		 11938 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11939 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11940 "10/100/1000Base-T")));
1da177e4
LT		 11941
11942 for (i = 0; i < 6; i++)
11943 printk("%2.2x%c", dev->dev_addr[i],
11944 i == 5 ? '\n' : ':');
11945
11946 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11947 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11948 "TSOcap[%d] \n",
11949 dev->name,
11950 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11951 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11952 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11953 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11954 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11955 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11956 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 11957 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11958 dev->name, tp->dma_rwctrl,
11959 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11960 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 11961
11962 return 0;
11963
11964err_out_iounmap:
6892914f
MC		 11965 if (tp->regs) {
11966 iounmap(tp->regs);
22abe310 11967 tp->regs = NULL;
6892914f 11968 }
1da177e4
LT		 11969
11970err_out_free_dev:
11971 free_netdev(dev);
11972
11973err_out_free_res:
11974 pci_release_regions(pdev);
11975
11976err_out_disable_pdev:
11977 pci_disable_device(pdev);
11978 pci_set_drvdata(pdev, NULL);
11979 return err;
11980}
11981
11982static void __devexit tg3_remove_one(struct pci_dev *pdev)
11983{
11984 struct net_device *dev = pci_get_drvdata(pdev);
11985
11986 if (dev) {
11987 struct tg3 *tp = netdev_priv(dev);
11988
7faa006f 11989 flush_scheduled_work();
1da177e4 11990 unregister_netdev(dev);
6892914f
MC		 11991 if (tp->regs) {
11992 iounmap(tp->regs);
22abe310 11993 tp->regs = NULL;
6892914f 11994 }
1da177e4
LT		 11995 free_netdev(dev);
11996 pci_release_regions(pdev);
11997 pci_disable_device(pdev);
11998 pci_set_drvdata(pdev, NULL);
11999 }
12000}
12001
12002static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12003{
12004 struct net_device *dev = pci_get_drvdata(pdev);
12005 struct tg3 *tp = netdev_priv(dev);
12006 int err;
12007
12008 if (!netif_running(dev))
12009 return 0;
12010
7faa006f 12011 flush_scheduled_work();
1da177e4
LT		 12012 tg3_netif_stop(tp);
12013
12014 del_timer_sync(&tp->timer);
12015
f47c11ee 12016 tg3_full_lock(tp, 1);
1da177e4 12017 tg3_disable_ints(tp);
f47c11ee 12018 tg3_full_unlock(tp);
1da177e4
LT		 12019
12020 netif_device_detach(dev);
12021
f47c11ee 12022 tg3_full_lock(tp, 0);
944d980e 12023 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 12024 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 12025 tg3_full_unlock(tp);
1da177e4 12026
436f1379
MC		 12027 /* Save MSI address and data for resume. */
12028 pci_save_state(pdev);
12029
1da177e4
LT		 12030 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12031 if (err) {
f47c11ee 12032 tg3_full_lock(tp, 0);
1da177e4 12033
6a9eba15 12034 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12035 if (tg3_restart_hw(tp, 1))
12036 goto out;
1da177e4
LT		 12037
12038 tp->timer.expires = jiffies + tp->timer_offset;
12039 add_timer(&tp->timer);
12040
12041 netif_device_attach(dev);
12042 tg3_netif_start(tp);
12043
b9ec6c1b 12044out:
f47c11ee 12045 tg3_full_unlock(tp);
1da177e4
LT		 12046 }
12047
12048 return err;
12049}
12050
12051static int tg3_resume(struct pci_dev *pdev)
12052{
12053 struct net_device *dev = pci_get_drvdata(pdev);
12054 struct tg3 *tp = netdev_priv(dev);
12055 int err;
12056
12057 if (!netif_running(dev))
12058 return 0;
12059
12060 pci_restore_state(tp->pdev);
12061
bc1c7567 12062 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12063 if (err)
12064 return err;
12065
12066 netif_device_attach(dev);
12067
f47c11ee 12068 tg3_full_lock(tp, 0);
1da177e4 12069
6a9eba15 12070 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12071 err = tg3_restart_hw(tp, 1);
12072 if (err)
12073 goto out;
1da177e4
LT		 12074
12075 tp->timer.expires = jiffies + tp->timer_offset;
12076 add_timer(&tp->timer);
12077
1da177e4
LT		 12078 tg3_netif_start(tp);
12079
b9ec6c1b 12080out:
f47c11ee 12081 tg3_full_unlock(tp);
1da177e4 12082
b9ec6c1b 12083 return err;
1da177e4
LT		 12084}
12085
12086static struct pci_driver tg3_driver = {
12087 .name = DRV_MODULE_NAME,
12088 .id_table = tg3_pci_tbl,
12089 .probe = tg3_init_one,
12090 .remove = __devexit_p(tg3_remove_one),
12091 .suspend = tg3_suspend,
12092 .resume = tg3_resume
12093};
12094
12095static int __init tg3_init(void)
12096{
29917620 12097 return pci_register_driver(&tg3_driver);
1da177e4
LT		 12098}
12099
12100static void __exit tg3_cleanup(void)
12101{
12102 pci_unregister_driver(&tg3_driver);
12103}
12104
12105module_init(tg3_init);
12106module_exit(tg3_cleanup);
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