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[PKT_SCHED]: Eliminate unnecessary includes in simple.c
[net-next-2.6.git] / drivers / net / tg3.c
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1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Copyright (C) 2000-2003 Broadcom Corporation.
11 */
12
13#include <linux/config.h>
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/compiler.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/pci.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/ethtool.h>
29#include <linux/mii.h>
30#include <linux/if_vlan.h>
31#include <linux/ip.h>
32#include <linux/tcp.h>
33#include <linux/workqueue.h>
34
35#include <net/checksum.h>
36
37#include <asm/system.h>
38#include <asm/io.h>
39#include <asm/byteorder.h>
40#include <asm/uaccess.h>
41
42#ifdef CONFIG_SPARC64
43#include <asm/idprom.h>
44#include <asm/oplib.h>
45#include <asm/pbm.h>
46#endif
47
48#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49#define TG3_VLAN_TAG_USED 1
50#else
51#define TG3_VLAN_TAG_USED 0
52#endif
53
54#ifdef NETIF_F_TSO
55#define TG3_TSO_SUPPORT 1
56#else
57#define TG3_TSO_SUPPORT 0
58#endif
59
60#include "tg3.h"
61
62#define DRV_MODULE_NAME "tg3"
63#define PFX DRV_MODULE_NAME ": "
ac6910e1
DM		 64#define DRV_MODULE_VERSION "3.26"
65#define DRV_MODULE_RELDATE "April 24, 2005"
1da177e4
LT		 66
67#define TG3_DEF_MAC_MODE 0
68#define TG3_DEF_RX_MODE 0
69#define TG3_DEF_TX_MODE 0
70#define TG3_DEF_MSG_ENABLE \
71 (NETIF_MSG_DRV | \
72 NETIF_MSG_PROBE | \
73 NETIF_MSG_LINK | \
74 NETIF_MSG_TIMER | \
75 NETIF_MSG_IFDOWN | \
76 NETIF_MSG_IFUP | \
77 NETIF_MSG_RX_ERR | \
78 NETIF_MSG_TX_ERR)
79
80/* length of time before we decide the hardware is borked,
81 * and dev->tx_timeout() should be called to fix the problem
82 */
83#define TG3_TX_TIMEOUT (5 * HZ)
84
85/* hardware minimum and maximum for a single frame's data payload */
86#define TG3_MIN_MTU 60
87#define TG3_MAX_MTU(tp) \
fcf02693 88 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
1da177e4
LT		 89
90/* These numbers seem to be hard coded in the NIC firmware somehow.
91 * You can't change the ring sizes, but you can change where you place
92 * them in the NIC onboard memory.
93 */
94#define TG3_RX_RING_SIZE 512
95#define TG3_DEF_RX_RING_PENDING 200
96#define TG3_RX_JUMBO_RING_SIZE 256
97#define TG3_DEF_RX_JUMBO_RING_PENDING 100
98
99/* Do not place this n-ring entries value into the tp struct itself,
100 * we really want to expose these constants to GCC so that modulo et
101 * al. operations are done with shifts and masks instead of with
102 * hw multiply/modulo instructions. Another solution would be to
103 * replace things like '% foo' with '& (foo - 1)'.
104 */
105#define TG3_RX_RCB_RING_SIZE(tp) \
106 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
107
108#define TG3_TX_RING_SIZE 512
109#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
110
111#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
112 TG3_RX_RING_SIZE)
113#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
114 TG3_RX_JUMBO_RING_SIZE)
115#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
116 TG3_RX_RCB_RING_SIZE(tp))
117#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
118 TG3_TX_RING_SIZE)
119#define TX_RING_GAP(TP) \
120 (TG3_TX_RING_SIZE - (TP)->tx_pending)
121#define TX_BUFFS_AVAIL(TP) \
122 (((TP)->tx_cons <= (TP)->tx_prod) ? \
123 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
124 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
125#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
126
127#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
128#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
129
130/* minimum number of free TX descriptors required to wake up TX process */
131#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
132
133/* number of ETHTOOL_GSTATS u64's */
134#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
135
136static char version[] __devinitdata =
137 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138
139MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
140MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_MODULE_VERSION);
143
144static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
145module_param(tg3_debug, int, 0);
146MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147
148static struct pci_device_id tg3_pci_tbl[] = {
149 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
151 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
153 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
155 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
6e9017a7 207 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
af2bcd97 208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 209 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
213 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
215 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
217 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
219 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
221 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
227 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
229 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
231 { 0, }
232};
233
234MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
235
236static struct {
237 const char string[ETH_GSTRING_LEN];
238} ethtool_stats_keys[TG3_NUM_STATS] = {
239 { "rx_octets" },
240 { "rx_fragments" },
241 { "rx_ucast_packets" },
242 { "rx_mcast_packets" },
243 { "rx_bcast_packets" },
244 { "rx_fcs_errors" },
245 { "rx_align_errors" },
246 { "rx_xon_pause_rcvd" },
247 { "rx_xoff_pause_rcvd" },
248 { "rx_mac_ctrl_rcvd" },
249 { "rx_xoff_entered" },
250 { "rx_frame_too_long_errors" },
251 { "rx_jabbers" },
252 { "rx_undersize_packets" },
253 { "rx_in_length_errors" },
254 { "rx_out_length_errors" },
255 { "rx_64_or_less_octet_packets" },
256 { "rx_65_to_127_octet_packets" },
257 { "rx_128_to_255_octet_packets" },
258 { "rx_256_to_511_octet_packets" },
259 { "rx_512_to_1023_octet_packets" },
260 { "rx_1024_to_1522_octet_packets" },
261 { "rx_1523_to_2047_octet_packets" },
262 { "rx_2048_to_4095_octet_packets" },
263 { "rx_4096_to_8191_octet_packets" },
264 { "rx_8192_to_9022_octet_packets" },
265
266 { "tx_octets" },
267 { "tx_collisions" },
268
269 { "tx_xon_sent" },
270 { "tx_xoff_sent" },
271 { "tx_flow_control" },
272 { "tx_mac_errors" },
273 { "tx_single_collisions" },
274 { "tx_mult_collisions" },
275 { "tx_deferred" },
276 { "tx_excessive_collisions" },
277 { "tx_late_collisions" },
278 { "tx_collide_2times" },
279 { "tx_collide_3times" },
280 { "tx_collide_4times" },
281 { "tx_collide_5times" },
282 { "tx_collide_6times" },
283 { "tx_collide_7times" },
284 { "tx_collide_8times" },
285 { "tx_collide_9times" },
286 { "tx_collide_10times" },
287 { "tx_collide_11times" },
288 { "tx_collide_12times" },
289 { "tx_collide_13times" },
290 { "tx_collide_14times" },
291 { "tx_collide_15times" },
292 { "tx_ucast_packets" },
293 { "tx_mcast_packets" },
294 { "tx_bcast_packets" },
295 { "tx_carrier_sense_errors" },
296 { "tx_discards" },
297 { "tx_errors" },
298
299 { "dma_writeq_full" },
300 { "dma_write_prioq_full" },
301 { "rxbds_empty" },
302 { "rx_discards" },
303 { "rx_errors" },
304 { "rx_threshold_hit" },
305
306 { "dma_readq_full" },
307 { "dma_read_prioq_full" },
308 { "tx_comp_queue_full" },
309
310 { "ring_set_send_prod_index" },
311 { "ring_status_update" },
312 { "nic_irqs" },
313 { "nic_avoided_irqs" },
314 { "nic_tx_threshold_hit" }
315};
316
317static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
318{
319 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
320 unsigned long flags;
321
322 spin_lock_irqsave(&tp->indirect_lock, flags);
323 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
324 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
325 spin_unlock_irqrestore(&tp->indirect_lock, flags);
326 } else {
327 writel(val, tp->regs + off);
328 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
329 readl(tp->regs + off);
330 }
331}
332
333static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
334{
335 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
336 unsigned long flags;
337
338 spin_lock_irqsave(&tp->indirect_lock, flags);
339 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
340 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
341 spin_unlock_irqrestore(&tp->indirect_lock, flags);
342 } else {
343 void __iomem *dest = tp->regs + off;
344 writel(val, dest);
345 readl(dest); /* always flush PCI write */
346 }
347}
348
349static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
350{
351 void __iomem *mbox = tp->regs + off;
352 writel(val, mbox);
353 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
354 readl(mbox);
355}
356
357static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
358{
359 void __iomem *mbox = tp->regs + off;
360 writel(val, mbox);
361 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
362 writel(val, mbox);
363 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
364 readl(mbox);
365}
366
367#define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tp->regs + (reg))
368#define tw32_rx_mbox(reg, val) _tw32_rx_mbox(tp, reg, val)
369#define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
370
371#define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
372#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
373#define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
374#define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
375#define tr32(reg) readl(tp->regs + (reg))
376#define tr16(reg) readw(tp->regs + (reg))
377#define tr8(reg) readb(tp->regs + (reg))
378
379static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
380{
381 unsigned long flags;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
385 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
386
387 /* Always leave this as zero. */
388 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
389 spin_unlock_irqrestore(&tp->indirect_lock, flags);
390}
391
392static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
393{
394 unsigned long flags;
395
396 spin_lock_irqsave(&tp->indirect_lock, flags);
397 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
398 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
399
400 /* Always leave this as zero. */
401 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
402 spin_unlock_irqrestore(&tp->indirect_lock, flags);
403}
404
405static void tg3_disable_ints(struct tg3 *tp)
406{
407 tw32(TG3PCI_MISC_HOST_CTRL,
408 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
409 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
410 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
411}
412
413static inline void tg3_cond_int(struct tg3 *tp)
414{
415 if (tp->hw_status->status & SD_STATUS_UPDATED)
416 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
417}
418
419static void tg3_enable_ints(struct tg3 *tp)
420{
421 tw32(TG3PCI_MISC_HOST_CTRL,
422 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
423 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
424 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
425
426 tg3_cond_int(tp);
427}
428
429/* tg3_restart_ints
430 * similar to tg3_enable_ints, but it can return without flushing the
431 * PIO write which reenables interrupts
432 */
433static void tg3_restart_ints(struct tg3 *tp)
434{
435 tw32(TG3PCI_MISC_HOST_CTRL,
436 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
437 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
438 mmiowb();
439
440 tg3_cond_int(tp);
441}
442
443static inline void tg3_netif_stop(struct tg3 *tp)
444{
445 netif_poll_disable(tp->dev);
446 netif_tx_disable(tp->dev);
447}
448
449static inline void tg3_netif_start(struct tg3 *tp)
450{
451 netif_wake_queue(tp->dev);
452 /* NOTE: unconditional netif_wake_queue is only appropriate
453 * so long as all callers are assured to have free tx slots
454 * (such as after tg3_init_hw)
455 */
456 netif_poll_enable(tp->dev);
457 tg3_cond_int(tp);
458}
459
460static void tg3_switch_clocks(struct tg3 *tp)
461{
462 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
463 u32 orig_clock_ctrl;
464
465 orig_clock_ctrl = clock_ctrl;
466 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
467 CLOCK_CTRL_CLKRUN_OENABLE |
468 0x1f);
469 tp->pci_clock_ctrl = clock_ctrl;
470
471 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
472 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
473 tw32_f(TG3PCI_CLOCK_CTRL,
474 clock_ctrl | CLOCK_CTRL_625_CORE);
475 udelay(40);
476 }
477 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
478 tw32_f(TG3PCI_CLOCK_CTRL,
479 clock_ctrl |
480 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
481 udelay(40);
482 tw32_f(TG3PCI_CLOCK_CTRL,
483 clock_ctrl | (CLOCK_CTRL_ALTCLK));
484 udelay(40);
485 }
486 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
487 udelay(40);
488}
489
490#define PHY_BUSY_LOOPS 5000
491
492static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
493{
494 u32 frame_val;
495 unsigned int loops;
496 int ret;
497
498 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
499 tw32_f(MAC_MI_MODE,
500 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
501 udelay(80);
502 }
503
504 *val = 0x0;
505
506 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
507 MI_COM_PHY_ADDR_MASK);
508 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
509 MI_COM_REG_ADDR_MASK);
510 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
511
512 tw32_f(MAC_MI_COM, frame_val);
513
514 loops = PHY_BUSY_LOOPS;
515 while (loops != 0) {
516 udelay(10);
517 frame_val = tr32(MAC_MI_COM);
518
519 if ((frame_val & MI_COM_BUSY) == 0) {
520 udelay(5);
521 frame_val = tr32(MAC_MI_COM);
522 break;
523 }
524 loops -= 1;
525 }
526
527 ret = -EBUSY;
528 if (loops != 0) {
529 *val = frame_val & MI_COM_DATA_MASK;
530 ret = 0;
531 }
532
533 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
534 tw32_f(MAC_MI_MODE, tp->mi_mode);
535 udelay(80);
536 }
537
538 return ret;
539}
540
541static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
542{
543 u32 frame_val;
544 unsigned int loops;
545 int ret;
546
547 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
548 tw32_f(MAC_MI_MODE,
549 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
550 udelay(80);
551 }
552
553 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
554 MI_COM_PHY_ADDR_MASK);
555 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
556 MI_COM_REG_ADDR_MASK);
557 frame_val |= (val & MI_COM_DATA_MASK);
558 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
559
560 tw32_f(MAC_MI_COM, frame_val);
561
562 loops = PHY_BUSY_LOOPS;
563 while (loops != 0) {
564 udelay(10);
565 frame_val = tr32(MAC_MI_COM);
566 if ((frame_val & MI_COM_BUSY) == 0) {
567 udelay(5);
568 frame_val = tr32(MAC_MI_COM);
569 break;
570 }
571 loops -= 1;
572 }
573
574 ret = -EBUSY;
575 if (loops != 0)
576 ret = 0;
577
578 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
579 tw32_f(MAC_MI_MODE, tp->mi_mode);
580 udelay(80);
581 }
582
583 return ret;
584}
585
586static void tg3_phy_set_wirespeed(struct tg3 *tp)
587{
588 u32 val;
589
590 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
591 return;
592
593 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
594 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
595 tg3_writephy(tp, MII_TG3_AUX_CTRL,
596 (val | (1 << 15) | (1 << 4)));
597}
598
599static int tg3_bmcr_reset(struct tg3 *tp)
600{
601 u32 phy_control;
602 int limit, err;
603
604 /* OK, reset it, and poll the BMCR_RESET bit until it
605 * clears or we time out.
606 */
607 phy_control = BMCR_RESET;
608 err = tg3_writephy(tp, MII_BMCR, phy_control);
609 if (err != 0)
610 return -EBUSY;
611
612 limit = 5000;
613 while (limit--) {
614 err = tg3_readphy(tp, MII_BMCR, &phy_control);
615 if (err != 0)
616 return -EBUSY;
617
618 if ((phy_control & BMCR_RESET) == 0) {
619 udelay(40);
620 break;
621 }
622 udelay(10);
623 }
624 if (limit <= 0)
625 return -EBUSY;
626
627 return 0;
628}
629
630static int tg3_wait_macro_done(struct tg3 *tp)
631{
632 int limit = 100;
633
634 while (limit--) {
635 u32 tmp32;
636
637 if (!tg3_readphy(tp, 0x16, &tmp32)) {
638 if ((tmp32 & 0x1000) == 0)
639 break;
640 }
641 }
642 if (limit <= 0)
643 return -EBUSY;
644
645 return 0;
646}
647
648static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
649{
650 static const u32 test_pat[4][6] = {
651 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
652 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
653 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
654 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
655 };
656 int chan;
657
658 for (chan = 0; chan < 4; chan++) {
659 int i;
660
661 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
662 (chan * 0x2000) | 0x0200);
663 tg3_writephy(tp, 0x16, 0x0002);
664
665 for (i = 0; i < 6; i++)
666 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
667 test_pat[chan][i]);
668
669 tg3_writephy(tp, 0x16, 0x0202);
670 if (tg3_wait_macro_done(tp)) {
671 *resetp = 1;
672 return -EBUSY;
673 }
674
675 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
676 (chan * 0x2000) | 0x0200);
677 tg3_writephy(tp, 0x16, 0x0082);
678 if (tg3_wait_macro_done(tp)) {
679 *resetp = 1;
680 return -EBUSY;
681 }
682
683 tg3_writephy(tp, 0x16, 0x0802);
684 if (tg3_wait_macro_done(tp)) {
685 *resetp = 1;
686 return -EBUSY;
687 }
688
689 for (i = 0; i < 6; i += 2) {
690 u32 low, high;
691
692 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
693 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
694 tg3_wait_macro_done(tp)) {
695 *resetp = 1;
696 return -EBUSY;
697 }
698 low &= 0x7fff;
699 high &= 0x000f;
700 if (low != test_pat[chan][i] ||
701 high != test_pat[chan][i+1]) {
702 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
703 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
704 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
705
706 return -EBUSY;
707 }
708 }
709 }
710
711 return 0;
712}
713
714static int tg3_phy_reset_chanpat(struct tg3 *tp)
715{
716 int chan;
717
718 for (chan = 0; chan < 4; chan++) {
719 int i;
720
721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
722 (chan * 0x2000) | 0x0200);
723 tg3_writephy(tp, 0x16, 0x0002);
724 for (i = 0; i < 6; i++)
725 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
726 tg3_writephy(tp, 0x16, 0x0202);
727 if (tg3_wait_macro_done(tp))
728 return -EBUSY;
729 }
730
731 return 0;
732}
733
734static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
735{
736 u32 reg32, phy9_orig;
737 int retries, do_phy_reset, err;
738
739 retries = 10;
740 do_phy_reset = 1;
741 do {
742 if (do_phy_reset) {
743 err = tg3_bmcr_reset(tp);
744 if (err)
745 return err;
746 do_phy_reset = 0;
747 }
748
749 /* Disable transmitter and interrupt. */
750 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
751 continue;
752
753 reg32 |= 0x3000;
754 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
755
756 /* Set full-duplex, 1000 mbps. */
757 tg3_writephy(tp, MII_BMCR,
758 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
759
760 /* Set to master mode. */
761 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
762 continue;
763
764 tg3_writephy(tp, MII_TG3_CTRL,
765 (MII_TG3_CTRL_AS_MASTER |
766 MII_TG3_CTRL_ENABLE_AS_MASTER));
767
768 /* Enable SM_DSP_CLOCK and 6dB. */
769 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
770
771 /* Block the PHY control access. */
772 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
773 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
774
775 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
776 if (!err)
777 break;
778 } while (--retries);
779
780 err = tg3_phy_reset_chanpat(tp);
781 if (err)
782 return err;
783
784 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
785 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
786
787 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
788 tg3_writephy(tp, 0x16, 0x0000);
789
790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
791 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
792 /* Set Extended packet length bit for jumbo frames */
793 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
794 }
795 else {
796 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
797 }
798
799 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
800
801 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
802 reg32 &= ~0x3000;
803 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
804 } else if (!err)
805 err = -EBUSY;
806
807 return err;
808}
809
810/* This will reset the tigon3 PHY if there is no valid
811 * link unless the FORCE argument is non-zero.
812 */
813static int tg3_phy_reset(struct tg3 *tp)
814{
815 u32 phy_status;
816 int err;
817
818 err = tg3_readphy(tp, MII_BMSR, &phy_status);
819 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
820 if (err != 0)
821 return -EBUSY;
822
823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
824 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
825 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
826 err = tg3_phy_reset_5703_4_5(tp);
827 if (err)
828 return err;
829 goto out;
830 }
831
832 err = tg3_bmcr_reset(tp);
833 if (err)
834 return err;
835
836out:
837 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
838 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
839 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
840 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
841 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
843 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
844 }
845 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
846 tg3_writephy(tp, 0x1c, 0x8d68);
847 tg3_writephy(tp, 0x1c, 0x8d68);
848 }
849 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
850 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
852 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
853 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
854 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
857 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
858 }
859 /* Set Extended packet length bit (bit 14) on all chips that */
860 /* support jumbo frames */
861 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
862 /* Cannot do read-modify-write on 5401 */
863 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
fcf02693 864 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1da177e4
LT		 865 u32 phy_reg;
866
867 /* Set bit 14 with read-modify-write to preserve other bits */
868 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
869 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
870 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
871 }
872
873 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
874 * jumbo frames transmission.
875 */
fcf02693 876 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1da177e4
LT		 877 u32 phy_reg;
878
879 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
880 tg3_writephy(tp, MII_TG3_EXT_CTRL,
881 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
882 }
883
884 tg3_phy_set_wirespeed(tp);
885 return 0;
886}
887
888static void tg3_frob_aux_power(struct tg3 *tp)
889{
890 struct tg3 *tp_peer = tp;
891
892 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
893 return;
894
895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
896 tp_peer = pci_get_drvdata(tp->pdev_peer);
897 if (!tp_peer)
898 BUG();
899 }
900
901
902 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
903 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
906 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
907 (GRC_LCLCTRL_GPIO_OE0 |
908 GRC_LCLCTRL_GPIO_OE1 |
909 GRC_LCLCTRL_GPIO_OE2 |
910 GRC_LCLCTRL_GPIO_OUTPUT0 |
911 GRC_LCLCTRL_GPIO_OUTPUT1));
912 udelay(100);
913 } else {
914 u32 no_gpio2;
915 u32 grc_local_ctrl;
916
917 if (tp_peer != tp &&
918 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
919 return;
920
921 /* On 5753 and variants, GPIO2 cannot be used. */
922 no_gpio2 = tp->nic_sram_data_cfg &
923 NIC_SRAM_DATA_CFG_NO_GPIO2;
924
925 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
926 GRC_LCLCTRL_GPIO_OE1 |
927 GRC_LCLCTRL_GPIO_OE2 |
928 GRC_LCLCTRL_GPIO_OUTPUT1 |
929 GRC_LCLCTRL_GPIO_OUTPUT2;
930 if (no_gpio2) {
931 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
932 GRC_LCLCTRL_GPIO_OUTPUT2);
933 }
934 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
935 grc_local_ctrl);
936 udelay(100);
937
938 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
939
940 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
941 grc_local_ctrl);
942 udelay(100);
943
944 if (!no_gpio2) {
945 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
946 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
947 grc_local_ctrl);
948 udelay(100);
949 }
950 }
951 } else {
952 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
953 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
954 if (tp_peer != tp &&
955 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
956 return;
957
958 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
959 (GRC_LCLCTRL_GPIO_OE1 |
960 GRC_LCLCTRL_GPIO_OUTPUT1));
961 udelay(100);
962
963 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
964 (GRC_LCLCTRL_GPIO_OE1));
965 udelay(100);
966
967 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
968 (GRC_LCLCTRL_GPIO_OE1 |
969 GRC_LCLCTRL_GPIO_OUTPUT1));
970 udelay(100);
971 }
972 }
973}
974
975static int tg3_setup_phy(struct tg3 *, int);
976
977#define RESET_KIND_SHUTDOWN 0
978#define RESET_KIND_INIT 1
979#define RESET_KIND_SUSPEND 2
980
981static void tg3_write_sig_post_reset(struct tg3 *, int);
982static int tg3_halt_cpu(struct tg3 *, u32);
983
984static int tg3_set_power_state(struct tg3 *tp, int state)
985{
986 u32 misc_host_ctrl;
987 u16 power_control, power_caps;
988 int pm = tp->pm_cap;
989
990 /* Make sure register accesses (indirect or otherwise)
991 * will function correctly.
992 */
993 pci_write_config_dword(tp->pdev,
994 TG3PCI_MISC_HOST_CTRL,
995 tp->misc_host_ctrl);
996
997 pci_read_config_word(tp->pdev,
998 pm + PCI_PM_CTRL,
999 &power_control);
1000 power_control |= PCI_PM_CTRL_PME_STATUS;
1001 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1002 switch (state) {
1003 case 0:
1004 power_control |= 0;
1005 pci_write_config_word(tp->pdev,
1006 pm + PCI_PM_CTRL,
1007 power_control);
8c6bda1a
MC		 1008 udelay(100); /* Delay after power state change */
1009
1010 /* Switch out of Vaux if it is not a LOM */
1011 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1012 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1013 udelay(100);
1014 }
1da177e4
LT		 1015
1016 return 0;
1017
1018 case 1:
1019 power_control |= 1;
1020 break;
1021
1022 case 2:
1023 power_control |= 2;
1024 break;
1025
1026 case 3:
1027 power_control |= 3;
1028 break;
1029
1030 default:
1031 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1032 "requested.\n",
1033 tp->dev->name, state);
1034 return -EINVAL;
1035 };
1036
1037 power_control |= PCI_PM_CTRL_PME_ENABLE;
1038
1039 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1040 tw32(TG3PCI_MISC_HOST_CTRL,
1041 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1042
1043 if (tp->link_config.phy_is_low_power == 0) {
1044 tp->link_config.phy_is_low_power = 1;
1045 tp->link_config.orig_speed = tp->link_config.speed;
1046 tp->link_config.orig_duplex = tp->link_config.duplex;
1047 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1048 }
1049
1050 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1051 tp->link_config.speed = SPEED_10;
1052 tp->link_config.duplex = DUPLEX_HALF;
1053 tp->link_config.autoneg = AUTONEG_ENABLE;
1054 tg3_setup_phy(tp, 0);
1055 }
1056
1057 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1058
1059 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1060 u32 mac_mode;
1061
1062 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1064 udelay(40);
1065
1066 mac_mode = MAC_MODE_PORT_MODE_MII;
1067
1068 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1069 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1070 mac_mode |= MAC_MODE_LINK_POLARITY;
1071 } else {
1072 mac_mode = MAC_MODE_PORT_MODE_TBI;
1073 }
1074
cbf46853 1075 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1076 tw32(MAC_LED_CTRL, tp->led_ctrl);
1077
1078 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1079 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1080 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1081
1082 tw32_f(MAC_MODE, mac_mode);
1083 udelay(100);
1084
1085 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1086 udelay(10);
1087 }
1088
1089 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1090 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1092 u32 base_val;
1093
1094 base_val = tp->pci_clock_ctrl;
1095 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1096 CLOCK_CTRL_TXCLK_DISABLE);
1097
1098 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1099 CLOCK_CTRL_ALTCLK |
1100 CLOCK_CTRL_PWRDOWN_PLL133);
1101 udelay(40);
85e94ced 1102 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1103 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1104 u32 newbits1, newbits2;
1105
1106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1108 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1109 CLOCK_CTRL_TXCLK_DISABLE |
1110 CLOCK_CTRL_ALTCLK);
1111 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1112 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1113 newbits1 = CLOCK_CTRL_625_CORE;
1114 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1115 } else {
1116 newbits1 = CLOCK_CTRL_ALTCLK;
1117 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1118 }
1119
1120 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1121 udelay(40);
1122
1123 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1124 udelay(40);
1125
1126 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1127 u32 newbits3;
1128
1129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1131 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1132 CLOCK_CTRL_TXCLK_DISABLE |
1133 CLOCK_CTRL_44MHZ_CORE);
1134 } else {
1135 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1136 }
1137
1138 tw32_f(TG3PCI_CLOCK_CTRL,
1139 tp->pci_clock_ctrl | newbits3);
1140 udelay(40);
1141 }
1142 }
1143
1144 tg3_frob_aux_power(tp);
1145
1146 /* Workaround for unstable PLL clock */
1147 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1148 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1149 u32 val = tr32(0x7d00);
1150
1151 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1152 tw32(0x7d00, val);
1153 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1154 tg3_halt_cpu(tp, RX_CPU_BASE);
1155 }
1156
1157 /* Finally, set the new power state. */
1158 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1159 udelay(100); /* Delay after power state change */
1da177e4
LT		 1160
1161 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1162
1163 return 0;
1164}
1165
1166static void tg3_link_report(struct tg3 *tp)
1167{
1168 if (!netif_carrier_ok(tp->dev)) {
1169 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1170 } else {
1171 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1172 tp->dev->name,
1173 (tp->link_config.active_speed == SPEED_1000 ?
1174 1000 :
1175 (tp->link_config.active_speed == SPEED_100 ?
1176 100 : 10)),
1177 (tp->link_config.active_duplex == DUPLEX_FULL ?
1178 "full" : "half"));
1179
1180 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1181 "%s for RX.\n",
1182 tp->dev->name,
1183 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1184 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1185 }
1186}
1187
1188static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1189{
1190 u32 new_tg3_flags = 0;
1191 u32 old_rx_mode = tp->rx_mode;
1192 u32 old_tx_mode = tp->tx_mode;
1193
1194 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1195 if (local_adv & ADVERTISE_PAUSE_CAP) {
1196 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1197 if (remote_adv & LPA_PAUSE_CAP)
1198 new_tg3_flags |=
1199 (TG3_FLAG_RX_PAUSE |
1200 TG3_FLAG_TX_PAUSE);
1201 else if (remote_adv & LPA_PAUSE_ASYM)
1202 new_tg3_flags |=
1203 (TG3_FLAG_RX_PAUSE);
1204 } else {
1205 if (remote_adv & LPA_PAUSE_CAP)
1206 new_tg3_flags |=
1207 (TG3_FLAG_RX_PAUSE |
1208 TG3_FLAG_TX_PAUSE);
1209 }
1210 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1211 if ((remote_adv & LPA_PAUSE_CAP) &&
1212 (remote_adv & LPA_PAUSE_ASYM))
1213 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1214 }
1215
1216 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1217 tp->tg3_flags |= new_tg3_flags;
1218 } else {
1219 new_tg3_flags = tp->tg3_flags;
1220 }
1221
1222 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1223 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1224 else
1225 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1226
1227 if (old_rx_mode != tp->rx_mode) {
1228 tw32_f(MAC_RX_MODE, tp->rx_mode);
1229 }
1230
1231 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1232 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1233 else
1234 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1235
1236 if (old_tx_mode != tp->tx_mode) {
1237 tw32_f(MAC_TX_MODE, tp->tx_mode);
1238 }
1239}
1240
1241static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1242{
1243 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1244 case MII_TG3_AUX_STAT_10HALF:
1245 *speed = SPEED_10;
1246 *duplex = DUPLEX_HALF;
1247 break;
1248
1249 case MII_TG3_AUX_STAT_10FULL:
1250 *speed = SPEED_10;
1251 *duplex = DUPLEX_FULL;
1252 break;
1253
1254 case MII_TG3_AUX_STAT_100HALF:
1255 *speed = SPEED_100;
1256 *duplex = DUPLEX_HALF;
1257 break;
1258
1259 case MII_TG3_AUX_STAT_100FULL:
1260 *speed = SPEED_100;
1261 *duplex = DUPLEX_FULL;
1262 break;
1263
1264 case MII_TG3_AUX_STAT_1000HALF:
1265 *speed = SPEED_1000;
1266 *duplex = DUPLEX_HALF;
1267 break;
1268
1269 case MII_TG3_AUX_STAT_1000FULL:
1270 *speed = SPEED_1000;
1271 *duplex = DUPLEX_FULL;
1272 break;
1273
1274 default:
1275 *speed = SPEED_INVALID;
1276 *duplex = DUPLEX_INVALID;
1277 break;
1278 };
1279}
1280
1281static void tg3_phy_copper_begin(struct tg3 *tp)
1282{
1283 u32 new_adv;
1284 int i;
1285
1286 if (tp->link_config.phy_is_low_power) {
1287 /* Entering low power mode. Disable gigabit and
1288 * 100baseT advertisements.
1289 */
1290 tg3_writephy(tp, MII_TG3_CTRL, 0);
1291
1292 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1293 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1294 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1295 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1296
1297 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1298 } else if (tp->link_config.speed == SPEED_INVALID) {
1299 tp->link_config.advertising =
1300 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1301 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1302 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1303 ADVERTISED_Autoneg | ADVERTISED_MII);
1304
1305 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1306 tp->link_config.advertising &=
1307 ~(ADVERTISED_1000baseT_Half |
1308 ADVERTISED_1000baseT_Full);
1309
1310 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1311 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1312 new_adv |= ADVERTISE_10HALF;
1313 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1314 new_adv |= ADVERTISE_10FULL;
1315 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1316 new_adv |= ADVERTISE_100HALF;
1317 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1318 new_adv |= ADVERTISE_100FULL;
1319 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1320
1321 if (tp->link_config.advertising &
1322 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1323 new_adv = 0;
1324 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1325 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1326 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1327 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1328 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1329 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1330 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1331 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1332 MII_TG3_CTRL_ENABLE_AS_MASTER);
1333 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1334 } else {
1335 tg3_writephy(tp, MII_TG3_CTRL, 0);
1336 }
1337 } else {
1338 /* Asking for a specific link mode. */
1339 if (tp->link_config.speed == SPEED_1000) {
1340 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1341 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1342
1343 if (tp->link_config.duplex == DUPLEX_FULL)
1344 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1345 else
1346 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1347 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1348 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1349 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1350 MII_TG3_CTRL_ENABLE_AS_MASTER);
1351 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1352 } else {
1353 tg3_writephy(tp, MII_TG3_CTRL, 0);
1354
1355 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1356 if (tp->link_config.speed == SPEED_100) {
1357 if (tp->link_config.duplex == DUPLEX_FULL)
1358 new_adv |= ADVERTISE_100FULL;
1359 else
1360 new_adv |= ADVERTISE_100HALF;
1361 } else {
1362 if (tp->link_config.duplex == DUPLEX_FULL)
1363 new_adv |= ADVERTISE_10FULL;
1364 else
1365 new_adv |= ADVERTISE_10HALF;
1366 }
1367 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1368 }
1369 }
1370
1371 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1372 tp->link_config.speed != SPEED_INVALID) {
1373 u32 bmcr, orig_bmcr;
1374
1375 tp->link_config.active_speed = tp->link_config.speed;
1376 tp->link_config.active_duplex = tp->link_config.duplex;
1377
1378 bmcr = 0;
1379 switch (tp->link_config.speed) {
1380 default:
1381 case SPEED_10:
1382 break;
1383
1384 case SPEED_100:
1385 bmcr |= BMCR_SPEED100;
1386 break;
1387
1388 case SPEED_1000:
1389 bmcr |= TG3_BMCR_SPEED1000;
1390 break;
1391 };
1392
1393 if (tp->link_config.duplex == DUPLEX_FULL)
1394 bmcr |= BMCR_FULLDPLX;
1395
1396 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1397 (bmcr != orig_bmcr)) {
1398 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1399 for (i = 0; i < 1500; i++) {
1400 u32 tmp;
1401
1402 udelay(10);
1403 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1404 tg3_readphy(tp, MII_BMSR, &tmp))
1405 continue;
1406 if (!(tmp & BMSR_LSTATUS)) {
1407 udelay(40);
1408 break;
1409 }
1410 }
1411 tg3_writephy(tp, MII_BMCR, bmcr);
1412 udelay(40);
1413 }
1414 } else {
1415 tg3_writephy(tp, MII_BMCR,
1416 BMCR_ANENABLE | BMCR_ANRESTART);
1417 }
1418}
1419
1420static int tg3_init_5401phy_dsp(struct tg3 *tp)
1421{
1422 int err;
1423
1424 /* Turn off tap power management. */
1425 /* Set Extended packet length bit */
1426 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1427
1428 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1429 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1430
1431 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1432 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1433
1434 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1435 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1436
1437 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1438 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1439
1440 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1441 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1442
1443 udelay(40);
1444
1445 return err;
1446}
1447
1448static int tg3_copper_is_advertising_all(struct tg3 *tp)
1449{
1450 u32 adv_reg, all_mask;
1451
1452 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1453 return 0;
1454
1455 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1456 ADVERTISE_100HALF | ADVERTISE_100FULL);
1457 if ((adv_reg & all_mask) != all_mask)
1458 return 0;
1459 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1460 u32 tg3_ctrl;
1461
1462 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1463 return 0;
1464
1465 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1466 MII_TG3_CTRL_ADV_1000_FULL);
1467 if ((tg3_ctrl & all_mask) != all_mask)
1468 return 0;
1469 }
1470 return 1;
1471}
1472
1473static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1474{
1475 int current_link_up;
1476 u32 bmsr, dummy;
1477 u16 current_speed;
1478 u8 current_duplex;
1479 int i, err;
1480
1481 tw32(MAC_EVENT, 0);
1482
1483 tw32_f(MAC_STATUS,
1484 (MAC_STATUS_SYNC_CHANGED |
1485 MAC_STATUS_CFG_CHANGED |
1486 MAC_STATUS_MI_COMPLETION |
1487 MAC_STATUS_LNKSTATE_CHANGED));
1488 udelay(40);
1489
1490 tp->mi_mode = MAC_MI_MODE_BASE;
1491 tw32_f(MAC_MI_MODE, tp->mi_mode);
1492 udelay(80);
1493
1494 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1495
1496 /* Some third-party PHYs need to be reset on link going
1497 * down.
1498 */
1499 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1502 netif_carrier_ok(tp->dev)) {
1503 tg3_readphy(tp, MII_BMSR, &bmsr);
1504 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1505 !(bmsr & BMSR_LSTATUS))
1506 force_reset = 1;
1507 }
1508 if (force_reset)
1509 tg3_phy_reset(tp);
1510
1511 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1512 tg3_readphy(tp, MII_BMSR, &bmsr);
1513 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1514 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1515 bmsr = 0;
1516
1517 if (!(bmsr & BMSR_LSTATUS)) {
1518 err = tg3_init_5401phy_dsp(tp);
1519 if (err)
1520 return err;
1521
1522 tg3_readphy(tp, MII_BMSR, &bmsr);
1523 for (i = 0; i < 1000; i++) {
1524 udelay(10);
1525 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1526 (bmsr & BMSR_LSTATUS)) {
1527 udelay(40);
1528 break;
1529 }
1530 }
1531
1532 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1533 !(bmsr & BMSR_LSTATUS) &&
1534 tp->link_config.active_speed == SPEED_1000) {
1535 err = tg3_phy_reset(tp);
1536 if (!err)
1537 err = tg3_init_5401phy_dsp(tp);
1538 if (err)
1539 return err;
1540 }
1541 }
1542 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1543 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1544 /* 5701 {A0,B0} CRC bug workaround */
1545 tg3_writephy(tp, 0x15, 0x0a75);
1546 tg3_writephy(tp, 0x1c, 0x8c68);
1547 tg3_writephy(tp, 0x1c, 0x8d68);
1548 tg3_writephy(tp, 0x1c, 0x8c68);
1549 }
1550
1551 /* Clear pending interrupts... */
1552 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1553 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1554
1555 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1556 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1557 else
1558 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1559
1560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1561 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1562 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1563 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1564 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1565 else
1566 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1567 }
1568
1569 current_link_up = 0;
1570 current_speed = SPEED_INVALID;
1571 current_duplex = DUPLEX_INVALID;
1572
1573 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1574 u32 val;
1575
1576 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1577 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1578 if (!(val & (1 << 10))) {
1579 val |= (1 << 10);
1580 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1581 goto relink;
1582 }
1583 }
1584
1585 bmsr = 0;
1586 for (i = 0; i < 100; i++) {
1587 tg3_readphy(tp, MII_BMSR, &bmsr);
1588 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1589 (bmsr & BMSR_LSTATUS))
1590 break;
1591 udelay(40);
1592 }
1593
1594 if (bmsr & BMSR_LSTATUS) {
1595 u32 aux_stat, bmcr;
1596
1597 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1598 for (i = 0; i < 2000; i++) {
1599 udelay(10);
1600 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1601 aux_stat)
1602 break;
1603 }
1604
1605 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1606 &current_speed,
1607 &current_duplex);
1608
1609 bmcr = 0;
1610 for (i = 0; i < 200; i++) {
1611 tg3_readphy(tp, MII_BMCR, &bmcr);
1612 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1613 continue;
1614 if (bmcr && bmcr != 0x7fff)
1615 break;
1616 udelay(10);
1617 }
1618
1619 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1620 if (bmcr & BMCR_ANENABLE) {
1621 current_link_up = 1;
1622
1623 /* Force autoneg restart if we are exiting
1624 * low power mode.
1625 */
1626 if (!tg3_copper_is_advertising_all(tp))
1627 current_link_up = 0;
1628 } else {
1629 current_link_up = 0;
1630 }
1631 } else {
1632 if (!(bmcr & BMCR_ANENABLE) &&
1633 tp->link_config.speed == current_speed &&
1634 tp->link_config.duplex == current_duplex) {
1635 current_link_up = 1;
1636 } else {
1637 current_link_up = 0;
1638 }
1639 }
1640
1641 tp->link_config.active_speed = current_speed;
1642 tp->link_config.active_duplex = current_duplex;
1643 }
1644
1645 if (current_link_up == 1 &&
1646 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1647 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1648 u32 local_adv, remote_adv;
1649
1650 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1651 local_adv = 0;
1652 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1653
1654 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1655 remote_adv = 0;
1656
1657 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1658
1659 /* If we are not advertising full pause capability,
1660 * something is wrong. Bring the link down and reconfigure.
1661 */
1662 if (local_adv != ADVERTISE_PAUSE_CAP) {
1663 current_link_up = 0;
1664 } else {
1665 tg3_setup_flow_control(tp, local_adv, remote_adv);
1666 }
1667 }
1668relink:
1669 if (current_link_up == 0) {
1670 u32 tmp;
1671
1672 tg3_phy_copper_begin(tp);
1673
1674 tg3_readphy(tp, MII_BMSR, &tmp);
1675 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1676 (tmp & BMSR_LSTATUS))
1677 current_link_up = 1;
1678 }
1679
1680 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1681 if (current_link_up == 1) {
1682 if (tp->link_config.active_speed == SPEED_100 ||
1683 tp->link_config.active_speed == SPEED_10)
1684 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1685 else
1686 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1687 } else
1688 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1689
1690 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1691 if (tp->link_config.active_duplex == DUPLEX_HALF)
1692 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1693
1694 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1696 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1697 (current_link_up == 1 &&
1698 tp->link_config.active_speed == SPEED_10))
1699 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1700 } else {
1701 if (current_link_up == 1)
1702 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1703 }
1704
1705 /* ??? Without this setting Netgear GA302T PHY does not
1706 * ??? send/receive packets...
1707 */
1708 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1709 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1710 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1711 tw32_f(MAC_MI_MODE, tp->mi_mode);
1712 udelay(80);
1713 }
1714
1715 tw32_f(MAC_MODE, tp->mac_mode);
1716 udelay(40);
1717
1718 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1719 /* Polled via timer. */
1720 tw32_f(MAC_EVENT, 0);
1721 } else {
1722 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1723 }
1724 udelay(40);
1725
1726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1727 current_link_up == 1 &&
1728 tp->link_config.active_speed == SPEED_1000 &&
1729 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1730 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1731 udelay(120);
1732 tw32_f(MAC_STATUS,
1733 (MAC_STATUS_SYNC_CHANGED |
1734 MAC_STATUS_CFG_CHANGED));
1735 udelay(40);
1736 tg3_write_mem(tp,
1737 NIC_SRAM_FIRMWARE_MBOX,
1738 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1739 }
1740
1741 if (current_link_up != netif_carrier_ok(tp->dev)) {
1742 if (current_link_up)
1743 netif_carrier_on(tp->dev);
1744 else
1745 netif_carrier_off(tp->dev);
1746 tg3_link_report(tp);
1747 }
1748
1749 return 0;
1750}
1751
1752struct tg3_fiber_aneginfo {
1753 int state;
1754#define ANEG_STATE_UNKNOWN 0
1755#define ANEG_STATE_AN_ENABLE 1
1756#define ANEG_STATE_RESTART_INIT 2
1757#define ANEG_STATE_RESTART 3
1758#define ANEG_STATE_DISABLE_LINK_OK 4
1759#define ANEG_STATE_ABILITY_DETECT_INIT 5
1760#define ANEG_STATE_ABILITY_DETECT 6
1761#define ANEG_STATE_ACK_DETECT_INIT 7
1762#define ANEG_STATE_ACK_DETECT 8
1763#define ANEG_STATE_COMPLETE_ACK_INIT 9
1764#define ANEG_STATE_COMPLETE_ACK 10
1765#define ANEG_STATE_IDLE_DETECT_INIT 11
1766#define ANEG_STATE_IDLE_DETECT 12
1767#define ANEG_STATE_LINK_OK 13
1768#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1769#define ANEG_STATE_NEXT_PAGE_WAIT 15
1770
1771 u32 flags;
1772#define MR_AN_ENABLE 0x00000001
1773#define MR_RESTART_AN 0x00000002
1774#define MR_AN_COMPLETE 0x00000004
1775#define MR_PAGE_RX 0x00000008
1776#define MR_NP_LOADED 0x00000010
1777#define MR_TOGGLE_TX 0x00000020
1778#define MR_LP_ADV_FULL_DUPLEX 0x00000040
1779#define MR_LP_ADV_HALF_DUPLEX 0x00000080
1780#define MR_LP_ADV_SYM_PAUSE 0x00000100
1781#define MR_LP_ADV_ASYM_PAUSE 0x00000200
1782#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1783#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1784#define MR_LP_ADV_NEXT_PAGE 0x00001000
1785#define MR_TOGGLE_RX 0x00002000
1786#define MR_NP_RX 0x00004000
1787
1788#define MR_LINK_OK 0x80000000
1789
1790 unsigned long link_time, cur_time;
1791
1792 u32 ability_match_cfg;
1793 int ability_match_count;
1794
1795 char ability_match, idle_match, ack_match;
1796
1797 u32 txconfig, rxconfig;
1798#define ANEG_CFG_NP 0x00000080
1799#define ANEG_CFG_ACK 0x00000040
1800#define ANEG_CFG_RF2 0x00000020
1801#define ANEG_CFG_RF1 0x00000010
1802#define ANEG_CFG_PS2 0x00000001
1803#define ANEG_CFG_PS1 0x00008000
1804#define ANEG_CFG_HD 0x00004000
1805#define ANEG_CFG_FD 0x00002000
1806#define ANEG_CFG_INVAL 0x00001f06
1807
1808};
1809#define ANEG_OK 0
1810#define ANEG_DONE 1
1811#define ANEG_TIMER_ENAB 2
1812#define ANEG_FAILED -1
1813
1814#define ANEG_STATE_SETTLE_TIME 10000
1815
1816static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1817 struct tg3_fiber_aneginfo *ap)
1818{
1819 unsigned long delta;
1820 u32 rx_cfg_reg;
1821 int ret;
1822
1823 if (ap->state == ANEG_STATE_UNKNOWN) {
1824 ap->rxconfig = 0;
1825 ap->link_time = 0;
1826 ap->cur_time = 0;
1827 ap->ability_match_cfg = 0;
1828 ap->ability_match_count = 0;
1829 ap->ability_match = 0;
1830 ap->idle_match = 0;
1831 ap->ack_match = 0;
1832 }
1833 ap->cur_time++;
1834
1835 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1836 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1837
1838 if (rx_cfg_reg != ap->ability_match_cfg) {
1839 ap->ability_match_cfg = rx_cfg_reg;
1840 ap->ability_match = 0;
1841 ap->ability_match_count = 0;
1842 } else {
1843 if (++ap->ability_match_count > 1) {
1844 ap->ability_match = 1;
1845 ap->ability_match_cfg = rx_cfg_reg;
1846 }
1847 }
1848 if (rx_cfg_reg & ANEG_CFG_ACK)
1849 ap->ack_match = 1;
1850 else
1851 ap->ack_match = 0;
1852
1853 ap->idle_match = 0;
1854 } else {
1855 ap->idle_match = 1;
1856 ap->ability_match_cfg = 0;
1857 ap->ability_match_count = 0;
1858 ap->ability_match = 0;
1859 ap->ack_match = 0;
1860
1861 rx_cfg_reg = 0;
1862 }
1863
1864 ap->rxconfig = rx_cfg_reg;
1865 ret = ANEG_OK;
1866
1867 switch(ap->state) {
1868 case ANEG_STATE_UNKNOWN:
1869 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1870 ap->state = ANEG_STATE_AN_ENABLE;
1871
1872 /* fallthru */
1873 case ANEG_STATE_AN_ENABLE:
1874 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1875 if (ap->flags & MR_AN_ENABLE) {
1876 ap->link_time = 0;
1877 ap->cur_time = 0;
1878 ap->ability_match_cfg = 0;
1879 ap->ability_match_count = 0;
1880 ap->ability_match = 0;
1881 ap->idle_match = 0;
1882 ap->ack_match = 0;
1883
1884 ap->state = ANEG_STATE_RESTART_INIT;
1885 } else {
1886 ap->state = ANEG_STATE_DISABLE_LINK_OK;
1887 }
1888 break;
1889
1890 case ANEG_STATE_RESTART_INIT:
1891 ap->link_time = ap->cur_time;
1892 ap->flags &= ~(MR_NP_LOADED);
1893 ap->txconfig = 0;
1894 tw32(MAC_TX_AUTO_NEG, 0);
1895 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1896 tw32_f(MAC_MODE, tp->mac_mode);
1897 udelay(40);
1898
1899 ret = ANEG_TIMER_ENAB;
1900 ap->state = ANEG_STATE_RESTART;
1901
1902 /* fallthru */
1903 case ANEG_STATE_RESTART:
1904 delta = ap->cur_time - ap->link_time;
1905 if (delta > ANEG_STATE_SETTLE_TIME) {
1906 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1907 } else {
1908 ret = ANEG_TIMER_ENAB;
1909 }
1910 break;
1911
1912 case ANEG_STATE_DISABLE_LINK_OK:
1913 ret = ANEG_DONE;
1914 break;
1915
1916 case ANEG_STATE_ABILITY_DETECT_INIT:
1917 ap->flags &= ~(MR_TOGGLE_TX);
1918 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1919 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1920 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1921 tw32_f(MAC_MODE, tp->mac_mode);
1922 udelay(40);
1923
1924 ap->state = ANEG_STATE_ABILITY_DETECT;
1925 break;
1926
1927 case ANEG_STATE_ABILITY_DETECT:
1928 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1929 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1930 }
1931 break;
1932
1933 case ANEG_STATE_ACK_DETECT_INIT:
1934 ap->txconfig |= ANEG_CFG_ACK;
1935 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1936 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1937 tw32_f(MAC_MODE, tp->mac_mode);
1938 udelay(40);
1939
1940 ap->state = ANEG_STATE_ACK_DETECT;
1941
1942 /* fallthru */
1943 case ANEG_STATE_ACK_DETECT:
1944 if (ap->ack_match != 0) {
1945 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1946 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1947 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1948 } else {
1949 ap->state = ANEG_STATE_AN_ENABLE;
1950 }
1951 } else if (ap->ability_match != 0 &&
1952 ap->rxconfig == 0) {
1953 ap->state = ANEG_STATE_AN_ENABLE;
1954 }
1955 break;
1956
1957 case ANEG_STATE_COMPLETE_ACK_INIT:
1958 if (ap->rxconfig & ANEG_CFG_INVAL) {
1959 ret = ANEG_FAILED;
1960 break;
1961 }
1962 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1963 MR_LP_ADV_HALF_DUPLEX |
1964 MR_LP_ADV_SYM_PAUSE |
1965 MR_LP_ADV_ASYM_PAUSE |
1966 MR_LP_ADV_REMOTE_FAULT1 |
1967 MR_LP_ADV_REMOTE_FAULT2 |
1968 MR_LP_ADV_NEXT_PAGE |
1969 MR_TOGGLE_RX |
1970 MR_NP_RX);
1971 if (ap->rxconfig & ANEG_CFG_FD)
1972 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1973 if (ap->rxconfig & ANEG_CFG_HD)
1974 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1975 if (ap->rxconfig & ANEG_CFG_PS1)
1976 ap->flags |= MR_LP_ADV_SYM_PAUSE;
1977 if (ap->rxconfig & ANEG_CFG_PS2)
1978 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1979 if (ap->rxconfig & ANEG_CFG_RF1)
1980 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1981 if (ap->rxconfig & ANEG_CFG_RF2)
1982 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1983 if (ap->rxconfig & ANEG_CFG_NP)
1984 ap->flags |= MR_LP_ADV_NEXT_PAGE;
1985
1986 ap->link_time = ap->cur_time;
1987
1988 ap->flags ^= (MR_TOGGLE_TX);
1989 if (ap->rxconfig & 0x0008)
1990 ap->flags |= MR_TOGGLE_RX;
1991 if (ap->rxconfig & ANEG_CFG_NP)
1992 ap->flags |= MR_NP_RX;
1993 ap->flags |= MR_PAGE_RX;
1994
1995 ap->state = ANEG_STATE_COMPLETE_ACK;
1996 ret = ANEG_TIMER_ENAB;
1997 break;
1998
1999 case ANEG_STATE_COMPLETE_ACK:
2000 if (ap->ability_match != 0 &&
2001 ap->rxconfig == 0) {
2002 ap->state = ANEG_STATE_AN_ENABLE;
2003 break;
2004 }
2005 delta = ap->cur_time - ap->link_time;
2006 if (delta > ANEG_STATE_SETTLE_TIME) {
2007 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2008 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2009 } else {
2010 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2011 !(ap->flags & MR_NP_RX)) {
2012 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2013 } else {
2014 ret = ANEG_FAILED;
2015 }
2016 }
2017 }
2018 break;
2019
2020 case ANEG_STATE_IDLE_DETECT_INIT:
2021 ap->link_time = ap->cur_time;
2022 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2023 tw32_f(MAC_MODE, tp->mac_mode);
2024 udelay(40);
2025
2026 ap->state = ANEG_STATE_IDLE_DETECT;
2027 ret = ANEG_TIMER_ENAB;
2028 break;
2029
2030 case ANEG_STATE_IDLE_DETECT:
2031 if (ap->ability_match != 0 &&
2032 ap->rxconfig == 0) {
2033 ap->state = ANEG_STATE_AN_ENABLE;
2034 break;
2035 }
2036 delta = ap->cur_time - ap->link_time;
2037 if (delta > ANEG_STATE_SETTLE_TIME) {
2038 /* XXX another gem from the Broadcom driver :( */
2039 ap->state = ANEG_STATE_LINK_OK;
2040 }
2041 break;
2042
2043 case ANEG_STATE_LINK_OK:
2044 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2045 ret = ANEG_DONE;
2046 break;
2047
2048 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2049 /* ??? unimplemented */
2050 break;
2051
2052 case ANEG_STATE_NEXT_PAGE_WAIT:
2053 /* ??? unimplemented */
2054 break;
2055
2056 default:
2057 ret = ANEG_FAILED;
2058 break;
2059 };
2060
2061 return ret;
2062}
2063
2064static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2065{
2066 int res = 0;
2067 struct tg3_fiber_aneginfo aninfo;
2068 int status = ANEG_FAILED;
2069 unsigned int tick;
2070 u32 tmp;
2071
2072 tw32_f(MAC_TX_AUTO_NEG, 0);
2073
2074 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2075 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2076 udelay(40);
2077
2078 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2079 udelay(40);
2080
2081 memset(&aninfo, 0, sizeof(aninfo));
2082 aninfo.flags |= MR_AN_ENABLE;
2083 aninfo.state = ANEG_STATE_UNKNOWN;
2084 aninfo.cur_time = 0;
2085 tick = 0;
2086 while (++tick < 195000) {
2087 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2088 if (status == ANEG_DONE || status == ANEG_FAILED)
2089 break;
2090
2091 udelay(1);
2092 }
2093
2094 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2095 tw32_f(MAC_MODE, tp->mac_mode);
2096 udelay(40);
2097
2098 *flags = aninfo.flags;
2099
2100 if (status == ANEG_DONE &&
2101 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2102 MR_LP_ADV_FULL_DUPLEX)))
2103 res = 1;
2104
2105 return res;
2106}
2107
2108static void tg3_init_bcm8002(struct tg3 *tp)
2109{
2110 u32 mac_status = tr32(MAC_STATUS);
2111 int i;
2112
2113 /* Reset when initting first time or we have a link. */
2114 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2115 !(mac_status & MAC_STATUS_PCS_SYNCED))
2116 return;
2117
2118 /* Set PLL lock range. */
2119 tg3_writephy(tp, 0x16, 0x8007);
2120
2121 /* SW reset */
2122 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2123
2124 /* Wait for reset to complete. */
2125 /* XXX schedule_timeout() ... */
2126 for (i = 0; i < 500; i++)
2127 udelay(10);
2128
2129 /* Config mode; select PMA/Ch 1 regs. */
2130 tg3_writephy(tp, 0x10, 0x8411);
2131
2132 /* Enable auto-lock and comdet, select txclk for tx. */
2133 tg3_writephy(tp, 0x11, 0x0a10);
2134
2135 tg3_writephy(tp, 0x18, 0x00a0);
2136 tg3_writephy(tp, 0x16, 0x41ff);
2137
2138 /* Assert and deassert POR. */
2139 tg3_writephy(tp, 0x13, 0x0400);
2140 udelay(40);
2141 tg3_writephy(tp, 0x13, 0x0000);
2142
2143 tg3_writephy(tp, 0x11, 0x0a50);
2144 udelay(40);
2145 tg3_writephy(tp, 0x11, 0x0a10);
2146
2147 /* Wait for signal to stabilize */
2148 /* XXX schedule_timeout() ... */
2149 for (i = 0; i < 15000; i++)
2150 udelay(10);
2151
2152 /* Deselect the channel register so we can read the PHYID
2153 * later.
2154 */
2155 tg3_writephy(tp, 0x10, 0x8011);
2156}
2157
2158static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2159{
2160 u32 sg_dig_ctrl, sg_dig_status;
2161 u32 serdes_cfg, expected_sg_dig_ctrl;
2162 int workaround, port_a;
2163 int current_link_up;
2164
2165 serdes_cfg = 0;
2166 expected_sg_dig_ctrl = 0;
2167 workaround = 0;
2168 port_a = 1;
2169 current_link_up = 0;
2170
2171 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2172 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2173 workaround = 1;
2174 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2175 port_a = 0;
2176
2177 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2178 /* preserve bits 20-23 for voltage regulator */
2179 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2180 }
2181
2182 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2183
2184 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2185 if (sg_dig_ctrl & (1 << 31)) {
2186 if (workaround) {
2187 u32 val = serdes_cfg;
2188
2189 if (port_a)
2190 val |= 0xc010000;
2191 else
2192 val |= 0x4010000;
2193 tw32_f(MAC_SERDES_CFG, val);
2194 }
2195 tw32_f(SG_DIG_CTRL, 0x01388400);
2196 }
2197 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2198 tg3_setup_flow_control(tp, 0, 0);
2199 current_link_up = 1;
2200 }
2201 goto out;
2202 }
2203
2204 /* Want auto-negotiation. */
2205 expected_sg_dig_ctrl = 0x81388400;
2206
2207 /* Pause capability */
2208 expected_sg_dig_ctrl |= (1 << 11);
2209
2210 /* Asymettric pause */
2211 expected_sg_dig_ctrl |= (1 << 12);
2212
2213 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2214 if (workaround)
2215 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2216 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2217 udelay(5);
2218 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2219
2220 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2221 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2222 MAC_STATUS_SIGNAL_DET)) {
2223 int i;
2224
2225 /* Giver time to negotiate (~200ms) */
2226 for (i = 0; i < 40000; i++) {
2227 sg_dig_status = tr32(SG_DIG_STATUS);
2228 if (sg_dig_status & (0x3))
2229 break;
2230 udelay(5);
2231 }
2232 mac_status = tr32(MAC_STATUS);
2233
2234 if ((sg_dig_status & (1 << 1)) &&
2235 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2236 u32 local_adv, remote_adv;
2237
2238 local_adv = ADVERTISE_PAUSE_CAP;
2239 remote_adv = 0;
2240 if (sg_dig_status & (1 << 19))
2241 remote_adv |= LPA_PAUSE_CAP;
2242 if (sg_dig_status & (1 << 20))
2243 remote_adv |= LPA_PAUSE_ASYM;
2244
2245 tg3_setup_flow_control(tp, local_adv, remote_adv);
2246 current_link_up = 1;
2247 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2248 } else if (!(sg_dig_status & (1 << 1))) {
2249 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2250 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2251 else {
2252 if (workaround) {
2253 u32 val = serdes_cfg;
2254
2255 if (port_a)
2256 val |= 0xc010000;
2257 else
2258 val |= 0x4010000;
2259
2260 tw32_f(MAC_SERDES_CFG, val);
2261 }
2262
2263 tw32_f(SG_DIG_CTRL, 0x01388400);
2264 udelay(40);
2265
2266 /* Link parallel detection - link is up */
2267 /* only if we have PCS_SYNC and not */
2268 /* receiving config code words */
2269 mac_status = tr32(MAC_STATUS);
2270 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2271 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2272 tg3_setup_flow_control(tp, 0, 0);
2273 current_link_up = 1;
2274 }
2275 }
2276 }
2277 }
2278
2279out:
2280 return current_link_up;
2281}
2282
2283static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2284{
2285 int current_link_up = 0;
2286
2287 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2288 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2289 goto out;
2290 }
2291
2292 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2293 u32 flags;
2294 int i;
2295
2296 if (fiber_autoneg(tp, &flags)) {
2297 u32 local_adv, remote_adv;
2298
2299 local_adv = ADVERTISE_PAUSE_CAP;
2300 remote_adv = 0;
2301 if (flags & MR_LP_ADV_SYM_PAUSE)
2302 remote_adv |= LPA_PAUSE_CAP;
2303 if (flags & MR_LP_ADV_ASYM_PAUSE)
2304 remote_adv |= LPA_PAUSE_ASYM;
2305
2306 tg3_setup_flow_control(tp, local_adv, remote_adv);
2307
2308 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2309 current_link_up = 1;
2310 }
2311 for (i = 0; i < 30; i++) {
2312 udelay(20);
2313 tw32_f(MAC_STATUS,
2314 (MAC_STATUS_SYNC_CHANGED |
2315 MAC_STATUS_CFG_CHANGED));
2316 udelay(40);
2317 if ((tr32(MAC_STATUS) &
2318 (MAC_STATUS_SYNC_CHANGED |
2319 MAC_STATUS_CFG_CHANGED)) == 0)
2320 break;
2321 }
2322
2323 mac_status = tr32(MAC_STATUS);
2324 if (current_link_up == 0 &&
2325 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2326 !(mac_status & MAC_STATUS_RCVD_CFG))
2327 current_link_up = 1;
2328 } else {
2329 /* Forcing 1000FD link up. */
2330 current_link_up = 1;
2331 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2332
2333 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2334 udelay(40);
2335 }
2336
2337out:
2338 return current_link_up;
2339}
2340
2341static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2342{
2343 u32 orig_pause_cfg;
2344 u16 orig_active_speed;
2345 u8 orig_active_duplex;
2346 u32 mac_status;
2347 int current_link_up;
2348 int i;
2349
2350 orig_pause_cfg =
2351 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2352 TG3_FLAG_TX_PAUSE));
2353 orig_active_speed = tp->link_config.active_speed;
2354 orig_active_duplex = tp->link_config.active_duplex;
2355
2356 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2357 netif_carrier_ok(tp->dev) &&
2358 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2359 mac_status = tr32(MAC_STATUS);
2360 mac_status &= (MAC_STATUS_PCS_SYNCED |
2361 MAC_STATUS_SIGNAL_DET |
2362 MAC_STATUS_CFG_CHANGED |
2363 MAC_STATUS_RCVD_CFG);
2364 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2365 MAC_STATUS_SIGNAL_DET)) {
2366 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2367 MAC_STATUS_CFG_CHANGED));
2368 return 0;
2369 }
2370 }
2371
2372 tw32_f(MAC_TX_AUTO_NEG, 0);
2373
2374 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2375 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2376 tw32_f(MAC_MODE, tp->mac_mode);
2377 udelay(40);
2378
2379 if (tp->phy_id == PHY_ID_BCM8002)
2380 tg3_init_bcm8002(tp);
2381
2382 /* Enable link change event even when serdes polling. */
2383 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2384 udelay(40);
2385
2386 current_link_up = 0;
2387 mac_status = tr32(MAC_STATUS);
2388
2389 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2390 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2391 else
2392 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2393
2394 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2395 tw32_f(MAC_MODE, tp->mac_mode);
2396 udelay(40);
2397
2398 tp->hw_status->status =
2399 (SD_STATUS_UPDATED |
2400 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2401
2402 for (i = 0; i < 100; i++) {
2403 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2404 MAC_STATUS_CFG_CHANGED));
2405 udelay(5);
2406 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2407 MAC_STATUS_CFG_CHANGED)) == 0)
2408 break;
2409 }
2410
2411 mac_status = tr32(MAC_STATUS);
2412 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2413 current_link_up = 0;
2414 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2415 tw32_f(MAC_MODE, (tp->mac_mode |
2416 MAC_MODE_SEND_CONFIGS));
2417 udelay(1);
2418 tw32_f(MAC_MODE, tp->mac_mode);
2419 }
2420 }
2421
2422 if (current_link_up == 1) {
2423 tp->link_config.active_speed = SPEED_1000;
2424 tp->link_config.active_duplex = DUPLEX_FULL;
2425 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2426 LED_CTRL_LNKLED_OVERRIDE |
2427 LED_CTRL_1000MBPS_ON));
2428 } else {
2429 tp->link_config.active_speed = SPEED_INVALID;
2430 tp->link_config.active_duplex = DUPLEX_INVALID;
2431 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2432 LED_CTRL_LNKLED_OVERRIDE |
2433 LED_CTRL_TRAFFIC_OVERRIDE));
2434 }
2435
2436 if (current_link_up != netif_carrier_ok(tp->dev)) {
2437 if (current_link_up)
2438 netif_carrier_on(tp->dev);
2439 else
2440 netif_carrier_off(tp->dev);
2441 tg3_link_report(tp);
2442 } else {
2443 u32 now_pause_cfg =
2444 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2445 TG3_FLAG_TX_PAUSE);
2446 if (orig_pause_cfg != now_pause_cfg ||
2447 orig_active_speed != tp->link_config.active_speed ||
2448 orig_active_duplex != tp->link_config.active_duplex)
2449 tg3_link_report(tp);
2450 }
2451
2452 return 0;
2453}
2454
2455static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2456{
2457 int err;
2458
2459 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2460 err = tg3_setup_fiber_phy(tp, force_reset);
2461 } else {
2462 err = tg3_setup_copper_phy(tp, force_reset);
2463 }
2464
2465 if (tp->link_config.active_speed == SPEED_1000 &&
2466 tp->link_config.active_duplex == DUPLEX_HALF)
2467 tw32(MAC_TX_LENGTHS,
2468 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2469 (6 << TX_LENGTHS_IPG_SHIFT) |
2470 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2471 else
2472 tw32(MAC_TX_LENGTHS,
2473 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2474 (6 << TX_LENGTHS_IPG_SHIFT) |
2475 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2476
2477 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2478 if (netif_carrier_ok(tp->dev)) {
2479 tw32(HOSTCC_STAT_COAL_TICKS,
2480 DEFAULT_STAT_COAL_TICKS);
2481 } else {
2482 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2483 }
2484 }
2485
2486 return err;
2487}
2488
2489/* Tigon3 never reports partial packet sends. So we do not
2490 * need special logic to handle SKBs that have not had all
2491 * of their frags sent yet, like SunGEM does.
2492 */
2493static void tg3_tx(struct tg3 *tp)
2494{
2495 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2496 u32 sw_idx = tp->tx_cons;
2497
2498 while (sw_idx != hw_idx) {
2499 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2500 struct sk_buff *skb = ri->skb;
2501 int i;
2502
2503 if (unlikely(skb == NULL))
2504 BUG();
2505
2506 pci_unmap_single(tp->pdev,
2507 pci_unmap_addr(ri, mapping),
2508 skb_headlen(skb),
2509 PCI_DMA_TODEVICE);
2510
2511 ri->skb = NULL;
2512
2513 sw_idx = NEXT_TX(sw_idx);
2514
2515 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2516 if (unlikely(sw_idx == hw_idx))
2517 BUG();
2518
2519 ri = &tp->tx_buffers[sw_idx];
2520 if (unlikely(ri->skb != NULL))
2521 BUG();
2522
2523 pci_unmap_page(tp->pdev,
2524 pci_unmap_addr(ri, mapping),
2525 skb_shinfo(skb)->frags[i].size,
2526 PCI_DMA_TODEVICE);
2527
2528 sw_idx = NEXT_TX(sw_idx);
2529 }
2530
2531 dev_kfree_skb_irq(skb);
2532 }
2533
2534 tp->tx_cons = sw_idx;
2535
2536 if (netif_queue_stopped(tp->dev) &&
2537 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2538 netif_wake_queue(tp->dev);
2539}
2540
2541/* Returns size of skb allocated or < 0 on error.
2542 *
2543 * We only need to fill in the address because the other members
2544 * of the RX descriptor are invariant, see tg3_init_rings.
2545 *
2546 * Note the purposeful assymetry of cpu vs. chip accesses. For
2547 * posting buffers we only dirty the first cache line of the RX
2548 * descriptor (containing the address). Whereas for the RX status
2549 * buffers the cpu only reads the last cacheline of the RX descriptor
2550 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2551 */
2552static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2553 int src_idx, u32 dest_idx_unmasked)
2554{
2555 struct tg3_rx_buffer_desc *desc;
2556 struct ring_info *map, *src_map;
2557 struct sk_buff *skb;
2558 dma_addr_t mapping;
2559 int skb_size, dest_idx;
2560
2561 src_map = NULL;
2562 switch (opaque_key) {
2563 case RXD_OPAQUE_RING_STD:
2564 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2565 desc = &tp->rx_std[dest_idx];
2566 map = &tp->rx_std_buffers[dest_idx];
2567 if (src_idx >= 0)
2568 src_map = &tp->rx_std_buffers[src_idx];
2569 skb_size = RX_PKT_BUF_SZ;
2570 break;
2571
2572 case RXD_OPAQUE_RING_JUMBO:
2573 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2574 desc = &tp->rx_jumbo[dest_idx];
2575 map = &tp->rx_jumbo_buffers[dest_idx];
2576 if (src_idx >= 0)
2577 src_map = &tp->rx_jumbo_buffers[src_idx];
2578 skb_size = RX_JUMBO_PKT_BUF_SZ;
2579 break;
2580
2581 default:
2582 return -EINVAL;
2583 };
2584
2585 /* Do not overwrite any of the map or rp information
2586 * until we are sure we can commit to a new buffer.
2587 *
2588 * Callers depend upon this behavior and assume that
2589 * we leave everything unchanged if we fail.
2590 */
2591 skb = dev_alloc_skb(skb_size);
2592 if (skb == NULL)
2593 return -ENOMEM;
2594
2595 skb->dev = tp->dev;
2596 skb_reserve(skb, tp->rx_offset);
2597
2598 mapping = pci_map_single(tp->pdev, skb->data,
2599 skb_size - tp->rx_offset,
2600 PCI_DMA_FROMDEVICE);
2601
2602 map->skb = skb;
2603 pci_unmap_addr_set(map, mapping, mapping);
2604
2605 if (src_map != NULL)
2606 src_map->skb = NULL;
2607
2608 desc->addr_hi = ((u64)mapping >> 32);
2609 desc->addr_lo = ((u64)mapping & 0xffffffff);
2610
2611 return skb_size;
2612}
2613
2614/* We only need to move over in the address because the other
2615 * members of the RX descriptor are invariant. See notes above
2616 * tg3_alloc_rx_skb for full details.
2617 */
2618static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2619 int src_idx, u32 dest_idx_unmasked)
2620{
2621 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2622 struct ring_info *src_map, *dest_map;
2623 int dest_idx;
2624
2625 switch (opaque_key) {
2626 case RXD_OPAQUE_RING_STD:
2627 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2628 dest_desc = &tp->rx_std[dest_idx];
2629 dest_map = &tp->rx_std_buffers[dest_idx];
2630 src_desc = &tp->rx_std[src_idx];
2631 src_map = &tp->rx_std_buffers[src_idx];
2632 break;
2633
2634 case RXD_OPAQUE_RING_JUMBO:
2635 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2636 dest_desc = &tp->rx_jumbo[dest_idx];
2637 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2638 src_desc = &tp->rx_jumbo[src_idx];
2639 src_map = &tp->rx_jumbo_buffers[src_idx];
2640 break;
2641
2642 default:
2643 return;
2644 };
2645
2646 dest_map->skb = src_map->skb;
2647 pci_unmap_addr_set(dest_map, mapping,
2648 pci_unmap_addr(src_map, mapping));
2649 dest_desc->addr_hi = src_desc->addr_hi;
2650 dest_desc->addr_lo = src_desc->addr_lo;
2651
2652 src_map->skb = NULL;
2653}
2654
2655#if TG3_VLAN_TAG_USED
2656static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2657{
2658 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2659}
2660#endif
2661
2662/* The RX ring scheme is composed of multiple rings which post fresh
2663 * buffers to the chip, and one special ring the chip uses to report
2664 * status back to the host.
2665 *
2666 * The special ring reports the status of received packets to the
2667 * host. The chip does not write into the original descriptor the
2668 * RX buffer was obtained from. The chip simply takes the original
2669 * descriptor as provided by the host, updates the status and length
2670 * field, then writes this into the next status ring entry.
2671 *
2672 * Each ring the host uses to post buffers to the chip is described
2673 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
2674 * it is first placed into the on-chip ram. When the packet's length
2675 * is known, it walks down the TG3_BDINFO entries to select the ring.
2676 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2677 * which is within the range of the new packet's length is chosen.
2678 *
2679 * The "separate ring for rx status" scheme may sound queer, but it makes
2680 * sense from a cache coherency perspective. If only the host writes
2681 * to the buffer post rings, and only the chip writes to the rx status
2682 * rings, then cache lines never move beyond shared-modified state.
2683 * If both the host and chip were to write into the same ring, cache line
2684 * eviction could occur since both entities want it in an exclusive state.
2685 */
2686static int tg3_rx(struct tg3 *tp, int budget)
2687{
2688 u32 work_mask;
2689 u32 rx_rcb_ptr = tp->rx_rcb_ptr;
2690 u16 hw_idx, sw_idx;
2691 int received;
2692
2693 hw_idx = tp->hw_status->idx[0].rx_producer;
2694 /*
2695 * We need to order the read of hw_idx and the read of
2696 * the opaque cookie.
2697 */
2698 rmb();
2699 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2700 work_mask = 0;
2701 received = 0;
2702 while (sw_idx != hw_idx && budget > 0) {
2703 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2704 unsigned int len;
2705 struct sk_buff *skb;
2706 dma_addr_t dma_addr;
2707 u32 opaque_key, desc_idx, *post_ptr;
2708
2709 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2710 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2711 if (opaque_key == RXD_OPAQUE_RING_STD) {
2712 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2713 mapping);
2714 skb = tp->rx_std_buffers[desc_idx].skb;
2715 post_ptr = &tp->rx_std_ptr;
2716 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2717 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2718 mapping);
2719 skb = tp->rx_jumbo_buffers[desc_idx].skb;
2720 post_ptr = &tp->rx_jumbo_ptr;
2721 }
2722 else {
2723 goto next_pkt_nopost;
2724 }
2725
2726 work_mask |= opaque_key;
2727
2728 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2729 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2730 drop_it:
2731 tg3_recycle_rx(tp, opaque_key,
2732 desc_idx, *post_ptr);
2733 drop_it_no_recycle:
2734 /* Other statistics kept track of by card. */
2735 tp->net_stats.rx_dropped++;
2736 goto next_pkt;
2737 }
2738
2739 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2740
2741 if (len > RX_COPY_THRESHOLD
2742 && tp->rx_offset == 2
2743 /* rx_offset != 2 iff this is a 5701 card running
2744 * in PCI-X mode [see tg3_get_invariants()] */
2745 ) {
2746 int skb_size;
2747
2748 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2749 desc_idx, *post_ptr);
2750 if (skb_size < 0)
2751 goto drop_it;
2752
2753 pci_unmap_single(tp->pdev, dma_addr,
2754 skb_size - tp->rx_offset,
2755 PCI_DMA_FROMDEVICE);
2756
2757 skb_put(skb, len);
2758 } else {
2759 struct sk_buff *copy_skb;
2760
2761 tg3_recycle_rx(tp, opaque_key,
2762 desc_idx, *post_ptr);
2763
2764 copy_skb = dev_alloc_skb(len + 2);
2765 if (copy_skb == NULL)
2766 goto drop_it_no_recycle;
2767
2768 copy_skb->dev = tp->dev;
2769 skb_reserve(copy_skb, 2);
2770 skb_put(copy_skb, len);
2771 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2772 memcpy(copy_skb->data, skb->data, len);
2773 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2774
2775 /* We'll reuse the original ring buffer. */
2776 skb = copy_skb;
2777 }
2778
2779 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2780 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2781 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2782 >> RXD_TCPCSUM_SHIFT) == 0xffff))
2783 skb->ip_summed = CHECKSUM_UNNECESSARY;
2784 else
2785 skb->ip_summed = CHECKSUM_NONE;
2786
2787 skb->protocol = eth_type_trans(skb, tp->dev);
2788#if TG3_VLAN_TAG_USED
2789 if (tp->vlgrp != NULL &&
2790 desc->type_flags & RXD_FLAG_VLAN) {
2791 tg3_vlan_rx(tp, skb,
2792 desc->err_vlan & RXD_VLAN_MASK);
2793 } else
2794#endif
2795 netif_receive_skb(skb);
2796
2797 tp->dev->last_rx = jiffies;
2798 received++;
2799 budget--;
2800
2801next_pkt:
2802 (*post_ptr)++;
2803next_pkt_nopost:
2804 rx_rcb_ptr++;
2805 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2806 }
2807
2808 /* ACK the status ring. */
2809 tp->rx_rcb_ptr = rx_rcb_ptr;
2810 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW,
2811 (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp)));
2812
2813 /* Refill RX ring(s). */
2814 if (work_mask & RXD_OPAQUE_RING_STD) {
2815 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2816 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2817 sw_idx);
2818 }
2819 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2820 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2821 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2822 sw_idx);
2823 }
2824 mmiowb();
2825
2826 return received;
2827}
2828
2829static int tg3_poll(struct net_device *netdev, int *budget)
2830{
2831 struct tg3 *tp = netdev_priv(netdev);
2832 struct tg3_hw_status *sblk = tp->hw_status;
2833 unsigned long flags;
2834 int done;
2835
2836 spin_lock_irqsave(&tp->lock, flags);
2837
2838 /* handle link change and other phy events */
2839 if (!(tp->tg3_flags &
2840 (TG3_FLAG_USE_LINKCHG_REG |
2841 TG3_FLAG_POLL_SERDES))) {
2842 if (sblk->status & SD_STATUS_LINK_CHG) {
2843 sblk->status = SD_STATUS_UPDATED |
2844 (sblk->status & ~SD_STATUS_LINK_CHG);
2845 tg3_setup_phy(tp, 0);
2846 }
2847 }
2848
2849 /* run TX completion thread */
2850 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2851 spin_lock(&tp->tx_lock);
2852 tg3_tx(tp);
2853 spin_unlock(&tp->tx_lock);
2854 }
2855
2856 spin_unlock_irqrestore(&tp->lock, flags);
2857
2858 /* run RX thread, within the bounds set by NAPI.
2859 * All RX "locking" is done by ensuring outside
2860 * code synchronizes with dev->poll()
2861 */
2862 done = 1;
2863 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2864 int orig_budget = *budget;
2865 int work_done;
2866
2867 if (orig_budget > netdev->quota)
2868 orig_budget = netdev->quota;
2869
2870 work_done = tg3_rx(tp, orig_budget);
2871
2872 *budget -= work_done;
2873 netdev->quota -= work_done;
2874
2875 if (work_done >= orig_budget)
2876 done = 0;
2877 }
2878
2879 /* if no more work, tell net stack and NIC we're done */
2880 if (done) {
2881 spin_lock_irqsave(&tp->lock, flags);
2882 __netif_rx_complete(netdev);
2883 tg3_restart_ints(tp);
2884 spin_unlock_irqrestore(&tp->lock, flags);
2885 }
2886
2887 return (done ? 0 : 1);
2888}
2889
2890static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp)
2891{
2892 struct tg3_hw_status *sblk = tp->hw_status;
2893 unsigned int work_exists = 0;
2894
2895 /* check for phy events */
2896 if (!(tp->tg3_flags &
2897 (TG3_FLAG_USE_LINKCHG_REG |
2898 TG3_FLAG_POLL_SERDES))) {
2899 if (sblk->status & SD_STATUS_LINK_CHG)
2900 work_exists = 1;
2901 }
2902 /* check for RX/TX work to do */
2903 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
2904 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
2905 work_exists = 1;
2906
2907 return work_exists;
2908}
2909
88b06bc2
MC		 2910/* MSI ISR - No need to check for interrupt sharing and no need to
2911 * flush status block and interrupt mailbox. PCI ordering rules
2912 * guarantee that MSI will arrive after the status block.
2913 */
2914static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2915{
2916 struct net_device *dev = dev_id;
2917 struct tg3 *tp = netdev_priv(dev);
2918 struct tg3_hw_status *sblk = tp->hw_status;
2919 unsigned long flags;
2920
2921 spin_lock_irqsave(&tp->lock, flags);
2922
2923 /*
2924 * writing any value to intr-mbox-0 clears PCI INTA# and
2925 * chip-internal interrupt pending events.
2926 * writing non-zero to intr-mbox-0 additional tells the
2927 * NIC to stop sending us irqs, engaging "in-intr-handler"
2928 * event coalescing.
2929 */
2930 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
2931 sblk->status &= ~SD_STATUS_UPDATED;
2932
2933 if (likely(tg3_has_work(dev, tp)))
2934 netif_rx_schedule(dev); /* schedule NAPI poll */
2935 else {
2936 /* no work, re-enable interrupts
2937 */
2938 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2939 0x00000000);
2940 }
2941
2942 spin_unlock_irqrestore(&tp->lock, flags);
2943
2944 return IRQ_RETVAL(1);
2945}
2946
1da177e4
LT		 2947static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2948{
2949 struct net_device *dev = dev_id;
2950 struct tg3 *tp = netdev_priv(dev);
2951 struct tg3_hw_status *sblk = tp->hw_status;
2952 unsigned long flags;
2953 unsigned int handled = 1;
2954
2955 spin_lock_irqsave(&tp->lock, flags);
2956
2957 /* In INTx mode, it is possible for the interrupt to arrive at
2958 * the CPU before the status block posted prior to the interrupt.
2959 * Reading the PCI State register will confirm whether the
2960 * interrupt is ours and will flush the status block.
2961 */
2962 if ((sblk->status & SD_STATUS_UPDATED) ||
2963 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2964 /*
2965 * writing any value to intr-mbox-0 clears PCI INTA# and
2966 * chip-internal interrupt pending events.
2967 * writing non-zero to intr-mbox-0 additional tells the
2968 * NIC to stop sending us irqs, engaging "in-intr-handler"
2969 * event coalescing.
2970 */
2971 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2972 0x00000001);
2973 /*
2974 * Flush PCI write. This also guarantees that our
2975 * status block has been flushed to host memory.
2976 */
2977 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2978 sblk->status &= ~SD_STATUS_UPDATED;
2979
2980 if (likely(tg3_has_work(dev, tp)))
2981 netif_rx_schedule(dev); /* schedule NAPI poll */
2982 else {
2983 /* no work, shared interrupt perhaps? re-enable
2984 * interrupts, and flush that PCI write
2985 */
2986 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2987 0x00000000);
2988 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2989 }
2990 } else { /* shared interrupt */
2991 handled = 0;
2992 }
2993
2994 spin_unlock_irqrestore(&tp->lock, flags);
2995
2996 return IRQ_RETVAL(handled);
2997}
2998
7938109f
MC		 2999/* ISR for interrupt test */
3000static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3001 struct pt_regs *regs)
3002{
3003 struct net_device *dev = dev_id;
3004 struct tg3 *tp = netdev_priv(dev);
3005 struct tg3_hw_status *sblk = tp->hw_status;
3006
3007 if (sblk->status & SD_STATUS_UPDATED) {
3008 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3009 0x00000001);
3010 return IRQ_RETVAL(1);
3011 }
3012 return IRQ_RETVAL(0);
3013}
3014
1da177e4
LT		 3015static int tg3_init_hw(struct tg3 *);
3016static int tg3_halt(struct tg3 *);
3017
3018#ifdef CONFIG_NET_POLL_CONTROLLER
3019static void tg3_poll_controller(struct net_device *dev)
3020{
88b06bc2
MC		 3021 struct tg3 *tp = netdev_priv(dev);
3022
3023 tg3_interrupt(tp->pdev->irq, dev, NULL);
1da177e4
LT		 3024}
3025#endif
3026
3027static void tg3_reset_task(void *_data)
3028{
3029 struct tg3 *tp = _data;
3030 unsigned int restart_timer;
3031
3032 tg3_netif_stop(tp);
3033
3034 spin_lock_irq(&tp->lock);
3035 spin_lock(&tp->tx_lock);
3036
3037 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3038 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3039
3040 tg3_halt(tp);
3041 tg3_init_hw(tp);
3042
3043 tg3_netif_start(tp);
3044
3045 spin_unlock(&tp->tx_lock);
3046 spin_unlock_irq(&tp->lock);
3047
3048 if (restart_timer)
3049 mod_timer(&tp->timer, jiffies + 1);
3050}
3051
3052static void tg3_tx_timeout(struct net_device *dev)
3053{
3054 struct tg3 *tp = netdev_priv(dev);
3055
3056 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3057 dev->name);
3058
3059 schedule_work(&tp->reset_task);
3060}
3061
3062static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3063
3064static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3065 u32 guilty_entry, int guilty_len,
3066 u32 last_plus_one, u32 *start, u32 mss)
3067{
3068 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3069 dma_addr_t new_addr;
3070 u32 entry = *start;
3071 int i;
3072
3073 if (!new_skb) {
3074 dev_kfree_skb(skb);
3075 return -1;
3076 }
3077
3078 /* New SKB is guaranteed to be linear. */
3079 entry = *start;
3080 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3081 PCI_DMA_TODEVICE);
3082 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3083 (skb->ip_summed == CHECKSUM_HW) ?
3084 TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3085 *start = NEXT_TX(entry);
3086
3087 /* Now clean up the sw ring entries. */
3088 i = 0;
3089 while (entry != last_plus_one) {
3090 int len;
3091
3092 if (i == 0)
3093 len = skb_headlen(skb);
3094 else
3095 len = skb_shinfo(skb)->frags[i-1].size;
3096 pci_unmap_single(tp->pdev,
3097 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3098 len, PCI_DMA_TODEVICE);
3099 if (i == 0) {
3100 tp->tx_buffers[entry].skb = new_skb;
3101 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3102 } else {
3103 tp->tx_buffers[entry].skb = NULL;
3104 }
3105 entry = NEXT_TX(entry);
3106 i++;
3107 }
3108
3109 dev_kfree_skb(skb);
3110
3111 return 0;
3112}
3113
3114static void tg3_set_txd(struct tg3 *tp, int entry,
3115 dma_addr_t mapping, int len, u32 flags,
3116 u32 mss_and_is_end)
3117{
3118 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3119 int is_end = (mss_and_is_end & 0x1);
3120 u32 mss = (mss_and_is_end >> 1);
3121 u32 vlan_tag = 0;
3122
3123 if (is_end)
3124 flags |= TXD_FLAG_END;
3125 if (flags & TXD_FLAG_VLAN) {
3126 vlan_tag = flags >> 16;
3127 flags &= 0xffff;
3128 }
3129 vlan_tag |= (mss << TXD_MSS_SHIFT);
3130
3131 txd->addr_hi = ((u64) mapping >> 32);
3132 txd->addr_lo = ((u64) mapping & 0xffffffff);
3133 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3134 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3135}
3136
3137static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3138{
3139 u32 base = (u32) mapping & 0xffffffff;
3140
3141 return ((base > 0xffffdcc0) &&
3142 (base + len + 8 < base));
3143}
3144
3145static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3146{
3147 struct tg3 *tp = netdev_priv(dev);
3148 dma_addr_t mapping;
3149 unsigned int i;
3150 u32 len, entry, base_flags, mss;
3151 int would_hit_hwbug;
3152 unsigned long flags;
3153
3154 len = skb_headlen(skb);
3155
3156 /* No BH disabling for tx_lock here. We are running in BH disabled
3157 * context and TX reclaim runs via tp->poll inside of a software
3158 * interrupt. Rejoice!
3159 *
3160 * Actually, things are not so simple. If we are to take a hw
3161 * IRQ here, we can deadlock, consider:
3162 *
3163 * CPU1 CPU2
3164 * tg3_start_xmit
3165 * take tp->tx_lock
3166 * tg3_timer
3167 * take tp->lock
3168 * tg3_interrupt
3169 * spin on tp->lock
3170 * spin on tp->tx_lock
3171 *
3172 * So we really do need to disable interrupts when taking
3173 * tx_lock here.
3174 */
3175 local_irq_save(flags);
3176 if (!spin_trylock(&tp->tx_lock)) {
3177 local_irq_restore(flags);
3178 return NETDEV_TX_LOCKED;
3179 }
3180
3181 /* This is a hard error, log it. */
3182 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3183 netif_stop_queue(dev);
3184 spin_unlock_irqrestore(&tp->tx_lock, flags);
3185 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3186 dev->name);
3187 return NETDEV_TX_BUSY;
3188 }
3189
3190 entry = tp->tx_prod;
3191 base_flags = 0;
3192 if (skb->ip_summed == CHECKSUM_HW)
3193 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3194#if TG3_TSO_SUPPORT != 0
3195 mss = 0;
3196 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3197 (mss = skb_shinfo(skb)->tso_size) != 0) {
3198 int tcp_opt_len, ip_tcp_len;
3199
3200 if (skb_header_cloned(skb) &&
3201 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3202 dev_kfree_skb(skb);
3203 goto out_unlock;
3204 }
3205
3206 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3207 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3208
3209 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3210 TXD_FLAG_CPU_POST_DMA);
3211
3212 skb->nh.iph->check = 0;
3213 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3214 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3215 skb->h.th->check = 0;
3216 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3217 }
3218 else {
3219 skb->h.th->check =
3220 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3221 skb->nh.iph->daddr,
3222 0, IPPROTO_TCP, 0);
3223 }
3224
3225 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3226 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3227 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3228 int tsflags;
3229
3230 tsflags = ((skb->nh.iph->ihl - 5) +
3231 (tcp_opt_len >> 2));
3232 mss |= (tsflags << 11);
3233 }
3234 } else {
3235 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3236 int tsflags;
3237
3238 tsflags = ((skb->nh.iph->ihl - 5) +
3239 (tcp_opt_len >> 2));
3240 base_flags |= tsflags << 12;
3241 }
3242 }
3243 }
3244#else
3245 mss = 0;
3246#endif
3247#if TG3_VLAN_TAG_USED
3248 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3249 base_flags |= (TXD_FLAG_VLAN |
3250 (vlan_tx_tag_get(skb) << 16));
3251#endif
3252
3253 /* Queue skb data, a.k.a. the main skb fragment. */
3254 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3255
3256 tp->tx_buffers[entry].skb = skb;
3257 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3258
3259 would_hit_hwbug = 0;
3260
3261 if (tg3_4g_overflow_test(mapping, len))
3262 would_hit_hwbug = entry + 1;
3263
3264 tg3_set_txd(tp, entry, mapping, len, base_flags,
3265 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3266
3267 entry = NEXT_TX(entry);
3268
3269 /* Now loop through additional data fragments, and queue them. */
3270 if (skb_shinfo(skb)->nr_frags > 0) {
3271 unsigned int i, last;
3272
3273 last = skb_shinfo(skb)->nr_frags - 1;
3274 for (i = 0; i <= last; i++) {
3275 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3276
3277 len = frag->size;
3278 mapping = pci_map_page(tp->pdev,
3279 frag->page,
3280 frag->page_offset,
3281 len, PCI_DMA_TODEVICE);
3282
3283 tp->tx_buffers[entry].skb = NULL;
3284 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3285
3286 if (tg3_4g_overflow_test(mapping, len)) {
3287 /* Only one should match. */
3288 if (would_hit_hwbug)
3289 BUG();
3290 would_hit_hwbug = entry + 1;
3291 }
3292
3293 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3294 tg3_set_txd(tp, entry, mapping, len,
3295 base_flags, (i == last)|(mss << 1));
3296 else
3297 tg3_set_txd(tp, entry, mapping, len,
3298 base_flags, (i == last));
3299
3300 entry = NEXT_TX(entry);
3301 }
3302 }
3303
3304 if (would_hit_hwbug) {
3305 u32 last_plus_one = entry;
3306 u32 start;
3307 unsigned int len = 0;
3308
3309 would_hit_hwbug -= 1;
3310 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3311 entry &= (TG3_TX_RING_SIZE - 1);
3312 start = entry;
3313 i = 0;
3314 while (entry != last_plus_one) {
3315 if (i == 0)
3316 len = skb_headlen(skb);
3317 else
3318 len = skb_shinfo(skb)->frags[i-1].size;
3319
3320 if (entry == would_hit_hwbug)
3321 break;
3322
3323 i++;
3324 entry = NEXT_TX(entry);
3325
3326 }
3327
3328 /* If the workaround fails due to memory/mapping
3329 * failure, silently drop this packet.
3330 */
3331 if (tigon3_4gb_hwbug_workaround(tp, skb,
3332 entry, len,
3333 last_plus_one,
3334 &start, mss))
3335 goto out_unlock;
3336
3337 entry = start;
3338 }
3339
3340 /* Packets are ready, update Tx producer idx local and on card. */
3341 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3342
3343 tp->tx_prod = entry;
3344 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3345 netif_stop_queue(dev);
3346
3347out_unlock:
3348 mmiowb();
3349 spin_unlock_irqrestore(&tp->tx_lock, flags);
3350
3351 dev->trans_start = jiffies;
3352
3353 return NETDEV_TX_OK;
3354}
3355
3356static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3357 int new_mtu)
3358{
3359 dev->mtu = new_mtu;
3360
3361 if (new_mtu > ETH_DATA_LEN)
3362 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3363 else
3364 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3365}
3366
3367static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3368{
3369 struct tg3 *tp = netdev_priv(dev);
3370
3371 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3372 return -EINVAL;
3373
3374 if (!netif_running(dev)) {
3375 /* We'll just catch it later when the
3376 * device is up'd.
3377 */
3378 tg3_set_mtu(dev, tp, new_mtu);
3379 return 0;
3380 }
3381
3382 tg3_netif_stop(tp);
3383 spin_lock_irq(&tp->lock);
3384 spin_lock(&tp->tx_lock);
3385
3386 tg3_halt(tp);
3387
3388 tg3_set_mtu(dev, tp, new_mtu);
3389
3390 tg3_init_hw(tp);
3391
3392 tg3_netif_start(tp);
3393
3394 spin_unlock(&tp->tx_lock);
3395 spin_unlock_irq(&tp->lock);
3396
3397 return 0;
3398}
3399
3400/* Free up pending packets in all rx/tx rings.
3401 *
3402 * The chip has been shut down and the driver detached from
3403 * the networking, so no interrupts or new tx packets will
3404 * end up in the driver. tp->{tx,}lock is not held and we are not
3405 * in an interrupt context and thus may sleep.
3406 */
3407static void tg3_free_rings(struct tg3 *tp)
3408{
3409 struct ring_info *rxp;
3410 int i;
3411
3412 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3413 rxp = &tp->rx_std_buffers[i];
3414
3415 if (rxp->skb == NULL)
3416 continue;
3417 pci_unmap_single(tp->pdev,
3418 pci_unmap_addr(rxp, mapping),
3419 RX_PKT_BUF_SZ - tp->rx_offset,
3420 PCI_DMA_FROMDEVICE);
3421 dev_kfree_skb_any(rxp->skb);
3422 rxp->skb = NULL;
3423 }
3424
3425 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3426 rxp = &tp->rx_jumbo_buffers[i];
3427
3428 if (rxp->skb == NULL)
3429 continue;
3430 pci_unmap_single(tp->pdev,
3431 pci_unmap_addr(rxp, mapping),
3432 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3433 PCI_DMA_FROMDEVICE);
3434 dev_kfree_skb_any(rxp->skb);
3435 rxp->skb = NULL;
3436 }
3437
3438 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3439 struct tx_ring_info *txp;
3440 struct sk_buff *skb;
3441 int j;
3442
3443 txp = &tp->tx_buffers[i];
3444 skb = txp->skb;
3445
3446 if (skb == NULL) {
3447 i++;
3448 continue;
3449 }
3450
3451 pci_unmap_single(tp->pdev,
3452 pci_unmap_addr(txp, mapping),
3453 skb_headlen(skb),
3454 PCI_DMA_TODEVICE);
3455 txp->skb = NULL;
3456
3457 i++;
3458
3459 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3460 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3461 pci_unmap_page(tp->pdev,
3462 pci_unmap_addr(txp, mapping),
3463 skb_shinfo(skb)->frags[j].size,
3464 PCI_DMA_TODEVICE);
3465 i++;
3466 }
3467
3468 dev_kfree_skb_any(skb);
3469 }
3470}
3471
3472/* Initialize tx/rx rings for packet processing.
3473 *
3474 * The chip has been shut down and the driver detached from
3475 * the networking, so no interrupts or new tx packets will
3476 * end up in the driver. tp->{tx,}lock are held and thus
3477 * we may not sleep.
3478 */
3479static void tg3_init_rings(struct tg3 *tp)
3480{
3481 u32 i;
3482
3483 /* Free up all the SKBs. */
3484 tg3_free_rings(tp);
3485
3486 /* Zero out all descriptors. */
3487 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3488 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3489 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3490 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3491
3492 /* Initialize invariants of the rings, we only set this
3493 * stuff once. This works because the card does not
3494 * write into the rx buffer posting rings.
3495 */
3496 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3497 struct tg3_rx_buffer_desc *rxd;
3498
3499 rxd = &tp->rx_std[i];
3500 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3501 << RXD_LEN_SHIFT;
3502 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3503 rxd->opaque = (RXD_OPAQUE_RING_STD |
3504 (i << RXD_OPAQUE_INDEX_SHIFT));
3505 }
3506
3507 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3508 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3509 struct tg3_rx_buffer_desc *rxd;
3510
3511 rxd = &tp->rx_jumbo[i];
3512 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3513 << RXD_LEN_SHIFT;
3514 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3515 RXD_FLAG_JUMBO;
3516 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3517 (i << RXD_OPAQUE_INDEX_SHIFT));
3518 }
3519 }
3520
3521 /* Now allocate fresh SKBs for each rx ring. */
3522 for (i = 0; i < tp->rx_pending; i++) {
3523 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3524 -1, i) < 0)
3525 break;
3526 }
3527
3528 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3529 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3530 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3531 -1, i) < 0)
3532 break;
3533 }
3534 }
3535}
3536
3537/*
3538 * Must not be invoked with interrupt sources disabled and
3539 * the hardware shutdown down.
3540 */
3541static void tg3_free_consistent(struct tg3 *tp)
3542{
3543 if (tp->rx_std_buffers) {
3544 kfree(tp->rx_std_buffers);
3545 tp->rx_std_buffers = NULL;
3546 }
3547 if (tp->rx_std) {
3548 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3549 tp->rx_std, tp->rx_std_mapping);
3550 tp->rx_std = NULL;
3551 }
3552 if (tp->rx_jumbo) {
3553 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3554 tp->rx_jumbo, tp->rx_jumbo_mapping);
3555 tp->rx_jumbo = NULL;
3556 }
3557 if (tp->rx_rcb) {
3558 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3559 tp->rx_rcb, tp->rx_rcb_mapping);
3560 tp->rx_rcb = NULL;
3561 }
3562 if (tp->tx_ring) {
3563 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3564 tp->tx_ring, tp->tx_desc_mapping);
3565 tp->tx_ring = NULL;
3566 }
3567 if (tp->hw_status) {
3568 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3569 tp->hw_status, tp->status_mapping);
3570 tp->hw_status = NULL;
3571 }
3572 if (tp->hw_stats) {
3573 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3574 tp->hw_stats, tp->stats_mapping);
3575 tp->hw_stats = NULL;
3576 }
3577}
3578
3579/*
3580 * Must not be invoked with interrupt sources disabled and
3581 * the hardware shutdown down. Can sleep.
3582 */
3583static int tg3_alloc_consistent(struct tg3 *tp)
3584{
3585 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3586 (TG3_RX_RING_SIZE +
3587 TG3_RX_JUMBO_RING_SIZE)) +
3588 (sizeof(struct tx_ring_info) *
3589 TG3_TX_RING_SIZE),
3590 GFP_KERNEL);
3591 if (!tp->rx_std_buffers)
3592 return -ENOMEM;
3593
3594 memset(tp->rx_std_buffers, 0,
3595 (sizeof(struct ring_info) *
3596 (TG3_RX_RING_SIZE +
3597 TG3_RX_JUMBO_RING_SIZE)) +
3598 (sizeof(struct tx_ring_info) *
3599 TG3_TX_RING_SIZE));
3600
3601 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3602 tp->tx_buffers = (struct tx_ring_info *)
3603 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3604
3605 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3606 &tp->rx_std_mapping);
3607 if (!tp->rx_std)
3608 goto err_out;
3609
3610 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3611 &tp->rx_jumbo_mapping);
3612
3613 if (!tp->rx_jumbo)
3614 goto err_out;
3615
3616 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3617 &tp->rx_rcb_mapping);
3618 if (!tp->rx_rcb)
3619 goto err_out;
3620
3621 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3622 &tp->tx_desc_mapping);
3623 if (!tp->tx_ring)
3624 goto err_out;
3625
3626 tp->hw_status = pci_alloc_consistent(tp->pdev,
3627 TG3_HW_STATUS_SIZE,
3628 &tp->status_mapping);
3629 if (!tp->hw_status)
3630 goto err_out;
3631
3632 tp->hw_stats = pci_alloc_consistent(tp->pdev,
3633 sizeof(struct tg3_hw_stats),
3634 &tp->stats_mapping);
3635 if (!tp->hw_stats)
3636 goto err_out;
3637
3638 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3639 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3640
3641 return 0;
3642
3643err_out:
3644 tg3_free_consistent(tp);
3645 return -ENOMEM;
3646}
3647
3648#define MAX_WAIT_CNT 1000
3649
3650/* To stop a block, clear the enable bit and poll till it
3651 * clears. tp->lock is held.
3652 */
3653static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)
3654{
3655 unsigned int i;
3656 u32 val;
3657
3658 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3659 switch (ofs) {
3660 case RCVLSC_MODE:
3661 case DMAC_MODE:
3662 case MBFREE_MODE:
3663 case BUFMGR_MODE:
3664 case MEMARB_MODE:
3665 /* We can't enable/disable these bits of the
3666 * 5705/5750, just say success.
3667 */
3668 return 0;
3669
3670 default:
3671 break;
3672 };
3673 }
3674
3675 val = tr32(ofs);
3676 val &= ~enable_bit;
3677 tw32_f(ofs, val);
3678
3679 for (i = 0; i < MAX_WAIT_CNT; i++) {
3680 udelay(100);
3681 val = tr32(ofs);
3682 if ((val & enable_bit) == 0)
3683 break;
3684 }
3685
3686 if (i == MAX_WAIT_CNT) {
3687 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3688 "ofs=%lx enable_bit=%x\n",
3689 ofs, enable_bit);
3690 return -ENODEV;
3691 }
3692
3693 return 0;
3694}
3695
3696/* tp->lock is held. */
3697static int tg3_abort_hw(struct tg3 *tp)
3698{
3699 int i, err;
3700
3701 tg3_disable_ints(tp);
3702
3703 tp->rx_mode &= ~RX_MODE_ENABLE;
3704 tw32_f(MAC_RX_MODE, tp->rx_mode);
3705 udelay(10);
3706
3707 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
3708 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE);
3709 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE);
3710 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE);
3711 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE);
3712 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE);
3713
3714 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE);
3715 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE);
3716 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
3717 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
3718 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
3719 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE);
3720 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
3721 if (err)
3722 goto out;
3723
3724 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3725 tw32_f(MAC_MODE, tp->mac_mode);
3726 udelay(40);
3727
3728 tp->tx_mode &= ~TX_MODE_ENABLE;
3729 tw32_f(MAC_TX_MODE, tp->tx_mode);
3730
3731 for (i = 0; i < MAX_WAIT_CNT; i++) {
3732 udelay(100);
3733 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3734 break;
3735 }
3736 if (i >= MAX_WAIT_CNT) {
3737 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3738 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3739 tp->dev->name, tr32(MAC_TX_MODE));
3740 return -ENODEV;
3741 }
3742
3743 err = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
3744 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
3745 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
3746
3747 tw32(FTQ_RESET, 0xffffffff);
3748 tw32(FTQ_RESET, 0x00000000);
3749
3750 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
3751 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
3752 if (err)
3753 goto out;
3754
3755 if (tp->hw_status)
3756 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3757 if (tp->hw_stats)
3758 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3759
3760out:
3761 return err;
3762}
3763
3764/* tp->lock is held. */
3765static int tg3_nvram_lock(struct tg3 *tp)
3766{
3767 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3768 int i;
3769
3770 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3771 for (i = 0; i < 8000; i++) {
3772 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3773 break;
3774 udelay(20);
3775 }
3776 if (i == 8000)
3777 return -ENODEV;
3778 }
3779 return 0;
3780}
3781
3782/* tp->lock is held. */
3783static void tg3_nvram_unlock(struct tg3 *tp)
3784{
3785 if (tp->tg3_flags & TG3_FLAG_NVRAM)
3786 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3787}
3788
e6af301b
MC		 3789/* tp->lock is held. */
3790static void tg3_enable_nvram_access(struct tg3 *tp)
3791{
3792 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3793 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3794 u32 nvaccess = tr32(NVRAM_ACCESS);
3795
3796 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3797 }
3798}
3799
3800/* tp->lock is held. */
3801static void tg3_disable_nvram_access(struct tg3 *tp)
3802{
3803 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3804 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3805 u32 nvaccess = tr32(NVRAM_ACCESS);
3806
3807 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3808 }
3809}
3810
1da177e4
LT		 3811/* tp->lock is held. */
3812static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3813{
3814 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3815 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3816 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3817
3818 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3819 switch (kind) {
3820 case RESET_KIND_INIT:
3821 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3822 DRV_STATE_START);
3823 break;
3824
3825 case RESET_KIND_SHUTDOWN:
3826 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3827 DRV_STATE_UNLOAD);
3828 break;
3829
3830 case RESET_KIND_SUSPEND:
3831 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3832 DRV_STATE_SUSPEND);
3833 break;
3834
3835 default:
3836 break;
3837 };
3838 }
3839}
3840
3841/* tp->lock is held. */
3842static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3843{
3844 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3845 switch (kind) {
3846 case RESET_KIND_INIT:
3847 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3848 DRV_STATE_START_DONE);
3849 break;
3850
3851 case RESET_KIND_SHUTDOWN:
3852 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3853 DRV_STATE_UNLOAD_DONE);
3854 break;
3855
3856 default:
3857 break;
3858 };
3859 }
3860}
3861
3862/* tp->lock is held. */
3863static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3864{
3865 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3866 switch (kind) {
3867 case RESET_KIND_INIT:
3868 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3869 DRV_STATE_START);
3870 break;
3871
3872 case RESET_KIND_SHUTDOWN:
3873 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3874 DRV_STATE_UNLOAD);
3875 break;
3876
3877 case RESET_KIND_SUSPEND:
3878 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3879 DRV_STATE_SUSPEND);
3880 break;
3881
3882 default:
3883 break;
3884 };
3885 }
3886}
3887
3888static void tg3_stop_fw(struct tg3 *);
3889
3890/* tp->lock is held. */
3891static int tg3_chip_reset(struct tg3 *tp)
3892{
3893 u32 val;
3894 u32 flags_save;
3895 int i;
3896
3897 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3898 tg3_nvram_lock(tp);
3899
3900 /*
3901 * We must avoid the readl() that normally takes place.
3902 * It locks machines, causes machine checks, and other
3903 * fun things. So, temporarily disable the 5701
3904 * hardware workaround, while we do the reset.
3905 */
3906 flags_save = tp->tg3_flags;
3907 tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3908
3909 /* do the reset */
3910 val = GRC_MISC_CFG_CORECLK_RESET;
3911
3912 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3913 if (tr32(0x7e2c) == 0x60) {
3914 tw32(0x7e2c, 0x20);
3915 }
3916 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3917 tw32(GRC_MISC_CFG, (1 << 29));
3918 val |= (1 << 29);
3919 }
3920 }
3921
3922 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3923 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3924 tw32(GRC_MISC_CFG, val);
3925
3926 /* restore 5701 hardware bug workaround flag */
3927 tp->tg3_flags = flags_save;
3928
3929 /* Unfortunately, we have to delay before the PCI read back.
3930 * Some 575X chips even will not respond to a PCI cfg access
3931 * when the reset command is given to the chip.
3932 *
3933 * How do these hardware designers expect things to work
3934 * properly if the PCI write is posted for a long period
3935 * of time? It is always necessary to have some method by
3936 * which a register read back can occur to push the write
3937 * out which does the reset.
3938 *
3939 * For most tg3 variants the trick below was working.
3940 * Ho hum...
3941 */
3942 udelay(120);
3943
3944 /* Flush PCI posted writes. The normal MMIO registers
3945 * are inaccessible at this time so this is the only
3946 * way to make this reliably (actually, this is no longer
3947 * the case, see above). I tried to use indirect
3948 * register read/write but this upset some 5701 variants.
3949 */
3950 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
3951
3952 udelay(120);
3953
3954 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3955 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
3956 int i;
3957 u32 cfg_val;
3958
3959 /* Wait for link training to complete. */
3960 for (i = 0; i < 5000; i++)
3961 udelay(100);
3962
3963 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
3964 pci_write_config_dword(tp->pdev, 0xc4,
3965 cfg_val | (1 << 15));
3966 }
3967 /* Set PCIE max payload size and clear error status. */
3968 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
3969 }
3970
3971 /* Re-enable indirect register accesses. */
3972 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
3973 tp->misc_host_ctrl);
3974
3975 /* Set MAX PCI retry to zero. */
3976 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
3977 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
3978 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
3979 val |= PCISTATE_RETRY_SAME_DMA;
3980 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
3981
3982 pci_restore_state(tp->pdev);
3983
3984 /* Make sure PCI-X relaxed ordering bit is clear. */
3985 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
3986 val &= ~PCIX_CAPS_RELAXED_ORDERING;
3987 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
3988
3989 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
3990
3991 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
3992 tg3_stop_fw(tp);
3993 tw32(0x5000, 0x400);
3994 }
3995
3996 tw32(GRC_MODE, tp->grc_mode);
3997
3998 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
3999 u32 val = tr32(0xc4);
4000
4001 tw32(0xc4, val | (1 << 15));
4002 }
4003
4004 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4005 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4006 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4007 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4008 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4009 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4010 }
4011
4012 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4013 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4014 tw32_f(MAC_MODE, tp->mac_mode);
4015 } else
4016 tw32_f(MAC_MODE, 0);
4017 udelay(40);
4018
4019 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4020 /* Wait for firmware initialization to complete. */
4021 for (i = 0; i < 100000; i++) {
4022 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4023 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4024 break;
4025 udelay(10);
4026 }
4027 if (i >= 100000) {
4028 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4029 "firmware will not restart magic=%08x\n",
4030 tp->dev->name, val);
4031 return -ENODEV;
4032 }
4033 }
4034
4035 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4036 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4037 u32 val = tr32(0x7c00);
4038
4039 tw32(0x7c00, val | (1 << 25));
4040 }
4041
4042 /* Reprobe ASF enable state. */
4043 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4044 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4045 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4046 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4047 u32 nic_cfg;
4048
4049 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4050 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4051 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4052 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4053 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4054 }
4055 }
4056
4057 return 0;
4058}
4059
4060/* tp->lock is held. */
4061static void tg3_stop_fw(struct tg3 *tp)
4062{
4063 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4064 u32 val;
4065 int i;
4066
4067 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4068 val = tr32(GRC_RX_CPU_EVENT);
4069 val |= (1 << 14);
4070 tw32(GRC_RX_CPU_EVENT, val);
4071
4072 /* Wait for RX cpu to ACK the event. */
4073 for (i = 0; i < 100; i++) {
4074 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4075 break;
4076 udelay(1);
4077 }
4078 }
4079}
4080
4081/* tp->lock is held. */
4082static int tg3_halt(struct tg3 *tp)
4083{
4084 int err;
4085
4086 tg3_stop_fw(tp);
4087
4088 tg3_write_sig_pre_reset(tp, RESET_KIND_SHUTDOWN);
4089
4090 tg3_abort_hw(tp);
4091 err = tg3_chip_reset(tp);
4092
4093 tg3_write_sig_legacy(tp, RESET_KIND_SHUTDOWN);
4094 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4095
4096 if (err)
4097 return err;
4098
4099 return 0;
4100}
4101
4102#define TG3_FW_RELEASE_MAJOR 0x0
4103#define TG3_FW_RELASE_MINOR 0x0
4104#define TG3_FW_RELEASE_FIX 0x0
4105#define TG3_FW_START_ADDR 0x08000000
4106#define TG3_FW_TEXT_ADDR 0x08000000
4107#define TG3_FW_TEXT_LEN 0x9c0
4108#define TG3_FW_RODATA_ADDR 0x080009c0
4109#define TG3_FW_RODATA_LEN 0x60
4110#define TG3_FW_DATA_ADDR 0x08000a40
4111#define TG3_FW_DATA_LEN 0x20
4112#define TG3_FW_SBSS_ADDR 0x08000a60
4113#define TG3_FW_SBSS_LEN 0xc
4114#define TG3_FW_BSS_ADDR 0x08000a70
4115#define TG3_FW_BSS_LEN 0x10
4116
4117static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4118 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4119 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4120 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4121 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4122 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4123 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4124 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4125 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4126 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4127 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4128 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4129 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4130 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4131 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4132 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4133 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4134 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4135 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4136 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4137 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4138 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4139 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4140 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4142 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4143 0, 0, 0, 0, 0, 0,
4144 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4145 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4146 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4147 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4148 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4149 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4150 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4151 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4152 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4153 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4154 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4156 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4157 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4158 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4159 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4160 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4161 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4162 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4163 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4164 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4165 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4166 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4167 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4168 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4169 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4170 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4171 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4172 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4173 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4174 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4175 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4176 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4177 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4178 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4179 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4180 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4181 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4182 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4183 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4184 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4185 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4186 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4187 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4188 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4189 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4190 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4191 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4192 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4193 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4194 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4195 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4196 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4197 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4198 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4199 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4200 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4201 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4202 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4203 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4204 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4205 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4206 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4207 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4208 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4209};
4210
4211static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4212 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4213 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4214 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4215 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4216 0x00000000
4217};
4218
4219#if 0 /* All zeros, don't eat up space with it. */
4220u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4221 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4222 0x00000000, 0x00000000, 0x00000000, 0x00000000
4223};
4224#endif
4225
4226#define RX_CPU_SCRATCH_BASE 0x30000
4227#define RX_CPU_SCRATCH_SIZE 0x04000
4228#define TX_CPU_SCRATCH_BASE 0x34000
4229#define TX_CPU_SCRATCH_SIZE 0x04000
4230
4231/* tp->lock is held. */
4232static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4233{
4234 int i;
4235
4236 if (offset == TX_CPU_BASE &&
4237 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4238 BUG();
4239
4240 if (offset == RX_CPU_BASE) {
4241 for (i = 0; i < 10000; i++) {
4242 tw32(offset + CPU_STATE, 0xffffffff);
4243 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4244 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4245 break;
4246 }
4247
4248 tw32(offset + CPU_STATE, 0xffffffff);
4249 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4250 udelay(10);
4251 } else {
4252 for (i = 0; i < 10000; i++) {
4253 tw32(offset + CPU_STATE, 0xffffffff);
4254 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4255 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4256 break;
4257 }
4258 }
4259
4260 if (i >= 10000) {
4261 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4262 "and %s CPU\n",
4263 tp->dev->name,
4264 (offset == RX_CPU_BASE ? "RX" : "TX"));
4265 return -ENODEV;
4266 }
4267 return 0;
4268}
4269
4270struct fw_info {
4271 unsigned int text_base;
4272 unsigned int text_len;
4273 u32 *text_data;
4274 unsigned int rodata_base;
4275 unsigned int rodata_len;
4276 u32 *rodata_data;
4277 unsigned int data_base;
4278 unsigned int data_len;
4279 u32 *data_data;
4280};
4281
4282/* tp->lock is held. */
4283static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4284 int cpu_scratch_size, struct fw_info *info)
4285{
4286 int err, i;
4287 u32 orig_tg3_flags = tp->tg3_flags;
4288 void (*write_op)(struct tg3 *, u32, u32);
4289
4290 if (cpu_base == TX_CPU_BASE &&
4291 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4292 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4293 "TX cpu firmware on %s which is 5705.\n",
4294 tp->dev->name);
4295 return -EINVAL;
4296 }
4297
4298 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4299 write_op = tg3_write_mem;
4300 else
4301 write_op = tg3_write_indirect_reg32;
4302
4303 /* Force use of PCI config space for indirect register
4304 * write calls.
4305 */
4306 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4307
4308 err = tg3_halt_cpu(tp, cpu_base);
4309 if (err)
4310 goto out;
4311
4312 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4313 write_op(tp, cpu_scratch_base + i, 0);
4314 tw32(cpu_base + CPU_STATE, 0xffffffff);
4315 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4316 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4317 write_op(tp, (cpu_scratch_base +
4318 (info->text_base & 0xffff) +
4319 (i * sizeof(u32))),
4320 (info->text_data ?
4321 info->text_data[i] : 0));
4322 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4323 write_op(tp, (cpu_scratch_base +
4324 (info->rodata_base & 0xffff) +
4325 (i * sizeof(u32))),
4326 (info->rodata_data ?
4327 info->rodata_data[i] : 0));
4328 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4329 write_op(tp, (cpu_scratch_base +
4330 (info->data_base & 0xffff) +
4331 (i * sizeof(u32))),
4332 (info->data_data ?
4333 info->data_data[i] : 0));
4334
4335 err = 0;
4336
4337out:
4338 tp->tg3_flags = orig_tg3_flags;
4339 return err;
4340}
4341
4342/* tp->lock is held. */
4343static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4344{
4345 struct fw_info info;
4346 int err, i;
4347
4348 info.text_base = TG3_FW_TEXT_ADDR;
4349 info.text_len = TG3_FW_TEXT_LEN;
4350 info.text_data = &tg3FwText[0];
4351 info.rodata_base = TG3_FW_RODATA_ADDR;
4352 info.rodata_len = TG3_FW_RODATA_LEN;
4353 info.rodata_data = &tg3FwRodata[0];
4354 info.data_base = TG3_FW_DATA_ADDR;
4355 info.data_len = TG3_FW_DATA_LEN;
4356 info.data_data = NULL;
4357
4358 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4359 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4360 &info);
4361 if (err)
4362 return err;
4363
4364 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4365 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4366 &info);
4367 if (err)
4368 return err;
4369
4370 /* Now startup only the RX cpu. */
4371 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4372 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4373
4374 for (i = 0; i < 5; i++) {
4375 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4376 break;
4377 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4378 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4379 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4380 udelay(1000);
4381 }
4382 if (i >= 5) {
4383 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4384 "to set RX CPU PC, is %08x should be %08x\n",
4385 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4386 TG3_FW_TEXT_ADDR);
4387 return -ENODEV;
4388 }
4389 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4390 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4391
4392 return 0;
4393}
4394
4395#if TG3_TSO_SUPPORT != 0
4396
4397#define TG3_TSO_FW_RELEASE_MAJOR 0x1
4398#define TG3_TSO_FW_RELASE_MINOR 0x6
4399#define TG3_TSO_FW_RELEASE_FIX 0x0
4400#define TG3_TSO_FW_START_ADDR 0x08000000
4401#define TG3_TSO_FW_TEXT_ADDR 0x08000000
4402#define TG3_TSO_FW_TEXT_LEN 0x1aa0
4403#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4404#define TG3_TSO_FW_RODATA_LEN 0x60
4405#define TG3_TSO_FW_DATA_ADDR 0x08001b20
4406#define TG3_TSO_FW_DATA_LEN 0x30
4407#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4408#define TG3_TSO_FW_SBSS_LEN 0x2c
4409#define TG3_TSO_FW_BSS_ADDR 0x08001b80
4410#define TG3_TSO_FW_BSS_LEN 0x894
4411
4412static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4413 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4414 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4415 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4416 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4417 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4418 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4419 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4420 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4421 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4422 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4423 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4424 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4425 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4426 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4427 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4428 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4429 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4430 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4431 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4432 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4433 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4434 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4435 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4436 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4437 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4438 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4439 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4440 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4441 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4442 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4443 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4444 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4445 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4446 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4447 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4448 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4449 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4450 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4451 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4452 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4453 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4454 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4455 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4456 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4457 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4458 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4459 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4460 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4461 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4462 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4463 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4464 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4465 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4466 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4467 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4468 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4469 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4470 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4471 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4472 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4473 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4474 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4475 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4476 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4477 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4478 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4479 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4480 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4481 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4482 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4483 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4484 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4485 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4486 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4487 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4488 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4489 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4490 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4491 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4492 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4493 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4494 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4495 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4496 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4497 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4498 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4499 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4500 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4501 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4502 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4503 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4504 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4505 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4506 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4507 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4508 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4509 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4510 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4511 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4512 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4513 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4514 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4515 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4516 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4517 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4518 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4519 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4520 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4521 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4522 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4523 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4524 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4525 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4526 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4527 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4528 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4529 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4530 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4531 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4532 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4533 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4534 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4535 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4536 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4537 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4538 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4539 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4540 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4541 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4542 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4543 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4544 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4545 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4546 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4547 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4548 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4549 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4550 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4551 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4552 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4553 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4554 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4555 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4556 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4557 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4558 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4559 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4560 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4561 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4562 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4563 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4564 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4565 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4566 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4567 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4568 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4569 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4570 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4571 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4572 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4573 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4574 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4575 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4576 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4577 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4578 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4579 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4580 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4581 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4582 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4583 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4584 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4585 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4586 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4587 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4588 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4589 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4590 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4591 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4592 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4593 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4594 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4595 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4596 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4597 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4598 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4599 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4600 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4601 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4602 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4603 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4604 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4605 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4606 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4607 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4608 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4609 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4610 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4611 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4612 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4613 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4614 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4615 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4616 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4617 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4618 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4619 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4620 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4621 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4622 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4623 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4624 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4625 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4626 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4627 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4628 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4629 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4630 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4631 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4632 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4633 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4634 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4635 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4636 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4637 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4638 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4639 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4640 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4641 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4642 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4643 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4644 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4645 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4646 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4647 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4648 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4649 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4650 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4651 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4652 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4653 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4654 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4655 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4656 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4657 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4658 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4659 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4660 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4661 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4662 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4663 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4664 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4665 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4666 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4667 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4668 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4669 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4670 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4671 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4672 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4673 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4674 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4675 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4676 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4677 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4678 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4679 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4680 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4681 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4682 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4683 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4684 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4685 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4686 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4687 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4688 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4689 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4690 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4691 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4692 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4693 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4694 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4695 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4696 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4697};
4698
4699static u32 tg3TsoFwRodata[] = {
4700 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4701 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4702 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4703 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4704 0x00000000,
4705};
4706
4707static u32 tg3TsoFwData[] = {
4708 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4709 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4710 0x00000000,
4711};
4712
4713/* 5705 needs a special version of the TSO firmware. */
4714#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
4715#define TG3_TSO5_FW_RELASE_MINOR 0x2
4716#define TG3_TSO5_FW_RELEASE_FIX 0x0
4717#define TG3_TSO5_FW_START_ADDR 0x00010000
4718#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
4719#define TG3_TSO5_FW_TEXT_LEN 0xe90
4720#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
4721#define TG3_TSO5_FW_RODATA_LEN 0x50
4722#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
4723#define TG3_TSO5_FW_DATA_LEN 0x20
4724#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
4725#define TG3_TSO5_FW_SBSS_LEN 0x28
4726#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
4727#define TG3_TSO5_FW_BSS_LEN 0x88
4728
4729static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4730 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4731 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4732 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4733 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4734 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4735 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4736 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4737 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4738 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4739 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4740 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4741 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4742 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4743 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4744 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4745 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4746 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4747 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4748 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4749 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4750 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4751 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4752 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4753 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4754 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4755 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4756 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4757 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4758 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4759 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4760 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4761 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4762 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4763 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4764 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4765 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4766 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4767 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4768 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4769 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4770 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4771 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4772 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4773 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4774 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4775 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4776 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4777 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4778 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4779 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4780 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4781 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4782 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4783 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4784 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4785 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4786 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4787 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4788 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4789 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4790 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4791 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4792 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4793 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4794 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4795 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4796 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4797 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4798 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4799 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4800 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4801 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4802 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4803 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4804 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4805 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4806 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4807 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4808 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4809 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4810 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4811 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4812 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4813 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4814 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4815 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4816 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4817 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4818 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4819 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4820 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4821 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4822 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4823 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4824 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4825 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4826 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4827 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4828 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4829 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4830 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4831 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4832 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4833 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4834 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4835 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4836 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4837 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4838 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4839 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4840 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4841 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4842 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4843 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4844 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4845 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4846 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4847 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4848 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4849 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4850 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4851 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4852 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4853 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4854 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4855 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4856 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4857 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4858 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4859 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4860 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4861 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4862 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4863 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4864 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4865 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4866 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4867 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4868 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4869 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4870 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4871 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4872 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4873 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4874 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4875 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4876 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4877 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4878 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4879 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4880 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4881 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4882 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4883 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4884 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4885 0x00000000, 0x00000000, 0x00000000,
4886};
4887
4888static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4889 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4890 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4891 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4892 0x00000000, 0x00000000, 0x00000000,
4893};
4894
4895static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4896 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4897 0x00000000, 0x00000000, 0x00000000,
4898};
4899
4900/* tp->lock is held. */
4901static int tg3_load_tso_firmware(struct tg3 *tp)
4902{
4903 struct fw_info info;
4904 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4905 int err, i;
4906
4907 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4908 return 0;
4909
4910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4911 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4912 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4913 info.text_data = &tg3Tso5FwText[0];
4914 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4915 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4916 info.rodata_data = &tg3Tso5FwRodata[0];
4917 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4918 info.data_len = TG3_TSO5_FW_DATA_LEN;
4919 info.data_data = &tg3Tso5FwData[0];
4920 cpu_base = RX_CPU_BASE;
4921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4922 cpu_scratch_size = (info.text_len +
4923 info.rodata_len +
4924 info.data_len +
4925 TG3_TSO5_FW_SBSS_LEN +
4926 TG3_TSO5_FW_BSS_LEN);
4927 } else {
4928 info.text_base = TG3_TSO_FW_TEXT_ADDR;
4929 info.text_len = TG3_TSO_FW_TEXT_LEN;
4930 info.text_data = &tg3TsoFwText[0];
4931 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
4932 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
4933 info.rodata_data = &tg3TsoFwRodata[0];
4934 info.data_base = TG3_TSO_FW_DATA_ADDR;
4935 info.data_len = TG3_TSO_FW_DATA_LEN;
4936 info.data_data = &tg3TsoFwData[0];
4937 cpu_base = TX_CPU_BASE;
4938 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
4939 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
4940 }
4941
4942 err = tg3_load_firmware_cpu(tp, cpu_base,
4943 cpu_scratch_base, cpu_scratch_size,
4944 &info);
4945 if (err)
4946 return err;
4947
4948 /* Now startup the cpu. */
4949 tw32(cpu_base + CPU_STATE, 0xffffffff);
4950 tw32_f(cpu_base + CPU_PC, info.text_base);
4951
4952 for (i = 0; i < 5; i++) {
4953 if (tr32(cpu_base + CPU_PC) == info.text_base)
4954 break;
4955 tw32(cpu_base + CPU_STATE, 0xffffffff);
4956 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
4957 tw32_f(cpu_base + CPU_PC, info.text_base);
4958 udelay(1000);
4959 }
4960 if (i >= 5) {
4961 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
4962 "to set CPU PC, is %08x should be %08x\n",
4963 tp->dev->name, tr32(cpu_base + CPU_PC),
4964 info.text_base);
4965 return -ENODEV;
4966 }
4967 tw32(cpu_base + CPU_STATE, 0xffffffff);
4968 tw32_f(cpu_base + CPU_MODE, 0x00000000);
4969 return 0;
4970}
4971
4972#endif /* TG3_TSO_SUPPORT != 0 */
4973
4974/* tp->lock is held. */
4975static void __tg3_set_mac_addr(struct tg3 *tp)
4976{
4977 u32 addr_high, addr_low;
4978 int i;
4979
4980 addr_high = ((tp->dev->dev_addr[0] << 8) |
4981 tp->dev->dev_addr[1]);
4982 addr_low = ((tp->dev->dev_addr[2] << 24) |
4983 (tp->dev->dev_addr[3] << 16) |
4984 (tp->dev->dev_addr[4] << 8) |
4985 (tp->dev->dev_addr[5] << 0));
4986 for (i = 0; i < 4; i++) {
4987 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
4988 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
4989 }
4990
4991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
4993 for (i = 0; i < 12; i++) {
4994 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
4995 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
4996 }
4997 }
4998
4999 addr_high = (tp->dev->dev_addr[0] +
5000 tp->dev->dev_addr[1] +
5001 tp->dev->dev_addr[2] +
5002 tp->dev->dev_addr[3] +
5003 tp->dev->dev_addr[4] +
5004 tp->dev->dev_addr[5]) &
5005 TX_BACKOFF_SEED_MASK;
5006 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5007}
5008
5009static int tg3_set_mac_addr(struct net_device *dev, void *p)
5010{
5011 struct tg3 *tp = netdev_priv(dev);
5012 struct sockaddr *addr = p;
5013
5014 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5015
5016 spin_lock_irq(&tp->lock);
5017 __tg3_set_mac_addr(tp);
5018 spin_unlock_irq(&tp->lock);
5019
5020 return 0;
5021}
5022
5023/* tp->lock is held. */
5024static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5025 dma_addr_t mapping, u32 maxlen_flags,
5026 u32 nic_addr)
5027{
5028 tg3_write_mem(tp,
5029 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5030 ((u64) mapping >> 32));
5031 tg3_write_mem(tp,
5032 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5033 ((u64) mapping & 0xffffffff));
5034 tg3_write_mem(tp,
5035 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5036 maxlen_flags);
5037
5038 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5039 tg3_write_mem(tp,
5040 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5041 nic_addr);
5042}
5043
5044static void __tg3_set_rx_mode(struct net_device *);
5045
5046/* tp->lock is held. */
5047static int tg3_reset_hw(struct tg3 *tp)
5048{
5049 u32 val, rdmac_mode;
5050 int i, err, limit;
5051
5052 tg3_disable_ints(tp);
5053
5054 tg3_stop_fw(tp);
5055
5056 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5057
5058 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5059 err = tg3_abort_hw(tp);
5060 if (err)
5061 return err;
5062 }
5063
5064 err = tg3_chip_reset(tp);
5065 if (err)
5066 return err;
5067
5068 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5069
5070 /* This works around an issue with Athlon chipsets on
5071 * B3 tigon3 silicon. This bit has no effect on any
5072 * other revision. But do not set this on PCI Express
5073 * chips.
5074 */
5075 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5076 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5077 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5078
5079 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5080 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5081 val = tr32(TG3PCI_PCISTATE);
5082 val |= PCISTATE_RETRY_SAME_DMA;
5083 tw32(TG3PCI_PCISTATE, val);
5084 }
5085
5086 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5087 /* Enable some hw fixes. */
5088 val = tr32(TG3PCI_MSI_DATA);
5089 val |= (1 << 26) | (1 << 28) | (1 << 29);
5090 tw32(TG3PCI_MSI_DATA, val);
5091 }
5092
5093 /* Descriptor ring init may make accesses to the
5094 * NIC SRAM area to setup the TX descriptors, so we
5095 * can only do this after the hardware has been
5096 * successfully reset.
5097 */
5098 tg3_init_rings(tp);
5099
5100 /* This value is determined during the probe time DMA
5101 * engine test, tg3_test_dma.
5102 */
5103 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5104
5105 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5106 GRC_MODE_4X_NIC_SEND_RINGS |
5107 GRC_MODE_NO_TX_PHDR_CSUM |
5108 GRC_MODE_NO_RX_PHDR_CSUM);
5109 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5110 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5111 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5112 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5113 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5114
5115 tw32(GRC_MODE,
5116 tp->grc_mode |
5117 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5118
5119 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5120 val = tr32(GRC_MISC_CFG);
5121 val &= ~0xff;
5122 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5123 tw32(GRC_MISC_CFG, val);
5124
5125 /* Initialize MBUF/DESC pool. */
cbf46853 5126 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 5127 /* Do nothing. */
5128 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5129 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5131 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5132 else
5133 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5134 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5135 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5136 }
5137#if TG3_TSO_SUPPORT != 0
5138 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5139 int fw_len;
5140
5141 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5142 TG3_TSO5_FW_RODATA_LEN +
5143 TG3_TSO5_FW_DATA_LEN +
5144 TG3_TSO5_FW_SBSS_LEN +
5145 TG3_TSO5_FW_BSS_LEN);
5146 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5147 tw32(BUFMGR_MB_POOL_ADDR,
5148 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5149 tw32(BUFMGR_MB_POOL_SIZE,
5150 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5151 }
5152#endif
5153
5154 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5155 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5156 tp->bufmgr_config.mbuf_read_dma_low_water);
5157 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5158 tp->bufmgr_config.mbuf_mac_rx_low_water);
5159 tw32(BUFMGR_MB_HIGH_WATER,
5160 tp->bufmgr_config.mbuf_high_water);
5161 } else {
5162 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5163 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5164 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5165 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5166 tw32(BUFMGR_MB_HIGH_WATER,
5167 tp->bufmgr_config.mbuf_high_water_jumbo);
5168 }
5169 tw32(BUFMGR_DMA_LOW_WATER,
5170 tp->bufmgr_config.dma_low_water);
5171 tw32(BUFMGR_DMA_HIGH_WATER,
5172 tp->bufmgr_config.dma_high_water);
5173
5174 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5175 for (i = 0; i < 2000; i++) {
5176 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5177 break;
5178 udelay(10);
5179 }
5180 if (i >= 2000) {
5181 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5182 tp->dev->name);
5183 return -ENODEV;
5184 }
5185
5186 /* Setup replenish threshold. */
5187 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5188
5189 /* Initialize TG3_BDINFO's at:
5190 * RCVDBDI_STD_BD: standard eth size rx ring
5191 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5192 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5193 *
5194 * like so:
5195 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5196 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5197 * ring attribute flags
5198 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5199 *
5200 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5201 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5202 *
5203 * The size of each ring is fixed in the firmware, but the location is
5204 * configurable.
5205 */
5206 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5207 ((u64) tp->rx_std_mapping >> 32));
5208 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5209 ((u64) tp->rx_std_mapping & 0xffffffff));
5210 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5211 NIC_SRAM_RX_BUFFER_DESC);
5212
5213 /* Don't even try to program the JUMBO/MINI buffer descriptor
5214 * configs on 5705.
5215 */
5216 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5217 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5218 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5219 } else {
5220 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5221 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5222
5223 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5224 BDINFO_FLAGS_DISABLED);
5225
5226 /* Setup replenish threshold. */
5227 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5228
5229 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5230 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5231 ((u64) tp->rx_jumbo_mapping >> 32));
5232 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5233 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5234 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5235 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5236 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5237 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5238 } else {
5239 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5240 BDINFO_FLAGS_DISABLED);
5241 }
5242
5243 }
5244
5245 /* There is only one send ring on 5705/5750, no need to explicitly
5246 * disable the others.
5247 */
5248 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5249 /* Clear out send RCB ring in SRAM. */
5250 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5251 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5252 BDINFO_FLAGS_DISABLED);
5253 }
5254
5255 tp->tx_prod = 0;
5256 tp->tx_cons = 0;
5257 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5258 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5259
5260 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5261 tp->tx_desc_mapping,
5262 (TG3_TX_RING_SIZE <<
5263 BDINFO_FLAGS_MAXLEN_SHIFT),
5264 NIC_SRAM_TX_BUFFER_DESC);
5265
5266 /* There is only one receive return ring on 5705/5750, no need
5267 * to explicitly disable the others.
5268 */
5269 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5270 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5271 i += TG3_BDINFO_SIZE) {
5272 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5273 BDINFO_FLAGS_DISABLED);
5274 }
5275 }
5276
5277 tp->rx_rcb_ptr = 0;
5278 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5279
5280 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5281 tp->rx_rcb_mapping,
5282 (TG3_RX_RCB_RING_SIZE(tp) <<
5283 BDINFO_FLAGS_MAXLEN_SHIFT),
5284 0);
5285
5286 tp->rx_std_ptr = tp->rx_pending;
5287 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5288 tp->rx_std_ptr);
5289
5290 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5291 tp->rx_jumbo_pending : 0;
5292 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5293 tp->rx_jumbo_ptr);
5294
5295 /* Initialize MAC address and backoff seed. */
5296 __tg3_set_mac_addr(tp);
5297
5298 /* MTU + ethernet header + FCS + optional VLAN tag */
5299 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5300
5301 /* The slot time is changed by tg3_setup_phy if we
5302 * run at gigabit with half duplex.
5303 */
5304 tw32(MAC_TX_LENGTHS,
5305 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5306 (6 << TX_LENGTHS_IPG_SHIFT) |
5307 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5308
5309 /* Receive rules. */
5310 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5311 tw32(RCVLPC_CONFIG, 0x0181);
5312
5313 /* Calculate RDMAC_MODE setting early, we need it to determine
5314 * the RCVLPC_STATE_ENABLE mask.
5315 */
5316 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5317 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5318 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5319 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5320 RDMAC_MODE_LNGREAD_ENAB);
5321 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5322 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 5323
5324 /* If statement applies to 5705 and 5750 PCI devices only */
5325 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5326 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5327 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 5328 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5329 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5330 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5331 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5332 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5333 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5334 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5335 }
5336 }
5337
85e94ced
MC		 5338 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5339 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5340
1da177e4
LT		 5341#if TG3_TSO_SUPPORT != 0
5342 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5343 rdmac_mode |= (1 << 27);
5344#endif
5345
5346 /* Receive/send statistics. */
5347 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5348 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5349 val = tr32(RCVLPC_STATS_ENABLE);
5350 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5351 tw32(RCVLPC_STATS_ENABLE, val);
5352 } else {
5353 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5354 }
5355 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5356 tw32(SNDDATAI_STATSENAB, 0xffffff);
5357 tw32(SNDDATAI_STATSCTRL,
5358 (SNDDATAI_SCTRL_ENABLE |
5359 SNDDATAI_SCTRL_FASTUPD));
5360
5361 /* Setup host coalescing engine. */
5362 tw32(HOSTCC_MODE, 0);
5363 for (i = 0; i < 2000; i++) {
5364 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5365 break;
5366 udelay(10);
5367 }
5368
5369 tw32(HOSTCC_RXCOL_TICKS, 0);
5370 tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
5371 tw32(HOSTCC_RXMAX_FRAMES, 1);
5372 tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
5373 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5374 tw32(HOSTCC_RXCOAL_TICK_INT, 0);
5375 tw32(HOSTCC_TXCOAL_TICK_INT, 0);
5376 }
5377 tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
5378 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
5379
5380 /* set status block DMA address */
5381 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5382 ((u64) tp->status_mapping >> 32));
5383 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5384 ((u64) tp->status_mapping & 0xffffffff));
5385
5386 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5387 /* Status/statistics block address. See tg3_timer,
5388 * the tg3_periodic_fetch_stats call there, and
5389 * tg3_get_stats to see how this works for 5705/5750 chips.
5390 */
5391 tw32(HOSTCC_STAT_COAL_TICKS,
5392 DEFAULT_STAT_COAL_TICKS);
5393 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5394 ((u64) tp->stats_mapping >> 32));
5395 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5396 ((u64) tp->stats_mapping & 0xffffffff));
5397 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5398 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5399 }
5400
5401 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5402
5403 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5404 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5405 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5406 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5407
5408 /* Clear statistics/status block in chip, and status block in ram. */
5409 for (i = NIC_SRAM_STATS_BLK;
5410 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5411 i += sizeof(u32)) {
5412 tg3_write_mem(tp, i, 0);
5413 udelay(40);
5414 }
5415 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5416
5417 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5418 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5419 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5420 udelay(40);
5421
314fba34
MC		 5422 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5423 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5424 * register to preserve the GPIO settings for LOMs. The GPIOs,
5425 * whether used as inputs or outputs, are set by boot code after
5426 * reset.
5427 */
5428 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5429 u32 gpio_mask;
5430
5431 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5432 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 5433
5434 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5435 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5436 GRC_LCLCTRL_GPIO_OUTPUT3;
5437
314fba34
MC		 5438 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5439
5440 /* GPIO1 must be driven high for eeprom write protect */
1da177e4
LT		 5441 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5442 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 5443 }
1da177e4
LT		 5444 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5445 udelay(100);
5446
5447 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5448 tr32(MAILBOX_INTERRUPT_0);
5449
5450 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5451 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5452 udelay(40);
5453 }
5454
5455 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5456 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5457 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5458 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5459 WDMAC_MODE_LNGREAD_ENAB);
5460
85e94ced
MC		 5461 /* If statement applies to 5705 and 5750 PCI devices only */
5462 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5463 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 5465 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5466 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5467 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5468 /* nothing */
5469 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5470 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5471 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5472 val |= WDMAC_MODE_RX_ACCEL;
5473 }
5474 }
5475
5476 tw32_f(WDMAC_MODE, val);
5477 udelay(40);
5478
5479 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5480 val = tr32(TG3PCI_X_CAPS);
5481 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5482 val &= ~PCIX_CAPS_BURST_MASK;
5483 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5484 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5485 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5486 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5487 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5488 val |= (tp->split_mode_max_reqs <<
5489 PCIX_CAPS_SPLIT_SHIFT);
5490 }
5491 tw32(TG3PCI_X_CAPS, val);
5492 }
5493
5494 tw32_f(RDMAC_MODE, rdmac_mode);
5495 udelay(40);
5496
5497 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5498 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5499 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5500 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5501 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5502 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5503 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5504 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5505#if TG3_TSO_SUPPORT != 0
5506 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5507 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5508#endif
5509 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5510 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5511
5512 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5513 err = tg3_load_5701_a0_firmware_fix(tp);
5514 if (err)
5515 return err;
5516 }
5517
5518#if TG3_TSO_SUPPORT != 0
5519 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5520 err = tg3_load_tso_firmware(tp);
5521 if (err)
5522 return err;
5523 }
5524#endif
5525
5526 tp->tx_mode = TX_MODE_ENABLE;
5527 tw32_f(MAC_TX_MODE, tp->tx_mode);
5528 udelay(100);
5529
5530 tp->rx_mode = RX_MODE_ENABLE;
5531 tw32_f(MAC_RX_MODE, tp->rx_mode);
5532 udelay(10);
5533
5534 if (tp->link_config.phy_is_low_power) {
5535 tp->link_config.phy_is_low_power = 0;
5536 tp->link_config.speed = tp->link_config.orig_speed;
5537 tp->link_config.duplex = tp->link_config.orig_duplex;
5538 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5539 }
5540
5541 tp->mi_mode = MAC_MI_MODE_BASE;
5542 tw32_f(MAC_MI_MODE, tp->mi_mode);
5543 udelay(80);
5544
5545 tw32(MAC_LED_CTRL, tp->led_ctrl);
5546
5547 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5548 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5549 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5550 udelay(10);
5551 }
5552 tw32_f(MAC_RX_MODE, tp->rx_mode);
5553 udelay(10);
5554
5555 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5556 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5557 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5558 /* Set drive transmission level to 1.2V */
5559 /* only if the signal pre-emphasis bit is not set */
5560 val = tr32(MAC_SERDES_CFG);
5561 val &= 0xfffff000;
5562 val |= 0x880;
5563 tw32(MAC_SERDES_CFG, val);
5564 }
5565 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5566 tw32(MAC_SERDES_CFG, 0x616000);
5567 }
5568
5569 /* Prevent chip from dropping frames when flow control
5570 * is enabled.
5571 */
5572 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5573
5574 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5575 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5576 /* Use hardware link auto-negotiation */
5577 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5578 }
5579
5580 err = tg3_setup_phy(tp, 1);
5581 if (err)
5582 return err;
5583
5584 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5585 u32 tmp;
5586
5587 /* Clear CRC stats. */
5588 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5589 tg3_writephy(tp, 0x1e, tmp | 0x8000);
5590 tg3_readphy(tp, 0x14, &tmp);
5591 }
5592 }
5593
5594 __tg3_set_rx_mode(tp->dev);
5595
5596 /* Initialize receive rules. */
5597 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
5598 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5599 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
5600 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5601
5602 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5603 limit = 8;
5604 else
5605 limit = 16;
5606 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5607 limit -= 4;
5608 switch (limit) {
5609 case 16:
5610 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
5611 case 15:
5612 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
5613 case 14:
5614 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
5615 case 13:
5616 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
5617 case 12:
5618 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
5619 case 11:
5620 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
5621 case 10:
5622 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
5623 case 9:
5624 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
5625 case 8:
5626 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
5627 case 7:
5628 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
5629 case 6:
5630 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
5631 case 5:
5632 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
5633 case 4:
5634 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
5635 case 3:
5636 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
5637 case 2:
5638 case 1:
5639
5640 default:
5641 break;
5642 };
5643
5644 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5645
5646 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5647 tg3_enable_ints(tp);
5648
5649 return 0;
5650}
5651
5652/* Called at device open time to get the chip ready for
5653 * packet processing. Invoked with tp->lock held.
5654 */
5655static int tg3_init_hw(struct tg3 *tp)
5656{
5657 int err;
5658
5659 /* Force the chip into D0. */
5660 err = tg3_set_power_state(tp, 0);
5661 if (err)
5662 goto out;
5663
5664 tg3_switch_clocks(tp);
5665
5666 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5667
5668 err = tg3_reset_hw(tp);
5669
5670out:
5671 return err;
5672}
5673
5674#define TG3_STAT_ADD32(PSTAT, REG) \
5675do { u32 __val = tr32(REG); \
5676 (PSTAT)->low += __val; \
5677 if ((PSTAT)->low < __val) \
5678 (PSTAT)->high += 1; \
5679} while (0)
5680
5681static void tg3_periodic_fetch_stats(struct tg3 *tp)
5682{
5683 struct tg3_hw_stats *sp = tp->hw_stats;
5684
5685 if (!netif_carrier_ok(tp->dev))
5686 return;
5687
5688 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5689 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5690 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5691 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5692 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5693 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5694 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5695 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5696 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5697 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5698 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5699 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5700 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5701
5702 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5703 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5704 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5705 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5706 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5707 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5708 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5709 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5710 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5711 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5712 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5713 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5714 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5715 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5716}
5717
5718static void tg3_timer(unsigned long __opaque)
5719{
5720 struct tg3 *tp = (struct tg3 *) __opaque;
5721 unsigned long flags;
5722
5723 spin_lock_irqsave(&tp->lock, flags);
5724 spin_lock(&tp->tx_lock);
5725
5726 /* All of this garbage is because when using non-tagged
5727 * IRQ status the mailbox/status_block protocol the chip
5728 * uses with the cpu is race prone.
5729 */
5730 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5731 tw32(GRC_LOCAL_CTRL,
5732 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5733 } else {
5734 tw32(HOSTCC_MODE, tp->coalesce_mode |
5735 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5736 }
5737
5738 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5739 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5740 spin_unlock(&tp->tx_lock);
5741 spin_unlock_irqrestore(&tp->lock, flags);
5742 schedule_work(&tp->reset_task);
5743 return;
5744 }
5745
5746 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5747 tg3_periodic_fetch_stats(tp);
5748
5749 /* This part only runs once per second. */
5750 if (!--tp->timer_counter) {
5751 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5752 u32 mac_stat;
5753 int phy_event;
5754
5755 mac_stat = tr32(MAC_STATUS);
5756
5757 phy_event = 0;
5758 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5759 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5760 phy_event = 1;
5761 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5762 phy_event = 1;
5763
5764 if (phy_event)
5765 tg3_setup_phy(tp, 0);
5766 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5767 u32 mac_stat = tr32(MAC_STATUS);
5768 int need_setup = 0;
5769
5770 if (netif_carrier_ok(tp->dev) &&
5771 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5772 need_setup = 1;
5773 }
5774 if (! netif_carrier_ok(tp->dev) &&
5775 (mac_stat & (MAC_STATUS_PCS_SYNCED |
5776 MAC_STATUS_SIGNAL_DET))) {
5777 need_setup = 1;
5778 }
5779 if (need_setup) {
5780 tw32_f(MAC_MODE,
5781 (tp->mac_mode &
5782 ~MAC_MODE_PORT_MODE_MASK));
5783 udelay(40);
5784 tw32_f(MAC_MODE, tp->mac_mode);
5785 udelay(40);
5786 tg3_setup_phy(tp, 0);
5787 }
5788 }
5789
5790 tp->timer_counter = tp->timer_multiplier;
5791 }
5792
5793 /* Heartbeat is only sent once every 120 seconds. */
5794 if (!--tp->asf_counter) {
5795 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5796 u32 val;
5797
5798 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5799 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5800 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5801 val = tr32(GRC_RX_CPU_EVENT);
5802 val |= (1 << 14);
5803 tw32(GRC_RX_CPU_EVENT, val);
5804 }
5805 tp->asf_counter = tp->asf_multiplier;
5806 }
5807
5808 spin_unlock(&tp->tx_lock);
5809 spin_unlock_irqrestore(&tp->lock, flags);
5810
5811 tp->timer.expires = jiffies + tp->timer_offset;
5812 add_timer(&tp->timer);
5813}
5814
7938109f
MC		 5815static int tg3_test_interrupt(struct tg3 *tp)
5816{
5817 struct net_device *dev = tp->dev;
5818 int err, i;
5819 u32 int_mbox = 0;
5820
5821 tg3_disable_ints(tp);
5822
5823 free_irq(tp->pdev->irq, dev);
5824
5825 err = request_irq(tp->pdev->irq, tg3_test_isr,
5826 SA_SHIRQ, dev->name, dev);
5827 if (err)
5828 return err;
5829
5830 tg3_enable_ints(tp);
5831
5832 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
5833 HOSTCC_MODE_NOW);
5834
5835 for (i = 0; i < 5; i++) {
5836 int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5837 if (int_mbox != 0)
5838 break;
5839 msleep(10);
5840 }
5841
5842 tg3_disable_ints(tp);
5843
5844 free_irq(tp->pdev->irq, dev);
5845
5846 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5847 err = request_irq(tp->pdev->irq, tg3_msi,
5848 0, dev->name, dev);
5849 else
5850 err = request_irq(tp->pdev->irq, tg3_interrupt,
5851 SA_SHIRQ, dev->name, dev);
5852
5853 if (err)
5854 return err;
5855
5856 if (int_mbox != 0)
5857 return 0;
5858
5859 return -EIO;
5860}
5861
5862/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5863 * successfully restored
5864 */
5865static int tg3_test_msi(struct tg3 *tp)
5866{
5867 struct net_device *dev = tp->dev;
5868 int err;
5869 u16 pci_cmd;
5870
5871 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
5872 return 0;
5873
5874 /* Turn off SERR reporting in case MSI terminates with Master
5875 * Abort.
5876 */
5877 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
5878 pci_write_config_word(tp->pdev, PCI_COMMAND,
5879 pci_cmd & ~PCI_COMMAND_SERR);
5880
5881 err = tg3_test_interrupt(tp);
5882
5883 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
5884
5885 if (!err)
5886 return 0;
5887
5888 /* other failures */
5889 if (err != -EIO)
5890 return err;
5891
5892 /* MSI test failed, go back to INTx mode */
5893 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
5894 "switching to INTx mode. Please report this failure to "
5895 "the PCI maintainer and include system chipset information.\n",
5896 tp->dev->name);
5897
5898 free_irq(tp->pdev->irq, dev);
5899 pci_disable_msi(tp->pdev);
5900
5901 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5902
5903 err = request_irq(tp->pdev->irq, tg3_interrupt,
5904 SA_SHIRQ, dev->name, dev);
5905
5906 if (err)
5907 return err;
5908
5909 /* Need to reset the chip because the MSI cycle may have terminated
5910 * with Master Abort.
5911 */
5912 spin_lock_irq(&tp->lock);
5913 spin_lock(&tp->tx_lock);
5914
5915 tg3_halt(tp);
5916 err = tg3_init_hw(tp);
5917
5918 spin_unlock(&tp->tx_lock);
5919 spin_unlock_irq(&tp->lock);
5920
5921 if (err)
5922 free_irq(tp->pdev->irq, dev);
5923
5924 return err;
5925}
5926
1da177e4
LT		 5927static int tg3_open(struct net_device *dev)
5928{
5929 struct tg3 *tp = netdev_priv(dev);
5930 int err;
5931
5932 spin_lock_irq(&tp->lock);
5933 spin_lock(&tp->tx_lock);
5934
5935 tg3_disable_ints(tp);
5936 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
5937
5938 spin_unlock(&tp->tx_lock);
5939 spin_unlock_irq(&tp->lock);
5940
5941 /* The placement of this call is tied
5942 * to the setup and use of Host TX descriptors.
5943 */
5944 err = tg3_alloc_consistent(tp);
5945 if (err)
5946 return err;
5947
88b06bc2
MC		 5948 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5949 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
5950 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
5951 if (pci_enable_msi(tp->pdev) == 0) {
5952 u32 msi_mode;
5953
5954 msi_mode = tr32(MSGINT_MODE);
5955 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
5956 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
5957 }
5958 }
5959 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5960 err = request_irq(tp->pdev->irq, tg3_msi,
5961 0, dev->name, dev);
5962 else
5963 err = request_irq(tp->pdev->irq, tg3_interrupt,
5964 SA_SHIRQ, dev->name, dev);
1da177e4
LT		 5965
5966 if (err) {
88b06bc2
MC		 5967 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5968 pci_disable_msi(tp->pdev);
5969 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5970 }
1da177e4
LT		 5971 tg3_free_consistent(tp);
5972 return err;
5973 }
5974
5975 spin_lock_irq(&tp->lock);
5976 spin_lock(&tp->tx_lock);
5977
5978 err = tg3_init_hw(tp);
5979 if (err) {
5980 tg3_halt(tp);
5981 tg3_free_rings(tp);
5982 } else {
5983 tp->timer_offset = HZ / 10;
5984 tp->timer_counter = tp->timer_multiplier = 10;
5985 tp->asf_counter = tp->asf_multiplier = (10 * 120);
5986
5987 init_timer(&tp->timer);
5988 tp->timer.expires = jiffies + tp->timer_offset;
5989 tp->timer.data = (unsigned long) tp;
5990 tp->timer.function = tg3_timer;
1da177e4
LT		 5991 }
5992
5993 spin_unlock(&tp->tx_lock);
5994 spin_unlock_irq(&tp->lock);
5995
5996 if (err) {
88b06bc2
MC		 5997 free_irq(tp->pdev->irq, dev);
5998 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5999 pci_disable_msi(tp->pdev);
6000 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6001 }
1da177e4
LT		 6002 tg3_free_consistent(tp);
6003 return err;
6004 }
6005
7938109f
MC		 6006 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6007 err = tg3_test_msi(tp);
6008 if (err) {
6009 spin_lock_irq(&tp->lock);
6010 spin_lock(&tp->tx_lock);
6011
6012 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6013 pci_disable_msi(tp->pdev);
6014 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6015 }
6016 tg3_halt(tp);
6017 tg3_free_rings(tp);
6018 tg3_free_consistent(tp);
6019
6020 spin_unlock(&tp->tx_lock);
6021 spin_unlock_irq(&tp->lock);
6022
6023 return err;
6024 }
6025 }
6026
1da177e4
LT		 6027 spin_lock_irq(&tp->lock);
6028 spin_lock(&tp->tx_lock);
6029
7938109f
MC		 6030 add_timer(&tp->timer);
6031 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 6032 tg3_enable_ints(tp);
6033
6034 spin_unlock(&tp->tx_lock);
6035 spin_unlock_irq(&tp->lock);
6036
6037 netif_start_queue(dev);
6038
6039 return 0;
6040}
6041
6042#if 0
6043/*static*/ void tg3_dump_state(struct tg3 *tp)
6044{
6045 u32 val32, val32_2, val32_3, val32_4, val32_5;
6046 u16 val16;
6047 int i;
6048
6049 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6050 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6051 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6052 val16, val32);
6053
6054 /* MAC block */
6055 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6056 tr32(MAC_MODE), tr32(MAC_STATUS));
6057 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6058 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6059 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6060 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6061 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6062 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6063
6064 /* Send data initiator control block */
6065 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6066 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6067 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6068 tr32(SNDDATAI_STATSCTRL));
6069
6070 /* Send data completion control block */
6071 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6072
6073 /* Send BD ring selector block */
6074 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6075 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6076
6077 /* Send BD initiator control block */
6078 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6079 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6080
6081 /* Send BD completion control block */
6082 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6083
6084 /* Receive list placement control block */
6085 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6086 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6087 printk(" RCVLPC_STATSCTRL[%08x]\n",
6088 tr32(RCVLPC_STATSCTRL));
6089
6090 /* Receive data and receive BD initiator control block */
6091 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6092 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6093
6094 /* Receive data completion control block */
6095 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6096 tr32(RCVDCC_MODE));
6097
6098 /* Receive BD initiator control block */
6099 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6100 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6101
6102 /* Receive BD completion control block */
6103 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6104 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6105
6106 /* Receive list selector control block */
6107 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6108 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6109
6110 /* Mbuf cluster free block */
6111 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6112 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6113
6114 /* Host coalescing control block */
6115 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6116 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6117 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6118 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6119 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6120 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6121 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6122 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6123 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6124 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6125 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6126 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6127
6128 /* Memory arbiter control block */
6129 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6130 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6131
6132 /* Buffer manager control block */
6133 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6134 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6135 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6136 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6137 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6138 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6139 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6140 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6141
6142 /* Read DMA control block */
6143 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6144 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6145
6146 /* Write DMA control block */
6147 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6148 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6149
6150 /* DMA completion block */
6151 printk("DEBUG: DMAC_MODE[%08x]\n",
6152 tr32(DMAC_MODE));
6153
6154 /* GRC block */
6155 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6156 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6157 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6158 tr32(GRC_LOCAL_CTRL));
6159
6160 /* TG3_BDINFOs */
6161 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6162 tr32(RCVDBDI_JUMBO_BD + 0x0),
6163 tr32(RCVDBDI_JUMBO_BD + 0x4),
6164 tr32(RCVDBDI_JUMBO_BD + 0x8),
6165 tr32(RCVDBDI_JUMBO_BD + 0xc));
6166 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6167 tr32(RCVDBDI_STD_BD + 0x0),
6168 tr32(RCVDBDI_STD_BD + 0x4),
6169 tr32(RCVDBDI_STD_BD + 0x8),
6170 tr32(RCVDBDI_STD_BD + 0xc));
6171 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6172 tr32(RCVDBDI_MINI_BD + 0x0),
6173 tr32(RCVDBDI_MINI_BD + 0x4),
6174 tr32(RCVDBDI_MINI_BD + 0x8),
6175 tr32(RCVDBDI_MINI_BD + 0xc));
6176
6177 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6178 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6179 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6180 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6181 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6182 val32, val32_2, val32_3, val32_4);
6183
6184 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6185 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6186 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6187 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6188 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6189 val32, val32_2, val32_3, val32_4);
6190
6191 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6192 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6193 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6194 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6195 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6196 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6197 val32, val32_2, val32_3, val32_4, val32_5);
6198
6199 /* SW status block */
6200 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6201 tp->hw_status->status,
6202 tp->hw_status->status_tag,
6203 tp->hw_status->rx_jumbo_consumer,
6204 tp->hw_status->rx_consumer,
6205 tp->hw_status->rx_mini_consumer,
6206 tp->hw_status->idx[0].rx_producer,
6207 tp->hw_status->idx[0].tx_consumer);
6208
6209 /* SW statistics block */
6210 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6211 ((u32 *)tp->hw_stats)[0],
6212 ((u32 *)tp->hw_stats)[1],
6213 ((u32 *)tp->hw_stats)[2],
6214 ((u32 *)tp->hw_stats)[3]);
6215
6216 /* Mailboxes */
6217 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6218 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6219 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6220 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6221 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6222
6223 /* NIC side send descriptors. */
6224 for (i = 0; i < 6; i++) {
6225 unsigned long txd;
6226
6227 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6228 + (i * sizeof(struct tg3_tx_buffer_desc));
6229 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6230 i,
6231 readl(txd + 0x0), readl(txd + 0x4),
6232 readl(txd + 0x8), readl(txd + 0xc));
6233 }
6234
6235 /* NIC side RX descriptors. */
6236 for (i = 0; i < 6; i++) {
6237 unsigned long rxd;
6238
6239 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6240 + (i * sizeof(struct tg3_rx_buffer_desc));
6241 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6242 i,
6243 readl(rxd + 0x0), readl(rxd + 0x4),
6244 readl(rxd + 0x8), readl(rxd + 0xc));
6245 rxd += (4 * sizeof(u32));
6246 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6247 i,
6248 readl(rxd + 0x0), readl(rxd + 0x4),
6249 readl(rxd + 0x8), readl(rxd + 0xc));
6250 }
6251
6252 for (i = 0; i < 6; i++) {
6253 unsigned long rxd;
6254
6255 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6256 + (i * sizeof(struct tg3_rx_buffer_desc));
6257 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6258 i,
6259 readl(rxd + 0x0), readl(rxd + 0x4),
6260 readl(rxd + 0x8), readl(rxd + 0xc));
6261 rxd += (4 * sizeof(u32));
6262 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6263 i,
6264 readl(rxd + 0x0), readl(rxd + 0x4),
6265 readl(rxd + 0x8), readl(rxd + 0xc));
6266 }
6267}
6268#endif
6269
6270static struct net_device_stats *tg3_get_stats(struct net_device *);
6271static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6272
6273static int tg3_close(struct net_device *dev)
6274{
6275 struct tg3 *tp = netdev_priv(dev);
6276
6277 netif_stop_queue(dev);
6278
6279 del_timer_sync(&tp->timer);
6280
6281 spin_lock_irq(&tp->lock);
6282 spin_lock(&tp->tx_lock);
6283#if 0
6284 tg3_dump_state(tp);
6285#endif
6286
6287 tg3_disable_ints(tp);
6288
6289 tg3_halt(tp);
6290 tg3_free_rings(tp);
6291 tp->tg3_flags &=
6292 ~(TG3_FLAG_INIT_COMPLETE |
6293 TG3_FLAG_GOT_SERDES_FLOWCTL);
6294 netif_carrier_off(tp->dev);
6295
6296 spin_unlock(&tp->tx_lock);
6297 spin_unlock_irq(&tp->lock);
6298
88b06bc2
MC		 6299 free_irq(tp->pdev->irq, dev);
6300 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6301 pci_disable_msi(tp->pdev);
6302 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6303 }
1da177e4
LT		 6304
6305 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6306 sizeof(tp->net_stats_prev));
6307 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6308 sizeof(tp->estats_prev));
6309
6310 tg3_free_consistent(tp);
6311
6312 return 0;
6313}
6314
6315static inline unsigned long get_stat64(tg3_stat64_t *val)
6316{
6317 unsigned long ret;
6318
6319#if (BITS_PER_LONG == 32)
6320 ret = val->low;
6321#else
6322 ret = ((u64)val->high << 32) | ((u64)val->low);
6323#endif
6324 return ret;
6325}
6326
6327static unsigned long calc_crc_errors(struct tg3 *tp)
6328{
6329 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6330
6331 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6332 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6333 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6334 unsigned long flags;
6335 u32 val;
6336
6337 spin_lock_irqsave(&tp->lock, flags);
6338 if (!tg3_readphy(tp, 0x1e, &val)) {
6339 tg3_writephy(tp, 0x1e, val | 0x8000);
6340 tg3_readphy(tp, 0x14, &val);
6341 } else
6342 val = 0;
6343 spin_unlock_irqrestore(&tp->lock, flags);
6344
6345 tp->phy_crc_errors += val;
6346
6347 return tp->phy_crc_errors;
6348 }
6349
6350 return get_stat64(&hw_stats->rx_fcs_errors);
6351}
6352
6353#define ESTAT_ADD(member) \
6354 estats->member = old_estats->member + \
6355 get_stat64(&hw_stats->member)
6356
6357static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6358{
6359 struct tg3_ethtool_stats *estats = &tp->estats;
6360 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6361 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6362
6363 if (!hw_stats)
6364 return old_estats;
6365
6366 ESTAT_ADD(rx_octets);
6367 ESTAT_ADD(rx_fragments);
6368 ESTAT_ADD(rx_ucast_packets);
6369 ESTAT_ADD(rx_mcast_packets);
6370 ESTAT_ADD(rx_bcast_packets);
6371 ESTAT_ADD(rx_fcs_errors);
6372 ESTAT_ADD(rx_align_errors);
6373 ESTAT_ADD(rx_xon_pause_rcvd);
6374 ESTAT_ADD(rx_xoff_pause_rcvd);
6375 ESTAT_ADD(rx_mac_ctrl_rcvd);
6376 ESTAT_ADD(rx_xoff_entered);
6377 ESTAT_ADD(rx_frame_too_long_errors);
6378 ESTAT_ADD(rx_jabbers);
6379 ESTAT_ADD(rx_undersize_packets);
6380 ESTAT_ADD(rx_in_length_errors);
6381 ESTAT_ADD(rx_out_length_errors);
6382 ESTAT_ADD(rx_64_or_less_octet_packets);
6383 ESTAT_ADD(rx_65_to_127_octet_packets);
6384 ESTAT_ADD(rx_128_to_255_octet_packets);
6385 ESTAT_ADD(rx_256_to_511_octet_packets);
6386 ESTAT_ADD(rx_512_to_1023_octet_packets);
6387 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6388 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6389 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6390 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6391 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6392
6393 ESTAT_ADD(tx_octets);
6394 ESTAT_ADD(tx_collisions);
6395 ESTAT_ADD(tx_xon_sent);
6396 ESTAT_ADD(tx_xoff_sent);
6397 ESTAT_ADD(tx_flow_control);
6398 ESTAT_ADD(tx_mac_errors);
6399 ESTAT_ADD(tx_single_collisions);
6400 ESTAT_ADD(tx_mult_collisions);
6401 ESTAT_ADD(tx_deferred);
6402 ESTAT_ADD(tx_excessive_collisions);
6403 ESTAT_ADD(tx_late_collisions);
6404 ESTAT_ADD(tx_collide_2times);
6405 ESTAT_ADD(tx_collide_3times);
6406 ESTAT_ADD(tx_collide_4times);
6407 ESTAT_ADD(tx_collide_5times);
6408 ESTAT_ADD(tx_collide_6times);
6409 ESTAT_ADD(tx_collide_7times);
6410 ESTAT_ADD(tx_collide_8times);
6411 ESTAT_ADD(tx_collide_9times);
6412 ESTAT_ADD(tx_collide_10times);
6413 ESTAT_ADD(tx_collide_11times);
6414 ESTAT_ADD(tx_collide_12times);
6415 ESTAT_ADD(tx_collide_13times);
6416 ESTAT_ADD(tx_collide_14times);
6417 ESTAT_ADD(tx_collide_15times);
6418 ESTAT_ADD(tx_ucast_packets);
6419 ESTAT_ADD(tx_mcast_packets);
6420 ESTAT_ADD(tx_bcast_packets);
6421 ESTAT_ADD(tx_carrier_sense_errors);
6422 ESTAT_ADD(tx_discards);
6423 ESTAT_ADD(tx_errors);
6424
6425 ESTAT_ADD(dma_writeq_full);
6426 ESTAT_ADD(dma_write_prioq_full);
6427 ESTAT_ADD(rxbds_empty);
6428 ESTAT_ADD(rx_discards);
6429 ESTAT_ADD(rx_errors);
6430 ESTAT_ADD(rx_threshold_hit);
6431
6432 ESTAT_ADD(dma_readq_full);
6433 ESTAT_ADD(dma_read_prioq_full);
6434 ESTAT_ADD(tx_comp_queue_full);
6435
6436 ESTAT_ADD(ring_set_send_prod_index);
6437 ESTAT_ADD(ring_status_update);
6438 ESTAT_ADD(nic_irqs);
6439 ESTAT_ADD(nic_avoided_irqs);
6440 ESTAT_ADD(nic_tx_threshold_hit);
6441
6442 return estats;
6443}
6444
6445static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6446{
6447 struct tg3 *tp = netdev_priv(dev);
6448 struct net_device_stats *stats = &tp->net_stats;
6449 struct net_device_stats *old_stats = &tp->net_stats_prev;
6450 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6451
6452 if (!hw_stats)
6453 return old_stats;
6454
6455 stats->rx_packets = old_stats->rx_packets +
6456 get_stat64(&hw_stats->rx_ucast_packets) +
6457 get_stat64(&hw_stats->rx_mcast_packets) +
6458 get_stat64(&hw_stats->rx_bcast_packets);
6459
6460 stats->tx_packets = old_stats->tx_packets +
6461 get_stat64(&hw_stats->tx_ucast_packets) +
6462 get_stat64(&hw_stats->tx_mcast_packets) +
6463 get_stat64(&hw_stats->tx_bcast_packets);
6464
6465 stats->rx_bytes = old_stats->rx_bytes +
6466 get_stat64(&hw_stats->rx_octets);
6467 stats->tx_bytes = old_stats->tx_bytes +
6468 get_stat64(&hw_stats->tx_octets);
6469
6470 stats->rx_errors = old_stats->rx_errors +
6471 get_stat64(&hw_stats->rx_errors) +
6472 get_stat64(&hw_stats->rx_discards);
6473 stats->tx_errors = old_stats->tx_errors +
6474 get_stat64(&hw_stats->tx_errors) +
6475 get_stat64(&hw_stats->tx_mac_errors) +
6476 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6477 get_stat64(&hw_stats->tx_discards);
6478
6479 stats->multicast = old_stats->multicast +
6480 get_stat64(&hw_stats->rx_mcast_packets);
6481 stats->collisions = old_stats->collisions +
6482 get_stat64(&hw_stats->tx_collisions);
6483
6484 stats->rx_length_errors = old_stats->rx_length_errors +
6485 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6486 get_stat64(&hw_stats->rx_undersize_packets);
6487
6488 stats->rx_over_errors = old_stats->rx_over_errors +
6489 get_stat64(&hw_stats->rxbds_empty);
6490 stats->rx_frame_errors = old_stats->rx_frame_errors +
6491 get_stat64(&hw_stats->rx_align_errors);
6492 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6493 get_stat64(&hw_stats->tx_discards);
6494 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6495 get_stat64(&hw_stats->tx_carrier_sense_errors);
6496
6497 stats->rx_crc_errors = old_stats->rx_crc_errors +
6498 calc_crc_errors(tp);
6499
6500 return stats;
6501}
6502
6503static inline u32 calc_crc(unsigned char *buf, int len)
6504{
6505 u32 reg;
6506 u32 tmp;
6507 int j, k;
6508
6509 reg = 0xffffffff;
6510
6511 for (j = 0; j < len; j++) {
6512 reg ^= buf[j];
6513
6514 for (k = 0; k < 8; k++) {
6515 tmp = reg & 0x01;
6516
6517 reg >>= 1;
6518
6519 if (tmp) {
6520 reg ^= 0xedb88320;
6521 }
6522 }
6523 }
6524
6525 return ~reg;
6526}
6527
6528static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6529{
6530 /* accept or reject all multicast frames */
6531 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6532 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6533 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6534 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6535}
6536
6537static void __tg3_set_rx_mode(struct net_device *dev)
6538{
6539 struct tg3 *tp = netdev_priv(dev);
6540 u32 rx_mode;
6541
6542 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6543 RX_MODE_KEEP_VLAN_TAG);
6544
6545 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6546 * flag clear.
6547 */
6548#if TG3_VLAN_TAG_USED
6549 if (!tp->vlgrp &&
6550 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6551 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6552#else
6553 /* By definition, VLAN is disabled always in this
6554 * case.
6555 */
6556 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6557 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6558#endif
6559
6560 if (dev->flags & IFF_PROMISC) {
6561 /* Promiscuous mode. */
6562 rx_mode |= RX_MODE_PROMISC;
6563 } else if (dev->flags & IFF_ALLMULTI) {
6564 /* Accept all multicast. */
6565 tg3_set_multi (tp, 1);
6566 } else if (dev->mc_count < 1) {
6567 /* Reject all multicast. */
6568 tg3_set_multi (tp, 0);
6569 } else {
6570 /* Accept one or more multicast(s). */
6571 struct dev_mc_list *mclist;
6572 unsigned int i;
6573 u32 mc_filter[4] = { 0, };
6574 u32 regidx;
6575 u32 bit;
6576 u32 crc;
6577
6578 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6579 i++, mclist = mclist->next) {
6580
6581 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6582 bit = ~crc & 0x7f;
6583 regidx = (bit & 0x60) >> 5;
6584 bit &= 0x1f;
6585 mc_filter[regidx] |= (1 << bit);
6586 }
6587
6588 tw32(MAC_HASH_REG_0, mc_filter[0]);
6589 tw32(MAC_HASH_REG_1, mc_filter[1]);
6590 tw32(MAC_HASH_REG_2, mc_filter[2]);
6591 tw32(MAC_HASH_REG_3, mc_filter[3]);
6592 }
6593
6594 if (rx_mode != tp->rx_mode) {
6595 tp->rx_mode = rx_mode;
6596 tw32_f(MAC_RX_MODE, rx_mode);
6597 udelay(10);
6598 }
6599}
6600
6601static void tg3_set_rx_mode(struct net_device *dev)
6602{
6603 struct tg3 *tp = netdev_priv(dev);
6604
6605 spin_lock_irq(&tp->lock);
6606 spin_lock(&tp->tx_lock);
6607 __tg3_set_rx_mode(dev);
6608 spin_unlock(&tp->tx_lock);
6609 spin_unlock_irq(&tp->lock);
6610}
6611
6612#define TG3_REGDUMP_LEN (32 * 1024)
6613
6614static int tg3_get_regs_len(struct net_device *dev)
6615{
6616 return TG3_REGDUMP_LEN;
6617}
6618
6619static void tg3_get_regs(struct net_device *dev,
6620 struct ethtool_regs *regs, void *_p)
6621{
6622 u32 *p = _p;
6623 struct tg3 *tp = netdev_priv(dev);
6624 u8 *orig_p = _p;
6625 int i;
6626
6627 regs->version = 0;
6628
6629 memset(p, 0, TG3_REGDUMP_LEN);
6630
6631 spin_lock_irq(&tp->lock);
6632 spin_lock(&tp->tx_lock);
6633
6634#define __GET_REG32(reg) (*(p)++ = tr32(reg))
6635#define GET_REG32_LOOP(base,len) \
6636do { p = (u32 *)(orig_p + (base)); \
6637 for (i = 0; i < len; i += 4) \
6638 __GET_REG32((base) + i); \
6639} while (0)
6640#define GET_REG32_1(reg) \
6641do { p = (u32 *)(orig_p + (reg)); \
6642 __GET_REG32((reg)); \
6643} while (0)
6644
6645 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6646 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6647 GET_REG32_LOOP(MAC_MODE, 0x4f0);
6648 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6649 GET_REG32_1(SNDDATAC_MODE);
6650 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6651 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6652 GET_REG32_1(SNDBDC_MODE);
6653 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6654 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6655 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6656 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6657 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6658 GET_REG32_1(RCVDCC_MODE);
6659 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6660 GET_REG32_LOOP(RCVCC_MODE, 0x14);
6661 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6662 GET_REG32_1(MBFREE_MODE);
6663 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6664 GET_REG32_LOOP(MEMARB_MODE, 0x10);
6665 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6666 GET_REG32_LOOP(RDMAC_MODE, 0x08);
6667 GET_REG32_LOOP(WDMAC_MODE, 0x08);
6668 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6669 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6670 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6671 GET_REG32_LOOP(FTQ_RESET, 0x120);
6672 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6673 GET_REG32_1(DMAC_MODE);
6674 GET_REG32_LOOP(GRC_MODE, 0x4c);
6675 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6676 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6677
6678#undef __GET_REG32
6679#undef GET_REG32_LOOP
6680#undef GET_REG32_1
6681
6682 spin_unlock(&tp->tx_lock);
6683 spin_unlock_irq(&tp->lock);
6684}
6685
6686static int tg3_get_eeprom_len(struct net_device *dev)
6687{
6688 struct tg3 *tp = netdev_priv(dev);
6689
6690 return tp->nvram_size;
6691}
6692
6693static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6694
6695static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6696{
6697 struct tg3 *tp = netdev_priv(dev);
6698 int ret;
6699 u8 *pd;
6700 u32 i, offset, len, val, b_offset, b_count;
6701
6702 offset = eeprom->offset;
6703 len = eeprom->len;
6704 eeprom->len = 0;
6705
6706 eeprom->magic = TG3_EEPROM_MAGIC;
6707
6708 if (offset & 3) {
6709 /* adjustments to start on required 4 byte boundary */
6710 b_offset = offset & 3;
6711 b_count = 4 - b_offset;
6712 if (b_count > len) {
6713 /* i.e. offset=1 len=2 */
6714 b_count = len;
6715 }
6716 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6717 if (ret)
6718 return ret;
6719 val = cpu_to_le32(val);
6720 memcpy(data, ((char*)&val) + b_offset, b_count);
6721 len -= b_count;
6722 offset += b_count;
6723 eeprom->len += b_count;
6724 }
6725
6726 /* read bytes upto the last 4 byte boundary */
6727 pd = &data[eeprom->len];
6728 for (i = 0; i < (len - (len & 3)); i += 4) {
6729 ret = tg3_nvram_read(tp, offset + i, &val);
6730 if (ret) {
6731 eeprom->len += i;
6732 return ret;
6733 }
6734 val = cpu_to_le32(val);
6735 memcpy(pd + i, &val, 4);
6736 }
6737 eeprom->len += i;
6738
6739 if (len & 3) {
6740 /* read last bytes not ending on 4 byte boundary */
6741 pd = &data[eeprom->len];
6742 b_count = len & 3;
6743 b_offset = offset + len - b_count;
6744 ret = tg3_nvram_read(tp, b_offset, &val);
6745 if (ret)
6746 return ret;
6747 val = cpu_to_le32(val);
6748 memcpy(pd, ((char*)&val), b_count);
6749 eeprom->len += b_count;
6750 }
6751 return 0;
6752}
6753
6754static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6755
6756static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6757{
6758 struct tg3 *tp = netdev_priv(dev);
6759 int ret;
6760 u32 offset, len, b_offset, odd_len, start, end;
6761 u8 *buf;
6762
6763 if (eeprom->magic != TG3_EEPROM_MAGIC)
6764 return -EINVAL;
6765
6766 offset = eeprom->offset;
6767 len = eeprom->len;
6768
6769 if ((b_offset = (offset & 3))) {
6770 /* adjustments to start on required 4 byte boundary */
6771 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6772 if (ret)
6773 return ret;
6774 start = cpu_to_le32(start);
6775 len += b_offset;
6776 offset &= ~3;
1c8594b4
MC		 6777 if (len < 4)
6778 len = 4;
1da177e4
LT		 6779 }
6780
6781 odd_len = 0;
1c8594b4 6782 if (len & 3) {
1da177e4
LT		 6783 /* adjustments to end on required 4 byte boundary */
6784 odd_len = 1;
6785 len = (len + 3) & ~3;
6786 ret = tg3_nvram_read(tp, offset+len-4, &end);
6787 if (ret)
6788 return ret;
6789 end = cpu_to_le32(end);
6790 }
6791
6792 buf = data;
6793 if (b_offset || odd_len) {
6794 buf = kmalloc(len, GFP_KERNEL);
6795 if (buf == 0)
6796 return -ENOMEM;
6797 if (b_offset)
6798 memcpy(buf, &start, 4);
6799 if (odd_len)
6800 memcpy(buf+len-4, &end, 4);
6801 memcpy(buf + b_offset, data, eeprom->len);
6802 }
6803
6804 ret = tg3_nvram_write_block(tp, offset, len, buf);
6805
6806 if (buf != data)
6807 kfree(buf);
6808
6809 return ret;
6810}
6811
6812static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6813{
6814 struct tg3 *tp = netdev_priv(dev);
6815
6816 cmd->supported = (SUPPORTED_Autoneg);
6817
6818 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6819 cmd->supported |= (SUPPORTED_1000baseT_Half |
6820 SUPPORTED_1000baseT_Full);
6821
6822 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6823 cmd->supported |= (SUPPORTED_100baseT_Half |
6824 SUPPORTED_100baseT_Full |
6825 SUPPORTED_10baseT_Half |
6826 SUPPORTED_10baseT_Full |
6827 SUPPORTED_MII);
6828 else
6829 cmd->supported |= SUPPORTED_FIBRE;
6830
6831 cmd->advertising = tp->link_config.advertising;
6832 if (netif_running(dev)) {
6833 cmd->speed = tp->link_config.active_speed;
6834 cmd->duplex = tp->link_config.active_duplex;
6835 }
6836 cmd->port = 0;
6837 cmd->phy_address = PHY_ADDR;
6838 cmd->transceiver = 0;
6839 cmd->autoneg = tp->link_config.autoneg;
6840 cmd->maxtxpkt = 0;
6841 cmd->maxrxpkt = 0;
6842 return 0;
6843}
6844
6845static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6846{
6847 struct tg3 *tp = netdev_priv(dev);
6848
6849 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6850 /* These are the only valid advertisement bits allowed. */
6851 if (cmd->autoneg == AUTONEG_ENABLE &&
6852 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6853 ADVERTISED_1000baseT_Full |
6854 ADVERTISED_Autoneg |
6855 ADVERTISED_FIBRE)))
6856 return -EINVAL;
6857 }
6858
6859 spin_lock_irq(&tp->lock);
6860 spin_lock(&tp->tx_lock);
6861
6862 tp->link_config.autoneg = cmd->autoneg;
6863 if (cmd->autoneg == AUTONEG_ENABLE) {
6864 tp->link_config.advertising = cmd->advertising;
6865 tp->link_config.speed = SPEED_INVALID;
6866 tp->link_config.duplex = DUPLEX_INVALID;
6867 } else {
6868 tp->link_config.advertising = 0;
6869 tp->link_config.speed = cmd->speed;
6870 tp->link_config.duplex = cmd->duplex;
6871 }
6872
6873 if (netif_running(dev))
6874 tg3_setup_phy(tp, 1);
6875
6876 spin_unlock(&tp->tx_lock);
6877 spin_unlock_irq(&tp->lock);
6878
6879 return 0;
6880}
6881
6882static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6883{
6884 struct tg3 *tp = netdev_priv(dev);
6885
6886 strcpy(info->driver, DRV_MODULE_NAME);
6887 strcpy(info->version, DRV_MODULE_VERSION);
6888 strcpy(info->bus_info, pci_name(tp->pdev));
6889}
6890
6891static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6892{
6893 struct tg3 *tp = netdev_priv(dev);
6894
6895 wol->supported = WAKE_MAGIC;
6896 wol->wolopts = 0;
6897 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
6898 wol->wolopts = WAKE_MAGIC;
6899 memset(&wol->sopass, 0, sizeof(wol->sopass));
6900}
6901
6902static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6903{
6904 struct tg3 *tp = netdev_priv(dev);
6905
6906 if (wol->wolopts & ~WAKE_MAGIC)
6907 return -EINVAL;
6908 if ((wol->wolopts & WAKE_MAGIC) &&
6909 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
6910 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
6911 return -EINVAL;
6912
6913 spin_lock_irq(&tp->lock);
6914 if (wol->wolopts & WAKE_MAGIC)
6915 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
6916 else
6917 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
6918 spin_unlock_irq(&tp->lock);
6919
6920 return 0;
6921}
6922
6923static u32 tg3_get_msglevel(struct net_device *dev)
6924{
6925 struct tg3 *tp = netdev_priv(dev);
6926 return tp->msg_enable;
6927}
6928
6929static void tg3_set_msglevel(struct net_device *dev, u32 value)
6930{
6931 struct tg3 *tp = netdev_priv(dev);
6932 tp->msg_enable = value;
6933}
6934
6935#if TG3_TSO_SUPPORT != 0
6936static int tg3_set_tso(struct net_device *dev, u32 value)
6937{
6938 struct tg3 *tp = netdev_priv(dev);
6939
6940 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6941 if (value)
6942 return -EINVAL;
6943 return 0;
6944 }
6945 return ethtool_op_set_tso(dev, value);
6946}
6947#endif
6948
6949static int tg3_nway_reset(struct net_device *dev)
6950{
6951 struct tg3 *tp = netdev_priv(dev);
6952 u32 bmcr;
6953 int r;
6954
6955 if (!netif_running(dev))
6956 return -EAGAIN;
6957
6958 spin_lock_irq(&tp->lock);
6959 r = -EINVAL;
6960 tg3_readphy(tp, MII_BMCR, &bmcr);
6961 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
6962 (bmcr & BMCR_ANENABLE)) {
6963 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
6964 r = 0;
6965 }
6966 spin_unlock_irq(&tp->lock);
6967
6968 return r;
6969}
6970
6971static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6972{
6973 struct tg3 *tp = netdev_priv(dev);
6974
6975 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
6976 ering->rx_mini_max_pending = 0;
6977 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
6978
6979 ering->rx_pending = tp->rx_pending;
6980 ering->rx_mini_pending = 0;
6981 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
6982 ering->tx_pending = tp->tx_pending;
6983}
6984
6985static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6986{
6987 struct tg3 *tp = netdev_priv(dev);
6988
6989 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
6990 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
6991 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
6992 return -EINVAL;
6993
6994 if (netif_running(dev))
6995 tg3_netif_stop(tp);
6996
6997 spin_lock_irq(&tp->lock);
6998 spin_lock(&tp->tx_lock);
6999
7000 tp->rx_pending = ering->rx_pending;
7001
7002 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7003 tp->rx_pending > 63)
7004 tp->rx_pending = 63;
7005 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7006 tp->tx_pending = ering->tx_pending;
7007
7008 if (netif_running(dev)) {
7009 tg3_halt(tp);
7010 tg3_init_hw(tp);
7011 tg3_netif_start(tp);
7012 }
7013
7014 spin_unlock(&tp->tx_lock);
7015 spin_unlock_irq(&tp->lock);
7016
7017 return 0;
7018}
7019
7020static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7021{
7022 struct tg3 *tp = netdev_priv(dev);
7023
7024 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7025 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7026 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7027}
7028
7029static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7030{
7031 struct tg3 *tp = netdev_priv(dev);
7032
7033 if (netif_running(dev))
7034 tg3_netif_stop(tp);
7035
7036 spin_lock_irq(&tp->lock);
7037 spin_lock(&tp->tx_lock);
7038 if (epause->autoneg)
7039 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7040 else
7041 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7042 if (epause->rx_pause)
7043 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7044 else
7045 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7046 if (epause->tx_pause)
7047 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7048 else
7049 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7050
7051 if (netif_running(dev)) {
7052 tg3_halt(tp);
7053 tg3_init_hw(tp);
7054 tg3_netif_start(tp);
7055 }
7056 spin_unlock(&tp->tx_lock);
7057 spin_unlock_irq(&tp->lock);
7058
7059 return 0;
7060}
7061
7062static u32 tg3_get_rx_csum(struct net_device *dev)
7063{
7064 struct tg3 *tp = netdev_priv(dev);
7065 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7066}
7067
7068static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7069{
7070 struct tg3 *tp = netdev_priv(dev);
7071
7072 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7073 if (data != 0)
7074 return -EINVAL;
7075 return 0;
7076 }
7077
7078 spin_lock_irq(&tp->lock);
7079 if (data)
7080 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7081 else
7082 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7083 spin_unlock_irq(&tp->lock);
7084
7085 return 0;
7086}
7087
7088static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7089{
7090 struct tg3 *tp = netdev_priv(dev);
7091
7092 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7093 if (data != 0)
7094 return -EINVAL;
7095 return 0;
7096 }
7097
7098 if (data)
7099 dev->features |= NETIF_F_IP_CSUM;
7100 else
7101 dev->features &= ~NETIF_F_IP_CSUM;
7102
7103 return 0;
7104}
7105
7106static int tg3_get_stats_count (struct net_device *dev)
7107{
7108 return TG3_NUM_STATS;
7109}
7110
7111static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7112{
7113 switch (stringset) {
7114 case ETH_SS_STATS:
7115 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7116 break;
7117 default:
7118 WARN_ON(1); /* we need a WARN() */
7119 break;
7120 }
7121}
7122
7123static void tg3_get_ethtool_stats (struct net_device *dev,
7124 struct ethtool_stats *estats, u64 *tmp_stats)
7125{
7126 struct tg3 *tp = netdev_priv(dev);
7127 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7128}
7129
7130static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7131{
7132 struct mii_ioctl_data *data = if_mii(ifr);
7133 struct tg3 *tp = netdev_priv(dev);
7134 int err;
7135
7136 switch(cmd) {
7137 case SIOCGMIIPHY:
7138 data->phy_id = PHY_ADDR;
7139
7140 /* fallthru */
7141 case SIOCGMIIREG: {
7142 u32 mii_regval;
7143
7144 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7145 break; /* We have no PHY */
7146
7147 spin_lock_irq(&tp->lock);
7148 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7149 spin_unlock_irq(&tp->lock);
7150
7151 data->val_out = mii_regval;
7152
7153 return err;
7154 }
7155
7156 case SIOCSMIIREG:
7157 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7158 break; /* We have no PHY */
7159
7160 if (!capable(CAP_NET_ADMIN))
7161 return -EPERM;
7162
7163 spin_lock_irq(&tp->lock);
7164 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7165 spin_unlock_irq(&tp->lock);
7166
7167 return err;
7168
7169 default:
7170 /* do nothing */
7171 break;
7172 }
7173 return -EOPNOTSUPP;
7174}
7175
7176#if TG3_VLAN_TAG_USED
7177static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7178{
7179 struct tg3 *tp = netdev_priv(dev);
7180
7181 spin_lock_irq(&tp->lock);
7182 spin_lock(&tp->tx_lock);
7183
7184 tp->vlgrp = grp;
7185
7186 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7187 __tg3_set_rx_mode(dev);
7188
7189 spin_unlock(&tp->tx_lock);
7190 spin_unlock_irq(&tp->lock);
7191}
7192
7193static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7194{
7195 struct tg3 *tp = netdev_priv(dev);
7196
7197 spin_lock_irq(&tp->lock);
7198 spin_lock(&tp->tx_lock);
7199 if (tp->vlgrp)
7200 tp->vlgrp->vlan_devices[vid] = NULL;
7201 spin_unlock(&tp->tx_lock);
7202 spin_unlock_irq(&tp->lock);
7203}
7204#endif
7205
7206static struct ethtool_ops tg3_ethtool_ops = {
7207 .get_settings = tg3_get_settings,
7208 .set_settings = tg3_set_settings,
7209 .get_drvinfo = tg3_get_drvinfo,
7210 .get_regs_len = tg3_get_regs_len,
7211 .get_regs = tg3_get_regs,
7212 .get_wol = tg3_get_wol,
7213 .set_wol = tg3_set_wol,
7214 .get_msglevel = tg3_get_msglevel,
7215 .set_msglevel = tg3_set_msglevel,
7216 .nway_reset = tg3_nway_reset,
7217 .get_link = ethtool_op_get_link,
7218 .get_eeprom_len = tg3_get_eeprom_len,
7219 .get_eeprom = tg3_get_eeprom,
7220 .set_eeprom = tg3_set_eeprom,
7221 .get_ringparam = tg3_get_ringparam,
7222 .set_ringparam = tg3_set_ringparam,
7223 .get_pauseparam = tg3_get_pauseparam,
7224 .set_pauseparam = tg3_set_pauseparam,
7225 .get_rx_csum = tg3_get_rx_csum,
7226 .set_rx_csum = tg3_set_rx_csum,
7227 .get_tx_csum = ethtool_op_get_tx_csum,
7228 .set_tx_csum = tg3_set_tx_csum,
7229 .get_sg = ethtool_op_get_sg,
7230 .set_sg = ethtool_op_set_sg,
7231#if TG3_TSO_SUPPORT != 0
7232 .get_tso = ethtool_op_get_tso,
7233 .set_tso = tg3_set_tso,
7234#endif
7235 .get_strings = tg3_get_strings,
7236 .get_stats_count = tg3_get_stats_count,
7237 .get_ethtool_stats = tg3_get_ethtool_stats,
7238};
7239
7240static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7241{
7242 u32 cursize, val;
7243
7244 tp->nvram_size = EEPROM_CHIP_SIZE;
7245
7246 if (tg3_nvram_read(tp, 0, &val) != 0)
7247 return;
7248
7249 if (swab32(val) != TG3_EEPROM_MAGIC)
7250 return;
7251
7252 /*
7253 * Size the chip by reading offsets at increasing powers of two.
7254 * When we encounter our validation signature, we know the addressing
7255 * has wrapped around, and thus have our chip size.
7256 */
7257 cursize = 0x800;
7258
7259 while (cursize < tp->nvram_size) {
7260 if (tg3_nvram_read(tp, cursize, &val) != 0)
7261 return;
7262
7263 if (swab32(val) == TG3_EEPROM_MAGIC)
7264 break;
7265
7266 cursize <<= 1;
7267 }
7268
7269 tp->nvram_size = cursize;
7270}
7271
7272static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7273{
7274 u32 val;
7275
7276 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7277 if (val != 0) {
7278 tp->nvram_size = (val >> 16) * 1024;
7279 return;
7280 }
7281 }
7282 tp->nvram_size = 0x20000;
7283}
7284
7285static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7286{
7287 u32 nvcfg1;
7288
7289 nvcfg1 = tr32(NVRAM_CFG1);
7290 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7291 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7292 }
7293 else {
7294 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7295 tw32(NVRAM_CFG1, nvcfg1);
7296 }
7297
85e94ced 7298 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7299 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7300 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7301 tp->nvram_jedecnum = JEDEC_ATMEL;
7302 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7303 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7304 break;
7305 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7306 tp->nvram_jedecnum = JEDEC_ATMEL;
7307 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7308 break;
7309 case FLASH_VENDOR_ATMEL_EEPROM:
7310 tp->nvram_jedecnum = JEDEC_ATMEL;
7311 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7312 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7313 break;
7314 case FLASH_VENDOR_ST:
7315 tp->nvram_jedecnum = JEDEC_ST;
7316 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7317 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7318 break;
7319 case FLASH_VENDOR_SAIFUN:
7320 tp->nvram_jedecnum = JEDEC_SAIFUN;
7321 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7322 break;
7323 case FLASH_VENDOR_SST_SMALL:
7324 case FLASH_VENDOR_SST_LARGE:
7325 tp->nvram_jedecnum = JEDEC_SST;
7326 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7327 break;
7328 }
7329 }
7330 else {
7331 tp->nvram_jedecnum = JEDEC_ATMEL;
7332 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7333 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7334 }
7335}
7336
361b4ac2
MC		 7337static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7338{
7339 u32 nvcfg1;
7340
7341 nvcfg1 = tr32(NVRAM_CFG1);
7342
e6af301b
MC		 7343 /* NVRAM protection for TPM */
7344 if (nvcfg1 & (1 << 27))
7345 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7346
361b4ac2
MC		 7347 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7348 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7349 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
7350 tp->nvram_jedecnum = JEDEC_ATMEL;
7351 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7352 break;
7353 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
7354 tp->nvram_jedecnum = JEDEC_ATMEL;
7355 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7356 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7357 break;
7358 case FLASH_5752VENDOR_ST_M45PE10:
7359 case FLASH_5752VENDOR_ST_M45PE20:
7360 case FLASH_5752VENDOR_ST_M45PE40:
7361 tp->nvram_jedecnum = JEDEC_ST;
7362 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7363 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7364 break;
7365 }
7366
7367 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
7368 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
7369 case FLASH_5752PAGE_SIZE_256:
7370 tp->nvram_pagesize = 256;
7371 break;
7372 case FLASH_5752PAGE_SIZE_512:
7373 tp->nvram_pagesize = 512;
7374 break;
7375 case FLASH_5752PAGE_SIZE_1K:
7376 tp->nvram_pagesize = 1024;
7377 break;
7378 case FLASH_5752PAGE_SIZE_2K:
7379 tp->nvram_pagesize = 2048;
7380 break;
7381 case FLASH_5752PAGE_SIZE_4K:
7382 tp->nvram_pagesize = 4096;
7383 break;
7384 case FLASH_5752PAGE_SIZE_264:
7385 tp->nvram_pagesize = 264;
7386 break;
7387 }
7388 }
7389 else {
7390 /* For eeprom, set pagesize to maximum eeprom size */
7391 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7392
7393 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7394 tw32(NVRAM_CFG1, nvcfg1);
7395 }
7396}
7397
1da177e4
LT		 7398/* Chips other than 5700/5701 use the NVRAM for fetching info. */
7399static void __devinit tg3_nvram_init(struct tg3 *tp)
7400{
7401 int j;
7402
7403 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
7404 return;
7405
7406 tw32_f(GRC_EEPROM_ADDR,
7407 (EEPROM_ADDR_FSM_RESET |
7408 (EEPROM_DEFAULT_CLOCK_PERIOD <<
7409 EEPROM_ADDR_CLKPERD_SHIFT)));
7410
7411 /* XXX schedule_timeout() ... */
7412 for (j = 0; j < 100; j++)
7413 udelay(10);
7414
7415 /* Enable seeprom accesses. */
7416 tw32_f(GRC_LOCAL_CTRL,
7417 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
7418 udelay(100);
7419
7420 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
7421 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
7422 tp->tg3_flags |= TG3_FLAG_NVRAM;
7423
e6af301b 7424 tg3_enable_nvram_access(tp);
1da177e4 7425
361b4ac2
MC		 7426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7427 tg3_get_5752_nvram_info(tp);
7428 else
7429 tg3_get_nvram_info(tp);
7430
1da177e4
LT		 7431 tg3_get_nvram_size(tp);
7432
e6af301b 7433 tg3_disable_nvram_access(tp);
1da177e4
LT		 7434
7435 } else {
7436 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
7437
7438 tg3_get_eeprom_size(tp);
7439 }
7440}
7441
7442static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
7443 u32 offset, u32 *val)
7444{
7445 u32 tmp;
7446 int i;
7447
7448 if (offset > EEPROM_ADDR_ADDR_MASK ||
7449 (offset % 4) != 0)
7450 return -EINVAL;
7451
7452 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
7453 EEPROM_ADDR_DEVID_MASK |
7454 EEPROM_ADDR_READ);
7455 tw32(GRC_EEPROM_ADDR,
7456 tmp |
7457 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7458 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
7459 EEPROM_ADDR_ADDR_MASK) |
7460 EEPROM_ADDR_READ | EEPROM_ADDR_START);
7461
7462 for (i = 0; i < 10000; i++) {
7463 tmp = tr32(GRC_EEPROM_ADDR);
7464
7465 if (tmp & EEPROM_ADDR_COMPLETE)
7466 break;
7467 udelay(100);
7468 }
7469 if (!(tmp & EEPROM_ADDR_COMPLETE))
7470 return -EBUSY;
7471
7472 *val = tr32(GRC_EEPROM_DATA);
7473 return 0;
7474}
7475
7476#define NVRAM_CMD_TIMEOUT 10000
7477
7478static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
7479{
7480 int i;
7481
7482 tw32(NVRAM_CMD, nvram_cmd);
7483 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
7484 udelay(10);
7485 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
7486 udelay(10);
7487 break;
7488 }
7489 }
7490 if (i == NVRAM_CMD_TIMEOUT) {
7491 return -EBUSY;
7492 }
7493 return 0;
7494}
7495
7496static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7497{
7498 int ret;
7499
7500 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7501 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
7502 return -EINVAL;
7503 }
7504
7505 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
7506 return tg3_nvram_read_using_eeprom(tp, offset, val);
7507
7508 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
7509 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7510 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7511
7512 offset = ((offset / tp->nvram_pagesize) <<
7513 ATMEL_AT45DB0X1B_PAGE_POS) +
7514 (offset % tp->nvram_pagesize);
7515 }
7516
7517 if (offset > NVRAM_ADDR_MSK)
7518 return -EINVAL;
7519
7520 tg3_nvram_lock(tp);
7521
e6af301b 7522 tg3_enable_nvram_access(tp);
1da177e4
LT		 7523
7524 tw32(NVRAM_ADDR, offset);
7525 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
7526 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
7527
7528 if (ret == 0)
7529 *val = swab32(tr32(NVRAM_RDDATA));
7530
7531 tg3_nvram_unlock(tp);
7532
e6af301b 7533 tg3_disable_nvram_access(tp);
1da177e4
LT		 7534
7535 return ret;
7536}
7537
7538static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
7539 u32 offset, u32 len, u8 *buf)
7540{
7541 int i, j, rc = 0;
7542 u32 val;
7543
7544 for (i = 0; i < len; i += 4) {
7545 u32 addr, data;
7546
7547 addr = offset + i;
7548
7549 memcpy(&data, buf + i, 4);
7550
7551 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
7552
7553 val = tr32(GRC_EEPROM_ADDR);
7554 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
7555
7556 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
7557 EEPROM_ADDR_READ);
7558 tw32(GRC_EEPROM_ADDR, val |
7559 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7560 (addr & EEPROM_ADDR_ADDR_MASK) |
7561 EEPROM_ADDR_START |
7562 EEPROM_ADDR_WRITE);
7563
7564 for (j = 0; j < 10000; j++) {
7565 val = tr32(GRC_EEPROM_ADDR);
7566
7567 if (val & EEPROM_ADDR_COMPLETE)
7568 break;
7569 udelay(100);
7570 }
7571 if (!(val & EEPROM_ADDR_COMPLETE)) {
7572 rc = -EBUSY;
7573 break;
7574 }
7575 }
7576
7577 return rc;
7578}
7579
7580/* offset and length are dword aligned */
7581static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
7582 u8 *buf)
7583{
7584 int ret = 0;
7585 u32 pagesize = tp->nvram_pagesize;
7586 u32 pagemask = pagesize - 1;
7587 u32 nvram_cmd;
7588 u8 *tmp;
7589
7590 tmp = kmalloc(pagesize, GFP_KERNEL);
7591 if (tmp == NULL)
7592 return -ENOMEM;
7593
7594 while (len) {
7595 int j;
e6af301b 7596 u32 phy_addr, page_off, size;
1da177e4
LT		 7597
7598 phy_addr = offset & ~pagemask;
7599
7600 for (j = 0; j < pagesize; j += 4) {
7601 if ((ret = tg3_nvram_read(tp, phy_addr + j,
7602 (u32 *) (tmp + j))))
7603 break;
7604 }
7605 if (ret)
7606 break;
7607
7608 page_off = offset & pagemask;
7609 size = pagesize;
7610 if (len < size)
7611 size = len;
7612
7613 len -= size;
7614
7615 memcpy(tmp + page_off, buf, size);
7616
7617 offset = offset + (pagesize - page_off);
7618
e6af301b 7619 tg3_enable_nvram_access(tp);
1da177e4
LT		 7620
7621 /*
7622 * Before we can erase the flash page, we need
7623 * to issue a special "write enable" command.
7624 */
7625 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7626
7627 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7628 break;
7629
7630 /* Erase the target page */
7631 tw32(NVRAM_ADDR, phy_addr);
7632
7633 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
7634 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
7635
7636 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7637 break;
7638
7639 /* Issue another write enable to start the write. */
7640 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7641
7642 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7643 break;
7644
7645 for (j = 0; j < pagesize; j += 4) {
7646 u32 data;
7647
7648 data = *((u32 *) (tmp + j));
7649 tw32(NVRAM_WRDATA, cpu_to_be32(data));
7650
7651 tw32(NVRAM_ADDR, phy_addr + j);
7652
7653 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
7654 NVRAM_CMD_WR;
7655
7656 if (j == 0)
7657 nvram_cmd |= NVRAM_CMD_FIRST;
7658 else if (j == (pagesize - 4))
7659 nvram_cmd |= NVRAM_CMD_LAST;
7660
7661 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
7662 break;
7663 }
7664 if (ret)
7665 break;
7666 }
7667
7668 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7669 tg3_nvram_exec_cmd(tp, nvram_cmd);
7670
7671 kfree(tmp);
7672
7673 return ret;
7674}
7675
7676/* offset and length are dword aligned */
7677static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
7678 u8 *buf)
7679{
7680 int i, ret = 0;
7681
7682 for (i = 0; i < len; i += 4, offset += 4) {
7683 u32 data, page_off, phy_addr, nvram_cmd;
7684
7685 memcpy(&data, buf + i, 4);
7686 tw32(NVRAM_WRDATA, cpu_to_be32(data));
7687
7688 page_off = offset % tp->nvram_pagesize;
7689
7690 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7691 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7692
7693 phy_addr = ((offset / tp->nvram_pagesize) <<
7694 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
7695 }
7696 else {
7697 phy_addr = offset;
7698 }
7699
7700 tw32(NVRAM_ADDR, phy_addr);
7701
7702 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
7703
7704 if ((page_off == 0) || (i == 0))
7705 nvram_cmd |= NVRAM_CMD_FIRST;
7706 else if (page_off == (tp->nvram_pagesize - 4))
7707 nvram_cmd |= NVRAM_CMD_LAST;
7708
7709 if (i == (len - 4))
7710 nvram_cmd |= NVRAM_CMD_LAST;
7711
7712 if ((tp->nvram_jedecnum == JEDEC_ST) &&
7713 (nvram_cmd & NVRAM_CMD_FIRST)) {
7714
7715 if ((ret = tg3_nvram_exec_cmd(tp,
7716 NVRAM_CMD_WREN | NVRAM_CMD_GO |
7717 NVRAM_CMD_DONE)))
7718
7719 break;
7720 }
7721 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
7722 /* We always do complete word writes to eeprom. */
7723 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
7724 }
7725
7726 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
7727 break;
7728 }
7729 return ret;
7730}
7731
7732/* offset and length are dword aligned */
7733static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7734{
7735 int ret;
7736
7737 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7738 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
7739 return -EINVAL;
7740 }
7741
7742 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 7743 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
7744 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 7745 udelay(40);
7746 }
7747
7748 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
7749 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
7750 }
7751 else {
7752 u32 grc_mode;
7753
7754 tg3_nvram_lock(tp);
7755
e6af301b
MC		 7756 tg3_enable_nvram_access(tp);
7757 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7758 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 7759 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 7760
7761 grc_mode = tr32(GRC_MODE);
7762 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
7763
7764 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
7765 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
7766
7767 ret = tg3_nvram_write_block_buffered(tp, offset, len,
7768 buf);
7769 }
7770 else {
7771 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
7772 buf);
7773 }
7774
7775 grc_mode = tr32(GRC_MODE);
7776 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
7777
e6af301b 7778 tg3_disable_nvram_access(tp);
1da177e4
LT		 7779 tg3_nvram_unlock(tp);
7780 }
7781
7782 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 7783 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 7784 udelay(40);
7785 }
7786
7787 return ret;
7788}
7789
7790struct subsys_tbl_ent {
7791 u16 subsys_vendor, subsys_devid;
7792 u32 phy_id;
7793};
7794
7795static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
7796 /* Broadcom boards. */
7797 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
7798 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
7799 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
7800 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
7801 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
7802 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
7803 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
7804 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
7805 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
7806 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
7807 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
7808
7809 /* 3com boards. */
7810 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
7811 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
7812 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
7813 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
7814 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
7815
7816 /* DELL boards. */
7817 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
7818 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
7819 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
7820 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
7821
7822 /* Compaq boards. */
7823 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
7824 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
7825 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
7826 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
7827 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
7828
7829 /* IBM boards. */
7830 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
7831};
7832
7833static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
7834{
7835 int i;
7836
7837 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
7838 if ((subsys_id_to_phy_id[i].subsys_vendor ==
7839 tp->pdev->subsystem_vendor) &&
7840 (subsys_id_to_phy_id[i].subsys_devid ==
7841 tp->pdev->subsystem_device))
7842 return &subsys_id_to_phy_id[i];
7843 }
7844 return NULL;
7845}
7846
7d0c41ef
MC		 7847/* Since this function may be called in D3-hot power state during
7848 * tg3_init_one(), only config cycles are allowed.
7849 */
7850static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 7851{
1da177e4 7852 u32 val;
7d0c41ef
MC		 7853
7854 /* Make sure register accesses (indirect or otherwise)
7855 * will function correctly.
7856 */
7857 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7858 tp->misc_host_ctrl);
1da177e4
LT		 7859
7860 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 7861 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7862
1da177e4
LT		 7863 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7864 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7865 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 7866 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
7867 int eeprom_phy_serdes = 0;
1da177e4
LT		 7868
7869 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7870 tp->nic_sram_data_cfg = nic_cfg;
7871
7872 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
7873 ver >>= NIC_SRAM_DATA_VER_SHIFT;
7874 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
7875 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
7876 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
7877 (ver > 0) && (ver < 0x100))
7878 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
7879
1da177e4
LT		 7880 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
7881 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
7882 eeprom_phy_serdes = 1;
7883
7884 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
7885 if (nic_phy_id != 0) {
7886 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
7887 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
7888
7889 eeprom_phy_id = (id1 >> 16) << 10;
7890 eeprom_phy_id |= (id2 & 0xfc00) << 16;
7891 eeprom_phy_id |= (id2 & 0x03ff) << 0;
7892 } else
7893 eeprom_phy_id = 0;
7894
7d0c41ef
MC		 7895 tp->phy_id = eeprom_phy_id;
7896 if (eeprom_phy_serdes)
7897 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7898
cbf46853 7899 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7900 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
7901 SHASTA_EXT_LED_MODE_MASK);
cbf46853 7902 else
1da177e4
LT		 7903 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
7904
7905 switch (led_cfg) {
7906 default:
7907 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
7908 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7909 break;
7910
7911 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
7912 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
7913 break;
7914
7915 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
7916 tp->led_ctrl = LED_CTRL_MODE_MAC;
7917 break;
7918
7919 case SHASTA_EXT_LED_SHARED:
7920 tp->led_ctrl = LED_CTRL_MODE_SHARED;
7921 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7922 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
7923 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
7924 LED_CTRL_MODE_PHY_2);
7925 break;
7926
7927 case SHASTA_EXT_LED_MAC:
7928 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
7929 break;
7930
7931 case SHASTA_EXT_LED_COMBO:
7932 tp->led_ctrl = LED_CTRL_MODE_COMBO;
7933 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
7934 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
7935 LED_CTRL_MODE_PHY_2);
7936 break;
7937
7938 };
7939
7940 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
7942 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
7943 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
7944
7945 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
7946 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
7947 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
7948 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
7949
7950 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7951 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 7952 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7953 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7954 }
7955 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
7956 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
7957
7958 if (cfg2 & (1 << 17))
7959 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
7960
7961 /* serdes signal pre-emphasis in register 0x590 set by */
7962 /* bootcode if bit 18 is set */
7963 if (cfg2 & (1 << 18))
7964 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
7965 }
7d0c41ef
MC		 7966}
7967
7968static int __devinit tg3_phy_probe(struct tg3 *tp)
7969{
7970 u32 hw_phy_id_1, hw_phy_id_2;
7971 u32 hw_phy_id, hw_phy_id_masked;
7972 int err;
1da177e4
LT		 7973
7974 /* Reading the PHY ID register can conflict with ASF
7975 * firwmare access to the PHY hardware.
7976 */
7977 err = 0;
7978 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7979 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
7980 } else {
7981 /* Now read the physical PHY_ID from the chip and verify
7982 * that it is sane. If it doesn't look good, we fall back
7983 * to either the hard-coded table based PHY_ID and failing
7984 * that the value found in the eeprom area.
7985 */
7986 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
7987 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
7988
7989 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
7990 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
7991 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
7992
7993 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
7994 }
7995
7996 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
7997 tp->phy_id = hw_phy_id;
7998 if (hw_phy_id_masked == PHY_ID_BCM8002)
7999 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8000 } else {
7d0c41ef
MC		 8001 if (tp->phy_id != PHY_ID_INVALID) {
8002 /* Do nothing, phy ID already set up in
8003 * tg3_get_eeprom_hw_cfg().
8004 */
1da177e4
LT		 8005 } else {
8006 struct subsys_tbl_ent *p;
8007
8008 /* No eeprom signature? Try the hardcoded
8009 * subsys device table.
8010 */
8011 p = lookup_by_subsys(tp);
8012 if (!p)
8013 return -ENODEV;
8014
8015 tp->phy_id = p->phy_id;
8016 if (!tp->phy_id ||
8017 tp->phy_id == PHY_ID_BCM8002)
8018 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8019 }
8020 }
8021
8022 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8023 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8024 u32 bmsr, adv_reg, tg3_ctrl;
8025
8026 tg3_readphy(tp, MII_BMSR, &bmsr);
8027 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
8028 (bmsr & BMSR_LSTATUS))
8029 goto skip_phy_reset;
8030
8031 err = tg3_phy_reset(tp);
8032 if (err)
8033 return err;
8034
8035 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
8036 ADVERTISE_100HALF | ADVERTISE_100FULL |
8037 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
8038 tg3_ctrl = 0;
8039 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
8040 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
8041 MII_TG3_CTRL_ADV_1000_FULL);
8042 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8043 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
8044 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
8045 MII_TG3_CTRL_ENABLE_AS_MASTER);
8046 }
8047
8048 if (!tg3_copper_is_advertising_all(tp)) {
8049 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8050
8051 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8052 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8053
8054 tg3_writephy(tp, MII_BMCR,
8055 BMCR_ANENABLE | BMCR_ANRESTART);
8056 }
8057 tg3_phy_set_wirespeed(tp);
8058
8059 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8060 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8061 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8062 }
8063
8064skip_phy_reset:
8065 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8066 err = tg3_init_5401phy_dsp(tp);
8067 if (err)
8068 return err;
8069 }
8070
8071 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
8072 err = tg3_init_5401phy_dsp(tp);
8073 }
8074
1da177e4
LT		 8075 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8076 tp->link_config.advertising =
8077 (ADVERTISED_1000baseT_Half |
8078 ADVERTISED_1000baseT_Full |
8079 ADVERTISED_Autoneg |
8080 ADVERTISED_FIBRE);
8081 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8082 tp->link_config.advertising &=
8083 ~(ADVERTISED_1000baseT_Half |
8084 ADVERTISED_1000baseT_Full);
8085
8086 return err;
8087}
8088
8089static void __devinit tg3_read_partno(struct tg3 *tp)
8090{
8091 unsigned char vpd_data[256];
8092 int i;
8093
8094 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8095 /* Sun decided not to put the necessary bits in the
8096 * NVRAM of their onboard tg3 parts :(
8097 */
8098 strcpy(tp->board_part_number, "Sun 570X");
8099 return;
8100 }
8101
8102 for (i = 0; i < 256; i += 4) {
8103 u32 tmp;
8104
8105 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
8106 goto out_not_found;
8107
8108 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
8109 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
8110 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
8111 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
8112 }
8113
8114 /* Now parse and find the part number. */
8115 for (i = 0; i < 256; ) {
8116 unsigned char val = vpd_data[i];
8117 int block_end;
8118
8119 if (val == 0x82 || val == 0x91) {
8120 i = (i + 3 +
8121 (vpd_data[i + 1] +
8122 (vpd_data[i + 2] << 8)));
8123 continue;
8124 }
8125
8126 if (val != 0x90)
8127 goto out_not_found;
8128
8129 block_end = (i + 3 +
8130 (vpd_data[i + 1] +
8131 (vpd_data[i + 2] << 8)));
8132 i += 3;
8133 while (i < block_end) {
8134 if (vpd_data[i + 0] == 'P' &&
8135 vpd_data[i + 1] == 'N') {
8136 int partno_len = vpd_data[i + 2];
8137
8138 if (partno_len > 24)
8139 goto out_not_found;
8140
8141 memcpy(tp->board_part_number,
8142 &vpd_data[i + 3],
8143 partno_len);
8144
8145 /* Success. */
8146 return;
8147 }
8148 }
8149
8150 /* Part number not found. */
8151 goto out_not_found;
8152 }
8153
8154out_not_found:
8155 strcpy(tp->board_part_number, "none");
8156}
8157
8158#ifdef CONFIG_SPARC64
8159static int __devinit tg3_is_sun_570X(struct tg3 *tp)
8160{
8161 struct pci_dev *pdev = tp->pdev;
8162 struct pcidev_cookie *pcp = pdev->sysdata;
8163
8164 if (pcp != NULL) {
8165 int node = pcp->prom_node;
8166 u32 venid;
8167 int err;
8168
8169 err = prom_getproperty(node, "subsystem-vendor-id",
8170 (char *) &venid, sizeof(venid));
8171 if (err == 0 || err == -1)
8172 return 0;
8173 if (venid == PCI_VENDOR_ID_SUN)
8174 return 1;
8175 }
8176 return 0;
8177}
8178#endif
8179
8180static int __devinit tg3_get_invariants(struct tg3 *tp)
8181{
8182 static struct pci_device_id write_reorder_chipsets[] = {
8183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8184 PCI_DEVICE_ID_INTEL_82801AA_8) },
8185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8186 PCI_DEVICE_ID_INTEL_82801AB_8) },
8187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8188 PCI_DEVICE_ID_INTEL_82801BA_11) },
8189 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8190 PCI_DEVICE_ID_INTEL_82801BA_6) },
8191 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
8192 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
8193 { },
8194 };
8195 u32 misc_ctrl_reg;
8196 u32 cacheline_sz_reg;
8197 u32 pci_state_reg, grc_misc_cfg;
8198 u32 val;
8199 u16 pci_cmd;
8200 int err;
8201
8202#ifdef CONFIG_SPARC64
8203 if (tg3_is_sun_570X(tp))
8204 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
8205#endif
8206
8207 /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8208 * reordering to the mailbox registers done by the host
8209 * controller can cause major troubles. We read back from
8210 * every mailbox register write to force the writes to be
8211 * posted to the chip in order.
8212 */
8213 if (pci_dev_present(write_reorder_chipsets))
8214 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
8215
8216 /* Force memory write invalidate off. If we leave it on,
8217 * then on 5700_BX chips we have to enable a workaround.
8218 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8219 * to match the cacheline size. The Broadcom driver have this
8220 * workaround but turns MWI off all the times so never uses
8221 * it. This seems to suggest that the workaround is insufficient.
8222 */
8223 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8224 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8225 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8226
8227 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8228 * has the register indirect write enable bit set before
8229 * we try to access any of the MMIO registers. It is also
8230 * critical that the PCI-X hw workaround situation is decided
8231 * before that as well.
8232 */
8233 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8234 &misc_ctrl_reg);
8235
8236 tp->pci_chip_rev_id = (misc_ctrl_reg >>
8237 MISC_HOST_CTRL_CHIPREV_SHIFT);
8238
ff645bec
MC		 8239 /* Wrong chip ID in 5752 A0. This code can be removed later
8240 * as A0 is not in production.
8241 */
8242 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8243 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8244
1da177e4
LT		 8245 /* Initialize misc host control in PCI block. */
8246 tp->misc_host_ctrl |= (misc_ctrl_reg &
8247 MISC_HOST_CTRL_CHIPREV);
8248 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8249 tp->misc_host_ctrl);
8250
8251 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8252 &cacheline_sz_reg);
8253
8254 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
8255 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
8256 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
8257 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
8258
6708e5cc 8259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
ff645bec 8260 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6708e5cc
JL		 8261 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8262
1b440c56
JL		 8263 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
8264 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
8265 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
8266
bb7064dc 8267 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8268 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8269
8270 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8271 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8272
8273 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8274 tp->pci_lat_timer < 64) {
8275 tp->pci_lat_timer = 64;
8276
8277 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
8278 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
8279 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
8280 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
8281
8282 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8283 cacheline_sz_reg);
8284 }
8285
8286 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8287 &pci_state_reg);
8288
8289 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8290 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8291
8292 /* If this is a 5700 BX chipset, and we are in PCI-X
8293 * mode, enable register write workaround.
8294 *
8295 * The workaround is to use indirect register accesses
8296 * for all chip writes not to mailbox registers.
8297 */
8298 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8299 u32 pm_reg;
8300 u16 pci_cmd;
8301
8302 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8303
8304 /* The chip can have it's power management PCI config
8305 * space registers clobbered due to this bug.
8306 * So explicitly force the chip into D0 here.
8307 */
8308 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8309 &pm_reg);
8310 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8311 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8312 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8313 pm_reg);
8314
8315 /* Also, force SERR#/PERR# in PCI command. */
8316 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8317 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8318 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8319 }
8320 }
8321
8322 /* Back to back register writes can cause problems on this chip,
8323 * the workaround is to read back all reg writes except those to
8324 * mailbox regs. See tg3_write_indirect_reg32().
8325 *
8326 * PCI Express 5750_A0 rev chips need this workaround too.
8327 */
8328 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8329 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8330 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8331 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8332
8333 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8334 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8335 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8336 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8337
8338 /* Chip-specific fixup from Broadcom driver */
8339 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8340 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8341 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8342 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8343 }
8344
7d0c41ef
MC		 8345 /* Get eeprom hw config before calling tg3_set_power_state().
8346 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8347 * determined before calling tg3_set_power_state() so that
8348 * we know whether or not to switch out of Vaux power.
8349 * When the flag is set, it means that GPIO1 is used for eeprom
8350 * write protect and also implies that it is a LOM where GPIOs
8351 * are not used to switch power.
8352 */
8353 tg3_get_eeprom_hw_cfg(tp);
8354
314fba34
MC		 8355 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8356 * GPIO1 driven high will bring 5700's external PHY out of reset.
8357 * It is also used as eeprom write protect on LOMs.
8358 */
8359 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
8360 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8361 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
8362 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8363 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 8364 /* Unused GPIO3 must be driven as output on 5752 because there
8365 * are no pull-up resistors on unused GPIO pins.
8366 */
8367 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8368 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 8369
1da177e4
LT		 8370 /* Force the chip into D0. */
8371 err = tg3_set_power_state(tp, 0);
8372 if (err) {
8373 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
8374 pci_name(tp->pdev));
8375 return err;
8376 }
8377
8378 /* 5700 B0 chips do not support checksumming correctly due
8379 * to hardware bugs.
8380 */
8381 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
8382 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
8383
8384 /* Pseudo-header checksum is done by hardware logic and not
8385 * the offload processers, so make the chip do the pseudo-
8386 * header checksums on receive. For transmit it is more
8387 * convenient to do the pseudo-header checksum in software
8388 * as Linux does that on transmit for us in all cases.
8389 */
8390 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
8391 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
8392
8393 /* Derive initial jumbo mode from MTU assigned in
8394 * ether_setup() via the alloc_etherdev() call
8395 */
8396 if (tp->dev->mtu > ETH_DATA_LEN)
8397 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
8398
8399 /* Determine WakeOnLan speed to use. */
8400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8401 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8402 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
8403 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
8404 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
8405 } else {
8406 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
8407 }
8408
8409 /* A few boards don't want Ethernet@WireSpeed phy feature */
8410 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8411 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
8412 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
8413 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
8414 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
8415
8416 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
8417 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
8418 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
8419 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
8420 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
8421
bb7064dc 8422 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
1da177e4
LT		 8423 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
8424
8425 /* Only 5701 and later support tagged irq status mode.
8426 * Also, 5788 chips cannot use tagged irq status.
8427 *
8428 * However, since we are using NAPI avoid tagged irq status
8429 * because the interrupt condition is more difficult to
8430 * fully clear in that mode.
8431 */
8432 tp->coalesce_mode = 0;
8433
8434 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
8435 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
8436 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
8437
8438 /* Initialize MAC MI mode, polling disabled. */
8439 tw32_f(MAC_MI_MODE, tp->mi_mode);
8440 udelay(80);
8441
8442 /* Initialize data/descriptor byte/word swapping. */
8443 val = tr32(GRC_MODE);
8444 val &= GRC_MODE_HOST_STACKUP;
8445 tw32(GRC_MODE, val | tp->grc_mode);
8446
8447 tg3_switch_clocks(tp);
8448
8449 /* Clear this out for sanity. */
8450 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8451
8452 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8453 &pci_state_reg);
8454 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
8455 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
8456 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
8457
8458 if (chiprevid == CHIPREV_ID_5701_A0 ||
8459 chiprevid == CHIPREV_ID_5701_B0 ||
8460 chiprevid == CHIPREV_ID_5701_B2 ||
8461 chiprevid == CHIPREV_ID_5701_B5) {
8462 void __iomem *sram_base;
8463
8464 /* Write some dummy words into the SRAM status block
8465 * area, see if it reads back correctly. If the return
8466 * value is bad, force enable the PCIX workaround.
8467 */
8468 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
8469
8470 writel(0x00000000, sram_base);
8471 writel(0x00000000, sram_base + 4);
8472 writel(0xffffffff, sram_base + 4);
8473 if (readl(sram_base) != 0x00000000)
8474 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8475 }
8476 }
8477
8478 udelay(50);
8479 tg3_nvram_init(tp);
8480
8481 grc_misc_cfg = tr32(GRC_MISC_CFG);
8482 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
8483
8484 /* Broadcom's driver says that CIOBE multisplit has a bug */
8485#if 0
8486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8487 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
8488 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
8489 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
8490 }
8491#endif
8492 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8493 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
8494 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
8495 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
8496
8497 /* these are limited to 10/100 only */
8498 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8499 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
8500 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8501 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8502 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
8503 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
8504 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
8505 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8506 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
8507 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
8508 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
8509
8510 err = tg3_phy_probe(tp);
8511 if (err) {
8512 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
8513 pci_name(tp->pdev), err);
8514 /* ... but do not return immediately ... */
8515 }
8516
8517 tg3_read_partno(tp);
8518
8519 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8520 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8521 } else {
8522 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8523 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
8524 else
8525 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8526 }
8527
8528 /* 5700 {AX,BX} chips have a broken status block link
8529 * change bit implementation, so we must use the
8530 * status register in those cases.
8531 */
8532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8533 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
8534 else
8535 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
8536
8537 /* The led_ctrl is set during tg3_phy_probe, here we might
8538 * have to force the link status polling mechanism based
8539 * upon subsystem IDs.
8540 */
8541 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
8542 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8543 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
8544 TG3_FLAG_USE_LINKCHG_REG);
8545 }
8546
8547 /* For all SERDES we poll the MAC status register. */
8548 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8549 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
8550 else
8551 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
8552
8553 /* 5700 BX chips need to have their TX producer index mailboxes
8554 * written twice to workaround a bug.
8555 */
8556 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
8557 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
8558 else
8559 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
8560
8561 /* It seems all chips can get confused if TX buffers
8562 * straddle the 4GB address boundary in some cases.
8563 */
8564 tp->dev->hard_start_xmit = tg3_start_xmit;
8565
8566 tp->rx_offset = 2;
8567 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
8568 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
8569 tp->rx_offset = 0;
8570
8571 /* By default, disable wake-on-lan. User can change this
8572 * using ETHTOOL_SWOL.
8573 */
8574 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8575
8576 return err;
8577}
8578
8579#ifdef CONFIG_SPARC64
8580static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
8581{
8582 struct net_device *dev = tp->dev;
8583 struct pci_dev *pdev = tp->pdev;
8584 struct pcidev_cookie *pcp = pdev->sysdata;
8585
8586 if (pcp != NULL) {
8587 int node = pcp->prom_node;
8588
8589 if (prom_getproplen(node, "local-mac-address") == 6) {
8590 prom_getproperty(node, "local-mac-address",
8591 dev->dev_addr, 6);
8592 return 0;
8593 }
8594 }
8595 return -ENODEV;
8596}
8597
8598static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
8599{
8600 struct net_device *dev = tp->dev;
8601
8602 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
8603 return 0;
8604}
8605#endif
8606
8607static int __devinit tg3_get_device_address(struct tg3 *tp)
8608{
8609 struct net_device *dev = tp->dev;
8610 u32 hi, lo, mac_offset;
8611
8612#ifdef CONFIG_SPARC64
8613 if (!tg3_get_macaddr_sparc(tp))
8614 return 0;
8615#endif
8616
8617 mac_offset = 0x7c;
8618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8619 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
8620 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
8621 mac_offset = 0xcc;
8622 if (tg3_nvram_lock(tp))
8623 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
8624 else
8625 tg3_nvram_unlock(tp);
8626 }
8627
8628 /* First try to get it from MAC address mailbox. */
8629 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
8630 if ((hi >> 16) == 0x484b) {
8631 dev->dev_addr[0] = (hi >> 8) & 0xff;
8632 dev->dev_addr[1] = (hi >> 0) & 0xff;
8633
8634 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
8635 dev->dev_addr[2] = (lo >> 24) & 0xff;
8636 dev->dev_addr[3] = (lo >> 16) & 0xff;
8637 dev->dev_addr[4] = (lo >> 8) & 0xff;
8638 dev->dev_addr[5] = (lo >> 0) & 0xff;
8639 }
8640 /* Next, try NVRAM. */
8641 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
8642 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
8643 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
8644 dev->dev_addr[0] = ((hi >> 16) & 0xff);
8645 dev->dev_addr[1] = ((hi >> 24) & 0xff);
8646 dev->dev_addr[2] = ((lo >> 0) & 0xff);
8647 dev->dev_addr[3] = ((lo >> 8) & 0xff);
8648 dev->dev_addr[4] = ((lo >> 16) & 0xff);
8649 dev->dev_addr[5] = ((lo >> 24) & 0xff);
8650 }
8651 /* Finally just fetch it out of the MAC control regs. */
8652 else {
8653 hi = tr32(MAC_ADDR_0_HIGH);
8654 lo = tr32(MAC_ADDR_0_LOW);
8655
8656 dev->dev_addr[5] = lo & 0xff;
8657 dev->dev_addr[4] = (lo >> 8) & 0xff;
8658 dev->dev_addr[3] = (lo >> 16) & 0xff;
8659 dev->dev_addr[2] = (lo >> 24) & 0xff;
8660 dev->dev_addr[1] = hi & 0xff;
8661 dev->dev_addr[0] = (hi >> 8) & 0xff;
8662 }
8663
8664 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8665#ifdef CONFIG_SPARC64
8666 if (!tg3_get_default_macaddr_sparc(tp))
8667 return 0;
8668#endif
8669 return -EINVAL;
8670 }
8671 return 0;
8672}
8673
8674static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
8675{
8676 struct tg3_internal_buffer_desc test_desc;
8677 u32 sram_dma_descs;
8678 int i, ret;
8679
8680 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
8681
8682 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
8683 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
8684 tw32(RDMAC_STATUS, 0);
8685 tw32(WDMAC_STATUS, 0);
8686
8687 tw32(BUFMGR_MODE, 0);
8688 tw32(FTQ_RESET, 0);
8689
8690 test_desc.addr_hi = ((u64) buf_dma) >> 32;
8691 test_desc.addr_lo = buf_dma & 0xffffffff;
8692 test_desc.nic_mbuf = 0x00002100;
8693 test_desc.len = size;
8694
8695 /*
8696 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
8697 * the *second* time the tg3 driver was getting loaded after an
8698 * initial scan.
8699 *
8700 * Broadcom tells me:
8701 * ...the DMA engine is connected to the GRC block and a DMA
8702 * reset may affect the GRC block in some unpredictable way...
8703 * The behavior of resets to individual blocks has not been tested.
8704 *
8705 * Broadcom noted the GRC reset will also reset all sub-components.
8706 */
8707 if (to_device) {
8708 test_desc.cqid_sqid = (13 << 8) | 2;
8709
8710 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
8711 udelay(40);
8712 } else {
8713 test_desc.cqid_sqid = (16 << 8) | 7;
8714
8715 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
8716 udelay(40);
8717 }
8718 test_desc.flags = 0x00000005;
8719
8720 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
8721 u32 val;
8722
8723 val = *(((u32 *)&test_desc) + i);
8724 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
8725 sram_dma_descs + (i * sizeof(u32)));
8726 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
8727 }
8728 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
8729
8730 if (to_device) {
8731 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
8732 } else {
8733 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
8734 }
8735
8736 ret = -ENODEV;
8737 for (i = 0; i < 40; i++) {
8738 u32 val;
8739
8740 if (to_device)
8741 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
8742 else
8743 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
8744 if ((val & 0xffff) == sram_dma_descs) {
8745 ret = 0;
8746 break;
8747 }
8748
8749 udelay(100);
8750 }
8751
8752 return ret;
8753}
8754
8755#define TEST_BUFFER_SIZE 0x400
8756
8757static int __devinit tg3_test_dma(struct tg3 *tp)
8758{
8759 dma_addr_t buf_dma;
8760 u32 *buf;
8761 int ret;
8762
8763 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
8764 if (!buf) {
8765 ret = -ENOMEM;
8766 goto out_nofree;
8767 }
8768
8769 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
8770 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
8771
8772#ifndef CONFIG_X86
8773 {
8774 u8 byte;
8775 int cacheline_size;
8776 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
8777
8778 if (byte == 0)
8779 cacheline_size = 1024;
8780 else
8781 cacheline_size = (int) byte * 4;
8782
8783 switch (cacheline_size) {
8784 case 16:
8785 case 32:
8786 case 64:
8787 case 128:
8788 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8789 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8790 tp->dma_rwctrl |=
8791 DMA_RWCTRL_WRITE_BNDRY_384_PCIX;
8792 break;
8793 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8794 tp->dma_rwctrl &=
8795 ~(DMA_RWCTRL_PCI_WRITE_CMD);
8796 tp->dma_rwctrl |=
8797 DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
8798 break;
8799 }
8800 /* fallthrough */
8801 case 256:
8802 if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8803 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8804 tp->dma_rwctrl |=
8805 DMA_RWCTRL_WRITE_BNDRY_256;
8806 else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8807 tp->dma_rwctrl |=
8808 DMA_RWCTRL_WRITE_BNDRY_256_PCIX;
8809 };
8810 }
8811#endif
8812
8813 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8814 /* DMA read watermark not used on PCIE */
8815 tp->dma_rwctrl |= 0x00180000;
8816 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 8817 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
8818 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 8819 tp->dma_rwctrl |= 0x003f0000;
8820 else
8821 tp->dma_rwctrl |= 0x003f000f;
8822 } else {
8823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
8824 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8825 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
8826
8827 if (ccval == 0x6 || ccval == 0x7)
8828 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
8829
8830 /* Set bit 23 to renable PCIX hw bug fix */
8831 tp->dma_rwctrl |= 0x009f0000;
8832 } else {
8833 tp->dma_rwctrl |= 0x001b000f;
8834 }
8835 }
8836
8837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
8838 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8839 tp->dma_rwctrl &= 0xfffffff0;
8840
8841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
8843 /* Remove this if it causes problems for some boards. */
8844 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
8845
8846 /* On 5700/5701 chips, we need to set this bit.
8847 * Otherwise the chip will issue cacheline transactions
8848 * to streamable DMA memory with not all the byte
8849 * enables turned on. This is an error on several
8850 * RISC PCI controllers, in particular sparc64.
8851 *
8852 * On 5703/5704 chips, this bit has been reassigned
8853 * a different meaning. In particular, it is used
8854 * on those chips to enable a PCI-X workaround.
8855 */
8856 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
8857 }
8858
8859 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8860
8861#if 0
8862 /* Unneeded, already done by tg3_get_invariants. */
8863 tg3_switch_clocks(tp);
8864#endif
8865
8866 ret = 0;
8867 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8868 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
8869 goto out;
8870
8871 while (1) {
8872 u32 *p = buf, i;
8873
8874 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
8875 p[i] = i;
8876
8877 /* Send the buffer to the chip. */
8878 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
8879 if (ret) {
8880 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
8881 break;
8882 }
8883
8884#if 0
8885 /* validate data reached card RAM correctly. */
8886 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
8887 u32 val;
8888 tg3_read_mem(tp, 0x2100 + (i*4), &val);
8889 if (le32_to_cpu(val) != p[i]) {
8890 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
8891 /* ret = -ENODEV here? */
8892 }
8893 p[i] = 0;
8894 }
8895#endif
8896 /* Now read it back. */
8897 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
8898 if (ret) {
8899 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
8900
8901 break;
8902 }
8903
8904 /* Verify it. */
8905 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
8906 if (p[i] == i)
8907 continue;
8908
8909 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) ==
8910 DMA_RWCTRL_WRITE_BNDRY_DISAB) {
8911 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
8912 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8913 break;
8914 } else {
8915 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
8916 ret = -ENODEV;
8917 goto out;
8918 }
8919 }
8920
8921 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
8922 /* Success. */
8923 ret = 0;
8924 break;
8925 }
8926 }
8927
8928out:
8929 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
8930out_nofree:
8931 return ret;
8932}
8933
8934static void __devinit tg3_init_link_config(struct tg3 *tp)
8935{
8936 tp->link_config.advertising =
8937 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
8938 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
8939 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
8940 ADVERTISED_Autoneg | ADVERTISED_MII);
8941 tp->link_config.speed = SPEED_INVALID;
8942 tp->link_config.duplex = DUPLEX_INVALID;
8943 tp->link_config.autoneg = AUTONEG_ENABLE;
8944 netif_carrier_off(tp->dev);
8945 tp->link_config.active_speed = SPEED_INVALID;
8946 tp->link_config.active_duplex = DUPLEX_INVALID;
8947 tp->link_config.phy_is_low_power = 0;
8948 tp->link_config.orig_speed = SPEED_INVALID;
8949 tp->link_config.orig_duplex = DUPLEX_INVALID;
8950 tp->link_config.orig_autoneg = AUTONEG_INVALID;
8951}
8952
8953static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
8954{
8955 tp->bufmgr_config.mbuf_read_dma_low_water =
8956 DEFAULT_MB_RDMA_LOW_WATER;
8957 tp->bufmgr_config.mbuf_mac_rx_low_water =
8958 DEFAULT_MB_MACRX_LOW_WATER;
8959 tp->bufmgr_config.mbuf_high_water =
8960 DEFAULT_MB_HIGH_WATER;
8961
8962 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
8963 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
8964 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
8965 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
8966 tp->bufmgr_config.mbuf_high_water_jumbo =
8967 DEFAULT_MB_HIGH_WATER_JUMBO;
8968
8969 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
8970 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
8971}
8972
8973static char * __devinit tg3_phy_string(struct tg3 *tp)
8974{
8975 switch (tp->phy_id & PHY_ID_MASK) {
8976 case PHY_ID_BCM5400: return "5400";
8977 case PHY_ID_BCM5401: return "5401";
8978 case PHY_ID_BCM5411: return "5411";
8979 case PHY_ID_BCM5701: return "5701";
8980 case PHY_ID_BCM5703: return "5703";
8981 case PHY_ID_BCM5704: return "5704";
8982 case PHY_ID_BCM5705: return "5705";
8983 case PHY_ID_BCM5750: return "5750";
85e94ced 8984 case PHY_ID_BCM5752: return "5752";
1da177e4
LT		 8985 case PHY_ID_BCM8002: return "8002/serdes";
8986 case 0: return "serdes";
8987 default: return "unknown";
8988 };
8989}
8990
8991static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
8992{
8993 struct pci_dev *peer;
8994 unsigned int func, devnr = tp->pdev->devfn & ~7;
8995
8996 for (func = 0; func < 8; func++) {
8997 peer = pci_get_slot(tp->pdev->bus, devnr | func);
8998 if (peer && peer != tp->pdev)
8999 break;
9000 pci_dev_put(peer);
9001 }
9002 if (!peer || peer == tp->pdev)
9003 BUG();
9004
9005 /*
9006 * We don't need to keep the refcount elevated; there's no way
9007 * to remove one half of this device without removing the other
9008 */
9009 pci_dev_put(peer);
9010
9011 return peer;
9012}
9013
9014static int __devinit tg3_init_one(struct pci_dev *pdev,
9015 const struct pci_device_id *ent)
9016{
9017 static int tg3_version_printed = 0;
9018 unsigned long tg3reg_base, tg3reg_len;
9019 struct net_device *dev;
9020 struct tg3 *tp;
9021 int i, err, pci_using_dac, pm_cap;
9022
9023 if (tg3_version_printed++ == 0)
9024 printk(KERN_INFO "%s", version);
9025
9026 err = pci_enable_device(pdev);
9027 if (err) {
9028 printk(KERN_ERR PFX "Cannot enable PCI device, "
9029 "aborting.\n");
9030 return err;
9031 }
9032
9033 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9034 printk(KERN_ERR PFX "Cannot find proper PCI device "
9035 "base address, aborting.\n");
9036 err = -ENODEV;
9037 goto err_out_disable_pdev;
9038 }
9039
9040 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9041 if (err) {
9042 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
9043 "aborting.\n");
9044 goto err_out_disable_pdev;
9045 }
9046
9047 pci_set_master(pdev);
9048
9049 /* Find power-management capability. */
9050 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9051 if (pm_cap == 0) {
9052 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
9053 "aborting.\n");
9054 err = -EIO;
9055 goto err_out_free_res;
9056 }
9057
9058 /* Configure DMA attributes. */
9059 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
9060 if (!err) {
9061 pci_using_dac = 1;
9062 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
9063 if (err < 0) {
9064 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
9065 "for consistent allocations\n");
9066 goto err_out_free_res;
9067 }
9068 } else {
9069 err = pci_set_dma_mask(pdev, 0xffffffffULL);
9070 if (err) {
9071 printk(KERN_ERR PFX "No usable DMA configuration, "
9072 "aborting.\n");
9073 goto err_out_free_res;
9074 }
9075 pci_using_dac = 0;
9076 }
9077
9078 tg3reg_base = pci_resource_start(pdev, 0);
9079 tg3reg_len = pci_resource_len(pdev, 0);
9080
9081 dev = alloc_etherdev(sizeof(*tp));
9082 if (!dev) {
9083 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
9084 err = -ENOMEM;
9085 goto err_out_free_res;
9086 }
9087
9088 SET_MODULE_OWNER(dev);
9089 SET_NETDEV_DEV(dev, &pdev->dev);
9090
9091 if (pci_using_dac)
9092 dev->features |= NETIF_F_HIGHDMA;
9093 dev->features |= NETIF_F_LLTX;
9094#if TG3_VLAN_TAG_USED
9095 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
9096 dev->vlan_rx_register = tg3_vlan_rx_register;
9097 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
9098#endif
9099
9100 tp = netdev_priv(dev);
9101 tp->pdev = pdev;
9102 tp->dev = dev;
9103 tp->pm_cap = pm_cap;
9104 tp->mac_mode = TG3_DEF_MAC_MODE;
9105 tp->rx_mode = TG3_DEF_RX_MODE;
9106 tp->tx_mode = TG3_DEF_TX_MODE;
9107 tp->mi_mode = MAC_MI_MODE_BASE;
9108 if (tg3_debug > 0)
9109 tp->msg_enable = tg3_debug;
9110 else
9111 tp->msg_enable = TG3_DEF_MSG_ENABLE;
9112
9113 /* The word/byte swap controls here control register access byte
9114 * swapping. DMA data byte swapping is controlled in the GRC_MODE
9115 * setting below.
9116 */
9117 tp->misc_host_ctrl =
9118 MISC_HOST_CTRL_MASK_PCI_INT |
9119 MISC_HOST_CTRL_WORD_SWAP |
9120 MISC_HOST_CTRL_INDIR_ACCESS |
9121 MISC_HOST_CTRL_PCISTATE_RW;
9122
9123 /* The NONFRM (non-frame) byte/word swap controls take effect
9124 * on descriptor entries, anything which isn't packet data.
9125 *
9126 * The StrongARM chips on the board (one for tx, one for rx)
9127 * are running in big-endian mode.
9128 */
9129 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
9130 GRC_MODE_WSWAP_NONFRM_DATA);
9131#ifdef __BIG_ENDIAN
9132 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
9133#endif
9134 spin_lock_init(&tp->lock);
9135 spin_lock_init(&tp->tx_lock);
9136 spin_lock_init(&tp->indirect_lock);
9137 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
9138
9139 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
9140 if (tp->regs == 0UL) {
9141 printk(KERN_ERR PFX "Cannot map device registers, "
9142 "aborting.\n");
9143 err = -ENOMEM;
9144 goto err_out_free_dev;
9145 }
9146
9147 tg3_init_link_config(tp);
9148
9149 tg3_init_bufmgr_config(tp);
9150
9151 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
9152 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
9153 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
9154
9155 dev->open = tg3_open;
9156 dev->stop = tg3_close;
9157 dev->get_stats = tg3_get_stats;
9158 dev->set_multicast_list = tg3_set_rx_mode;
9159 dev->set_mac_address = tg3_set_mac_addr;
9160 dev->do_ioctl = tg3_ioctl;
9161 dev->tx_timeout = tg3_tx_timeout;
9162 dev->poll = tg3_poll;
9163 dev->ethtool_ops = &tg3_ethtool_ops;
9164 dev->weight = 64;
9165 dev->watchdog_timeo = TG3_TX_TIMEOUT;
9166 dev->change_mtu = tg3_change_mtu;
9167 dev->irq = pdev->irq;
9168#ifdef CONFIG_NET_POLL_CONTROLLER
9169 dev->poll_controller = tg3_poll_controller;
9170#endif
9171
9172 err = tg3_get_invariants(tp);
9173 if (err) {
9174 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
9175 "aborting.\n");
9176 goto err_out_iounmap;
9177 }
9178
9179 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9180 tp->bufmgr_config.mbuf_read_dma_low_water =
9181 DEFAULT_MB_RDMA_LOW_WATER_5705;
9182 tp->bufmgr_config.mbuf_mac_rx_low_water =
9183 DEFAULT_MB_MACRX_LOW_WATER_5705;
9184 tp->bufmgr_config.mbuf_high_water =
9185 DEFAULT_MB_HIGH_WATER_5705;
9186 }
9187
9188#if TG3_TSO_SUPPORT != 0
9189 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
9190 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9191 }
9192 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9193 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9194 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
9195 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
9196 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9197 } else {
9198 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9199 }
9200
9201 /* TSO is off by default, user can enable using ethtool. */
9202#if 0
9203 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
9204 dev->features |= NETIF_F_TSO;
9205#endif
9206
9207#endif
9208
9209 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
9210 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
9211 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
9212 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
9213 tp->rx_pending = 63;
9214 }
9215
9216 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9217 tp->pdev_peer = tg3_find_5704_peer(tp);
9218
9219 err = tg3_get_device_address(tp);
9220 if (err) {
9221 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
9222 "aborting.\n");
9223 goto err_out_iounmap;
9224 }
9225
9226 /*
9227 * Reset chip in case UNDI or EFI driver did not shutdown
9228 * DMA self test will enable WDMAC and we'll see (spurious)
9229 * pending DMA on the PCI bus at that point.
9230 */
9231 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
9232 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9233 pci_save_state(tp->pdev);
9234 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
9235 tg3_halt(tp);
9236 }
9237
9238 err = tg3_test_dma(tp);
9239 if (err) {
9240 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
9241 goto err_out_iounmap;
9242 }
9243
9244 /* Tigon3 can do ipv4 only... and some chips have buggy
9245 * checksumming.
9246 */
9247 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
9248 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
9249 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9250 } else
9251 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9252
9253 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
9254 dev->features &= ~NETIF_F_HIGHDMA;
9255
9256 /* flow control autonegotiation is default behavior */
9257 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9258
9259 err = register_netdev(dev);
9260 if (err) {
9261 printk(KERN_ERR PFX "Cannot register net device, "
9262 "aborting.\n");
9263 goto err_out_iounmap;
9264 }
9265
9266 pci_set_drvdata(pdev, dev);
9267
9268 /* Now that we have fully setup the chip, save away a snapshot
9269 * of the PCI config space. We need to restore this after
9270 * GRC_MISC_CFG core clock resets and some resume events.
9271 */
9272 pci_save_state(tp->pdev);
9273
9274 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
9275 dev->name,
9276 tp->board_part_number,
9277 tp->pci_chip_rev_id,
9278 tg3_phy_string(tp),
9279 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
9280 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
9281 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
9282 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
9283 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
9284 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
9285
9286 for (i = 0; i < 6; i++)
9287 printk("%2.2x%c", dev->dev_addr[i],
9288 i == 5 ? '\n' : ':');
9289
9290 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
9291 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
9292 "TSOcap[%d] \n",
9293 dev->name,
9294 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
9295 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
9296 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
9297 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
9298 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
9299 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
9300 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
9301
9302 return 0;
9303
9304err_out_iounmap:
9305 iounmap(tp->regs);
9306
9307err_out_free_dev:
9308 free_netdev(dev);
9309
9310err_out_free_res:
9311 pci_release_regions(pdev);
9312
9313err_out_disable_pdev:
9314 pci_disable_device(pdev);
9315 pci_set_drvdata(pdev, NULL);
9316 return err;
9317}
9318
9319static void __devexit tg3_remove_one(struct pci_dev *pdev)
9320{
9321 struct net_device *dev = pci_get_drvdata(pdev);
9322
9323 if (dev) {
9324 struct tg3 *tp = netdev_priv(dev);
9325
9326 unregister_netdev(dev);
9327 iounmap(tp->regs);
9328 free_netdev(dev);
9329 pci_release_regions(pdev);
9330 pci_disable_device(pdev);
9331 pci_set_drvdata(pdev, NULL);
9332 }
9333}
9334
9335static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
9336{
9337 struct net_device *dev = pci_get_drvdata(pdev);
9338 struct tg3 *tp = netdev_priv(dev);
9339 int err;
9340
9341 if (!netif_running(dev))
9342 return 0;
9343
9344 tg3_netif_stop(tp);
9345
9346 del_timer_sync(&tp->timer);
9347
9348 spin_lock_irq(&tp->lock);
9349 spin_lock(&tp->tx_lock);
9350 tg3_disable_ints(tp);
9351 spin_unlock(&tp->tx_lock);
9352 spin_unlock_irq(&tp->lock);
9353
9354 netif_device_detach(dev);
9355
9356 spin_lock_irq(&tp->lock);
9357 spin_lock(&tp->tx_lock);
9358 tg3_halt(tp);
9359 spin_unlock(&tp->tx_lock);
9360 spin_unlock_irq(&tp->lock);
9361
9362 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
9363 if (err) {
9364 spin_lock_irq(&tp->lock);
9365 spin_lock(&tp->tx_lock);
9366
9367 tg3_init_hw(tp);
9368
9369 tp->timer.expires = jiffies + tp->timer_offset;
9370 add_timer(&tp->timer);
9371
9372 netif_device_attach(dev);
9373 tg3_netif_start(tp);
9374
9375 spin_unlock(&tp->tx_lock);
9376 spin_unlock_irq(&tp->lock);
9377 }
9378
9379 return err;
9380}
9381
9382static int tg3_resume(struct pci_dev *pdev)
9383{
9384 struct net_device *dev = pci_get_drvdata(pdev);
9385 struct tg3 *tp = netdev_priv(dev);
9386 int err;
9387
9388 if (!netif_running(dev))
9389 return 0;
9390
9391 pci_restore_state(tp->pdev);
9392
9393 err = tg3_set_power_state(tp, 0);
9394 if (err)
9395 return err;
9396
9397 netif_device_attach(dev);
9398
9399 spin_lock_irq(&tp->lock);
9400 spin_lock(&tp->tx_lock);
9401
9402 tg3_init_hw(tp);
9403
9404 tp->timer.expires = jiffies + tp->timer_offset;
9405 add_timer(&tp->timer);
9406
9407 tg3_enable_ints(tp);
9408
9409 tg3_netif_start(tp);
9410
9411 spin_unlock(&tp->tx_lock);
9412 spin_unlock_irq(&tp->lock);
9413
9414 return 0;
9415}
9416
9417static struct pci_driver tg3_driver = {
9418 .name = DRV_MODULE_NAME,
9419 .id_table = tg3_pci_tbl,
9420 .probe = tg3_init_one,
9421 .remove = __devexit_p(tg3_remove_one),
9422 .suspend = tg3_suspend,
9423 .resume = tg3_resume
9424};
9425
9426static int __init tg3_init(void)
9427{
9428 return pci_module_init(&tg3_driver);
9429}
9430
9431static void __exit tg3_cleanup(void)
9432{
9433 pci_unregister_driver(&tg3_driver);
9434}
9435
9436module_init(tg3_init);
9437module_exit(tg3_cleanup);
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