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[PATCH] Fix more radeon GART start calculation cases
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
18#include <linux/config.h>
19
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
43
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/byteorder.h>
47#include <asm/uaccess.h>
48
49#ifdef CONFIG_SPARC64
50#include <asm/idprom.h>
51#include <asm/oplib.h>
52#include <asm/pbm.h>
53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
61#ifdef NETIF_F_TSO
62#define TG3_TSO_SUPPORT 1
63#else
64#define TG3_TSO_SUPPORT 0
65#endif
66
67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
38690194
MC		 71#define DRV_MODULE_VERSION "3.46"
72#define DRV_MODULE_RELDATE "Dec 19, 2005"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
0f893dc6 95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4 126#define TX_BUFFS_AVAIL(TP) \
51b91468
MC		 127 ((TP)->tx_pending - \
128 (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
1da177e4
LT		 129#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130
131#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
132#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
133
134/* minimum number of free TX descriptors required to wake up TX process */
135#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
136
137/* number of ETHTOOL_GSTATS u64's */
138#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
139
4cafd3f5
MC		 140#define TG3_NUM_TEST 6
141
1da177e4
LT		 142static char version[] __devinitdata =
143 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
144
145MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
146MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
147MODULE_LICENSE("GPL");
148MODULE_VERSION(DRV_MODULE_VERSION);
149
150static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
151module_param(tg3_debug, int, 0);
152MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
153
154static struct pci_device_id tg3_pci_tbl[] = {
155 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
207 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
209 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
6e9017a7 213 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
af2bcd97 214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
d8659255
XVP		 215 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 217 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
219 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
221 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
a4e2b347
MC		 223 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
4cf78e4f
MC		 227 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
229 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 231 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
233 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
235 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
237 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
241 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
243 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
245 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
247 { 0, }
248};
249
250MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
251
252static struct {
253 const char string[ETH_GSTRING_LEN];
254} ethtool_stats_keys[TG3_NUM_STATS] = {
255 { "rx_octets" },
256 { "rx_fragments" },
257 { "rx_ucast_packets" },
258 { "rx_mcast_packets" },
259 { "rx_bcast_packets" },
260 { "rx_fcs_errors" },
261 { "rx_align_errors" },
262 { "rx_xon_pause_rcvd" },
263 { "rx_xoff_pause_rcvd" },
264 { "rx_mac_ctrl_rcvd" },
265 { "rx_xoff_entered" },
266 { "rx_frame_too_long_errors" },
267 { "rx_jabbers" },
268 { "rx_undersize_packets" },
269 { "rx_in_length_errors" },
270 { "rx_out_length_errors" },
271 { "rx_64_or_less_octet_packets" },
272 { "rx_65_to_127_octet_packets" },
273 { "rx_128_to_255_octet_packets" },
274 { "rx_256_to_511_octet_packets" },
275 { "rx_512_to_1023_octet_packets" },
276 { "rx_1024_to_1522_octet_packets" },
277 { "rx_1523_to_2047_octet_packets" },
278 { "rx_2048_to_4095_octet_packets" },
279 { "rx_4096_to_8191_octet_packets" },
280 { "rx_8192_to_9022_octet_packets" },
281
282 { "tx_octets" },
283 { "tx_collisions" },
284
285 { "tx_xon_sent" },
286 { "tx_xoff_sent" },
287 { "tx_flow_control" },
288 { "tx_mac_errors" },
289 { "tx_single_collisions" },
290 { "tx_mult_collisions" },
291 { "tx_deferred" },
292 { "tx_excessive_collisions" },
293 { "tx_late_collisions" },
294 { "tx_collide_2times" },
295 { "tx_collide_3times" },
296 { "tx_collide_4times" },
297 { "tx_collide_5times" },
298 { "tx_collide_6times" },
299 { "tx_collide_7times" },
300 { "tx_collide_8times" },
301 { "tx_collide_9times" },
302 { "tx_collide_10times" },
303 { "tx_collide_11times" },
304 { "tx_collide_12times" },
305 { "tx_collide_13times" },
306 { "tx_collide_14times" },
307 { "tx_collide_15times" },
308 { "tx_ucast_packets" },
309 { "tx_mcast_packets" },
310 { "tx_bcast_packets" },
311 { "tx_carrier_sense_errors" },
312 { "tx_discards" },
313 { "tx_errors" },
314
315 { "dma_writeq_full" },
316 { "dma_write_prioq_full" },
317 { "rxbds_empty" },
318 { "rx_discards" },
319 { "rx_errors" },
320 { "rx_threshold_hit" },
321
322 { "dma_readq_full" },
323 { "dma_read_prioq_full" },
324 { "tx_comp_queue_full" },
325
326 { "ring_set_send_prod_index" },
327 { "ring_status_update" },
328 { "nic_irqs" },
329 { "nic_avoided_irqs" },
330 { "nic_tx_threshold_hit" }
331};
332
4cafd3f5
MC		 333static struct {
334 const char string[ETH_GSTRING_LEN];
335} ethtool_test_keys[TG3_NUM_TEST] = {
336 { "nvram test (online) " },
337 { "link test (online) " },
338 { "register test (offline)" },
339 { "memory test (offline)" },
340 { "loopback test (offline)" },
341 { "interrupt test (offline)" },
342};
343
b401e9e2
MC		 344static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
345{
346 writel(val, tp->regs + off);
347}
348
349static u32 tg3_read32(struct tg3 *tp, u32 off)
350{
351 return (readl(tp->regs + off));
352}
353
1da177e4
LT		 354static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
355{
6892914f
MC		 356 unsigned long flags;
357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 362}
363
364static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
365{
366 writel(val, tp->regs + off);
367 readl(tp->regs + off);
1da177e4
LT		 368}
369
6892914f 370static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 371{
6892914f
MC		 372 unsigned long flags;
373 u32 val;
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
379 return val;
380}
381
382static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
383{
384 unsigned long flags;
385
386 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
387 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
388 TG3_64BIT_REG_LOW, val);
389 return;
390 }
391 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
393 TG3_64BIT_REG_LOW, val);
394 return;
1da177e4 395 }
6892914f
MC		 396
397 spin_lock_irqsave(&tp->indirect_lock, flags);
398 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
400 spin_unlock_irqrestore(&tp->indirect_lock, flags);
401
402 /* In indirect mode when disabling interrupts, we also need
403 * to clear the interrupt bit in the GRC local ctrl register.
404 */
405 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
406 (val == 0x1)) {
407 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
408 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
409 }
410}
411
412static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
413{
414 unsigned long flags;
415 u32 val;
416
417 spin_lock_irqsave(&tp->indirect_lock, flags);
418 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
419 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
420 spin_unlock_irqrestore(&tp->indirect_lock, flags);
421 return val;
422}
423
b401e9e2
MC		 424/* usec_wait specifies the wait time in usec when writing to certain registers
425 * where it is unsafe to read back the register without some delay.
426 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
427 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
428 */
429static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 430{
b401e9e2
MC		 431 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
432 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
433 /* Non-posted methods */
434 tp->write32(tp, off, val);
435 else {
436 /* Posted method */
437 tg3_write32(tp, off, val);
438 if (usec_wait)
439 udelay(usec_wait);
440 tp->read32(tp, off);
441 }
442 /* Wait again after the read for the posted method to guarantee that
443 * the wait time is met.
444 */
445 if (usec_wait)
446 udelay(usec_wait);
1da177e4
LT		 447}
448
09ee929c
MC		 449static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
450{
451 tp->write32_mbox(tp, off, val);
6892914f
MC		 452 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
453 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
454 tp->read32_mbox(tp, off);
09ee929c
MC		 455}
456
20094930 457static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 458{
459 void __iomem *mbox = tp->regs + off;
460 writel(val, mbox);
461 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
462 writel(val, mbox);
463 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
464 readl(mbox);
465}
466
20094930 467#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 468#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 469#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
470#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 471#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 472
473#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 474#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
475#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 476#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 477
478static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
479{
6892914f
MC		 480 unsigned long flags;
481
482 spin_lock_irqsave(&tp->indirect_lock, flags);
1da177e4
LT		 483 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
484 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
485
486 /* Always leave this as zero. */
487 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
6892914f 488 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 489}
490
28fbef78
MC		 491static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
492{
493 /* If no workaround is needed, write to mem space directly */
494 if (tp->write32 != tg3_write_indirect_reg32)
495 tw32(NIC_SRAM_WIN_BASE + off, val);
496 else
497 tg3_write_mem(tp, off, val);
498}
499
1da177e4
LT		 500static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
501{
6892914f
MC		 502 unsigned long flags;
503
504 spin_lock_irqsave(&tp->indirect_lock, flags);
1da177e4
LT		 505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
506 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
507
508 /* Always leave this as zero. */
509 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
6892914f 510 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 511}
512
513static void tg3_disable_ints(struct tg3 *tp)
514{
515 tw32(TG3PCI_MISC_HOST_CTRL,
516 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 517 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 518}
519
520static inline void tg3_cond_int(struct tg3 *tp)
521{
38f3843e
MC		 522 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
523 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4
LT		 524 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
525}
526
527static void tg3_enable_ints(struct tg3 *tp)
528{
bbe832c0
MC		 529 tp->irq_sync = 0;
530 wmb();
531
1da177e4
LT		 532 tw32(TG3PCI_MISC_HOST_CTRL,
533 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 534 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
535 (tp->last_tag << 24));
1da177e4
LT		 536 tg3_cond_int(tp);
537}
538
04237ddd
MC		 539static inline unsigned int tg3_has_work(struct tg3 *tp)
540{
541 struct tg3_hw_status *sblk = tp->hw_status;
542 unsigned int work_exists = 0;
543
544 /* check for phy events */
545 if (!(tp->tg3_flags &
546 (TG3_FLAG_USE_LINKCHG_REG |
547 TG3_FLAG_POLL_SERDES))) {
548 if (sblk->status & SD_STATUS_LINK_CHG)
549 work_exists = 1;
550 }
551 /* check for RX/TX work to do */
552 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
553 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
554 work_exists = 1;
555
556 return work_exists;
557}
558
1da177e4 559/* tg3_restart_ints
04237ddd
MC		 560 * similar to tg3_enable_ints, but it accurately determines whether there
561 * is new work pending and can return without flushing the PIO write
562 * which reenables interrupts
1da177e4
LT		 563 */
564static void tg3_restart_ints(struct tg3 *tp)
565{
fac9b83e
DM		 566 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
567 tp->last_tag << 24);
1da177e4
LT		 568 mmiowb();
569
fac9b83e
DM		 570 /* When doing tagged status, this work check is unnecessary.
571 * The last_tag we write above tells the chip which piece of
572 * work we've completed.
573 */
574 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
575 tg3_has_work(tp))
04237ddd
MC		 576 tw32(HOSTCC_MODE, tp->coalesce_mode |
577 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 578}
579
580static inline void tg3_netif_stop(struct tg3 *tp)
581{
bbe832c0 582 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 583 netif_poll_disable(tp->dev);
584 netif_tx_disable(tp->dev);
585}
586
587static inline void tg3_netif_start(struct tg3 *tp)
588{
589 netif_wake_queue(tp->dev);
590 /* NOTE: unconditional netif_wake_queue is only appropriate
591 * so long as all callers are assured to have free tx slots
592 * (such as after tg3_init_hw)
593 */
594 netif_poll_enable(tp->dev);
f47c11ee
DM		 595 tp->hw_status->status |= SD_STATUS_UPDATED;
596 tg3_enable_ints(tp);
1da177e4
LT		 597}
598
599static void tg3_switch_clocks(struct tg3 *tp)
600{
601 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
602 u32 orig_clock_ctrl;
603
a4e2b347 604 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f
MC		 605 return;
606
1da177e4
LT		 607 orig_clock_ctrl = clock_ctrl;
608 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
609 CLOCK_CTRL_CLKRUN_OENABLE |
610 0x1f);
611 tp->pci_clock_ctrl = clock_ctrl;
612
613 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
614 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 615 tw32_wait_f(TG3PCI_CLOCK_CTRL,
616 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 617 }
618 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 619 tw32_wait_f(TG3PCI_CLOCK_CTRL,
620 clock_ctrl |
621 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
622 40);
623 tw32_wait_f(TG3PCI_CLOCK_CTRL,
624 clock_ctrl | (CLOCK_CTRL_ALTCLK),
625 40);
1da177e4 626 }
b401e9e2 627 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 628}
629
630#define PHY_BUSY_LOOPS 5000
631
632static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
633{
634 u32 frame_val;
635 unsigned int loops;
636 int ret;
637
638 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
639 tw32_f(MAC_MI_MODE,
640 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
641 udelay(80);
642 }
643
644 *val = 0x0;
645
646 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
647 MI_COM_PHY_ADDR_MASK);
648 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
649 MI_COM_REG_ADDR_MASK);
650 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
651
652 tw32_f(MAC_MI_COM, frame_val);
653
654 loops = PHY_BUSY_LOOPS;
655 while (loops != 0) {
656 udelay(10);
657 frame_val = tr32(MAC_MI_COM);
658
659 if ((frame_val & MI_COM_BUSY) == 0) {
660 udelay(5);
661 frame_val = tr32(MAC_MI_COM);
662 break;
663 }
664 loops -= 1;
665 }
666
667 ret = -EBUSY;
668 if (loops != 0) {
669 *val = frame_val & MI_COM_DATA_MASK;
670 ret = 0;
671 }
672
673 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
674 tw32_f(MAC_MI_MODE, tp->mi_mode);
675 udelay(80);
676 }
677
678 return ret;
679}
680
681static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
682{
683 u32 frame_val;
684 unsigned int loops;
685 int ret;
686
687 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
688 tw32_f(MAC_MI_MODE,
689 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
690 udelay(80);
691 }
692
693 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
694 MI_COM_PHY_ADDR_MASK);
695 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
696 MI_COM_REG_ADDR_MASK);
697 frame_val |= (val & MI_COM_DATA_MASK);
698 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
699
700 tw32_f(MAC_MI_COM, frame_val);
701
702 loops = PHY_BUSY_LOOPS;
703 while (loops != 0) {
704 udelay(10);
705 frame_val = tr32(MAC_MI_COM);
706 if ((frame_val & MI_COM_BUSY) == 0) {
707 udelay(5);
708 frame_val = tr32(MAC_MI_COM);
709 break;
710 }
711 loops -= 1;
712 }
713
714 ret = -EBUSY;
715 if (loops != 0)
716 ret = 0;
717
718 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
719 tw32_f(MAC_MI_MODE, tp->mi_mode);
720 udelay(80);
721 }
722
723 return ret;
724}
725
726static void tg3_phy_set_wirespeed(struct tg3 *tp)
727{
728 u32 val;
729
730 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
731 return;
732
733 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
734 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
735 tg3_writephy(tp, MII_TG3_AUX_CTRL,
736 (val | (1 << 15) | (1 << 4)));
737}
738
739static int tg3_bmcr_reset(struct tg3 *tp)
740{
741 u32 phy_control;
742 int limit, err;
743
744 /* OK, reset it, and poll the BMCR_RESET bit until it
745 * clears or we time out.
746 */
747 phy_control = BMCR_RESET;
748 err = tg3_writephy(tp, MII_BMCR, phy_control);
749 if (err != 0)
750 return -EBUSY;
751
752 limit = 5000;
753 while (limit--) {
754 err = tg3_readphy(tp, MII_BMCR, &phy_control);
755 if (err != 0)
756 return -EBUSY;
757
758 if ((phy_control & BMCR_RESET) == 0) {
759 udelay(40);
760 break;
761 }
762 udelay(10);
763 }
764 if (limit <= 0)
765 return -EBUSY;
766
767 return 0;
768}
769
770static int tg3_wait_macro_done(struct tg3 *tp)
771{
772 int limit = 100;
773
774 while (limit--) {
775 u32 tmp32;
776
777 if (!tg3_readphy(tp, 0x16, &tmp32)) {
778 if ((tmp32 & 0x1000) == 0)
779 break;
780 }
781 }
782 if (limit <= 0)
783 return -EBUSY;
784
785 return 0;
786}
787
788static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
789{
790 static const u32 test_pat[4][6] = {
791 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
792 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
793 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
794 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
795 };
796 int chan;
797
798 for (chan = 0; chan < 4; chan++) {
799 int i;
800
801 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
802 (chan * 0x2000) | 0x0200);
803 tg3_writephy(tp, 0x16, 0x0002);
804
805 for (i = 0; i < 6; i++)
806 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
807 test_pat[chan][i]);
808
809 tg3_writephy(tp, 0x16, 0x0202);
810 if (tg3_wait_macro_done(tp)) {
811 *resetp = 1;
812 return -EBUSY;
813 }
814
815 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
816 (chan * 0x2000) | 0x0200);
817 tg3_writephy(tp, 0x16, 0x0082);
818 if (tg3_wait_macro_done(tp)) {
819 *resetp = 1;
820 return -EBUSY;
821 }
822
823 tg3_writephy(tp, 0x16, 0x0802);
824 if (tg3_wait_macro_done(tp)) {
825 *resetp = 1;
826 return -EBUSY;
827 }
828
829 for (i = 0; i < 6; i += 2) {
830 u32 low, high;
831
832 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
833 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
834 tg3_wait_macro_done(tp)) {
835 *resetp = 1;
836 return -EBUSY;
837 }
838 low &= 0x7fff;
839 high &= 0x000f;
840 if (low != test_pat[chan][i] ||
841 high != test_pat[chan][i+1]) {
842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
845
846 return -EBUSY;
847 }
848 }
849 }
850
851 return 0;
852}
853
854static int tg3_phy_reset_chanpat(struct tg3 *tp)
855{
856 int chan;
857
858 for (chan = 0; chan < 4; chan++) {
859 int i;
860
861 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
862 (chan * 0x2000) | 0x0200);
863 tg3_writephy(tp, 0x16, 0x0002);
864 for (i = 0; i < 6; i++)
865 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
866 tg3_writephy(tp, 0x16, 0x0202);
867 if (tg3_wait_macro_done(tp))
868 return -EBUSY;
869 }
870
871 return 0;
872}
873
874static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
875{
876 u32 reg32, phy9_orig;
877 int retries, do_phy_reset, err;
878
879 retries = 10;
880 do_phy_reset = 1;
881 do {
882 if (do_phy_reset) {
883 err = tg3_bmcr_reset(tp);
884 if (err)
885 return err;
886 do_phy_reset = 0;
887 }
888
889 /* Disable transmitter and interrupt. */
890 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
891 continue;
892
893 reg32 |= 0x3000;
894 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
895
896 /* Set full-duplex, 1000 mbps. */
897 tg3_writephy(tp, MII_BMCR,
898 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
899
900 /* Set to master mode. */
901 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
902 continue;
903
904 tg3_writephy(tp, MII_TG3_CTRL,
905 (MII_TG3_CTRL_AS_MASTER |
906 MII_TG3_CTRL_ENABLE_AS_MASTER));
907
908 /* Enable SM_DSP_CLOCK and 6dB. */
909 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
910
911 /* Block the PHY control access. */
912 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
913 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
914
915 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
916 if (!err)
917 break;
918 } while (--retries);
919
920 err = tg3_phy_reset_chanpat(tp);
921 if (err)
922 return err;
923
924 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
926
927 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
928 tg3_writephy(tp, 0x16, 0x0000);
929
930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
932 /* Set Extended packet length bit for jumbo frames */
933 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
934 }
935 else {
936 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
937 }
938
939 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
940
941 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
942 reg32 &= ~0x3000;
943 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
944 } else if (!err)
945 err = -EBUSY;
946
947 return err;
948}
949
950/* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
952 */
953static int tg3_phy_reset(struct tg3 *tp)
954{
955 u32 phy_status;
956 int err;
957
958 err = tg3_readphy(tp, MII_BMSR, &phy_status);
959 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
960 if (err != 0)
961 return -EBUSY;
962
963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
966 err = tg3_phy_reset_5703_4_5(tp);
967 if (err)
968 return err;
969 goto out;
970 }
971
972 err = tg3_bmcr_reset(tp);
973 if (err)
974 return err;
975
976out:
977 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
978 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
979 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
980 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
984 }
985 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
986 tg3_writephy(tp, 0x1c, 0x8d68);
987 tg3_writephy(tp, 0x1c, 0x8d68);
988 }
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
995 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
996 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
997 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
998 }
999 /* Set Extended packet length bit (bit 14) on all chips that */
1000 /* support jumbo frames */
1001 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1002 /* Cannot do read-modify-write on 5401 */
1003 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1004 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1005 u32 phy_reg;
1006
1007 /* Set bit 14 with read-modify-write to preserve other bits */
1008 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1009 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1010 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1011 }
1012
1013 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1014 * jumbo frames transmission.
1015 */
0f893dc6 1016 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1017 u32 phy_reg;
1018
1019 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1020 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1021 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1022 }
1023
1024 tg3_phy_set_wirespeed(tp);
1025 return 0;
1026}
1027
1028static void tg3_frob_aux_power(struct tg3 *tp)
1029{
1030 struct tg3 *tp_peer = tp;
1031
1032 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1033 return;
1034
8c2dc7e1
MC		 1035 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1036 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1037 struct net_device *dev_peer;
1038
1039 dev_peer = pci_get_drvdata(tp->pdev_peer);
1040 if (!dev_peer)
1da177e4 1041 BUG();
8c2dc7e1 1042 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1043 }
1044
1da177e4 1045 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1046 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1047 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1048 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1051 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1052 (GRC_LCLCTRL_GPIO_OE0 |
1053 GRC_LCLCTRL_GPIO_OE1 |
1054 GRC_LCLCTRL_GPIO_OE2 |
1055 GRC_LCLCTRL_GPIO_OUTPUT0 |
1056 GRC_LCLCTRL_GPIO_OUTPUT1),
1057 100);
1da177e4
LT		 1058 } else {
1059 u32 no_gpio2;
dc56b7d4 1060 u32 grc_local_ctrl = 0;
1da177e4
LT		 1061
1062 if (tp_peer != tp &&
1063 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1064 return;
1065
dc56b7d4
MC		 1066 /* Workaround to prevent overdrawing Amps. */
1067 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1068 ASIC_REV_5714) {
1069 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1070 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1071 grc_local_ctrl, 100);
dc56b7d4
MC		 1072 }
1073
1da177e4
LT		 1074 /* On 5753 and variants, GPIO2 cannot be used. */
1075 no_gpio2 = tp->nic_sram_data_cfg &
1076 NIC_SRAM_DATA_CFG_NO_GPIO2;
1077
dc56b7d4 1078 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1079 GRC_LCLCTRL_GPIO_OE1 |
1080 GRC_LCLCTRL_GPIO_OE2 |
1081 GRC_LCLCTRL_GPIO_OUTPUT1 |
1082 GRC_LCLCTRL_GPIO_OUTPUT2;
1083 if (no_gpio2) {
1084 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1085 GRC_LCLCTRL_GPIO_OUTPUT2);
1086 }
b401e9e2
MC		 1087 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1088 grc_local_ctrl, 100);
1da177e4
LT		 1089
1090 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1091
b401e9e2
MC		 1092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1093 grc_local_ctrl, 100);
1da177e4
LT		 1094
1095 if (!no_gpio2) {
1096 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1098 grc_local_ctrl, 100);
1da177e4
LT		 1099 }
1100 }
1101 } else {
1102 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1103 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1104 if (tp_peer != tp &&
1105 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1106 return;
1107
b401e9e2
MC		 1108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1109 (GRC_LCLCTRL_GPIO_OE1 |
1110 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1111
b401e9e2
MC		 1112 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1113 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1114
b401e9e2
MC		 1115 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1116 (GRC_LCLCTRL_GPIO_OE1 |
1117 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1118 }
1119 }
1120}
1121
1122static int tg3_setup_phy(struct tg3 *, int);
1123
1124#define RESET_KIND_SHUTDOWN 0
1125#define RESET_KIND_INIT 1
1126#define RESET_KIND_SUSPEND 2
1127
1128static void tg3_write_sig_post_reset(struct tg3 *, int);
1129static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1130static int tg3_nvram_lock(struct tg3 *);
1131static void tg3_nvram_unlock(struct tg3 *);
1da177e4
LT		 1132
1133static int tg3_set_power_state(struct tg3 *tp, int state)
1134{
1135 u32 misc_host_ctrl;
1136 u16 power_control, power_caps;
1137 int pm = tp->pm_cap;
1138
1139 /* Make sure register accesses (indirect or otherwise)
1140 * will function correctly.
1141 */
1142 pci_write_config_dword(tp->pdev,
1143 TG3PCI_MISC_HOST_CTRL,
1144 tp->misc_host_ctrl);
1145
1146 pci_read_config_word(tp->pdev,
1147 pm + PCI_PM_CTRL,
1148 &power_control);
1149 power_control |= PCI_PM_CTRL_PME_STATUS;
1150 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1151 switch (state) {
1152 case 0:
1153 power_control |= 0;
1154 pci_write_config_word(tp->pdev,
1155 pm + PCI_PM_CTRL,
1156 power_control);
8c6bda1a
MC		 1157 udelay(100); /* Delay after power state change */
1158
1159 /* Switch out of Vaux if it is not a LOM */
b401e9e2
MC		 1160 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1162
1163 return 0;
1164
1165 case 1:
1166 power_control |= 1;
1167 break;
1168
1169 case 2:
1170 power_control |= 2;
1171 break;
1172
1173 case 3:
1174 power_control |= 3;
1175 break;
1176
1177 default:
1178 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1179 "requested.\n",
1180 tp->dev->name, state);
1181 return -EINVAL;
1182 };
1183
1184 power_control |= PCI_PM_CTRL_PME_ENABLE;
1185
1186 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1187 tw32(TG3PCI_MISC_HOST_CTRL,
1188 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1189
1190 if (tp->link_config.phy_is_low_power == 0) {
1191 tp->link_config.phy_is_low_power = 1;
1192 tp->link_config.orig_speed = tp->link_config.speed;
1193 tp->link_config.orig_duplex = tp->link_config.duplex;
1194 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1195 }
1196
747e8f8b 1197 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1198 tp->link_config.speed = SPEED_10;
1199 tp->link_config.duplex = DUPLEX_HALF;
1200 tp->link_config.autoneg = AUTONEG_ENABLE;
1201 tg3_setup_phy(tp, 0);
1202 }
1203
6921d201
MC		 1204 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1205 int i;
1206 u32 val;
1207
1208 for (i = 0; i < 200; i++) {
1209 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1210 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1211 break;
1212 msleep(1);
1213 }
1214 }
1215 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1216 WOL_DRV_STATE_SHUTDOWN |
1217 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1218
1da177e4
LT		 1219 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1220
1221 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1222 u32 mac_mode;
1223
1224 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1225 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1226 udelay(40);
1227
1228 mac_mode = MAC_MODE_PORT_MODE_MII;
1229
1230 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1231 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1232 mac_mode |= MAC_MODE_LINK_POLARITY;
1233 } else {
1234 mac_mode = MAC_MODE_PORT_MODE_TBI;
1235 }
1236
cbf46853 1237 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1238 tw32(MAC_LED_CTRL, tp->led_ctrl);
1239
1240 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1241 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1242 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1243
1244 tw32_f(MAC_MODE, mac_mode);
1245 udelay(100);
1246
1247 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1248 udelay(10);
1249 }
1250
1251 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1252 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1253 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1254 u32 base_val;
1255
1256 base_val = tp->pci_clock_ctrl;
1257 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1258 CLOCK_CTRL_TXCLK_DISABLE);
1259
b401e9e2
MC		 1260 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1261 CLOCK_CTRL_PWRDOWN_PLL133, 40);
a4e2b347 1262 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f 1263 /* do nothing */
85e94ced 1264 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1265 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1266 u32 newbits1, newbits2;
1267
1268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1270 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1271 CLOCK_CTRL_TXCLK_DISABLE |
1272 CLOCK_CTRL_ALTCLK);
1273 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1274 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1275 newbits1 = CLOCK_CTRL_625_CORE;
1276 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1277 } else {
1278 newbits1 = CLOCK_CTRL_ALTCLK;
1279 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1280 }
1281
b401e9e2
MC		 1282 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1283 40);
1da177e4 1284
b401e9e2
MC		 1285 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1286 40);
1da177e4
LT		 1287
1288 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1289 u32 newbits3;
1290
1291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1292 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1293 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1294 CLOCK_CTRL_TXCLK_DISABLE |
1295 CLOCK_CTRL_44MHZ_CORE);
1296 } else {
1297 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1298 }
1299
b401e9e2
MC		 1300 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1301 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1302 }
1303 }
1304
6921d201
MC		 1305 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1306 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1307 /* Turn off the PHY */
1308 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1309 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1310 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1311 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
dc56b7d4
MC		 1312 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
1313 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
6921d201
MC		 1314 }
1315 }
1316
1da177e4
LT		 1317 tg3_frob_aux_power(tp);
1318
1319 /* Workaround for unstable PLL clock */
1320 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1321 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1322 u32 val = tr32(0x7d00);
1323
1324 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1325 tw32(0x7d00, val);
6921d201
MC		 1326 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1327 tg3_nvram_lock(tp);
1da177e4 1328 tg3_halt_cpu(tp, RX_CPU_BASE);
6921d201
MC		 1329 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR0);
1330 tg3_nvram_unlock(tp);
1331 }
1da177e4
LT		 1332 }
1333
1334 /* Finally, set the new power state. */
1335 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1336 udelay(100); /* Delay after power state change */
1da177e4
LT		 1337
1338 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1339
1340 return 0;
1341}
1342
1343static void tg3_link_report(struct tg3 *tp)
1344{
1345 if (!netif_carrier_ok(tp->dev)) {
1346 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1347 } else {
1348 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1349 tp->dev->name,
1350 (tp->link_config.active_speed == SPEED_1000 ?
1351 1000 :
1352 (tp->link_config.active_speed == SPEED_100 ?
1353 100 : 10)),
1354 (tp->link_config.active_duplex == DUPLEX_FULL ?
1355 "full" : "half"));
1356
1357 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1358 "%s for RX.\n",
1359 tp->dev->name,
1360 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1361 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1362 }
1363}
1364
1365static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1366{
1367 u32 new_tg3_flags = 0;
1368 u32 old_rx_mode = tp->rx_mode;
1369 u32 old_tx_mode = tp->tx_mode;
1370
1371 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1372
1373 /* Convert 1000BaseX flow control bits to 1000BaseT
1374 * bits before resolving flow control.
1375 */
1376 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1377 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1378 ADVERTISE_PAUSE_ASYM);
1379 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1380
1381 if (local_adv & ADVERTISE_1000XPAUSE)
1382 local_adv |= ADVERTISE_PAUSE_CAP;
1383 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1384 local_adv |= ADVERTISE_PAUSE_ASYM;
1385 if (remote_adv & LPA_1000XPAUSE)
1386 remote_adv |= LPA_PAUSE_CAP;
1387 if (remote_adv & LPA_1000XPAUSE_ASYM)
1388 remote_adv |= LPA_PAUSE_ASYM;
1389 }
1390
1da177e4
LT		 1391 if (local_adv & ADVERTISE_PAUSE_CAP) {
1392 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1393 if (remote_adv & LPA_PAUSE_CAP)
1394 new_tg3_flags |=
1395 (TG3_FLAG_RX_PAUSE |
1396 TG3_FLAG_TX_PAUSE);
1397 else if (remote_adv & LPA_PAUSE_ASYM)
1398 new_tg3_flags |=
1399 (TG3_FLAG_RX_PAUSE);
1400 } else {
1401 if (remote_adv & LPA_PAUSE_CAP)
1402 new_tg3_flags |=
1403 (TG3_FLAG_RX_PAUSE |
1404 TG3_FLAG_TX_PAUSE);
1405 }
1406 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1407 if ((remote_adv & LPA_PAUSE_CAP) &&
1408 (remote_adv & LPA_PAUSE_ASYM))
1409 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1410 }
1411
1412 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1413 tp->tg3_flags |= new_tg3_flags;
1414 } else {
1415 new_tg3_flags = tp->tg3_flags;
1416 }
1417
1418 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1419 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1420 else
1421 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1422
1423 if (old_rx_mode != tp->rx_mode) {
1424 tw32_f(MAC_RX_MODE, tp->rx_mode);
1425 }
1426
1427 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1428 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1429 else
1430 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1431
1432 if (old_tx_mode != tp->tx_mode) {
1433 tw32_f(MAC_TX_MODE, tp->tx_mode);
1434 }
1435}
1436
1437static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1438{
1439 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1440 case MII_TG3_AUX_STAT_10HALF:
1441 *speed = SPEED_10;
1442 *duplex = DUPLEX_HALF;
1443 break;
1444
1445 case MII_TG3_AUX_STAT_10FULL:
1446 *speed = SPEED_10;
1447 *duplex = DUPLEX_FULL;
1448 break;
1449
1450 case MII_TG3_AUX_STAT_100HALF:
1451 *speed = SPEED_100;
1452 *duplex = DUPLEX_HALF;
1453 break;
1454
1455 case MII_TG3_AUX_STAT_100FULL:
1456 *speed = SPEED_100;
1457 *duplex = DUPLEX_FULL;
1458 break;
1459
1460 case MII_TG3_AUX_STAT_1000HALF:
1461 *speed = SPEED_1000;
1462 *duplex = DUPLEX_HALF;
1463 break;
1464
1465 case MII_TG3_AUX_STAT_1000FULL:
1466 *speed = SPEED_1000;
1467 *duplex = DUPLEX_FULL;
1468 break;
1469
1470 default:
1471 *speed = SPEED_INVALID;
1472 *duplex = DUPLEX_INVALID;
1473 break;
1474 };
1475}
1476
1477static void tg3_phy_copper_begin(struct tg3 *tp)
1478{
1479 u32 new_adv;
1480 int i;
1481
1482 if (tp->link_config.phy_is_low_power) {
1483 /* Entering low power mode. Disable gigabit and
1484 * 100baseT advertisements.
1485 */
1486 tg3_writephy(tp, MII_TG3_CTRL, 0);
1487
1488 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1489 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1490 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1491 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1492
1493 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1494 } else if (tp->link_config.speed == SPEED_INVALID) {
1495 tp->link_config.advertising =
1496 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1497 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1498 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1499 ADVERTISED_Autoneg | ADVERTISED_MII);
1500
1501 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1502 tp->link_config.advertising &=
1503 ~(ADVERTISED_1000baseT_Half |
1504 ADVERTISED_1000baseT_Full);
1505
1506 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1507 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1508 new_adv |= ADVERTISE_10HALF;
1509 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1510 new_adv |= ADVERTISE_10FULL;
1511 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1512 new_adv |= ADVERTISE_100HALF;
1513 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1514 new_adv |= ADVERTISE_100FULL;
1515 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1516
1517 if (tp->link_config.advertising &
1518 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1519 new_adv = 0;
1520 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1521 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1522 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1523 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1524 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1525 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1526 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1527 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1528 MII_TG3_CTRL_ENABLE_AS_MASTER);
1529 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1530 } else {
1531 tg3_writephy(tp, MII_TG3_CTRL, 0);
1532 }
1533 } else {
1534 /* Asking for a specific link mode. */
1535 if (tp->link_config.speed == SPEED_1000) {
1536 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1537 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1538
1539 if (tp->link_config.duplex == DUPLEX_FULL)
1540 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1541 else
1542 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1543 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1544 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1545 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1546 MII_TG3_CTRL_ENABLE_AS_MASTER);
1547 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1548 } else {
1549 tg3_writephy(tp, MII_TG3_CTRL, 0);
1550
1551 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1552 if (tp->link_config.speed == SPEED_100) {
1553 if (tp->link_config.duplex == DUPLEX_FULL)
1554 new_adv |= ADVERTISE_100FULL;
1555 else
1556 new_adv |= ADVERTISE_100HALF;
1557 } else {
1558 if (tp->link_config.duplex == DUPLEX_FULL)
1559 new_adv |= ADVERTISE_10FULL;
1560 else
1561 new_adv |= ADVERTISE_10HALF;
1562 }
1563 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1564 }
1565 }
1566
1567 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1568 tp->link_config.speed != SPEED_INVALID) {
1569 u32 bmcr, orig_bmcr;
1570
1571 tp->link_config.active_speed = tp->link_config.speed;
1572 tp->link_config.active_duplex = tp->link_config.duplex;
1573
1574 bmcr = 0;
1575 switch (tp->link_config.speed) {
1576 default:
1577 case SPEED_10:
1578 break;
1579
1580 case SPEED_100:
1581 bmcr |= BMCR_SPEED100;
1582 break;
1583
1584 case SPEED_1000:
1585 bmcr |= TG3_BMCR_SPEED1000;
1586 break;
1587 };
1588
1589 if (tp->link_config.duplex == DUPLEX_FULL)
1590 bmcr |= BMCR_FULLDPLX;
1591
1592 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1593 (bmcr != orig_bmcr)) {
1594 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1595 for (i = 0; i < 1500; i++) {
1596 u32 tmp;
1597
1598 udelay(10);
1599 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1600 tg3_readphy(tp, MII_BMSR, &tmp))
1601 continue;
1602 if (!(tmp & BMSR_LSTATUS)) {
1603 udelay(40);
1604 break;
1605 }
1606 }
1607 tg3_writephy(tp, MII_BMCR, bmcr);
1608 udelay(40);
1609 }
1610 } else {
1611 tg3_writephy(tp, MII_BMCR,
1612 BMCR_ANENABLE | BMCR_ANRESTART);
1613 }
1614}
1615
1616static int tg3_init_5401phy_dsp(struct tg3 *tp)
1617{
1618 int err;
1619
1620 /* Turn off tap power management. */
1621 /* Set Extended packet length bit */
1622 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1623
1624 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1625 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1626
1627 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1628 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1629
1630 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1631 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1632
1633 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1634 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1635
1636 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1637 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1638
1639 udelay(40);
1640
1641 return err;
1642}
1643
1644static int tg3_copper_is_advertising_all(struct tg3 *tp)
1645{
1646 u32 adv_reg, all_mask;
1647
1648 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1649 return 0;
1650
1651 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1652 ADVERTISE_100HALF | ADVERTISE_100FULL);
1653 if ((adv_reg & all_mask) != all_mask)
1654 return 0;
1655 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1656 u32 tg3_ctrl;
1657
1658 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1659 return 0;
1660
1661 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1662 MII_TG3_CTRL_ADV_1000_FULL);
1663 if ((tg3_ctrl & all_mask) != all_mask)
1664 return 0;
1665 }
1666 return 1;
1667}
1668
1669static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1670{
1671 int current_link_up;
1672 u32 bmsr, dummy;
1673 u16 current_speed;
1674 u8 current_duplex;
1675 int i, err;
1676
1677 tw32(MAC_EVENT, 0);
1678
1679 tw32_f(MAC_STATUS,
1680 (MAC_STATUS_SYNC_CHANGED |
1681 MAC_STATUS_CFG_CHANGED |
1682 MAC_STATUS_MI_COMPLETION |
1683 MAC_STATUS_LNKSTATE_CHANGED));
1684 udelay(40);
1685
1686 tp->mi_mode = MAC_MI_MODE_BASE;
1687 tw32_f(MAC_MI_MODE, tp->mi_mode);
1688 udelay(80);
1689
1690 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1691
1692 /* Some third-party PHYs need to be reset on link going
1693 * down.
1694 */
1695 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1696 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1697 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1698 netif_carrier_ok(tp->dev)) {
1699 tg3_readphy(tp, MII_BMSR, &bmsr);
1700 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1701 !(bmsr & BMSR_LSTATUS))
1702 force_reset = 1;
1703 }
1704 if (force_reset)
1705 tg3_phy_reset(tp);
1706
1707 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1708 tg3_readphy(tp, MII_BMSR, &bmsr);
1709 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1710 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1711 bmsr = 0;
1712
1713 if (!(bmsr & BMSR_LSTATUS)) {
1714 err = tg3_init_5401phy_dsp(tp);
1715 if (err)
1716 return err;
1717
1718 tg3_readphy(tp, MII_BMSR, &bmsr);
1719 for (i = 0; i < 1000; i++) {
1720 udelay(10);
1721 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1722 (bmsr & BMSR_LSTATUS)) {
1723 udelay(40);
1724 break;
1725 }
1726 }
1727
1728 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1729 !(bmsr & BMSR_LSTATUS) &&
1730 tp->link_config.active_speed == SPEED_1000) {
1731 err = tg3_phy_reset(tp);
1732 if (!err)
1733 err = tg3_init_5401phy_dsp(tp);
1734 if (err)
1735 return err;
1736 }
1737 }
1738 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1739 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1740 /* 5701 {A0,B0} CRC bug workaround */
1741 tg3_writephy(tp, 0x15, 0x0a75);
1742 tg3_writephy(tp, 0x1c, 0x8c68);
1743 tg3_writephy(tp, 0x1c, 0x8d68);
1744 tg3_writephy(tp, 0x1c, 0x8c68);
1745 }
1746
1747 /* Clear pending interrupts... */
1748 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1749 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1750
1751 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1752 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1753 else
1754 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1755
1756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1757 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1758 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1759 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1760 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1761 else
1762 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1763 }
1764
1765 current_link_up = 0;
1766 current_speed = SPEED_INVALID;
1767 current_duplex = DUPLEX_INVALID;
1768
1769 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1770 u32 val;
1771
1772 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1773 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1774 if (!(val & (1 << 10))) {
1775 val |= (1 << 10);
1776 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1777 goto relink;
1778 }
1779 }
1780
1781 bmsr = 0;
1782 for (i = 0; i < 100; i++) {
1783 tg3_readphy(tp, MII_BMSR, &bmsr);
1784 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1785 (bmsr & BMSR_LSTATUS))
1786 break;
1787 udelay(40);
1788 }
1789
1790 if (bmsr & BMSR_LSTATUS) {
1791 u32 aux_stat, bmcr;
1792
1793 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1794 for (i = 0; i < 2000; i++) {
1795 udelay(10);
1796 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1797 aux_stat)
1798 break;
1799 }
1800
1801 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1802 &current_speed,
1803 &current_duplex);
1804
1805 bmcr = 0;
1806 for (i = 0; i < 200; i++) {
1807 tg3_readphy(tp, MII_BMCR, &bmcr);
1808 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1809 continue;
1810 if (bmcr && bmcr != 0x7fff)
1811 break;
1812 udelay(10);
1813 }
1814
1815 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1816 if (bmcr & BMCR_ANENABLE) {
1817 current_link_up = 1;
1818
1819 /* Force autoneg restart if we are exiting
1820 * low power mode.
1821 */
1822 if (!tg3_copper_is_advertising_all(tp))
1823 current_link_up = 0;
1824 } else {
1825 current_link_up = 0;
1826 }
1827 } else {
1828 if (!(bmcr & BMCR_ANENABLE) &&
1829 tp->link_config.speed == current_speed &&
1830 tp->link_config.duplex == current_duplex) {
1831 current_link_up = 1;
1832 } else {
1833 current_link_up = 0;
1834 }
1835 }
1836
1837 tp->link_config.active_speed = current_speed;
1838 tp->link_config.active_duplex = current_duplex;
1839 }
1840
1841 if (current_link_up == 1 &&
1842 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1843 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1844 u32 local_adv, remote_adv;
1845
1846 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1847 local_adv = 0;
1848 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1849
1850 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1851 remote_adv = 0;
1852
1853 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1854
1855 /* If we are not advertising full pause capability,
1856 * something is wrong. Bring the link down and reconfigure.
1857 */
1858 if (local_adv != ADVERTISE_PAUSE_CAP) {
1859 current_link_up = 0;
1860 } else {
1861 tg3_setup_flow_control(tp, local_adv, remote_adv);
1862 }
1863 }
1864relink:
6921d201 1865 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 1866 u32 tmp;
1867
1868 tg3_phy_copper_begin(tp);
1869
1870 tg3_readphy(tp, MII_BMSR, &tmp);
1871 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1872 (tmp & BMSR_LSTATUS))
1873 current_link_up = 1;
1874 }
1875
1876 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1877 if (current_link_up == 1) {
1878 if (tp->link_config.active_speed == SPEED_100 ||
1879 tp->link_config.active_speed == SPEED_10)
1880 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1881 else
1882 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1883 } else
1884 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1885
1886 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1887 if (tp->link_config.active_duplex == DUPLEX_HALF)
1888 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1889
1890 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1891 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1892 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1893 (current_link_up == 1 &&
1894 tp->link_config.active_speed == SPEED_10))
1895 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1896 } else {
1897 if (current_link_up == 1)
1898 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1899 }
1900
1901 /* ??? Without this setting Netgear GA302T PHY does not
1902 * ??? send/receive packets...
1903 */
1904 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1905 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1906 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1907 tw32_f(MAC_MI_MODE, tp->mi_mode);
1908 udelay(80);
1909 }
1910
1911 tw32_f(MAC_MODE, tp->mac_mode);
1912 udelay(40);
1913
1914 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1915 /* Polled via timer. */
1916 tw32_f(MAC_EVENT, 0);
1917 } else {
1918 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1919 }
1920 udelay(40);
1921
1922 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1923 current_link_up == 1 &&
1924 tp->link_config.active_speed == SPEED_1000 &&
1925 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1926 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1927 udelay(120);
1928 tw32_f(MAC_STATUS,
1929 (MAC_STATUS_SYNC_CHANGED |
1930 MAC_STATUS_CFG_CHANGED));
1931 udelay(40);
1932 tg3_write_mem(tp,
1933 NIC_SRAM_FIRMWARE_MBOX,
1934 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1935 }
1936
1937 if (current_link_up != netif_carrier_ok(tp->dev)) {
1938 if (current_link_up)
1939 netif_carrier_on(tp->dev);
1940 else
1941 netif_carrier_off(tp->dev);
1942 tg3_link_report(tp);
1943 }
1944
1945 return 0;
1946}
1947
1948struct tg3_fiber_aneginfo {
1949 int state;
1950#define ANEG_STATE_UNKNOWN 0
1951#define ANEG_STATE_AN_ENABLE 1
1952#define ANEG_STATE_RESTART_INIT 2
1953#define ANEG_STATE_RESTART 3
1954#define ANEG_STATE_DISABLE_LINK_OK 4
1955#define ANEG_STATE_ABILITY_DETECT_INIT 5
1956#define ANEG_STATE_ABILITY_DETECT 6
1957#define ANEG_STATE_ACK_DETECT_INIT 7
1958#define ANEG_STATE_ACK_DETECT 8
1959#define ANEG_STATE_COMPLETE_ACK_INIT 9
1960#define ANEG_STATE_COMPLETE_ACK 10
1961#define ANEG_STATE_IDLE_DETECT_INIT 11
1962#define ANEG_STATE_IDLE_DETECT 12
1963#define ANEG_STATE_LINK_OK 13
1964#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1965#define ANEG_STATE_NEXT_PAGE_WAIT 15
1966
1967 u32 flags;
1968#define MR_AN_ENABLE 0x00000001
1969#define MR_RESTART_AN 0x00000002
1970#define MR_AN_COMPLETE 0x00000004
1971#define MR_PAGE_RX 0x00000008
1972#define MR_NP_LOADED 0x00000010
1973#define MR_TOGGLE_TX 0x00000020
1974#define MR_LP_ADV_FULL_DUPLEX 0x00000040
1975#define MR_LP_ADV_HALF_DUPLEX 0x00000080
1976#define MR_LP_ADV_SYM_PAUSE 0x00000100
1977#define MR_LP_ADV_ASYM_PAUSE 0x00000200
1978#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1979#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1980#define MR_LP_ADV_NEXT_PAGE 0x00001000
1981#define MR_TOGGLE_RX 0x00002000
1982#define MR_NP_RX 0x00004000
1983
1984#define MR_LINK_OK 0x80000000
1985
1986 unsigned long link_time, cur_time;
1987
1988 u32 ability_match_cfg;
1989 int ability_match_count;
1990
1991 char ability_match, idle_match, ack_match;
1992
1993 u32 txconfig, rxconfig;
1994#define ANEG_CFG_NP 0x00000080
1995#define ANEG_CFG_ACK 0x00000040
1996#define ANEG_CFG_RF2 0x00000020
1997#define ANEG_CFG_RF1 0x00000010
1998#define ANEG_CFG_PS2 0x00000001
1999#define ANEG_CFG_PS1 0x00008000
2000#define ANEG_CFG_HD 0x00004000
2001#define ANEG_CFG_FD 0x00002000
2002#define ANEG_CFG_INVAL 0x00001f06
2003
2004};
2005#define ANEG_OK 0
2006#define ANEG_DONE 1
2007#define ANEG_TIMER_ENAB 2
2008#define ANEG_FAILED -1
2009
2010#define ANEG_STATE_SETTLE_TIME 10000
2011
2012static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2013 struct tg3_fiber_aneginfo *ap)
2014{
2015 unsigned long delta;
2016 u32 rx_cfg_reg;
2017 int ret;
2018
2019 if (ap->state == ANEG_STATE_UNKNOWN) {
2020 ap->rxconfig = 0;
2021 ap->link_time = 0;
2022 ap->cur_time = 0;
2023 ap->ability_match_cfg = 0;
2024 ap->ability_match_count = 0;
2025 ap->ability_match = 0;
2026 ap->idle_match = 0;
2027 ap->ack_match = 0;
2028 }
2029 ap->cur_time++;
2030
2031 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2032 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2033
2034 if (rx_cfg_reg != ap->ability_match_cfg) {
2035 ap->ability_match_cfg = rx_cfg_reg;
2036 ap->ability_match = 0;
2037 ap->ability_match_count = 0;
2038 } else {
2039 if (++ap->ability_match_count > 1) {
2040 ap->ability_match = 1;
2041 ap->ability_match_cfg = rx_cfg_reg;
2042 }
2043 }
2044 if (rx_cfg_reg & ANEG_CFG_ACK)
2045 ap->ack_match = 1;
2046 else
2047 ap->ack_match = 0;
2048
2049 ap->idle_match = 0;
2050 } else {
2051 ap->idle_match = 1;
2052 ap->ability_match_cfg = 0;
2053 ap->ability_match_count = 0;
2054 ap->ability_match = 0;
2055 ap->ack_match = 0;
2056
2057 rx_cfg_reg = 0;
2058 }
2059
2060 ap->rxconfig = rx_cfg_reg;
2061 ret = ANEG_OK;
2062
2063 switch(ap->state) {
2064 case ANEG_STATE_UNKNOWN:
2065 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2066 ap->state = ANEG_STATE_AN_ENABLE;
2067
2068 /* fallthru */
2069 case ANEG_STATE_AN_ENABLE:
2070 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2071 if (ap->flags & MR_AN_ENABLE) {
2072 ap->link_time = 0;
2073 ap->cur_time = 0;
2074 ap->ability_match_cfg = 0;
2075 ap->ability_match_count = 0;
2076 ap->ability_match = 0;
2077 ap->idle_match = 0;
2078 ap->ack_match = 0;
2079
2080 ap->state = ANEG_STATE_RESTART_INIT;
2081 } else {
2082 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2083 }
2084 break;
2085
2086 case ANEG_STATE_RESTART_INIT:
2087 ap->link_time = ap->cur_time;
2088 ap->flags &= ~(MR_NP_LOADED);
2089 ap->txconfig = 0;
2090 tw32(MAC_TX_AUTO_NEG, 0);
2091 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2092 tw32_f(MAC_MODE, tp->mac_mode);
2093 udelay(40);
2094
2095 ret = ANEG_TIMER_ENAB;
2096 ap->state = ANEG_STATE_RESTART;
2097
2098 /* fallthru */
2099 case ANEG_STATE_RESTART:
2100 delta = ap->cur_time - ap->link_time;
2101 if (delta > ANEG_STATE_SETTLE_TIME) {
2102 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2103 } else {
2104 ret = ANEG_TIMER_ENAB;
2105 }
2106 break;
2107
2108 case ANEG_STATE_DISABLE_LINK_OK:
2109 ret = ANEG_DONE;
2110 break;
2111
2112 case ANEG_STATE_ABILITY_DETECT_INIT:
2113 ap->flags &= ~(MR_TOGGLE_TX);
2114 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2115 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2116 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2117 tw32_f(MAC_MODE, tp->mac_mode);
2118 udelay(40);
2119
2120 ap->state = ANEG_STATE_ABILITY_DETECT;
2121 break;
2122
2123 case ANEG_STATE_ABILITY_DETECT:
2124 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2125 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2126 }
2127 break;
2128
2129 case ANEG_STATE_ACK_DETECT_INIT:
2130 ap->txconfig |= ANEG_CFG_ACK;
2131 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2132 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2133 tw32_f(MAC_MODE, tp->mac_mode);
2134 udelay(40);
2135
2136 ap->state = ANEG_STATE_ACK_DETECT;
2137
2138 /* fallthru */
2139 case ANEG_STATE_ACK_DETECT:
2140 if (ap->ack_match != 0) {
2141 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2142 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2143 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2144 } else {
2145 ap->state = ANEG_STATE_AN_ENABLE;
2146 }
2147 } else if (ap->ability_match != 0 &&
2148 ap->rxconfig == 0) {
2149 ap->state = ANEG_STATE_AN_ENABLE;
2150 }
2151 break;
2152
2153 case ANEG_STATE_COMPLETE_ACK_INIT:
2154 if (ap->rxconfig & ANEG_CFG_INVAL) {
2155 ret = ANEG_FAILED;
2156 break;
2157 }
2158 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2159 MR_LP_ADV_HALF_DUPLEX |
2160 MR_LP_ADV_SYM_PAUSE |
2161 MR_LP_ADV_ASYM_PAUSE |
2162 MR_LP_ADV_REMOTE_FAULT1 |
2163 MR_LP_ADV_REMOTE_FAULT2 |
2164 MR_LP_ADV_NEXT_PAGE |
2165 MR_TOGGLE_RX |
2166 MR_NP_RX);
2167 if (ap->rxconfig & ANEG_CFG_FD)
2168 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2169 if (ap->rxconfig & ANEG_CFG_HD)
2170 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2171 if (ap->rxconfig & ANEG_CFG_PS1)
2172 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2173 if (ap->rxconfig & ANEG_CFG_PS2)
2174 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2175 if (ap->rxconfig & ANEG_CFG_RF1)
2176 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2177 if (ap->rxconfig & ANEG_CFG_RF2)
2178 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2179 if (ap->rxconfig & ANEG_CFG_NP)
2180 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2181
2182 ap->link_time = ap->cur_time;
2183
2184 ap->flags ^= (MR_TOGGLE_TX);
2185 if (ap->rxconfig & 0x0008)
2186 ap->flags |= MR_TOGGLE_RX;
2187 if (ap->rxconfig & ANEG_CFG_NP)
2188 ap->flags |= MR_NP_RX;
2189 ap->flags |= MR_PAGE_RX;
2190
2191 ap->state = ANEG_STATE_COMPLETE_ACK;
2192 ret = ANEG_TIMER_ENAB;
2193 break;
2194
2195 case ANEG_STATE_COMPLETE_ACK:
2196 if (ap->ability_match != 0 &&
2197 ap->rxconfig == 0) {
2198 ap->state = ANEG_STATE_AN_ENABLE;
2199 break;
2200 }
2201 delta = ap->cur_time - ap->link_time;
2202 if (delta > ANEG_STATE_SETTLE_TIME) {
2203 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2204 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2205 } else {
2206 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2207 !(ap->flags & MR_NP_RX)) {
2208 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2209 } else {
2210 ret = ANEG_FAILED;
2211 }
2212 }
2213 }
2214 break;
2215
2216 case ANEG_STATE_IDLE_DETECT_INIT:
2217 ap->link_time = ap->cur_time;
2218 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2219 tw32_f(MAC_MODE, tp->mac_mode);
2220 udelay(40);
2221
2222 ap->state = ANEG_STATE_IDLE_DETECT;
2223 ret = ANEG_TIMER_ENAB;
2224 break;
2225
2226 case ANEG_STATE_IDLE_DETECT:
2227 if (ap->ability_match != 0 &&
2228 ap->rxconfig == 0) {
2229 ap->state = ANEG_STATE_AN_ENABLE;
2230 break;
2231 }
2232 delta = ap->cur_time - ap->link_time;
2233 if (delta > ANEG_STATE_SETTLE_TIME) {
2234 /* XXX another gem from the Broadcom driver :( */
2235 ap->state = ANEG_STATE_LINK_OK;
2236 }
2237 break;
2238
2239 case ANEG_STATE_LINK_OK:
2240 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2241 ret = ANEG_DONE;
2242 break;
2243
2244 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2245 /* ??? unimplemented */
2246 break;
2247
2248 case ANEG_STATE_NEXT_PAGE_WAIT:
2249 /* ??? unimplemented */
2250 break;
2251
2252 default:
2253 ret = ANEG_FAILED;
2254 break;
2255 };
2256
2257 return ret;
2258}
2259
2260static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2261{
2262 int res = 0;
2263 struct tg3_fiber_aneginfo aninfo;
2264 int status = ANEG_FAILED;
2265 unsigned int tick;
2266 u32 tmp;
2267
2268 tw32_f(MAC_TX_AUTO_NEG, 0);
2269
2270 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2271 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2272 udelay(40);
2273
2274 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2275 udelay(40);
2276
2277 memset(&aninfo, 0, sizeof(aninfo));
2278 aninfo.flags |= MR_AN_ENABLE;
2279 aninfo.state = ANEG_STATE_UNKNOWN;
2280 aninfo.cur_time = 0;
2281 tick = 0;
2282 while (++tick < 195000) {
2283 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2284 if (status == ANEG_DONE || status == ANEG_FAILED)
2285 break;
2286
2287 udelay(1);
2288 }
2289
2290 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2291 tw32_f(MAC_MODE, tp->mac_mode);
2292 udelay(40);
2293
2294 *flags = aninfo.flags;
2295
2296 if (status == ANEG_DONE &&
2297 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2298 MR_LP_ADV_FULL_DUPLEX)))
2299 res = 1;
2300
2301 return res;
2302}
2303
2304static void tg3_init_bcm8002(struct tg3 *tp)
2305{
2306 u32 mac_status = tr32(MAC_STATUS);
2307 int i;
2308
2309 /* Reset when initting first time or we have a link. */
2310 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2311 !(mac_status & MAC_STATUS_PCS_SYNCED))
2312 return;
2313
2314 /* Set PLL lock range. */
2315 tg3_writephy(tp, 0x16, 0x8007);
2316
2317 /* SW reset */
2318 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2319
2320 /* Wait for reset to complete. */
2321 /* XXX schedule_timeout() ... */
2322 for (i = 0; i < 500; i++)
2323 udelay(10);
2324
2325 /* Config mode; select PMA/Ch 1 regs. */
2326 tg3_writephy(tp, 0x10, 0x8411);
2327
2328 /* Enable auto-lock and comdet, select txclk for tx. */
2329 tg3_writephy(tp, 0x11, 0x0a10);
2330
2331 tg3_writephy(tp, 0x18, 0x00a0);
2332 tg3_writephy(tp, 0x16, 0x41ff);
2333
2334 /* Assert and deassert POR. */
2335 tg3_writephy(tp, 0x13, 0x0400);
2336 udelay(40);
2337 tg3_writephy(tp, 0x13, 0x0000);
2338
2339 tg3_writephy(tp, 0x11, 0x0a50);
2340 udelay(40);
2341 tg3_writephy(tp, 0x11, 0x0a10);
2342
2343 /* Wait for signal to stabilize */
2344 /* XXX schedule_timeout() ... */
2345 for (i = 0; i < 15000; i++)
2346 udelay(10);
2347
2348 /* Deselect the channel register so we can read the PHYID
2349 * later.
2350 */
2351 tg3_writephy(tp, 0x10, 0x8011);
2352}
2353
2354static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2355{
2356 u32 sg_dig_ctrl, sg_dig_status;
2357 u32 serdes_cfg, expected_sg_dig_ctrl;
2358 int workaround, port_a;
2359 int current_link_up;
2360
2361 serdes_cfg = 0;
2362 expected_sg_dig_ctrl = 0;
2363 workaround = 0;
2364 port_a = 1;
2365 current_link_up = 0;
2366
2367 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2368 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2369 workaround = 1;
2370 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2371 port_a = 0;
2372
2373 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2374 /* preserve bits 20-23 for voltage regulator */
2375 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2376 }
2377
2378 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2379
2380 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2381 if (sg_dig_ctrl & (1 << 31)) {
2382 if (workaround) {
2383 u32 val = serdes_cfg;
2384
2385 if (port_a)
2386 val |= 0xc010000;
2387 else
2388 val |= 0x4010000;
2389 tw32_f(MAC_SERDES_CFG, val);
2390 }
2391 tw32_f(SG_DIG_CTRL, 0x01388400);
2392 }
2393 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2394 tg3_setup_flow_control(tp, 0, 0);
2395 current_link_up = 1;
2396 }
2397 goto out;
2398 }
2399
2400 /* Want auto-negotiation. */
2401 expected_sg_dig_ctrl = 0x81388400;
2402
2403 /* Pause capability */
2404 expected_sg_dig_ctrl |= (1 << 11);
2405
2406 /* Asymettric pause */
2407 expected_sg_dig_ctrl |= (1 << 12);
2408
2409 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2410 if (workaround)
2411 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2412 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2413 udelay(5);
2414 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2415
2416 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2417 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2418 MAC_STATUS_SIGNAL_DET)) {
2419 int i;
2420
2421 /* Giver time to negotiate (~200ms) */
2422 for (i = 0; i < 40000; i++) {
2423 sg_dig_status = tr32(SG_DIG_STATUS);
2424 if (sg_dig_status & (0x3))
2425 break;
2426 udelay(5);
2427 }
2428 mac_status = tr32(MAC_STATUS);
2429
2430 if ((sg_dig_status & (1 << 1)) &&
2431 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2432 u32 local_adv, remote_adv;
2433
2434 local_adv = ADVERTISE_PAUSE_CAP;
2435 remote_adv = 0;
2436 if (sg_dig_status & (1 << 19))
2437 remote_adv |= LPA_PAUSE_CAP;
2438 if (sg_dig_status & (1 << 20))
2439 remote_adv |= LPA_PAUSE_ASYM;
2440
2441 tg3_setup_flow_control(tp, local_adv, remote_adv);
2442 current_link_up = 1;
2443 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2444 } else if (!(sg_dig_status & (1 << 1))) {
2445 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2446 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2447 else {
2448 if (workaround) {
2449 u32 val = serdes_cfg;
2450
2451 if (port_a)
2452 val |= 0xc010000;
2453 else
2454 val |= 0x4010000;
2455
2456 tw32_f(MAC_SERDES_CFG, val);
2457 }
2458
2459 tw32_f(SG_DIG_CTRL, 0x01388400);
2460 udelay(40);
2461
2462 /* Link parallel detection - link is up */
2463 /* only if we have PCS_SYNC and not */
2464 /* receiving config code words */
2465 mac_status = tr32(MAC_STATUS);
2466 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2467 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2468 tg3_setup_flow_control(tp, 0, 0);
2469 current_link_up = 1;
2470 }
2471 }
2472 }
2473 }
2474
2475out:
2476 return current_link_up;
2477}
2478
2479static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2480{
2481 int current_link_up = 0;
2482
2483 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2484 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2485 goto out;
2486 }
2487
2488 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2489 u32 flags;
2490 int i;
2491
2492 if (fiber_autoneg(tp, &flags)) {
2493 u32 local_adv, remote_adv;
2494
2495 local_adv = ADVERTISE_PAUSE_CAP;
2496 remote_adv = 0;
2497 if (flags & MR_LP_ADV_SYM_PAUSE)
2498 remote_adv |= LPA_PAUSE_CAP;
2499 if (flags & MR_LP_ADV_ASYM_PAUSE)
2500 remote_adv |= LPA_PAUSE_ASYM;
2501
2502 tg3_setup_flow_control(tp, local_adv, remote_adv);
2503
2504 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2505 current_link_up = 1;
2506 }
2507 for (i = 0; i < 30; i++) {
2508 udelay(20);
2509 tw32_f(MAC_STATUS,
2510 (MAC_STATUS_SYNC_CHANGED |
2511 MAC_STATUS_CFG_CHANGED));
2512 udelay(40);
2513 if ((tr32(MAC_STATUS) &
2514 (MAC_STATUS_SYNC_CHANGED |
2515 MAC_STATUS_CFG_CHANGED)) == 0)
2516 break;
2517 }
2518
2519 mac_status = tr32(MAC_STATUS);
2520 if (current_link_up == 0 &&
2521 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2522 !(mac_status & MAC_STATUS_RCVD_CFG))
2523 current_link_up = 1;
2524 } else {
2525 /* Forcing 1000FD link up. */
2526 current_link_up = 1;
2527 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2528
2529 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2530 udelay(40);
2531 }
2532
2533out:
2534 return current_link_up;
2535}
2536
2537static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2538{
2539 u32 orig_pause_cfg;
2540 u16 orig_active_speed;
2541 u8 orig_active_duplex;
2542 u32 mac_status;
2543 int current_link_up;
2544 int i;
2545
2546 orig_pause_cfg =
2547 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2548 TG3_FLAG_TX_PAUSE));
2549 orig_active_speed = tp->link_config.active_speed;
2550 orig_active_duplex = tp->link_config.active_duplex;
2551
2552 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2553 netif_carrier_ok(tp->dev) &&
2554 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2555 mac_status = tr32(MAC_STATUS);
2556 mac_status &= (MAC_STATUS_PCS_SYNCED |
2557 MAC_STATUS_SIGNAL_DET |
2558 MAC_STATUS_CFG_CHANGED |
2559 MAC_STATUS_RCVD_CFG);
2560 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2561 MAC_STATUS_SIGNAL_DET)) {
2562 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2563 MAC_STATUS_CFG_CHANGED));
2564 return 0;
2565 }
2566 }
2567
2568 tw32_f(MAC_TX_AUTO_NEG, 0);
2569
2570 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2571 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2572 tw32_f(MAC_MODE, tp->mac_mode);
2573 udelay(40);
2574
2575 if (tp->phy_id == PHY_ID_BCM8002)
2576 tg3_init_bcm8002(tp);
2577
2578 /* Enable link change event even when serdes polling. */
2579 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2580 udelay(40);
2581
2582 current_link_up = 0;
2583 mac_status = tr32(MAC_STATUS);
2584
2585 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2586 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2587 else
2588 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2589
2590 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2591 tw32_f(MAC_MODE, tp->mac_mode);
2592 udelay(40);
2593
2594 tp->hw_status->status =
2595 (SD_STATUS_UPDATED |
2596 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2597
2598 for (i = 0; i < 100; i++) {
2599 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2600 MAC_STATUS_CFG_CHANGED));
2601 udelay(5);
2602 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2603 MAC_STATUS_CFG_CHANGED)) == 0)
2604 break;
2605 }
2606
2607 mac_status = tr32(MAC_STATUS);
2608 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2609 current_link_up = 0;
2610 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2611 tw32_f(MAC_MODE, (tp->mac_mode |
2612 MAC_MODE_SEND_CONFIGS));
2613 udelay(1);
2614 tw32_f(MAC_MODE, tp->mac_mode);
2615 }
2616 }
2617
2618 if (current_link_up == 1) {
2619 tp->link_config.active_speed = SPEED_1000;
2620 tp->link_config.active_duplex = DUPLEX_FULL;
2621 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2622 LED_CTRL_LNKLED_OVERRIDE |
2623 LED_CTRL_1000MBPS_ON));
2624 } else {
2625 tp->link_config.active_speed = SPEED_INVALID;
2626 tp->link_config.active_duplex = DUPLEX_INVALID;
2627 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2628 LED_CTRL_LNKLED_OVERRIDE |
2629 LED_CTRL_TRAFFIC_OVERRIDE));
2630 }
2631
2632 if (current_link_up != netif_carrier_ok(tp->dev)) {
2633 if (current_link_up)
2634 netif_carrier_on(tp->dev);
2635 else
2636 netif_carrier_off(tp->dev);
2637 tg3_link_report(tp);
2638 } else {
2639 u32 now_pause_cfg =
2640 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2641 TG3_FLAG_TX_PAUSE);
2642 if (orig_pause_cfg != now_pause_cfg ||
2643 orig_active_speed != tp->link_config.active_speed ||
2644 orig_active_duplex != tp->link_config.active_duplex)
2645 tg3_link_report(tp);
2646 }
2647
2648 return 0;
2649}
2650
747e8f8b
MC		 2651static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2652{
2653 int current_link_up, err = 0;
2654 u32 bmsr, bmcr;
2655 u16 current_speed;
2656 u8 current_duplex;
2657
2658 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2659 tw32_f(MAC_MODE, tp->mac_mode);
2660 udelay(40);
2661
2662 tw32(MAC_EVENT, 0);
2663
2664 tw32_f(MAC_STATUS,
2665 (MAC_STATUS_SYNC_CHANGED |
2666 MAC_STATUS_CFG_CHANGED |
2667 MAC_STATUS_MI_COMPLETION |
2668 MAC_STATUS_LNKSTATE_CHANGED));
2669 udelay(40);
2670
2671 if (force_reset)
2672 tg3_phy_reset(tp);
2673
2674 current_link_up = 0;
2675 current_speed = SPEED_INVALID;
2676 current_duplex = DUPLEX_INVALID;
2677
2678 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2679 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2680
2681 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2682
2683 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2684 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2685 /* do nothing, just check for link up at the end */
2686 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2687 u32 adv, new_adv;
2688
2689 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2690 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2691 ADVERTISE_1000XPAUSE |
2692 ADVERTISE_1000XPSE_ASYM |
2693 ADVERTISE_SLCT);
2694
2695 /* Always advertise symmetric PAUSE just like copper */
2696 new_adv |= ADVERTISE_1000XPAUSE;
2697
2698 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2699 new_adv |= ADVERTISE_1000XHALF;
2700 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2701 new_adv |= ADVERTISE_1000XFULL;
2702
2703 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2704 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2705 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2706 tg3_writephy(tp, MII_BMCR, bmcr);
2707
2708 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2709 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2710 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2711
2712 return err;
2713 }
2714 } else {
2715 u32 new_bmcr;
2716
2717 bmcr &= ~BMCR_SPEED1000;
2718 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2719
2720 if (tp->link_config.duplex == DUPLEX_FULL)
2721 new_bmcr |= BMCR_FULLDPLX;
2722
2723 if (new_bmcr != bmcr) {
2724 /* BMCR_SPEED1000 is a reserved bit that needs
2725 * to be set on write.
2726 */
2727 new_bmcr |= BMCR_SPEED1000;
2728
2729 /* Force a linkdown */
2730 if (netif_carrier_ok(tp->dev)) {
2731 u32 adv;
2732
2733 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2734 adv &= ~(ADVERTISE_1000XFULL |
2735 ADVERTISE_1000XHALF |
2736 ADVERTISE_SLCT);
2737 tg3_writephy(tp, MII_ADVERTISE, adv);
2738 tg3_writephy(tp, MII_BMCR, bmcr |
2739 BMCR_ANRESTART |
2740 BMCR_ANENABLE);
2741 udelay(10);
2742 netif_carrier_off(tp->dev);
2743 }
2744 tg3_writephy(tp, MII_BMCR, new_bmcr);
2745 bmcr = new_bmcr;
2746 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2747 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2748 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2749 }
2750 }
2751
2752 if (bmsr & BMSR_LSTATUS) {
2753 current_speed = SPEED_1000;
2754 current_link_up = 1;
2755 if (bmcr & BMCR_FULLDPLX)
2756 current_duplex = DUPLEX_FULL;
2757 else
2758 current_duplex = DUPLEX_HALF;
2759
2760 if (bmcr & BMCR_ANENABLE) {
2761 u32 local_adv, remote_adv, common;
2762
2763 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2764 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2765 common = local_adv & remote_adv;
2766 if (common & (ADVERTISE_1000XHALF |
2767 ADVERTISE_1000XFULL)) {
2768 if (common & ADVERTISE_1000XFULL)
2769 current_duplex = DUPLEX_FULL;
2770 else
2771 current_duplex = DUPLEX_HALF;
2772
2773 tg3_setup_flow_control(tp, local_adv,
2774 remote_adv);
2775 }
2776 else
2777 current_link_up = 0;
2778 }
2779 }
2780
2781 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2782 if (tp->link_config.active_duplex == DUPLEX_HALF)
2783 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2784
2785 tw32_f(MAC_MODE, tp->mac_mode);
2786 udelay(40);
2787
2788 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2789
2790 tp->link_config.active_speed = current_speed;
2791 tp->link_config.active_duplex = current_duplex;
2792
2793 if (current_link_up != netif_carrier_ok(tp->dev)) {
2794 if (current_link_up)
2795 netif_carrier_on(tp->dev);
2796 else {
2797 netif_carrier_off(tp->dev);
2798 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2799 }
2800 tg3_link_report(tp);
2801 }
2802 return err;
2803}
2804
2805static void tg3_serdes_parallel_detect(struct tg3 *tp)
2806{
2807 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2808 /* Give autoneg time to complete. */
2809 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2810 return;
2811 }
2812 if (!netif_carrier_ok(tp->dev) &&
2813 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2814 u32 bmcr;
2815
2816 tg3_readphy(tp, MII_BMCR, &bmcr);
2817 if (bmcr & BMCR_ANENABLE) {
2818 u32 phy1, phy2;
2819
2820 /* Select shadow register 0x1f */
2821 tg3_writephy(tp, 0x1c, 0x7c00);
2822 tg3_readphy(tp, 0x1c, &phy1);
2823
2824 /* Select expansion interrupt status register */
2825 tg3_writephy(tp, 0x17, 0x0f01);
2826 tg3_readphy(tp, 0x15, &phy2);
2827 tg3_readphy(tp, 0x15, &phy2);
2828
2829 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2830 /* We have signal detect and not receiving
2831 * config code words, link is up by parallel
2832 * detection.
2833 */
2834
2835 bmcr &= ~BMCR_ANENABLE;
2836 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2837 tg3_writephy(tp, MII_BMCR, bmcr);
2838 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2839 }
2840 }
2841 }
2842 else if (netif_carrier_ok(tp->dev) &&
2843 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2844 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2845 u32 phy2;
2846
2847 /* Select expansion interrupt status register */
2848 tg3_writephy(tp, 0x17, 0x0f01);
2849 tg3_readphy(tp, 0x15, &phy2);
2850 if (phy2 & 0x20) {
2851 u32 bmcr;
2852
2853 /* Config code words received, turn on autoneg. */
2854 tg3_readphy(tp, MII_BMCR, &bmcr);
2855 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2856
2857 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2858
2859 }
2860 }
2861}
2862
1da177e4
LT		 2863static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2864{
2865 int err;
2866
2867 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2868 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2869 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2870 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2871 } else {
2872 err = tg3_setup_copper_phy(tp, force_reset);
2873 }
2874
2875 if (tp->link_config.active_speed == SPEED_1000 &&
2876 tp->link_config.active_duplex == DUPLEX_HALF)
2877 tw32(MAC_TX_LENGTHS,
2878 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2879 (6 << TX_LENGTHS_IPG_SHIFT) |
2880 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2881 else
2882 tw32(MAC_TX_LENGTHS,
2883 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2884 (6 << TX_LENGTHS_IPG_SHIFT) |
2885 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2886
2887 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2888 if (netif_carrier_ok(tp->dev)) {
2889 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 2890 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 2891 } else {
2892 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2893 }
2894 }
2895
2896 return err;
2897}
2898
2899/* Tigon3 never reports partial packet sends. So we do not
2900 * need special logic to handle SKBs that have not had all
2901 * of their frags sent yet, like SunGEM does.
2902 */
2903static void tg3_tx(struct tg3 *tp)
2904{
2905 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2906 u32 sw_idx = tp->tx_cons;
2907
2908 while (sw_idx != hw_idx) {
2909 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2910 struct sk_buff *skb = ri->skb;
2911 int i;
2912
2913 if (unlikely(skb == NULL))
2914 BUG();
2915
2916 pci_unmap_single(tp->pdev,
2917 pci_unmap_addr(ri, mapping),
2918 skb_headlen(skb),
2919 PCI_DMA_TODEVICE);
2920
2921 ri->skb = NULL;
2922
2923 sw_idx = NEXT_TX(sw_idx);
2924
2925 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2926 if (unlikely(sw_idx == hw_idx))
2927 BUG();
2928
2929 ri = &tp->tx_buffers[sw_idx];
2930 if (unlikely(ri->skb != NULL))
2931 BUG();
2932
2933 pci_unmap_page(tp->pdev,
2934 pci_unmap_addr(ri, mapping),
2935 skb_shinfo(skb)->frags[i].size,
2936 PCI_DMA_TODEVICE);
2937
2938 sw_idx = NEXT_TX(sw_idx);
2939 }
2940
f47c11ee 2941 dev_kfree_skb(skb);
1da177e4
LT		 2942 }
2943
2944 tp->tx_cons = sw_idx;
2945
51b91468
MC		 2946 if (unlikely(netif_queue_stopped(tp->dev))) {
2947 spin_lock(&tp->tx_lock);
2948 if (netif_queue_stopped(tp->dev) &&
2949 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2950 netif_wake_queue(tp->dev);
2951 spin_unlock(&tp->tx_lock);
2952 }
1da177e4
LT		 2953}
2954
2955/* Returns size of skb allocated or < 0 on error.
2956 *
2957 * We only need to fill in the address because the other members
2958 * of the RX descriptor are invariant, see tg3_init_rings.
2959 *
2960 * Note the purposeful assymetry of cpu vs. chip accesses. For
2961 * posting buffers we only dirty the first cache line of the RX
2962 * descriptor (containing the address). Whereas for the RX status
2963 * buffers the cpu only reads the last cacheline of the RX descriptor
2964 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2965 */
2966static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2967 int src_idx, u32 dest_idx_unmasked)
2968{
2969 struct tg3_rx_buffer_desc *desc;
2970 struct ring_info *map, *src_map;
2971 struct sk_buff *skb;
2972 dma_addr_t mapping;
2973 int skb_size, dest_idx;
2974
2975 src_map = NULL;
2976 switch (opaque_key) {
2977 case RXD_OPAQUE_RING_STD:
2978 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2979 desc = &tp->rx_std[dest_idx];
2980 map = &tp->rx_std_buffers[dest_idx];
2981 if (src_idx >= 0)
2982 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 2983 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 2984 break;
2985
2986 case RXD_OPAQUE_RING_JUMBO:
2987 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2988 desc = &tp->rx_jumbo[dest_idx];
2989 map = &tp->rx_jumbo_buffers[dest_idx];
2990 if (src_idx >= 0)
2991 src_map = &tp->rx_jumbo_buffers[src_idx];
2992 skb_size = RX_JUMBO_PKT_BUF_SZ;
2993 break;
2994
2995 default:
2996 return -EINVAL;
2997 };
2998
2999 /* Do not overwrite any of the map or rp information
3000 * until we are sure we can commit to a new buffer.
3001 *
3002 * Callers depend upon this behavior and assume that
3003 * we leave everything unchanged if we fail.
3004 */
3005 skb = dev_alloc_skb(skb_size);
3006 if (skb == NULL)
3007 return -ENOMEM;
3008
3009 skb->dev = tp->dev;
3010 skb_reserve(skb, tp->rx_offset);
3011
3012 mapping = pci_map_single(tp->pdev, skb->data,
3013 skb_size - tp->rx_offset,
3014 PCI_DMA_FROMDEVICE);
3015
3016 map->skb = skb;
3017 pci_unmap_addr_set(map, mapping, mapping);
3018
3019 if (src_map != NULL)
3020 src_map->skb = NULL;
3021
3022 desc->addr_hi = ((u64)mapping >> 32);
3023 desc->addr_lo = ((u64)mapping & 0xffffffff);
3024
3025 return skb_size;
3026}
3027
3028/* We only need to move over in the address because the other
3029 * members of the RX descriptor are invariant. See notes above
3030 * tg3_alloc_rx_skb for full details.
3031 */
3032static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3033 int src_idx, u32 dest_idx_unmasked)
3034{
3035 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3036 struct ring_info *src_map, *dest_map;
3037 int dest_idx;
3038
3039 switch (opaque_key) {
3040 case RXD_OPAQUE_RING_STD:
3041 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3042 dest_desc = &tp->rx_std[dest_idx];
3043 dest_map = &tp->rx_std_buffers[dest_idx];
3044 src_desc = &tp->rx_std[src_idx];
3045 src_map = &tp->rx_std_buffers[src_idx];
3046 break;
3047
3048 case RXD_OPAQUE_RING_JUMBO:
3049 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3050 dest_desc = &tp->rx_jumbo[dest_idx];
3051 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3052 src_desc = &tp->rx_jumbo[src_idx];
3053 src_map = &tp->rx_jumbo_buffers[src_idx];
3054 break;
3055
3056 default:
3057 return;
3058 };
3059
3060 dest_map->skb = src_map->skb;
3061 pci_unmap_addr_set(dest_map, mapping,
3062 pci_unmap_addr(src_map, mapping));
3063 dest_desc->addr_hi = src_desc->addr_hi;
3064 dest_desc->addr_lo = src_desc->addr_lo;
3065
3066 src_map->skb = NULL;
3067}
3068
3069#if TG3_VLAN_TAG_USED
3070static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3071{
3072 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3073}
3074#endif
3075
3076/* The RX ring scheme is composed of multiple rings which post fresh
3077 * buffers to the chip, and one special ring the chip uses to report
3078 * status back to the host.
3079 *
3080 * The special ring reports the status of received packets to the
3081 * host. The chip does not write into the original descriptor the
3082 * RX buffer was obtained from. The chip simply takes the original
3083 * descriptor as provided by the host, updates the status and length
3084 * field, then writes this into the next status ring entry.
3085 *
3086 * Each ring the host uses to post buffers to the chip is described
3087 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3088 * it is first placed into the on-chip ram. When the packet's length
3089 * is known, it walks down the TG3_BDINFO entries to select the ring.
3090 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3091 * which is within the range of the new packet's length is chosen.
3092 *
3093 * The "separate ring for rx status" scheme may sound queer, but it makes
3094 * sense from a cache coherency perspective. If only the host writes
3095 * to the buffer post rings, and only the chip writes to the rx status
3096 * rings, then cache lines never move beyond shared-modified state.
3097 * If both the host and chip were to write into the same ring, cache line
3098 * eviction could occur since both entities want it in an exclusive state.
3099 */
3100static int tg3_rx(struct tg3 *tp, int budget)
3101{
3102 u32 work_mask;
483ba50b
MC		 3103 u32 sw_idx = tp->rx_rcb_ptr;
3104 u16 hw_idx;
1da177e4
LT		 3105 int received;
3106
3107 hw_idx = tp->hw_status->idx[0].rx_producer;
3108 /*
3109 * We need to order the read of hw_idx and the read of
3110 * the opaque cookie.
3111 */
3112 rmb();
1da177e4
LT		 3113 work_mask = 0;
3114 received = 0;
3115 while (sw_idx != hw_idx && budget > 0) {
3116 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3117 unsigned int len;
3118 struct sk_buff *skb;
3119 dma_addr_t dma_addr;
3120 u32 opaque_key, desc_idx, *post_ptr;
3121
3122 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3123 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3124 if (opaque_key == RXD_OPAQUE_RING_STD) {
3125 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3126 mapping);
3127 skb = tp->rx_std_buffers[desc_idx].skb;
3128 post_ptr = &tp->rx_std_ptr;
3129 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3130 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3131 mapping);
3132 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3133 post_ptr = &tp->rx_jumbo_ptr;
3134 }
3135 else {
3136 goto next_pkt_nopost;
3137 }
3138
3139 work_mask |= opaque_key;
3140
3141 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3142 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3143 drop_it:
3144 tg3_recycle_rx(tp, opaque_key,
3145 desc_idx, *post_ptr);
3146 drop_it_no_recycle:
3147 /* Other statistics kept track of by card. */
3148 tp->net_stats.rx_dropped++;
3149 goto next_pkt;
3150 }
3151
3152 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3153
3154 if (len > RX_COPY_THRESHOLD
3155 && tp->rx_offset == 2
3156 /* rx_offset != 2 iff this is a 5701 card running
3157 * in PCI-X mode [see tg3_get_invariants()] */
3158 ) {
3159 int skb_size;
3160
3161 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3162 desc_idx, *post_ptr);
3163 if (skb_size < 0)
3164 goto drop_it;
3165
3166 pci_unmap_single(tp->pdev, dma_addr,
3167 skb_size - tp->rx_offset,
3168 PCI_DMA_FROMDEVICE);
3169
3170 skb_put(skb, len);
3171 } else {
3172 struct sk_buff *copy_skb;
3173
3174 tg3_recycle_rx(tp, opaque_key,
3175 desc_idx, *post_ptr);
3176
3177 copy_skb = dev_alloc_skb(len + 2);
3178 if (copy_skb == NULL)
3179 goto drop_it_no_recycle;
3180
3181 copy_skb->dev = tp->dev;
3182 skb_reserve(copy_skb, 2);
3183 skb_put(copy_skb, len);
3184 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3185 memcpy(copy_skb->data, skb->data, len);
3186 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3187
3188 /* We'll reuse the original ring buffer. */
3189 skb = copy_skb;
3190 }
3191
3192 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3193 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3194 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3195 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3196 skb->ip_summed = CHECKSUM_UNNECESSARY;
3197 else
3198 skb->ip_summed = CHECKSUM_NONE;
3199
3200 skb->protocol = eth_type_trans(skb, tp->dev);
3201#if TG3_VLAN_TAG_USED
3202 if (tp->vlgrp != NULL &&
3203 desc->type_flags & RXD_FLAG_VLAN) {
3204 tg3_vlan_rx(tp, skb,
3205 desc->err_vlan & RXD_VLAN_MASK);
3206 } else
3207#endif
3208 netif_receive_skb(skb);
3209
3210 tp->dev->last_rx = jiffies;
3211 received++;
3212 budget--;
3213
3214next_pkt:
3215 (*post_ptr)++;
3216next_pkt_nopost:
483ba50b
MC		 3217 sw_idx++;
3218 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
52f6d697
MC		 3219
3220 /* Refresh hw_idx to see if there is new work */
3221 if (sw_idx == hw_idx) {
3222 hw_idx = tp->hw_status->idx[0].rx_producer;
3223 rmb();
3224 }
1da177e4
LT		 3225 }
3226
3227 /* ACK the status ring. */
483ba50b
MC		 3228 tp->rx_rcb_ptr = sw_idx;
3229 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3230
3231 /* Refill RX ring(s). */
3232 if (work_mask & RXD_OPAQUE_RING_STD) {
3233 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3234 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3235 sw_idx);
3236 }
3237 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3238 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3239 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3240 sw_idx);
3241 }
3242 mmiowb();
3243
3244 return received;
3245}
3246
3247static int tg3_poll(struct net_device *netdev, int *budget)
3248{
3249 struct tg3 *tp = netdev_priv(netdev);
3250 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3251 int done;
3252
1da177e4
LT		 3253 /* handle link change and other phy events */
3254 if (!(tp->tg3_flags &
3255 (TG3_FLAG_USE_LINKCHG_REG |
3256 TG3_FLAG_POLL_SERDES))) {
3257 if (sblk->status & SD_STATUS_LINK_CHG) {
3258 sblk->status = SD_STATUS_UPDATED |
3259 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3260 spin_lock(&tp->lock);
1da177e4 3261 tg3_setup_phy(tp, 0);
f47c11ee 3262 spin_unlock(&tp->lock);
1da177e4
LT		 3263 }
3264 }
3265
3266 /* run TX completion thread */
3267 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3268 tg3_tx(tp);
1da177e4
LT		 3269 }
3270
1da177e4
LT		 3271 /* run RX thread, within the bounds set by NAPI.
3272 * All RX "locking" is done by ensuring outside
3273 * code synchronizes with dev->poll()
3274 */
1da177e4
LT		 3275 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3276 int orig_budget = *budget;
3277 int work_done;
3278
3279 if (orig_budget > netdev->quota)
3280 orig_budget = netdev->quota;
3281
3282 work_done = tg3_rx(tp, orig_budget);
3283
3284 *budget -= work_done;
3285 netdev->quota -= work_done;
1da177e4
LT		 3286 }
3287
38f3843e 3288 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
f7383c22 3289 tp->last_tag = sblk->status_tag;
38f3843e
MC		 3290 rmb();
3291 } else
3292 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3293
1da177e4 3294 /* if no more work, tell net stack and NIC we're done */
f7383c22 3295 done = !tg3_has_work(tp);
1da177e4 3296 if (done) {
f47c11ee 3297 netif_rx_complete(netdev);
1da177e4 3298 tg3_restart_ints(tp);
1da177e4
LT		 3299 }
3300
3301 return (done ? 0 : 1);
3302}
3303
f47c11ee
DM		 3304static void tg3_irq_quiesce(struct tg3 *tp)
3305{
3306 BUG_ON(tp->irq_sync);
3307
3308 tp->irq_sync = 1;
3309 smp_mb();
3310
3311 synchronize_irq(tp->pdev->irq);
3312}
3313
3314static inline int tg3_irq_sync(struct tg3 *tp)
3315{
3316 return tp->irq_sync;
3317}
3318
3319/* Fully shutdown all tg3 driver activity elsewhere in the system.
3320 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3321 * with as well. Most of the time, this is not necessary except when
3322 * shutting down the device.
3323 */
3324static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3325{
3326 if (irq_sync)
3327 tg3_irq_quiesce(tp);
3328 spin_lock_bh(&tp->lock);
3329 spin_lock(&tp->tx_lock);
3330}
3331
3332static inline void tg3_full_unlock(struct tg3 *tp)
3333{
3334 spin_unlock(&tp->tx_lock);
3335 spin_unlock_bh(&tp->lock);
3336}
3337
88b06bc2
MC		 3338/* MSI ISR - No need to check for interrupt sharing and no need to
3339 * flush status block and interrupt mailbox. PCI ordering rules
3340 * guarantee that MSI will arrive after the status block.
3341 */
3342static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3343{
3344 struct net_device *dev = dev_id;
3345 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3346
61487480
MC		 3347 prefetch(tp->hw_status);
3348 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3349 /*
fac9b83e 3350 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3351 * chip-internal interrupt pending events.
fac9b83e 3352 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3353 * NIC to stop sending us irqs, engaging "in-intr-handler"
3354 * event coalescing.
3355 */
3356 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3357 if (likely(!tg3_irq_sync(tp)))
88b06bc2 3358 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3359
88b06bc2
MC		 3360 return IRQ_RETVAL(1);
3361}
3362
1da177e4
LT		 3363static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3364{
3365 struct net_device *dev = dev_id;
3366 struct tg3 *tp = netdev_priv(dev);
3367 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3368 unsigned int handled = 1;
3369
1da177e4
LT		 3370 /* In INTx mode, it is possible for the interrupt to arrive at
3371 * the CPU before the status block posted prior to the interrupt.
3372 * Reading the PCI State register will confirm whether the
3373 * interrupt is ours and will flush the status block.
3374 */
3375 if ((sblk->status & SD_STATUS_UPDATED) ||
3376 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3377 /*
fac9b83e 3378 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 3379 * chip-internal interrupt pending events.
fac9b83e 3380 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 3381 * NIC to stop sending us irqs, engaging "in-intr-handler"
3382 * event coalescing.
3383 */
3384 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3385 0x00000001);
f47c11ee
DM		 3386 if (tg3_irq_sync(tp))
3387 goto out;
fac9b83e 3388 sblk->status &= ~SD_STATUS_UPDATED;
61487480
MC		 3389 if (likely(tg3_has_work(tp))) {
3390 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
fac9b83e 3391 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3392 } else {
fac9b83e
DM		 3393 /* No work, shared interrupt perhaps? re-enable
3394 * interrupts, and flush that PCI write
3395 */
09ee929c 3396 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3397 0x00000000);
fac9b83e
DM		 3398 }
3399 } else { /* shared interrupt */
3400 handled = 0;
3401 }
f47c11ee 3402out:
fac9b83e
DM		 3403 return IRQ_RETVAL(handled);
3404}
3405
3406static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3407{
3408 struct net_device *dev = dev_id;
3409 struct tg3 *tp = netdev_priv(dev);
3410 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3411 unsigned int handled = 1;
3412
fac9b83e
DM		 3413 /* In INTx mode, it is possible for the interrupt to arrive at
3414 * the CPU before the status block posted prior to the interrupt.
3415 * Reading the PCI State register will confirm whether the
3416 * interrupt is ours and will flush the status block.
3417 */
38f3843e 3418 if ((sblk->status_tag != tp->last_tag) ||
fac9b83e 3419 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3420 /*
fac9b83e
DM		 3421 * writing any value to intr-mbox-0 clears PCI INTA# and
3422 * chip-internal interrupt pending events.
3423 * writing non-zero to intr-mbox-0 additional tells the
3424 * NIC to stop sending us irqs, engaging "in-intr-handler"
3425 * event coalescing.
1da177e4 3426 */
fac9b83e
DM		 3427 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3428 0x00000001);
f47c11ee
DM		 3429 if (tg3_irq_sync(tp))
3430 goto out;
38f3843e 3431 if (netif_rx_schedule_prep(dev)) {
61487480 3432 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
38f3843e
MC		 3433 /* Update last_tag to mark that this status has been
3434 * seen. Because interrupt may be shared, we may be
3435 * racing with tg3_poll(), so only update last_tag
3436 * if tg3_poll() is not scheduled.
1da177e4 3437 */
38f3843e
MC		 3438 tp->last_tag = sblk->status_tag;
3439 __netif_rx_schedule(dev);
1da177e4
LT		 3440 }
3441 } else { /* shared interrupt */
3442 handled = 0;
3443 }
f47c11ee 3444out:
1da177e4
LT		 3445 return IRQ_RETVAL(handled);
3446}
3447
7938109f
MC		 3448/* ISR for interrupt test */
3449static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3450 struct pt_regs *regs)
3451{
3452 struct net_device *dev = dev_id;
3453 struct tg3 *tp = netdev_priv(dev);
3454 struct tg3_hw_status *sblk = tp->hw_status;
3455
f9804ddb
MC		 3456 if ((sblk->status & SD_STATUS_UPDATED) ||
3457 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7938109f
MC		 3458 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3459 0x00000001);
3460 return IRQ_RETVAL(1);
3461 }
3462 return IRQ_RETVAL(0);
3463}
3464
1da177e4 3465static int tg3_init_hw(struct tg3 *);
944d980e 3466static int tg3_halt(struct tg3 *, int, int);
1da177e4
LT		 3467
3468#ifdef CONFIG_NET_POLL_CONTROLLER
3469static void tg3_poll_controller(struct net_device *dev)
3470{
88b06bc2
MC		 3471 struct tg3 *tp = netdev_priv(dev);
3472
3473 tg3_interrupt(tp->pdev->irq, dev, NULL);
1da177e4
LT		 3474}
3475#endif
3476
3477static void tg3_reset_task(void *_data)
3478{
3479 struct tg3 *tp = _data;
3480 unsigned int restart_timer;
3481
3482 tg3_netif_stop(tp);
3483
f47c11ee 3484 tg3_full_lock(tp, 1);
1da177e4
LT		 3485
3486 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3487 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3488
944d980e 3489 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
1da177e4
LT		 3490 tg3_init_hw(tp);
3491
3492 tg3_netif_start(tp);
3493
f47c11ee 3494 tg3_full_unlock(tp);
1da177e4
LT		 3495
3496 if (restart_timer)
3497 mod_timer(&tp->timer, jiffies + 1);
3498}
3499
3500static void tg3_tx_timeout(struct net_device *dev)
3501{
3502 struct tg3 *tp = netdev_priv(dev);
3503
3504 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3505 dev->name);
3506
3507 schedule_work(&tp->reset_task);
3508}
3509
c58ec932
MC		 3510/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3511static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3512{
3513 u32 base = (u32) mapping & 0xffffffff;
3514
3515 return ((base > 0xffffdcc0) &&
3516 (base + len + 8 < base));
3517}
3518
1da177e4
LT		 3519static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3520
3521static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3522 u32 last_plus_one, u32 *start,
3523 u32 base_flags, u32 mss)
1da177e4
LT		 3524{
3525 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3526 dma_addr_t new_addr = 0;
1da177e4 3527 u32 entry = *start;
c58ec932 3528 int i, ret = 0;
1da177e4
LT		 3529
3530 if (!new_skb) {
c58ec932
MC		 3531 ret = -1;
3532 } else {
3533 /* New SKB is guaranteed to be linear. */
3534 entry = *start;
3535 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3536 PCI_DMA_TODEVICE);
3537 /* Make sure new skb does not cross any 4G boundaries.
3538 * Drop the packet if it does.
3539 */
3540 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3541 ret = -1;
3542 dev_kfree_skb(new_skb);
3543 new_skb = NULL;
3544 } else {
3545 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3546 base_flags, 1 | (mss << 1));
3547 *start = NEXT_TX(entry);
3548 }
1da177e4
LT		 3549 }
3550
1da177e4
LT		 3551 /* Now clean up the sw ring entries. */
3552 i = 0;
3553 while (entry != last_plus_one) {
3554 int len;
3555
3556 if (i == 0)
3557 len = skb_headlen(skb);
3558 else
3559 len = skb_shinfo(skb)->frags[i-1].size;
3560 pci_unmap_single(tp->pdev,
3561 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3562 len, PCI_DMA_TODEVICE);
3563 if (i == 0) {
3564 tp->tx_buffers[entry].skb = new_skb;
3565 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3566 } else {
3567 tp->tx_buffers[entry].skb = NULL;
3568 }
3569 entry = NEXT_TX(entry);
3570 i++;
3571 }
3572
3573 dev_kfree_skb(skb);
3574
c58ec932 3575 return ret;
1da177e4
LT		 3576}
3577
3578static void tg3_set_txd(struct tg3 *tp, int entry,
3579 dma_addr_t mapping, int len, u32 flags,
3580 u32 mss_and_is_end)
3581{
3582 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3583 int is_end = (mss_and_is_end & 0x1);
3584 u32 mss = (mss_and_is_end >> 1);
3585 u32 vlan_tag = 0;
3586
3587 if (is_end)
3588 flags |= TXD_FLAG_END;
3589 if (flags & TXD_FLAG_VLAN) {
3590 vlan_tag = flags >> 16;
3591 flags &= 0xffff;
3592 }
3593 vlan_tag |= (mss << TXD_MSS_SHIFT);
3594
3595 txd->addr_hi = ((u64) mapping >> 32);
3596 txd->addr_lo = ((u64) mapping & 0xffffffff);
3597 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3598 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3599}
3600
1da177e4
LT		 3601static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3602{
3603 struct tg3 *tp = netdev_priv(dev);
3604 dma_addr_t mapping;
1da177e4
LT		 3605 u32 len, entry, base_flags, mss;
3606 int would_hit_hwbug;
1da177e4
LT		 3607
3608 len = skb_headlen(skb);
3609
3610 /* No BH disabling for tx_lock here. We are running in BH disabled
3611 * context and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 3612 * interrupt. Furthermore, IRQ processing runs lockless so we have
3613 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 3614 */
f47c11ee 3615 if (!spin_trylock(&tp->tx_lock))
1da177e4 3616 return NETDEV_TX_LOCKED;
1da177e4 3617
1da177e4 3618 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 3619 if (!netif_queue_stopped(dev)) {
3620 netif_stop_queue(dev);
3621
3622 /* This is a hard error, log it. */
3623 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3624 "queue awake!\n", dev->name);
3625 }
f47c11ee 3626 spin_unlock(&tp->tx_lock);
1da177e4
LT		 3627 return NETDEV_TX_BUSY;
3628 }
3629
3630 entry = tp->tx_prod;
3631 base_flags = 0;
3632 if (skb->ip_summed == CHECKSUM_HW)
3633 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3634#if TG3_TSO_SUPPORT != 0
3635 mss = 0;
3636 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3637 (mss = skb_shinfo(skb)->tso_size) != 0) {
3638 int tcp_opt_len, ip_tcp_len;
3639
3640 if (skb_header_cloned(skb) &&
3641 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3642 dev_kfree_skb(skb);
3643 goto out_unlock;
3644 }
3645
3646 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3647 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3648
3649 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3650 TXD_FLAG_CPU_POST_DMA);
3651
3652 skb->nh.iph->check = 0;
3653 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3654 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3655 skb->h.th->check = 0;
3656 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3657 }
3658 else {
3659 skb->h.th->check =
3660 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3661 skb->nh.iph->daddr,
3662 0, IPPROTO_TCP, 0);
3663 }
3664
3665 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3666 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3667 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3668 int tsflags;
3669
3670 tsflags = ((skb->nh.iph->ihl - 5) +
3671 (tcp_opt_len >> 2));
3672 mss |= (tsflags << 11);
3673 }
3674 } else {
3675 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3676 int tsflags;
3677
3678 tsflags = ((skb->nh.iph->ihl - 5) +
3679 (tcp_opt_len >> 2));
3680 base_flags |= tsflags << 12;
3681 }
3682 }
3683 }
3684#else
3685 mss = 0;
3686#endif
3687#if TG3_VLAN_TAG_USED
3688 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3689 base_flags |= (TXD_FLAG_VLAN |
3690 (vlan_tx_tag_get(skb) << 16));
3691#endif
3692
3693 /* Queue skb data, a.k.a. the main skb fragment. */
3694 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3695
3696 tp->tx_buffers[entry].skb = skb;
3697 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3698
3699 would_hit_hwbug = 0;
3700
3701 if (tg3_4g_overflow_test(mapping, len))
c58ec932 3702 would_hit_hwbug = 1;
1da177e4
LT		 3703
3704 tg3_set_txd(tp, entry, mapping, len, base_flags,
3705 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3706
3707 entry = NEXT_TX(entry);
3708
3709 /* Now loop through additional data fragments, and queue them. */
3710 if (skb_shinfo(skb)->nr_frags > 0) {
3711 unsigned int i, last;
3712
3713 last = skb_shinfo(skb)->nr_frags - 1;
3714 for (i = 0; i <= last; i++) {
3715 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3716
3717 len = frag->size;
3718 mapping = pci_map_page(tp->pdev,
3719 frag->page,
3720 frag->page_offset,
3721 len, PCI_DMA_TODEVICE);
3722
3723 tp->tx_buffers[entry].skb = NULL;
3724 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3725
c58ec932
MC		 3726 if (tg3_4g_overflow_test(mapping, len))
3727 would_hit_hwbug = 1;
1da177e4
LT		 3728
3729 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3730 tg3_set_txd(tp, entry, mapping, len,
3731 base_flags, (i == last)|(mss << 1));
3732 else
3733 tg3_set_txd(tp, entry, mapping, len,
3734 base_flags, (i == last));
3735
3736 entry = NEXT_TX(entry);
3737 }
3738 }
3739
3740 if (would_hit_hwbug) {
3741 u32 last_plus_one = entry;
3742 u32 start;
1da177e4 3743
c58ec932
MC		 3744 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3745 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 3746
3747 /* If the workaround fails due to memory/mapping
3748 * failure, silently drop this packet.
3749 */
c58ec932
MC		 3750 if (tigon3_4gb_hwbug_workaround(tp, skb, last_plus_one,
3751 &start, base_flags, mss))
1da177e4
LT		 3752 goto out_unlock;
3753
3754 entry = start;
3755 }
3756
3757 /* Packets are ready, update Tx producer idx local and on card. */
3758 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3759
3760 tp->tx_prod = entry;
51b91468 3761 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
1da177e4 3762 netif_stop_queue(dev);
51b91468
MC		 3763 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3764 netif_wake_queue(tp->dev);
3765 }
1da177e4
LT		 3766
3767out_unlock:
3768 mmiowb();
f47c11ee 3769 spin_unlock(&tp->tx_lock);
1da177e4
LT		 3770
3771 dev->trans_start = jiffies;
3772
3773 return NETDEV_TX_OK;
3774}
3775
3776static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3777 int new_mtu)
3778{
3779 dev->mtu = new_mtu;
3780
ef7f5ec0 3781 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 3782 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 3783 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3784 ethtool_op_set_tso(dev, 0);
3785 }
3786 else
3787 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3788 } else {
a4e2b347 3789 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 3790 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 3791 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 3792 }
1da177e4
LT		 3793}
3794
3795static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3796{
3797 struct tg3 *tp = netdev_priv(dev);
3798
3799 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3800 return -EINVAL;
3801
3802 if (!netif_running(dev)) {
3803 /* We'll just catch it later when the
3804 * device is up'd.
3805 */
3806 tg3_set_mtu(dev, tp, new_mtu);
3807 return 0;
3808 }
3809
3810 tg3_netif_stop(tp);
f47c11ee
DM		 3811
3812 tg3_full_lock(tp, 1);
1da177e4 3813
944d980e 3814 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 3815
3816 tg3_set_mtu(dev, tp, new_mtu);
3817
3818 tg3_init_hw(tp);
3819
3820 tg3_netif_start(tp);
3821
f47c11ee 3822 tg3_full_unlock(tp);
1da177e4
LT		 3823
3824 return 0;
3825}
3826
3827/* Free up pending packets in all rx/tx rings.
3828 *
3829 * The chip has been shut down and the driver detached from
3830 * the networking, so no interrupts or new tx packets will
3831 * end up in the driver. tp->{tx,}lock is not held and we are not
3832 * in an interrupt context and thus may sleep.
3833 */
3834static void tg3_free_rings(struct tg3 *tp)
3835{
3836 struct ring_info *rxp;
3837 int i;
3838
3839 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3840 rxp = &tp->rx_std_buffers[i];
3841
3842 if (rxp->skb == NULL)
3843 continue;
3844 pci_unmap_single(tp->pdev,
3845 pci_unmap_addr(rxp, mapping),
7e72aad4 3846 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 3847 PCI_DMA_FROMDEVICE);
3848 dev_kfree_skb_any(rxp->skb);
3849 rxp->skb = NULL;
3850 }
3851
3852 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3853 rxp = &tp->rx_jumbo_buffers[i];
3854
3855 if (rxp->skb == NULL)
3856 continue;
3857 pci_unmap_single(tp->pdev,
3858 pci_unmap_addr(rxp, mapping),
3859 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3860 PCI_DMA_FROMDEVICE);
3861 dev_kfree_skb_any(rxp->skb);
3862 rxp->skb = NULL;
3863 }
3864
3865 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3866 struct tx_ring_info *txp;
3867 struct sk_buff *skb;
3868 int j;
3869
3870 txp = &tp->tx_buffers[i];
3871 skb = txp->skb;
3872
3873 if (skb == NULL) {
3874 i++;
3875 continue;
3876 }
3877
3878 pci_unmap_single(tp->pdev,
3879 pci_unmap_addr(txp, mapping),
3880 skb_headlen(skb),
3881 PCI_DMA_TODEVICE);
3882 txp->skb = NULL;
3883
3884 i++;
3885
3886 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3887 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3888 pci_unmap_page(tp->pdev,
3889 pci_unmap_addr(txp, mapping),
3890 skb_shinfo(skb)->frags[j].size,
3891 PCI_DMA_TODEVICE);
3892 i++;
3893 }
3894
3895 dev_kfree_skb_any(skb);
3896 }
3897}
3898
3899/* Initialize tx/rx rings for packet processing.
3900 *
3901 * The chip has been shut down and the driver detached from
3902 * the networking, so no interrupts or new tx packets will
3903 * end up in the driver. tp->{tx,}lock are held and thus
3904 * we may not sleep.
3905 */
3906static void tg3_init_rings(struct tg3 *tp)
3907{
3908 u32 i;
3909
3910 /* Free up all the SKBs. */
3911 tg3_free_rings(tp);
3912
3913 /* Zero out all descriptors. */
3914 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3915 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3916 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3917 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3918
7e72aad4 3919 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 3920 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 3921 (tp->dev->mtu > ETH_DATA_LEN))
3922 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3923
1da177e4
LT		 3924 /* Initialize invariants of the rings, we only set this
3925 * stuff once. This works because the card does not
3926 * write into the rx buffer posting rings.
3927 */
3928 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3929 struct tg3_rx_buffer_desc *rxd;
3930
3931 rxd = &tp->rx_std[i];
7e72aad4 3932 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 3933 << RXD_LEN_SHIFT;
3934 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3935 rxd->opaque = (RXD_OPAQUE_RING_STD |
3936 (i << RXD_OPAQUE_INDEX_SHIFT));
3937 }
3938
0f893dc6 3939 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 3940 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3941 struct tg3_rx_buffer_desc *rxd;
3942
3943 rxd = &tp->rx_jumbo[i];
3944 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3945 << RXD_LEN_SHIFT;
3946 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3947 RXD_FLAG_JUMBO;
3948 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3949 (i << RXD_OPAQUE_INDEX_SHIFT));
3950 }
3951 }
3952
3953 /* Now allocate fresh SKBs for each rx ring. */
3954 for (i = 0; i < tp->rx_pending; i++) {
3955 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3956 -1, i) < 0)
3957 break;
3958 }
3959
0f893dc6 3960 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 3961 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3962 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3963 -1, i) < 0)
3964 break;
3965 }
3966 }
3967}
3968
3969/*
3970 * Must not be invoked with interrupt sources disabled and
3971 * the hardware shutdown down.
3972 */
3973static void tg3_free_consistent(struct tg3 *tp)
3974{
b4558ea9
JJ		 3975 kfree(tp->rx_std_buffers);
3976 tp->rx_std_buffers = NULL;
1da177e4
LT		 3977 if (tp->rx_std) {
3978 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3979 tp->rx_std, tp->rx_std_mapping);
3980 tp->rx_std = NULL;
3981 }
3982 if (tp->rx_jumbo) {
3983 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3984 tp->rx_jumbo, tp->rx_jumbo_mapping);
3985 tp->rx_jumbo = NULL;
3986 }
3987 if (tp->rx_rcb) {
3988 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3989 tp->rx_rcb, tp->rx_rcb_mapping);
3990 tp->rx_rcb = NULL;
3991 }
3992 if (tp->tx_ring) {
3993 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3994 tp->tx_ring, tp->tx_desc_mapping);
3995 tp->tx_ring = NULL;
3996 }
3997 if (tp->hw_status) {
3998 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3999 tp->hw_status, tp->status_mapping);
4000 tp->hw_status = NULL;
4001 }
4002 if (tp->hw_stats) {
4003 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4004 tp->hw_stats, tp->stats_mapping);
4005 tp->hw_stats = NULL;
4006 }
4007}
4008
4009/*
4010 * Must not be invoked with interrupt sources disabled and
4011 * the hardware shutdown down. Can sleep.
4012 */
4013static int tg3_alloc_consistent(struct tg3 *tp)
4014{
4015 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4016 (TG3_RX_RING_SIZE +
4017 TG3_RX_JUMBO_RING_SIZE)) +
4018 (sizeof(struct tx_ring_info) *
4019 TG3_TX_RING_SIZE),
4020 GFP_KERNEL);
4021 if (!tp->rx_std_buffers)
4022 return -ENOMEM;
4023
4024 memset(tp->rx_std_buffers, 0,
4025 (sizeof(struct ring_info) *
4026 (TG3_RX_RING_SIZE +
4027 TG3_RX_JUMBO_RING_SIZE)) +
4028 (sizeof(struct tx_ring_info) *
4029 TG3_TX_RING_SIZE));
4030
4031 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4032 tp->tx_buffers = (struct tx_ring_info *)
4033 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4034
4035 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4036 &tp->rx_std_mapping);
4037 if (!tp->rx_std)
4038 goto err_out;
4039
4040 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4041 &tp->rx_jumbo_mapping);
4042
4043 if (!tp->rx_jumbo)
4044 goto err_out;
4045
4046 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4047 &tp->rx_rcb_mapping);
4048 if (!tp->rx_rcb)
4049 goto err_out;
4050
4051 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4052 &tp->tx_desc_mapping);
4053 if (!tp->tx_ring)
4054 goto err_out;
4055
4056 tp->hw_status = pci_alloc_consistent(tp->pdev,
4057 TG3_HW_STATUS_SIZE,
4058 &tp->status_mapping);
4059 if (!tp->hw_status)
4060 goto err_out;
4061
4062 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4063 sizeof(struct tg3_hw_stats),
4064 &tp->stats_mapping);
4065 if (!tp->hw_stats)
4066 goto err_out;
4067
4068 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4069 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4070
4071 return 0;
4072
4073err_out:
4074 tg3_free_consistent(tp);
4075 return -ENOMEM;
4076}
4077
4078#define MAX_WAIT_CNT 1000
4079
4080/* To stop a block, clear the enable bit and poll till it
4081 * clears. tp->lock is held.
4082 */
b3b7d6be 4083static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4084{
4085 unsigned int i;
4086 u32 val;
4087
4088 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4089 switch (ofs) {
4090 case RCVLSC_MODE:
4091 case DMAC_MODE:
4092 case MBFREE_MODE:
4093 case BUFMGR_MODE:
4094 case MEMARB_MODE:
4095 /* We can't enable/disable these bits of the
4096 * 5705/5750, just say success.
4097 */
4098 return 0;
4099
4100 default:
4101 break;
4102 };
4103 }
4104
4105 val = tr32(ofs);
4106 val &= ~enable_bit;
4107 tw32_f(ofs, val);
4108
4109 for (i = 0; i < MAX_WAIT_CNT; i++) {
4110 udelay(100);
4111 val = tr32(ofs);
4112 if ((val & enable_bit) == 0)
4113 break;
4114 }
4115
b3b7d6be 4116 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4117 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4118 "ofs=%lx enable_bit=%x\n",
4119 ofs, enable_bit);
4120 return -ENODEV;
4121 }
4122
4123 return 0;
4124}
4125
4126/* tp->lock is held. */
b3b7d6be 4127static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4128{
4129 int i, err;
4130
4131 tg3_disable_ints(tp);
4132
4133 tp->rx_mode &= ~RX_MODE_ENABLE;
4134 tw32_f(MAC_RX_MODE, tp->rx_mode);
4135 udelay(10);
4136
b3b7d6be
DM		 4137 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4138 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4139 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4140 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4141 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4142 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4143
4144 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4145 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4146 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4147 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4148 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4149 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4150 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4151
4152 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4153 tw32_f(MAC_MODE, tp->mac_mode);
4154 udelay(40);
4155
4156 tp->tx_mode &= ~TX_MODE_ENABLE;
4157 tw32_f(MAC_TX_MODE, tp->tx_mode);
4158
4159 for (i = 0; i < MAX_WAIT_CNT; i++) {
4160 udelay(100);
4161 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4162 break;
4163 }
4164 if (i >= MAX_WAIT_CNT) {
4165 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4166 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4167 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4168 err |= -ENODEV;
1da177e4
LT		 4169 }
4170
e6de8ad1 4171 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4172 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4173 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4174
4175 tw32(FTQ_RESET, 0xffffffff);
4176 tw32(FTQ_RESET, 0x00000000);
4177
b3b7d6be
DM		 4178 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4179 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4180
4181 if (tp->hw_status)
4182 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4183 if (tp->hw_stats)
4184 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4185
1da177e4
LT		 4186 return err;
4187}
4188
4189/* tp->lock is held. */
4190static int tg3_nvram_lock(struct tg3 *tp)
4191{
4192 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4193 int i;
4194
4195 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4196 for (i = 0; i < 8000; i++) {
4197 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4198 break;
4199 udelay(20);
4200 }
4201 if (i == 8000)
4202 return -ENODEV;
4203 }
4204 return 0;
4205}
4206
4207/* tp->lock is held. */
4208static void tg3_nvram_unlock(struct tg3 *tp)
4209{
4210 if (tp->tg3_flags & TG3_FLAG_NVRAM)
4211 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4212}
4213
e6af301b
MC		 4214/* tp->lock is held. */
4215static void tg3_enable_nvram_access(struct tg3 *tp)
4216{
4217 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4218 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4219 u32 nvaccess = tr32(NVRAM_ACCESS);
4220
4221 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4222 }
4223}
4224
4225/* tp->lock is held. */
4226static void tg3_disable_nvram_access(struct tg3 *tp)
4227{
4228 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4229 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4230 u32 nvaccess = tr32(NVRAM_ACCESS);
4231
4232 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4233 }
4234}
4235
1da177e4
LT		 4236/* tp->lock is held. */
4237static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4238{
4239 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4240 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4241 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4242
4243 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4244 switch (kind) {
4245 case RESET_KIND_INIT:
4246 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4247 DRV_STATE_START);
4248 break;
4249
4250 case RESET_KIND_SHUTDOWN:
4251 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4252 DRV_STATE_UNLOAD);
4253 break;
4254
4255 case RESET_KIND_SUSPEND:
4256 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4257 DRV_STATE_SUSPEND);
4258 break;
4259
4260 default:
4261 break;
4262 };
4263 }
4264}
4265
4266/* tp->lock is held. */
4267static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4268{
4269 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4270 switch (kind) {
4271 case RESET_KIND_INIT:
4272 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4273 DRV_STATE_START_DONE);
4274 break;
4275
4276 case RESET_KIND_SHUTDOWN:
4277 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4278 DRV_STATE_UNLOAD_DONE);
4279 break;
4280
4281 default:
4282 break;
4283 };
4284 }
4285}
4286
4287/* tp->lock is held. */
4288static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4289{
4290 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4291 switch (kind) {
4292 case RESET_KIND_INIT:
4293 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4294 DRV_STATE_START);
4295 break;
4296
4297 case RESET_KIND_SHUTDOWN:
4298 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4299 DRV_STATE_UNLOAD);
4300 break;
4301
4302 case RESET_KIND_SUSPEND:
4303 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4304 DRV_STATE_SUSPEND);
4305 break;
4306
4307 default:
4308 break;
4309 };
4310 }
4311}
4312
4313static void tg3_stop_fw(struct tg3 *);
4314
4315/* tp->lock is held. */
4316static int tg3_chip_reset(struct tg3 *tp)
4317{
4318 u32 val;
1ee582d8 4319 void (*write_op)(struct tg3 *, u32, u32);
1da177e4
LT		 4320 int i;
4321
4322 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4323 tg3_nvram_lock(tp);
4324
4325 /*
4326 * We must avoid the readl() that normally takes place.
4327 * It locks machines, causes machine checks, and other
4328 * fun things. So, temporarily disable the 5701
4329 * hardware workaround, while we do the reset.
4330 */
1ee582d8
MC		 4331 write_op = tp->write32;
4332 if (write_op == tg3_write_flush_reg32)
4333 tp->write32 = tg3_write32;
1da177e4
LT		 4334
4335 /* do the reset */
4336 val = GRC_MISC_CFG_CORECLK_RESET;
4337
4338 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4339 if (tr32(0x7e2c) == 0x60) {
4340 tw32(0x7e2c, 0x20);
4341 }
4342 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4343 tw32(GRC_MISC_CFG, (1 << 29));
4344 val |= (1 << 29);
4345 }
4346 }
4347
4348 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4349 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4350 tw32(GRC_MISC_CFG, val);
4351
1ee582d8
MC		 4352 /* restore 5701 hardware bug workaround write method */
4353 tp->write32 = write_op;
1da177e4
LT		 4354
4355 /* Unfortunately, we have to delay before the PCI read back.
4356 * Some 575X chips even will not respond to a PCI cfg access
4357 * when the reset command is given to the chip.
4358 *
4359 * How do these hardware designers expect things to work
4360 * properly if the PCI write is posted for a long period
4361 * of time? It is always necessary to have some method by
4362 * which a register read back can occur to push the write
4363 * out which does the reset.
4364 *
4365 * For most tg3 variants the trick below was working.
4366 * Ho hum...
4367 */
4368 udelay(120);
4369
4370 /* Flush PCI posted writes. The normal MMIO registers
4371 * are inaccessible at this time so this is the only
4372 * way to make this reliably (actually, this is no longer
4373 * the case, see above). I tried to use indirect
4374 * register read/write but this upset some 5701 variants.
4375 */
4376 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4377
4378 udelay(120);
4379
4380 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4381 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4382 int i;
4383 u32 cfg_val;
4384
4385 /* Wait for link training to complete. */
4386 for (i = 0; i < 5000; i++)
4387 udelay(100);
4388
4389 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4390 pci_write_config_dword(tp->pdev, 0xc4,
4391 cfg_val | (1 << 15));
4392 }
4393 /* Set PCIE max payload size and clear error status. */
4394 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4395 }
4396
4397 /* Re-enable indirect register accesses. */
4398 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4399 tp->misc_host_ctrl);
4400
4401 /* Set MAX PCI retry to zero. */
4402 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4403 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4404 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4405 val |= PCISTATE_RETRY_SAME_DMA;
4406 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4407
4408 pci_restore_state(tp->pdev);
4409
4410 /* Make sure PCI-X relaxed ordering bit is clear. */
4411 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4412 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4413 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4414
a4e2b347 4415 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f
MC		 4416 u32 val;
4417
4418 /* Chip reset on 5780 will reset MSI enable bit,
4419 * so need to restore it.
4420 */
4421 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4422 u16 ctrl;
4423
4424 pci_read_config_word(tp->pdev,
4425 tp->msi_cap + PCI_MSI_FLAGS,
4426 &ctrl);
4427 pci_write_config_word(tp->pdev,
4428 tp->msi_cap + PCI_MSI_FLAGS,
4429 ctrl | PCI_MSI_FLAGS_ENABLE);
4430 val = tr32(MSGINT_MODE);
4431 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4432 }
4433
4434 val = tr32(MEMARB_MODE);
4435 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4436
4437 } else
4438 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4439
4440 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4441 tg3_stop_fw(tp);
4442 tw32(0x5000, 0x400);
4443 }
4444
4445 tw32(GRC_MODE, tp->grc_mode);
4446
4447 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4448 u32 val = tr32(0xc4);
4449
4450 tw32(0xc4, val | (1 << 15));
4451 }
4452
4453 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4455 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4456 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4457 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4458 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4459 }
4460
4461 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4462 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4463 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4464 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4465 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4466 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4467 } else
4468 tw32_f(MAC_MODE, 0);
4469 udelay(40);
4470
4471 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4472 /* Wait for firmware initialization to complete. */
4473 for (i = 0; i < 100000; i++) {
4474 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4475 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4476 break;
4477 udelay(10);
4478 }
4479 if (i >= 100000) {
4480 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4481 "firmware will not restart magic=%08x\n",
4482 tp->dev->name, val);
4483 return -ENODEV;
4484 }
4485 }
4486
4487 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4488 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4489 u32 val = tr32(0x7c00);
4490
4491 tw32(0x7c00, val | (1 << 25));
4492 }
4493
4494 /* Reprobe ASF enable state. */
4495 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4496 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4497 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4498 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4499 u32 nic_cfg;
4500
4501 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4502 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4503 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4504 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4505 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4506 }
4507 }
4508
4509 return 0;
4510}
4511
4512/* tp->lock is held. */
4513static void tg3_stop_fw(struct tg3 *tp)
4514{
4515 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4516 u32 val;
4517 int i;
4518
4519 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4520 val = tr32(GRC_RX_CPU_EVENT);
4521 val |= (1 << 14);
4522 tw32(GRC_RX_CPU_EVENT, val);
4523
4524 /* Wait for RX cpu to ACK the event. */
4525 for (i = 0; i < 100; i++) {
4526 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4527 break;
4528 udelay(1);
4529 }
4530 }
4531}
4532
4533/* tp->lock is held. */
944d980e 4534static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 4535{
4536 int err;
4537
4538 tg3_stop_fw(tp);
4539
944d980e 4540 tg3_write_sig_pre_reset(tp, kind);
1da177e4 4541
b3b7d6be 4542 tg3_abort_hw(tp, silent);
1da177e4
LT		 4543 err = tg3_chip_reset(tp);
4544
944d980e
MC		 4545 tg3_write_sig_legacy(tp, kind);
4546 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 4547
4548 if (err)
4549 return err;
4550
4551 return 0;
4552}
4553
4554#define TG3_FW_RELEASE_MAJOR 0x0
4555#define TG3_FW_RELASE_MINOR 0x0
4556#define TG3_FW_RELEASE_FIX 0x0
4557#define TG3_FW_START_ADDR 0x08000000
4558#define TG3_FW_TEXT_ADDR 0x08000000
4559#define TG3_FW_TEXT_LEN 0x9c0
4560#define TG3_FW_RODATA_ADDR 0x080009c0
4561#define TG3_FW_RODATA_LEN 0x60
4562#define TG3_FW_DATA_ADDR 0x08000a40
4563#define TG3_FW_DATA_LEN 0x20
4564#define TG3_FW_SBSS_ADDR 0x08000a60
4565#define TG3_FW_SBSS_LEN 0xc
4566#define TG3_FW_BSS_ADDR 0x08000a70
4567#define TG3_FW_BSS_LEN 0x10
4568
4569static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4570 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4571 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4572 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4573 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4574 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4575 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4576 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4577 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4578 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4579 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4580 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4581 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4582 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4583 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4584 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4585 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4586 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4587 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4588 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4589 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4590 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4591 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4592 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4595 0, 0, 0, 0, 0, 0,
4596 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4597 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4598 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4599 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4600 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4601 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4602 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4603 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4604 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4605 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4606 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4610 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4611 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4612 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4613 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4614 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4615 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4616 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4617 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4618 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4619 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4620 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4621 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4622 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4623 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4624 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4625 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4626 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4627 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4628 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4629 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4630 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4631 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4632 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4633 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4634 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4635 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4636 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4637 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4638 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4639 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4640 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4641 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4642 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4643 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4644 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4645 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4646 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4647 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4648 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4649 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4650 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4651 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4652 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4653 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4654 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4655 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4656 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4657 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4658 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4659 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4660 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4661};
4662
4663static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4664 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4665 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4666 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4667 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4668 0x00000000
4669};
4670
4671#if 0 /* All zeros, don't eat up space with it. */
4672u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4673 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4674 0x00000000, 0x00000000, 0x00000000, 0x00000000
4675};
4676#endif
4677
4678#define RX_CPU_SCRATCH_BASE 0x30000
4679#define RX_CPU_SCRATCH_SIZE 0x04000
4680#define TX_CPU_SCRATCH_BASE 0x34000
4681#define TX_CPU_SCRATCH_SIZE 0x04000
4682
4683/* tp->lock is held. */
4684static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4685{
4686 int i;
4687
4688 if (offset == TX_CPU_BASE &&
4689 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4690 BUG();
4691
4692 if (offset == RX_CPU_BASE) {
4693 for (i = 0; i < 10000; i++) {
4694 tw32(offset + CPU_STATE, 0xffffffff);
4695 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4696 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4697 break;
4698 }
4699
4700 tw32(offset + CPU_STATE, 0xffffffff);
4701 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4702 udelay(10);
4703 } else {
4704 for (i = 0; i < 10000; i++) {
4705 tw32(offset + CPU_STATE, 0xffffffff);
4706 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4707 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4708 break;
4709 }
4710 }
4711
4712 if (i >= 10000) {
4713 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4714 "and %s CPU\n",
4715 tp->dev->name,
4716 (offset == RX_CPU_BASE ? "RX" : "TX"));
4717 return -ENODEV;
4718 }
4719 return 0;
4720}
4721
4722struct fw_info {
4723 unsigned int text_base;
4724 unsigned int text_len;
4725 u32 *text_data;
4726 unsigned int rodata_base;
4727 unsigned int rodata_len;
4728 u32 *rodata_data;
4729 unsigned int data_base;
4730 unsigned int data_len;
4731 u32 *data_data;
4732};
4733
4734/* tp->lock is held. */
4735static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4736 int cpu_scratch_size, struct fw_info *info)
4737{
4738 int err, i;
1da177e4
LT		 4739 void (*write_op)(struct tg3 *, u32, u32);
4740
4741 if (cpu_base == TX_CPU_BASE &&
4742 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4743 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4744 "TX cpu firmware on %s which is 5705.\n",
4745 tp->dev->name);
4746 return -EINVAL;
4747 }
4748
4749 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4750 write_op = tg3_write_mem;
4751 else
4752 write_op = tg3_write_indirect_reg32;
4753
1b628151
MC		 4754 /* It is possible that bootcode is still loading at this point.
4755 * Get the nvram lock first before halting the cpu.
4756 */
4757 tg3_nvram_lock(tp);
1da177e4 4758 err = tg3_halt_cpu(tp, cpu_base);
1b628151 4759 tg3_nvram_unlock(tp);
1da177e4
LT		 4760 if (err)
4761 goto out;
4762
4763 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4764 write_op(tp, cpu_scratch_base + i, 0);
4765 tw32(cpu_base + CPU_STATE, 0xffffffff);
4766 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4767 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4768 write_op(tp, (cpu_scratch_base +
4769 (info->text_base & 0xffff) +
4770 (i * sizeof(u32))),
4771 (info->text_data ?
4772 info->text_data[i] : 0));
4773 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4774 write_op(tp, (cpu_scratch_base +
4775 (info->rodata_base & 0xffff) +
4776 (i * sizeof(u32))),
4777 (info->rodata_data ?
4778 info->rodata_data[i] : 0));
4779 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4780 write_op(tp, (cpu_scratch_base +
4781 (info->data_base & 0xffff) +
4782 (i * sizeof(u32))),
4783 (info->data_data ?
4784 info->data_data[i] : 0));
4785
4786 err = 0;
4787
4788out:
1da177e4
LT		 4789 return err;
4790}
4791
4792/* tp->lock is held. */
4793static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4794{
4795 struct fw_info info;
4796 int err, i;
4797
4798 info.text_base = TG3_FW_TEXT_ADDR;
4799 info.text_len = TG3_FW_TEXT_LEN;
4800 info.text_data = &tg3FwText[0];
4801 info.rodata_base = TG3_FW_RODATA_ADDR;
4802 info.rodata_len = TG3_FW_RODATA_LEN;
4803 info.rodata_data = &tg3FwRodata[0];
4804 info.data_base = TG3_FW_DATA_ADDR;
4805 info.data_len = TG3_FW_DATA_LEN;
4806 info.data_data = NULL;
4807
4808 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4809 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4810 &info);
4811 if (err)
4812 return err;
4813
4814 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4815 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4816 &info);
4817 if (err)
4818 return err;
4819
4820 /* Now startup only the RX cpu. */
4821 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4822 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4823
4824 for (i = 0; i < 5; i++) {
4825 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4826 break;
4827 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4828 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4829 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4830 udelay(1000);
4831 }
4832 if (i >= 5) {
4833 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4834 "to set RX CPU PC, is %08x should be %08x\n",
4835 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4836 TG3_FW_TEXT_ADDR);
4837 return -ENODEV;
4838 }
4839 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4840 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4841
4842 return 0;
4843}
4844
4845#if TG3_TSO_SUPPORT != 0
4846
4847#define TG3_TSO_FW_RELEASE_MAJOR 0x1
4848#define TG3_TSO_FW_RELASE_MINOR 0x6
4849#define TG3_TSO_FW_RELEASE_FIX 0x0
4850#define TG3_TSO_FW_START_ADDR 0x08000000
4851#define TG3_TSO_FW_TEXT_ADDR 0x08000000
4852#define TG3_TSO_FW_TEXT_LEN 0x1aa0
4853#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4854#define TG3_TSO_FW_RODATA_LEN 0x60
4855#define TG3_TSO_FW_DATA_ADDR 0x08001b20
4856#define TG3_TSO_FW_DATA_LEN 0x30
4857#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4858#define TG3_TSO_FW_SBSS_LEN 0x2c
4859#define TG3_TSO_FW_BSS_ADDR 0x08001b80
4860#define TG3_TSO_FW_BSS_LEN 0x894
4861
4862static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4863 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4864 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4865 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4866 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4867 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4868 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4869 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4870 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4871 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4872 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4873 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4874 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4875 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4876 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4877 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4878 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4879 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4880 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4881 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4882 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4883 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4884 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4885 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4886 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4887 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4888 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4889 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4890 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4891 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4892 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4893 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4894 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4895 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4896 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4897 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4898 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4899 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4900 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4901 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4902 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4903 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4904 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4905 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4906 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4907 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4908 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4909 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4910 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4911 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4912 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4913 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4914 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4915 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4916 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4917 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4918 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4919 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4920 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4921 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4922 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4923 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4924 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4925 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4926 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4927 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4928 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4929 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4930 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4931 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4932 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4933 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4934 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4935 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4936 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4937 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4938 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4939 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4940 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4941 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4942 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4943 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4944 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4945 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4946 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4947 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4948 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4949 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4950 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4951 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4952 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4953 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4954 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4955 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4956 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4957 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4958 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4959 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4960 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4961 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4962 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4963 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4964 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4965 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4966 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4967 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4968 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4969 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4970 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4971 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4972 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4973 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4974 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4975 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4976 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4977 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4978 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4979 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4980 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4981 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4982 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4983 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4984 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4985 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4986 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4987 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4988 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4989 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4990 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4991 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4992 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4993 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4994 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4995 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4996 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4997 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4998 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4999 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5000 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5001 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5002 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5003 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5004 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5005 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5006 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5007 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5008 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5009 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5010 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5011 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5012 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5013 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5014 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5015 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5016 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5017 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5018 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5019 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5020 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5021 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5022 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5023 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5024 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5025 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5026 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5027 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5028 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5029 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5030 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5031 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5032 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5033 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5034 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5035 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5036 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5037 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5038 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5039 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5040 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5041 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5042 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5043 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5044 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5045 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5046 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5047 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5048 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5049 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5050 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5051 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5052 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5053 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5054 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5055 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5056 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5057 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5058 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5059 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5060 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5061 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5062 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5063 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5064 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5065 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5066 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5067 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5068 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5069 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5070 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5071 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5072 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5073 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5074 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5075 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5076 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5077 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5078 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5079 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5080 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5081 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5082 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5083 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5084 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5085 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5086 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5087 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5088 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5089 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5090 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5091 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5092 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5093 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5094 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5095 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5096 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5097 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5098 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5099 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5100 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5101 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5102 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5103 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5104 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5105 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5106 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5107 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5108 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5109 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5110 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5111 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5112 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5113 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5114 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5115 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5116 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5117 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5118 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5119 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5120 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5121 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5122 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5123 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5124 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5125 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5126 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5127 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5128 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5129 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5130 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5131 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5132 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5133 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5134 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5135 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5136 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5137 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5138 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5139 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5140 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5141 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5142 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5143 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5144 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5145 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5146 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5147};
5148
5149static u32 tg3TsoFwRodata[] = {
5150 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5151 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5152 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5153 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5154 0x00000000,
5155};
5156
5157static u32 tg3TsoFwData[] = {
5158 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5159 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5160 0x00000000,
5161};
5162
5163/* 5705 needs a special version of the TSO firmware. */
5164#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5165#define TG3_TSO5_FW_RELASE_MINOR 0x2
5166#define TG3_TSO5_FW_RELEASE_FIX 0x0
5167#define TG3_TSO5_FW_START_ADDR 0x00010000
5168#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5169#define TG3_TSO5_FW_TEXT_LEN 0xe90
5170#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5171#define TG3_TSO5_FW_RODATA_LEN 0x50
5172#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5173#define TG3_TSO5_FW_DATA_LEN 0x20
5174#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5175#define TG3_TSO5_FW_SBSS_LEN 0x28
5176#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5177#define TG3_TSO5_FW_BSS_LEN 0x88
5178
5179static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5180 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5181 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5182 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5183 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5184 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5185 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5186 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5187 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5188 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5189 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5190 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5191 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5192 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5193 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5194 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5195 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5196 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5197 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5198 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5199 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5200 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5201 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5202 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5203 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5204 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5205 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5206 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5207 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5208 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5209 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5210 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5211 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5212 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5213 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5214 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5215 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5216 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5217 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5218 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5219 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5220 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5221 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5222 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5223 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5224 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5225 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5226 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5227 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5228 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5229 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5230 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5231 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5232 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5233 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5234 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5235 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5236 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5237 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5238 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5239 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5240 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5241 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5242 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5243 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5244 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5245 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5246 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5247 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5248 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5249 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5250 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5251 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5252 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5253 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5254 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5255 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5256 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5257 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5258 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5259 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5260 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5261 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5262 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5263 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5264 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5265 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5266 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5267 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5268 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5269 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5270 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5271 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5272 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5273 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5274 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5275 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5276 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5277 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5278 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5279 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5280 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5281 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5282 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5283 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5284 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5285 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5286 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5287 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5288 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5289 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5290 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5291 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5292 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5293 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5294 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5295 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5296 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5297 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5298 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5299 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5300 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5301 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5302 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5303 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5304 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5305 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5306 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5307 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5308 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5309 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5310 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5311 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5312 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5313 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5314 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5315 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5316 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5317 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5318 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5319 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5320 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5321 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5322 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5323 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5324 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5325 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5326 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5327 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5328 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5329 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5330 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5331 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5332 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5333 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5334 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5335 0x00000000, 0x00000000, 0x00000000,
5336};
5337
5338static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5339 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5340 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5341 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5342 0x00000000, 0x00000000, 0x00000000,
5343};
5344
5345static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5346 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5347 0x00000000, 0x00000000, 0x00000000,
5348};
5349
5350/* tp->lock is held. */
5351static int tg3_load_tso_firmware(struct tg3 *tp)
5352{
5353 struct fw_info info;
5354 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5355 int err, i;
5356
5357 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5358 return 0;
5359
5360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5361 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5362 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5363 info.text_data = &tg3Tso5FwText[0];
5364 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5365 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5366 info.rodata_data = &tg3Tso5FwRodata[0];
5367 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5368 info.data_len = TG3_TSO5_FW_DATA_LEN;
5369 info.data_data = &tg3Tso5FwData[0];
5370 cpu_base = RX_CPU_BASE;
5371 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5372 cpu_scratch_size = (info.text_len +
5373 info.rodata_len +
5374 info.data_len +
5375 TG3_TSO5_FW_SBSS_LEN +
5376 TG3_TSO5_FW_BSS_LEN);
5377 } else {
5378 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5379 info.text_len = TG3_TSO_FW_TEXT_LEN;
5380 info.text_data = &tg3TsoFwText[0];
5381 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5382 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5383 info.rodata_data = &tg3TsoFwRodata[0];
5384 info.data_base = TG3_TSO_FW_DATA_ADDR;
5385 info.data_len = TG3_TSO_FW_DATA_LEN;
5386 info.data_data = &tg3TsoFwData[0];
5387 cpu_base = TX_CPU_BASE;
5388 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5389 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5390 }
5391
5392 err = tg3_load_firmware_cpu(tp, cpu_base,
5393 cpu_scratch_base, cpu_scratch_size,
5394 &info);
5395 if (err)
5396 return err;
5397
5398 /* Now startup the cpu. */
5399 tw32(cpu_base + CPU_STATE, 0xffffffff);
5400 tw32_f(cpu_base + CPU_PC, info.text_base);
5401
5402 for (i = 0; i < 5; i++) {
5403 if (tr32(cpu_base + CPU_PC) == info.text_base)
5404 break;
5405 tw32(cpu_base + CPU_STATE, 0xffffffff);
5406 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5407 tw32_f(cpu_base + CPU_PC, info.text_base);
5408 udelay(1000);
5409 }
5410 if (i >= 5) {
5411 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5412 "to set CPU PC, is %08x should be %08x\n",
5413 tp->dev->name, tr32(cpu_base + CPU_PC),
5414 info.text_base);
5415 return -ENODEV;
5416 }
5417 tw32(cpu_base + CPU_STATE, 0xffffffff);
5418 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5419 return 0;
5420}
5421
5422#endif /* TG3_TSO_SUPPORT != 0 */
5423
5424/* tp->lock is held. */
5425static void __tg3_set_mac_addr(struct tg3 *tp)
5426{
5427 u32 addr_high, addr_low;
5428 int i;
5429
5430 addr_high = ((tp->dev->dev_addr[0] << 8) |
5431 tp->dev->dev_addr[1]);
5432 addr_low = ((tp->dev->dev_addr[2] << 24) |
5433 (tp->dev->dev_addr[3] << 16) |
5434 (tp->dev->dev_addr[4] << 8) |
5435 (tp->dev->dev_addr[5] << 0));
5436 for (i = 0; i < 4; i++) {
5437 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5438 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5439 }
5440
5441 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5443 for (i = 0; i < 12; i++) {
5444 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5445 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5446 }
5447 }
5448
5449 addr_high = (tp->dev->dev_addr[0] +
5450 tp->dev->dev_addr[1] +
5451 tp->dev->dev_addr[2] +
5452 tp->dev->dev_addr[3] +
5453 tp->dev->dev_addr[4] +
5454 tp->dev->dev_addr[5]) &
5455 TX_BACKOFF_SEED_MASK;
5456 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5457}
5458
5459static int tg3_set_mac_addr(struct net_device *dev, void *p)
5460{
5461 struct tg3 *tp = netdev_priv(dev);
5462 struct sockaddr *addr = p;
5463
f9804ddb
MC		 5464 if (!is_valid_ether_addr(addr->sa_data))
5465 return -EINVAL;
5466
1da177e4
LT		 5467 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5468
f47c11ee 5469 spin_lock_bh(&tp->lock);
1da177e4 5470 __tg3_set_mac_addr(tp);
f47c11ee 5471 spin_unlock_bh(&tp->lock);
1da177e4
LT		 5472
5473 return 0;
5474}
5475
5476/* tp->lock is held. */
5477static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5478 dma_addr_t mapping, u32 maxlen_flags,
5479 u32 nic_addr)
5480{
5481 tg3_write_mem(tp,
5482 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5483 ((u64) mapping >> 32));
5484 tg3_write_mem(tp,
5485 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5486 ((u64) mapping & 0xffffffff));
5487 tg3_write_mem(tp,
5488 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5489 maxlen_flags);
5490
5491 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5492 tg3_write_mem(tp,
5493 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5494 nic_addr);
5495}
5496
5497static void __tg3_set_rx_mode(struct net_device *);
d244c892 5498static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 5499{
5500 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5501 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5502 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5503 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5504 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5505 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5506 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5507 }
5508 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5509 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5510 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5511 u32 val = ec->stats_block_coalesce_usecs;
5512
5513 if (!netif_carrier_ok(tp->dev))
5514 val = 0;
5515
5516 tw32(HOSTCC_STAT_COAL_TICKS, val);
5517 }
5518}
1da177e4
LT		 5519
5520/* tp->lock is held. */
5521static int tg3_reset_hw(struct tg3 *tp)
5522{
5523 u32 val, rdmac_mode;
5524 int i, err, limit;
5525
5526 tg3_disable_ints(tp);
5527
5528 tg3_stop_fw(tp);
5529
5530 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5531
5532 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 5533 tg3_abort_hw(tp, 1);
1da177e4
LT		 5534 }
5535
5536 err = tg3_chip_reset(tp);
5537 if (err)
5538 return err;
5539
5540 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5541
5542 /* This works around an issue with Athlon chipsets on
5543 * B3 tigon3 silicon. This bit has no effect on any
5544 * other revision. But do not set this on PCI Express
5545 * chips.
5546 */
5547 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5548 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5549 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5550
5551 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5552 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5553 val = tr32(TG3PCI_PCISTATE);
5554 val |= PCISTATE_RETRY_SAME_DMA;
5555 tw32(TG3PCI_PCISTATE, val);
5556 }
5557
5558 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5559 /* Enable some hw fixes. */
5560 val = tr32(TG3PCI_MSI_DATA);
5561 val |= (1 << 26) | (1 << 28) | (1 << 29);
5562 tw32(TG3PCI_MSI_DATA, val);
5563 }
5564
5565 /* Descriptor ring init may make accesses to the
5566 * NIC SRAM area to setup the TX descriptors, so we
5567 * can only do this after the hardware has been
5568 * successfully reset.
5569 */
5570 tg3_init_rings(tp);
5571
5572 /* This value is determined during the probe time DMA
5573 * engine test, tg3_test_dma.
5574 */
5575 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5576
5577 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5578 GRC_MODE_4X_NIC_SEND_RINGS |
5579 GRC_MODE_NO_TX_PHDR_CSUM |
5580 GRC_MODE_NO_RX_PHDR_CSUM);
5581 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5582 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5583 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5584 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5585 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5586
5587 tw32(GRC_MODE,
5588 tp->grc_mode |
5589 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5590
5591 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5592 val = tr32(GRC_MISC_CFG);
5593 val &= ~0xff;
5594 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5595 tw32(GRC_MISC_CFG, val);
5596
5597 /* Initialize MBUF/DESC pool. */
cbf46853 5598 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 5599 /* Do nothing. */
5600 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5601 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5603 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5604 else
5605 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5606 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5607 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5608 }
5609#if TG3_TSO_SUPPORT != 0
5610 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5611 int fw_len;
5612
5613 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5614 TG3_TSO5_FW_RODATA_LEN +
5615 TG3_TSO5_FW_DATA_LEN +
5616 TG3_TSO5_FW_SBSS_LEN +
5617 TG3_TSO5_FW_BSS_LEN);
5618 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5619 tw32(BUFMGR_MB_POOL_ADDR,
5620 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5621 tw32(BUFMGR_MB_POOL_SIZE,
5622 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5623 }
5624#endif
5625
0f893dc6 5626 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 5627 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5628 tp->bufmgr_config.mbuf_read_dma_low_water);
5629 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5630 tp->bufmgr_config.mbuf_mac_rx_low_water);
5631 tw32(BUFMGR_MB_HIGH_WATER,
5632 tp->bufmgr_config.mbuf_high_water);
5633 } else {
5634 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5635 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5636 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5637 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5638 tw32(BUFMGR_MB_HIGH_WATER,
5639 tp->bufmgr_config.mbuf_high_water_jumbo);
5640 }
5641 tw32(BUFMGR_DMA_LOW_WATER,
5642 tp->bufmgr_config.dma_low_water);
5643 tw32(BUFMGR_DMA_HIGH_WATER,
5644 tp->bufmgr_config.dma_high_water);
5645
5646 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5647 for (i = 0; i < 2000; i++) {
5648 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5649 break;
5650 udelay(10);
5651 }
5652 if (i >= 2000) {
5653 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5654 tp->dev->name);
5655 return -ENODEV;
5656 }
5657
5658 /* Setup replenish threshold. */
5659 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5660
5661 /* Initialize TG3_BDINFO's at:
5662 * RCVDBDI_STD_BD: standard eth size rx ring
5663 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5664 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5665 *
5666 * like so:
5667 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5668 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5669 * ring attribute flags
5670 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5671 *
5672 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5673 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5674 *
5675 * The size of each ring is fixed in the firmware, but the location is
5676 * configurable.
5677 */
5678 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5679 ((u64) tp->rx_std_mapping >> 32));
5680 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5681 ((u64) tp->rx_std_mapping & 0xffffffff));
5682 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5683 NIC_SRAM_RX_BUFFER_DESC);
5684
5685 /* Don't even try to program the JUMBO/MINI buffer descriptor
5686 * configs on 5705.
5687 */
5688 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5689 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5690 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5691 } else {
5692 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5693 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5694
5695 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5696 BDINFO_FLAGS_DISABLED);
5697
5698 /* Setup replenish threshold. */
5699 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5700
0f893dc6 5701 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5702 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5703 ((u64) tp->rx_jumbo_mapping >> 32));
5704 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5705 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5706 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5707 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5708 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5709 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5710 } else {
5711 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5712 BDINFO_FLAGS_DISABLED);
5713 }
5714
5715 }
5716
5717 /* There is only one send ring on 5705/5750, no need to explicitly
5718 * disable the others.
5719 */
5720 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5721 /* Clear out send RCB ring in SRAM. */
5722 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5723 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5724 BDINFO_FLAGS_DISABLED);
5725 }
5726
5727 tp->tx_prod = 0;
5728 tp->tx_cons = 0;
5729 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5730 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5731
5732 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5733 tp->tx_desc_mapping,
5734 (TG3_TX_RING_SIZE <<
5735 BDINFO_FLAGS_MAXLEN_SHIFT),
5736 NIC_SRAM_TX_BUFFER_DESC);
5737
5738 /* There is only one receive return ring on 5705/5750, no need
5739 * to explicitly disable the others.
5740 */
5741 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5742 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5743 i += TG3_BDINFO_SIZE) {
5744 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5745 BDINFO_FLAGS_DISABLED);
5746 }
5747 }
5748
5749 tp->rx_rcb_ptr = 0;
5750 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5751
5752 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5753 tp->rx_rcb_mapping,
5754 (TG3_RX_RCB_RING_SIZE(tp) <<
5755 BDINFO_FLAGS_MAXLEN_SHIFT),
5756 0);
5757
5758 tp->rx_std_ptr = tp->rx_pending;
5759 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5760 tp->rx_std_ptr);
5761
0f893dc6 5762 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 5763 tp->rx_jumbo_pending : 0;
5764 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5765 tp->rx_jumbo_ptr);
5766
5767 /* Initialize MAC address and backoff seed. */
5768 __tg3_set_mac_addr(tp);
5769
5770 /* MTU + ethernet header + FCS + optional VLAN tag */
5771 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5772
5773 /* The slot time is changed by tg3_setup_phy if we
5774 * run at gigabit with half duplex.
5775 */
5776 tw32(MAC_TX_LENGTHS,
5777 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5778 (6 << TX_LENGTHS_IPG_SHIFT) |
5779 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5780
5781 /* Receive rules. */
5782 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5783 tw32(RCVLPC_CONFIG, 0x0181);
5784
5785 /* Calculate RDMAC_MODE setting early, we need it to determine
5786 * the RCVLPC_STATE_ENABLE mask.
5787 */
5788 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5789 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5790 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5791 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5792 RDMAC_MODE_LNGREAD_ENAB);
5793 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5794 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 5795
5796 /* If statement applies to 5705 and 5750 PCI devices only */
5797 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5798 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5799 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 5800 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5801 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5802 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5803 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5804 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5805 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5806 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5807 }
5808 }
5809
85e94ced
MC		 5810 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5811 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5812
1da177e4
LT		 5813#if TG3_TSO_SUPPORT != 0
5814 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5815 rdmac_mode |= (1 << 27);
5816#endif
5817
5818 /* Receive/send statistics. */
5819 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5820 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5821 val = tr32(RCVLPC_STATS_ENABLE);
5822 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5823 tw32(RCVLPC_STATS_ENABLE, val);
5824 } else {
5825 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5826 }
5827 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5828 tw32(SNDDATAI_STATSENAB, 0xffffff);
5829 tw32(SNDDATAI_STATSCTRL,
5830 (SNDDATAI_SCTRL_ENABLE |
5831 SNDDATAI_SCTRL_FASTUPD));
5832
5833 /* Setup host coalescing engine. */
5834 tw32(HOSTCC_MODE, 0);
5835 for (i = 0; i < 2000; i++) {
5836 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5837 break;
5838 udelay(10);
5839 }
5840
d244c892 5841 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 5842
5843 /* set status block DMA address */
5844 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5845 ((u64) tp->status_mapping >> 32));
5846 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5847 ((u64) tp->status_mapping & 0xffffffff));
5848
5849 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5850 /* Status/statistics block address. See tg3_timer,
5851 * the tg3_periodic_fetch_stats call there, and
5852 * tg3_get_stats to see how this works for 5705/5750 chips.
5853 */
1da177e4
LT		 5854 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5855 ((u64) tp->stats_mapping >> 32));
5856 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5857 ((u64) tp->stats_mapping & 0xffffffff));
5858 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5859 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5860 }
5861
5862 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5863
5864 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5865 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5866 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5867 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5868
5869 /* Clear statistics/status block in chip, and status block in ram. */
5870 for (i = NIC_SRAM_STATS_BLK;
5871 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5872 i += sizeof(u32)) {
5873 tg3_write_mem(tp, i, 0);
5874 udelay(40);
5875 }
5876 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5877
c94e3941
MC		 5878 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5879 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
5880 /* reset to prevent losing 1st rx packet intermittently */
5881 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5882 udelay(10);
5883 }
5884
1da177e4
LT		 5885 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5886 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5887 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5888 udelay(40);
5889
314fba34
MC		 5890 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5891 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5892 * register to preserve the GPIO settings for LOMs. The GPIOs,
5893 * whether used as inputs or outputs, are set by boot code after
5894 * reset.
5895 */
5896 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5897 u32 gpio_mask;
5898
5899 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5900 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 5901
5902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5903 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5904 GRC_LCLCTRL_GPIO_OUTPUT3;
5905
314fba34
MC		 5906 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5907
5908 /* GPIO1 must be driven high for eeprom write protect */
1da177e4
LT		 5909 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5910 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 5911 }
1da177e4
LT		 5912 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5913 udelay(100);
5914
09ee929c 5915 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 5916 tp->last_tag = 0;
1da177e4
LT		 5917
5918 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5919 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5920 udelay(40);
5921 }
5922
5923 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5924 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5925 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5926 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5927 WDMAC_MODE_LNGREAD_ENAB);
5928
85e94ced
MC		 5929 /* If statement applies to 5705 and 5750 PCI devices only */
5930 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5931 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 5933 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5934 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5935 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5936 /* nothing */
5937 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5938 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5939 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5940 val |= WDMAC_MODE_RX_ACCEL;
5941 }
5942 }
5943
5944 tw32_f(WDMAC_MODE, val);
5945 udelay(40);
5946
5947 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5948 val = tr32(TG3PCI_X_CAPS);
5949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5950 val &= ~PCIX_CAPS_BURST_MASK;
5951 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5952 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5953 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5954 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5955 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5956 val |= (tp->split_mode_max_reqs <<
5957 PCIX_CAPS_SPLIT_SHIFT);
5958 }
5959 tw32(TG3PCI_X_CAPS, val);
5960 }
5961
5962 tw32_f(RDMAC_MODE, rdmac_mode);
5963 udelay(40);
5964
5965 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5966 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5967 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5968 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5969 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5970 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5971 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5972 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5973#if TG3_TSO_SUPPORT != 0
5974 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5975 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5976#endif
5977 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5978 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5979
5980 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5981 err = tg3_load_5701_a0_firmware_fix(tp);
5982 if (err)
5983 return err;
5984 }
5985
5986#if TG3_TSO_SUPPORT != 0
5987 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5988 err = tg3_load_tso_firmware(tp);
5989 if (err)
5990 return err;
5991 }
5992#endif
5993
5994 tp->tx_mode = TX_MODE_ENABLE;
5995 tw32_f(MAC_TX_MODE, tp->tx_mode);
5996 udelay(100);
5997
5998 tp->rx_mode = RX_MODE_ENABLE;
5999 tw32_f(MAC_RX_MODE, tp->rx_mode);
6000 udelay(10);
6001
6002 if (tp->link_config.phy_is_low_power) {
6003 tp->link_config.phy_is_low_power = 0;
6004 tp->link_config.speed = tp->link_config.orig_speed;
6005 tp->link_config.duplex = tp->link_config.orig_duplex;
6006 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6007 }
6008
6009 tp->mi_mode = MAC_MI_MODE_BASE;
6010 tw32_f(MAC_MI_MODE, tp->mi_mode);
6011 udelay(80);
6012
6013 tw32(MAC_LED_CTRL, tp->led_ctrl);
6014
6015 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6016 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6017 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6018 udelay(10);
6019 }
6020 tw32_f(MAC_RX_MODE, tp->rx_mode);
6021 udelay(10);
6022
6023 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6024 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6025 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6026 /* Set drive transmission level to 1.2V */
6027 /* only if the signal pre-emphasis bit is not set */
6028 val = tr32(MAC_SERDES_CFG);
6029 val &= 0xfffff000;
6030 val |= 0x880;
6031 tw32(MAC_SERDES_CFG, val);
6032 }
6033 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6034 tw32(MAC_SERDES_CFG, 0x616000);
6035 }
6036
6037 /* Prevent chip from dropping frames when flow control
6038 * is enabled.
6039 */
6040 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6041
6042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6043 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6044 /* Use hardware link auto-negotiation */
6045 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6046 }
6047
6048 err = tg3_setup_phy(tp, 1);
6049 if (err)
6050 return err;
6051
6052 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6053 u32 tmp;
6054
6055 /* Clear CRC stats. */
6056 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6057 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6058 tg3_readphy(tp, 0x14, &tmp);
6059 }
6060 }
6061
6062 __tg3_set_rx_mode(tp->dev);
6063
6064 /* Initialize receive rules. */
6065 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6066 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6067 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6068 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6069
4cf78e4f 6070 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 6071 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 6072 limit = 8;
6073 else
6074 limit = 16;
6075 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6076 limit -= 4;
6077 switch (limit) {
6078 case 16:
6079 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6080 case 15:
6081 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6082 case 14:
6083 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6084 case 13:
6085 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6086 case 12:
6087 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6088 case 11:
6089 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6090 case 10:
6091 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6092 case 9:
6093 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6094 case 8:
6095 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6096 case 7:
6097 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6098 case 6:
6099 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6100 case 5:
6101 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6102 case 4:
6103 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6104 case 3:
6105 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6106 case 2:
6107 case 1:
6108
6109 default:
6110 break;
6111 };
6112
6113 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6114
1da177e4
LT		 6115 return 0;
6116}
6117
6118/* Called at device open time to get the chip ready for
6119 * packet processing. Invoked with tp->lock held.
6120 */
6121static int tg3_init_hw(struct tg3 *tp)
6122{
6123 int err;
6124
6125 /* Force the chip into D0. */
6126 err = tg3_set_power_state(tp, 0);
6127 if (err)
6128 goto out;
6129
6130 tg3_switch_clocks(tp);
6131
6132 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6133
6134 err = tg3_reset_hw(tp);
6135
6136out:
6137 return err;
6138}
6139
6140#define TG3_STAT_ADD32(PSTAT, REG) \
6141do { u32 __val = tr32(REG); \
6142 (PSTAT)->low += __val; \
6143 if ((PSTAT)->low < __val) \
6144 (PSTAT)->high += 1; \
6145} while (0)
6146
6147static void tg3_periodic_fetch_stats(struct tg3 *tp)
6148{
6149 struct tg3_hw_stats *sp = tp->hw_stats;
6150
6151 if (!netif_carrier_ok(tp->dev))
6152 return;
6153
6154 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6155 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6156 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6157 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6158 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6159 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6160 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6161 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6162 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6163 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6164 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6165 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6166 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6167
6168 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6169 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6170 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6171 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6172 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6173 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6174 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6175 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6176 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6177 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6178 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6179 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6180 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6181 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6182}
6183
6184static void tg3_timer(unsigned long __opaque)
6185{
6186 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6187
f47c11ee 6188 spin_lock(&tp->lock);
1da177e4 6189
fac9b83e
DM		 6190 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6191 /* All of this garbage is because when using non-tagged
6192 * IRQ status the mailbox/status_block protocol the chip
6193 * uses with the cpu is race prone.
6194 */
6195 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6196 tw32(GRC_LOCAL_CTRL,
6197 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6198 } else {
6199 tw32(HOSTCC_MODE, tp->coalesce_mode |
6200 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6201 }
1da177e4 6202
fac9b83e
DM		 6203 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6204 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6205 spin_unlock(&tp->lock);
fac9b83e
DM		 6206 schedule_work(&tp->reset_task);
6207 return;
6208 }
1da177e4
LT		 6209 }
6210
1da177e4
LT		 6211 /* This part only runs once per second. */
6212 if (!--tp->timer_counter) {
fac9b83e
DM		 6213 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6214 tg3_periodic_fetch_stats(tp);
6215
1da177e4
LT		 6216 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6217 u32 mac_stat;
6218 int phy_event;
6219
6220 mac_stat = tr32(MAC_STATUS);
6221
6222 phy_event = 0;
6223 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6224 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6225 phy_event = 1;
6226 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6227 phy_event = 1;
6228
6229 if (phy_event)
6230 tg3_setup_phy(tp, 0);
6231 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6232 u32 mac_stat = tr32(MAC_STATUS);
6233 int need_setup = 0;
6234
6235 if (netif_carrier_ok(tp->dev) &&
6236 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6237 need_setup = 1;
6238 }
6239 if (! netif_carrier_ok(tp->dev) &&
6240 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6241 MAC_STATUS_SIGNAL_DET))) {
6242 need_setup = 1;
6243 }
6244 if (need_setup) {
6245 tw32_f(MAC_MODE,
6246 (tp->mac_mode &
6247 ~MAC_MODE_PORT_MODE_MASK));
6248 udelay(40);
6249 tw32_f(MAC_MODE, tp->mac_mode);
6250 udelay(40);
6251 tg3_setup_phy(tp, 0);
6252 }
747e8f8b
MC		 6253 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6254 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6255
6256 tp->timer_counter = tp->timer_multiplier;
6257 }
6258
28fbef78 6259 /* Heartbeat is only sent once every 2 seconds. */
1da177e4
LT		 6260 if (!--tp->asf_counter) {
6261 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6262 u32 val;
6263
28fbef78
MC		 6264 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX,
6265 FWCMD_NICDRV_ALIVE2);
6266 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6267 /* 5 seconds timeout */
6268 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 6269 val = tr32(GRC_RX_CPU_EVENT);
6270 val |= (1 << 14);
6271 tw32(GRC_RX_CPU_EVENT, val);
6272 }
6273 tp->asf_counter = tp->asf_multiplier;
6274 }
6275
f47c11ee 6276 spin_unlock(&tp->lock);
1da177e4
LT		 6277
6278 tp->timer.expires = jiffies + tp->timer_offset;
6279 add_timer(&tp->timer);
6280}
6281
7938109f
MC		 6282static int tg3_test_interrupt(struct tg3 *tp)
6283{
6284 struct net_device *dev = tp->dev;
6285 int err, i;
6286 u32 int_mbox = 0;
6287
d4bc3927
MC		 6288 if (!netif_running(dev))
6289 return -ENODEV;
6290
7938109f
MC		 6291 tg3_disable_ints(tp);
6292
6293 free_irq(tp->pdev->irq, dev);
6294
6295 err = request_irq(tp->pdev->irq, tg3_test_isr,
f4d0ee98 6296 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6297 if (err)
6298 return err;
6299
38f3843e 6300 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 6301 tg3_enable_ints(tp);
6302
6303 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6304 HOSTCC_MODE_NOW);
6305
6306 for (i = 0; i < 5; i++) {
09ee929c
MC		 6307 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6308 TG3_64BIT_REG_LOW);
7938109f
MC		 6309 if (int_mbox != 0)
6310 break;
6311 msleep(10);
6312 }
6313
6314 tg3_disable_ints(tp);
6315
6316 free_irq(tp->pdev->irq, dev);
6317
6318 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6319 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6320 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6321 else {
6322 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6323 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6324 fn = tg3_interrupt_tagged;
6325 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6326 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6327 }
7938109f
MC		 6328
6329 if (err)
6330 return err;
6331
6332 if (int_mbox != 0)
6333 return 0;
6334
6335 return -EIO;
6336}
6337
6338/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6339 * successfully restored
6340 */
6341static int tg3_test_msi(struct tg3 *tp)
6342{
6343 struct net_device *dev = tp->dev;
6344 int err;
6345 u16 pci_cmd;
6346
6347 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6348 return 0;
6349
6350 /* Turn off SERR reporting in case MSI terminates with Master
6351 * Abort.
6352 */
6353 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6354 pci_write_config_word(tp->pdev, PCI_COMMAND,
6355 pci_cmd & ~PCI_COMMAND_SERR);
6356
6357 err = tg3_test_interrupt(tp);
6358
6359 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6360
6361 if (!err)
6362 return 0;
6363
6364 /* other failures */
6365 if (err != -EIO)
6366 return err;
6367
6368 /* MSI test failed, go back to INTx mode */
6369 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6370 "switching to INTx mode. Please report this failure to "
6371 "the PCI maintainer and include system chipset information.\n",
6372 tp->dev->name);
6373
6374 free_irq(tp->pdev->irq, dev);
6375 pci_disable_msi(tp->pdev);
6376
6377 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6378
fac9b83e
DM		 6379 {
6380 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6381 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6382 fn = tg3_interrupt_tagged;
7938109f 6383
fac9b83e
DM		 6384 err = request_irq(tp->pdev->irq, fn,
6385 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6386 }
7938109f
MC		 6387 if (err)
6388 return err;
6389
6390 /* Need to reset the chip because the MSI cycle may have terminated
6391 * with Master Abort.
6392 */
f47c11ee 6393 tg3_full_lock(tp, 1);
7938109f 6394
944d980e 6395 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6396 err = tg3_init_hw(tp);
6397
f47c11ee 6398 tg3_full_unlock(tp);
7938109f
MC		 6399
6400 if (err)
6401 free_irq(tp->pdev->irq, dev);
6402
6403 return err;
6404}
6405
1da177e4
LT		 6406static int tg3_open(struct net_device *dev)
6407{
6408 struct tg3 *tp = netdev_priv(dev);
6409 int err;
6410
f47c11ee 6411 tg3_full_lock(tp, 0);
1da177e4
LT		 6412
6413 tg3_disable_ints(tp);
6414 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6415
f47c11ee 6416 tg3_full_unlock(tp);
1da177e4
LT		 6417
6418 /* The placement of this call is tied
6419 * to the setup and use of Host TX descriptors.
6420 */
6421 err = tg3_alloc_consistent(tp);
6422 if (err)
6423 return err;
6424
88b06bc2
MC		 6425 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6426 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6427 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
fac9b83e
DM		 6428 /* All MSI supporting chips should support tagged
6429 * status. Assert that this is the case.
6430 */
6431 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6432 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6433 "Not using MSI.\n", tp->dev->name);
6434 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 6435 u32 msi_mode;
6436
6437 msi_mode = tr32(MSGINT_MODE);
6438 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6439 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6440 }
6441 }
6442 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6443 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6444 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6445 else {
6446 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6447 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6448 fn = tg3_interrupt_tagged;
6449
6450 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6451 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6452 }
1da177e4
LT		 6453
6454 if (err) {
88b06bc2
MC		 6455 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6456 pci_disable_msi(tp->pdev);
6457 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6458 }
1da177e4
LT		 6459 tg3_free_consistent(tp);
6460 return err;
6461 }
6462
f47c11ee 6463 tg3_full_lock(tp, 0);
1da177e4
LT		 6464
6465 err = tg3_init_hw(tp);
6466 if (err) {
944d980e 6467 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6468 tg3_free_rings(tp);
6469 } else {
fac9b83e
DM		 6470 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6471 tp->timer_offset = HZ;
6472 else
6473 tp->timer_offset = HZ / 10;
6474
6475 BUG_ON(tp->timer_offset > HZ);
6476 tp->timer_counter = tp->timer_multiplier =
6477 (HZ / tp->timer_offset);
6478 tp->asf_counter = tp->asf_multiplier =
28fbef78 6479 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 6480
6481 init_timer(&tp->timer);
6482 tp->timer.expires = jiffies + tp->timer_offset;
6483 tp->timer.data = (unsigned long) tp;
6484 tp->timer.function = tg3_timer;
1da177e4
LT		 6485 }
6486
f47c11ee 6487 tg3_full_unlock(tp);
1da177e4
LT		 6488
6489 if (err) {
88b06bc2
MC		 6490 free_irq(tp->pdev->irq, dev);
6491 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6492 pci_disable_msi(tp->pdev);
6493 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6494 }
1da177e4
LT		 6495 tg3_free_consistent(tp);
6496 return err;
6497 }
6498
7938109f
MC		 6499 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6500 err = tg3_test_msi(tp);
fac9b83e 6501
7938109f 6502 if (err) {
f47c11ee 6503 tg3_full_lock(tp, 0);
7938109f
MC		 6504
6505 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6506 pci_disable_msi(tp->pdev);
6507 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6508 }
944d980e 6509 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6510 tg3_free_rings(tp);
6511 tg3_free_consistent(tp);
6512
f47c11ee 6513 tg3_full_unlock(tp);
7938109f
MC		 6514
6515 return err;
6516 }
6517 }
6518
f47c11ee 6519 tg3_full_lock(tp, 0);
1da177e4 6520
7938109f
MC		 6521 add_timer(&tp->timer);
6522 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 6523 tg3_enable_ints(tp);
6524
f47c11ee 6525 tg3_full_unlock(tp);
1da177e4
LT		 6526
6527 netif_start_queue(dev);
6528
6529 return 0;
6530}
6531
6532#if 0
6533/*static*/ void tg3_dump_state(struct tg3 *tp)
6534{
6535 u32 val32, val32_2, val32_3, val32_4, val32_5;
6536 u16 val16;
6537 int i;
6538
6539 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6540 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6541 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6542 val16, val32);
6543
6544 /* MAC block */
6545 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6546 tr32(MAC_MODE), tr32(MAC_STATUS));
6547 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6548 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6549 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6550 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6551 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6552 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6553
6554 /* Send data initiator control block */
6555 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6556 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6557 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6558 tr32(SNDDATAI_STATSCTRL));
6559
6560 /* Send data completion control block */
6561 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6562
6563 /* Send BD ring selector block */
6564 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6565 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6566
6567 /* Send BD initiator control block */
6568 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6569 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6570
6571 /* Send BD completion control block */
6572 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6573
6574 /* Receive list placement control block */
6575 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6576 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6577 printk(" RCVLPC_STATSCTRL[%08x]\n",
6578 tr32(RCVLPC_STATSCTRL));
6579
6580 /* Receive data and receive BD initiator control block */
6581 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6582 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6583
6584 /* Receive data completion control block */
6585 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6586 tr32(RCVDCC_MODE));
6587
6588 /* Receive BD initiator control block */
6589 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6590 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6591
6592 /* Receive BD completion control block */
6593 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6594 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6595
6596 /* Receive list selector control block */
6597 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6598 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6599
6600 /* Mbuf cluster free block */
6601 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6602 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6603
6604 /* Host coalescing control block */
6605 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6606 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6607 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6608 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6609 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6610 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6611 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6612 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6613 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6614 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6615 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6616 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6617
6618 /* Memory arbiter control block */
6619 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6620 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6621
6622 /* Buffer manager control block */
6623 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6624 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6625 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6626 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6627 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6628 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6629 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6630 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6631
6632 /* Read DMA control block */
6633 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6634 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6635
6636 /* Write DMA control block */
6637 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6638 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6639
6640 /* DMA completion block */
6641 printk("DEBUG: DMAC_MODE[%08x]\n",
6642 tr32(DMAC_MODE));
6643
6644 /* GRC block */
6645 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6646 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6647 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6648 tr32(GRC_LOCAL_CTRL));
6649
6650 /* TG3_BDINFOs */
6651 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6652 tr32(RCVDBDI_JUMBO_BD + 0x0),
6653 tr32(RCVDBDI_JUMBO_BD + 0x4),
6654 tr32(RCVDBDI_JUMBO_BD + 0x8),
6655 tr32(RCVDBDI_JUMBO_BD + 0xc));
6656 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6657 tr32(RCVDBDI_STD_BD + 0x0),
6658 tr32(RCVDBDI_STD_BD + 0x4),
6659 tr32(RCVDBDI_STD_BD + 0x8),
6660 tr32(RCVDBDI_STD_BD + 0xc));
6661 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6662 tr32(RCVDBDI_MINI_BD + 0x0),
6663 tr32(RCVDBDI_MINI_BD + 0x4),
6664 tr32(RCVDBDI_MINI_BD + 0x8),
6665 tr32(RCVDBDI_MINI_BD + 0xc));
6666
6667 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6668 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6669 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6670 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6671 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6672 val32, val32_2, val32_3, val32_4);
6673
6674 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6675 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6676 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6677 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6678 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6679 val32, val32_2, val32_3, val32_4);
6680
6681 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6682 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6683 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6684 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6685 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6686 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6687 val32, val32_2, val32_3, val32_4, val32_5);
6688
6689 /* SW status block */
6690 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6691 tp->hw_status->status,
6692 tp->hw_status->status_tag,
6693 tp->hw_status->rx_jumbo_consumer,
6694 tp->hw_status->rx_consumer,
6695 tp->hw_status->rx_mini_consumer,
6696 tp->hw_status->idx[0].rx_producer,
6697 tp->hw_status->idx[0].tx_consumer);
6698
6699 /* SW statistics block */
6700 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6701 ((u32 *)tp->hw_stats)[0],
6702 ((u32 *)tp->hw_stats)[1],
6703 ((u32 *)tp->hw_stats)[2],
6704 ((u32 *)tp->hw_stats)[3]);
6705
6706 /* Mailboxes */
6707 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 6708 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6709 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6710 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6711 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 6712
6713 /* NIC side send descriptors. */
6714 for (i = 0; i < 6; i++) {
6715 unsigned long txd;
6716
6717 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6718 + (i * sizeof(struct tg3_tx_buffer_desc));
6719 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6720 i,
6721 readl(txd + 0x0), readl(txd + 0x4),
6722 readl(txd + 0x8), readl(txd + 0xc));
6723 }
6724
6725 /* NIC side RX descriptors. */
6726 for (i = 0; i < 6; i++) {
6727 unsigned long rxd;
6728
6729 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6730 + (i * sizeof(struct tg3_rx_buffer_desc));
6731 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6732 i,
6733 readl(rxd + 0x0), readl(rxd + 0x4),
6734 readl(rxd + 0x8), readl(rxd + 0xc));
6735 rxd += (4 * sizeof(u32));
6736 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6737 i,
6738 readl(rxd + 0x0), readl(rxd + 0x4),
6739 readl(rxd + 0x8), readl(rxd + 0xc));
6740 }
6741
6742 for (i = 0; i < 6; i++) {
6743 unsigned long rxd;
6744
6745 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6746 + (i * sizeof(struct tg3_rx_buffer_desc));
6747 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6748 i,
6749 readl(rxd + 0x0), readl(rxd + 0x4),
6750 readl(rxd + 0x8), readl(rxd + 0xc));
6751 rxd += (4 * sizeof(u32));
6752 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6753 i,
6754 readl(rxd + 0x0), readl(rxd + 0x4),
6755 readl(rxd + 0x8), readl(rxd + 0xc));
6756 }
6757}
6758#endif
6759
6760static struct net_device_stats *tg3_get_stats(struct net_device *);
6761static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6762
6763static int tg3_close(struct net_device *dev)
6764{
6765 struct tg3 *tp = netdev_priv(dev);
6766
6767 netif_stop_queue(dev);
6768
6769 del_timer_sync(&tp->timer);
6770
f47c11ee 6771 tg3_full_lock(tp, 1);
1da177e4
LT		 6772#if 0
6773 tg3_dump_state(tp);
6774#endif
6775
6776 tg3_disable_ints(tp);
6777
944d980e 6778 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6779 tg3_free_rings(tp);
6780 tp->tg3_flags &=
6781 ~(TG3_FLAG_INIT_COMPLETE |
6782 TG3_FLAG_GOT_SERDES_FLOWCTL);
6783 netif_carrier_off(tp->dev);
6784
f47c11ee 6785 tg3_full_unlock(tp);
1da177e4 6786
88b06bc2
MC		 6787 free_irq(tp->pdev->irq, dev);
6788 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6789 pci_disable_msi(tp->pdev);
6790 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6791 }
1da177e4
LT		 6792
6793 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6794 sizeof(tp->net_stats_prev));
6795 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6796 sizeof(tp->estats_prev));
6797
6798 tg3_free_consistent(tp);
6799
6800 return 0;
6801}
6802
6803static inline unsigned long get_stat64(tg3_stat64_t *val)
6804{
6805 unsigned long ret;
6806
6807#if (BITS_PER_LONG == 32)
6808 ret = val->low;
6809#else
6810 ret = ((u64)val->high << 32) | ((u64)val->low);
6811#endif
6812 return ret;
6813}
6814
6815static unsigned long calc_crc_errors(struct tg3 *tp)
6816{
6817 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6818
6819 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6820 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 6822 u32 val;
6823
f47c11ee 6824 spin_lock_bh(&tp->lock);
1da177e4
LT		 6825 if (!tg3_readphy(tp, 0x1e, &val)) {
6826 tg3_writephy(tp, 0x1e, val | 0x8000);
6827 tg3_readphy(tp, 0x14, &val);
6828 } else
6829 val = 0;
f47c11ee 6830 spin_unlock_bh(&tp->lock);
1da177e4
LT		 6831
6832 tp->phy_crc_errors += val;
6833
6834 return tp->phy_crc_errors;
6835 }
6836
6837 return get_stat64(&hw_stats->rx_fcs_errors);
6838}
6839
6840#define ESTAT_ADD(member) \
6841 estats->member = old_estats->member + \
6842 get_stat64(&hw_stats->member)
6843
6844static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6845{
6846 struct tg3_ethtool_stats *estats = &tp->estats;
6847 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6848 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6849
6850 if (!hw_stats)
6851 return old_estats;
6852
6853 ESTAT_ADD(rx_octets);
6854 ESTAT_ADD(rx_fragments);
6855 ESTAT_ADD(rx_ucast_packets);
6856 ESTAT_ADD(rx_mcast_packets);
6857 ESTAT_ADD(rx_bcast_packets);
6858 ESTAT_ADD(rx_fcs_errors);
6859 ESTAT_ADD(rx_align_errors);
6860 ESTAT_ADD(rx_xon_pause_rcvd);
6861 ESTAT_ADD(rx_xoff_pause_rcvd);
6862 ESTAT_ADD(rx_mac_ctrl_rcvd);
6863 ESTAT_ADD(rx_xoff_entered);
6864 ESTAT_ADD(rx_frame_too_long_errors);
6865 ESTAT_ADD(rx_jabbers);
6866 ESTAT_ADD(rx_undersize_packets);
6867 ESTAT_ADD(rx_in_length_errors);
6868 ESTAT_ADD(rx_out_length_errors);
6869 ESTAT_ADD(rx_64_or_less_octet_packets);
6870 ESTAT_ADD(rx_65_to_127_octet_packets);
6871 ESTAT_ADD(rx_128_to_255_octet_packets);
6872 ESTAT_ADD(rx_256_to_511_octet_packets);
6873 ESTAT_ADD(rx_512_to_1023_octet_packets);
6874 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6875 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6876 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6877 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6878 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6879
6880 ESTAT_ADD(tx_octets);
6881 ESTAT_ADD(tx_collisions);
6882 ESTAT_ADD(tx_xon_sent);
6883 ESTAT_ADD(tx_xoff_sent);
6884 ESTAT_ADD(tx_flow_control);
6885 ESTAT_ADD(tx_mac_errors);
6886 ESTAT_ADD(tx_single_collisions);
6887 ESTAT_ADD(tx_mult_collisions);
6888 ESTAT_ADD(tx_deferred);
6889 ESTAT_ADD(tx_excessive_collisions);
6890 ESTAT_ADD(tx_late_collisions);
6891 ESTAT_ADD(tx_collide_2times);
6892 ESTAT_ADD(tx_collide_3times);
6893 ESTAT_ADD(tx_collide_4times);
6894 ESTAT_ADD(tx_collide_5times);
6895 ESTAT_ADD(tx_collide_6times);
6896 ESTAT_ADD(tx_collide_7times);
6897 ESTAT_ADD(tx_collide_8times);
6898 ESTAT_ADD(tx_collide_9times);
6899 ESTAT_ADD(tx_collide_10times);
6900 ESTAT_ADD(tx_collide_11times);
6901 ESTAT_ADD(tx_collide_12times);
6902 ESTAT_ADD(tx_collide_13times);
6903 ESTAT_ADD(tx_collide_14times);
6904 ESTAT_ADD(tx_collide_15times);
6905 ESTAT_ADD(tx_ucast_packets);
6906 ESTAT_ADD(tx_mcast_packets);
6907 ESTAT_ADD(tx_bcast_packets);
6908 ESTAT_ADD(tx_carrier_sense_errors);
6909 ESTAT_ADD(tx_discards);
6910 ESTAT_ADD(tx_errors);
6911
6912 ESTAT_ADD(dma_writeq_full);
6913 ESTAT_ADD(dma_write_prioq_full);
6914 ESTAT_ADD(rxbds_empty);
6915 ESTAT_ADD(rx_discards);
6916 ESTAT_ADD(rx_errors);
6917 ESTAT_ADD(rx_threshold_hit);
6918
6919 ESTAT_ADD(dma_readq_full);
6920 ESTAT_ADD(dma_read_prioq_full);
6921 ESTAT_ADD(tx_comp_queue_full);
6922
6923 ESTAT_ADD(ring_set_send_prod_index);
6924 ESTAT_ADD(ring_status_update);
6925 ESTAT_ADD(nic_irqs);
6926 ESTAT_ADD(nic_avoided_irqs);
6927 ESTAT_ADD(nic_tx_threshold_hit);
6928
6929 return estats;
6930}
6931
6932static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6933{
6934 struct tg3 *tp = netdev_priv(dev);
6935 struct net_device_stats *stats = &tp->net_stats;
6936 struct net_device_stats *old_stats = &tp->net_stats_prev;
6937 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6938
6939 if (!hw_stats)
6940 return old_stats;
6941
6942 stats->rx_packets = old_stats->rx_packets +
6943 get_stat64(&hw_stats->rx_ucast_packets) +
6944 get_stat64(&hw_stats->rx_mcast_packets) +
6945 get_stat64(&hw_stats->rx_bcast_packets);
6946
6947 stats->tx_packets = old_stats->tx_packets +
6948 get_stat64(&hw_stats->tx_ucast_packets) +
6949 get_stat64(&hw_stats->tx_mcast_packets) +
6950 get_stat64(&hw_stats->tx_bcast_packets);
6951
6952 stats->rx_bytes = old_stats->rx_bytes +
6953 get_stat64(&hw_stats->rx_octets);
6954 stats->tx_bytes = old_stats->tx_bytes +
6955 get_stat64(&hw_stats->tx_octets);
6956
6957 stats->rx_errors = old_stats->rx_errors +
4f63b877 6958 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 6959 stats->tx_errors = old_stats->tx_errors +
6960 get_stat64(&hw_stats->tx_errors) +
6961 get_stat64(&hw_stats->tx_mac_errors) +
6962 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6963 get_stat64(&hw_stats->tx_discards);
6964
6965 stats->multicast = old_stats->multicast +
6966 get_stat64(&hw_stats->rx_mcast_packets);
6967 stats->collisions = old_stats->collisions +
6968 get_stat64(&hw_stats->tx_collisions);
6969
6970 stats->rx_length_errors = old_stats->rx_length_errors +
6971 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6972 get_stat64(&hw_stats->rx_undersize_packets);
6973
6974 stats->rx_over_errors = old_stats->rx_over_errors +
6975 get_stat64(&hw_stats->rxbds_empty);
6976 stats->rx_frame_errors = old_stats->rx_frame_errors +
6977 get_stat64(&hw_stats->rx_align_errors);
6978 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6979 get_stat64(&hw_stats->tx_discards);
6980 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6981 get_stat64(&hw_stats->tx_carrier_sense_errors);
6982
6983 stats->rx_crc_errors = old_stats->rx_crc_errors +
6984 calc_crc_errors(tp);
6985
4f63b877
JL		 6986 stats->rx_missed_errors = old_stats->rx_missed_errors +
6987 get_stat64(&hw_stats->rx_discards);
6988
1da177e4
LT		 6989 return stats;
6990}
6991
6992static inline u32 calc_crc(unsigned char *buf, int len)
6993{
6994 u32 reg;
6995 u32 tmp;
6996 int j, k;
6997
6998 reg = 0xffffffff;
6999
7000 for (j = 0; j < len; j++) {
7001 reg ^= buf[j];
7002
7003 for (k = 0; k < 8; k++) {
7004 tmp = reg & 0x01;
7005
7006 reg >>= 1;
7007
7008 if (tmp) {
7009 reg ^= 0xedb88320;
7010 }
7011 }
7012 }
7013
7014 return ~reg;
7015}
7016
7017static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7018{
7019 /* accept or reject all multicast frames */
7020 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7021 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7022 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7023 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7024}
7025
7026static void __tg3_set_rx_mode(struct net_device *dev)
7027{
7028 struct tg3 *tp = netdev_priv(dev);
7029 u32 rx_mode;
7030
7031 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7032 RX_MODE_KEEP_VLAN_TAG);
7033
7034 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7035 * flag clear.
7036 */
7037#if TG3_VLAN_TAG_USED
7038 if (!tp->vlgrp &&
7039 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7040 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7041#else
7042 /* By definition, VLAN is disabled always in this
7043 * case.
7044 */
7045 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7046 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7047#endif
7048
7049 if (dev->flags & IFF_PROMISC) {
7050 /* Promiscuous mode. */
7051 rx_mode |= RX_MODE_PROMISC;
7052 } else if (dev->flags & IFF_ALLMULTI) {
7053 /* Accept all multicast. */
7054 tg3_set_multi (tp, 1);
7055 } else if (dev->mc_count < 1) {
7056 /* Reject all multicast. */
7057 tg3_set_multi (tp, 0);
7058 } else {
7059 /* Accept one or more multicast(s). */
7060 struct dev_mc_list *mclist;
7061 unsigned int i;
7062 u32 mc_filter[4] = { 0, };
7063 u32 regidx;
7064 u32 bit;
7065 u32 crc;
7066
7067 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7068 i++, mclist = mclist->next) {
7069
7070 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7071 bit = ~crc & 0x7f;
7072 regidx = (bit & 0x60) >> 5;
7073 bit &= 0x1f;
7074 mc_filter[regidx] |= (1 << bit);
7075 }
7076
7077 tw32(MAC_HASH_REG_0, mc_filter[0]);
7078 tw32(MAC_HASH_REG_1, mc_filter[1]);
7079 tw32(MAC_HASH_REG_2, mc_filter[2]);
7080 tw32(MAC_HASH_REG_3, mc_filter[3]);
7081 }
7082
7083 if (rx_mode != tp->rx_mode) {
7084 tp->rx_mode = rx_mode;
7085 tw32_f(MAC_RX_MODE, rx_mode);
7086 udelay(10);
7087 }
7088}
7089
7090static void tg3_set_rx_mode(struct net_device *dev)
7091{
7092 struct tg3 *tp = netdev_priv(dev);
7093
f47c11ee 7094 tg3_full_lock(tp, 0);
1da177e4 7095 __tg3_set_rx_mode(dev);
f47c11ee 7096 tg3_full_unlock(tp);
1da177e4
LT		 7097}
7098
7099#define TG3_REGDUMP_LEN (32 * 1024)
7100
7101static int tg3_get_regs_len(struct net_device *dev)
7102{
7103 return TG3_REGDUMP_LEN;
7104}
7105
7106static void tg3_get_regs(struct net_device *dev,
7107 struct ethtool_regs *regs, void *_p)
7108{
7109 u32 *p = _p;
7110 struct tg3 *tp = netdev_priv(dev);
7111 u8 *orig_p = _p;
7112 int i;
7113
7114 regs->version = 0;
7115
7116 memset(p, 0, TG3_REGDUMP_LEN);
7117
f47c11ee 7118 tg3_full_lock(tp, 0);
1da177e4
LT		 7119
7120#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7121#define GET_REG32_LOOP(base,len) \
7122do { p = (u32 *)(orig_p + (base)); \
7123 for (i = 0; i < len; i += 4) \
7124 __GET_REG32((base) + i); \
7125} while (0)
7126#define GET_REG32_1(reg) \
7127do { p = (u32 *)(orig_p + (reg)); \
7128 __GET_REG32((reg)); \
7129} while (0)
7130
7131 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7132 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7133 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7134 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7135 GET_REG32_1(SNDDATAC_MODE);
7136 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7137 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7138 GET_REG32_1(SNDBDC_MODE);
7139 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7140 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7141 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7142 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7143 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7144 GET_REG32_1(RCVDCC_MODE);
7145 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7146 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7147 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7148 GET_REG32_1(MBFREE_MODE);
7149 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7150 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7151 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7152 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7153 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7154 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
7155 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
7156 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7157 GET_REG32_LOOP(FTQ_RESET, 0x120);
7158 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7159 GET_REG32_1(DMAC_MODE);
7160 GET_REG32_LOOP(GRC_MODE, 0x4c);
7161 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7162 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7163
7164#undef __GET_REG32
7165#undef GET_REG32_LOOP
7166#undef GET_REG32_1
7167
f47c11ee 7168 tg3_full_unlock(tp);
1da177e4
LT		 7169}
7170
7171static int tg3_get_eeprom_len(struct net_device *dev)
7172{
7173 struct tg3 *tp = netdev_priv(dev);
7174
7175 return tp->nvram_size;
7176}
7177
7178static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7179
7180static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7181{
7182 struct tg3 *tp = netdev_priv(dev);
7183 int ret;
7184 u8 *pd;
7185 u32 i, offset, len, val, b_offset, b_count;
7186
7187 offset = eeprom->offset;
7188 len = eeprom->len;
7189 eeprom->len = 0;
7190
7191 eeprom->magic = TG3_EEPROM_MAGIC;
7192
7193 if (offset & 3) {
7194 /* adjustments to start on required 4 byte boundary */
7195 b_offset = offset & 3;
7196 b_count = 4 - b_offset;
7197 if (b_count > len) {
7198 /* i.e. offset=1 len=2 */
7199 b_count = len;
7200 }
7201 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7202 if (ret)
7203 return ret;
7204 val = cpu_to_le32(val);
7205 memcpy(data, ((char*)&val) + b_offset, b_count);
7206 len -= b_count;
7207 offset += b_count;
7208 eeprom->len += b_count;
7209 }
7210
7211 /* read bytes upto the last 4 byte boundary */
7212 pd = &data[eeprom->len];
7213 for (i = 0; i < (len - (len & 3)); i += 4) {
7214 ret = tg3_nvram_read(tp, offset + i, &val);
7215 if (ret) {
7216 eeprom->len += i;
7217 return ret;
7218 }
7219 val = cpu_to_le32(val);
7220 memcpy(pd + i, &val, 4);
7221 }
7222 eeprom->len += i;
7223
7224 if (len & 3) {
7225 /* read last bytes not ending on 4 byte boundary */
7226 pd = &data[eeprom->len];
7227 b_count = len & 3;
7228 b_offset = offset + len - b_count;
7229 ret = tg3_nvram_read(tp, b_offset, &val);
7230 if (ret)
7231 return ret;
7232 val = cpu_to_le32(val);
7233 memcpy(pd, ((char*)&val), b_count);
7234 eeprom->len += b_count;
7235 }
7236 return 0;
7237}
7238
7239static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7240
7241static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7242{
7243 struct tg3 *tp = netdev_priv(dev);
7244 int ret;
7245 u32 offset, len, b_offset, odd_len, start, end;
7246 u8 *buf;
7247
7248 if (eeprom->magic != TG3_EEPROM_MAGIC)
7249 return -EINVAL;
7250
7251 offset = eeprom->offset;
7252 len = eeprom->len;
7253
7254 if ((b_offset = (offset & 3))) {
7255 /* adjustments to start on required 4 byte boundary */
7256 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7257 if (ret)
7258 return ret;
7259 start = cpu_to_le32(start);
7260 len += b_offset;
7261 offset &= ~3;
1c8594b4
MC		 7262 if (len < 4)
7263 len = 4;
1da177e4
LT		 7264 }
7265
7266 odd_len = 0;
1c8594b4 7267 if (len & 3) {
1da177e4
LT		 7268 /* adjustments to end on required 4 byte boundary */
7269 odd_len = 1;
7270 len = (len + 3) & ~3;
7271 ret = tg3_nvram_read(tp, offset+len-4, &end);
7272 if (ret)
7273 return ret;
7274 end = cpu_to_le32(end);
7275 }
7276
7277 buf = data;
7278 if (b_offset || odd_len) {
7279 buf = kmalloc(len, GFP_KERNEL);
7280 if (buf == 0)
7281 return -ENOMEM;
7282 if (b_offset)
7283 memcpy(buf, &start, 4);
7284 if (odd_len)
7285 memcpy(buf+len-4, &end, 4);
7286 memcpy(buf + b_offset, data, eeprom->len);
7287 }
7288
7289 ret = tg3_nvram_write_block(tp, offset, len, buf);
7290
7291 if (buf != data)
7292 kfree(buf);
7293
7294 return ret;
7295}
7296
7297static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7298{
7299 struct tg3 *tp = netdev_priv(dev);
7300
7301 cmd->supported = (SUPPORTED_Autoneg);
7302
7303 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7304 cmd->supported |= (SUPPORTED_1000baseT_Half |
7305 SUPPORTED_1000baseT_Full);
7306
a4e2b347 7307 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 7308 cmd->supported |= (SUPPORTED_100baseT_Half |
7309 SUPPORTED_100baseT_Full |
7310 SUPPORTED_10baseT_Half |
7311 SUPPORTED_10baseT_Full |
7312 SUPPORTED_MII);
7313 else
7314 cmd->supported |= SUPPORTED_FIBRE;
7315
7316 cmd->advertising = tp->link_config.advertising;
7317 if (netif_running(dev)) {
7318 cmd->speed = tp->link_config.active_speed;
7319 cmd->duplex = tp->link_config.active_duplex;
7320 }
7321 cmd->port = 0;
7322 cmd->phy_address = PHY_ADDR;
7323 cmd->transceiver = 0;
7324 cmd->autoneg = tp->link_config.autoneg;
7325 cmd->maxtxpkt = 0;
7326 cmd->maxrxpkt = 0;
7327 return 0;
7328}
7329
7330static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7331{
7332 struct tg3 *tp = netdev_priv(dev);
7333
37ff238d 7334 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 7335 /* These are the only valid advertisement bits allowed. */
7336 if (cmd->autoneg == AUTONEG_ENABLE &&
7337 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7338 ADVERTISED_1000baseT_Full |
7339 ADVERTISED_Autoneg |
7340 ADVERTISED_FIBRE)))
7341 return -EINVAL;
37ff238d
MC		 7342 /* Fiber can only do SPEED_1000. */
7343 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7344 (cmd->speed != SPEED_1000))
7345 return -EINVAL;
7346 /* Copper cannot force SPEED_1000. */
7347 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7348 (cmd->speed == SPEED_1000))
7349 return -EINVAL;
7350 else if ((cmd->speed == SPEED_1000) &&
7351 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7352 return -EINVAL;
1da177e4 7353
f47c11ee 7354 tg3_full_lock(tp, 0);
1da177e4
LT		 7355
7356 tp->link_config.autoneg = cmd->autoneg;
7357 if (cmd->autoneg == AUTONEG_ENABLE) {
7358 tp->link_config.advertising = cmd->advertising;
7359 tp->link_config.speed = SPEED_INVALID;
7360 tp->link_config.duplex = DUPLEX_INVALID;
7361 } else {
7362 tp->link_config.advertising = 0;
7363 tp->link_config.speed = cmd->speed;
7364 tp->link_config.duplex = cmd->duplex;
7365 }
7366
7367 if (netif_running(dev))
7368 tg3_setup_phy(tp, 1);
7369
f47c11ee 7370 tg3_full_unlock(tp);
1da177e4
LT		 7371
7372 return 0;
7373}
7374
7375static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7376{
7377 struct tg3 *tp = netdev_priv(dev);
7378
7379 strcpy(info->driver, DRV_MODULE_NAME);
7380 strcpy(info->version, DRV_MODULE_VERSION);
7381 strcpy(info->bus_info, pci_name(tp->pdev));
7382}
7383
7384static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7385{
7386 struct tg3 *tp = netdev_priv(dev);
7387
7388 wol->supported = WAKE_MAGIC;
7389 wol->wolopts = 0;
7390 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7391 wol->wolopts = WAKE_MAGIC;
7392 memset(&wol->sopass, 0, sizeof(wol->sopass));
7393}
7394
7395static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7396{
7397 struct tg3 *tp = netdev_priv(dev);
7398
7399 if (wol->wolopts & ~WAKE_MAGIC)
7400 return -EINVAL;
7401 if ((wol->wolopts & WAKE_MAGIC) &&
7402 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7403 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7404 return -EINVAL;
7405
f47c11ee 7406 spin_lock_bh(&tp->lock);
1da177e4
LT		 7407 if (wol->wolopts & WAKE_MAGIC)
7408 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7409 else
7410 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 7411 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7412
7413 return 0;
7414}
7415
7416static u32 tg3_get_msglevel(struct net_device *dev)
7417{
7418 struct tg3 *tp = netdev_priv(dev);
7419 return tp->msg_enable;
7420}
7421
7422static void tg3_set_msglevel(struct net_device *dev, u32 value)
7423{
7424 struct tg3 *tp = netdev_priv(dev);
7425 tp->msg_enable = value;
7426}
7427
7428#if TG3_TSO_SUPPORT != 0
7429static int tg3_set_tso(struct net_device *dev, u32 value)
7430{
7431 struct tg3 *tp = netdev_priv(dev);
7432
7433 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7434 if (value)
7435 return -EINVAL;
7436 return 0;
7437 }
7438 return ethtool_op_set_tso(dev, value);
7439}
7440#endif
7441
7442static int tg3_nway_reset(struct net_device *dev)
7443{
7444 struct tg3 *tp = netdev_priv(dev);
7445 u32 bmcr;
7446 int r;
7447
7448 if (!netif_running(dev))
7449 return -EAGAIN;
7450
c94e3941
MC		 7451 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7452 return -EINVAL;
7453
f47c11ee 7454 spin_lock_bh(&tp->lock);
1da177e4
LT		 7455 r = -EINVAL;
7456 tg3_readphy(tp, MII_BMCR, &bmcr);
7457 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 7458 ((bmcr & BMCR_ANENABLE) ||
7459 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7460 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7461 BMCR_ANENABLE);
1da177e4
LT		 7462 r = 0;
7463 }
f47c11ee 7464 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7465
7466 return r;
7467}
7468
7469static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7470{
7471 struct tg3 *tp = netdev_priv(dev);
7472
7473 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7474 ering->rx_mini_max_pending = 0;
7475 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7476
7477 ering->rx_pending = tp->rx_pending;
7478 ering->rx_mini_pending = 0;
7479 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7480 ering->tx_pending = tp->tx_pending;
7481}
7482
7483static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7484{
7485 struct tg3 *tp = netdev_priv(dev);
bbe832c0 7486 int irq_sync = 0;
1da177e4
LT		 7487
7488 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7489 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7490 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7491 return -EINVAL;
7492
bbe832c0 7493 if (netif_running(dev)) {
1da177e4 7494 tg3_netif_stop(tp);
bbe832c0
MC		 7495 irq_sync = 1;
7496 }
1da177e4 7497
bbe832c0 7498 tg3_full_lock(tp, irq_sync);
1da177e4
LT		 7499
7500 tp->rx_pending = ering->rx_pending;
7501
7502 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7503 tp->rx_pending > 63)
7504 tp->rx_pending = 63;
7505 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7506 tp->tx_pending = ering->tx_pending;
7507
7508 if (netif_running(dev)) {
944d980e 7509 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7510 tg3_init_hw(tp);
7511 tg3_netif_start(tp);
7512 }
7513
f47c11ee 7514 tg3_full_unlock(tp);
1da177e4
LT		 7515
7516 return 0;
7517}
7518
7519static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7520{
7521 struct tg3 *tp = netdev_priv(dev);
7522
7523 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7524 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7525 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7526}
7527
7528static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7529{
7530 struct tg3 *tp = netdev_priv(dev);
bbe832c0 7531 int irq_sync = 0;
1da177e4 7532
bbe832c0 7533 if (netif_running(dev)) {
1da177e4 7534 tg3_netif_stop(tp);
bbe832c0
MC		 7535 irq_sync = 1;
7536 }
1da177e4 7537
bbe832c0 7538 tg3_full_lock(tp, irq_sync);
f47c11ee 7539
1da177e4
LT		 7540 if (epause->autoneg)
7541 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7542 else
7543 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7544 if (epause->rx_pause)
7545 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7546 else
7547 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7548 if (epause->tx_pause)
7549 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7550 else
7551 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7552
7553 if (netif_running(dev)) {
944d980e 7554 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7555 tg3_init_hw(tp);
7556 tg3_netif_start(tp);
7557 }
f47c11ee
DM		 7558
7559 tg3_full_unlock(tp);
1da177e4
LT		 7560
7561 return 0;
7562}
7563
7564static u32 tg3_get_rx_csum(struct net_device *dev)
7565{
7566 struct tg3 *tp = netdev_priv(dev);
7567 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7568}
7569
7570static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7571{
7572 struct tg3 *tp = netdev_priv(dev);
7573
7574 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7575 if (data != 0)
7576 return -EINVAL;
7577 return 0;
7578 }
7579
f47c11ee 7580 spin_lock_bh(&tp->lock);
1da177e4
LT		 7581 if (data)
7582 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7583 else
7584 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 7585 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7586
7587 return 0;
7588}
7589
7590static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7591{
7592 struct tg3 *tp = netdev_priv(dev);
7593
7594 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7595 if (data != 0)
7596 return -EINVAL;
7597 return 0;
7598 }
7599
7600 if (data)
7601 dev->features |= NETIF_F_IP_CSUM;
7602 else
7603 dev->features &= ~NETIF_F_IP_CSUM;
7604
7605 return 0;
7606}
7607
7608static int tg3_get_stats_count (struct net_device *dev)
7609{
7610 return TG3_NUM_STATS;
7611}
7612
4cafd3f5
MC		 7613static int tg3_get_test_count (struct net_device *dev)
7614{
7615 return TG3_NUM_TEST;
7616}
7617
1da177e4
LT		 7618static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7619{
7620 switch (stringset) {
7621 case ETH_SS_STATS:
7622 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7623 break;
4cafd3f5
MC		 7624 case ETH_SS_TEST:
7625 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7626 break;
1da177e4
LT		 7627 default:
7628 WARN_ON(1); /* we need a WARN() */
7629 break;
7630 }
7631}
7632
4009a93d
MC		 7633static int tg3_phys_id(struct net_device *dev, u32 data)
7634{
7635 struct tg3 *tp = netdev_priv(dev);
7636 int i;
7637
7638 if (!netif_running(tp->dev))
7639 return -EAGAIN;
7640
7641 if (data == 0)
7642 data = 2;
7643
7644 for (i = 0; i < (data * 2); i++) {
7645 if ((i % 2) == 0)
7646 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7647 LED_CTRL_1000MBPS_ON |
7648 LED_CTRL_100MBPS_ON |
7649 LED_CTRL_10MBPS_ON |
7650 LED_CTRL_TRAFFIC_OVERRIDE |
7651 LED_CTRL_TRAFFIC_BLINK |
7652 LED_CTRL_TRAFFIC_LED);
7653
7654 else
7655 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7656 LED_CTRL_TRAFFIC_OVERRIDE);
7657
7658 if (msleep_interruptible(500))
7659 break;
7660 }
7661 tw32(MAC_LED_CTRL, tp->led_ctrl);
7662 return 0;
7663}
7664
1da177e4
LT		 7665static void tg3_get_ethtool_stats (struct net_device *dev,
7666 struct ethtool_stats *estats, u64 *tmp_stats)
7667{
7668 struct tg3 *tp = netdev_priv(dev);
7669 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7670}
7671
566f86ad
MC		 7672#define NVRAM_TEST_SIZE 0x100
7673
7674static int tg3_test_nvram(struct tg3 *tp)
7675{
7676 u32 *buf, csum;
7677 int i, j, err = 0;
7678
7679 buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7680 if (buf == NULL)
7681 return -ENOMEM;
7682
7683 for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7684 u32 val;
7685
7686 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7687 break;
7688 buf[j] = cpu_to_le32(val);
7689 }
7690 if (i < NVRAM_TEST_SIZE)
7691 goto out;
7692
7693 err = -EIO;
7694 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7695 goto out;
7696
7697 /* Bootstrap checksum at offset 0x10 */
7698 csum = calc_crc((unsigned char *) buf, 0x10);
7699 if(csum != cpu_to_le32(buf[0x10/4]))
7700 goto out;
7701
7702 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7703 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7704 if (csum != cpu_to_le32(buf[0xfc/4]))
7705 goto out;
7706
7707 err = 0;
7708
7709out:
7710 kfree(buf);
7711 return err;
7712}
7713
ca43007a
MC		 7714#define TG3_SERDES_TIMEOUT_SEC 2
7715#define TG3_COPPER_TIMEOUT_SEC 6
7716
7717static int tg3_test_link(struct tg3 *tp)
7718{
7719 int i, max;
7720
7721 if (!netif_running(tp->dev))
7722 return -ENODEV;
7723
4c987487 7724 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 7725 max = TG3_SERDES_TIMEOUT_SEC;
7726 else
7727 max = TG3_COPPER_TIMEOUT_SEC;
7728
7729 for (i = 0; i < max; i++) {
7730 if (netif_carrier_ok(tp->dev))
7731 return 0;
7732
7733 if (msleep_interruptible(1000))
7734 break;
7735 }
7736
7737 return -EIO;
7738}
7739
a71116d1
MC		 7740/* Only test the commonly used registers */
7741static int tg3_test_registers(struct tg3 *tp)
7742{
7743 int i, is_5705;
7744 u32 offset, read_mask, write_mask, val, save_val, read_val;
7745 static struct {
7746 u16 offset;
7747 u16 flags;
7748#define TG3_FL_5705 0x1
7749#define TG3_FL_NOT_5705 0x2
7750#define TG3_FL_NOT_5788 0x4
7751 u32 read_mask;
7752 u32 write_mask;
7753 } reg_tbl[] = {
7754 /* MAC Control Registers */
7755 { MAC_MODE, TG3_FL_NOT_5705,
7756 0x00000000, 0x00ef6f8c },
7757 { MAC_MODE, TG3_FL_5705,
7758 0x00000000, 0x01ef6b8c },
7759 { MAC_STATUS, TG3_FL_NOT_5705,
7760 0x03800107, 0x00000000 },
7761 { MAC_STATUS, TG3_FL_5705,
7762 0x03800100, 0x00000000 },
7763 { MAC_ADDR_0_HIGH, 0x0000,
7764 0x00000000, 0x0000ffff },
7765 { MAC_ADDR_0_LOW, 0x0000,
7766 0x00000000, 0xffffffff },
7767 { MAC_RX_MTU_SIZE, 0x0000,
7768 0x00000000, 0x0000ffff },
7769 { MAC_TX_MODE, 0x0000,
7770 0x00000000, 0x00000070 },
7771 { MAC_TX_LENGTHS, 0x0000,
7772 0x00000000, 0x00003fff },
7773 { MAC_RX_MODE, TG3_FL_NOT_5705,
7774 0x00000000, 0x000007fc },
7775 { MAC_RX_MODE, TG3_FL_5705,
7776 0x00000000, 0x000007dc },
7777 { MAC_HASH_REG_0, 0x0000,
7778 0x00000000, 0xffffffff },
7779 { MAC_HASH_REG_1, 0x0000,
7780 0x00000000, 0xffffffff },
7781 { MAC_HASH_REG_2, 0x0000,
7782 0x00000000, 0xffffffff },
7783 { MAC_HASH_REG_3, 0x0000,
7784 0x00000000, 0xffffffff },
7785
7786 /* Receive Data and Receive BD Initiator Control Registers. */
7787 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7788 0x00000000, 0xffffffff },
7789 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7790 0x00000000, 0xffffffff },
7791 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7792 0x00000000, 0x00000003 },
7793 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7794 0x00000000, 0xffffffff },
7795 { RCVDBDI_STD_BD+0, 0x0000,
7796 0x00000000, 0xffffffff },
7797 { RCVDBDI_STD_BD+4, 0x0000,
7798 0x00000000, 0xffffffff },
7799 { RCVDBDI_STD_BD+8, 0x0000,
7800 0x00000000, 0xffff0002 },
7801 { RCVDBDI_STD_BD+0xc, 0x0000,
7802 0x00000000, 0xffffffff },
7803
7804 /* Receive BD Initiator Control Registers. */
7805 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7806 0x00000000, 0xffffffff },
7807 { RCVBDI_STD_THRESH, TG3_FL_5705,
7808 0x00000000, 0x000003ff },
7809 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7810 0x00000000, 0xffffffff },
7811
7812 /* Host Coalescing Control Registers. */
7813 { HOSTCC_MODE, TG3_FL_NOT_5705,
7814 0x00000000, 0x00000004 },
7815 { HOSTCC_MODE, TG3_FL_5705,
7816 0x00000000, 0x000000f6 },
7817 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7818 0x00000000, 0xffffffff },
7819 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7820 0x00000000, 0x000003ff },
7821 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7822 0x00000000, 0xffffffff },
7823 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7824 0x00000000, 0x000003ff },
7825 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7826 0x00000000, 0xffffffff },
7827 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7828 0x00000000, 0x000000ff },
7829 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7830 0x00000000, 0xffffffff },
7831 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7832 0x00000000, 0x000000ff },
7833 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7834 0x00000000, 0xffffffff },
7835 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7836 0x00000000, 0xffffffff },
7837 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7838 0x00000000, 0xffffffff },
7839 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7840 0x00000000, 0x000000ff },
7841 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7842 0x00000000, 0xffffffff },
7843 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7844 0x00000000, 0x000000ff },
7845 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7846 0x00000000, 0xffffffff },
7847 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7848 0x00000000, 0xffffffff },
7849 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7850 0x00000000, 0xffffffff },
7851 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7852 0x00000000, 0xffffffff },
7853 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7854 0x00000000, 0xffffffff },
7855 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7856 0xffffffff, 0x00000000 },
7857 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7858 0xffffffff, 0x00000000 },
7859
7860 /* Buffer Manager Control Registers. */
7861 { BUFMGR_MB_POOL_ADDR, 0x0000,
7862 0x00000000, 0x007fff80 },
7863 { BUFMGR_MB_POOL_SIZE, 0x0000,
7864 0x00000000, 0x007fffff },
7865 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7866 0x00000000, 0x0000003f },
7867 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7868 0x00000000, 0x000001ff },
7869 { BUFMGR_MB_HIGH_WATER, 0x0000,
7870 0x00000000, 0x000001ff },
7871 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7872 0xffffffff, 0x00000000 },
7873 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7874 0xffffffff, 0x00000000 },
7875
7876 /* Mailbox Registers */
7877 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7878 0x00000000, 0x000001ff },
7879 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7880 0x00000000, 0x000001ff },
7881 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7882 0x00000000, 0x000007ff },
7883 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7884 0x00000000, 0x000001ff },
7885
7886 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7887 };
7888
7889 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7890 is_5705 = 1;
7891 else
7892 is_5705 = 0;
7893
7894 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7895 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7896 continue;
7897
7898 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7899 continue;
7900
7901 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7902 (reg_tbl[i].flags & TG3_FL_NOT_5788))
7903 continue;
7904
7905 offset = (u32) reg_tbl[i].offset;
7906 read_mask = reg_tbl[i].read_mask;
7907 write_mask = reg_tbl[i].write_mask;
7908
7909 /* Save the original register content */
7910 save_val = tr32(offset);
7911
7912 /* Determine the read-only value. */
7913 read_val = save_val & read_mask;
7914
7915 /* Write zero to the register, then make sure the read-only bits
7916 * are not changed and the read/write bits are all zeros.
7917 */
7918 tw32(offset, 0);
7919
7920 val = tr32(offset);
7921
7922 /* Test the read-only and read/write bits. */
7923 if (((val & read_mask) != read_val) || (val & write_mask))
7924 goto out;
7925
7926 /* Write ones to all the bits defined by RdMask and WrMask, then
7927 * make sure the read-only bits are not changed and the
7928 * read/write bits are all ones.
7929 */
7930 tw32(offset, read_mask | write_mask);
7931
7932 val = tr32(offset);
7933
7934 /* Test the read-only bits. */
7935 if ((val & read_mask) != read_val)
7936 goto out;
7937
7938 /* Test the read/write bits. */
7939 if ((val & write_mask) != write_mask)
7940 goto out;
7941
7942 tw32(offset, save_val);
7943 }
7944
7945 return 0;
7946
7947out:
7948 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7949 tw32(offset, save_val);
7950 return -EIO;
7951}
7952
7942e1db
MC		 7953static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7954{
7955 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7956 int i;
7957 u32 j;
7958
7959 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7960 for (j = 0; j < len; j += 4) {
7961 u32 val;
7962
7963 tg3_write_mem(tp, offset + j, test_pattern[i]);
7964 tg3_read_mem(tp, offset + j, &val);
7965 if (val != test_pattern[i])
7966 return -EIO;
7967 }
7968 }
7969 return 0;
7970}
7971
7972static int tg3_test_memory(struct tg3 *tp)
7973{
7974 static struct mem_entry {
7975 u32 offset;
7976 u32 len;
7977 } mem_tbl_570x[] = {
38690194 7978 { 0x00000000, 0x00b50},
7942e1db
MC		 7979 { 0x00002000, 0x1c000},
7980 { 0xffffffff, 0x00000}
7981 }, mem_tbl_5705[] = {
7982 { 0x00000100, 0x0000c},
7983 { 0x00000200, 0x00008},
7942e1db
MC		 7984 { 0x00004000, 0x00800},
7985 { 0x00006000, 0x01000},
7986 { 0x00008000, 0x02000},
7987 { 0x00010000, 0x0e000},
7988 { 0xffffffff, 0x00000}
7989 };
7990 struct mem_entry *mem_tbl;
7991 int err = 0;
7992 int i;
7993
7994 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7995 mem_tbl = mem_tbl_5705;
7996 else
7997 mem_tbl = mem_tbl_570x;
7998
7999 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8000 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8001 mem_tbl[i].len)) != 0)
8002 break;
8003 }
8004
8005 return err;
8006}
8007
9f40dead
MC		 8008#define TG3_MAC_LOOPBACK 0
8009#define TG3_PHY_LOOPBACK 1
8010
8011static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 8012{
9f40dead 8013 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 8014 u32 desc_idx;
8015 struct sk_buff *skb, *rx_skb;
8016 u8 *tx_data;
8017 dma_addr_t map;
8018 int num_pkts, tx_len, rx_len, i, err;
8019 struct tg3_rx_buffer_desc *desc;
8020
9f40dead 8021 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 8022 /* HW errata - mac loopback fails in some cases on 5780.
8023 * Normal traffic and PHY loopback are not affected by
8024 * errata.
8025 */
8026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8027 return 0;
8028
9f40dead
MC		 8029 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8030 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8031 MAC_MODE_PORT_MODE_GMII;
8032 tw32(MAC_MODE, mac_mode);
8033 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
c94e3941
MC		 8034 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8035 BMCR_SPEED1000);
8036 udelay(40);
8037 /* reset to prevent losing 1st rx packet intermittently */
8038 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8039 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8040 udelay(10);
8041 tw32_f(MAC_RX_MODE, tp->rx_mode);
8042 }
9f40dead
MC		 8043 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8044 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8045 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8046 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8047 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 8048 }
8049 else
8050 return -EINVAL;
c76949a6
MC		 8051
8052 err = -EIO;
8053
c76949a6
MC		 8054 tx_len = 1514;
8055 skb = dev_alloc_skb(tx_len);
8056 tx_data = skb_put(skb, tx_len);
8057 memcpy(tx_data, tp->dev->dev_addr, 6);
8058 memset(tx_data + 6, 0x0, 8);
8059
8060 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8061
8062 for (i = 14; i < tx_len; i++)
8063 tx_data[i] = (u8) (i & 0xff);
8064
8065 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8066
8067 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8068 HOSTCC_MODE_NOW);
8069
8070 udelay(10);
8071
8072 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8073
c76949a6
MC		 8074 num_pkts = 0;
8075
9f40dead 8076 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 8077
9f40dead 8078 tp->tx_prod++;
c76949a6
MC		 8079 num_pkts++;
8080
9f40dead
MC		 8081 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8082 tp->tx_prod);
09ee929c 8083 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 8084
8085 udelay(10);
8086
8087 for (i = 0; i < 10; i++) {
8088 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8089 HOSTCC_MODE_NOW);
8090
8091 udelay(10);
8092
8093 tx_idx = tp->hw_status->idx[0].tx_consumer;
8094 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 8095 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 8096 (rx_idx == (rx_start_idx + num_pkts)))
8097 break;
8098 }
8099
8100 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8101 dev_kfree_skb(skb);
8102
9f40dead 8103 if (tx_idx != tp->tx_prod)
c76949a6
MC		 8104 goto out;
8105
8106 if (rx_idx != rx_start_idx + num_pkts)
8107 goto out;
8108
8109 desc = &tp->rx_rcb[rx_start_idx];
8110 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8111 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8112 if (opaque_key != RXD_OPAQUE_RING_STD)
8113 goto out;
8114
8115 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8116 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8117 goto out;
8118
8119 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8120 if (rx_len != tx_len)
8121 goto out;
8122
8123 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8124
8125 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8126 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8127
8128 for (i = 14; i < tx_len; i++) {
8129 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8130 goto out;
8131 }
8132 err = 0;
8133
8134 /* tg3_free_rings will unmap and free the rx_skb */
8135out:
8136 return err;
8137}
8138
9f40dead
MC		 8139#define TG3_MAC_LOOPBACK_FAILED 1
8140#define TG3_PHY_LOOPBACK_FAILED 2
8141#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8142 TG3_PHY_LOOPBACK_FAILED)
8143
8144static int tg3_test_loopback(struct tg3 *tp)
8145{
8146 int err = 0;
8147
8148 if (!netif_running(tp->dev))
8149 return TG3_LOOPBACK_FAILED;
8150
8151 tg3_reset_hw(tp);
8152
8153 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8154 err |= TG3_MAC_LOOPBACK_FAILED;
8155 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8156 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8157 err |= TG3_PHY_LOOPBACK_FAILED;
8158 }
8159
8160 return err;
8161}
8162
4cafd3f5
MC		 8163static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8164 u64 *data)
8165{
566f86ad
MC		 8166 struct tg3 *tp = netdev_priv(dev);
8167
8168 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8169
8170 if (tg3_test_nvram(tp) != 0) {
8171 etest->flags |= ETH_TEST_FL_FAILED;
8172 data[0] = 1;
8173 }
ca43007a
MC		 8174 if (tg3_test_link(tp) != 0) {
8175 etest->flags |= ETH_TEST_FL_FAILED;
8176 data[1] = 1;
8177 }
a71116d1 8178 if (etest->flags & ETH_TEST_FL_OFFLINE) {
bbe832c0
MC		 8179 int irq_sync = 0;
8180
8181 if (netif_running(dev)) {
a71116d1 8182 tg3_netif_stop(tp);
bbe832c0
MC		 8183 irq_sync = 1;
8184 }
a71116d1 8185
bbe832c0 8186 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 8187
8188 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8189 tg3_nvram_lock(tp);
8190 tg3_halt_cpu(tp, RX_CPU_BASE);
8191 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8192 tg3_halt_cpu(tp, TX_CPU_BASE);
8193 tg3_nvram_unlock(tp);
8194
8195 if (tg3_test_registers(tp) != 0) {
8196 etest->flags |= ETH_TEST_FL_FAILED;
8197 data[2] = 1;
8198 }
7942e1db
MC		 8199 if (tg3_test_memory(tp) != 0) {
8200 etest->flags |= ETH_TEST_FL_FAILED;
8201 data[3] = 1;
8202 }
9f40dead 8203 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 8204 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 8205
f47c11ee
DM		 8206 tg3_full_unlock(tp);
8207
d4bc3927
MC		 8208 if (tg3_test_interrupt(tp) != 0) {
8209 etest->flags |= ETH_TEST_FL_FAILED;
8210 data[5] = 1;
8211 }
f47c11ee
DM		 8212
8213 tg3_full_lock(tp, 0);
d4bc3927 8214
a71116d1
MC		 8215 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8216 if (netif_running(dev)) {
8217 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8218 tg3_init_hw(tp);
8219 tg3_netif_start(tp);
8220 }
f47c11ee
DM		 8221
8222 tg3_full_unlock(tp);
a71116d1 8223 }
4cafd3f5
MC		 8224}
8225
1da177e4
LT		 8226static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8227{
8228 struct mii_ioctl_data *data = if_mii(ifr);
8229 struct tg3 *tp = netdev_priv(dev);
8230 int err;
8231
8232 switch(cmd) {
8233 case SIOCGMIIPHY:
8234 data->phy_id = PHY_ADDR;
8235
8236 /* fallthru */
8237 case SIOCGMIIREG: {
8238 u32 mii_regval;
8239
8240 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8241 break; /* We have no PHY */
8242
f47c11ee 8243 spin_lock_bh(&tp->lock);
1da177e4 8244 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 8245 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8246
8247 data->val_out = mii_regval;
8248
8249 return err;
8250 }
8251
8252 case SIOCSMIIREG:
8253 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8254 break; /* We have no PHY */
8255
8256 if (!capable(CAP_NET_ADMIN))
8257 return -EPERM;
8258
f47c11ee 8259 spin_lock_bh(&tp->lock);
1da177e4 8260 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 8261 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8262
8263 return err;
8264
8265 default:
8266 /* do nothing */
8267 break;
8268 }
8269 return -EOPNOTSUPP;
8270}
8271
8272#if TG3_VLAN_TAG_USED
8273static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8274{
8275 struct tg3 *tp = netdev_priv(dev);
8276
f47c11ee 8277 tg3_full_lock(tp, 0);
1da177e4
LT		 8278
8279 tp->vlgrp = grp;
8280
8281 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8282 __tg3_set_rx_mode(dev);
8283
f47c11ee 8284 tg3_full_unlock(tp);
1da177e4
LT		 8285}
8286
8287static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8288{
8289 struct tg3 *tp = netdev_priv(dev);
8290
f47c11ee 8291 tg3_full_lock(tp, 0);
1da177e4
LT		 8292 if (tp->vlgrp)
8293 tp->vlgrp->vlan_devices[vid] = NULL;
f47c11ee 8294 tg3_full_unlock(tp);
1da177e4
LT		 8295}
8296#endif
8297
15f9850d
DM		 8298static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8299{
8300 struct tg3 *tp = netdev_priv(dev);
8301
8302 memcpy(ec, &tp->coal, sizeof(*ec));
8303 return 0;
8304}
8305
d244c892
MC		 8306static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8307{
8308 struct tg3 *tp = netdev_priv(dev);
8309 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8310 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8311
8312 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8313 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8314 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8315 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8316 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8317 }
8318
8319 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8320 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8321 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8322 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8323 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8324 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8325 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8326 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8327 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8328 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8329 return -EINVAL;
8330
8331 /* No rx interrupts will be generated if both are zero */
8332 if ((ec->rx_coalesce_usecs == 0) &&
8333 (ec->rx_max_coalesced_frames == 0))
8334 return -EINVAL;
8335
8336 /* No tx interrupts will be generated if both are zero */
8337 if ((ec->tx_coalesce_usecs == 0) &&
8338 (ec->tx_max_coalesced_frames == 0))
8339 return -EINVAL;
8340
8341 /* Only copy relevant parameters, ignore all others. */
8342 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8343 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8344 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8345 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8346 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8347 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8348 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8349 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8350 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8351
8352 if (netif_running(dev)) {
8353 tg3_full_lock(tp, 0);
8354 __tg3_set_coalesce(tp, &tp->coal);
8355 tg3_full_unlock(tp);
8356 }
8357 return 0;
8358}
8359
1da177e4
LT		 8360static struct ethtool_ops tg3_ethtool_ops = {
8361 .get_settings = tg3_get_settings,
8362 .set_settings = tg3_set_settings,
8363 .get_drvinfo = tg3_get_drvinfo,
8364 .get_regs_len = tg3_get_regs_len,
8365 .get_regs = tg3_get_regs,
8366 .get_wol = tg3_get_wol,
8367 .set_wol = tg3_set_wol,
8368 .get_msglevel = tg3_get_msglevel,
8369 .set_msglevel = tg3_set_msglevel,
8370 .nway_reset = tg3_nway_reset,
8371 .get_link = ethtool_op_get_link,
8372 .get_eeprom_len = tg3_get_eeprom_len,
8373 .get_eeprom = tg3_get_eeprom,
8374 .set_eeprom = tg3_set_eeprom,
8375 .get_ringparam = tg3_get_ringparam,
8376 .set_ringparam = tg3_set_ringparam,
8377 .get_pauseparam = tg3_get_pauseparam,
8378 .set_pauseparam = tg3_set_pauseparam,
8379 .get_rx_csum = tg3_get_rx_csum,
8380 .set_rx_csum = tg3_set_rx_csum,
8381 .get_tx_csum = ethtool_op_get_tx_csum,
8382 .set_tx_csum = tg3_set_tx_csum,
8383 .get_sg = ethtool_op_get_sg,
8384 .set_sg = ethtool_op_set_sg,
8385#if TG3_TSO_SUPPORT != 0
8386 .get_tso = ethtool_op_get_tso,
8387 .set_tso = tg3_set_tso,
8388#endif
4cafd3f5
MC		 8389 .self_test_count = tg3_get_test_count,
8390 .self_test = tg3_self_test,
1da177e4 8391 .get_strings = tg3_get_strings,
4009a93d 8392 .phys_id = tg3_phys_id,
1da177e4
LT		 8393 .get_stats_count = tg3_get_stats_count,
8394 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 8395 .get_coalesce = tg3_get_coalesce,
d244c892 8396 .set_coalesce = tg3_set_coalesce,
2ff43697 8397 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 8398};
8399
8400static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8401{
8402 u32 cursize, val;
8403
8404 tp->nvram_size = EEPROM_CHIP_SIZE;
8405
8406 if (tg3_nvram_read(tp, 0, &val) != 0)
8407 return;
8408
8409 if (swab32(val) != TG3_EEPROM_MAGIC)
8410 return;
8411
8412 /*
8413 * Size the chip by reading offsets at increasing powers of two.
8414 * When we encounter our validation signature, we know the addressing
8415 * has wrapped around, and thus have our chip size.
8416 */
8417 cursize = 0x800;
8418
8419 while (cursize < tp->nvram_size) {
8420 if (tg3_nvram_read(tp, cursize, &val) != 0)
8421 return;
8422
8423 if (swab32(val) == TG3_EEPROM_MAGIC)
8424 break;
8425
8426 cursize <<= 1;
8427 }
8428
8429 tp->nvram_size = cursize;
8430}
8431
8432static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8433{
8434 u32 val;
8435
8436 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8437 if (val != 0) {
8438 tp->nvram_size = (val >> 16) * 1024;
8439 return;
8440 }
8441 }
8442 tp->nvram_size = 0x20000;
8443}
8444
8445static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8446{
8447 u32 nvcfg1;
8448
8449 nvcfg1 = tr32(NVRAM_CFG1);
8450 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8451 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8452 }
8453 else {
8454 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8455 tw32(NVRAM_CFG1, nvcfg1);
8456 }
8457
4c987487 8458 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 8459 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 8460 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8461 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8462 tp->nvram_jedecnum = JEDEC_ATMEL;
8463 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8464 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8465 break;
8466 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8467 tp->nvram_jedecnum = JEDEC_ATMEL;
8468 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8469 break;
8470 case FLASH_VENDOR_ATMEL_EEPROM:
8471 tp->nvram_jedecnum = JEDEC_ATMEL;
8472 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8473 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8474 break;
8475 case FLASH_VENDOR_ST:
8476 tp->nvram_jedecnum = JEDEC_ST;
8477 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8478 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8479 break;
8480 case FLASH_VENDOR_SAIFUN:
8481 tp->nvram_jedecnum = JEDEC_SAIFUN;
8482 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8483 break;
8484 case FLASH_VENDOR_SST_SMALL:
8485 case FLASH_VENDOR_SST_LARGE:
8486 tp->nvram_jedecnum = JEDEC_SST;
8487 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8488 break;
8489 }
8490 }
8491 else {
8492 tp->nvram_jedecnum = JEDEC_ATMEL;
8493 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8494 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8495 }
8496}
8497
361b4ac2
MC		 8498static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8499{
8500 u32 nvcfg1;
8501
8502 nvcfg1 = tr32(NVRAM_CFG1);
8503
e6af301b
MC		 8504 /* NVRAM protection for TPM */
8505 if (nvcfg1 & (1 << 27))
8506 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8507
361b4ac2
MC		 8508 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8509 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8510 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8511 tp->nvram_jedecnum = JEDEC_ATMEL;
8512 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8513 break;
8514 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8515 tp->nvram_jedecnum = JEDEC_ATMEL;
8516 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8517 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8518 break;
8519 case FLASH_5752VENDOR_ST_M45PE10:
8520 case FLASH_5752VENDOR_ST_M45PE20:
8521 case FLASH_5752VENDOR_ST_M45PE40:
8522 tp->nvram_jedecnum = JEDEC_ST;
8523 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8524 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8525 break;
8526 }
8527
8528 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8529 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8530 case FLASH_5752PAGE_SIZE_256:
8531 tp->nvram_pagesize = 256;
8532 break;
8533 case FLASH_5752PAGE_SIZE_512:
8534 tp->nvram_pagesize = 512;
8535 break;
8536 case FLASH_5752PAGE_SIZE_1K:
8537 tp->nvram_pagesize = 1024;
8538 break;
8539 case FLASH_5752PAGE_SIZE_2K:
8540 tp->nvram_pagesize = 2048;
8541 break;
8542 case FLASH_5752PAGE_SIZE_4K:
8543 tp->nvram_pagesize = 4096;
8544 break;
8545 case FLASH_5752PAGE_SIZE_264:
8546 tp->nvram_pagesize = 264;
8547 break;
8548 }
8549 }
8550 else {
8551 /* For eeprom, set pagesize to maximum eeprom size */
8552 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8553
8554 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8555 tw32(NVRAM_CFG1, nvcfg1);
8556 }
8557}
8558
1da177e4
LT		 8559/* Chips other than 5700/5701 use the NVRAM for fetching info. */
8560static void __devinit tg3_nvram_init(struct tg3 *tp)
8561{
8562 int j;
8563
8564 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8565 return;
8566
8567 tw32_f(GRC_EEPROM_ADDR,
8568 (EEPROM_ADDR_FSM_RESET |
8569 (EEPROM_DEFAULT_CLOCK_PERIOD <<
8570 EEPROM_ADDR_CLKPERD_SHIFT)));
8571
8572 /* XXX schedule_timeout() ... */
8573 for (j = 0; j < 100; j++)
8574 udelay(10);
8575
8576 /* Enable seeprom accesses. */
8577 tw32_f(GRC_LOCAL_CTRL,
8578 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8579 udelay(100);
8580
8581 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8582 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8583 tp->tg3_flags |= TG3_FLAG_NVRAM;
8584
381291b7 8585 tg3_nvram_lock(tp);
e6af301b 8586 tg3_enable_nvram_access(tp);
1da177e4 8587
361b4ac2
MC		 8588 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8589 tg3_get_5752_nvram_info(tp);
8590 else
8591 tg3_get_nvram_info(tp);
8592
1da177e4
LT		 8593 tg3_get_nvram_size(tp);
8594
e6af301b 8595 tg3_disable_nvram_access(tp);
381291b7 8596 tg3_nvram_unlock(tp);
1da177e4
LT		 8597
8598 } else {
8599 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8600
8601 tg3_get_eeprom_size(tp);
8602 }
8603}
8604
8605static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8606 u32 offset, u32 *val)
8607{
8608 u32 tmp;
8609 int i;
8610
8611 if (offset > EEPROM_ADDR_ADDR_MASK ||
8612 (offset % 4) != 0)
8613 return -EINVAL;
8614
8615 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8616 EEPROM_ADDR_DEVID_MASK |
8617 EEPROM_ADDR_READ);
8618 tw32(GRC_EEPROM_ADDR,
8619 tmp |
8620 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8621 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8622 EEPROM_ADDR_ADDR_MASK) |
8623 EEPROM_ADDR_READ | EEPROM_ADDR_START);
8624
8625 for (i = 0; i < 10000; i++) {
8626 tmp = tr32(GRC_EEPROM_ADDR);
8627
8628 if (tmp & EEPROM_ADDR_COMPLETE)
8629 break;
8630 udelay(100);
8631 }
8632 if (!(tmp & EEPROM_ADDR_COMPLETE))
8633 return -EBUSY;
8634
8635 *val = tr32(GRC_EEPROM_DATA);
8636 return 0;
8637}
8638
8639#define NVRAM_CMD_TIMEOUT 10000
8640
8641static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8642{
8643 int i;
8644
8645 tw32(NVRAM_CMD, nvram_cmd);
8646 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8647 udelay(10);
8648 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8649 udelay(10);
8650 break;
8651 }
8652 }
8653 if (i == NVRAM_CMD_TIMEOUT) {
8654 return -EBUSY;
8655 }
8656 return 0;
8657}
8658
8659static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8660{
8661 int ret;
8662
8663 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8664 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8665 return -EINVAL;
8666 }
8667
8668 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8669 return tg3_nvram_read_using_eeprom(tp, offset, val);
8670
8671 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8672 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8673 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8674
8675 offset = ((offset / tp->nvram_pagesize) <<
8676 ATMEL_AT45DB0X1B_PAGE_POS) +
8677 (offset % tp->nvram_pagesize);
8678 }
8679
8680 if (offset > NVRAM_ADDR_MSK)
8681 return -EINVAL;
8682
8683 tg3_nvram_lock(tp);
8684
e6af301b 8685 tg3_enable_nvram_access(tp);
1da177e4
LT		 8686
8687 tw32(NVRAM_ADDR, offset);
8688 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8689 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8690
8691 if (ret == 0)
8692 *val = swab32(tr32(NVRAM_RDDATA));
8693
e6af301b 8694 tg3_disable_nvram_access(tp);
1da177e4 8695
381291b7
MC		 8696 tg3_nvram_unlock(tp);
8697
1da177e4
LT		 8698 return ret;
8699}
8700
8701static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8702 u32 offset, u32 len, u8 *buf)
8703{
8704 int i, j, rc = 0;
8705 u32 val;
8706
8707 for (i = 0; i < len; i += 4) {
8708 u32 addr, data;
8709
8710 addr = offset + i;
8711
8712 memcpy(&data, buf + i, 4);
8713
8714 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8715
8716 val = tr32(GRC_EEPROM_ADDR);
8717 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8718
8719 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8720 EEPROM_ADDR_READ);
8721 tw32(GRC_EEPROM_ADDR, val |
8722 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8723 (addr & EEPROM_ADDR_ADDR_MASK) |
8724 EEPROM_ADDR_START |
8725 EEPROM_ADDR_WRITE);
8726
8727 for (j = 0; j < 10000; j++) {
8728 val = tr32(GRC_EEPROM_ADDR);
8729
8730 if (val & EEPROM_ADDR_COMPLETE)
8731 break;
8732 udelay(100);
8733 }
8734 if (!(val & EEPROM_ADDR_COMPLETE)) {
8735 rc = -EBUSY;
8736 break;
8737 }
8738 }
8739
8740 return rc;
8741}
8742
8743/* offset and length are dword aligned */
8744static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8745 u8 *buf)
8746{
8747 int ret = 0;
8748 u32 pagesize = tp->nvram_pagesize;
8749 u32 pagemask = pagesize - 1;
8750 u32 nvram_cmd;
8751 u8 *tmp;
8752
8753 tmp = kmalloc(pagesize, GFP_KERNEL);
8754 if (tmp == NULL)
8755 return -ENOMEM;
8756
8757 while (len) {
8758 int j;
e6af301b 8759 u32 phy_addr, page_off, size;
1da177e4
LT		 8760
8761 phy_addr = offset & ~pagemask;
8762
8763 for (j = 0; j < pagesize; j += 4) {
8764 if ((ret = tg3_nvram_read(tp, phy_addr + j,
8765 (u32 *) (tmp + j))))
8766 break;
8767 }
8768 if (ret)
8769 break;
8770
8771 page_off = offset & pagemask;
8772 size = pagesize;
8773 if (len < size)
8774 size = len;
8775
8776 len -= size;
8777
8778 memcpy(tmp + page_off, buf, size);
8779
8780 offset = offset + (pagesize - page_off);
8781
381291b7
MC		 8782 /* Nvram lock released by tg3_nvram_read() above,
8783 * so need to get it again.
8784 */
8785 tg3_nvram_lock(tp);
e6af301b 8786 tg3_enable_nvram_access(tp);
1da177e4
LT		 8787
8788 /*
8789 * Before we can erase the flash page, we need
8790 * to issue a special "write enable" command.
8791 */
8792 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8793
8794 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8795 break;
8796
8797 /* Erase the target page */
8798 tw32(NVRAM_ADDR, phy_addr);
8799
8800 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8801 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8802
8803 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8804 break;
8805
8806 /* Issue another write enable to start the write. */
8807 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8808
8809 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8810 break;
8811
8812 for (j = 0; j < pagesize; j += 4) {
8813 u32 data;
8814
8815 data = *((u32 *) (tmp + j));
8816 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8817
8818 tw32(NVRAM_ADDR, phy_addr + j);
8819
8820 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8821 NVRAM_CMD_WR;
8822
8823 if (j == 0)
8824 nvram_cmd |= NVRAM_CMD_FIRST;
8825 else if (j == (pagesize - 4))
8826 nvram_cmd |= NVRAM_CMD_LAST;
8827
8828 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8829 break;
8830 }
8831 if (ret)
8832 break;
8833 }
8834
8835 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8836 tg3_nvram_exec_cmd(tp, nvram_cmd);
8837
8838 kfree(tmp);
8839
8840 return ret;
8841}
8842
8843/* offset and length are dword aligned */
8844static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8845 u8 *buf)
8846{
8847 int i, ret = 0;
8848
8849 for (i = 0; i < len; i += 4, offset += 4) {
8850 u32 data, page_off, phy_addr, nvram_cmd;
8851
8852 memcpy(&data, buf + i, 4);
8853 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8854
8855 page_off = offset % tp->nvram_pagesize;
8856
8857 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8858 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8859
8860 phy_addr = ((offset / tp->nvram_pagesize) <<
8861 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8862 }
8863 else {
8864 phy_addr = offset;
8865 }
8866
8867 tw32(NVRAM_ADDR, phy_addr);
8868
8869 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8870
8871 if ((page_off == 0) || (i == 0))
8872 nvram_cmd |= NVRAM_CMD_FIRST;
8873 else if (page_off == (tp->nvram_pagesize - 4))
8874 nvram_cmd |= NVRAM_CMD_LAST;
8875
8876 if (i == (len - 4))
8877 nvram_cmd |= NVRAM_CMD_LAST;
8878
4c987487
MC		 8879 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
8880 (tp->nvram_jedecnum == JEDEC_ST) &&
8881 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 8882
8883 if ((ret = tg3_nvram_exec_cmd(tp,
8884 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8885 NVRAM_CMD_DONE)))
8886
8887 break;
8888 }
8889 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8890 /* We always do complete word writes to eeprom. */
8891 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8892 }
8893
8894 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8895 break;
8896 }
8897 return ret;
8898}
8899
8900/* offset and length are dword aligned */
8901static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8902{
8903 int ret;
8904
8905 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8906 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8907 return -EINVAL;
8908 }
8909
8910 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 8911 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8912 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 8913 udelay(40);
8914 }
8915
8916 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8917 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8918 }
8919 else {
8920 u32 grc_mode;
8921
8922 tg3_nvram_lock(tp);
8923
e6af301b
MC		 8924 tg3_enable_nvram_access(tp);
8925 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8926 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 8927 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 8928
8929 grc_mode = tr32(GRC_MODE);
8930 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8931
8932 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8933 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8934
8935 ret = tg3_nvram_write_block_buffered(tp, offset, len,
8936 buf);
8937 }
8938 else {
8939 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8940 buf);
8941 }
8942
8943 grc_mode = tr32(GRC_MODE);
8944 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8945
e6af301b 8946 tg3_disable_nvram_access(tp);
1da177e4
LT		 8947 tg3_nvram_unlock(tp);
8948 }
8949
8950 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 8951 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 8952 udelay(40);
8953 }
8954
8955 return ret;
8956}
8957
8958struct subsys_tbl_ent {
8959 u16 subsys_vendor, subsys_devid;
8960 u32 phy_id;
8961};
8962
8963static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8964 /* Broadcom boards. */
8965 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8966 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8967 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8968 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
8969 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8970 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8971 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
8972 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8973 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8974 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8975 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8976
8977 /* 3com boards. */
8978 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8979 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8980 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
8981 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8982 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8983
8984 /* DELL boards. */
8985 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8986 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8987 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8988 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8989
8990 /* Compaq boards. */
8991 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8992 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8993 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
8994 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8995 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8996
8997 /* IBM boards. */
8998 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8999};
9000
9001static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9002{
9003 int i;
9004
9005 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9006 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9007 tp->pdev->subsystem_vendor) &&
9008 (subsys_id_to_phy_id[i].subsys_devid ==
9009 tp->pdev->subsystem_device))
9010 return &subsys_id_to_phy_id[i];
9011 }
9012 return NULL;
9013}
9014
7d0c41ef
MC		 9015/* Since this function may be called in D3-hot power state during
9016 * tg3_init_one(), only config cycles are allowed.
9017 */
9018static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 9019{
1da177e4 9020 u32 val;
7d0c41ef
MC		 9021
9022 /* Make sure register accesses (indirect or otherwise)
9023 * will function correctly.
9024 */
9025 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9026 tp->misc_host_ctrl);
1da177e4
LT		 9027
9028 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 9029 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9030
1da177e4
LT		 9031 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9032 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9033 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 9034 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9035 int eeprom_phy_serdes = 0;
1da177e4
LT		 9036
9037 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9038 tp->nic_sram_data_cfg = nic_cfg;
9039
9040 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9041 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9042 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9043 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9044 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9045 (ver > 0) && (ver < 0x100))
9046 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9047
1da177e4
LT		 9048 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9049 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9050 eeprom_phy_serdes = 1;
9051
9052 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9053 if (nic_phy_id != 0) {
9054 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9055 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9056
9057 eeprom_phy_id = (id1 >> 16) << 10;
9058 eeprom_phy_id |= (id2 & 0xfc00) << 16;
9059 eeprom_phy_id |= (id2 & 0x03ff) << 0;
9060 } else
9061 eeprom_phy_id = 0;
9062
7d0c41ef 9063 tp->phy_id = eeprom_phy_id;
747e8f8b 9064 if (eeprom_phy_serdes) {
a4e2b347 9065 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 9066 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9067 else
9068 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9069 }
7d0c41ef 9070
cbf46853 9071 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9072 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9073 SHASTA_EXT_LED_MODE_MASK);
cbf46853 9074 else
1da177e4
LT		 9075 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9076
9077 switch (led_cfg) {
9078 default:
9079 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9080 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9081 break;
9082
9083 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9084 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9085 break;
9086
9087 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9088 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 9089
9090 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9091 * read on some older 5700/5701 bootcode.
9092 */
9093 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9094 ASIC_REV_5700 ||
9095 GET_ASIC_REV(tp->pci_chip_rev_id) ==
9096 ASIC_REV_5701)
9097 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9098
1da177e4
LT		 9099 break;
9100
9101 case SHASTA_EXT_LED_SHARED:
9102 tp->led_ctrl = LED_CTRL_MODE_SHARED;
9103 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9104 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9105 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9106 LED_CTRL_MODE_PHY_2);
9107 break;
9108
9109 case SHASTA_EXT_LED_MAC:
9110 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9111 break;
9112
9113 case SHASTA_EXT_LED_COMBO:
9114 tp->led_ctrl = LED_CTRL_MODE_COMBO;
9115 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9116 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9117 LED_CTRL_MODE_PHY_2);
9118 break;
9119
9120 };
9121
9122 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9123 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9124 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9125 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9126
9127 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9128 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9129 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
9130 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9131
9132 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9133 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 9134 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9135 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9136 }
9137 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9138 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9139
9140 if (cfg2 & (1 << 17))
9141 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9142
9143 /* serdes signal pre-emphasis in register 0x590 set by */
9144 /* bootcode if bit 18 is set */
9145 if (cfg2 & (1 << 18))
9146 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9147 }
7d0c41ef
MC		 9148}
9149
9150static int __devinit tg3_phy_probe(struct tg3 *tp)
9151{
9152 u32 hw_phy_id_1, hw_phy_id_2;
9153 u32 hw_phy_id, hw_phy_id_masked;
9154 int err;
1da177e4
LT		 9155
9156 /* Reading the PHY ID register can conflict with ASF
9157 * firwmare access to the PHY hardware.
9158 */
9159 err = 0;
9160 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9161 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9162 } else {
9163 /* Now read the physical PHY_ID from the chip and verify
9164 * that it is sane. If it doesn't look good, we fall back
9165 * to either the hard-coded table based PHY_ID and failing
9166 * that the value found in the eeprom area.
9167 */
9168 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9169 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9170
9171 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
9172 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9173 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
9174
9175 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9176 }
9177
9178 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9179 tp->phy_id = hw_phy_id;
9180 if (hw_phy_id_masked == PHY_ID_BCM8002)
9181 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 9182 else
9183 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 9184 } else {
7d0c41ef
MC		 9185 if (tp->phy_id != PHY_ID_INVALID) {
9186 /* Do nothing, phy ID already set up in
9187 * tg3_get_eeprom_hw_cfg().
9188 */
1da177e4
LT		 9189 } else {
9190 struct subsys_tbl_ent *p;
9191
9192 /* No eeprom signature? Try the hardcoded
9193 * subsys device table.
9194 */
9195 p = lookup_by_subsys(tp);
9196 if (!p)
9197 return -ENODEV;
9198
9199 tp->phy_id = p->phy_id;
9200 if (!tp->phy_id ||
9201 tp->phy_id == PHY_ID_BCM8002)
9202 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9203 }
9204 }
9205
747e8f8b 9206 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4
LT		 9207 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9208 u32 bmsr, adv_reg, tg3_ctrl;
9209
9210 tg3_readphy(tp, MII_BMSR, &bmsr);
9211 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9212 (bmsr & BMSR_LSTATUS))
9213 goto skip_phy_reset;
9214
9215 err = tg3_phy_reset(tp);
9216 if (err)
9217 return err;
9218
9219 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9220 ADVERTISE_100HALF | ADVERTISE_100FULL |
9221 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9222 tg3_ctrl = 0;
9223 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9224 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9225 MII_TG3_CTRL_ADV_1000_FULL);
9226 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9227 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9228 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9229 MII_TG3_CTRL_ENABLE_AS_MASTER);
9230 }
9231
9232 if (!tg3_copper_is_advertising_all(tp)) {
9233 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9234
9235 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9236 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9237
9238 tg3_writephy(tp, MII_BMCR,
9239 BMCR_ANENABLE | BMCR_ANRESTART);
9240 }
9241 tg3_phy_set_wirespeed(tp);
9242
9243 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9244 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9245 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9246 }
9247
9248skip_phy_reset:
9249 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9250 err = tg3_init_5401phy_dsp(tp);
9251 if (err)
9252 return err;
9253 }
9254
9255 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9256 err = tg3_init_5401phy_dsp(tp);
9257 }
9258
747e8f8b 9259 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 9260 tp->link_config.advertising =
9261 (ADVERTISED_1000baseT_Half |
9262 ADVERTISED_1000baseT_Full |
9263 ADVERTISED_Autoneg |
9264 ADVERTISED_FIBRE);
9265 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9266 tp->link_config.advertising &=
9267 ~(ADVERTISED_1000baseT_Half |
9268 ADVERTISED_1000baseT_Full);
9269
9270 return err;
9271}
9272
9273static void __devinit tg3_read_partno(struct tg3 *tp)
9274{
9275 unsigned char vpd_data[256];
9276 int i;
9277
9278 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9279 /* Sun decided not to put the necessary bits in the
9280 * NVRAM of their onboard tg3 parts :(
9281 */
9282 strcpy(tp->board_part_number, "Sun 570X");
9283 return;
9284 }
9285
9286 for (i = 0; i < 256; i += 4) {
9287 u32 tmp;
9288
9289 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9290 goto out_not_found;
9291
9292 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9293 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9294 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9295 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9296 }
9297
9298 /* Now parse and find the part number. */
9299 for (i = 0; i < 256; ) {
9300 unsigned char val = vpd_data[i];
9301 int block_end;
9302
9303 if (val == 0x82 || val == 0x91) {
9304 i = (i + 3 +
9305 (vpd_data[i + 1] +
9306 (vpd_data[i + 2] << 8)));
9307 continue;
9308 }
9309
9310 if (val != 0x90)
9311 goto out_not_found;
9312
9313 block_end = (i + 3 +
9314 (vpd_data[i + 1] +
9315 (vpd_data[i + 2] << 8)));
9316 i += 3;
9317 while (i < block_end) {
9318 if (vpd_data[i + 0] == 'P' &&
9319 vpd_data[i + 1] == 'N') {
9320 int partno_len = vpd_data[i + 2];
9321
9322 if (partno_len > 24)
9323 goto out_not_found;
9324
9325 memcpy(tp->board_part_number,
9326 &vpd_data[i + 3],
9327 partno_len);
9328
9329 /* Success. */
9330 return;
9331 }
9332 }
9333
9334 /* Part number not found. */
9335 goto out_not_found;
9336 }
9337
9338out_not_found:
9339 strcpy(tp->board_part_number, "none");
9340}
9341
9342#ifdef CONFIG_SPARC64
9343static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9344{
9345 struct pci_dev *pdev = tp->pdev;
9346 struct pcidev_cookie *pcp = pdev->sysdata;
9347
9348 if (pcp != NULL) {
9349 int node = pcp->prom_node;
9350 u32 venid;
9351 int err;
9352
9353 err = prom_getproperty(node, "subsystem-vendor-id",
9354 (char *) &venid, sizeof(venid));
9355 if (err == 0 || err == -1)
9356 return 0;
9357 if (venid == PCI_VENDOR_ID_SUN)
9358 return 1;
9359 }
9360 return 0;
9361}
9362#endif
9363
9364static int __devinit tg3_get_invariants(struct tg3 *tp)
9365{
9366 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 9367 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9368 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
399de50b
MC		 9369 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9370 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 9371 { },
9372 };
9373 u32 misc_ctrl_reg;
9374 u32 cacheline_sz_reg;
9375 u32 pci_state_reg, grc_misc_cfg;
9376 u32 val;
9377 u16 pci_cmd;
9378 int err;
9379
9380#ifdef CONFIG_SPARC64
9381 if (tg3_is_sun_570X(tp))
9382 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9383#endif
9384
1da177e4
LT		 9385 /* Force memory write invalidate off. If we leave it on,
9386 * then on 5700_BX chips we have to enable a workaround.
9387 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9388 * to match the cacheline size. The Broadcom driver have this
9389 * workaround but turns MWI off all the times so never uses
9390 * it. This seems to suggest that the workaround is insufficient.
9391 */
9392 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9393 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9394 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9395
9396 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9397 * has the register indirect write enable bit set before
9398 * we try to access any of the MMIO registers. It is also
9399 * critical that the PCI-X hw workaround situation is decided
9400 * before that as well.
9401 */
9402 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9403 &misc_ctrl_reg);
9404
9405 tp->pci_chip_rev_id = (misc_ctrl_reg >>
9406 MISC_HOST_CTRL_CHIPREV_SHIFT);
9407
ff645bec
MC		 9408 /* Wrong chip ID in 5752 A0. This code can be removed later
9409 * as A0 is not in production.
9410 */
9411 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
9412 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
9413
6892914f
MC		 9414 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
9415 * we need to disable memory and use config. cycles
9416 * only to access all registers. The 5702/03 chips
9417 * can mistakenly decode the special cycles from the
9418 * ICH chipsets as memory write cycles, causing corruption
9419 * of register and memory space. Only certain ICH bridges
9420 * will drive special cycles with non-zero data during the
9421 * address phase which can fall within the 5703's address
9422 * range. This is not an ICH bug as the PCI spec allows
9423 * non-zero address during special cycles. However, only
9424 * these ICH bridges are known to drive non-zero addresses
9425 * during special cycles.
9426 *
9427 * Since special cycles do not cross PCI bridges, we only
9428 * enable this workaround if the 5703 is on the secondary
9429 * bus of these ICH bridges.
9430 */
9431 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
9432 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
9433 static struct tg3_dev_id {
9434 u32 vendor;
9435 u32 device;
9436 u32 rev;
9437 } ich_chipsets[] = {
9438 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
9439 PCI_ANY_ID },
9440 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
9441 PCI_ANY_ID },
9442 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
9443 0xa },
9444 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
9445 PCI_ANY_ID },
9446 { },
9447 };
9448 struct tg3_dev_id *pci_id = &ich_chipsets[0];
9449 struct pci_dev *bridge = NULL;
9450
9451 while (pci_id->vendor != 0) {
9452 bridge = pci_get_device(pci_id->vendor, pci_id->device,
9453 bridge);
9454 if (!bridge) {
9455 pci_id++;
9456 continue;
9457 }
9458 if (pci_id->rev != PCI_ANY_ID) {
9459 u8 rev;
9460
9461 pci_read_config_byte(bridge, PCI_REVISION_ID,
9462 &rev);
9463 if (rev > pci_id->rev)
9464 continue;
9465 }
9466 if (bridge->subordinate &&
9467 (bridge->subordinate->number ==
9468 tp->pdev->bus->number)) {
9469
9470 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
9471 pci_dev_put(bridge);
9472 break;
9473 }
9474 }
9475 }
9476
4cf78e4f 9477 /* Find msi capability. */
a4e2b347
MC		 9478 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
9479 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9480 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4cf78e4f 9481 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 9482 }
4cf78e4f 9483
1da177e4
LT		 9484 /* Initialize misc host control in PCI block. */
9485 tp->misc_host_ctrl |= (misc_ctrl_reg &
9486 MISC_HOST_CTRL_CHIPREV);
9487 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9488 tp->misc_host_ctrl);
9489
9490 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9491 &cacheline_sz_reg);
9492
9493 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
9494 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
9495 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
9496 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
9497
6708e5cc 9498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 9499 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
a4e2b347 9500 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 9501 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
9502
1b440c56
JL		 9503 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9504 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9505 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9506
bb7064dc 9507 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9508 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9509
0f893dc6
MC		 9510 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9511 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9512 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9513 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9514
1da177e4
LT		 9515 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9516 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9517
399de50b
MC		 9518 /* If we have an AMD 762 or VIA K8T800 chipset, write
9519 * reordering to the mailbox registers done by the host
9520 * controller can cause major troubles. We read back from
9521 * every mailbox register write to force the writes to be
9522 * posted to the chip in order.
9523 */
9524 if (pci_dev_present(write_reorder_chipsets) &&
9525 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9526 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9527
1da177e4
LT		 9528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9529 tp->pci_lat_timer < 64) {
9530 tp->pci_lat_timer = 64;
9531
9532 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
9533 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
9534 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
9535 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
9536
9537 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9538 cacheline_sz_reg);
9539 }
9540
9541 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9542 &pci_state_reg);
9543
9544 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9545 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9546
9547 /* If this is a 5700 BX chipset, and we are in PCI-X
9548 * mode, enable register write workaround.
9549 *
9550 * The workaround is to use indirect register accesses
9551 * for all chip writes not to mailbox registers.
9552 */
9553 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9554 u32 pm_reg;
9555 u16 pci_cmd;
9556
9557 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9558
9559 /* The chip can have it's power management PCI config
9560 * space registers clobbered due to this bug.
9561 * So explicitly force the chip into D0 here.
9562 */
9563 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9564 &pm_reg);
9565 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9566 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9567 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9568 pm_reg);
9569
9570 /* Also, force SERR#/PERR# in PCI command. */
9571 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9572 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9573 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9574 }
9575 }
9576
087fe256
MC		 9577 /* 5700 BX chips need to have their TX producer index mailboxes
9578 * written twice to workaround a bug.
9579 */
9580 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9581 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9582
1da177e4
LT		 9583 /* Back to back register writes can cause problems on this chip,
9584 * the workaround is to read back all reg writes except those to
9585 * mailbox regs. See tg3_write_indirect_reg32().
9586 *
9587 * PCI Express 5750_A0 rev chips need this workaround too.
9588 */
9589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9590 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9591 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9592 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9593
9594 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9595 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9596 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9597 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9598
9599 /* Chip-specific fixup from Broadcom driver */
9600 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9601 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9602 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9603 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9604 }
9605
1ee582d8 9606 /* Default fast path register access methods */
20094930 9607 tp->read32 = tg3_read32;
1ee582d8 9608 tp->write32 = tg3_write32;
09ee929c 9609 tp->read32_mbox = tg3_read32;
20094930 9610 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 9611 tp->write32_tx_mbox = tg3_write32;
9612 tp->write32_rx_mbox = tg3_write32;
9613
9614 /* Various workaround register access methods */
9615 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
9616 tp->write32 = tg3_write_indirect_reg32;
9617 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
9618 tp->write32 = tg3_write_flush_reg32;
9619
9620 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
9621 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
9622 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9623 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
9624 tp->write32_rx_mbox = tg3_write_flush_reg32;
9625 }
20094930 9626
6892914f
MC		 9627 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
9628 tp->read32 = tg3_read_indirect_reg32;
9629 tp->write32 = tg3_write_indirect_reg32;
9630 tp->read32_mbox = tg3_read_indirect_mbox;
9631 tp->write32_mbox = tg3_write_indirect_mbox;
9632 tp->write32_tx_mbox = tg3_write_indirect_mbox;
9633 tp->write32_rx_mbox = tg3_write_indirect_mbox;
9634
9635 iounmap(tp->regs);
22abe310 9636 tp->regs = NULL;
6892914f
MC		 9637
9638 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9639 pci_cmd &= ~PCI_COMMAND_MEMORY;
9640 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9641 }
9642
7d0c41ef
MC		 9643 /* Get eeprom hw config before calling tg3_set_power_state().
9644 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9645 * determined before calling tg3_set_power_state() so that
9646 * we know whether or not to switch out of Vaux power.
9647 * When the flag is set, it means that GPIO1 is used for eeprom
9648 * write protect and also implies that it is a LOM where GPIOs
9649 * are not used to switch power.
9650 */
9651 tg3_get_eeprom_hw_cfg(tp);
9652
314fba34
MC		 9653 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9654 * GPIO1 driven high will bring 5700's external PHY out of reset.
9655 * It is also used as eeprom write protect on LOMs.
9656 */
9657 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9658 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9659 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9660 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9661 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 9662 /* Unused GPIO3 must be driven as output on 5752 because there
9663 * are no pull-up resistors on unused GPIO pins.
9664 */
9665 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9666 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 9667
1da177e4
LT		 9668 /* Force the chip into D0. */
9669 err = tg3_set_power_state(tp, 0);
9670 if (err) {
9671 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9672 pci_name(tp->pdev));
9673 return err;
9674 }
9675
9676 /* 5700 B0 chips do not support checksumming correctly due
9677 * to hardware bugs.
9678 */
9679 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9680 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9681
9682 /* Pseudo-header checksum is done by hardware logic and not
9683 * the offload processers, so make the chip do the pseudo-
9684 * header checksums on receive. For transmit it is more
9685 * convenient to do the pseudo-header checksum in software
9686 * as Linux does that on transmit for us in all cases.
9687 */
9688 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9689 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9690
9691 /* Derive initial jumbo mode from MTU assigned in
9692 * ether_setup() via the alloc_etherdev() call
9693 */
0f893dc6 9694 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 9695 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 9696 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 9697
9698 /* Determine WakeOnLan speed to use. */
9699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9700 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9701 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9702 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9703 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9704 } else {
9705 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9706 }
9707
9708 /* A few boards don't want Ethernet@WireSpeed phy feature */
9709 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9710 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9711 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b
MC		 9712 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9713 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 9714 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9715
9716 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9717 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9718 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9719 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9720 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9721
bb7064dc 9722 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
1da177e4
LT		 9723 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9724
1da177e4 9725 tp->coalesce_mode = 0;
1da177e4
LT		 9726 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9727 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9728 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9729
9730 /* Initialize MAC MI mode, polling disabled. */
9731 tw32_f(MAC_MI_MODE, tp->mi_mode);
9732 udelay(80);
9733
9734 /* Initialize data/descriptor byte/word swapping. */
9735 val = tr32(GRC_MODE);
9736 val &= GRC_MODE_HOST_STACKUP;
9737 tw32(GRC_MODE, val | tp->grc_mode);
9738
9739 tg3_switch_clocks(tp);
9740
9741 /* Clear this out for sanity. */
9742 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9743
9744 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9745 &pci_state_reg);
9746 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9747 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9748 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9749
9750 if (chiprevid == CHIPREV_ID_5701_A0 ||
9751 chiprevid == CHIPREV_ID_5701_B0 ||
9752 chiprevid == CHIPREV_ID_5701_B2 ||
9753 chiprevid == CHIPREV_ID_5701_B5) {
9754 void __iomem *sram_base;
9755
9756 /* Write some dummy words into the SRAM status block
9757 * area, see if it reads back correctly. If the return
9758 * value is bad, force enable the PCIX workaround.
9759 */
9760 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9761
9762 writel(0x00000000, sram_base);
9763 writel(0x00000000, sram_base + 4);
9764 writel(0xffffffff, sram_base + 4);
9765 if (readl(sram_base) != 0x00000000)
9766 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9767 }
9768 }
9769
9770 udelay(50);
9771 tg3_nvram_init(tp);
9772
9773 grc_misc_cfg = tr32(GRC_MISC_CFG);
9774 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9775
9776 /* Broadcom's driver says that CIOBE multisplit has a bug */
9777#if 0
9778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9779 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9780 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9781 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9782 }
9783#endif
9784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9785 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9786 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9787 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9788
fac9b83e
DM		 9789 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9790 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9791 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9792 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9793 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9794 HOSTCC_MODE_CLRTICK_TXBD);
9795
9796 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9797 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9798 tp->misc_host_ctrl);
9799 }
9800
1da177e4
LT		 9801 /* these are limited to 10/100 only */
9802 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9803 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9804 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9805 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9806 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9807 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9808 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9809 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9810 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9811 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9812 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9813
9814 err = tg3_phy_probe(tp);
9815 if (err) {
9816 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9817 pci_name(tp->pdev), err);
9818 /* ... but do not return immediately ... */
9819 }
9820
9821 tg3_read_partno(tp);
9822
9823 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9824 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9825 } else {
9826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9827 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9828 else
9829 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9830 }
9831
9832 /* 5700 {AX,BX} chips have a broken status block link
9833 * change bit implementation, so we must use the
9834 * status register in those cases.
9835 */
9836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9837 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9838 else
9839 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9840
9841 /* The led_ctrl is set during tg3_phy_probe, here we might
9842 * have to force the link status polling mechanism based
9843 * upon subsystem IDs.
9844 */
9845 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9846 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9847 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9848 TG3_FLAG_USE_LINKCHG_REG);
9849 }
9850
9851 /* For all SERDES we poll the MAC status register. */
9852 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9853 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9854 else
9855 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9856
1da177e4
LT		 9857 /* It seems all chips can get confused if TX buffers
9858 * straddle the 4GB address boundary in some cases.
9859 */
9860 tp->dev->hard_start_xmit = tg3_start_xmit;
9861
9862 tp->rx_offset = 2;
9863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9864 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9865 tp->rx_offset = 0;
9866
9867 /* By default, disable wake-on-lan. User can change this
9868 * using ETHTOOL_SWOL.
9869 */
9870 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9871
9872 return err;
9873}
9874
9875#ifdef CONFIG_SPARC64
9876static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9877{
9878 struct net_device *dev = tp->dev;
9879 struct pci_dev *pdev = tp->pdev;
9880 struct pcidev_cookie *pcp = pdev->sysdata;
9881
9882 if (pcp != NULL) {
9883 int node = pcp->prom_node;
9884
9885 if (prom_getproplen(node, "local-mac-address") == 6) {
9886 prom_getproperty(node, "local-mac-address",
9887 dev->dev_addr, 6);
2ff43697 9888 memcpy(dev->perm_addr, dev->dev_addr, 6);
1da177e4
LT		 9889 return 0;
9890 }
9891 }
9892 return -ENODEV;
9893}
9894
9895static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9896{
9897 struct net_device *dev = tp->dev;
9898
9899 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 9900 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 9901 return 0;
9902}
9903#endif
9904
9905static int __devinit tg3_get_device_address(struct tg3 *tp)
9906{
9907 struct net_device *dev = tp->dev;
9908 u32 hi, lo, mac_offset;
9909
9910#ifdef CONFIG_SPARC64
9911 if (!tg3_get_macaddr_sparc(tp))
9912 return 0;
9913#endif
9914
9915 mac_offset = 0x7c;
4cf78e4f
MC		 9916 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9917 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
a4e2b347 9918 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9919 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9920 mac_offset = 0xcc;
9921 if (tg3_nvram_lock(tp))
9922 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9923 else
9924 tg3_nvram_unlock(tp);
9925 }
9926
9927 /* First try to get it from MAC address mailbox. */
9928 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9929 if ((hi >> 16) == 0x484b) {
9930 dev->dev_addr[0] = (hi >> 8) & 0xff;
9931 dev->dev_addr[1] = (hi >> 0) & 0xff;
9932
9933 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9934 dev->dev_addr[2] = (lo >> 24) & 0xff;
9935 dev->dev_addr[3] = (lo >> 16) & 0xff;
9936 dev->dev_addr[4] = (lo >> 8) & 0xff;
9937 dev->dev_addr[5] = (lo >> 0) & 0xff;
9938 }
9939 /* Next, try NVRAM. */
9940 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9941 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9942 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9943 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9944 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9945 dev->dev_addr[2] = ((lo >> 0) & 0xff);
9946 dev->dev_addr[3] = ((lo >> 8) & 0xff);
9947 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9948 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9949 }
9950 /* Finally just fetch it out of the MAC control regs. */
9951 else {
9952 hi = tr32(MAC_ADDR_0_HIGH);
9953 lo = tr32(MAC_ADDR_0_LOW);
9954
9955 dev->dev_addr[5] = lo & 0xff;
9956 dev->dev_addr[4] = (lo >> 8) & 0xff;
9957 dev->dev_addr[3] = (lo >> 16) & 0xff;
9958 dev->dev_addr[2] = (lo >> 24) & 0xff;
9959 dev->dev_addr[1] = hi & 0xff;
9960 dev->dev_addr[0] = (hi >> 8) & 0xff;
9961 }
9962
9963 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9964#ifdef CONFIG_SPARC64
9965 if (!tg3_get_default_macaddr_sparc(tp))
9966 return 0;
9967#endif
9968 return -EINVAL;
9969 }
2ff43697 9970 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 9971 return 0;
9972}
9973
59e6b434
DM		 9974#define BOUNDARY_SINGLE_CACHELINE 1
9975#define BOUNDARY_MULTI_CACHELINE 2
9976
9977static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9978{
9979 int cacheline_size;
9980 u8 byte;
9981 int goal;
9982
9983 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9984 if (byte == 0)
9985 cacheline_size = 1024;
9986 else
9987 cacheline_size = (int) byte * 4;
9988
9989 /* On 5703 and later chips, the boundary bits have no
9990 * effect.
9991 */
9992 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9993 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9994 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9995 goto out;
9996
9997#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9998 goal = BOUNDARY_MULTI_CACHELINE;
9999#else
10000#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10001 goal = BOUNDARY_SINGLE_CACHELINE;
10002#else
10003 goal = 0;
10004#endif
10005#endif
10006
10007 if (!goal)
10008 goto out;
10009
10010 /* PCI controllers on most RISC systems tend to disconnect
10011 * when a device tries to burst across a cache-line boundary.
10012 * Therefore, letting tg3 do so just wastes PCI bandwidth.
10013 *
10014 * Unfortunately, for PCI-E there are only limited
10015 * write-side controls for this, and thus for reads
10016 * we will still get the disconnects. We'll also waste
10017 * these PCI cycles for both read and write for chips
10018 * other than 5700 and 5701 which do not implement the
10019 * boundary bits.
10020 */
10021 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10022 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10023 switch (cacheline_size) {
10024 case 16:
10025 case 32:
10026 case 64:
10027 case 128:
10028 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10029 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10030 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10031 } else {
10032 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10033 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10034 }
10035 break;
10036
10037 case 256:
10038 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10039 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10040 break;
10041
10042 default:
10043 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10044 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10045 break;
10046 };
10047 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10048 switch (cacheline_size) {
10049 case 16:
10050 case 32:
10051 case 64:
10052 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10053 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10054 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10055 break;
10056 }
10057 /* fallthrough */
10058 case 128:
10059 default:
10060 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10061 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10062 break;
10063 };
10064 } else {
10065 switch (cacheline_size) {
10066 case 16:
10067 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10068 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10069 DMA_RWCTRL_WRITE_BNDRY_16);
10070 break;
10071 }
10072 /* fallthrough */
10073 case 32:
10074 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10075 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10076 DMA_RWCTRL_WRITE_BNDRY_32);
10077 break;
10078 }
10079 /* fallthrough */
10080 case 64:
10081 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10082 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10083 DMA_RWCTRL_WRITE_BNDRY_64);
10084 break;
10085 }
10086 /* fallthrough */
10087 case 128:
10088 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10089 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10090 DMA_RWCTRL_WRITE_BNDRY_128);
10091 break;
10092 }
10093 /* fallthrough */
10094 case 256:
10095 val |= (DMA_RWCTRL_READ_BNDRY_256 |
10096 DMA_RWCTRL_WRITE_BNDRY_256);
10097 break;
10098 case 512:
10099 val |= (DMA_RWCTRL_READ_BNDRY_512 |
10100 DMA_RWCTRL_WRITE_BNDRY_512);
10101 break;
10102 case 1024:
10103 default:
10104 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10105 DMA_RWCTRL_WRITE_BNDRY_1024);
10106 break;
10107 };
10108 }
10109
10110out:
10111 return val;
10112}
10113
1da177e4
LT		 10114static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10115{
10116 struct tg3_internal_buffer_desc test_desc;
10117 u32 sram_dma_descs;
10118 int i, ret;
10119
10120 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10121
10122 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10123 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10124 tw32(RDMAC_STATUS, 0);
10125 tw32(WDMAC_STATUS, 0);
10126
10127 tw32(BUFMGR_MODE, 0);
10128 tw32(FTQ_RESET, 0);
10129
10130 test_desc.addr_hi = ((u64) buf_dma) >> 32;
10131 test_desc.addr_lo = buf_dma & 0xffffffff;
10132 test_desc.nic_mbuf = 0x00002100;
10133 test_desc.len = size;
10134
10135 /*
10136 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10137 * the *second* time the tg3 driver was getting loaded after an
10138 * initial scan.
10139 *
10140 * Broadcom tells me:
10141 * ...the DMA engine is connected to the GRC block and a DMA
10142 * reset may affect the GRC block in some unpredictable way...
10143 * The behavior of resets to individual blocks has not been tested.
10144 *
10145 * Broadcom noted the GRC reset will also reset all sub-components.
10146 */
10147 if (to_device) {
10148 test_desc.cqid_sqid = (13 << 8) | 2;
10149
10150 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10151 udelay(40);
10152 } else {
10153 test_desc.cqid_sqid = (16 << 8) | 7;
10154
10155 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10156 udelay(40);
10157 }
10158 test_desc.flags = 0x00000005;
10159
10160 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10161 u32 val;
10162
10163 val = *(((u32 *)&test_desc) + i);
10164 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10165 sram_dma_descs + (i * sizeof(u32)));
10166 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10167 }
10168 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10169
10170 if (to_device) {
10171 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10172 } else {
10173 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10174 }
10175
10176 ret = -ENODEV;
10177 for (i = 0; i < 40; i++) {
10178 u32 val;
10179
10180 if (to_device)
10181 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10182 else
10183 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10184 if ((val & 0xffff) == sram_dma_descs) {
10185 ret = 0;
10186 break;
10187 }
10188
10189 udelay(100);
10190 }
10191
10192 return ret;
10193}
10194
ded7340d 10195#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 10196
10197static int __devinit tg3_test_dma(struct tg3 *tp)
10198{
10199 dma_addr_t buf_dma;
59e6b434 10200 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 10201 int ret;
10202
10203 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10204 if (!buf) {
10205 ret = -ENOMEM;
10206 goto out_nofree;
10207 }
10208
10209 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10210 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10211
59e6b434 10212 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 10213
10214 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10215 /* DMA read watermark not used on PCIE */
10216 tp->dma_rwctrl |= 0x00180000;
10217 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 10218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10219 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 10220 tp->dma_rwctrl |= 0x003f0000;
10221 else
10222 tp->dma_rwctrl |= 0x003f000f;
10223 } else {
10224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10226 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10227
10228 if (ccval == 0x6 || ccval == 0x7)
10229 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10230
59e6b434 10231 /* Set bit 23 to enable PCIX hw bug fix */
1da177e4 10232 tp->dma_rwctrl |= 0x009f0000;
4cf78e4f
MC		 10233 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10234 /* 5780 always in PCIX mode */
10235 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 10236 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10237 /* 5714 always in PCIX mode */
10238 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 10239 } else {
10240 tp->dma_rwctrl |= 0x001b000f;
10241 }
10242 }
10243
10244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10245 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10246 tp->dma_rwctrl &= 0xfffffff0;
10247
10248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10250 /* Remove this if it causes problems for some boards. */
10251 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10252
10253 /* On 5700/5701 chips, we need to set this bit.
10254 * Otherwise the chip will issue cacheline transactions
10255 * to streamable DMA memory with not all the byte
10256 * enables turned on. This is an error on several
10257 * RISC PCI controllers, in particular sparc64.
10258 *
10259 * On 5703/5704 chips, this bit has been reassigned
10260 * a different meaning. In particular, it is used
10261 * on those chips to enable a PCI-X workaround.
10262 */
10263 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10264 }
10265
10266 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10267
10268#if 0
10269 /* Unneeded, already done by tg3_get_invariants. */
10270 tg3_switch_clocks(tp);
10271#endif
10272
10273 ret = 0;
10274 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10275 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10276 goto out;
10277
59e6b434
DM		 10278 /* It is best to perform DMA test with maximum write burst size
10279 * to expose the 5700/5701 write DMA bug.
10280 */
10281 saved_dma_rwctrl = tp->dma_rwctrl;
10282 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10283 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10284
1da177e4
LT		 10285 while (1) {
10286 u32 *p = buf, i;
10287
10288 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10289 p[i] = i;
10290
10291 /* Send the buffer to the chip. */
10292 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10293 if (ret) {
10294 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10295 break;
10296 }
10297
10298#if 0
10299 /* validate data reached card RAM correctly. */
10300 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10301 u32 val;
10302 tg3_read_mem(tp, 0x2100 + (i*4), &val);
10303 if (le32_to_cpu(val) != p[i]) {
10304 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
10305 /* ret = -ENODEV here? */
10306 }
10307 p[i] = 0;
10308 }
10309#endif
10310 /* Now read it back. */
10311 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10312 if (ret) {
10313 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10314
10315 break;
10316 }
10317
10318 /* Verify it. */
10319 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10320 if (p[i] == i)
10321 continue;
10322
59e6b434
DM		 10323 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10324 DMA_RWCTRL_WRITE_BNDRY_16) {
10325 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 10326 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10327 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10328 break;
10329 } else {
10330 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10331 ret = -ENODEV;
10332 goto out;
10333 }
10334 }
10335
10336 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10337 /* Success. */
10338 ret = 0;
10339 break;
10340 }
10341 }
59e6b434
DM		 10342 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10343 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 10344 static struct pci_device_id dma_wait_state_chipsets[] = {
10345 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10346 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10347 { },
10348 };
10349
59e6b434 10350 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 10351 * now look for chipsets that are known to expose the
10352 * DMA bug without failing the test.
59e6b434 10353 */
6d1cfbab
MC		 10354 if (pci_dev_present(dma_wait_state_chipsets)) {
10355 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10356 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10357 }
10358 else
10359 /* Safe to use the calculated DMA boundary. */
10360 tp->dma_rwctrl = saved_dma_rwctrl;
10361
59e6b434
DM		 10362 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10363 }
1da177e4
LT		 10364
10365out:
10366 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
10367out_nofree:
10368 return ret;
10369}
10370
10371static void __devinit tg3_init_link_config(struct tg3 *tp)
10372{
10373 tp->link_config.advertising =
10374 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10375 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10376 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
10377 ADVERTISED_Autoneg | ADVERTISED_MII);
10378 tp->link_config.speed = SPEED_INVALID;
10379 tp->link_config.duplex = DUPLEX_INVALID;
10380 tp->link_config.autoneg = AUTONEG_ENABLE;
10381 netif_carrier_off(tp->dev);
10382 tp->link_config.active_speed = SPEED_INVALID;
10383 tp->link_config.active_duplex = DUPLEX_INVALID;
10384 tp->link_config.phy_is_low_power = 0;
10385 tp->link_config.orig_speed = SPEED_INVALID;
10386 tp->link_config.orig_duplex = DUPLEX_INVALID;
10387 tp->link_config.orig_autoneg = AUTONEG_INVALID;
10388}
10389
10390static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
10391{
fdfec172
MC		 10392 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10393 tp->bufmgr_config.mbuf_read_dma_low_water =
10394 DEFAULT_MB_RDMA_LOW_WATER_5705;
10395 tp->bufmgr_config.mbuf_mac_rx_low_water =
10396 DEFAULT_MB_MACRX_LOW_WATER_5705;
10397 tp->bufmgr_config.mbuf_high_water =
10398 DEFAULT_MB_HIGH_WATER_5705;
10399
10400 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10401 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10402 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10403 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10404 tp->bufmgr_config.mbuf_high_water_jumbo =
10405 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10406 } else {
10407 tp->bufmgr_config.mbuf_read_dma_low_water =
10408 DEFAULT_MB_RDMA_LOW_WATER;
10409 tp->bufmgr_config.mbuf_mac_rx_low_water =
10410 DEFAULT_MB_MACRX_LOW_WATER;
10411 tp->bufmgr_config.mbuf_high_water =
10412 DEFAULT_MB_HIGH_WATER;
10413
10414 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10415 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
10416 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10417 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
10418 tp->bufmgr_config.mbuf_high_water_jumbo =
10419 DEFAULT_MB_HIGH_WATER_JUMBO;
10420 }
1da177e4
LT		 10421
10422 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
10423 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
10424}
10425
10426static char * __devinit tg3_phy_string(struct tg3 *tp)
10427{
10428 switch (tp->phy_id & PHY_ID_MASK) {
10429 case PHY_ID_BCM5400: return "5400";
10430 case PHY_ID_BCM5401: return "5401";
10431 case PHY_ID_BCM5411: return "5411";
10432 case PHY_ID_BCM5701: return "5701";
10433 case PHY_ID_BCM5703: return "5703";
10434 case PHY_ID_BCM5704: return "5704";
10435 case PHY_ID_BCM5705: return "5705";
10436 case PHY_ID_BCM5750: return "5750";
85e94ced 10437 case PHY_ID_BCM5752: return "5752";
a4e2b347 10438 case PHY_ID_BCM5714: return "5714";
4cf78e4f 10439 case PHY_ID_BCM5780: return "5780";
1da177e4
LT		 10440 case PHY_ID_BCM8002: return "8002/serdes";
10441 case 0: return "serdes";
10442 default: return "unknown";
10443 };
10444}
10445
f9804ddb
MC		 10446static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10447{
10448 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10449 strcpy(str, "PCI Express");
10450 return str;
10451 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
10452 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
10453
10454 strcpy(str, "PCIX:");
10455
10456 if ((clock_ctrl == 7) ||
10457 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
10458 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
10459 strcat(str, "133MHz");
10460 else if (clock_ctrl == 0)
10461 strcat(str, "33MHz");
10462 else if (clock_ctrl == 2)
10463 strcat(str, "50MHz");
10464 else if (clock_ctrl == 4)
10465 strcat(str, "66MHz");
10466 else if (clock_ctrl == 6)
10467 strcat(str, "100MHz");
10468 else if (clock_ctrl == 7)
10469 strcat(str, "133MHz");
10470 } else {
10471 strcpy(str, "PCI:");
10472 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
10473 strcat(str, "66MHz");
10474 else
10475 strcat(str, "33MHz");
10476 }
10477 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
10478 strcat(str, ":32-bit");
10479 else
10480 strcat(str, ":64-bit");
10481 return str;
10482}
10483
8c2dc7e1 10484static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 10485{
10486 struct pci_dev *peer;
10487 unsigned int func, devnr = tp->pdev->devfn & ~7;
10488
10489 for (func = 0; func < 8; func++) {
10490 peer = pci_get_slot(tp->pdev->bus, devnr | func);
10491 if (peer && peer != tp->pdev)
10492 break;
10493 pci_dev_put(peer);
10494 }
16fe9d74
MC		 10495 /* 5704 can be configured in single-port mode, set peer to
10496 * tp->pdev in that case.
10497 */
10498 if (!peer) {
10499 peer = tp->pdev;
10500 return peer;
10501 }
1da177e4
LT		 10502
10503 /*
10504 * We don't need to keep the refcount elevated; there's no way
10505 * to remove one half of this device without removing the other
10506 */
10507 pci_dev_put(peer);
10508
10509 return peer;
10510}
10511
15f9850d
DM		 10512static void __devinit tg3_init_coal(struct tg3 *tp)
10513{
10514 struct ethtool_coalesce *ec = &tp->coal;
10515
10516 memset(ec, 0, sizeof(*ec));
10517 ec->cmd = ETHTOOL_GCOALESCE;
10518 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
10519 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
10520 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
10521 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
10522 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
10523 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
10524 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
10525 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
10526 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
10527
10528 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
10529 HOSTCC_MODE_CLRTICK_TXBD)) {
10530 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
10531 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
10532 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
10533 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
10534 }
d244c892
MC		 10535
10536 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10537 ec->rx_coalesce_usecs_irq = 0;
10538 ec->tx_coalesce_usecs_irq = 0;
10539 ec->stats_block_coalesce_usecs = 0;
10540 }
15f9850d
DM		 10541}
10542
1da177e4
LT		 10543static int __devinit tg3_init_one(struct pci_dev *pdev,
10544 const struct pci_device_id *ent)
10545{
10546 static int tg3_version_printed = 0;
10547 unsigned long tg3reg_base, tg3reg_len;
10548 struct net_device *dev;
10549 struct tg3 *tp;
10550 int i, err, pci_using_dac, pm_cap;
f9804ddb 10551 char str[40];
1da177e4
LT		 10552
10553 if (tg3_version_printed++ == 0)
10554 printk(KERN_INFO "%s", version);
10555
10556 err = pci_enable_device(pdev);
10557 if (err) {
10558 printk(KERN_ERR PFX "Cannot enable PCI device, "
10559 "aborting.\n");
10560 return err;
10561 }
10562
10563 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10564 printk(KERN_ERR PFX "Cannot find proper PCI device "
10565 "base address, aborting.\n");
10566 err = -ENODEV;
10567 goto err_out_disable_pdev;
10568 }
10569
10570 err = pci_request_regions(pdev, DRV_MODULE_NAME);
10571 if (err) {
10572 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
10573 "aborting.\n");
10574 goto err_out_disable_pdev;
10575 }
10576
10577 pci_set_master(pdev);
10578
10579 /* Find power-management capability. */
10580 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10581 if (pm_cap == 0) {
10582 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
10583 "aborting.\n");
10584 err = -EIO;
10585 goto err_out_free_res;
10586 }
10587
10588 /* Configure DMA attributes. */
f9a5f7d3 10589 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1da177e4
LT		 10590 if (!err) {
10591 pci_using_dac = 1;
f9a5f7d3 10592 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1da177e4
LT		 10593 if (err < 0) {
10594 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10595 "for consistent allocations\n");
10596 goto err_out_free_res;
10597 }
10598 } else {
f9a5f7d3 10599 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 10600 if (err) {
10601 printk(KERN_ERR PFX "No usable DMA configuration, "
10602 "aborting.\n");
10603 goto err_out_free_res;
10604 }
10605 pci_using_dac = 0;
10606 }
10607
10608 tg3reg_base = pci_resource_start(pdev, 0);
10609 tg3reg_len = pci_resource_len(pdev, 0);
10610
10611 dev = alloc_etherdev(sizeof(*tp));
10612 if (!dev) {
10613 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10614 err = -ENOMEM;
10615 goto err_out_free_res;
10616 }
10617
10618 SET_MODULE_OWNER(dev);
10619 SET_NETDEV_DEV(dev, &pdev->dev);
10620
10621 if (pci_using_dac)
10622 dev->features |= NETIF_F_HIGHDMA;
10623 dev->features |= NETIF_F_LLTX;
10624#if TG3_VLAN_TAG_USED
10625 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10626 dev->vlan_rx_register = tg3_vlan_rx_register;
10627 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10628#endif
10629
10630 tp = netdev_priv(dev);
10631 tp->pdev = pdev;
10632 tp->dev = dev;
10633 tp->pm_cap = pm_cap;
10634 tp->mac_mode = TG3_DEF_MAC_MODE;
10635 tp->rx_mode = TG3_DEF_RX_MODE;
10636 tp->tx_mode = TG3_DEF_TX_MODE;
10637 tp->mi_mode = MAC_MI_MODE_BASE;
10638 if (tg3_debug > 0)
10639 tp->msg_enable = tg3_debug;
10640 else
10641 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10642
10643 /* The word/byte swap controls here control register access byte
10644 * swapping. DMA data byte swapping is controlled in the GRC_MODE
10645 * setting below.
10646 */
10647 tp->misc_host_ctrl =
10648 MISC_HOST_CTRL_MASK_PCI_INT |
10649 MISC_HOST_CTRL_WORD_SWAP |
10650 MISC_HOST_CTRL_INDIR_ACCESS |
10651 MISC_HOST_CTRL_PCISTATE_RW;
10652
10653 /* The NONFRM (non-frame) byte/word swap controls take effect
10654 * on descriptor entries, anything which isn't packet data.
10655 *
10656 * The StrongARM chips on the board (one for tx, one for rx)
10657 * are running in big-endian mode.
10658 */
10659 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10660 GRC_MODE_WSWAP_NONFRM_DATA);
10661#ifdef __BIG_ENDIAN
10662 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10663#endif
10664 spin_lock_init(&tp->lock);
10665 spin_lock_init(&tp->tx_lock);
10666 spin_lock_init(&tp->indirect_lock);
10667 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10668
10669 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10670 if (tp->regs == 0UL) {
10671 printk(KERN_ERR PFX "Cannot map device registers, "
10672 "aborting.\n");
10673 err = -ENOMEM;
10674 goto err_out_free_dev;
10675 }
10676
10677 tg3_init_link_config(tp);
10678
1da177e4
LT		 10679 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10680 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10681 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10682
10683 dev->open = tg3_open;
10684 dev->stop = tg3_close;
10685 dev->get_stats = tg3_get_stats;
10686 dev->set_multicast_list = tg3_set_rx_mode;
10687 dev->set_mac_address = tg3_set_mac_addr;
10688 dev->do_ioctl = tg3_ioctl;
10689 dev->tx_timeout = tg3_tx_timeout;
10690 dev->poll = tg3_poll;
10691 dev->ethtool_ops = &tg3_ethtool_ops;
10692 dev->weight = 64;
10693 dev->watchdog_timeo = TG3_TX_TIMEOUT;
10694 dev->change_mtu = tg3_change_mtu;
10695 dev->irq = pdev->irq;
10696#ifdef CONFIG_NET_POLL_CONTROLLER
10697 dev->poll_controller = tg3_poll_controller;
10698#endif
10699
10700 err = tg3_get_invariants(tp);
10701 if (err) {
10702 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10703 "aborting.\n");
10704 goto err_out_iounmap;
10705 }
10706
fdfec172 10707 tg3_init_bufmgr_config(tp);
1da177e4
LT		 10708
10709#if TG3_TSO_SUPPORT != 0
10710 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10711 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10712 }
10713 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10714 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10715 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10716 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10717 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10718 } else {
10719 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10720 }
10721
10722 /* TSO is off by default, user can enable using ethtool. */
10723#if 0
10724 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10725 dev->features |= NETIF_F_TSO;
10726#endif
10727
10728#endif
10729
10730 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10731 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10732 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10733 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10734 tp->rx_pending = 63;
10735 }
10736
8c2dc7e1
MC		 10737 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10738 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10739 tp->pdev_peer = tg3_find_peer(tp);
1da177e4
LT		 10740
10741 err = tg3_get_device_address(tp);
10742 if (err) {
10743 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10744 "aborting.\n");
10745 goto err_out_iounmap;
10746 }
10747
10748 /*
10749 * Reset chip in case UNDI or EFI driver did not shutdown
10750 * DMA self test will enable WDMAC and we'll see (spurious)
10751 * pending DMA on the PCI bus at that point.
10752 */
10753 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10754 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10755 pci_save_state(tp->pdev);
10756 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 10757 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 10758 }
10759
10760 err = tg3_test_dma(tp);
10761 if (err) {
10762 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10763 goto err_out_iounmap;
10764 }
10765
10766 /* Tigon3 can do ipv4 only... and some chips have buggy
10767 * checksumming.
10768 */
10769 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10770 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10771 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10772 } else
10773 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10774
10775 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10776 dev->features &= ~NETIF_F_HIGHDMA;
10777
10778 /* flow control autonegotiation is default behavior */
10779 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10780
15f9850d
DM		 10781 tg3_init_coal(tp);
10782
7d3f4c97
DM		 10783 /* Now that we have fully setup the chip, save away a snapshot
10784 * of the PCI config space. We need to restore this after
10785 * GRC_MISC_CFG core clock resets and some resume events.
10786 */
10787 pci_save_state(tp->pdev);
10788
1da177e4
LT		 10789 err = register_netdev(dev);
10790 if (err) {
10791 printk(KERN_ERR PFX "Cannot register net device, "
10792 "aborting.\n");
10793 goto err_out_iounmap;
10794 }
10795
10796 pci_set_drvdata(pdev, dev);
10797
f9804ddb 10798 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
1da177e4
LT		 10799 dev->name,
10800 tp->board_part_number,
10801 tp->pci_chip_rev_id,
10802 tg3_phy_string(tp),
f9804ddb 10803 tg3_bus_string(tp, str),
1da177e4
LT		 10804 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10805
10806 for (i = 0; i < 6; i++)
10807 printk("%2.2x%c", dev->dev_addr[i],
10808 i == 5 ? '\n' : ':');
10809
10810 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10811 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10812 "TSOcap[%d] \n",
10813 dev->name,
10814 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10815 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10816 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10817 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10818 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10819 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10820 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
59e6b434
DM		 10821 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10822 dev->name, tp->dma_rwctrl);
1da177e4
LT		 10823
10824 return 0;
10825
10826err_out_iounmap:
6892914f
MC		 10827 if (tp->regs) {
10828 iounmap(tp->regs);
22abe310 10829 tp->regs = NULL;
6892914f 10830 }
1da177e4
LT		 10831
10832err_out_free_dev:
10833 free_netdev(dev);
10834
10835err_out_free_res:
10836 pci_release_regions(pdev);
10837
10838err_out_disable_pdev:
10839 pci_disable_device(pdev);
10840 pci_set_drvdata(pdev, NULL);
10841 return err;
10842}
10843
10844static void __devexit tg3_remove_one(struct pci_dev *pdev)
10845{
10846 struct net_device *dev = pci_get_drvdata(pdev);
10847
10848 if (dev) {
10849 struct tg3 *tp = netdev_priv(dev);
10850
10851 unregister_netdev(dev);
6892914f
MC		 10852 if (tp->regs) {
10853 iounmap(tp->regs);
22abe310 10854 tp->regs = NULL;
6892914f 10855 }
1da177e4
LT		 10856 free_netdev(dev);
10857 pci_release_regions(pdev);
10858 pci_disable_device(pdev);
10859 pci_set_drvdata(pdev, NULL);
10860 }
10861}
10862
10863static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10864{
10865 struct net_device *dev = pci_get_drvdata(pdev);
10866 struct tg3 *tp = netdev_priv(dev);
10867 int err;
10868
10869 if (!netif_running(dev))
10870 return 0;
10871
10872 tg3_netif_stop(tp);
10873
10874 del_timer_sync(&tp->timer);
10875
f47c11ee 10876 tg3_full_lock(tp, 1);
1da177e4 10877 tg3_disable_ints(tp);
f47c11ee 10878 tg3_full_unlock(tp);
1da177e4
LT		 10879
10880 netif_device_detach(dev);
10881
f47c11ee 10882 tg3_full_lock(tp, 0);
944d980e 10883 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 10884 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 10885 tg3_full_unlock(tp);
1da177e4
LT		 10886
10887 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10888 if (err) {
f47c11ee 10889 tg3_full_lock(tp, 0);
1da177e4 10890
6a9eba15 10891 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 10892 tg3_init_hw(tp);
10893
10894 tp->timer.expires = jiffies + tp->timer_offset;
10895 add_timer(&tp->timer);
10896
10897 netif_device_attach(dev);
10898 tg3_netif_start(tp);
10899
f47c11ee 10900 tg3_full_unlock(tp);
1da177e4
LT		 10901 }
10902
10903 return err;
10904}
10905
10906static int tg3_resume(struct pci_dev *pdev)
10907{
10908 struct net_device *dev = pci_get_drvdata(pdev);
10909 struct tg3 *tp = netdev_priv(dev);
10910 int err;
10911
10912 if (!netif_running(dev))
10913 return 0;
10914
10915 pci_restore_state(tp->pdev);
10916
10917 err = tg3_set_power_state(tp, 0);
10918 if (err)
10919 return err;
10920
10921 netif_device_attach(dev);
10922
f47c11ee 10923 tg3_full_lock(tp, 0);
1da177e4 10924
6a9eba15 10925 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 10926 tg3_init_hw(tp);
10927
10928 tp->timer.expires = jiffies + tp->timer_offset;
10929 add_timer(&tp->timer);
10930
1da177e4
LT		 10931 tg3_netif_start(tp);
10932
f47c11ee 10933 tg3_full_unlock(tp);
1da177e4
LT		 10934
10935 return 0;
10936}
10937
10938static struct pci_driver tg3_driver = {
10939 .name = DRV_MODULE_NAME,
10940 .id_table = tg3_pci_tbl,
10941 .probe = tg3_init_one,
10942 .remove = __devexit_p(tg3_remove_one),
10943 .suspend = tg3_suspend,
10944 .resume = tg3_resume
10945};
10946
10947static int __init tg3_init(void)
10948{
10949 return pci_module_init(&tg3_driver);
10950}
10951
10952static void __exit tg3_cleanup(void)
10953{
10954 pci_unregister_driver(&tg3_driver);
10955}
10956
10957module_init(tg3_init);
10958module_exit(tg3_cleanup);
Clone of davem's net-next-2.6 tree