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[TG3]: Add register test
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Copyright (C) 2000-2003 Broadcom Corporation.
11 */
12
13#include <linux/config.h>
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/compiler.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/pci.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/ethtool.h>
29#include <linux/mii.h>
30#include <linux/if_vlan.h>
31#include <linux/ip.h>
32#include <linux/tcp.h>
33#include <linux/workqueue.h>
34
35#include <net/checksum.h>
36
37#include <asm/system.h>
38#include <asm/io.h>
39#include <asm/byteorder.h>
40#include <asm/uaccess.h>
41
42#ifdef CONFIG_SPARC64
43#include <asm/idprom.h>
44#include <asm/oplib.h>
45#include <asm/pbm.h>
46#endif
47
48#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49#define TG3_VLAN_TAG_USED 1
50#else
51#define TG3_VLAN_TAG_USED 0
52#endif
53
54#ifdef NETIF_F_TSO
55#define TG3_TSO_SUPPORT 1
56#else
57#define TG3_TSO_SUPPORT 0
58#endif
59
60#include "tg3.h"
61
62#define DRV_MODULE_NAME "tg3"
63#define PFX DRV_MODULE_NAME ": "
d1faeaeb 64#define DRV_MODULE_VERSION "3.29"
413f5431 65#define DRV_MODULE_RELDATE "May 23, 2005"
1da177e4
LT		 66
67#define TG3_DEF_MAC_MODE 0
68#define TG3_DEF_RX_MODE 0
69#define TG3_DEF_TX_MODE 0
70#define TG3_DEF_MSG_ENABLE \
71 (NETIF_MSG_DRV | \
72 NETIF_MSG_PROBE | \
73 NETIF_MSG_LINK | \
74 NETIF_MSG_TIMER | \
75 NETIF_MSG_IFDOWN | \
76 NETIF_MSG_IFUP | \
77 NETIF_MSG_RX_ERR | \
78 NETIF_MSG_TX_ERR)
79
80/* length of time before we decide the hardware is borked,
81 * and dev->tx_timeout() should be called to fix the problem
82 */
83#define TG3_TX_TIMEOUT (5 * HZ)
84
85/* hardware minimum and maximum for a single frame's data payload */
86#define TG3_MIN_MTU 60
87#define TG3_MAX_MTU(tp) \
fcf02693 88 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
1da177e4
LT		 89
90/* These numbers seem to be hard coded in the NIC firmware somehow.
91 * You can't change the ring sizes, but you can change where you place
92 * them in the NIC onboard memory.
93 */
94#define TG3_RX_RING_SIZE 512
95#define TG3_DEF_RX_RING_PENDING 200
96#define TG3_RX_JUMBO_RING_SIZE 256
97#define TG3_DEF_RX_JUMBO_RING_PENDING 100
98
99/* Do not place this n-ring entries value into the tp struct itself,
100 * we really want to expose these constants to GCC so that modulo et
101 * al. operations are done with shifts and masks instead of with
102 * hw multiply/modulo instructions. Another solution would be to
103 * replace things like '% foo' with '& (foo - 1)'.
104 */
105#define TG3_RX_RCB_RING_SIZE(tp) \
106 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
107
108#define TG3_TX_RING_SIZE 512
109#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
110
111#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
112 TG3_RX_RING_SIZE)
113#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
114 TG3_RX_JUMBO_RING_SIZE)
115#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
116 TG3_RX_RCB_RING_SIZE(tp))
117#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
118 TG3_TX_RING_SIZE)
119#define TX_RING_GAP(TP) \
120 (TG3_TX_RING_SIZE - (TP)->tx_pending)
121#define TX_BUFFS_AVAIL(TP) \
122 (((TP)->tx_cons <= (TP)->tx_prod) ? \
123 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
124 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
125#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
126
127#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
128#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
129
130/* minimum number of free TX descriptors required to wake up TX process */
131#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
132
133/* number of ETHTOOL_GSTATS u64's */
134#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
135
4cafd3f5
MC		 136#define TG3_NUM_TEST 6
137
1da177e4
LT		 138static char version[] __devinitdata =
139 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
140
141MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
142MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
143MODULE_LICENSE("GPL");
144MODULE_VERSION(DRV_MODULE_VERSION);
145
146static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
147module_param(tg3_debug, int, 0);
148MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
149
150static struct pci_device_id tg3_pci_tbl[] = {
151 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
153 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
155 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
207 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
6e9017a7 209 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
af2bcd97 210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
d8659255
XVP		 211 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 213 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
215 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
217 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
219 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
221 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
227 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
229 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
231 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
233 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
235 { 0, }
236};
237
238MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
239
240static struct {
241 const char string[ETH_GSTRING_LEN];
242} ethtool_stats_keys[TG3_NUM_STATS] = {
243 { "rx_octets" },
244 { "rx_fragments" },
245 { "rx_ucast_packets" },
246 { "rx_mcast_packets" },
247 { "rx_bcast_packets" },
248 { "rx_fcs_errors" },
249 { "rx_align_errors" },
250 { "rx_xon_pause_rcvd" },
251 { "rx_xoff_pause_rcvd" },
252 { "rx_mac_ctrl_rcvd" },
253 { "rx_xoff_entered" },
254 { "rx_frame_too_long_errors" },
255 { "rx_jabbers" },
256 { "rx_undersize_packets" },
257 { "rx_in_length_errors" },
258 { "rx_out_length_errors" },
259 { "rx_64_or_less_octet_packets" },
260 { "rx_65_to_127_octet_packets" },
261 { "rx_128_to_255_octet_packets" },
262 { "rx_256_to_511_octet_packets" },
263 { "rx_512_to_1023_octet_packets" },
264 { "rx_1024_to_1522_octet_packets" },
265 { "rx_1523_to_2047_octet_packets" },
266 { "rx_2048_to_4095_octet_packets" },
267 { "rx_4096_to_8191_octet_packets" },
268 { "rx_8192_to_9022_octet_packets" },
269
270 { "tx_octets" },
271 { "tx_collisions" },
272
273 { "tx_xon_sent" },
274 { "tx_xoff_sent" },
275 { "tx_flow_control" },
276 { "tx_mac_errors" },
277 { "tx_single_collisions" },
278 { "tx_mult_collisions" },
279 { "tx_deferred" },
280 { "tx_excessive_collisions" },
281 { "tx_late_collisions" },
282 { "tx_collide_2times" },
283 { "tx_collide_3times" },
284 { "tx_collide_4times" },
285 { "tx_collide_5times" },
286 { "tx_collide_6times" },
287 { "tx_collide_7times" },
288 { "tx_collide_8times" },
289 { "tx_collide_9times" },
290 { "tx_collide_10times" },
291 { "tx_collide_11times" },
292 { "tx_collide_12times" },
293 { "tx_collide_13times" },
294 { "tx_collide_14times" },
295 { "tx_collide_15times" },
296 { "tx_ucast_packets" },
297 { "tx_mcast_packets" },
298 { "tx_bcast_packets" },
299 { "tx_carrier_sense_errors" },
300 { "tx_discards" },
301 { "tx_errors" },
302
303 { "dma_writeq_full" },
304 { "dma_write_prioq_full" },
305 { "rxbds_empty" },
306 { "rx_discards" },
307 { "rx_errors" },
308 { "rx_threshold_hit" },
309
310 { "dma_readq_full" },
311 { "dma_read_prioq_full" },
312 { "tx_comp_queue_full" },
313
314 { "ring_set_send_prod_index" },
315 { "ring_status_update" },
316 { "nic_irqs" },
317 { "nic_avoided_irqs" },
318 { "nic_tx_threshold_hit" }
319};
320
4cafd3f5
MC		 321static struct {
322 const char string[ETH_GSTRING_LEN];
323} ethtool_test_keys[TG3_NUM_TEST] = {
324 { "nvram test (online) " },
325 { "link test (online) " },
326 { "register test (offline)" },
327 { "memory test (offline)" },
328 { "loopback test (offline)" },
329 { "interrupt test (offline)" },
330};
331
1da177e4
LT		 332static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
333{
334 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
335 unsigned long flags;
336
337 spin_lock_irqsave(&tp->indirect_lock, flags);
338 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
339 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
340 spin_unlock_irqrestore(&tp->indirect_lock, flags);
341 } else {
342 writel(val, tp->regs + off);
343 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
344 readl(tp->regs + off);
345 }
346}
347
348static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
349{
350 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
351 unsigned long flags;
352
353 spin_lock_irqsave(&tp->indirect_lock, flags);
354 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
355 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
356 spin_unlock_irqrestore(&tp->indirect_lock, flags);
357 } else {
358 void __iomem *dest = tp->regs + off;
359 writel(val, dest);
360 readl(dest); /* always flush PCI write */
361 }
362}
363
364static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
365{
366 void __iomem *mbox = tp->regs + off;
367 writel(val, mbox);
368 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
369 readl(mbox);
370}
371
372static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
373{
374 void __iomem *mbox = tp->regs + off;
375 writel(val, mbox);
376 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
377 writel(val, mbox);
378 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
379 readl(mbox);
380}
381
382#define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tp->regs + (reg))
383#define tw32_rx_mbox(reg, val) _tw32_rx_mbox(tp, reg, val)
384#define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
385
386#define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
387#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
388#define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
389#define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
390#define tr32(reg) readl(tp->regs + (reg))
391#define tr16(reg) readw(tp->regs + (reg))
392#define tr8(reg) readb(tp->regs + (reg))
393
394static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
395{
396 unsigned long flags;
397
398 spin_lock_irqsave(&tp->indirect_lock, flags);
399 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
400 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
401
402 /* Always leave this as zero. */
403 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
404 spin_unlock_irqrestore(&tp->indirect_lock, flags);
405}
406
407static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
408{
409 unsigned long flags;
410
411 spin_lock_irqsave(&tp->indirect_lock, flags);
412 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
413 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
414
415 /* Always leave this as zero. */
416 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418}
419
420static void tg3_disable_ints(struct tg3 *tp)
421{
422 tw32(TG3PCI_MISC_HOST_CTRL,
423 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
424 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
425 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
426}
427
428static inline void tg3_cond_int(struct tg3 *tp)
429{
430 if (tp->hw_status->status & SD_STATUS_UPDATED)
431 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
432}
433
434static void tg3_enable_ints(struct tg3 *tp)
435{
436 tw32(TG3PCI_MISC_HOST_CTRL,
437 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
fac9b83e
DM		 438 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
439 (tp->last_tag << 24));
1da177e4
LT		 440 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
441
442 tg3_cond_int(tp);
443}
444
04237ddd
MC		 445static inline unsigned int tg3_has_work(struct tg3 *tp)
446{
447 struct tg3_hw_status *sblk = tp->hw_status;
448 unsigned int work_exists = 0;
449
450 /* check for phy events */
451 if (!(tp->tg3_flags &
452 (TG3_FLAG_USE_LINKCHG_REG |
453 TG3_FLAG_POLL_SERDES))) {
454 if (sblk->status & SD_STATUS_LINK_CHG)
455 work_exists = 1;
456 }
457 /* check for RX/TX work to do */
458 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
459 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
460 work_exists = 1;
461
462 return work_exists;
463}
464
1da177e4 465/* tg3_restart_ints
04237ddd
MC		 466 * similar to tg3_enable_ints, but it accurately determines whether there
467 * is new work pending and can return without flushing the PIO write
468 * which reenables interrupts
1da177e4
LT		 469 */
470static void tg3_restart_ints(struct tg3 *tp)
471{
472 tw32(TG3PCI_MISC_HOST_CTRL,
473 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
fac9b83e
DM		 474 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
475 tp->last_tag << 24);
1da177e4
LT		 476 mmiowb();
477
fac9b83e
DM		 478 /* When doing tagged status, this work check is unnecessary.
479 * The last_tag we write above tells the chip which piece of
480 * work we've completed.
481 */
482 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
483 tg3_has_work(tp))
04237ddd
MC		 484 tw32(HOSTCC_MODE, tp->coalesce_mode |
485 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 486}
487
488static inline void tg3_netif_stop(struct tg3 *tp)
489{
490 netif_poll_disable(tp->dev);
491 netif_tx_disable(tp->dev);
492}
493
494static inline void tg3_netif_start(struct tg3 *tp)
495{
496 netif_wake_queue(tp->dev);
497 /* NOTE: unconditional netif_wake_queue is only appropriate
498 * so long as all callers are assured to have free tx slots
499 * (such as after tg3_init_hw)
500 */
501 netif_poll_enable(tp->dev);
502 tg3_cond_int(tp);
503}
504
505static void tg3_switch_clocks(struct tg3 *tp)
506{
507 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
508 u32 orig_clock_ctrl;
509
510 orig_clock_ctrl = clock_ctrl;
511 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
512 CLOCK_CTRL_CLKRUN_OENABLE |
513 0x1f);
514 tp->pci_clock_ctrl = clock_ctrl;
515
516 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
517 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
518 tw32_f(TG3PCI_CLOCK_CTRL,
519 clock_ctrl | CLOCK_CTRL_625_CORE);
520 udelay(40);
521 }
522 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
523 tw32_f(TG3PCI_CLOCK_CTRL,
524 clock_ctrl |
525 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
526 udelay(40);
527 tw32_f(TG3PCI_CLOCK_CTRL,
528 clock_ctrl | (CLOCK_CTRL_ALTCLK));
529 udelay(40);
530 }
531 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
532 udelay(40);
533}
534
535#define PHY_BUSY_LOOPS 5000
536
537static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
538{
539 u32 frame_val;
540 unsigned int loops;
541 int ret;
542
543 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
544 tw32_f(MAC_MI_MODE,
545 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
546 udelay(80);
547 }
548
549 *val = 0x0;
550
551 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
552 MI_COM_PHY_ADDR_MASK);
553 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
554 MI_COM_REG_ADDR_MASK);
555 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
556
557 tw32_f(MAC_MI_COM, frame_val);
558
559 loops = PHY_BUSY_LOOPS;
560 while (loops != 0) {
561 udelay(10);
562 frame_val = tr32(MAC_MI_COM);
563
564 if ((frame_val & MI_COM_BUSY) == 0) {
565 udelay(5);
566 frame_val = tr32(MAC_MI_COM);
567 break;
568 }
569 loops -= 1;
570 }
571
572 ret = -EBUSY;
573 if (loops != 0) {
574 *val = frame_val & MI_COM_DATA_MASK;
575 ret = 0;
576 }
577
578 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
579 tw32_f(MAC_MI_MODE, tp->mi_mode);
580 udelay(80);
581 }
582
583 return ret;
584}
585
586static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
587{
588 u32 frame_val;
589 unsigned int loops;
590 int ret;
591
592 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
593 tw32_f(MAC_MI_MODE,
594 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
595 udelay(80);
596 }
597
598 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
599 MI_COM_PHY_ADDR_MASK);
600 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
601 MI_COM_REG_ADDR_MASK);
602 frame_val |= (val & MI_COM_DATA_MASK);
603 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
604
605 tw32_f(MAC_MI_COM, frame_val);
606
607 loops = PHY_BUSY_LOOPS;
608 while (loops != 0) {
609 udelay(10);
610 frame_val = tr32(MAC_MI_COM);
611 if ((frame_val & MI_COM_BUSY) == 0) {
612 udelay(5);
613 frame_val = tr32(MAC_MI_COM);
614 break;
615 }
616 loops -= 1;
617 }
618
619 ret = -EBUSY;
620 if (loops != 0)
621 ret = 0;
622
623 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
624 tw32_f(MAC_MI_MODE, tp->mi_mode);
625 udelay(80);
626 }
627
628 return ret;
629}
630
631static void tg3_phy_set_wirespeed(struct tg3 *tp)
632{
633 u32 val;
634
635 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
636 return;
637
638 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
639 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
640 tg3_writephy(tp, MII_TG3_AUX_CTRL,
641 (val | (1 << 15) | (1 << 4)));
642}
643
644static int tg3_bmcr_reset(struct tg3 *tp)
645{
646 u32 phy_control;
647 int limit, err;
648
649 /* OK, reset it, and poll the BMCR_RESET bit until it
650 * clears or we time out.
651 */
652 phy_control = BMCR_RESET;
653 err = tg3_writephy(tp, MII_BMCR, phy_control);
654 if (err != 0)
655 return -EBUSY;
656
657 limit = 5000;
658 while (limit--) {
659 err = tg3_readphy(tp, MII_BMCR, &phy_control);
660 if (err != 0)
661 return -EBUSY;
662
663 if ((phy_control & BMCR_RESET) == 0) {
664 udelay(40);
665 break;
666 }
667 udelay(10);
668 }
669 if (limit <= 0)
670 return -EBUSY;
671
672 return 0;
673}
674
675static int tg3_wait_macro_done(struct tg3 *tp)
676{
677 int limit = 100;
678
679 while (limit--) {
680 u32 tmp32;
681
682 if (!tg3_readphy(tp, 0x16, &tmp32)) {
683 if ((tmp32 & 0x1000) == 0)
684 break;
685 }
686 }
687 if (limit <= 0)
688 return -EBUSY;
689
690 return 0;
691}
692
693static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
694{
695 static const u32 test_pat[4][6] = {
696 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
697 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
698 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
699 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
700 };
701 int chan;
702
703 for (chan = 0; chan < 4; chan++) {
704 int i;
705
706 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
707 (chan * 0x2000) | 0x0200);
708 tg3_writephy(tp, 0x16, 0x0002);
709
710 for (i = 0; i < 6; i++)
711 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
712 test_pat[chan][i]);
713
714 tg3_writephy(tp, 0x16, 0x0202);
715 if (tg3_wait_macro_done(tp)) {
716 *resetp = 1;
717 return -EBUSY;
718 }
719
720 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
721 (chan * 0x2000) | 0x0200);
722 tg3_writephy(tp, 0x16, 0x0082);
723 if (tg3_wait_macro_done(tp)) {
724 *resetp = 1;
725 return -EBUSY;
726 }
727
728 tg3_writephy(tp, 0x16, 0x0802);
729 if (tg3_wait_macro_done(tp)) {
730 *resetp = 1;
731 return -EBUSY;
732 }
733
734 for (i = 0; i < 6; i += 2) {
735 u32 low, high;
736
737 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
738 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
739 tg3_wait_macro_done(tp)) {
740 *resetp = 1;
741 return -EBUSY;
742 }
743 low &= 0x7fff;
744 high &= 0x000f;
745 if (low != test_pat[chan][i] ||
746 high != test_pat[chan][i+1]) {
747 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
748 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
749 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
750
751 return -EBUSY;
752 }
753 }
754 }
755
756 return 0;
757}
758
759static int tg3_phy_reset_chanpat(struct tg3 *tp)
760{
761 int chan;
762
763 for (chan = 0; chan < 4; chan++) {
764 int i;
765
766 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
767 (chan * 0x2000) | 0x0200);
768 tg3_writephy(tp, 0x16, 0x0002);
769 for (i = 0; i < 6; i++)
770 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
771 tg3_writephy(tp, 0x16, 0x0202);
772 if (tg3_wait_macro_done(tp))
773 return -EBUSY;
774 }
775
776 return 0;
777}
778
779static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
780{
781 u32 reg32, phy9_orig;
782 int retries, do_phy_reset, err;
783
784 retries = 10;
785 do_phy_reset = 1;
786 do {
787 if (do_phy_reset) {
788 err = tg3_bmcr_reset(tp);
789 if (err)
790 return err;
791 do_phy_reset = 0;
792 }
793
794 /* Disable transmitter and interrupt. */
795 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
796 continue;
797
798 reg32 |= 0x3000;
799 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
800
801 /* Set full-duplex, 1000 mbps. */
802 tg3_writephy(tp, MII_BMCR,
803 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
804
805 /* Set to master mode. */
806 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
807 continue;
808
809 tg3_writephy(tp, MII_TG3_CTRL,
810 (MII_TG3_CTRL_AS_MASTER |
811 MII_TG3_CTRL_ENABLE_AS_MASTER));
812
813 /* Enable SM_DSP_CLOCK and 6dB. */
814 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
815
816 /* Block the PHY control access. */
817 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
818 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
819
820 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
821 if (!err)
822 break;
823 } while (--retries);
824
825 err = tg3_phy_reset_chanpat(tp);
826 if (err)
827 return err;
828
829 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
830 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
831
832 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
833 tg3_writephy(tp, 0x16, 0x0000);
834
835 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
837 /* Set Extended packet length bit for jumbo frames */
838 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
839 }
840 else {
841 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
842 }
843
844 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
845
846 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
847 reg32 &= ~0x3000;
848 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
849 } else if (!err)
850 err = -EBUSY;
851
852 return err;
853}
854
855/* This will reset the tigon3 PHY if there is no valid
856 * link unless the FORCE argument is non-zero.
857 */
858static int tg3_phy_reset(struct tg3 *tp)
859{
860 u32 phy_status;
861 int err;
862
863 err = tg3_readphy(tp, MII_BMSR, &phy_status);
864 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
865 if (err != 0)
866 return -EBUSY;
867
868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
869 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
870 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
871 err = tg3_phy_reset_5703_4_5(tp);
872 if (err)
873 return err;
874 goto out;
875 }
876
877 err = tg3_bmcr_reset(tp);
878 if (err)
879 return err;
880
881out:
882 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
883 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
884 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
885 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
886 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
887 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
888 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
889 }
890 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
891 tg3_writephy(tp, 0x1c, 0x8d68);
892 tg3_writephy(tp, 0x1c, 0x8d68);
893 }
894 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
895 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
896 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
897 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
898 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
899 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
900 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
901 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
902 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
903 }
904 /* Set Extended packet length bit (bit 14) on all chips that */
905 /* support jumbo frames */
906 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
907 /* Cannot do read-modify-write on 5401 */
908 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
fcf02693 909 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1da177e4
LT		 910 u32 phy_reg;
911
912 /* Set bit 14 with read-modify-write to preserve other bits */
913 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
914 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
915 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
916 }
917
918 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
919 * jumbo frames transmission.
920 */
fcf02693 921 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1da177e4
LT		 922 u32 phy_reg;
923
924 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
925 tg3_writephy(tp, MII_TG3_EXT_CTRL,
926 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
927 }
928
929 tg3_phy_set_wirespeed(tp);
930 return 0;
931}
932
933static void tg3_frob_aux_power(struct tg3 *tp)
934{
935 struct tg3 *tp_peer = tp;
936
937 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
938 return;
939
940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
941 tp_peer = pci_get_drvdata(tp->pdev_peer);
942 if (!tp_peer)
943 BUG();
944 }
945
946
947 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
948 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
951 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
952 (GRC_LCLCTRL_GPIO_OE0 |
953 GRC_LCLCTRL_GPIO_OE1 |
954 GRC_LCLCTRL_GPIO_OE2 |
955 GRC_LCLCTRL_GPIO_OUTPUT0 |
956 GRC_LCLCTRL_GPIO_OUTPUT1));
957 udelay(100);
958 } else {
959 u32 no_gpio2;
960 u32 grc_local_ctrl;
961
962 if (tp_peer != tp &&
963 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
964 return;
965
966 /* On 5753 and variants, GPIO2 cannot be used. */
967 no_gpio2 = tp->nic_sram_data_cfg &
968 NIC_SRAM_DATA_CFG_NO_GPIO2;
969
970 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
971 GRC_LCLCTRL_GPIO_OE1 |
972 GRC_LCLCTRL_GPIO_OE2 |
973 GRC_LCLCTRL_GPIO_OUTPUT1 |
974 GRC_LCLCTRL_GPIO_OUTPUT2;
975 if (no_gpio2) {
976 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
977 GRC_LCLCTRL_GPIO_OUTPUT2);
978 }
979 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
980 grc_local_ctrl);
981 udelay(100);
982
983 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
984
985 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
986 grc_local_ctrl);
987 udelay(100);
988
989 if (!no_gpio2) {
990 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
991 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
992 grc_local_ctrl);
993 udelay(100);
994 }
995 }
996 } else {
997 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
998 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
999 if (tp_peer != tp &&
1000 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1001 return;
1002
1003 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1004 (GRC_LCLCTRL_GPIO_OE1 |
1005 GRC_LCLCTRL_GPIO_OUTPUT1));
1006 udelay(100);
1007
1008 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1009 (GRC_LCLCTRL_GPIO_OE1));
1010 udelay(100);
1011
1012 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1013 (GRC_LCLCTRL_GPIO_OE1 |
1014 GRC_LCLCTRL_GPIO_OUTPUT1));
1015 udelay(100);
1016 }
1017 }
1018}
1019
1020static int tg3_setup_phy(struct tg3 *, int);
1021
1022#define RESET_KIND_SHUTDOWN 0
1023#define RESET_KIND_INIT 1
1024#define RESET_KIND_SUSPEND 2
1025
1026static void tg3_write_sig_post_reset(struct tg3 *, int);
1027static int tg3_halt_cpu(struct tg3 *, u32);
1028
1029static int tg3_set_power_state(struct tg3 *tp, int state)
1030{
1031 u32 misc_host_ctrl;
1032 u16 power_control, power_caps;
1033 int pm = tp->pm_cap;
1034
1035 /* Make sure register accesses (indirect or otherwise)
1036 * will function correctly.
1037 */
1038 pci_write_config_dword(tp->pdev,
1039 TG3PCI_MISC_HOST_CTRL,
1040 tp->misc_host_ctrl);
1041
1042 pci_read_config_word(tp->pdev,
1043 pm + PCI_PM_CTRL,
1044 &power_control);
1045 power_control |= PCI_PM_CTRL_PME_STATUS;
1046 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1047 switch (state) {
1048 case 0:
1049 power_control |= 0;
1050 pci_write_config_word(tp->pdev,
1051 pm + PCI_PM_CTRL,
1052 power_control);
8c6bda1a
MC		 1053 udelay(100); /* Delay after power state change */
1054
1055 /* Switch out of Vaux if it is not a LOM */
1056 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1057 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1058 udelay(100);
1059 }
1da177e4
LT		 1060
1061 return 0;
1062
1063 case 1:
1064 power_control |= 1;
1065 break;
1066
1067 case 2:
1068 power_control |= 2;
1069 break;
1070
1071 case 3:
1072 power_control |= 3;
1073 break;
1074
1075 default:
1076 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1077 "requested.\n",
1078 tp->dev->name, state);
1079 return -EINVAL;
1080 };
1081
1082 power_control |= PCI_PM_CTRL_PME_ENABLE;
1083
1084 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1085 tw32(TG3PCI_MISC_HOST_CTRL,
1086 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1087
1088 if (tp->link_config.phy_is_low_power == 0) {
1089 tp->link_config.phy_is_low_power = 1;
1090 tp->link_config.orig_speed = tp->link_config.speed;
1091 tp->link_config.orig_duplex = tp->link_config.duplex;
1092 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1093 }
1094
1095 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1096 tp->link_config.speed = SPEED_10;
1097 tp->link_config.duplex = DUPLEX_HALF;
1098 tp->link_config.autoneg = AUTONEG_ENABLE;
1099 tg3_setup_phy(tp, 0);
1100 }
1101
1102 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1103
1104 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1105 u32 mac_mode;
1106
1107 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1108 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1109 udelay(40);
1110
1111 mac_mode = MAC_MODE_PORT_MODE_MII;
1112
1113 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1114 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1115 mac_mode |= MAC_MODE_LINK_POLARITY;
1116 } else {
1117 mac_mode = MAC_MODE_PORT_MODE_TBI;
1118 }
1119
cbf46853 1120 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1121 tw32(MAC_LED_CTRL, tp->led_ctrl);
1122
1123 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1124 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1125 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1126
1127 tw32_f(MAC_MODE, mac_mode);
1128 udelay(100);
1129
1130 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1131 udelay(10);
1132 }
1133
1134 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1135 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1137 u32 base_val;
1138
1139 base_val = tp->pci_clock_ctrl;
1140 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1141 CLOCK_CTRL_TXCLK_DISABLE);
1142
1143 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1144 CLOCK_CTRL_ALTCLK |
1145 CLOCK_CTRL_PWRDOWN_PLL133);
1146 udelay(40);
85e94ced 1147 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1148 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1149 u32 newbits1, newbits2;
1150
1151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1153 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1154 CLOCK_CTRL_TXCLK_DISABLE |
1155 CLOCK_CTRL_ALTCLK);
1156 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1157 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1158 newbits1 = CLOCK_CTRL_625_CORE;
1159 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1160 } else {
1161 newbits1 = CLOCK_CTRL_ALTCLK;
1162 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1163 }
1164
1165 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1166 udelay(40);
1167
1168 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1169 udelay(40);
1170
1171 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1172 u32 newbits3;
1173
1174 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1175 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1176 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1177 CLOCK_CTRL_TXCLK_DISABLE |
1178 CLOCK_CTRL_44MHZ_CORE);
1179 } else {
1180 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1181 }
1182
1183 tw32_f(TG3PCI_CLOCK_CTRL,
1184 tp->pci_clock_ctrl | newbits3);
1185 udelay(40);
1186 }
1187 }
1188
1189 tg3_frob_aux_power(tp);
1190
1191 /* Workaround for unstable PLL clock */
1192 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1193 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1194 u32 val = tr32(0x7d00);
1195
1196 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1197 tw32(0x7d00, val);
1198 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1199 tg3_halt_cpu(tp, RX_CPU_BASE);
1200 }
1201
1202 /* Finally, set the new power state. */
1203 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1204 udelay(100); /* Delay after power state change */
1da177e4
LT		 1205
1206 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1207
1208 return 0;
1209}
1210
1211static void tg3_link_report(struct tg3 *tp)
1212{
1213 if (!netif_carrier_ok(tp->dev)) {
1214 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1215 } else {
1216 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1217 tp->dev->name,
1218 (tp->link_config.active_speed == SPEED_1000 ?
1219 1000 :
1220 (tp->link_config.active_speed == SPEED_100 ?
1221 100 : 10)),
1222 (tp->link_config.active_duplex == DUPLEX_FULL ?
1223 "full" : "half"));
1224
1225 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1226 "%s for RX.\n",
1227 tp->dev->name,
1228 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1229 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1230 }
1231}
1232
1233static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1234{
1235 u32 new_tg3_flags = 0;
1236 u32 old_rx_mode = tp->rx_mode;
1237 u32 old_tx_mode = tp->tx_mode;
1238
1239 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1240 if (local_adv & ADVERTISE_PAUSE_CAP) {
1241 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1242 if (remote_adv & LPA_PAUSE_CAP)
1243 new_tg3_flags |=
1244 (TG3_FLAG_RX_PAUSE |
1245 TG3_FLAG_TX_PAUSE);
1246 else if (remote_adv & LPA_PAUSE_ASYM)
1247 new_tg3_flags |=
1248 (TG3_FLAG_RX_PAUSE);
1249 } else {
1250 if (remote_adv & LPA_PAUSE_CAP)
1251 new_tg3_flags |=
1252 (TG3_FLAG_RX_PAUSE |
1253 TG3_FLAG_TX_PAUSE);
1254 }
1255 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1256 if ((remote_adv & LPA_PAUSE_CAP) &&
1257 (remote_adv & LPA_PAUSE_ASYM))
1258 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1259 }
1260
1261 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1262 tp->tg3_flags |= new_tg3_flags;
1263 } else {
1264 new_tg3_flags = tp->tg3_flags;
1265 }
1266
1267 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1268 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1269 else
1270 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1271
1272 if (old_rx_mode != tp->rx_mode) {
1273 tw32_f(MAC_RX_MODE, tp->rx_mode);
1274 }
1275
1276 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1277 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1278 else
1279 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1280
1281 if (old_tx_mode != tp->tx_mode) {
1282 tw32_f(MAC_TX_MODE, tp->tx_mode);
1283 }
1284}
1285
1286static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1287{
1288 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1289 case MII_TG3_AUX_STAT_10HALF:
1290 *speed = SPEED_10;
1291 *duplex = DUPLEX_HALF;
1292 break;
1293
1294 case MII_TG3_AUX_STAT_10FULL:
1295 *speed = SPEED_10;
1296 *duplex = DUPLEX_FULL;
1297 break;
1298
1299 case MII_TG3_AUX_STAT_100HALF:
1300 *speed = SPEED_100;
1301 *duplex = DUPLEX_HALF;
1302 break;
1303
1304 case MII_TG3_AUX_STAT_100FULL:
1305 *speed = SPEED_100;
1306 *duplex = DUPLEX_FULL;
1307 break;
1308
1309 case MII_TG3_AUX_STAT_1000HALF:
1310 *speed = SPEED_1000;
1311 *duplex = DUPLEX_HALF;
1312 break;
1313
1314 case MII_TG3_AUX_STAT_1000FULL:
1315 *speed = SPEED_1000;
1316 *duplex = DUPLEX_FULL;
1317 break;
1318
1319 default:
1320 *speed = SPEED_INVALID;
1321 *duplex = DUPLEX_INVALID;
1322 break;
1323 };
1324}
1325
1326static void tg3_phy_copper_begin(struct tg3 *tp)
1327{
1328 u32 new_adv;
1329 int i;
1330
1331 if (tp->link_config.phy_is_low_power) {
1332 /* Entering low power mode. Disable gigabit and
1333 * 100baseT advertisements.
1334 */
1335 tg3_writephy(tp, MII_TG3_CTRL, 0);
1336
1337 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1338 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1339 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1340 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1341
1342 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1343 } else if (tp->link_config.speed == SPEED_INVALID) {
1344 tp->link_config.advertising =
1345 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1346 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1347 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1348 ADVERTISED_Autoneg | ADVERTISED_MII);
1349
1350 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1351 tp->link_config.advertising &=
1352 ~(ADVERTISED_1000baseT_Half |
1353 ADVERTISED_1000baseT_Full);
1354
1355 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1356 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1357 new_adv |= ADVERTISE_10HALF;
1358 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1359 new_adv |= ADVERTISE_10FULL;
1360 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1361 new_adv |= ADVERTISE_100HALF;
1362 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1363 new_adv |= ADVERTISE_100FULL;
1364 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1365
1366 if (tp->link_config.advertising &
1367 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1368 new_adv = 0;
1369 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1370 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1371 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1372 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1373 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1374 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1375 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1376 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1377 MII_TG3_CTRL_ENABLE_AS_MASTER);
1378 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1379 } else {
1380 tg3_writephy(tp, MII_TG3_CTRL, 0);
1381 }
1382 } else {
1383 /* Asking for a specific link mode. */
1384 if (tp->link_config.speed == SPEED_1000) {
1385 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1386 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1387
1388 if (tp->link_config.duplex == DUPLEX_FULL)
1389 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1390 else
1391 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1392 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1393 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1394 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1395 MII_TG3_CTRL_ENABLE_AS_MASTER);
1396 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1397 } else {
1398 tg3_writephy(tp, MII_TG3_CTRL, 0);
1399
1400 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1401 if (tp->link_config.speed == SPEED_100) {
1402 if (tp->link_config.duplex == DUPLEX_FULL)
1403 new_adv |= ADVERTISE_100FULL;
1404 else
1405 new_adv |= ADVERTISE_100HALF;
1406 } else {
1407 if (tp->link_config.duplex == DUPLEX_FULL)
1408 new_adv |= ADVERTISE_10FULL;
1409 else
1410 new_adv |= ADVERTISE_10HALF;
1411 }
1412 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1413 }
1414 }
1415
1416 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1417 tp->link_config.speed != SPEED_INVALID) {
1418 u32 bmcr, orig_bmcr;
1419
1420 tp->link_config.active_speed = tp->link_config.speed;
1421 tp->link_config.active_duplex = tp->link_config.duplex;
1422
1423 bmcr = 0;
1424 switch (tp->link_config.speed) {
1425 default:
1426 case SPEED_10:
1427 break;
1428
1429 case SPEED_100:
1430 bmcr |= BMCR_SPEED100;
1431 break;
1432
1433 case SPEED_1000:
1434 bmcr |= TG3_BMCR_SPEED1000;
1435 break;
1436 };
1437
1438 if (tp->link_config.duplex == DUPLEX_FULL)
1439 bmcr |= BMCR_FULLDPLX;
1440
1441 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1442 (bmcr != orig_bmcr)) {
1443 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1444 for (i = 0; i < 1500; i++) {
1445 u32 tmp;
1446
1447 udelay(10);
1448 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1449 tg3_readphy(tp, MII_BMSR, &tmp))
1450 continue;
1451 if (!(tmp & BMSR_LSTATUS)) {
1452 udelay(40);
1453 break;
1454 }
1455 }
1456 tg3_writephy(tp, MII_BMCR, bmcr);
1457 udelay(40);
1458 }
1459 } else {
1460 tg3_writephy(tp, MII_BMCR,
1461 BMCR_ANENABLE | BMCR_ANRESTART);
1462 }
1463}
1464
1465static int tg3_init_5401phy_dsp(struct tg3 *tp)
1466{
1467 int err;
1468
1469 /* Turn off tap power management. */
1470 /* Set Extended packet length bit */
1471 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1472
1473 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1474 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1475
1476 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1477 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1478
1479 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1480 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1481
1482 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1483 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1484
1485 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1486 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1487
1488 udelay(40);
1489
1490 return err;
1491}
1492
1493static int tg3_copper_is_advertising_all(struct tg3 *tp)
1494{
1495 u32 adv_reg, all_mask;
1496
1497 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1498 return 0;
1499
1500 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1501 ADVERTISE_100HALF | ADVERTISE_100FULL);
1502 if ((adv_reg & all_mask) != all_mask)
1503 return 0;
1504 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1505 u32 tg3_ctrl;
1506
1507 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1508 return 0;
1509
1510 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1511 MII_TG3_CTRL_ADV_1000_FULL);
1512 if ((tg3_ctrl & all_mask) != all_mask)
1513 return 0;
1514 }
1515 return 1;
1516}
1517
1518static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1519{
1520 int current_link_up;
1521 u32 bmsr, dummy;
1522 u16 current_speed;
1523 u8 current_duplex;
1524 int i, err;
1525
1526 tw32(MAC_EVENT, 0);
1527
1528 tw32_f(MAC_STATUS,
1529 (MAC_STATUS_SYNC_CHANGED |
1530 MAC_STATUS_CFG_CHANGED |
1531 MAC_STATUS_MI_COMPLETION |
1532 MAC_STATUS_LNKSTATE_CHANGED));
1533 udelay(40);
1534
1535 tp->mi_mode = MAC_MI_MODE_BASE;
1536 tw32_f(MAC_MI_MODE, tp->mi_mode);
1537 udelay(80);
1538
1539 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1540
1541 /* Some third-party PHYs need to be reset on link going
1542 * down.
1543 */
1544 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1547 netif_carrier_ok(tp->dev)) {
1548 tg3_readphy(tp, MII_BMSR, &bmsr);
1549 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1550 !(bmsr & BMSR_LSTATUS))
1551 force_reset = 1;
1552 }
1553 if (force_reset)
1554 tg3_phy_reset(tp);
1555
1556 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1557 tg3_readphy(tp, MII_BMSR, &bmsr);
1558 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1559 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1560 bmsr = 0;
1561
1562 if (!(bmsr & BMSR_LSTATUS)) {
1563 err = tg3_init_5401phy_dsp(tp);
1564 if (err)
1565 return err;
1566
1567 tg3_readphy(tp, MII_BMSR, &bmsr);
1568 for (i = 0; i < 1000; i++) {
1569 udelay(10);
1570 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1571 (bmsr & BMSR_LSTATUS)) {
1572 udelay(40);
1573 break;
1574 }
1575 }
1576
1577 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1578 !(bmsr & BMSR_LSTATUS) &&
1579 tp->link_config.active_speed == SPEED_1000) {
1580 err = tg3_phy_reset(tp);
1581 if (!err)
1582 err = tg3_init_5401phy_dsp(tp);
1583 if (err)
1584 return err;
1585 }
1586 }
1587 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1588 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1589 /* 5701 {A0,B0} CRC bug workaround */
1590 tg3_writephy(tp, 0x15, 0x0a75);
1591 tg3_writephy(tp, 0x1c, 0x8c68);
1592 tg3_writephy(tp, 0x1c, 0x8d68);
1593 tg3_writephy(tp, 0x1c, 0x8c68);
1594 }
1595
1596 /* Clear pending interrupts... */
1597 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1598 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1599
1600 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1601 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1602 else
1603 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1604
1605 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1606 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1607 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1608 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1609 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1610 else
1611 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1612 }
1613
1614 current_link_up = 0;
1615 current_speed = SPEED_INVALID;
1616 current_duplex = DUPLEX_INVALID;
1617
1618 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1619 u32 val;
1620
1621 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1622 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1623 if (!(val & (1 << 10))) {
1624 val |= (1 << 10);
1625 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1626 goto relink;
1627 }
1628 }
1629
1630 bmsr = 0;
1631 for (i = 0; i < 100; i++) {
1632 tg3_readphy(tp, MII_BMSR, &bmsr);
1633 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1634 (bmsr & BMSR_LSTATUS))
1635 break;
1636 udelay(40);
1637 }
1638
1639 if (bmsr & BMSR_LSTATUS) {
1640 u32 aux_stat, bmcr;
1641
1642 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1643 for (i = 0; i < 2000; i++) {
1644 udelay(10);
1645 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1646 aux_stat)
1647 break;
1648 }
1649
1650 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1651 &current_speed,
1652 &current_duplex);
1653
1654 bmcr = 0;
1655 for (i = 0; i < 200; i++) {
1656 tg3_readphy(tp, MII_BMCR, &bmcr);
1657 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1658 continue;
1659 if (bmcr && bmcr != 0x7fff)
1660 break;
1661 udelay(10);
1662 }
1663
1664 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1665 if (bmcr & BMCR_ANENABLE) {
1666 current_link_up = 1;
1667
1668 /* Force autoneg restart if we are exiting
1669 * low power mode.
1670 */
1671 if (!tg3_copper_is_advertising_all(tp))
1672 current_link_up = 0;
1673 } else {
1674 current_link_up = 0;
1675 }
1676 } else {
1677 if (!(bmcr & BMCR_ANENABLE) &&
1678 tp->link_config.speed == current_speed &&
1679 tp->link_config.duplex == current_duplex) {
1680 current_link_up = 1;
1681 } else {
1682 current_link_up = 0;
1683 }
1684 }
1685
1686 tp->link_config.active_speed = current_speed;
1687 tp->link_config.active_duplex = current_duplex;
1688 }
1689
1690 if (current_link_up == 1 &&
1691 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1692 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1693 u32 local_adv, remote_adv;
1694
1695 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1696 local_adv = 0;
1697 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1698
1699 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1700 remote_adv = 0;
1701
1702 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1703
1704 /* If we are not advertising full pause capability,
1705 * something is wrong. Bring the link down and reconfigure.
1706 */
1707 if (local_adv != ADVERTISE_PAUSE_CAP) {
1708 current_link_up = 0;
1709 } else {
1710 tg3_setup_flow_control(tp, local_adv, remote_adv);
1711 }
1712 }
1713relink:
1714 if (current_link_up == 0) {
1715 u32 tmp;
1716
1717 tg3_phy_copper_begin(tp);
1718
1719 tg3_readphy(tp, MII_BMSR, &tmp);
1720 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1721 (tmp & BMSR_LSTATUS))
1722 current_link_up = 1;
1723 }
1724
1725 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1726 if (current_link_up == 1) {
1727 if (tp->link_config.active_speed == SPEED_100 ||
1728 tp->link_config.active_speed == SPEED_10)
1729 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1730 else
1731 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1732 } else
1733 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1734
1735 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1736 if (tp->link_config.active_duplex == DUPLEX_HALF)
1737 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1738
1739 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1741 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1742 (current_link_up == 1 &&
1743 tp->link_config.active_speed == SPEED_10))
1744 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1745 } else {
1746 if (current_link_up == 1)
1747 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1748 }
1749
1750 /* ??? Without this setting Netgear GA302T PHY does not
1751 * ??? send/receive packets...
1752 */
1753 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1754 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1755 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1756 tw32_f(MAC_MI_MODE, tp->mi_mode);
1757 udelay(80);
1758 }
1759
1760 tw32_f(MAC_MODE, tp->mac_mode);
1761 udelay(40);
1762
1763 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1764 /* Polled via timer. */
1765 tw32_f(MAC_EVENT, 0);
1766 } else {
1767 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1768 }
1769 udelay(40);
1770
1771 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1772 current_link_up == 1 &&
1773 tp->link_config.active_speed == SPEED_1000 &&
1774 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1775 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1776 udelay(120);
1777 tw32_f(MAC_STATUS,
1778 (MAC_STATUS_SYNC_CHANGED |
1779 MAC_STATUS_CFG_CHANGED));
1780 udelay(40);
1781 tg3_write_mem(tp,
1782 NIC_SRAM_FIRMWARE_MBOX,
1783 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1784 }
1785
1786 if (current_link_up != netif_carrier_ok(tp->dev)) {
1787 if (current_link_up)
1788 netif_carrier_on(tp->dev);
1789 else
1790 netif_carrier_off(tp->dev);
1791 tg3_link_report(tp);
1792 }
1793
1794 return 0;
1795}
1796
1797struct tg3_fiber_aneginfo {
1798 int state;
1799#define ANEG_STATE_UNKNOWN 0
1800#define ANEG_STATE_AN_ENABLE 1
1801#define ANEG_STATE_RESTART_INIT 2
1802#define ANEG_STATE_RESTART 3
1803#define ANEG_STATE_DISABLE_LINK_OK 4
1804#define ANEG_STATE_ABILITY_DETECT_INIT 5
1805#define ANEG_STATE_ABILITY_DETECT 6
1806#define ANEG_STATE_ACK_DETECT_INIT 7
1807#define ANEG_STATE_ACK_DETECT 8
1808#define ANEG_STATE_COMPLETE_ACK_INIT 9
1809#define ANEG_STATE_COMPLETE_ACK 10
1810#define ANEG_STATE_IDLE_DETECT_INIT 11
1811#define ANEG_STATE_IDLE_DETECT 12
1812#define ANEG_STATE_LINK_OK 13
1813#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1814#define ANEG_STATE_NEXT_PAGE_WAIT 15
1815
1816 u32 flags;
1817#define MR_AN_ENABLE 0x00000001
1818#define MR_RESTART_AN 0x00000002
1819#define MR_AN_COMPLETE 0x00000004
1820#define MR_PAGE_RX 0x00000008
1821#define MR_NP_LOADED 0x00000010
1822#define MR_TOGGLE_TX 0x00000020
1823#define MR_LP_ADV_FULL_DUPLEX 0x00000040
1824#define MR_LP_ADV_HALF_DUPLEX 0x00000080
1825#define MR_LP_ADV_SYM_PAUSE 0x00000100
1826#define MR_LP_ADV_ASYM_PAUSE 0x00000200
1827#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1828#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1829#define MR_LP_ADV_NEXT_PAGE 0x00001000
1830#define MR_TOGGLE_RX 0x00002000
1831#define MR_NP_RX 0x00004000
1832
1833#define MR_LINK_OK 0x80000000
1834
1835 unsigned long link_time, cur_time;
1836
1837 u32 ability_match_cfg;
1838 int ability_match_count;
1839
1840 char ability_match, idle_match, ack_match;
1841
1842 u32 txconfig, rxconfig;
1843#define ANEG_CFG_NP 0x00000080
1844#define ANEG_CFG_ACK 0x00000040
1845#define ANEG_CFG_RF2 0x00000020
1846#define ANEG_CFG_RF1 0x00000010
1847#define ANEG_CFG_PS2 0x00000001
1848#define ANEG_CFG_PS1 0x00008000
1849#define ANEG_CFG_HD 0x00004000
1850#define ANEG_CFG_FD 0x00002000
1851#define ANEG_CFG_INVAL 0x00001f06
1852
1853};
1854#define ANEG_OK 0
1855#define ANEG_DONE 1
1856#define ANEG_TIMER_ENAB 2
1857#define ANEG_FAILED -1
1858
1859#define ANEG_STATE_SETTLE_TIME 10000
1860
1861static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1862 struct tg3_fiber_aneginfo *ap)
1863{
1864 unsigned long delta;
1865 u32 rx_cfg_reg;
1866 int ret;
1867
1868 if (ap->state == ANEG_STATE_UNKNOWN) {
1869 ap->rxconfig = 0;
1870 ap->link_time = 0;
1871 ap->cur_time = 0;
1872 ap->ability_match_cfg = 0;
1873 ap->ability_match_count = 0;
1874 ap->ability_match = 0;
1875 ap->idle_match = 0;
1876 ap->ack_match = 0;
1877 }
1878 ap->cur_time++;
1879
1880 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1881 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1882
1883 if (rx_cfg_reg != ap->ability_match_cfg) {
1884 ap->ability_match_cfg = rx_cfg_reg;
1885 ap->ability_match = 0;
1886 ap->ability_match_count = 0;
1887 } else {
1888 if (++ap->ability_match_count > 1) {
1889 ap->ability_match = 1;
1890 ap->ability_match_cfg = rx_cfg_reg;
1891 }
1892 }
1893 if (rx_cfg_reg & ANEG_CFG_ACK)
1894 ap->ack_match = 1;
1895 else
1896 ap->ack_match = 0;
1897
1898 ap->idle_match = 0;
1899 } else {
1900 ap->idle_match = 1;
1901 ap->ability_match_cfg = 0;
1902 ap->ability_match_count = 0;
1903 ap->ability_match = 0;
1904 ap->ack_match = 0;
1905
1906 rx_cfg_reg = 0;
1907 }
1908
1909 ap->rxconfig = rx_cfg_reg;
1910 ret = ANEG_OK;
1911
1912 switch(ap->state) {
1913 case ANEG_STATE_UNKNOWN:
1914 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1915 ap->state = ANEG_STATE_AN_ENABLE;
1916
1917 /* fallthru */
1918 case ANEG_STATE_AN_ENABLE:
1919 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1920 if (ap->flags & MR_AN_ENABLE) {
1921 ap->link_time = 0;
1922 ap->cur_time = 0;
1923 ap->ability_match_cfg = 0;
1924 ap->ability_match_count = 0;
1925 ap->ability_match = 0;
1926 ap->idle_match = 0;
1927 ap->ack_match = 0;
1928
1929 ap->state = ANEG_STATE_RESTART_INIT;
1930 } else {
1931 ap->state = ANEG_STATE_DISABLE_LINK_OK;
1932 }
1933 break;
1934
1935 case ANEG_STATE_RESTART_INIT:
1936 ap->link_time = ap->cur_time;
1937 ap->flags &= ~(MR_NP_LOADED);
1938 ap->txconfig = 0;
1939 tw32(MAC_TX_AUTO_NEG, 0);
1940 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1941 tw32_f(MAC_MODE, tp->mac_mode);
1942 udelay(40);
1943
1944 ret = ANEG_TIMER_ENAB;
1945 ap->state = ANEG_STATE_RESTART;
1946
1947 /* fallthru */
1948 case ANEG_STATE_RESTART:
1949 delta = ap->cur_time - ap->link_time;
1950 if (delta > ANEG_STATE_SETTLE_TIME) {
1951 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1952 } else {
1953 ret = ANEG_TIMER_ENAB;
1954 }
1955 break;
1956
1957 case ANEG_STATE_DISABLE_LINK_OK:
1958 ret = ANEG_DONE;
1959 break;
1960
1961 case ANEG_STATE_ABILITY_DETECT_INIT:
1962 ap->flags &= ~(MR_TOGGLE_TX);
1963 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1964 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1965 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1966 tw32_f(MAC_MODE, tp->mac_mode);
1967 udelay(40);
1968
1969 ap->state = ANEG_STATE_ABILITY_DETECT;
1970 break;
1971
1972 case ANEG_STATE_ABILITY_DETECT:
1973 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1974 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1975 }
1976 break;
1977
1978 case ANEG_STATE_ACK_DETECT_INIT:
1979 ap->txconfig |= ANEG_CFG_ACK;
1980 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1981 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1982 tw32_f(MAC_MODE, tp->mac_mode);
1983 udelay(40);
1984
1985 ap->state = ANEG_STATE_ACK_DETECT;
1986
1987 /* fallthru */
1988 case ANEG_STATE_ACK_DETECT:
1989 if (ap->ack_match != 0) {
1990 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1991 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1992 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1993 } else {
1994 ap->state = ANEG_STATE_AN_ENABLE;
1995 }
1996 } else if (ap->ability_match != 0 &&
1997 ap->rxconfig == 0) {
1998 ap->state = ANEG_STATE_AN_ENABLE;
1999 }
2000 break;
2001
2002 case ANEG_STATE_COMPLETE_ACK_INIT:
2003 if (ap->rxconfig & ANEG_CFG_INVAL) {
2004 ret = ANEG_FAILED;
2005 break;
2006 }
2007 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2008 MR_LP_ADV_HALF_DUPLEX |
2009 MR_LP_ADV_SYM_PAUSE |
2010 MR_LP_ADV_ASYM_PAUSE |
2011 MR_LP_ADV_REMOTE_FAULT1 |
2012 MR_LP_ADV_REMOTE_FAULT2 |
2013 MR_LP_ADV_NEXT_PAGE |
2014 MR_TOGGLE_RX |
2015 MR_NP_RX);
2016 if (ap->rxconfig & ANEG_CFG_FD)
2017 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2018 if (ap->rxconfig & ANEG_CFG_HD)
2019 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2020 if (ap->rxconfig & ANEG_CFG_PS1)
2021 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2022 if (ap->rxconfig & ANEG_CFG_PS2)
2023 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2024 if (ap->rxconfig & ANEG_CFG_RF1)
2025 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2026 if (ap->rxconfig & ANEG_CFG_RF2)
2027 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2028 if (ap->rxconfig & ANEG_CFG_NP)
2029 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2030
2031 ap->link_time = ap->cur_time;
2032
2033 ap->flags ^= (MR_TOGGLE_TX);
2034 if (ap->rxconfig & 0x0008)
2035 ap->flags |= MR_TOGGLE_RX;
2036 if (ap->rxconfig & ANEG_CFG_NP)
2037 ap->flags |= MR_NP_RX;
2038 ap->flags |= MR_PAGE_RX;
2039
2040 ap->state = ANEG_STATE_COMPLETE_ACK;
2041 ret = ANEG_TIMER_ENAB;
2042 break;
2043
2044 case ANEG_STATE_COMPLETE_ACK:
2045 if (ap->ability_match != 0 &&
2046 ap->rxconfig == 0) {
2047 ap->state = ANEG_STATE_AN_ENABLE;
2048 break;
2049 }
2050 delta = ap->cur_time - ap->link_time;
2051 if (delta > ANEG_STATE_SETTLE_TIME) {
2052 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2053 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2054 } else {
2055 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2056 !(ap->flags & MR_NP_RX)) {
2057 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2058 } else {
2059 ret = ANEG_FAILED;
2060 }
2061 }
2062 }
2063 break;
2064
2065 case ANEG_STATE_IDLE_DETECT_INIT:
2066 ap->link_time = ap->cur_time;
2067 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2068 tw32_f(MAC_MODE, tp->mac_mode);
2069 udelay(40);
2070
2071 ap->state = ANEG_STATE_IDLE_DETECT;
2072 ret = ANEG_TIMER_ENAB;
2073 break;
2074
2075 case ANEG_STATE_IDLE_DETECT:
2076 if (ap->ability_match != 0 &&
2077 ap->rxconfig == 0) {
2078 ap->state = ANEG_STATE_AN_ENABLE;
2079 break;
2080 }
2081 delta = ap->cur_time - ap->link_time;
2082 if (delta > ANEG_STATE_SETTLE_TIME) {
2083 /* XXX another gem from the Broadcom driver :( */
2084 ap->state = ANEG_STATE_LINK_OK;
2085 }
2086 break;
2087
2088 case ANEG_STATE_LINK_OK:
2089 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2090 ret = ANEG_DONE;
2091 break;
2092
2093 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2094 /* ??? unimplemented */
2095 break;
2096
2097 case ANEG_STATE_NEXT_PAGE_WAIT:
2098 /* ??? unimplemented */
2099 break;
2100
2101 default:
2102 ret = ANEG_FAILED;
2103 break;
2104 };
2105
2106 return ret;
2107}
2108
2109static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2110{
2111 int res = 0;
2112 struct tg3_fiber_aneginfo aninfo;
2113 int status = ANEG_FAILED;
2114 unsigned int tick;
2115 u32 tmp;
2116
2117 tw32_f(MAC_TX_AUTO_NEG, 0);
2118
2119 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2120 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2121 udelay(40);
2122
2123 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2124 udelay(40);
2125
2126 memset(&aninfo, 0, sizeof(aninfo));
2127 aninfo.flags |= MR_AN_ENABLE;
2128 aninfo.state = ANEG_STATE_UNKNOWN;
2129 aninfo.cur_time = 0;
2130 tick = 0;
2131 while (++tick < 195000) {
2132 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2133 if (status == ANEG_DONE || status == ANEG_FAILED)
2134 break;
2135
2136 udelay(1);
2137 }
2138
2139 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2140 tw32_f(MAC_MODE, tp->mac_mode);
2141 udelay(40);
2142
2143 *flags = aninfo.flags;
2144
2145 if (status == ANEG_DONE &&
2146 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2147 MR_LP_ADV_FULL_DUPLEX)))
2148 res = 1;
2149
2150 return res;
2151}
2152
2153static void tg3_init_bcm8002(struct tg3 *tp)
2154{
2155 u32 mac_status = tr32(MAC_STATUS);
2156 int i;
2157
2158 /* Reset when initting first time or we have a link. */
2159 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2160 !(mac_status & MAC_STATUS_PCS_SYNCED))
2161 return;
2162
2163 /* Set PLL lock range. */
2164 tg3_writephy(tp, 0x16, 0x8007);
2165
2166 /* SW reset */
2167 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2168
2169 /* Wait for reset to complete. */
2170 /* XXX schedule_timeout() ... */
2171 for (i = 0; i < 500; i++)
2172 udelay(10);
2173
2174 /* Config mode; select PMA/Ch 1 regs. */
2175 tg3_writephy(tp, 0x10, 0x8411);
2176
2177 /* Enable auto-lock and comdet, select txclk for tx. */
2178 tg3_writephy(tp, 0x11, 0x0a10);
2179
2180 tg3_writephy(tp, 0x18, 0x00a0);
2181 tg3_writephy(tp, 0x16, 0x41ff);
2182
2183 /* Assert and deassert POR. */
2184 tg3_writephy(tp, 0x13, 0x0400);
2185 udelay(40);
2186 tg3_writephy(tp, 0x13, 0x0000);
2187
2188 tg3_writephy(tp, 0x11, 0x0a50);
2189 udelay(40);
2190 tg3_writephy(tp, 0x11, 0x0a10);
2191
2192 /* Wait for signal to stabilize */
2193 /* XXX schedule_timeout() ... */
2194 for (i = 0; i < 15000; i++)
2195 udelay(10);
2196
2197 /* Deselect the channel register so we can read the PHYID
2198 * later.
2199 */
2200 tg3_writephy(tp, 0x10, 0x8011);
2201}
2202
2203static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2204{
2205 u32 sg_dig_ctrl, sg_dig_status;
2206 u32 serdes_cfg, expected_sg_dig_ctrl;
2207 int workaround, port_a;
2208 int current_link_up;
2209
2210 serdes_cfg = 0;
2211 expected_sg_dig_ctrl = 0;
2212 workaround = 0;
2213 port_a = 1;
2214 current_link_up = 0;
2215
2216 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2217 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2218 workaround = 1;
2219 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2220 port_a = 0;
2221
2222 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2223 /* preserve bits 20-23 for voltage regulator */
2224 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2225 }
2226
2227 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2228
2229 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2230 if (sg_dig_ctrl & (1 << 31)) {
2231 if (workaround) {
2232 u32 val = serdes_cfg;
2233
2234 if (port_a)
2235 val |= 0xc010000;
2236 else
2237 val |= 0x4010000;
2238 tw32_f(MAC_SERDES_CFG, val);
2239 }
2240 tw32_f(SG_DIG_CTRL, 0x01388400);
2241 }
2242 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2243 tg3_setup_flow_control(tp, 0, 0);
2244 current_link_up = 1;
2245 }
2246 goto out;
2247 }
2248
2249 /* Want auto-negotiation. */
2250 expected_sg_dig_ctrl = 0x81388400;
2251
2252 /* Pause capability */
2253 expected_sg_dig_ctrl |= (1 << 11);
2254
2255 /* Asymettric pause */
2256 expected_sg_dig_ctrl |= (1 << 12);
2257
2258 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2259 if (workaround)
2260 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2261 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2262 udelay(5);
2263 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2264
2265 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2266 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2267 MAC_STATUS_SIGNAL_DET)) {
2268 int i;
2269
2270 /* Giver time to negotiate (~200ms) */
2271 for (i = 0; i < 40000; i++) {
2272 sg_dig_status = tr32(SG_DIG_STATUS);
2273 if (sg_dig_status & (0x3))
2274 break;
2275 udelay(5);
2276 }
2277 mac_status = tr32(MAC_STATUS);
2278
2279 if ((sg_dig_status & (1 << 1)) &&
2280 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2281 u32 local_adv, remote_adv;
2282
2283 local_adv = ADVERTISE_PAUSE_CAP;
2284 remote_adv = 0;
2285 if (sg_dig_status & (1 << 19))
2286 remote_adv |= LPA_PAUSE_CAP;
2287 if (sg_dig_status & (1 << 20))
2288 remote_adv |= LPA_PAUSE_ASYM;
2289
2290 tg3_setup_flow_control(tp, local_adv, remote_adv);
2291 current_link_up = 1;
2292 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2293 } else if (!(sg_dig_status & (1 << 1))) {
2294 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2295 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2296 else {
2297 if (workaround) {
2298 u32 val = serdes_cfg;
2299
2300 if (port_a)
2301 val |= 0xc010000;
2302 else
2303 val |= 0x4010000;
2304
2305 tw32_f(MAC_SERDES_CFG, val);
2306 }
2307
2308 tw32_f(SG_DIG_CTRL, 0x01388400);
2309 udelay(40);
2310
2311 /* Link parallel detection - link is up */
2312 /* only if we have PCS_SYNC and not */
2313 /* receiving config code words */
2314 mac_status = tr32(MAC_STATUS);
2315 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2316 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2317 tg3_setup_flow_control(tp, 0, 0);
2318 current_link_up = 1;
2319 }
2320 }
2321 }
2322 }
2323
2324out:
2325 return current_link_up;
2326}
2327
2328static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2329{
2330 int current_link_up = 0;
2331
2332 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2333 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2334 goto out;
2335 }
2336
2337 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2338 u32 flags;
2339 int i;
2340
2341 if (fiber_autoneg(tp, &flags)) {
2342 u32 local_adv, remote_adv;
2343
2344 local_adv = ADVERTISE_PAUSE_CAP;
2345 remote_adv = 0;
2346 if (flags & MR_LP_ADV_SYM_PAUSE)
2347 remote_adv |= LPA_PAUSE_CAP;
2348 if (flags & MR_LP_ADV_ASYM_PAUSE)
2349 remote_adv |= LPA_PAUSE_ASYM;
2350
2351 tg3_setup_flow_control(tp, local_adv, remote_adv);
2352
2353 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2354 current_link_up = 1;
2355 }
2356 for (i = 0; i < 30; i++) {
2357 udelay(20);
2358 tw32_f(MAC_STATUS,
2359 (MAC_STATUS_SYNC_CHANGED |
2360 MAC_STATUS_CFG_CHANGED));
2361 udelay(40);
2362 if ((tr32(MAC_STATUS) &
2363 (MAC_STATUS_SYNC_CHANGED |
2364 MAC_STATUS_CFG_CHANGED)) == 0)
2365 break;
2366 }
2367
2368 mac_status = tr32(MAC_STATUS);
2369 if (current_link_up == 0 &&
2370 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2371 !(mac_status & MAC_STATUS_RCVD_CFG))
2372 current_link_up = 1;
2373 } else {
2374 /* Forcing 1000FD link up. */
2375 current_link_up = 1;
2376 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2377
2378 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2379 udelay(40);
2380 }
2381
2382out:
2383 return current_link_up;
2384}
2385
2386static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2387{
2388 u32 orig_pause_cfg;
2389 u16 orig_active_speed;
2390 u8 orig_active_duplex;
2391 u32 mac_status;
2392 int current_link_up;
2393 int i;
2394
2395 orig_pause_cfg =
2396 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2397 TG3_FLAG_TX_PAUSE));
2398 orig_active_speed = tp->link_config.active_speed;
2399 orig_active_duplex = tp->link_config.active_duplex;
2400
2401 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2402 netif_carrier_ok(tp->dev) &&
2403 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2404 mac_status = tr32(MAC_STATUS);
2405 mac_status &= (MAC_STATUS_PCS_SYNCED |
2406 MAC_STATUS_SIGNAL_DET |
2407 MAC_STATUS_CFG_CHANGED |
2408 MAC_STATUS_RCVD_CFG);
2409 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2410 MAC_STATUS_SIGNAL_DET)) {
2411 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2412 MAC_STATUS_CFG_CHANGED));
2413 return 0;
2414 }
2415 }
2416
2417 tw32_f(MAC_TX_AUTO_NEG, 0);
2418
2419 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2420 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2421 tw32_f(MAC_MODE, tp->mac_mode);
2422 udelay(40);
2423
2424 if (tp->phy_id == PHY_ID_BCM8002)
2425 tg3_init_bcm8002(tp);
2426
2427 /* Enable link change event even when serdes polling. */
2428 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2429 udelay(40);
2430
2431 current_link_up = 0;
2432 mac_status = tr32(MAC_STATUS);
2433
2434 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2435 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2436 else
2437 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2438
2439 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2440 tw32_f(MAC_MODE, tp->mac_mode);
2441 udelay(40);
2442
2443 tp->hw_status->status =
2444 (SD_STATUS_UPDATED |
2445 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2446
2447 for (i = 0; i < 100; i++) {
2448 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2449 MAC_STATUS_CFG_CHANGED));
2450 udelay(5);
2451 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2452 MAC_STATUS_CFG_CHANGED)) == 0)
2453 break;
2454 }
2455
2456 mac_status = tr32(MAC_STATUS);
2457 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2458 current_link_up = 0;
2459 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2460 tw32_f(MAC_MODE, (tp->mac_mode |
2461 MAC_MODE_SEND_CONFIGS));
2462 udelay(1);
2463 tw32_f(MAC_MODE, tp->mac_mode);
2464 }
2465 }
2466
2467 if (current_link_up == 1) {
2468 tp->link_config.active_speed = SPEED_1000;
2469 tp->link_config.active_duplex = DUPLEX_FULL;
2470 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2471 LED_CTRL_LNKLED_OVERRIDE |
2472 LED_CTRL_1000MBPS_ON));
2473 } else {
2474 tp->link_config.active_speed = SPEED_INVALID;
2475 tp->link_config.active_duplex = DUPLEX_INVALID;
2476 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2477 LED_CTRL_LNKLED_OVERRIDE |
2478 LED_CTRL_TRAFFIC_OVERRIDE));
2479 }
2480
2481 if (current_link_up != netif_carrier_ok(tp->dev)) {
2482 if (current_link_up)
2483 netif_carrier_on(tp->dev);
2484 else
2485 netif_carrier_off(tp->dev);
2486 tg3_link_report(tp);
2487 } else {
2488 u32 now_pause_cfg =
2489 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2490 TG3_FLAG_TX_PAUSE);
2491 if (orig_pause_cfg != now_pause_cfg ||
2492 orig_active_speed != tp->link_config.active_speed ||
2493 orig_active_duplex != tp->link_config.active_duplex)
2494 tg3_link_report(tp);
2495 }
2496
2497 return 0;
2498}
2499
2500static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2501{
2502 int err;
2503
2504 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2505 err = tg3_setup_fiber_phy(tp, force_reset);
2506 } else {
2507 err = tg3_setup_copper_phy(tp, force_reset);
2508 }
2509
2510 if (tp->link_config.active_speed == SPEED_1000 &&
2511 tp->link_config.active_duplex == DUPLEX_HALF)
2512 tw32(MAC_TX_LENGTHS,
2513 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2514 (6 << TX_LENGTHS_IPG_SHIFT) |
2515 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2516 else
2517 tw32(MAC_TX_LENGTHS,
2518 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2519 (6 << TX_LENGTHS_IPG_SHIFT) |
2520 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2521
2522 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2523 if (netif_carrier_ok(tp->dev)) {
2524 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 2525 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 2526 } else {
2527 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2528 }
2529 }
2530
2531 return err;
2532}
2533
2534/* Tigon3 never reports partial packet sends. So we do not
2535 * need special logic to handle SKBs that have not had all
2536 * of their frags sent yet, like SunGEM does.
2537 */
2538static void tg3_tx(struct tg3 *tp)
2539{
2540 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2541 u32 sw_idx = tp->tx_cons;
2542
2543 while (sw_idx != hw_idx) {
2544 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2545 struct sk_buff *skb = ri->skb;
2546 int i;
2547
2548 if (unlikely(skb == NULL))
2549 BUG();
2550
2551 pci_unmap_single(tp->pdev,
2552 pci_unmap_addr(ri, mapping),
2553 skb_headlen(skb),
2554 PCI_DMA_TODEVICE);
2555
2556 ri->skb = NULL;
2557
2558 sw_idx = NEXT_TX(sw_idx);
2559
2560 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2561 if (unlikely(sw_idx == hw_idx))
2562 BUG();
2563
2564 ri = &tp->tx_buffers[sw_idx];
2565 if (unlikely(ri->skb != NULL))
2566 BUG();
2567
2568 pci_unmap_page(tp->pdev,
2569 pci_unmap_addr(ri, mapping),
2570 skb_shinfo(skb)->frags[i].size,
2571 PCI_DMA_TODEVICE);
2572
2573 sw_idx = NEXT_TX(sw_idx);
2574 }
2575
2576 dev_kfree_skb_irq(skb);
2577 }
2578
2579 tp->tx_cons = sw_idx;
2580
2581 if (netif_queue_stopped(tp->dev) &&
2582 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2583 netif_wake_queue(tp->dev);
2584}
2585
2586/* Returns size of skb allocated or < 0 on error.
2587 *
2588 * We only need to fill in the address because the other members
2589 * of the RX descriptor are invariant, see tg3_init_rings.
2590 *
2591 * Note the purposeful assymetry of cpu vs. chip accesses. For
2592 * posting buffers we only dirty the first cache line of the RX
2593 * descriptor (containing the address). Whereas for the RX status
2594 * buffers the cpu only reads the last cacheline of the RX descriptor
2595 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2596 */
2597static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2598 int src_idx, u32 dest_idx_unmasked)
2599{
2600 struct tg3_rx_buffer_desc *desc;
2601 struct ring_info *map, *src_map;
2602 struct sk_buff *skb;
2603 dma_addr_t mapping;
2604 int skb_size, dest_idx;
2605
2606 src_map = NULL;
2607 switch (opaque_key) {
2608 case RXD_OPAQUE_RING_STD:
2609 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2610 desc = &tp->rx_std[dest_idx];
2611 map = &tp->rx_std_buffers[dest_idx];
2612 if (src_idx >= 0)
2613 src_map = &tp->rx_std_buffers[src_idx];
2614 skb_size = RX_PKT_BUF_SZ;
2615 break;
2616
2617 case RXD_OPAQUE_RING_JUMBO:
2618 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2619 desc = &tp->rx_jumbo[dest_idx];
2620 map = &tp->rx_jumbo_buffers[dest_idx];
2621 if (src_idx >= 0)
2622 src_map = &tp->rx_jumbo_buffers[src_idx];
2623 skb_size = RX_JUMBO_PKT_BUF_SZ;
2624 break;
2625
2626 default:
2627 return -EINVAL;
2628 };
2629
2630 /* Do not overwrite any of the map or rp information
2631 * until we are sure we can commit to a new buffer.
2632 *
2633 * Callers depend upon this behavior and assume that
2634 * we leave everything unchanged if we fail.
2635 */
2636 skb = dev_alloc_skb(skb_size);
2637 if (skb == NULL)
2638 return -ENOMEM;
2639
2640 skb->dev = tp->dev;
2641 skb_reserve(skb, tp->rx_offset);
2642
2643 mapping = pci_map_single(tp->pdev, skb->data,
2644 skb_size - tp->rx_offset,
2645 PCI_DMA_FROMDEVICE);
2646
2647 map->skb = skb;
2648 pci_unmap_addr_set(map, mapping, mapping);
2649
2650 if (src_map != NULL)
2651 src_map->skb = NULL;
2652
2653 desc->addr_hi = ((u64)mapping >> 32);
2654 desc->addr_lo = ((u64)mapping & 0xffffffff);
2655
2656 return skb_size;
2657}
2658
2659/* We only need to move over in the address because the other
2660 * members of the RX descriptor are invariant. See notes above
2661 * tg3_alloc_rx_skb for full details.
2662 */
2663static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2664 int src_idx, u32 dest_idx_unmasked)
2665{
2666 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2667 struct ring_info *src_map, *dest_map;
2668 int dest_idx;
2669
2670 switch (opaque_key) {
2671 case RXD_OPAQUE_RING_STD:
2672 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2673 dest_desc = &tp->rx_std[dest_idx];
2674 dest_map = &tp->rx_std_buffers[dest_idx];
2675 src_desc = &tp->rx_std[src_idx];
2676 src_map = &tp->rx_std_buffers[src_idx];
2677 break;
2678
2679 case RXD_OPAQUE_RING_JUMBO:
2680 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2681 dest_desc = &tp->rx_jumbo[dest_idx];
2682 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2683 src_desc = &tp->rx_jumbo[src_idx];
2684 src_map = &tp->rx_jumbo_buffers[src_idx];
2685 break;
2686
2687 default:
2688 return;
2689 };
2690
2691 dest_map->skb = src_map->skb;
2692 pci_unmap_addr_set(dest_map, mapping,
2693 pci_unmap_addr(src_map, mapping));
2694 dest_desc->addr_hi = src_desc->addr_hi;
2695 dest_desc->addr_lo = src_desc->addr_lo;
2696
2697 src_map->skb = NULL;
2698}
2699
2700#if TG3_VLAN_TAG_USED
2701static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2702{
2703 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2704}
2705#endif
2706
2707/* The RX ring scheme is composed of multiple rings which post fresh
2708 * buffers to the chip, and one special ring the chip uses to report
2709 * status back to the host.
2710 *
2711 * The special ring reports the status of received packets to the
2712 * host. The chip does not write into the original descriptor the
2713 * RX buffer was obtained from. The chip simply takes the original
2714 * descriptor as provided by the host, updates the status and length
2715 * field, then writes this into the next status ring entry.
2716 *
2717 * Each ring the host uses to post buffers to the chip is described
2718 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
2719 * it is first placed into the on-chip ram. When the packet's length
2720 * is known, it walks down the TG3_BDINFO entries to select the ring.
2721 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2722 * which is within the range of the new packet's length is chosen.
2723 *
2724 * The "separate ring for rx status" scheme may sound queer, but it makes
2725 * sense from a cache coherency perspective. If only the host writes
2726 * to the buffer post rings, and only the chip writes to the rx status
2727 * rings, then cache lines never move beyond shared-modified state.
2728 * If both the host and chip were to write into the same ring, cache line
2729 * eviction could occur since both entities want it in an exclusive state.
2730 */
2731static int tg3_rx(struct tg3 *tp, int budget)
2732{
2733 u32 work_mask;
483ba50b
MC		 2734 u32 sw_idx = tp->rx_rcb_ptr;
2735 u16 hw_idx;
1da177e4
LT		 2736 int received;
2737
2738 hw_idx = tp->hw_status->idx[0].rx_producer;
2739 /*
2740 * We need to order the read of hw_idx and the read of
2741 * the opaque cookie.
2742 */
2743 rmb();
1da177e4
LT		 2744 work_mask = 0;
2745 received = 0;
2746 while (sw_idx != hw_idx && budget > 0) {
2747 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2748 unsigned int len;
2749 struct sk_buff *skb;
2750 dma_addr_t dma_addr;
2751 u32 opaque_key, desc_idx, *post_ptr;
2752
2753 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2754 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2755 if (opaque_key == RXD_OPAQUE_RING_STD) {
2756 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2757 mapping);
2758 skb = tp->rx_std_buffers[desc_idx].skb;
2759 post_ptr = &tp->rx_std_ptr;
2760 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2761 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2762 mapping);
2763 skb = tp->rx_jumbo_buffers[desc_idx].skb;
2764 post_ptr = &tp->rx_jumbo_ptr;
2765 }
2766 else {
2767 goto next_pkt_nopost;
2768 }
2769
2770 work_mask |= opaque_key;
2771
2772 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2773 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2774 drop_it:
2775 tg3_recycle_rx(tp, opaque_key,
2776 desc_idx, *post_ptr);
2777 drop_it_no_recycle:
2778 /* Other statistics kept track of by card. */
2779 tp->net_stats.rx_dropped++;
2780 goto next_pkt;
2781 }
2782
2783 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2784
2785 if (len > RX_COPY_THRESHOLD
2786 && tp->rx_offset == 2
2787 /* rx_offset != 2 iff this is a 5701 card running
2788 * in PCI-X mode [see tg3_get_invariants()] */
2789 ) {
2790 int skb_size;
2791
2792 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2793 desc_idx, *post_ptr);
2794 if (skb_size < 0)
2795 goto drop_it;
2796
2797 pci_unmap_single(tp->pdev, dma_addr,
2798 skb_size - tp->rx_offset,
2799 PCI_DMA_FROMDEVICE);
2800
2801 skb_put(skb, len);
2802 } else {
2803 struct sk_buff *copy_skb;
2804
2805 tg3_recycle_rx(tp, opaque_key,
2806 desc_idx, *post_ptr);
2807
2808 copy_skb = dev_alloc_skb(len + 2);
2809 if (copy_skb == NULL)
2810 goto drop_it_no_recycle;
2811
2812 copy_skb->dev = tp->dev;
2813 skb_reserve(copy_skb, 2);
2814 skb_put(copy_skb, len);
2815 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2816 memcpy(copy_skb->data, skb->data, len);
2817 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2818
2819 /* We'll reuse the original ring buffer. */
2820 skb = copy_skb;
2821 }
2822
2823 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2824 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2825 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2826 >> RXD_TCPCSUM_SHIFT) == 0xffff))
2827 skb->ip_summed = CHECKSUM_UNNECESSARY;
2828 else
2829 skb->ip_summed = CHECKSUM_NONE;
2830
2831 skb->protocol = eth_type_trans(skb, tp->dev);
2832#if TG3_VLAN_TAG_USED
2833 if (tp->vlgrp != NULL &&
2834 desc->type_flags & RXD_FLAG_VLAN) {
2835 tg3_vlan_rx(tp, skb,
2836 desc->err_vlan & RXD_VLAN_MASK);
2837 } else
2838#endif
2839 netif_receive_skb(skb);
2840
2841 tp->dev->last_rx = jiffies;
2842 received++;
2843 budget--;
2844
2845next_pkt:
2846 (*post_ptr)++;
2847next_pkt_nopost:
483ba50b
MC		 2848 sw_idx++;
2849 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
52f6d697
MC		 2850
2851 /* Refresh hw_idx to see if there is new work */
2852 if (sw_idx == hw_idx) {
2853 hw_idx = tp->hw_status->idx[0].rx_producer;
2854 rmb();
2855 }
1da177e4
LT		 2856 }
2857
2858 /* ACK the status ring. */
483ba50b
MC		 2859 tp->rx_rcb_ptr = sw_idx;
2860 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 2861
2862 /* Refill RX ring(s). */
2863 if (work_mask & RXD_OPAQUE_RING_STD) {
2864 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2865 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2866 sw_idx);
2867 }
2868 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2869 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2870 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2871 sw_idx);
2872 }
2873 mmiowb();
2874
2875 return received;
2876}
2877
2878static int tg3_poll(struct net_device *netdev, int *budget)
2879{
2880 struct tg3 *tp = netdev_priv(netdev);
2881 struct tg3_hw_status *sblk = tp->hw_status;
2882 unsigned long flags;
2883 int done;
2884
2885 spin_lock_irqsave(&tp->lock, flags);
2886
2887 /* handle link change and other phy events */
2888 if (!(tp->tg3_flags &
2889 (TG3_FLAG_USE_LINKCHG_REG |
2890 TG3_FLAG_POLL_SERDES))) {
2891 if (sblk->status & SD_STATUS_LINK_CHG) {
2892 sblk->status = SD_STATUS_UPDATED |
2893 (sblk->status & ~SD_STATUS_LINK_CHG);
2894 tg3_setup_phy(tp, 0);
2895 }
2896 }
2897
2898 /* run TX completion thread */
2899 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2900 spin_lock(&tp->tx_lock);
2901 tg3_tx(tp);
2902 spin_unlock(&tp->tx_lock);
2903 }
2904
2905 spin_unlock_irqrestore(&tp->lock, flags);
2906
2907 /* run RX thread, within the bounds set by NAPI.
2908 * All RX "locking" is done by ensuring outside
2909 * code synchronizes with dev->poll()
2910 */
1da177e4
LT		 2911 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2912 int orig_budget = *budget;
2913 int work_done;
2914
2915 if (orig_budget > netdev->quota)
2916 orig_budget = netdev->quota;
2917
2918 work_done = tg3_rx(tp, orig_budget);
2919
2920 *budget -= work_done;
2921 netdev->quota -= work_done;
1da177e4
LT		 2922 }
2923
f7383c22
DM		 2924 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
2925 tp->last_tag = sblk->status_tag;
2926 rmb();
2927
1da177e4 2928 /* if no more work, tell net stack and NIC we're done */
f7383c22 2929 done = !tg3_has_work(tp);
1da177e4
LT		 2930 if (done) {
2931 spin_lock_irqsave(&tp->lock, flags);
2932 __netif_rx_complete(netdev);
2933 tg3_restart_ints(tp);
2934 spin_unlock_irqrestore(&tp->lock, flags);
2935 }
2936
2937 return (done ? 0 : 1);
2938}
2939
88b06bc2
MC		 2940/* MSI ISR - No need to check for interrupt sharing and no need to
2941 * flush status block and interrupt mailbox. PCI ordering rules
2942 * guarantee that MSI will arrive after the status block.
2943 */
2944static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2945{
2946 struct net_device *dev = dev_id;
2947 struct tg3 *tp = netdev_priv(dev);
2948 struct tg3_hw_status *sblk = tp->hw_status;
2949 unsigned long flags;
2950
2951 spin_lock_irqsave(&tp->lock, flags);
2952
2953 /*
fac9b83e 2954 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 2955 * chip-internal interrupt pending events.
fac9b83e 2956 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 2957 * NIC to stop sending us irqs, engaging "in-intr-handler"
2958 * event coalescing.
2959 */
2960 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
fac9b83e 2961 tp->last_tag = sblk->status_tag;
88b06bc2 2962 sblk->status &= ~SD_STATUS_UPDATED;
04237ddd 2963 if (likely(tg3_has_work(tp)))
88b06bc2
MC		 2964 netif_rx_schedule(dev); /* schedule NAPI poll */
2965 else {
fac9b83e 2966 /* No work, re-enable interrupts. */
88b06bc2 2967 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 2968 tp->last_tag << 24);
88b06bc2
MC		 2969 }
2970
2971 spin_unlock_irqrestore(&tp->lock, flags);
2972
2973 return IRQ_RETVAL(1);
2974}
2975
1da177e4
LT		 2976static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2977{
2978 struct net_device *dev = dev_id;
2979 struct tg3 *tp = netdev_priv(dev);
2980 struct tg3_hw_status *sblk = tp->hw_status;
2981 unsigned long flags;
2982 unsigned int handled = 1;
2983
2984 spin_lock_irqsave(&tp->lock, flags);
2985
2986 /* In INTx mode, it is possible for the interrupt to arrive at
2987 * the CPU before the status block posted prior to the interrupt.
2988 * Reading the PCI State register will confirm whether the
2989 * interrupt is ours and will flush the status block.
2990 */
2991 if ((sblk->status & SD_STATUS_UPDATED) ||
2992 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2993 /*
fac9b83e 2994 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 2995 * chip-internal interrupt pending events.
fac9b83e 2996 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 2997 * NIC to stop sending us irqs, engaging "in-intr-handler"
2998 * event coalescing.
2999 */
3000 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3001 0x00000001);
fac9b83e
DM		 3002 sblk->status &= ~SD_STATUS_UPDATED;
3003 if (likely(tg3_has_work(tp)))
3004 netif_rx_schedule(dev); /* schedule NAPI poll */
3005 else {
3006 /* No work, shared interrupt perhaps? re-enable
3007 * interrupts, and flush that PCI write
3008 */
3009 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3010 0x00000000);
3011 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3012 }
3013 } else { /* shared interrupt */
3014 handled = 0;
3015 }
3016
3017 spin_unlock_irqrestore(&tp->lock, flags);
3018
3019 return IRQ_RETVAL(handled);
3020}
3021
3022static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3023{
3024 struct net_device *dev = dev_id;
3025 struct tg3 *tp = netdev_priv(dev);
3026 struct tg3_hw_status *sblk = tp->hw_status;
3027 unsigned long flags;
3028 unsigned int handled = 1;
3029
3030 spin_lock_irqsave(&tp->lock, flags);
3031
3032 /* In INTx mode, it is possible for the interrupt to arrive at
3033 * the CPU before the status block posted prior to the interrupt.
3034 * Reading the PCI State register will confirm whether the
3035 * interrupt is ours and will flush the status block.
3036 */
3037 if ((sblk->status & SD_STATUS_UPDATED) ||
3038 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3039 /*
fac9b83e
DM		 3040 * writing any value to intr-mbox-0 clears PCI INTA# and
3041 * chip-internal interrupt pending events.
3042 * writing non-zero to intr-mbox-0 additional tells the
3043 * NIC to stop sending us irqs, engaging "in-intr-handler"
3044 * event coalescing.
1da177e4 3045 */
fac9b83e
DM		 3046 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3047 0x00000001);
3048 tp->last_tag = sblk->status_tag;
1da177e4 3049 sblk->status &= ~SD_STATUS_UPDATED;
04237ddd 3050 if (likely(tg3_has_work(tp)))
1da177e4
LT		 3051 netif_rx_schedule(dev); /* schedule NAPI poll */
3052 else {
3053 /* no work, shared interrupt perhaps? re-enable
3054 * interrupts, and flush that PCI write
3055 */
3056 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3057 tp->last_tag << 24);
1da177e4
LT		 3058 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3059 }
3060 } else { /* shared interrupt */
3061 handled = 0;
3062 }
3063
3064 spin_unlock_irqrestore(&tp->lock, flags);
3065
3066 return IRQ_RETVAL(handled);
3067}
3068
7938109f
MC		 3069/* ISR for interrupt test */
3070static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3071 struct pt_regs *regs)
3072{
3073 struct net_device *dev = dev_id;
3074 struct tg3 *tp = netdev_priv(dev);
3075 struct tg3_hw_status *sblk = tp->hw_status;
3076
3077 if (sblk->status & SD_STATUS_UPDATED) {
3078 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3079 0x00000001);
3080 return IRQ_RETVAL(1);
3081 }
3082 return IRQ_RETVAL(0);
3083}
3084
1da177e4 3085static int tg3_init_hw(struct tg3 *);
944d980e 3086static int tg3_halt(struct tg3 *, int, int);
1da177e4
LT		 3087
3088#ifdef CONFIG_NET_POLL_CONTROLLER
3089static void tg3_poll_controller(struct net_device *dev)
3090{
88b06bc2
MC		 3091 struct tg3 *tp = netdev_priv(dev);
3092
3093 tg3_interrupt(tp->pdev->irq, dev, NULL);
1da177e4
LT		 3094}
3095#endif
3096
3097static void tg3_reset_task(void *_data)
3098{
3099 struct tg3 *tp = _data;
3100 unsigned int restart_timer;
3101
3102 tg3_netif_stop(tp);
3103
3104 spin_lock_irq(&tp->lock);
3105 spin_lock(&tp->tx_lock);
3106
3107 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3108 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3109
944d980e 3110 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
1da177e4
LT		 3111 tg3_init_hw(tp);
3112
3113 tg3_netif_start(tp);
3114
3115 spin_unlock(&tp->tx_lock);
3116 spin_unlock_irq(&tp->lock);
3117
3118 if (restart_timer)
3119 mod_timer(&tp->timer, jiffies + 1);
3120}
3121
3122static void tg3_tx_timeout(struct net_device *dev)
3123{
3124 struct tg3 *tp = netdev_priv(dev);
3125
3126 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3127 dev->name);
3128
3129 schedule_work(&tp->reset_task);
3130}
3131
3132static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3133
3134static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3135 u32 guilty_entry, int guilty_len,
3136 u32 last_plus_one, u32 *start, u32 mss)
3137{
3138 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3139 dma_addr_t new_addr;
3140 u32 entry = *start;
3141 int i;
3142
3143 if (!new_skb) {
3144 dev_kfree_skb(skb);
3145 return -1;
3146 }
3147
3148 /* New SKB is guaranteed to be linear. */
3149 entry = *start;
3150 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3151 PCI_DMA_TODEVICE);
3152 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3153 (skb->ip_summed == CHECKSUM_HW) ?
3154 TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3155 *start = NEXT_TX(entry);
3156
3157 /* Now clean up the sw ring entries. */
3158 i = 0;
3159 while (entry != last_plus_one) {
3160 int len;
3161
3162 if (i == 0)
3163 len = skb_headlen(skb);
3164 else
3165 len = skb_shinfo(skb)->frags[i-1].size;
3166 pci_unmap_single(tp->pdev,
3167 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3168 len, PCI_DMA_TODEVICE);
3169 if (i == 0) {
3170 tp->tx_buffers[entry].skb = new_skb;
3171 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3172 } else {
3173 tp->tx_buffers[entry].skb = NULL;
3174 }
3175 entry = NEXT_TX(entry);
3176 i++;
3177 }
3178
3179 dev_kfree_skb(skb);
3180
3181 return 0;
3182}
3183
3184static void tg3_set_txd(struct tg3 *tp, int entry,
3185 dma_addr_t mapping, int len, u32 flags,
3186 u32 mss_and_is_end)
3187{
3188 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3189 int is_end = (mss_and_is_end & 0x1);
3190 u32 mss = (mss_and_is_end >> 1);
3191 u32 vlan_tag = 0;
3192
3193 if (is_end)
3194 flags |= TXD_FLAG_END;
3195 if (flags & TXD_FLAG_VLAN) {
3196 vlan_tag = flags >> 16;
3197 flags &= 0xffff;
3198 }
3199 vlan_tag |= (mss << TXD_MSS_SHIFT);
3200
3201 txd->addr_hi = ((u64) mapping >> 32);
3202 txd->addr_lo = ((u64) mapping & 0xffffffff);
3203 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3204 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3205}
3206
3207static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3208{
3209 u32 base = (u32) mapping & 0xffffffff;
3210
3211 return ((base > 0xffffdcc0) &&
3212 (base + len + 8 < base));
3213}
3214
3215static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3216{
3217 struct tg3 *tp = netdev_priv(dev);
3218 dma_addr_t mapping;
3219 unsigned int i;
3220 u32 len, entry, base_flags, mss;
3221 int would_hit_hwbug;
3222 unsigned long flags;
3223
3224 len = skb_headlen(skb);
3225
3226 /* No BH disabling for tx_lock here. We are running in BH disabled
3227 * context and TX reclaim runs via tp->poll inside of a software
3228 * interrupt. Rejoice!
3229 *
3230 * Actually, things are not so simple. If we are to take a hw
3231 * IRQ here, we can deadlock, consider:
3232 *
3233 * CPU1 CPU2
3234 * tg3_start_xmit
3235 * take tp->tx_lock
3236 * tg3_timer
3237 * take tp->lock
3238 * tg3_interrupt
3239 * spin on tp->lock
3240 * spin on tp->tx_lock
3241 *
3242 * So we really do need to disable interrupts when taking
3243 * tx_lock here.
3244 */
3245 local_irq_save(flags);
3246 if (!spin_trylock(&tp->tx_lock)) {
3247 local_irq_restore(flags);
3248 return NETDEV_TX_LOCKED;
3249 }
3250
3251 /* This is a hard error, log it. */
3252 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3253 netif_stop_queue(dev);
3254 spin_unlock_irqrestore(&tp->tx_lock, flags);
3255 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3256 dev->name);
3257 return NETDEV_TX_BUSY;
3258 }
3259
3260 entry = tp->tx_prod;
3261 base_flags = 0;
3262 if (skb->ip_summed == CHECKSUM_HW)
3263 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3264#if TG3_TSO_SUPPORT != 0
3265 mss = 0;
3266 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3267 (mss = skb_shinfo(skb)->tso_size) != 0) {
3268 int tcp_opt_len, ip_tcp_len;
3269
3270 if (skb_header_cloned(skb) &&
3271 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3272 dev_kfree_skb(skb);
3273 goto out_unlock;
3274 }
3275
3276 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3277 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3278
3279 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3280 TXD_FLAG_CPU_POST_DMA);
3281
3282 skb->nh.iph->check = 0;
3283 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3284 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3285 skb->h.th->check = 0;
3286 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3287 }
3288 else {
3289 skb->h.th->check =
3290 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3291 skb->nh.iph->daddr,
3292 0, IPPROTO_TCP, 0);
3293 }
3294
3295 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3296 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3297 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3298 int tsflags;
3299
3300 tsflags = ((skb->nh.iph->ihl - 5) +
3301 (tcp_opt_len >> 2));
3302 mss |= (tsflags << 11);
3303 }
3304 } else {
3305 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3306 int tsflags;
3307
3308 tsflags = ((skb->nh.iph->ihl - 5) +
3309 (tcp_opt_len >> 2));
3310 base_flags |= tsflags << 12;
3311 }
3312 }
3313 }
3314#else
3315 mss = 0;
3316#endif
3317#if TG3_VLAN_TAG_USED
3318 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3319 base_flags |= (TXD_FLAG_VLAN |
3320 (vlan_tx_tag_get(skb) << 16));
3321#endif
3322
3323 /* Queue skb data, a.k.a. the main skb fragment. */
3324 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3325
3326 tp->tx_buffers[entry].skb = skb;
3327 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3328
3329 would_hit_hwbug = 0;
3330
3331 if (tg3_4g_overflow_test(mapping, len))
3332 would_hit_hwbug = entry + 1;
3333
3334 tg3_set_txd(tp, entry, mapping, len, base_flags,
3335 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3336
3337 entry = NEXT_TX(entry);
3338
3339 /* Now loop through additional data fragments, and queue them. */
3340 if (skb_shinfo(skb)->nr_frags > 0) {
3341 unsigned int i, last;
3342
3343 last = skb_shinfo(skb)->nr_frags - 1;
3344 for (i = 0; i <= last; i++) {
3345 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3346
3347 len = frag->size;
3348 mapping = pci_map_page(tp->pdev,
3349 frag->page,
3350 frag->page_offset,
3351 len, PCI_DMA_TODEVICE);
3352
3353 tp->tx_buffers[entry].skb = NULL;
3354 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3355
3356 if (tg3_4g_overflow_test(mapping, len)) {
3357 /* Only one should match. */
3358 if (would_hit_hwbug)
3359 BUG();
3360 would_hit_hwbug = entry + 1;
3361 }
3362
3363 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3364 tg3_set_txd(tp, entry, mapping, len,
3365 base_flags, (i == last)|(mss << 1));
3366 else
3367 tg3_set_txd(tp, entry, mapping, len,
3368 base_flags, (i == last));
3369
3370 entry = NEXT_TX(entry);
3371 }
3372 }
3373
3374 if (would_hit_hwbug) {
3375 u32 last_plus_one = entry;
3376 u32 start;
3377 unsigned int len = 0;
3378
3379 would_hit_hwbug -= 1;
3380 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3381 entry &= (TG3_TX_RING_SIZE - 1);
3382 start = entry;
3383 i = 0;
3384 while (entry != last_plus_one) {
3385 if (i == 0)
3386 len = skb_headlen(skb);
3387 else
3388 len = skb_shinfo(skb)->frags[i-1].size;
3389
3390 if (entry == would_hit_hwbug)
3391 break;
3392
3393 i++;
3394 entry = NEXT_TX(entry);
3395
3396 }
3397
3398 /* If the workaround fails due to memory/mapping
3399 * failure, silently drop this packet.
3400 */
3401 if (tigon3_4gb_hwbug_workaround(tp, skb,
3402 entry, len,
3403 last_plus_one,
3404 &start, mss))
3405 goto out_unlock;
3406
3407 entry = start;
3408 }
3409
3410 /* Packets are ready, update Tx producer idx local and on card. */
3411 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3412
3413 tp->tx_prod = entry;
3414 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3415 netif_stop_queue(dev);
3416
3417out_unlock:
3418 mmiowb();
3419 spin_unlock_irqrestore(&tp->tx_lock, flags);
3420
3421 dev->trans_start = jiffies;
3422
3423 return NETDEV_TX_OK;
3424}
3425
3426static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3427 int new_mtu)
3428{
3429 dev->mtu = new_mtu;
3430
3431 if (new_mtu > ETH_DATA_LEN)
3432 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3433 else
3434 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3435}
3436
3437static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3438{
3439 struct tg3 *tp = netdev_priv(dev);
3440
3441 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3442 return -EINVAL;
3443
3444 if (!netif_running(dev)) {
3445 /* We'll just catch it later when the
3446 * device is up'd.
3447 */
3448 tg3_set_mtu(dev, tp, new_mtu);
3449 return 0;
3450 }
3451
3452 tg3_netif_stop(tp);
3453 spin_lock_irq(&tp->lock);
3454 spin_lock(&tp->tx_lock);
3455
944d980e 3456 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 3457
3458 tg3_set_mtu(dev, tp, new_mtu);
3459
3460 tg3_init_hw(tp);
3461
3462 tg3_netif_start(tp);
3463
3464 spin_unlock(&tp->tx_lock);
3465 spin_unlock_irq(&tp->lock);
3466
3467 return 0;
3468}
3469
3470/* Free up pending packets in all rx/tx rings.
3471 *
3472 * The chip has been shut down and the driver detached from
3473 * the networking, so no interrupts or new tx packets will
3474 * end up in the driver. tp->{tx,}lock is not held and we are not
3475 * in an interrupt context and thus may sleep.
3476 */
3477static void tg3_free_rings(struct tg3 *tp)
3478{
3479 struct ring_info *rxp;
3480 int i;
3481
3482 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3483 rxp = &tp->rx_std_buffers[i];
3484
3485 if (rxp->skb == NULL)
3486 continue;
3487 pci_unmap_single(tp->pdev,
3488 pci_unmap_addr(rxp, mapping),
3489 RX_PKT_BUF_SZ - tp->rx_offset,
3490 PCI_DMA_FROMDEVICE);
3491 dev_kfree_skb_any(rxp->skb);
3492 rxp->skb = NULL;
3493 }
3494
3495 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3496 rxp = &tp->rx_jumbo_buffers[i];
3497
3498 if (rxp->skb == NULL)
3499 continue;
3500 pci_unmap_single(tp->pdev,
3501 pci_unmap_addr(rxp, mapping),
3502 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3503 PCI_DMA_FROMDEVICE);
3504 dev_kfree_skb_any(rxp->skb);
3505 rxp->skb = NULL;
3506 }
3507
3508 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3509 struct tx_ring_info *txp;
3510 struct sk_buff *skb;
3511 int j;
3512
3513 txp = &tp->tx_buffers[i];
3514 skb = txp->skb;
3515
3516 if (skb == NULL) {
3517 i++;
3518 continue;
3519 }
3520
3521 pci_unmap_single(tp->pdev,
3522 pci_unmap_addr(txp, mapping),
3523 skb_headlen(skb),
3524 PCI_DMA_TODEVICE);
3525 txp->skb = NULL;
3526
3527 i++;
3528
3529 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3530 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3531 pci_unmap_page(tp->pdev,
3532 pci_unmap_addr(txp, mapping),
3533 skb_shinfo(skb)->frags[j].size,
3534 PCI_DMA_TODEVICE);
3535 i++;
3536 }
3537
3538 dev_kfree_skb_any(skb);
3539 }
3540}
3541
3542/* Initialize tx/rx rings for packet processing.
3543 *
3544 * The chip has been shut down and the driver detached from
3545 * the networking, so no interrupts or new tx packets will
3546 * end up in the driver. tp->{tx,}lock are held and thus
3547 * we may not sleep.
3548 */
3549static void tg3_init_rings(struct tg3 *tp)
3550{
3551 u32 i;
3552
3553 /* Free up all the SKBs. */
3554 tg3_free_rings(tp);
3555
3556 /* Zero out all descriptors. */
3557 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3558 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3559 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3560 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3561
3562 /* Initialize invariants of the rings, we only set this
3563 * stuff once. This works because the card does not
3564 * write into the rx buffer posting rings.
3565 */
3566 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3567 struct tg3_rx_buffer_desc *rxd;
3568
3569 rxd = &tp->rx_std[i];
3570 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3571 << RXD_LEN_SHIFT;
3572 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3573 rxd->opaque = (RXD_OPAQUE_RING_STD |
3574 (i << RXD_OPAQUE_INDEX_SHIFT));
3575 }
3576
3577 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3578 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3579 struct tg3_rx_buffer_desc *rxd;
3580
3581 rxd = &tp->rx_jumbo[i];
3582 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3583 << RXD_LEN_SHIFT;
3584 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3585 RXD_FLAG_JUMBO;
3586 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3587 (i << RXD_OPAQUE_INDEX_SHIFT));
3588 }
3589 }
3590
3591 /* Now allocate fresh SKBs for each rx ring. */
3592 for (i = 0; i < tp->rx_pending; i++) {
3593 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3594 -1, i) < 0)
3595 break;
3596 }
3597
3598 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3599 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3600 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3601 -1, i) < 0)
3602 break;
3603 }
3604 }
3605}
3606
3607/*
3608 * Must not be invoked with interrupt sources disabled and
3609 * the hardware shutdown down.
3610 */
3611static void tg3_free_consistent(struct tg3 *tp)
3612{
3613 if (tp->rx_std_buffers) {
3614 kfree(tp->rx_std_buffers);
3615 tp->rx_std_buffers = NULL;
3616 }
3617 if (tp->rx_std) {
3618 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3619 tp->rx_std, tp->rx_std_mapping);
3620 tp->rx_std = NULL;
3621 }
3622 if (tp->rx_jumbo) {
3623 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3624 tp->rx_jumbo, tp->rx_jumbo_mapping);
3625 tp->rx_jumbo = NULL;
3626 }
3627 if (tp->rx_rcb) {
3628 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3629 tp->rx_rcb, tp->rx_rcb_mapping);
3630 tp->rx_rcb = NULL;
3631 }
3632 if (tp->tx_ring) {
3633 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3634 tp->tx_ring, tp->tx_desc_mapping);
3635 tp->tx_ring = NULL;
3636 }
3637 if (tp->hw_status) {
3638 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3639 tp->hw_status, tp->status_mapping);
3640 tp->hw_status = NULL;
3641 }
3642 if (tp->hw_stats) {
3643 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3644 tp->hw_stats, tp->stats_mapping);
3645 tp->hw_stats = NULL;
3646 }
3647}
3648
3649/*
3650 * Must not be invoked with interrupt sources disabled and
3651 * the hardware shutdown down. Can sleep.
3652 */
3653static int tg3_alloc_consistent(struct tg3 *tp)
3654{
3655 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3656 (TG3_RX_RING_SIZE +
3657 TG3_RX_JUMBO_RING_SIZE)) +
3658 (sizeof(struct tx_ring_info) *
3659 TG3_TX_RING_SIZE),
3660 GFP_KERNEL);
3661 if (!tp->rx_std_buffers)
3662 return -ENOMEM;
3663
3664 memset(tp->rx_std_buffers, 0,
3665 (sizeof(struct ring_info) *
3666 (TG3_RX_RING_SIZE +
3667 TG3_RX_JUMBO_RING_SIZE)) +
3668 (sizeof(struct tx_ring_info) *
3669 TG3_TX_RING_SIZE));
3670
3671 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3672 tp->tx_buffers = (struct tx_ring_info *)
3673 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3674
3675 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3676 &tp->rx_std_mapping);
3677 if (!tp->rx_std)
3678 goto err_out;
3679
3680 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3681 &tp->rx_jumbo_mapping);
3682
3683 if (!tp->rx_jumbo)
3684 goto err_out;
3685
3686 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3687 &tp->rx_rcb_mapping);
3688 if (!tp->rx_rcb)
3689 goto err_out;
3690
3691 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3692 &tp->tx_desc_mapping);
3693 if (!tp->tx_ring)
3694 goto err_out;
3695
3696 tp->hw_status = pci_alloc_consistent(tp->pdev,
3697 TG3_HW_STATUS_SIZE,
3698 &tp->status_mapping);
3699 if (!tp->hw_status)
3700 goto err_out;
3701
3702 tp->hw_stats = pci_alloc_consistent(tp->pdev,
3703 sizeof(struct tg3_hw_stats),
3704 &tp->stats_mapping);
3705 if (!tp->hw_stats)
3706 goto err_out;
3707
3708 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3709 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3710
3711 return 0;
3712
3713err_out:
3714 tg3_free_consistent(tp);
3715 return -ENOMEM;
3716}
3717
3718#define MAX_WAIT_CNT 1000
3719
3720/* To stop a block, clear the enable bit and poll till it
3721 * clears. tp->lock is held.
3722 */
b3b7d6be 3723static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 3724{
3725 unsigned int i;
3726 u32 val;
3727
3728 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3729 switch (ofs) {
3730 case RCVLSC_MODE:
3731 case DMAC_MODE:
3732 case MBFREE_MODE:
3733 case BUFMGR_MODE:
3734 case MEMARB_MODE:
3735 /* We can't enable/disable these bits of the
3736 * 5705/5750, just say success.
3737 */
3738 return 0;
3739
3740 default:
3741 break;
3742 };
3743 }
3744
3745 val = tr32(ofs);
3746 val &= ~enable_bit;
3747 tw32_f(ofs, val);
3748
3749 for (i = 0; i < MAX_WAIT_CNT; i++) {
3750 udelay(100);
3751 val = tr32(ofs);
3752 if ((val & enable_bit) == 0)
3753 break;
3754 }
3755
b3b7d6be 3756 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 3757 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3758 "ofs=%lx enable_bit=%x\n",
3759 ofs, enable_bit);
3760 return -ENODEV;
3761 }
3762
3763 return 0;
3764}
3765
3766/* tp->lock is held. */
b3b7d6be 3767static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 3768{
3769 int i, err;
3770
3771 tg3_disable_ints(tp);
3772
3773 tp->rx_mode &= ~RX_MODE_ENABLE;
3774 tw32_f(MAC_RX_MODE, tp->rx_mode);
3775 udelay(10);
3776
b3b7d6be
DM		 3777 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
3778 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
3779 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
3780 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
3781 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
3782 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
3783
3784 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
3785 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
3786 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
3787 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
3788 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
3789 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
3790 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 3791
3792 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3793 tw32_f(MAC_MODE, tp->mac_mode);
3794 udelay(40);
3795
3796 tp->tx_mode &= ~TX_MODE_ENABLE;
3797 tw32_f(MAC_TX_MODE, tp->tx_mode);
3798
3799 for (i = 0; i < MAX_WAIT_CNT; i++) {
3800 udelay(100);
3801 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3802 break;
3803 }
3804 if (i >= MAX_WAIT_CNT) {
3805 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3806 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3807 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 3808 err |= -ENODEV;
1da177e4
LT		 3809 }
3810
e6de8ad1 3811 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 3812 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
3813 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 3814
3815 tw32(FTQ_RESET, 0xffffffff);
3816 tw32(FTQ_RESET, 0x00000000);
3817
b3b7d6be
DM		 3818 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
3819 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 3820
3821 if (tp->hw_status)
3822 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3823 if (tp->hw_stats)
3824 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3825
1da177e4
LT		 3826 return err;
3827}
3828
3829/* tp->lock is held. */
3830static int tg3_nvram_lock(struct tg3 *tp)
3831{
3832 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3833 int i;
3834
3835 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3836 for (i = 0; i < 8000; i++) {
3837 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3838 break;
3839 udelay(20);
3840 }
3841 if (i == 8000)
3842 return -ENODEV;
3843 }
3844 return 0;
3845}
3846
3847/* tp->lock is held. */
3848static void tg3_nvram_unlock(struct tg3 *tp)
3849{
3850 if (tp->tg3_flags & TG3_FLAG_NVRAM)
3851 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3852}
3853
e6af301b
MC		 3854/* tp->lock is held. */
3855static void tg3_enable_nvram_access(struct tg3 *tp)
3856{
3857 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3858 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3859 u32 nvaccess = tr32(NVRAM_ACCESS);
3860
3861 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3862 }
3863}
3864
3865/* tp->lock is held. */
3866static void tg3_disable_nvram_access(struct tg3 *tp)
3867{
3868 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3869 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3870 u32 nvaccess = tr32(NVRAM_ACCESS);
3871
3872 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3873 }
3874}
3875
1da177e4
LT		 3876/* tp->lock is held. */
3877static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3878{
3879 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3880 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3881 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3882
3883 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3884 switch (kind) {
3885 case RESET_KIND_INIT:
3886 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3887 DRV_STATE_START);
3888 break;
3889
3890 case RESET_KIND_SHUTDOWN:
3891 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3892 DRV_STATE_UNLOAD);
3893 break;
3894
3895 case RESET_KIND_SUSPEND:
3896 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3897 DRV_STATE_SUSPEND);
3898 break;
3899
3900 default:
3901 break;
3902 };
3903 }
3904}
3905
3906/* tp->lock is held. */
3907static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3908{
3909 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3910 switch (kind) {
3911 case RESET_KIND_INIT:
3912 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3913 DRV_STATE_START_DONE);
3914 break;
3915
3916 case RESET_KIND_SHUTDOWN:
3917 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3918 DRV_STATE_UNLOAD_DONE);
3919 break;
3920
3921 default:
3922 break;
3923 };
3924 }
3925}
3926
3927/* tp->lock is held. */
3928static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3929{
3930 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3931 switch (kind) {
3932 case RESET_KIND_INIT:
3933 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3934 DRV_STATE_START);
3935 break;
3936
3937 case RESET_KIND_SHUTDOWN:
3938 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3939 DRV_STATE_UNLOAD);
3940 break;
3941
3942 case RESET_KIND_SUSPEND:
3943 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3944 DRV_STATE_SUSPEND);
3945 break;
3946
3947 default:
3948 break;
3949 };
3950 }
3951}
3952
3953static void tg3_stop_fw(struct tg3 *);
3954
3955/* tp->lock is held. */
3956static int tg3_chip_reset(struct tg3 *tp)
3957{
3958 u32 val;
3959 u32 flags_save;
3960 int i;
3961
3962 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3963 tg3_nvram_lock(tp);
3964
3965 /*
3966 * We must avoid the readl() that normally takes place.
3967 * It locks machines, causes machine checks, and other
3968 * fun things. So, temporarily disable the 5701
3969 * hardware workaround, while we do the reset.
3970 */
3971 flags_save = tp->tg3_flags;
3972 tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3973
3974 /* do the reset */
3975 val = GRC_MISC_CFG_CORECLK_RESET;
3976
3977 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3978 if (tr32(0x7e2c) == 0x60) {
3979 tw32(0x7e2c, 0x20);
3980 }
3981 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3982 tw32(GRC_MISC_CFG, (1 << 29));
3983 val |= (1 << 29);
3984 }
3985 }
3986
3987 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3988 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3989 tw32(GRC_MISC_CFG, val);
3990
3991 /* restore 5701 hardware bug workaround flag */
3992 tp->tg3_flags = flags_save;
3993
3994 /* Unfortunately, we have to delay before the PCI read back.
3995 * Some 575X chips even will not respond to a PCI cfg access
3996 * when the reset command is given to the chip.
3997 *
3998 * How do these hardware designers expect things to work
3999 * properly if the PCI write is posted for a long period
4000 * of time? It is always necessary to have some method by
4001 * which a register read back can occur to push the write
4002 * out which does the reset.
4003 *
4004 * For most tg3 variants the trick below was working.
4005 * Ho hum...
4006 */
4007 udelay(120);
4008
4009 /* Flush PCI posted writes. The normal MMIO registers
4010 * are inaccessible at this time so this is the only
4011 * way to make this reliably (actually, this is no longer
4012 * the case, see above). I tried to use indirect
4013 * register read/write but this upset some 5701 variants.
4014 */
4015 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4016
4017 udelay(120);
4018
4019 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4020 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4021 int i;
4022 u32 cfg_val;
4023
4024 /* Wait for link training to complete. */
4025 for (i = 0; i < 5000; i++)
4026 udelay(100);
4027
4028 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4029 pci_write_config_dword(tp->pdev, 0xc4,
4030 cfg_val | (1 << 15));
4031 }
4032 /* Set PCIE max payload size and clear error status. */
4033 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4034 }
4035
4036 /* Re-enable indirect register accesses. */
4037 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4038 tp->misc_host_ctrl);
4039
4040 /* Set MAX PCI retry to zero. */
4041 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4042 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4043 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4044 val |= PCISTATE_RETRY_SAME_DMA;
4045 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4046
4047 pci_restore_state(tp->pdev);
4048
4049 /* Make sure PCI-X relaxed ordering bit is clear. */
4050 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4051 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4052 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4053
4054 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4055
4056 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4057 tg3_stop_fw(tp);
4058 tw32(0x5000, 0x400);
4059 }
4060
4061 tw32(GRC_MODE, tp->grc_mode);
4062
4063 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4064 u32 val = tr32(0xc4);
4065
4066 tw32(0xc4, val | (1 << 15));
4067 }
4068
4069 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4071 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4072 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4073 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4074 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4075 }
4076
4077 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4078 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4079 tw32_f(MAC_MODE, tp->mac_mode);
4080 } else
4081 tw32_f(MAC_MODE, 0);
4082 udelay(40);
4083
4084 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4085 /* Wait for firmware initialization to complete. */
4086 for (i = 0; i < 100000; i++) {
4087 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4088 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4089 break;
4090 udelay(10);
4091 }
4092 if (i >= 100000) {
4093 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4094 "firmware will not restart magic=%08x\n",
4095 tp->dev->name, val);
4096 return -ENODEV;
4097 }
4098 }
4099
4100 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4101 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4102 u32 val = tr32(0x7c00);
4103
4104 tw32(0x7c00, val | (1 << 25));
4105 }
4106
4107 /* Reprobe ASF enable state. */
4108 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4109 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4110 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4111 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4112 u32 nic_cfg;
4113
4114 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4115 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4116 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4117 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4118 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4119 }
4120 }
4121
4122 return 0;
4123}
4124
4125/* tp->lock is held. */
4126static void tg3_stop_fw(struct tg3 *tp)
4127{
4128 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4129 u32 val;
4130 int i;
4131
4132 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4133 val = tr32(GRC_RX_CPU_EVENT);
4134 val |= (1 << 14);
4135 tw32(GRC_RX_CPU_EVENT, val);
4136
4137 /* Wait for RX cpu to ACK the event. */
4138 for (i = 0; i < 100; i++) {
4139 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4140 break;
4141 udelay(1);
4142 }
4143 }
4144}
4145
4146/* tp->lock is held. */
944d980e 4147static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 4148{
4149 int err;
4150
4151 tg3_stop_fw(tp);
4152
944d980e 4153 tg3_write_sig_pre_reset(tp, kind);
1da177e4 4154
b3b7d6be 4155 tg3_abort_hw(tp, silent);
1da177e4
LT		 4156 err = tg3_chip_reset(tp);
4157
944d980e
MC		 4158 tg3_write_sig_legacy(tp, kind);
4159 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 4160
4161 if (err)
4162 return err;
4163
4164 return 0;
4165}
4166
4167#define TG3_FW_RELEASE_MAJOR 0x0
4168#define TG3_FW_RELASE_MINOR 0x0
4169#define TG3_FW_RELEASE_FIX 0x0
4170#define TG3_FW_START_ADDR 0x08000000
4171#define TG3_FW_TEXT_ADDR 0x08000000
4172#define TG3_FW_TEXT_LEN 0x9c0
4173#define TG3_FW_RODATA_ADDR 0x080009c0
4174#define TG3_FW_RODATA_LEN 0x60
4175#define TG3_FW_DATA_ADDR 0x08000a40
4176#define TG3_FW_DATA_LEN 0x20
4177#define TG3_FW_SBSS_ADDR 0x08000a60
4178#define TG3_FW_SBSS_LEN 0xc
4179#define TG3_FW_BSS_ADDR 0x08000a70
4180#define TG3_FW_BSS_LEN 0x10
4181
4182static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4183 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4184 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4185 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4186 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4187 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4188 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4189 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4190 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4191 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4192 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4193 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4194 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4195 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4196 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4197 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4198 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4199 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4200 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4201 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4202 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4203 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4204 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4205 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4206 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4208 0, 0, 0, 0, 0, 0,
4209 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4210 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4211 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4212 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4213 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4214 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4215 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4216 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4217 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4218 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4219 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4223 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4224 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4225 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4226 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4227 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4228 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4229 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4230 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4231 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4232 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4233 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4234 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4235 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4236 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4237 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4238 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4239 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4240 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4241 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4242 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4243 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4244 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4245 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4246 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4247 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4248 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4249 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4250 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4251 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4252 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4253 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4254 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4255 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4256 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4257 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4258 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4259 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4260 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4261 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4262 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4263 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4264 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4265 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4266 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4267 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4268 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4269 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4270 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4271 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4272 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4273 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4274};
4275
4276static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4277 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4278 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4279 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4280 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4281 0x00000000
4282};
4283
4284#if 0 /* All zeros, don't eat up space with it. */
4285u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4286 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4287 0x00000000, 0x00000000, 0x00000000, 0x00000000
4288};
4289#endif
4290
4291#define RX_CPU_SCRATCH_BASE 0x30000
4292#define RX_CPU_SCRATCH_SIZE 0x04000
4293#define TX_CPU_SCRATCH_BASE 0x34000
4294#define TX_CPU_SCRATCH_SIZE 0x04000
4295
4296/* tp->lock is held. */
4297static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4298{
4299 int i;
4300
4301 if (offset == TX_CPU_BASE &&
4302 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4303 BUG();
4304
4305 if (offset == RX_CPU_BASE) {
4306 for (i = 0; i < 10000; i++) {
4307 tw32(offset + CPU_STATE, 0xffffffff);
4308 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4309 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4310 break;
4311 }
4312
4313 tw32(offset + CPU_STATE, 0xffffffff);
4314 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4315 udelay(10);
4316 } else {
4317 for (i = 0; i < 10000; i++) {
4318 tw32(offset + CPU_STATE, 0xffffffff);
4319 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4320 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4321 break;
4322 }
4323 }
4324
4325 if (i >= 10000) {
4326 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4327 "and %s CPU\n",
4328 tp->dev->name,
4329 (offset == RX_CPU_BASE ? "RX" : "TX"));
4330 return -ENODEV;
4331 }
4332 return 0;
4333}
4334
4335struct fw_info {
4336 unsigned int text_base;
4337 unsigned int text_len;
4338 u32 *text_data;
4339 unsigned int rodata_base;
4340 unsigned int rodata_len;
4341 u32 *rodata_data;
4342 unsigned int data_base;
4343 unsigned int data_len;
4344 u32 *data_data;
4345};
4346
4347/* tp->lock is held. */
4348static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4349 int cpu_scratch_size, struct fw_info *info)
4350{
4351 int err, i;
4352 u32 orig_tg3_flags = tp->tg3_flags;
4353 void (*write_op)(struct tg3 *, u32, u32);
4354
4355 if (cpu_base == TX_CPU_BASE &&
4356 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4357 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4358 "TX cpu firmware on %s which is 5705.\n",
4359 tp->dev->name);
4360 return -EINVAL;
4361 }
4362
4363 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4364 write_op = tg3_write_mem;
4365 else
4366 write_op = tg3_write_indirect_reg32;
4367
4368 /* Force use of PCI config space for indirect register
4369 * write calls.
4370 */
4371 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4372
4373 err = tg3_halt_cpu(tp, cpu_base);
4374 if (err)
4375 goto out;
4376
4377 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4378 write_op(tp, cpu_scratch_base + i, 0);
4379 tw32(cpu_base + CPU_STATE, 0xffffffff);
4380 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4381 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4382 write_op(tp, (cpu_scratch_base +
4383 (info->text_base & 0xffff) +
4384 (i * sizeof(u32))),
4385 (info->text_data ?
4386 info->text_data[i] : 0));
4387 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4388 write_op(tp, (cpu_scratch_base +
4389 (info->rodata_base & 0xffff) +
4390 (i * sizeof(u32))),
4391 (info->rodata_data ?
4392 info->rodata_data[i] : 0));
4393 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4394 write_op(tp, (cpu_scratch_base +
4395 (info->data_base & 0xffff) +
4396 (i * sizeof(u32))),
4397 (info->data_data ?
4398 info->data_data[i] : 0));
4399
4400 err = 0;
4401
4402out:
4403 tp->tg3_flags = orig_tg3_flags;
4404 return err;
4405}
4406
4407/* tp->lock is held. */
4408static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4409{
4410 struct fw_info info;
4411 int err, i;
4412
4413 info.text_base = TG3_FW_TEXT_ADDR;
4414 info.text_len = TG3_FW_TEXT_LEN;
4415 info.text_data = &tg3FwText[0];
4416 info.rodata_base = TG3_FW_RODATA_ADDR;
4417 info.rodata_len = TG3_FW_RODATA_LEN;
4418 info.rodata_data = &tg3FwRodata[0];
4419 info.data_base = TG3_FW_DATA_ADDR;
4420 info.data_len = TG3_FW_DATA_LEN;
4421 info.data_data = NULL;
4422
4423 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4424 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4425 &info);
4426 if (err)
4427 return err;
4428
4429 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4430 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4431 &info);
4432 if (err)
4433 return err;
4434
4435 /* Now startup only the RX cpu. */
4436 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4437 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4438
4439 for (i = 0; i < 5; i++) {
4440 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4441 break;
4442 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4443 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4444 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4445 udelay(1000);
4446 }
4447 if (i >= 5) {
4448 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4449 "to set RX CPU PC, is %08x should be %08x\n",
4450 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4451 TG3_FW_TEXT_ADDR);
4452 return -ENODEV;
4453 }
4454 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4455 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4456
4457 return 0;
4458}
4459
4460#if TG3_TSO_SUPPORT != 0
4461
4462#define TG3_TSO_FW_RELEASE_MAJOR 0x1
4463#define TG3_TSO_FW_RELASE_MINOR 0x6
4464#define TG3_TSO_FW_RELEASE_FIX 0x0
4465#define TG3_TSO_FW_START_ADDR 0x08000000
4466#define TG3_TSO_FW_TEXT_ADDR 0x08000000
4467#define TG3_TSO_FW_TEXT_LEN 0x1aa0
4468#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4469#define TG3_TSO_FW_RODATA_LEN 0x60
4470#define TG3_TSO_FW_DATA_ADDR 0x08001b20
4471#define TG3_TSO_FW_DATA_LEN 0x30
4472#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4473#define TG3_TSO_FW_SBSS_LEN 0x2c
4474#define TG3_TSO_FW_BSS_ADDR 0x08001b80
4475#define TG3_TSO_FW_BSS_LEN 0x894
4476
4477static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4478 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4479 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4480 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4481 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4482 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4483 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4484 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4485 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4486 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4487 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4488 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4489 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4490 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4491 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4492 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4493 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4494 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4495 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4496 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4497 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4498 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4499 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4500 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4501 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4502 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4503 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4504 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4505 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4506 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4507 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4508 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4509 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4510 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4511 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4512 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4513 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4514 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4515 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4516 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4517 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4518 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4519 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4520 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4521 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4522 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4523 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4524 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4525 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4526 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4527 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4528 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4529 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4530 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4531 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4532 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4533 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4534 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4535 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4536 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4537 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4538 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4539 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4540 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4541 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4542 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4543 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4544 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4545 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4546 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4547 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4548 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4549 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4550 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4551 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4552 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4553 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4554 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4555 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4556 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4557 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4558 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4559 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4560 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4561 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4562 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4563 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4564 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4565 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4566 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4567 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4568 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4569 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4570 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4571 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4572 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4573 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4574 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4575 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4576 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4577 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4578 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4579 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4580 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4581 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4582 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4583 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4584 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4585 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4586 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4587 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4588 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4589 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4590 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4591 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4592 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4593 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4594 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4595 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4596 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4597 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4598 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4599 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4600 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4601 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4602 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4603 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4604 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4605 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4606 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4607 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4608 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4609 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4610 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4611 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4612 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4613 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4614 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4615 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4616 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4617 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4618 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4619 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4620 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4621 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4622 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4623 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4624 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4625 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4626 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4627 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4628 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4629 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4630 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4631 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4632 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4633 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4634 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4635 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4636 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4637 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4638 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4639 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4640 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4641 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4642 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4643 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4644 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4645 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4646 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4647 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4648 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4649 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4650 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4651 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4652 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4653 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4654 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4655 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4656 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4657 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4658 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4659 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4660 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4661 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4662 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4663 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4664 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4665 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4666 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4667 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4668 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4669 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4670 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4671 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4672 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4673 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4674 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4675 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4676 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4677 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4678 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4679 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4680 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4681 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4682 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4683 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4684 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4685 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4686 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4687 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4688 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4689 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4690 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4691 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4692 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4693 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4694 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4695 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4696 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4697 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4698 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4699 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4700 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4701 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4702 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4703 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4704 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4705 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4706 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4707 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4708 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4709 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4710 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4711 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4712 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4713 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4714 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4715 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4716 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4717 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4718 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4719 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4720 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4721 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4722 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4723 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4724 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4725 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4726 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4727 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4728 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4729 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4730 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4731 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4732 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4733 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4734 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4735 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4736 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4737 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4738 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4739 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4740 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4741 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4742 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4743 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4744 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4745 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4746 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4747 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4748 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4749 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4750 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4751 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4752 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4753 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4754 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4755 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4756 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4757 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4758 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4759 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4760 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4761 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4762};
4763
4764static u32 tg3TsoFwRodata[] = {
4765 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4766 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4767 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4768 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4769 0x00000000,
4770};
4771
4772static u32 tg3TsoFwData[] = {
4773 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4774 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4775 0x00000000,
4776};
4777
4778/* 5705 needs a special version of the TSO firmware. */
4779#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
4780#define TG3_TSO5_FW_RELASE_MINOR 0x2
4781#define TG3_TSO5_FW_RELEASE_FIX 0x0
4782#define TG3_TSO5_FW_START_ADDR 0x00010000
4783#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
4784#define TG3_TSO5_FW_TEXT_LEN 0xe90
4785#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
4786#define TG3_TSO5_FW_RODATA_LEN 0x50
4787#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
4788#define TG3_TSO5_FW_DATA_LEN 0x20
4789#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
4790#define TG3_TSO5_FW_SBSS_LEN 0x28
4791#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
4792#define TG3_TSO5_FW_BSS_LEN 0x88
4793
4794static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4795 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4796 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4797 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4798 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4799 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4800 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4801 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4802 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4803 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4804 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4805 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4806 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4807 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4808 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4809 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4810 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4811 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4812 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4813 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4814 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4815 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4816 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4817 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4818 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4819 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4820 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4821 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4822 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4823 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4824 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4825 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4826 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4827 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4828 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4829 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4830 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4831 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4832 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4833 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4834 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4835 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4836 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4837 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4838 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4839 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4840 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4841 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4842 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4843 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4844 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4845 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4846 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4847 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4848 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4849 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4850 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4851 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4852 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4853 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4854 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4855 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4856 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4857 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4858 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4859 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4860 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4861 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4862 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4863 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4864 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4865 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4866 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4867 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4868 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4869 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4870 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4871 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4872 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4873 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4874 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4875 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4876 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4877 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4878 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4879 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4880 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4881 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4882 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4883 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4884 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4885 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4886 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4887 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4888 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4889 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4890 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4891 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4892 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4893 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4894 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4895 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4896 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4897 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4898 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4899 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4900 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4901 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4902 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4903 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4904 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4905 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4906 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4907 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4908 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4909 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4910 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4911 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4912 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4913 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4914 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4915 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4916 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4917 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4918 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4919 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4920 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4921 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4922 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4923 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4924 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4925 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4926 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4927 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4928 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4929 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4930 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4931 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4932 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4933 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4934 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4935 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4936 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4937 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4938 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4939 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4940 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4941 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4942 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4943 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4944 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4945 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4946 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4947 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4948 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4949 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4950 0x00000000, 0x00000000, 0x00000000,
4951};
4952
4953static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4954 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4955 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4956 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4957 0x00000000, 0x00000000, 0x00000000,
4958};
4959
4960static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4961 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4962 0x00000000, 0x00000000, 0x00000000,
4963};
4964
4965/* tp->lock is held. */
4966static int tg3_load_tso_firmware(struct tg3 *tp)
4967{
4968 struct fw_info info;
4969 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4970 int err, i;
4971
4972 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4973 return 0;
4974
4975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4976 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4977 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4978 info.text_data = &tg3Tso5FwText[0];
4979 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4980 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4981 info.rodata_data = &tg3Tso5FwRodata[0];
4982 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4983 info.data_len = TG3_TSO5_FW_DATA_LEN;
4984 info.data_data = &tg3Tso5FwData[0];
4985 cpu_base = RX_CPU_BASE;
4986 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4987 cpu_scratch_size = (info.text_len +
4988 info.rodata_len +
4989 info.data_len +
4990 TG3_TSO5_FW_SBSS_LEN +
4991 TG3_TSO5_FW_BSS_LEN);
4992 } else {
4993 info.text_base = TG3_TSO_FW_TEXT_ADDR;
4994 info.text_len = TG3_TSO_FW_TEXT_LEN;
4995 info.text_data = &tg3TsoFwText[0];
4996 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
4997 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
4998 info.rodata_data = &tg3TsoFwRodata[0];
4999 info.data_base = TG3_TSO_FW_DATA_ADDR;
5000 info.data_len = TG3_TSO_FW_DATA_LEN;
5001 info.data_data = &tg3TsoFwData[0];
5002 cpu_base = TX_CPU_BASE;
5003 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5004 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5005 }
5006
5007 err = tg3_load_firmware_cpu(tp, cpu_base,
5008 cpu_scratch_base, cpu_scratch_size,
5009 &info);
5010 if (err)
5011 return err;
5012
5013 /* Now startup the cpu. */
5014 tw32(cpu_base + CPU_STATE, 0xffffffff);
5015 tw32_f(cpu_base + CPU_PC, info.text_base);
5016
5017 for (i = 0; i < 5; i++) {
5018 if (tr32(cpu_base + CPU_PC) == info.text_base)
5019 break;
5020 tw32(cpu_base + CPU_STATE, 0xffffffff);
5021 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5022 tw32_f(cpu_base + CPU_PC, info.text_base);
5023 udelay(1000);
5024 }
5025 if (i >= 5) {
5026 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5027 "to set CPU PC, is %08x should be %08x\n",
5028 tp->dev->name, tr32(cpu_base + CPU_PC),
5029 info.text_base);
5030 return -ENODEV;
5031 }
5032 tw32(cpu_base + CPU_STATE, 0xffffffff);
5033 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5034 return 0;
5035}
5036
5037#endif /* TG3_TSO_SUPPORT != 0 */
5038
5039/* tp->lock is held. */
5040static void __tg3_set_mac_addr(struct tg3 *tp)
5041{
5042 u32 addr_high, addr_low;
5043 int i;
5044
5045 addr_high = ((tp->dev->dev_addr[0] << 8) |
5046 tp->dev->dev_addr[1]);
5047 addr_low = ((tp->dev->dev_addr[2] << 24) |
5048 (tp->dev->dev_addr[3] << 16) |
5049 (tp->dev->dev_addr[4] << 8) |
5050 (tp->dev->dev_addr[5] << 0));
5051 for (i = 0; i < 4; i++) {
5052 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5053 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5054 }
5055
5056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5058 for (i = 0; i < 12; i++) {
5059 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5060 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5061 }
5062 }
5063
5064 addr_high = (tp->dev->dev_addr[0] +
5065 tp->dev->dev_addr[1] +
5066 tp->dev->dev_addr[2] +
5067 tp->dev->dev_addr[3] +
5068 tp->dev->dev_addr[4] +
5069 tp->dev->dev_addr[5]) &
5070 TX_BACKOFF_SEED_MASK;
5071 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5072}
5073
5074static int tg3_set_mac_addr(struct net_device *dev, void *p)
5075{
5076 struct tg3 *tp = netdev_priv(dev);
5077 struct sockaddr *addr = p;
5078
5079 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5080
5081 spin_lock_irq(&tp->lock);
5082 __tg3_set_mac_addr(tp);
5083 spin_unlock_irq(&tp->lock);
5084
5085 return 0;
5086}
5087
5088/* tp->lock is held. */
5089static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5090 dma_addr_t mapping, u32 maxlen_flags,
5091 u32 nic_addr)
5092{
5093 tg3_write_mem(tp,
5094 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5095 ((u64) mapping >> 32));
5096 tg3_write_mem(tp,
5097 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5098 ((u64) mapping & 0xffffffff));
5099 tg3_write_mem(tp,
5100 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5101 maxlen_flags);
5102
5103 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5104 tg3_write_mem(tp,
5105 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5106 nic_addr);
5107}
5108
5109static void __tg3_set_rx_mode(struct net_device *);
15f9850d
DM		 5110static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5111{
5112 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5113 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5114 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5115 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5116 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5117 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5118 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5119 }
5120 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5121 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5122 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5123 u32 val = ec->stats_block_coalesce_usecs;
5124
5125 if (!netif_carrier_ok(tp->dev))
5126 val = 0;
5127
5128 tw32(HOSTCC_STAT_COAL_TICKS, val);
5129 }
5130}
1da177e4
LT		 5131
5132/* tp->lock is held. */
5133static int tg3_reset_hw(struct tg3 *tp)
5134{
5135 u32 val, rdmac_mode;
5136 int i, err, limit;
5137
5138 tg3_disable_ints(tp);
5139
5140 tg3_stop_fw(tp);
5141
5142 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5143
5144 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 5145 tg3_abort_hw(tp, 1);
1da177e4
LT		 5146 }
5147
5148 err = tg3_chip_reset(tp);
5149 if (err)
5150 return err;
5151
5152 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5153
5154 /* This works around an issue with Athlon chipsets on
5155 * B3 tigon3 silicon. This bit has no effect on any
5156 * other revision. But do not set this on PCI Express
5157 * chips.
5158 */
5159 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5160 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5161 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5162
5163 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5164 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5165 val = tr32(TG3PCI_PCISTATE);
5166 val |= PCISTATE_RETRY_SAME_DMA;
5167 tw32(TG3PCI_PCISTATE, val);
5168 }
5169
5170 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5171 /* Enable some hw fixes. */
5172 val = tr32(TG3PCI_MSI_DATA);
5173 val |= (1 << 26) | (1 << 28) | (1 << 29);
5174 tw32(TG3PCI_MSI_DATA, val);
5175 }
5176
5177 /* Descriptor ring init may make accesses to the
5178 * NIC SRAM area to setup the TX descriptors, so we
5179 * can only do this after the hardware has been
5180 * successfully reset.
5181 */
5182 tg3_init_rings(tp);
5183
5184 /* This value is determined during the probe time DMA
5185 * engine test, tg3_test_dma.
5186 */
5187 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5188
5189 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5190 GRC_MODE_4X_NIC_SEND_RINGS |
5191 GRC_MODE_NO_TX_PHDR_CSUM |
5192 GRC_MODE_NO_RX_PHDR_CSUM);
5193 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5194 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5195 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5196 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5197 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5198
5199 tw32(GRC_MODE,
5200 tp->grc_mode |
5201 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5202
5203 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5204 val = tr32(GRC_MISC_CFG);
5205 val &= ~0xff;
5206 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5207 tw32(GRC_MISC_CFG, val);
5208
5209 /* Initialize MBUF/DESC pool. */
cbf46853 5210 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 5211 /* Do nothing. */
5212 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5213 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5214 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5215 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5216 else
5217 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5218 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5219 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5220 }
5221#if TG3_TSO_SUPPORT != 0
5222 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5223 int fw_len;
5224
5225 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5226 TG3_TSO5_FW_RODATA_LEN +
5227 TG3_TSO5_FW_DATA_LEN +
5228 TG3_TSO5_FW_SBSS_LEN +
5229 TG3_TSO5_FW_BSS_LEN);
5230 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5231 tw32(BUFMGR_MB_POOL_ADDR,
5232 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5233 tw32(BUFMGR_MB_POOL_SIZE,
5234 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5235 }
5236#endif
5237
5238 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5239 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5240 tp->bufmgr_config.mbuf_read_dma_low_water);
5241 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5242 tp->bufmgr_config.mbuf_mac_rx_low_water);
5243 tw32(BUFMGR_MB_HIGH_WATER,
5244 tp->bufmgr_config.mbuf_high_water);
5245 } else {
5246 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5247 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5248 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5249 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5250 tw32(BUFMGR_MB_HIGH_WATER,
5251 tp->bufmgr_config.mbuf_high_water_jumbo);
5252 }
5253 tw32(BUFMGR_DMA_LOW_WATER,
5254 tp->bufmgr_config.dma_low_water);
5255 tw32(BUFMGR_DMA_HIGH_WATER,
5256 tp->bufmgr_config.dma_high_water);
5257
5258 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5259 for (i = 0; i < 2000; i++) {
5260 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5261 break;
5262 udelay(10);
5263 }
5264 if (i >= 2000) {
5265 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5266 tp->dev->name);
5267 return -ENODEV;
5268 }
5269
5270 /* Setup replenish threshold. */
5271 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5272
5273 /* Initialize TG3_BDINFO's at:
5274 * RCVDBDI_STD_BD: standard eth size rx ring
5275 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5276 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5277 *
5278 * like so:
5279 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5280 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5281 * ring attribute flags
5282 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5283 *
5284 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5285 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5286 *
5287 * The size of each ring is fixed in the firmware, but the location is
5288 * configurable.
5289 */
5290 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5291 ((u64) tp->rx_std_mapping >> 32));
5292 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5293 ((u64) tp->rx_std_mapping & 0xffffffff));
5294 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5295 NIC_SRAM_RX_BUFFER_DESC);
5296
5297 /* Don't even try to program the JUMBO/MINI buffer descriptor
5298 * configs on 5705.
5299 */
5300 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5301 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5302 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5303 } else {
5304 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5305 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5306
5307 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5308 BDINFO_FLAGS_DISABLED);
5309
5310 /* Setup replenish threshold. */
5311 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5312
5313 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5314 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5315 ((u64) tp->rx_jumbo_mapping >> 32));
5316 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5317 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5318 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5319 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5320 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5321 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5322 } else {
5323 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5324 BDINFO_FLAGS_DISABLED);
5325 }
5326
5327 }
5328
5329 /* There is only one send ring on 5705/5750, no need to explicitly
5330 * disable the others.
5331 */
5332 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5333 /* Clear out send RCB ring in SRAM. */
5334 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5335 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5336 BDINFO_FLAGS_DISABLED);
5337 }
5338
5339 tp->tx_prod = 0;
5340 tp->tx_cons = 0;
5341 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5342 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5343
5344 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5345 tp->tx_desc_mapping,
5346 (TG3_TX_RING_SIZE <<
5347 BDINFO_FLAGS_MAXLEN_SHIFT),
5348 NIC_SRAM_TX_BUFFER_DESC);
5349
5350 /* There is only one receive return ring on 5705/5750, no need
5351 * to explicitly disable the others.
5352 */
5353 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5354 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5355 i += TG3_BDINFO_SIZE) {
5356 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5357 BDINFO_FLAGS_DISABLED);
5358 }
5359 }
5360
5361 tp->rx_rcb_ptr = 0;
5362 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5363
5364 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5365 tp->rx_rcb_mapping,
5366 (TG3_RX_RCB_RING_SIZE(tp) <<
5367 BDINFO_FLAGS_MAXLEN_SHIFT),
5368 0);
5369
5370 tp->rx_std_ptr = tp->rx_pending;
5371 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5372 tp->rx_std_ptr);
5373
5374 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5375 tp->rx_jumbo_pending : 0;
5376 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5377 tp->rx_jumbo_ptr);
5378
5379 /* Initialize MAC address and backoff seed. */
5380 __tg3_set_mac_addr(tp);
5381
5382 /* MTU + ethernet header + FCS + optional VLAN tag */
5383 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5384
5385 /* The slot time is changed by tg3_setup_phy if we
5386 * run at gigabit with half duplex.
5387 */
5388 tw32(MAC_TX_LENGTHS,
5389 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5390 (6 << TX_LENGTHS_IPG_SHIFT) |
5391 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5392
5393 /* Receive rules. */
5394 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5395 tw32(RCVLPC_CONFIG, 0x0181);
5396
5397 /* Calculate RDMAC_MODE setting early, we need it to determine
5398 * the RCVLPC_STATE_ENABLE mask.
5399 */
5400 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5401 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5402 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5403 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5404 RDMAC_MODE_LNGREAD_ENAB);
5405 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5406 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 5407
5408 /* If statement applies to 5705 and 5750 PCI devices only */
5409 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5410 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5411 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 5412 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5413 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5414 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5415 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5416 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5417 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5418 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5419 }
5420 }
5421
85e94ced
MC		 5422 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5423 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5424
1da177e4
LT		 5425#if TG3_TSO_SUPPORT != 0
5426 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5427 rdmac_mode |= (1 << 27);
5428#endif
5429
5430 /* Receive/send statistics. */
5431 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5432 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5433 val = tr32(RCVLPC_STATS_ENABLE);
5434 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5435 tw32(RCVLPC_STATS_ENABLE, val);
5436 } else {
5437 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5438 }
5439 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5440 tw32(SNDDATAI_STATSENAB, 0xffffff);
5441 tw32(SNDDATAI_STATSCTRL,
5442 (SNDDATAI_SCTRL_ENABLE |
5443 SNDDATAI_SCTRL_FASTUPD));
5444
5445 /* Setup host coalescing engine. */
5446 tw32(HOSTCC_MODE, 0);
5447 for (i = 0; i < 2000; i++) {
5448 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5449 break;
5450 udelay(10);
5451 }
5452
15f9850d 5453 tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 5454
5455 /* set status block DMA address */
5456 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5457 ((u64) tp->status_mapping >> 32));
5458 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5459 ((u64) tp->status_mapping & 0xffffffff));
5460
5461 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5462 /* Status/statistics block address. See tg3_timer,
5463 * the tg3_periodic_fetch_stats call there, and
5464 * tg3_get_stats to see how this works for 5705/5750 chips.
5465 */
1da177e4
LT		 5466 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5467 ((u64) tp->stats_mapping >> 32));
5468 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5469 ((u64) tp->stats_mapping & 0xffffffff));
5470 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5471 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5472 }
5473
5474 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5475
5476 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5477 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5478 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5479 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5480
5481 /* Clear statistics/status block in chip, and status block in ram. */
5482 for (i = NIC_SRAM_STATS_BLK;
5483 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5484 i += sizeof(u32)) {
5485 tg3_write_mem(tp, i, 0);
5486 udelay(40);
5487 }
5488 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5489
5490 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5491 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5492 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5493 udelay(40);
5494
314fba34
MC		 5495 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5496 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5497 * register to preserve the GPIO settings for LOMs. The GPIOs,
5498 * whether used as inputs or outputs, are set by boot code after
5499 * reset.
5500 */
5501 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5502 u32 gpio_mask;
5503
5504 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5505 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 5506
5507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5508 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5509 GRC_LCLCTRL_GPIO_OUTPUT3;
5510
314fba34
MC		 5511 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5512
5513 /* GPIO1 must be driven high for eeprom write protect */
1da177e4
LT		 5514 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5515 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 5516 }
1da177e4
LT		 5517 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5518 udelay(100);
5519
5520 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e
DM		 5521 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5522 tp->last_tag = 0;
1da177e4
LT		 5523
5524 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5525 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5526 udelay(40);
5527 }
5528
5529 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5530 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5531 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5532 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5533 WDMAC_MODE_LNGREAD_ENAB);
5534
85e94ced
MC		 5535 /* If statement applies to 5705 and 5750 PCI devices only */
5536 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5537 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5538 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 5539 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5540 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5541 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5542 /* nothing */
5543 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5544 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5545 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5546 val |= WDMAC_MODE_RX_ACCEL;
5547 }
5548 }
5549
5550 tw32_f(WDMAC_MODE, val);
5551 udelay(40);
5552
5553 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5554 val = tr32(TG3PCI_X_CAPS);
5555 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5556 val &= ~PCIX_CAPS_BURST_MASK;
5557 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5558 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5559 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5560 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5561 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5562 val |= (tp->split_mode_max_reqs <<
5563 PCIX_CAPS_SPLIT_SHIFT);
5564 }
5565 tw32(TG3PCI_X_CAPS, val);
5566 }
5567
5568 tw32_f(RDMAC_MODE, rdmac_mode);
5569 udelay(40);
5570
5571 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5572 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5573 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5574 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5575 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5576 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5577 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5578 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5579#if TG3_TSO_SUPPORT != 0
5580 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5581 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5582#endif
5583 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5584 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5585
5586 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5587 err = tg3_load_5701_a0_firmware_fix(tp);
5588 if (err)
5589 return err;
5590 }
5591
5592#if TG3_TSO_SUPPORT != 0
5593 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5594 err = tg3_load_tso_firmware(tp);
5595 if (err)
5596 return err;
5597 }
5598#endif
5599
5600 tp->tx_mode = TX_MODE_ENABLE;
5601 tw32_f(MAC_TX_MODE, tp->tx_mode);
5602 udelay(100);
5603
5604 tp->rx_mode = RX_MODE_ENABLE;
5605 tw32_f(MAC_RX_MODE, tp->rx_mode);
5606 udelay(10);
5607
5608 if (tp->link_config.phy_is_low_power) {
5609 tp->link_config.phy_is_low_power = 0;
5610 tp->link_config.speed = tp->link_config.orig_speed;
5611 tp->link_config.duplex = tp->link_config.orig_duplex;
5612 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5613 }
5614
5615 tp->mi_mode = MAC_MI_MODE_BASE;
5616 tw32_f(MAC_MI_MODE, tp->mi_mode);
5617 udelay(80);
5618
5619 tw32(MAC_LED_CTRL, tp->led_ctrl);
5620
5621 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5622 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5623 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5624 udelay(10);
5625 }
5626 tw32_f(MAC_RX_MODE, tp->rx_mode);
5627 udelay(10);
5628
5629 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5630 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5631 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5632 /* Set drive transmission level to 1.2V */
5633 /* only if the signal pre-emphasis bit is not set */
5634 val = tr32(MAC_SERDES_CFG);
5635 val &= 0xfffff000;
5636 val |= 0x880;
5637 tw32(MAC_SERDES_CFG, val);
5638 }
5639 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5640 tw32(MAC_SERDES_CFG, 0x616000);
5641 }
5642
5643 /* Prevent chip from dropping frames when flow control
5644 * is enabled.
5645 */
5646 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5647
5648 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5649 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5650 /* Use hardware link auto-negotiation */
5651 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5652 }
5653
5654 err = tg3_setup_phy(tp, 1);
5655 if (err)
5656 return err;
5657
5658 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5659 u32 tmp;
5660
5661 /* Clear CRC stats. */
5662 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5663 tg3_writephy(tp, 0x1e, tmp | 0x8000);
5664 tg3_readphy(tp, 0x14, &tmp);
5665 }
5666 }
5667
5668 __tg3_set_rx_mode(tp->dev);
5669
5670 /* Initialize receive rules. */
5671 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
5672 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5673 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
5674 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5675
5676 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5677 limit = 8;
5678 else
5679 limit = 16;
5680 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5681 limit -= 4;
5682 switch (limit) {
5683 case 16:
5684 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
5685 case 15:
5686 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
5687 case 14:
5688 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
5689 case 13:
5690 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
5691 case 12:
5692 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
5693 case 11:
5694 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
5695 case 10:
5696 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
5697 case 9:
5698 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
5699 case 8:
5700 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
5701 case 7:
5702 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
5703 case 6:
5704 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
5705 case 5:
5706 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
5707 case 4:
5708 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
5709 case 3:
5710 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
5711 case 2:
5712 case 1:
5713
5714 default:
5715 break;
5716 };
5717
5718 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5719
5720 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5721 tg3_enable_ints(tp);
5722
5723 return 0;
5724}
5725
5726/* Called at device open time to get the chip ready for
5727 * packet processing. Invoked with tp->lock held.
5728 */
5729static int tg3_init_hw(struct tg3 *tp)
5730{
5731 int err;
5732
5733 /* Force the chip into D0. */
5734 err = tg3_set_power_state(tp, 0);
5735 if (err)
5736 goto out;
5737
5738 tg3_switch_clocks(tp);
5739
5740 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5741
5742 err = tg3_reset_hw(tp);
5743
5744out:
5745 return err;
5746}
5747
5748#define TG3_STAT_ADD32(PSTAT, REG) \
5749do { u32 __val = tr32(REG); \
5750 (PSTAT)->low += __val; \
5751 if ((PSTAT)->low < __val) \
5752 (PSTAT)->high += 1; \
5753} while (0)
5754
5755static void tg3_periodic_fetch_stats(struct tg3 *tp)
5756{
5757 struct tg3_hw_stats *sp = tp->hw_stats;
5758
5759 if (!netif_carrier_ok(tp->dev))
5760 return;
5761
5762 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5763 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5764 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5765 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5766 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5767 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5768 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5769 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5770 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5771 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5772 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5773 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5774 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5775
5776 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5777 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5778 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5779 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5780 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5781 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5782 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5783 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5784 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5785 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5786 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5787 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5788 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5789 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5790}
5791
5792static void tg3_timer(unsigned long __opaque)
5793{
5794 struct tg3 *tp = (struct tg3 *) __opaque;
5795 unsigned long flags;
5796
5797 spin_lock_irqsave(&tp->lock, flags);
5798 spin_lock(&tp->tx_lock);
5799
fac9b83e
DM		 5800 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
5801 /* All of this garbage is because when using non-tagged
5802 * IRQ status the mailbox/status_block protocol the chip
5803 * uses with the cpu is race prone.
5804 */
5805 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5806 tw32(GRC_LOCAL_CTRL,
5807 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5808 } else {
5809 tw32(HOSTCC_MODE, tp->coalesce_mode |
5810 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5811 }
1da177e4 5812
fac9b83e
DM		 5813 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5814 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5815 spin_unlock(&tp->tx_lock);
5816 spin_unlock_irqrestore(&tp->lock, flags);
5817 schedule_work(&tp->reset_task);
5818 return;
5819 }
1da177e4
LT		 5820 }
5821
1da177e4
LT		 5822 /* This part only runs once per second. */
5823 if (!--tp->timer_counter) {
fac9b83e
DM		 5824 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5825 tg3_periodic_fetch_stats(tp);
5826
1da177e4
LT		 5827 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5828 u32 mac_stat;
5829 int phy_event;
5830
5831 mac_stat = tr32(MAC_STATUS);
5832
5833 phy_event = 0;
5834 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5835 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5836 phy_event = 1;
5837 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5838 phy_event = 1;
5839
5840 if (phy_event)
5841 tg3_setup_phy(tp, 0);
5842 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5843 u32 mac_stat = tr32(MAC_STATUS);
5844 int need_setup = 0;
5845
5846 if (netif_carrier_ok(tp->dev) &&
5847 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5848 need_setup = 1;
5849 }
5850 if (! netif_carrier_ok(tp->dev) &&
5851 (mac_stat & (MAC_STATUS_PCS_SYNCED |
5852 MAC_STATUS_SIGNAL_DET))) {
5853 need_setup = 1;
5854 }
5855 if (need_setup) {
5856 tw32_f(MAC_MODE,
5857 (tp->mac_mode &
5858 ~MAC_MODE_PORT_MODE_MASK));
5859 udelay(40);
5860 tw32_f(MAC_MODE, tp->mac_mode);
5861 udelay(40);
5862 tg3_setup_phy(tp, 0);
5863 }
5864 }
5865
5866 tp->timer_counter = tp->timer_multiplier;
5867 }
5868
5869 /* Heartbeat is only sent once every 120 seconds. */
5870 if (!--tp->asf_counter) {
5871 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5872 u32 val;
5873
5874 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5875 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5876 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5877 val = tr32(GRC_RX_CPU_EVENT);
5878 val |= (1 << 14);
5879 tw32(GRC_RX_CPU_EVENT, val);
5880 }
5881 tp->asf_counter = tp->asf_multiplier;
5882 }
5883
5884 spin_unlock(&tp->tx_lock);
5885 spin_unlock_irqrestore(&tp->lock, flags);
5886
5887 tp->timer.expires = jiffies + tp->timer_offset;
5888 add_timer(&tp->timer);
5889}
5890
7938109f
MC		 5891static int tg3_test_interrupt(struct tg3 *tp)
5892{
5893 struct net_device *dev = tp->dev;
5894 int err, i;
5895 u32 int_mbox = 0;
5896
5897 tg3_disable_ints(tp);
5898
5899 free_irq(tp->pdev->irq, dev);
5900
5901 err = request_irq(tp->pdev->irq, tg3_test_isr,
f4d0ee98 5902 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 5903 if (err)
5904 return err;
5905
5906 tg3_enable_ints(tp);
5907
5908 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
5909 HOSTCC_MODE_NOW);
5910
5911 for (i = 0; i < 5; i++) {
5912 int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5913 if (int_mbox != 0)
5914 break;
5915 msleep(10);
5916 }
5917
5918 tg3_disable_ints(tp);
5919
5920 free_irq(tp->pdev->irq, dev);
5921
5922 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5923 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 5924 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 5925 else {
5926 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5927 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5928 fn = tg3_interrupt_tagged;
5929 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 5930 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 5931 }
7938109f
MC		 5932
5933 if (err)
5934 return err;
5935
5936 if (int_mbox != 0)
5937 return 0;
5938
5939 return -EIO;
5940}
5941
5942/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5943 * successfully restored
5944 */
5945static int tg3_test_msi(struct tg3 *tp)
5946{
5947 struct net_device *dev = tp->dev;
5948 int err;
5949 u16 pci_cmd;
5950
5951 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
5952 return 0;
5953
5954 /* Turn off SERR reporting in case MSI terminates with Master
5955 * Abort.
5956 */
5957 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
5958 pci_write_config_word(tp->pdev, PCI_COMMAND,
5959 pci_cmd & ~PCI_COMMAND_SERR);
5960
5961 err = tg3_test_interrupt(tp);
5962
5963 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
5964
5965 if (!err)
5966 return 0;
5967
5968 /* other failures */
5969 if (err != -EIO)
5970 return err;
5971
5972 /* MSI test failed, go back to INTx mode */
5973 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
5974 "switching to INTx mode. Please report this failure to "
5975 "the PCI maintainer and include system chipset information.\n",
5976 tp->dev->name);
5977
5978 free_irq(tp->pdev->irq, dev);
5979 pci_disable_msi(tp->pdev);
5980
5981 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5982
fac9b83e
DM		 5983 {
5984 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5985 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5986 fn = tg3_interrupt_tagged;
7938109f 5987
fac9b83e
DM		 5988 err = request_irq(tp->pdev->irq, fn,
5989 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5990 }
7938109f
MC		 5991 if (err)
5992 return err;
5993
5994 /* Need to reset the chip because the MSI cycle may have terminated
5995 * with Master Abort.
5996 */
5997 spin_lock_irq(&tp->lock);
5998 spin_lock(&tp->tx_lock);
5999
944d980e 6000 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6001 err = tg3_init_hw(tp);
6002
6003 spin_unlock(&tp->tx_lock);
6004 spin_unlock_irq(&tp->lock);
6005
6006 if (err)
6007 free_irq(tp->pdev->irq, dev);
6008
6009 return err;
6010}
6011
1da177e4
LT		 6012static int tg3_open(struct net_device *dev)
6013{
6014 struct tg3 *tp = netdev_priv(dev);
6015 int err;
6016
6017 spin_lock_irq(&tp->lock);
6018 spin_lock(&tp->tx_lock);
6019
6020 tg3_disable_ints(tp);
6021 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6022
6023 spin_unlock(&tp->tx_lock);
6024 spin_unlock_irq(&tp->lock);
6025
6026 /* The placement of this call is tied
6027 * to the setup and use of Host TX descriptors.
6028 */
6029 err = tg3_alloc_consistent(tp);
6030 if (err)
6031 return err;
6032
88b06bc2
MC		 6033 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6034 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6035 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
fac9b83e
DM		 6036 /* All MSI supporting chips should support tagged
6037 * status. Assert that this is the case.
6038 */
6039 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6040 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6041 "Not using MSI.\n", tp->dev->name);
6042 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 6043 u32 msi_mode;
6044
6045 msi_mode = tr32(MSGINT_MODE);
6046 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6047 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6048 }
6049 }
6050 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6051 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6052 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6053 else {
6054 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6055 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6056 fn = tg3_interrupt_tagged;
6057
6058 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6059 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6060 }
1da177e4
LT		 6061
6062 if (err) {
88b06bc2
MC		 6063 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6064 pci_disable_msi(tp->pdev);
6065 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6066 }
1da177e4
LT		 6067 tg3_free_consistent(tp);
6068 return err;
6069 }
6070
6071 spin_lock_irq(&tp->lock);
6072 spin_lock(&tp->tx_lock);
6073
6074 err = tg3_init_hw(tp);
6075 if (err) {
944d980e 6076 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6077 tg3_free_rings(tp);
6078 } else {
fac9b83e
DM		 6079 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6080 tp->timer_offset = HZ;
6081 else
6082 tp->timer_offset = HZ / 10;
6083
6084 BUG_ON(tp->timer_offset > HZ);
6085 tp->timer_counter = tp->timer_multiplier =
6086 (HZ / tp->timer_offset);
6087 tp->asf_counter = tp->asf_multiplier =
6088 ((HZ / tp->timer_offset) * 120);
1da177e4
LT		 6089
6090 init_timer(&tp->timer);
6091 tp->timer.expires = jiffies + tp->timer_offset;
6092 tp->timer.data = (unsigned long) tp;
6093 tp->timer.function = tg3_timer;
1da177e4
LT		 6094 }
6095
6096 spin_unlock(&tp->tx_lock);
6097 spin_unlock_irq(&tp->lock);
6098
6099 if (err) {
88b06bc2
MC		 6100 free_irq(tp->pdev->irq, dev);
6101 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6102 pci_disable_msi(tp->pdev);
6103 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6104 }
1da177e4
LT		 6105 tg3_free_consistent(tp);
6106 return err;
6107 }
6108
7938109f
MC		 6109 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6110 err = tg3_test_msi(tp);
fac9b83e 6111
7938109f
MC		 6112 if (err) {
6113 spin_lock_irq(&tp->lock);
6114 spin_lock(&tp->tx_lock);
6115
6116 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6117 pci_disable_msi(tp->pdev);
6118 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6119 }
944d980e 6120 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6121 tg3_free_rings(tp);
6122 tg3_free_consistent(tp);
6123
6124 spin_unlock(&tp->tx_lock);
6125 spin_unlock_irq(&tp->lock);
6126
6127 return err;
6128 }
6129 }
6130
1da177e4
LT		 6131 spin_lock_irq(&tp->lock);
6132 spin_lock(&tp->tx_lock);
6133
7938109f
MC		 6134 add_timer(&tp->timer);
6135 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 6136 tg3_enable_ints(tp);
6137
6138 spin_unlock(&tp->tx_lock);
6139 spin_unlock_irq(&tp->lock);
6140
6141 netif_start_queue(dev);
6142
6143 return 0;
6144}
6145
6146#if 0
6147/*static*/ void tg3_dump_state(struct tg3 *tp)
6148{
6149 u32 val32, val32_2, val32_3, val32_4, val32_5;
6150 u16 val16;
6151 int i;
6152
6153 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6154 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6155 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6156 val16, val32);
6157
6158 /* MAC block */
6159 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6160 tr32(MAC_MODE), tr32(MAC_STATUS));
6161 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6162 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6163 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6164 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6165 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6166 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6167
6168 /* Send data initiator control block */
6169 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6170 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6171 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6172 tr32(SNDDATAI_STATSCTRL));
6173
6174 /* Send data completion control block */
6175 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6176
6177 /* Send BD ring selector block */
6178 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6179 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6180
6181 /* Send BD initiator control block */
6182 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6183 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6184
6185 /* Send BD completion control block */
6186 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6187
6188 /* Receive list placement control block */
6189 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6190 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6191 printk(" RCVLPC_STATSCTRL[%08x]\n",
6192 tr32(RCVLPC_STATSCTRL));
6193
6194 /* Receive data and receive BD initiator control block */
6195 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6196 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6197
6198 /* Receive data completion control block */
6199 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6200 tr32(RCVDCC_MODE));
6201
6202 /* Receive BD initiator control block */
6203 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6204 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6205
6206 /* Receive BD completion control block */
6207 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6208 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6209
6210 /* Receive list selector control block */
6211 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6212 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6213
6214 /* Mbuf cluster free block */
6215 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6216 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6217
6218 /* Host coalescing control block */
6219 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6220 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6221 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6222 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6223 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6224 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6225 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6226 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6227 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6228 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6229 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6230 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6231
6232 /* Memory arbiter control block */
6233 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6234 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6235
6236 /* Buffer manager control block */
6237 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6238 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6239 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6240 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6241 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6242 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6243 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6244 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6245
6246 /* Read DMA control block */
6247 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6248 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6249
6250 /* Write DMA control block */
6251 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6252 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6253
6254 /* DMA completion block */
6255 printk("DEBUG: DMAC_MODE[%08x]\n",
6256 tr32(DMAC_MODE));
6257
6258 /* GRC block */
6259 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6260 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6261 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6262 tr32(GRC_LOCAL_CTRL));
6263
6264 /* TG3_BDINFOs */
6265 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6266 tr32(RCVDBDI_JUMBO_BD + 0x0),
6267 tr32(RCVDBDI_JUMBO_BD + 0x4),
6268 tr32(RCVDBDI_JUMBO_BD + 0x8),
6269 tr32(RCVDBDI_JUMBO_BD + 0xc));
6270 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6271 tr32(RCVDBDI_STD_BD + 0x0),
6272 tr32(RCVDBDI_STD_BD + 0x4),
6273 tr32(RCVDBDI_STD_BD + 0x8),
6274 tr32(RCVDBDI_STD_BD + 0xc));
6275 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6276 tr32(RCVDBDI_MINI_BD + 0x0),
6277 tr32(RCVDBDI_MINI_BD + 0x4),
6278 tr32(RCVDBDI_MINI_BD + 0x8),
6279 tr32(RCVDBDI_MINI_BD + 0xc));
6280
6281 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6282 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6283 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6284 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6285 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6286 val32, val32_2, val32_3, val32_4);
6287
6288 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6289 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6290 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6291 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6292 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6293 val32, val32_2, val32_3, val32_4);
6294
6295 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6296 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6297 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6298 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6299 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6300 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6301 val32, val32_2, val32_3, val32_4, val32_5);
6302
6303 /* SW status block */
6304 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6305 tp->hw_status->status,
6306 tp->hw_status->status_tag,
6307 tp->hw_status->rx_jumbo_consumer,
6308 tp->hw_status->rx_consumer,
6309 tp->hw_status->rx_mini_consumer,
6310 tp->hw_status->idx[0].rx_producer,
6311 tp->hw_status->idx[0].tx_consumer);
6312
6313 /* SW statistics block */
6314 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6315 ((u32 *)tp->hw_stats)[0],
6316 ((u32 *)tp->hw_stats)[1],
6317 ((u32 *)tp->hw_stats)[2],
6318 ((u32 *)tp->hw_stats)[3]);
6319
6320 /* Mailboxes */
6321 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6322 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6323 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6324 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6325 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6326
6327 /* NIC side send descriptors. */
6328 for (i = 0; i < 6; i++) {
6329 unsigned long txd;
6330
6331 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6332 + (i * sizeof(struct tg3_tx_buffer_desc));
6333 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6334 i,
6335 readl(txd + 0x0), readl(txd + 0x4),
6336 readl(txd + 0x8), readl(txd + 0xc));
6337 }
6338
6339 /* NIC side RX descriptors. */
6340 for (i = 0; i < 6; i++) {
6341 unsigned long rxd;
6342
6343 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6344 + (i * sizeof(struct tg3_rx_buffer_desc));
6345 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6346 i,
6347 readl(rxd + 0x0), readl(rxd + 0x4),
6348 readl(rxd + 0x8), readl(rxd + 0xc));
6349 rxd += (4 * sizeof(u32));
6350 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6351 i,
6352 readl(rxd + 0x0), readl(rxd + 0x4),
6353 readl(rxd + 0x8), readl(rxd + 0xc));
6354 }
6355
6356 for (i = 0; i < 6; i++) {
6357 unsigned long rxd;
6358
6359 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6360 + (i * sizeof(struct tg3_rx_buffer_desc));
6361 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6362 i,
6363 readl(rxd + 0x0), readl(rxd + 0x4),
6364 readl(rxd + 0x8), readl(rxd + 0xc));
6365 rxd += (4 * sizeof(u32));
6366 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6367 i,
6368 readl(rxd + 0x0), readl(rxd + 0x4),
6369 readl(rxd + 0x8), readl(rxd + 0xc));
6370 }
6371}
6372#endif
6373
6374static struct net_device_stats *tg3_get_stats(struct net_device *);
6375static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6376
6377static int tg3_close(struct net_device *dev)
6378{
6379 struct tg3 *tp = netdev_priv(dev);
6380
6381 netif_stop_queue(dev);
6382
6383 del_timer_sync(&tp->timer);
6384
6385 spin_lock_irq(&tp->lock);
6386 spin_lock(&tp->tx_lock);
6387#if 0
6388 tg3_dump_state(tp);
6389#endif
6390
6391 tg3_disable_ints(tp);
6392
944d980e 6393 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6394 tg3_free_rings(tp);
6395 tp->tg3_flags &=
6396 ~(TG3_FLAG_INIT_COMPLETE |
6397 TG3_FLAG_GOT_SERDES_FLOWCTL);
6398 netif_carrier_off(tp->dev);
6399
6400 spin_unlock(&tp->tx_lock);
6401 spin_unlock_irq(&tp->lock);
6402
88b06bc2
MC		 6403 free_irq(tp->pdev->irq, dev);
6404 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6405 pci_disable_msi(tp->pdev);
6406 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6407 }
1da177e4
LT		 6408
6409 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6410 sizeof(tp->net_stats_prev));
6411 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6412 sizeof(tp->estats_prev));
6413
6414 tg3_free_consistent(tp);
6415
6416 return 0;
6417}
6418
6419static inline unsigned long get_stat64(tg3_stat64_t *val)
6420{
6421 unsigned long ret;
6422
6423#if (BITS_PER_LONG == 32)
6424 ret = val->low;
6425#else
6426 ret = ((u64)val->high << 32) | ((u64)val->low);
6427#endif
6428 return ret;
6429}
6430
6431static unsigned long calc_crc_errors(struct tg3 *tp)
6432{
6433 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6434
6435 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6436 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6437 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6438 unsigned long flags;
6439 u32 val;
6440
6441 spin_lock_irqsave(&tp->lock, flags);
6442 if (!tg3_readphy(tp, 0x1e, &val)) {
6443 tg3_writephy(tp, 0x1e, val | 0x8000);
6444 tg3_readphy(tp, 0x14, &val);
6445 } else
6446 val = 0;
6447 spin_unlock_irqrestore(&tp->lock, flags);
6448
6449 tp->phy_crc_errors += val;
6450
6451 return tp->phy_crc_errors;
6452 }
6453
6454 return get_stat64(&hw_stats->rx_fcs_errors);
6455}
6456
6457#define ESTAT_ADD(member) \
6458 estats->member = old_estats->member + \
6459 get_stat64(&hw_stats->member)
6460
6461static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6462{
6463 struct tg3_ethtool_stats *estats = &tp->estats;
6464 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6465 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6466
6467 if (!hw_stats)
6468 return old_estats;
6469
6470 ESTAT_ADD(rx_octets);
6471 ESTAT_ADD(rx_fragments);
6472 ESTAT_ADD(rx_ucast_packets);
6473 ESTAT_ADD(rx_mcast_packets);
6474 ESTAT_ADD(rx_bcast_packets);
6475 ESTAT_ADD(rx_fcs_errors);
6476 ESTAT_ADD(rx_align_errors);
6477 ESTAT_ADD(rx_xon_pause_rcvd);
6478 ESTAT_ADD(rx_xoff_pause_rcvd);
6479 ESTAT_ADD(rx_mac_ctrl_rcvd);
6480 ESTAT_ADD(rx_xoff_entered);
6481 ESTAT_ADD(rx_frame_too_long_errors);
6482 ESTAT_ADD(rx_jabbers);
6483 ESTAT_ADD(rx_undersize_packets);
6484 ESTAT_ADD(rx_in_length_errors);
6485 ESTAT_ADD(rx_out_length_errors);
6486 ESTAT_ADD(rx_64_or_less_octet_packets);
6487 ESTAT_ADD(rx_65_to_127_octet_packets);
6488 ESTAT_ADD(rx_128_to_255_octet_packets);
6489 ESTAT_ADD(rx_256_to_511_octet_packets);
6490 ESTAT_ADD(rx_512_to_1023_octet_packets);
6491 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6492 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6493 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6494 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6495 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6496
6497 ESTAT_ADD(tx_octets);
6498 ESTAT_ADD(tx_collisions);
6499 ESTAT_ADD(tx_xon_sent);
6500 ESTAT_ADD(tx_xoff_sent);
6501 ESTAT_ADD(tx_flow_control);
6502 ESTAT_ADD(tx_mac_errors);
6503 ESTAT_ADD(tx_single_collisions);
6504 ESTAT_ADD(tx_mult_collisions);
6505 ESTAT_ADD(tx_deferred);
6506 ESTAT_ADD(tx_excessive_collisions);
6507 ESTAT_ADD(tx_late_collisions);
6508 ESTAT_ADD(tx_collide_2times);
6509 ESTAT_ADD(tx_collide_3times);
6510 ESTAT_ADD(tx_collide_4times);
6511 ESTAT_ADD(tx_collide_5times);
6512 ESTAT_ADD(tx_collide_6times);
6513 ESTAT_ADD(tx_collide_7times);
6514 ESTAT_ADD(tx_collide_8times);
6515 ESTAT_ADD(tx_collide_9times);
6516 ESTAT_ADD(tx_collide_10times);
6517 ESTAT_ADD(tx_collide_11times);
6518 ESTAT_ADD(tx_collide_12times);
6519 ESTAT_ADD(tx_collide_13times);
6520 ESTAT_ADD(tx_collide_14times);
6521 ESTAT_ADD(tx_collide_15times);
6522 ESTAT_ADD(tx_ucast_packets);
6523 ESTAT_ADD(tx_mcast_packets);
6524 ESTAT_ADD(tx_bcast_packets);
6525 ESTAT_ADD(tx_carrier_sense_errors);
6526 ESTAT_ADD(tx_discards);
6527 ESTAT_ADD(tx_errors);
6528
6529 ESTAT_ADD(dma_writeq_full);
6530 ESTAT_ADD(dma_write_prioq_full);
6531 ESTAT_ADD(rxbds_empty);
6532 ESTAT_ADD(rx_discards);
6533 ESTAT_ADD(rx_errors);
6534 ESTAT_ADD(rx_threshold_hit);
6535
6536 ESTAT_ADD(dma_readq_full);
6537 ESTAT_ADD(dma_read_prioq_full);
6538 ESTAT_ADD(tx_comp_queue_full);
6539
6540 ESTAT_ADD(ring_set_send_prod_index);
6541 ESTAT_ADD(ring_status_update);
6542 ESTAT_ADD(nic_irqs);
6543 ESTAT_ADD(nic_avoided_irqs);
6544 ESTAT_ADD(nic_tx_threshold_hit);
6545
6546 return estats;
6547}
6548
6549static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6550{
6551 struct tg3 *tp = netdev_priv(dev);
6552 struct net_device_stats *stats = &tp->net_stats;
6553 struct net_device_stats *old_stats = &tp->net_stats_prev;
6554 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6555
6556 if (!hw_stats)
6557 return old_stats;
6558
6559 stats->rx_packets = old_stats->rx_packets +
6560 get_stat64(&hw_stats->rx_ucast_packets) +
6561 get_stat64(&hw_stats->rx_mcast_packets) +
6562 get_stat64(&hw_stats->rx_bcast_packets);
6563
6564 stats->tx_packets = old_stats->tx_packets +
6565 get_stat64(&hw_stats->tx_ucast_packets) +
6566 get_stat64(&hw_stats->tx_mcast_packets) +
6567 get_stat64(&hw_stats->tx_bcast_packets);
6568
6569 stats->rx_bytes = old_stats->rx_bytes +
6570 get_stat64(&hw_stats->rx_octets);
6571 stats->tx_bytes = old_stats->tx_bytes +
6572 get_stat64(&hw_stats->tx_octets);
6573
6574 stats->rx_errors = old_stats->rx_errors +
6575 get_stat64(&hw_stats->rx_errors) +
6576 get_stat64(&hw_stats->rx_discards);
6577 stats->tx_errors = old_stats->tx_errors +
6578 get_stat64(&hw_stats->tx_errors) +
6579 get_stat64(&hw_stats->tx_mac_errors) +
6580 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6581 get_stat64(&hw_stats->tx_discards);
6582
6583 stats->multicast = old_stats->multicast +
6584 get_stat64(&hw_stats->rx_mcast_packets);
6585 stats->collisions = old_stats->collisions +
6586 get_stat64(&hw_stats->tx_collisions);
6587
6588 stats->rx_length_errors = old_stats->rx_length_errors +
6589 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6590 get_stat64(&hw_stats->rx_undersize_packets);
6591
6592 stats->rx_over_errors = old_stats->rx_over_errors +
6593 get_stat64(&hw_stats->rxbds_empty);
6594 stats->rx_frame_errors = old_stats->rx_frame_errors +
6595 get_stat64(&hw_stats->rx_align_errors);
6596 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6597 get_stat64(&hw_stats->tx_discards);
6598 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6599 get_stat64(&hw_stats->tx_carrier_sense_errors);
6600
6601 stats->rx_crc_errors = old_stats->rx_crc_errors +
6602 calc_crc_errors(tp);
6603
6604 return stats;
6605}
6606
6607static inline u32 calc_crc(unsigned char *buf, int len)
6608{
6609 u32 reg;
6610 u32 tmp;
6611 int j, k;
6612
6613 reg = 0xffffffff;
6614
6615 for (j = 0; j < len; j++) {
6616 reg ^= buf[j];
6617
6618 for (k = 0; k < 8; k++) {
6619 tmp = reg & 0x01;
6620
6621 reg >>= 1;
6622
6623 if (tmp) {
6624 reg ^= 0xedb88320;
6625 }
6626 }
6627 }
6628
6629 return ~reg;
6630}
6631
6632static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6633{
6634 /* accept or reject all multicast frames */
6635 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6636 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6637 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6638 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6639}
6640
6641static void __tg3_set_rx_mode(struct net_device *dev)
6642{
6643 struct tg3 *tp = netdev_priv(dev);
6644 u32 rx_mode;
6645
6646 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6647 RX_MODE_KEEP_VLAN_TAG);
6648
6649 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6650 * flag clear.
6651 */
6652#if TG3_VLAN_TAG_USED
6653 if (!tp->vlgrp &&
6654 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6655 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6656#else
6657 /* By definition, VLAN is disabled always in this
6658 * case.
6659 */
6660 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6661 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6662#endif
6663
6664 if (dev->flags & IFF_PROMISC) {
6665 /* Promiscuous mode. */
6666 rx_mode |= RX_MODE_PROMISC;
6667 } else if (dev->flags & IFF_ALLMULTI) {
6668 /* Accept all multicast. */
6669 tg3_set_multi (tp, 1);
6670 } else if (dev->mc_count < 1) {
6671 /* Reject all multicast. */
6672 tg3_set_multi (tp, 0);
6673 } else {
6674 /* Accept one or more multicast(s). */
6675 struct dev_mc_list *mclist;
6676 unsigned int i;
6677 u32 mc_filter[4] = { 0, };
6678 u32 regidx;
6679 u32 bit;
6680 u32 crc;
6681
6682 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6683 i++, mclist = mclist->next) {
6684
6685 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6686 bit = ~crc & 0x7f;
6687 regidx = (bit & 0x60) >> 5;
6688 bit &= 0x1f;
6689 mc_filter[regidx] |= (1 << bit);
6690 }
6691
6692 tw32(MAC_HASH_REG_0, mc_filter[0]);
6693 tw32(MAC_HASH_REG_1, mc_filter[1]);
6694 tw32(MAC_HASH_REG_2, mc_filter[2]);
6695 tw32(MAC_HASH_REG_3, mc_filter[3]);
6696 }
6697
6698 if (rx_mode != tp->rx_mode) {
6699 tp->rx_mode = rx_mode;
6700 tw32_f(MAC_RX_MODE, rx_mode);
6701 udelay(10);
6702 }
6703}
6704
6705static void tg3_set_rx_mode(struct net_device *dev)
6706{
6707 struct tg3 *tp = netdev_priv(dev);
6708
6709 spin_lock_irq(&tp->lock);
6710 spin_lock(&tp->tx_lock);
6711 __tg3_set_rx_mode(dev);
6712 spin_unlock(&tp->tx_lock);
6713 spin_unlock_irq(&tp->lock);
6714}
6715
6716#define TG3_REGDUMP_LEN (32 * 1024)
6717
6718static int tg3_get_regs_len(struct net_device *dev)
6719{
6720 return TG3_REGDUMP_LEN;
6721}
6722
6723static void tg3_get_regs(struct net_device *dev,
6724 struct ethtool_regs *regs, void *_p)
6725{
6726 u32 *p = _p;
6727 struct tg3 *tp = netdev_priv(dev);
6728 u8 *orig_p = _p;
6729 int i;
6730
6731 regs->version = 0;
6732
6733 memset(p, 0, TG3_REGDUMP_LEN);
6734
6735 spin_lock_irq(&tp->lock);
6736 spin_lock(&tp->tx_lock);
6737
6738#define __GET_REG32(reg) (*(p)++ = tr32(reg))
6739#define GET_REG32_LOOP(base,len) \
6740do { p = (u32 *)(orig_p + (base)); \
6741 for (i = 0; i < len; i += 4) \
6742 __GET_REG32((base) + i); \
6743} while (0)
6744#define GET_REG32_1(reg) \
6745do { p = (u32 *)(orig_p + (reg)); \
6746 __GET_REG32((reg)); \
6747} while (0)
6748
6749 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6750 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6751 GET_REG32_LOOP(MAC_MODE, 0x4f0);
6752 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6753 GET_REG32_1(SNDDATAC_MODE);
6754 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6755 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6756 GET_REG32_1(SNDBDC_MODE);
6757 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6758 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6759 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6760 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6761 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6762 GET_REG32_1(RCVDCC_MODE);
6763 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6764 GET_REG32_LOOP(RCVCC_MODE, 0x14);
6765 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6766 GET_REG32_1(MBFREE_MODE);
6767 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6768 GET_REG32_LOOP(MEMARB_MODE, 0x10);
6769 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6770 GET_REG32_LOOP(RDMAC_MODE, 0x08);
6771 GET_REG32_LOOP(WDMAC_MODE, 0x08);
6772 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6773 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6774 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6775 GET_REG32_LOOP(FTQ_RESET, 0x120);
6776 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6777 GET_REG32_1(DMAC_MODE);
6778 GET_REG32_LOOP(GRC_MODE, 0x4c);
6779 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6780 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6781
6782#undef __GET_REG32
6783#undef GET_REG32_LOOP
6784#undef GET_REG32_1
6785
6786 spin_unlock(&tp->tx_lock);
6787 spin_unlock_irq(&tp->lock);
6788}
6789
6790static int tg3_get_eeprom_len(struct net_device *dev)
6791{
6792 struct tg3 *tp = netdev_priv(dev);
6793
6794 return tp->nvram_size;
6795}
6796
6797static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6798
6799static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6800{
6801 struct tg3 *tp = netdev_priv(dev);
6802 int ret;
6803 u8 *pd;
6804 u32 i, offset, len, val, b_offset, b_count;
6805
6806 offset = eeprom->offset;
6807 len = eeprom->len;
6808 eeprom->len = 0;
6809
6810 eeprom->magic = TG3_EEPROM_MAGIC;
6811
6812 if (offset & 3) {
6813 /* adjustments to start on required 4 byte boundary */
6814 b_offset = offset & 3;
6815 b_count = 4 - b_offset;
6816 if (b_count > len) {
6817 /* i.e. offset=1 len=2 */
6818 b_count = len;
6819 }
6820 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6821 if (ret)
6822 return ret;
6823 val = cpu_to_le32(val);
6824 memcpy(data, ((char*)&val) + b_offset, b_count);
6825 len -= b_count;
6826 offset += b_count;
6827 eeprom->len += b_count;
6828 }
6829
6830 /* read bytes upto the last 4 byte boundary */
6831 pd = &data[eeprom->len];
6832 for (i = 0; i < (len - (len & 3)); i += 4) {
6833 ret = tg3_nvram_read(tp, offset + i, &val);
6834 if (ret) {
6835 eeprom->len += i;
6836 return ret;
6837 }
6838 val = cpu_to_le32(val);
6839 memcpy(pd + i, &val, 4);
6840 }
6841 eeprom->len += i;
6842
6843 if (len & 3) {
6844 /* read last bytes not ending on 4 byte boundary */
6845 pd = &data[eeprom->len];
6846 b_count = len & 3;
6847 b_offset = offset + len - b_count;
6848 ret = tg3_nvram_read(tp, b_offset, &val);
6849 if (ret)
6850 return ret;
6851 val = cpu_to_le32(val);
6852 memcpy(pd, ((char*)&val), b_count);
6853 eeprom->len += b_count;
6854 }
6855 return 0;
6856}
6857
6858static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6859
6860static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6861{
6862 struct tg3 *tp = netdev_priv(dev);
6863 int ret;
6864 u32 offset, len, b_offset, odd_len, start, end;
6865 u8 *buf;
6866
6867 if (eeprom->magic != TG3_EEPROM_MAGIC)
6868 return -EINVAL;
6869
6870 offset = eeprom->offset;
6871 len = eeprom->len;
6872
6873 if ((b_offset = (offset & 3))) {
6874 /* adjustments to start on required 4 byte boundary */
6875 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6876 if (ret)
6877 return ret;
6878 start = cpu_to_le32(start);
6879 len += b_offset;
6880 offset &= ~3;
1c8594b4
MC		 6881 if (len < 4)
6882 len = 4;
1da177e4
LT		 6883 }
6884
6885 odd_len = 0;
1c8594b4 6886 if (len & 3) {
1da177e4
LT		 6887 /* adjustments to end on required 4 byte boundary */
6888 odd_len = 1;
6889 len = (len + 3) & ~3;
6890 ret = tg3_nvram_read(tp, offset+len-4, &end);
6891 if (ret)
6892 return ret;
6893 end = cpu_to_le32(end);
6894 }
6895
6896 buf = data;
6897 if (b_offset || odd_len) {
6898 buf = kmalloc(len, GFP_KERNEL);
6899 if (buf == 0)
6900 return -ENOMEM;
6901 if (b_offset)
6902 memcpy(buf, &start, 4);
6903 if (odd_len)
6904 memcpy(buf+len-4, &end, 4);
6905 memcpy(buf + b_offset, data, eeprom->len);
6906 }
6907
6908 ret = tg3_nvram_write_block(tp, offset, len, buf);
6909
6910 if (buf != data)
6911 kfree(buf);
6912
6913 return ret;
6914}
6915
6916static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6917{
6918 struct tg3 *tp = netdev_priv(dev);
6919
6920 cmd->supported = (SUPPORTED_Autoneg);
6921
6922 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6923 cmd->supported |= (SUPPORTED_1000baseT_Half |
6924 SUPPORTED_1000baseT_Full);
6925
6926 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6927 cmd->supported |= (SUPPORTED_100baseT_Half |
6928 SUPPORTED_100baseT_Full |
6929 SUPPORTED_10baseT_Half |
6930 SUPPORTED_10baseT_Full |
6931 SUPPORTED_MII);
6932 else
6933 cmd->supported |= SUPPORTED_FIBRE;
6934
6935 cmd->advertising = tp->link_config.advertising;
6936 if (netif_running(dev)) {
6937 cmd->speed = tp->link_config.active_speed;
6938 cmd->duplex = tp->link_config.active_duplex;
6939 }
6940 cmd->port = 0;
6941 cmd->phy_address = PHY_ADDR;
6942 cmd->transceiver = 0;
6943 cmd->autoneg = tp->link_config.autoneg;
6944 cmd->maxtxpkt = 0;
6945 cmd->maxrxpkt = 0;
6946 return 0;
6947}
6948
6949static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6950{
6951 struct tg3 *tp = netdev_priv(dev);
6952
6953 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6954 /* These are the only valid advertisement bits allowed. */
6955 if (cmd->autoneg == AUTONEG_ENABLE &&
6956 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6957 ADVERTISED_1000baseT_Full |
6958 ADVERTISED_Autoneg |
6959 ADVERTISED_FIBRE)))
6960 return -EINVAL;
6961 }
6962
6963 spin_lock_irq(&tp->lock);
6964 spin_lock(&tp->tx_lock);
6965
6966 tp->link_config.autoneg = cmd->autoneg;
6967 if (cmd->autoneg == AUTONEG_ENABLE) {
6968 tp->link_config.advertising = cmd->advertising;
6969 tp->link_config.speed = SPEED_INVALID;
6970 tp->link_config.duplex = DUPLEX_INVALID;
6971 } else {
6972 tp->link_config.advertising = 0;
6973 tp->link_config.speed = cmd->speed;
6974 tp->link_config.duplex = cmd->duplex;
6975 }
6976
6977 if (netif_running(dev))
6978 tg3_setup_phy(tp, 1);
6979
6980 spin_unlock(&tp->tx_lock);
6981 spin_unlock_irq(&tp->lock);
6982
6983 return 0;
6984}
6985
6986static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6987{
6988 struct tg3 *tp = netdev_priv(dev);
6989
6990 strcpy(info->driver, DRV_MODULE_NAME);
6991 strcpy(info->version, DRV_MODULE_VERSION);
6992 strcpy(info->bus_info, pci_name(tp->pdev));
6993}
6994
6995static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6996{
6997 struct tg3 *tp = netdev_priv(dev);
6998
6999 wol->supported = WAKE_MAGIC;
7000 wol->wolopts = 0;
7001 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7002 wol->wolopts = WAKE_MAGIC;
7003 memset(&wol->sopass, 0, sizeof(wol->sopass));
7004}
7005
7006static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7007{
7008 struct tg3 *tp = netdev_priv(dev);
7009
7010 if (wol->wolopts & ~WAKE_MAGIC)
7011 return -EINVAL;
7012 if ((wol->wolopts & WAKE_MAGIC) &&
7013 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7014 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7015 return -EINVAL;
7016
7017 spin_lock_irq(&tp->lock);
7018 if (wol->wolopts & WAKE_MAGIC)
7019 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7020 else
7021 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7022 spin_unlock_irq(&tp->lock);
7023
7024 return 0;
7025}
7026
7027static u32 tg3_get_msglevel(struct net_device *dev)
7028{
7029 struct tg3 *tp = netdev_priv(dev);
7030 return tp->msg_enable;
7031}
7032
7033static void tg3_set_msglevel(struct net_device *dev, u32 value)
7034{
7035 struct tg3 *tp = netdev_priv(dev);
7036 tp->msg_enable = value;
7037}
7038
7039#if TG3_TSO_SUPPORT != 0
7040static int tg3_set_tso(struct net_device *dev, u32 value)
7041{
7042 struct tg3 *tp = netdev_priv(dev);
7043
7044 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7045 if (value)
7046 return -EINVAL;
7047 return 0;
7048 }
7049 return ethtool_op_set_tso(dev, value);
7050}
7051#endif
7052
7053static int tg3_nway_reset(struct net_device *dev)
7054{
7055 struct tg3 *tp = netdev_priv(dev);
7056 u32 bmcr;
7057 int r;
7058
7059 if (!netif_running(dev))
7060 return -EAGAIN;
7061
7062 spin_lock_irq(&tp->lock);
7063 r = -EINVAL;
7064 tg3_readphy(tp, MII_BMCR, &bmcr);
7065 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7066 (bmcr & BMCR_ANENABLE)) {
7067 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7068 r = 0;
7069 }
7070 spin_unlock_irq(&tp->lock);
7071
7072 return r;
7073}
7074
7075static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7076{
7077 struct tg3 *tp = netdev_priv(dev);
7078
7079 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7080 ering->rx_mini_max_pending = 0;
7081 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7082
7083 ering->rx_pending = tp->rx_pending;
7084 ering->rx_mini_pending = 0;
7085 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7086 ering->tx_pending = tp->tx_pending;
7087}
7088
7089static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7090{
7091 struct tg3 *tp = netdev_priv(dev);
7092
7093 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7094 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7095 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7096 return -EINVAL;
7097
7098 if (netif_running(dev))
7099 tg3_netif_stop(tp);
7100
7101 spin_lock_irq(&tp->lock);
7102 spin_lock(&tp->tx_lock);
7103
7104 tp->rx_pending = ering->rx_pending;
7105
7106 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7107 tp->rx_pending > 63)
7108 tp->rx_pending = 63;
7109 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7110 tp->tx_pending = ering->tx_pending;
7111
7112 if (netif_running(dev)) {
944d980e 7113 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7114 tg3_init_hw(tp);
7115 tg3_netif_start(tp);
7116 }
7117
7118 spin_unlock(&tp->tx_lock);
7119 spin_unlock_irq(&tp->lock);
7120
7121 return 0;
7122}
7123
7124static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7125{
7126 struct tg3 *tp = netdev_priv(dev);
7127
7128 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7129 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7130 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7131}
7132
7133static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7134{
7135 struct tg3 *tp = netdev_priv(dev);
7136
7137 if (netif_running(dev))
7138 tg3_netif_stop(tp);
7139
7140 spin_lock_irq(&tp->lock);
7141 spin_lock(&tp->tx_lock);
7142 if (epause->autoneg)
7143 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7144 else
7145 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7146 if (epause->rx_pause)
7147 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7148 else
7149 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7150 if (epause->tx_pause)
7151 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7152 else
7153 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7154
7155 if (netif_running(dev)) {
944d980e 7156 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7157 tg3_init_hw(tp);
7158 tg3_netif_start(tp);
7159 }
7160 spin_unlock(&tp->tx_lock);
7161 spin_unlock_irq(&tp->lock);
7162
7163 return 0;
7164}
7165
7166static u32 tg3_get_rx_csum(struct net_device *dev)
7167{
7168 struct tg3 *tp = netdev_priv(dev);
7169 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7170}
7171
7172static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7173{
7174 struct tg3 *tp = netdev_priv(dev);
7175
7176 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7177 if (data != 0)
7178 return -EINVAL;
7179 return 0;
7180 }
7181
7182 spin_lock_irq(&tp->lock);
7183 if (data)
7184 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7185 else
7186 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7187 spin_unlock_irq(&tp->lock);
7188
7189 return 0;
7190}
7191
7192static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7193{
7194 struct tg3 *tp = netdev_priv(dev);
7195
7196 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7197 if (data != 0)
7198 return -EINVAL;
7199 return 0;
7200 }
7201
7202 if (data)
7203 dev->features |= NETIF_F_IP_CSUM;
7204 else
7205 dev->features &= ~NETIF_F_IP_CSUM;
7206
7207 return 0;
7208}
7209
7210static int tg3_get_stats_count (struct net_device *dev)
7211{
7212 return TG3_NUM_STATS;
7213}
7214
4cafd3f5
MC		 7215static int tg3_get_test_count (struct net_device *dev)
7216{
7217 return TG3_NUM_TEST;
7218}
7219
1da177e4
LT		 7220static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7221{
7222 switch (stringset) {
7223 case ETH_SS_STATS:
7224 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7225 break;
4cafd3f5
MC		 7226 case ETH_SS_TEST:
7227 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7228 break;
1da177e4
LT		 7229 default:
7230 WARN_ON(1); /* we need a WARN() */
7231 break;
7232 }
7233}
7234
7235static void tg3_get_ethtool_stats (struct net_device *dev,
7236 struct ethtool_stats *estats, u64 *tmp_stats)
7237{
7238 struct tg3 *tp = netdev_priv(dev);
7239 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7240}
7241
566f86ad
MC		 7242#define NVRAM_TEST_SIZE 0x100
7243
7244static int tg3_test_nvram(struct tg3 *tp)
7245{
7246 u32 *buf, csum;
7247 int i, j, err = 0;
7248
7249 buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7250 if (buf == NULL)
7251 return -ENOMEM;
7252
7253 for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7254 u32 val;
7255
7256 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7257 break;
7258 buf[j] = cpu_to_le32(val);
7259 }
7260 if (i < NVRAM_TEST_SIZE)
7261 goto out;
7262
7263 err = -EIO;
7264 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7265 goto out;
7266
7267 /* Bootstrap checksum at offset 0x10 */
7268 csum = calc_crc((unsigned char *) buf, 0x10);
7269 if(csum != cpu_to_le32(buf[0x10/4]))
7270 goto out;
7271
7272 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7273 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7274 if (csum != cpu_to_le32(buf[0xfc/4]))
7275 goto out;
7276
7277 err = 0;
7278
7279out:
7280 kfree(buf);
7281 return err;
7282}
7283
ca43007a
MC		 7284#define TG3_SERDES_TIMEOUT_SEC 2
7285#define TG3_COPPER_TIMEOUT_SEC 6
7286
7287static int tg3_test_link(struct tg3 *tp)
7288{
7289 int i, max;
7290
7291 if (!netif_running(tp->dev))
7292 return -ENODEV;
7293
7294 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7295 max = TG3_SERDES_TIMEOUT_SEC;
7296 else
7297 max = TG3_COPPER_TIMEOUT_SEC;
7298
7299 for (i = 0; i < max; i++) {
7300 if (netif_carrier_ok(tp->dev))
7301 return 0;
7302
7303 if (msleep_interruptible(1000))
7304 break;
7305 }
7306
7307 return -EIO;
7308}
7309
a71116d1
MC		 7310/* Only test the commonly used registers */
7311static int tg3_test_registers(struct tg3 *tp)
7312{
7313 int i, is_5705;
7314 u32 offset, read_mask, write_mask, val, save_val, read_val;
7315 static struct {
7316 u16 offset;
7317 u16 flags;
7318#define TG3_FL_5705 0x1
7319#define TG3_FL_NOT_5705 0x2
7320#define TG3_FL_NOT_5788 0x4
7321 u32 read_mask;
7322 u32 write_mask;
7323 } reg_tbl[] = {
7324 /* MAC Control Registers */
7325 { MAC_MODE, TG3_FL_NOT_5705,
7326 0x00000000, 0x00ef6f8c },
7327 { MAC_MODE, TG3_FL_5705,
7328 0x00000000, 0x01ef6b8c },
7329 { MAC_STATUS, TG3_FL_NOT_5705,
7330 0x03800107, 0x00000000 },
7331 { MAC_STATUS, TG3_FL_5705,
7332 0x03800100, 0x00000000 },
7333 { MAC_ADDR_0_HIGH, 0x0000,
7334 0x00000000, 0x0000ffff },
7335 { MAC_ADDR_0_LOW, 0x0000,
7336 0x00000000, 0xffffffff },
7337 { MAC_RX_MTU_SIZE, 0x0000,
7338 0x00000000, 0x0000ffff },
7339 { MAC_TX_MODE, 0x0000,
7340 0x00000000, 0x00000070 },
7341 { MAC_TX_LENGTHS, 0x0000,
7342 0x00000000, 0x00003fff },
7343 { MAC_RX_MODE, TG3_FL_NOT_5705,
7344 0x00000000, 0x000007fc },
7345 { MAC_RX_MODE, TG3_FL_5705,
7346 0x00000000, 0x000007dc },
7347 { MAC_HASH_REG_0, 0x0000,
7348 0x00000000, 0xffffffff },
7349 { MAC_HASH_REG_1, 0x0000,
7350 0x00000000, 0xffffffff },
7351 { MAC_HASH_REG_2, 0x0000,
7352 0x00000000, 0xffffffff },
7353 { MAC_HASH_REG_3, 0x0000,
7354 0x00000000, 0xffffffff },
7355
7356 /* Receive Data and Receive BD Initiator Control Registers. */
7357 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7358 0x00000000, 0xffffffff },
7359 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7360 0x00000000, 0xffffffff },
7361 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7362 0x00000000, 0x00000003 },
7363 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7364 0x00000000, 0xffffffff },
7365 { RCVDBDI_STD_BD+0, 0x0000,
7366 0x00000000, 0xffffffff },
7367 { RCVDBDI_STD_BD+4, 0x0000,
7368 0x00000000, 0xffffffff },
7369 { RCVDBDI_STD_BD+8, 0x0000,
7370 0x00000000, 0xffff0002 },
7371 { RCVDBDI_STD_BD+0xc, 0x0000,
7372 0x00000000, 0xffffffff },
7373
7374 /* Receive BD Initiator Control Registers. */
7375 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7376 0x00000000, 0xffffffff },
7377 { RCVBDI_STD_THRESH, TG3_FL_5705,
7378 0x00000000, 0x000003ff },
7379 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7380 0x00000000, 0xffffffff },
7381
7382 /* Host Coalescing Control Registers. */
7383 { HOSTCC_MODE, TG3_FL_NOT_5705,
7384 0x00000000, 0x00000004 },
7385 { HOSTCC_MODE, TG3_FL_5705,
7386 0x00000000, 0x000000f6 },
7387 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7388 0x00000000, 0xffffffff },
7389 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7390 0x00000000, 0x000003ff },
7391 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7392 0x00000000, 0xffffffff },
7393 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7394 0x00000000, 0x000003ff },
7395 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7396 0x00000000, 0xffffffff },
7397 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7398 0x00000000, 0x000000ff },
7399 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7400 0x00000000, 0xffffffff },
7401 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7402 0x00000000, 0x000000ff },
7403 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7404 0x00000000, 0xffffffff },
7405 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7406 0x00000000, 0xffffffff },
7407 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7408 0x00000000, 0xffffffff },
7409 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7410 0x00000000, 0x000000ff },
7411 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7412 0x00000000, 0xffffffff },
7413 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7414 0x00000000, 0x000000ff },
7415 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7416 0x00000000, 0xffffffff },
7417 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7418 0x00000000, 0xffffffff },
7419 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7420 0x00000000, 0xffffffff },
7421 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7422 0x00000000, 0xffffffff },
7423 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7424 0x00000000, 0xffffffff },
7425 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7426 0xffffffff, 0x00000000 },
7427 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7428 0xffffffff, 0x00000000 },
7429
7430 /* Buffer Manager Control Registers. */
7431 { BUFMGR_MB_POOL_ADDR, 0x0000,
7432 0x00000000, 0x007fff80 },
7433 { BUFMGR_MB_POOL_SIZE, 0x0000,
7434 0x00000000, 0x007fffff },
7435 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7436 0x00000000, 0x0000003f },
7437 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7438 0x00000000, 0x000001ff },
7439 { BUFMGR_MB_HIGH_WATER, 0x0000,
7440 0x00000000, 0x000001ff },
7441 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7442 0xffffffff, 0x00000000 },
7443 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7444 0xffffffff, 0x00000000 },
7445
7446 /* Mailbox Registers */
7447 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7448 0x00000000, 0x000001ff },
7449 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7450 0x00000000, 0x000001ff },
7451 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7452 0x00000000, 0x000007ff },
7453 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7454 0x00000000, 0x000001ff },
7455
7456 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7457 };
7458
7459 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7460 is_5705 = 1;
7461 else
7462 is_5705 = 0;
7463
7464 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7465 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7466 continue;
7467
7468 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7469 continue;
7470
7471 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7472 (reg_tbl[i].flags & TG3_FL_NOT_5788))
7473 continue;
7474
7475 offset = (u32) reg_tbl[i].offset;
7476 read_mask = reg_tbl[i].read_mask;
7477 write_mask = reg_tbl[i].write_mask;
7478
7479 /* Save the original register content */
7480 save_val = tr32(offset);
7481
7482 /* Determine the read-only value. */
7483 read_val = save_val & read_mask;
7484
7485 /* Write zero to the register, then make sure the read-only bits
7486 * are not changed and the read/write bits are all zeros.
7487 */
7488 tw32(offset, 0);
7489
7490 val = tr32(offset);
7491
7492 /* Test the read-only and read/write bits. */
7493 if (((val & read_mask) != read_val) || (val & write_mask))
7494 goto out;
7495
7496 /* Write ones to all the bits defined by RdMask and WrMask, then
7497 * make sure the read-only bits are not changed and the
7498 * read/write bits are all ones.
7499 */
7500 tw32(offset, read_mask | write_mask);
7501
7502 val = tr32(offset);
7503
7504 /* Test the read-only bits. */
7505 if ((val & read_mask) != read_val)
7506 goto out;
7507
7508 /* Test the read/write bits. */
7509 if ((val & write_mask) != write_mask)
7510 goto out;
7511
7512 tw32(offset, save_val);
7513 }
7514
7515 return 0;
7516
7517out:
7518 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7519 tw32(offset, save_val);
7520 return -EIO;
7521}
7522
4cafd3f5
MC		 7523static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
7524 u64 *data)
7525{
566f86ad
MC		 7526 struct tg3 *tp = netdev_priv(dev);
7527
7528 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
7529
7530 if (tg3_test_nvram(tp) != 0) {
7531 etest->flags |= ETH_TEST_FL_FAILED;
7532 data[0] = 1;
7533 }
ca43007a
MC		 7534 if (tg3_test_link(tp) != 0) {
7535 etest->flags |= ETH_TEST_FL_FAILED;
7536 data[1] = 1;
7537 }
a71116d1
MC		 7538 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7539 if (netif_running(dev))
7540 tg3_netif_stop(tp);
7541
7542 spin_lock_irq(&tp->lock);
7543 spin_lock(&tp->tx_lock);
7544
7545 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
7546 tg3_nvram_lock(tp);
7547 tg3_halt_cpu(tp, RX_CPU_BASE);
7548 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7549 tg3_halt_cpu(tp, TX_CPU_BASE);
7550 tg3_nvram_unlock(tp);
7551
7552 if (tg3_test_registers(tp) != 0) {
7553 etest->flags |= ETH_TEST_FL_FAILED;
7554 data[2] = 1;
7555 }
7556
7557 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7558 if (netif_running(dev)) {
7559 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7560 tg3_init_hw(tp);
7561 tg3_netif_start(tp);
7562 }
7563 spin_unlock(&tp->tx_lock);
7564 spin_unlock_irq(&tp->lock);
7565 }
4cafd3f5
MC		 7566}
7567
1da177e4
LT		 7568static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7569{
7570 struct mii_ioctl_data *data = if_mii(ifr);
7571 struct tg3 *tp = netdev_priv(dev);
7572 int err;
7573
7574 switch(cmd) {
7575 case SIOCGMIIPHY:
7576 data->phy_id = PHY_ADDR;
7577
7578 /* fallthru */
7579 case SIOCGMIIREG: {
7580 u32 mii_regval;
7581
7582 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7583 break; /* We have no PHY */
7584
7585 spin_lock_irq(&tp->lock);
7586 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7587 spin_unlock_irq(&tp->lock);
7588
7589 data->val_out = mii_regval;
7590
7591 return err;
7592 }
7593
7594 case SIOCSMIIREG:
7595 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7596 break; /* We have no PHY */
7597
7598 if (!capable(CAP_NET_ADMIN))
7599 return -EPERM;
7600
7601 spin_lock_irq(&tp->lock);
7602 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7603 spin_unlock_irq(&tp->lock);
7604
7605 return err;
7606
7607 default:
7608 /* do nothing */
7609 break;
7610 }
7611 return -EOPNOTSUPP;
7612}
7613
7614#if TG3_VLAN_TAG_USED
7615static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7616{
7617 struct tg3 *tp = netdev_priv(dev);
7618
7619 spin_lock_irq(&tp->lock);
7620 spin_lock(&tp->tx_lock);
7621
7622 tp->vlgrp = grp;
7623
7624 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7625 __tg3_set_rx_mode(dev);
7626
7627 spin_unlock(&tp->tx_lock);
7628 spin_unlock_irq(&tp->lock);
7629}
7630
7631static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7632{
7633 struct tg3 *tp = netdev_priv(dev);
7634
7635 spin_lock_irq(&tp->lock);
7636 spin_lock(&tp->tx_lock);
7637 if (tp->vlgrp)
7638 tp->vlgrp->vlan_devices[vid] = NULL;
7639 spin_unlock(&tp->tx_lock);
7640 spin_unlock_irq(&tp->lock);
7641}
7642#endif
7643
15f9850d
DM		 7644static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7645{
7646 struct tg3 *tp = netdev_priv(dev);
7647
7648 memcpy(ec, &tp->coal, sizeof(*ec));
7649 return 0;
7650}
7651
1da177e4
LT		 7652static struct ethtool_ops tg3_ethtool_ops = {
7653 .get_settings = tg3_get_settings,
7654 .set_settings = tg3_set_settings,
7655 .get_drvinfo = tg3_get_drvinfo,
7656 .get_regs_len = tg3_get_regs_len,
7657 .get_regs = tg3_get_regs,
7658 .get_wol = tg3_get_wol,
7659 .set_wol = tg3_set_wol,
7660 .get_msglevel = tg3_get_msglevel,
7661 .set_msglevel = tg3_set_msglevel,
7662 .nway_reset = tg3_nway_reset,
7663 .get_link = ethtool_op_get_link,
7664 .get_eeprom_len = tg3_get_eeprom_len,
7665 .get_eeprom = tg3_get_eeprom,
7666 .set_eeprom = tg3_set_eeprom,
7667 .get_ringparam = tg3_get_ringparam,
7668 .set_ringparam = tg3_set_ringparam,
7669 .get_pauseparam = tg3_get_pauseparam,
7670 .set_pauseparam = tg3_set_pauseparam,
7671 .get_rx_csum = tg3_get_rx_csum,
7672 .set_rx_csum = tg3_set_rx_csum,
7673 .get_tx_csum = ethtool_op_get_tx_csum,
7674 .set_tx_csum = tg3_set_tx_csum,
7675 .get_sg = ethtool_op_get_sg,
7676 .set_sg = ethtool_op_set_sg,
7677#if TG3_TSO_SUPPORT != 0
7678 .get_tso = ethtool_op_get_tso,
7679 .set_tso = tg3_set_tso,
7680#endif
4cafd3f5
MC		 7681 .self_test_count = tg3_get_test_count,
7682 .self_test = tg3_self_test,
1da177e4
LT		 7683 .get_strings = tg3_get_strings,
7684 .get_stats_count = tg3_get_stats_count,
7685 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 7686 .get_coalesce = tg3_get_coalesce,
1da177e4
LT		 7687};
7688
7689static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7690{
7691 u32 cursize, val;
7692
7693 tp->nvram_size = EEPROM_CHIP_SIZE;
7694
7695 if (tg3_nvram_read(tp, 0, &val) != 0)
7696 return;
7697
7698 if (swab32(val) != TG3_EEPROM_MAGIC)
7699 return;
7700
7701 /*
7702 * Size the chip by reading offsets at increasing powers of two.
7703 * When we encounter our validation signature, we know the addressing
7704 * has wrapped around, and thus have our chip size.
7705 */
7706 cursize = 0x800;
7707
7708 while (cursize < tp->nvram_size) {
7709 if (tg3_nvram_read(tp, cursize, &val) != 0)
7710 return;
7711
7712 if (swab32(val) == TG3_EEPROM_MAGIC)
7713 break;
7714
7715 cursize <<= 1;
7716 }
7717
7718 tp->nvram_size = cursize;
7719}
7720
7721static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7722{
7723 u32 val;
7724
7725 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7726 if (val != 0) {
7727 tp->nvram_size = (val >> 16) * 1024;
7728 return;
7729 }
7730 }
7731 tp->nvram_size = 0x20000;
7732}
7733
7734static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7735{
7736 u32 nvcfg1;
7737
7738 nvcfg1 = tr32(NVRAM_CFG1);
7739 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7740 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7741 }
7742 else {
7743 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7744 tw32(NVRAM_CFG1, nvcfg1);
7745 }
7746
85e94ced 7747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7748 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7749 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7750 tp->nvram_jedecnum = JEDEC_ATMEL;
7751 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7752 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7753 break;
7754 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7755 tp->nvram_jedecnum = JEDEC_ATMEL;
7756 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7757 break;
7758 case FLASH_VENDOR_ATMEL_EEPROM:
7759 tp->nvram_jedecnum = JEDEC_ATMEL;
7760 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7761 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7762 break;
7763 case FLASH_VENDOR_ST:
7764 tp->nvram_jedecnum = JEDEC_ST;
7765 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7766 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7767 break;
7768 case FLASH_VENDOR_SAIFUN:
7769 tp->nvram_jedecnum = JEDEC_SAIFUN;
7770 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7771 break;
7772 case FLASH_VENDOR_SST_SMALL:
7773 case FLASH_VENDOR_SST_LARGE:
7774 tp->nvram_jedecnum = JEDEC_SST;
7775 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7776 break;
7777 }
7778 }
7779 else {
7780 tp->nvram_jedecnum = JEDEC_ATMEL;
7781 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7782 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7783 }
7784}
7785
361b4ac2
MC		 7786static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7787{
7788 u32 nvcfg1;
7789
7790 nvcfg1 = tr32(NVRAM_CFG1);
7791
e6af301b
MC		 7792 /* NVRAM protection for TPM */
7793 if (nvcfg1 & (1 << 27))
7794 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7795
361b4ac2
MC		 7796 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7797 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7798 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
7799 tp->nvram_jedecnum = JEDEC_ATMEL;
7800 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7801 break;
7802 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
7803 tp->nvram_jedecnum = JEDEC_ATMEL;
7804 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7805 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7806 break;
7807 case FLASH_5752VENDOR_ST_M45PE10:
7808 case FLASH_5752VENDOR_ST_M45PE20:
7809 case FLASH_5752VENDOR_ST_M45PE40:
7810 tp->nvram_jedecnum = JEDEC_ST;
7811 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7812 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7813 break;
7814 }
7815
7816 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
7817 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
7818 case FLASH_5752PAGE_SIZE_256:
7819 tp->nvram_pagesize = 256;
7820 break;
7821 case FLASH_5752PAGE_SIZE_512:
7822 tp->nvram_pagesize = 512;
7823 break;
7824 case FLASH_5752PAGE_SIZE_1K:
7825 tp->nvram_pagesize = 1024;
7826 break;
7827 case FLASH_5752PAGE_SIZE_2K:
7828 tp->nvram_pagesize = 2048;
7829 break;
7830 case FLASH_5752PAGE_SIZE_4K:
7831 tp->nvram_pagesize = 4096;
7832 break;
7833 case FLASH_5752PAGE_SIZE_264:
7834 tp->nvram_pagesize = 264;
7835 break;
7836 }
7837 }
7838 else {
7839 /* For eeprom, set pagesize to maximum eeprom size */
7840 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7841
7842 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7843 tw32(NVRAM_CFG1, nvcfg1);
7844 }
7845}
7846
1da177e4
LT		 7847/* Chips other than 5700/5701 use the NVRAM for fetching info. */
7848static void __devinit tg3_nvram_init(struct tg3 *tp)
7849{
7850 int j;
7851
7852 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
7853 return;
7854
7855 tw32_f(GRC_EEPROM_ADDR,
7856 (EEPROM_ADDR_FSM_RESET |
7857 (EEPROM_DEFAULT_CLOCK_PERIOD <<
7858 EEPROM_ADDR_CLKPERD_SHIFT)));
7859
7860 /* XXX schedule_timeout() ... */
7861 for (j = 0; j < 100; j++)
7862 udelay(10);
7863
7864 /* Enable seeprom accesses. */
7865 tw32_f(GRC_LOCAL_CTRL,
7866 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
7867 udelay(100);
7868
7869 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
7870 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
7871 tp->tg3_flags |= TG3_FLAG_NVRAM;
7872
e6af301b 7873 tg3_enable_nvram_access(tp);
1da177e4 7874
361b4ac2
MC		 7875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7876 tg3_get_5752_nvram_info(tp);
7877 else
7878 tg3_get_nvram_info(tp);
7879
1da177e4
LT		 7880 tg3_get_nvram_size(tp);
7881
e6af301b 7882 tg3_disable_nvram_access(tp);
1da177e4
LT		 7883
7884 } else {
7885 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
7886
7887 tg3_get_eeprom_size(tp);
7888 }
7889}
7890
7891static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
7892 u32 offset, u32 *val)
7893{
7894 u32 tmp;
7895 int i;
7896
7897 if (offset > EEPROM_ADDR_ADDR_MASK ||
7898 (offset % 4) != 0)
7899 return -EINVAL;
7900
7901 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
7902 EEPROM_ADDR_DEVID_MASK |
7903 EEPROM_ADDR_READ);
7904 tw32(GRC_EEPROM_ADDR,
7905 tmp |
7906 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7907 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
7908 EEPROM_ADDR_ADDR_MASK) |
7909 EEPROM_ADDR_READ | EEPROM_ADDR_START);
7910
7911 for (i = 0; i < 10000; i++) {
7912 tmp = tr32(GRC_EEPROM_ADDR);
7913
7914 if (tmp & EEPROM_ADDR_COMPLETE)
7915 break;
7916 udelay(100);
7917 }
7918 if (!(tmp & EEPROM_ADDR_COMPLETE))
7919 return -EBUSY;
7920
7921 *val = tr32(GRC_EEPROM_DATA);
7922 return 0;
7923}
7924
7925#define NVRAM_CMD_TIMEOUT 10000
7926
7927static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
7928{
7929 int i;
7930
7931 tw32(NVRAM_CMD, nvram_cmd);
7932 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
7933 udelay(10);
7934 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
7935 udelay(10);
7936 break;
7937 }
7938 }
7939 if (i == NVRAM_CMD_TIMEOUT) {
7940 return -EBUSY;
7941 }
7942 return 0;
7943}
7944
7945static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7946{
7947 int ret;
7948
7949 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7950 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
7951 return -EINVAL;
7952 }
7953
7954 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
7955 return tg3_nvram_read_using_eeprom(tp, offset, val);
7956
7957 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
7958 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7959 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7960
7961 offset = ((offset / tp->nvram_pagesize) <<
7962 ATMEL_AT45DB0X1B_PAGE_POS) +
7963 (offset % tp->nvram_pagesize);
7964 }
7965
7966 if (offset > NVRAM_ADDR_MSK)
7967 return -EINVAL;
7968
7969 tg3_nvram_lock(tp);
7970
e6af301b 7971 tg3_enable_nvram_access(tp);
1da177e4
LT		 7972
7973 tw32(NVRAM_ADDR, offset);
7974 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
7975 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
7976
7977 if (ret == 0)
7978 *val = swab32(tr32(NVRAM_RDDATA));
7979
7980 tg3_nvram_unlock(tp);
7981
e6af301b 7982 tg3_disable_nvram_access(tp);
1da177e4
LT		 7983
7984 return ret;
7985}
7986
7987static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
7988 u32 offset, u32 len, u8 *buf)
7989{
7990 int i, j, rc = 0;
7991 u32 val;
7992
7993 for (i = 0; i < len; i += 4) {
7994 u32 addr, data;
7995
7996 addr = offset + i;
7997
7998 memcpy(&data, buf + i, 4);
7999
8000 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8001
8002 val = tr32(GRC_EEPROM_ADDR);
8003 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8004
8005 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8006 EEPROM_ADDR_READ);
8007 tw32(GRC_EEPROM_ADDR, val |
8008 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8009 (addr & EEPROM_ADDR_ADDR_MASK) |
8010 EEPROM_ADDR_START |
8011 EEPROM_ADDR_WRITE);
8012
8013 for (j = 0; j < 10000; j++) {
8014 val = tr32(GRC_EEPROM_ADDR);
8015
8016 if (val & EEPROM_ADDR_COMPLETE)
8017 break;
8018 udelay(100);
8019 }
8020 if (!(val & EEPROM_ADDR_COMPLETE)) {
8021 rc = -EBUSY;
8022 break;
8023 }
8024 }
8025
8026 return rc;
8027}
8028
8029/* offset and length are dword aligned */
8030static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8031 u8 *buf)
8032{
8033 int ret = 0;
8034 u32 pagesize = tp->nvram_pagesize;
8035 u32 pagemask = pagesize - 1;
8036 u32 nvram_cmd;
8037 u8 *tmp;
8038
8039 tmp = kmalloc(pagesize, GFP_KERNEL);
8040 if (tmp == NULL)
8041 return -ENOMEM;
8042
8043 while (len) {
8044 int j;
e6af301b 8045 u32 phy_addr, page_off, size;
1da177e4
LT		 8046
8047 phy_addr = offset & ~pagemask;
8048
8049 for (j = 0; j < pagesize; j += 4) {
8050 if ((ret = tg3_nvram_read(tp, phy_addr + j,
8051 (u32 *) (tmp + j))))
8052 break;
8053 }
8054 if (ret)
8055 break;
8056
8057 page_off = offset & pagemask;
8058 size = pagesize;
8059 if (len < size)
8060 size = len;
8061
8062 len -= size;
8063
8064 memcpy(tmp + page_off, buf, size);
8065
8066 offset = offset + (pagesize - page_off);
8067
e6af301b 8068 tg3_enable_nvram_access(tp);
1da177e4
LT		 8069
8070 /*
8071 * Before we can erase the flash page, we need
8072 * to issue a special "write enable" command.
8073 */
8074 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8075
8076 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8077 break;
8078
8079 /* Erase the target page */
8080 tw32(NVRAM_ADDR, phy_addr);
8081
8082 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8083 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8084
8085 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8086 break;
8087
8088 /* Issue another write enable to start the write. */
8089 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8090
8091 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8092 break;
8093
8094 for (j = 0; j < pagesize; j += 4) {
8095 u32 data;
8096
8097 data = *((u32 *) (tmp + j));
8098 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8099
8100 tw32(NVRAM_ADDR, phy_addr + j);
8101
8102 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8103 NVRAM_CMD_WR;
8104
8105 if (j == 0)
8106 nvram_cmd |= NVRAM_CMD_FIRST;
8107 else if (j == (pagesize - 4))
8108 nvram_cmd |= NVRAM_CMD_LAST;
8109
8110 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8111 break;
8112 }
8113 if (ret)
8114 break;
8115 }
8116
8117 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8118 tg3_nvram_exec_cmd(tp, nvram_cmd);
8119
8120 kfree(tmp);
8121
8122 return ret;
8123}
8124
8125/* offset and length are dword aligned */
8126static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8127 u8 *buf)
8128{
8129 int i, ret = 0;
8130
8131 for (i = 0; i < len; i += 4, offset += 4) {
8132 u32 data, page_off, phy_addr, nvram_cmd;
8133
8134 memcpy(&data, buf + i, 4);
8135 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8136
8137 page_off = offset % tp->nvram_pagesize;
8138
8139 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8140 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8141
8142 phy_addr = ((offset / tp->nvram_pagesize) <<
8143 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8144 }
8145 else {
8146 phy_addr = offset;
8147 }
8148
8149 tw32(NVRAM_ADDR, phy_addr);
8150
8151 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8152
8153 if ((page_off == 0) || (i == 0))
8154 nvram_cmd |= NVRAM_CMD_FIRST;
8155 else if (page_off == (tp->nvram_pagesize - 4))
8156 nvram_cmd |= NVRAM_CMD_LAST;
8157
8158 if (i == (len - 4))
8159 nvram_cmd |= NVRAM_CMD_LAST;
8160
8161 if ((tp->nvram_jedecnum == JEDEC_ST) &&
8162 (nvram_cmd & NVRAM_CMD_FIRST)) {
8163
8164 if ((ret = tg3_nvram_exec_cmd(tp,
8165 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8166 NVRAM_CMD_DONE)))
8167
8168 break;
8169 }
8170 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8171 /* We always do complete word writes to eeprom. */
8172 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8173 }
8174
8175 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8176 break;
8177 }
8178 return ret;
8179}
8180
8181/* offset and length are dword aligned */
8182static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8183{
8184 int ret;
8185
8186 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8187 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8188 return -EINVAL;
8189 }
8190
8191 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 8192 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8193 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 8194 udelay(40);
8195 }
8196
8197 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8198 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8199 }
8200 else {
8201 u32 grc_mode;
8202
8203 tg3_nvram_lock(tp);
8204
e6af301b
MC		 8205 tg3_enable_nvram_access(tp);
8206 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8207 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 8208 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 8209
8210 grc_mode = tr32(GRC_MODE);
8211 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8212
8213 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8214 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8215
8216 ret = tg3_nvram_write_block_buffered(tp, offset, len,
8217 buf);
8218 }
8219 else {
8220 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8221 buf);
8222 }
8223
8224 grc_mode = tr32(GRC_MODE);
8225 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8226
e6af301b 8227 tg3_disable_nvram_access(tp);
1da177e4
LT		 8228 tg3_nvram_unlock(tp);
8229 }
8230
8231 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 8232 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 8233 udelay(40);
8234 }
8235
8236 return ret;
8237}
8238
8239struct subsys_tbl_ent {
8240 u16 subsys_vendor, subsys_devid;
8241 u32 phy_id;
8242};
8243
8244static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8245 /* Broadcom boards. */
8246 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8247 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8248 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8249 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
8250 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8251 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8252 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
8253 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8254 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8255 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8256 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8257
8258 /* 3com boards. */
8259 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8260 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8261 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
8262 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8263 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8264
8265 /* DELL boards. */
8266 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8267 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8268 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8269 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8270
8271 /* Compaq boards. */
8272 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8273 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8274 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
8275 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8276 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8277
8278 /* IBM boards. */
8279 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8280};
8281
8282static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8283{
8284 int i;
8285
8286 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8287 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8288 tp->pdev->subsystem_vendor) &&
8289 (subsys_id_to_phy_id[i].subsys_devid ==
8290 tp->pdev->subsystem_device))
8291 return &subsys_id_to_phy_id[i];
8292 }
8293 return NULL;
8294}
8295
7d0c41ef
MC		 8296/* Since this function may be called in D3-hot power state during
8297 * tg3_init_one(), only config cycles are allowed.
8298 */
8299static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 8300{
1da177e4 8301 u32 val;
7d0c41ef
MC		 8302
8303 /* Make sure register accesses (indirect or otherwise)
8304 * will function correctly.
8305 */
8306 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8307 tp->misc_host_ctrl);
1da177e4
LT		 8308
8309 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 8310 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8311
1da177e4
LT		 8312 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8313 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8314 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 8315 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8316 int eeprom_phy_serdes = 0;
1da177e4
LT		 8317
8318 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8319 tp->nic_sram_data_cfg = nic_cfg;
8320
8321 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8322 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8323 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8324 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8325 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8326 (ver > 0) && (ver < 0x100))
8327 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8328
1da177e4
LT		 8329 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8330 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8331 eeprom_phy_serdes = 1;
8332
8333 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8334 if (nic_phy_id != 0) {
8335 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8336 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8337
8338 eeprom_phy_id = (id1 >> 16) << 10;
8339 eeprom_phy_id |= (id2 & 0xfc00) << 16;
8340 eeprom_phy_id |= (id2 & 0x03ff) << 0;
8341 } else
8342 eeprom_phy_id = 0;
8343
7d0c41ef
MC		 8344 tp->phy_id = eeprom_phy_id;
8345 if (eeprom_phy_serdes)
8346 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8347
cbf46853 8348 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8349 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8350 SHASTA_EXT_LED_MODE_MASK);
cbf46853 8351 else
1da177e4
LT		 8352 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8353
8354 switch (led_cfg) {
8355 default:
8356 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8357 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8358 break;
8359
8360 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8361 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8362 break;
8363
8364 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8365 tp->led_ctrl = LED_CTRL_MODE_MAC;
8366 break;
8367
8368 case SHASTA_EXT_LED_SHARED:
8369 tp->led_ctrl = LED_CTRL_MODE_SHARED;
8370 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8371 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
8372 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8373 LED_CTRL_MODE_PHY_2);
8374 break;
8375
8376 case SHASTA_EXT_LED_MAC:
8377 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
8378 break;
8379
8380 case SHASTA_EXT_LED_COMBO:
8381 tp->led_ctrl = LED_CTRL_MODE_COMBO;
8382 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
8383 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8384 LED_CTRL_MODE_PHY_2);
8385 break;
8386
8387 };
8388
8389 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8390 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
8391 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
8392 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8393
8394 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8395 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8396 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
8397 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
8398
8399 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8400 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 8401 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8402 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
8403 }
8404 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
8405 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
8406
8407 if (cfg2 & (1 << 17))
8408 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
8409
8410 /* serdes signal pre-emphasis in register 0x590 set by */
8411 /* bootcode if bit 18 is set */
8412 if (cfg2 & (1 << 18))
8413 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8414 }
7d0c41ef
MC		 8415}
8416
8417static int __devinit tg3_phy_probe(struct tg3 *tp)
8418{
8419 u32 hw_phy_id_1, hw_phy_id_2;
8420 u32 hw_phy_id, hw_phy_id_masked;
8421 int err;
1da177e4
LT		 8422
8423 /* Reading the PHY ID register can conflict with ASF
8424 * firwmare access to the PHY hardware.
8425 */
8426 err = 0;
8427 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
8428 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
8429 } else {
8430 /* Now read the physical PHY_ID from the chip and verify
8431 * that it is sane. If it doesn't look good, we fall back
8432 * to either the hard-coded table based PHY_ID and failing
8433 * that the value found in the eeprom area.
8434 */
8435 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
8436 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
8437
8438 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
8439 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
8440 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
8441
8442 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
8443 }
8444
8445 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
8446 tp->phy_id = hw_phy_id;
8447 if (hw_phy_id_masked == PHY_ID_BCM8002)
8448 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8449 } else {
7d0c41ef
MC		 8450 if (tp->phy_id != PHY_ID_INVALID) {
8451 /* Do nothing, phy ID already set up in
8452 * tg3_get_eeprom_hw_cfg().
8453 */
1da177e4
LT		 8454 } else {
8455 struct subsys_tbl_ent *p;
8456
8457 /* No eeprom signature? Try the hardcoded
8458 * subsys device table.
8459 */
8460 p = lookup_by_subsys(tp);
8461 if (!p)
8462 return -ENODEV;
8463
8464 tp->phy_id = p->phy_id;
8465 if (!tp->phy_id ||
8466 tp->phy_id == PHY_ID_BCM8002)
8467 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8468 }
8469 }
8470
8471 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8472 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8473 u32 bmsr, adv_reg, tg3_ctrl;
8474
8475 tg3_readphy(tp, MII_BMSR, &bmsr);
8476 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
8477 (bmsr & BMSR_LSTATUS))
8478 goto skip_phy_reset;
8479
8480 err = tg3_phy_reset(tp);
8481 if (err)
8482 return err;
8483
8484 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
8485 ADVERTISE_100HALF | ADVERTISE_100FULL |
8486 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
8487 tg3_ctrl = 0;
8488 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
8489 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
8490 MII_TG3_CTRL_ADV_1000_FULL);
8491 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8492 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
8493 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
8494 MII_TG3_CTRL_ENABLE_AS_MASTER);
8495 }
8496
8497 if (!tg3_copper_is_advertising_all(tp)) {
8498 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8499
8500 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8501 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8502
8503 tg3_writephy(tp, MII_BMCR,
8504 BMCR_ANENABLE | BMCR_ANRESTART);
8505 }
8506 tg3_phy_set_wirespeed(tp);
8507
8508 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8509 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8510 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8511 }
8512
8513skip_phy_reset:
8514 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8515 err = tg3_init_5401phy_dsp(tp);
8516 if (err)
8517 return err;
8518 }
8519
8520 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
8521 err = tg3_init_5401phy_dsp(tp);
8522 }
8523
1da177e4
LT		 8524 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8525 tp->link_config.advertising =
8526 (ADVERTISED_1000baseT_Half |
8527 ADVERTISED_1000baseT_Full |
8528 ADVERTISED_Autoneg |
8529 ADVERTISED_FIBRE);
8530 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8531 tp->link_config.advertising &=
8532 ~(ADVERTISED_1000baseT_Half |
8533 ADVERTISED_1000baseT_Full);
8534
8535 return err;
8536}
8537
8538static void __devinit tg3_read_partno(struct tg3 *tp)
8539{
8540 unsigned char vpd_data[256];
8541 int i;
8542
8543 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8544 /* Sun decided not to put the necessary bits in the
8545 * NVRAM of their onboard tg3 parts :(
8546 */
8547 strcpy(tp->board_part_number, "Sun 570X");
8548 return;
8549 }
8550
8551 for (i = 0; i < 256; i += 4) {
8552 u32 tmp;
8553
8554 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
8555 goto out_not_found;
8556
8557 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
8558 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
8559 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
8560 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
8561 }
8562
8563 /* Now parse and find the part number. */
8564 for (i = 0; i < 256; ) {
8565 unsigned char val = vpd_data[i];
8566 int block_end;
8567
8568 if (val == 0x82 || val == 0x91) {
8569 i = (i + 3 +
8570 (vpd_data[i + 1] +
8571 (vpd_data[i + 2] << 8)));
8572 continue;
8573 }
8574
8575 if (val != 0x90)
8576 goto out_not_found;
8577
8578 block_end = (i + 3 +
8579 (vpd_data[i + 1] +
8580 (vpd_data[i + 2] << 8)));
8581 i += 3;
8582 while (i < block_end) {
8583 if (vpd_data[i + 0] == 'P' &&
8584 vpd_data[i + 1] == 'N') {
8585 int partno_len = vpd_data[i + 2];
8586
8587 if (partno_len > 24)
8588 goto out_not_found;
8589
8590 memcpy(tp->board_part_number,
8591 &vpd_data[i + 3],
8592 partno_len);
8593
8594 /* Success. */
8595 return;
8596 }
8597 }
8598
8599 /* Part number not found. */
8600 goto out_not_found;
8601 }
8602
8603out_not_found:
8604 strcpy(tp->board_part_number, "none");
8605}
8606
8607#ifdef CONFIG_SPARC64
8608static int __devinit tg3_is_sun_570X(struct tg3 *tp)
8609{
8610 struct pci_dev *pdev = tp->pdev;
8611 struct pcidev_cookie *pcp = pdev->sysdata;
8612
8613 if (pcp != NULL) {
8614 int node = pcp->prom_node;
8615 u32 venid;
8616 int err;
8617
8618 err = prom_getproperty(node, "subsystem-vendor-id",
8619 (char *) &venid, sizeof(venid));
8620 if (err == 0 || err == -1)
8621 return 0;
8622 if (venid == PCI_VENDOR_ID_SUN)
8623 return 1;
8624 }
8625 return 0;
8626}
8627#endif
8628
8629static int __devinit tg3_get_invariants(struct tg3 *tp)
8630{
8631 static struct pci_device_id write_reorder_chipsets[] = {
8632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8633 PCI_DEVICE_ID_INTEL_82801AA_8) },
8634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8635 PCI_DEVICE_ID_INTEL_82801AB_8) },
8636 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8637 PCI_DEVICE_ID_INTEL_82801BA_11) },
8638 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8639 PCI_DEVICE_ID_INTEL_82801BA_6) },
8640 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
8641 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
8642 { },
8643 };
8644 u32 misc_ctrl_reg;
8645 u32 cacheline_sz_reg;
8646 u32 pci_state_reg, grc_misc_cfg;
8647 u32 val;
8648 u16 pci_cmd;
8649 int err;
8650
8651#ifdef CONFIG_SPARC64
8652 if (tg3_is_sun_570X(tp))
8653 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
8654#endif
8655
8656 /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8657 * reordering to the mailbox registers done by the host
8658 * controller can cause major troubles. We read back from
8659 * every mailbox register write to force the writes to be
8660 * posted to the chip in order.
8661 */
8662 if (pci_dev_present(write_reorder_chipsets))
8663 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
8664
8665 /* Force memory write invalidate off. If we leave it on,
8666 * then on 5700_BX chips we have to enable a workaround.
8667 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8668 * to match the cacheline size. The Broadcom driver have this
8669 * workaround but turns MWI off all the times so never uses
8670 * it. This seems to suggest that the workaround is insufficient.
8671 */
8672 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8673 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8674 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8675
8676 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8677 * has the register indirect write enable bit set before
8678 * we try to access any of the MMIO registers. It is also
8679 * critical that the PCI-X hw workaround situation is decided
8680 * before that as well.
8681 */
8682 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8683 &misc_ctrl_reg);
8684
8685 tp->pci_chip_rev_id = (misc_ctrl_reg >>
8686 MISC_HOST_CTRL_CHIPREV_SHIFT);
8687
ff645bec
MC		 8688 /* Wrong chip ID in 5752 A0. This code can be removed later
8689 * as A0 is not in production.
8690 */
8691 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8692 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8693
1da177e4
LT		 8694 /* Initialize misc host control in PCI block. */
8695 tp->misc_host_ctrl |= (misc_ctrl_reg &
8696 MISC_HOST_CTRL_CHIPREV);
8697 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8698 tp->misc_host_ctrl);
8699
8700 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8701 &cacheline_sz_reg);
8702
8703 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
8704 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
8705 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
8706 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
8707
6708e5cc 8708 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
ff645bec 8709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6708e5cc
JL		 8710 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8711
1b440c56
JL		 8712 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
8713 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
8714 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
8715
bb7064dc 8716 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8717 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8718
8719 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8720 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8721
8722 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8723 tp->pci_lat_timer < 64) {
8724 tp->pci_lat_timer = 64;
8725
8726 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
8727 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
8728 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
8729 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
8730
8731 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8732 cacheline_sz_reg);
8733 }
8734
8735 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8736 &pci_state_reg);
8737
8738 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8739 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8740
8741 /* If this is a 5700 BX chipset, and we are in PCI-X
8742 * mode, enable register write workaround.
8743 *
8744 * The workaround is to use indirect register accesses
8745 * for all chip writes not to mailbox registers.
8746 */
8747 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8748 u32 pm_reg;
8749 u16 pci_cmd;
8750
8751 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8752
8753 /* The chip can have it's power management PCI config
8754 * space registers clobbered due to this bug.
8755 * So explicitly force the chip into D0 here.
8756 */
8757 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8758 &pm_reg);
8759 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8760 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8761 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8762 pm_reg);
8763
8764 /* Also, force SERR#/PERR# in PCI command. */
8765 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8766 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8767 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8768 }
8769 }
8770
8771 /* Back to back register writes can cause problems on this chip,
8772 * the workaround is to read back all reg writes except those to
8773 * mailbox regs. See tg3_write_indirect_reg32().
8774 *
8775 * PCI Express 5750_A0 rev chips need this workaround too.
8776 */
8777 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8778 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8779 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8780 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8781
8782 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8783 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8784 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8785 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8786
8787 /* Chip-specific fixup from Broadcom driver */
8788 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8789 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8790 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8791 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8792 }
8793
7d0c41ef
MC		 8794 /* Get eeprom hw config before calling tg3_set_power_state().
8795 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8796 * determined before calling tg3_set_power_state() so that
8797 * we know whether or not to switch out of Vaux power.
8798 * When the flag is set, it means that GPIO1 is used for eeprom
8799 * write protect and also implies that it is a LOM where GPIOs
8800 * are not used to switch power.
8801 */
8802 tg3_get_eeprom_hw_cfg(tp);
8803
314fba34
MC		 8804 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8805 * GPIO1 driven high will bring 5700's external PHY out of reset.
8806 * It is also used as eeprom write protect on LOMs.
8807 */
8808 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
8809 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8810 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
8811 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8812 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 8813 /* Unused GPIO3 must be driven as output on 5752 because there
8814 * are no pull-up resistors on unused GPIO pins.
8815 */
8816 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8817 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 8818
1da177e4
LT		 8819 /* Force the chip into D0. */
8820 err = tg3_set_power_state(tp, 0);
8821 if (err) {
8822 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
8823 pci_name(tp->pdev));
8824 return err;
8825 }
8826
8827 /* 5700 B0 chips do not support checksumming correctly due
8828 * to hardware bugs.
8829 */
8830 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
8831 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
8832
8833 /* Pseudo-header checksum is done by hardware logic and not
8834 * the offload processers, so make the chip do the pseudo-
8835 * header checksums on receive. For transmit it is more
8836 * convenient to do the pseudo-header checksum in software
8837 * as Linux does that on transmit for us in all cases.
8838 */
8839 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
8840 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
8841
8842 /* Derive initial jumbo mode from MTU assigned in
8843 * ether_setup() via the alloc_etherdev() call
8844 */
8845 if (tp->dev->mtu > ETH_DATA_LEN)
8846 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
8847
8848 /* Determine WakeOnLan speed to use. */
8849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8850 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8851 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
8852 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
8853 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
8854 } else {
8855 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
8856 }
8857
8858 /* A few boards don't want Ethernet@WireSpeed phy feature */
8859 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8860 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
8861 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
8862 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
8863 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
8864
8865 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
8866 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
8867 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
8868 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
8869 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
8870
bb7064dc 8871 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
1da177e4
LT		 8872 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
8873
1da177e4 8874 tp->coalesce_mode = 0;
1da177e4
LT		 8875 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
8876 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
8877 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
8878
8879 /* Initialize MAC MI mode, polling disabled. */
8880 tw32_f(MAC_MI_MODE, tp->mi_mode);
8881 udelay(80);
8882
8883 /* Initialize data/descriptor byte/word swapping. */
8884 val = tr32(GRC_MODE);
8885 val &= GRC_MODE_HOST_STACKUP;
8886 tw32(GRC_MODE, val | tp->grc_mode);
8887
8888 tg3_switch_clocks(tp);
8889
8890 /* Clear this out for sanity. */
8891 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8892
8893 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8894 &pci_state_reg);
8895 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
8896 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
8897 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
8898
8899 if (chiprevid == CHIPREV_ID_5701_A0 ||
8900 chiprevid == CHIPREV_ID_5701_B0 ||
8901 chiprevid == CHIPREV_ID_5701_B2 ||
8902 chiprevid == CHIPREV_ID_5701_B5) {
8903 void __iomem *sram_base;
8904
8905 /* Write some dummy words into the SRAM status block
8906 * area, see if it reads back correctly. If the return
8907 * value is bad, force enable the PCIX workaround.
8908 */
8909 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
8910
8911 writel(0x00000000, sram_base);
8912 writel(0x00000000, sram_base + 4);
8913 writel(0xffffffff, sram_base + 4);
8914 if (readl(sram_base) != 0x00000000)
8915 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8916 }
8917 }
8918
8919 udelay(50);
8920 tg3_nvram_init(tp);
8921
8922 grc_misc_cfg = tr32(GRC_MISC_CFG);
8923 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
8924
8925 /* Broadcom's driver says that CIOBE multisplit has a bug */
8926#if 0
8927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8928 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
8929 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
8930 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
8931 }
8932#endif
8933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8934 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
8935 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
8936 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
8937
fac9b83e
DM		 8938 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8939 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
8940 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
8941 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
8942 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
8943 HOSTCC_MODE_CLRTICK_TXBD);
8944
8945 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
8946 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8947 tp->misc_host_ctrl);
8948 }
8949
1da177e4
LT		 8950 /* these are limited to 10/100 only */
8951 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8952 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
8953 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8954 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8955 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
8956 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
8957 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
8958 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8959 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
8960 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
8961 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
8962
8963 err = tg3_phy_probe(tp);
8964 if (err) {
8965 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
8966 pci_name(tp->pdev), err);
8967 /* ... but do not return immediately ... */
8968 }
8969
8970 tg3_read_partno(tp);
8971
8972 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8973 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8974 } else {
8975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8976 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
8977 else
8978 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8979 }
8980
8981 /* 5700 {AX,BX} chips have a broken status block link
8982 * change bit implementation, so we must use the
8983 * status register in those cases.
8984 */
8985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8986 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
8987 else
8988 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
8989
8990 /* The led_ctrl is set during tg3_phy_probe, here we might
8991 * have to force the link status polling mechanism based
8992 * upon subsystem IDs.
8993 */
8994 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
8995 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8996 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
8997 TG3_FLAG_USE_LINKCHG_REG);
8998 }
8999
9000 /* For all SERDES we poll the MAC status register. */
9001 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9002 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9003 else
9004 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9005
9006 /* 5700 BX chips need to have their TX producer index mailboxes
9007 * written twice to workaround a bug.
9008 */
9009 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9010 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9011 else
9012 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
9013
9014 /* It seems all chips can get confused if TX buffers
9015 * straddle the 4GB address boundary in some cases.
9016 */
9017 tp->dev->hard_start_xmit = tg3_start_xmit;
9018
9019 tp->rx_offset = 2;
9020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9021 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9022 tp->rx_offset = 0;
9023
9024 /* By default, disable wake-on-lan. User can change this
9025 * using ETHTOOL_SWOL.
9026 */
9027 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9028
9029 return err;
9030}
9031
9032#ifdef CONFIG_SPARC64
9033static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9034{
9035 struct net_device *dev = tp->dev;
9036 struct pci_dev *pdev = tp->pdev;
9037 struct pcidev_cookie *pcp = pdev->sysdata;
9038
9039 if (pcp != NULL) {
9040 int node = pcp->prom_node;
9041
9042 if (prom_getproplen(node, "local-mac-address") == 6) {
9043 prom_getproperty(node, "local-mac-address",
9044 dev->dev_addr, 6);
9045 return 0;
9046 }
9047 }
9048 return -ENODEV;
9049}
9050
9051static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9052{
9053 struct net_device *dev = tp->dev;
9054
9055 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9056 return 0;
9057}
9058#endif
9059
9060static int __devinit tg3_get_device_address(struct tg3 *tp)
9061{
9062 struct net_device *dev = tp->dev;
9063 u32 hi, lo, mac_offset;
9064
9065#ifdef CONFIG_SPARC64
9066 if (!tg3_get_macaddr_sparc(tp))
9067 return 0;
9068#endif
9069
9070 mac_offset = 0x7c;
9071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9072 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
9073 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9074 mac_offset = 0xcc;
9075 if (tg3_nvram_lock(tp))
9076 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9077 else
9078 tg3_nvram_unlock(tp);
9079 }
9080
9081 /* First try to get it from MAC address mailbox. */
9082 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9083 if ((hi >> 16) == 0x484b) {
9084 dev->dev_addr[0] = (hi >> 8) & 0xff;
9085 dev->dev_addr[1] = (hi >> 0) & 0xff;
9086
9087 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9088 dev->dev_addr[2] = (lo >> 24) & 0xff;
9089 dev->dev_addr[3] = (lo >> 16) & 0xff;
9090 dev->dev_addr[4] = (lo >> 8) & 0xff;
9091 dev->dev_addr[5] = (lo >> 0) & 0xff;
9092 }
9093 /* Next, try NVRAM. */
9094 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9095 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9096 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9097 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9098 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9099 dev->dev_addr[2] = ((lo >> 0) & 0xff);
9100 dev->dev_addr[3] = ((lo >> 8) & 0xff);
9101 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9102 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9103 }
9104 /* Finally just fetch it out of the MAC control regs. */
9105 else {
9106 hi = tr32(MAC_ADDR_0_HIGH);
9107 lo = tr32(MAC_ADDR_0_LOW);
9108
9109 dev->dev_addr[5] = lo & 0xff;
9110 dev->dev_addr[4] = (lo >> 8) & 0xff;
9111 dev->dev_addr[3] = (lo >> 16) & 0xff;
9112 dev->dev_addr[2] = (lo >> 24) & 0xff;
9113 dev->dev_addr[1] = hi & 0xff;
9114 dev->dev_addr[0] = (hi >> 8) & 0xff;
9115 }
9116
9117 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9118#ifdef CONFIG_SPARC64
9119 if (!tg3_get_default_macaddr_sparc(tp))
9120 return 0;
9121#endif
9122 return -EINVAL;
9123 }
9124 return 0;
9125}
9126
59e6b434
DM		 9127#define BOUNDARY_SINGLE_CACHELINE 1
9128#define BOUNDARY_MULTI_CACHELINE 2
9129
9130static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9131{
9132 int cacheline_size;
9133 u8 byte;
9134 int goal;
9135
9136 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9137 if (byte == 0)
9138 cacheline_size = 1024;
9139 else
9140 cacheline_size = (int) byte * 4;
9141
9142 /* On 5703 and later chips, the boundary bits have no
9143 * effect.
9144 */
9145 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9146 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9147 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9148 goto out;
9149
9150#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9151 goal = BOUNDARY_MULTI_CACHELINE;
9152#else
9153#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9154 goal = BOUNDARY_SINGLE_CACHELINE;
9155#else
9156 goal = 0;
9157#endif
9158#endif
9159
9160 if (!goal)
9161 goto out;
9162
9163 /* PCI controllers on most RISC systems tend to disconnect
9164 * when a device tries to burst across a cache-line boundary.
9165 * Therefore, letting tg3 do so just wastes PCI bandwidth.
9166 *
9167 * Unfortunately, for PCI-E there are only limited
9168 * write-side controls for this, and thus for reads
9169 * we will still get the disconnects. We'll also waste
9170 * these PCI cycles for both read and write for chips
9171 * other than 5700 and 5701 which do not implement the
9172 * boundary bits.
9173 */
9174 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9175 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9176 switch (cacheline_size) {
9177 case 16:
9178 case 32:
9179 case 64:
9180 case 128:
9181 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9182 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9183 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9184 } else {
9185 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9186 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9187 }
9188 break;
9189
9190 case 256:
9191 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9192 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9193 break;
9194
9195 default:
9196 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9197 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9198 break;
9199 };
9200 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9201 switch (cacheline_size) {
9202 case 16:
9203 case 32:
9204 case 64:
9205 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9206 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9207 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9208 break;
9209 }
9210 /* fallthrough */
9211 case 128:
9212 default:
9213 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9214 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9215 break;
9216 };
9217 } else {
9218 switch (cacheline_size) {
9219 case 16:
9220 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9221 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9222 DMA_RWCTRL_WRITE_BNDRY_16);
9223 break;
9224 }
9225 /* fallthrough */
9226 case 32:
9227 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9228 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9229 DMA_RWCTRL_WRITE_BNDRY_32);
9230 break;
9231 }
9232 /* fallthrough */
9233 case 64:
9234 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9235 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9236 DMA_RWCTRL_WRITE_BNDRY_64);
9237 break;
9238 }
9239 /* fallthrough */
9240 case 128:
9241 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9242 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9243 DMA_RWCTRL_WRITE_BNDRY_128);
9244 break;
9245 }
9246 /* fallthrough */
9247 case 256:
9248 val |= (DMA_RWCTRL_READ_BNDRY_256 |
9249 DMA_RWCTRL_WRITE_BNDRY_256);
9250 break;
9251 case 512:
9252 val |= (DMA_RWCTRL_READ_BNDRY_512 |
9253 DMA_RWCTRL_WRITE_BNDRY_512);
9254 break;
9255 case 1024:
9256 default:
9257 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
9258 DMA_RWCTRL_WRITE_BNDRY_1024);
9259 break;
9260 };
9261 }
9262
9263out:
9264 return val;
9265}
9266
1da177e4
LT		 9267static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
9268{
9269 struct tg3_internal_buffer_desc test_desc;
9270 u32 sram_dma_descs;
9271 int i, ret;
9272
9273 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
9274
9275 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
9276 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
9277 tw32(RDMAC_STATUS, 0);
9278 tw32(WDMAC_STATUS, 0);
9279
9280 tw32(BUFMGR_MODE, 0);
9281 tw32(FTQ_RESET, 0);
9282
9283 test_desc.addr_hi = ((u64) buf_dma) >> 32;
9284 test_desc.addr_lo = buf_dma & 0xffffffff;
9285 test_desc.nic_mbuf = 0x00002100;
9286 test_desc.len = size;
9287
9288 /*
9289 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
9290 * the *second* time the tg3 driver was getting loaded after an
9291 * initial scan.
9292 *
9293 * Broadcom tells me:
9294 * ...the DMA engine is connected to the GRC block and a DMA
9295 * reset may affect the GRC block in some unpredictable way...
9296 * The behavior of resets to individual blocks has not been tested.
9297 *
9298 * Broadcom noted the GRC reset will also reset all sub-components.
9299 */
9300 if (to_device) {
9301 test_desc.cqid_sqid = (13 << 8) | 2;
9302
9303 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
9304 udelay(40);
9305 } else {
9306 test_desc.cqid_sqid = (16 << 8) | 7;
9307
9308 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
9309 udelay(40);
9310 }
9311 test_desc.flags = 0x00000005;
9312
9313 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
9314 u32 val;
9315
9316 val = *(((u32 *)&test_desc) + i);
9317 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
9318 sram_dma_descs + (i * sizeof(u32)));
9319 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
9320 }
9321 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
9322
9323 if (to_device) {
9324 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
9325 } else {
9326 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
9327 }
9328
9329 ret = -ENODEV;
9330 for (i = 0; i < 40; i++) {
9331 u32 val;
9332
9333 if (to_device)
9334 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
9335 else
9336 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
9337 if ((val & 0xffff) == sram_dma_descs) {
9338 ret = 0;
9339 break;
9340 }
9341
9342 udelay(100);
9343 }
9344
9345 return ret;
9346}
9347
ded7340d 9348#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 9349
9350static int __devinit tg3_test_dma(struct tg3 *tp)
9351{
9352 dma_addr_t buf_dma;
59e6b434 9353 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 9354 int ret;
9355
9356 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
9357 if (!buf) {
9358 ret = -ENOMEM;
9359 goto out_nofree;
9360 }
9361
9362 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
9363 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
9364
59e6b434 9365 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 9366
9367 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9368 /* DMA read watermark not used on PCIE */
9369 tp->dma_rwctrl |= 0x00180000;
9370 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 9371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
9372 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 9373 tp->dma_rwctrl |= 0x003f0000;
9374 else
9375 tp->dma_rwctrl |= 0x003f000f;
9376 } else {
9377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9379 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
9380
9381 if (ccval == 0x6 || ccval == 0x7)
9382 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
9383
59e6b434 9384 /* Set bit 23 to enable PCIX hw bug fix */
1da177e4
LT		 9385 tp->dma_rwctrl |= 0x009f0000;
9386 } else {
9387 tp->dma_rwctrl |= 0x001b000f;
9388 }
9389 }
9390
9391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9392 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9393 tp->dma_rwctrl &= 0xfffffff0;
9394
9395 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
9397 /* Remove this if it causes problems for some boards. */
9398 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
9399
9400 /* On 5700/5701 chips, we need to set this bit.
9401 * Otherwise the chip will issue cacheline transactions
9402 * to streamable DMA memory with not all the byte
9403 * enables turned on. This is an error on several
9404 * RISC PCI controllers, in particular sparc64.
9405 *
9406 * On 5703/5704 chips, this bit has been reassigned
9407 * a different meaning. In particular, it is used
9408 * on those chips to enable a PCI-X workaround.
9409 */
9410 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
9411 }
9412
9413 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9414
9415#if 0
9416 /* Unneeded, already done by tg3_get_invariants. */
9417 tg3_switch_clocks(tp);
9418#endif
9419
9420 ret = 0;
9421 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9422 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
9423 goto out;
9424
59e6b434
DM		 9425 /* It is best to perform DMA test with maximum write burst size
9426 * to expose the 5700/5701 write DMA bug.
9427 */
9428 saved_dma_rwctrl = tp->dma_rwctrl;
9429 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9430 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9431
1da177e4
LT		 9432 while (1) {
9433 u32 *p = buf, i;
9434
9435 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
9436 p[i] = i;
9437
9438 /* Send the buffer to the chip. */
9439 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
9440 if (ret) {
9441 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
9442 break;
9443 }
9444
9445#if 0
9446 /* validate data reached card RAM correctly. */
9447 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9448 u32 val;
9449 tg3_read_mem(tp, 0x2100 + (i*4), &val);
9450 if (le32_to_cpu(val) != p[i]) {
9451 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
9452 /* ret = -ENODEV here? */
9453 }
9454 p[i] = 0;
9455 }
9456#endif
9457 /* Now read it back. */
9458 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
9459 if (ret) {
9460 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
9461
9462 break;
9463 }
9464
9465 /* Verify it. */
9466 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9467 if (p[i] == i)
9468 continue;
9469
59e6b434
DM		 9470 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9471 DMA_RWCTRL_WRITE_BNDRY_16) {
9472 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 9473 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9474 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9475 break;
9476 } else {
9477 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
9478 ret = -ENODEV;
9479 goto out;
9480 }
9481 }
9482
9483 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
9484 /* Success. */
9485 ret = 0;
9486 break;
9487 }
9488 }
59e6b434
DM		 9489 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9490 DMA_RWCTRL_WRITE_BNDRY_16) {
9491 /* DMA test passed without adjusting DMA boundary,
9492 * just restore the calculated DMA boundary
9493 */
9494 tp->dma_rwctrl = saved_dma_rwctrl;
9495 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9496 }
1da177e4
LT		 9497
9498out:
9499 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
9500out_nofree:
9501 return ret;
9502}
9503
9504static void __devinit tg3_init_link_config(struct tg3 *tp)
9505{
9506 tp->link_config.advertising =
9507 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
9508 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
9509 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
9510 ADVERTISED_Autoneg | ADVERTISED_MII);
9511 tp->link_config.speed = SPEED_INVALID;
9512 tp->link_config.duplex = DUPLEX_INVALID;
9513 tp->link_config.autoneg = AUTONEG_ENABLE;
9514 netif_carrier_off(tp->dev);
9515 tp->link_config.active_speed = SPEED_INVALID;
9516 tp->link_config.active_duplex = DUPLEX_INVALID;
9517 tp->link_config.phy_is_low_power = 0;
9518 tp->link_config.orig_speed = SPEED_INVALID;
9519 tp->link_config.orig_duplex = DUPLEX_INVALID;
9520 tp->link_config.orig_autoneg = AUTONEG_INVALID;
9521}
9522
9523static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9524{
9525 tp->bufmgr_config.mbuf_read_dma_low_water =
9526 DEFAULT_MB_RDMA_LOW_WATER;
9527 tp->bufmgr_config.mbuf_mac_rx_low_water =
9528 DEFAULT_MB_MACRX_LOW_WATER;
9529 tp->bufmgr_config.mbuf_high_water =
9530 DEFAULT_MB_HIGH_WATER;
9531
9532 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9533 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9534 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9535 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9536 tp->bufmgr_config.mbuf_high_water_jumbo =
9537 DEFAULT_MB_HIGH_WATER_JUMBO;
9538
9539 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9540 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
9541}
9542
9543static char * __devinit tg3_phy_string(struct tg3 *tp)
9544{
9545 switch (tp->phy_id & PHY_ID_MASK) {
9546 case PHY_ID_BCM5400: return "5400";
9547 case PHY_ID_BCM5401: return "5401";
9548 case PHY_ID_BCM5411: return "5411";
9549 case PHY_ID_BCM5701: return "5701";
9550 case PHY_ID_BCM5703: return "5703";
9551 case PHY_ID_BCM5704: return "5704";
9552 case PHY_ID_BCM5705: return "5705";
9553 case PHY_ID_BCM5750: return "5750";
85e94ced 9554 case PHY_ID_BCM5752: return "5752";
1da177e4
LT		 9555 case PHY_ID_BCM8002: return "8002/serdes";
9556 case 0: return "serdes";
9557 default: return "unknown";
9558 };
9559}
9560
9561static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9562{
9563 struct pci_dev *peer;
9564 unsigned int func, devnr = tp->pdev->devfn & ~7;
9565
9566 for (func = 0; func < 8; func++) {
9567 peer = pci_get_slot(tp->pdev->bus, devnr | func);
9568 if (peer && peer != tp->pdev)
9569 break;
9570 pci_dev_put(peer);
9571 }
9572 if (!peer || peer == tp->pdev)
9573 BUG();
9574
9575 /*
9576 * We don't need to keep the refcount elevated; there's no way
9577 * to remove one half of this device without removing the other
9578 */
9579 pci_dev_put(peer);
9580
9581 return peer;
9582}
9583
15f9850d
DM		 9584static void __devinit tg3_init_coal(struct tg3 *tp)
9585{
9586 struct ethtool_coalesce *ec = &tp->coal;
9587
9588 memset(ec, 0, sizeof(*ec));
9589 ec->cmd = ETHTOOL_GCOALESCE;
9590 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9591 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9592 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9593 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9594 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9595 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9596 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9597 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9598 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9599
9600 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9601 HOSTCC_MODE_CLRTICK_TXBD)) {
9602 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9603 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9604 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9605 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9606 }
9607}
9608
1da177e4
LT		 9609static int __devinit tg3_init_one(struct pci_dev *pdev,
9610 const struct pci_device_id *ent)
9611{
9612 static int tg3_version_printed = 0;
9613 unsigned long tg3reg_base, tg3reg_len;
9614 struct net_device *dev;
9615 struct tg3 *tp;
9616 int i, err, pci_using_dac, pm_cap;
9617
9618 if (tg3_version_printed++ == 0)
9619 printk(KERN_INFO "%s", version);
9620
9621 err = pci_enable_device(pdev);
9622 if (err) {
9623 printk(KERN_ERR PFX "Cannot enable PCI device, "
9624 "aborting.\n");
9625 return err;
9626 }
9627
9628 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9629 printk(KERN_ERR PFX "Cannot find proper PCI device "
9630 "base address, aborting.\n");
9631 err = -ENODEV;
9632 goto err_out_disable_pdev;
9633 }
9634
9635 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9636 if (err) {
9637 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
9638 "aborting.\n");
9639 goto err_out_disable_pdev;
9640 }
9641
9642 pci_set_master(pdev);
9643
9644 /* Find power-management capability. */
9645 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9646 if (pm_cap == 0) {
9647 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
9648 "aborting.\n");
9649 err = -EIO;
9650 goto err_out_free_res;
9651 }
9652
9653 /* Configure DMA attributes. */
9654 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
9655 if (!err) {
9656 pci_using_dac = 1;
9657 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
9658 if (err < 0) {
9659 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
9660 "for consistent allocations\n");
9661 goto err_out_free_res;
9662 }
9663 } else {
9664 err = pci_set_dma_mask(pdev, 0xffffffffULL);
9665 if (err) {
9666 printk(KERN_ERR PFX "No usable DMA configuration, "
9667 "aborting.\n");
9668 goto err_out_free_res;
9669 }
9670 pci_using_dac = 0;
9671 }
9672
9673 tg3reg_base = pci_resource_start(pdev, 0);
9674 tg3reg_len = pci_resource_len(pdev, 0);
9675
9676 dev = alloc_etherdev(sizeof(*tp));
9677 if (!dev) {
9678 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
9679 err = -ENOMEM;
9680 goto err_out_free_res;
9681 }
9682
9683 SET_MODULE_OWNER(dev);
9684 SET_NETDEV_DEV(dev, &pdev->dev);
9685
9686 if (pci_using_dac)
9687 dev->features |= NETIF_F_HIGHDMA;
9688 dev->features |= NETIF_F_LLTX;
9689#if TG3_VLAN_TAG_USED
9690 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
9691 dev->vlan_rx_register = tg3_vlan_rx_register;
9692 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
9693#endif
9694
9695 tp = netdev_priv(dev);
9696 tp->pdev = pdev;
9697 tp->dev = dev;
9698 tp->pm_cap = pm_cap;
9699 tp->mac_mode = TG3_DEF_MAC_MODE;
9700 tp->rx_mode = TG3_DEF_RX_MODE;
9701 tp->tx_mode = TG3_DEF_TX_MODE;
9702 tp->mi_mode = MAC_MI_MODE_BASE;
9703 if (tg3_debug > 0)
9704 tp->msg_enable = tg3_debug;
9705 else
9706 tp->msg_enable = TG3_DEF_MSG_ENABLE;
9707
9708 /* The word/byte swap controls here control register access byte
9709 * swapping. DMA data byte swapping is controlled in the GRC_MODE
9710 * setting below.
9711 */
9712 tp->misc_host_ctrl =
9713 MISC_HOST_CTRL_MASK_PCI_INT |
9714 MISC_HOST_CTRL_WORD_SWAP |
9715 MISC_HOST_CTRL_INDIR_ACCESS |
9716 MISC_HOST_CTRL_PCISTATE_RW;
9717
9718 /* The NONFRM (non-frame) byte/word swap controls take effect
9719 * on descriptor entries, anything which isn't packet data.
9720 *
9721 * The StrongARM chips on the board (one for tx, one for rx)
9722 * are running in big-endian mode.
9723 */
9724 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
9725 GRC_MODE_WSWAP_NONFRM_DATA);
9726#ifdef __BIG_ENDIAN
9727 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
9728#endif
9729 spin_lock_init(&tp->lock);
9730 spin_lock_init(&tp->tx_lock);
9731 spin_lock_init(&tp->indirect_lock);
9732 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
9733
9734 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
9735 if (tp->regs == 0UL) {
9736 printk(KERN_ERR PFX "Cannot map device registers, "
9737 "aborting.\n");
9738 err = -ENOMEM;
9739 goto err_out_free_dev;
9740 }
9741
9742 tg3_init_link_config(tp);
9743
9744 tg3_init_bufmgr_config(tp);
9745
9746 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
9747 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
9748 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
9749
9750 dev->open = tg3_open;
9751 dev->stop = tg3_close;
9752 dev->get_stats = tg3_get_stats;
9753 dev->set_multicast_list = tg3_set_rx_mode;
9754 dev->set_mac_address = tg3_set_mac_addr;
9755 dev->do_ioctl = tg3_ioctl;
9756 dev->tx_timeout = tg3_tx_timeout;
9757 dev->poll = tg3_poll;
9758 dev->ethtool_ops = &tg3_ethtool_ops;
9759 dev->weight = 64;
9760 dev->watchdog_timeo = TG3_TX_TIMEOUT;
9761 dev->change_mtu = tg3_change_mtu;
9762 dev->irq = pdev->irq;
9763#ifdef CONFIG_NET_POLL_CONTROLLER
9764 dev->poll_controller = tg3_poll_controller;
9765#endif
9766
9767 err = tg3_get_invariants(tp);
9768 if (err) {
9769 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
9770 "aborting.\n");
9771 goto err_out_iounmap;
9772 }
9773
9774 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9775 tp->bufmgr_config.mbuf_read_dma_low_water =
9776 DEFAULT_MB_RDMA_LOW_WATER_5705;
9777 tp->bufmgr_config.mbuf_mac_rx_low_water =
9778 DEFAULT_MB_MACRX_LOW_WATER_5705;
9779 tp->bufmgr_config.mbuf_high_water =
9780 DEFAULT_MB_HIGH_WATER_5705;
9781 }
9782
9783#if TG3_TSO_SUPPORT != 0
9784 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
9785 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9786 }
9787 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9788 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9789 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
9790 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
9791 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9792 } else {
9793 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9794 }
9795
9796 /* TSO is off by default, user can enable using ethtool. */
9797#if 0
9798 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
9799 dev->features |= NETIF_F_TSO;
9800#endif
9801
9802#endif
9803
9804 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
9805 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
9806 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
9807 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
9808 tp->rx_pending = 63;
9809 }
9810
9811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9812 tp->pdev_peer = tg3_find_5704_peer(tp);
9813
9814 err = tg3_get_device_address(tp);
9815 if (err) {
9816 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
9817 "aborting.\n");
9818 goto err_out_iounmap;
9819 }
9820
9821 /*
9822 * Reset chip in case UNDI or EFI driver did not shutdown
9823 * DMA self test will enable WDMAC and we'll see (spurious)
9824 * pending DMA on the PCI bus at that point.
9825 */
9826 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
9827 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9828 pci_save_state(tp->pdev);
9829 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 9830 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 9831 }
9832
9833 err = tg3_test_dma(tp);
9834 if (err) {
9835 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
9836 goto err_out_iounmap;
9837 }
9838
9839 /* Tigon3 can do ipv4 only... and some chips have buggy
9840 * checksumming.
9841 */
9842 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
9843 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
9844 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9845 } else
9846 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9847
9848 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
9849 dev->features &= ~NETIF_F_HIGHDMA;
9850
9851 /* flow control autonegotiation is default behavior */
9852 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9853
15f9850d
DM		 9854 tg3_init_coal(tp);
9855
1da177e4
LT		 9856 err = register_netdev(dev);
9857 if (err) {
9858 printk(KERN_ERR PFX "Cannot register net device, "
9859 "aborting.\n");
9860 goto err_out_iounmap;
9861 }
9862
9863 pci_set_drvdata(pdev, dev);
9864
9865 /* Now that we have fully setup the chip, save away a snapshot
9866 * of the PCI config space. We need to restore this after
9867 * GRC_MISC_CFG core clock resets and some resume events.
9868 */
9869 pci_save_state(tp->pdev);
9870
9871 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
9872 dev->name,
9873 tp->board_part_number,
9874 tp->pci_chip_rev_id,
9875 tg3_phy_string(tp),
9876 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
9877 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
9878 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
9879 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
9880 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
9881 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
9882
9883 for (i = 0; i < 6; i++)
9884 printk("%2.2x%c", dev->dev_addr[i],
9885 i == 5 ? '\n' : ':');
9886
9887 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
9888 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
9889 "TSOcap[%d] \n",
9890 dev->name,
9891 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
9892 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
9893 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
9894 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
9895 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
9896 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
9897 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
59e6b434
DM		 9898 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
9899 dev->name, tp->dma_rwctrl);
1da177e4
LT		 9900
9901 return 0;
9902
9903err_out_iounmap:
9904 iounmap(tp->regs);
9905
9906err_out_free_dev:
9907 free_netdev(dev);
9908
9909err_out_free_res:
9910 pci_release_regions(pdev);
9911
9912err_out_disable_pdev:
9913 pci_disable_device(pdev);
9914 pci_set_drvdata(pdev, NULL);
9915 return err;
9916}
9917
9918static void __devexit tg3_remove_one(struct pci_dev *pdev)
9919{
9920 struct net_device *dev = pci_get_drvdata(pdev);
9921
9922 if (dev) {
9923 struct tg3 *tp = netdev_priv(dev);
9924
9925 unregister_netdev(dev);
9926 iounmap(tp->regs);
9927 free_netdev(dev);
9928 pci_release_regions(pdev);
9929 pci_disable_device(pdev);
9930 pci_set_drvdata(pdev, NULL);
9931 }
9932}
9933
9934static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
9935{
9936 struct net_device *dev = pci_get_drvdata(pdev);
9937 struct tg3 *tp = netdev_priv(dev);
9938 int err;
9939
9940 if (!netif_running(dev))
9941 return 0;
9942
9943 tg3_netif_stop(tp);
9944
9945 del_timer_sync(&tp->timer);
9946
9947 spin_lock_irq(&tp->lock);
9948 spin_lock(&tp->tx_lock);
9949 tg3_disable_ints(tp);
9950 spin_unlock(&tp->tx_lock);
9951 spin_unlock_irq(&tp->lock);
9952
9953 netif_device_detach(dev);
9954
9955 spin_lock_irq(&tp->lock);
9956 spin_lock(&tp->tx_lock);
944d980e 9957 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 9958 spin_unlock(&tp->tx_lock);
9959 spin_unlock_irq(&tp->lock);
9960
9961 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
9962 if (err) {
9963 spin_lock_irq(&tp->lock);
9964 spin_lock(&tp->tx_lock);
9965
9966 tg3_init_hw(tp);
9967
9968 tp->timer.expires = jiffies + tp->timer_offset;
9969 add_timer(&tp->timer);
9970
9971 netif_device_attach(dev);
9972 tg3_netif_start(tp);
9973
9974 spin_unlock(&tp->tx_lock);
9975 spin_unlock_irq(&tp->lock);
9976 }
9977
9978 return err;
9979}
9980
9981static int tg3_resume(struct pci_dev *pdev)
9982{
9983 struct net_device *dev = pci_get_drvdata(pdev);
9984 struct tg3 *tp = netdev_priv(dev);
9985 int err;
9986
9987 if (!netif_running(dev))
9988 return 0;
9989
9990 pci_restore_state(tp->pdev);
9991
9992 err = tg3_set_power_state(tp, 0);
9993 if (err)
9994 return err;
9995
9996 netif_device_attach(dev);
9997
9998 spin_lock_irq(&tp->lock);
9999 spin_lock(&tp->tx_lock);
10000
10001 tg3_init_hw(tp);
10002
10003 tp->timer.expires = jiffies + tp->timer_offset;
10004 add_timer(&tp->timer);
10005
10006 tg3_enable_ints(tp);
10007
10008 tg3_netif_start(tp);
10009
10010 spin_unlock(&tp->tx_lock);
10011 spin_unlock_irq(&tp->lock);
10012
10013 return 0;
10014}
10015
10016static struct pci_driver tg3_driver = {
10017 .name = DRV_MODULE_NAME,
10018 .id_table = tg3_pci_tbl,
10019 .probe = tg3_init_one,
10020 .remove = __devexit_p(tg3_remove_one),
10021 .suspend = tg3_suspend,
10022 .resume = tg3_resume
10023};
10024
10025static int __init tg3_init(void)
10026{
10027 return pci_module_init(&tg3_driver);
10028}
10029
10030static void __exit tg3_cleanup(void)
10031{
10032 pci_unregister_driver(&tg3_driver);
10033}
10034
10035module_init(tg3_init);
10036module_exit(tg3_cleanup);
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