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[CASSINI]: Convert to ethtool_ops
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
18#include <linux/config.h>
19
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
1da177e4
LT		 40
41#include <net/checksum.h>
42
43#include <asm/system.h>
44#include <asm/io.h>
45#include <asm/byteorder.h>
46#include <asm/uaccess.h>
47
48#ifdef CONFIG_SPARC64
49#include <asm/idprom.h>
50#include <asm/oplib.h>
51#include <asm/pbm.h>
52#endif
53
54#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
55#define TG3_VLAN_TAG_USED 1
56#else
57#define TG3_VLAN_TAG_USED 0
58#endif
59
60#ifdef NETIF_F_TSO
61#define TG3_TSO_SUPPORT 1
62#else
63#define TG3_TSO_SUPPORT 0
64#endif
65
66#include "tg3.h"
67
68#define DRV_MODULE_NAME "tg3"
69#define PFX DRV_MODULE_NAME ": "
c8a6c296
DM		 70#define DRV_MODULE_VERSION "3.41"
71#define DRV_MODULE_RELDATE "September 27, 2005"
1da177e4
LT		 72
73#define TG3_DEF_MAC_MODE 0
74#define TG3_DEF_RX_MODE 0
75#define TG3_DEF_TX_MODE 0
76#define TG3_DEF_MSG_ENABLE \
77 (NETIF_MSG_DRV | \
78 NETIF_MSG_PROBE | \
79 NETIF_MSG_LINK | \
80 NETIF_MSG_TIMER | \
81 NETIF_MSG_IFDOWN | \
82 NETIF_MSG_IFUP | \
83 NETIF_MSG_RX_ERR | \
84 NETIF_MSG_TX_ERR)
85
86/* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
88 */
89#define TG3_TX_TIMEOUT (5 * HZ)
90
91/* hardware minimum and maximum for a single frame's data payload */
92#define TG3_MIN_MTU 60
93#define TG3_MAX_MTU(tp) \
0f893dc6 94 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 95
96/* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
99 */
100#define TG3_RX_RING_SIZE 512
101#define TG3_DEF_RX_RING_PENDING 200
102#define TG3_RX_JUMBO_RING_SIZE 256
103#define TG3_DEF_RX_JUMBO_RING_PENDING 100
104
105/* Do not place this n-ring entries value into the tp struct itself,
106 * we really want to expose these constants to GCC so that modulo et
107 * al. operations are done with shifts and masks instead of with
108 * hw multiply/modulo instructions. Another solution would be to
109 * replace things like '% foo' with '& (foo - 1)'.
110 */
111#define TG3_RX_RCB_RING_SIZE(tp) \
112 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
113
114#define TG3_TX_RING_SIZE 512
115#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
116
117#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
118 TG3_RX_RING_SIZE)
119#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_JUMBO_RING_SIZE)
121#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
122 TG3_RX_RCB_RING_SIZE(tp))
123#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
124 TG3_TX_RING_SIZE)
1da177e4 125#define TX_BUFFS_AVAIL(TP) \
51b91468
MC		 126 ((TP)->tx_pending - \
127 (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
131#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
132
133/* minimum number of free TX descriptors required to wake up TX process */
134#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
135
136/* number of ETHTOOL_GSTATS u64's */
137#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
4cafd3f5
MC		 139#define TG3_NUM_TEST 6
140
1da177e4
LT		 141static char version[] __devinitdata =
142 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
143
144MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
145MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
146MODULE_LICENSE("GPL");
147MODULE_VERSION(DRV_MODULE_VERSION);
148
149static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
150module_param(tg3_debug, int, 0);
151MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
152
153static struct pci_device_id tg3_pci_tbl[] = {
154 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
156 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
158 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
160 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
162 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
164 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
166 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
168 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
170 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
172 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
174 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
176 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
178 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
180 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
182 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
184 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
186 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
188 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
190 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
192 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
194 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
196 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
198 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
200 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
202 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
206 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
208 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
210 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
6e9017a7 212 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
af2bcd97 213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
d8659255
XVP		 214 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 216 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
218 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
220 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
4cf78e4f
MC		 222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 226 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
228 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
232 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242 { 0, }
243};
244
245MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
247static struct {
248 const char string[ETH_GSTRING_LEN];
249} ethtool_stats_keys[TG3_NUM_STATS] = {
250 { "rx_octets" },
251 { "rx_fragments" },
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
255 { "rx_fcs_errors" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
262 { "rx_jabbers" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
276
277 { "tx_octets" },
278 { "tx_collisions" },
279
280 { "tx_xon_sent" },
281 { "tx_xoff_sent" },
282 { "tx_flow_control" },
283 { "tx_mac_errors" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
286 { "tx_deferred" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
307 { "tx_discards" },
308 { "tx_errors" },
309
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
312 { "rxbds_empty" },
313 { "rx_discards" },
314 { "rx_errors" },
315 { "rx_threshold_hit" },
316
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
320
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
323 { "nic_irqs" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
326};
327
4cafd3f5
MC		 328static struct {
329 const char string[ETH_GSTRING_LEN];
330} ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
337};
338
1da177e4
LT		 339static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
340{
6892914f
MC		 341 unsigned long flags;
342
343 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 344 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
345 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 346 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 347}
348
349static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
350{
351 writel(val, tp->regs + off);
352 readl(tp->regs + off);
1da177e4
LT		 353}
354
6892914f 355static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 356{
6892914f
MC		 357 unsigned long flags;
358 u32 val;
359
360 spin_lock_irqsave(&tp->indirect_lock, flags);
361 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
362 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
363 spin_unlock_irqrestore(&tp->indirect_lock, flags);
364 return val;
365}
366
367static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
368{
369 unsigned long flags;
370
371 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
372 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
373 TG3_64BIT_REG_LOW, val);
374 return;
375 }
376 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
377 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
378 TG3_64BIT_REG_LOW, val);
379 return;
1da177e4 380 }
6892914f
MC		 381
382 spin_lock_irqsave(&tp->indirect_lock, flags);
383 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
385 spin_unlock_irqrestore(&tp->indirect_lock, flags);
386
387 /* In indirect mode when disabling interrupts, we also need
388 * to clear the interrupt bit in the GRC local ctrl register.
389 */
390 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
391 (val == 0x1)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
393 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
394 }
395}
396
397static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
398{
399 unsigned long flags;
400 u32 val;
401
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406 return val;
407}
408
409static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
410{
411 tp->write32(tp, off, val);
412 if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
413 !(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32(tp, off); /* flush */
1da177e4
LT		 416}
417
09ee929c
MC		 418static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
419{
420 tp->write32_mbox(tp, off, val);
6892914f
MC		 421 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
422 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
423 tp->read32_mbox(tp, off);
09ee929c
MC		 424}
425
20094930 426static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 427{
428 void __iomem *mbox = tp->regs + off;
429 writel(val, mbox);
430 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
431 writel(val, mbox);
432 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
433 readl(mbox);
434}
435
20094930
MC		 436static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
437{
438 writel(val, tp->regs + off);
439}
1da177e4 440
20094930
MC		 441static u32 tg3_read32(struct tg3 *tp, u32 off)
442{
443 return (readl(tp->regs + off));
444}
445
446#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 447#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 448#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
449#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 450#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 451
452#define tw32(reg,val) tp->write32(tp, reg, val)
1da177e4 453#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
20094930 454#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 455
456static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
457{
6892914f
MC		 458 unsigned long flags;
459
460 spin_lock_irqsave(&tp->indirect_lock, flags);
1da177e4
LT		 461 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
462 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
463
464 /* Always leave this as zero. */
465 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
6892914f 466 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 467}
468
469static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
470{
6892914f
MC		 471 unsigned long flags;
472
473 spin_lock_irqsave(&tp->indirect_lock, flags);
1da177e4
LT		 474 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
475 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
476
477 /* Always leave this as zero. */
478 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
6892914f 479 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 480}
481
482static void tg3_disable_ints(struct tg3 *tp)
483{
484 tw32(TG3PCI_MISC_HOST_CTRL,
485 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 486 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 487}
488
489static inline void tg3_cond_int(struct tg3 *tp)
490{
38f3843e
MC		 491 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
492 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4
LT		 493 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
494}
495
496static void tg3_enable_ints(struct tg3 *tp)
497{
bbe832c0
MC		 498 tp->irq_sync = 0;
499 wmb();
500
1da177e4
LT		 501 tw32(TG3PCI_MISC_HOST_CTRL,
502 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 503 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
504 (tp->last_tag << 24));
1da177e4
LT		 505 tg3_cond_int(tp);
506}
507
04237ddd
MC		 508static inline unsigned int tg3_has_work(struct tg3 *tp)
509{
510 struct tg3_hw_status *sblk = tp->hw_status;
511 unsigned int work_exists = 0;
512
513 /* check for phy events */
514 if (!(tp->tg3_flags &
515 (TG3_FLAG_USE_LINKCHG_REG |
516 TG3_FLAG_POLL_SERDES))) {
517 if (sblk->status & SD_STATUS_LINK_CHG)
518 work_exists = 1;
519 }
520 /* check for RX/TX work to do */
521 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
522 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
523 work_exists = 1;
524
525 return work_exists;
526}
527
1da177e4 528/* tg3_restart_ints
04237ddd
MC		 529 * similar to tg3_enable_ints, but it accurately determines whether there
530 * is new work pending and can return without flushing the PIO write
531 * which reenables interrupts
1da177e4
LT		 532 */
533static void tg3_restart_ints(struct tg3 *tp)
534{
fac9b83e
DM		 535 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
536 tp->last_tag << 24);
1da177e4
LT		 537 mmiowb();
538
fac9b83e
DM		 539 /* When doing tagged status, this work check is unnecessary.
540 * The last_tag we write above tells the chip which piece of
541 * work we've completed.
542 */
543 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
544 tg3_has_work(tp))
04237ddd
MC		 545 tw32(HOSTCC_MODE, tp->coalesce_mode |
546 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 547}
548
549static inline void tg3_netif_stop(struct tg3 *tp)
550{
bbe832c0 551 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 552 netif_poll_disable(tp->dev);
553 netif_tx_disable(tp->dev);
554}
555
556static inline void tg3_netif_start(struct tg3 *tp)
557{
558 netif_wake_queue(tp->dev);
559 /* NOTE: unconditional netif_wake_queue is only appropriate
560 * so long as all callers are assured to have free tx slots
561 * (such as after tg3_init_hw)
562 */
563 netif_poll_enable(tp->dev);
f47c11ee
DM		 564 tp->hw_status->status |= SD_STATUS_UPDATED;
565 tg3_enable_ints(tp);
1da177e4
LT		 566}
567
568static void tg3_switch_clocks(struct tg3 *tp)
569{
570 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
571 u32 orig_clock_ctrl;
572
4cf78e4f
MC		 573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
574 return;
575
1da177e4
LT		 576 orig_clock_ctrl = clock_ctrl;
577 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
578 CLOCK_CTRL_CLKRUN_OENABLE |
579 0x1f);
580 tp->pci_clock_ctrl = clock_ctrl;
581
582 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
583 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
584 tw32_f(TG3PCI_CLOCK_CTRL,
585 clock_ctrl | CLOCK_CTRL_625_CORE);
586 udelay(40);
587 }
588 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
589 tw32_f(TG3PCI_CLOCK_CTRL,
590 clock_ctrl |
591 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
592 udelay(40);
593 tw32_f(TG3PCI_CLOCK_CTRL,
594 clock_ctrl | (CLOCK_CTRL_ALTCLK));
595 udelay(40);
596 }
597 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
598 udelay(40);
599}
600
601#define PHY_BUSY_LOOPS 5000
602
603static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
604{
605 u32 frame_val;
606 unsigned int loops;
607 int ret;
608
609 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
610 tw32_f(MAC_MI_MODE,
611 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
612 udelay(80);
613 }
614
615 *val = 0x0;
616
617 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
618 MI_COM_PHY_ADDR_MASK);
619 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
620 MI_COM_REG_ADDR_MASK);
621 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
622
623 tw32_f(MAC_MI_COM, frame_val);
624
625 loops = PHY_BUSY_LOOPS;
626 while (loops != 0) {
627 udelay(10);
628 frame_val = tr32(MAC_MI_COM);
629
630 if ((frame_val & MI_COM_BUSY) == 0) {
631 udelay(5);
632 frame_val = tr32(MAC_MI_COM);
633 break;
634 }
635 loops -= 1;
636 }
637
638 ret = -EBUSY;
639 if (loops != 0) {
640 *val = frame_val & MI_COM_DATA_MASK;
641 ret = 0;
642 }
643
644 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
645 tw32_f(MAC_MI_MODE, tp->mi_mode);
646 udelay(80);
647 }
648
649 return ret;
650}
651
652static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
653{
654 u32 frame_val;
655 unsigned int loops;
656 int ret;
657
658 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
659 tw32_f(MAC_MI_MODE,
660 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
661 udelay(80);
662 }
663
664 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
665 MI_COM_PHY_ADDR_MASK);
666 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
667 MI_COM_REG_ADDR_MASK);
668 frame_val |= (val & MI_COM_DATA_MASK);
669 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
670
671 tw32_f(MAC_MI_COM, frame_val);
672
673 loops = PHY_BUSY_LOOPS;
674 while (loops != 0) {
675 udelay(10);
676 frame_val = tr32(MAC_MI_COM);
677 if ((frame_val & MI_COM_BUSY) == 0) {
678 udelay(5);
679 frame_val = tr32(MAC_MI_COM);
680 break;
681 }
682 loops -= 1;
683 }
684
685 ret = -EBUSY;
686 if (loops != 0)
687 ret = 0;
688
689 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
690 tw32_f(MAC_MI_MODE, tp->mi_mode);
691 udelay(80);
692 }
693
694 return ret;
695}
696
697static void tg3_phy_set_wirespeed(struct tg3 *tp)
698{
699 u32 val;
700
701 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
702 return;
703
704 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
705 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
706 tg3_writephy(tp, MII_TG3_AUX_CTRL,
707 (val | (1 << 15) | (1 << 4)));
708}
709
710static int tg3_bmcr_reset(struct tg3 *tp)
711{
712 u32 phy_control;
713 int limit, err;
714
715 /* OK, reset it, and poll the BMCR_RESET bit until it
716 * clears or we time out.
717 */
718 phy_control = BMCR_RESET;
719 err = tg3_writephy(tp, MII_BMCR, phy_control);
720 if (err != 0)
721 return -EBUSY;
722
723 limit = 5000;
724 while (limit--) {
725 err = tg3_readphy(tp, MII_BMCR, &phy_control);
726 if (err != 0)
727 return -EBUSY;
728
729 if ((phy_control & BMCR_RESET) == 0) {
730 udelay(40);
731 break;
732 }
733 udelay(10);
734 }
735 if (limit <= 0)
736 return -EBUSY;
737
738 return 0;
739}
740
741static int tg3_wait_macro_done(struct tg3 *tp)
742{
743 int limit = 100;
744
745 while (limit--) {
746 u32 tmp32;
747
748 if (!tg3_readphy(tp, 0x16, &tmp32)) {
749 if ((tmp32 & 0x1000) == 0)
750 break;
751 }
752 }
753 if (limit <= 0)
754 return -EBUSY;
755
756 return 0;
757}
758
759static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
760{
761 static const u32 test_pat[4][6] = {
762 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
763 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
764 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
765 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
766 };
767 int chan;
768
769 for (chan = 0; chan < 4; chan++) {
770 int i;
771
772 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
773 (chan * 0x2000) | 0x0200);
774 tg3_writephy(tp, 0x16, 0x0002);
775
776 for (i = 0; i < 6; i++)
777 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
778 test_pat[chan][i]);
779
780 tg3_writephy(tp, 0x16, 0x0202);
781 if (tg3_wait_macro_done(tp)) {
782 *resetp = 1;
783 return -EBUSY;
784 }
785
786 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
787 (chan * 0x2000) | 0x0200);
788 tg3_writephy(tp, 0x16, 0x0082);
789 if (tg3_wait_macro_done(tp)) {
790 *resetp = 1;
791 return -EBUSY;
792 }
793
794 tg3_writephy(tp, 0x16, 0x0802);
795 if (tg3_wait_macro_done(tp)) {
796 *resetp = 1;
797 return -EBUSY;
798 }
799
800 for (i = 0; i < 6; i += 2) {
801 u32 low, high;
802
803 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
804 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
805 tg3_wait_macro_done(tp)) {
806 *resetp = 1;
807 return -EBUSY;
808 }
809 low &= 0x7fff;
810 high &= 0x000f;
811 if (low != test_pat[chan][i] ||
812 high != test_pat[chan][i+1]) {
813 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
814 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
815 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
816
817 return -EBUSY;
818 }
819 }
820 }
821
822 return 0;
823}
824
825static int tg3_phy_reset_chanpat(struct tg3 *tp)
826{
827 int chan;
828
829 for (chan = 0; chan < 4; chan++) {
830 int i;
831
832 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
833 (chan * 0x2000) | 0x0200);
834 tg3_writephy(tp, 0x16, 0x0002);
835 for (i = 0; i < 6; i++)
836 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
837 tg3_writephy(tp, 0x16, 0x0202);
838 if (tg3_wait_macro_done(tp))
839 return -EBUSY;
840 }
841
842 return 0;
843}
844
845static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
846{
847 u32 reg32, phy9_orig;
848 int retries, do_phy_reset, err;
849
850 retries = 10;
851 do_phy_reset = 1;
852 do {
853 if (do_phy_reset) {
854 err = tg3_bmcr_reset(tp);
855 if (err)
856 return err;
857 do_phy_reset = 0;
858 }
859
860 /* Disable transmitter and interrupt. */
861 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
862 continue;
863
864 reg32 |= 0x3000;
865 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
866
867 /* Set full-duplex, 1000 mbps. */
868 tg3_writephy(tp, MII_BMCR,
869 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
870
871 /* Set to master mode. */
872 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
873 continue;
874
875 tg3_writephy(tp, MII_TG3_CTRL,
876 (MII_TG3_CTRL_AS_MASTER |
877 MII_TG3_CTRL_ENABLE_AS_MASTER));
878
879 /* Enable SM_DSP_CLOCK and 6dB. */
880 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
881
882 /* Block the PHY control access. */
883 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
884 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
885
886 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
887 if (!err)
888 break;
889 } while (--retries);
890
891 err = tg3_phy_reset_chanpat(tp);
892 if (err)
893 return err;
894
895 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
896 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
897
898 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
899 tg3_writephy(tp, 0x16, 0x0000);
900
901 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
902 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
903 /* Set Extended packet length bit for jumbo frames */
904 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
905 }
906 else {
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
908 }
909
910 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
911
912 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
913 reg32 &= ~0x3000;
914 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
915 } else if (!err)
916 err = -EBUSY;
917
918 return err;
919}
920
921/* This will reset the tigon3 PHY if there is no valid
922 * link unless the FORCE argument is non-zero.
923 */
924static int tg3_phy_reset(struct tg3 *tp)
925{
926 u32 phy_status;
927 int err;
928
929 err = tg3_readphy(tp, MII_BMSR, &phy_status);
930 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
931 if (err != 0)
932 return -EBUSY;
933
934 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
935 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
937 err = tg3_phy_reset_5703_4_5(tp);
938 if (err)
939 return err;
940 goto out;
941 }
942
943 err = tg3_bmcr_reset(tp);
944 if (err)
945 return err;
946
947out:
948 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
949 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
951 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
952 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
953 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
954 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
955 }
956 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
957 tg3_writephy(tp, 0x1c, 0x8d68);
958 tg3_writephy(tp, 0x1c, 0x8d68);
959 }
960 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
961 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
964 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
965 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
966 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
968 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
969 }
970 /* Set Extended packet length bit (bit 14) on all chips that */
971 /* support jumbo frames */
972 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
973 /* Cannot do read-modify-write on 5401 */
974 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 975 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 976 u32 phy_reg;
977
978 /* Set bit 14 with read-modify-write to preserve other bits */
979 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
980 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
981 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
982 }
983
984 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
985 * jumbo frames transmission.
986 */
0f893dc6 987 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 988 u32 phy_reg;
989
990 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
991 tg3_writephy(tp, MII_TG3_EXT_CTRL,
992 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
993 }
994
995 tg3_phy_set_wirespeed(tp);
996 return 0;
997}
998
999static void tg3_frob_aux_power(struct tg3 *tp)
1000{
1001 struct tg3 *tp_peer = tp;
1002
1003 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1004 return;
1005
1006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1007 tp_peer = pci_get_drvdata(tp->pdev_peer);
1008 if (!tp_peer)
1009 BUG();
1010 }
1011
1012
1013 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1014 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
1015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1016 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1017 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1018 (GRC_LCLCTRL_GPIO_OE0 |
1019 GRC_LCLCTRL_GPIO_OE1 |
1020 GRC_LCLCTRL_GPIO_OE2 |
1021 GRC_LCLCTRL_GPIO_OUTPUT0 |
1022 GRC_LCLCTRL_GPIO_OUTPUT1));
1023 udelay(100);
1024 } else {
1025 u32 no_gpio2;
1026 u32 grc_local_ctrl;
1027
1028 if (tp_peer != tp &&
1029 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1030 return;
1031
1032 /* On 5753 and variants, GPIO2 cannot be used. */
1033 no_gpio2 = tp->nic_sram_data_cfg &
1034 NIC_SRAM_DATA_CFG_NO_GPIO2;
1035
1036 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1037 GRC_LCLCTRL_GPIO_OE1 |
1038 GRC_LCLCTRL_GPIO_OE2 |
1039 GRC_LCLCTRL_GPIO_OUTPUT1 |
1040 GRC_LCLCTRL_GPIO_OUTPUT2;
1041 if (no_gpio2) {
1042 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1043 GRC_LCLCTRL_GPIO_OUTPUT2);
1044 }
1045 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1046 grc_local_ctrl);
1047 udelay(100);
1048
1049 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1050
1051 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1052 grc_local_ctrl);
1053 udelay(100);
1054
1055 if (!no_gpio2) {
1056 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1057 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1058 grc_local_ctrl);
1059 udelay(100);
1060 }
1061 }
1062 } else {
1063 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1064 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1065 if (tp_peer != tp &&
1066 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1067 return;
1068
1069 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1070 (GRC_LCLCTRL_GPIO_OE1 |
1071 GRC_LCLCTRL_GPIO_OUTPUT1));
1072 udelay(100);
1073
1074 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1075 (GRC_LCLCTRL_GPIO_OE1));
1076 udelay(100);
1077
1078 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1079 (GRC_LCLCTRL_GPIO_OE1 |
1080 GRC_LCLCTRL_GPIO_OUTPUT1));
1081 udelay(100);
1082 }
1083 }
1084}
1085
1086static int tg3_setup_phy(struct tg3 *, int);
1087
1088#define RESET_KIND_SHUTDOWN 0
1089#define RESET_KIND_INIT 1
1090#define RESET_KIND_SUSPEND 2
1091
1092static void tg3_write_sig_post_reset(struct tg3 *, int);
1093static int tg3_halt_cpu(struct tg3 *, u32);
1094
1095static int tg3_set_power_state(struct tg3 *tp, int state)
1096{
1097 u32 misc_host_ctrl;
1098 u16 power_control, power_caps;
1099 int pm = tp->pm_cap;
1100
1101 /* Make sure register accesses (indirect or otherwise)
1102 * will function correctly.
1103 */
1104 pci_write_config_dword(tp->pdev,
1105 TG3PCI_MISC_HOST_CTRL,
1106 tp->misc_host_ctrl);
1107
1108 pci_read_config_word(tp->pdev,
1109 pm + PCI_PM_CTRL,
1110 &power_control);
1111 power_control |= PCI_PM_CTRL_PME_STATUS;
1112 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1113 switch (state) {
1114 case 0:
1115 power_control |= 0;
1116 pci_write_config_word(tp->pdev,
1117 pm + PCI_PM_CTRL,
1118 power_control);
8c6bda1a
MC		 1119 udelay(100); /* Delay after power state change */
1120
1121 /* Switch out of Vaux if it is not a LOM */
1122 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1123 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1124 udelay(100);
1125 }
1da177e4
LT		 1126
1127 return 0;
1128
1129 case 1:
1130 power_control |= 1;
1131 break;
1132
1133 case 2:
1134 power_control |= 2;
1135 break;
1136
1137 case 3:
1138 power_control |= 3;
1139 break;
1140
1141 default:
1142 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1143 "requested.\n",
1144 tp->dev->name, state);
1145 return -EINVAL;
1146 };
1147
1148 power_control |= PCI_PM_CTRL_PME_ENABLE;
1149
1150 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1151 tw32(TG3PCI_MISC_HOST_CTRL,
1152 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1153
1154 if (tp->link_config.phy_is_low_power == 0) {
1155 tp->link_config.phy_is_low_power = 1;
1156 tp->link_config.orig_speed = tp->link_config.speed;
1157 tp->link_config.orig_duplex = tp->link_config.duplex;
1158 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1159 }
1160
747e8f8b 1161 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1162 tp->link_config.speed = SPEED_10;
1163 tp->link_config.duplex = DUPLEX_HALF;
1164 tp->link_config.autoneg = AUTONEG_ENABLE;
1165 tg3_setup_phy(tp, 0);
1166 }
1167
1168 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1169
1170 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1171 u32 mac_mode;
1172
1173 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1174 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1175 udelay(40);
1176
1177 mac_mode = MAC_MODE_PORT_MODE_MII;
1178
1179 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1180 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1181 mac_mode |= MAC_MODE_LINK_POLARITY;
1182 } else {
1183 mac_mode = MAC_MODE_PORT_MODE_TBI;
1184 }
1185
cbf46853 1186 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1187 tw32(MAC_LED_CTRL, tp->led_ctrl);
1188
1189 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1190 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1191 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1192
1193 tw32_f(MAC_MODE, mac_mode);
1194 udelay(100);
1195
1196 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1197 udelay(10);
1198 }
1199
1200 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1201 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1203 u32 base_val;
1204
1205 base_val = tp->pci_clock_ctrl;
1206 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1207 CLOCK_CTRL_TXCLK_DISABLE);
1208
1209 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1210 CLOCK_CTRL_ALTCLK |
1211 CLOCK_CTRL_PWRDOWN_PLL133);
1212 udelay(40);
4cf78e4f
MC		 1213 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1214 /* do nothing */
85e94ced 1215 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1216 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1217 u32 newbits1, newbits2;
1218
1219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1221 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1222 CLOCK_CTRL_TXCLK_DISABLE |
1223 CLOCK_CTRL_ALTCLK);
1224 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1225 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1226 newbits1 = CLOCK_CTRL_625_CORE;
1227 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1228 } else {
1229 newbits1 = CLOCK_CTRL_ALTCLK;
1230 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1231 }
1232
1233 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1234 udelay(40);
1235
1236 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1237 udelay(40);
1238
1239 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1240 u32 newbits3;
1241
1242 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1243 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1244 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1245 CLOCK_CTRL_TXCLK_DISABLE |
1246 CLOCK_CTRL_44MHZ_CORE);
1247 } else {
1248 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1249 }
1250
1251 tw32_f(TG3PCI_CLOCK_CTRL,
1252 tp->pci_clock_ctrl | newbits3);
1253 udelay(40);
1254 }
1255 }
1256
1257 tg3_frob_aux_power(tp);
1258
1259 /* Workaround for unstable PLL clock */
1260 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1261 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1262 u32 val = tr32(0x7d00);
1263
1264 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1265 tw32(0x7d00, val);
1266 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1267 tg3_halt_cpu(tp, RX_CPU_BASE);
1268 }
1269
1270 /* Finally, set the new power state. */
1271 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1272 udelay(100); /* Delay after power state change */
1da177e4
LT		 1273
1274 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1275
1276 return 0;
1277}
1278
1279static void tg3_link_report(struct tg3 *tp)
1280{
1281 if (!netif_carrier_ok(tp->dev)) {
1282 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1283 } else {
1284 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1285 tp->dev->name,
1286 (tp->link_config.active_speed == SPEED_1000 ?
1287 1000 :
1288 (tp->link_config.active_speed == SPEED_100 ?
1289 100 : 10)),
1290 (tp->link_config.active_duplex == DUPLEX_FULL ?
1291 "full" : "half"));
1292
1293 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1294 "%s for RX.\n",
1295 tp->dev->name,
1296 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1297 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1298 }
1299}
1300
1301static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1302{
1303 u32 new_tg3_flags = 0;
1304 u32 old_rx_mode = tp->rx_mode;
1305 u32 old_tx_mode = tp->tx_mode;
1306
1307 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1308
1309 /* Convert 1000BaseX flow control bits to 1000BaseT
1310 * bits before resolving flow control.
1311 */
1312 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1313 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1314 ADVERTISE_PAUSE_ASYM);
1315 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1316
1317 if (local_adv & ADVERTISE_1000XPAUSE)
1318 local_adv |= ADVERTISE_PAUSE_CAP;
1319 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1320 local_adv |= ADVERTISE_PAUSE_ASYM;
1321 if (remote_adv & LPA_1000XPAUSE)
1322 remote_adv |= LPA_PAUSE_CAP;
1323 if (remote_adv & LPA_1000XPAUSE_ASYM)
1324 remote_adv |= LPA_PAUSE_ASYM;
1325 }
1326
1da177e4
LT		 1327 if (local_adv & ADVERTISE_PAUSE_CAP) {
1328 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1329 if (remote_adv & LPA_PAUSE_CAP)
1330 new_tg3_flags |=
1331 (TG3_FLAG_RX_PAUSE |
1332 TG3_FLAG_TX_PAUSE);
1333 else if (remote_adv & LPA_PAUSE_ASYM)
1334 new_tg3_flags |=
1335 (TG3_FLAG_RX_PAUSE);
1336 } else {
1337 if (remote_adv & LPA_PAUSE_CAP)
1338 new_tg3_flags |=
1339 (TG3_FLAG_RX_PAUSE |
1340 TG3_FLAG_TX_PAUSE);
1341 }
1342 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1343 if ((remote_adv & LPA_PAUSE_CAP) &&
1344 (remote_adv & LPA_PAUSE_ASYM))
1345 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1346 }
1347
1348 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1349 tp->tg3_flags |= new_tg3_flags;
1350 } else {
1351 new_tg3_flags = tp->tg3_flags;
1352 }
1353
1354 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1355 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1356 else
1357 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1358
1359 if (old_rx_mode != tp->rx_mode) {
1360 tw32_f(MAC_RX_MODE, tp->rx_mode);
1361 }
1362
1363 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1364 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1365 else
1366 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1367
1368 if (old_tx_mode != tp->tx_mode) {
1369 tw32_f(MAC_TX_MODE, tp->tx_mode);
1370 }
1371}
1372
1373static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1374{
1375 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1376 case MII_TG3_AUX_STAT_10HALF:
1377 *speed = SPEED_10;
1378 *duplex = DUPLEX_HALF;
1379 break;
1380
1381 case MII_TG3_AUX_STAT_10FULL:
1382 *speed = SPEED_10;
1383 *duplex = DUPLEX_FULL;
1384 break;
1385
1386 case MII_TG3_AUX_STAT_100HALF:
1387 *speed = SPEED_100;
1388 *duplex = DUPLEX_HALF;
1389 break;
1390
1391 case MII_TG3_AUX_STAT_100FULL:
1392 *speed = SPEED_100;
1393 *duplex = DUPLEX_FULL;
1394 break;
1395
1396 case MII_TG3_AUX_STAT_1000HALF:
1397 *speed = SPEED_1000;
1398 *duplex = DUPLEX_HALF;
1399 break;
1400
1401 case MII_TG3_AUX_STAT_1000FULL:
1402 *speed = SPEED_1000;
1403 *duplex = DUPLEX_FULL;
1404 break;
1405
1406 default:
1407 *speed = SPEED_INVALID;
1408 *duplex = DUPLEX_INVALID;
1409 break;
1410 };
1411}
1412
1413static void tg3_phy_copper_begin(struct tg3 *tp)
1414{
1415 u32 new_adv;
1416 int i;
1417
1418 if (tp->link_config.phy_is_low_power) {
1419 /* Entering low power mode. Disable gigabit and
1420 * 100baseT advertisements.
1421 */
1422 tg3_writephy(tp, MII_TG3_CTRL, 0);
1423
1424 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1425 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1426 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1427 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1428
1429 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1430 } else if (tp->link_config.speed == SPEED_INVALID) {
1431 tp->link_config.advertising =
1432 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1433 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1434 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1435 ADVERTISED_Autoneg | ADVERTISED_MII);
1436
1437 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1438 tp->link_config.advertising &=
1439 ~(ADVERTISED_1000baseT_Half |
1440 ADVERTISED_1000baseT_Full);
1441
1442 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1443 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1444 new_adv |= ADVERTISE_10HALF;
1445 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1446 new_adv |= ADVERTISE_10FULL;
1447 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1448 new_adv |= ADVERTISE_100HALF;
1449 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1450 new_adv |= ADVERTISE_100FULL;
1451 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1452
1453 if (tp->link_config.advertising &
1454 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1455 new_adv = 0;
1456 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1457 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1458 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1459 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1460 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1461 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1462 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1463 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1464 MII_TG3_CTRL_ENABLE_AS_MASTER);
1465 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1466 } else {
1467 tg3_writephy(tp, MII_TG3_CTRL, 0);
1468 }
1469 } else {
1470 /* Asking for a specific link mode. */
1471 if (tp->link_config.speed == SPEED_1000) {
1472 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1473 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1474
1475 if (tp->link_config.duplex == DUPLEX_FULL)
1476 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1477 else
1478 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1479 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1480 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1481 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1482 MII_TG3_CTRL_ENABLE_AS_MASTER);
1483 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1484 } else {
1485 tg3_writephy(tp, MII_TG3_CTRL, 0);
1486
1487 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1488 if (tp->link_config.speed == SPEED_100) {
1489 if (tp->link_config.duplex == DUPLEX_FULL)
1490 new_adv |= ADVERTISE_100FULL;
1491 else
1492 new_adv |= ADVERTISE_100HALF;
1493 } else {
1494 if (tp->link_config.duplex == DUPLEX_FULL)
1495 new_adv |= ADVERTISE_10FULL;
1496 else
1497 new_adv |= ADVERTISE_10HALF;
1498 }
1499 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1500 }
1501 }
1502
1503 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1504 tp->link_config.speed != SPEED_INVALID) {
1505 u32 bmcr, orig_bmcr;
1506
1507 tp->link_config.active_speed = tp->link_config.speed;
1508 tp->link_config.active_duplex = tp->link_config.duplex;
1509
1510 bmcr = 0;
1511 switch (tp->link_config.speed) {
1512 default:
1513 case SPEED_10:
1514 break;
1515
1516 case SPEED_100:
1517 bmcr |= BMCR_SPEED100;
1518 break;
1519
1520 case SPEED_1000:
1521 bmcr |= TG3_BMCR_SPEED1000;
1522 break;
1523 };
1524
1525 if (tp->link_config.duplex == DUPLEX_FULL)
1526 bmcr |= BMCR_FULLDPLX;
1527
1528 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1529 (bmcr != orig_bmcr)) {
1530 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1531 for (i = 0; i < 1500; i++) {
1532 u32 tmp;
1533
1534 udelay(10);
1535 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1536 tg3_readphy(tp, MII_BMSR, &tmp))
1537 continue;
1538 if (!(tmp & BMSR_LSTATUS)) {
1539 udelay(40);
1540 break;
1541 }
1542 }
1543 tg3_writephy(tp, MII_BMCR, bmcr);
1544 udelay(40);
1545 }
1546 } else {
1547 tg3_writephy(tp, MII_BMCR,
1548 BMCR_ANENABLE | BMCR_ANRESTART);
1549 }
1550}
1551
1552static int tg3_init_5401phy_dsp(struct tg3 *tp)
1553{
1554 int err;
1555
1556 /* Turn off tap power management. */
1557 /* Set Extended packet length bit */
1558 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1559
1560 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1561 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1562
1563 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1564 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1565
1566 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1567 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1568
1569 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1570 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1571
1572 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1573 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1574
1575 udelay(40);
1576
1577 return err;
1578}
1579
1580static int tg3_copper_is_advertising_all(struct tg3 *tp)
1581{
1582 u32 adv_reg, all_mask;
1583
1584 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1585 return 0;
1586
1587 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1588 ADVERTISE_100HALF | ADVERTISE_100FULL);
1589 if ((adv_reg & all_mask) != all_mask)
1590 return 0;
1591 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1592 u32 tg3_ctrl;
1593
1594 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1595 return 0;
1596
1597 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1598 MII_TG3_CTRL_ADV_1000_FULL);
1599 if ((tg3_ctrl & all_mask) != all_mask)
1600 return 0;
1601 }
1602 return 1;
1603}
1604
1605static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1606{
1607 int current_link_up;
1608 u32 bmsr, dummy;
1609 u16 current_speed;
1610 u8 current_duplex;
1611 int i, err;
1612
1613 tw32(MAC_EVENT, 0);
1614
1615 tw32_f(MAC_STATUS,
1616 (MAC_STATUS_SYNC_CHANGED |
1617 MAC_STATUS_CFG_CHANGED |
1618 MAC_STATUS_MI_COMPLETION |
1619 MAC_STATUS_LNKSTATE_CHANGED));
1620 udelay(40);
1621
1622 tp->mi_mode = MAC_MI_MODE_BASE;
1623 tw32_f(MAC_MI_MODE, tp->mi_mode);
1624 udelay(80);
1625
1626 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1627
1628 /* Some third-party PHYs need to be reset on link going
1629 * down.
1630 */
1631 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1633 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1634 netif_carrier_ok(tp->dev)) {
1635 tg3_readphy(tp, MII_BMSR, &bmsr);
1636 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1637 !(bmsr & BMSR_LSTATUS))
1638 force_reset = 1;
1639 }
1640 if (force_reset)
1641 tg3_phy_reset(tp);
1642
1643 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1644 tg3_readphy(tp, MII_BMSR, &bmsr);
1645 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1646 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1647 bmsr = 0;
1648
1649 if (!(bmsr & BMSR_LSTATUS)) {
1650 err = tg3_init_5401phy_dsp(tp);
1651 if (err)
1652 return err;
1653
1654 tg3_readphy(tp, MII_BMSR, &bmsr);
1655 for (i = 0; i < 1000; i++) {
1656 udelay(10);
1657 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1658 (bmsr & BMSR_LSTATUS)) {
1659 udelay(40);
1660 break;
1661 }
1662 }
1663
1664 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1665 !(bmsr & BMSR_LSTATUS) &&
1666 tp->link_config.active_speed == SPEED_1000) {
1667 err = tg3_phy_reset(tp);
1668 if (!err)
1669 err = tg3_init_5401phy_dsp(tp);
1670 if (err)
1671 return err;
1672 }
1673 }
1674 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1675 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1676 /* 5701 {A0,B0} CRC bug workaround */
1677 tg3_writephy(tp, 0x15, 0x0a75);
1678 tg3_writephy(tp, 0x1c, 0x8c68);
1679 tg3_writephy(tp, 0x1c, 0x8d68);
1680 tg3_writephy(tp, 0x1c, 0x8c68);
1681 }
1682
1683 /* Clear pending interrupts... */
1684 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1685 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1686
1687 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1688 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1689 else
1690 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1691
1692 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1693 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1694 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1695 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1696 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1697 else
1698 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1699 }
1700
1701 current_link_up = 0;
1702 current_speed = SPEED_INVALID;
1703 current_duplex = DUPLEX_INVALID;
1704
1705 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1706 u32 val;
1707
1708 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1709 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1710 if (!(val & (1 << 10))) {
1711 val |= (1 << 10);
1712 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1713 goto relink;
1714 }
1715 }
1716
1717 bmsr = 0;
1718 for (i = 0; i < 100; i++) {
1719 tg3_readphy(tp, MII_BMSR, &bmsr);
1720 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1721 (bmsr & BMSR_LSTATUS))
1722 break;
1723 udelay(40);
1724 }
1725
1726 if (bmsr & BMSR_LSTATUS) {
1727 u32 aux_stat, bmcr;
1728
1729 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1730 for (i = 0; i < 2000; i++) {
1731 udelay(10);
1732 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1733 aux_stat)
1734 break;
1735 }
1736
1737 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1738 &current_speed,
1739 &current_duplex);
1740
1741 bmcr = 0;
1742 for (i = 0; i < 200; i++) {
1743 tg3_readphy(tp, MII_BMCR, &bmcr);
1744 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1745 continue;
1746 if (bmcr && bmcr != 0x7fff)
1747 break;
1748 udelay(10);
1749 }
1750
1751 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1752 if (bmcr & BMCR_ANENABLE) {
1753 current_link_up = 1;
1754
1755 /* Force autoneg restart if we are exiting
1756 * low power mode.
1757 */
1758 if (!tg3_copper_is_advertising_all(tp))
1759 current_link_up = 0;
1760 } else {
1761 current_link_up = 0;
1762 }
1763 } else {
1764 if (!(bmcr & BMCR_ANENABLE) &&
1765 tp->link_config.speed == current_speed &&
1766 tp->link_config.duplex == current_duplex) {
1767 current_link_up = 1;
1768 } else {
1769 current_link_up = 0;
1770 }
1771 }
1772
1773 tp->link_config.active_speed = current_speed;
1774 tp->link_config.active_duplex = current_duplex;
1775 }
1776
1777 if (current_link_up == 1 &&
1778 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1779 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1780 u32 local_adv, remote_adv;
1781
1782 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1783 local_adv = 0;
1784 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1785
1786 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1787 remote_adv = 0;
1788
1789 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1790
1791 /* If we are not advertising full pause capability,
1792 * something is wrong. Bring the link down and reconfigure.
1793 */
1794 if (local_adv != ADVERTISE_PAUSE_CAP) {
1795 current_link_up = 0;
1796 } else {
1797 tg3_setup_flow_control(tp, local_adv, remote_adv);
1798 }
1799 }
1800relink:
1801 if (current_link_up == 0) {
1802 u32 tmp;
1803
1804 tg3_phy_copper_begin(tp);
1805
1806 tg3_readphy(tp, MII_BMSR, &tmp);
1807 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1808 (tmp & BMSR_LSTATUS))
1809 current_link_up = 1;
1810 }
1811
1812 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1813 if (current_link_up == 1) {
1814 if (tp->link_config.active_speed == SPEED_100 ||
1815 tp->link_config.active_speed == SPEED_10)
1816 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1817 else
1818 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1819 } else
1820 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1821
1822 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1823 if (tp->link_config.active_duplex == DUPLEX_HALF)
1824 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1825
1826 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1827 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1828 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1829 (current_link_up == 1 &&
1830 tp->link_config.active_speed == SPEED_10))
1831 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1832 } else {
1833 if (current_link_up == 1)
1834 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1835 }
1836
1837 /* ??? Without this setting Netgear GA302T PHY does not
1838 * ??? send/receive packets...
1839 */
1840 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1841 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1842 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1843 tw32_f(MAC_MI_MODE, tp->mi_mode);
1844 udelay(80);
1845 }
1846
1847 tw32_f(MAC_MODE, tp->mac_mode);
1848 udelay(40);
1849
1850 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1851 /* Polled via timer. */
1852 tw32_f(MAC_EVENT, 0);
1853 } else {
1854 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1855 }
1856 udelay(40);
1857
1858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1859 current_link_up == 1 &&
1860 tp->link_config.active_speed == SPEED_1000 &&
1861 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1862 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1863 udelay(120);
1864 tw32_f(MAC_STATUS,
1865 (MAC_STATUS_SYNC_CHANGED |
1866 MAC_STATUS_CFG_CHANGED));
1867 udelay(40);
1868 tg3_write_mem(tp,
1869 NIC_SRAM_FIRMWARE_MBOX,
1870 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1871 }
1872
1873 if (current_link_up != netif_carrier_ok(tp->dev)) {
1874 if (current_link_up)
1875 netif_carrier_on(tp->dev);
1876 else
1877 netif_carrier_off(tp->dev);
1878 tg3_link_report(tp);
1879 }
1880
1881 return 0;
1882}
1883
1884struct tg3_fiber_aneginfo {
1885 int state;
1886#define ANEG_STATE_UNKNOWN 0
1887#define ANEG_STATE_AN_ENABLE 1
1888#define ANEG_STATE_RESTART_INIT 2
1889#define ANEG_STATE_RESTART 3
1890#define ANEG_STATE_DISABLE_LINK_OK 4
1891#define ANEG_STATE_ABILITY_DETECT_INIT 5
1892#define ANEG_STATE_ABILITY_DETECT 6
1893#define ANEG_STATE_ACK_DETECT_INIT 7
1894#define ANEG_STATE_ACK_DETECT 8
1895#define ANEG_STATE_COMPLETE_ACK_INIT 9
1896#define ANEG_STATE_COMPLETE_ACK 10
1897#define ANEG_STATE_IDLE_DETECT_INIT 11
1898#define ANEG_STATE_IDLE_DETECT 12
1899#define ANEG_STATE_LINK_OK 13
1900#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1901#define ANEG_STATE_NEXT_PAGE_WAIT 15
1902
1903 u32 flags;
1904#define MR_AN_ENABLE 0x00000001
1905#define MR_RESTART_AN 0x00000002
1906#define MR_AN_COMPLETE 0x00000004
1907#define MR_PAGE_RX 0x00000008
1908#define MR_NP_LOADED 0x00000010
1909#define MR_TOGGLE_TX 0x00000020
1910#define MR_LP_ADV_FULL_DUPLEX 0x00000040
1911#define MR_LP_ADV_HALF_DUPLEX 0x00000080
1912#define MR_LP_ADV_SYM_PAUSE 0x00000100
1913#define MR_LP_ADV_ASYM_PAUSE 0x00000200
1914#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1915#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1916#define MR_LP_ADV_NEXT_PAGE 0x00001000
1917#define MR_TOGGLE_RX 0x00002000
1918#define MR_NP_RX 0x00004000
1919
1920#define MR_LINK_OK 0x80000000
1921
1922 unsigned long link_time, cur_time;
1923
1924 u32 ability_match_cfg;
1925 int ability_match_count;
1926
1927 char ability_match, idle_match, ack_match;
1928
1929 u32 txconfig, rxconfig;
1930#define ANEG_CFG_NP 0x00000080
1931#define ANEG_CFG_ACK 0x00000040
1932#define ANEG_CFG_RF2 0x00000020
1933#define ANEG_CFG_RF1 0x00000010
1934#define ANEG_CFG_PS2 0x00000001
1935#define ANEG_CFG_PS1 0x00008000
1936#define ANEG_CFG_HD 0x00004000
1937#define ANEG_CFG_FD 0x00002000
1938#define ANEG_CFG_INVAL 0x00001f06
1939
1940};
1941#define ANEG_OK 0
1942#define ANEG_DONE 1
1943#define ANEG_TIMER_ENAB 2
1944#define ANEG_FAILED -1
1945
1946#define ANEG_STATE_SETTLE_TIME 10000
1947
1948static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1949 struct tg3_fiber_aneginfo *ap)
1950{
1951 unsigned long delta;
1952 u32 rx_cfg_reg;
1953 int ret;
1954
1955 if (ap->state == ANEG_STATE_UNKNOWN) {
1956 ap->rxconfig = 0;
1957 ap->link_time = 0;
1958 ap->cur_time = 0;
1959 ap->ability_match_cfg = 0;
1960 ap->ability_match_count = 0;
1961 ap->ability_match = 0;
1962 ap->idle_match = 0;
1963 ap->ack_match = 0;
1964 }
1965 ap->cur_time++;
1966
1967 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1968 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1969
1970 if (rx_cfg_reg != ap->ability_match_cfg) {
1971 ap->ability_match_cfg = rx_cfg_reg;
1972 ap->ability_match = 0;
1973 ap->ability_match_count = 0;
1974 } else {
1975 if (++ap->ability_match_count > 1) {
1976 ap->ability_match = 1;
1977 ap->ability_match_cfg = rx_cfg_reg;
1978 }
1979 }
1980 if (rx_cfg_reg & ANEG_CFG_ACK)
1981 ap->ack_match = 1;
1982 else
1983 ap->ack_match = 0;
1984
1985 ap->idle_match = 0;
1986 } else {
1987 ap->idle_match = 1;
1988 ap->ability_match_cfg = 0;
1989 ap->ability_match_count = 0;
1990 ap->ability_match = 0;
1991 ap->ack_match = 0;
1992
1993 rx_cfg_reg = 0;
1994 }
1995
1996 ap->rxconfig = rx_cfg_reg;
1997 ret = ANEG_OK;
1998
1999 switch(ap->state) {
2000 case ANEG_STATE_UNKNOWN:
2001 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2002 ap->state = ANEG_STATE_AN_ENABLE;
2003
2004 /* fallthru */
2005 case ANEG_STATE_AN_ENABLE:
2006 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2007 if (ap->flags & MR_AN_ENABLE) {
2008 ap->link_time = 0;
2009 ap->cur_time = 0;
2010 ap->ability_match_cfg = 0;
2011 ap->ability_match_count = 0;
2012 ap->ability_match = 0;
2013 ap->idle_match = 0;
2014 ap->ack_match = 0;
2015
2016 ap->state = ANEG_STATE_RESTART_INIT;
2017 } else {
2018 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2019 }
2020 break;
2021
2022 case ANEG_STATE_RESTART_INIT:
2023 ap->link_time = ap->cur_time;
2024 ap->flags &= ~(MR_NP_LOADED);
2025 ap->txconfig = 0;
2026 tw32(MAC_TX_AUTO_NEG, 0);
2027 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2028 tw32_f(MAC_MODE, tp->mac_mode);
2029 udelay(40);
2030
2031 ret = ANEG_TIMER_ENAB;
2032 ap->state = ANEG_STATE_RESTART;
2033
2034 /* fallthru */
2035 case ANEG_STATE_RESTART:
2036 delta = ap->cur_time - ap->link_time;
2037 if (delta > ANEG_STATE_SETTLE_TIME) {
2038 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2039 } else {
2040 ret = ANEG_TIMER_ENAB;
2041 }
2042 break;
2043
2044 case ANEG_STATE_DISABLE_LINK_OK:
2045 ret = ANEG_DONE;
2046 break;
2047
2048 case ANEG_STATE_ABILITY_DETECT_INIT:
2049 ap->flags &= ~(MR_TOGGLE_TX);
2050 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2051 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2052 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2053 tw32_f(MAC_MODE, tp->mac_mode);
2054 udelay(40);
2055
2056 ap->state = ANEG_STATE_ABILITY_DETECT;
2057 break;
2058
2059 case ANEG_STATE_ABILITY_DETECT:
2060 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2061 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2062 }
2063 break;
2064
2065 case ANEG_STATE_ACK_DETECT_INIT:
2066 ap->txconfig |= ANEG_CFG_ACK;
2067 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2068 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2069 tw32_f(MAC_MODE, tp->mac_mode);
2070 udelay(40);
2071
2072 ap->state = ANEG_STATE_ACK_DETECT;
2073
2074 /* fallthru */
2075 case ANEG_STATE_ACK_DETECT:
2076 if (ap->ack_match != 0) {
2077 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2078 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2079 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2080 } else {
2081 ap->state = ANEG_STATE_AN_ENABLE;
2082 }
2083 } else if (ap->ability_match != 0 &&
2084 ap->rxconfig == 0) {
2085 ap->state = ANEG_STATE_AN_ENABLE;
2086 }
2087 break;
2088
2089 case ANEG_STATE_COMPLETE_ACK_INIT:
2090 if (ap->rxconfig & ANEG_CFG_INVAL) {
2091 ret = ANEG_FAILED;
2092 break;
2093 }
2094 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2095 MR_LP_ADV_HALF_DUPLEX |
2096 MR_LP_ADV_SYM_PAUSE |
2097 MR_LP_ADV_ASYM_PAUSE |
2098 MR_LP_ADV_REMOTE_FAULT1 |
2099 MR_LP_ADV_REMOTE_FAULT2 |
2100 MR_LP_ADV_NEXT_PAGE |
2101 MR_TOGGLE_RX |
2102 MR_NP_RX);
2103 if (ap->rxconfig & ANEG_CFG_FD)
2104 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2105 if (ap->rxconfig & ANEG_CFG_HD)
2106 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2107 if (ap->rxconfig & ANEG_CFG_PS1)
2108 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2109 if (ap->rxconfig & ANEG_CFG_PS2)
2110 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2111 if (ap->rxconfig & ANEG_CFG_RF1)
2112 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2113 if (ap->rxconfig & ANEG_CFG_RF2)
2114 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2115 if (ap->rxconfig & ANEG_CFG_NP)
2116 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2117
2118 ap->link_time = ap->cur_time;
2119
2120 ap->flags ^= (MR_TOGGLE_TX);
2121 if (ap->rxconfig & 0x0008)
2122 ap->flags |= MR_TOGGLE_RX;
2123 if (ap->rxconfig & ANEG_CFG_NP)
2124 ap->flags |= MR_NP_RX;
2125 ap->flags |= MR_PAGE_RX;
2126
2127 ap->state = ANEG_STATE_COMPLETE_ACK;
2128 ret = ANEG_TIMER_ENAB;
2129 break;
2130
2131 case ANEG_STATE_COMPLETE_ACK:
2132 if (ap->ability_match != 0 &&
2133 ap->rxconfig == 0) {
2134 ap->state = ANEG_STATE_AN_ENABLE;
2135 break;
2136 }
2137 delta = ap->cur_time - ap->link_time;
2138 if (delta > ANEG_STATE_SETTLE_TIME) {
2139 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2140 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2141 } else {
2142 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2143 !(ap->flags & MR_NP_RX)) {
2144 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2145 } else {
2146 ret = ANEG_FAILED;
2147 }
2148 }
2149 }
2150 break;
2151
2152 case ANEG_STATE_IDLE_DETECT_INIT:
2153 ap->link_time = ap->cur_time;
2154 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2155 tw32_f(MAC_MODE, tp->mac_mode);
2156 udelay(40);
2157
2158 ap->state = ANEG_STATE_IDLE_DETECT;
2159 ret = ANEG_TIMER_ENAB;
2160 break;
2161
2162 case ANEG_STATE_IDLE_DETECT:
2163 if (ap->ability_match != 0 &&
2164 ap->rxconfig == 0) {
2165 ap->state = ANEG_STATE_AN_ENABLE;
2166 break;
2167 }
2168 delta = ap->cur_time - ap->link_time;
2169 if (delta > ANEG_STATE_SETTLE_TIME) {
2170 /* XXX another gem from the Broadcom driver :( */
2171 ap->state = ANEG_STATE_LINK_OK;
2172 }
2173 break;
2174
2175 case ANEG_STATE_LINK_OK:
2176 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2177 ret = ANEG_DONE;
2178 break;
2179
2180 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2181 /* ??? unimplemented */
2182 break;
2183
2184 case ANEG_STATE_NEXT_PAGE_WAIT:
2185 /* ??? unimplemented */
2186 break;
2187
2188 default:
2189 ret = ANEG_FAILED;
2190 break;
2191 };
2192
2193 return ret;
2194}
2195
2196static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2197{
2198 int res = 0;
2199 struct tg3_fiber_aneginfo aninfo;
2200 int status = ANEG_FAILED;
2201 unsigned int tick;
2202 u32 tmp;
2203
2204 tw32_f(MAC_TX_AUTO_NEG, 0);
2205
2206 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2207 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2208 udelay(40);
2209
2210 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2211 udelay(40);
2212
2213 memset(&aninfo, 0, sizeof(aninfo));
2214 aninfo.flags |= MR_AN_ENABLE;
2215 aninfo.state = ANEG_STATE_UNKNOWN;
2216 aninfo.cur_time = 0;
2217 tick = 0;
2218 while (++tick < 195000) {
2219 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2220 if (status == ANEG_DONE || status == ANEG_FAILED)
2221 break;
2222
2223 udelay(1);
2224 }
2225
2226 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2227 tw32_f(MAC_MODE, tp->mac_mode);
2228 udelay(40);
2229
2230 *flags = aninfo.flags;
2231
2232 if (status == ANEG_DONE &&
2233 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2234 MR_LP_ADV_FULL_DUPLEX)))
2235 res = 1;
2236
2237 return res;
2238}
2239
2240static void tg3_init_bcm8002(struct tg3 *tp)
2241{
2242 u32 mac_status = tr32(MAC_STATUS);
2243 int i;
2244
2245 /* Reset when initting first time or we have a link. */
2246 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2247 !(mac_status & MAC_STATUS_PCS_SYNCED))
2248 return;
2249
2250 /* Set PLL lock range. */
2251 tg3_writephy(tp, 0x16, 0x8007);
2252
2253 /* SW reset */
2254 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2255
2256 /* Wait for reset to complete. */
2257 /* XXX schedule_timeout() ... */
2258 for (i = 0; i < 500; i++)
2259 udelay(10);
2260
2261 /* Config mode; select PMA/Ch 1 regs. */
2262 tg3_writephy(tp, 0x10, 0x8411);
2263
2264 /* Enable auto-lock and comdet, select txclk for tx. */
2265 tg3_writephy(tp, 0x11, 0x0a10);
2266
2267 tg3_writephy(tp, 0x18, 0x00a0);
2268 tg3_writephy(tp, 0x16, 0x41ff);
2269
2270 /* Assert and deassert POR. */
2271 tg3_writephy(tp, 0x13, 0x0400);
2272 udelay(40);
2273 tg3_writephy(tp, 0x13, 0x0000);
2274
2275 tg3_writephy(tp, 0x11, 0x0a50);
2276 udelay(40);
2277 tg3_writephy(tp, 0x11, 0x0a10);
2278
2279 /* Wait for signal to stabilize */
2280 /* XXX schedule_timeout() ... */
2281 for (i = 0; i < 15000; i++)
2282 udelay(10);
2283
2284 /* Deselect the channel register so we can read the PHYID
2285 * later.
2286 */
2287 tg3_writephy(tp, 0x10, 0x8011);
2288}
2289
2290static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2291{
2292 u32 sg_dig_ctrl, sg_dig_status;
2293 u32 serdes_cfg, expected_sg_dig_ctrl;
2294 int workaround, port_a;
2295 int current_link_up;
2296
2297 serdes_cfg = 0;
2298 expected_sg_dig_ctrl = 0;
2299 workaround = 0;
2300 port_a = 1;
2301 current_link_up = 0;
2302
2303 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2304 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2305 workaround = 1;
2306 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2307 port_a = 0;
2308
2309 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2310 /* preserve bits 20-23 for voltage regulator */
2311 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2312 }
2313
2314 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2315
2316 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2317 if (sg_dig_ctrl & (1 << 31)) {
2318 if (workaround) {
2319 u32 val = serdes_cfg;
2320
2321 if (port_a)
2322 val |= 0xc010000;
2323 else
2324 val |= 0x4010000;
2325 tw32_f(MAC_SERDES_CFG, val);
2326 }
2327 tw32_f(SG_DIG_CTRL, 0x01388400);
2328 }
2329 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2330 tg3_setup_flow_control(tp, 0, 0);
2331 current_link_up = 1;
2332 }
2333 goto out;
2334 }
2335
2336 /* Want auto-negotiation. */
2337 expected_sg_dig_ctrl = 0x81388400;
2338
2339 /* Pause capability */
2340 expected_sg_dig_ctrl |= (1 << 11);
2341
2342 /* Asymettric pause */
2343 expected_sg_dig_ctrl |= (1 << 12);
2344
2345 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2346 if (workaround)
2347 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2348 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2349 udelay(5);
2350 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2351
2352 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2353 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2354 MAC_STATUS_SIGNAL_DET)) {
2355 int i;
2356
2357 /* Giver time to negotiate (~200ms) */
2358 for (i = 0; i < 40000; i++) {
2359 sg_dig_status = tr32(SG_DIG_STATUS);
2360 if (sg_dig_status & (0x3))
2361 break;
2362 udelay(5);
2363 }
2364 mac_status = tr32(MAC_STATUS);
2365
2366 if ((sg_dig_status & (1 << 1)) &&
2367 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2368 u32 local_adv, remote_adv;
2369
2370 local_adv = ADVERTISE_PAUSE_CAP;
2371 remote_adv = 0;
2372 if (sg_dig_status & (1 << 19))
2373 remote_adv |= LPA_PAUSE_CAP;
2374 if (sg_dig_status & (1 << 20))
2375 remote_adv |= LPA_PAUSE_ASYM;
2376
2377 tg3_setup_flow_control(tp, local_adv, remote_adv);
2378 current_link_up = 1;
2379 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2380 } else if (!(sg_dig_status & (1 << 1))) {
2381 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2382 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2383 else {
2384 if (workaround) {
2385 u32 val = serdes_cfg;
2386
2387 if (port_a)
2388 val |= 0xc010000;
2389 else
2390 val |= 0x4010000;
2391
2392 tw32_f(MAC_SERDES_CFG, val);
2393 }
2394
2395 tw32_f(SG_DIG_CTRL, 0x01388400);
2396 udelay(40);
2397
2398 /* Link parallel detection - link is up */
2399 /* only if we have PCS_SYNC and not */
2400 /* receiving config code words */
2401 mac_status = tr32(MAC_STATUS);
2402 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2403 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2404 tg3_setup_flow_control(tp, 0, 0);
2405 current_link_up = 1;
2406 }
2407 }
2408 }
2409 }
2410
2411out:
2412 return current_link_up;
2413}
2414
2415static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2416{
2417 int current_link_up = 0;
2418
2419 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2420 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2421 goto out;
2422 }
2423
2424 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2425 u32 flags;
2426 int i;
2427
2428 if (fiber_autoneg(tp, &flags)) {
2429 u32 local_adv, remote_adv;
2430
2431 local_adv = ADVERTISE_PAUSE_CAP;
2432 remote_adv = 0;
2433 if (flags & MR_LP_ADV_SYM_PAUSE)
2434 remote_adv |= LPA_PAUSE_CAP;
2435 if (flags & MR_LP_ADV_ASYM_PAUSE)
2436 remote_adv |= LPA_PAUSE_ASYM;
2437
2438 tg3_setup_flow_control(tp, local_adv, remote_adv);
2439
2440 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2441 current_link_up = 1;
2442 }
2443 for (i = 0; i < 30; i++) {
2444 udelay(20);
2445 tw32_f(MAC_STATUS,
2446 (MAC_STATUS_SYNC_CHANGED |
2447 MAC_STATUS_CFG_CHANGED));
2448 udelay(40);
2449 if ((tr32(MAC_STATUS) &
2450 (MAC_STATUS_SYNC_CHANGED |
2451 MAC_STATUS_CFG_CHANGED)) == 0)
2452 break;
2453 }
2454
2455 mac_status = tr32(MAC_STATUS);
2456 if (current_link_up == 0 &&
2457 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2458 !(mac_status & MAC_STATUS_RCVD_CFG))
2459 current_link_up = 1;
2460 } else {
2461 /* Forcing 1000FD link up. */
2462 current_link_up = 1;
2463 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2464
2465 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2466 udelay(40);
2467 }
2468
2469out:
2470 return current_link_up;
2471}
2472
2473static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2474{
2475 u32 orig_pause_cfg;
2476 u16 orig_active_speed;
2477 u8 orig_active_duplex;
2478 u32 mac_status;
2479 int current_link_up;
2480 int i;
2481
2482 orig_pause_cfg =
2483 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2484 TG3_FLAG_TX_PAUSE));
2485 orig_active_speed = tp->link_config.active_speed;
2486 orig_active_duplex = tp->link_config.active_duplex;
2487
2488 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2489 netif_carrier_ok(tp->dev) &&
2490 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2491 mac_status = tr32(MAC_STATUS);
2492 mac_status &= (MAC_STATUS_PCS_SYNCED |
2493 MAC_STATUS_SIGNAL_DET |
2494 MAC_STATUS_CFG_CHANGED |
2495 MAC_STATUS_RCVD_CFG);
2496 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2497 MAC_STATUS_SIGNAL_DET)) {
2498 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2499 MAC_STATUS_CFG_CHANGED));
2500 return 0;
2501 }
2502 }
2503
2504 tw32_f(MAC_TX_AUTO_NEG, 0);
2505
2506 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2507 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2508 tw32_f(MAC_MODE, tp->mac_mode);
2509 udelay(40);
2510
2511 if (tp->phy_id == PHY_ID_BCM8002)
2512 tg3_init_bcm8002(tp);
2513
2514 /* Enable link change event even when serdes polling. */
2515 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2516 udelay(40);
2517
2518 current_link_up = 0;
2519 mac_status = tr32(MAC_STATUS);
2520
2521 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2522 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2523 else
2524 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2525
2526 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2527 tw32_f(MAC_MODE, tp->mac_mode);
2528 udelay(40);
2529
2530 tp->hw_status->status =
2531 (SD_STATUS_UPDATED |
2532 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2533
2534 for (i = 0; i < 100; i++) {
2535 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2536 MAC_STATUS_CFG_CHANGED));
2537 udelay(5);
2538 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2539 MAC_STATUS_CFG_CHANGED)) == 0)
2540 break;
2541 }
2542
2543 mac_status = tr32(MAC_STATUS);
2544 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2545 current_link_up = 0;
2546 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2547 tw32_f(MAC_MODE, (tp->mac_mode |
2548 MAC_MODE_SEND_CONFIGS));
2549 udelay(1);
2550 tw32_f(MAC_MODE, tp->mac_mode);
2551 }
2552 }
2553
2554 if (current_link_up == 1) {
2555 tp->link_config.active_speed = SPEED_1000;
2556 tp->link_config.active_duplex = DUPLEX_FULL;
2557 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2558 LED_CTRL_LNKLED_OVERRIDE |
2559 LED_CTRL_1000MBPS_ON));
2560 } else {
2561 tp->link_config.active_speed = SPEED_INVALID;
2562 tp->link_config.active_duplex = DUPLEX_INVALID;
2563 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2564 LED_CTRL_LNKLED_OVERRIDE |
2565 LED_CTRL_TRAFFIC_OVERRIDE));
2566 }
2567
2568 if (current_link_up != netif_carrier_ok(tp->dev)) {
2569 if (current_link_up)
2570 netif_carrier_on(tp->dev);
2571 else
2572 netif_carrier_off(tp->dev);
2573 tg3_link_report(tp);
2574 } else {
2575 u32 now_pause_cfg =
2576 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2577 TG3_FLAG_TX_PAUSE);
2578 if (orig_pause_cfg != now_pause_cfg ||
2579 orig_active_speed != tp->link_config.active_speed ||
2580 orig_active_duplex != tp->link_config.active_duplex)
2581 tg3_link_report(tp);
2582 }
2583
2584 return 0;
2585}
2586
747e8f8b
MC		 2587static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2588{
2589 int current_link_up, err = 0;
2590 u32 bmsr, bmcr;
2591 u16 current_speed;
2592 u8 current_duplex;
2593
2594 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2595 tw32_f(MAC_MODE, tp->mac_mode);
2596 udelay(40);
2597
2598 tw32(MAC_EVENT, 0);
2599
2600 tw32_f(MAC_STATUS,
2601 (MAC_STATUS_SYNC_CHANGED |
2602 MAC_STATUS_CFG_CHANGED |
2603 MAC_STATUS_MI_COMPLETION |
2604 MAC_STATUS_LNKSTATE_CHANGED));
2605 udelay(40);
2606
2607 if (force_reset)
2608 tg3_phy_reset(tp);
2609
2610 current_link_up = 0;
2611 current_speed = SPEED_INVALID;
2612 current_duplex = DUPLEX_INVALID;
2613
2614 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2615 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2616
2617 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2618
2619 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2620 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2621 /* do nothing, just check for link up at the end */
2622 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2623 u32 adv, new_adv;
2624
2625 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2626 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2627 ADVERTISE_1000XPAUSE |
2628 ADVERTISE_1000XPSE_ASYM |
2629 ADVERTISE_SLCT);
2630
2631 /* Always advertise symmetric PAUSE just like copper */
2632 new_adv |= ADVERTISE_1000XPAUSE;
2633
2634 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2635 new_adv |= ADVERTISE_1000XHALF;
2636 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2637 new_adv |= ADVERTISE_1000XFULL;
2638
2639 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2640 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2641 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2642 tg3_writephy(tp, MII_BMCR, bmcr);
2643
2644 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2645 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2646 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2647
2648 return err;
2649 }
2650 } else {
2651 u32 new_bmcr;
2652
2653 bmcr &= ~BMCR_SPEED1000;
2654 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2655
2656 if (tp->link_config.duplex == DUPLEX_FULL)
2657 new_bmcr |= BMCR_FULLDPLX;
2658
2659 if (new_bmcr != bmcr) {
2660 /* BMCR_SPEED1000 is a reserved bit that needs
2661 * to be set on write.
2662 */
2663 new_bmcr |= BMCR_SPEED1000;
2664
2665 /* Force a linkdown */
2666 if (netif_carrier_ok(tp->dev)) {
2667 u32 adv;
2668
2669 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2670 adv &= ~(ADVERTISE_1000XFULL |
2671 ADVERTISE_1000XHALF |
2672 ADVERTISE_SLCT);
2673 tg3_writephy(tp, MII_ADVERTISE, adv);
2674 tg3_writephy(tp, MII_BMCR, bmcr |
2675 BMCR_ANRESTART |
2676 BMCR_ANENABLE);
2677 udelay(10);
2678 netif_carrier_off(tp->dev);
2679 }
2680 tg3_writephy(tp, MII_BMCR, new_bmcr);
2681 bmcr = new_bmcr;
2682 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2683 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2684 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2685 }
2686 }
2687
2688 if (bmsr & BMSR_LSTATUS) {
2689 current_speed = SPEED_1000;
2690 current_link_up = 1;
2691 if (bmcr & BMCR_FULLDPLX)
2692 current_duplex = DUPLEX_FULL;
2693 else
2694 current_duplex = DUPLEX_HALF;
2695
2696 if (bmcr & BMCR_ANENABLE) {
2697 u32 local_adv, remote_adv, common;
2698
2699 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2700 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2701 common = local_adv & remote_adv;
2702 if (common & (ADVERTISE_1000XHALF |
2703 ADVERTISE_1000XFULL)) {
2704 if (common & ADVERTISE_1000XFULL)
2705 current_duplex = DUPLEX_FULL;
2706 else
2707 current_duplex = DUPLEX_HALF;
2708
2709 tg3_setup_flow_control(tp, local_adv,
2710 remote_adv);
2711 }
2712 else
2713 current_link_up = 0;
2714 }
2715 }
2716
2717 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2718 if (tp->link_config.active_duplex == DUPLEX_HALF)
2719 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2720
2721 tw32_f(MAC_MODE, tp->mac_mode);
2722 udelay(40);
2723
2724 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2725
2726 tp->link_config.active_speed = current_speed;
2727 tp->link_config.active_duplex = current_duplex;
2728
2729 if (current_link_up != netif_carrier_ok(tp->dev)) {
2730 if (current_link_up)
2731 netif_carrier_on(tp->dev);
2732 else {
2733 netif_carrier_off(tp->dev);
2734 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2735 }
2736 tg3_link_report(tp);
2737 }
2738 return err;
2739}
2740
2741static void tg3_serdes_parallel_detect(struct tg3 *tp)
2742{
2743 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2744 /* Give autoneg time to complete. */
2745 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2746 return;
2747 }
2748 if (!netif_carrier_ok(tp->dev) &&
2749 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2750 u32 bmcr;
2751
2752 tg3_readphy(tp, MII_BMCR, &bmcr);
2753 if (bmcr & BMCR_ANENABLE) {
2754 u32 phy1, phy2;
2755
2756 /* Select shadow register 0x1f */
2757 tg3_writephy(tp, 0x1c, 0x7c00);
2758 tg3_readphy(tp, 0x1c, &phy1);
2759
2760 /* Select expansion interrupt status register */
2761 tg3_writephy(tp, 0x17, 0x0f01);
2762 tg3_readphy(tp, 0x15, &phy2);
2763 tg3_readphy(tp, 0x15, &phy2);
2764
2765 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2766 /* We have signal detect and not receiving
2767 * config code words, link is up by parallel
2768 * detection.
2769 */
2770
2771 bmcr &= ~BMCR_ANENABLE;
2772 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2773 tg3_writephy(tp, MII_BMCR, bmcr);
2774 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2775 }
2776 }
2777 }
2778 else if (netif_carrier_ok(tp->dev) &&
2779 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2780 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2781 u32 phy2;
2782
2783 /* Select expansion interrupt status register */
2784 tg3_writephy(tp, 0x17, 0x0f01);
2785 tg3_readphy(tp, 0x15, &phy2);
2786 if (phy2 & 0x20) {
2787 u32 bmcr;
2788
2789 /* Config code words received, turn on autoneg. */
2790 tg3_readphy(tp, MII_BMCR, &bmcr);
2791 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2792
2793 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2794
2795 }
2796 }
2797}
2798
1da177e4
LT		 2799static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2800{
2801 int err;
2802
2803 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2804 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2805 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2806 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2807 } else {
2808 err = tg3_setup_copper_phy(tp, force_reset);
2809 }
2810
2811 if (tp->link_config.active_speed == SPEED_1000 &&
2812 tp->link_config.active_duplex == DUPLEX_HALF)
2813 tw32(MAC_TX_LENGTHS,
2814 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2815 (6 << TX_LENGTHS_IPG_SHIFT) |
2816 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2817 else
2818 tw32(MAC_TX_LENGTHS,
2819 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2820 (6 << TX_LENGTHS_IPG_SHIFT) |
2821 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2822
2823 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2824 if (netif_carrier_ok(tp->dev)) {
2825 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 2826 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 2827 } else {
2828 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2829 }
2830 }
2831
2832 return err;
2833}
2834
2835/* Tigon3 never reports partial packet sends. So we do not
2836 * need special logic to handle SKBs that have not had all
2837 * of their frags sent yet, like SunGEM does.
2838 */
2839static void tg3_tx(struct tg3 *tp)
2840{
2841 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2842 u32 sw_idx = tp->tx_cons;
2843
2844 while (sw_idx != hw_idx) {
2845 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2846 struct sk_buff *skb = ri->skb;
2847 int i;
2848
2849 if (unlikely(skb == NULL))
2850 BUG();
2851
2852 pci_unmap_single(tp->pdev,
2853 pci_unmap_addr(ri, mapping),
2854 skb_headlen(skb),
2855 PCI_DMA_TODEVICE);
2856
2857 ri->skb = NULL;
2858
2859 sw_idx = NEXT_TX(sw_idx);
2860
2861 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2862 if (unlikely(sw_idx == hw_idx))
2863 BUG();
2864
2865 ri = &tp->tx_buffers[sw_idx];
2866 if (unlikely(ri->skb != NULL))
2867 BUG();
2868
2869 pci_unmap_page(tp->pdev,
2870 pci_unmap_addr(ri, mapping),
2871 skb_shinfo(skb)->frags[i].size,
2872 PCI_DMA_TODEVICE);
2873
2874 sw_idx = NEXT_TX(sw_idx);
2875 }
2876
f47c11ee 2877 dev_kfree_skb(skb);
1da177e4
LT		 2878 }
2879
2880 tp->tx_cons = sw_idx;
2881
51b91468
MC		 2882 if (unlikely(netif_queue_stopped(tp->dev))) {
2883 spin_lock(&tp->tx_lock);
2884 if (netif_queue_stopped(tp->dev) &&
2885 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2886 netif_wake_queue(tp->dev);
2887 spin_unlock(&tp->tx_lock);
2888 }
1da177e4
LT		 2889}
2890
2891/* Returns size of skb allocated or < 0 on error.
2892 *
2893 * We only need to fill in the address because the other members
2894 * of the RX descriptor are invariant, see tg3_init_rings.
2895 *
2896 * Note the purposeful assymetry of cpu vs. chip accesses. For
2897 * posting buffers we only dirty the first cache line of the RX
2898 * descriptor (containing the address). Whereas for the RX status
2899 * buffers the cpu only reads the last cacheline of the RX descriptor
2900 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2901 */
2902static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2903 int src_idx, u32 dest_idx_unmasked)
2904{
2905 struct tg3_rx_buffer_desc *desc;
2906 struct ring_info *map, *src_map;
2907 struct sk_buff *skb;
2908 dma_addr_t mapping;
2909 int skb_size, dest_idx;
2910
2911 src_map = NULL;
2912 switch (opaque_key) {
2913 case RXD_OPAQUE_RING_STD:
2914 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2915 desc = &tp->rx_std[dest_idx];
2916 map = &tp->rx_std_buffers[dest_idx];
2917 if (src_idx >= 0)
2918 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 2919 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 2920 break;
2921
2922 case RXD_OPAQUE_RING_JUMBO:
2923 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2924 desc = &tp->rx_jumbo[dest_idx];
2925 map = &tp->rx_jumbo_buffers[dest_idx];
2926 if (src_idx >= 0)
2927 src_map = &tp->rx_jumbo_buffers[src_idx];
2928 skb_size = RX_JUMBO_PKT_BUF_SZ;
2929 break;
2930
2931 default:
2932 return -EINVAL;
2933 };
2934
2935 /* Do not overwrite any of the map or rp information
2936 * until we are sure we can commit to a new buffer.
2937 *
2938 * Callers depend upon this behavior and assume that
2939 * we leave everything unchanged if we fail.
2940 */
2941 skb = dev_alloc_skb(skb_size);
2942 if (skb == NULL)
2943 return -ENOMEM;
2944
2945 skb->dev = tp->dev;
2946 skb_reserve(skb, tp->rx_offset);
2947
2948 mapping = pci_map_single(tp->pdev, skb->data,
2949 skb_size - tp->rx_offset,
2950 PCI_DMA_FROMDEVICE);
2951
2952 map->skb = skb;
2953 pci_unmap_addr_set(map, mapping, mapping);
2954
2955 if (src_map != NULL)
2956 src_map->skb = NULL;
2957
2958 desc->addr_hi = ((u64)mapping >> 32);
2959 desc->addr_lo = ((u64)mapping & 0xffffffff);
2960
2961 return skb_size;
2962}
2963
2964/* We only need to move over in the address because the other
2965 * members of the RX descriptor are invariant. See notes above
2966 * tg3_alloc_rx_skb for full details.
2967 */
2968static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2969 int src_idx, u32 dest_idx_unmasked)
2970{
2971 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2972 struct ring_info *src_map, *dest_map;
2973 int dest_idx;
2974
2975 switch (opaque_key) {
2976 case RXD_OPAQUE_RING_STD:
2977 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2978 dest_desc = &tp->rx_std[dest_idx];
2979 dest_map = &tp->rx_std_buffers[dest_idx];
2980 src_desc = &tp->rx_std[src_idx];
2981 src_map = &tp->rx_std_buffers[src_idx];
2982 break;
2983
2984 case RXD_OPAQUE_RING_JUMBO:
2985 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2986 dest_desc = &tp->rx_jumbo[dest_idx];
2987 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2988 src_desc = &tp->rx_jumbo[src_idx];
2989 src_map = &tp->rx_jumbo_buffers[src_idx];
2990 break;
2991
2992 default:
2993 return;
2994 };
2995
2996 dest_map->skb = src_map->skb;
2997 pci_unmap_addr_set(dest_map, mapping,
2998 pci_unmap_addr(src_map, mapping));
2999 dest_desc->addr_hi = src_desc->addr_hi;
3000 dest_desc->addr_lo = src_desc->addr_lo;
3001
3002 src_map->skb = NULL;
3003}
3004
3005#if TG3_VLAN_TAG_USED
3006static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3007{
3008 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3009}
3010#endif
3011
3012/* The RX ring scheme is composed of multiple rings which post fresh
3013 * buffers to the chip, and one special ring the chip uses to report
3014 * status back to the host.
3015 *
3016 * The special ring reports the status of received packets to the
3017 * host. The chip does not write into the original descriptor the
3018 * RX buffer was obtained from. The chip simply takes the original
3019 * descriptor as provided by the host, updates the status and length
3020 * field, then writes this into the next status ring entry.
3021 *
3022 * Each ring the host uses to post buffers to the chip is described
3023 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3024 * it is first placed into the on-chip ram. When the packet's length
3025 * is known, it walks down the TG3_BDINFO entries to select the ring.
3026 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3027 * which is within the range of the new packet's length is chosen.
3028 *
3029 * The "separate ring for rx status" scheme may sound queer, but it makes
3030 * sense from a cache coherency perspective. If only the host writes
3031 * to the buffer post rings, and only the chip writes to the rx status
3032 * rings, then cache lines never move beyond shared-modified state.
3033 * If both the host and chip were to write into the same ring, cache line
3034 * eviction could occur since both entities want it in an exclusive state.
3035 */
3036static int tg3_rx(struct tg3 *tp, int budget)
3037{
3038 u32 work_mask;
483ba50b
MC		 3039 u32 sw_idx = tp->rx_rcb_ptr;
3040 u16 hw_idx;
1da177e4
LT		 3041 int received;
3042
3043 hw_idx = tp->hw_status->idx[0].rx_producer;
3044 /*
3045 * We need to order the read of hw_idx and the read of
3046 * the opaque cookie.
3047 */
3048 rmb();
1da177e4
LT		 3049 work_mask = 0;
3050 received = 0;
3051 while (sw_idx != hw_idx && budget > 0) {
3052 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3053 unsigned int len;
3054 struct sk_buff *skb;
3055 dma_addr_t dma_addr;
3056 u32 opaque_key, desc_idx, *post_ptr;
3057
3058 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3059 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3060 if (opaque_key == RXD_OPAQUE_RING_STD) {
3061 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3062 mapping);
3063 skb = tp->rx_std_buffers[desc_idx].skb;
3064 post_ptr = &tp->rx_std_ptr;
3065 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3066 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3067 mapping);
3068 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3069 post_ptr = &tp->rx_jumbo_ptr;
3070 }
3071 else {
3072 goto next_pkt_nopost;
3073 }
3074
3075 work_mask |= opaque_key;
3076
3077 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3078 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3079 drop_it:
3080 tg3_recycle_rx(tp, opaque_key,
3081 desc_idx, *post_ptr);
3082 drop_it_no_recycle:
3083 /* Other statistics kept track of by card. */
3084 tp->net_stats.rx_dropped++;
3085 goto next_pkt;
3086 }
3087
3088 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3089
3090 if (len > RX_COPY_THRESHOLD
3091 && tp->rx_offset == 2
3092 /* rx_offset != 2 iff this is a 5701 card running
3093 * in PCI-X mode [see tg3_get_invariants()] */
3094 ) {
3095 int skb_size;
3096
3097 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3098 desc_idx, *post_ptr);
3099 if (skb_size < 0)
3100 goto drop_it;
3101
3102 pci_unmap_single(tp->pdev, dma_addr,
3103 skb_size - tp->rx_offset,
3104 PCI_DMA_FROMDEVICE);
3105
3106 skb_put(skb, len);
3107 } else {
3108 struct sk_buff *copy_skb;
3109
3110 tg3_recycle_rx(tp, opaque_key,
3111 desc_idx, *post_ptr);
3112
3113 copy_skb = dev_alloc_skb(len + 2);
3114 if (copy_skb == NULL)
3115 goto drop_it_no_recycle;
3116
3117 copy_skb->dev = tp->dev;
3118 skb_reserve(copy_skb, 2);
3119 skb_put(copy_skb, len);
3120 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3121 memcpy(copy_skb->data, skb->data, len);
3122 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3123
3124 /* We'll reuse the original ring buffer. */
3125 skb = copy_skb;
3126 }
3127
3128 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3129 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3130 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3131 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3132 skb->ip_summed = CHECKSUM_UNNECESSARY;
3133 else
3134 skb->ip_summed = CHECKSUM_NONE;
3135
3136 skb->protocol = eth_type_trans(skb, tp->dev);
3137#if TG3_VLAN_TAG_USED
3138 if (tp->vlgrp != NULL &&
3139 desc->type_flags & RXD_FLAG_VLAN) {
3140 tg3_vlan_rx(tp, skb,
3141 desc->err_vlan & RXD_VLAN_MASK);
3142 } else
3143#endif
3144 netif_receive_skb(skb);
3145
3146 tp->dev->last_rx = jiffies;
3147 received++;
3148 budget--;
3149
3150next_pkt:
3151 (*post_ptr)++;
3152next_pkt_nopost:
483ba50b
MC		 3153 sw_idx++;
3154 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
52f6d697
MC		 3155
3156 /* Refresh hw_idx to see if there is new work */
3157 if (sw_idx == hw_idx) {
3158 hw_idx = tp->hw_status->idx[0].rx_producer;
3159 rmb();
3160 }
1da177e4
LT		 3161 }
3162
3163 /* ACK the status ring. */
483ba50b
MC		 3164 tp->rx_rcb_ptr = sw_idx;
3165 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3166
3167 /* Refill RX ring(s). */
3168 if (work_mask & RXD_OPAQUE_RING_STD) {
3169 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3170 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3171 sw_idx);
3172 }
3173 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3174 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3175 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3176 sw_idx);
3177 }
3178 mmiowb();
3179
3180 return received;
3181}
3182
3183static int tg3_poll(struct net_device *netdev, int *budget)
3184{
3185 struct tg3 *tp = netdev_priv(netdev);
3186 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3187 int done;
3188
1da177e4
LT		 3189 /* handle link change and other phy events */
3190 if (!(tp->tg3_flags &
3191 (TG3_FLAG_USE_LINKCHG_REG |
3192 TG3_FLAG_POLL_SERDES))) {
3193 if (sblk->status & SD_STATUS_LINK_CHG) {
3194 sblk->status = SD_STATUS_UPDATED |
3195 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3196 spin_lock(&tp->lock);
1da177e4 3197 tg3_setup_phy(tp, 0);
f47c11ee 3198 spin_unlock(&tp->lock);
1da177e4
LT		 3199 }
3200 }
3201
3202 /* run TX completion thread */
3203 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3204 tg3_tx(tp);
1da177e4
LT		 3205 }
3206
1da177e4
LT		 3207 /* run RX thread, within the bounds set by NAPI.
3208 * All RX "locking" is done by ensuring outside
3209 * code synchronizes with dev->poll()
3210 */
1da177e4
LT		 3211 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3212 int orig_budget = *budget;
3213 int work_done;
3214
3215 if (orig_budget > netdev->quota)
3216 orig_budget = netdev->quota;
3217
3218 work_done = tg3_rx(tp, orig_budget);
3219
3220 *budget -= work_done;
3221 netdev->quota -= work_done;
1da177e4
LT		 3222 }
3223
38f3843e 3224 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
f7383c22 3225 tp->last_tag = sblk->status_tag;
38f3843e
MC		 3226 rmb();
3227 } else
3228 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3229
1da177e4 3230 /* if no more work, tell net stack and NIC we're done */
f7383c22 3231 done = !tg3_has_work(tp);
1da177e4 3232 if (done) {
f47c11ee 3233 netif_rx_complete(netdev);
1da177e4 3234 tg3_restart_ints(tp);
1da177e4
LT		 3235 }
3236
3237 return (done ? 0 : 1);
3238}
3239
f47c11ee
DM		 3240static void tg3_irq_quiesce(struct tg3 *tp)
3241{
3242 BUG_ON(tp->irq_sync);
3243
3244 tp->irq_sync = 1;
3245 smp_mb();
3246
3247 synchronize_irq(tp->pdev->irq);
3248}
3249
3250static inline int tg3_irq_sync(struct tg3 *tp)
3251{
3252 return tp->irq_sync;
3253}
3254
3255/* Fully shutdown all tg3 driver activity elsewhere in the system.
3256 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3257 * with as well. Most of the time, this is not necessary except when
3258 * shutting down the device.
3259 */
3260static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3261{
3262 if (irq_sync)
3263 tg3_irq_quiesce(tp);
3264 spin_lock_bh(&tp->lock);
3265 spin_lock(&tp->tx_lock);
3266}
3267
3268static inline void tg3_full_unlock(struct tg3 *tp)
3269{
3270 spin_unlock(&tp->tx_lock);
3271 spin_unlock_bh(&tp->lock);
3272}
3273
88b06bc2
MC		 3274/* MSI ISR - No need to check for interrupt sharing and no need to
3275 * flush status block and interrupt mailbox. PCI ordering rules
3276 * guarantee that MSI will arrive after the status block.
3277 */
3278static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3279{
3280 struct net_device *dev = dev_id;
3281 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3282
61487480
MC		 3283 prefetch(tp->hw_status);
3284 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3285 /*
fac9b83e 3286 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3287 * chip-internal interrupt pending events.
fac9b83e 3288 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3289 * NIC to stop sending us irqs, engaging "in-intr-handler"
3290 * event coalescing.
3291 */
3292 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3293 if (likely(!tg3_irq_sync(tp)))
88b06bc2 3294 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3295
88b06bc2
MC		 3296 return IRQ_RETVAL(1);
3297}
3298
1da177e4
LT		 3299static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3300{
3301 struct net_device *dev = dev_id;
3302 struct tg3 *tp = netdev_priv(dev);
3303 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3304 unsigned int handled = 1;
3305
1da177e4
LT		 3306 /* In INTx mode, it is possible for the interrupt to arrive at
3307 * the CPU before the status block posted prior to the interrupt.
3308 * Reading the PCI State register will confirm whether the
3309 * interrupt is ours and will flush the status block.
3310 */
3311 if ((sblk->status & SD_STATUS_UPDATED) ||
3312 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3313 /*
fac9b83e 3314 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 3315 * chip-internal interrupt pending events.
fac9b83e 3316 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 3317 * NIC to stop sending us irqs, engaging "in-intr-handler"
3318 * event coalescing.
3319 */
3320 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3321 0x00000001);
f47c11ee
DM		 3322 if (tg3_irq_sync(tp))
3323 goto out;
fac9b83e 3324 sblk->status &= ~SD_STATUS_UPDATED;
61487480
MC		 3325 if (likely(tg3_has_work(tp))) {
3326 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
fac9b83e 3327 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3328 } else {
fac9b83e
DM		 3329 /* No work, shared interrupt perhaps? re-enable
3330 * interrupts, and flush that PCI write
3331 */
09ee929c 3332 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3333 0x00000000);
fac9b83e
DM		 3334 }
3335 } else { /* shared interrupt */
3336 handled = 0;
3337 }
f47c11ee 3338out:
fac9b83e
DM		 3339 return IRQ_RETVAL(handled);
3340}
3341
3342static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3343{
3344 struct net_device *dev = dev_id;
3345 struct tg3 *tp = netdev_priv(dev);
3346 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3347 unsigned int handled = 1;
3348
fac9b83e
DM		 3349 /* In INTx mode, it is possible for the interrupt to arrive at
3350 * the CPU before the status block posted prior to the interrupt.
3351 * Reading the PCI State register will confirm whether the
3352 * interrupt is ours and will flush the status block.
3353 */
38f3843e 3354 if ((sblk->status_tag != tp->last_tag) ||
fac9b83e 3355 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3356 /*
fac9b83e
DM		 3357 * writing any value to intr-mbox-0 clears PCI INTA# and
3358 * chip-internal interrupt pending events.
3359 * writing non-zero to intr-mbox-0 additional tells the
3360 * NIC to stop sending us irqs, engaging "in-intr-handler"
3361 * event coalescing.
1da177e4 3362 */
fac9b83e
DM		 3363 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3364 0x00000001);
f47c11ee
DM		 3365 if (tg3_irq_sync(tp))
3366 goto out;
38f3843e 3367 if (netif_rx_schedule_prep(dev)) {
61487480 3368 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
38f3843e
MC		 3369 /* Update last_tag to mark that this status has been
3370 * seen. Because interrupt may be shared, we may be
3371 * racing with tg3_poll(), so only update last_tag
3372 * if tg3_poll() is not scheduled.
1da177e4 3373 */
38f3843e
MC		 3374 tp->last_tag = sblk->status_tag;
3375 __netif_rx_schedule(dev);
1da177e4
LT		 3376 }
3377 } else { /* shared interrupt */
3378 handled = 0;
3379 }
f47c11ee 3380out:
1da177e4
LT		 3381 return IRQ_RETVAL(handled);
3382}
3383
7938109f
MC		 3384/* ISR for interrupt test */
3385static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3386 struct pt_regs *regs)
3387{
3388 struct net_device *dev = dev_id;
3389 struct tg3 *tp = netdev_priv(dev);
3390 struct tg3_hw_status *sblk = tp->hw_status;
3391
f9804ddb
MC		 3392 if ((sblk->status & SD_STATUS_UPDATED) ||
3393 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7938109f
MC		 3394 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3395 0x00000001);
3396 return IRQ_RETVAL(1);
3397 }
3398 return IRQ_RETVAL(0);
3399}
3400
1da177e4 3401static int tg3_init_hw(struct tg3 *);
944d980e 3402static int tg3_halt(struct tg3 *, int, int);
1da177e4
LT		 3403
3404#ifdef CONFIG_NET_POLL_CONTROLLER
3405static void tg3_poll_controller(struct net_device *dev)
3406{
88b06bc2
MC		 3407 struct tg3 *tp = netdev_priv(dev);
3408
3409 tg3_interrupt(tp->pdev->irq, dev, NULL);
1da177e4
LT		 3410}
3411#endif
3412
3413static void tg3_reset_task(void *_data)
3414{
3415 struct tg3 *tp = _data;
3416 unsigned int restart_timer;
3417
3418 tg3_netif_stop(tp);
3419
f47c11ee 3420 tg3_full_lock(tp, 1);
1da177e4
LT		 3421
3422 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3423 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3424
944d980e 3425 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
1da177e4
LT		 3426 tg3_init_hw(tp);
3427
3428 tg3_netif_start(tp);
3429
f47c11ee 3430 tg3_full_unlock(tp);
1da177e4
LT		 3431
3432 if (restart_timer)
3433 mod_timer(&tp->timer, jiffies + 1);
3434}
3435
3436static void tg3_tx_timeout(struct net_device *dev)
3437{
3438 struct tg3 *tp = netdev_priv(dev);
3439
3440 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3441 dev->name);
3442
3443 schedule_work(&tp->reset_task);
3444}
3445
c58ec932
MC		 3446/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3447static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3448{
3449 u32 base = (u32) mapping & 0xffffffff;
3450
3451 return ((base > 0xffffdcc0) &&
3452 (base + len + 8 < base));
3453}
3454
1da177e4
LT		 3455static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3456
3457static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3458 u32 last_plus_one, u32 *start,
3459 u32 base_flags, u32 mss)
1da177e4
LT		 3460{
3461 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3462 dma_addr_t new_addr = 0;
1da177e4 3463 u32 entry = *start;
c58ec932 3464 int i, ret = 0;
1da177e4
LT		 3465
3466 if (!new_skb) {
c58ec932
MC		 3467 ret = -1;
3468 } else {
3469 /* New SKB is guaranteed to be linear. */
3470 entry = *start;
3471 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3472 PCI_DMA_TODEVICE);
3473 /* Make sure new skb does not cross any 4G boundaries.
3474 * Drop the packet if it does.
3475 */
3476 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3477 ret = -1;
3478 dev_kfree_skb(new_skb);
3479 new_skb = NULL;
3480 } else {
3481 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3482 base_flags, 1 | (mss << 1));
3483 *start = NEXT_TX(entry);
3484 }
1da177e4
LT		 3485 }
3486
1da177e4
LT		 3487 /* Now clean up the sw ring entries. */
3488 i = 0;
3489 while (entry != last_plus_one) {
3490 int len;
3491
3492 if (i == 0)
3493 len = skb_headlen(skb);
3494 else
3495 len = skb_shinfo(skb)->frags[i-1].size;
3496 pci_unmap_single(tp->pdev,
3497 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3498 len, PCI_DMA_TODEVICE);
3499 if (i == 0) {
3500 tp->tx_buffers[entry].skb = new_skb;
3501 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3502 } else {
3503 tp->tx_buffers[entry].skb = NULL;
3504 }
3505 entry = NEXT_TX(entry);
3506 i++;
3507 }
3508
3509 dev_kfree_skb(skb);
3510
c58ec932 3511 return ret;
1da177e4
LT		 3512}
3513
3514static void tg3_set_txd(struct tg3 *tp, int entry,
3515 dma_addr_t mapping, int len, u32 flags,
3516 u32 mss_and_is_end)
3517{
3518 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3519 int is_end = (mss_and_is_end & 0x1);
3520 u32 mss = (mss_and_is_end >> 1);
3521 u32 vlan_tag = 0;
3522
3523 if (is_end)
3524 flags |= TXD_FLAG_END;
3525 if (flags & TXD_FLAG_VLAN) {
3526 vlan_tag = flags >> 16;
3527 flags &= 0xffff;
3528 }
3529 vlan_tag |= (mss << TXD_MSS_SHIFT);
3530
3531 txd->addr_hi = ((u64) mapping >> 32);
3532 txd->addr_lo = ((u64) mapping & 0xffffffff);
3533 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3534 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3535}
3536
1da177e4
LT		 3537static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3538{
3539 struct tg3 *tp = netdev_priv(dev);
3540 dma_addr_t mapping;
1da177e4
LT		 3541 u32 len, entry, base_flags, mss;
3542 int would_hit_hwbug;
1da177e4
LT		 3543
3544 len = skb_headlen(skb);
3545
3546 /* No BH disabling for tx_lock here. We are running in BH disabled
3547 * context and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 3548 * interrupt. Furthermore, IRQ processing runs lockless so we have
3549 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 3550 */
f47c11ee 3551 if (!spin_trylock(&tp->tx_lock))
1da177e4 3552 return NETDEV_TX_LOCKED;
1da177e4
LT		 3553
3554 /* This is a hard error, log it. */
3555 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3556 netif_stop_queue(dev);
f47c11ee 3557 spin_unlock(&tp->tx_lock);
1da177e4
LT		 3558 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3559 dev->name);
3560 return NETDEV_TX_BUSY;
3561 }
3562
3563 entry = tp->tx_prod;
3564 base_flags = 0;
3565 if (skb->ip_summed == CHECKSUM_HW)
3566 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3567#if TG3_TSO_SUPPORT != 0
3568 mss = 0;
3569 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3570 (mss = skb_shinfo(skb)->tso_size) != 0) {
3571 int tcp_opt_len, ip_tcp_len;
3572
3573 if (skb_header_cloned(skb) &&
3574 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3575 dev_kfree_skb(skb);
3576 goto out_unlock;
3577 }
3578
3579 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3580 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3581
3582 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3583 TXD_FLAG_CPU_POST_DMA);
3584
3585 skb->nh.iph->check = 0;
3586 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3587 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3588 skb->h.th->check = 0;
3589 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3590 }
3591 else {
3592 skb->h.th->check =
3593 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3594 skb->nh.iph->daddr,
3595 0, IPPROTO_TCP, 0);
3596 }
3597
3598 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3599 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3600 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3601 int tsflags;
3602
3603 tsflags = ((skb->nh.iph->ihl - 5) +
3604 (tcp_opt_len >> 2));
3605 mss |= (tsflags << 11);
3606 }
3607 } else {
3608 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3609 int tsflags;
3610
3611 tsflags = ((skb->nh.iph->ihl - 5) +
3612 (tcp_opt_len >> 2));
3613 base_flags |= tsflags << 12;
3614 }
3615 }
3616 }
3617#else
3618 mss = 0;
3619#endif
3620#if TG3_VLAN_TAG_USED
3621 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3622 base_flags |= (TXD_FLAG_VLAN |
3623 (vlan_tx_tag_get(skb) << 16));
3624#endif
3625
3626 /* Queue skb data, a.k.a. the main skb fragment. */
3627 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3628
3629 tp->tx_buffers[entry].skb = skb;
3630 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3631
3632 would_hit_hwbug = 0;
3633
3634 if (tg3_4g_overflow_test(mapping, len))
c58ec932 3635 would_hit_hwbug = 1;
1da177e4
LT		 3636
3637 tg3_set_txd(tp, entry, mapping, len, base_flags,
3638 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3639
3640 entry = NEXT_TX(entry);
3641
3642 /* Now loop through additional data fragments, and queue them. */
3643 if (skb_shinfo(skb)->nr_frags > 0) {
3644 unsigned int i, last;
3645
3646 last = skb_shinfo(skb)->nr_frags - 1;
3647 for (i = 0; i <= last; i++) {
3648 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3649
3650 len = frag->size;
3651 mapping = pci_map_page(tp->pdev,
3652 frag->page,
3653 frag->page_offset,
3654 len, PCI_DMA_TODEVICE);
3655
3656 tp->tx_buffers[entry].skb = NULL;
3657 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3658
c58ec932
MC		 3659 if (tg3_4g_overflow_test(mapping, len))
3660 would_hit_hwbug = 1;
1da177e4
LT		 3661
3662 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3663 tg3_set_txd(tp, entry, mapping, len,
3664 base_flags, (i == last)|(mss << 1));
3665 else
3666 tg3_set_txd(tp, entry, mapping, len,
3667 base_flags, (i == last));
3668
3669 entry = NEXT_TX(entry);
3670 }
3671 }
3672
3673 if (would_hit_hwbug) {
3674 u32 last_plus_one = entry;
3675 u32 start;
1da177e4 3676
c58ec932
MC		 3677 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3678 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 3679
3680 /* If the workaround fails due to memory/mapping
3681 * failure, silently drop this packet.
3682 */
c58ec932
MC		 3683 if (tigon3_4gb_hwbug_workaround(tp, skb, last_plus_one,
3684 &start, base_flags, mss))
1da177e4
LT		 3685 goto out_unlock;
3686
3687 entry = start;
3688 }
3689
3690 /* Packets are ready, update Tx producer idx local and on card. */
3691 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3692
3693 tp->tx_prod = entry;
51b91468 3694 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
1da177e4 3695 netif_stop_queue(dev);
51b91468
MC		 3696 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3697 netif_wake_queue(tp->dev);
3698 }
1da177e4
LT		 3699
3700out_unlock:
3701 mmiowb();
f47c11ee 3702 spin_unlock(&tp->tx_lock);
1da177e4
LT		 3703
3704 dev->trans_start = jiffies;
3705
3706 return NETDEV_TX_OK;
3707}
3708
3709static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3710 int new_mtu)
3711{
3712 dev->mtu = new_mtu;
3713
ef7f5ec0
MC		 3714 if (new_mtu > ETH_DATA_LEN) {
3715 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
3716 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3717 ethtool_op_set_tso(dev, 0);
3718 }
3719 else
3720 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3721 } else {
3722 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
3723 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 3724 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 3725 }
1da177e4
LT		 3726}
3727
3728static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3729{
3730 struct tg3 *tp = netdev_priv(dev);
3731
3732 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3733 return -EINVAL;
3734
3735 if (!netif_running(dev)) {
3736 /* We'll just catch it later when the
3737 * device is up'd.
3738 */
3739 tg3_set_mtu(dev, tp, new_mtu);
3740 return 0;
3741 }
3742
3743 tg3_netif_stop(tp);
f47c11ee
DM		 3744
3745 tg3_full_lock(tp, 1);
1da177e4 3746
944d980e 3747 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 3748
3749 tg3_set_mtu(dev, tp, new_mtu);
3750
3751 tg3_init_hw(tp);
3752
3753 tg3_netif_start(tp);
3754
f47c11ee 3755 tg3_full_unlock(tp);
1da177e4
LT		 3756
3757 return 0;
3758}
3759
3760/* Free up pending packets in all rx/tx rings.
3761 *
3762 * The chip has been shut down and the driver detached from
3763 * the networking, so no interrupts or new tx packets will
3764 * end up in the driver. tp->{tx,}lock is not held and we are not
3765 * in an interrupt context and thus may sleep.
3766 */
3767static void tg3_free_rings(struct tg3 *tp)
3768{
3769 struct ring_info *rxp;
3770 int i;
3771
3772 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3773 rxp = &tp->rx_std_buffers[i];
3774
3775 if (rxp->skb == NULL)
3776 continue;
3777 pci_unmap_single(tp->pdev,
3778 pci_unmap_addr(rxp, mapping),
7e72aad4 3779 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 3780 PCI_DMA_FROMDEVICE);
3781 dev_kfree_skb_any(rxp->skb);
3782 rxp->skb = NULL;
3783 }
3784
3785 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3786 rxp = &tp->rx_jumbo_buffers[i];
3787
3788 if (rxp->skb == NULL)
3789 continue;
3790 pci_unmap_single(tp->pdev,
3791 pci_unmap_addr(rxp, mapping),
3792 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3793 PCI_DMA_FROMDEVICE);
3794 dev_kfree_skb_any(rxp->skb);
3795 rxp->skb = NULL;
3796 }
3797
3798 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3799 struct tx_ring_info *txp;
3800 struct sk_buff *skb;
3801 int j;
3802
3803 txp = &tp->tx_buffers[i];
3804 skb = txp->skb;
3805
3806 if (skb == NULL) {
3807 i++;
3808 continue;
3809 }
3810
3811 pci_unmap_single(tp->pdev,
3812 pci_unmap_addr(txp, mapping),
3813 skb_headlen(skb),
3814 PCI_DMA_TODEVICE);
3815 txp->skb = NULL;
3816
3817 i++;
3818
3819 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3820 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3821 pci_unmap_page(tp->pdev,
3822 pci_unmap_addr(txp, mapping),
3823 skb_shinfo(skb)->frags[j].size,
3824 PCI_DMA_TODEVICE);
3825 i++;
3826 }
3827
3828 dev_kfree_skb_any(skb);
3829 }
3830}
3831
3832/* Initialize tx/rx rings for packet processing.
3833 *
3834 * The chip has been shut down and the driver detached from
3835 * the networking, so no interrupts or new tx packets will
3836 * end up in the driver. tp->{tx,}lock are held and thus
3837 * we may not sleep.
3838 */
3839static void tg3_init_rings(struct tg3 *tp)
3840{
3841 u32 i;
3842
3843 /* Free up all the SKBs. */
3844 tg3_free_rings(tp);
3845
3846 /* Zero out all descriptors. */
3847 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3848 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3849 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3850 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3851
7e72aad4
MC		 3852 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
3853 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) &&
3854 (tp->dev->mtu > ETH_DATA_LEN))
3855 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3856
1da177e4
LT		 3857 /* Initialize invariants of the rings, we only set this
3858 * stuff once. This works because the card does not
3859 * write into the rx buffer posting rings.
3860 */
3861 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3862 struct tg3_rx_buffer_desc *rxd;
3863
3864 rxd = &tp->rx_std[i];
7e72aad4 3865 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 3866 << RXD_LEN_SHIFT;
3867 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3868 rxd->opaque = (RXD_OPAQUE_RING_STD |
3869 (i << RXD_OPAQUE_INDEX_SHIFT));
3870 }
3871
0f893dc6 3872 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 3873 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3874 struct tg3_rx_buffer_desc *rxd;
3875
3876 rxd = &tp->rx_jumbo[i];
3877 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3878 << RXD_LEN_SHIFT;
3879 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3880 RXD_FLAG_JUMBO;
3881 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3882 (i << RXD_OPAQUE_INDEX_SHIFT));
3883 }
3884 }
3885
3886 /* Now allocate fresh SKBs for each rx ring. */
3887 for (i = 0; i < tp->rx_pending; i++) {
3888 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3889 -1, i) < 0)
3890 break;
3891 }
3892
0f893dc6 3893 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 3894 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3895 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3896 -1, i) < 0)
3897 break;
3898 }
3899 }
3900}
3901
3902/*
3903 * Must not be invoked with interrupt sources disabled and
3904 * the hardware shutdown down.
3905 */
3906static void tg3_free_consistent(struct tg3 *tp)
3907{
3908 if (tp->rx_std_buffers) {
3909 kfree(tp->rx_std_buffers);
3910 tp->rx_std_buffers = NULL;
3911 }
3912 if (tp->rx_std) {
3913 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3914 tp->rx_std, tp->rx_std_mapping);
3915 tp->rx_std = NULL;
3916 }
3917 if (tp->rx_jumbo) {
3918 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3919 tp->rx_jumbo, tp->rx_jumbo_mapping);
3920 tp->rx_jumbo = NULL;
3921 }
3922 if (tp->rx_rcb) {
3923 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3924 tp->rx_rcb, tp->rx_rcb_mapping);
3925 tp->rx_rcb = NULL;
3926 }
3927 if (tp->tx_ring) {
3928 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3929 tp->tx_ring, tp->tx_desc_mapping);
3930 tp->tx_ring = NULL;
3931 }
3932 if (tp->hw_status) {
3933 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3934 tp->hw_status, tp->status_mapping);
3935 tp->hw_status = NULL;
3936 }
3937 if (tp->hw_stats) {
3938 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3939 tp->hw_stats, tp->stats_mapping);
3940 tp->hw_stats = NULL;
3941 }
3942}
3943
3944/*
3945 * Must not be invoked with interrupt sources disabled and
3946 * the hardware shutdown down. Can sleep.
3947 */
3948static int tg3_alloc_consistent(struct tg3 *tp)
3949{
3950 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3951 (TG3_RX_RING_SIZE +
3952 TG3_RX_JUMBO_RING_SIZE)) +
3953 (sizeof(struct tx_ring_info) *
3954 TG3_TX_RING_SIZE),
3955 GFP_KERNEL);
3956 if (!tp->rx_std_buffers)
3957 return -ENOMEM;
3958
3959 memset(tp->rx_std_buffers, 0,
3960 (sizeof(struct ring_info) *
3961 (TG3_RX_RING_SIZE +
3962 TG3_RX_JUMBO_RING_SIZE)) +
3963 (sizeof(struct tx_ring_info) *
3964 TG3_TX_RING_SIZE));
3965
3966 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3967 tp->tx_buffers = (struct tx_ring_info *)
3968 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3969
3970 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3971 &tp->rx_std_mapping);
3972 if (!tp->rx_std)
3973 goto err_out;
3974
3975 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3976 &tp->rx_jumbo_mapping);
3977
3978 if (!tp->rx_jumbo)
3979 goto err_out;
3980
3981 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3982 &tp->rx_rcb_mapping);
3983 if (!tp->rx_rcb)
3984 goto err_out;
3985
3986 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3987 &tp->tx_desc_mapping);
3988 if (!tp->tx_ring)
3989 goto err_out;
3990
3991 tp->hw_status = pci_alloc_consistent(tp->pdev,
3992 TG3_HW_STATUS_SIZE,
3993 &tp->status_mapping);
3994 if (!tp->hw_status)
3995 goto err_out;
3996
3997 tp->hw_stats = pci_alloc_consistent(tp->pdev,
3998 sizeof(struct tg3_hw_stats),
3999 &tp->stats_mapping);
4000 if (!tp->hw_stats)
4001 goto err_out;
4002
4003 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4004 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4005
4006 return 0;
4007
4008err_out:
4009 tg3_free_consistent(tp);
4010 return -ENOMEM;
4011}
4012
4013#define MAX_WAIT_CNT 1000
4014
4015/* To stop a block, clear the enable bit and poll till it
4016 * clears. tp->lock is held.
4017 */
b3b7d6be 4018static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4019{
4020 unsigned int i;
4021 u32 val;
4022
4023 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4024 switch (ofs) {
4025 case RCVLSC_MODE:
4026 case DMAC_MODE:
4027 case MBFREE_MODE:
4028 case BUFMGR_MODE:
4029 case MEMARB_MODE:
4030 /* We can't enable/disable these bits of the
4031 * 5705/5750, just say success.
4032 */
4033 return 0;
4034
4035 default:
4036 break;
4037 };
4038 }
4039
4040 val = tr32(ofs);
4041 val &= ~enable_bit;
4042 tw32_f(ofs, val);
4043
4044 for (i = 0; i < MAX_WAIT_CNT; i++) {
4045 udelay(100);
4046 val = tr32(ofs);
4047 if ((val & enable_bit) == 0)
4048 break;
4049 }
4050
b3b7d6be 4051 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4052 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4053 "ofs=%lx enable_bit=%x\n",
4054 ofs, enable_bit);
4055 return -ENODEV;
4056 }
4057
4058 return 0;
4059}
4060
4061/* tp->lock is held. */
b3b7d6be 4062static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4063{
4064 int i, err;
4065
4066 tg3_disable_ints(tp);
4067
4068 tp->rx_mode &= ~RX_MODE_ENABLE;
4069 tw32_f(MAC_RX_MODE, tp->rx_mode);
4070 udelay(10);
4071
b3b7d6be
DM		 4072 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4073 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4074 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4075 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4076 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4077 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4078
4079 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4080 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4081 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4082 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4083 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4084 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4085 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4086
4087 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4088 tw32_f(MAC_MODE, tp->mac_mode);
4089 udelay(40);
4090
4091 tp->tx_mode &= ~TX_MODE_ENABLE;
4092 tw32_f(MAC_TX_MODE, tp->tx_mode);
4093
4094 for (i = 0; i < MAX_WAIT_CNT; i++) {
4095 udelay(100);
4096 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4097 break;
4098 }
4099 if (i >= MAX_WAIT_CNT) {
4100 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4101 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4102 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4103 err |= -ENODEV;
1da177e4
LT		 4104 }
4105
e6de8ad1 4106 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4107 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4108 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4109
4110 tw32(FTQ_RESET, 0xffffffff);
4111 tw32(FTQ_RESET, 0x00000000);
4112
b3b7d6be
DM		 4113 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4114 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4115
4116 if (tp->hw_status)
4117 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4118 if (tp->hw_stats)
4119 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4120
1da177e4
LT		 4121 return err;
4122}
4123
4124/* tp->lock is held. */
4125static int tg3_nvram_lock(struct tg3 *tp)
4126{
4127 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4128 int i;
4129
4130 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4131 for (i = 0; i < 8000; i++) {
4132 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4133 break;
4134 udelay(20);
4135 }
4136 if (i == 8000)
4137 return -ENODEV;
4138 }
4139 return 0;
4140}
4141
4142/* tp->lock is held. */
4143static void tg3_nvram_unlock(struct tg3 *tp)
4144{
4145 if (tp->tg3_flags & TG3_FLAG_NVRAM)
4146 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4147}
4148
e6af301b
MC		 4149/* tp->lock is held. */
4150static void tg3_enable_nvram_access(struct tg3 *tp)
4151{
4152 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4153 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4154 u32 nvaccess = tr32(NVRAM_ACCESS);
4155
4156 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4157 }
4158}
4159
4160/* tp->lock is held. */
4161static void tg3_disable_nvram_access(struct tg3 *tp)
4162{
4163 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4164 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4165 u32 nvaccess = tr32(NVRAM_ACCESS);
4166
4167 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4168 }
4169}
4170
1da177e4
LT		 4171/* tp->lock is held. */
4172static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4173{
4174 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4175 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4176 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4177
4178 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4179 switch (kind) {
4180 case RESET_KIND_INIT:
4181 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4182 DRV_STATE_START);
4183 break;
4184
4185 case RESET_KIND_SHUTDOWN:
4186 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4187 DRV_STATE_UNLOAD);
4188 break;
4189
4190 case RESET_KIND_SUSPEND:
4191 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4192 DRV_STATE_SUSPEND);
4193 break;
4194
4195 default:
4196 break;
4197 };
4198 }
4199}
4200
4201/* tp->lock is held. */
4202static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4203{
4204 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4205 switch (kind) {
4206 case RESET_KIND_INIT:
4207 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4208 DRV_STATE_START_DONE);
4209 break;
4210
4211 case RESET_KIND_SHUTDOWN:
4212 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4213 DRV_STATE_UNLOAD_DONE);
4214 break;
4215
4216 default:
4217 break;
4218 };
4219 }
4220}
4221
4222/* tp->lock is held. */
4223static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4224{
4225 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4226 switch (kind) {
4227 case RESET_KIND_INIT:
4228 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4229 DRV_STATE_START);
4230 break;
4231
4232 case RESET_KIND_SHUTDOWN:
4233 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4234 DRV_STATE_UNLOAD);
4235 break;
4236
4237 case RESET_KIND_SUSPEND:
4238 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4239 DRV_STATE_SUSPEND);
4240 break;
4241
4242 default:
4243 break;
4244 };
4245 }
4246}
4247
4248static void tg3_stop_fw(struct tg3 *);
4249
4250/* tp->lock is held. */
4251static int tg3_chip_reset(struct tg3 *tp)
4252{
4253 u32 val;
1ee582d8 4254 void (*write_op)(struct tg3 *, u32, u32);
1da177e4
LT		 4255 int i;
4256
4257 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4258 tg3_nvram_lock(tp);
4259
4260 /*
4261 * We must avoid the readl() that normally takes place.
4262 * It locks machines, causes machine checks, and other
4263 * fun things. So, temporarily disable the 5701
4264 * hardware workaround, while we do the reset.
4265 */
1ee582d8
MC		 4266 write_op = tp->write32;
4267 if (write_op == tg3_write_flush_reg32)
4268 tp->write32 = tg3_write32;
1da177e4
LT		 4269
4270 /* do the reset */
4271 val = GRC_MISC_CFG_CORECLK_RESET;
4272
4273 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4274 if (tr32(0x7e2c) == 0x60) {
4275 tw32(0x7e2c, 0x20);
4276 }
4277 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4278 tw32(GRC_MISC_CFG, (1 << 29));
4279 val |= (1 << 29);
4280 }
4281 }
4282
4283 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4284 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4285 tw32(GRC_MISC_CFG, val);
4286
1ee582d8
MC		 4287 /* restore 5701 hardware bug workaround write method */
4288 tp->write32 = write_op;
1da177e4
LT		 4289
4290 /* Unfortunately, we have to delay before the PCI read back.
4291 * Some 575X chips even will not respond to a PCI cfg access
4292 * when the reset command is given to the chip.
4293 *
4294 * How do these hardware designers expect things to work
4295 * properly if the PCI write is posted for a long period
4296 * of time? It is always necessary to have some method by
4297 * which a register read back can occur to push the write
4298 * out which does the reset.
4299 *
4300 * For most tg3 variants the trick below was working.
4301 * Ho hum...
4302 */
4303 udelay(120);
4304
4305 /* Flush PCI posted writes. The normal MMIO registers
4306 * are inaccessible at this time so this is the only
4307 * way to make this reliably (actually, this is no longer
4308 * the case, see above). I tried to use indirect
4309 * register read/write but this upset some 5701 variants.
4310 */
4311 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4312
4313 udelay(120);
4314
4315 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4316 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4317 int i;
4318 u32 cfg_val;
4319
4320 /* Wait for link training to complete. */
4321 for (i = 0; i < 5000; i++)
4322 udelay(100);
4323
4324 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4325 pci_write_config_dword(tp->pdev, 0xc4,
4326 cfg_val | (1 << 15));
4327 }
4328 /* Set PCIE max payload size and clear error status. */
4329 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4330 }
4331
4332 /* Re-enable indirect register accesses. */
4333 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4334 tp->misc_host_ctrl);
4335
4336 /* Set MAX PCI retry to zero. */
4337 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4338 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4339 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4340 val |= PCISTATE_RETRY_SAME_DMA;
4341 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4342
4343 pci_restore_state(tp->pdev);
4344
4345 /* Make sure PCI-X relaxed ordering bit is clear. */
4346 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4347 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4348 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4349
4cf78e4f
MC		 4350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
4351 u32 val;
4352
4353 /* Chip reset on 5780 will reset MSI enable bit,
4354 * so need to restore it.
4355 */
4356 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4357 u16 ctrl;
4358
4359 pci_read_config_word(tp->pdev,
4360 tp->msi_cap + PCI_MSI_FLAGS,
4361 &ctrl);
4362 pci_write_config_word(tp->pdev,
4363 tp->msi_cap + PCI_MSI_FLAGS,
4364 ctrl | PCI_MSI_FLAGS_ENABLE);
4365 val = tr32(MSGINT_MODE);
4366 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4367 }
4368
4369 val = tr32(MEMARB_MODE);
4370 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4371
4372 } else
4373 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4374
4375 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4376 tg3_stop_fw(tp);
4377 tw32(0x5000, 0x400);
4378 }
4379
4380 tw32(GRC_MODE, tp->grc_mode);
4381
4382 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4383 u32 val = tr32(0xc4);
4384
4385 tw32(0xc4, val | (1 << 15));
4386 }
4387
4388 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4389 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4390 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4391 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4392 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4393 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4394 }
4395
4396 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4397 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4398 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4399 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4400 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4401 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4402 } else
4403 tw32_f(MAC_MODE, 0);
4404 udelay(40);
4405
4406 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4407 /* Wait for firmware initialization to complete. */
4408 for (i = 0; i < 100000; i++) {
4409 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4410 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4411 break;
4412 udelay(10);
4413 }
4414 if (i >= 100000) {
4415 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4416 "firmware will not restart magic=%08x\n",
4417 tp->dev->name, val);
4418 return -ENODEV;
4419 }
4420 }
4421
4422 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4423 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4424 u32 val = tr32(0x7c00);
4425
4426 tw32(0x7c00, val | (1 << 25));
4427 }
4428
4429 /* Reprobe ASF enable state. */
4430 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4431 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4432 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4433 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4434 u32 nic_cfg;
4435
4436 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4437 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4438 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4439 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4440 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4441 }
4442 }
4443
4444 return 0;
4445}
4446
4447/* tp->lock is held. */
4448static void tg3_stop_fw(struct tg3 *tp)
4449{
4450 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4451 u32 val;
4452 int i;
4453
4454 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4455 val = tr32(GRC_RX_CPU_EVENT);
4456 val |= (1 << 14);
4457 tw32(GRC_RX_CPU_EVENT, val);
4458
4459 /* Wait for RX cpu to ACK the event. */
4460 for (i = 0; i < 100; i++) {
4461 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4462 break;
4463 udelay(1);
4464 }
4465 }
4466}
4467
4468/* tp->lock is held. */
944d980e 4469static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 4470{
4471 int err;
4472
4473 tg3_stop_fw(tp);
4474
944d980e 4475 tg3_write_sig_pre_reset(tp, kind);
1da177e4 4476
b3b7d6be 4477 tg3_abort_hw(tp, silent);
1da177e4
LT		 4478 err = tg3_chip_reset(tp);
4479
944d980e
MC		 4480 tg3_write_sig_legacy(tp, kind);
4481 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 4482
4483 if (err)
4484 return err;
4485
4486 return 0;
4487}
4488
4489#define TG3_FW_RELEASE_MAJOR 0x0
4490#define TG3_FW_RELASE_MINOR 0x0
4491#define TG3_FW_RELEASE_FIX 0x0
4492#define TG3_FW_START_ADDR 0x08000000
4493#define TG3_FW_TEXT_ADDR 0x08000000
4494#define TG3_FW_TEXT_LEN 0x9c0
4495#define TG3_FW_RODATA_ADDR 0x080009c0
4496#define TG3_FW_RODATA_LEN 0x60
4497#define TG3_FW_DATA_ADDR 0x08000a40
4498#define TG3_FW_DATA_LEN 0x20
4499#define TG3_FW_SBSS_ADDR 0x08000a60
4500#define TG3_FW_SBSS_LEN 0xc
4501#define TG3_FW_BSS_ADDR 0x08000a70
4502#define TG3_FW_BSS_LEN 0x10
4503
4504static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4505 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4506 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4507 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4508 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4509 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4510 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4511 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4512 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4513 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4514 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4515 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4516 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4517 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4518 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4519 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4520 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4521 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4522 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4523 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4524 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4525 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4526 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4527 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4530 0, 0, 0, 0, 0, 0,
4531 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4532 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4533 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4534 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4535 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4536 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4537 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4538 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4539 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4540 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4541 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4545 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4546 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4547 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4548 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4549 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4550 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4551 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4552 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4553 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4554 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4555 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4556 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4557 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4558 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4559 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4560 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4561 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4562 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4563 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4564 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4565 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4566 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4567 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4568 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4569 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4570 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4571 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4572 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4573 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4574 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4575 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4576 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4577 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4578 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4579 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4580 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4581 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4582 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4583 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4584 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4585 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4586 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4587 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4588 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4589 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4590 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4591 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4592 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4593 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4594 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4595 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4596};
4597
4598static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4599 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4600 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4601 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4602 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4603 0x00000000
4604};
4605
4606#if 0 /* All zeros, don't eat up space with it. */
4607u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4608 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4609 0x00000000, 0x00000000, 0x00000000, 0x00000000
4610};
4611#endif
4612
4613#define RX_CPU_SCRATCH_BASE 0x30000
4614#define RX_CPU_SCRATCH_SIZE 0x04000
4615#define TX_CPU_SCRATCH_BASE 0x34000
4616#define TX_CPU_SCRATCH_SIZE 0x04000
4617
4618/* tp->lock is held. */
4619static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4620{
4621 int i;
4622
4623 if (offset == TX_CPU_BASE &&
4624 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4625 BUG();
4626
4627 if (offset == RX_CPU_BASE) {
4628 for (i = 0; i < 10000; i++) {
4629 tw32(offset + CPU_STATE, 0xffffffff);
4630 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4631 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4632 break;
4633 }
4634
4635 tw32(offset + CPU_STATE, 0xffffffff);
4636 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4637 udelay(10);
4638 } else {
4639 for (i = 0; i < 10000; i++) {
4640 tw32(offset + CPU_STATE, 0xffffffff);
4641 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4642 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4643 break;
4644 }
4645 }
4646
4647 if (i >= 10000) {
4648 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4649 "and %s CPU\n",
4650 tp->dev->name,
4651 (offset == RX_CPU_BASE ? "RX" : "TX"));
4652 return -ENODEV;
4653 }
4654 return 0;
4655}
4656
4657struct fw_info {
4658 unsigned int text_base;
4659 unsigned int text_len;
4660 u32 *text_data;
4661 unsigned int rodata_base;
4662 unsigned int rodata_len;
4663 u32 *rodata_data;
4664 unsigned int data_base;
4665 unsigned int data_len;
4666 u32 *data_data;
4667};
4668
4669/* tp->lock is held. */
4670static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4671 int cpu_scratch_size, struct fw_info *info)
4672{
4673 int err, i;
1da177e4
LT		 4674 void (*write_op)(struct tg3 *, u32, u32);
4675
4676 if (cpu_base == TX_CPU_BASE &&
4677 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4678 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4679 "TX cpu firmware on %s which is 5705.\n",
4680 tp->dev->name);
4681 return -EINVAL;
4682 }
4683
4684 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4685 write_op = tg3_write_mem;
4686 else
4687 write_op = tg3_write_indirect_reg32;
4688
1b628151
MC		 4689 /* It is possible that bootcode is still loading at this point.
4690 * Get the nvram lock first before halting the cpu.
4691 */
4692 tg3_nvram_lock(tp);
1da177e4 4693 err = tg3_halt_cpu(tp, cpu_base);
1b628151 4694 tg3_nvram_unlock(tp);
1da177e4
LT		 4695 if (err)
4696 goto out;
4697
4698 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4699 write_op(tp, cpu_scratch_base + i, 0);
4700 tw32(cpu_base + CPU_STATE, 0xffffffff);
4701 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4702 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4703 write_op(tp, (cpu_scratch_base +
4704 (info->text_base & 0xffff) +
4705 (i * sizeof(u32))),
4706 (info->text_data ?
4707 info->text_data[i] : 0));
4708 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4709 write_op(tp, (cpu_scratch_base +
4710 (info->rodata_base & 0xffff) +
4711 (i * sizeof(u32))),
4712 (info->rodata_data ?
4713 info->rodata_data[i] : 0));
4714 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4715 write_op(tp, (cpu_scratch_base +
4716 (info->data_base & 0xffff) +
4717 (i * sizeof(u32))),
4718 (info->data_data ?
4719 info->data_data[i] : 0));
4720
4721 err = 0;
4722
4723out:
1da177e4
LT		 4724 return err;
4725}
4726
4727/* tp->lock is held. */
4728static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4729{
4730 struct fw_info info;
4731 int err, i;
4732
4733 info.text_base = TG3_FW_TEXT_ADDR;
4734 info.text_len = TG3_FW_TEXT_LEN;
4735 info.text_data = &tg3FwText[0];
4736 info.rodata_base = TG3_FW_RODATA_ADDR;
4737 info.rodata_len = TG3_FW_RODATA_LEN;
4738 info.rodata_data = &tg3FwRodata[0];
4739 info.data_base = TG3_FW_DATA_ADDR;
4740 info.data_len = TG3_FW_DATA_LEN;
4741 info.data_data = NULL;
4742
4743 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4744 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4745 &info);
4746 if (err)
4747 return err;
4748
4749 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4750 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4751 &info);
4752 if (err)
4753 return err;
4754
4755 /* Now startup only the RX cpu. */
4756 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4757 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4758
4759 for (i = 0; i < 5; i++) {
4760 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4761 break;
4762 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4763 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4764 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4765 udelay(1000);
4766 }
4767 if (i >= 5) {
4768 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4769 "to set RX CPU PC, is %08x should be %08x\n",
4770 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4771 TG3_FW_TEXT_ADDR);
4772 return -ENODEV;
4773 }
4774 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4775 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4776
4777 return 0;
4778}
4779
4780#if TG3_TSO_SUPPORT != 0
4781
4782#define TG3_TSO_FW_RELEASE_MAJOR 0x1
4783#define TG3_TSO_FW_RELASE_MINOR 0x6
4784#define TG3_TSO_FW_RELEASE_FIX 0x0
4785#define TG3_TSO_FW_START_ADDR 0x08000000
4786#define TG3_TSO_FW_TEXT_ADDR 0x08000000
4787#define TG3_TSO_FW_TEXT_LEN 0x1aa0
4788#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4789#define TG3_TSO_FW_RODATA_LEN 0x60
4790#define TG3_TSO_FW_DATA_ADDR 0x08001b20
4791#define TG3_TSO_FW_DATA_LEN 0x30
4792#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4793#define TG3_TSO_FW_SBSS_LEN 0x2c
4794#define TG3_TSO_FW_BSS_ADDR 0x08001b80
4795#define TG3_TSO_FW_BSS_LEN 0x894
4796
4797static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4798 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4799 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4800 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4801 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4802 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4803 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4804 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4805 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4806 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4807 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4808 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4809 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4810 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4811 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4812 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4813 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4814 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4815 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4816 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4817 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4818 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4819 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4820 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4821 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4822 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4823 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4824 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4825 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4826 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4827 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4828 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4829 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4830 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4831 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4832 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4833 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4834 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4835 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4836 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4837 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4838 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4839 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4840 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4841 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4842 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4843 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4844 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4845 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4846 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4847 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4848 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4849 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4850 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4851 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4852 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4853 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4854 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4855 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4856 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4857 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4858 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4859 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4860 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4861 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4862 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4863 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4864 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4865 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4866 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4867 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4868 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4869 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4870 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4871 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4872 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4873 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4874 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4875 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4876 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4877 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4878 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4879 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4880 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4881 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4882 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4883 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4884 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4885 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4886 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4887 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4888 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4889 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4890 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4891 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4892 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4893 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4894 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4895 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4896 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4897 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4898 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4899 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4900 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4901 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4902 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4903 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4904 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4905 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4906 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4907 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4908 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4909 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4910 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4911 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4912 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4913 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4914 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4915 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4916 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4917 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4918 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4919 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4920 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4921 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4922 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4923 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4924 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4925 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4926 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4927 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4928 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4929 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4930 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4931 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4932 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4933 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4934 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4935 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4936 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4937 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4938 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4939 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4940 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4941 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4942 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4943 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4944 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4945 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4946 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4947 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4948 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4949 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4950 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4951 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4952 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4953 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4954 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4955 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4956 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4957 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4958 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4959 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4960 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4961 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4962 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4963 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4964 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4965 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4966 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4967 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4968 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4969 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4970 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4971 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4972 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4973 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4974 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4975 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4976 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4977 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4978 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4979 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4980 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4981 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4982 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4983 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4984 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4985 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4986 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4987 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4988 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4989 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4990 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4991 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4992 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4993 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4994 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4995 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4996 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4997 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4998 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4999 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5000 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5001 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5002 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5003 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5004 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5005 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5006 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5007 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5008 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5009 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5010 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5011 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5012 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5013 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5014 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5015 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5016 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5017 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5018 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5019 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5020 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5021 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5022 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5023 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5024 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5025 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5026 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5027 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5028 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5029 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5030 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5031 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5032 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5033 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5034 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5035 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5036 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5037 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5038 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5039 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5040 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5041 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5042 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5043 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5044 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5045 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5046 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5047 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5048 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5049 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5050 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5051 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5052 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5053 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5054 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5055 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5056 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5057 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5058 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5059 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5060 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5061 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5062 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5063 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5064 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5065 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5066 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5067 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5068 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5069 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5070 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5071 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5072 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5073 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5074 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5075 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5076 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5077 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5078 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5079 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5080 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5081 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5082};
5083
5084static u32 tg3TsoFwRodata[] = {
5085 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5086 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5087 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5088 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5089 0x00000000,
5090};
5091
5092static u32 tg3TsoFwData[] = {
5093 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5094 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5095 0x00000000,
5096};
5097
5098/* 5705 needs a special version of the TSO firmware. */
5099#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5100#define TG3_TSO5_FW_RELASE_MINOR 0x2
5101#define TG3_TSO5_FW_RELEASE_FIX 0x0
5102#define TG3_TSO5_FW_START_ADDR 0x00010000
5103#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5104#define TG3_TSO5_FW_TEXT_LEN 0xe90
5105#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5106#define TG3_TSO5_FW_RODATA_LEN 0x50
5107#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5108#define TG3_TSO5_FW_DATA_LEN 0x20
5109#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5110#define TG3_TSO5_FW_SBSS_LEN 0x28
5111#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5112#define TG3_TSO5_FW_BSS_LEN 0x88
5113
5114static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5115 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5116 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5117 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5118 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5119 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5120 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5121 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5122 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5123 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5124 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5125 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5126 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5127 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5128 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5129 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5130 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5131 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5132 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5133 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5134 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5135 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5136 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5137 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5138 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5139 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5140 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5141 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5142 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5143 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5144 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5145 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5146 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5147 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5148 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5149 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5150 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5151 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5152 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5153 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5154 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5155 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5156 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5157 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5158 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5159 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5160 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5161 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5162 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5163 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5164 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5165 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5166 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5167 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5168 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5169 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5170 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5171 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5172 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5173 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5174 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5175 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5176 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5177 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5178 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5179 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5180 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5181 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5182 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5183 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5184 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5185 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5186 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5187 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5188 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5189 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5190 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5191 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5192 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5193 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5194 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5195 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5196 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5197 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5198 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5199 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5200 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5201 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5202 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5203 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5204 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5205 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5206 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5207 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5208 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5209 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5210 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5211 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5212 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5213 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5214 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5215 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5216 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5217 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5218 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5219 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5220 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5221 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5222 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5223 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5224 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5225 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5226 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5227 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5228 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5229 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5230 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5231 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5232 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5233 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5234 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5235 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5236 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5237 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5238 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5239 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5240 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5241 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5242 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5243 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5244 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5245 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5246 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5247 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5248 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5249 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5250 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5251 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5252 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5253 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5254 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5255 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5256 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5257 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5258 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5259 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5260 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5261 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5262 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5263 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5264 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5265 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5266 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5267 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5268 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5269 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5270 0x00000000, 0x00000000, 0x00000000,
5271};
5272
5273static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5274 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5275 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5276 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5277 0x00000000, 0x00000000, 0x00000000,
5278};
5279
5280static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5281 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5282 0x00000000, 0x00000000, 0x00000000,
5283};
5284
5285/* tp->lock is held. */
5286static int tg3_load_tso_firmware(struct tg3 *tp)
5287{
5288 struct fw_info info;
5289 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5290 int err, i;
5291
5292 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5293 return 0;
5294
5295 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5296 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5297 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5298 info.text_data = &tg3Tso5FwText[0];
5299 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5300 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5301 info.rodata_data = &tg3Tso5FwRodata[0];
5302 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5303 info.data_len = TG3_TSO5_FW_DATA_LEN;
5304 info.data_data = &tg3Tso5FwData[0];
5305 cpu_base = RX_CPU_BASE;
5306 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5307 cpu_scratch_size = (info.text_len +
5308 info.rodata_len +
5309 info.data_len +
5310 TG3_TSO5_FW_SBSS_LEN +
5311 TG3_TSO5_FW_BSS_LEN);
5312 } else {
5313 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5314 info.text_len = TG3_TSO_FW_TEXT_LEN;
5315 info.text_data = &tg3TsoFwText[0];
5316 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5317 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5318 info.rodata_data = &tg3TsoFwRodata[0];
5319 info.data_base = TG3_TSO_FW_DATA_ADDR;
5320 info.data_len = TG3_TSO_FW_DATA_LEN;
5321 info.data_data = &tg3TsoFwData[0];
5322 cpu_base = TX_CPU_BASE;
5323 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5324 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5325 }
5326
5327 err = tg3_load_firmware_cpu(tp, cpu_base,
5328 cpu_scratch_base, cpu_scratch_size,
5329 &info);
5330 if (err)
5331 return err;
5332
5333 /* Now startup the cpu. */
5334 tw32(cpu_base + CPU_STATE, 0xffffffff);
5335 tw32_f(cpu_base + CPU_PC, info.text_base);
5336
5337 for (i = 0; i < 5; i++) {
5338 if (tr32(cpu_base + CPU_PC) == info.text_base)
5339 break;
5340 tw32(cpu_base + CPU_STATE, 0xffffffff);
5341 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5342 tw32_f(cpu_base + CPU_PC, info.text_base);
5343 udelay(1000);
5344 }
5345 if (i >= 5) {
5346 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5347 "to set CPU PC, is %08x should be %08x\n",
5348 tp->dev->name, tr32(cpu_base + CPU_PC),
5349 info.text_base);
5350 return -ENODEV;
5351 }
5352 tw32(cpu_base + CPU_STATE, 0xffffffff);
5353 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5354 return 0;
5355}
5356
5357#endif /* TG3_TSO_SUPPORT != 0 */
5358
5359/* tp->lock is held. */
5360static void __tg3_set_mac_addr(struct tg3 *tp)
5361{
5362 u32 addr_high, addr_low;
5363 int i;
5364
5365 addr_high = ((tp->dev->dev_addr[0] << 8) |
5366 tp->dev->dev_addr[1]);
5367 addr_low = ((tp->dev->dev_addr[2] << 24) |
5368 (tp->dev->dev_addr[3] << 16) |
5369 (tp->dev->dev_addr[4] << 8) |
5370 (tp->dev->dev_addr[5] << 0));
5371 for (i = 0; i < 4; i++) {
5372 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5373 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5374 }
5375
5376 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5377 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5378 for (i = 0; i < 12; i++) {
5379 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5380 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5381 }
5382 }
5383
5384 addr_high = (tp->dev->dev_addr[0] +
5385 tp->dev->dev_addr[1] +
5386 tp->dev->dev_addr[2] +
5387 tp->dev->dev_addr[3] +
5388 tp->dev->dev_addr[4] +
5389 tp->dev->dev_addr[5]) &
5390 TX_BACKOFF_SEED_MASK;
5391 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5392}
5393
5394static int tg3_set_mac_addr(struct net_device *dev, void *p)
5395{
5396 struct tg3 *tp = netdev_priv(dev);
5397 struct sockaddr *addr = p;
5398
f9804ddb
MC		 5399 if (!is_valid_ether_addr(addr->sa_data))
5400 return -EINVAL;
5401
1da177e4
LT		 5402 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5403
f47c11ee 5404 spin_lock_bh(&tp->lock);
1da177e4 5405 __tg3_set_mac_addr(tp);
f47c11ee 5406 spin_unlock_bh(&tp->lock);
1da177e4
LT		 5407
5408 return 0;
5409}
5410
5411/* tp->lock is held. */
5412static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5413 dma_addr_t mapping, u32 maxlen_flags,
5414 u32 nic_addr)
5415{
5416 tg3_write_mem(tp,
5417 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5418 ((u64) mapping >> 32));
5419 tg3_write_mem(tp,
5420 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5421 ((u64) mapping & 0xffffffff));
5422 tg3_write_mem(tp,
5423 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5424 maxlen_flags);
5425
5426 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5427 tg3_write_mem(tp,
5428 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5429 nic_addr);
5430}
5431
5432static void __tg3_set_rx_mode(struct net_device *);
d244c892 5433static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 5434{
5435 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5436 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5437 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5438 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5439 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5440 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5441 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5442 }
5443 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5444 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5445 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5446 u32 val = ec->stats_block_coalesce_usecs;
5447
5448 if (!netif_carrier_ok(tp->dev))
5449 val = 0;
5450
5451 tw32(HOSTCC_STAT_COAL_TICKS, val);
5452 }
5453}
1da177e4
LT		 5454
5455/* tp->lock is held. */
5456static int tg3_reset_hw(struct tg3 *tp)
5457{
5458 u32 val, rdmac_mode;
5459 int i, err, limit;
5460
5461 tg3_disable_ints(tp);
5462
5463 tg3_stop_fw(tp);
5464
5465 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5466
5467 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 5468 tg3_abort_hw(tp, 1);
1da177e4
LT		 5469 }
5470
5471 err = tg3_chip_reset(tp);
5472 if (err)
5473 return err;
5474
5475 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5476
5477 /* This works around an issue with Athlon chipsets on
5478 * B3 tigon3 silicon. This bit has no effect on any
5479 * other revision. But do not set this on PCI Express
5480 * chips.
5481 */
5482 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5483 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5484 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5485
5486 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5487 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5488 val = tr32(TG3PCI_PCISTATE);
5489 val |= PCISTATE_RETRY_SAME_DMA;
5490 tw32(TG3PCI_PCISTATE, val);
5491 }
5492
5493 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5494 /* Enable some hw fixes. */
5495 val = tr32(TG3PCI_MSI_DATA);
5496 val |= (1 << 26) | (1 << 28) | (1 << 29);
5497 tw32(TG3PCI_MSI_DATA, val);
5498 }
5499
5500 /* Descriptor ring init may make accesses to the
5501 * NIC SRAM area to setup the TX descriptors, so we
5502 * can only do this after the hardware has been
5503 * successfully reset.
5504 */
5505 tg3_init_rings(tp);
5506
5507 /* This value is determined during the probe time DMA
5508 * engine test, tg3_test_dma.
5509 */
5510 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5511
5512 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5513 GRC_MODE_4X_NIC_SEND_RINGS |
5514 GRC_MODE_NO_TX_PHDR_CSUM |
5515 GRC_MODE_NO_RX_PHDR_CSUM);
5516 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5517 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5518 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5519 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5520 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5521
5522 tw32(GRC_MODE,
5523 tp->grc_mode |
5524 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5525
5526 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5527 val = tr32(GRC_MISC_CFG);
5528 val &= ~0xff;
5529 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5530 tw32(GRC_MISC_CFG, val);
5531
5532 /* Initialize MBUF/DESC pool. */
cbf46853 5533 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 5534 /* Do nothing. */
5535 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5536 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5538 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5539 else
5540 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5541 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5542 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5543 }
5544#if TG3_TSO_SUPPORT != 0
5545 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5546 int fw_len;
5547
5548 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5549 TG3_TSO5_FW_RODATA_LEN +
5550 TG3_TSO5_FW_DATA_LEN +
5551 TG3_TSO5_FW_SBSS_LEN +
5552 TG3_TSO5_FW_BSS_LEN);
5553 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5554 tw32(BUFMGR_MB_POOL_ADDR,
5555 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5556 tw32(BUFMGR_MB_POOL_SIZE,
5557 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5558 }
5559#endif
5560
0f893dc6 5561 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 5562 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5563 tp->bufmgr_config.mbuf_read_dma_low_water);
5564 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5565 tp->bufmgr_config.mbuf_mac_rx_low_water);
5566 tw32(BUFMGR_MB_HIGH_WATER,
5567 tp->bufmgr_config.mbuf_high_water);
5568 } else {
5569 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5570 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5571 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5572 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5573 tw32(BUFMGR_MB_HIGH_WATER,
5574 tp->bufmgr_config.mbuf_high_water_jumbo);
5575 }
5576 tw32(BUFMGR_DMA_LOW_WATER,
5577 tp->bufmgr_config.dma_low_water);
5578 tw32(BUFMGR_DMA_HIGH_WATER,
5579 tp->bufmgr_config.dma_high_water);
5580
5581 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5582 for (i = 0; i < 2000; i++) {
5583 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5584 break;
5585 udelay(10);
5586 }
5587 if (i >= 2000) {
5588 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5589 tp->dev->name);
5590 return -ENODEV;
5591 }
5592
5593 /* Setup replenish threshold. */
5594 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5595
5596 /* Initialize TG3_BDINFO's at:
5597 * RCVDBDI_STD_BD: standard eth size rx ring
5598 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5599 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5600 *
5601 * like so:
5602 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5603 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5604 * ring attribute flags
5605 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5606 *
5607 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5608 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5609 *
5610 * The size of each ring is fixed in the firmware, but the location is
5611 * configurable.
5612 */
5613 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5614 ((u64) tp->rx_std_mapping >> 32));
5615 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5616 ((u64) tp->rx_std_mapping & 0xffffffff));
5617 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5618 NIC_SRAM_RX_BUFFER_DESC);
5619
5620 /* Don't even try to program the JUMBO/MINI buffer descriptor
5621 * configs on 5705.
5622 */
5623 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5624 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5625 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5626 } else {
5627 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5628 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5629
5630 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5631 BDINFO_FLAGS_DISABLED);
5632
5633 /* Setup replenish threshold. */
5634 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5635
0f893dc6 5636 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5637 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5638 ((u64) tp->rx_jumbo_mapping >> 32));
5639 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5640 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5641 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5642 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5643 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5644 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5645 } else {
5646 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5647 BDINFO_FLAGS_DISABLED);
5648 }
5649
5650 }
5651
5652 /* There is only one send ring on 5705/5750, no need to explicitly
5653 * disable the others.
5654 */
5655 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5656 /* Clear out send RCB ring in SRAM. */
5657 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5658 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5659 BDINFO_FLAGS_DISABLED);
5660 }
5661
5662 tp->tx_prod = 0;
5663 tp->tx_cons = 0;
5664 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5665 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5666
5667 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5668 tp->tx_desc_mapping,
5669 (TG3_TX_RING_SIZE <<
5670 BDINFO_FLAGS_MAXLEN_SHIFT),
5671 NIC_SRAM_TX_BUFFER_DESC);
5672
5673 /* There is only one receive return ring on 5705/5750, no need
5674 * to explicitly disable the others.
5675 */
5676 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5677 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5678 i += TG3_BDINFO_SIZE) {
5679 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5680 BDINFO_FLAGS_DISABLED);
5681 }
5682 }
5683
5684 tp->rx_rcb_ptr = 0;
5685 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5686
5687 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5688 tp->rx_rcb_mapping,
5689 (TG3_RX_RCB_RING_SIZE(tp) <<
5690 BDINFO_FLAGS_MAXLEN_SHIFT),
5691 0);
5692
5693 tp->rx_std_ptr = tp->rx_pending;
5694 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5695 tp->rx_std_ptr);
5696
0f893dc6 5697 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 5698 tp->rx_jumbo_pending : 0;
5699 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5700 tp->rx_jumbo_ptr);
5701
5702 /* Initialize MAC address and backoff seed. */
5703 __tg3_set_mac_addr(tp);
5704
5705 /* MTU + ethernet header + FCS + optional VLAN tag */
5706 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5707
5708 /* The slot time is changed by tg3_setup_phy if we
5709 * run at gigabit with half duplex.
5710 */
5711 tw32(MAC_TX_LENGTHS,
5712 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5713 (6 << TX_LENGTHS_IPG_SHIFT) |
5714 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5715
5716 /* Receive rules. */
5717 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5718 tw32(RCVLPC_CONFIG, 0x0181);
5719
5720 /* Calculate RDMAC_MODE setting early, we need it to determine
5721 * the RCVLPC_STATE_ENABLE mask.
5722 */
5723 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5724 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5725 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5726 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5727 RDMAC_MODE_LNGREAD_ENAB);
5728 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5729 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 5730
5731 /* If statement applies to 5705 and 5750 PCI devices only */
5732 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5733 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5734 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 5735 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5736 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5737 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5738 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5739 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5740 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5741 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5742 }
5743 }
5744
85e94ced
MC		 5745 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5746 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5747
1da177e4
LT		 5748#if TG3_TSO_SUPPORT != 0
5749 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5750 rdmac_mode |= (1 << 27);
5751#endif
5752
5753 /* Receive/send statistics. */
5754 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5755 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5756 val = tr32(RCVLPC_STATS_ENABLE);
5757 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5758 tw32(RCVLPC_STATS_ENABLE, val);
5759 } else {
5760 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5761 }
5762 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5763 tw32(SNDDATAI_STATSENAB, 0xffffff);
5764 tw32(SNDDATAI_STATSCTRL,
5765 (SNDDATAI_SCTRL_ENABLE |
5766 SNDDATAI_SCTRL_FASTUPD));
5767
5768 /* Setup host coalescing engine. */
5769 tw32(HOSTCC_MODE, 0);
5770 for (i = 0; i < 2000; i++) {
5771 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5772 break;
5773 udelay(10);
5774 }
5775
d244c892 5776 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 5777
5778 /* set status block DMA address */
5779 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5780 ((u64) tp->status_mapping >> 32));
5781 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5782 ((u64) tp->status_mapping & 0xffffffff));
5783
5784 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5785 /* Status/statistics block address. See tg3_timer,
5786 * the tg3_periodic_fetch_stats call there, and
5787 * tg3_get_stats to see how this works for 5705/5750 chips.
5788 */
1da177e4
LT		 5789 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5790 ((u64) tp->stats_mapping >> 32));
5791 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5792 ((u64) tp->stats_mapping & 0xffffffff));
5793 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5794 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5795 }
5796
5797 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5798
5799 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5800 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5801 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5802 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5803
5804 /* Clear statistics/status block in chip, and status block in ram. */
5805 for (i = NIC_SRAM_STATS_BLK;
5806 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5807 i += sizeof(u32)) {
5808 tg3_write_mem(tp, i, 0);
5809 udelay(40);
5810 }
5811 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5812
c94e3941
MC		 5813 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5814 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
5815 /* reset to prevent losing 1st rx packet intermittently */
5816 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5817 udelay(10);
5818 }
5819
1da177e4
LT		 5820 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5821 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5822 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5823 udelay(40);
5824
314fba34
MC		 5825 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5826 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5827 * register to preserve the GPIO settings for LOMs. The GPIOs,
5828 * whether used as inputs or outputs, are set by boot code after
5829 * reset.
5830 */
5831 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5832 u32 gpio_mask;
5833
5834 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5835 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 5836
5837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5838 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5839 GRC_LCLCTRL_GPIO_OUTPUT3;
5840
314fba34
MC		 5841 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5842
5843 /* GPIO1 must be driven high for eeprom write protect */
1da177e4
LT		 5844 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5845 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 5846 }
1da177e4
LT		 5847 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5848 udelay(100);
5849
09ee929c 5850 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 5851 tp->last_tag = 0;
1da177e4
LT		 5852
5853 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5854 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5855 udelay(40);
5856 }
5857
5858 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5859 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5860 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5861 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5862 WDMAC_MODE_LNGREAD_ENAB);
5863
85e94ced
MC		 5864 /* If statement applies to 5705 and 5750 PCI devices only */
5865 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5866 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 5868 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5869 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5870 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5871 /* nothing */
5872 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5873 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5874 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5875 val |= WDMAC_MODE_RX_ACCEL;
5876 }
5877 }
5878
5879 tw32_f(WDMAC_MODE, val);
5880 udelay(40);
5881
5882 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5883 val = tr32(TG3PCI_X_CAPS);
5884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5885 val &= ~PCIX_CAPS_BURST_MASK;
5886 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5887 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5888 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5889 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5890 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5891 val |= (tp->split_mode_max_reqs <<
5892 PCIX_CAPS_SPLIT_SHIFT);
5893 }
5894 tw32(TG3PCI_X_CAPS, val);
5895 }
5896
5897 tw32_f(RDMAC_MODE, rdmac_mode);
5898 udelay(40);
5899
5900 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5901 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5902 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5903 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5904 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5905 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5906 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5907 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5908#if TG3_TSO_SUPPORT != 0
5909 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5910 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5911#endif
5912 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5913 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5914
5915 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5916 err = tg3_load_5701_a0_firmware_fix(tp);
5917 if (err)
5918 return err;
5919 }
5920
5921#if TG3_TSO_SUPPORT != 0
5922 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5923 err = tg3_load_tso_firmware(tp);
5924 if (err)
5925 return err;
5926 }
5927#endif
5928
5929 tp->tx_mode = TX_MODE_ENABLE;
5930 tw32_f(MAC_TX_MODE, tp->tx_mode);
5931 udelay(100);
5932
5933 tp->rx_mode = RX_MODE_ENABLE;
5934 tw32_f(MAC_RX_MODE, tp->rx_mode);
5935 udelay(10);
5936
5937 if (tp->link_config.phy_is_low_power) {
5938 tp->link_config.phy_is_low_power = 0;
5939 tp->link_config.speed = tp->link_config.orig_speed;
5940 tp->link_config.duplex = tp->link_config.orig_duplex;
5941 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5942 }
5943
5944 tp->mi_mode = MAC_MI_MODE_BASE;
5945 tw32_f(MAC_MI_MODE, tp->mi_mode);
5946 udelay(80);
5947
5948 tw32(MAC_LED_CTRL, tp->led_ctrl);
5949
5950 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 5951 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 5952 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5953 udelay(10);
5954 }
5955 tw32_f(MAC_RX_MODE, tp->rx_mode);
5956 udelay(10);
5957
5958 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5959 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5960 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5961 /* Set drive transmission level to 1.2V */
5962 /* only if the signal pre-emphasis bit is not set */
5963 val = tr32(MAC_SERDES_CFG);
5964 val &= 0xfffff000;
5965 val |= 0x880;
5966 tw32(MAC_SERDES_CFG, val);
5967 }
5968 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5969 tw32(MAC_SERDES_CFG, 0x616000);
5970 }
5971
5972 /* Prevent chip from dropping frames when flow control
5973 * is enabled.
5974 */
5975 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5976
5977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5978 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5979 /* Use hardware link auto-negotiation */
5980 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5981 }
5982
5983 err = tg3_setup_phy(tp, 1);
5984 if (err)
5985 return err;
5986
5987 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5988 u32 tmp;
5989
5990 /* Clear CRC stats. */
5991 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5992 tg3_writephy(tp, 0x1e, tmp | 0x8000);
5993 tg3_readphy(tp, 0x14, &tmp);
5994 }
5995 }
5996
5997 __tg3_set_rx_mode(tp->dev);
5998
5999 /* Initialize receive rules. */
6000 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6001 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6002 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6003 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6004
4cf78e4f
MC		 6005 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6006 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780))
1da177e4
LT		 6007 limit = 8;
6008 else
6009 limit = 16;
6010 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6011 limit -= 4;
6012 switch (limit) {
6013 case 16:
6014 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6015 case 15:
6016 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6017 case 14:
6018 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6019 case 13:
6020 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6021 case 12:
6022 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6023 case 11:
6024 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6025 case 10:
6026 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6027 case 9:
6028 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6029 case 8:
6030 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6031 case 7:
6032 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6033 case 6:
6034 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6035 case 5:
6036 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6037 case 4:
6038 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6039 case 3:
6040 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6041 case 2:
6042 case 1:
6043
6044 default:
6045 break;
6046 };
6047
6048 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6049
1da177e4
LT		 6050 return 0;
6051}
6052
6053/* Called at device open time to get the chip ready for
6054 * packet processing. Invoked with tp->lock held.
6055 */
6056static int tg3_init_hw(struct tg3 *tp)
6057{
6058 int err;
6059
6060 /* Force the chip into D0. */
6061 err = tg3_set_power_state(tp, 0);
6062 if (err)
6063 goto out;
6064
6065 tg3_switch_clocks(tp);
6066
6067 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6068
6069 err = tg3_reset_hw(tp);
6070
6071out:
6072 return err;
6073}
6074
6075#define TG3_STAT_ADD32(PSTAT, REG) \
6076do { u32 __val = tr32(REG); \
6077 (PSTAT)->low += __val; \
6078 if ((PSTAT)->low < __val) \
6079 (PSTAT)->high += 1; \
6080} while (0)
6081
6082static void tg3_periodic_fetch_stats(struct tg3 *tp)
6083{
6084 struct tg3_hw_stats *sp = tp->hw_stats;
6085
6086 if (!netif_carrier_ok(tp->dev))
6087 return;
6088
6089 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6090 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6091 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6092 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6093 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6094 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6095 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6096 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6097 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6098 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6099 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6100 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6101 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6102
6103 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6104 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6105 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6106 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6107 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6108 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6109 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6110 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6111 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6112 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6113 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6114 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6115 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6116 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6117}
6118
6119static void tg3_timer(unsigned long __opaque)
6120{
6121 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6122
f47c11ee 6123 spin_lock(&tp->lock);
1da177e4 6124
fac9b83e
DM		 6125 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6126 /* All of this garbage is because when using non-tagged
6127 * IRQ status the mailbox/status_block protocol the chip
6128 * uses with the cpu is race prone.
6129 */
6130 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6131 tw32(GRC_LOCAL_CTRL,
6132 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6133 } else {
6134 tw32(HOSTCC_MODE, tp->coalesce_mode |
6135 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6136 }
1da177e4 6137
fac9b83e
DM		 6138 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6139 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6140 spin_unlock(&tp->lock);
fac9b83e
DM		 6141 schedule_work(&tp->reset_task);
6142 return;
6143 }
1da177e4
LT		 6144 }
6145
1da177e4
LT		 6146 /* This part only runs once per second. */
6147 if (!--tp->timer_counter) {
fac9b83e
DM		 6148 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6149 tg3_periodic_fetch_stats(tp);
6150
1da177e4
LT		 6151 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6152 u32 mac_stat;
6153 int phy_event;
6154
6155 mac_stat = tr32(MAC_STATUS);
6156
6157 phy_event = 0;
6158 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6159 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6160 phy_event = 1;
6161 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6162 phy_event = 1;
6163
6164 if (phy_event)
6165 tg3_setup_phy(tp, 0);
6166 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6167 u32 mac_stat = tr32(MAC_STATUS);
6168 int need_setup = 0;
6169
6170 if (netif_carrier_ok(tp->dev) &&
6171 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6172 need_setup = 1;
6173 }
6174 if (! netif_carrier_ok(tp->dev) &&
6175 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6176 MAC_STATUS_SIGNAL_DET))) {
6177 need_setup = 1;
6178 }
6179 if (need_setup) {
6180 tw32_f(MAC_MODE,
6181 (tp->mac_mode &
6182 ~MAC_MODE_PORT_MODE_MASK));
6183 udelay(40);
6184 tw32_f(MAC_MODE, tp->mac_mode);
6185 udelay(40);
6186 tg3_setup_phy(tp, 0);
6187 }
747e8f8b
MC		 6188 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6189 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6190
6191 tp->timer_counter = tp->timer_multiplier;
6192 }
6193
6194 /* Heartbeat is only sent once every 120 seconds. */
6195 if (!--tp->asf_counter) {
6196 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6197 u32 val;
6198
6199 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
6200 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6201 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
6202 val = tr32(GRC_RX_CPU_EVENT);
6203 val |= (1 << 14);
6204 tw32(GRC_RX_CPU_EVENT, val);
6205 }
6206 tp->asf_counter = tp->asf_multiplier;
6207 }
6208
f47c11ee 6209 spin_unlock(&tp->lock);
1da177e4
LT		 6210
6211 tp->timer.expires = jiffies + tp->timer_offset;
6212 add_timer(&tp->timer);
6213}
6214
7938109f
MC		 6215static int tg3_test_interrupt(struct tg3 *tp)
6216{
6217 struct net_device *dev = tp->dev;
6218 int err, i;
6219 u32 int_mbox = 0;
6220
d4bc3927
MC		 6221 if (!netif_running(dev))
6222 return -ENODEV;
6223
7938109f
MC		 6224 tg3_disable_ints(tp);
6225
6226 free_irq(tp->pdev->irq, dev);
6227
6228 err = request_irq(tp->pdev->irq, tg3_test_isr,
f4d0ee98 6229 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6230 if (err)
6231 return err;
6232
38f3843e 6233 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 6234 tg3_enable_ints(tp);
6235
6236 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6237 HOSTCC_MODE_NOW);
6238
6239 for (i = 0; i < 5; i++) {
09ee929c
MC		 6240 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6241 TG3_64BIT_REG_LOW);
7938109f
MC		 6242 if (int_mbox != 0)
6243 break;
6244 msleep(10);
6245 }
6246
6247 tg3_disable_ints(tp);
6248
6249 free_irq(tp->pdev->irq, dev);
6250
6251 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6252 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6253 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6254 else {
6255 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6256 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6257 fn = tg3_interrupt_tagged;
6258 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6259 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6260 }
7938109f
MC		 6261
6262 if (err)
6263 return err;
6264
6265 if (int_mbox != 0)
6266 return 0;
6267
6268 return -EIO;
6269}
6270
6271/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6272 * successfully restored
6273 */
6274static int tg3_test_msi(struct tg3 *tp)
6275{
6276 struct net_device *dev = tp->dev;
6277 int err;
6278 u16 pci_cmd;
6279
6280 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6281 return 0;
6282
6283 /* Turn off SERR reporting in case MSI terminates with Master
6284 * Abort.
6285 */
6286 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6287 pci_write_config_word(tp->pdev, PCI_COMMAND,
6288 pci_cmd & ~PCI_COMMAND_SERR);
6289
6290 err = tg3_test_interrupt(tp);
6291
6292 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6293
6294 if (!err)
6295 return 0;
6296
6297 /* other failures */
6298 if (err != -EIO)
6299 return err;
6300
6301 /* MSI test failed, go back to INTx mode */
6302 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6303 "switching to INTx mode. Please report this failure to "
6304 "the PCI maintainer and include system chipset information.\n",
6305 tp->dev->name);
6306
6307 free_irq(tp->pdev->irq, dev);
6308 pci_disable_msi(tp->pdev);
6309
6310 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6311
fac9b83e
DM		 6312 {
6313 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6314 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6315 fn = tg3_interrupt_tagged;
7938109f 6316
fac9b83e
DM		 6317 err = request_irq(tp->pdev->irq, fn,
6318 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6319 }
7938109f
MC		 6320 if (err)
6321 return err;
6322
6323 /* Need to reset the chip because the MSI cycle may have terminated
6324 * with Master Abort.
6325 */
f47c11ee 6326 tg3_full_lock(tp, 1);
7938109f 6327
944d980e 6328 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6329 err = tg3_init_hw(tp);
6330
f47c11ee 6331 tg3_full_unlock(tp);
7938109f
MC		 6332
6333 if (err)
6334 free_irq(tp->pdev->irq, dev);
6335
6336 return err;
6337}
6338
1da177e4
LT		 6339static int tg3_open(struct net_device *dev)
6340{
6341 struct tg3 *tp = netdev_priv(dev);
6342 int err;
6343
f47c11ee 6344 tg3_full_lock(tp, 0);
1da177e4
LT		 6345
6346 tg3_disable_ints(tp);
6347 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6348
f47c11ee 6349 tg3_full_unlock(tp);
1da177e4
LT		 6350
6351 /* The placement of this call is tied
6352 * to the setup and use of Host TX descriptors.
6353 */
6354 err = tg3_alloc_consistent(tp);
6355 if (err)
6356 return err;
6357
88b06bc2
MC		 6358 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6359 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6360 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
fac9b83e
DM		 6361 /* All MSI supporting chips should support tagged
6362 * status. Assert that this is the case.
6363 */
6364 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6365 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6366 "Not using MSI.\n", tp->dev->name);
6367 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 6368 u32 msi_mode;
6369
6370 msi_mode = tr32(MSGINT_MODE);
6371 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6372 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6373 }
6374 }
6375 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6376 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6377 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6378 else {
6379 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6380 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6381 fn = tg3_interrupt_tagged;
6382
6383 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6384 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6385 }
1da177e4
LT		 6386
6387 if (err) {
88b06bc2
MC		 6388 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6389 pci_disable_msi(tp->pdev);
6390 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6391 }
1da177e4
LT		 6392 tg3_free_consistent(tp);
6393 return err;
6394 }
6395
f47c11ee 6396 tg3_full_lock(tp, 0);
1da177e4
LT		 6397
6398 err = tg3_init_hw(tp);
6399 if (err) {
944d980e 6400 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6401 tg3_free_rings(tp);
6402 } else {
fac9b83e
DM		 6403 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6404 tp->timer_offset = HZ;
6405 else
6406 tp->timer_offset = HZ / 10;
6407
6408 BUG_ON(tp->timer_offset > HZ);
6409 tp->timer_counter = tp->timer_multiplier =
6410 (HZ / tp->timer_offset);
6411 tp->asf_counter = tp->asf_multiplier =
6412 ((HZ / tp->timer_offset) * 120);
1da177e4
LT		 6413
6414 init_timer(&tp->timer);
6415 tp->timer.expires = jiffies + tp->timer_offset;
6416 tp->timer.data = (unsigned long) tp;
6417 tp->timer.function = tg3_timer;
1da177e4
LT		 6418 }
6419
f47c11ee 6420 tg3_full_unlock(tp);
1da177e4
LT		 6421
6422 if (err) {
88b06bc2
MC		 6423 free_irq(tp->pdev->irq, dev);
6424 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6425 pci_disable_msi(tp->pdev);
6426 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6427 }
1da177e4
LT		 6428 tg3_free_consistent(tp);
6429 return err;
6430 }
6431
7938109f
MC		 6432 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6433 err = tg3_test_msi(tp);
fac9b83e 6434
7938109f 6435 if (err) {
f47c11ee 6436 tg3_full_lock(tp, 0);
7938109f
MC		 6437
6438 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6439 pci_disable_msi(tp->pdev);
6440 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6441 }
944d980e 6442 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6443 tg3_free_rings(tp);
6444 tg3_free_consistent(tp);
6445
f47c11ee 6446 tg3_full_unlock(tp);
7938109f
MC		 6447
6448 return err;
6449 }
6450 }
6451
f47c11ee 6452 tg3_full_lock(tp, 0);
1da177e4 6453
7938109f
MC		 6454 add_timer(&tp->timer);
6455 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 6456 tg3_enable_ints(tp);
6457
f47c11ee 6458 tg3_full_unlock(tp);
1da177e4
LT		 6459
6460 netif_start_queue(dev);
6461
6462 return 0;
6463}
6464
6465#if 0
6466/*static*/ void tg3_dump_state(struct tg3 *tp)
6467{
6468 u32 val32, val32_2, val32_3, val32_4, val32_5;
6469 u16 val16;
6470 int i;
6471
6472 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6473 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6474 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6475 val16, val32);
6476
6477 /* MAC block */
6478 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6479 tr32(MAC_MODE), tr32(MAC_STATUS));
6480 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6481 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6482 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6483 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6484 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6485 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6486
6487 /* Send data initiator control block */
6488 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6489 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6490 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6491 tr32(SNDDATAI_STATSCTRL));
6492
6493 /* Send data completion control block */
6494 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6495
6496 /* Send BD ring selector block */
6497 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6498 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6499
6500 /* Send BD initiator control block */
6501 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6502 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6503
6504 /* Send BD completion control block */
6505 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6506
6507 /* Receive list placement control block */
6508 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6509 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6510 printk(" RCVLPC_STATSCTRL[%08x]\n",
6511 tr32(RCVLPC_STATSCTRL));
6512
6513 /* Receive data and receive BD initiator control block */
6514 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6515 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6516
6517 /* Receive data completion control block */
6518 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6519 tr32(RCVDCC_MODE));
6520
6521 /* Receive BD initiator control block */
6522 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6523 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6524
6525 /* Receive BD completion control block */
6526 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6527 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6528
6529 /* Receive list selector control block */
6530 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6531 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6532
6533 /* Mbuf cluster free block */
6534 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6535 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6536
6537 /* Host coalescing control block */
6538 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6539 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6540 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6541 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6542 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6543 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6544 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6545 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6546 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6547 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6548 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6549 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6550
6551 /* Memory arbiter control block */
6552 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6553 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6554
6555 /* Buffer manager control block */
6556 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6557 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6558 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6559 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6560 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6561 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6562 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6563 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6564
6565 /* Read DMA control block */
6566 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6567 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6568
6569 /* Write DMA control block */
6570 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6571 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6572
6573 /* DMA completion block */
6574 printk("DEBUG: DMAC_MODE[%08x]\n",
6575 tr32(DMAC_MODE));
6576
6577 /* GRC block */
6578 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6579 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6580 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6581 tr32(GRC_LOCAL_CTRL));
6582
6583 /* TG3_BDINFOs */
6584 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6585 tr32(RCVDBDI_JUMBO_BD + 0x0),
6586 tr32(RCVDBDI_JUMBO_BD + 0x4),
6587 tr32(RCVDBDI_JUMBO_BD + 0x8),
6588 tr32(RCVDBDI_JUMBO_BD + 0xc));
6589 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6590 tr32(RCVDBDI_STD_BD + 0x0),
6591 tr32(RCVDBDI_STD_BD + 0x4),
6592 tr32(RCVDBDI_STD_BD + 0x8),
6593 tr32(RCVDBDI_STD_BD + 0xc));
6594 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6595 tr32(RCVDBDI_MINI_BD + 0x0),
6596 tr32(RCVDBDI_MINI_BD + 0x4),
6597 tr32(RCVDBDI_MINI_BD + 0x8),
6598 tr32(RCVDBDI_MINI_BD + 0xc));
6599
6600 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6601 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6602 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6603 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6604 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6605 val32, val32_2, val32_3, val32_4);
6606
6607 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6608 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6609 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6610 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6611 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6612 val32, val32_2, val32_3, val32_4);
6613
6614 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6615 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6616 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6617 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6618 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6619 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6620 val32, val32_2, val32_3, val32_4, val32_5);
6621
6622 /* SW status block */
6623 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6624 tp->hw_status->status,
6625 tp->hw_status->status_tag,
6626 tp->hw_status->rx_jumbo_consumer,
6627 tp->hw_status->rx_consumer,
6628 tp->hw_status->rx_mini_consumer,
6629 tp->hw_status->idx[0].rx_producer,
6630 tp->hw_status->idx[0].tx_consumer);
6631
6632 /* SW statistics block */
6633 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6634 ((u32 *)tp->hw_stats)[0],
6635 ((u32 *)tp->hw_stats)[1],
6636 ((u32 *)tp->hw_stats)[2],
6637 ((u32 *)tp->hw_stats)[3]);
6638
6639 /* Mailboxes */
6640 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 6641 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6642 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6643 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6644 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 6645
6646 /* NIC side send descriptors. */
6647 for (i = 0; i < 6; i++) {
6648 unsigned long txd;
6649
6650 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6651 + (i * sizeof(struct tg3_tx_buffer_desc));
6652 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6653 i,
6654 readl(txd + 0x0), readl(txd + 0x4),
6655 readl(txd + 0x8), readl(txd + 0xc));
6656 }
6657
6658 /* NIC side RX descriptors. */
6659 for (i = 0; i < 6; i++) {
6660 unsigned long rxd;
6661
6662 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6663 + (i * sizeof(struct tg3_rx_buffer_desc));
6664 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6665 i,
6666 readl(rxd + 0x0), readl(rxd + 0x4),
6667 readl(rxd + 0x8), readl(rxd + 0xc));
6668 rxd += (4 * sizeof(u32));
6669 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6670 i,
6671 readl(rxd + 0x0), readl(rxd + 0x4),
6672 readl(rxd + 0x8), readl(rxd + 0xc));
6673 }
6674
6675 for (i = 0; i < 6; i++) {
6676 unsigned long rxd;
6677
6678 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6679 + (i * sizeof(struct tg3_rx_buffer_desc));
6680 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6681 i,
6682 readl(rxd + 0x0), readl(rxd + 0x4),
6683 readl(rxd + 0x8), readl(rxd + 0xc));
6684 rxd += (4 * sizeof(u32));
6685 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6686 i,
6687 readl(rxd + 0x0), readl(rxd + 0x4),
6688 readl(rxd + 0x8), readl(rxd + 0xc));
6689 }
6690}
6691#endif
6692
6693static struct net_device_stats *tg3_get_stats(struct net_device *);
6694static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6695
6696static int tg3_close(struct net_device *dev)
6697{
6698 struct tg3 *tp = netdev_priv(dev);
6699
6700 netif_stop_queue(dev);
6701
6702 del_timer_sync(&tp->timer);
6703
f47c11ee 6704 tg3_full_lock(tp, 1);
1da177e4
LT		 6705#if 0
6706 tg3_dump_state(tp);
6707#endif
6708
6709 tg3_disable_ints(tp);
6710
944d980e 6711 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6712 tg3_free_rings(tp);
6713 tp->tg3_flags &=
6714 ~(TG3_FLAG_INIT_COMPLETE |
6715 TG3_FLAG_GOT_SERDES_FLOWCTL);
6716 netif_carrier_off(tp->dev);
6717
f47c11ee 6718 tg3_full_unlock(tp);
1da177e4 6719
88b06bc2
MC		 6720 free_irq(tp->pdev->irq, dev);
6721 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6722 pci_disable_msi(tp->pdev);
6723 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6724 }
1da177e4
LT		 6725
6726 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6727 sizeof(tp->net_stats_prev));
6728 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6729 sizeof(tp->estats_prev));
6730
6731 tg3_free_consistent(tp);
6732
6733 return 0;
6734}
6735
6736static inline unsigned long get_stat64(tg3_stat64_t *val)
6737{
6738 unsigned long ret;
6739
6740#if (BITS_PER_LONG == 32)
6741 ret = val->low;
6742#else
6743 ret = ((u64)val->high << 32) | ((u64)val->low);
6744#endif
6745 return ret;
6746}
6747
6748static unsigned long calc_crc_errors(struct tg3 *tp)
6749{
6750 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6751
6752 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6753 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6754 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 6755 u32 val;
6756
f47c11ee 6757 spin_lock_bh(&tp->lock);
1da177e4
LT		 6758 if (!tg3_readphy(tp, 0x1e, &val)) {
6759 tg3_writephy(tp, 0x1e, val | 0x8000);
6760 tg3_readphy(tp, 0x14, &val);
6761 } else
6762 val = 0;
f47c11ee 6763 spin_unlock_bh(&tp->lock);
1da177e4
LT		 6764
6765 tp->phy_crc_errors += val;
6766
6767 return tp->phy_crc_errors;
6768 }
6769
6770 return get_stat64(&hw_stats->rx_fcs_errors);
6771}
6772
6773#define ESTAT_ADD(member) \
6774 estats->member = old_estats->member + \
6775 get_stat64(&hw_stats->member)
6776
6777static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6778{
6779 struct tg3_ethtool_stats *estats = &tp->estats;
6780 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6781 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6782
6783 if (!hw_stats)
6784 return old_estats;
6785
6786 ESTAT_ADD(rx_octets);
6787 ESTAT_ADD(rx_fragments);
6788 ESTAT_ADD(rx_ucast_packets);
6789 ESTAT_ADD(rx_mcast_packets);
6790 ESTAT_ADD(rx_bcast_packets);
6791 ESTAT_ADD(rx_fcs_errors);
6792 ESTAT_ADD(rx_align_errors);
6793 ESTAT_ADD(rx_xon_pause_rcvd);
6794 ESTAT_ADD(rx_xoff_pause_rcvd);
6795 ESTAT_ADD(rx_mac_ctrl_rcvd);
6796 ESTAT_ADD(rx_xoff_entered);
6797 ESTAT_ADD(rx_frame_too_long_errors);
6798 ESTAT_ADD(rx_jabbers);
6799 ESTAT_ADD(rx_undersize_packets);
6800 ESTAT_ADD(rx_in_length_errors);
6801 ESTAT_ADD(rx_out_length_errors);
6802 ESTAT_ADD(rx_64_or_less_octet_packets);
6803 ESTAT_ADD(rx_65_to_127_octet_packets);
6804 ESTAT_ADD(rx_128_to_255_octet_packets);
6805 ESTAT_ADD(rx_256_to_511_octet_packets);
6806 ESTAT_ADD(rx_512_to_1023_octet_packets);
6807 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6808 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6809 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6810 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6811 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6812
6813 ESTAT_ADD(tx_octets);
6814 ESTAT_ADD(tx_collisions);
6815 ESTAT_ADD(tx_xon_sent);
6816 ESTAT_ADD(tx_xoff_sent);
6817 ESTAT_ADD(tx_flow_control);
6818 ESTAT_ADD(tx_mac_errors);
6819 ESTAT_ADD(tx_single_collisions);
6820 ESTAT_ADD(tx_mult_collisions);
6821 ESTAT_ADD(tx_deferred);
6822 ESTAT_ADD(tx_excessive_collisions);
6823 ESTAT_ADD(tx_late_collisions);
6824 ESTAT_ADD(tx_collide_2times);
6825 ESTAT_ADD(tx_collide_3times);
6826 ESTAT_ADD(tx_collide_4times);
6827 ESTAT_ADD(tx_collide_5times);
6828 ESTAT_ADD(tx_collide_6times);
6829 ESTAT_ADD(tx_collide_7times);
6830 ESTAT_ADD(tx_collide_8times);
6831 ESTAT_ADD(tx_collide_9times);
6832 ESTAT_ADD(tx_collide_10times);
6833 ESTAT_ADD(tx_collide_11times);
6834 ESTAT_ADD(tx_collide_12times);
6835 ESTAT_ADD(tx_collide_13times);
6836 ESTAT_ADD(tx_collide_14times);
6837 ESTAT_ADD(tx_collide_15times);
6838 ESTAT_ADD(tx_ucast_packets);
6839 ESTAT_ADD(tx_mcast_packets);
6840 ESTAT_ADD(tx_bcast_packets);
6841 ESTAT_ADD(tx_carrier_sense_errors);
6842 ESTAT_ADD(tx_discards);
6843 ESTAT_ADD(tx_errors);
6844
6845 ESTAT_ADD(dma_writeq_full);
6846 ESTAT_ADD(dma_write_prioq_full);
6847 ESTAT_ADD(rxbds_empty);
6848 ESTAT_ADD(rx_discards);
6849 ESTAT_ADD(rx_errors);
6850 ESTAT_ADD(rx_threshold_hit);
6851
6852 ESTAT_ADD(dma_readq_full);
6853 ESTAT_ADD(dma_read_prioq_full);
6854 ESTAT_ADD(tx_comp_queue_full);
6855
6856 ESTAT_ADD(ring_set_send_prod_index);
6857 ESTAT_ADD(ring_status_update);
6858 ESTAT_ADD(nic_irqs);
6859 ESTAT_ADD(nic_avoided_irqs);
6860 ESTAT_ADD(nic_tx_threshold_hit);
6861
6862 return estats;
6863}
6864
6865static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6866{
6867 struct tg3 *tp = netdev_priv(dev);
6868 struct net_device_stats *stats = &tp->net_stats;
6869 struct net_device_stats *old_stats = &tp->net_stats_prev;
6870 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6871
6872 if (!hw_stats)
6873 return old_stats;
6874
6875 stats->rx_packets = old_stats->rx_packets +
6876 get_stat64(&hw_stats->rx_ucast_packets) +
6877 get_stat64(&hw_stats->rx_mcast_packets) +
6878 get_stat64(&hw_stats->rx_bcast_packets);
6879
6880 stats->tx_packets = old_stats->tx_packets +
6881 get_stat64(&hw_stats->tx_ucast_packets) +
6882 get_stat64(&hw_stats->tx_mcast_packets) +
6883 get_stat64(&hw_stats->tx_bcast_packets);
6884
6885 stats->rx_bytes = old_stats->rx_bytes +
6886 get_stat64(&hw_stats->rx_octets);
6887 stats->tx_bytes = old_stats->tx_bytes +
6888 get_stat64(&hw_stats->tx_octets);
6889
6890 stats->rx_errors = old_stats->rx_errors +
4f63b877 6891 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 6892 stats->tx_errors = old_stats->tx_errors +
6893 get_stat64(&hw_stats->tx_errors) +
6894 get_stat64(&hw_stats->tx_mac_errors) +
6895 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6896 get_stat64(&hw_stats->tx_discards);
6897
6898 stats->multicast = old_stats->multicast +
6899 get_stat64(&hw_stats->rx_mcast_packets);
6900 stats->collisions = old_stats->collisions +
6901 get_stat64(&hw_stats->tx_collisions);
6902
6903 stats->rx_length_errors = old_stats->rx_length_errors +
6904 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6905 get_stat64(&hw_stats->rx_undersize_packets);
6906
6907 stats->rx_over_errors = old_stats->rx_over_errors +
6908 get_stat64(&hw_stats->rxbds_empty);
6909 stats->rx_frame_errors = old_stats->rx_frame_errors +
6910 get_stat64(&hw_stats->rx_align_errors);
6911 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6912 get_stat64(&hw_stats->tx_discards);
6913 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6914 get_stat64(&hw_stats->tx_carrier_sense_errors);
6915
6916 stats->rx_crc_errors = old_stats->rx_crc_errors +
6917 calc_crc_errors(tp);
6918
4f63b877
JL		 6919 stats->rx_missed_errors = old_stats->rx_missed_errors +
6920 get_stat64(&hw_stats->rx_discards);
6921
1da177e4
LT		 6922 return stats;
6923}
6924
6925static inline u32 calc_crc(unsigned char *buf, int len)
6926{
6927 u32 reg;
6928 u32 tmp;
6929 int j, k;
6930
6931 reg = 0xffffffff;
6932
6933 for (j = 0; j < len; j++) {
6934 reg ^= buf[j];
6935
6936 for (k = 0; k < 8; k++) {
6937 tmp = reg & 0x01;
6938
6939 reg >>= 1;
6940
6941 if (tmp) {
6942 reg ^= 0xedb88320;
6943 }
6944 }
6945 }
6946
6947 return ~reg;
6948}
6949
6950static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6951{
6952 /* accept or reject all multicast frames */
6953 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6954 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6955 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6956 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6957}
6958
6959static void __tg3_set_rx_mode(struct net_device *dev)
6960{
6961 struct tg3 *tp = netdev_priv(dev);
6962 u32 rx_mode;
6963
6964 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6965 RX_MODE_KEEP_VLAN_TAG);
6966
6967 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6968 * flag clear.
6969 */
6970#if TG3_VLAN_TAG_USED
6971 if (!tp->vlgrp &&
6972 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6973 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6974#else
6975 /* By definition, VLAN is disabled always in this
6976 * case.
6977 */
6978 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6979 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6980#endif
6981
6982 if (dev->flags & IFF_PROMISC) {
6983 /* Promiscuous mode. */
6984 rx_mode |= RX_MODE_PROMISC;
6985 } else if (dev->flags & IFF_ALLMULTI) {
6986 /* Accept all multicast. */
6987 tg3_set_multi (tp, 1);
6988 } else if (dev->mc_count < 1) {
6989 /* Reject all multicast. */
6990 tg3_set_multi (tp, 0);
6991 } else {
6992 /* Accept one or more multicast(s). */
6993 struct dev_mc_list *mclist;
6994 unsigned int i;
6995 u32 mc_filter[4] = { 0, };
6996 u32 regidx;
6997 u32 bit;
6998 u32 crc;
6999
7000 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7001 i++, mclist = mclist->next) {
7002
7003 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7004 bit = ~crc & 0x7f;
7005 regidx = (bit & 0x60) >> 5;
7006 bit &= 0x1f;
7007 mc_filter[regidx] |= (1 << bit);
7008 }
7009
7010 tw32(MAC_HASH_REG_0, mc_filter[0]);
7011 tw32(MAC_HASH_REG_1, mc_filter[1]);
7012 tw32(MAC_HASH_REG_2, mc_filter[2]);
7013 tw32(MAC_HASH_REG_3, mc_filter[3]);
7014 }
7015
7016 if (rx_mode != tp->rx_mode) {
7017 tp->rx_mode = rx_mode;
7018 tw32_f(MAC_RX_MODE, rx_mode);
7019 udelay(10);
7020 }
7021}
7022
7023static void tg3_set_rx_mode(struct net_device *dev)
7024{
7025 struct tg3 *tp = netdev_priv(dev);
7026
f47c11ee 7027 tg3_full_lock(tp, 0);
1da177e4 7028 __tg3_set_rx_mode(dev);
f47c11ee 7029 tg3_full_unlock(tp);
1da177e4
LT		 7030}
7031
7032#define TG3_REGDUMP_LEN (32 * 1024)
7033
7034static int tg3_get_regs_len(struct net_device *dev)
7035{
7036 return TG3_REGDUMP_LEN;
7037}
7038
7039static void tg3_get_regs(struct net_device *dev,
7040 struct ethtool_regs *regs, void *_p)
7041{
7042 u32 *p = _p;
7043 struct tg3 *tp = netdev_priv(dev);
7044 u8 *orig_p = _p;
7045 int i;
7046
7047 regs->version = 0;
7048
7049 memset(p, 0, TG3_REGDUMP_LEN);
7050
f47c11ee 7051 tg3_full_lock(tp, 0);
1da177e4
LT		 7052
7053#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7054#define GET_REG32_LOOP(base,len) \
7055do { p = (u32 *)(orig_p + (base)); \
7056 for (i = 0; i < len; i += 4) \
7057 __GET_REG32((base) + i); \
7058} while (0)
7059#define GET_REG32_1(reg) \
7060do { p = (u32 *)(orig_p + (reg)); \
7061 __GET_REG32((reg)); \
7062} while (0)
7063
7064 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7065 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7066 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7067 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7068 GET_REG32_1(SNDDATAC_MODE);
7069 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7070 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7071 GET_REG32_1(SNDBDC_MODE);
7072 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7073 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7074 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7075 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7076 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7077 GET_REG32_1(RCVDCC_MODE);
7078 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7079 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7080 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7081 GET_REG32_1(MBFREE_MODE);
7082 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7083 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7084 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7085 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7086 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7087 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
7088 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
7089 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7090 GET_REG32_LOOP(FTQ_RESET, 0x120);
7091 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7092 GET_REG32_1(DMAC_MODE);
7093 GET_REG32_LOOP(GRC_MODE, 0x4c);
7094 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7095 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7096
7097#undef __GET_REG32
7098#undef GET_REG32_LOOP
7099#undef GET_REG32_1
7100
f47c11ee 7101 tg3_full_unlock(tp);
1da177e4
LT		 7102}
7103
7104static int tg3_get_eeprom_len(struct net_device *dev)
7105{
7106 struct tg3 *tp = netdev_priv(dev);
7107
7108 return tp->nvram_size;
7109}
7110
7111static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7112
7113static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7114{
7115 struct tg3 *tp = netdev_priv(dev);
7116 int ret;
7117 u8 *pd;
7118 u32 i, offset, len, val, b_offset, b_count;
7119
7120 offset = eeprom->offset;
7121 len = eeprom->len;
7122 eeprom->len = 0;
7123
7124 eeprom->magic = TG3_EEPROM_MAGIC;
7125
7126 if (offset & 3) {
7127 /* adjustments to start on required 4 byte boundary */
7128 b_offset = offset & 3;
7129 b_count = 4 - b_offset;
7130 if (b_count > len) {
7131 /* i.e. offset=1 len=2 */
7132 b_count = len;
7133 }
7134 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7135 if (ret)
7136 return ret;
7137 val = cpu_to_le32(val);
7138 memcpy(data, ((char*)&val) + b_offset, b_count);
7139 len -= b_count;
7140 offset += b_count;
7141 eeprom->len += b_count;
7142 }
7143
7144 /* read bytes upto the last 4 byte boundary */
7145 pd = &data[eeprom->len];
7146 for (i = 0; i < (len - (len & 3)); i += 4) {
7147 ret = tg3_nvram_read(tp, offset + i, &val);
7148 if (ret) {
7149 eeprom->len += i;
7150 return ret;
7151 }
7152 val = cpu_to_le32(val);
7153 memcpy(pd + i, &val, 4);
7154 }
7155 eeprom->len += i;
7156
7157 if (len & 3) {
7158 /* read last bytes not ending on 4 byte boundary */
7159 pd = &data[eeprom->len];
7160 b_count = len & 3;
7161 b_offset = offset + len - b_count;
7162 ret = tg3_nvram_read(tp, b_offset, &val);
7163 if (ret)
7164 return ret;
7165 val = cpu_to_le32(val);
7166 memcpy(pd, ((char*)&val), b_count);
7167 eeprom->len += b_count;
7168 }
7169 return 0;
7170}
7171
7172static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7173
7174static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7175{
7176 struct tg3 *tp = netdev_priv(dev);
7177 int ret;
7178 u32 offset, len, b_offset, odd_len, start, end;
7179 u8 *buf;
7180
7181 if (eeprom->magic != TG3_EEPROM_MAGIC)
7182 return -EINVAL;
7183
7184 offset = eeprom->offset;
7185 len = eeprom->len;
7186
7187 if ((b_offset = (offset & 3))) {
7188 /* adjustments to start on required 4 byte boundary */
7189 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7190 if (ret)
7191 return ret;
7192 start = cpu_to_le32(start);
7193 len += b_offset;
7194 offset &= ~3;
1c8594b4
MC		 7195 if (len < 4)
7196 len = 4;
1da177e4
LT		 7197 }
7198
7199 odd_len = 0;
1c8594b4 7200 if (len & 3) {
1da177e4
LT		 7201 /* adjustments to end on required 4 byte boundary */
7202 odd_len = 1;
7203 len = (len + 3) & ~3;
7204 ret = tg3_nvram_read(tp, offset+len-4, &end);
7205 if (ret)
7206 return ret;
7207 end = cpu_to_le32(end);
7208 }
7209
7210 buf = data;
7211 if (b_offset || odd_len) {
7212 buf = kmalloc(len, GFP_KERNEL);
7213 if (buf == 0)
7214 return -ENOMEM;
7215 if (b_offset)
7216 memcpy(buf, &start, 4);
7217 if (odd_len)
7218 memcpy(buf+len-4, &end, 4);
7219 memcpy(buf + b_offset, data, eeprom->len);
7220 }
7221
7222 ret = tg3_nvram_write_block(tp, offset, len, buf);
7223
7224 if (buf != data)
7225 kfree(buf);
7226
7227 return ret;
7228}
7229
7230static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7231{
7232 struct tg3 *tp = netdev_priv(dev);
7233
7234 cmd->supported = (SUPPORTED_Autoneg);
7235
7236 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7237 cmd->supported |= (SUPPORTED_1000baseT_Half |
7238 SUPPORTED_1000baseT_Full);
7239
7240 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
7241 cmd->supported |= (SUPPORTED_100baseT_Half |
7242 SUPPORTED_100baseT_Full |
7243 SUPPORTED_10baseT_Half |
7244 SUPPORTED_10baseT_Full |
7245 SUPPORTED_MII);
7246 else
7247 cmd->supported |= SUPPORTED_FIBRE;
7248
7249 cmd->advertising = tp->link_config.advertising;
7250 if (netif_running(dev)) {
7251 cmd->speed = tp->link_config.active_speed;
7252 cmd->duplex = tp->link_config.active_duplex;
7253 }
7254 cmd->port = 0;
7255 cmd->phy_address = PHY_ADDR;
7256 cmd->transceiver = 0;
7257 cmd->autoneg = tp->link_config.autoneg;
7258 cmd->maxtxpkt = 0;
7259 cmd->maxrxpkt = 0;
7260 return 0;
7261}
7262
7263static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7264{
7265 struct tg3 *tp = netdev_priv(dev);
7266
7267 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7268 /* These are the only valid advertisement bits allowed. */
7269 if (cmd->autoneg == AUTONEG_ENABLE &&
7270 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7271 ADVERTISED_1000baseT_Full |
7272 ADVERTISED_Autoneg |
7273 ADVERTISED_FIBRE)))
7274 return -EINVAL;
7275 }
7276
f47c11ee 7277 tg3_full_lock(tp, 0);
1da177e4
LT		 7278
7279 tp->link_config.autoneg = cmd->autoneg;
7280 if (cmd->autoneg == AUTONEG_ENABLE) {
7281 tp->link_config.advertising = cmd->advertising;
7282 tp->link_config.speed = SPEED_INVALID;
7283 tp->link_config.duplex = DUPLEX_INVALID;
7284 } else {
7285 tp->link_config.advertising = 0;
7286 tp->link_config.speed = cmd->speed;
7287 tp->link_config.duplex = cmd->duplex;
7288 }
7289
7290 if (netif_running(dev))
7291 tg3_setup_phy(tp, 1);
7292
f47c11ee 7293 tg3_full_unlock(tp);
1da177e4
LT		 7294
7295 return 0;
7296}
7297
7298static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7299{
7300 struct tg3 *tp = netdev_priv(dev);
7301
7302 strcpy(info->driver, DRV_MODULE_NAME);
7303 strcpy(info->version, DRV_MODULE_VERSION);
7304 strcpy(info->bus_info, pci_name(tp->pdev));
7305}
7306
7307static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7308{
7309 struct tg3 *tp = netdev_priv(dev);
7310
7311 wol->supported = WAKE_MAGIC;
7312 wol->wolopts = 0;
7313 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7314 wol->wolopts = WAKE_MAGIC;
7315 memset(&wol->sopass, 0, sizeof(wol->sopass));
7316}
7317
7318static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7319{
7320 struct tg3 *tp = netdev_priv(dev);
7321
7322 if (wol->wolopts & ~WAKE_MAGIC)
7323 return -EINVAL;
7324 if ((wol->wolopts & WAKE_MAGIC) &&
7325 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7326 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7327 return -EINVAL;
7328
f47c11ee 7329 spin_lock_bh(&tp->lock);
1da177e4
LT		 7330 if (wol->wolopts & WAKE_MAGIC)
7331 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7332 else
7333 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 7334 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7335
7336 return 0;
7337}
7338
7339static u32 tg3_get_msglevel(struct net_device *dev)
7340{
7341 struct tg3 *tp = netdev_priv(dev);
7342 return tp->msg_enable;
7343}
7344
7345static void tg3_set_msglevel(struct net_device *dev, u32 value)
7346{
7347 struct tg3 *tp = netdev_priv(dev);
7348 tp->msg_enable = value;
7349}
7350
7351#if TG3_TSO_SUPPORT != 0
7352static int tg3_set_tso(struct net_device *dev, u32 value)
7353{
7354 struct tg3 *tp = netdev_priv(dev);
7355
7356 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7357 if (value)
7358 return -EINVAL;
7359 return 0;
7360 }
7361 return ethtool_op_set_tso(dev, value);
7362}
7363#endif
7364
7365static int tg3_nway_reset(struct net_device *dev)
7366{
7367 struct tg3 *tp = netdev_priv(dev);
7368 u32 bmcr;
7369 int r;
7370
7371 if (!netif_running(dev))
7372 return -EAGAIN;
7373
c94e3941
MC		 7374 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7375 return -EINVAL;
7376
f47c11ee 7377 spin_lock_bh(&tp->lock);
1da177e4
LT		 7378 r = -EINVAL;
7379 tg3_readphy(tp, MII_BMCR, &bmcr);
7380 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 7381 ((bmcr & BMCR_ANENABLE) ||
7382 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7383 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7384 BMCR_ANENABLE);
1da177e4
LT		 7385 r = 0;
7386 }
f47c11ee 7387 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7388
7389 return r;
7390}
7391
7392static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7393{
7394 struct tg3 *tp = netdev_priv(dev);
7395
7396 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7397 ering->rx_mini_max_pending = 0;
7398 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7399
7400 ering->rx_pending = tp->rx_pending;
7401 ering->rx_mini_pending = 0;
7402 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7403 ering->tx_pending = tp->tx_pending;
7404}
7405
7406static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7407{
7408 struct tg3 *tp = netdev_priv(dev);
bbe832c0 7409 int irq_sync = 0;
1da177e4
LT		 7410
7411 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7412 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7413 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7414 return -EINVAL;
7415
bbe832c0 7416 if (netif_running(dev)) {
1da177e4 7417 tg3_netif_stop(tp);
bbe832c0
MC		 7418 irq_sync = 1;
7419 }
1da177e4 7420
bbe832c0 7421 tg3_full_lock(tp, irq_sync);
1da177e4
LT		 7422
7423 tp->rx_pending = ering->rx_pending;
7424
7425 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7426 tp->rx_pending > 63)
7427 tp->rx_pending = 63;
7428 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7429 tp->tx_pending = ering->tx_pending;
7430
7431 if (netif_running(dev)) {
944d980e 7432 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7433 tg3_init_hw(tp);
7434 tg3_netif_start(tp);
7435 }
7436
f47c11ee 7437 tg3_full_unlock(tp);
1da177e4
LT		 7438
7439 return 0;
7440}
7441
7442static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7443{
7444 struct tg3 *tp = netdev_priv(dev);
7445
7446 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7447 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7448 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7449}
7450
7451static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7452{
7453 struct tg3 *tp = netdev_priv(dev);
bbe832c0 7454 int irq_sync = 0;
1da177e4 7455
bbe832c0 7456 if (netif_running(dev)) {
1da177e4 7457 tg3_netif_stop(tp);
bbe832c0
MC		 7458 irq_sync = 1;
7459 }
1da177e4 7460
bbe832c0 7461 tg3_full_lock(tp, irq_sync);
f47c11ee 7462
1da177e4
LT		 7463 if (epause->autoneg)
7464 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7465 else
7466 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7467 if (epause->rx_pause)
7468 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7469 else
7470 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7471 if (epause->tx_pause)
7472 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7473 else
7474 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7475
7476 if (netif_running(dev)) {
944d980e 7477 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7478 tg3_init_hw(tp);
7479 tg3_netif_start(tp);
7480 }
f47c11ee
DM		 7481
7482 tg3_full_unlock(tp);
1da177e4
LT		 7483
7484 return 0;
7485}
7486
7487static u32 tg3_get_rx_csum(struct net_device *dev)
7488{
7489 struct tg3 *tp = netdev_priv(dev);
7490 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7491}
7492
7493static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7494{
7495 struct tg3 *tp = netdev_priv(dev);
7496
7497 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7498 if (data != 0)
7499 return -EINVAL;
7500 return 0;
7501 }
7502
f47c11ee 7503 spin_lock_bh(&tp->lock);
1da177e4
LT		 7504 if (data)
7505 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7506 else
7507 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 7508 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7509
7510 return 0;
7511}
7512
7513static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7514{
7515 struct tg3 *tp = netdev_priv(dev);
7516
7517 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7518 if (data != 0)
7519 return -EINVAL;
7520 return 0;
7521 }
7522
7523 if (data)
7524 dev->features |= NETIF_F_IP_CSUM;
7525 else
7526 dev->features &= ~NETIF_F_IP_CSUM;
7527
7528 return 0;
7529}
7530
7531static int tg3_get_stats_count (struct net_device *dev)
7532{
7533 return TG3_NUM_STATS;
7534}
7535
4cafd3f5
MC		 7536static int tg3_get_test_count (struct net_device *dev)
7537{
7538 return TG3_NUM_TEST;
7539}
7540
1da177e4
LT		 7541static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7542{
7543 switch (stringset) {
7544 case ETH_SS_STATS:
7545 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7546 break;
4cafd3f5
MC		 7547 case ETH_SS_TEST:
7548 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7549 break;
1da177e4
LT		 7550 default:
7551 WARN_ON(1); /* we need a WARN() */
7552 break;
7553 }
7554}
7555
4009a93d
MC		 7556static int tg3_phys_id(struct net_device *dev, u32 data)
7557{
7558 struct tg3 *tp = netdev_priv(dev);
7559 int i;
7560
7561 if (!netif_running(tp->dev))
7562 return -EAGAIN;
7563
7564 if (data == 0)
7565 data = 2;
7566
7567 for (i = 0; i < (data * 2); i++) {
7568 if ((i % 2) == 0)
7569 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7570 LED_CTRL_1000MBPS_ON |
7571 LED_CTRL_100MBPS_ON |
7572 LED_CTRL_10MBPS_ON |
7573 LED_CTRL_TRAFFIC_OVERRIDE |
7574 LED_CTRL_TRAFFIC_BLINK |
7575 LED_CTRL_TRAFFIC_LED);
7576
7577 else
7578 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7579 LED_CTRL_TRAFFIC_OVERRIDE);
7580
7581 if (msleep_interruptible(500))
7582 break;
7583 }
7584 tw32(MAC_LED_CTRL, tp->led_ctrl);
7585 return 0;
7586}
7587
1da177e4
LT		 7588static void tg3_get_ethtool_stats (struct net_device *dev,
7589 struct ethtool_stats *estats, u64 *tmp_stats)
7590{
7591 struct tg3 *tp = netdev_priv(dev);
7592 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7593}
7594
566f86ad
MC		 7595#define NVRAM_TEST_SIZE 0x100
7596
7597static int tg3_test_nvram(struct tg3 *tp)
7598{
7599 u32 *buf, csum;
7600 int i, j, err = 0;
7601
7602 buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7603 if (buf == NULL)
7604 return -ENOMEM;
7605
7606 for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7607 u32 val;
7608
7609 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7610 break;
7611 buf[j] = cpu_to_le32(val);
7612 }
7613 if (i < NVRAM_TEST_SIZE)
7614 goto out;
7615
7616 err = -EIO;
7617 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7618 goto out;
7619
7620 /* Bootstrap checksum at offset 0x10 */
7621 csum = calc_crc((unsigned char *) buf, 0x10);
7622 if(csum != cpu_to_le32(buf[0x10/4]))
7623 goto out;
7624
7625 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7626 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7627 if (csum != cpu_to_le32(buf[0xfc/4]))
7628 goto out;
7629
7630 err = 0;
7631
7632out:
7633 kfree(buf);
7634 return err;
7635}
7636
ca43007a
MC		 7637#define TG3_SERDES_TIMEOUT_SEC 2
7638#define TG3_COPPER_TIMEOUT_SEC 6
7639
7640static int tg3_test_link(struct tg3 *tp)
7641{
7642 int i, max;
7643
7644 if (!netif_running(tp->dev))
7645 return -ENODEV;
7646
4c987487 7647 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 7648 max = TG3_SERDES_TIMEOUT_SEC;
7649 else
7650 max = TG3_COPPER_TIMEOUT_SEC;
7651
7652 for (i = 0; i < max; i++) {
7653 if (netif_carrier_ok(tp->dev))
7654 return 0;
7655
7656 if (msleep_interruptible(1000))
7657 break;
7658 }
7659
7660 return -EIO;
7661}
7662
a71116d1
MC		 7663/* Only test the commonly used registers */
7664static int tg3_test_registers(struct tg3 *tp)
7665{
7666 int i, is_5705;
7667 u32 offset, read_mask, write_mask, val, save_val, read_val;
7668 static struct {
7669 u16 offset;
7670 u16 flags;
7671#define TG3_FL_5705 0x1
7672#define TG3_FL_NOT_5705 0x2
7673#define TG3_FL_NOT_5788 0x4
7674 u32 read_mask;
7675 u32 write_mask;
7676 } reg_tbl[] = {
7677 /* MAC Control Registers */
7678 { MAC_MODE, TG3_FL_NOT_5705,
7679 0x00000000, 0x00ef6f8c },
7680 { MAC_MODE, TG3_FL_5705,
7681 0x00000000, 0x01ef6b8c },
7682 { MAC_STATUS, TG3_FL_NOT_5705,
7683 0x03800107, 0x00000000 },
7684 { MAC_STATUS, TG3_FL_5705,
7685 0x03800100, 0x00000000 },
7686 { MAC_ADDR_0_HIGH, 0x0000,
7687 0x00000000, 0x0000ffff },
7688 { MAC_ADDR_0_LOW, 0x0000,
7689 0x00000000, 0xffffffff },
7690 { MAC_RX_MTU_SIZE, 0x0000,
7691 0x00000000, 0x0000ffff },
7692 { MAC_TX_MODE, 0x0000,
7693 0x00000000, 0x00000070 },
7694 { MAC_TX_LENGTHS, 0x0000,
7695 0x00000000, 0x00003fff },
7696 { MAC_RX_MODE, TG3_FL_NOT_5705,
7697 0x00000000, 0x000007fc },
7698 { MAC_RX_MODE, TG3_FL_5705,
7699 0x00000000, 0x000007dc },
7700 { MAC_HASH_REG_0, 0x0000,
7701 0x00000000, 0xffffffff },
7702 { MAC_HASH_REG_1, 0x0000,
7703 0x00000000, 0xffffffff },
7704 { MAC_HASH_REG_2, 0x0000,
7705 0x00000000, 0xffffffff },
7706 { MAC_HASH_REG_3, 0x0000,
7707 0x00000000, 0xffffffff },
7708
7709 /* Receive Data and Receive BD Initiator Control Registers. */
7710 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7711 0x00000000, 0xffffffff },
7712 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7713 0x00000000, 0xffffffff },
7714 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7715 0x00000000, 0x00000003 },
7716 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7717 0x00000000, 0xffffffff },
7718 { RCVDBDI_STD_BD+0, 0x0000,
7719 0x00000000, 0xffffffff },
7720 { RCVDBDI_STD_BD+4, 0x0000,
7721 0x00000000, 0xffffffff },
7722 { RCVDBDI_STD_BD+8, 0x0000,
7723 0x00000000, 0xffff0002 },
7724 { RCVDBDI_STD_BD+0xc, 0x0000,
7725 0x00000000, 0xffffffff },
7726
7727 /* Receive BD Initiator Control Registers. */
7728 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7729 0x00000000, 0xffffffff },
7730 { RCVBDI_STD_THRESH, TG3_FL_5705,
7731 0x00000000, 0x000003ff },
7732 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7733 0x00000000, 0xffffffff },
7734
7735 /* Host Coalescing Control Registers. */
7736 { HOSTCC_MODE, TG3_FL_NOT_5705,
7737 0x00000000, 0x00000004 },
7738 { HOSTCC_MODE, TG3_FL_5705,
7739 0x00000000, 0x000000f6 },
7740 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7741 0x00000000, 0xffffffff },
7742 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7743 0x00000000, 0x000003ff },
7744 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7745 0x00000000, 0xffffffff },
7746 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7747 0x00000000, 0x000003ff },
7748 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7749 0x00000000, 0xffffffff },
7750 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7751 0x00000000, 0x000000ff },
7752 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7753 0x00000000, 0xffffffff },
7754 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7755 0x00000000, 0x000000ff },
7756 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7757 0x00000000, 0xffffffff },
7758 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7759 0x00000000, 0xffffffff },
7760 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7761 0x00000000, 0xffffffff },
7762 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7763 0x00000000, 0x000000ff },
7764 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7765 0x00000000, 0xffffffff },
7766 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7767 0x00000000, 0x000000ff },
7768 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7769 0x00000000, 0xffffffff },
7770 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7771 0x00000000, 0xffffffff },
7772 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7773 0x00000000, 0xffffffff },
7774 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7775 0x00000000, 0xffffffff },
7776 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7777 0x00000000, 0xffffffff },
7778 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7779 0xffffffff, 0x00000000 },
7780 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7781 0xffffffff, 0x00000000 },
7782
7783 /* Buffer Manager Control Registers. */
7784 { BUFMGR_MB_POOL_ADDR, 0x0000,
7785 0x00000000, 0x007fff80 },
7786 { BUFMGR_MB_POOL_SIZE, 0x0000,
7787 0x00000000, 0x007fffff },
7788 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7789 0x00000000, 0x0000003f },
7790 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7791 0x00000000, 0x000001ff },
7792 { BUFMGR_MB_HIGH_WATER, 0x0000,
7793 0x00000000, 0x000001ff },
7794 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7795 0xffffffff, 0x00000000 },
7796 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7797 0xffffffff, 0x00000000 },
7798
7799 /* Mailbox Registers */
7800 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7801 0x00000000, 0x000001ff },
7802 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7803 0x00000000, 0x000001ff },
7804 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7805 0x00000000, 0x000007ff },
7806 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7807 0x00000000, 0x000001ff },
7808
7809 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7810 };
7811
7812 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7813 is_5705 = 1;
7814 else
7815 is_5705 = 0;
7816
7817 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7818 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7819 continue;
7820
7821 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7822 continue;
7823
7824 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7825 (reg_tbl[i].flags & TG3_FL_NOT_5788))
7826 continue;
7827
7828 offset = (u32) reg_tbl[i].offset;
7829 read_mask = reg_tbl[i].read_mask;
7830 write_mask = reg_tbl[i].write_mask;
7831
7832 /* Save the original register content */
7833 save_val = tr32(offset);
7834
7835 /* Determine the read-only value. */
7836 read_val = save_val & read_mask;
7837
7838 /* Write zero to the register, then make sure the read-only bits
7839 * are not changed and the read/write bits are all zeros.
7840 */
7841 tw32(offset, 0);
7842
7843 val = tr32(offset);
7844
7845 /* Test the read-only and read/write bits. */
7846 if (((val & read_mask) != read_val) || (val & write_mask))
7847 goto out;
7848
7849 /* Write ones to all the bits defined by RdMask and WrMask, then
7850 * make sure the read-only bits are not changed and the
7851 * read/write bits are all ones.
7852 */
7853 tw32(offset, read_mask | write_mask);
7854
7855 val = tr32(offset);
7856
7857 /* Test the read-only bits. */
7858 if ((val & read_mask) != read_val)
7859 goto out;
7860
7861 /* Test the read/write bits. */
7862 if ((val & write_mask) != write_mask)
7863 goto out;
7864
7865 tw32(offset, save_val);
7866 }
7867
7868 return 0;
7869
7870out:
7871 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7872 tw32(offset, save_val);
7873 return -EIO;
7874}
7875
7942e1db
MC		 7876static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7877{
7878 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7879 int i;
7880 u32 j;
7881
7882 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7883 for (j = 0; j < len; j += 4) {
7884 u32 val;
7885
7886 tg3_write_mem(tp, offset + j, test_pattern[i]);
7887 tg3_read_mem(tp, offset + j, &val);
7888 if (val != test_pattern[i])
7889 return -EIO;
7890 }
7891 }
7892 return 0;
7893}
7894
7895static int tg3_test_memory(struct tg3 *tp)
7896{
7897 static struct mem_entry {
7898 u32 offset;
7899 u32 len;
7900 } mem_tbl_570x[] = {
7901 { 0x00000000, 0x01000},
7902 { 0x00002000, 0x1c000},
7903 { 0xffffffff, 0x00000}
7904 }, mem_tbl_5705[] = {
7905 { 0x00000100, 0x0000c},
7906 { 0x00000200, 0x00008},
7907 { 0x00000b50, 0x00400},
7908 { 0x00004000, 0x00800},
7909 { 0x00006000, 0x01000},
7910 { 0x00008000, 0x02000},
7911 { 0x00010000, 0x0e000},
7912 { 0xffffffff, 0x00000}
7913 };
7914 struct mem_entry *mem_tbl;
7915 int err = 0;
7916 int i;
7917
7918 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7919 mem_tbl = mem_tbl_5705;
7920 else
7921 mem_tbl = mem_tbl_570x;
7922
7923 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7924 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7925 mem_tbl[i].len)) != 0)
7926 break;
7927 }
7928
7929 return err;
7930}
7931
9f40dead
MC		 7932#define TG3_MAC_LOOPBACK 0
7933#define TG3_PHY_LOOPBACK 1
7934
7935static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 7936{
9f40dead 7937 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 7938 u32 desc_idx;
7939 struct sk_buff *skb, *rx_skb;
7940 u8 *tx_data;
7941 dma_addr_t map;
7942 int num_pkts, tx_len, rx_len, i, err;
7943 struct tg3_rx_buffer_desc *desc;
7944
9f40dead 7945 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 7946 /* HW errata - mac loopback fails in some cases on 5780.
7947 * Normal traffic and PHY loopback are not affected by
7948 * errata.
7949 */
7950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
7951 return 0;
7952
9f40dead
MC		 7953 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7954 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7955 MAC_MODE_PORT_MODE_GMII;
7956 tw32(MAC_MODE, mac_mode);
7957 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
c94e3941
MC		 7958 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
7959 BMCR_SPEED1000);
7960 udelay(40);
7961 /* reset to prevent losing 1st rx packet intermittently */
7962 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7963 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7964 udelay(10);
7965 tw32_f(MAC_RX_MODE, tp->rx_mode);
7966 }
9f40dead
MC		 7967 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7968 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
7969 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
7970 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7971 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 7972 }
7973 else
7974 return -EINVAL;
c76949a6
MC		 7975
7976 err = -EIO;
7977
c76949a6
MC		 7978 tx_len = 1514;
7979 skb = dev_alloc_skb(tx_len);
7980 tx_data = skb_put(skb, tx_len);
7981 memcpy(tx_data, tp->dev->dev_addr, 6);
7982 memset(tx_data + 6, 0x0, 8);
7983
7984 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7985
7986 for (i = 14; i < tx_len; i++)
7987 tx_data[i] = (u8) (i & 0xff);
7988
7989 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7990
7991 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7992 HOSTCC_MODE_NOW);
7993
7994 udelay(10);
7995
7996 rx_start_idx = tp->hw_status->idx[0].rx_producer;
7997
c76949a6
MC		 7998 num_pkts = 0;
7999
9f40dead 8000 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 8001
9f40dead 8002 tp->tx_prod++;
c76949a6
MC		 8003 num_pkts++;
8004
9f40dead
MC		 8005 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8006 tp->tx_prod);
09ee929c 8007 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 8008
8009 udelay(10);
8010
8011 for (i = 0; i < 10; i++) {
8012 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8013 HOSTCC_MODE_NOW);
8014
8015 udelay(10);
8016
8017 tx_idx = tp->hw_status->idx[0].tx_consumer;
8018 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 8019 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 8020 (rx_idx == (rx_start_idx + num_pkts)))
8021 break;
8022 }
8023
8024 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8025 dev_kfree_skb(skb);
8026
9f40dead 8027 if (tx_idx != tp->tx_prod)
c76949a6
MC		 8028 goto out;
8029
8030 if (rx_idx != rx_start_idx + num_pkts)
8031 goto out;
8032
8033 desc = &tp->rx_rcb[rx_start_idx];
8034 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8035 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8036 if (opaque_key != RXD_OPAQUE_RING_STD)
8037 goto out;
8038
8039 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8040 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8041 goto out;
8042
8043 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8044 if (rx_len != tx_len)
8045 goto out;
8046
8047 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8048
8049 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8050 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8051
8052 for (i = 14; i < tx_len; i++) {
8053 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8054 goto out;
8055 }
8056 err = 0;
8057
8058 /* tg3_free_rings will unmap and free the rx_skb */
8059out:
8060 return err;
8061}
8062
9f40dead
MC		 8063#define TG3_MAC_LOOPBACK_FAILED 1
8064#define TG3_PHY_LOOPBACK_FAILED 2
8065#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8066 TG3_PHY_LOOPBACK_FAILED)
8067
8068static int tg3_test_loopback(struct tg3 *tp)
8069{
8070 int err = 0;
8071
8072 if (!netif_running(tp->dev))
8073 return TG3_LOOPBACK_FAILED;
8074
8075 tg3_reset_hw(tp);
8076
8077 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8078 err |= TG3_MAC_LOOPBACK_FAILED;
8079 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8080 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8081 err |= TG3_PHY_LOOPBACK_FAILED;
8082 }
8083
8084 return err;
8085}
8086
4cafd3f5
MC		 8087static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8088 u64 *data)
8089{
566f86ad
MC		 8090 struct tg3 *tp = netdev_priv(dev);
8091
8092 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8093
8094 if (tg3_test_nvram(tp) != 0) {
8095 etest->flags |= ETH_TEST_FL_FAILED;
8096 data[0] = 1;
8097 }
ca43007a
MC		 8098 if (tg3_test_link(tp) != 0) {
8099 etest->flags |= ETH_TEST_FL_FAILED;
8100 data[1] = 1;
8101 }
a71116d1 8102 if (etest->flags & ETH_TEST_FL_OFFLINE) {
bbe832c0
MC		 8103 int irq_sync = 0;
8104
8105 if (netif_running(dev)) {
a71116d1 8106 tg3_netif_stop(tp);
bbe832c0
MC		 8107 irq_sync = 1;
8108 }
a71116d1 8109
bbe832c0 8110 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 8111
8112 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8113 tg3_nvram_lock(tp);
8114 tg3_halt_cpu(tp, RX_CPU_BASE);
8115 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8116 tg3_halt_cpu(tp, TX_CPU_BASE);
8117 tg3_nvram_unlock(tp);
8118
8119 if (tg3_test_registers(tp) != 0) {
8120 etest->flags |= ETH_TEST_FL_FAILED;
8121 data[2] = 1;
8122 }
7942e1db
MC		 8123 if (tg3_test_memory(tp) != 0) {
8124 etest->flags |= ETH_TEST_FL_FAILED;
8125 data[3] = 1;
8126 }
9f40dead 8127 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 8128 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 8129
f47c11ee
DM		 8130 tg3_full_unlock(tp);
8131
d4bc3927
MC		 8132 if (tg3_test_interrupt(tp) != 0) {
8133 etest->flags |= ETH_TEST_FL_FAILED;
8134 data[5] = 1;
8135 }
f47c11ee
DM		 8136
8137 tg3_full_lock(tp, 0);
d4bc3927 8138
a71116d1
MC		 8139 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8140 if (netif_running(dev)) {
8141 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8142 tg3_init_hw(tp);
8143 tg3_netif_start(tp);
8144 }
f47c11ee
DM		 8145
8146 tg3_full_unlock(tp);
a71116d1 8147 }
4cafd3f5
MC		 8148}
8149
1da177e4
LT		 8150static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8151{
8152 struct mii_ioctl_data *data = if_mii(ifr);
8153 struct tg3 *tp = netdev_priv(dev);
8154 int err;
8155
8156 switch(cmd) {
8157 case SIOCGMIIPHY:
8158 data->phy_id = PHY_ADDR;
8159
8160 /* fallthru */
8161 case SIOCGMIIREG: {
8162 u32 mii_regval;
8163
8164 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8165 break; /* We have no PHY */
8166
f47c11ee 8167 spin_lock_bh(&tp->lock);
1da177e4 8168 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 8169 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8170
8171 data->val_out = mii_regval;
8172
8173 return err;
8174 }
8175
8176 case SIOCSMIIREG:
8177 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8178 break; /* We have no PHY */
8179
8180 if (!capable(CAP_NET_ADMIN))
8181 return -EPERM;
8182
f47c11ee 8183 spin_lock_bh(&tp->lock);
1da177e4 8184 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 8185 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8186
8187 return err;
8188
8189 default:
8190 /* do nothing */
8191 break;
8192 }
8193 return -EOPNOTSUPP;
8194}
8195
8196#if TG3_VLAN_TAG_USED
8197static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8198{
8199 struct tg3 *tp = netdev_priv(dev);
8200
f47c11ee 8201 tg3_full_lock(tp, 0);
1da177e4
LT		 8202
8203 tp->vlgrp = grp;
8204
8205 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8206 __tg3_set_rx_mode(dev);
8207
f47c11ee 8208 tg3_full_unlock(tp);
1da177e4
LT		 8209}
8210
8211static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8212{
8213 struct tg3 *tp = netdev_priv(dev);
8214
f47c11ee 8215 tg3_full_lock(tp, 0);
1da177e4
LT		 8216 if (tp->vlgrp)
8217 tp->vlgrp->vlan_devices[vid] = NULL;
f47c11ee 8218 tg3_full_unlock(tp);
1da177e4
LT		 8219}
8220#endif
8221
15f9850d
DM		 8222static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8223{
8224 struct tg3 *tp = netdev_priv(dev);
8225
8226 memcpy(ec, &tp->coal, sizeof(*ec));
8227 return 0;
8228}
8229
d244c892
MC		 8230static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8231{
8232 struct tg3 *tp = netdev_priv(dev);
8233 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8234 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8235
8236 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8237 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8238 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8239 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8240 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8241 }
8242
8243 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8244 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8245 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8246 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8247 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8248 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8249 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8250 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8251 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8252 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8253 return -EINVAL;
8254
8255 /* No rx interrupts will be generated if both are zero */
8256 if ((ec->rx_coalesce_usecs == 0) &&
8257 (ec->rx_max_coalesced_frames == 0))
8258 return -EINVAL;
8259
8260 /* No tx interrupts will be generated if both are zero */
8261 if ((ec->tx_coalesce_usecs == 0) &&
8262 (ec->tx_max_coalesced_frames == 0))
8263 return -EINVAL;
8264
8265 /* Only copy relevant parameters, ignore all others. */
8266 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8267 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8268 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8269 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8270 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8271 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8272 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8273 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8274 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8275
8276 if (netif_running(dev)) {
8277 tg3_full_lock(tp, 0);
8278 __tg3_set_coalesce(tp, &tp->coal);
8279 tg3_full_unlock(tp);
8280 }
8281 return 0;
8282}
8283
1da177e4
LT		 8284static struct ethtool_ops tg3_ethtool_ops = {
8285 .get_settings = tg3_get_settings,
8286 .set_settings = tg3_set_settings,
8287 .get_drvinfo = tg3_get_drvinfo,
8288 .get_regs_len = tg3_get_regs_len,
8289 .get_regs = tg3_get_regs,
8290 .get_wol = tg3_get_wol,
8291 .set_wol = tg3_set_wol,
8292 .get_msglevel = tg3_get_msglevel,
8293 .set_msglevel = tg3_set_msglevel,
8294 .nway_reset = tg3_nway_reset,
8295 .get_link = ethtool_op_get_link,
8296 .get_eeprom_len = tg3_get_eeprom_len,
8297 .get_eeprom = tg3_get_eeprom,
8298 .set_eeprom = tg3_set_eeprom,
8299 .get_ringparam = tg3_get_ringparam,
8300 .set_ringparam = tg3_set_ringparam,
8301 .get_pauseparam = tg3_get_pauseparam,
8302 .set_pauseparam = tg3_set_pauseparam,
8303 .get_rx_csum = tg3_get_rx_csum,
8304 .set_rx_csum = tg3_set_rx_csum,
8305 .get_tx_csum = ethtool_op_get_tx_csum,
8306 .set_tx_csum = tg3_set_tx_csum,
8307 .get_sg = ethtool_op_get_sg,
8308 .set_sg = ethtool_op_set_sg,
8309#if TG3_TSO_SUPPORT != 0
8310 .get_tso = ethtool_op_get_tso,
8311 .set_tso = tg3_set_tso,
8312#endif
4cafd3f5
MC		 8313 .self_test_count = tg3_get_test_count,
8314 .self_test = tg3_self_test,
1da177e4 8315 .get_strings = tg3_get_strings,
4009a93d 8316 .phys_id = tg3_phys_id,
1da177e4
LT		 8317 .get_stats_count = tg3_get_stats_count,
8318 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 8319 .get_coalesce = tg3_get_coalesce,
d244c892 8320 .set_coalesce = tg3_set_coalesce,
2ff43697 8321 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 8322};
8323
8324static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8325{
8326 u32 cursize, val;
8327
8328 tp->nvram_size = EEPROM_CHIP_SIZE;
8329
8330 if (tg3_nvram_read(tp, 0, &val) != 0)
8331 return;
8332
8333 if (swab32(val) != TG3_EEPROM_MAGIC)
8334 return;
8335
8336 /*
8337 * Size the chip by reading offsets at increasing powers of two.
8338 * When we encounter our validation signature, we know the addressing
8339 * has wrapped around, and thus have our chip size.
8340 */
8341 cursize = 0x800;
8342
8343 while (cursize < tp->nvram_size) {
8344 if (tg3_nvram_read(tp, cursize, &val) != 0)
8345 return;
8346
8347 if (swab32(val) == TG3_EEPROM_MAGIC)
8348 break;
8349
8350 cursize <<= 1;
8351 }
8352
8353 tp->nvram_size = cursize;
8354}
8355
8356static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8357{
8358 u32 val;
8359
8360 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8361 if (val != 0) {
8362 tp->nvram_size = (val >> 16) * 1024;
8363 return;
8364 }
8365 }
8366 tp->nvram_size = 0x20000;
8367}
8368
8369static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8370{
8371 u32 nvcfg1;
8372
8373 nvcfg1 = tr32(NVRAM_CFG1);
8374 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8375 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8376 }
8377 else {
8378 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8379 tw32(NVRAM_CFG1, nvcfg1);
8380 }
8381
4c987487
MC		 8382 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8383 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)) {
1da177e4
LT		 8384 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8385 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8386 tp->nvram_jedecnum = JEDEC_ATMEL;
8387 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8388 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8389 break;
8390 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8391 tp->nvram_jedecnum = JEDEC_ATMEL;
8392 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8393 break;
8394 case FLASH_VENDOR_ATMEL_EEPROM:
8395 tp->nvram_jedecnum = JEDEC_ATMEL;
8396 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8397 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8398 break;
8399 case FLASH_VENDOR_ST:
8400 tp->nvram_jedecnum = JEDEC_ST;
8401 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8402 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8403 break;
8404 case FLASH_VENDOR_SAIFUN:
8405 tp->nvram_jedecnum = JEDEC_SAIFUN;
8406 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8407 break;
8408 case FLASH_VENDOR_SST_SMALL:
8409 case FLASH_VENDOR_SST_LARGE:
8410 tp->nvram_jedecnum = JEDEC_SST;
8411 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8412 break;
8413 }
8414 }
8415 else {
8416 tp->nvram_jedecnum = JEDEC_ATMEL;
8417 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8418 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8419 }
8420}
8421
361b4ac2
MC		 8422static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8423{
8424 u32 nvcfg1;
8425
8426 nvcfg1 = tr32(NVRAM_CFG1);
8427
e6af301b
MC		 8428 /* NVRAM protection for TPM */
8429 if (nvcfg1 & (1 << 27))
8430 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8431
361b4ac2
MC		 8432 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8433 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8434 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8435 tp->nvram_jedecnum = JEDEC_ATMEL;
8436 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8437 break;
8438 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8439 tp->nvram_jedecnum = JEDEC_ATMEL;
8440 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8441 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8442 break;
8443 case FLASH_5752VENDOR_ST_M45PE10:
8444 case FLASH_5752VENDOR_ST_M45PE20:
8445 case FLASH_5752VENDOR_ST_M45PE40:
8446 tp->nvram_jedecnum = JEDEC_ST;
8447 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8448 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8449 break;
8450 }
8451
8452 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8453 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8454 case FLASH_5752PAGE_SIZE_256:
8455 tp->nvram_pagesize = 256;
8456 break;
8457 case FLASH_5752PAGE_SIZE_512:
8458 tp->nvram_pagesize = 512;
8459 break;
8460 case FLASH_5752PAGE_SIZE_1K:
8461 tp->nvram_pagesize = 1024;
8462 break;
8463 case FLASH_5752PAGE_SIZE_2K:
8464 tp->nvram_pagesize = 2048;
8465 break;
8466 case FLASH_5752PAGE_SIZE_4K:
8467 tp->nvram_pagesize = 4096;
8468 break;
8469 case FLASH_5752PAGE_SIZE_264:
8470 tp->nvram_pagesize = 264;
8471 break;
8472 }
8473 }
8474 else {
8475 /* For eeprom, set pagesize to maximum eeprom size */
8476 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8477
8478 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8479 tw32(NVRAM_CFG1, nvcfg1);
8480 }
8481}
8482
1da177e4
LT		 8483/* Chips other than 5700/5701 use the NVRAM for fetching info. */
8484static void __devinit tg3_nvram_init(struct tg3 *tp)
8485{
8486 int j;
8487
8488 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8489 return;
8490
8491 tw32_f(GRC_EEPROM_ADDR,
8492 (EEPROM_ADDR_FSM_RESET |
8493 (EEPROM_DEFAULT_CLOCK_PERIOD <<
8494 EEPROM_ADDR_CLKPERD_SHIFT)));
8495
8496 /* XXX schedule_timeout() ... */
8497 for (j = 0; j < 100; j++)
8498 udelay(10);
8499
8500 /* Enable seeprom accesses. */
8501 tw32_f(GRC_LOCAL_CTRL,
8502 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8503 udelay(100);
8504
8505 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8506 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8507 tp->tg3_flags |= TG3_FLAG_NVRAM;
8508
e6af301b 8509 tg3_enable_nvram_access(tp);
1da177e4 8510
361b4ac2
MC		 8511 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8512 tg3_get_5752_nvram_info(tp);
8513 else
8514 tg3_get_nvram_info(tp);
8515
1da177e4
LT		 8516 tg3_get_nvram_size(tp);
8517
e6af301b 8518 tg3_disable_nvram_access(tp);
1da177e4
LT		 8519
8520 } else {
8521 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8522
8523 tg3_get_eeprom_size(tp);
8524 }
8525}
8526
8527static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8528 u32 offset, u32 *val)
8529{
8530 u32 tmp;
8531 int i;
8532
8533 if (offset > EEPROM_ADDR_ADDR_MASK ||
8534 (offset % 4) != 0)
8535 return -EINVAL;
8536
8537 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8538 EEPROM_ADDR_DEVID_MASK |
8539 EEPROM_ADDR_READ);
8540 tw32(GRC_EEPROM_ADDR,
8541 tmp |
8542 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8543 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8544 EEPROM_ADDR_ADDR_MASK) |
8545 EEPROM_ADDR_READ | EEPROM_ADDR_START);
8546
8547 for (i = 0; i < 10000; i++) {
8548 tmp = tr32(GRC_EEPROM_ADDR);
8549
8550 if (tmp & EEPROM_ADDR_COMPLETE)
8551 break;
8552 udelay(100);
8553 }
8554 if (!(tmp & EEPROM_ADDR_COMPLETE))
8555 return -EBUSY;
8556
8557 *val = tr32(GRC_EEPROM_DATA);
8558 return 0;
8559}
8560
8561#define NVRAM_CMD_TIMEOUT 10000
8562
8563static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8564{
8565 int i;
8566
8567 tw32(NVRAM_CMD, nvram_cmd);
8568 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8569 udelay(10);
8570 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8571 udelay(10);
8572 break;
8573 }
8574 }
8575 if (i == NVRAM_CMD_TIMEOUT) {
8576 return -EBUSY;
8577 }
8578 return 0;
8579}
8580
8581static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8582{
8583 int ret;
8584
8585 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8586 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8587 return -EINVAL;
8588 }
8589
8590 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8591 return tg3_nvram_read_using_eeprom(tp, offset, val);
8592
8593 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8594 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8595 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8596
8597 offset = ((offset / tp->nvram_pagesize) <<
8598 ATMEL_AT45DB0X1B_PAGE_POS) +
8599 (offset % tp->nvram_pagesize);
8600 }
8601
8602 if (offset > NVRAM_ADDR_MSK)
8603 return -EINVAL;
8604
8605 tg3_nvram_lock(tp);
8606
e6af301b 8607 tg3_enable_nvram_access(tp);
1da177e4
LT		 8608
8609 tw32(NVRAM_ADDR, offset);
8610 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8611 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8612
8613 if (ret == 0)
8614 *val = swab32(tr32(NVRAM_RDDATA));
8615
8616 tg3_nvram_unlock(tp);
8617
e6af301b 8618 tg3_disable_nvram_access(tp);
1da177e4
LT		 8619
8620 return ret;
8621}
8622
8623static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8624 u32 offset, u32 len, u8 *buf)
8625{
8626 int i, j, rc = 0;
8627 u32 val;
8628
8629 for (i = 0; i < len; i += 4) {
8630 u32 addr, data;
8631
8632 addr = offset + i;
8633
8634 memcpy(&data, buf + i, 4);
8635
8636 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8637
8638 val = tr32(GRC_EEPROM_ADDR);
8639 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8640
8641 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8642 EEPROM_ADDR_READ);
8643 tw32(GRC_EEPROM_ADDR, val |
8644 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8645 (addr & EEPROM_ADDR_ADDR_MASK) |
8646 EEPROM_ADDR_START |
8647 EEPROM_ADDR_WRITE);
8648
8649 for (j = 0; j < 10000; j++) {
8650 val = tr32(GRC_EEPROM_ADDR);
8651
8652 if (val & EEPROM_ADDR_COMPLETE)
8653 break;
8654 udelay(100);
8655 }
8656 if (!(val & EEPROM_ADDR_COMPLETE)) {
8657 rc = -EBUSY;
8658 break;
8659 }
8660 }
8661
8662 return rc;
8663}
8664
8665/* offset and length are dword aligned */
8666static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8667 u8 *buf)
8668{
8669 int ret = 0;
8670 u32 pagesize = tp->nvram_pagesize;
8671 u32 pagemask = pagesize - 1;
8672 u32 nvram_cmd;
8673 u8 *tmp;
8674
8675 tmp = kmalloc(pagesize, GFP_KERNEL);
8676 if (tmp == NULL)
8677 return -ENOMEM;
8678
8679 while (len) {
8680 int j;
e6af301b 8681 u32 phy_addr, page_off, size;
1da177e4
LT		 8682
8683 phy_addr = offset & ~pagemask;
8684
8685 for (j = 0; j < pagesize; j += 4) {
8686 if ((ret = tg3_nvram_read(tp, phy_addr + j,
8687 (u32 *) (tmp + j))))
8688 break;
8689 }
8690 if (ret)
8691 break;
8692
8693 page_off = offset & pagemask;
8694 size = pagesize;
8695 if (len < size)
8696 size = len;
8697
8698 len -= size;
8699
8700 memcpy(tmp + page_off, buf, size);
8701
8702 offset = offset + (pagesize - page_off);
8703
e6af301b 8704 tg3_enable_nvram_access(tp);
1da177e4
LT		 8705
8706 /*
8707 * Before we can erase the flash page, we need
8708 * to issue a special "write enable" command.
8709 */
8710 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8711
8712 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8713 break;
8714
8715 /* Erase the target page */
8716 tw32(NVRAM_ADDR, phy_addr);
8717
8718 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8719 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8720
8721 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8722 break;
8723
8724 /* Issue another write enable to start the write. */
8725 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8726
8727 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8728 break;
8729
8730 for (j = 0; j < pagesize; j += 4) {
8731 u32 data;
8732
8733 data = *((u32 *) (tmp + j));
8734 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8735
8736 tw32(NVRAM_ADDR, phy_addr + j);
8737
8738 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8739 NVRAM_CMD_WR;
8740
8741 if (j == 0)
8742 nvram_cmd |= NVRAM_CMD_FIRST;
8743 else if (j == (pagesize - 4))
8744 nvram_cmd |= NVRAM_CMD_LAST;
8745
8746 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8747 break;
8748 }
8749 if (ret)
8750 break;
8751 }
8752
8753 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8754 tg3_nvram_exec_cmd(tp, nvram_cmd);
8755
8756 kfree(tmp);
8757
8758 return ret;
8759}
8760
8761/* offset and length are dword aligned */
8762static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8763 u8 *buf)
8764{
8765 int i, ret = 0;
8766
8767 for (i = 0; i < len; i += 4, offset += 4) {
8768 u32 data, page_off, phy_addr, nvram_cmd;
8769
8770 memcpy(&data, buf + i, 4);
8771 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8772
8773 page_off = offset % tp->nvram_pagesize;
8774
8775 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8776 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8777
8778 phy_addr = ((offset / tp->nvram_pagesize) <<
8779 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8780 }
8781 else {
8782 phy_addr = offset;
8783 }
8784
8785 tw32(NVRAM_ADDR, phy_addr);
8786
8787 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8788
8789 if ((page_off == 0) || (i == 0))
8790 nvram_cmd |= NVRAM_CMD_FIRST;
8791 else if (page_off == (tp->nvram_pagesize - 4))
8792 nvram_cmd |= NVRAM_CMD_LAST;
8793
8794 if (i == (len - 4))
8795 nvram_cmd |= NVRAM_CMD_LAST;
8796
4c987487
MC		 8797 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
8798 (tp->nvram_jedecnum == JEDEC_ST) &&
8799 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 8800
8801 if ((ret = tg3_nvram_exec_cmd(tp,
8802 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8803 NVRAM_CMD_DONE)))
8804
8805 break;
8806 }
8807 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8808 /* We always do complete word writes to eeprom. */
8809 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8810 }
8811
8812 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8813 break;
8814 }
8815 return ret;
8816}
8817
8818/* offset and length are dword aligned */
8819static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8820{
8821 int ret;
8822
8823 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8824 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8825 return -EINVAL;
8826 }
8827
8828 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 8829 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8830 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 8831 udelay(40);
8832 }
8833
8834 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8835 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8836 }
8837 else {
8838 u32 grc_mode;
8839
8840 tg3_nvram_lock(tp);
8841
e6af301b
MC		 8842 tg3_enable_nvram_access(tp);
8843 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8844 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 8845 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 8846
8847 grc_mode = tr32(GRC_MODE);
8848 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8849
8850 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8851 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8852
8853 ret = tg3_nvram_write_block_buffered(tp, offset, len,
8854 buf);
8855 }
8856 else {
8857 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8858 buf);
8859 }
8860
8861 grc_mode = tr32(GRC_MODE);
8862 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8863
e6af301b 8864 tg3_disable_nvram_access(tp);
1da177e4
LT		 8865 tg3_nvram_unlock(tp);
8866 }
8867
8868 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 8869 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 8870 udelay(40);
8871 }
8872
8873 return ret;
8874}
8875
8876struct subsys_tbl_ent {
8877 u16 subsys_vendor, subsys_devid;
8878 u32 phy_id;
8879};
8880
8881static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8882 /* Broadcom boards. */
8883 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8884 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8885 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8886 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
8887 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8888 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8889 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
8890 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8891 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8892 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8893 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8894
8895 /* 3com boards. */
8896 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8897 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8898 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
8899 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8900 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8901
8902 /* DELL boards. */
8903 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8904 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8905 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8906 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8907
8908 /* Compaq boards. */
8909 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8910 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8911 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
8912 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8913 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8914
8915 /* IBM boards. */
8916 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8917};
8918
8919static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8920{
8921 int i;
8922
8923 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8924 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8925 tp->pdev->subsystem_vendor) &&
8926 (subsys_id_to_phy_id[i].subsys_devid ==
8927 tp->pdev->subsystem_device))
8928 return &subsys_id_to_phy_id[i];
8929 }
8930 return NULL;
8931}
8932
7d0c41ef
MC		 8933/* Since this function may be called in D3-hot power state during
8934 * tg3_init_one(), only config cycles are allowed.
8935 */
8936static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 8937{
1da177e4 8938 u32 val;
7d0c41ef
MC		 8939
8940 /* Make sure register accesses (indirect or otherwise)
8941 * will function correctly.
8942 */
8943 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8944 tp->misc_host_ctrl);
1da177e4
LT		 8945
8946 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 8947 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8948
1da177e4
LT		 8949 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8950 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8951 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 8952 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8953 int eeprom_phy_serdes = 0;
1da177e4
LT		 8954
8955 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8956 tp->nic_sram_data_cfg = nic_cfg;
8957
8958 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8959 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8960 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8961 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8962 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8963 (ver > 0) && (ver < 0x100))
8964 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8965
1da177e4
LT		 8966 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8967 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8968 eeprom_phy_serdes = 1;
8969
8970 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8971 if (nic_phy_id != 0) {
8972 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8973 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8974
8975 eeprom_phy_id = (id1 >> 16) << 10;
8976 eeprom_phy_id |= (id2 & 0xfc00) << 16;
8977 eeprom_phy_id |= (id2 & 0x03ff) << 0;
8978 } else
8979 eeprom_phy_id = 0;
8980
7d0c41ef 8981 tp->phy_id = eeprom_phy_id;
747e8f8b
MC		 8982 if (eeprom_phy_serdes) {
8983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8984 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
8985 else
8986 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8987 }
7d0c41ef 8988
cbf46853 8989 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8990 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8991 SHASTA_EXT_LED_MODE_MASK);
cbf46853 8992 else
1da177e4
LT		 8993 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8994
8995 switch (led_cfg) {
8996 default:
8997 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8998 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8999 break;
9000
9001 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9002 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9003 break;
9004
9005 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9006 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 9007
9008 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9009 * read on some older 5700/5701 bootcode.
9010 */
9011 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9012 ASIC_REV_5700 ||
9013 GET_ASIC_REV(tp->pci_chip_rev_id) ==
9014 ASIC_REV_5701)
9015 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9016
1da177e4
LT		 9017 break;
9018
9019 case SHASTA_EXT_LED_SHARED:
9020 tp->led_ctrl = LED_CTRL_MODE_SHARED;
9021 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9022 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9023 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9024 LED_CTRL_MODE_PHY_2);
9025 break;
9026
9027 case SHASTA_EXT_LED_MAC:
9028 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9029 break;
9030
9031 case SHASTA_EXT_LED_COMBO:
9032 tp->led_ctrl = LED_CTRL_MODE_COMBO;
9033 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9034 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9035 LED_CTRL_MODE_PHY_2);
9036 break;
9037
9038 };
9039
9040 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9042 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9043 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9044
9045 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9046 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9047 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
9048 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9049
9050 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9051 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 9052 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9053 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9054 }
9055 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9056 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9057
9058 if (cfg2 & (1 << 17))
9059 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9060
9061 /* serdes signal pre-emphasis in register 0x590 set by */
9062 /* bootcode if bit 18 is set */
9063 if (cfg2 & (1 << 18))
9064 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9065 }
7d0c41ef
MC		 9066}
9067
9068static int __devinit tg3_phy_probe(struct tg3 *tp)
9069{
9070 u32 hw_phy_id_1, hw_phy_id_2;
9071 u32 hw_phy_id, hw_phy_id_masked;
9072 int err;
1da177e4
LT		 9073
9074 /* Reading the PHY ID register can conflict with ASF
9075 * firwmare access to the PHY hardware.
9076 */
9077 err = 0;
9078 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9079 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9080 } else {
9081 /* Now read the physical PHY_ID from the chip and verify
9082 * that it is sane. If it doesn't look good, we fall back
9083 * to either the hard-coded table based PHY_ID and failing
9084 * that the value found in the eeprom area.
9085 */
9086 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9087 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9088
9089 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
9090 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9091 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
9092
9093 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9094 }
9095
9096 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9097 tp->phy_id = hw_phy_id;
9098 if (hw_phy_id_masked == PHY_ID_BCM8002)
9099 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 9100 else
9101 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 9102 } else {
7d0c41ef
MC		 9103 if (tp->phy_id != PHY_ID_INVALID) {
9104 /* Do nothing, phy ID already set up in
9105 * tg3_get_eeprom_hw_cfg().
9106 */
1da177e4
LT		 9107 } else {
9108 struct subsys_tbl_ent *p;
9109
9110 /* No eeprom signature? Try the hardcoded
9111 * subsys device table.
9112 */
9113 p = lookup_by_subsys(tp);
9114 if (!p)
9115 return -ENODEV;
9116
9117 tp->phy_id = p->phy_id;
9118 if (!tp->phy_id ||
9119 tp->phy_id == PHY_ID_BCM8002)
9120 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9121 }
9122 }
9123
747e8f8b 9124 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4
LT		 9125 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9126 u32 bmsr, adv_reg, tg3_ctrl;
9127
9128 tg3_readphy(tp, MII_BMSR, &bmsr);
9129 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9130 (bmsr & BMSR_LSTATUS))
9131 goto skip_phy_reset;
9132
9133 err = tg3_phy_reset(tp);
9134 if (err)
9135 return err;
9136
9137 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9138 ADVERTISE_100HALF | ADVERTISE_100FULL |
9139 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9140 tg3_ctrl = 0;
9141 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9142 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9143 MII_TG3_CTRL_ADV_1000_FULL);
9144 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9145 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9146 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9147 MII_TG3_CTRL_ENABLE_AS_MASTER);
9148 }
9149
9150 if (!tg3_copper_is_advertising_all(tp)) {
9151 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9152
9153 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9154 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9155
9156 tg3_writephy(tp, MII_BMCR,
9157 BMCR_ANENABLE | BMCR_ANRESTART);
9158 }
9159 tg3_phy_set_wirespeed(tp);
9160
9161 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9162 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9163 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9164 }
9165
9166skip_phy_reset:
9167 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9168 err = tg3_init_5401phy_dsp(tp);
9169 if (err)
9170 return err;
9171 }
9172
9173 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9174 err = tg3_init_5401phy_dsp(tp);
9175 }
9176
747e8f8b 9177 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 9178 tp->link_config.advertising =
9179 (ADVERTISED_1000baseT_Half |
9180 ADVERTISED_1000baseT_Full |
9181 ADVERTISED_Autoneg |
9182 ADVERTISED_FIBRE);
9183 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9184 tp->link_config.advertising &=
9185 ~(ADVERTISED_1000baseT_Half |
9186 ADVERTISED_1000baseT_Full);
9187
9188 return err;
9189}
9190
9191static void __devinit tg3_read_partno(struct tg3 *tp)
9192{
9193 unsigned char vpd_data[256];
9194 int i;
9195
9196 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9197 /* Sun decided not to put the necessary bits in the
9198 * NVRAM of their onboard tg3 parts :(
9199 */
9200 strcpy(tp->board_part_number, "Sun 570X");
9201 return;
9202 }
9203
9204 for (i = 0; i < 256; i += 4) {
9205 u32 tmp;
9206
9207 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9208 goto out_not_found;
9209
9210 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9211 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9212 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9213 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9214 }
9215
9216 /* Now parse and find the part number. */
9217 for (i = 0; i < 256; ) {
9218 unsigned char val = vpd_data[i];
9219 int block_end;
9220
9221 if (val == 0x82 || val == 0x91) {
9222 i = (i + 3 +
9223 (vpd_data[i + 1] +
9224 (vpd_data[i + 2] << 8)));
9225 continue;
9226 }
9227
9228 if (val != 0x90)
9229 goto out_not_found;
9230
9231 block_end = (i + 3 +
9232 (vpd_data[i + 1] +
9233 (vpd_data[i + 2] << 8)));
9234 i += 3;
9235 while (i < block_end) {
9236 if (vpd_data[i + 0] == 'P' &&
9237 vpd_data[i + 1] == 'N') {
9238 int partno_len = vpd_data[i + 2];
9239
9240 if (partno_len > 24)
9241 goto out_not_found;
9242
9243 memcpy(tp->board_part_number,
9244 &vpd_data[i + 3],
9245 partno_len);
9246
9247 /* Success. */
9248 return;
9249 }
9250 }
9251
9252 /* Part number not found. */
9253 goto out_not_found;
9254 }
9255
9256out_not_found:
9257 strcpy(tp->board_part_number, "none");
9258}
9259
9260#ifdef CONFIG_SPARC64
9261static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9262{
9263 struct pci_dev *pdev = tp->pdev;
9264 struct pcidev_cookie *pcp = pdev->sysdata;
9265
9266 if (pcp != NULL) {
9267 int node = pcp->prom_node;
9268 u32 venid;
9269 int err;
9270
9271 err = prom_getproperty(node, "subsystem-vendor-id",
9272 (char *) &venid, sizeof(venid));
9273 if (err == 0 || err == -1)
9274 return 0;
9275 if (venid == PCI_VENDOR_ID_SUN)
9276 return 1;
9277 }
9278 return 0;
9279}
9280#endif
9281
9282static int __devinit tg3_get_invariants(struct tg3 *tp)
9283{
9284 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 9285 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9286 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
1cbf0747
DM		 9287 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9288 PCI_DEVICE_ID_AMD_K8_NB) },
1da177e4
LT		 9289 { },
9290 };
9291 u32 misc_ctrl_reg;
9292 u32 cacheline_sz_reg;
9293 u32 pci_state_reg, grc_misc_cfg;
9294 u32 val;
9295 u16 pci_cmd;
9296 int err;
9297
9298#ifdef CONFIG_SPARC64
9299 if (tg3_is_sun_570X(tp))
9300 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9301#endif
9302
1cbf0747 9303 /* If we have an AMD 762 or K8 chipset, write
1da177e4
LT		 9304 * reordering to the mailbox registers done by the host
9305 * controller can cause major troubles. We read back from
9306 * every mailbox register write to force the writes to be
9307 * posted to the chip in order.
9308 */
9309 if (pci_dev_present(write_reorder_chipsets))
9310 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9311
9312 /* Force memory write invalidate off. If we leave it on,
9313 * then on 5700_BX chips we have to enable a workaround.
9314 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9315 * to match the cacheline size. The Broadcom driver have this
9316 * workaround but turns MWI off all the times so never uses
9317 * it. This seems to suggest that the workaround is insufficient.
9318 */
9319 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9320 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9321 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9322
9323 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9324 * has the register indirect write enable bit set before
9325 * we try to access any of the MMIO registers. It is also
9326 * critical that the PCI-X hw workaround situation is decided
9327 * before that as well.
9328 */
9329 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9330 &misc_ctrl_reg);
9331
9332 tp->pci_chip_rev_id = (misc_ctrl_reg >>
9333 MISC_HOST_CTRL_CHIPREV_SHIFT);
9334
ff645bec
MC		 9335 /* Wrong chip ID in 5752 A0. This code can be removed later
9336 * as A0 is not in production.
9337 */
9338 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
9339 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
9340
6892914f
MC		 9341 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
9342 * we need to disable memory and use config. cycles
9343 * only to access all registers. The 5702/03 chips
9344 * can mistakenly decode the special cycles from the
9345 * ICH chipsets as memory write cycles, causing corruption
9346 * of register and memory space. Only certain ICH bridges
9347 * will drive special cycles with non-zero data during the
9348 * address phase which can fall within the 5703's address
9349 * range. This is not an ICH bug as the PCI spec allows
9350 * non-zero address during special cycles. However, only
9351 * these ICH bridges are known to drive non-zero addresses
9352 * during special cycles.
9353 *
9354 * Since special cycles do not cross PCI bridges, we only
9355 * enable this workaround if the 5703 is on the secondary
9356 * bus of these ICH bridges.
9357 */
9358 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
9359 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
9360 static struct tg3_dev_id {
9361 u32 vendor;
9362 u32 device;
9363 u32 rev;
9364 } ich_chipsets[] = {
9365 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
9366 PCI_ANY_ID },
9367 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
9368 PCI_ANY_ID },
9369 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
9370 0xa },
9371 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
9372 PCI_ANY_ID },
9373 { },
9374 };
9375 struct tg3_dev_id *pci_id = &ich_chipsets[0];
9376 struct pci_dev *bridge = NULL;
9377
9378 while (pci_id->vendor != 0) {
9379 bridge = pci_get_device(pci_id->vendor, pci_id->device,
9380 bridge);
9381 if (!bridge) {
9382 pci_id++;
9383 continue;
9384 }
9385 if (pci_id->rev != PCI_ANY_ID) {
9386 u8 rev;
9387
9388 pci_read_config_byte(bridge, PCI_REVISION_ID,
9389 &rev);
9390 if (rev > pci_id->rev)
9391 continue;
9392 }
9393 if (bridge->subordinate &&
9394 (bridge->subordinate->number ==
9395 tp->pdev->bus->number)) {
9396
9397 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
9398 pci_dev_put(bridge);
9399 break;
9400 }
9401 }
9402 }
9403
4cf78e4f
MC		 9404 /* Find msi capability. */
9405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9406 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
9407
1da177e4
LT		 9408 /* Initialize misc host control in PCI block. */
9409 tp->misc_host_ctrl |= (misc_ctrl_reg &
9410 MISC_HOST_CTRL_CHIPREV);
9411 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9412 tp->misc_host_ctrl);
9413
9414 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9415 &cacheline_sz_reg);
9416
9417 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
9418 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
9419 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
9420 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
9421
6708e5cc 9422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f
MC		 9423 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
9424 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
6708e5cc
JL		 9425 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
9426
1b440c56
JL		 9427 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9428 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9429 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9430
bb7064dc 9431 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9432 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9433
0f893dc6
MC		 9434 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9435 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9436 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9437 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9438
1da177e4
LT		 9439 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9440 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9441
9442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9443 tp->pci_lat_timer < 64) {
9444 tp->pci_lat_timer = 64;
9445
9446 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
9447 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
9448 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
9449 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
9450
9451 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9452 cacheline_sz_reg);
9453 }
9454
9455 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9456 &pci_state_reg);
9457
9458 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9459 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9460
9461 /* If this is a 5700 BX chipset, and we are in PCI-X
9462 * mode, enable register write workaround.
9463 *
9464 * The workaround is to use indirect register accesses
9465 * for all chip writes not to mailbox registers.
9466 */
9467 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9468 u32 pm_reg;
9469 u16 pci_cmd;
9470
9471 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9472
9473 /* The chip can have it's power management PCI config
9474 * space registers clobbered due to this bug.
9475 * So explicitly force the chip into D0 here.
9476 */
9477 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9478 &pm_reg);
9479 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9480 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9481 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9482 pm_reg);
9483
9484 /* Also, force SERR#/PERR# in PCI command. */
9485 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9486 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9487 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9488 }
9489 }
9490
087fe256
MC		 9491 /* 5700 BX chips need to have their TX producer index mailboxes
9492 * written twice to workaround a bug.
9493 */
9494 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9495 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9496
1da177e4
LT		 9497 /* Back to back register writes can cause problems on this chip,
9498 * the workaround is to read back all reg writes except those to
9499 * mailbox regs. See tg3_write_indirect_reg32().
9500 *
9501 * PCI Express 5750_A0 rev chips need this workaround too.
9502 */
9503 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9504 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9505 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9506 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9507
9508 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9509 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9510 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9511 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9512
9513 /* Chip-specific fixup from Broadcom driver */
9514 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9515 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9516 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9517 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9518 }
9519
1ee582d8 9520 /* Default fast path register access methods */
20094930 9521 tp->read32 = tg3_read32;
1ee582d8 9522 tp->write32 = tg3_write32;
09ee929c 9523 tp->read32_mbox = tg3_read32;
20094930 9524 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 9525 tp->write32_tx_mbox = tg3_write32;
9526 tp->write32_rx_mbox = tg3_write32;
9527
9528 /* Various workaround register access methods */
9529 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
9530 tp->write32 = tg3_write_indirect_reg32;
9531 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
9532 tp->write32 = tg3_write_flush_reg32;
9533
9534 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
9535 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
9536 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9537 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
9538 tp->write32_rx_mbox = tg3_write_flush_reg32;
9539 }
20094930 9540
6892914f
MC		 9541 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
9542 tp->read32 = tg3_read_indirect_reg32;
9543 tp->write32 = tg3_write_indirect_reg32;
9544 tp->read32_mbox = tg3_read_indirect_mbox;
9545 tp->write32_mbox = tg3_write_indirect_mbox;
9546 tp->write32_tx_mbox = tg3_write_indirect_mbox;
9547 tp->write32_rx_mbox = tg3_write_indirect_mbox;
9548
9549 iounmap(tp->regs);
22abe310 9550 tp->regs = NULL;
6892914f
MC		 9551
9552 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9553 pci_cmd &= ~PCI_COMMAND_MEMORY;
9554 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9555 }
9556
7d0c41ef
MC		 9557 /* Get eeprom hw config before calling tg3_set_power_state().
9558 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9559 * determined before calling tg3_set_power_state() so that
9560 * we know whether or not to switch out of Vaux power.
9561 * When the flag is set, it means that GPIO1 is used for eeprom
9562 * write protect and also implies that it is a LOM where GPIOs
9563 * are not used to switch power.
9564 */
9565 tg3_get_eeprom_hw_cfg(tp);
9566
314fba34
MC		 9567 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9568 * GPIO1 driven high will bring 5700's external PHY out of reset.
9569 * It is also used as eeprom write protect on LOMs.
9570 */
9571 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9572 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9573 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9574 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9575 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 9576 /* Unused GPIO3 must be driven as output on 5752 because there
9577 * are no pull-up resistors on unused GPIO pins.
9578 */
9579 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9580 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 9581
1da177e4
LT		 9582 /* Force the chip into D0. */
9583 err = tg3_set_power_state(tp, 0);
9584 if (err) {
9585 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9586 pci_name(tp->pdev));
9587 return err;
9588 }
9589
9590 /* 5700 B0 chips do not support checksumming correctly due
9591 * to hardware bugs.
9592 */
9593 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9594 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9595
9596 /* Pseudo-header checksum is done by hardware logic and not
9597 * the offload processers, so make the chip do the pseudo-
9598 * header checksums on receive. For transmit it is more
9599 * convenient to do the pseudo-header checksum in software
9600 * as Linux does that on transmit for us in all cases.
9601 */
9602 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9603 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9604
9605 /* Derive initial jumbo mode from MTU assigned in
9606 * ether_setup() via the alloc_etherdev() call
9607 */
0f893dc6
MC		 9608 if (tp->dev->mtu > ETH_DATA_LEN &&
9609 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)
9610 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 9611
9612 /* Determine WakeOnLan speed to use. */
9613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9614 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9615 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9616 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9617 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9618 } else {
9619 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9620 }
9621
9622 /* A few boards don't want Ethernet@WireSpeed phy feature */
9623 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9624 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9625 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b
MC		 9626 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9627 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 9628 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9629
9630 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9631 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9632 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9633 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9634 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9635
bb7064dc 9636 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
1da177e4
LT		 9637 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9638
1da177e4 9639 tp->coalesce_mode = 0;
1da177e4
LT		 9640 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9641 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9642 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9643
9644 /* Initialize MAC MI mode, polling disabled. */
9645 tw32_f(MAC_MI_MODE, tp->mi_mode);
9646 udelay(80);
9647
9648 /* Initialize data/descriptor byte/word swapping. */
9649 val = tr32(GRC_MODE);
9650 val &= GRC_MODE_HOST_STACKUP;
9651 tw32(GRC_MODE, val | tp->grc_mode);
9652
9653 tg3_switch_clocks(tp);
9654
9655 /* Clear this out for sanity. */
9656 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9657
9658 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9659 &pci_state_reg);
9660 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9661 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9662 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9663
9664 if (chiprevid == CHIPREV_ID_5701_A0 ||
9665 chiprevid == CHIPREV_ID_5701_B0 ||
9666 chiprevid == CHIPREV_ID_5701_B2 ||
9667 chiprevid == CHIPREV_ID_5701_B5) {
9668 void __iomem *sram_base;
9669
9670 /* Write some dummy words into the SRAM status block
9671 * area, see if it reads back correctly. If the return
9672 * value is bad, force enable the PCIX workaround.
9673 */
9674 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9675
9676 writel(0x00000000, sram_base);
9677 writel(0x00000000, sram_base + 4);
9678 writel(0xffffffff, sram_base + 4);
9679 if (readl(sram_base) != 0x00000000)
9680 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9681 }
9682 }
9683
9684 udelay(50);
9685 tg3_nvram_init(tp);
9686
9687 grc_misc_cfg = tr32(GRC_MISC_CFG);
9688 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9689
9690 /* Broadcom's driver says that CIOBE multisplit has a bug */
9691#if 0
9692 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9693 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9694 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9695 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9696 }
9697#endif
9698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9699 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9700 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9701 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9702
fac9b83e
DM		 9703 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9704 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9705 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9706 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9707 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9708 HOSTCC_MODE_CLRTICK_TXBD);
9709
9710 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9711 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9712 tp->misc_host_ctrl);
9713 }
9714
1da177e4
LT		 9715 /* these are limited to 10/100 only */
9716 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9717 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9718 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9719 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9720 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9721 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9722 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9723 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9724 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9725 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9726 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9727
9728 err = tg3_phy_probe(tp);
9729 if (err) {
9730 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9731 pci_name(tp->pdev), err);
9732 /* ... but do not return immediately ... */
9733 }
9734
9735 tg3_read_partno(tp);
9736
9737 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9738 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9739 } else {
9740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9741 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9742 else
9743 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9744 }
9745
9746 /* 5700 {AX,BX} chips have a broken status block link
9747 * change bit implementation, so we must use the
9748 * status register in those cases.
9749 */
9750 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9751 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9752 else
9753 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9754
9755 /* The led_ctrl is set during tg3_phy_probe, here we might
9756 * have to force the link status polling mechanism based
9757 * upon subsystem IDs.
9758 */
9759 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9760 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9761 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9762 TG3_FLAG_USE_LINKCHG_REG);
9763 }
9764
9765 /* For all SERDES we poll the MAC status register. */
9766 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9767 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9768 else
9769 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9770
1da177e4
LT		 9771 /* It seems all chips can get confused if TX buffers
9772 * straddle the 4GB address boundary in some cases.
9773 */
9774 tp->dev->hard_start_xmit = tg3_start_xmit;
9775
9776 tp->rx_offset = 2;
9777 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9778 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9779 tp->rx_offset = 0;
9780
9781 /* By default, disable wake-on-lan. User can change this
9782 * using ETHTOOL_SWOL.
9783 */
9784 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9785
9786 return err;
9787}
9788
9789#ifdef CONFIG_SPARC64
9790static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9791{
9792 struct net_device *dev = tp->dev;
9793 struct pci_dev *pdev = tp->pdev;
9794 struct pcidev_cookie *pcp = pdev->sysdata;
9795
9796 if (pcp != NULL) {
9797 int node = pcp->prom_node;
9798
9799 if (prom_getproplen(node, "local-mac-address") == 6) {
9800 prom_getproperty(node, "local-mac-address",
9801 dev->dev_addr, 6);
2ff43697 9802 memcpy(dev->perm_addr, dev->dev_addr, 6);
1da177e4
LT		 9803 return 0;
9804 }
9805 }
9806 return -ENODEV;
9807}
9808
9809static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9810{
9811 struct net_device *dev = tp->dev;
9812
9813 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 9814 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 9815 return 0;
9816}
9817#endif
9818
9819static int __devinit tg3_get_device_address(struct tg3 *tp)
9820{
9821 struct net_device *dev = tp->dev;
9822 u32 hi, lo, mac_offset;
9823
9824#ifdef CONFIG_SPARC64
9825 if (!tg3_get_macaddr_sparc(tp))
9826 return 0;
9827#endif
9828
9829 mac_offset = 0x7c;
4cf78e4f
MC		 9830 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9831 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9832 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1da177e4
LT		 9833 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9834 mac_offset = 0xcc;
9835 if (tg3_nvram_lock(tp))
9836 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9837 else
9838 tg3_nvram_unlock(tp);
9839 }
9840
9841 /* First try to get it from MAC address mailbox. */
9842 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9843 if ((hi >> 16) == 0x484b) {
9844 dev->dev_addr[0] = (hi >> 8) & 0xff;
9845 dev->dev_addr[1] = (hi >> 0) & 0xff;
9846
9847 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9848 dev->dev_addr[2] = (lo >> 24) & 0xff;
9849 dev->dev_addr[3] = (lo >> 16) & 0xff;
9850 dev->dev_addr[4] = (lo >> 8) & 0xff;
9851 dev->dev_addr[5] = (lo >> 0) & 0xff;
9852 }
9853 /* Next, try NVRAM. */
9854 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9855 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9856 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9857 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9858 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9859 dev->dev_addr[2] = ((lo >> 0) & 0xff);
9860 dev->dev_addr[3] = ((lo >> 8) & 0xff);
9861 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9862 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9863 }
9864 /* Finally just fetch it out of the MAC control regs. */
9865 else {
9866 hi = tr32(MAC_ADDR_0_HIGH);
9867 lo = tr32(MAC_ADDR_0_LOW);
9868
9869 dev->dev_addr[5] = lo & 0xff;
9870 dev->dev_addr[4] = (lo >> 8) & 0xff;
9871 dev->dev_addr[3] = (lo >> 16) & 0xff;
9872 dev->dev_addr[2] = (lo >> 24) & 0xff;
9873 dev->dev_addr[1] = hi & 0xff;
9874 dev->dev_addr[0] = (hi >> 8) & 0xff;
9875 }
9876
9877 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9878#ifdef CONFIG_SPARC64
9879 if (!tg3_get_default_macaddr_sparc(tp))
9880 return 0;
9881#endif
9882 return -EINVAL;
9883 }
2ff43697 9884 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 9885 return 0;
9886}
9887
59e6b434
DM		 9888#define BOUNDARY_SINGLE_CACHELINE 1
9889#define BOUNDARY_MULTI_CACHELINE 2
9890
9891static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9892{
9893 int cacheline_size;
9894 u8 byte;
9895 int goal;
9896
9897 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9898 if (byte == 0)
9899 cacheline_size = 1024;
9900 else
9901 cacheline_size = (int) byte * 4;
9902
9903 /* On 5703 and later chips, the boundary bits have no
9904 * effect.
9905 */
9906 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9907 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9908 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9909 goto out;
9910
9911#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9912 goal = BOUNDARY_MULTI_CACHELINE;
9913#else
9914#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9915 goal = BOUNDARY_SINGLE_CACHELINE;
9916#else
9917 goal = 0;
9918#endif
9919#endif
9920
9921 if (!goal)
9922 goto out;
9923
9924 /* PCI controllers on most RISC systems tend to disconnect
9925 * when a device tries to burst across a cache-line boundary.
9926 * Therefore, letting tg3 do so just wastes PCI bandwidth.
9927 *
9928 * Unfortunately, for PCI-E there are only limited
9929 * write-side controls for this, and thus for reads
9930 * we will still get the disconnects. We'll also waste
9931 * these PCI cycles for both read and write for chips
9932 * other than 5700 and 5701 which do not implement the
9933 * boundary bits.
9934 */
9935 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9936 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9937 switch (cacheline_size) {
9938 case 16:
9939 case 32:
9940 case 64:
9941 case 128:
9942 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9943 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9944 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9945 } else {
9946 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9947 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9948 }
9949 break;
9950
9951 case 256:
9952 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9953 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9954 break;
9955
9956 default:
9957 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9958 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9959 break;
9960 };
9961 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9962 switch (cacheline_size) {
9963 case 16:
9964 case 32:
9965 case 64:
9966 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9967 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9968 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9969 break;
9970 }
9971 /* fallthrough */
9972 case 128:
9973 default:
9974 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9975 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9976 break;
9977 };
9978 } else {
9979 switch (cacheline_size) {
9980 case 16:
9981 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9982 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9983 DMA_RWCTRL_WRITE_BNDRY_16);
9984 break;
9985 }
9986 /* fallthrough */
9987 case 32:
9988 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9989 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9990 DMA_RWCTRL_WRITE_BNDRY_32);
9991 break;
9992 }
9993 /* fallthrough */
9994 case 64:
9995 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9996 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9997 DMA_RWCTRL_WRITE_BNDRY_64);
9998 break;
9999 }
10000 /* fallthrough */
10001 case 128:
10002 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10003 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10004 DMA_RWCTRL_WRITE_BNDRY_128);
10005 break;
10006 }
10007 /* fallthrough */
10008 case 256:
10009 val |= (DMA_RWCTRL_READ_BNDRY_256 |
10010 DMA_RWCTRL_WRITE_BNDRY_256);
10011 break;
10012 case 512:
10013 val |= (DMA_RWCTRL_READ_BNDRY_512 |
10014 DMA_RWCTRL_WRITE_BNDRY_512);
10015 break;
10016 case 1024:
10017 default:
10018 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10019 DMA_RWCTRL_WRITE_BNDRY_1024);
10020 break;
10021 };
10022 }
10023
10024out:
10025 return val;
10026}
10027
1da177e4
LT		 10028static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10029{
10030 struct tg3_internal_buffer_desc test_desc;
10031 u32 sram_dma_descs;
10032 int i, ret;
10033
10034 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10035
10036 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10037 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10038 tw32(RDMAC_STATUS, 0);
10039 tw32(WDMAC_STATUS, 0);
10040
10041 tw32(BUFMGR_MODE, 0);
10042 tw32(FTQ_RESET, 0);
10043
10044 test_desc.addr_hi = ((u64) buf_dma) >> 32;
10045 test_desc.addr_lo = buf_dma & 0xffffffff;
10046 test_desc.nic_mbuf = 0x00002100;
10047 test_desc.len = size;
10048
10049 /*
10050 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10051 * the *second* time the tg3 driver was getting loaded after an
10052 * initial scan.
10053 *
10054 * Broadcom tells me:
10055 * ...the DMA engine is connected to the GRC block and a DMA
10056 * reset may affect the GRC block in some unpredictable way...
10057 * The behavior of resets to individual blocks has not been tested.
10058 *
10059 * Broadcom noted the GRC reset will also reset all sub-components.
10060 */
10061 if (to_device) {
10062 test_desc.cqid_sqid = (13 << 8) | 2;
10063
10064 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10065 udelay(40);
10066 } else {
10067 test_desc.cqid_sqid = (16 << 8) | 7;
10068
10069 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10070 udelay(40);
10071 }
10072 test_desc.flags = 0x00000005;
10073
10074 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10075 u32 val;
10076
10077 val = *(((u32 *)&test_desc) + i);
10078 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10079 sram_dma_descs + (i * sizeof(u32)));
10080 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10081 }
10082 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10083
10084 if (to_device) {
10085 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10086 } else {
10087 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10088 }
10089
10090 ret = -ENODEV;
10091 for (i = 0; i < 40; i++) {
10092 u32 val;
10093
10094 if (to_device)
10095 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10096 else
10097 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10098 if ((val & 0xffff) == sram_dma_descs) {
10099 ret = 0;
10100 break;
10101 }
10102
10103 udelay(100);
10104 }
10105
10106 return ret;
10107}
10108
ded7340d 10109#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 10110
10111static int __devinit tg3_test_dma(struct tg3 *tp)
10112{
10113 dma_addr_t buf_dma;
59e6b434 10114 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 10115 int ret;
10116
10117 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10118 if (!buf) {
10119 ret = -ENOMEM;
10120 goto out_nofree;
10121 }
10122
10123 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10124 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10125
59e6b434 10126 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 10127
10128 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10129 /* DMA read watermark not used on PCIE */
10130 tp->dma_rwctrl |= 0x00180000;
10131 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 10132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 10134 tp->dma_rwctrl |= 0x003f0000;
10135 else
10136 tp->dma_rwctrl |= 0x003f000f;
10137 } else {
10138 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10139 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10140 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10141
10142 if (ccval == 0x6 || ccval == 0x7)
10143 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10144
59e6b434 10145 /* Set bit 23 to enable PCIX hw bug fix */
1da177e4 10146 tp->dma_rwctrl |= 0x009f0000;
4cf78e4f
MC		 10147 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10148 /* 5780 always in PCIX mode */
10149 tp->dma_rwctrl |= 0x00144000;
1da177e4
LT		 10150 } else {
10151 tp->dma_rwctrl |= 0x001b000f;
10152 }
10153 }
10154
10155 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10156 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10157 tp->dma_rwctrl &= 0xfffffff0;
10158
10159 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10161 /* Remove this if it causes problems for some boards. */
10162 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10163
10164 /* On 5700/5701 chips, we need to set this bit.
10165 * Otherwise the chip will issue cacheline transactions
10166 * to streamable DMA memory with not all the byte
10167 * enables turned on. This is an error on several
10168 * RISC PCI controllers, in particular sparc64.
10169 *
10170 * On 5703/5704 chips, this bit has been reassigned
10171 * a different meaning. In particular, it is used
10172 * on those chips to enable a PCI-X workaround.
10173 */
10174 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10175 }
10176
10177 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10178
10179#if 0
10180 /* Unneeded, already done by tg3_get_invariants. */
10181 tg3_switch_clocks(tp);
10182#endif
10183
10184 ret = 0;
10185 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10186 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10187 goto out;
10188
59e6b434
DM		 10189 /* It is best to perform DMA test with maximum write burst size
10190 * to expose the 5700/5701 write DMA bug.
10191 */
10192 saved_dma_rwctrl = tp->dma_rwctrl;
10193 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10194 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10195
1da177e4
LT		 10196 while (1) {
10197 u32 *p = buf, i;
10198
10199 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10200 p[i] = i;
10201
10202 /* Send the buffer to the chip. */
10203 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10204 if (ret) {
10205 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10206 break;
10207 }
10208
10209#if 0
10210 /* validate data reached card RAM correctly. */
10211 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10212 u32 val;
10213 tg3_read_mem(tp, 0x2100 + (i*4), &val);
10214 if (le32_to_cpu(val) != p[i]) {
10215 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
10216 /* ret = -ENODEV here? */
10217 }
10218 p[i] = 0;
10219 }
10220#endif
10221 /* Now read it back. */
10222 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10223 if (ret) {
10224 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10225
10226 break;
10227 }
10228
10229 /* Verify it. */
10230 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10231 if (p[i] == i)
10232 continue;
10233
59e6b434
DM		 10234 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10235 DMA_RWCTRL_WRITE_BNDRY_16) {
10236 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 10237 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10238 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10239 break;
10240 } else {
10241 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10242 ret = -ENODEV;
10243 goto out;
10244 }
10245 }
10246
10247 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10248 /* Success. */
10249 ret = 0;
10250 break;
10251 }
10252 }
59e6b434
DM		 10253 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10254 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 10255 static struct pci_device_id dma_wait_state_chipsets[] = {
10256 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10257 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10258 { },
10259 };
10260
59e6b434 10261 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 10262 * now look for chipsets that are known to expose the
10263 * DMA bug without failing the test.
59e6b434 10264 */
6d1cfbab
MC		 10265 if (pci_dev_present(dma_wait_state_chipsets)) {
10266 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10267 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10268 }
10269 else
10270 /* Safe to use the calculated DMA boundary. */
10271 tp->dma_rwctrl = saved_dma_rwctrl;
10272
59e6b434
DM		 10273 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10274 }
1da177e4
LT		 10275
10276out:
10277 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
10278out_nofree:
10279 return ret;
10280}
10281
10282static void __devinit tg3_init_link_config(struct tg3 *tp)
10283{
10284 tp->link_config.advertising =
10285 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10286 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10287 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
10288 ADVERTISED_Autoneg | ADVERTISED_MII);
10289 tp->link_config.speed = SPEED_INVALID;
10290 tp->link_config.duplex = DUPLEX_INVALID;
10291 tp->link_config.autoneg = AUTONEG_ENABLE;
10292 netif_carrier_off(tp->dev);
10293 tp->link_config.active_speed = SPEED_INVALID;
10294 tp->link_config.active_duplex = DUPLEX_INVALID;
10295 tp->link_config.phy_is_low_power = 0;
10296 tp->link_config.orig_speed = SPEED_INVALID;
10297 tp->link_config.orig_duplex = DUPLEX_INVALID;
10298 tp->link_config.orig_autoneg = AUTONEG_INVALID;
10299}
10300
10301static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
10302{
fdfec172
MC		 10303 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10304 tp->bufmgr_config.mbuf_read_dma_low_water =
10305 DEFAULT_MB_RDMA_LOW_WATER_5705;
10306 tp->bufmgr_config.mbuf_mac_rx_low_water =
10307 DEFAULT_MB_MACRX_LOW_WATER_5705;
10308 tp->bufmgr_config.mbuf_high_water =
10309 DEFAULT_MB_HIGH_WATER_5705;
10310
10311 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10312 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10313 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10314 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10315 tp->bufmgr_config.mbuf_high_water_jumbo =
10316 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10317 } else {
10318 tp->bufmgr_config.mbuf_read_dma_low_water =
10319 DEFAULT_MB_RDMA_LOW_WATER;
10320 tp->bufmgr_config.mbuf_mac_rx_low_water =
10321 DEFAULT_MB_MACRX_LOW_WATER;
10322 tp->bufmgr_config.mbuf_high_water =
10323 DEFAULT_MB_HIGH_WATER;
10324
10325 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10326 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
10327 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10328 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
10329 tp->bufmgr_config.mbuf_high_water_jumbo =
10330 DEFAULT_MB_HIGH_WATER_JUMBO;
10331 }
1da177e4
LT		 10332
10333 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
10334 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
10335}
10336
10337static char * __devinit tg3_phy_string(struct tg3 *tp)
10338{
10339 switch (tp->phy_id & PHY_ID_MASK) {
10340 case PHY_ID_BCM5400: return "5400";
10341 case PHY_ID_BCM5401: return "5401";
10342 case PHY_ID_BCM5411: return "5411";
10343 case PHY_ID_BCM5701: return "5701";
10344 case PHY_ID_BCM5703: return "5703";
10345 case PHY_ID_BCM5704: return "5704";
10346 case PHY_ID_BCM5705: return "5705";
10347 case PHY_ID_BCM5750: return "5750";
85e94ced 10348 case PHY_ID_BCM5752: return "5752";
4cf78e4f 10349 case PHY_ID_BCM5780: return "5780";
1da177e4
LT		 10350 case PHY_ID_BCM8002: return "8002/serdes";
10351 case 0: return "serdes";
10352 default: return "unknown";
10353 };
10354}
10355
f9804ddb
MC		 10356static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10357{
10358 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10359 strcpy(str, "PCI Express");
10360 return str;
10361 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
10362 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
10363
10364 strcpy(str, "PCIX:");
10365
10366 if ((clock_ctrl == 7) ||
10367 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
10368 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
10369 strcat(str, "133MHz");
10370 else if (clock_ctrl == 0)
10371 strcat(str, "33MHz");
10372 else if (clock_ctrl == 2)
10373 strcat(str, "50MHz");
10374 else if (clock_ctrl == 4)
10375 strcat(str, "66MHz");
10376 else if (clock_ctrl == 6)
10377 strcat(str, "100MHz");
10378 else if (clock_ctrl == 7)
10379 strcat(str, "133MHz");
10380 } else {
10381 strcpy(str, "PCI:");
10382 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
10383 strcat(str, "66MHz");
10384 else
10385 strcat(str, "33MHz");
10386 }
10387 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
10388 strcat(str, ":32-bit");
10389 else
10390 strcat(str, ":64-bit");
10391 return str;
10392}
10393
1da177e4
LT		 10394static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
10395{
10396 struct pci_dev *peer;
10397 unsigned int func, devnr = tp->pdev->devfn & ~7;
10398
10399 for (func = 0; func < 8; func++) {
10400 peer = pci_get_slot(tp->pdev->bus, devnr | func);
10401 if (peer && peer != tp->pdev)
10402 break;
10403 pci_dev_put(peer);
10404 }
10405 if (!peer || peer == tp->pdev)
10406 BUG();
10407
10408 /*
10409 * We don't need to keep the refcount elevated; there's no way
10410 * to remove one half of this device without removing the other
10411 */
10412 pci_dev_put(peer);
10413
10414 return peer;
10415}
10416
15f9850d
DM		 10417static void __devinit tg3_init_coal(struct tg3 *tp)
10418{
10419 struct ethtool_coalesce *ec = &tp->coal;
10420
10421 memset(ec, 0, sizeof(*ec));
10422 ec->cmd = ETHTOOL_GCOALESCE;
10423 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
10424 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
10425 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
10426 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
10427 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
10428 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
10429 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
10430 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
10431 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
10432
10433 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
10434 HOSTCC_MODE_CLRTICK_TXBD)) {
10435 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
10436 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
10437 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
10438 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
10439 }
d244c892
MC		 10440
10441 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10442 ec->rx_coalesce_usecs_irq = 0;
10443 ec->tx_coalesce_usecs_irq = 0;
10444 ec->stats_block_coalesce_usecs = 0;
10445 }
15f9850d
DM		 10446}
10447
1da177e4
LT		 10448static int __devinit tg3_init_one(struct pci_dev *pdev,
10449 const struct pci_device_id *ent)
10450{
10451 static int tg3_version_printed = 0;
10452 unsigned long tg3reg_base, tg3reg_len;
10453 struct net_device *dev;
10454 struct tg3 *tp;
10455 int i, err, pci_using_dac, pm_cap;
f9804ddb 10456 char str[40];
1da177e4
LT		 10457
10458 if (tg3_version_printed++ == 0)
10459 printk(KERN_INFO "%s", version);
10460
10461 err = pci_enable_device(pdev);
10462 if (err) {
10463 printk(KERN_ERR PFX "Cannot enable PCI device, "
10464 "aborting.\n");
10465 return err;
10466 }
10467
10468 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10469 printk(KERN_ERR PFX "Cannot find proper PCI device "
10470 "base address, aborting.\n");
10471 err = -ENODEV;
10472 goto err_out_disable_pdev;
10473 }
10474
10475 err = pci_request_regions(pdev, DRV_MODULE_NAME);
10476 if (err) {
10477 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
10478 "aborting.\n");
10479 goto err_out_disable_pdev;
10480 }
10481
10482 pci_set_master(pdev);
10483
10484 /* Find power-management capability. */
10485 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10486 if (pm_cap == 0) {
10487 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
10488 "aborting.\n");
10489 err = -EIO;
10490 goto err_out_free_res;
10491 }
10492
10493 /* Configure DMA attributes. */
10494 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
10495 if (!err) {
10496 pci_using_dac = 1;
10497 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
10498 if (err < 0) {
10499 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10500 "for consistent allocations\n");
10501 goto err_out_free_res;
10502 }
10503 } else {
10504 err = pci_set_dma_mask(pdev, 0xffffffffULL);
10505 if (err) {
10506 printk(KERN_ERR PFX "No usable DMA configuration, "
10507 "aborting.\n");
10508 goto err_out_free_res;
10509 }
10510 pci_using_dac = 0;
10511 }
10512
10513 tg3reg_base = pci_resource_start(pdev, 0);
10514 tg3reg_len = pci_resource_len(pdev, 0);
10515
10516 dev = alloc_etherdev(sizeof(*tp));
10517 if (!dev) {
10518 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10519 err = -ENOMEM;
10520 goto err_out_free_res;
10521 }
10522
10523 SET_MODULE_OWNER(dev);
10524 SET_NETDEV_DEV(dev, &pdev->dev);
10525
10526 if (pci_using_dac)
10527 dev->features |= NETIF_F_HIGHDMA;
10528 dev->features |= NETIF_F_LLTX;
10529#if TG3_VLAN_TAG_USED
10530 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10531 dev->vlan_rx_register = tg3_vlan_rx_register;
10532 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10533#endif
10534
10535 tp = netdev_priv(dev);
10536 tp->pdev = pdev;
10537 tp->dev = dev;
10538 tp->pm_cap = pm_cap;
10539 tp->mac_mode = TG3_DEF_MAC_MODE;
10540 tp->rx_mode = TG3_DEF_RX_MODE;
10541 tp->tx_mode = TG3_DEF_TX_MODE;
10542 tp->mi_mode = MAC_MI_MODE_BASE;
10543 if (tg3_debug > 0)
10544 tp->msg_enable = tg3_debug;
10545 else
10546 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10547
10548 /* The word/byte swap controls here control register access byte
10549 * swapping. DMA data byte swapping is controlled in the GRC_MODE
10550 * setting below.
10551 */
10552 tp->misc_host_ctrl =
10553 MISC_HOST_CTRL_MASK_PCI_INT |
10554 MISC_HOST_CTRL_WORD_SWAP |
10555 MISC_HOST_CTRL_INDIR_ACCESS |
10556 MISC_HOST_CTRL_PCISTATE_RW;
10557
10558 /* The NONFRM (non-frame) byte/word swap controls take effect
10559 * on descriptor entries, anything which isn't packet data.
10560 *
10561 * The StrongARM chips on the board (one for tx, one for rx)
10562 * are running in big-endian mode.
10563 */
10564 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10565 GRC_MODE_WSWAP_NONFRM_DATA);
10566#ifdef __BIG_ENDIAN
10567 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10568#endif
10569 spin_lock_init(&tp->lock);
10570 spin_lock_init(&tp->tx_lock);
10571 spin_lock_init(&tp->indirect_lock);
10572 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10573
10574 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10575 if (tp->regs == 0UL) {
10576 printk(KERN_ERR PFX "Cannot map device registers, "
10577 "aborting.\n");
10578 err = -ENOMEM;
10579 goto err_out_free_dev;
10580 }
10581
10582 tg3_init_link_config(tp);
10583
1da177e4
LT		 10584 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10585 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10586 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10587
10588 dev->open = tg3_open;
10589 dev->stop = tg3_close;
10590 dev->get_stats = tg3_get_stats;
10591 dev->set_multicast_list = tg3_set_rx_mode;
10592 dev->set_mac_address = tg3_set_mac_addr;
10593 dev->do_ioctl = tg3_ioctl;
10594 dev->tx_timeout = tg3_tx_timeout;
10595 dev->poll = tg3_poll;
10596 dev->ethtool_ops = &tg3_ethtool_ops;
10597 dev->weight = 64;
10598 dev->watchdog_timeo = TG3_TX_TIMEOUT;
10599 dev->change_mtu = tg3_change_mtu;
10600 dev->irq = pdev->irq;
10601#ifdef CONFIG_NET_POLL_CONTROLLER
10602 dev->poll_controller = tg3_poll_controller;
10603#endif
10604
10605 err = tg3_get_invariants(tp);
10606 if (err) {
10607 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10608 "aborting.\n");
10609 goto err_out_iounmap;
10610 }
10611
fdfec172 10612 tg3_init_bufmgr_config(tp);
1da177e4
LT		 10613
10614#if TG3_TSO_SUPPORT != 0
10615 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10616 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10617 }
10618 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10620 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10621 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10622 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10623 } else {
10624 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10625 }
10626
10627 /* TSO is off by default, user can enable using ethtool. */
10628#if 0
10629 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10630 dev->features |= NETIF_F_TSO;
10631#endif
10632
10633#endif
10634
10635 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10636 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10637 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10638 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10639 tp->rx_pending = 63;
10640 }
10641
10642 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10643 tp->pdev_peer = tg3_find_5704_peer(tp);
10644
10645 err = tg3_get_device_address(tp);
10646 if (err) {
10647 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10648 "aborting.\n");
10649 goto err_out_iounmap;
10650 }
10651
10652 /*
10653 * Reset chip in case UNDI or EFI driver did not shutdown
10654 * DMA self test will enable WDMAC and we'll see (spurious)
10655 * pending DMA on the PCI bus at that point.
10656 */
10657 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10658 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10659 pci_save_state(tp->pdev);
10660 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 10661 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 10662 }
10663
10664 err = tg3_test_dma(tp);
10665 if (err) {
10666 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10667 goto err_out_iounmap;
10668 }
10669
10670 /* Tigon3 can do ipv4 only... and some chips have buggy
10671 * checksumming.
10672 */
10673 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10674 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10675 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10676 } else
10677 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10678
10679 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10680 dev->features &= ~NETIF_F_HIGHDMA;
10681
10682 /* flow control autonegotiation is default behavior */
10683 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10684
15f9850d
DM		 10685 tg3_init_coal(tp);
10686
7d3f4c97
DM		 10687 /* Now that we have fully setup the chip, save away a snapshot
10688 * of the PCI config space. We need to restore this after
10689 * GRC_MISC_CFG core clock resets and some resume events.
10690 */
10691 pci_save_state(tp->pdev);
10692
1da177e4
LT		 10693 err = register_netdev(dev);
10694 if (err) {
10695 printk(KERN_ERR PFX "Cannot register net device, "
10696 "aborting.\n");
10697 goto err_out_iounmap;
10698 }
10699
10700 pci_set_drvdata(pdev, dev);
10701
f9804ddb 10702 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
1da177e4
LT		 10703 dev->name,
10704 tp->board_part_number,
10705 tp->pci_chip_rev_id,
10706 tg3_phy_string(tp),
f9804ddb 10707 tg3_bus_string(tp, str),
1da177e4
LT		 10708 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10709
10710 for (i = 0; i < 6; i++)
10711 printk("%2.2x%c", dev->dev_addr[i],
10712 i == 5 ? '\n' : ':');
10713
10714 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10715 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10716 "TSOcap[%d] \n",
10717 dev->name,
10718 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10719 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10720 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10721 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10722 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10723 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10724 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
59e6b434
DM		 10725 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10726 dev->name, tp->dma_rwctrl);
1da177e4
LT		 10727
10728 return 0;
10729
10730err_out_iounmap:
6892914f
MC		 10731 if (tp->regs) {
10732 iounmap(tp->regs);
22abe310 10733 tp->regs = NULL;
6892914f 10734 }
1da177e4
LT		 10735
10736err_out_free_dev:
10737 free_netdev(dev);
10738
10739err_out_free_res:
10740 pci_release_regions(pdev);
10741
10742err_out_disable_pdev:
10743 pci_disable_device(pdev);
10744 pci_set_drvdata(pdev, NULL);
10745 return err;
10746}
10747
10748static void __devexit tg3_remove_one(struct pci_dev *pdev)
10749{
10750 struct net_device *dev = pci_get_drvdata(pdev);
10751
10752 if (dev) {
10753 struct tg3 *tp = netdev_priv(dev);
10754
10755 unregister_netdev(dev);
6892914f
MC		 10756 if (tp->regs) {
10757 iounmap(tp->regs);
22abe310 10758 tp->regs = NULL;
6892914f 10759 }
1da177e4
LT		 10760 free_netdev(dev);
10761 pci_release_regions(pdev);
10762 pci_disable_device(pdev);
10763 pci_set_drvdata(pdev, NULL);
10764 }
10765}
10766
10767static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10768{
10769 struct net_device *dev = pci_get_drvdata(pdev);
10770 struct tg3 *tp = netdev_priv(dev);
10771 int err;
10772
10773 if (!netif_running(dev))
10774 return 0;
10775
10776 tg3_netif_stop(tp);
10777
10778 del_timer_sync(&tp->timer);
10779
f47c11ee 10780 tg3_full_lock(tp, 1);
1da177e4 10781 tg3_disable_ints(tp);
f47c11ee 10782 tg3_full_unlock(tp);
1da177e4
LT		 10783
10784 netif_device_detach(dev);
10785
f47c11ee 10786 tg3_full_lock(tp, 0);
944d980e 10787 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
f47c11ee 10788 tg3_full_unlock(tp);
1da177e4
LT		 10789
10790 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10791 if (err) {
f47c11ee 10792 tg3_full_lock(tp, 0);
1da177e4
LT		 10793
10794 tg3_init_hw(tp);
10795
10796 tp->timer.expires = jiffies + tp->timer_offset;
10797 add_timer(&tp->timer);
10798
10799 netif_device_attach(dev);
10800 tg3_netif_start(tp);
10801
f47c11ee 10802 tg3_full_unlock(tp);
1da177e4
LT		 10803 }
10804
10805 return err;
10806}
10807
10808static int tg3_resume(struct pci_dev *pdev)
10809{
10810 struct net_device *dev = pci_get_drvdata(pdev);
10811 struct tg3 *tp = netdev_priv(dev);
10812 int err;
10813
10814 if (!netif_running(dev))
10815 return 0;
10816
10817 pci_restore_state(tp->pdev);
10818
10819 err = tg3_set_power_state(tp, 0);
10820 if (err)
10821 return err;
10822
10823 netif_device_attach(dev);
10824
f47c11ee 10825 tg3_full_lock(tp, 0);
1da177e4
LT		 10826
10827 tg3_init_hw(tp);
10828
10829 tp->timer.expires = jiffies + tp->timer_offset;
10830 add_timer(&tp->timer);
10831
1da177e4
LT		 10832 tg3_netif_start(tp);
10833
f47c11ee 10834 tg3_full_unlock(tp);
1da177e4
LT		 10835
10836 return 0;
10837}
10838
10839static struct pci_driver tg3_driver = {
10840 .name = DRV_MODULE_NAME,
10841 .id_table = tg3_pci_tbl,
10842 .probe = tg3_init_one,
10843 .remove = __devexit_p(tg3_remove_one),
10844 .suspend = tg3_suspend,
10845 .resume = tg3_resume
10846};
10847
10848static int __init tg3_init(void)
10849{
10850 return pci_module_init(&tg3_driver);
10851}
10852
10853static void __exit tg3_cleanup(void)
10854{
10855 pci_unregister_driver(&tg3_driver);
10856}
10857
10858module_init(tg3_init);
10859module_exit(tg3_cleanup);
Clone of davem's net-next-2.6 tree