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[TG3]: Add TSO firmware license
[net-next-2.6.git] / drivers / net / tg3.c
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1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
18#include <linux/config.h>
19
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
39
40#include <net/checksum.h>
41
42#include <asm/system.h>
43#include <asm/io.h>
44#include <asm/byteorder.h>
45#include <asm/uaccess.h>
46
47#ifdef CONFIG_SPARC64
48#include <asm/idprom.h>
49#include <asm/oplib.h>
50#include <asm/pbm.h>
51#endif
52
53#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54#define TG3_VLAN_TAG_USED 1
55#else
56#define TG3_VLAN_TAG_USED 0
57#endif
58
59#ifdef NETIF_F_TSO
60#define TG3_TSO_SUPPORT 1
61#else
62#define TG3_TSO_SUPPORT 0
63#endif
64
65#include "tg3.h"
66
67#define DRV_MODULE_NAME "tg3"
68#define PFX DRV_MODULE_NAME ": "
d1faeaeb 69#define DRV_MODULE_VERSION "3.29"
413f5431 70#define DRV_MODULE_RELDATE "May 23, 2005"
1da177e4
LT		 71
72#define TG3_DEF_MAC_MODE 0
73#define TG3_DEF_RX_MODE 0
74#define TG3_DEF_TX_MODE 0
75#define TG3_DEF_MSG_ENABLE \
76 (NETIF_MSG_DRV | \
77 NETIF_MSG_PROBE | \
78 NETIF_MSG_LINK | \
79 NETIF_MSG_TIMER | \
80 NETIF_MSG_IFDOWN | \
81 NETIF_MSG_IFUP | \
82 NETIF_MSG_RX_ERR | \
83 NETIF_MSG_TX_ERR)
84
85/* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
87 */
88#define TG3_TX_TIMEOUT (5 * HZ)
89
90/* hardware minimum and maximum for a single frame's data payload */
91#define TG3_MIN_MTU 60
92#define TG3_MAX_MTU(tp) \
fcf02693 93 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
1da177e4
LT		 94
95/* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
98 */
99#define TG3_RX_RING_SIZE 512
100#define TG3_DEF_RX_RING_PENDING 200
101#define TG3_RX_JUMBO_RING_SIZE 256
102#define TG3_DEF_RX_JUMBO_RING_PENDING 100
103
104/* Do not place this n-ring entries value into the tp struct itself,
105 * we really want to expose these constants to GCC so that modulo et
106 * al. operations are done with shifts and masks instead of with
107 * hw multiply/modulo instructions. Another solution would be to
108 * replace things like '% foo' with '& (foo - 1)'.
109 */
110#define TG3_RX_RCB_RING_SIZE(tp) \
111 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
112
113#define TG3_TX_RING_SIZE 512
114#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
115
116#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_RING_SIZE)
118#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_JUMBO_RING_SIZE)
120#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RCB_RING_SIZE(tp))
122#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
123 TG3_TX_RING_SIZE)
124#define TX_RING_GAP(TP) \
125 (TG3_TX_RING_SIZE - (TP)->tx_pending)
126#define TX_BUFFS_AVAIL(TP) \
127 (((TP)->tx_cons <= (TP)->tx_prod) ? \
128 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
129 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
130#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
131
132#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
133#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
134
135/* minimum number of free TX descriptors required to wake up TX process */
136#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
137
138/* number of ETHTOOL_GSTATS u64's */
139#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
140
4cafd3f5
MC		 141#define TG3_NUM_TEST 6
142
1da177e4
LT		 143static char version[] __devinitdata =
144 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
145
146MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
147MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
148MODULE_LICENSE("GPL");
149MODULE_VERSION(DRV_MODULE_VERSION);
150
151static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
152module_param(tg3_debug, int, 0);
153MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
154
155static struct pci_device_id tg3_pci_tbl[] = {
156 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
158 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
160 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
162 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
164 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
166 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
168 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
170 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
172 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
174 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
176 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
178 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
180 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
182 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
184 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
186 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
188 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
190 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
192 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
194 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
196 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
198 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
200 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
202 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
206 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
208 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
210 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
212 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
6e9017a7 214 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
af2bcd97 215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
d8659255
XVP		 216 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 218 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
220 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
228 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
232 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { 0, }
241};
242
243MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
244
245static struct {
246 const char string[ETH_GSTRING_LEN];
247} ethtool_stats_keys[TG3_NUM_STATS] = {
248 { "rx_octets" },
249 { "rx_fragments" },
250 { "rx_ucast_packets" },
251 { "rx_mcast_packets" },
252 { "rx_bcast_packets" },
253 { "rx_fcs_errors" },
254 { "rx_align_errors" },
255 { "rx_xon_pause_rcvd" },
256 { "rx_xoff_pause_rcvd" },
257 { "rx_mac_ctrl_rcvd" },
258 { "rx_xoff_entered" },
259 { "rx_frame_too_long_errors" },
260 { "rx_jabbers" },
261 { "rx_undersize_packets" },
262 { "rx_in_length_errors" },
263 { "rx_out_length_errors" },
264 { "rx_64_or_less_octet_packets" },
265 { "rx_65_to_127_octet_packets" },
266 { "rx_128_to_255_octet_packets" },
267 { "rx_256_to_511_octet_packets" },
268 { "rx_512_to_1023_octet_packets" },
269 { "rx_1024_to_1522_octet_packets" },
270 { "rx_1523_to_2047_octet_packets" },
271 { "rx_2048_to_4095_octet_packets" },
272 { "rx_4096_to_8191_octet_packets" },
273 { "rx_8192_to_9022_octet_packets" },
274
275 { "tx_octets" },
276 { "tx_collisions" },
277
278 { "tx_xon_sent" },
279 { "tx_xoff_sent" },
280 { "tx_flow_control" },
281 { "tx_mac_errors" },
282 { "tx_single_collisions" },
283 { "tx_mult_collisions" },
284 { "tx_deferred" },
285 { "tx_excessive_collisions" },
286 { "tx_late_collisions" },
287 { "tx_collide_2times" },
288 { "tx_collide_3times" },
289 { "tx_collide_4times" },
290 { "tx_collide_5times" },
291 { "tx_collide_6times" },
292 { "tx_collide_7times" },
293 { "tx_collide_8times" },
294 { "tx_collide_9times" },
295 { "tx_collide_10times" },
296 { "tx_collide_11times" },
297 { "tx_collide_12times" },
298 { "tx_collide_13times" },
299 { "tx_collide_14times" },
300 { "tx_collide_15times" },
301 { "tx_ucast_packets" },
302 { "tx_mcast_packets" },
303 { "tx_bcast_packets" },
304 { "tx_carrier_sense_errors" },
305 { "tx_discards" },
306 { "tx_errors" },
307
308 { "dma_writeq_full" },
309 { "dma_write_prioq_full" },
310 { "rxbds_empty" },
311 { "rx_discards" },
312 { "rx_errors" },
313 { "rx_threshold_hit" },
314
315 { "dma_readq_full" },
316 { "dma_read_prioq_full" },
317 { "tx_comp_queue_full" },
318
319 { "ring_set_send_prod_index" },
320 { "ring_status_update" },
321 { "nic_irqs" },
322 { "nic_avoided_irqs" },
323 { "nic_tx_threshold_hit" }
324};
325
4cafd3f5
MC		 326static struct {
327 const char string[ETH_GSTRING_LEN];
328} ethtool_test_keys[TG3_NUM_TEST] = {
329 { "nvram test (online) " },
330 { "link test (online) " },
331 { "register test (offline)" },
332 { "memory test (offline)" },
333 { "loopback test (offline)" },
334 { "interrupt test (offline)" },
335};
336
1da177e4
LT		 337static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
338{
339 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
340 unsigned long flags;
341
342 spin_lock_irqsave(&tp->indirect_lock, flags);
343 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
344 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
345 spin_unlock_irqrestore(&tp->indirect_lock, flags);
346 } else {
347 writel(val, tp->regs + off);
348 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
349 readl(tp->regs + off);
350 }
351}
352
353static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
354{
355 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
356 unsigned long flags;
357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362 } else {
363 void __iomem *dest = tp->regs + off;
364 writel(val, dest);
365 readl(dest); /* always flush PCI write */
366 }
367}
368
369static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
370{
371 void __iomem *mbox = tp->regs + off;
372 writel(val, mbox);
373 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
374 readl(mbox);
375}
376
377static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
378{
379 void __iomem *mbox = tp->regs + off;
380 writel(val, mbox);
381 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
382 writel(val, mbox);
383 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
384 readl(mbox);
385}
386
387#define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tp->regs + (reg))
388#define tw32_rx_mbox(reg, val) _tw32_rx_mbox(tp, reg, val)
389#define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
390
391#define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
392#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
393#define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
394#define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
395#define tr32(reg) readl(tp->regs + (reg))
396#define tr16(reg) readw(tp->regs + (reg))
397#define tr8(reg) readb(tp->regs + (reg))
398
399static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
400{
401 unsigned long flags;
402
403 spin_lock_irqsave(&tp->indirect_lock, flags);
404 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
405 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
406
407 /* Always leave this as zero. */
408 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
409 spin_unlock_irqrestore(&tp->indirect_lock, flags);
410}
411
412static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
413{
414 unsigned long flags;
415
416 spin_lock_irqsave(&tp->indirect_lock, flags);
417 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
418 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
419
420 /* Always leave this as zero. */
421 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
422 spin_unlock_irqrestore(&tp->indirect_lock, flags);
423}
424
425static void tg3_disable_ints(struct tg3 *tp)
426{
427 tw32(TG3PCI_MISC_HOST_CTRL,
428 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
429 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
430 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
431}
432
433static inline void tg3_cond_int(struct tg3 *tp)
434{
435 if (tp->hw_status->status & SD_STATUS_UPDATED)
436 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
437}
438
439static void tg3_enable_ints(struct tg3 *tp)
440{
441 tw32(TG3PCI_MISC_HOST_CTRL,
442 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
fac9b83e
DM		 443 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
444 (tp->last_tag << 24));
1da177e4
LT		 445 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
446
447 tg3_cond_int(tp);
448}
449
04237ddd
MC		 450static inline unsigned int tg3_has_work(struct tg3 *tp)
451{
452 struct tg3_hw_status *sblk = tp->hw_status;
453 unsigned int work_exists = 0;
454
455 /* check for phy events */
456 if (!(tp->tg3_flags &
457 (TG3_FLAG_USE_LINKCHG_REG |
458 TG3_FLAG_POLL_SERDES))) {
459 if (sblk->status & SD_STATUS_LINK_CHG)
460 work_exists = 1;
461 }
462 /* check for RX/TX work to do */
463 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
464 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
465 work_exists = 1;
466
467 return work_exists;
468}
469
1da177e4 470/* tg3_restart_ints
04237ddd
MC		 471 * similar to tg3_enable_ints, but it accurately determines whether there
472 * is new work pending and can return without flushing the PIO write
473 * which reenables interrupts
1da177e4
LT		 474 */
475static void tg3_restart_ints(struct tg3 *tp)
476{
477 tw32(TG3PCI_MISC_HOST_CTRL,
478 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
fac9b83e
DM		 479 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
480 tp->last_tag << 24);
1da177e4
LT		 481 mmiowb();
482
fac9b83e
DM		 483 /* When doing tagged status, this work check is unnecessary.
484 * The last_tag we write above tells the chip which piece of
485 * work we've completed.
486 */
487 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
488 tg3_has_work(tp))
04237ddd
MC		 489 tw32(HOSTCC_MODE, tp->coalesce_mode |
490 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 491}
492
493static inline void tg3_netif_stop(struct tg3 *tp)
494{
495 netif_poll_disable(tp->dev);
496 netif_tx_disable(tp->dev);
497}
498
499static inline void tg3_netif_start(struct tg3 *tp)
500{
501 netif_wake_queue(tp->dev);
502 /* NOTE: unconditional netif_wake_queue is only appropriate
503 * so long as all callers are assured to have free tx slots
504 * (such as after tg3_init_hw)
505 */
506 netif_poll_enable(tp->dev);
507 tg3_cond_int(tp);
508}
509
510static void tg3_switch_clocks(struct tg3 *tp)
511{
512 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
513 u32 orig_clock_ctrl;
514
515 orig_clock_ctrl = clock_ctrl;
516 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
517 CLOCK_CTRL_CLKRUN_OENABLE |
518 0x1f);
519 tp->pci_clock_ctrl = clock_ctrl;
520
521 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
522 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
523 tw32_f(TG3PCI_CLOCK_CTRL,
524 clock_ctrl | CLOCK_CTRL_625_CORE);
525 udelay(40);
526 }
527 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
528 tw32_f(TG3PCI_CLOCK_CTRL,
529 clock_ctrl |
530 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
531 udelay(40);
532 tw32_f(TG3PCI_CLOCK_CTRL,
533 clock_ctrl | (CLOCK_CTRL_ALTCLK));
534 udelay(40);
535 }
536 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
537 udelay(40);
538}
539
540#define PHY_BUSY_LOOPS 5000
541
542static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
543{
544 u32 frame_val;
545 unsigned int loops;
546 int ret;
547
548 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
549 tw32_f(MAC_MI_MODE,
550 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
551 udelay(80);
552 }
553
554 *val = 0x0;
555
556 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
557 MI_COM_PHY_ADDR_MASK);
558 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
559 MI_COM_REG_ADDR_MASK);
560 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
561
562 tw32_f(MAC_MI_COM, frame_val);
563
564 loops = PHY_BUSY_LOOPS;
565 while (loops != 0) {
566 udelay(10);
567 frame_val = tr32(MAC_MI_COM);
568
569 if ((frame_val & MI_COM_BUSY) == 0) {
570 udelay(5);
571 frame_val = tr32(MAC_MI_COM);
572 break;
573 }
574 loops -= 1;
575 }
576
577 ret = -EBUSY;
578 if (loops != 0) {
579 *val = frame_val & MI_COM_DATA_MASK;
580 ret = 0;
581 }
582
583 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
584 tw32_f(MAC_MI_MODE, tp->mi_mode);
585 udelay(80);
586 }
587
588 return ret;
589}
590
591static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
592{
593 u32 frame_val;
594 unsigned int loops;
595 int ret;
596
597 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
598 tw32_f(MAC_MI_MODE,
599 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
600 udelay(80);
601 }
602
603 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
604 MI_COM_PHY_ADDR_MASK);
605 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
606 MI_COM_REG_ADDR_MASK);
607 frame_val |= (val & MI_COM_DATA_MASK);
608 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
609
610 tw32_f(MAC_MI_COM, frame_val);
611
612 loops = PHY_BUSY_LOOPS;
613 while (loops != 0) {
614 udelay(10);
615 frame_val = tr32(MAC_MI_COM);
616 if ((frame_val & MI_COM_BUSY) == 0) {
617 udelay(5);
618 frame_val = tr32(MAC_MI_COM);
619 break;
620 }
621 loops -= 1;
622 }
623
624 ret = -EBUSY;
625 if (loops != 0)
626 ret = 0;
627
628 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
629 tw32_f(MAC_MI_MODE, tp->mi_mode);
630 udelay(80);
631 }
632
633 return ret;
634}
635
636static void tg3_phy_set_wirespeed(struct tg3 *tp)
637{
638 u32 val;
639
640 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
641 return;
642
643 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
644 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
645 tg3_writephy(tp, MII_TG3_AUX_CTRL,
646 (val | (1 << 15) | (1 << 4)));
647}
648
649static int tg3_bmcr_reset(struct tg3 *tp)
650{
651 u32 phy_control;
652 int limit, err;
653
654 /* OK, reset it, and poll the BMCR_RESET bit until it
655 * clears or we time out.
656 */
657 phy_control = BMCR_RESET;
658 err = tg3_writephy(tp, MII_BMCR, phy_control);
659 if (err != 0)
660 return -EBUSY;
661
662 limit = 5000;
663 while (limit--) {
664 err = tg3_readphy(tp, MII_BMCR, &phy_control);
665 if (err != 0)
666 return -EBUSY;
667
668 if ((phy_control & BMCR_RESET) == 0) {
669 udelay(40);
670 break;
671 }
672 udelay(10);
673 }
674 if (limit <= 0)
675 return -EBUSY;
676
677 return 0;
678}
679
680static int tg3_wait_macro_done(struct tg3 *tp)
681{
682 int limit = 100;
683
684 while (limit--) {
685 u32 tmp32;
686
687 if (!tg3_readphy(tp, 0x16, &tmp32)) {
688 if ((tmp32 & 0x1000) == 0)
689 break;
690 }
691 }
692 if (limit <= 0)
693 return -EBUSY;
694
695 return 0;
696}
697
698static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
699{
700 static const u32 test_pat[4][6] = {
701 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
702 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
703 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
704 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
705 };
706 int chan;
707
708 for (chan = 0; chan < 4; chan++) {
709 int i;
710
711 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
712 (chan * 0x2000) | 0x0200);
713 tg3_writephy(tp, 0x16, 0x0002);
714
715 for (i = 0; i < 6; i++)
716 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
717 test_pat[chan][i]);
718
719 tg3_writephy(tp, 0x16, 0x0202);
720 if (tg3_wait_macro_done(tp)) {
721 *resetp = 1;
722 return -EBUSY;
723 }
724
725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
726 (chan * 0x2000) | 0x0200);
727 tg3_writephy(tp, 0x16, 0x0082);
728 if (tg3_wait_macro_done(tp)) {
729 *resetp = 1;
730 return -EBUSY;
731 }
732
733 tg3_writephy(tp, 0x16, 0x0802);
734 if (tg3_wait_macro_done(tp)) {
735 *resetp = 1;
736 return -EBUSY;
737 }
738
739 for (i = 0; i < 6; i += 2) {
740 u32 low, high;
741
742 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
743 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
744 tg3_wait_macro_done(tp)) {
745 *resetp = 1;
746 return -EBUSY;
747 }
748 low &= 0x7fff;
749 high &= 0x000f;
750 if (low != test_pat[chan][i] ||
751 high != test_pat[chan][i+1]) {
752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
753 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
754 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
755
756 return -EBUSY;
757 }
758 }
759 }
760
761 return 0;
762}
763
764static int tg3_phy_reset_chanpat(struct tg3 *tp)
765{
766 int chan;
767
768 for (chan = 0; chan < 4; chan++) {
769 int i;
770
771 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
772 (chan * 0x2000) | 0x0200);
773 tg3_writephy(tp, 0x16, 0x0002);
774 for (i = 0; i < 6; i++)
775 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
776 tg3_writephy(tp, 0x16, 0x0202);
777 if (tg3_wait_macro_done(tp))
778 return -EBUSY;
779 }
780
781 return 0;
782}
783
784static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
785{
786 u32 reg32, phy9_orig;
787 int retries, do_phy_reset, err;
788
789 retries = 10;
790 do_phy_reset = 1;
791 do {
792 if (do_phy_reset) {
793 err = tg3_bmcr_reset(tp);
794 if (err)
795 return err;
796 do_phy_reset = 0;
797 }
798
799 /* Disable transmitter and interrupt. */
800 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
801 continue;
802
803 reg32 |= 0x3000;
804 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
805
806 /* Set full-duplex, 1000 mbps. */
807 tg3_writephy(tp, MII_BMCR,
808 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
809
810 /* Set to master mode. */
811 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
812 continue;
813
814 tg3_writephy(tp, MII_TG3_CTRL,
815 (MII_TG3_CTRL_AS_MASTER |
816 MII_TG3_CTRL_ENABLE_AS_MASTER));
817
818 /* Enable SM_DSP_CLOCK and 6dB. */
819 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
820
821 /* Block the PHY control access. */
822 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
823 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
824
825 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
826 if (!err)
827 break;
828 } while (--retries);
829
830 err = tg3_phy_reset_chanpat(tp);
831 if (err)
832 return err;
833
834 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
835 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
836
837 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
838 tg3_writephy(tp, 0x16, 0x0000);
839
840 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
841 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
842 /* Set Extended packet length bit for jumbo frames */
843 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
844 }
845 else {
846 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
847 }
848
849 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
850
851 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
852 reg32 &= ~0x3000;
853 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
854 } else if (!err)
855 err = -EBUSY;
856
857 return err;
858}
859
860/* This will reset the tigon3 PHY if there is no valid
861 * link unless the FORCE argument is non-zero.
862 */
863static int tg3_phy_reset(struct tg3 *tp)
864{
865 u32 phy_status;
866 int err;
867
868 err = tg3_readphy(tp, MII_BMSR, &phy_status);
869 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
870 if (err != 0)
871 return -EBUSY;
872
873 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
874 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
876 err = tg3_phy_reset_5703_4_5(tp);
877 if (err)
878 return err;
879 goto out;
880 }
881
882 err = tg3_bmcr_reset(tp);
883 if (err)
884 return err;
885
886out:
887 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
888 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
889 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
890 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
891 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
892 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
893 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
894 }
895 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
896 tg3_writephy(tp, 0x1c, 0x8d68);
897 tg3_writephy(tp, 0x1c, 0x8d68);
898 }
899 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
900 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
901 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
902 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
903 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
904 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
905 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
906 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
908 }
909 /* Set Extended packet length bit (bit 14) on all chips that */
910 /* support jumbo frames */
911 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
912 /* Cannot do read-modify-write on 5401 */
913 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
fcf02693 914 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1da177e4
LT		 915 u32 phy_reg;
916
917 /* Set bit 14 with read-modify-write to preserve other bits */
918 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
919 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
920 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
921 }
922
923 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
924 * jumbo frames transmission.
925 */
fcf02693 926 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1da177e4
LT		 927 u32 phy_reg;
928
929 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
930 tg3_writephy(tp, MII_TG3_EXT_CTRL,
931 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
932 }
933
934 tg3_phy_set_wirespeed(tp);
935 return 0;
936}
937
938static void tg3_frob_aux_power(struct tg3 *tp)
939{
940 struct tg3 *tp_peer = tp;
941
942 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
943 return;
944
945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
946 tp_peer = pci_get_drvdata(tp->pdev_peer);
947 if (!tp_peer)
948 BUG();
949 }
950
951
952 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
953 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
956 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
957 (GRC_LCLCTRL_GPIO_OE0 |
958 GRC_LCLCTRL_GPIO_OE1 |
959 GRC_LCLCTRL_GPIO_OE2 |
960 GRC_LCLCTRL_GPIO_OUTPUT0 |
961 GRC_LCLCTRL_GPIO_OUTPUT1));
962 udelay(100);
963 } else {
964 u32 no_gpio2;
965 u32 grc_local_ctrl;
966
967 if (tp_peer != tp &&
968 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
969 return;
970
971 /* On 5753 and variants, GPIO2 cannot be used. */
972 no_gpio2 = tp->nic_sram_data_cfg &
973 NIC_SRAM_DATA_CFG_NO_GPIO2;
974
975 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
976 GRC_LCLCTRL_GPIO_OE1 |
977 GRC_LCLCTRL_GPIO_OE2 |
978 GRC_LCLCTRL_GPIO_OUTPUT1 |
979 GRC_LCLCTRL_GPIO_OUTPUT2;
980 if (no_gpio2) {
981 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
982 GRC_LCLCTRL_GPIO_OUTPUT2);
983 }
984 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
985 grc_local_ctrl);
986 udelay(100);
987
988 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
989
990 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
991 grc_local_ctrl);
992 udelay(100);
993
994 if (!no_gpio2) {
995 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
996 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
997 grc_local_ctrl);
998 udelay(100);
999 }
1000 }
1001 } else {
1002 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1003 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1004 if (tp_peer != tp &&
1005 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1006 return;
1007
1008 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1009 (GRC_LCLCTRL_GPIO_OE1 |
1010 GRC_LCLCTRL_GPIO_OUTPUT1));
1011 udelay(100);
1012
1013 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1014 (GRC_LCLCTRL_GPIO_OE1));
1015 udelay(100);
1016
1017 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1018 (GRC_LCLCTRL_GPIO_OE1 |
1019 GRC_LCLCTRL_GPIO_OUTPUT1));
1020 udelay(100);
1021 }
1022 }
1023}
1024
1025static int tg3_setup_phy(struct tg3 *, int);
1026
1027#define RESET_KIND_SHUTDOWN 0
1028#define RESET_KIND_INIT 1
1029#define RESET_KIND_SUSPEND 2
1030
1031static void tg3_write_sig_post_reset(struct tg3 *, int);
1032static int tg3_halt_cpu(struct tg3 *, u32);
1033
1034static int tg3_set_power_state(struct tg3 *tp, int state)
1035{
1036 u32 misc_host_ctrl;
1037 u16 power_control, power_caps;
1038 int pm = tp->pm_cap;
1039
1040 /* Make sure register accesses (indirect or otherwise)
1041 * will function correctly.
1042 */
1043 pci_write_config_dword(tp->pdev,
1044 TG3PCI_MISC_HOST_CTRL,
1045 tp->misc_host_ctrl);
1046
1047 pci_read_config_word(tp->pdev,
1048 pm + PCI_PM_CTRL,
1049 &power_control);
1050 power_control |= PCI_PM_CTRL_PME_STATUS;
1051 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1052 switch (state) {
1053 case 0:
1054 power_control |= 0;
1055 pci_write_config_word(tp->pdev,
1056 pm + PCI_PM_CTRL,
1057 power_control);
8c6bda1a
MC		 1058 udelay(100); /* Delay after power state change */
1059
1060 /* Switch out of Vaux if it is not a LOM */
1061 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1062 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1063 udelay(100);
1064 }
1da177e4
LT		 1065
1066 return 0;
1067
1068 case 1:
1069 power_control |= 1;
1070 break;
1071
1072 case 2:
1073 power_control |= 2;
1074 break;
1075
1076 case 3:
1077 power_control |= 3;
1078 break;
1079
1080 default:
1081 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1082 "requested.\n",
1083 tp->dev->name, state);
1084 return -EINVAL;
1085 };
1086
1087 power_control |= PCI_PM_CTRL_PME_ENABLE;
1088
1089 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1090 tw32(TG3PCI_MISC_HOST_CTRL,
1091 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1092
1093 if (tp->link_config.phy_is_low_power == 0) {
1094 tp->link_config.phy_is_low_power = 1;
1095 tp->link_config.orig_speed = tp->link_config.speed;
1096 tp->link_config.orig_duplex = tp->link_config.duplex;
1097 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1098 }
1099
1100 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1101 tp->link_config.speed = SPEED_10;
1102 tp->link_config.duplex = DUPLEX_HALF;
1103 tp->link_config.autoneg = AUTONEG_ENABLE;
1104 tg3_setup_phy(tp, 0);
1105 }
1106
1107 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1108
1109 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1110 u32 mac_mode;
1111
1112 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1113 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1114 udelay(40);
1115
1116 mac_mode = MAC_MODE_PORT_MODE_MII;
1117
1118 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1119 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1120 mac_mode |= MAC_MODE_LINK_POLARITY;
1121 } else {
1122 mac_mode = MAC_MODE_PORT_MODE_TBI;
1123 }
1124
cbf46853 1125 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1126 tw32(MAC_LED_CTRL, tp->led_ctrl);
1127
1128 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1129 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1130 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1131
1132 tw32_f(MAC_MODE, mac_mode);
1133 udelay(100);
1134
1135 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1136 udelay(10);
1137 }
1138
1139 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1140 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1141 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1142 u32 base_val;
1143
1144 base_val = tp->pci_clock_ctrl;
1145 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1146 CLOCK_CTRL_TXCLK_DISABLE);
1147
1148 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1149 CLOCK_CTRL_ALTCLK |
1150 CLOCK_CTRL_PWRDOWN_PLL133);
1151 udelay(40);
85e94ced 1152 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1153 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1154 u32 newbits1, newbits2;
1155
1156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1158 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1159 CLOCK_CTRL_TXCLK_DISABLE |
1160 CLOCK_CTRL_ALTCLK);
1161 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1162 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1163 newbits1 = CLOCK_CTRL_625_CORE;
1164 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1165 } else {
1166 newbits1 = CLOCK_CTRL_ALTCLK;
1167 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1168 }
1169
1170 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1171 udelay(40);
1172
1173 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1174 udelay(40);
1175
1176 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1177 u32 newbits3;
1178
1179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1180 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1181 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1182 CLOCK_CTRL_TXCLK_DISABLE |
1183 CLOCK_CTRL_44MHZ_CORE);
1184 } else {
1185 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1186 }
1187
1188 tw32_f(TG3PCI_CLOCK_CTRL,
1189 tp->pci_clock_ctrl | newbits3);
1190 udelay(40);
1191 }
1192 }
1193
1194 tg3_frob_aux_power(tp);
1195
1196 /* Workaround for unstable PLL clock */
1197 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1198 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1199 u32 val = tr32(0x7d00);
1200
1201 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1202 tw32(0x7d00, val);
1203 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1204 tg3_halt_cpu(tp, RX_CPU_BASE);
1205 }
1206
1207 /* Finally, set the new power state. */
1208 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1209 udelay(100); /* Delay after power state change */
1da177e4
LT		 1210
1211 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1212
1213 return 0;
1214}
1215
1216static void tg3_link_report(struct tg3 *tp)
1217{
1218 if (!netif_carrier_ok(tp->dev)) {
1219 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1220 } else {
1221 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1222 tp->dev->name,
1223 (tp->link_config.active_speed == SPEED_1000 ?
1224 1000 :
1225 (tp->link_config.active_speed == SPEED_100 ?
1226 100 : 10)),
1227 (tp->link_config.active_duplex == DUPLEX_FULL ?
1228 "full" : "half"));
1229
1230 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1231 "%s for RX.\n",
1232 tp->dev->name,
1233 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1234 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1235 }
1236}
1237
1238static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1239{
1240 u32 new_tg3_flags = 0;
1241 u32 old_rx_mode = tp->rx_mode;
1242 u32 old_tx_mode = tp->tx_mode;
1243
1244 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1245 if (local_adv & ADVERTISE_PAUSE_CAP) {
1246 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1247 if (remote_adv & LPA_PAUSE_CAP)
1248 new_tg3_flags |=
1249 (TG3_FLAG_RX_PAUSE |
1250 TG3_FLAG_TX_PAUSE);
1251 else if (remote_adv & LPA_PAUSE_ASYM)
1252 new_tg3_flags |=
1253 (TG3_FLAG_RX_PAUSE);
1254 } else {
1255 if (remote_adv & LPA_PAUSE_CAP)
1256 new_tg3_flags |=
1257 (TG3_FLAG_RX_PAUSE |
1258 TG3_FLAG_TX_PAUSE);
1259 }
1260 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1261 if ((remote_adv & LPA_PAUSE_CAP) &&
1262 (remote_adv & LPA_PAUSE_ASYM))
1263 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1264 }
1265
1266 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1267 tp->tg3_flags |= new_tg3_flags;
1268 } else {
1269 new_tg3_flags = tp->tg3_flags;
1270 }
1271
1272 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1273 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1274 else
1275 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1276
1277 if (old_rx_mode != tp->rx_mode) {
1278 tw32_f(MAC_RX_MODE, tp->rx_mode);
1279 }
1280
1281 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1282 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1283 else
1284 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1285
1286 if (old_tx_mode != tp->tx_mode) {
1287 tw32_f(MAC_TX_MODE, tp->tx_mode);
1288 }
1289}
1290
1291static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1292{
1293 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1294 case MII_TG3_AUX_STAT_10HALF:
1295 *speed = SPEED_10;
1296 *duplex = DUPLEX_HALF;
1297 break;
1298
1299 case MII_TG3_AUX_STAT_10FULL:
1300 *speed = SPEED_10;
1301 *duplex = DUPLEX_FULL;
1302 break;
1303
1304 case MII_TG3_AUX_STAT_100HALF:
1305 *speed = SPEED_100;
1306 *duplex = DUPLEX_HALF;
1307 break;
1308
1309 case MII_TG3_AUX_STAT_100FULL:
1310 *speed = SPEED_100;
1311 *duplex = DUPLEX_FULL;
1312 break;
1313
1314 case MII_TG3_AUX_STAT_1000HALF:
1315 *speed = SPEED_1000;
1316 *duplex = DUPLEX_HALF;
1317 break;
1318
1319 case MII_TG3_AUX_STAT_1000FULL:
1320 *speed = SPEED_1000;
1321 *duplex = DUPLEX_FULL;
1322 break;
1323
1324 default:
1325 *speed = SPEED_INVALID;
1326 *duplex = DUPLEX_INVALID;
1327 break;
1328 };
1329}
1330
1331static void tg3_phy_copper_begin(struct tg3 *tp)
1332{
1333 u32 new_adv;
1334 int i;
1335
1336 if (tp->link_config.phy_is_low_power) {
1337 /* Entering low power mode. Disable gigabit and
1338 * 100baseT advertisements.
1339 */
1340 tg3_writephy(tp, MII_TG3_CTRL, 0);
1341
1342 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1343 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1344 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1345 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1346
1347 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1348 } else if (tp->link_config.speed == SPEED_INVALID) {
1349 tp->link_config.advertising =
1350 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1351 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1352 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1353 ADVERTISED_Autoneg | ADVERTISED_MII);
1354
1355 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1356 tp->link_config.advertising &=
1357 ~(ADVERTISED_1000baseT_Half |
1358 ADVERTISED_1000baseT_Full);
1359
1360 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1361 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1362 new_adv |= ADVERTISE_10HALF;
1363 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1364 new_adv |= ADVERTISE_10FULL;
1365 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1366 new_adv |= ADVERTISE_100HALF;
1367 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1368 new_adv |= ADVERTISE_100FULL;
1369 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1370
1371 if (tp->link_config.advertising &
1372 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1373 new_adv = 0;
1374 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1375 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1376 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1377 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1378 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1379 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1380 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1381 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1382 MII_TG3_CTRL_ENABLE_AS_MASTER);
1383 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1384 } else {
1385 tg3_writephy(tp, MII_TG3_CTRL, 0);
1386 }
1387 } else {
1388 /* Asking for a specific link mode. */
1389 if (tp->link_config.speed == SPEED_1000) {
1390 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1391 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1392
1393 if (tp->link_config.duplex == DUPLEX_FULL)
1394 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1395 else
1396 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1397 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1398 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1399 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1400 MII_TG3_CTRL_ENABLE_AS_MASTER);
1401 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1402 } else {
1403 tg3_writephy(tp, MII_TG3_CTRL, 0);
1404
1405 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1406 if (tp->link_config.speed == SPEED_100) {
1407 if (tp->link_config.duplex == DUPLEX_FULL)
1408 new_adv |= ADVERTISE_100FULL;
1409 else
1410 new_adv |= ADVERTISE_100HALF;
1411 } else {
1412 if (tp->link_config.duplex == DUPLEX_FULL)
1413 new_adv |= ADVERTISE_10FULL;
1414 else
1415 new_adv |= ADVERTISE_10HALF;
1416 }
1417 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1418 }
1419 }
1420
1421 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1422 tp->link_config.speed != SPEED_INVALID) {
1423 u32 bmcr, orig_bmcr;
1424
1425 tp->link_config.active_speed = tp->link_config.speed;
1426 tp->link_config.active_duplex = tp->link_config.duplex;
1427
1428 bmcr = 0;
1429 switch (tp->link_config.speed) {
1430 default:
1431 case SPEED_10:
1432 break;
1433
1434 case SPEED_100:
1435 bmcr |= BMCR_SPEED100;
1436 break;
1437
1438 case SPEED_1000:
1439 bmcr |= TG3_BMCR_SPEED1000;
1440 break;
1441 };
1442
1443 if (tp->link_config.duplex == DUPLEX_FULL)
1444 bmcr |= BMCR_FULLDPLX;
1445
1446 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1447 (bmcr != orig_bmcr)) {
1448 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1449 for (i = 0; i < 1500; i++) {
1450 u32 tmp;
1451
1452 udelay(10);
1453 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1454 tg3_readphy(tp, MII_BMSR, &tmp))
1455 continue;
1456 if (!(tmp & BMSR_LSTATUS)) {
1457 udelay(40);
1458 break;
1459 }
1460 }
1461 tg3_writephy(tp, MII_BMCR, bmcr);
1462 udelay(40);
1463 }
1464 } else {
1465 tg3_writephy(tp, MII_BMCR,
1466 BMCR_ANENABLE | BMCR_ANRESTART);
1467 }
1468}
1469
1470static int tg3_init_5401phy_dsp(struct tg3 *tp)
1471{
1472 int err;
1473
1474 /* Turn off tap power management. */
1475 /* Set Extended packet length bit */
1476 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1477
1478 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1479 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1480
1481 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1482 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1483
1484 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1485 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1486
1487 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1488 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1489
1490 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1491 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1492
1493 udelay(40);
1494
1495 return err;
1496}
1497
1498static int tg3_copper_is_advertising_all(struct tg3 *tp)
1499{
1500 u32 adv_reg, all_mask;
1501
1502 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1503 return 0;
1504
1505 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1506 ADVERTISE_100HALF | ADVERTISE_100FULL);
1507 if ((adv_reg & all_mask) != all_mask)
1508 return 0;
1509 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1510 u32 tg3_ctrl;
1511
1512 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1513 return 0;
1514
1515 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1516 MII_TG3_CTRL_ADV_1000_FULL);
1517 if ((tg3_ctrl & all_mask) != all_mask)
1518 return 0;
1519 }
1520 return 1;
1521}
1522
1523static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1524{
1525 int current_link_up;
1526 u32 bmsr, dummy;
1527 u16 current_speed;
1528 u8 current_duplex;
1529 int i, err;
1530
1531 tw32(MAC_EVENT, 0);
1532
1533 tw32_f(MAC_STATUS,
1534 (MAC_STATUS_SYNC_CHANGED |
1535 MAC_STATUS_CFG_CHANGED |
1536 MAC_STATUS_MI_COMPLETION |
1537 MAC_STATUS_LNKSTATE_CHANGED));
1538 udelay(40);
1539
1540 tp->mi_mode = MAC_MI_MODE_BASE;
1541 tw32_f(MAC_MI_MODE, tp->mi_mode);
1542 udelay(80);
1543
1544 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1545
1546 /* Some third-party PHYs need to be reset on link going
1547 * down.
1548 */
1549 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1550 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1551 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1552 netif_carrier_ok(tp->dev)) {
1553 tg3_readphy(tp, MII_BMSR, &bmsr);
1554 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1555 !(bmsr & BMSR_LSTATUS))
1556 force_reset = 1;
1557 }
1558 if (force_reset)
1559 tg3_phy_reset(tp);
1560
1561 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1562 tg3_readphy(tp, MII_BMSR, &bmsr);
1563 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1564 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1565 bmsr = 0;
1566
1567 if (!(bmsr & BMSR_LSTATUS)) {
1568 err = tg3_init_5401phy_dsp(tp);
1569 if (err)
1570 return err;
1571
1572 tg3_readphy(tp, MII_BMSR, &bmsr);
1573 for (i = 0; i < 1000; i++) {
1574 udelay(10);
1575 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1576 (bmsr & BMSR_LSTATUS)) {
1577 udelay(40);
1578 break;
1579 }
1580 }
1581
1582 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1583 !(bmsr & BMSR_LSTATUS) &&
1584 tp->link_config.active_speed == SPEED_1000) {
1585 err = tg3_phy_reset(tp);
1586 if (!err)
1587 err = tg3_init_5401phy_dsp(tp);
1588 if (err)
1589 return err;
1590 }
1591 }
1592 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1593 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1594 /* 5701 {A0,B0} CRC bug workaround */
1595 tg3_writephy(tp, 0x15, 0x0a75);
1596 tg3_writephy(tp, 0x1c, 0x8c68);
1597 tg3_writephy(tp, 0x1c, 0x8d68);
1598 tg3_writephy(tp, 0x1c, 0x8c68);
1599 }
1600
1601 /* Clear pending interrupts... */
1602 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1603 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1604
1605 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1606 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1607 else
1608 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1609
1610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1611 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1612 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1613 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1614 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1615 else
1616 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1617 }
1618
1619 current_link_up = 0;
1620 current_speed = SPEED_INVALID;
1621 current_duplex = DUPLEX_INVALID;
1622
1623 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1624 u32 val;
1625
1626 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1627 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1628 if (!(val & (1 << 10))) {
1629 val |= (1 << 10);
1630 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1631 goto relink;
1632 }
1633 }
1634
1635 bmsr = 0;
1636 for (i = 0; i < 100; i++) {
1637 tg3_readphy(tp, MII_BMSR, &bmsr);
1638 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1639 (bmsr & BMSR_LSTATUS))
1640 break;
1641 udelay(40);
1642 }
1643
1644 if (bmsr & BMSR_LSTATUS) {
1645 u32 aux_stat, bmcr;
1646
1647 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1648 for (i = 0; i < 2000; i++) {
1649 udelay(10);
1650 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1651 aux_stat)
1652 break;
1653 }
1654
1655 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1656 &current_speed,
1657 &current_duplex);
1658
1659 bmcr = 0;
1660 for (i = 0; i < 200; i++) {
1661 tg3_readphy(tp, MII_BMCR, &bmcr);
1662 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1663 continue;
1664 if (bmcr && bmcr != 0x7fff)
1665 break;
1666 udelay(10);
1667 }
1668
1669 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1670 if (bmcr & BMCR_ANENABLE) {
1671 current_link_up = 1;
1672
1673 /* Force autoneg restart if we are exiting
1674 * low power mode.
1675 */
1676 if (!tg3_copper_is_advertising_all(tp))
1677 current_link_up = 0;
1678 } else {
1679 current_link_up = 0;
1680 }
1681 } else {
1682 if (!(bmcr & BMCR_ANENABLE) &&
1683 tp->link_config.speed == current_speed &&
1684 tp->link_config.duplex == current_duplex) {
1685 current_link_up = 1;
1686 } else {
1687 current_link_up = 0;
1688 }
1689 }
1690
1691 tp->link_config.active_speed = current_speed;
1692 tp->link_config.active_duplex = current_duplex;
1693 }
1694
1695 if (current_link_up == 1 &&
1696 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1697 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1698 u32 local_adv, remote_adv;
1699
1700 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1701 local_adv = 0;
1702 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1703
1704 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1705 remote_adv = 0;
1706
1707 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1708
1709 /* If we are not advertising full pause capability,
1710 * something is wrong. Bring the link down and reconfigure.
1711 */
1712 if (local_adv != ADVERTISE_PAUSE_CAP) {
1713 current_link_up = 0;
1714 } else {
1715 tg3_setup_flow_control(tp, local_adv, remote_adv);
1716 }
1717 }
1718relink:
1719 if (current_link_up == 0) {
1720 u32 tmp;
1721
1722 tg3_phy_copper_begin(tp);
1723
1724 tg3_readphy(tp, MII_BMSR, &tmp);
1725 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1726 (tmp & BMSR_LSTATUS))
1727 current_link_up = 1;
1728 }
1729
1730 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1731 if (current_link_up == 1) {
1732 if (tp->link_config.active_speed == SPEED_100 ||
1733 tp->link_config.active_speed == SPEED_10)
1734 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1735 else
1736 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1737 } else
1738 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1739
1740 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1741 if (tp->link_config.active_duplex == DUPLEX_HALF)
1742 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1743
1744 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1746 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1747 (current_link_up == 1 &&
1748 tp->link_config.active_speed == SPEED_10))
1749 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1750 } else {
1751 if (current_link_up == 1)
1752 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1753 }
1754
1755 /* ??? Without this setting Netgear GA302T PHY does not
1756 * ??? send/receive packets...
1757 */
1758 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1759 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1760 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1761 tw32_f(MAC_MI_MODE, tp->mi_mode);
1762 udelay(80);
1763 }
1764
1765 tw32_f(MAC_MODE, tp->mac_mode);
1766 udelay(40);
1767
1768 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1769 /* Polled via timer. */
1770 tw32_f(MAC_EVENT, 0);
1771 } else {
1772 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1773 }
1774 udelay(40);
1775
1776 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1777 current_link_up == 1 &&
1778 tp->link_config.active_speed == SPEED_1000 &&
1779 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1780 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1781 udelay(120);
1782 tw32_f(MAC_STATUS,
1783 (MAC_STATUS_SYNC_CHANGED |
1784 MAC_STATUS_CFG_CHANGED));
1785 udelay(40);
1786 tg3_write_mem(tp,
1787 NIC_SRAM_FIRMWARE_MBOX,
1788 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1789 }
1790
1791 if (current_link_up != netif_carrier_ok(tp->dev)) {
1792 if (current_link_up)
1793 netif_carrier_on(tp->dev);
1794 else
1795 netif_carrier_off(tp->dev);
1796 tg3_link_report(tp);
1797 }
1798
1799 return 0;
1800}
1801
1802struct tg3_fiber_aneginfo {
1803 int state;
1804#define ANEG_STATE_UNKNOWN 0
1805#define ANEG_STATE_AN_ENABLE 1
1806#define ANEG_STATE_RESTART_INIT 2
1807#define ANEG_STATE_RESTART 3
1808#define ANEG_STATE_DISABLE_LINK_OK 4
1809#define ANEG_STATE_ABILITY_DETECT_INIT 5
1810#define ANEG_STATE_ABILITY_DETECT 6
1811#define ANEG_STATE_ACK_DETECT_INIT 7
1812#define ANEG_STATE_ACK_DETECT 8
1813#define ANEG_STATE_COMPLETE_ACK_INIT 9
1814#define ANEG_STATE_COMPLETE_ACK 10
1815#define ANEG_STATE_IDLE_DETECT_INIT 11
1816#define ANEG_STATE_IDLE_DETECT 12
1817#define ANEG_STATE_LINK_OK 13
1818#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1819#define ANEG_STATE_NEXT_PAGE_WAIT 15
1820
1821 u32 flags;
1822#define MR_AN_ENABLE 0x00000001
1823#define MR_RESTART_AN 0x00000002
1824#define MR_AN_COMPLETE 0x00000004
1825#define MR_PAGE_RX 0x00000008
1826#define MR_NP_LOADED 0x00000010
1827#define MR_TOGGLE_TX 0x00000020
1828#define MR_LP_ADV_FULL_DUPLEX 0x00000040
1829#define MR_LP_ADV_HALF_DUPLEX 0x00000080
1830#define MR_LP_ADV_SYM_PAUSE 0x00000100
1831#define MR_LP_ADV_ASYM_PAUSE 0x00000200
1832#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1833#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1834#define MR_LP_ADV_NEXT_PAGE 0x00001000
1835#define MR_TOGGLE_RX 0x00002000
1836#define MR_NP_RX 0x00004000
1837
1838#define MR_LINK_OK 0x80000000
1839
1840 unsigned long link_time, cur_time;
1841
1842 u32 ability_match_cfg;
1843 int ability_match_count;
1844
1845 char ability_match, idle_match, ack_match;
1846
1847 u32 txconfig, rxconfig;
1848#define ANEG_CFG_NP 0x00000080
1849#define ANEG_CFG_ACK 0x00000040
1850#define ANEG_CFG_RF2 0x00000020
1851#define ANEG_CFG_RF1 0x00000010
1852#define ANEG_CFG_PS2 0x00000001
1853#define ANEG_CFG_PS1 0x00008000
1854#define ANEG_CFG_HD 0x00004000
1855#define ANEG_CFG_FD 0x00002000
1856#define ANEG_CFG_INVAL 0x00001f06
1857
1858};
1859#define ANEG_OK 0
1860#define ANEG_DONE 1
1861#define ANEG_TIMER_ENAB 2
1862#define ANEG_FAILED -1
1863
1864#define ANEG_STATE_SETTLE_TIME 10000
1865
1866static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1867 struct tg3_fiber_aneginfo *ap)
1868{
1869 unsigned long delta;
1870 u32 rx_cfg_reg;
1871 int ret;
1872
1873 if (ap->state == ANEG_STATE_UNKNOWN) {
1874 ap->rxconfig = 0;
1875 ap->link_time = 0;
1876 ap->cur_time = 0;
1877 ap->ability_match_cfg = 0;
1878 ap->ability_match_count = 0;
1879 ap->ability_match = 0;
1880 ap->idle_match = 0;
1881 ap->ack_match = 0;
1882 }
1883 ap->cur_time++;
1884
1885 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1886 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1887
1888 if (rx_cfg_reg != ap->ability_match_cfg) {
1889 ap->ability_match_cfg = rx_cfg_reg;
1890 ap->ability_match = 0;
1891 ap->ability_match_count = 0;
1892 } else {
1893 if (++ap->ability_match_count > 1) {
1894 ap->ability_match = 1;
1895 ap->ability_match_cfg = rx_cfg_reg;
1896 }
1897 }
1898 if (rx_cfg_reg & ANEG_CFG_ACK)
1899 ap->ack_match = 1;
1900 else
1901 ap->ack_match = 0;
1902
1903 ap->idle_match = 0;
1904 } else {
1905 ap->idle_match = 1;
1906 ap->ability_match_cfg = 0;
1907 ap->ability_match_count = 0;
1908 ap->ability_match = 0;
1909 ap->ack_match = 0;
1910
1911 rx_cfg_reg = 0;
1912 }
1913
1914 ap->rxconfig = rx_cfg_reg;
1915 ret = ANEG_OK;
1916
1917 switch(ap->state) {
1918 case ANEG_STATE_UNKNOWN:
1919 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1920 ap->state = ANEG_STATE_AN_ENABLE;
1921
1922 /* fallthru */
1923 case ANEG_STATE_AN_ENABLE:
1924 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1925 if (ap->flags & MR_AN_ENABLE) {
1926 ap->link_time = 0;
1927 ap->cur_time = 0;
1928 ap->ability_match_cfg = 0;
1929 ap->ability_match_count = 0;
1930 ap->ability_match = 0;
1931 ap->idle_match = 0;
1932 ap->ack_match = 0;
1933
1934 ap->state = ANEG_STATE_RESTART_INIT;
1935 } else {
1936 ap->state = ANEG_STATE_DISABLE_LINK_OK;
1937 }
1938 break;
1939
1940 case ANEG_STATE_RESTART_INIT:
1941 ap->link_time = ap->cur_time;
1942 ap->flags &= ~(MR_NP_LOADED);
1943 ap->txconfig = 0;
1944 tw32(MAC_TX_AUTO_NEG, 0);
1945 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1946 tw32_f(MAC_MODE, tp->mac_mode);
1947 udelay(40);
1948
1949 ret = ANEG_TIMER_ENAB;
1950 ap->state = ANEG_STATE_RESTART;
1951
1952 /* fallthru */
1953 case ANEG_STATE_RESTART:
1954 delta = ap->cur_time - ap->link_time;
1955 if (delta > ANEG_STATE_SETTLE_TIME) {
1956 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1957 } else {
1958 ret = ANEG_TIMER_ENAB;
1959 }
1960 break;
1961
1962 case ANEG_STATE_DISABLE_LINK_OK:
1963 ret = ANEG_DONE;
1964 break;
1965
1966 case ANEG_STATE_ABILITY_DETECT_INIT:
1967 ap->flags &= ~(MR_TOGGLE_TX);
1968 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1969 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1970 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1971 tw32_f(MAC_MODE, tp->mac_mode);
1972 udelay(40);
1973
1974 ap->state = ANEG_STATE_ABILITY_DETECT;
1975 break;
1976
1977 case ANEG_STATE_ABILITY_DETECT:
1978 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1979 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1980 }
1981 break;
1982
1983 case ANEG_STATE_ACK_DETECT_INIT:
1984 ap->txconfig |= ANEG_CFG_ACK;
1985 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1986 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1987 tw32_f(MAC_MODE, tp->mac_mode);
1988 udelay(40);
1989
1990 ap->state = ANEG_STATE_ACK_DETECT;
1991
1992 /* fallthru */
1993 case ANEG_STATE_ACK_DETECT:
1994 if (ap->ack_match != 0) {
1995 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1996 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1997 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1998 } else {
1999 ap->state = ANEG_STATE_AN_ENABLE;
2000 }
2001 } else if (ap->ability_match != 0 &&
2002 ap->rxconfig == 0) {
2003 ap->state = ANEG_STATE_AN_ENABLE;
2004 }
2005 break;
2006
2007 case ANEG_STATE_COMPLETE_ACK_INIT:
2008 if (ap->rxconfig & ANEG_CFG_INVAL) {
2009 ret = ANEG_FAILED;
2010 break;
2011 }
2012 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2013 MR_LP_ADV_HALF_DUPLEX |
2014 MR_LP_ADV_SYM_PAUSE |
2015 MR_LP_ADV_ASYM_PAUSE |
2016 MR_LP_ADV_REMOTE_FAULT1 |
2017 MR_LP_ADV_REMOTE_FAULT2 |
2018 MR_LP_ADV_NEXT_PAGE |
2019 MR_TOGGLE_RX |
2020 MR_NP_RX);
2021 if (ap->rxconfig & ANEG_CFG_FD)
2022 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2023 if (ap->rxconfig & ANEG_CFG_HD)
2024 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2025 if (ap->rxconfig & ANEG_CFG_PS1)
2026 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2027 if (ap->rxconfig & ANEG_CFG_PS2)
2028 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2029 if (ap->rxconfig & ANEG_CFG_RF1)
2030 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2031 if (ap->rxconfig & ANEG_CFG_RF2)
2032 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2033 if (ap->rxconfig & ANEG_CFG_NP)
2034 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2035
2036 ap->link_time = ap->cur_time;
2037
2038 ap->flags ^= (MR_TOGGLE_TX);
2039 if (ap->rxconfig & 0x0008)
2040 ap->flags |= MR_TOGGLE_RX;
2041 if (ap->rxconfig & ANEG_CFG_NP)
2042 ap->flags |= MR_NP_RX;
2043 ap->flags |= MR_PAGE_RX;
2044
2045 ap->state = ANEG_STATE_COMPLETE_ACK;
2046 ret = ANEG_TIMER_ENAB;
2047 break;
2048
2049 case ANEG_STATE_COMPLETE_ACK:
2050 if (ap->ability_match != 0 &&
2051 ap->rxconfig == 0) {
2052 ap->state = ANEG_STATE_AN_ENABLE;
2053 break;
2054 }
2055 delta = ap->cur_time - ap->link_time;
2056 if (delta > ANEG_STATE_SETTLE_TIME) {
2057 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2058 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2059 } else {
2060 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2061 !(ap->flags & MR_NP_RX)) {
2062 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2063 } else {
2064 ret = ANEG_FAILED;
2065 }
2066 }
2067 }
2068 break;
2069
2070 case ANEG_STATE_IDLE_DETECT_INIT:
2071 ap->link_time = ap->cur_time;
2072 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2073 tw32_f(MAC_MODE, tp->mac_mode);
2074 udelay(40);
2075
2076 ap->state = ANEG_STATE_IDLE_DETECT;
2077 ret = ANEG_TIMER_ENAB;
2078 break;
2079
2080 case ANEG_STATE_IDLE_DETECT:
2081 if (ap->ability_match != 0 &&
2082 ap->rxconfig == 0) {
2083 ap->state = ANEG_STATE_AN_ENABLE;
2084 break;
2085 }
2086 delta = ap->cur_time - ap->link_time;
2087 if (delta > ANEG_STATE_SETTLE_TIME) {
2088 /* XXX another gem from the Broadcom driver :( */
2089 ap->state = ANEG_STATE_LINK_OK;
2090 }
2091 break;
2092
2093 case ANEG_STATE_LINK_OK:
2094 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2095 ret = ANEG_DONE;
2096 break;
2097
2098 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2099 /* ??? unimplemented */
2100 break;
2101
2102 case ANEG_STATE_NEXT_PAGE_WAIT:
2103 /* ??? unimplemented */
2104 break;
2105
2106 default:
2107 ret = ANEG_FAILED;
2108 break;
2109 };
2110
2111 return ret;
2112}
2113
2114static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2115{
2116 int res = 0;
2117 struct tg3_fiber_aneginfo aninfo;
2118 int status = ANEG_FAILED;
2119 unsigned int tick;
2120 u32 tmp;
2121
2122 tw32_f(MAC_TX_AUTO_NEG, 0);
2123
2124 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2125 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2126 udelay(40);
2127
2128 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2129 udelay(40);
2130
2131 memset(&aninfo, 0, sizeof(aninfo));
2132 aninfo.flags |= MR_AN_ENABLE;
2133 aninfo.state = ANEG_STATE_UNKNOWN;
2134 aninfo.cur_time = 0;
2135 tick = 0;
2136 while (++tick < 195000) {
2137 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2138 if (status == ANEG_DONE || status == ANEG_FAILED)
2139 break;
2140
2141 udelay(1);
2142 }
2143
2144 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2145 tw32_f(MAC_MODE, tp->mac_mode);
2146 udelay(40);
2147
2148 *flags = aninfo.flags;
2149
2150 if (status == ANEG_DONE &&
2151 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2152 MR_LP_ADV_FULL_DUPLEX)))
2153 res = 1;
2154
2155 return res;
2156}
2157
2158static void tg3_init_bcm8002(struct tg3 *tp)
2159{
2160 u32 mac_status = tr32(MAC_STATUS);
2161 int i;
2162
2163 /* Reset when initting first time or we have a link. */
2164 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2165 !(mac_status & MAC_STATUS_PCS_SYNCED))
2166 return;
2167
2168 /* Set PLL lock range. */
2169 tg3_writephy(tp, 0x16, 0x8007);
2170
2171 /* SW reset */
2172 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2173
2174 /* Wait for reset to complete. */
2175 /* XXX schedule_timeout() ... */
2176 for (i = 0; i < 500; i++)
2177 udelay(10);
2178
2179 /* Config mode; select PMA/Ch 1 regs. */
2180 tg3_writephy(tp, 0x10, 0x8411);
2181
2182 /* Enable auto-lock and comdet, select txclk for tx. */
2183 tg3_writephy(tp, 0x11, 0x0a10);
2184
2185 tg3_writephy(tp, 0x18, 0x00a0);
2186 tg3_writephy(tp, 0x16, 0x41ff);
2187
2188 /* Assert and deassert POR. */
2189 tg3_writephy(tp, 0x13, 0x0400);
2190 udelay(40);
2191 tg3_writephy(tp, 0x13, 0x0000);
2192
2193 tg3_writephy(tp, 0x11, 0x0a50);
2194 udelay(40);
2195 tg3_writephy(tp, 0x11, 0x0a10);
2196
2197 /* Wait for signal to stabilize */
2198 /* XXX schedule_timeout() ... */
2199 for (i = 0; i < 15000; i++)
2200 udelay(10);
2201
2202 /* Deselect the channel register so we can read the PHYID
2203 * later.
2204 */
2205 tg3_writephy(tp, 0x10, 0x8011);
2206}
2207
2208static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2209{
2210 u32 sg_dig_ctrl, sg_dig_status;
2211 u32 serdes_cfg, expected_sg_dig_ctrl;
2212 int workaround, port_a;
2213 int current_link_up;
2214
2215 serdes_cfg = 0;
2216 expected_sg_dig_ctrl = 0;
2217 workaround = 0;
2218 port_a = 1;
2219 current_link_up = 0;
2220
2221 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2222 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2223 workaround = 1;
2224 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2225 port_a = 0;
2226
2227 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2228 /* preserve bits 20-23 for voltage regulator */
2229 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2230 }
2231
2232 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2233
2234 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2235 if (sg_dig_ctrl & (1 << 31)) {
2236 if (workaround) {
2237 u32 val = serdes_cfg;
2238
2239 if (port_a)
2240 val |= 0xc010000;
2241 else
2242 val |= 0x4010000;
2243 tw32_f(MAC_SERDES_CFG, val);
2244 }
2245 tw32_f(SG_DIG_CTRL, 0x01388400);
2246 }
2247 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2248 tg3_setup_flow_control(tp, 0, 0);
2249 current_link_up = 1;
2250 }
2251 goto out;
2252 }
2253
2254 /* Want auto-negotiation. */
2255 expected_sg_dig_ctrl = 0x81388400;
2256
2257 /* Pause capability */
2258 expected_sg_dig_ctrl |= (1 << 11);
2259
2260 /* Asymettric pause */
2261 expected_sg_dig_ctrl |= (1 << 12);
2262
2263 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2264 if (workaround)
2265 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2266 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2267 udelay(5);
2268 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2269
2270 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2271 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2272 MAC_STATUS_SIGNAL_DET)) {
2273 int i;
2274
2275 /* Giver time to negotiate (~200ms) */
2276 for (i = 0; i < 40000; i++) {
2277 sg_dig_status = tr32(SG_DIG_STATUS);
2278 if (sg_dig_status & (0x3))
2279 break;
2280 udelay(5);
2281 }
2282 mac_status = tr32(MAC_STATUS);
2283
2284 if ((sg_dig_status & (1 << 1)) &&
2285 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2286 u32 local_adv, remote_adv;
2287
2288 local_adv = ADVERTISE_PAUSE_CAP;
2289 remote_adv = 0;
2290 if (sg_dig_status & (1 << 19))
2291 remote_adv |= LPA_PAUSE_CAP;
2292 if (sg_dig_status & (1 << 20))
2293 remote_adv |= LPA_PAUSE_ASYM;
2294
2295 tg3_setup_flow_control(tp, local_adv, remote_adv);
2296 current_link_up = 1;
2297 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2298 } else if (!(sg_dig_status & (1 << 1))) {
2299 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2300 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2301 else {
2302 if (workaround) {
2303 u32 val = serdes_cfg;
2304
2305 if (port_a)
2306 val |= 0xc010000;
2307 else
2308 val |= 0x4010000;
2309
2310 tw32_f(MAC_SERDES_CFG, val);
2311 }
2312
2313 tw32_f(SG_DIG_CTRL, 0x01388400);
2314 udelay(40);
2315
2316 /* Link parallel detection - link is up */
2317 /* only if we have PCS_SYNC and not */
2318 /* receiving config code words */
2319 mac_status = tr32(MAC_STATUS);
2320 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2321 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2322 tg3_setup_flow_control(tp, 0, 0);
2323 current_link_up = 1;
2324 }
2325 }
2326 }
2327 }
2328
2329out:
2330 return current_link_up;
2331}
2332
2333static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2334{
2335 int current_link_up = 0;
2336
2337 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2338 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2339 goto out;
2340 }
2341
2342 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2343 u32 flags;
2344 int i;
2345
2346 if (fiber_autoneg(tp, &flags)) {
2347 u32 local_adv, remote_adv;
2348
2349 local_adv = ADVERTISE_PAUSE_CAP;
2350 remote_adv = 0;
2351 if (flags & MR_LP_ADV_SYM_PAUSE)
2352 remote_adv |= LPA_PAUSE_CAP;
2353 if (flags & MR_LP_ADV_ASYM_PAUSE)
2354 remote_adv |= LPA_PAUSE_ASYM;
2355
2356 tg3_setup_flow_control(tp, local_adv, remote_adv);
2357
2358 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2359 current_link_up = 1;
2360 }
2361 for (i = 0; i < 30; i++) {
2362 udelay(20);
2363 tw32_f(MAC_STATUS,
2364 (MAC_STATUS_SYNC_CHANGED |
2365 MAC_STATUS_CFG_CHANGED));
2366 udelay(40);
2367 if ((tr32(MAC_STATUS) &
2368 (MAC_STATUS_SYNC_CHANGED |
2369 MAC_STATUS_CFG_CHANGED)) == 0)
2370 break;
2371 }
2372
2373 mac_status = tr32(MAC_STATUS);
2374 if (current_link_up == 0 &&
2375 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2376 !(mac_status & MAC_STATUS_RCVD_CFG))
2377 current_link_up = 1;
2378 } else {
2379 /* Forcing 1000FD link up. */
2380 current_link_up = 1;
2381 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2382
2383 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2384 udelay(40);
2385 }
2386
2387out:
2388 return current_link_up;
2389}
2390
2391static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2392{
2393 u32 orig_pause_cfg;
2394 u16 orig_active_speed;
2395 u8 orig_active_duplex;
2396 u32 mac_status;
2397 int current_link_up;
2398 int i;
2399
2400 orig_pause_cfg =
2401 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2402 TG3_FLAG_TX_PAUSE));
2403 orig_active_speed = tp->link_config.active_speed;
2404 orig_active_duplex = tp->link_config.active_duplex;
2405
2406 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2407 netif_carrier_ok(tp->dev) &&
2408 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2409 mac_status = tr32(MAC_STATUS);
2410 mac_status &= (MAC_STATUS_PCS_SYNCED |
2411 MAC_STATUS_SIGNAL_DET |
2412 MAC_STATUS_CFG_CHANGED |
2413 MAC_STATUS_RCVD_CFG);
2414 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2415 MAC_STATUS_SIGNAL_DET)) {
2416 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2417 MAC_STATUS_CFG_CHANGED));
2418 return 0;
2419 }
2420 }
2421
2422 tw32_f(MAC_TX_AUTO_NEG, 0);
2423
2424 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2425 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2426 tw32_f(MAC_MODE, tp->mac_mode);
2427 udelay(40);
2428
2429 if (tp->phy_id == PHY_ID_BCM8002)
2430 tg3_init_bcm8002(tp);
2431
2432 /* Enable link change event even when serdes polling. */
2433 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2434 udelay(40);
2435
2436 current_link_up = 0;
2437 mac_status = tr32(MAC_STATUS);
2438
2439 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2440 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2441 else
2442 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2443
2444 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2445 tw32_f(MAC_MODE, tp->mac_mode);
2446 udelay(40);
2447
2448 tp->hw_status->status =
2449 (SD_STATUS_UPDATED |
2450 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2451
2452 for (i = 0; i < 100; i++) {
2453 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2454 MAC_STATUS_CFG_CHANGED));
2455 udelay(5);
2456 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2457 MAC_STATUS_CFG_CHANGED)) == 0)
2458 break;
2459 }
2460
2461 mac_status = tr32(MAC_STATUS);
2462 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2463 current_link_up = 0;
2464 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2465 tw32_f(MAC_MODE, (tp->mac_mode |
2466 MAC_MODE_SEND_CONFIGS));
2467 udelay(1);
2468 tw32_f(MAC_MODE, tp->mac_mode);
2469 }
2470 }
2471
2472 if (current_link_up == 1) {
2473 tp->link_config.active_speed = SPEED_1000;
2474 tp->link_config.active_duplex = DUPLEX_FULL;
2475 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2476 LED_CTRL_LNKLED_OVERRIDE |
2477 LED_CTRL_1000MBPS_ON));
2478 } else {
2479 tp->link_config.active_speed = SPEED_INVALID;
2480 tp->link_config.active_duplex = DUPLEX_INVALID;
2481 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2482 LED_CTRL_LNKLED_OVERRIDE |
2483 LED_CTRL_TRAFFIC_OVERRIDE));
2484 }
2485
2486 if (current_link_up != netif_carrier_ok(tp->dev)) {
2487 if (current_link_up)
2488 netif_carrier_on(tp->dev);
2489 else
2490 netif_carrier_off(tp->dev);
2491 tg3_link_report(tp);
2492 } else {
2493 u32 now_pause_cfg =
2494 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2495 TG3_FLAG_TX_PAUSE);
2496 if (orig_pause_cfg != now_pause_cfg ||
2497 orig_active_speed != tp->link_config.active_speed ||
2498 orig_active_duplex != tp->link_config.active_duplex)
2499 tg3_link_report(tp);
2500 }
2501
2502 return 0;
2503}
2504
2505static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2506{
2507 int err;
2508
2509 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2510 err = tg3_setup_fiber_phy(tp, force_reset);
2511 } else {
2512 err = tg3_setup_copper_phy(tp, force_reset);
2513 }
2514
2515 if (tp->link_config.active_speed == SPEED_1000 &&
2516 tp->link_config.active_duplex == DUPLEX_HALF)
2517 tw32(MAC_TX_LENGTHS,
2518 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2519 (6 << TX_LENGTHS_IPG_SHIFT) |
2520 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2521 else
2522 tw32(MAC_TX_LENGTHS,
2523 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2524 (6 << TX_LENGTHS_IPG_SHIFT) |
2525 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2526
2527 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2528 if (netif_carrier_ok(tp->dev)) {
2529 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 2530 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 2531 } else {
2532 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2533 }
2534 }
2535
2536 return err;
2537}
2538
2539/* Tigon3 never reports partial packet sends. So we do not
2540 * need special logic to handle SKBs that have not had all
2541 * of their frags sent yet, like SunGEM does.
2542 */
2543static void tg3_tx(struct tg3 *tp)
2544{
2545 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2546 u32 sw_idx = tp->tx_cons;
2547
2548 while (sw_idx != hw_idx) {
2549 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2550 struct sk_buff *skb = ri->skb;
2551 int i;
2552
2553 if (unlikely(skb == NULL))
2554 BUG();
2555
2556 pci_unmap_single(tp->pdev,
2557 pci_unmap_addr(ri, mapping),
2558 skb_headlen(skb),
2559 PCI_DMA_TODEVICE);
2560
2561 ri->skb = NULL;
2562
2563 sw_idx = NEXT_TX(sw_idx);
2564
2565 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2566 if (unlikely(sw_idx == hw_idx))
2567 BUG();
2568
2569 ri = &tp->tx_buffers[sw_idx];
2570 if (unlikely(ri->skb != NULL))
2571 BUG();
2572
2573 pci_unmap_page(tp->pdev,
2574 pci_unmap_addr(ri, mapping),
2575 skb_shinfo(skb)->frags[i].size,
2576 PCI_DMA_TODEVICE);
2577
2578 sw_idx = NEXT_TX(sw_idx);
2579 }
2580
2581 dev_kfree_skb_irq(skb);
2582 }
2583
2584 tp->tx_cons = sw_idx;
2585
2586 if (netif_queue_stopped(tp->dev) &&
2587 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2588 netif_wake_queue(tp->dev);
2589}
2590
2591/* Returns size of skb allocated or < 0 on error.
2592 *
2593 * We only need to fill in the address because the other members
2594 * of the RX descriptor are invariant, see tg3_init_rings.
2595 *
2596 * Note the purposeful assymetry of cpu vs. chip accesses. For
2597 * posting buffers we only dirty the first cache line of the RX
2598 * descriptor (containing the address). Whereas for the RX status
2599 * buffers the cpu only reads the last cacheline of the RX descriptor
2600 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2601 */
2602static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2603 int src_idx, u32 dest_idx_unmasked)
2604{
2605 struct tg3_rx_buffer_desc *desc;
2606 struct ring_info *map, *src_map;
2607 struct sk_buff *skb;
2608 dma_addr_t mapping;
2609 int skb_size, dest_idx;
2610
2611 src_map = NULL;
2612 switch (opaque_key) {
2613 case RXD_OPAQUE_RING_STD:
2614 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2615 desc = &tp->rx_std[dest_idx];
2616 map = &tp->rx_std_buffers[dest_idx];
2617 if (src_idx >= 0)
2618 src_map = &tp->rx_std_buffers[src_idx];
2619 skb_size = RX_PKT_BUF_SZ;
2620 break;
2621
2622 case RXD_OPAQUE_RING_JUMBO:
2623 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2624 desc = &tp->rx_jumbo[dest_idx];
2625 map = &tp->rx_jumbo_buffers[dest_idx];
2626 if (src_idx >= 0)
2627 src_map = &tp->rx_jumbo_buffers[src_idx];
2628 skb_size = RX_JUMBO_PKT_BUF_SZ;
2629 break;
2630
2631 default:
2632 return -EINVAL;
2633 };
2634
2635 /* Do not overwrite any of the map or rp information
2636 * until we are sure we can commit to a new buffer.
2637 *
2638 * Callers depend upon this behavior and assume that
2639 * we leave everything unchanged if we fail.
2640 */
2641 skb = dev_alloc_skb(skb_size);
2642 if (skb == NULL)
2643 return -ENOMEM;
2644
2645 skb->dev = tp->dev;
2646 skb_reserve(skb, tp->rx_offset);
2647
2648 mapping = pci_map_single(tp->pdev, skb->data,
2649 skb_size - tp->rx_offset,
2650 PCI_DMA_FROMDEVICE);
2651
2652 map->skb = skb;
2653 pci_unmap_addr_set(map, mapping, mapping);
2654
2655 if (src_map != NULL)
2656 src_map->skb = NULL;
2657
2658 desc->addr_hi = ((u64)mapping >> 32);
2659 desc->addr_lo = ((u64)mapping & 0xffffffff);
2660
2661 return skb_size;
2662}
2663
2664/* We only need to move over in the address because the other
2665 * members of the RX descriptor are invariant. See notes above
2666 * tg3_alloc_rx_skb for full details.
2667 */
2668static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2669 int src_idx, u32 dest_idx_unmasked)
2670{
2671 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2672 struct ring_info *src_map, *dest_map;
2673 int dest_idx;
2674
2675 switch (opaque_key) {
2676 case RXD_OPAQUE_RING_STD:
2677 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2678 dest_desc = &tp->rx_std[dest_idx];
2679 dest_map = &tp->rx_std_buffers[dest_idx];
2680 src_desc = &tp->rx_std[src_idx];
2681 src_map = &tp->rx_std_buffers[src_idx];
2682 break;
2683
2684 case RXD_OPAQUE_RING_JUMBO:
2685 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2686 dest_desc = &tp->rx_jumbo[dest_idx];
2687 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2688 src_desc = &tp->rx_jumbo[src_idx];
2689 src_map = &tp->rx_jumbo_buffers[src_idx];
2690 break;
2691
2692 default:
2693 return;
2694 };
2695
2696 dest_map->skb = src_map->skb;
2697 pci_unmap_addr_set(dest_map, mapping,
2698 pci_unmap_addr(src_map, mapping));
2699 dest_desc->addr_hi = src_desc->addr_hi;
2700 dest_desc->addr_lo = src_desc->addr_lo;
2701
2702 src_map->skb = NULL;
2703}
2704
2705#if TG3_VLAN_TAG_USED
2706static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2707{
2708 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2709}
2710#endif
2711
2712/* The RX ring scheme is composed of multiple rings which post fresh
2713 * buffers to the chip, and one special ring the chip uses to report
2714 * status back to the host.
2715 *
2716 * The special ring reports the status of received packets to the
2717 * host. The chip does not write into the original descriptor the
2718 * RX buffer was obtained from. The chip simply takes the original
2719 * descriptor as provided by the host, updates the status and length
2720 * field, then writes this into the next status ring entry.
2721 *
2722 * Each ring the host uses to post buffers to the chip is described
2723 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
2724 * it is first placed into the on-chip ram. When the packet's length
2725 * is known, it walks down the TG3_BDINFO entries to select the ring.
2726 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2727 * which is within the range of the new packet's length is chosen.
2728 *
2729 * The "separate ring for rx status" scheme may sound queer, but it makes
2730 * sense from a cache coherency perspective. If only the host writes
2731 * to the buffer post rings, and only the chip writes to the rx status
2732 * rings, then cache lines never move beyond shared-modified state.
2733 * If both the host and chip were to write into the same ring, cache line
2734 * eviction could occur since both entities want it in an exclusive state.
2735 */
2736static int tg3_rx(struct tg3 *tp, int budget)
2737{
2738 u32 work_mask;
483ba50b
MC		 2739 u32 sw_idx = tp->rx_rcb_ptr;
2740 u16 hw_idx;
1da177e4
LT		 2741 int received;
2742
2743 hw_idx = tp->hw_status->idx[0].rx_producer;
2744 /*
2745 * We need to order the read of hw_idx and the read of
2746 * the opaque cookie.
2747 */
2748 rmb();
1da177e4
LT		 2749 work_mask = 0;
2750 received = 0;
2751 while (sw_idx != hw_idx && budget > 0) {
2752 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2753 unsigned int len;
2754 struct sk_buff *skb;
2755 dma_addr_t dma_addr;
2756 u32 opaque_key, desc_idx, *post_ptr;
2757
2758 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2759 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2760 if (opaque_key == RXD_OPAQUE_RING_STD) {
2761 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2762 mapping);
2763 skb = tp->rx_std_buffers[desc_idx].skb;
2764 post_ptr = &tp->rx_std_ptr;
2765 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2766 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2767 mapping);
2768 skb = tp->rx_jumbo_buffers[desc_idx].skb;
2769 post_ptr = &tp->rx_jumbo_ptr;
2770 }
2771 else {
2772 goto next_pkt_nopost;
2773 }
2774
2775 work_mask |= opaque_key;
2776
2777 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2778 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2779 drop_it:
2780 tg3_recycle_rx(tp, opaque_key,
2781 desc_idx, *post_ptr);
2782 drop_it_no_recycle:
2783 /* Other statistics kept track of by card. */
2784 tp->net_stats.rx_dropped++;
2785 goto next_pkt;
2786 }
2787
2788 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2789
2790 if (len > RX_COPY_THRESHOLD
2791 && tp->rx_offset == 2
2792 /* rx_offset != 2 iff this is a 5701 card running
2793 * in PCI-X mode [see tg3_get_invariants()] */
2794 ) {
2795 int skb_size;
2796
2797 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2798 desc_idx, *post_ptr);
2799 if (skb_size < 0)
2800 goto drop_it;
2801
2802 pci_unmap_single(tp->pdev, dma_addr,
2803 skb_size - tp->rx_offset,
2804 PCI_DMA_FROMDEVICE);
2805
2806 skb_put(skb, len);
2807 } else {
2808 struct sk_buff *copy_skb;
2809
2810 tg3_recycle_rx(tp, opaque_key,
2811 desc_idx, *post_ptr);
2812
2813 copy_skb = dev_alloc_skb(len + 2);
2814 if (copy_skb == NULL)
2815 goto drop_it_no_recycle;
2816
2817 copy_skb->dev = tp->dev;
2818 skb_reserve(copy_skb, 2);
2819 skb_put(copy_skb, len);
2820 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2821 memcpy(copy_skb->data, skb->data, len);
2822 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2823
2824 /* We'll reuse the original ring buffer. */
2825 skb = copy_skb;
2826 }
2827
2828 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2829 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2830 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2831 >> RXD_TCPCSUM_SHIFT) == 0xffff))
2832 skb->ip_summed = CHECKSUM_UNNECESSARY;
2833 else
2834 skb->ip_summed = CHECKSUM_NONE;
2835
2836 skb->protocol = eth_type_trans(skb, tp->dev);
2837#if TG3_VLAN_TAG_USED
2838 if (tp->vlgrp != NULL &&
2839 desc->type_flags & RXD_FLAG_VLAN) {
2840 tg3_vlan_rx(tp, skb,
2841 desc->err_vlan & RXD_VLAN_MASK);
2842 } else
2843#endif
2844 netif_receive_skb(skb);
2845
2846 tp->dev->last_rx = jiffies;
2847 received++;
2848 budget--;
2849
2850next_pkt:
2851 (*post_ptr)++;
2852next_pkt_nopost:
483ba50b
MC		 2853 sw_idx++;
2854 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
52f6d697
MC		 2855
2856 /* Refresh hw_idx to see if there is new work */
2857 if (sw_idx == hw_idx) {
2858 hw_idx = tp->hw_status->idx[0].rx_producer;
2859 rmb();
2860 }
1da177e4
LT		 2861 }
2862
2863 /* ACK the status ring. */
483ba50b
MC		 2864 tp->rx_rcb_ptr = sw_idx;
2865 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 2866
2867 /* Refill RX ring(s). */
2868 if (work_mask & RXD_OPAQUE_RING_STD) {
2869 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2870 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2871 sw_idx);
2872 }
2873 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2874 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2875 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2876 sw_idx);
2877 }
2878 mmiowb();
2879
2880 return received;
2881}
2882
2883static int tg3_poll(struct net_device *netdev, int *budget)
2884{
2885 struct tg3 *tp = netdev_priv(netdev);
2886 struct tg3_hw_status *sblk = tp->hw_status;
2887 unsigned long flags;
2888 int done;
2889
2890 spin_lock_irqsave(&tp->lock, flags);
2891
2892 /* handle link change and other phy events */
2893 if (!(tp->tg3_flags &
2894 (TG3_FLAG_USE_LINKCHG_REG |
2895 TG3_FLAG_POLL_SERDES))) {
2896 if (sblk->status & SD_STATUS_LINK_CHG) {
2897 sblk->status = SD_STATUS_UPDATED |
2898 (sblk->status & ~SD_STATUS_LINK_CHG);
2899 tg3_setup_phy(tp, 0);
2900 }
2901 }
2902
2903 /* run TX completion thread */
2904 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2905 spin_lock(&tp->tx_lock);
2906 tg3_tx(tp);
2907 spin_unlock(&tp->tx_lock);
2908 }
2909
2910 spin_unlock_irqrestore(&tp->lock, flags);
2911
2912 /* run RX thread, within the bounds set by NAPI.
2913 * All RX "locking" is done by ensuring outside
2914 * code synchronizes with dev->poll()
2915 */
1da177e4
LT		 2916 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2917 int orig_budget = *budget;
2918 int work_done;
2919
2920 if (orig_budget > netdev->quota)
2921 orig_budget = netdev->quota;
2922
2923 work_done = tg3_rx(tp, orig_budget);
2924
2925 *budget -= work_done;
2926 netdev->quota -= work_done;
1da177e4
LT		 2927 }
2928
f7383c22
DM		 2929 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
2930 tp->last_tag = sblk->status_tag;
2931 rmb();
2932
1da177e4 2933 /* if no more work, tell net stack and NIC we're done */
f7383c22 2934 done = !tg3_has_work(tp);
1da177e4
LT		 2935 if (done) {
2936 spin_lock_irqsave(&tp->lock, flags);
2937 __netif_rx_complete(netdev);
2938 tg3_restart_ints(tp);
2939 spin_unlock_irqrestore(&tp->lock, flags);
2940 }
2941
2942 return (done ? 0 : 1);
2943}
2944
88b06bc2
MC		 2945/* MSI ISR - No need to check for interrupt sharing and no need to
2946 * flush status block and interrupt mailbox. PCI ordering rules
2947 * guarantee that MSI will arrive after the status block.
2948 */
2949static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2950{
2951 struct net_device *dev = dev_id;
2952 struct tg3 *tp = netdev_priv(dev);
2953 struct tg3_hw_status *sblk = tp->hw_status;
2954 unsigned long flags;
2955
2956 spin_lock_irqsave(&tp->lock, flags);
2957
2958 /*
fac9b83e 2959 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 2960 * chip-internal interrupt pending events.
fac9b83e 2961 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 2962 * NIC to stop sending us irqs, engaging "in-intr-handler"
2963 * event coalescing.
2964 */
2965 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
fac9b83e 2966 tp->last_tag = sblk->status_tag;
88b06bc2 2967 sblk->status &= ~SD_STATUS_UPDATED;
04237ddd 2968 if (likely(tg3_has_work(tp)))
88b06bc2
MC		 2969 netif_rx_schedule(dev); /* schedule NAPI poll */
2970 else {
fac9b83e 2971 /* No work, re-enable interrupts. */
88b06bc2 2972 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 2973 tp->last_tag << 24);
88b06bc2
MC		 2974 }
2975
2976 spin_unlock_irqrestore(&tp->lock, flags);
2977
2978 return IRQ_RETVAL(1);
2979}
2980
1da177e4
LT		 2981static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2982{
2983 struct net_device *dev = dev_id;
2984 struct tg3 *tp = netdev_priv(dev);
2985 struct tg3_hw_status *sblk = tp->hw_status;
2986 unsigned long flags;
2987 unsigned int handled = 1;
2988
2989 spin_lock_irqsave(&tp->lock, flags);
2990
2991 /* In INTx mode, it is possible for the interrupt to arrive at
2992 * the CPU before the status block posted prior to the interrupt.
2993 * Reading the PCI State register will confirm whether the
2994 * interrupt is ours and will flush the status block.
2995 */
2996 if ((sblk->status & SD_STATUS_UPDATED) ||
2997 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2998 /*
fac9b83e 2999 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 3000 * chip-internal interrupt pending events.
fac9b83e 3001 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 3002 * NIC to stop sending us irqs, engaging "in-intr-handler"
3003 * event coalescing.
3004 */
3005 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3006 0x00000001);
fac9b83e
DM		 3007 sblk->status &= ~SD_STATUS_UPDATED;
3008 if (likely(tg3_has_work(tp)))
3009 netif_rx_schedule(dev); /* schedule NAPI poll */
3010 else {
3011 /* No work, shared interrupt perhaps? re-enable
3012 * interrupts, and flush that PCI write
3013 */
3014 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3015 0x00000000);
3016 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3017 }
3018 } else { /* shared interrupt */
3019 handled = 0;
3020 }
3021
3022 spin_unlock_irqrestore(&tp->lock, flags);
3023
3024 return IRQ_RETVAL(handled);
3025}
3026
3027static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3028{
3029 struct net_device *dev = dev_id;
3030 struct tg3 *tp = netdev_priv(dev);
3031 struct tg3_hw_status *sblk = tp->hw_status;
3032 unsigned long flags;
3033 unsigned int handled = 1;
3034
3035 spin_lock_irqsave(&tp->lock, flags);
3036
3037 /* In INTx mode, it is possible for the interrupt to arrive at
3038 * the CPU before the status block posted prior to the interrupt.
3039 * Reading the PCI State register will confirm whether the
3040 * interrupt is ours and will flush the status block.
3041 */
3042 if ((sblk->status & SD_STATUS_UPDATED) ||
3043 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3044 /*
fac9b83e
DM		 3045 * writing any value to intr-mbox-0 clears PCI INTA# and
3046 * chip-internal interrupt pending events.
3047 * writing non-zero to intr-mbox-0 additional tells the
3048 * NIC to stop sending us irqs, engaging "in-intr-handler"
3049 * event coalescing.
1da177e4 3050 */
fac9b83e
DM		 3051 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3052 0x00000001);
3053 tp->last_tag = sblk->status_tag;
1da177e4 3054 sblk->status &= ~SD_STATUS_UPDATED;
04237ddd 3055 if (likely(tg3_has_work(tp)))
1da177e4
LT		 3056 netif_rx_schedule(dev); /* schedule NAPI poll */
3057 else {
3058 /* no work, shared interrupt perhaps? re-enable
3059 * interrupts, and flush that PCI write
3060 */
3061 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3062 tp->last_tag << 24);
1da177e4
LT		 3063 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3064 }
3065 } else { /* shared interrupt */
3066 handled = 0;
3067 }
3068
3069 spin_unlock_irqrestore(&tp->lock, flags);
3070
3071 return IRQ_RETVAL(handled);
3072}
3073
7938109f
MC		 3074/* ISR for interrupt test */
3075static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3076 struct pt_regs *regs)
3077{
3078 struct net_device *dev = dev_id;
3079 struct tg3 *tp = netdev_priv(dev);
3080 struct tg3_hw_status *sblk = tp->hw_status;
3081
3082 if (sblk->status & SD_STATUS_UPDATED) {
3083 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3084 0x00000001);
3085 return IRQ_RETVAL(1);
3086 }
3087 return IRQ_RETVAL(0);
3088}
3089
1da177e4 3090static int tg3_init_hw(struct tg3 *);
944d980e 3091static int tg3_halt(struct tg3 *, int, int);
1da177e4
LT		 3092
3093#ifdef CONFIG_NET_POLL_CONTROLLER
3094static void tg3_poll_controller(struct net_device *dev)
3095{
88b06bc2
MC		 3096 struct tg3 *tp = netdev_priv(dev);
3097
3098 tg3_interrupt(tp->pdev->irq, dev, NULL);
1da177e4
LT		 3099}
3100#endif
3101
3102static void tg3_reset_task(void *_data)
3103{
3104 struct tg3 *tp = _data;
3105 unsigned int restart_timer;
3106
3107 tg3_netif_stop(tp);
3108
3109 spin_lock_irq(&tp->lock);
3110 spin_lock(&tp->tx_lock);
3111
3112 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3113 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3114
944d980e 3115 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
1da177e4
LT		 3116 tg3_init_hw(tp);
3117
3118 tg3_netif_start(tp);
3119
3120 spin_unlock(&tp->tx_lock);
3121 spin_unlock_irq(&tp->lock);
3122
3123 if (restart_timer)
3124 mod_timer(&tp->timer, jiffies + 1);
3125}
3126
3127static void tg3_tx_timeout(struct net_device *dev)
3128{
3129 struct tg3 *tp = netdev_priv(dev);
3130
3131 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3132 dev->name);
3133
3134 schedule_work(&tp->reset_task);
3135}
3136
3137static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3138
3139static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3140 u32 guilty_entry, int guilty_len,
3141 u32 last_plus_one, u32 *start, u32 mss)
3142{
3143 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3144 dma_addr_t new_addr;
3145 u32 entry = *start;
3146 int i;
3147
3148 if (!new_skb) {
3149 dev_kfree_skb(skb);
3150 return -1;
3151 }
3152
3153 /* New SKB is guaranteed to be linear. */
3154 entry = *start;
3155 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3156 PCI_DMA_TODEVICE);
3157 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3158 (skb->ip_summed == CHECKSUM_HW) ?
3159 TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3160 *start = NEXT_TX(entry);
3161
3162 /* Now clean up the sw ring entries. */
3163 i = 0;
3164 while (entry != last_plus_one) {
3165 int len;
3166
3167 if (i == 0)
3168 len = skb_headlen(skb);
3169 else
3170 len = skb_shinfo(skb)->frags[i-1].size;
3171 pci_unmap_single(tp->pdev,
3172 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3173 len, PCI_DMA_TODEVICE);
3174 if (i == 0) {
3175 tp->tx_buffers[entry].skb = new_skb;
3176 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3177 } else {
3178 tp->tx_buffers[entry].skb = NULL;
3179 }
3180 entry = NEXT_TX(entry);
3181 i++;
3182 }
3183
3184 dev_kfree_skb(skb);
3185
3186 return 0;
3187}
3188
3189static void tg3_set_txd(struct tg3 *tp, int entry,
3190 dma_addr_t mapping, int len, u32 flags,
3191 u32 mss_and_is_end)
3192{
3193 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3194 int is_end = (mss_and_is_end & 0x1);
3195 u32 mss = (mss_and_is_end >> 1);
3196 u32 vlan_tag = 0;
3197
3198 if (is_end)
3199 flags |= TXD_FLAG_END;
3200 if (flags & TXD_FLAG_VLAN) {
3201 vlan_tag = flags >> 16;
3202 flags &= 0xffff;
3203 }
3204 vlan_tag |= (mss << TXD_MSS_SHIFT);
3205
3206 txd->addr_hi = ((u64) mapping >> 32);
3207 txd->addr_lo = ((u64) mapping & 0xffffffff);
3208 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3209 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3210}
3211
3212static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3213{
3214 u32 base = (u32) mapping & 0xffffffff;
3215
3216 return ((base > 0xffffdcc0) &&
3217 (base + len + 8 < base));
3218}
3219
3220static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3221{
3222 struct tg3 *tp = netdev_priv(dev);
3223 dma_addr_t mapping;
3224 unsigned int i;
3225 u32 len, entry, base_flags, mss;
3226 int would_hit_hwbug;
3227 unsigned long flags;
3228
3229 len = skb_headlen(skb);
3230
3231 /* No BH disabling for tx_lock here. We are running in BH disabled
3232 * context and TX reclaim runs via tp->poll inside of a software
3233 * interrupt. Rejoice!
3234 *
3235 * Actually, things are not so simple. If we are to take a hw
3236 * IRQ here, we can deadlock, consider:
3237 *
3238 * CPU1 CPU2
3239 * tg3_start_xmit
3240 * take tp->tx_lock
3241 * tg3_timer
3242 * take tp->lock
3243 * tg3_interrupt
3244 * spin on tp->lock
3245 * spin on tp->tx_lock
3246 *
3247 * So we really do need to disable interrupts when taking
3248 * tx_lock here.
3249 */
3250 local_irq_save(flags);
3251 if (!spin_trylock(&tp->tx_lock)) {
3252 local_irq_restore(flags);
3253 return NETDEV_TX_LOCKED;
3254 }
3255
3256 /* This is a hard error, log it. */
3257 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3258 netif_stop_queue(dev);
3259 spin_unlock_irqrestore(&tp->tx_lock, flags);
3260 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3261 dev->name);
3262 return NETDEV_TX_BUSY;
3263 }
3264
3265 entry = tp->tx_prod;
3266 base_flags = 0;
3267 if (skb->ip_summed == CHECKSUM_HW)
3268 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3269#if TG3_TSO_SUPPORT != 0
3270 mss = 0;
3271 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3272 (mss = skb_shinfo(skb)->tso_size) != 0) {
3273 int tcp_opt_len, ip_tcp_len;
3274
3275 if (skb_header_cloned(skb) &&
3276 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3277 dev_kfree_skb(skb);
3278 goto out_unlock;
3279 }
3280
3281 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3282 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3283
3284 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3285 TXD_FLAG_CPU_POST_DMA);
3286
3287 skb->nh.iph->check = 0;
3288 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3289 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3290 skb->h.th->check = 0;
3291 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3292 }
3293 else {
3294 skb->h.th->check =
3295 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3296 skb->nh.iph->daddr,
3297 0, IPPROTO_TCP, 0);
3298 }
3299
3300 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3301 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3302 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3303 int tsflags;
3304
3305 tsflags = ((skb->nh.iph->ihl - 5) +
3306 (tcp_opt_len >> 2));
3307 mss |= (tsflags << 11);
3308 }
3309 } else {
3310 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3311 int tsflags;
3312
3313 tsflags = ((skb->nh.iph->ihl - 5) +
3314 (tcp_opt_len >> 2));
3315 base_flags |= tsflags << 12;
3316 }
3317 }
3318 }
3319#else
3320 mss = 0;
3321#endif
3322#if TG3_VLAN_TAG_USED
3323 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3324 base_flags |= (TXD_FLAG_VLAN |
3325 (vlan_tx_tag_get(skb) << 16));
3326#endif
3327
3328 /* Queue skb data, a.k.a. the main skb fragment. */
3329 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3330
3331 tp->tx_buffers[entry].skb = skb;
3332 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3333
3334 would_hit_hwbug = 0;
3335
3336 if (tg3_4g_overflow_test(mapping, len))
3337 would_hit_hwbug = entry + 1;
3338
3339 tg3_set_txd(tp, entry, mapping, len, base_flags,
3340 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3341
3342 entry = NEXT_TX(entry);
3343
3344 /* Now loop through additional data fragments, and queue them. */
3345 if (skb_shinfo(skb)->nr_frags > 0) {
3346 unsigned int i, last;
3347
3348 last = skb_shinfo(skb)->nr_frags - 1;
3349 for (i = 0; i <= last; i++) {
3350 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3351
3352 len = frag->size;
3353 mapping = pci_map_page(tp->pdev,
3354 frag->page,
3355 frag->page_offset,
3356 len, PCI_DMA_TODEVICE);
3357
3358 tp->tx_buffers[entry].skb = NULL;
3359 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3360
3361 if (tg3_4g_overflow_test(mapping, len)) {
3362 /* Only one should match. */
3363 if (would_hit_hwbug)
3364 BUG();
3365 would_hit_hwbug = entry + 1;
3366 }
3367
3368 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3369 tg3_set_txd(tp, entry, mapping, len,
3370 base_flags, (i == last)|(mss << 1));
3371 else
3372 tg3_set_txd(tp, entry, mapping, len,
3373 base_flags, (i == last));
3374
3375 entry = NEXT_TX(entry);
3376 }
3377 }
3378
3379 if (would_hit_hwbug) {
3380 u32 last_plus_one = entry;
3381 u32 start;
3382 unsigned int len = 0;
3383
3384 would_hit_hwbug -= 1;
3385 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3386 entry &= (TG3_TX_RING_SIZE - 1);
3387 start = entry;
3388 i = 0;
3389 while (entry != last_plus_one) {
3390 if (i == 0)
3391 len = skb_headlen(skb);
3392 else
3393 len = skb_shinfo(skb)->frags[i-1].size;
3394
3395 if (entry == would_hit_hwbug)
3396 break;
3397
3398 i++;
3399 entry = NEXT_TX(entry);
3400
3401 }
3402
3403 /* If the workaround fails due to memory/mapping
3404 * failure, silently drop this packet.
3405 */
3406 if (tigon3_4gb_hwbug_workaround(tp, skb,
3407 entry, len,
3408 last_plus_one,
3409 &start, mss))
3410 goto out_unlock;
3411
3412 entry = start;
3413 }
3414
3415 /* Packets are ready, update Tx producer idx local and on card. */
3416 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3417
3418 tp->tx_prod = entry;
3419 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3420 netif_stop_queue(dev);
3421
3422out_unlock:
3423 mmiowb();
3424 spin_unlock_irqrestore(&tp->tx_lock, flags);
3425
3426 dev->trans_start = jiffies;
3427
3428 return NETDEV_TX_OK;
3429}
3430
3431static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3432 int new_mtu)
3433{
3434 dev->mtu = new_mtu;
3435
3436 if (new_mtu > ETH_DATA_LEN)
3437 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3438 else
3439 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3440}
3441
3442static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3443{
3444 struct tg3 *tp = netdev_priv(dev);
3445
3446 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3447 return -EINVAL;
3448
3449 if (!netif_running(dev)) {
3450 /* We'll just catch it later when the
3451 * device is up'd.
3452 */
3453 tg3_set_mtu(dev, tp, new_mtu);
3454 return 0;
3455 }
3456
3457 tg3_netif_stop(tp);
3458 spin_lock_irq(&tp->lock);
3459 spin_lock(&tp->tx_lock);
3460
944d980e 3461 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 3462
3463 tg3_set_mtu(dev, tp, new_mtu);
3464
3465 tg3_init_hw(tp);
3466
3467 tg3_netif_start(tp);
3468
3469 spin_unlock(&tp->tx_lock);
3470 spin_unlock_irq(&tp->lock);
3471
3472 return 0;
3473}
3474
3475/* Free up pending packets in all rx/tx rings.
3476 *
3477 * The chip has been shut down and the driver detached from
3478 * the networking, so no interrupts or new tx packets will
3479 * end up in the driver. tp->{tx,}lock is not held and we are not
3480 * in an interrupt context and thus may sleep.
3481 */
3482static void tg3_free_rings(struct tg3 *tp)
3483{
3484 struct ring_info *rxp;
3485 int i;
3486
3487 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3488 rxp = &tp->rx_std_buffers[i];
3489
3490 if (rxp->skb == NULL)
3491 continue;
3492 pci_unmap_single(tp->pdev,
3493 pci_unmap_addr(rxp, mapping),
3494 RX_PKT_BUF_SZ - tp->rx_offset,
3495 PCI_DMA_FROMDEVICE);
3496 dev_kfree_skb_any(rxp->skb);
3497 rxp->skb = NULL;
3498 }
3499
3500 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3501 rxp = &tp->rx_jumbo_buffers[i];
3502
3503 if (rxp->skb == NULL)
3504 continue;
3505 pci_unmap_single(tp->pdev,
3506 pci_unmap_addr(rxp, mapping),
3507 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3508 PCI_DMA_FROMDEVICE);
3509 dev_kfree_skb_any(rxp->skb);
3510 rxp->skb = NULL;
3511 }
3512
3513 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3514 struct tx_ring_info *txp;
3515 struct sk_buff *skb;
3516 int j;
3517
3518 txp = &tp->tx_buffers[i];
3519 skb = txp->skb;
3520
3521 if (skb == NULL) {
3522 i++;
3523 continue;
3524 }
3525
3526 pci_unmap_single(tp->pdev,
3527 pci_unmap_addr(txp, mapping),
3528 skb_headlen(skb),
3529 PCI_DMA_TODEVICE);
3530 txp->skb = NULL;
3531
3532 i++;
3533
3534 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3535 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3536 pci_unmap_page(tp->pdev,
3537 pci_unmap_addr(txp, mapping),
3538 skb_shinfo(skb)->frags[j].size,
3539 PCI_DMA_TODEVICE);
3540 i++;
3541 }
3542
3543 dev_kfree_skb_any(skb);
3544 }
3545}
3546
3547/* Initialize tx/rx rings for packet processing.
3548 *
3549 * The chip has been shut down and the driver detached from
3550 * the networking, so no interrupts or new tx packets will
3551 * end up in the driver. tp->{tx,}lock are held and thus
3552 * we may not sleep.
3553 */
3554static void tg3_init_rings(struct tg3 *tp)
3555{
3556 u32 i;
3557
3558 /* Free up all the SKBs. */
3559 tg3_free_rings(tp);
3560
3561 /* Zero out all descriptors. */
3562 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3563 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3564 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3565 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3566
3567 /* Initialize invariants of the rings, we only set this
3568 * stuff once. This works because the card does not
3569 * write into the rx buffer posting rings.
3570 */
3571 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3572 struct tg3_rx_buffer_desc *rxd;
3573
3574 rxd = &tp->rx_std[i];
3575 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3576 << RXD_LEN_SHIFT;
3577 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3578 rxd->opaque = (RXD_OPAQUE_RING_STD |
3579 (i << RXD_OPAQUE_INDEX_SHIFT));
3580 }
3581
3582 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3583 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3584 struct tg3_rx_buffer_desc *rxd;
3585
3586 rxd = &tp->rx_jumbo[i];
3587 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3588 << RXD_LEN_SHIFT;
3589 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3590 RXD_FLAG_JUMBO;
3591 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3592 (i << RXD_OPAQUE_INDEX_SHIFT));
3593 }
3594 }
3595
3596 /* Now allocate fresh SKBs for each rx ring. */
3597 for (i = 0; i < tp->rx_pending; i++) {
3598 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3599 -1, i) < 0)
3600 break;
3601 }
3602
3603 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3604 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3605 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3606 -1, i) < 0)
3607 break;
3608 }
3609 }
3610}
3611
3612/*
3613 * Must not be invoked with interrupt sources disabled and
3614 * the hardware shutdown down.
3615 */
3616static void tg3_free_consistent(struct tg3 *tp)
3617{
3618 if (tp->rx_std_buffers) {
3619 kfree(tp->rx_std_buffers);
3620 tp->rx_std_buffers = NULL;
3621 }
3622 if (tp->rx_std) {
3623 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3624 tp->rx_std, tp->rx_std_mapping);
3625 tp->rx_std = NULL;
3626 }
3627 if (tp->rx_jumbo) {
3628 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3629 tp->rx_jumbo, tp->rx_jumbo_mapping);
3630 tp->rx_jumbo = NULL;
3631 }
3632 if (tp->rx_rcb) {
3633 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3634 tp->rx_rcb, tp->rx_rcb_mapping);
3635 tp->rx_rcb = NULL;
3636 }
3637 if (tp->tx_ring) {
3638 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3639 tp->tx_ring, tp->tx_desc_mapping);
3640 tp->tx_ring = NULL;
3641 }
3642 if (tp->hw_status) {
3643 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3644 tp->hw_status, tp->status_mapping);
3645 tp->hw_status = NULL;
3646 }
3647 if (tp->hw_stats) {
3648 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3649 tp->hw_stats, tp->stats_mapping);
3650 tp->hw_stats = NULL;
3651 }
3652}
3653
3654/*
3655 * Must not be invoked with interrupt sources disabled and
3656 * the hardware shutdown down. Can sleep.
3657 */
3658static int tg3_alloc_consistent(struct tg3 *tp)
3659{
3660 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3661 (TG3_RX_RING_SIZE +
3662 TG3_RX_JUMBO_RING_SIZE)) +
3663 (sizeof(struct tx_ring_info) *
3664 TG3_TX_RING_SIZE),
3665 GFP_KERNEL);
3666 if (!tp->rx_std_buffers)
3667 return -ENOMEM;
3668
3669 memset(tp->rx_std_buffers, 0,
3670 (sizeof(struct ring_info) *
3671 (TG3_RX_RING_SIZE +
3672 TG3_RX_JUMBO_RING_SIZE)) +
3673 (sizeof(struct tx_ring_info) *
3674 TG3_TX_RING_SIZE));
3675
3676 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3677 tp->tx_buffers = (struct tx_ring_info *)
3678 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3679
3680 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3681 &tp->rx_std_mapping);
3682 if (!tp->rx_std)
3683 goto err_out;
3684
3685 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3686 &tp->rx_jumbo_mapping);
3687
3688 if (!tp->rx_jumbo)
3689 goto err_out;
3690
3691 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3692 &tp->rx_rcb_mapping);
3693 if (!tp->rx_rcb)
3694 goto err_out;
3695
3696 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3697 &tp->tx_desc_mapping);
3698 if (!tp->tx_ring)
3699 goto err_out;
3700
3701 tp->hw_status = pci_alloc_consistent(tp->pdev,
3702 TG3_HW_STATUS_SIZE,
3703 &tp->status_mapping);
3704 if (!tp->hw_status)
3705 goto err_out;
3706
3707 tp->hw_stats = pci_alloc_consistent(tp->pdev,
3708 sizeof(struct tg3_hw_stats),
3709 &tp->stats_mapping);
3710 if (!tp->hw_stats)
3711 goto err_out;
3712
3713 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3714 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3715
3716 return 0;
3717
3718err_out:
3719 tg3_free_consistent(tp);
3720 return -ENOMEM;
3721}
3722
3723#define MAX_WAIT_CNT 1000
3724
3725/* To stop a block, clear the enable bit and poll till it
3726 * clears. tp->lock is held.
3727 */
b3b7d6be 3728static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 3729{
3730 unsigned int i;
3731 u32 val;
3732
3733 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3734 switch (ofs) {
3735 case RCVLSC_MODE:
3736 case DMAC_MODE:
3737 case MBFREE_MODE:
3738 case BUFMGR_MODE:
3739 case MEMARB_MODE:
3740 /* We can't enable/disable these bits of the
3741 * 5705/5750, just say success.
3742 */
3743 return 0;
3744
3745 default:
3746 break;
3747 };
3748 }
3749
3750 val = tr32(ofs);
3751 val &= ~enable_bit;
3752 tw32_f(ofs, val);
3753
3754 for (i = 0; i < MAX_WAIT_CNT; i++) {
3755 udelay(100);
3756 val = tr32(ofs);
3757 if ((val & enable_bit) == 0)
3758 break;
3759 }
3760
b3b7d6be 3761 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 3762 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3763 "ofs=%lx enable_bit=%x\n",
3764 ofs, enable_bit);
3765 return -ENODEV;
3766 }
3767
3768 return 0;
3769}
3770
3771/* tp->lock is held. */
b3b7d6be 3772static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 3773{
3774 int i, err;
3775
3776 tg3_disable_ints(tp);
3777
3778 tp->rx_mode &= ~RX_MODE_ENABLE;
3779 tw32_f(MAC_RX_MODE, tp->rx_mode);
3780 udelay(10);
3781
b3b7d6be
DM		 3782 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
3783 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
3784 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
3785 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
3786 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
3787 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
3788
3789 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
3790 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
3791 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
3792 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
3793 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
3794 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
3795 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 3796
3797 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3798 tw32_f(MAC_MODE, tp->mac_mode);
3799 udelay(40);
3800
3801 tp->tx_mode &= ~TX_MODE_ENABLE;
3802 tw32_f(MAC_TX_MODE, tp->tx_mode);
3803
3804 for (i = 0; i < MAX_WAIT_CNT; i++) {
3805 udelay(100);
3806 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3807 break;
3808 }
3809 if (i >= MAX_WAIT_CNT) {
3810 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3811 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3812 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 3813 err |= -ENODEV;
1da177e4
LT		 3814 }
3815
e6de8ad1 3816 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 3817 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
3818 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 3819
3820 tw32(FTQ_RESET, 0xffffffff);
3821 tw32(FTQ_RESET, 0x00000000);
3822
b3b7d6be
DM		 3823 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
3824 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 3825
3826 if (tp->hw_status)
3827 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3828 if (tp->hw_stats)
3829 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3830
1da177e4
LT		 3831 return err;
3832}
3833
3834/* tp->lock is held. */
3835static int tg3_nvram_lock(struct tg3 *tp)
3836{
3837 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3838 int i;
3839
3840 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3841 for (i = 0; i < 8000; i++) {
3842 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3843 break;
3844 udelay(20);
3845 }
3846 if (i == 8000)
3847 return -ENODEV;
3848 }
3849 return 0;
3850}
3851
3852/* tp->lock is held. */
3853static void tg3_nvram_unlock(struct tg3 *tp)
3854{
3855 if (tp->tg3_flags & TG3_FLAG_NVRAM)
3856 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3857}
3858
e6af301b
MC		 3859/* tp->lock is held. */
3860static void tg3_enable_nvram_access(struct tg3 *tp)
3861{
3862 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3863 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3864 u32 nvaccess = tr32(NVRAM_ACCESS);
3865
3866 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3867 }
3868}
3869
3870/* tp->lock is held. */
3871static void tg3_disable_nvram_access(struct tg3 *tp)
3872{
3873 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3874 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3875 u32 nvaccess = tr32(NVRAM_ACCESS);
3876
3877 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3878 }
3879}
3880
1da177e4
LT		 3881/* tp->lock is held. */
3882static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3883{
3884 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3885 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3886 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3887
3888 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3889 switch (kind) {
3890 case RESET_KIND_INIT:
3891 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3892 DRV_STATE_START);
3893 break;
3894
3895 case RESET_KIND_SHUTDOWN:
3896 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3897 DRV_STATE_UNLOAD);
3898 break;
3899
3900 case RESET_KIND_SUSPEND:
3901 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3902 DRV_STATE_SUSPEND);
3903 break;
3904
3905 default:
3906 break;
3907 };
3908 }
3909}
3910
3911/* tp->lock is held. */
3912static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3913{
3914 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3915 switch (kind) {
3916 case RESET_KIND_INIT:
3917 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3918 DRV_STATE_START_DONE);
3919 break;
3920
3921 case RESET_KIND_SHUTDOWN:
3922 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3923 DRV_STATE_UNLOAD_DONE);
3924 break;
3925
3926 default:
3927 break;
3928 };
3929 }
3930}
3931
3932/* tp->lock is held. */
3933static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3934{
3935 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3936 switch (kind) {
3937 case RESET_KIND_INIT:
3938 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3939 DRV_STATE_START);
3940 break;
3941
3942 case RESET_KIND_SHUTDOWN:
3943 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3944 DRV_STATE_UNLOAD);
3945 break;
3946
3947 case RESET_KIND_SUSPEND:
3948 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3949 DRV_STATE_SUSPEND);
3950 break;
3951
3952 default:
3953 break;
3954 };
3955 }
3956}
3957
3958static void tg3_stop_fw(struct tg3 *);
3959
3960/* tp->lock is held. */
3961static int tg3_chip_reset(struct tg3 *tp)
3962{
3963 u32 val;
3964 u32 flags_save;
3965 int i;
3966
3967 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3968 tg3_nvram_lock(tp);
3969
3970 /*
3971 * We must avoid the readl() that normally takes place.
3972 * It locks machines, causes machine checks, and other
3973 * fun things. So, temporarily disable the 5701
3974 * hardware workaround, while we do the reset.
3975 */
3976 flags_save = tp->tg3_flags;
3977 tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3978
3979 /* do the reset */
3980 val = GRC_MISC_CFG_CORECLK_RESET;
3981
3982 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3983 if (tr32(0x7e2c) == 0x60) {
3984 tw32(0x7e2c, 0x20);
3985 }
3986 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3987 tw32(GRC_MISC_CFG, (1 << 29));
3988 val |= (1 << 29);
3989 }
3990 }
3991
3992 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3993 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3994 tw32(GRC_MISC_CFG, val);
3995
3996 /* restore 5701 hardware bug workaround flag */
3997 tp->tg3_flags = flags_save;
3998
3999 /* Unfortunately, we have to delay before the PCI read back.
4000 * Some 575X chips even will not respond to a PCI cfg access
4001 * when the reset command is given to the chip.
4002 *
4003 * How do these hardware designers expect things to work
4004 * properly if the PCI write is posted for a long period
4005 * of time? It is always necessary to have some method by
4006 * which a register read back can occur to push the write
4007 * out which does the reset.
4008 *
4009 * For most tg3 variants the trick below was working.
4010 * Ho hum...
4011 */
4012 udelay(120);
4013
4014 /* Flush PCI posted writes. The normal MMIO registers
4015 * are inaccessible at this time so this is the only
4016 * way to make this reliably (actually, this is no longer
4017 * the case, see above). I tried to use indirect
4018 * register read/write but this upset some 5701 variants.
4019 */
4020 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4021
4022 udelay(120);
4023
4024 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4025 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4026 int i;
4027 u32 cfg_val;
4028
4029 /* Wait for link training to complete. */
4030 for (i = 0; i < 5000; i++)
4031 udelay(100);
4032
4033 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4034 pci_write_config_dword(tp->pdev, 0xc4,
4035 cfg_val | (1 << 15));
4036 }
4037 /* Set PCIE max payload size and clear error status. */
4038 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4039 }
4040
4041 /* Re-enable indirect register accesses. */
4042 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4043 tp->misc_host_ctrl);
4044
4045 /* Set MAX PCI retry to zero. */
4046 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4047 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4048 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4049 val |= PCISTATE_RETRY_SAME_DMA;
4050 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4051
4052 pci_restore_state(tp->pdev);
4053
4054 /* Make sure PCI-X relaxed ordering bit is clear. */
4055 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4056 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4057 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4058
4059 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4060
4061 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4062 tg3_stop_fw(tp);
4063 tw32(0x5000, 0x400);
4064 }
4065
4066 tw32(GRC_MODE, tp->grc_mode);
4067
4068 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4069 u32 val = tr32(0xc4);
4070
4071 tw32(0xc4, val | (1 << 15));
4072 }
4073
4074 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4076 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4077 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4078 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4079 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4080 }
4081
4082 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4083 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4084 tw32_f(MAC_MODE, tp->mac_mode);
4085 } else
4086 tw32_f(MAC_MODE, 0);
4087 udelay(40);
4088
4089 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4090 /* Wait for firmware initialization to complete. */
4091 for (i = 0; i < 100000; i++) {
4092 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4093 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4094 break;
4095 udelay(10);
4096 }
4097 if (i >= 100000) {
4098 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4099 "firmware will not restart magic=%08x\n",
4100 tp->dev->name, val);
4101 return -ENODEV;
4102 }
4103 }
4104
4105 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4106 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4107 u32 val = tr32(0x7c00);
4108
4109 tw32(0x7c00, val | (1 << 25));
4110 }
4111
4112 /* Reprobe ASF enable state. */
4113 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4114 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4115 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4116 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4117 u32 nic_cfg;
4118
4119 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4120 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4121 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4122 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4123 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4124 }
4125 }
4126
4127 return 0;
4128}
4129
4130/* tp->lock is held. */
4131static void tg3_stop_fw(struct tg3 *tp)
4132{
4133 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4134 u32 val;
4135 int i;
4136
4137 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4138 val = tr32(GRC_RX_CPU_EVENT);
4139 val |= (1 << 14);
4140 tw32(GRC_RX_CPU_EVENT, val);
4141
4142 /* Wait for RX cpu to ACK the event. */
4143 for (i = 0; i < 100; i++) {
4144 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4145 break;
4146 udelay(1);
4147 }
4148 }
4149}
4150
4151/* tp->lock is held. */
944d980e 4152static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 4153{
4154 int err;
4155
4156 tg3_stop_fw(tp);
4157
944d980e 4158 tg3_write_sig_pre_reset(tp, kind);
1da177e4 4159
b3b7d6be 4160 tg3_abort_hw(tp, silent);
1da177e4
LT		 4161 err = tg3_chip_reset(tp);
4162
944d980e
MC		 4163 tg3_write_sig_legacy(tp, kind);
4164 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 4165
4166 if (err)
4167 return err;
4168
4169 return 0;
4170}
4171
4172#define TG3_FW_RELEASE_MAJOR 0x0
4173#define TG3_FW_RELASE_MINOR 0x0
4174#define TG3_FW_RELEASE_FIX 0x0
4175#define TG3_FW_START_ADDR 0x08000000
4176#define TG3_FW_TEXT_ADDR 0x08000000
4177#define TG3_FW_TEXT_LEN 0x9c0
4178#define TG3_FW_RODATA_ADDR 0x080009c0
4179#define TG3_FW_RODATA_LEN 0x60
4180#define TG3_FW_DATA_ADDR 0x08000a40
4181#define TG3_FW_DATA_LEN 0x20
4182#define TG3_FW_SBSS_ADDR 0x08000a60
4183#define TG3_FW_SBSS_LEN 0xc
4184#define TG3_FW_BSS_ADDR 0x08000a70
4185#define TG3_FW_BSS_LEN 0x10
4186
4187static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4188 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4189 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4190 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4191 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4192 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4193 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4194 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4195 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4196 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4197 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4198 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4199 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4200 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4201 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4202 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4203 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4204 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4205 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4206 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4207 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4208 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4209 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4210 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4212 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4213 0, 0, 0, 0, 0, 0,
4214 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4215 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4216 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4217 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4218 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4219 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4220 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4221 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4222 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4223 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4224 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4228 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4229 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4230 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4231 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4232 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4233 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4234 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4235 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4236 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4237 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4238 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4239 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4240 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4241 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4242 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4243 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4244 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4245 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4246 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4247 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4248 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4249 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4250 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4251 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4252 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4253 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4254 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4255 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4256 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4257 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4258 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4259 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4260 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4261 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4262 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4263 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4264 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4265 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4266 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4267 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4268 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4269 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4270 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4271 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4272 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4273 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4274 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4275 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4276 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4277 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4278 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4279};
4280
4281static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4282 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4283 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4284 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4285 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4286 0x00000000
4287};
4288
4289#if 0 /* All zeros, don't eat up space with it. */
4290u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4291 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4292 0x00000000, 0x00000000, 0x00000000, 0x00000000
4293};
4294#endif
4295
4296#define RX_CPU_SCRATCH_BASE 0x30000
4297#define RX_CPU_SCRATCH_SIZE 0x04000
4298#define TX_CPU_SCRATCH_BASE 0x34000
4299#define TX_CPU_SCRATCH_SIZE 0x04000
4300
4301/* tp->lock is held. */
4302static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4303{
4304 int i;
4305
4306 if (offset == TX_CPU_BASE &&
4307 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4308 BUG();
4309
4310 if (offset == RX_CPU_BASE) {
4311 for (i = 0; i < 10000; i++) {
4312 tw32(offset + CPU_STATE, 0xffffffff);
4313 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4314 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4315 break;
4316 }
4317
4318 tw32(offset + CPU_STATE, 0xffffffff);
4319 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4320 udelay(10);
4321 } else {
4322 for (i = 0; i < 10000; i++) {
4323 tw32(offset + CPU_STATE, 0xffffffff);
4324 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4325 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4326 break;
4327 }
4328 }
4329
4330 if (i >= 10000) {
4331 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4332 "and %s CPU\n",
4333 tp->dev->name,
4334 (offset == RX_CPU_BASE ? "RX" : "TX"));
4335 return -ENODEV;
4336 }
4337 return 0;
4338}
4339
4340struct fw_info {
4341 unsigned int text_base;
4342 unsigned int text_len;
4343 u32 *text_data;
4344 unsigned int rodata_base;
4345 unsigned int rodata_len;
4346 u32 *rodata_data;
4347 unsigned int data_base;
4348 unsigned int data_len;
4349 u32 *data_data;
4350};
4351
4352/* tp->lock is held. */
4353static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4354 int cpu_scratch_size, struct fw_info *info)
4355{
4356 int err, i;
4357 u32 orig_tg3_flags = tp->tg3_flags;
4358 void (*write_op)(struct tg3 *, u32, u32);
4359
4360 if (cpu_base == TX_CPU_BASE &&
4361 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4362 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4363 "TX cpu firmware on %s which is 5705.\n",
4364 tp->dev->name);
4365 return -EINVAL;
4366 }
4367
4368 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4369 write_op = tg3_write_mem;
4370 else
4371 write_op = tg3_write_indirect_reg32;
4372
4373 /* Force use of PCI config space for indirect register
4374 * write calls.
4375 */
4376 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4377
1b628151
MC		 4378 /* It is possible that bootcode is still loading at this point.
4379 * Get the nvram lock first before halting the cpu.
4380 */
4381 tg3_nvram_lock(tp);
1da177e4 4382 err = tg3_halt_cpu(tp, cpu_base);
1b628151 4383 tg3_nvram_unlock(tp);
1da177e4
LT		 4384 if (err)
4385 goto out;
4386
4387 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4388 write_op(tp, cpu_scratch_base + i, 0);
4389 tw32(cpu_base + CPU_STATE, 0xffffffff);
4390 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4391 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4392 write_op(tp, (cpu_scratch_base +
4393 (info->text_base & 0xffff) +
4394 (i * sizeof(u32))),
4395 (info->text_data ?
4396 info->text_data[i] : 0));
4397 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4398 write_op(tp, (cpu_scratch_base +
4399 (info->rodata_base & 0xffff) +
4400 (i * sizeof(u32))),
4401 (info->rodata_data ?
4402 info->rodata_data[i] : 0));
4403 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4404 write_op(tp, (cpu_scratch_base +
4405 (info->data_base & 0xffff) +
4406 (i * sizeof(u32))),
4407 (info->data_data ?
4408 info->data_data[i] : 0));
4409
4410 err = 0;
4411
4412out:
4413 tp->tg3_flags = orig_tg3_flags;
4414 return err;
4415}
4416
4417/* tp->lock is held. */
4418static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4419{
4420 struct fw_info info;
4421 int err, i;
4422
4423 info.text_base = TG3_FW_TEXT_ADDR;
4424 info.text_len = TG3_FW_TEXT_LEN;
4425 info.text_data = &tg3FwText[0];
4426 info.rodata_base = TG3_FW_RODATA_ADDR;
4427 info.rodata_len = TG3_FW_RODATA_LEN;
4428 info.rodata_data = &tg3FwRodata[0];
4429 info.data_base = TG3_FW_DATA_ADDR;
4430 info.data_len = TG3_FW_DATA_LEN;
4431 info.data_data = NULL;
4432
4433 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4434 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4435 &info);
4436 if (err)
4437 return err;
4438
4439 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4440 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4441 &info);
4442 if (err)
4443 return err;
4444
4445 /* Now startup only the RX cpu. */
4446 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4447 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4448
4449 for (i = 0; i < 5; i++) {
4450 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4451 break;
4452 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4453 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4454 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4455 udelay(1000);
4456 }
4457 if (i >= 5) {
4458 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4459 "to set RX CPU PC, is %08x should be %08x\n",
4460 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4461 TG3_FW_TEXT_ADDR);
4462 return -ENODEV;
4463 }
4464 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4465 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4466
4467 return 0;
4468}
4469
4470#if TG3_TSO_SUPPORT != 0
4471
4472#define TG3_TSO_FW_RELEASE_MAJOR 0x1
4473#define TG3_TSO_FW_RELASE_MINOR 0x6
4474#define TG3_TSO_FW_RELEASE_FIX 0x0
4475#define TG3_TSO_FW_START_ADDR 0x08000000
4476#define TG3_TSO_FW_TEXT_ADDR 0x08000000
4477#define TG3_TSO_FW_TEXT_LEN 0x1aa0
4478#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4479#define TG3_TSO_FW_RODATA_LEN 0x60
4480#define TG3_TSO_FW_DATA_ADDR 0x08001b20
4481#define TG3_TSO_FW_DATA_LEN 0x30
4482#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4483#define TG3_TSO_FW_SBSS_LEN 0x2c
4484#define TG3_TSO_FW_BSS_ADDR 0x08001b80
4485#define TG3_TSO_FW_BSS_LEN 0x894
4486
4487static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4488 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4489 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4490 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4491 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4492 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4493 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4494 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4495 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4496 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4497 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4498 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4499 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4500 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4501 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4502 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4503 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4504 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4505 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4506 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4507 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4508 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4509 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4510 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4511 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4512 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4513 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4514 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4515 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4516 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4517 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4518 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4519 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4520 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4521 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4522 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4523 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4524 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4525 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4526 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4527 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4528 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4529 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4530 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4531 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4532 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4533 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4534 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4535 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4536 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4537 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4538 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4539 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4540 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4541 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4542 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4543 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4544 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4545 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4546 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4547 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4548 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4549 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4550 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4551 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4552 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4553 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4554 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4555 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4556 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4557 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4558 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4559 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4560 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4561 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4562 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4563 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4564 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4565 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4566 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4567 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4568 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4569 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4570 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4571 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4572 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4573 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4574 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4575 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4576 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4577 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4578 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4579 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4580 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4581 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4582 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4583 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4584 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4585 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4586 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4587 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4588 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4589 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4590 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4591 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4592 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4593 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4594 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4595 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4596 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4597 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4598 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4599 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4600 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4601 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4602 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4603 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4604 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4605 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4606 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4607 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4608 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4609 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4610 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4611 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4612 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4613 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4614 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4615 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4616 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4617 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4618 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4619 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4620 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4621 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4622 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4623 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4624 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4625 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4626 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4627 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4628 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4629 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4630 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4631 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4632 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4633 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4634 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4635 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4636 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4637 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4638 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4639 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4640 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4641 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4642 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4643 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4644 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4645 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4646 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4647 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4648 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4649 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4650 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4651 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4652 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4653 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4654 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4655 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4656 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4657 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4658 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4659 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4660 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4661 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4662 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4663 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4664 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4665 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4666 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4667 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4668 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4669 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4670 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4671 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4672 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4673 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4674 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4675 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4676 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4677 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4678 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4679 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4680 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4681 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4682 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4683 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4684 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4685 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4686 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4687 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4688 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4689 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4690 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4691 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4692 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4693 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4694 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4695 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4696 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4697 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4698 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4699 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4700 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4701 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4702 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4703 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4704 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4705 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4706 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4707 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4708 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4709 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4710 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4711 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4712 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4713 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4714 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4715 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4716 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4717 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4718 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4719 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4720 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4721 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4722 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4723 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4724 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4725 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4726 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4727 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4728 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4729 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4730 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4731 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4732 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4733 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4734 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4735 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4736 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4737 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4738 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4739 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4740 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4741 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4742 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4743 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4744 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4745 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4746 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4747 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4748 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4749 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4750 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4751 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4752 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4753 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4754 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4755 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4756 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4757 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4758 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4759 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4760 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4761 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4762 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4763 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4764 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4765 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4766 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4767 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4768 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4769 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4770 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4771 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4772};
4773
4774static u32 tg3TsoFwRodata[] = {
4775 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4776 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4777 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4778 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4779 0x00000000,
4780};
4781
4782static u32 tg3TsoFwData[] = {
4783 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4784 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4785 0x00000000,
4786};
4787
4788/* 5705 needs a special version of the TSO firmware. */
4789#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
4790#define TG3_TSO5_FW_RELASE_MINOR 0x2
4791#define TG3_TSO5_FW_RELEASE_FIX 0x0
4792#define TG3_TSO5_FW_START_ADDR 0x00010000
4793#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
4794#define TG3_TSO5_FW_TEXT_LEN 0xe90
4795#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
4796#define TG3_TSO5_FW_RODATA_LEN 0x50
4797#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
4798#define TG3_TSO5_FW_DATA_LEN 0x20
4799#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
4800#define TG3_TSO5_FW_SBSS_LEN 0x28
4801#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
4802#define TG3_TSO5_FW_BSS_LEN 0x88
4803
4804static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4805 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4806 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4807 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4808 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4809 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4810 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4811 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4812 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4813 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4814 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4815 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4816 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4817 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4818 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4819 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4820 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4821 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4822 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4823 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4824 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4825 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4826 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4827 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4828 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4829 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4830 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4831 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4832 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4833 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4834 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4835 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4836 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4837 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4838 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4839 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4840 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4841 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4842 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4843 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4844 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4845 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4846 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4847 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4848 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4849 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4850 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4851 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4852 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4853 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4854 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4855 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4856 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4857 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4858 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4859 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4860 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4861 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4862 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4863 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4864 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4865 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4866 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4867 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4868 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4869 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4870 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4871 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4872 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4873 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4874 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4875 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4876 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4877 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4878 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4879 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4880 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4881 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4882 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4883 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4884 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4885 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4886 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4887 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4888 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4889 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4890 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4891 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4892 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4893 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4894 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4895 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4896 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4897 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4898 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4899 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4900 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4901 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4902 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4903 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4904 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4905 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4906 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4907 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4908 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4909 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4910 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4911 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4912 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4913 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4914 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4915 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4916 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4917 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4918 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4919 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4920 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4921 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4922 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4923 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4924 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4925 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4926 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4927 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4928 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4929 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4930 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4931 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4932 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4933 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4934 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4935 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4936 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4937 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4938 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4939 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4940 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4941 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4942 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4943 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4944 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4945 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4946 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4947 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4948 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4949 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4950 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4951 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4952 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4953 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4954 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4955 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4956 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4957 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4958 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4959 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4960 0x00000000, 0x00000000, 0x00000000,
4961};
4962
4963static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4964 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4965 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4966 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4967 0x00000000, 0x00000000, 0x00000000,
4968};
4969
4970static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4971 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4972 0x00000000, 0x00000000, 0x00000000,
4973};
4974
4975/* tp->lock is held. */
4976static int tg3_load_tso_firmware(struct tg3 *tp)
4977{
4978 struct fw_info info;
4979 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4980 int err, i;
4981
4982 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4983 return 0;
4984
4985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4986 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4987 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4988 info.text_data = &tg3Tso5FwText[0];
4989 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4990 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4991 info.rodata_data = &tg3Tso5FwRodata[0];
4992 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4993 info.data_len = TG3_TSO5_FW_DATA_LEN;
4994 info.data_data = &tg3Tso5FwData[0];
4995 cpu_base = RX_CPU_BASE;
4996 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4997 cpu_scratch_size = (info.text_len +
4998 info.rodata_len +
4999 info.data_len +
5000 TG3_TSO5_FW_SBSS_LEN +
5001 TG3_TSO5_FW_BSS_LEN);
5002 } else {
5003 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5004 info.text_len = TG3_TSO_FW_TEXT_LEN;
5005 info.text_data = &tg3TsoFwText[0];
5006 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5007 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5008 info.rodata_data = &tg3TsoFwRodata[0];
5009 info.data_base = TG3_TSO_FW_DATA_ADDR;
5010 info.data_len = TG3_TSO_FW_DATA_LEN;
5011 info.data_data = &tg3TsoFwData[0];
5012 cpu_base = TX_CPU_BASE;
5013 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5014 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5015 }
5016
5017 err = tg3_load_firmware_cpu(tp, cpu_base,
5018 cpu_scratch_base, cpu_scratch_size,
5019 &info);
5020 if (err)
5021 return err;
5022
5023 /* Now startup the cpu. */
5024 tw32(cpu_base + CPU_STATE, 0xffffffff);
5025 tw32_f(cpu_base + CPU_PC, info.text_base);
5026
5027 for (i = 0; i < 5; i++) {
5028 if (tr32(cpu_base + CPU_PC) == info.text_base)
5029 break;
5030 tw32(cpu_base + CPU_STATE, 0xffffffff);
5031 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5032 tw32_f(cpu_base + CPU_PC, info.text_base);
5033 udelay(1000);
5034 }
5035 if (i >= 5) {
5036 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5037 "to set CPU PC, is %08x should be %08x\n",
5038 tp->dev->name, tr32(cpu_base + CPU_PC),
5039 info.text_base);
5040 return -ENODEV;
5041 }
5042 tw32(cpu_base + CPU_STATE, 0xffffffff);
5043 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5044 return 0;
5045}
5046
5047#endif /* TG3_TSO_SUPPORT != 0 */
5048
5049/* tp->lock is held. */
5050static void __tg3_set_mac_addr(struct tg3 *tp)
5051{
5052 u32 addr_high, addr_low;
5053 int i;
5054
5055 addr_high = ((tp->dev->dev_addr[0] << 8) |
5056 tp->dev->dev_addr[1]);
5057 addr_low = ((tp->dev->dev_addr[2] << 24) |
5058 (tp->dev->dev_addr[3] << 16) |
5059 (tp->dev->dev_addr[4] << 8) |
5060 (tp->dev->dev_addr[5] << 0));
5061 for (i = 0; i < 4; i++) {
5062 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5063 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5064 }
5065
5066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5068 for (i = 0; i < 12; i++) {
5069 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5070 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5071 }
5072 }
5073
5074 addr_high = (tp->dev->dev_addr[0] +
5075 tp->dev->dev_addr[1] +
5076 tp->dev->dev_addr[2] +
5077 tp->dev->dev_addr[3] +
5078 tp->dev->dev_addr[4] +
5079 tp->dev->dev_addr[5]) &
5080 TX_BACKOFF_SEED_MASK;
5081 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5082}
5083
5084static int tg3_set_mac_addr(struct net_device *dev, void *p)
5085{
5086 struct tg3 *tp = netdev_priv(dev);
5087 struct sockaddr *addr = p;
5088
5089 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5090
5091 spin_lock_irq(&tp->lock);
5092 __tg3_set_mac_addr(tp);
5093 spin_unlock_irq(&tp->lock);
5094
5095 return 0;
5096}
5097
5098/* tp->lock is held. */
5099static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5100 dma_addr_t mapping, u32 maxlen_flags,
5101 u32 nic_addr)
5102{
5103 tg3_write_mem(tp,
5104 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5105 ((u64) mapping >> 32));
5106 tg3_write_mem(tp,
5107 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5108 ((u64) mapping & 0xffffffff));
5109 tg3_write_mem(tp,
5110 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5111 maxlen_flags);
5112
5113 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5114 tg3_write_mem(tp,
5115 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5116 nic_addr);
5117}
5118
5119static void __tg3_set_rx_mode(struct net_device *);
15f9850d
DM		 5120static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5121{
5122 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5123 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5124 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5125 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5126 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5127 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5128 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5129 }
5130 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5131 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5132 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5133 u32 val = ec->stats_block_coalesce_usecs;
5134
5135 if (!netif_carrier_ok(tp->dev))
5136 val = 0;
5137
5138 tw32(HOSTCC_STAT_COAL_TICKS, val);
5139 }
5140}
1da177e4
LT		 5141
5142/* tp->lock is held. */
5143static int tg3_reset_hw(struct tg3 *tp)
5144{
5145 u32 val, rdmac_mode;
5146 int i, err, limit;
5147
5148 tg3_disable_ints(tp);
5149
5150 tg3_stop_fw(tp);
5151
5152 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5153
5154 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 5155 tg3_abort_hw(tp, 1);
1da177e4
LT		 5156 }
5157
5158 err = tg3_chip_reset(tp);
5159 if (err)
5160 return err;
5161
5162 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5163
5164 /* This works around an issue with Athlon chipsets on
5165 * B3 tigon3 silicon. This bit has no effect on any
5166 * other revision. But do not set this on PCI Express
5167 * chips.
5168 */
5169 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5170 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5171 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5172
5173 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5174 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5175 val = tr32(TG3PCI_PCISTATE);
5176 val |= PCISTATE_RETRY_SAME_DMA;
5177 tw32(TG3PCI_PCISTATE, val);
5178 }
5179
5180 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5181 /* Enable some hw fixes. */
5182 val = tr32(TG3PCI_MSI_DATA);
5183 val |= (1 << 26) | (1 << 28) | (1 << 29);
5184 tw32(TG3PCI_MSI_DATA, val);
5185 }
5186
5187 /* Descriptor ring init may make accesses to the
5188 * NIC SRAM area to setup the TX descriptors, so we
5189 * can only do this after the hardware has been
5190 * successfully reset.
5191 */
5192 tg3_init_rings(tp);
5193
5194 /* This value is determined during the probe time DMA
5195 * engine test, tg3_test_dma.
5196 */
5197 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5198
5199 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5200 GRC_MODE_4X_NIC_SEND_RINGS |
5201 GRC_MODE_NO_TX_PHDR_CSUM |
5202 GRC_MODE_NO_RX_PHDR_CSUM);
5203 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5204 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5205 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5206 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5207 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5208
5209 tw32(GRC_MODE,
5210 tp->grc_mode |
5211 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5212
5213 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5214 val = tr32(GRC_MISC_CFG);
5215 val &= ~0xff;
5216 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5217 tw32(GRC_MISC_CFG, val);
5218
5219 /* Initialize MBUF/DESC pool. */
cbf46853 5220 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 5221 /* Do nothing. */
5222 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5223 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5225 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5226 else
5227 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5228 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5229 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5230 }
5231#if TG3_TSO_SUPPORT != 0
5232 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5233 int fw_len;
5234
5235 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5236 TG3_TSO5_FW_RODATA_LEN +
5237 TG3_TSO5_FW_DATA_LEN +
5238 TG3_TSO5_FW_SBSS_LEN +
5239 TG3_TSO5_FW_BSS_LEN);
5240 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5241 tw32(BUFMGR_MB_POOL_ADDR,
5242 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5243 tw32(BUFMGR_MB_POOL_SIZE,
5244 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5245 }
5246#endif
5247
5248 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5249 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5250 tp->bufmgr_config.mbuf_read_dma_low_water);
5251 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5252 tp->bufmgr_config.mbuf_mac_rx_low_water);
5253 tw32(BUFMGR_MB_HIGH_WATER,
5254 tp->bufmgr_config.mbuf_high_water);
5255 } else {
5256 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5257 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5258 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5259 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5260 tw32(BUFMGR_MB_HIGH_WATER,
5261 tp->bufmgr_config.mbuf_high_water_jumbo);
5262 }
5263 tw32(BUFMGR_DMA_LOW_WATER,
5264 tp->bufmgr_config.dma_low_water);
5265 tw32(BUFMGR_DMA_HIGH_WATER,
5266 tp->bufmgr_config.dma_high_water);
5267
5268 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5269 for (i = 0; i < 2000; i++) {
5270 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5271 break;
5272 udelay(10);
5273 }
5274 if (i >= 2000) {
5275 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5276 tp->dev->name);
5277 return -ENODEV;
5278 }
5279
5280 /* Setup replenish threshold. */
5281 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5282
5283 /* Initialize TG3_BDINFO's at:
5284 * RCVDBDI_STD_BD: standard eth size rx ring
5285 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5286 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5287 *
5288 * like so:
5289 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5290 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5291 * ring attribute flags
5292 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5293 *
5294 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5295 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5296 *
5297 * The size of each ring is fixed in the firmware, but the location is
5298 * configurable.
5299 */
5300 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5301 ((u64) tp->rx_std_mapping >> 32));
5302 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5303 ((u64) tp->rx_std_mapping & 0xffffffff));
5304 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5305 NIC_SRAM_RX_BUFFER_DESC);
5306
5307 /* Don't even try to program the JUMBO/MINI buffer descriptor
5308 * configs on 5705.
5309 */
5310 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5311 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5312 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5313 } else {
5314 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5315 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5316
5317 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5318 BDINFO_FLAGS_DISABLED);
5319
5320 /* Setup replenish threshold. */
5321 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5322
5323 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5324 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5325 ((u64) tp->rx_jumbo_mapping >> 32));
5326 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5327 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5328 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5329 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5330 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5331 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5332 } else {
5333 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5334 BDINFO_FLAGS_DISABLED);
5335 }
5336
5337 }
5338
5339 /* There is only one send ring on 5705/5750, no need to explicitly
5340 * disable the others.
5341 */
5342 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5343 /* Clear out send RCB ring in SRAM. */
5344 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5345 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5346 BDINFO_FLAGS_DISABLED);
5347 }
5348
5349 tp->tx_prod = 0;
5350 tp->tx_cons = 0;
5351 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5352 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5353
5354 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5355 tp->tx_desc_mapping,
5356 (TG3_TX_RING_SIZE <<
5357 BDINFO_FLAGS_MAXLEN_SHIFT),
5358 NIC_SRAM_TX_BUFFER_DESC);
5359
5360 /* There is only one receive return ring on 5705/5750, no need
5361 * to explicitly disable the others.
5362 */
5363 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5364 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5365 i += TG3_BDINFO_SIZE) {
5366 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5367 BDINFO_FLAGS_DISABLED);
5368 }
5369 }
5370
5371 tp->rx_rcb_ptr = 0;
5372 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5373
5374 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5375 tp->rx_rcb_mapping,
5376 (TG3_RX_RCB_RING_SIZE(tp) <<
5377 BDINFO_FLAGS_MAXLEN_SHIFT),
5378 0);
5379
5380 tp->rx_std_ptr = tp->rx_pending;
5381 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5382 tp->rx_std_ptr);
5383
5384 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5385 tp->rx_jumbo_pending : 0;
5386 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5387 tp->rx_jumbo_ptr);
5388
5389 /* Initialize MAC address and backoff seed. */
5390 __tg3_set_mac_addr(tp);
5391
5392 /* MTU + ethernet header + FCS + optional VLAN tag */
5393 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5394
5395 /* The slot time is changed by tg3_setup_phy if we
5396 * run at gigabit with half duplex.
5397 */
5398 tw32(MAC_TX_LENGTHS,
5399 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5400 (6 << TX_LENGTHS_IPG_SHIFT) |
5401 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5402
5403 /* Receive rules. */
5404 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5405 tw32(RCVLPC_CONFIG, 0x0181);
5406
5407 /* Calculate RDMAC_MODE setting early, we need it to determine
5408 * the RCVLPC_STATE_ENABLE mask.
5409 */
5410 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5411 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5412 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5413 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5414 RDMAC_MODE_LNGREAD_ENAB);
5415 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5416 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 5417
5418 /* If statement applies to 5705 and 5750 PCI devices only */
5419 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5420 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5421 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 5422 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5423 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5424 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5425 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5426 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5427 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5428 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5429 }
5430 }
5431
85e94ced
MC		 5432 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5433 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5434
1da177e4
LT		 5435#if TG3_TSO_SUPPORT != 0
5436 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5437 rdmac_mode |= (1 << 27);
5438#endif
5439
5440 /* Receive/send statistics. */
5441 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5442 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5443 val = tr32(RCVLPC_STATS_ENABLE);
5444 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5445 tw32(RCVLPC_STATS_ENABLE, val);
5446 } else {
5447 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5448 }
5449 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5450 tw32(SNDDATAI_STATSENAB, 0xffffff);
5451 tw32(SNDDATAI_STATSCTRL,
5452 (SNDDATAI_SCTRL_ENABLE |
5453 SNDDATAI_SCTRL_FASTUPD));
5454
5455 /* Setup host coalescing engine. */
5456 tw32(HOSTCC_MODE, 0);
5457 for (i = 0; i < 2000; i++) {
5458 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5459 break;
5460 udelay(10);
5461 }
5462
15f9850d 5463 tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 5464
5465 /* set status block DMA address */
5466 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5467 ((u64) tp->status_mapping >> 32));
5468 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5469 ((u64) tp->status_mapping & 0xffffffff));
5470
5471 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5472 /* Status/statistics block address. See tg3_timer,
5473 * the tg3_periodic_fetch_stats call there, and
5474 * tg3_get_stats to see how this works for 5705/5750 chips.
5475 */
1da177e4
LT		 5476 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5477 ((u64) tp->stats_mapping >> 32));
5478 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5479 ((u64) tp->stats_mapping & 0xffffffff));
5480 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5481 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5482 }
5483
5484 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5485
5486 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5487 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5488 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5489 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5490
5491 /* Clear statistics/status block in chip, and status block in ram. */
5492 for (i = NIC_SRAM_STATS_BLK;
5493 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5494 i += sizeof(u32)) {
5495 tg3_write_mem(tp, i, 0);
5496 udelay(40);
5497 }
5498 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5499
5500 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5501 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5502 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5503 udelay(40);
5504
314fba34
MC		 5505 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5506 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5507 * register to preserve the GPIO settings for LOMs. The GPIOs,
5508 * whether used as inputs or outputs, are set by boot code after
5509 * reset.
5510 */
5511 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5512 u32 gpio_mask;
5513
5514 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5515 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 5516
5517 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5518 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5519 GRC_LCLCTRL_GPIO_OUTPUT3;
5520
314fba34
MC		 5521 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5522
5523 /* GPIO1 must be driven high for eeprom write protect */
1da177e4
LT		 5524 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5525 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 5526 }
1da177e4
LT		 5527 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5528 udelay(100);
5529
5530 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e
DM		 5531 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5532 tp->last_tag = 0;
1da177e4
LT		 5533
5534 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5535 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5536 udelay(40);
5537 }
5538
5539 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5540 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5541 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5542 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5543 WDMAC_MODE_LNGREAD_ENAB);
5544
85e94ced
MC		 5545 /* If statement applies to 5705 and 5750 PCI devices only */
5546 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5547 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5548 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 5549 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5550 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5551 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5552 /* nothing */
5553 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5554 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5555 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5556 val |= WDMAC_MODE_RX_ACCEL;
5557 }
5558 }
5559
5560 tw32_f(WDMAC_MODE, val);
5561 udelay(40);
5562
5563 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5564 val = tr32(TG3PCI_X_CAPS);
5565 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5566 val &= ~PCIX_CAPS_BURST_MASK;
5567 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5568 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5569 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5570 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5571 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5572 val |= (tp->split_mode_max_reqs <<
5573 PCIX_CAPS_SPLIT_SHIFT);
5574 }
5575 tw32(TG3PCI_X_CAPS, val);
5576 }
5577
5578 tw32_f(RDMAC_MODE, rdmac_mode);
5579 udelay(40);
5580
5581 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5582 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5583 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5584 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5585 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5586 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5587 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5588 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5589#if TG3_TSO_SUPPORT != 0
5590 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5591 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5592#endif
5593 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5594 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5595
5596 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5597 err = tg3_load_5701_a0_firmware_fix(tp);
5598 if (err)
5599 return err;
5600 }
5601
5602#if TG3_TSO_SUPPORT != 0
5603 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5604 err = tg3_load_tso_firmware(tp);
5605 if (err)
5606 return err;
5607 }
5608#endif
5609
5610 tp->tx_mode = TX_MODE_ENABLE;
5611 tw32_f(MAC_TX_MODE, tp->tx_mode);
5612 udelay(100);
5613
5614 tp->rx_mode = RX_MODE_ENABLE;
5615 tw32_f(MAC_RX_MODE, tp->rx_mode);
5616 udelay(10);
5617
5618 if (tp->link_config.phy_is_low_power) {
5619 tp->link_config.phy_is_low_power = 0;
5620 tp->link_config.speed = tp->link_config.orig_speed;
5621 tp->link_config.duplex = tp->link_config.orig_duplex;
5622 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5623 }
5624
5625 tp->mi_mode = MAC_MI_MODE_BASE;
5626 tw32_f(MAC_MI_MODE, tp->mi_mode);
5627 udelay(80);
5628
5629 tw32(MAC_LED_CTRL, tp->led_ctrl);
5630
5631 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5632 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5633 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5634 udelay(10);
5635 }
5636 tw32_f(MAC_RX_MODE, tp->rx_mode);
5637 udelay(10);
5638
5639 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5640 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5641 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5642 /* Set drive transmission level to 1.2V */
5643 /* only if the signal pre-emphasis bit is not set */
5644 val = tr32(MAC_SERDES_CFG);
5645 val &= 0xfffff000;
5646 val |= 0x880;
5647 tw32(MAC_SERDES_CFG, val);
5648 }
5649 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5650 tw32(MAC_SERDES_CFG, 0x616000);
5651 }
5652
5653 /* Prevent chip from dropping frames when flow control
5654 * is enabled.
5655 */
5656 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5657
5658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5659 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5660 /* Use hardware link auto-negotiation */
5661 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5662 }
5663
5664 err = tg3_setup_phy(tp, 1);
5665 if (err)
5666 return err;
5667
5668 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5669 u32 tmp;
5670
5671 /* Clear CRC stats. */
5672 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5673 tg3_writephy(tp, 0x1e, tmp | 0x8000);
5674 tg3_readphy(tp, 0x14, &tmp);
5675 }
5676 }
5677
5678 __tg3_set_rx_mode(tp->dev);
5679
5680 /* Initialize receive rules. */
5681 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
5682 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5683 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
5684 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5685
5686 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5687 limit = 8;
5688 else
5689 limit = 16;
5690 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5691 limit -= 4;
5692 switch (limit) {
5693 case 16:
5694 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
5695 case 15:
5696 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
5697 case 14:
5698 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
5699 case 13:
5700 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
5701 case 12:
5702 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
5703 case 11:
5704 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
5705 case 10:
5706 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
5707 case 9:
5708 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
5709 case 8:
5710 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
5711 case 7:
5712 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
5713 case 6:
5714 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
5715 case 5:
5716 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
5717 case 4:
5718 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
5719 case 3:
5720 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
5721 case 2:
5722 case 1:
5723
5724 default:
5725 break;
5726 };
5727
5728 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5729
5730 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5731 tg3_enable_ints(tp);
5732
5733 return 0;
5734}
5735
5736/* Called at device open time to get the chip ready for
5737 * packet processing. Invoked with tp->lock held.
5738 */
5739static int tg3_init_hw(struct tg3 *tp)
5740{
5741 int err;
5742
5743 /* Force the chip into D0. */
5744 err = tg3_set_power_state(tp, 0);
5745 if (err)
5746 goto out;
5747
5748 tg3_switch_clocks(tp);
5749
5750 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5751
5752 err = tg3_reset_hw(tp);
5753
5754out:
5755 return err;
5756}
5757
5758#define TG3_STAT_ADD32(PSTAT, REG) \
5759do { u32 __val = tr32(REG); \
5760 (PSTAT)->low += __val; \
5761 if ((PSTAT)->low < __val) \
5762 (PSTAT)->high += 1; \
5763} while (0)
5764
5765static void tg3_periodic_fetch_stats(struct tg3 *tp)
5766{
5767 struct tg3_hw_stats *sp = tp->hw_stats;
5768
5769 if (!netif_carrier_ok(tp->dev))
5770 return;
5771
5772 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5773 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5774 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5775 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5776 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5777 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5778 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5779 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5780 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5781 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5782 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5783 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5784 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5785
5786 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5787 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5788 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5789 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5790 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5791 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5792 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5793 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5794 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5795 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5796 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5797 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5798 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5799 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5800}
5801
5802static void tg3_timer(unsigned long __opaque)
5803{
5804 struct tg3 *tp = (struct tg3 *) __opaque;
5805 unsigned long flags;
5806
5807 spin_lock_irqsave(&tp->lock, flags);
5808 spin_lock(&tp->tx_lock);
5809
fac9b83e
DM		 5810 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
5811 /* All of this garbage is because when using non-tagged
5812 * IRQ status the mailbox/status_block protocol the chip
5813 * uses with the cpu is race prone.
5814 */
5815 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5816 tw32(GRC_LOCAL_CTRL,
5817 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5818 } else {
5819 tw32(HOSTCC_MODE, tp->coalesce_mode |
5820 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5821 }
1da177e4 5822
fac9b83e
DM		 5823 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5824 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5825 spin_unlock(&tp->tx_lock);
5826 spin_unlock_irqrestore(&tp->lock, flags);
5827 schedule_work(&tp->reset_task);
5828 return;
5829 }
1da177e4
LT		 5830 }
5831
1da177e4
LT		 5832 /* This part only runs once per second. */
5833 if (!--tp->timer_counter) {
fac9b83e
DM		 5834 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5835 tg3_periodic_fetch_stats(tp);
5836
1da177e4
LT		 5837 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5838 u32 mac_stat;
5839 int phy_event;
5840
5841 mac_stat = tr32(MAC_STATUS);
5842
5843 phy_event = 0;
5844 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5845 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5846 phy_event = 1;
5847 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5848 phy_event = 1;
5849
5850 if (phy_event)
5851 tg3_setup_phy(tp, 0);
5852 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5853 u32 mac_stat = tr32(MAC_STATUS);
5854 int need_setup = 0;
5855
5856 if (netif_carrier_ok(tp->dev) &&
5857 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5858 need_setup = 1;
5859 }
5860 if (! netif_carrier_ok(tp->dev) &&
5861 (mac_stat & (MAC_STATUS_PCS_SYNCED |
5862 MAC_STATUS_SIGNAL_DET))) {
5863 need_setup = 1;
5864 }
5865 if (need_setup) {
5866 tw32_f(MAC_MODE,
5867 (tp->mac_mode &
5868 ~MAC_MODE_PORT_MODE_MASK));
5869 udelay(40);
5870 tw32_f(MAC_MODE, tp->mac_mode);
5871 udelay(40);
5872 tg3_setup_phy(tp, 0);
5873 }
5874 }
5875
5876 tp->timer_counter = tp->timer_multiplier;
5877 }
5878
5879 /* Heartbeat is only sent once every 120 seconds. */
5880 if (!--tp->asf_counter) {
5881 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5882 u32 val;
5883
5884 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5885 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5886 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5887 val = tr32(GRC_RX_CPU_EVENT);
5888 val |= (1 << 14);
5889 tw32(GRC_RX_CPU_EVENT, val);
5890 }
5891 tp->asf_counter = tp->asf_multiplier;
5892 }
5893
5894 spin_unlock(&tp->tx_lock);
5895 spin_unlock_irqrestore(&tp->lock, flags);
5896
5897 tp->timer.expires = jiffies + tp->timer_offset;
5898 add_timer(&tp->timer);
5899}
5900
7938109f
MC		 5901static int tg3_test_interrupt(struct tg3 *tp)
5902{
5903 struct net_device *dev = tp->dev;
5904 int err, i;
5905 u32 int_mbox = 0;
5906
d4bc3927
MC		 5907 if (!netif_running(dev))
5908 return -ENODEV;
5909
7938109f
MC		 5910 tg3_disable_ints(tp);
5911
5912 free_irq(tp->pdev->irq, dev);
5913
5914 err = request_irq(tp->pdev->irq, tg3_test_isr,
f4d0ee98 5915 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 5916 if (err)
5917 return err;
5918
5919 tg3_enable_ints(tp);
5920
5921 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
5922 HOSTCC_MODE_NOW);
5923
5924 for (i = 0; i < 5; i++) {
5925 int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5926 if (int_mbox != 0)
5927 break;
5928 msleep(10);
5929 }
5930
5931 tg3_disable_ints(tp);
5932
5933 free_irq(tp->pdev->irq, dev);
5934
5935 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5936 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 5937 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 5938 else {
5939 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5940 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5941 fn = tg3_interrupt_tagged;
5942 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 5943 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 5944 }
7938109f
MC		 5945
5946 if (err)
5947 return err;
5948
5949 if (int_mbox != 0)
5950 return 0;
5951
5952 return -EIO;
5953}
5954
5955/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5956 * successfully restored
5957 */
5958static int tg3_test_msi(struct tg3 *tp)
5959{
5960 struct net_device *dev = tp->dev;
5961 int err;
5962 u16 pci_cmd;
5963
5964 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
5965 return 0;
5966
5967 /* Turn off SERR reporting in case MSI terminates with Master
5968 * Abort.
5969 */
5970 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
5971 pci_write_config_word(tp->pdev, PCI_COMMAND,
5972 pci_cmd & ~PCI_COMMAND_SERR);
5973
5974 err = tg3_test_interrupt(tp);
5975
5976 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
5977
5978 if (!err)
5979 return 0;
5980
5981 /* other failures */
5982 if (err != -EIO)
5983 return err;
5984
5985 /* MSI test failed, go back to INTx mode */
5986 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
5987 "switching to INTx mode. Please report this failure to "
5988 "the PCI maintainer and include system chipset information.\n",
5989 tp->dev->name);
5990
5991 free_irq(tp->pdev->irq, dev);
5992 pci_disable_msi(tp->pdev);
5993
5994 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5995
fac9b83e
DM		 5996 {
5997 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5998 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5999 fn = tg3_interrupt_tagged;
7938109f 6000
fac9b83e
DM		 6001 err = request_irq(tp->pdev->irq, fn,
6002 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6003 }
7938109f
MC		 6004 if (err)
6005 return err;
6006
6007 /* Need to reset the chip because the MSI cycle may have terminated
6008 * with Master Abort.
6009 */
6010 spin_lock_irq(&tp->lock);
6011 spin_lock(&tp->tx_lock);
6012
944d980e 6013 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6014 err = tg3_init_hw(tp);
6015
6016 spin_unlock(&tp->tx_lock);
6017 spin_unlock_irq(&tp->lock);
6018
6019 if (err)
6020 free_irq(tp->pdev->irq, dev);
6021
6022 return err;
6023}
6024
1da177e4
LT		 6025static int tg3_open(struct net_device *dev)
6026{
6027 struct tg3 *tp = netdev_priv(dev);
6028 int err;
6029
6030 spin_lock_irq(&tp->lock);
6031 spin_lock(&tp->tx_lock);
6032
6033 tg3_disable_ints(tp);
6034 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6035
6036 spin_unlock(&tp->tx_lock);
6037 spin_unlock_irq(&tp->lock);
6038
6039 /* The placement of this call is tied
6040 * to the setup and use of Host TX descriptors.
6041 */
6042 err = tg3_alloc_consistent(tp);
6043 if (err)
6044 return err;
6045
88b06bc2
MC		 6046 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6047 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6048 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
fac9b83e
DM		 6049 /* All MSI supporting chips should support tagged
6050 * status. Assert that this is the case.
6051 */
6052 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6053 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6054 "Not using MSI.\n", tp->dev->name);
6055 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 6056 u32 msi_mode;
6057
6058 msi_mode = tr32(MSGINT_MODE);
6059 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6060 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6061 }
6062 }
6063 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6064 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6065 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6066 else {
6067 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6068 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6069 fn = tg3_interrupt_tagged;
6070
6071 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6072 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6073 }
1da177e4
LT		 6074
6075 if (err) {
88b06bc2
MC		 6076 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6077 pci_disable_msi(tp->pdev);
6078 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6079 }
1da177e4
LT		 6080 tg3_free_consistent(tp);
6081 return err;
6082 }
6083
6084 spin_lock_irq(&tp->lock);
6085 spin_lock(&tp->tx_lock);
6086
6087 err = tg3_init_hw(tp);
6088 if (err) {
944d980e 6089 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6090 tg3_free_rings(tp);
6091 } else {
fac9b83e
DM		 6092 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6093 tp->timer_offset = HZ;
6094 else
6095 tp->timer_offset = HZ / 10;
6096
6097 BUG_ON(tp->timer_offset > HZ);
6098 tp->timer_counter = tp->timer_multiplier =
6099 (HZ / tp->timer_offset);
6100 tp->asf_counter = tp->asf_multiplier =
6101 ((HZ / tp->timer_offset) * 120);
1da177e4
LT		 6102
6103 init_timer(&tp->timer);
6104 tp->timer.expires = jiffies + tp->timer_offset;
6105 tp->timer.data = (unsigned long) tp;
6106 tp->timer.function = tg3_timer;
1da177e4
LT		 6107 }
6108
6109 spin_unlock(&tp->tx_lock);
6110 spin_unlock_irq(&tp->lock);
6111
6112 if (err) {
88b06bc2
MC		 6113 free_irq(tp->pdev->irq, dev);
6114 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6115 pci_disable_msi(tp->pdev);
6116 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6117 }
1da177e4
LT		 6118 tg3_free_consistent(tp);
6119 return err;
6120 }
6121
7938109f
MC		 6122 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6123 err = tg3_test_msi(tp);
fac9b83e 6124
7938109f
MC		 6125 if (err) {
6126 spin_lock_irq(&tp->lock);
6127 spin_lock(&tp->tx_lock);
6128
6129 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6130 pci_disable_msi(tp->pdev);
6131 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6132 }
944d980e 6133 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6134 tg3_free_rings(tp);
6135 tg3_free_consistent(tp);
6136
6137 spin_unlock(&tp->tx_lock);
6138 spin_unlock_irq(&tp->lock);
6139
6140 return err;
6141 }
6142 }
6143
1da177e4
LT		 6144 spin_lock_irq(&tp->lock);
6145 spin_lock(&tp->tx_lock);
6146
7938109f
MC		 6147 add_timer(&tp->timer);
6148 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 6149 tg3_enable_ints(tp);
6150
6151 spin_unlock(&tp->tx_lock);
6152 spin_unlock_irq(&tp->lock);
6153
6154 netif_start_queue(dev);
6155
6156 return 0;
6157}
6158
6159#if 0
6160/*static*/ void tg3_dump_state(struct tg3 *tp)
6161{
6162 u32 val32, val32_2, val32_3, val32_4, val32_5;
6163 u16 val16;
6164 int i;
6165
6166 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6167 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6168 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6169 val16, val32);
6170
6171 /* MAC block */
6172 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6173 tr32(MAC_MODE), tr32(MAC_STATUS));
6174 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6175 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6176 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6177 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6178 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6179 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6180
6181 /* Send data initiator control block */
6182 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6183 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6184 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6185 tr32(SNDDATAI_STATSCTRL));
6186
6187 /* Send data completion control block */
6188 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6189
6190 /* Send BD ring selector block */
6191 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6192 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6193
6194 /* Send BD initiator control block */
6195 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6196 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6197
6198 /* Send BD completion control block */
6199 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6200
6201 /* Receive list placement control block */
6202 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6203 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6204 printk(" RCVLPC_STATSCTRL[%08x]\n",
6205 tr32(RCVLPC_STATSCTRL));
6206
6207 /* Receive data and receive BD initiator control block */
6208 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6209 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6210
6211 /* Receive data completion control block */
6212 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6213 tr32(RCVDCC_MODE));
6214
6215 /* Receive BD initiator control block */
6216 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6217 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6218
6219 /* Receive BD completion control block */
6220 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6221 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6222
6223 /* Receive list selector control block */
6224 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6225 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6226
6227 /* Mbuf cluster free block */
6228 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6229 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6230
6231 /* Host coalescing control block */
6232 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6233 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6234 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6235 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6236 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6237 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6238 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6239 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6240 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6241 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6242 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6243 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6244
6245 /* Memory arbiter control block */
6246 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6247 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6248
6249 /* Buffer manager control block */
6250 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6251 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6252 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6253 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6254 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6255 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6256 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6257 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6258
6259 /* Read DMA control block */
6260 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6261 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6262
6263 /* Write DMA control block */
6264 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6265 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6266
6267 /* DMA completion block */
6268 printk("DEBUG: DMAC_MODE[%08x]\n",
6269 tr32(DMAC_MODE));
6270
6271 /* GRC block */
6272 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6273 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6274 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6275 tr32(GRC_LOCAL_CTRL));
6276
6277 /* TG3_BDINFOs */
6278 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6279 tr32(RCVDBDI_JUMBO_BD + 0x0),
6280 tr32(RCVDBDI_JUMBO_BD + 0x4),
6281 tr32(RCVDBDI_JUMBO_BD + 0x8),
6282 tr32(RCVDBDI_JUMBO_BD + 0xc));
6283 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6284 tr32(RCVDBDI_STD_BD + 0x0),
6285 tr32(RCVDBDI_STD_BD + 0x4),
6286 tr32(RCVDBDI_STD_BD + 0x8),
6287 tr32(RCVDBDI_STD_BD + 0xc));
6288 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6289 tr32(RCVDBDI_MINI_BD + 0x0),
6290 tr32(RCVDBDI_MINI_BD + 0x4),
6291 tr32(RCVDBDI_MINI_BD + 0x8),
6292 tr32(RCVDBDI_MINI_BD + 0xc));
6293
6294 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6295 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6296 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6297 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6298 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6299 val32, val32_2, val32_3, val32_4);
6300
6301 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6302 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6303 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6304 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6305 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6306 val32, val32_2, val32_3, val32_4);
6307
6308 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6309 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6310 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6311 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6312 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6313 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6314 val32, val32_2, val32_3, val32_4, val32_5);
6315
6316 /* SW status block */
6317 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6318 tp->hw_status->status,
6319 tp->hw_status->status_tag,
6320 tp->hw_status->rx_jumbo_consumer,
6321 tp->hw_status->rx_consumer,
6322 tp->hw_status->rx_mini_consumer,
6323 tp->hw_status->idx[0].rx_producer,
6324 tp->hw_status->idx[0].tx_consumer);
6325
6326 /* SW statistics block */
6327 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6328 ((u32 *)tp->hw_stats)[0],
6329 ((u32 *)tp->hw_stats)[1],
6330 ((u32 *)tp->hw_stats)[2],
6331 ((u32 *)tp->hw_stats)[3]);
6332
6333 /* Mailboxes */
6334 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6335 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6336 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6337 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6338 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6339
6340 /* NIC side send descriptors. */
6341 for (i = 0; i < 6; i++) {
6342 unsigned long txd;
6343
6344 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6345 + (i * sizeof(struct tg3_tx_buffer_desc));
6346 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6347 i,
6348 readl(txd + 0x0), readl(txd + 0x4),
6349 readl(txd + 0x8), readl(txd + 0xc));
6350 }
6351
6352 /* NIC side RX descriptors. */
6353 for (i = 0; i < 6; i++) {
6354 unsigned long rxd;
6355
6356 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6357 + (i * sizeof(struct tg3_rx_buffer_desc));
6358 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6359 i,
6360 readl(rxd + 0x0), readl(rxd + 0x4),
6361 readl(rxd + 0x8), readl(rxd + 0xc));
6362 rxd += (4 * sizeof(u32));
6363 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6364 i,
6365 readl(rxd + 0x0), readl(rxd + 0x4),
6366 readl(rxd + 0x8), readl(rxd + 0xc));
6367 }
6368
6369 for (i = 0; i < 6; i++) {
6370 unsigned long rxd;
6371
6372 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6373 + (i * sizeof(struct tg3_rx_buffer_desc));
6374 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6375 i,
6376 readl(rxd + 0x0), readl(rxd + 0x4),
6377 readl(rxd + 0x8), readl(rxd + 0xc));
6378 rxd += (4 * sizeof(u32));
6379 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6380 i,
6381 readl(rxd + 0x0), readl(rxd + 0x4),
6382 readl(rxd + 0x8), readl(rxd + 0xc));
6383 }
6384}
6385#endif
6386
6387static struct net_device_stats *tg3_get_stats(struct net_device *);
6388static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6389
6390static int tg3_close(struct net_device *dev)
6391{
6392 struct tg3 *tp = netdev_priv(dev);
6393
6394 netif_stop_queue(dev);
6395
6396 del_timer_sync(&tp->timer);
6397
6398 spin_lock_irq(&tp->lock);
6399 spin_lock(&tp->tx_lock);
6400#if 0
6401 tg3_dump_state(tp);
6402#endif
6403
6404 tg3_disable_ints(tp);
6405
944d980e 6406 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6407 tg3_free_rings(tp);
6408 tp->tg3_flags &=
6409 ~(TG3_FLAG_INIT_COMPLETE |
6410 TG3_FLAG_GOT_SERDES_FLOWCTL);
6411 netif_carrier_off(tp->dev);
6412
6413 spin_unlock(&tp->tx_lock);
6414 spin_unlock_irq(&tp->lock);
6415
88b06bc2
MC		 6416 free_irq(tp->pdev->irq, dev);
6417 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6418 pci_disable_msi(tp->pdev);
6419 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6420 }
1da177e4
LT		 6421
6422 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6423 sizeof(tp->net_stats_prev));
6424 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6425 sizeof(tp->estats_prev));
6426
6427 tg3_free_consistent(tp);
6428
6429 return 0;
6430}
6431
6432static inline unsigned long get_stat64(tg3_stat64_t *val)
6433{
6434 unsigned long ret;
6435
6436#if (BITS_PER_LONG == 32)
6437 ret = val->low;
6438#else
6439 ret = ((u64)val->high << 32) | ((u64)val->low);
6440#endif
6441 return ret;
6442}
6443
6444static unsigned long calc_crc_errors(struct tg3 *tp)
6445{
6446 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6447
6448 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6449 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6451 unsigned long flags;
6452 u32 val;
6453
6454 spin_lock_irqsave(&tp->lock, flags);
6455 if (!tg3_readphy(tp, 0x1e, &val)) {
6456 tg3_writephy(tp, 0x1e, val | 0x8000);
6457 tg3_readphy(tp, 0x14, &val);
6458 } else
6459 val = 0;
6460 spin_unlock_irqrestore(&tp->lock, flags);
6461
6462 tp->phy_crc_errors += val;
6463
6464 return tp->phy_crc_errors;
6465 }
6466
6467 return get_stat64(&hw_stats->rx_fcs_errors);
6468}
6469
6470#define ESTAT_ADD(member) \
6471 estats->member = old_estats->member + \
6472 get_stat64(&hw_stats->member)
6473
6474static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6475{
6476 struct tg3_ethtool_stats *estats = &tp->estats;
6477 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6478 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6479
6480 if (!hw_stats)
6481 return old_estats;
6482
6483 ESTAT_ADD(rx_octets);
6484 ESTAT_ADD(rx_fragments);
6485 ESTAT_ADD(rx_ucast_packets);
6486 ESTAT_ADD(rx_mcast_packets);
6487 ESTAT_ADD(rx_bcast_packets);
6488 ESTAT_ADD(rx_fcs_errors);
6489 ESTAT_ADD(rx_align_errors);
6490 ESTAT_ADD(rx_xon_pause_rcvd);
6491 ESTAT_ADD(rx_xoff_pause_rcvd);
6492 ESTAT_ADD(rx_mac_ctrl_rcvd);
6493 ESTAT_ADD(rx_xoff_entered);
6494 ESTAT_ADD(rx_frame_too_long_errors);
6495 ESTAT_ADD(rx_jabbers);
6496 ESTAT_ADD(rx_undersize_packets);
6497 ESTAT_ADD(rx_in_length_errors);
6498 ESTAT_ADD(rx_out_length_errors);
6499 ESTAT_ADD(rx_64_or_less_octet_packets);
6500 ESTAT_ADD(rx_65_to_127_octet_packets);
6501 ESTAT_ADD(rx_128_to_255_octet_packets);
6502 ESTAT_ADD(rx_256_to_511_octet_packets);
6503 ESTAT_ADD(rx_512_to_1023_octet_packets);
6504 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6505 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6506 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6507 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6508 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6509
6510 ESTAT_ADD(tx_octets);
6511 ESTAT_ADD(tx_collisions);
6512 ESTAT_ADD(tx_xon_sent);
6513 ESTAT_ADD(tx_xoff_sent);
6514 ESTAT_ADD(tx_flow_control);
6515 ESTAT_ADD(tx_mac_errors);
6516 ESTAT_ADD(tx_single_collisions);
6517 ESTAT_ADD(tx_mult_collisions);
6518 ESTAT_ADD(tx_deferred);
6519 ESTAT_ADD(tx_excessive_collisions);
6520 ESTAT_ADD(tx_late_collisions);
6521 ESTAT_ADD(tx_collide_2times);
6522 ESTAT_ADD(tx_collide_3times);
6523 ESTAT_ADD(tx_collide_4times);
6524 ESTAT_ADD(tx_collide_5times);
6525 ESTAT_ADD(tx_collide_6times);
6526 ESTAT_ADD(tx_collide_7times);
6527 ESTAT_ADD(tx_collide_8times);
6528 ESTAT_ADD(tx_collide_9times);
6529 ESTAT_ADD(tx_collide_10times);
6530 ESTAT_ADD(tx_collide_11times);
6531 ESTAT_ADD(tx_collide_12times);
6532 ESTAT_ADD(tx_collide_13times);
6533 ESTAT_ADD(tx_collide_14times);
6534 ESTAT_ADD(tx_collide_15times);
6535 ESTAT_ADD(tx_ucast_packets);
6536 ESTAT_ADD(tx_mcast_packets);
6537 ESTAT_ADD(tx_bcast_packets);
6538 ESTAT_ADD(tx_carrier_sense_errors);
6539 ESTAT_ADD(tx_discards);
6540 ESTAT_ADD(tx_errors);
6541
6542 ESTAT_ADD(dma_writeq_full);
6543 ESTAT_ADD(dma_write_prioq_full);
6544 ESTAT_ADD(rxbds_empty);
6545 ESTAT_ADD(rx_discards);
6546 ESTAT_ADD(rx_errors);
6547 ESTAT_ADD(rx_threshold_hit);
6548
6549 ESTAT_ADD(dma_readq_full);
6550 ESTAT_ADD(dma_read_prioq_full);
6551 ESTAT_ADD(tx_comp_queue_full);
6552
6553 ESTAT_ADD(ring_set_send_prod_index);
6554 ESTAT_ADD(ring_status_update);
6555 ESTAT_ADD(nic_irqs);
6556 ESTAT_ADD(nic_avoided_irqs);
6557 ESTAT_ADD(nic_tx_threshold_hit);
6558
6559 return estats;
6560}
6561
6562static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6563{
6564 struct tg3 *tp = netdev_priv(dev);
6565 struct net_device_stats *stats = &tp->net_stats;
6566 struct net_device_stats *old_stats = &tp->net_stats_prev;
6567 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6568
6569 if (!hw_stats)
6570 return old_stats;
6571
6572 stats->rx_packets = old_stats->rx_packets +
6573 get_stat64(&hw_stats->rx_ucast_packets) +
6574 get_stat64(&hw_stats->rx_mcast_packets) +
6575 get_stat64(&hw_stats->rx_bcast_packets);
6576
6577 stats->tx_packets = old_stats->tx_packets +
6578 get_stat64(&hw_stats->tx_ucast_packets) +
6579 get_stat64(&hw_stats->tx_mcast_packets) +
6580 get_stat64(&hw_stats->tx_bcast_packets);
6581
6582 stats->rx_bytes = old_stats->rx_bytes +
6583 get_stat64(&hw_stats->rx_octets);
6584 stats->tx_bytes = old_stats->tx_bytes +
6585 get_stat64(&hw_stats->tx_octets);
6586
6587 stats->rx_errors = old_stats->rx_errors +
6588 get_stat64(&hw_stats->rx_errors) +
6589 get_stat64(&hw_stats->rx_discards);
6590 stats->tx_errors = old_stats->tx_errors +
6591 get_stat64(&hw_stats->tx_errors) +
6592 get_stat64(&hw_stats->tx_mac_errors) +
6593 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6594 get_stat64(&hw_stats->tx_discards);
6595
6596 stats->multicast = old_stats->multicast +
6597 get_stat64(&hw_stats->rx_mcast_packets);
6598 stats->collisions = old_stats->collisions +
6599 get_stat64(&hw_stats->tx_collisions);
6600
6601 stats->rx_length_errors = old_stats->rx_length_errors +
6602 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6603 get_stat64(&hw_stats->rx_undersize_packets);
6604
6605 stats->rx_over_errors = old_stats->rx_over_errors +
6606 get_stat64(&hw_stats->rxbds_empty);
6607 stats->rx_frame_errors = old_stats->rx_frame_errors +
6608 get_stat64(&hw_stats->rx_align_errors);
6609 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6610 get_stat64(&hw_stats->tx_discards);
6611 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6612 get_stat64(&hw_stats->tx_carrier_sense_errors);
6613
6614 stats->rx_crc_errors = old_stats->rx_crc_errors +
6615 calc_crc_errors(tp);
6616
6617 return stats;
6618}
6619
6620static inline u32 calc_crc(unsigned char *buf, int len)
6621{
6622 u32 reg;
6623 u32 tmp;
6624 int j, k;
6625
6626 reg = 0xffffffff;
6627
6628 for (j = 0; j < len; j++) {
6629 reg ^= buf[j];
6630
6631 for (k = 0; k < 8; k++) {
6632 tmp = reg & 0x01;
6633
6634 reg >>= 1;
6635
6636 if (tmp) {
6637 reg ^= 0xedb88320;
6638 }
6639 }
6640 }
6641
6642 return ~reg;
6643}
6644
6645static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6646{
6647 /* accept or reject all multicast frames */
6648 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6649 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6650 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6651 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6652}
6653
6654static void __tg3_set_rx_mode(struct net_device *dev)
6655{
6656 struct tg3 *tp = netdev_priv(dev);
6657 u32 rx_mode;
6658
6659 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6660 RX_MODE_KEEP_VLAN_TAG);
6661
6662 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6663 * flag clear.
6664 */
6665#if TG3_VLAN_TAG_USED
6666 if (!tp->vlgrp &&
6667 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6668 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6669#else
6670 /* By definition, VLAN is disabled always in this
6671 * case.
6672 */
6673 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6674 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6675#endif
6676
6677 if (dev->flags & IFF_PROMISC) {
6678 /* Promiscuous mode. */
6679 rx_mode |= RX_MODE_PROMISC;
6680 } else if (dev->flags & IFF_ALLMULTI) {
6681 /* Accept all multicast. */
6682 tg3_set_multi (tp, 1);
6683 } else if (dev->mc_count < 1) {
6684 /* Reject all multicast. */
6685 tg3_set_multi (tp, 0);
6686 } else {
6687 /* Accept one or more multicast(s). */
6688 struct dev_mc_list *mclist;
6689 unsigned int i;
6690 u32 mc_filter[4] = { 0, };
6691 u32 regidx;
6692 u32 bit;
6693 u32 crc;
6694
6695 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6696 i++, mclist = mclist->next) {
6697
6698 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6699 bit = ~crc & 0x7f;
6700 regidx = (bit & 0x60) >> 5;
6701 bit &= 0x1f;
6702 mc_filter[regidx] |= (1 << bit);
6703 }
6704
6705 tw32(MAC_HASH_REG_0, mc_filter[0]);
6706 tw32(MAC_HASH_REG_1, mc_filter[1]);
6707 tw32(MAC_HASH_REG_2, mc_filter[2]);
6708 tw32(MAC_HASH_REG_3, mc_filter[3]);
6709 }
6710
6711 if (rx_mode != tp->rx_mode) {
6712 tp->rx_mode = rx_mode;
6713 tw32_f(MAC_RX_MODE, rx_mode);
6714 udelay(10);
6715 }
6716}
6717
6718static void tg3_set_rx_mode(struct net_device *dev)
6719{
6720 struct tg3 *tp = netdev_priv(dev);
6721
6722 spin_lock_irq(&tp->lock);
6723 spin_lock(&tp->tx_lock);
6724 __tg3_set_rx_mode(dev);
6725 spin_unlock(&tp->tx_lock);
6726 spin_unlock_irq(&tp->lock);
6727}
6728
6729#define TG3_REGDUMP_LEN (32 * 1024)
6730
6731static int tg3_get_regs_len(struct net_device *dev)
6732{
6733 return TG3_REGDUMP_LEN;
6734}
6735
6736static void tg3_get_regs(struct net_device *dev,
6737 struct ethtool_regs *regs, void *_p)
6738{
6739 u32 *p = _p;
6740 struct tg3 *tp = netdev_priv(dev);
6741 u8 *orig_p = _p;
6742 int i;
6743
6744 regs->version = 0;
6745
6746 memset(p, 0, TG3_REGDUMP_LEN);
6747
6748 spin_lock_irq(&tp->lock);
6749 spin_lock(&tp->tx_lock);
6750
6751#define __GET_REG32(reg) (*(p)++ = tr32(reg))
6752#define GET_REG32_LOOP(base,len) \
6753do { p = (u32 *)(orig_p + (base)); \
6754 for (i = 0; i < len; i += 4) \
6755 __GET_REG32((base) + i); \
6756} while (0)
6757#define GET_REG32_1(reg) \
6758do { p = (u32 *)(orig_p + (reg)); \
6759 __GET_REG32((reg)); \
6760} while (0)
6761
6762 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6763 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6764 GET_REG32_LOOP(MAC_MODE, 0x4f0);
6765 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6766 GET_REG32_1(SNDDATAC_MODE);
6767 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6768 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6769 GET_REG32_1(SNDBDC_MODE);
6770 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6771 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6772 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6773 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6774 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6775 GET_REG32_1(RCVDCC_MODE);
6776 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6777 GET_REG32_LOOP(RCVCC_MODE, 0x14);
6778 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6779 GET_REG32_1(MBFREE_MODE);
6780 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6781 GET_REG32_LOOP(MEMARB_MODE, 0x10);
6782 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6783 GET_REG32_LOOP(RDMAC_MODE, 0x08);
6784 GET_REG32_LOOP(WDMAC_MODE, 0x08);
6785 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6786 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6787 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6788 GET_REG32_LOOP(FTQ_RESET, 0x120);
6789 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6790 GET_REG32_1(DMAC_MODE);
6791 GET_REG32_LOOP(GRC_MODE, 0x4c);
6792 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6793 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6794
6795#undef __GET_REG32
6796#undef GET_REG32_LOOP
6797#undef GET_REG32_1
6798
6799 spin_unlock(&tp->tx_lock);
6800 spin_unlock_irq(&tp->lock);
6801}
6802
6803static int tg3_get_eeprom_len(struct net_device *dev)
6804{
6805 struct tg3 *tp = netdev_priv(dev);
6806
6807 return tp->nvram_size;
6808}
6809
6810static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6811
6812static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6813{
6814 struct tg3 *tp = netdev_priv(dev);
6815 int ret;
6816 u8 *pd;
6817 u32 i, offset, len, val, b_offset, b_count;
6818
6819 offset = eeprom->offset;
6820 len = eeprom->len;
6821 eeprom->len = 0;
6822
6823 eeprom->magic = TG3_EEPROM_MAGIC;
6824
6825 if (offset & 3) {
6826 /* adjustments to start on required 4 byte boundary */
6827 b_offset = offset & 3;
6828 b_count = 4 - b_offset;
6829 if (b_count > len) {
6830 /* i.e. offset=1 len=2 */
6831 b_count = len;
6832 }
6833 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6834 if (ret)
6835 return ret;
6836 val = cpu_to_le32(val);
6837 memcpy(data, ((char*)&val) + b_offset, b_count);
6838 len -= b_count;
6839 offset += b_count;
6840 eeprom->len += b_count;
6841 }
6842
6843 /* read bytes upto the last 4 byte boundary */
6844 pd = &data[eeprom->len];
6845 for (i = 0; i < (len - (len & 3)); i += 4) {
6846 ret = tg3_nvram_read(tp, offset + i, &val);
6847 if (ret) {
6848 eeprom->len += i;
6849 return ret;
6850 }
6851 val = cpu_to_le32(val);
6852 memcpy(pd + i, &val, 4);
6853 }
6854 eeprom->len += i;
6855
6856 if (len & 3) {
6857 /* read last bytes not ending on 4 byte boundary */
6858 pd = &data[eeprom->len];
6859 b_count = len & 3;
6860 b_offset = offset + len - b_count;
6861 ret = tg3_nvram_read(tp, b_offset, &val);
6862 if (ret)
6863 return ret;
6864 val = cpu_to_le32(val);
6865 memcpy(pd, ((char*)&val), b_count);
6866 eeprom->len += b_count;
6867 }
6868 return 0;
6869}
6870
6871static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6872
6873static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6874{
6875 struct tg3 *tp = netdev_priv(dev);
6876 int ret;
6877 u32 offset, len, b_offset, odd_len, start, end;
6878 u8 *buf;
6879
6880 if (eeprom->magic != TG3_EEPROM_MAGIC)
6881 return -EINVAL;
6882
6883 offset = eeprom->offset;
6884 len = eeprom->len;
6885
6886 if ((b_offset = (offset & 3))) {
6887 /* adjustments to start on required 4 byte boundary */
6888 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6889 if (ret)
6890 return ret;
6891 start = cpu_to_le32(start);
6892 len += b_offset;
6893 offset &= ~3;
1c8594b4
MC		 6894 if (len < 4)
6895 len = 4;
1da177e4
LT		 6896 }
6897
6898 odd_len = 0;
1c8594b4 6899 if (len & 3) {
1da177e4
LT		 6900 /* adjustments to end on required 4 byte boundary */
6901 odd_len = 1;
6902 len = (len + 3) & ~3;
6903 ret = tg3_nvram_read(tp, offset+len-4, &end);
6904 if (ret)
6905 return ret;
6906 end = cpu_to_le32(end);
6907 }
6908
6909 buf = data;
6910 if (b_offset || odd_len) {
6911 buf = kmalloc(len, GFP_KERNEL);
6912 if (buf == 0)
6913 return -ENOMEM;
6914 if (b_offset)
6915 memcpy(buf, &start, 4);
6916 if (odd_len)
6917 memcpy(buf+len-4, &end, 4);
6918 memcpy(buf + b_offset, data, eeprom->len);
6919 }
6920
6921 ret = tg3_nvram_write_block(tp, offset, len, buf);
6922
6923 if (buf != data)
6924 kfree(buf);
6925
6926 return ret;
6927}
6928
6929static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6930{
6931 struct tg3 *tp = netdev_priv(dev);
6932
6933 cmd->supported = (SUPPORTED_Autoneg);
6934
6935 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6936 cmd->supported |= (SUPPORTED_1000baseT_Half |
6937 SUPPORTED_1000baseT_Full);
6938
6939 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6940 cmd->supported |= (SUPPORTED_100baseT_Half |
6941 SUPPORTED_100baseT_Full |
6942 SUPPORTED_10baseT_Half |
6943 SUPPORTED_10baseT_Full |
6944 SUPPORTED_MII);
6945 else
6946 cmd->supported |= SUPPORTED_FIBRE;
6947
6948 cmd->advertising = tp->link_config.advertising;
6949 if (netif_running(dev)) {
6950 cmd->speed = tp->link_config.active_speed;
6951 cmd->duplex = tp->link_config.active_duplex;
6952 }
6953 cmd->port = 0;
6954 cmd->phy_address = PHY_ADDR;
6955 cmd->transceiver = 0;
6956 cmd->autoneg = tp->link_config.autoneg;
6957 cmd->maxtxpkt = 0;
6958 cmd->maxrxpkt = 0;
6959 return 0;
6960}
6961
6962static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6963{
6964 struct tg3 *tp = netdev_priv(dev);
6965
6966 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6967 /* These are the only valid advertisement bits allowed. */
6968 if (cmd->autoneg == AUTONEG_ENABLE &&
6969 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6970 ADVERTISED_1000baseT_Full |
6971 ADVERTISED_Autoneg |
6972 ADVERTISED_FIBRE)))
6973 return -EINVAL;
6974 }
6975
6976 spin_lock_irq(&tp->lock);
6977 spin_lock(&tp->tx_lock);
6978
6979 tp->link_config.autoneg = cmd->autoneg;
6980 if (cmd->autoneg == AUTONEG_ENABLE) {
6981 tp->link_config.advertising = cmd->advertising;
6982 tp->link_config.speed = SPEED_INVALID;
6983 tp->link_config.duplex = DUPLEX_INVALID;
6984 } else {
6985 tp->link_config.advertising = 0;
6986 tp->link_config.speed = cmd->speed;
6987 tp->link_config.duplex = cmd->duplex;
6988 }
6989
6990 if (netif_running(dev))
6991 tg3_setup_phy(tp, 1);
6992
6993 spin_unlock(&tp->tx_lock);
6994 spin_unlock_irq(&tp->lock);
6995
6996 return 0;
6997}
6998
6999static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7000{
7001 struct tg3 *tp = netdev_priv(dev);
7002
7003 strcpy(info->driver, DRV_MODULE_NAME);
7004 strcpy(info->version, DRV_MODULE_VERSION);
7005 strcpy(info->bus_info, pci_name(tp->pdev));
7006}
7007
7008static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7009{
7010 struct tg3 *tp = netdev_priv(dev);
7011
7012 wol->supported = WAKE_MAGIC;
7013 wol->wolopts = 0;
7014 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7015 wol->wolopts = WAKE_MAGIC;
7016 memset(&wol->sopass, 0, sizeof(wol->sopass));
7017}
7018
7019static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7020{
7021 struct tg3 *tp = netdev_priv(dev);
7022
7023 if (wol->wolopts & ~WAKE_MAGIC)
7024 return -EINVAL;
7025 if ((wol->wolopts & WAKE_MAGIC) &&
7026 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7027 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7028 return -EINVAL;
7029
7030 spin_lock_irq(&tp->lock);
7031 if (wol->wolopts & WAKE_MAGIC)
7032 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7033 else
7034 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7035 spin_unlock_irq(&tp->lock);
7036
7037 return 0;
7038}
7039
7040static u32 tg3_get_msglevel(struct net_device *dev)
7041{
7042 struct tg3 *tp = netdev_priv(dev);
7043 return tp->msg_enable;
7044}
7045
7046static void tg3_set_msglevel(struct net_device *dev, u32 value)
7047{
7048 struct tg3 *tp = netdev_priv(dev);
7049 tp->msg_enable = value;
7050}
7051
7052#if TG3_TSO_SUPPORT != 0
7053static int tg3_set_tso(struct net_device *dev, u32 value)
7054{
7055 struct tg3 *tp = netdev_priv(dev);
7056
7057 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7058 if (value)
7059 return -EINVAL;
7060 return 0;
7061 }
7062 return ethtool_op_set_tso(dev, value);
7063}
7064#endif
7065
7066static int tg3_nway_reset(struct net_device *dev)
7067{
7068 struct tg3 *tp = netdev_priv(dev);
7069 u32 bmcr;
7070 int r;
7071
7072 if (!netif_running(dev))
7073 return -EAGAIN;
7074
7075 spin_lock_irq(&tp->lock);
7076 r = -EINVAL;
7077 tg3_readphy(tp, MII_BMCR, &bmcr);
7078 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7079 (bmcr & BMCR_ANENABLE)) {
7080 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7081 r = 0;
7082 }
7083 spin_unlock_irq(&tp->lock);
7084
7085 return r;
7086}
7087
7088static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7089{
7090 struct tg3 *tp = netdev_priv(dev);
7091
7092 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7093 ering->rx_mini_max_pending = 0;
7094 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7095
7096 ering->rx_pending = tp->rx_pending;
7097 ering->rx_mini_pending = 0;
7098 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7099 ering->tx_pending = tp->tx_pending;
7100}
7101
7102static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7103{
7104 struct tg3 *tp = netdev_priv(dev);
7105
7106 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7107 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7108 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7109 return -EINVAL;
7110
7111 if (netif_running(dev))
7112 tg3_netif_stop(tp);
7113
7114 spin_lock_irq(&tp->lock);
7115 spin_lock(&tp->tx_lock);
7116
7117 tp->rx_pending = ering->rx_pending;
7118
7119 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7120 tp->rx_pending > 63)
7121 tp->rx_pending = 63;
7122 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7123 tp->tx_pending = ering->tx_pending;
7124
7125 if (netif_running(dev)) {
944d980e 7126 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7127 tg3_init_hw(tp);
7128 tg3_netif_start(tp);
7129 }
7130
7131 spin_unlock(&tp->tx_lock);
7132 spin_unlock_irq(&tp->lock);
7133
7134 return 0;
7135}
7136
7137static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7138{
7139 struct tg3 *tp = netdev_priv(dev);
7140
7141 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7142 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7143 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7144}
7145
7146static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7147{
7148 struct tg3 *tp = netdev_priv(dev);
7149
7150 if (netif_running(dev))
7151 tg3_netif_stop(tp);
7152
7153 spin_lock_irq(&tp->lock);
7154 spin_lock(&tp->tx_lock);
7155 if (epause->autoneg)
7156 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7157 else
7158 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7159 if (epause->rx_pause)
7160 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7161 else
7162 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7163 if (epause->tx_pause)
7164 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7165 else
7166 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7167
7168 if (netif_running(dev)) {
944d980e 7169 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7170 tg3_init_hw(tp);
7171 tg3_netif_start(tp);
7172 }
7173 spin_unlock(&tp->tx_lock);
7174 spin_unlock_irq(&tp->lock);
7175
7176 return 0;
7177}
7178
7179static u32 tg3_get_rx_csum(struct net_device *dev)
7180{
7181 struct tg3 *tp = netdev_priv(dev);
7182 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7183}
7184
7185static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7186{
7187 struct tg3 *tp = netdev_priv(dev);
7188
7189 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7190 if (data != 0)
7191 return -EINVAL;
7192 return 0;
7193 }
7194
7195 spin_lock_irq(&tp->lock);
7196 if (data)
7197 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7198 else
7199 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7200 spin_unlock_irq(&tp->lock);
7201
7202 return 0;
7203}
7204
7205static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7206{
7207 struct tg3 *tp = netdev_priv(dev);
7208
7209 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7210 if (data != 0)
7211 return -EINVAL;
7212 return 0;
7213 }
7214
7215 if (data)
7216 dev->features |= NETIF_F_IP_CSUM;
7217 else
7218 dev->features &= ~NETIF_F_IP_CSUM;
7219
7220 return 0;
7221}
7222
7223static int tg3_get_stats_count (struct net_device *dev)
7224{
7225 return TG3_NUM_STATS;
7226}
7227
4cafd3f5
MC		 7228static int tg3_get_test_count (struct net_device *dev)
7229{
7230 return TG3_NUM_TEST;
7231}
7232
1da177e4
LT		 7233static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7234{
7235 switch (stringset) {
7236 case ETH_SS_STATS:
7237 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7238 break;
4cafd3f5
MC		 7239 case ETH_SS_TEST:
7240 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7241 break;
1da177e4
LT		 7242 default:
7243 WARN_ON(1); /* we need a WARN() */
7244 break;
7245 }
7246}
7247
7248static void tg3_get_ethtool_stats (struct net_device *dev,
7249 struct ethtool_stats *estats, u64 *tmp_stats)
7250{
7251 struct tg3 *tp = netdev_priv(dev);
7252 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7253}
7254
566f86ad
MC		 7255#define NVRAM_TEST_SIZE 0x100
7256
7257static int tg3_test_nvram(struct tg3 *tp)
7258{
7259 u32 *buf, csum;
7260 int i, j, err = 0;
7261
7262 buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7263 if (buf == NULL)
7264 return -ENOMEM;
7265
7266 for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7267 u32 val;
7268
7269 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7270 break;
7271 buf[j] = cpu_to_le32(val);
7272 }
7273 if (i < NVRAM_TEST_SIZE)
7274 goto out;
7275
7276 err = -EIO;
7277 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7278 goto out;
7279
7280 /* Bootstrap checksum at offset 0x10 */
7281 csum = calc_crc((unsigned char *) buf, 0x10);
7282 if(csum != cpu_to_le32(buf[0x10/4]))
7283 goto out;
7284
7285 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7286 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7287 if (csum != cpu_to_le32(buf[0xfc/4]))
7288 goto out;
7289
7290 err = 0;
7291
7292out:
7293 kfree(buf);
7294 return err;
7295}
7296
ca43007a
MC		 7297#define TG3_SERDES_TIMEOUT_SEC 2
7298#define TG3_COPPER_TIMEOUT_SEC 6
7299
7300static int tg3_test_link(struct tg3 *tp)
7301{
7302 int i, max;
7303
7304 if (!netif_running(tp->dev))
7305 return -ENODEV;
7306
7307 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7308 max = TG3_SERDES_TIMEOUT_SEC;
7309 else
7310 max = TG3_COPPER_TIMEOUT_SEC;
7311
7312 for (i = 0; i < max; i++) {
7313 if (netif_carrier_ok(tp->dev))
7314 return 0;
7315
7316 if (msleep_interruptible(1000))
7317 break;
7318 }
7319
7320 return -EIO;
7321}
7322
a71116d1
MC		 7323/* Only test the commonly used registers */
7324static int tg3_test_registers(struct tg3 *tp)
7325{
7326 int i, is_5705;
7327 u32 offset, read_mask, write_mask, val, save_val, read_val;
7328 static struct {
7329 u16 offset;
7330 u16 flags;
7331#define TG3_FL_5705 0x1
7332#define TG3_FL_NOT_5705 0x2
7333#define TG3_FL_NOT_5788 0x4
7334 u32 read_mask;
7335 u32 write_mask;
7336 } reg_tbl[] = {
7337 /* MAC Control Registers */
7338 { MAC_MODE, TG3_FL_NOT_5705,
7339 0x00000000, 0x00ef6f8c },
7340 { MAC_MODE, TG3_FL_5705,
7341 0x00000000, 0x01ef6b8c },
7342 { MAC_STATUS, TG3_FL_NOT_5705,
7343 0x03800107, 0x00000000 },
7344 { MAC_STATUS, TG3_FL_5705,
7345 0x03800100, 0x00000000 },
7346 { MAC_ADDR_0_HIGH, 0x0000,
7347 0x00000000, 0x0000ffff },
7348 { MAC_ADDR_0_LOW, 0x0000,
7349 0x00000000, 0xffffffff },
7350 { MAC_RX_MTU_SIZE, 0x0000,
7351 0x00000000, 0x0000ffff },
7352 { MAC_TX_MODE, 0x0000,
7353 0x00000000, 0x00000070 },
7354 { MAC_TX_LENGTHS, 0x0000,
7355 0x00000000, 0x00003fff },
7356 { MAC_RX_MODE, TG3_FL_NOT_5705,
7357 0x00000000, 0x000007fc },
7358 { MAC_RX_MODE, TG3_FL_5705,
7359 0x00000000, 0x000007dc },
7360 { MAC_HASH_REG_0, 0x0000,
7361 0x00000000, 0xffffffff },
7362 { MAC_HASH_REG_1, 0x0000,
7363 0x00000000, 0xffffffff },
7364 { MAC_HASH_REG_2, 0x0000,
7365 0x00000000, 0xffffffff },
7366 { MAC_HASH_REG_3, 0x0000,
7367 0x00000000, 0xffffffff },
7368
7369 /* Receive Data and Receive BD Initiator Control Registers. */
7370 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7371 0x00000000, 0xffffffff },
7372 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7373 0x00000000, 0xffffffff },
7374 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7375 0x00000000, 0x00000003 },
7376 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7377 0x00000000, 0xffffffff },
7378 { RCVDBDI_STD_BD+0, 0x0000,
7379 0x00000000, 0xffffffff },
7380 { RCVDBDI_STD_BD+4, 0x0000,
7381 0x00000000, 0xffffffff },
7382 { RCVDBDI_STD_BD+8, 0x0000,
7383 0x00000000, 0xffff0002 },
7384 { RCVDBDI_STD_BD+0xc, 0x0000,
7385 0x00000000, 0xffffffff },
7386
7387 /* Receive BD Initiator Control Registers. */
7388 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7389 0x00000000, 0xffffffff },
7390 { RCVBDI_STD_THRESH, TG3_FL_5705,
7391 0x00000000, 0x000003ff },
7392 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7393 0x00000000, 0xffffffff },
7394
7395 /* Host Coalescing Control Registers. */
7396 { HOSTCC_MODE, TG3_FL_NOT_5705,
7397 0x00000000, 0x00000004 },
7398 { HOSTCC_MODE, TG3_FL_5705,
7399 0x00000000, 0x000000f6 },
7400 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7401 0x00000000, 0xffffffff },
7402 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7403 0x00000000, 0x000003ff },
7404 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7405 0x00000000, 0xffffffff },
7406 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7407 0x00000000, 0x000003ff },
7408 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7409 0x00000000, 0xffffffff },
7410 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7411 0x00000000, 0x000000ff },
7412 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7413 0x00000000, 0xffffffff },
7414 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7415 0x00000000, 0x000000ff },
7416 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7417 0x00000000, 0xffffffff },
7418 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7419 0x00000000, 0xffffffff },
7420 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7421 0x00000000, 0xffffffff },
7422 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7423 0x00000000, 0x000000ff },
7424 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7425 0x00000000, 0xffffffff },
7426 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7427 0x00000000, 0x000000ff },
7428 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7429 0x00000000, 0xffffffff },
7430 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7431 0x00000000, 0xffffffff },
7432 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7433 0x00000000, 0xffffffff },
7434 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7435 0x00000000, 0xffffffff },
7436 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7437 0x00000000, 0xffffffff },
7438 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7439 0xffffffff, 0x00000000 },
7440 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7441 0xffffffff, 0x00000000 },
7442
7443 /* Buffer Manager Control Registers. */
7444 { BUFMGR_MB_POOL_ADDR, 0x0000,
7445 0x00000000, 0x007fff80 },
7446 { BUFMGR_MB_POOL_SIZE, 0x0000,
7447 0x00000000, 0x007fffff },
7448 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7449 0x00000000, 0x0000003f },
7450 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7451 0x00000000, 0x000001ff },
7452 { BUFMGR_MB_HIGH_WATER, 0x0000,
7453 0x00000000, 0x000001ff },
7454 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7455 0xffffffff, 0x00000000 },
7456 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7457 0xffffffff, 0x00000000 },
7458
7459 /* Mailbox Registers */
7460 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7461 0x00000000, 0x000001ff },
7462 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7463 0x00000000, 0x000001ff },
7464 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7465 0x00000000, 0x000007ff },
7466 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7467 0x00000000, 0x000001ff },
7468
7469 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7470 };
7471
7472 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7473 is_5705 = 1;
7474 else
7475 is_5705 = 0;
7476
7477 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7478 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7479 continue;
7480
7481 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7482 continue;
7483
7484 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7485 (reg_tbl[i].flags & TG3_FL_NOT_5788))
7486 continue;
7487
7488 offset = (u32) reg_tbl[i].offset;
7489 read_mask = reg_tbl[i].read_mask;
7490 write_mask = reg_tbl[i].write_mask;
7491
7492 /* Save the original register content */
7493 save_val = tr32(offset);
7494
7495 /* Determine the read-only value. */
7496 read_val = save_val & read_mask;
7497
7498 /* Write zero to the register, then make sure the read-only bits
7499 * are not changed and the read/write bits are all zeros.
7500 */
7501 tw32(offset, 0);
7502
7503 val = tr32(offset);
7504
7505 /* Test the read-only and read/write bits. */
7506 if (((val & read_mask) != read_val) || (val & write_mask))
7507 goto out;
7508
7509 /* Write ones to all the bits defined by RdMask and WrMask, then
7510 * make sure the read-only bits are not changed and the
7511 * read/write bits are all ones.
7512 */
7513 tw32(offset, read_mask | write_mask);
7514
7515 val = tr32(offset);
7516
7517 /* Test the read-only bits. */
7518 if ((val & read_mask) != read_val)
7519 goto out;
7520
7521 /* Test the read/write bits. */
7522 if ((val & write_mask) != write_mask)
7523 goto out;
7524
7525 tw32(offset, save_val);
7526 }
7527
7528 return 0;
7529
7530out:
7531 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7532 tw32(offset, save_val);
7533 return -EIO;
7534}
7535
7942e1db
MC		 7536static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7537{
7538 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7539 int i;
7540 u32 j;
7541
7542 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7543 for (j = 0; j < len; j += 4) {
7544 u32 val;
7545
7546 tg3_write_mem(tp, offset + j, test_pattern[i]);
7547 tg3_read_mem(tp, offset + j, &val);
7548 if (val != test_pattern[i])
7549 return -EIO;
7550 }
7551 }
7552 return 0;
7553}
7554
7555static int tg3_test_memory(struct tg3 *tp)
7556{
7557 static struct mem_entry {
7558 u32 offset;
7559 u32 len;
7560 } mem_tbl_570x[] = {
7561 { 0x00000000, 0x01000},
7562 { 0x00002000, 0x1c000},
7563 { 0xffffffff, 0x00000}
7564 }, mem_tbl_5705[] = {
7565 { 0x00000100, 0x0000c},
7566 { 0x00000200, 0x00008},
7567 { 0x00000b50, 0x00400},
7568 { 0x00004000, 0x00800},
7569 { 0x00006000, 0x01000},
7570 { 0x00008000, 0x02000},
7571 { 0x00010000, 0x0e000},
7572 { 0xffffffff, 0x00000}
7573 };
7574 struct mem_entry *mem_tbl;
7575 int err = 0;
7576 int i;
7577
7578 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7579 mem_tbl = mem_tbl_5705;
7580 else
7581 mem_tbl = mem_tbl_570x;
7582
7583 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7584 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7585 mem_tbl[i].len)) != 0)
7586 break;
7587 }
7588
7589 return err;
7590}
7591
c76949a6
MC		 7592static int tg3_test_loopback(struct tg3 *tp)
7593{
7594 u32 mac_mode, send_idx, rx_start_idx, rx_idx, tx_idx, opaque_key;
7595 u32 desc_idx;
7596 struct sk_buff *skb, *rx_skb;
7597 u8 *tx_data;
7598 dma_addr_t map;
7599 int num_pkts, tx_len, rx_len, i, err;
7600 struct tg3_rx_buffer_desc *desc;
7601
7602 if (!netif_running(tp->dev))
7603 return -ENODEV;
7604
7605 err = -EIO;
7606
7607 tg3_abort_hw(tp, 1);
7608
7609 /* Clearing this flag to keep interrupts disabled */
7610 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7611 tg3_reset_hw(tp);
7612
7613 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7614 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7615 MAC_MODE_PORT_MODE_GMII;
7616 tw32(MAC_MODE, mac_mode);
7617
7618 tx_len = 1514;
7619 skb = dev_alloc_skb(tx_len);
7620 tx_data = skb_put(skb, tx_len);
7621 memcpy(tx_data, tp->dev->dev_addr, 6);
7622 memset(tx_data + 6, 0x0, 8);
7623
7624 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7625
7626 for (i = 14; i < tx_len; i++)
7627 tx_data[i] = (u8) (i & 0xff);
7628
7629 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7630
7631 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7632 HOSTCC_MODE_NOW);
7633
7634 udelay(10);
7635
7636 rx_start_idx = tp->hw_status->idx[0].rx_producer;
7637
7638 send_idx = 0;
7639 num_pkts = 0;
7640
7641 tg3_set_txd(tp, send_idx, map, tx_len, 0, 1);
7642
7643 send_idx++;
7644 num_pkts++;
7645
7646 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx);
7647 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
7648
7649 udelay(10);
7650
7651 for (i = 0; i < 10; i++) {
7652 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7653 HOSTCC_MODE_NOW);
7654
7655 udelay(10);
7656
7657 tx_idx = tp->hw_status->idx[0].tx_consumer;
7658 rx_idx = tp->hw_status->idx[0].rx_producer;
7659 if ((tx_idx == send_idx) &&
7660 (rx_idx == (rx_start_idx + num_pkts)))
7661 break;
7662 }
7663
7664 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
7665 dev_kfree_skb(skb);
7666
7667 if (tx_idx != send_idx)
7668 goto out;
7669
7670 if (rx_idx != rx_start_idx + num_pkts)
7671 goto out;
7672
7673 desc = &tp->rx_rcb[rx_start_idx];
7674 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
7675 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
7676 if (opaque_key != RXD_OPAQUE_RING_STD)
7677 goto out;
7678
7679 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
7680 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
7681 goto out;
7682
7683 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
7684 if (rx_len != tx_len)
7685 goto out;
7686
7687 rx_skb = tp->rx_std_buffers[desc_idx].skb;
7688
7689 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
7690 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
7691
7692 for (i = 14; i < tx_len; i++) {
7693 if (*(rx_skb->data + i) != (u8) (i & 0xff))
7694 goto out;
7695 }
7696 err = 0;
7697
7698 /* tg3_free_rings will unmap and free the rx_skb */
7699out:
7700 return err;
7701}
7702
4cafd3f5
MC		 7703static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
7704 u64 *data)
7705{
566f86ad
MC		 7706 struct tg3 *tp = netdev_priv(dev);
7707
7708 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
7709
7710 if (tg3_test_nvram(tp) != 0) {
7711 etest->flags |= ETH_TEST_FL_FAILED;
7712 data[0] = 1;
7713 }
ca43007a
MC		 7714 if (tg3_test_link(tp) != 0) {
7715 etest->flags |= ETH_TEST_FL_FAILED;
7716 data[1] = 1;
7717 }
a71116d1
MC		 7718 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7719 if (netif_running(dev))
7720 tg3_netif_stop(tp);
7721
7722 spin_lock_irq(&tp->lock);
7723 spin_lock(&tp->tx_lock);
7724
7725 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
7726 tg3_nvram_lock(tp);
7727 tg3_halt_cpu(tp, RX_CPU_BASE);
7728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7729 tg3_halt_cpu(tp, TX_CPU_BASE);
7730 tg3_nvram_unlock(tp);
7731
7732 if (tg3_test_registers(tp) != 0) {
7733 etest->flags |= ETH_TEST_FL_FAILED;
7734 data[2] = 1;
7735 }
7942e1db
MC		 7736 if (tg3_test_memory(tp) != 0) {
7737 etest->flags |= ETH_TEST_FL_FAILED;
7738 data[3] = 1;
7739 }
c76949a6
MC		 7740 if (tg3_test_loopback(tp) != 0) {
7741 etest->flags |= ETH_TEST_FL_FAILED;
7742 data[4] = 1;
7743 }
a71116d1 7744
d4bc3927
MC		 7745 spin_unlock(&tp->tx_lock);
7746 spin_unlock_irq(&tp->lock);
7747 if (tg3_test_interrupt(tp) != 0) {
7748 etest->flags |= ETH_TEST_FL_FAILED;
7749 data[5] = 1;
7750 }
7751 spin_lock_irq(&tp->lock);
7752 spin_lock(&tp->tx_lock);
7753
a71116d1
MC		 7754 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7755 if (netif_running(dev)) {
7756 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7757 tg3_init_hw(tp);
7758 tg3_netif_start(tp);
7759 }
7760 spin_unlock(&tp->tx_lock);
7761 spin_unlock_irq(&tp->lock);
7762 }
4cafd3f5
MC		 7763}
7764
1da177e4
LT		 7765static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7766{
7767 struct mii_ioctl_data *data = if_mii(ifr);
7768 struct tg3 *tp = netdev_priv(dev);
7769 int err;
7770
7771 switch(cmd) {
7772 case SIOCGMIIPHY:
7773 data->phy_id = PHY_ADDR;
7774
7775 /* fallthru */
7776 case SIOCGMIIREG: {
7777 u32 mii_regval;
7778
7779 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7780 break; /* We have no PHY */
7781
7782 spin_lock_irq(&tp->lock);
7783 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7784 spin_unlock_irq(&tp->lock);
7785
7786 data->val_out = mii_regval;
7787
7788 return err;
7789 }
7790
7791 case SIOCSMIIREG:
7792 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7793 break; /* We have no PHY */
7794
7795 if (!capable(CAP_NET_ADMIN))
7796 return -EPERM;
7797
7798 spin_lock_irq(&tp->lock);
7799 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7800 spin_unlock_irq(&tp->lock);
7801
7802 return err;
7803
7804 default:
7805 /* do nothing */
7806 break;
7807 }
7808 return -EOPNOTSUPP;
7809}
7810
7811#if TG3_VLAN_TAG_USED
7812static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7813{
7814 struct tg3 *tp = netdev_priv(dev);
7815
7816 spin_lock_irq(&tp->lock);
7817 spin_lock(&tp->tx_lock);
7818
7819 tp->vlgrp = grp;
7820
7821 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7822 __tg3_set_rx_mode(dev);
7823
7824 spin_unlock(&tp->tx_lock);
7825 spin_unlock_irq(&tp->lock);
7826}
7827
7828static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7829{
7830 struct tg3 *tp = netdev_priv(dev);
7831
7832 spin_lock_irq(&tp->lock);
7833 spin_lock(&tp->tx_lock);
7834 if (tp->vlgrp)
7835 tp->vlgrp->vlan_devices[vid] = NULL;
7836 spin_unlock(&tp->tx_lock);
7837 spin_unlock_irq(&tp->lock);
7838}
7839#endif
7840
15f9850d
DM		 7841static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7842{
7843 struct tg3 *tp = netdev_priv(dev);
7844
7845 memcpy(ec, &tp->coal, sizeof(*ec));
7846 return 0;
7847}
7848
1da177e4
LT		 7849static struct ethtool_ops tg3_ethtool_ops = {
7850 .get_settings = tg3_get_settings,
7851 .set_settings = tg3_set_settings,
7852 .get_drvinfo = tg3_get_drvinfo,
7853 .get_regs_len = tg3_get_regs_len,
7854 .get_regs = tg3_get_regs,
7855 .get_wol = tg3_get_wol,
7856 .set_wol = tg3_set_wol,
7857 .get_msglevel = tg3_get_msglevel,
7858 .set_msglevel = tg3_set_msglevel,
7859 .nway_reset = tg3_nway_reset,
7860 .get_link = ethtool_op_get_link,
7861 .get_eeprom_len = tg3_get_eeprom_len,
7862 .get_eeprom = tg3_get_eeprom,
7863 .set_eeprom = tg3_set_eeprom,
7864 .get_ringparam = tg3_get_ringparam,
7865 .set_ringparam = tg3_set_ringparam,
7866 .get_pauseparam = tg3_get_pauseparam,
7867 .set_pauseparam = tg3_set_pauseparam,
7868 .get_rx_csum = tg3_get_rx_csum,
7869 .set_rx_csum = tg3_set_rx_csum,
7870 .get_tx_csum = ethtool_op_get_tx_csum,
7871 .set_tx_csum = tg3_set_tx_csum,
7872 .get_sg = ethtool_op_get_sg,
7873 .set_sg = ethtool_op_set_sg,
7874#if TG3_TSO_SUPPORT != 0
7875 .get_tso = ethtool_op_get_tso,
7876 .set_tso = tg3_set_tso,
7877#endif
4cafd3f5
MC		 7878 .self_test_count = tg3_get_test_count,
7879 .self_test = tg3_self_test,
1da177e4
LT		 7880 .get_strings = tg3_get_strings,
7881 .get_stats_count = tg3_get_stats_count,
7882 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 7883 .get_coalesce = tg3_get_coalesce,
1da177e4
LT		 7884};
7885
7886static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7887{
7888 u32 cursize, val;
7889
7890 tp->nvram_size = EEPROM_CHIP_SIZE;
7891
7892 if (tg3_nvram_read(tp, 0, &val) != 0)
7893 return;
7894
7895 if (swab32(val) != TG3_EEPROM_MAGIC)
7896 return;
7897
7898 /*
7899 * Size the chip by reading offsets at increasing powers of two.
7900 * When we encounter our validation signature, we know the addressing
7901 * has wrapped around, and thus have our chip size.
7902 */
7903 cursize = 0x800;
7904
7905 while (cursize < tp->nvram_size) {
7906 if (tg3_nvram_read(tp, cursize, &val) != 0)
7907 return;
7908
7909 if (swab32(val) == TG3_EEPROM_MAGIC)
7910 break;
7911
7912 cursize <<= 1;
7913 }
7914
7915 tp->nvram_size = cursize;
7916}
7917
7918static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7919{
7920 u32 val;
7921
7922 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7923 if (val != 0) {
7924 tp->nvram_size = (val >> 16) * 1024;
7925 return;
7926 }
7927 }
7928 tp->nvram_size = 0x20000;
7929}
7930
7931static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7932{
7933 u32 nvcfg1;
7934
7935 nvcfg1 = tr32(NVRAM_CFG1);
7936 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7937 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7938 }
7939 else {
7940 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7941 tw32(NVRAM_CFG1, nvcfg1);
7942 }
7943
85e94ced 7944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7945 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7946 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7947 tp->nvram_jedecnum = JEDEC_ATMEL;
7948 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7949 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7950 break;
7951 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7952 tp->nvram_jedecnum = JEDEC_ATMEL;
7953 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7954 break;
7955 case FLASH_VENDOR_ATMEL_EEPROM:
7956 tp->nvram_jedecnum = JEDEC_ATMEL;
7957 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7958 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7959 break;
7960 case FLASH_VENDOR_ST:
7961 tp->nvram_jedecnum = JEDEC_ST;
7962 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7963 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7964 break;
7965 case FLASH_VENDOR_SAIFUN:
7966 tp->nvram_jedecnum = JEDEC_SAIFUN;
7967 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7968 break;
7969 case FLASH_VENDOR_SST_SMALL:
7970 case FLASH_VENDOR_SST_LARGE:
7971 tp->nvram_jedecnum = JEDEC_SST;
7972 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7973 break;
7974 }
7975 }
7976 else {
7977 tp->nvram_jedecnum = JEDEC_ATMEL;
7978 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7979 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7980 }
7981}
7982
361b4ac2
MC		 7983static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7984{
7985 u32 nvcfg1;
7986
7987 nvcfg1 = tr32(NVRAM_CFG1);
7988
e6af301b
MC		 7989 /* NVRAM protection for TPM */
7990 if (nvcfg1 & (1 << 27))
7991 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7992
361b4ac2
MC		 7993 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7994 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7995 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
7996 tp->nvram_jedecnum = JEDEC_ATMEL;
7997 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7998 break;
7999 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8000 tp->nvram_jedecnum = JEDEC_ATMEL;
8001 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8002 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8003 break;
8004 case FLASH_5752VENDOR_ST_M45PE10:
8005 case FLASH_5752VENDOR_ST_M45PE20:
8006 case FLASH_5752VENDOR_ST_M45PE40:
8007 tp->nvram_jedecnum = JEDEC_ST;
8008 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8009 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8010 break;
8011 }
8012
8013 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8014 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8015 case FLASH_5752PAGE_SIZE_256:
8016 tp->nvram_pagesize = 256;
8017 break;
8018 case FLASH_5752PAGE_SIZE_512:
8019 tp->nvram_pagesize = 512;
8020 break;
8021 case FLASH_5752PAGE_SIZE_1K:
8022 tp->nvram_pagesize = 1024;
8023 break;
8024 case FLASH_5752PAGE_SIZE_2K:
8025 tp->nvram_pagesize = 2048;
8026 break;
8027 case FLASH_5752PAGE_SIZE_4K:
8028 tp->nvram_pagesize = 4096;
8029 break;
8030 case FLASH_5752PAGE_SIZE_264:
8031 tp->nvram_pagesize = 264;
8032 break;
8033 }
8034 }
8035 else {
8036 /* For eeprom, set pagesize to maximum eeprom size */
8037 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8038
8039 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8040 tw32(NVRAM_CFG1, nvcfg1);
8041 }
8042}
8043
1da177e4
LT		 8044/* Chips other than 5700/5701 use the NVRAM for fetching info. */
8045static void __devinit tg3_nvram_init(struct tg3 *tp)
8046{
8047 int j;
8048
8049 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8050 return;
8051
8052 tw32_f(GRC_EEPROM_ADDR,
8053 (EEPROM_ADDR_FSM_RESET |
8054 (EEPROM_DEFAULT_CLOCK_PERIOD <<
8055 EEPROM_ADDR_CLKPERD_SHIFT)));
8056
8057 /* XXX schedule_timeout() ... */
8058 for (j = 0; j < 100; j++)
8059 udelay(10);
8060
8061 /* Enable seeprom accesses. */
8062 tw32_f(GRC_LOCAL_CTRL,
8063 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8064 udelay(100);
8065
8066 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8067 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8068 tp->tg3_flags |= TG3_FLAG_NVRAM;
8069
e6af301b 8070 tg3_enable_nvram_access(tp);
1da177e4 8071
361b4ac2
MC		 8072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8073 tg3_get_5752_nvram_info(tp);
8074 else
8075 tg3_get_nvram_info(tp);
8076
1da177e4
LT		 8077 tg3_get_nvram_size(tp);
8078
e6af301b 8079 tg3_disable_nvram_access(tp);
1da177e4
LT		 8080
8081 } else {
8082 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8083
8084 tg3_get_eeprom_size(tp);
8085 }
8086}
8087
8088static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8089 u32 offset, u32 *val)
8090{
8091 u32 tmp;
8092 int i;
8093
8094 if (offset > EEPROM_ADDR_ADDR_MASK ||
8095 (offset % 4) != 0)
8096 return -EINVAL;
8097
8098 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8099 EEPROM_ADDR_DEVID_MASK |
8100 EEPROM_ADDR_READ);
8101 tw32(GRC_EEPROM_ADDR,
8102 tmp |
8103 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8104 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8105 EEPROM_ADDR_ADDR_MASK) |
8106 EEPROM_ADDR_READ | EEPROM_ADDR_START);
8107
8108 for (i = 0; i < 10000; i++) {
8109 tmp = tr32(GRC_EEPROM_ADDR);
8110
8111 if (tmp & EEPROM_ADDR_COMPLETE)
8112 break;
8113 udelay(100);
8114 }
8115 if (!(tmp & EEPROM_ADDR_COMPLETE))
8116 return -EBUSY;
8117
8118 *val = tr32(GRC_EEPROM_DATA);
8119 return 0;
8120}
8121
8122#define NVRAM_CMD_TIMEOUT 10000
8123
8124static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8125{
8126 int i;
8127
8128 tw32(NVRAM_CMD, nvram_cmd);
8129 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8130 udelay(10);
8131 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8132 udelay(10);
8133 break;
8134 }
8135 }
8136 if (i == NVRAM_CMD_TIMEOUT) {
8137 return -EBUSY;
8138 }
8139 return 0;
8140}
8141
8142static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8143{
8144 int ret;
8145
8146 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8147 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8148 return -EINVAL;
8149 }
8150
8151 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8152 return tg3_nvram_read_using_eeprom(tp, offset, val);
8153
8154 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8155 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8156 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8157
8158 offset = ((offset / tp->nvram_pagesize) <<
8159 ATMEL_AT45DB0X1B_PAGE_POS) +
8160 (offset % tp->nvram_pagesize);
8161 }
8162
8163 if (offset > NVRAM_ADDR_MSK)
8164 return -EINVAL;
8165
8166 tg3_nvram_lock(tp);
8167
e6af301b 8168 tg3_enable_nvram_access(tp);
1da177e4
LT		 8169
8170 tw32(NVRAM_ADDR, offset);
8171 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8172 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8173
8174 if (ret == 0)
8175 *val = swab32(tr32(NVRAM_RDDATA));
8176
8177 tg3_nvram_unlock(tp);
8178
e6af301b 8179 tg3_disable_nvram_access(tp);
1da177e4
LT		 8180
8181 return ret;
8182}
8183
8184static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8185 u32 offset, u32 len, u8 *buf)
8186{
8187 int i, j, rc = 0;
8188 u32 val;
8189
8190 for (i = 0; i < len; i += 4) {
8191 u32 addr, data;
8192
8193 addr = offset + i;
8194
8195 memcpy(&data, buf + i, 4);
8196
8197 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8198
8199 val = tr32(GRC_EEPROM_ADDR);
8200 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8201
8202 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8203 EEPROM_ADDR_READ);
8204 tw32(GRC_EEPROM_ADDR, val |
8205 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8206 (addr & EEPROM_ADDR_ADDR_MASK) |
8207 EEPROM_ADDR_START |
8208 EEPROM_ADDR_WRITE);
8209
8210 for (j = 0; j < 10000; j++) {
8211 val = tr32(GRC_EEPROM_ADDR);
8212
8213 if (val & EEPROM_ADDR_COMPLETE)
8214 break;
8215 udelay(100);
8216 }
8217 if (!(val & EEPROM_ADDR_COMPLETE)) {
8218 rc = -EBUSY;
8219 break;
8220 }
8221 }
8222
8223 return rc;
8224}
8225
8226/* offset and length are dword aligned */
8227static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8228 u8 *buf)
8229{
8230 int ret = 0;
8231 u32 pagesize = tp->nvram_pagesize;
8232 u32 pagemask = pagesize - 1;
8233 u32 nvram_cmd;
8234 u8 *tmp;
8235
8236 tmp = kmalloc(pagesize, GFP_KERNEL);
8237 if (tmp == NULL)
8238 return -ENOMEM;
8239
8240 while (len) {
8241 int j;
e6af301b 8242 u32 phy_addr, page_off, size;
1da177e4
LT		 8243
8244 phy_addr = offset & ~pagemask;
8245
8246 for (j = 0; j < pagesize; j += 4) {
8247 if ((ret = tg3_nvram_read(tp, phy_addr + j,
8248 (u32 *) (tmp + j))))
8249 break;
8250 }
8251 if (ret)
8252 break;
8253
8254 page_off = offset & pagemask;
8255 size = pagesize;
8256 if (len < size)
8257 size = len;
8258
8259 len -= size;
8260
8261 memcpy(tmp + page_off, buf, size);
8262
8263 offset = offset + (pagesize - page_off);
8264
e6af301b 8265 tg3_enable_nvram_access(tp);
1da177e4
LT		 8266
8267 /*
8268 * Before we can erase the flash page, we need
8269 * to issue a special "write enable" command.
8270 */
8271 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8272
8273 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8274 break;
8275
8276 /* Erase the target page */
8277 tw32(NVRAM_ADDR, phy_addr);
8278
8279 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8280 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8281
8282 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8283 break;
8284
8285 /* Issue another write enable to start the write. */
8286 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8287
8288 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8289 break;
8290
8291 for (j = 0; j < pagesize; j += 4) {
8292 u32 data;
8293
8294 data = *((u32 *) (tmp + j));
8295 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8296
8297 tw32(NVRAM_ADDR, phy_addr + j);
8298
8299 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8300 NVRAM_CMD_WR;
8301
8302 if (j == 0)
8303 nvram_cmd |= NVRAM_CMD_FIRST;
8304 else if (j == (pagesize - 4))
8305 nvram_cmd |= NVRAM_CMD_LAST;
8306
8307 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8308 break;
8309 }
8310 if (ret)
8311 break;
8312 }
8313
8314 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8315 tg3_nvram_exec_cmd(tp, nvram_cmd);
8316
8317 kfree(tmp);
8318
8319 return ret;
8320}
8321
8322/* offset and length are dword aligned */
8323static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8324 u8 *buf)
8325{
8326 int i, ret = 0;
8327
8328 for (i = 0; i < len; i += 4, offset += 4) {
8329 u32 data, page_off, phy_addr, nvram_cmd;
8330
8331 memcpy(&data, buf + i, 4);
8332 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8333
8334 page_off = offset % tp->nvram_pagesize;
8335
8336 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8337 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8338
8339 phy_addr = ((offset / tp->nvram_pagesize) <<
8340 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8341 }
8342 else {
8343 phy_addr = offset;
8344 }
8345
8346 tw32(NVRAM_ADDR, phy_addr);
8347
8348 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8349
8350 if ((page_off == 0) || (i == 0))
8351 nvram_cmd |= NVRAM_CMD_FIRST;
8352 else if (page_off == (tp->nvram_pagesize - 4))
8353 nvram_cmd |= NVRAM_CMD_LAST;
8354
8355 if (i == (len - 4))
8356 nvram_cmd |= NVRAM_CMD_LAST;
8357
8358 if ((tp->nvram_jedecnum == JEDEC_ST) &&
8359 (nvram_cmd & NVRAM_CMD_FIRST)) {
8360
8361 if ((ret = tg3_nvram_exec_cmd(tp,
8362 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8363 NVRAM_CMD_DONE)))
8364
8365 break;
8366 }
8367 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8368 /* We always do complete word writes to eeprom. */
8369 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8370 }
8371
8372 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8373 break;
8374 }
8375 return ret;
8376}
8377
8378/* offset and length are dword aligned */
8379static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8380{
8381 int ret;
8382
8383 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8384 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8385 return -EINVAL;
8386 }
8387
8388 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 8389 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8390 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 8391 udelay(40);
8392 }
8393
8394 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8395 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8396 }
8397 else {
8398 u32 grc_mode;
8399
8400 tg3_nvram_lock(tp);
8401
e6af301b
MC		 8402 tg3_enable_nvram_access(tp);
8403 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8404 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 8405 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 8406
8407 grc_mode = tr32(GRC_MODE);
8408 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8409
8410 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8411 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8412
8413 ret = tg3_nvram_write_block_buffered(tp, offset, len,
8414 buf);
8415 }
8416 else {
8417 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8418 buf);
8419 }
8420
8421 grc_mode = tr32(GRC_MODE);
8422 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8423
e6af301b 8424 tg3_disable_nvram_access(tp);
1da177e4
LT		 8425 tg3_nvram_unlock(tp);
8426 }
8427
8428 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 8429 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 8430 udelay(40);
8431 }
8432
8433 return ret;
8434}
8435
8436struct subsys_tbl_ent {
8437 u16 subsys_vendor, subsys_devid;
8438 u32 phy_id;
8439};
8440
8441static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8442 /* Broadcom boards. */
8443 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8444 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8445 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8446 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
8447 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8448 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8449 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
8450 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8451 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8452 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8453 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8454
8455 /* 3com boards. */
8456 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8457 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8458 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
8459 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8460 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8461
8462 /* DELL boards. */
8463 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8464 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8465 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8466 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8467
8468 /* Compaq boards. */
8469 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8470 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8471 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
8472 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8473 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8474
8475 /* IBM boards. */
8476 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8477};
8478
8479static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8480{
8481 int i;
8482
8483 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8484 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8485 tp->pdev->subsystem_vendor) &&
8486 (subsys_id_to_phy_id[i].subsys_devid ==
8487 tp->pdev->subsystem_device))
8488 return &subsys_id_to_phy_id[i];
8489 }
8490 return NULL;
8491}
8492
7d0c41ef
MC		 8493/* Since this function may be called in D3-hot power state during
8494 * tg3_init_one(), only config cycles are allowed.
8495 */
8496static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 8497{
1da177e4 8498 u32 val;
7d0c41ef
MC		 8499
8500 /* Make sure register accesses (indirect or otherwise)
8501 * will function correctly.
8502 */
8503 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8504 tp->misc_host_ctrl);
1da177e4
LT		 8505
8506 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 8507 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8508
1da177e4
LT		 8509 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8510 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8511 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 8512 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8513 int eeprom_phy_serdes = 0;
1da177e4
LT		 8514
8515 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8516 tp->nic_sram_data_cfg = nic_cfg;
8517
8518 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8519 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8520 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8521 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8522 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8523 (ver > 0) && (ver < 0x100))
8524 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8525
1da177e4
LT		 8526 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8527 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8528 eeprom_phy_serdes = 1;
8529
8530 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8531 if (nic_phy_id != 0) {
8532 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8533 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8534
8535 eeprom_phy_id = (id1 >> 16) << 10;
8536 eeprom_phy_id |= (id2 & 0xfc00) << 16;
8537 eeprom_phy_id |= (id2 & 0x03ff) << 0;
8538 } else
8539 eeprom_phy_id = 0;
8540
7d0c41ef
MC		 8541 tp->phy_id = eeprom_phy_id;
8542 if (eeprom_phy_serdes)
8543 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8544
cbf46853 8545 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8546 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8547 SHASTA_EXT_LED_MODE_MASK);
cbf46853 8548 else
1da177e4
LT		 8549 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8550
8551 switch (led_cfg) {
8552 default:
8553 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8554 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8555 break;
8556
8557 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8558 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8559 break;
8560
8561 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8562 tp->led_ctrl = LED_CTRL_MODE_MAC;
8563 break;
8564
8565 case SHASTA_EXT_LED_SHARED:
8566 tp->led_ctrl = LED_CTRL_MODE_SHARED;
8567 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8568 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
8569 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8570 LED_CTRL_MODE_PHY_2);
8571 break;
8572
8573 case SHASTA_EXT_LED_MAC:
8574 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
8575 break;
8576
8577 case SHASTA_EXT_LED_COMBO:
8578 tp->led_ctrl = LED_CTRL_MODE_COMBO;
8579 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
8580 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8581 LED_CTRL_MODE_PHY_2);
8582 break;
8583
8584 };
8585
8586 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
8588 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
8589 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8590
8591 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8592 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8593 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
8594 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
8595
8596 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8597 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 8598 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8599 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
8600 }
8601 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
8602 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
8603
8604 if (cfg2 & (1 << 17))
8605 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
8606
8607 /* serdes signal pre-emphasis in register 0x590 set by */
8608 /* bootcode if bit 18 is set */
8609 if (cfg2 & (1 << 18))
8610 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8611 }
7d0c41ef
MC		 8612}
8613
8614static int __devinit tg3_phy_probe(struct tg3 *tp)
8615{
8616 u32 hw_phy_id_1, hw_phy_id_2;
8617 u32 hw_phy_id, hw_phy_id_masked;
8618 int err;
1da177e4
LT		 8619
8620 /* Reading the PHY ID register can conflict with ASF
8621 * firwmare access to the PHY hardware.
8622 */
8623 err = 0;
8624 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
8625 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
8626 } else {
8627 /* Now read the physical PHY_ID from the chip and verify
8628 * that it is sane. If it doesn't look good, we fall back
8629 * to either the hard-coded table based PHY_ID and failing
8630 * that the value found in the eeprom area.
8631 */
8632 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
8633 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
8634
8635 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
8636 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
8637 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
8638
8639 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
8640 }
8641
8642 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
8643 tp->phy_id = hw_phy_id;
8644 if (hw_phy_id_masked == PHY_ID_BCM8002)
8645 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8646 } else {
7d0c41ef
MC		 8647 if (tp->phy_id != PHY_ID_INVALID) {
8648 /* Do nothing, phy ID already set up in
8649 * tg3_get_eeprom_hw_cfg().
8650 */
1da177e4
LT		 8651 } else {
8652 struct subsys_tbl_ent *p;
8653
8654 /* No eeprom signature? Try the hardcoded
8655 * subsys device table.
8656 */
8657 p = lookup_by_subsys(tp);
8658 if (!p)
8659 return -ENODEV;
8660
8661 tp->phy_id = p->phy_id;
8662 if (!tp->phy_id ||
8663 tp->phy_id == PHY_ID_BCM8002)
8664 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8665 }
8666 }
8667
8668 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8669 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8670 u32 bmsr, adv_reg, tg3_ctrl;
8671
8672 tg3_readphy(tp, MII_BMSR, &bmsr);
8673 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
8674 (bmsr & BMSR_LSTATUS))
8675 goto skip_phy_reset;
8676
8677 err = tg3_phy_reset(tp);
8678 if (err)
8679 return err;
8680
8681 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
8682 ADVERTISE_100HALF | ADVERTISE_100FULL |
8683 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
8684 tg3_ctrl = 0;
8685 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
8686 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
8687 MII_TG3_CTRL_ADV_1000_FULL);
8688 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8689 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
8690 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
8691 MII_TG3_CTRL_ENABLE_AS_MASTER);
8692 }
8693
8694 if (!tg3_copper_is_advertising_all(tp)) {
8695 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8696
8697 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8698 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8699
8700 tg3_writephy(tp, MII_BMCR,
8701 BMCR_ANENABLE | BMCR_ANRESTART);
8702 }
8703 tg3_phy_set_wirespeed(tp);
8704
8705 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8706 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8707 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8708 }
8709
8710skip_phy_reset:
8711 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8712 err = tg3_init_5401phy_dsp(tp);
8713 if (err)
8714 return err;
8715 }
8716
8717 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
8718 err = tg3_init_5401phy_dsp(tp);
8719 }
8720
1da177e4
LT		 8721 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8722 tp->link_config.advertising =
8723 (ADVERTISED_1000baseT_Half |
8724 ADVERTISED_1000baseT_Full |
8725 ADVERTISED_Autoneg |
8726 ADVERTISED_FIBRE);
8727 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8728 tp->link_config.advertising &=
8729 ~(ADVERTISED_1000baseT_Half |
8730 ADVERTISED_1000baseT_Full);
8731
8732 return err;
8733}
8734
8735static void __devinit tg3_read_partno(struct tg3 *tp)
8736{
8737 unsigned char vpd_data[256];
8738 int i;
8739
8740 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8741 /* Sun decided not to put the necessary bits in the
8742 * NVRAM of their onboard tg3 parts :(
8743 */
8744 strcpy(tp->board_part_number, "Sun 570X");
8745 return;
8746 }
8747
8748 for (i = 0; i < 256; i += 4) {
8749 u32 tmp;
8750
8751 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
8752 goto out_not_found;
8753
8754 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
8755 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
8756 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
8757 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
8758 }
8759
8760 /* Now parse and find the part number. */
8761 for (i = 0; i < 256; ) {
8762 unsigned char val = vpd_data[i];
8763 int block_end;
8764
8765 if (val == 0x82 || val == 0x91) {
8766 i = (i + 3 +
8767 (vpd_data[i + 1] +
8768 (vpd_data[i + 2] << 8)));
8769 continue;
8770 }
8771
8772 if (val != 0x90)
8773 goto out_not_found;
8774
8775 block_end = (i + 3 +
8776 (vpd_data[i + 1] +
8777 (vpd_data[i + 2] << 8)));
8778 i += 3;
8779 while (i < block_end) {
8780 if (vpd_data[i + 0] == 'P' &&
8781 vpd_data[i + 1] == 'N') {
8782 int partno_len = vpd_data[i + 2];
8783
8784 if (partno_len > 24)
8785 goto out_not_found;
8786
8787 memcpy(tp->board_part_number,
8788 &vpd_data[i + 3],
8789 partno_len);
8790
8791 /* Success. */
8792 return;
8793 }
8794 }
8795
8796 /* Part number not found. */
8797 goto out_not_found;
8798 }
8799
8800out_not_found:
8801 strcpy(tp->board_part_number, "none");
8802}
8803
8804#ifdef CONFIG_SPARC64
8805static int __devinit tg3_is_sun_570X(struct tg3 *tp)
8806{
8807 struct pci_dev *pdev = tp->pdev;
8808 struct pcidev_cookie *pcp = pdev->sysdata;
8809
8810 if (pcp != NULL) {
8811 int node = pcp->prom_node;
8812 u32 venid;
8813 int err;
8814
8815 err = prom_getproperty(node, "subsystem-vendor-id",
8816 (char *) &venid, sizeof(venid));
8817 if (err == 0 || err == -1)
8818 return 0;
8819 if (venid == PCI_VENDOR_ID_SUN)
8820 return 1;
8821 }
8822 return 0;
8823}
8824#endif
8825
8826static int __devinit tg3_get_invariants(struct tg3 *tp)
8827{
8828 static struct pci_device_id write_reorder_chipsets[] = {
8829 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8830 PCI_DEVICE_ID_INTEL_82801AA_8) },
8831 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8832 PCI_DEVICE_ID_INTEL_82801AB_8) },
8833 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8834 PCI_DEVICE_ID_INTEL_82801BA_11) },
8835 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8836 PCI_DEVICE_ID_INTEL_82801BA_6) },
8837 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
8838 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
8839 { },
8840 };
8841 u32 misc_ctrl_reg;
8842 u32 cacheline_sz_reg;
8843 u32 pci_state_reg, grc_misc_cfg;
8844 u32 val;
8845 u16 pci_cmd;
8846 int err;
8847
8848#ifdef CONFIG_SPARC64
8849 if (tg3_is_sun_570X(tp))
8850 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
8851#endif
8852
8853 /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8854 * reordering to the mailbox registers done by the host
8855 * controller can cause major troubles. We read back from
8856 * every mailbox register write to force the writes to be
8857 * posted to the chip in order.
8858 */
8859 if (pci_dev_present(write_reorder_chipsets))
8860 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
8861
8862 /* Force memory write invalidate off. If we leave it on,
8863 * then on 5700_BX chips we have to enable a workaround.
8864 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8865 * to match the cacheline size. The Broadcom driver have this
8866 * workaround but turns MWI off all the times so never uses
8867 * it. This seems to suggest that the workaround is insufficient.
8868 */
8869 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8870 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8871 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8872
8873 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8874 * has the register indirect write enable bit set before
8875 * we try to access any of the MMIO registers. It is also
8876 * critical that the PCI-X hw workaround situation is decided
8877 * before that as well.
8878 */
8879 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8880 &misc_ctrl_reg);
8881
8882 tp->pci_chip_rev_id = (misc_ctrl_reg >>
8883 MISC_HOST_CTRL_CHIPREV_SHIFT);
8884
ff645bec
MC		 8885 /* Wrong chip ID in 5752 A0. This code can be removed later
8886 * as A0 is not in production.
8887 */
8888 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8889 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8890
1da177e4
LT		 8891 /* Initialize misc host control in PCI block. */
8892 tp->misc_host_ctrl |= (misc_ctrl_reg &
8893 MISC_HOST_CTRL_CHIPREV);
8894 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8895 tp->misc_host_ctrl);
8896
8897 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8898 &cacheline_sz_reg);
8899
8900 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
8901 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
8902 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
8903 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
8904
6708e5cc 8905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
ff645bec 8906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6708e5cc
JL		 8907 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8908
1b440c56
JL		 8909 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
8910 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
8911 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
8912
bb7064dc 8913 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8914 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8915
8916 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8917 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8918
8919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8920 tp->pci_lat_timer < 64) {
8921 tp->pci_lat_timer = 64;
8922
8923 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
8924 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
8925 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
8926 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
8927
8928 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8929 cacheline_sz_reg);
8930 }
8931
8932 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8933 &pci_state_reg);
8934
8935 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8936 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8937
8938 /* If this is a 5700 BX chipset, and we are in PCI-X
8939 * mode, enable register write workaround.
8940 *
8941 * The workaround is to use indirect register accesses
8942 * for all chip writes not to mailbox registers.
8943 */
8944 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8945 u32 pm_reg;
8946 u16 pci_cmd;
8947
8948 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8949
8950 /* The chip can have it's power management PCI config
8951 * space registers clobbered due to this bug.
8952 * So explicitly force the chip into D0 here.
8953 */
8954 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8955 &pm_reg);
8956 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8957 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8958 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8959 pm_reg);
8960
8961 /* Also, force SERR#/PERR# in PCI command. */
8962 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8963 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8964 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8965 }
8966 }
8967
8968 /* Back to back register writes can cause problems on this chip,
8969 * the workaround is to read back all reg writes except those to
8970 * mailbox regs. See tg3_write_indirect_reg32().
8971 *
8972 * PCI Express 5750_A0 rev chips need this workaround too.
8973 */
8974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8975 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8976 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8977 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8978
8979 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8980 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8981 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8982 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8983
8984 /* Chip-specific fixup from Broadcom driver */
8985 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8986 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8987 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8988 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8989 }
8990
7d0c41ef
MC		 8991 /* Get eeprom hw config before calling tg3_set_power_state().
8992 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8993 * determined before calling tg3_set_power_state() so that
8994 * we know whether or not to switch out of Vaux power.
8995 * When the flag is set, it means that GPIO1 is used for eeprom
8996 * write protect and also implies that it is a LOM where GPIOs
8997 * are not used to switch power.
8998 */
8999 tg3_get_eeprom_hw_cfg(tp);
9000
314fba34
MC		 9001 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9002 * GPIO1 driven high will bring 5700's external PHY out of reset.
9003 * It is also used as eeprom write protect on LOMs.
9004 */
9005 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9006 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9007 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9008 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9009 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 9010 /* Unused GPIO3 must be driven as output on 5752 because there
9011 * are no pull-up resistors on unused GPIO pins.
9012 */
9013 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9014 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 9015
1da177e4
LT		 9016 /* Force the chip into D0. */
9017 err = tg3_set_power_state(tp, 0);
9018 if (err) {
9019 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9020 pci_name(tp->pdev));
9021 return err;
9022 }
9023
9024 /* 5700 B0 chips do not support checksumming correctly due
9025 * to hardware bugs.
9026 */
9027 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9028 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9029
9030 /* Pseudo-header checksum is done by hardware logic and not
9031 * the offload processers, so make the chip do the pseudo-
9032 * header checksums on receive. For transmit it is more
9033 * convenient to do the pseudo-header checksum in software
9034 * as Linux does that on transmit for us in all cases.
9035 */
9036 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9037 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9038
9039 /* Derive initial jumbo mode from MTU assigned in
9040 * ether_setup() via the alloc_etherdev() call
9041 */
9042 if (tp->dev->mtu > ETH_DATA_LEN)
9043 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
9044
9045 /* Determine WakeOnLan speed to use. */
9046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9047 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9048 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9049 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9050 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9051 } else {
9052 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9053 }
9054
9055 /* A few boards don't want Ethernet@WireSpeed phy feature */
9056 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9057 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9058 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9059 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
9060 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9061
9062 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9063 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9064 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9065 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9066 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9067
bb7064dc 9068 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
1da177e4
LT		 9069 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9070
1da177e4 9071 tp->coalesce_mode = 0;
1da177e4
LT		 9072 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9073 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9074 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9075
9076 /* Initialize MAC MI mode, polling disabled. */
9077 tw32_f(MAC_MI_MODE, tp->mi_mode);
9078 udelay(80);
9079
9080 /* Initialize data/descriptor byte/word swapping. */
9081 val = tr32(GRC_MODE);
9082 val &= GRC_MODE_HOST_STACKUP;
9083 tw32(GRC_MODE, val | tp->grc_mode);
9084
9085 tg3_switch_clocks(tp);
9086
9087 /* Clear this out for sanity. */
9088 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9089
9090 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9091 &pci_state_reg);
9092 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9093 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9094 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9095
9096 if (chiprevid == CHIPREV_ID_5701_A0 ||
9097 chiprevid == CHIPREV_ID_5701_B0 ||
9098 chiprevid == CHIPREV_ID_5701_B2 ||
9099 chiprevid == CHIPREV_ID_5701_B5) {
9100 void __iomem *sram_base;
9101
9102 /* Write some dummy words into the SRAM status block
9103 * area, see if it reads back correctly. If the return
9104 * value is bad, force enable the PCIX workaround.
9105 */
9106 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9107
9108 writel(0x00000000, sram_base);
9109 writel(0x00000000, sram_base + 4);
9110 writel(0xffffffff, sram_base + 4);
9111 if (readl(sram_base) != 0x00000000)
9112 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9113 }
9114 }
9115
9116 udelay(50);
9117 tg3_nvram_init(tp);
9118
9119 grc_misc_cfg = tr32(GRC_MISC_CFG);
9120 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9121
9122 /* Broadcom's driver says that CIOBE multisplit has a bug */
9123#if 0
9124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9125 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9126 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9127 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9128 }
9129#endif
9130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9131 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9132 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9133 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9134
fac9b83e
DM		 9135 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9136 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9137 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9138 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9139 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9140 HOSTCC_MODE_CLRTICK_TXBD);
9141
9142 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9143 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9144 tp->misc_host_ctrl);
9145 }
9146
1da177e4
LT		 9147 /* these are limited to 10/100 only */
9148 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9149 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9150 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9151 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9152 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9153 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9154 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9155 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9156 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9157 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9158 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9159
9160 err = tg3_phy_probe(tp);
9161 if (err) {
9162 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9163 pci_name(tp->pdev), err);
9164 /* ... but do not return immediately ... */
9165 }
9166
9167 tg3_read_partno(tp);
9168
9169 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9170 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9171 } else {
9172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9173 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9174 else
9175 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9176 }
9177
9178 /* 5700 {AX,BX} chips have a broken status block link
9179 * change bit implementation, so we must use the
9180 * status register in those cases.
9181 */
9182 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9183 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9184 else
9185 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9186
9187 /* The led_ctrl is set during tg3_phy_probe, here we might
9188 * have to force the link status polling mechanism based
9189 * upon subsystem IDs.
9190 */
9191 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9192 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9193 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9194 TG3_FLAG_USE_LINKCHG_REG);
9195 }
9196
9197 /* For all SERDES we poll the MAC status register. */
9198 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9199 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9200 else
9201 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9202
9203 /* 5700 BX chips need to have their TX producer index mailboxes
9204 * written twice to workaround a bug.
9205 */
9206 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9207 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9208 else
9209 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
9210
9211 /* It seems all chips can get confused if TX buffers
9212 * straddle the 4GB address boundary in some cases.
9213 */
9214 tp->dev->hard_start_xmit = tg3_start_xmit;
9215
9216 tp->rx_offset = 2;
9217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9218 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9219 tp->rx_offset = 0;
9220
9221 /* By default, disable wake-on-lan. User can change this
9222 * using ETHTOOL_SWOL.
9223 */
9224 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9225
9226 return err;
9227}
9228
9229#ifdef CONFIG_SPARC64
9230static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9231{
9232 struct net_device *dev = tp->dev;
9233 struct pci_dev *pdev = tp->pdev;
9234 struct pcidev_cookie *pcp = pdev->sysdata;
9235
9236 if (pcp != NULL) {
9237 int node = pcp->prom_node;
9238
9239 if (prom_getproplen(node, "local-mac-address") == 6) {
9240 prom_getproperty(node, "local-mac-address",
9241 dev->dev_addr, 6);
9242 return 0;
9243 }
9244 }
9245 return -ENODEV;
9246}
9247
9248static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9249{
9250 struct net_device *dev = tp->dev;
9251
9252 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9253 return 0;
9254}
9255#endif
9256
9257static int __devinit tg3_get_device_address(struct tg3 *tp)
9258{
9259 struct net_device *dev = tp->dev;
9260 u32 hi, lo, mac_offset;
9261
9262#ifdef CONFIG_SPARC64
9263 if (!tg3_get_macaddr_sparc(tp))
9264 return 0;
9265#endif
9266
9267 mac_offset = 0x7c;
9268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9269 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
9270 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9271 mac_offset = 0xcc;
9272 if (tg3_nvram_lock(tp))
9273 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9274 else
9275 tg3_nvram_unlock(tp);
9276 }
9277
9278 /* First try to get it from MAC address mailbox. */
9279 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9280 if ((hi >> 16) == 0x484b) {
9281 dev->dev_addr[0] = (hi >> 8) & 0xff;
9282 dev->dev_addr[1] = (hi >> 0) & 0xff;
9283
9284 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9285 dev->dev_addr[2] = (lo >> 24) & 0xff;
9286 dev->dev_addr[3] = (lo >> 16) & 0xff;
9287 dev->dev_addr[4] = (lo >> 8) & 0xff;
9288 dev->dev_addr[5] = (lo >> 0) & 0xff;
9289 }
9290 /* Next, try NVRAM. */
9291 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9292 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9293 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9294 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9295 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9296 dev->dev_addr[2] = ((lo >> 0) & 0xff);
9297 dev->dev_addr[3] = ((lo >> 8) & 0xff);
9298 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9299 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9300 }
9301 /* Finally just fetch it out of the MAC control regs. */
9302 else {
9303 hi = tr32(MAC_ADDR_0_HIGH);
9304 lo = tr32(MAC_ADDR_0_LOW);
9305
9306 dev->dev_addr[5] = lo & 0xff;
9307 dev->dev_addr[4] = (lo >> 8) & 0xff;
9308 dev->dev_addr[3] = (lo >> 16) & 0xff;
9309 dev->dev_addr[2] = (lo >> 24) & 0xff;
9310 dev->dev_addr[1] = hi & 0xff;
9311 dev->dev_addr[0] = (hi >> 8) & 0xff;
9312 }
9313
9314 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9315#ifdef CONFIG_SPARC64
9316 if (!tg3_get_default_macaddr_sparc(tp))
9317 return 0;
9318#endif
9319 return -EINVAL;
9320 }
9321 return 0;
9322}
9323
59e6b434
DM		 9324#define BOUNDARY_SINGLE_CACHELINE 1
9325#define BOUNDARY_MULTI_CACHELINE 2
9326
9327static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9328{
9329 int cacheline_size;
9330 u8 byte;
9331 int goal;
9332
9333 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9334 if (byte == 0)
9335 cacheline_size = 1024;
9336 else
9337 cacheline_size = (int) byte * 4;
9338
9339 /* On 5703 and later chips, the boundary bits have no
9340 * effect.
9341 */
9342 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9343 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9344 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9345 goto out;
9346
9347#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9348 goal = BOUNDARY_MULTI_CACHELINE;
9349#else
9350#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9351 goal = BOUNDARY_SINGLE_CACHELINE;
9352#else
9353 goal = 0;
9354#endif
9355#endif
9356
9357 if (!goal)
9358 goto out;
9359
9360 /* PCI controllers on most RISC systems tend to disconnect
9361 * when a device tries to burst across a cache-line boundary.
9362 * Therefore, letting tg3 do so just wastes PCI bandwidth.
9363 *
9364 * Unfortunately, for PCI-E there are only limited
9365 * write-side controls for this, and thus for reads
9366 * we will still get the disconnects. We'll also waste
9367 * these PCI cycles for both read and write for chips
9368 * other than 5700 and 5701 which do not implement the
9369 * boundary bits.
9370 */
9371 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9372 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9373 switch (cacheline_size) {
9374 case 16:
9375 case 32:
9376 case 64:
9377 case 128:
9378 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9379 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9380 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9381 } else {
9382 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9383 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9384 }
9385 break;
9386
9387 case 256:
9388 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9389 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9390 break;
9391
9392 default:
9393 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9394 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9395 break;
9396 };
9397 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9398 switch (cacheline_size) {
9399 case 16:
9400 case 32:
9401 case 64:
9402 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9403 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9404 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9405 break;
9406 }
9407 /* fallthrough */
9408 case 128:
9409 default:
9410 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9411 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9412 break;
9413 };
9414 } else {
9415 switch (cacheline_size) {
9416 case 16:
9417 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9418 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9419 DMA_RWCTRL_WRITE_BNDRY_16);
9420 break;
9421 }
9422 /* fallthrough */
9423 case 32:
9424 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9425 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9426 DMA_RWCTRL_WRITE_BNDRY_32);
9427 break;
9428 }
9429 /* fallthrough */
9430 case 64:
9431 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9432 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9433 DMA_RWCTRL_WRITE_BNDRY_64);
9434 break;
9435 }
9436 /* fallthrough */
9437 case 128:
9438 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9439 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9440 DMA_RWCTRL_WRITE_BNDRY_128);
9441 break;
9442 }
9443 /* fallthrough */
9444 case 256:
9445 val |= (DMA_RWCTRL_READ_BNDRY_256 |
9446 DMA_RWCTRL_WRITE_BNDRY_256);
9447 break;
9448 case 512:
9449 val |= (DMA_RWCTRL_READ_BNDRY_512 |
9450 DMA_RWCTRL_WRITE_BNDRY_512);
9451 break;
9452 case 1024:
9453 default:
9454 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
9455 DMA_RWCTRL_WRITE_BNDRY_1024);
9456 break;
9457 };
9458 }
9459
9460out:
9461 return val;
9462}
9463
1da177e4
LT		 9464static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
9465{
9466 struct tg3_internal_buffer_desc test_desc;
9467 u32 sram_dma_descs;
9468 int i, ret;
9469
9470 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
9471
9472 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
9473 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
9474 tw32(RDMAC_STATUS, 0);
9475 tw32(WDMAC_STATUS, 0);
9476
9477 tw32(BUFMGR_MODE, 0);
9478 tw32(FTQ_RESET, 0);
9479
9480 test_desc.addr_hi = ((u64) buf_dma) >> 32;
9481 test_desc.addr_lo = buf_dma & 0xffffffff;
9482 test_desc.nic_mbuf = 0x00002100;
9483 test_desc.len = size;
9484
9485 /*
9486 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
9487 * the *second* time the tg3 driver was getting loaded after an
9488 * initial scan.
9489 *
9490 * Broadcom tells me:
9491 * ...the DMA engine is connected to the GRC block and a DMA
9492 * reset may affect the GRC block in some unpredictable way...
9493 * The behavior of resets to individual blocks has not been tested.
9494 *
9495 * Broadcom noted the GRC reset will also reset all sub-components.
9496 */
9497 if (to_device) {
9498 test_desc.cqid_sqid = (13 << 8) | 2;
9499
9500 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
9501 udelay(40);
9502 } else {
9503 test_desc.cqid_sqid = (16 << 8) | 7;
9504
9505 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
9506 udelay(40);
9507 }
9508 test_desc.flags = 0x00000005;
9509
9510 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
9511 u32 val;
9512
9513 val = *(((u32 *)&test_desc) + i);
9514 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
9515 sram_dma_descs + (i * sizeof(u32)));
9516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
9517 }
9518 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
9519
9520 if (to_device) {
9521 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
9522 } else {
9523 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
9524 }
9525
9526 ret = -ENODEV;
9527 for (i = 0; i < 40; i++) {
9528 u32 val;
9529
9530 if (to_device)
9531 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
9532 else
9533 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
9534 if ((val & 0xffff) == sram_dma_descs) {
9535 ret = 0;
9536 break;
9537 }
9538
9539 udelay(100);
9540 }
9541
9542 return ret;
9543}
9544
ded7340d 9545#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 9546
9547static int __devinit tg3_test_dma(struct tg3 *tp)
9548{
9549 dma_addr_t buf_dma;
59e6b434 9550 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 9551 int ret;
9552
9553 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
9554 if (!buf) {
9555 ret = -ENOMEM;
9556 goto out_nofree;
9557 }
9558
9559 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
9560 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
9561
59e6b434 9562 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 9563
9564 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9565 /* DMA read watermark not used on PCIE */
9566 tp->dma_rwctrl |= 0x00180000;
9567 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 9568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
9569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 9570 tp->dma_rwctrl |= 0x003f0000;
9571 else
9572 tp->dma_rwctrl |= 0x003f000f;
9573 } else {
9574 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9575 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9576 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
9577
9578 if (ccval == 0x6 || ccval == 0x7)
9579 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
9580
59e6b434 9581 /* Set bit 23 to enable PCIX hw bug fix */
1da177e4
LT		 9582 tp->dma_rwctrl |= 0x009f0000;
9583 } else {
9584 tp->dma_rwctrl |= 0x001b000f;
9585 }
9586 }
9587
9588 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9589 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9590 tp->dma_rwctrl &= 0xfffffff0;
9591
9592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9593 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
9594 /* Remove this if it causes problems for some boards. */
9595 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
9596
9597 /* On 5700/5701 chips, we need to set this bit.
9598 * Otherwise the chip will issue cacheline transactions
9599 * to streamable DMA memory with not all the byte
9600 * enables turned on. This is an error on several
9601 * RISC PCI controllers, in particular sparc64.
9602 *
9603 * On 5703/5704 chips, this bit has been reassigned
9604 * a different meaning. In particular, it is used
9605 * on those chips to enable a PCI-X workaround.
9606 */
9607 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
9608 }
9609
9610 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9611
9612#if 0
9613 /* Unneeded, already done by tg3_get_invariants. */
9614 tg3_switch_clocks(tp);
9615#endif
9616
9617 ret = 0;
9618 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9619 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
9620 goto out;
9621
59e6b434
DM		 9622 /* It is best to perform DMA test with maximum write burst size
9623 * to expose the 5700/5701 write DMA bug.
9624 */
9625 saved_dma_rwctrl = tp->dma_rwctrl;
9626 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9627 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9628
1da177e4
LT		 9629 while (1) {
9630 u32 *p = buf, i;
9631
9632 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
9633 p[i] = i;
9634
9635 /* Send the buffer to the chip. */
9636 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
9637 if (ret) {
9638 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
9639 break;
9640 }
9641
9642#if 0
9643 /* validate data reached card RAM correctly. */
9644 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9645 u32 val;
9646 tg3_read_mem(tp, 0x2100 + (i*4), &val);
9647 if (le32_to_cpu(val) != p[i]) {
9648 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
9649 /* ret = -ENODEV here? */
9650 }
9651 p[i] = 0;
9652 }
9653#endif
9654 /* Now read it back. */
9655 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
9656 if (ret) {
9657 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
9658
9659 break;
9660 }
9661
9662 /* Verify it. */
9663 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9664 if (p[i] == i)
9665 continue;
9666
59e6b434
DM		 9667 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9668 DMA_RWCTRL_WRITE_BNDRY_16) {
9669 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 9670 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9671 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9672 break;
9673 } else {
9674 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
9675 ret = -ENODEV;
9676 goto out;
9677 }
9678 }
9679
9680 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
9681 /* Success. */
9682 ret = 0;
9683 break;
9684 }
9685 }
59e6b434
DM		 9686 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9687 DMA_RWCTRL_WRITE_BNDRY_16) {
9688 /* DMA test passed without adjusting DMA boundary,
9689 * just restore the calculated DMA boundary
9690 */
9691 tp->dma_rwctrl = saved_dma_rwctrl;
9692 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9693 }
1da177e4
LT		 9694
9695out:
9696 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
9697out_nofree:
9698 return ret;
9699}
9700
9701static void __devinit tg3_init_link_config(struct tg3 *tp)
9702{
9703 tp->link_config.advertising =
9704 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
9705 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
9706 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
9707 ADVERTISED_Autoneg | ADVERTISED_MII);
9708 tp->link_config.speed = SPEED_INVALID;
9709 tp->link_config.duplex = DUPLEX_INVALID;
9710 tp->link_config.autoneg = AUTONEG_ENABLE;
9711 netif_carrier_off(tp->dev);
9712 tp->link_config.active_speed = SPEED_INVALID;
9713 tp->link_config.active_duplex = DUPLEX_INVALID;
9714 tp->link_config.phy_is_low_power = 0;
9715 tp->link_config.orig_speed = SPEED_INVALID;
9716 tp->link_config.orig_duplex = DUPLEX_INVALID;
9717 tp->link_config.orig_autoneg = AUTONEG_INVALID;
9718}
9719
9720static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9721{
9722 tp->bufmgr_config.mbuf_read_dma_low_water =
9723 DEFAULT_MB_RDMA_LOW_WATER;
9724 tp->bufmgr_config.mbuf_mac_rx_low_water =
9725 DEFAULT_MB_MACRX_LOW_WATER;
9726 tp->bufmgr_config.mbuf_high_water =
9727 DEFAULT_MB_HIGH_WATER;
9728
9729 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9730 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9731 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9732 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9733 tp->bufmgr_config.mbuf_high_water_jumbo =
9734 DEFAULT_MB_HIGH_WATER_JUMBO;
9735
9736 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9737 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
9738}
9739
9740static char * __devinit tg3_phy_string(struct tg3 *tp)
9741{
9742 switch (tp->phy_id & PHY_ID_MASK) {
9743 case PHY_ID_BCM5400: return "5400";
9744 case PHY_ID_BCM5401: return "5401";
9745 case PHY_ID_BCM5411: return "5411";
9746 case PHY_ID_BCM5701: return "5701";
9747 case PHY_ID_BCM5703: return "5703";
9748 case PHY_ID_BCM5704: return "5704";
9749 case PHY_ID_BCM5705: return "5705";
9750 case PHY_ID_BCM5750: return "5750";
85e94ced 9751 case PHY_ID_BCM5752: return "5752";
1da177e4
LT		 9752 case PHY_ID_BCM8002: return "8002/serdes";
9753 case 0: return "serdes";
9754 default: return "unknown";
9755 };
9756}
9757
9758static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9759{
9760 struct pci_dev *peer;
9761 unsigned int func, devnr = tp->pdev->devfn & ~7;
9762
9763 for (func = 0; func < 8; func++) {
9764 peer = pci_get_slot(tp->pdev->bus, devnr | func);
9765 if (peer && peer != tp->pdev)
9766 break;
9767 pci_dev_put(peer);
9768 }
9769 if (!peer || peer == tp->pdev)
9770 BUG();
9771
9772 /*
9773 * We don't need to keep the refcount elevated; there's no way
9774 * to remove one half of this device without removing the other
9775 */
9776 pci_dev_put(peer);
9777
9778 return peer;
9779}
9780
15f9850d
DM		 9781static void __devinit tg3_init_coal(struct tg3 *tp)
9782{
9783 struct ethtool_coalesce *ec = &tp->coal;
9784
9785 memset(ec, 0, sizeof(*ec));
9786 ec->cmd = ETHTOOL_GCOALESCE;
9787 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9788 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9789 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9790 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9791 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9792 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9793 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9794 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9795 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9796
9797 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9798 HOSTCC_MODE_CLRTICK_TXBD)) {
9799 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9800 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9801 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9802 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9803 }
9804}
9805
1da177e4
LT		 9806static int __devinit tg3_init_one(struct pci_dev *pdev,
9807 const struct pci_device_id *ent)
9808{
9809 static int tg3_version_printed = 0;
9810 unsigned long tg3reg_base, tg3reg_len;
9811 struct net_device *dev;
9812 struct tg3 *tp;
9813 int i, err, pci_using_dac, pm_cap;
9814
9815 if (tg3_version_printed++ == 0)
9816 printk(KERN_INFO "%s", version);
9817
9818 err = pci_enable_device(pdev);
9819 if (err) {
9820 printk(KERN_ERR PFX "Cannot enable PCI device, "
9821 "aborting.\n");
9822 return err;
9823 }
9824
9825 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9826 printk(KERN_ERR PFX "Cannot find proper PCI device "
9827 "base address, aborting.\n");
9828 err = -ENODEV;
9829 goto err_out_disable_pdev;
9830 }
9831
9832 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9833 if (err) {
9834 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
9835 "aborting.\n");
9836 goto err_out_disable_pdev;
9837 }
9838
9839 pci_set_master(pdev);
9840
9841 /* Find power-management capability. */
9842 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9843 if (pm_cap == 0) {
9844 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
9845 "aborting.\n");
9846 err = -EIO;
9847 goto err_out_free_res;
9848 }
9849
9850 /* Configure DMA attributes. */
9851 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
9852 if (!err) {
9853 pci_using_dac = 1;
9854 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
9855 if (err < 0) {
9856 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
9857 "for consistent allocations\n");
9858 goto err_out_free_res;
9859 }
9860 } else {
9861 err = pci_set_dma_mask(pdev, 0xffffffffULL);
9862 if (err) {
9863 printk(KERN_ERR PFX "No usable DMA configuration, "
9864 "aborting.\n");
9865 goto err_out_free_res;
9866 }
9867 pci_using_dac = 0;
9868 }
9869
9870 tg3reg_base = pci_resource_start(pdev, 0);
9871 tg3reg_len = pci_resource_len(pdev, 0);
9872
9873 dev = alloc_etherdev(sizeof(*tp));
9874 if (!dev) {
9875 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
9876 err = -ENOMEM;
9877 goto err_out_free_res;
9878 }
9879
9880 SET_MODULE_OWNER(dev);
9881 SET_NETDEV_DEV(dev, &pdev->dev);
9882
9883 if (pci_using_dac)
9884 dev->features |= NETIF_F_HIGHDMA;
9885 dev->features |= NETIF_F_LLTX;
9886#if TG3_VLAN_TAG_USED
9887 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
9888 dev->vlan_rx_register = tg3_vlan_rx_register;
9889 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
9890#endif
9891
9892 tp = netdev_priv(dev);
9893 tp->pdev = pdev;
9894 tp->dev = dev;
9895 tp->pm_cap = pm_cap;
9896 tp->mac_mode = TG3_DEF_MAC_MODE;
9897 tp->rx_mode = TG3_DEF_RX_MODE;
9898 tp->tx_mode = TG3_DEF_TX_MODE;
9899 tp->mi_mode = MAC_MI_MODE_BASE;
9900 if (tg3_debug > 0)
9901 tp->msg_enable = tg3_debug;
9902 else
9903 tp->msg_enable = TG3_DEF_MSG_ENABLE;
9904
9905 /* The word/byte swap controls here control register access byte
9906 * swapping. DMA data byte swapping is controlled in the GRC_MODE
9907 * setting below.
9908 */
9909 tp->misc_host_ctrl =
9910 MISC_HOST_CTRL_MASK_PCI_INT |
9911 MISC_HOST_CTRL_WORD_SWAP |
9912 MISC_HOST_CTRL_INDIR_ACCESS |
9913 MISC_HOST_CTRL_PCISTATE_RW;
9914
9915 /* The NONFRM (non-frame) byte/word swap controls take effect
9916 * on descriptor entries, anything which isn't packet data.
9917 *
9918 * The StrongARM chips on the board (one for tx, one for rx)
9919 * are running in big-endian mode.
9920 */
9921 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
9922 GRC_MODE_WSWAP_NONFRM_DATA);
9923#ifdef __BIG_ENDIAN
9924 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
9925#endif
9926 spin_lock_init(&tp->lock);
9927 spin_lock_init(&tp->tx_lock);
9928 spin_lock_init(&tp->indirect_lock);
9929 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
9930
9931 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
9932 if (tp->regs == 0UL) {
9933 printk(KERN_ERR PFX "Cannot map device registers, "
9934 "aborting.\n");
9935 err = -ENOMEM;
9936 goto err_out_free_dev;
9937 }
9938
9939 tg3_init_link_config(tp);
9940
9941 tg3_init_bufmgr_config(tp);
9942
9943 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
9944 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
9945 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
9946
9947 dev->open = tg3_open;
9948 dev->stop = tg3_close;
9949 dev->get_stats = tg3_get_stats;
9950 dev->set_multicast_list = tg3_set_rx_mode;
9951 dev->set_mac_address = tg3_set_mac_addr;
9952 dev->do_ioctl = tg3_ioctl;
9953 dev->tx_timeout = tg3_tx_timeout;
9954 dev->poll = tg3_poll;
9955 dev->ethtool_ops = &tg3_ethtool_ops;
9956 dev->weight = 64;
9957 dev->watchdog_timeo = TG3_TX_TIMEOUT;
9958 dev->change_mtu = tg3_change_mtu;
9959 dev->irq = pdev->irq;
9960#ifdef CONFIG_NET_POLL_CONTROLLER
9961 dev->poll_controller = tg3_poll_controller;
9962#endif
9963
9964 err = tg3_get_invariants(tp);
9965 if (err) {
9966 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
9967 "aborting.\n");
9968 goto err_out_iounmap;
9969 }
9970
9971 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9972 tp->bufmgr_config.mbuf_read_dma_low_water =
9973 DEFAULT_MB_RDMA_LOW_WATER_5705;
9974 tp->bufmgr_config.mbuf_mac_rx_low_water =
9975 DEFAULT_MB_MACRX_LOW_WATER_5705;
9976 tp->bufmgr_config.mbuf_high_water =
9977 DEFAULT_MB_HIGH_WATER_5705;
9978 }
9979
9980#if TG3_TSO_SUPPORT != 0
9981 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
9982 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9983 }
9984 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9986 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
9987 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
9988 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9989 } else {
9990 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9991 }
9992
9993 /* TSO is off by default, user can enable using ethtool. */
9994#if 0
9995 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
9996 dev->features |= NETIF_F_TSO;
9997#endif
9998
9999#endif
10000
10001 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10002 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10003 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10004 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10005 tp->rx_pending = 63;
10006 }
10007
10008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10009 tp->pdev_peer = tg3_find_5704_peer(tp);
10010
10011 err = tg3_get_device_address(tp);
10012 if (err) {
10013 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10014 "aborting.\n");
10015 goto err_out_iounmap;
10016 }
10017
10018 /*
10019 * Reset chip in case UNDI or EFI driver did not shutdown
10020 * DMA self test will enable WDMAC and we'll see (spurious)
10021 * pending DMA on the PCI bus at that point.
10022 */
10023 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10024 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10025 pci_save_state(tp->pdev);
10026 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 10027 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 10028 }
10029
10030 err = tg3_test_dma(tp);
10031 if (err) {
10032 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10033 goto err_out_iounmap;
10034 }
10035
10036 /* Tigon3 can do ipv4 only... and some chips have buggy
10037 * checksumming.
10038 */
10039 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10040 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10041 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10042 } else
10043 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10044
10045 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10046 dev->features &= ~NETIF_F_HIGHDMA;
10047
10048 /* flow control autonegotiation is default behavior */
10049 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10050
15f9850d
DM		 10051 tg3_init_coal(tp);
10052
1da177e4
LT		 10053 err = register_netdev(dev);
10054 if (err) {
10055 printk(KERN_ERR PFX "Cannot register net device, "
10056 "aborting.\n");
10057 goto err_out_iounmap;
10058 }
10059
10060 pci_set_drvdata(pdev, dev);
10061
10062 /* Now that we have fully setup the chip, save away a snapshot
10063 * of the PCI config space. We need to restore this after
10064 * GRC_MISC_CFG core clock resets and some resume events.
10065 */
10066 pci_save_state(tp->pdev);
10067
10068 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
10069 dev->name,
10070 tp->board_part_number,
10071 tp->pci_chip_rev_id,
10072 tg3_phy_string(tp),
10073 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
10074 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
10075 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
10076 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
10077 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
10078 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10079
10080 for (i = 0; i < 6; i++)
10081 printk("%2.2x%c", dev->dev_addr[i],
10082 i == 5 ? '\n' : ':');
10083
10084 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10085 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10086 "TSOcap[%d] \n",
10087 dev->name,
10088 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10089 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10090 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10091 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10092 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10093 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10094 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
59e6b434
DM		 10095 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10096 dev->name, tp->dma_rwctrl);
1da177e4
LT		 10097
10098 return 0;
10099
10100err_out_iounmap:
10101 iounmap(tp->regs);
10102
10103err_out_free_dev:
10104 free_netdev(dev);
10105
10106err_out_free_res:
10107 pci_release_regions(pdev);
10108
10109err_out_disable_pdev:
10110 pci_disable_device(pdev);
10111 pci_set_drvdata(pdev, NULL);
10112 return err;
10113}
10114
10115static void __devexit tg3_remove_one(struct pci_dev *pdev)
10116{
10117 struct net_device *dev = pci_get_drvdata(pdev);
10118
10119 if (dev) {
10120 struct tg3 *tp = netdev_priv(dev);
10121
10122 unregister_netdev(dev);
10123 iounmap(tp->regs);
10124 free_netdev(dev);
10125 pci_release_regions(pdev);
10126 pci_disable_device(pdev);
10127 pci_set_drvdata(pdev, NULL);
10128 }
10129}
10130
10131static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10132{
10133 struct net_device *dev = pci_get_drvdata(pdev);
10134 struct tg3 *tp = netdev_priv(dev);
10135 int err;
10136
10137 if (!netif_running(dev))
10138 return 0;
10139
10140 tg3_netif_stop(tp);
10141
10142 del_timer_sync(&tp->timer);
10143
10144 spin_lock_irq(&tp->lock);
10145 spin_lock(&tp->tx_lock);
10146 tg3_disable_ints(tp);
10147 spin_unlock(&tp->tx_lock);
10148 spin_unlock_irq(&tp->lock);
10149
10150 netif_device_detach(dev);
10151
10152 spin_lock_irq(&tp->lock);
10153 spin_lock(&tp->tx_lock);
944d980e 10154 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 10155 spin_unlock(&tp->tx_lock);
10156 spin_unlock_irq(&tp->lock);
10157
10158 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10159 if (err) {
10160 spin_lock_irq(&tp->lock);
10161 spin_lock(&tp->tx_lock);
10162
10163 tg3_init_hw(tp);
10164
10165 tp->timer.expires = jiffies + tp->timer_offset;
10166 add_timer(&tp->timer);
10167
10168 netif_device_attach(dev);
10169 tg3_netif_start(tp);
10170
10171 spin_unlock(&tp->tx_lock);
10172 spin_unlock_irq(&tp->lock);
10173 }
10174
10175 return err;
10176}
10177
10178static int tg3_resume(struct pci_dev *pdev)
10179{
10180 struct net_device *dev = pci_get_drvdata(pdev);
10181 struct tg3 *tp = netdev_priv(dev);
10182 int err;
10183
10184 if (!netif_running(dev))
10185 return 0;
10186
10187 pci_restore_state(tp->pdev);
10188
10189 err = tg3_set_power_state(tp, 0);
10190 if (err)
10191 return err;
10192
10193 netif_device_attach(dev);
10194
10195 spin_lock_irq(&tp->lock);
10196 spin_lock(&tp->tx_lock);
10197
10198 tg3_init_hw(tp);
10199
10200 tp->timer.expires = jiffies + tp->timer_offset;
10201 add_timer(&tp->timer);
10202
10203 tg3_enable_ints(tp);
10204
10205 tg3_netif_start(tp);
10206
10207 spin_unlock(&tp->tx_lock);
10208 spin_unlock_irq(&tp->lock);
10209
10210 return 0;
10211}
10212
10213static struct pci_driver tg3_driver = {
10214 .name = DRV_MODULE_NAME,
10215 .id_table = tg3_pci_tbl,
10216 .probe = tg3_init_one,
10217 .remove = __devexit_p(tg3_remove_one),
10218 .suspend = tg3_suspend,
10219 .resume = tg3_resume
10220};
10221
10222static int __init tg3_init(void)
10223{
10224 return pci_module_init(&tg3_driver);
10225}
10226
10227static void __exit tg3_cleanup(void)
10228{
10229 pci_unregister_driver(&tg3_driver);
10230}
10231
10232module_init(tg3_init);
10233module_exit(tg3_cleanup);
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