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[TG3]: Correct sw autoneg flow control advertisements
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
c9bdd4b5 43#include <net/ip.h>
1da177e4
LT		 44
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/byteorder.h>
48#include <asm/uaccess.h>
49
49b6e95f 50#ifdef CONFIG_SPARC
1da177e4 51#include <asm/idprom.h>
49b6e95f 52#include <asm/prom.h>
1da177e4
LT		 53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
1da177e4 61#define TG3_TSO_SUPPORT 1
1da177e4
LT		 62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
458c096e
MC		 67#define DRV_MODULE_VERSION "3.86"
68#define DRV_MODULE_RELDATE "November 9, 2007"
1da177e4
LT		 69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83/* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88/* hardware minimum and maximum for a single frame's data payload */
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
0f893dc6 91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 92
93/* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102/* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
1da177e4
LT		 122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127/* minimum number of free TX descriptors required to wake up TX process */
42952231 128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4
LT		 129
130/* number of ETHTOOL_GSTATS u64's */
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
4cafd3f5
MC		 133#define TG3_NUM_TEST 6
134
1da177e4
LT		 135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
207 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
209 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
210 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
212 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
213 {}
1da177e4
LT		 214};
215
216MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
217
50da859d 218static const struct {
1da177e4
LT		 219 const char string[ETH_GSTRING_LEN];
220} ethtool_stats_keys[TG3_NUM_STATS] = {
221 { "rx_octets" },
222 { "rx_fragments" },
223 { "rx_ucast_packets" },
224 { "rx_mcast_packets" },
225 { "rx_bcast_packets" },
226 { "rx_fcs_errors" },
227 { "rx_align_errors" },
228 { "rx_xon_pause_rcvd" },
229 { "rx_xoff_pause_rcvd" },
230 { "rx_mac_ctrl_rcvd" },
231 { "rx_xoff_entered" },
232 { "rx_frame_too_long_errors" },
233 { "rx_jabbers" },
234 { "rx_undersize_packets" },
235 { "rx_in_length_errors" },
236 { "rx_out_length_errors" },
237 { "rx_64_or_less_octet_packets" },
238 { "rx_65_to_127_octet_packets" },
239 { "rx_128_to_255_octet_packets" },
240 { "rx_256_to_511_octet_packets" },
241 { "rx_512_to_1023_octet_packets" },
242 { "rx_1024_to_1522_octet_packets" },
243 { "rx_1523_to_2047_octet_packets" },
244 { "rx_2048_to_4095_octet_packets" },
245 { "rx_4096_to_8191_octet_packets" },
246 { "rx_8192_to_9022_octet_packets" },
247
248 { "tx_octets" },
249 { "tx_collisions" },
250
251 { "tx_xon_sent" },
252 { "tx_xoff_sent" },
253 { "tx_flow_control" },
254 { "tx_mac_errors" },
255 { "tx_single_collisions" },
256 { "tx_mult_collisions" },
257 { "tx_deferred" },
258 { "tx_excessive_collisions" },
259 { "tx_late_collisions" },
260 { "tx_collide_2times" },
261 { "tx_collide_3times" },
262 { "tx_collide_4times" },
263 { "tx_collide_5times" },
264 { "tx_collide_6times" },
265 { "tx_collide_7times" },
266 { "tx_collide_8times" },
267 { "tx_collide_9times" },
268 { "tx_collide_10times" },
269 { "tx_collide_11times" },
270 { "tx_collide_12times" },
271 { "tx_collide_13times" },
272 { "tx_collide_14times" },
273 { "tx_collide_15times" },
274 { "tx_ucast_packets" },
275 { "tx_mcast_packets" },
276 { "tx_bcast_packets" },
277 { "tx_carrier_sense_errors" },
278 { "tx_discards" },
279 { "tx_errors" },
280
281 { "dma_writeq_full" },
282 { "dma_write_prioq_full" },
283 { "rxbds_empty" },
284 { "rx_discards" },
285 { "rx_errors" },
286 { "rx_threshold_hit" },
287
288 { "dma_readq_full" },
289 { "dma_read_prioq_full" },
290 { "tx_comp_queue_full" },
291
292 { "ring_set_send_prod_index" },
293 { "ring_status_update" },
294 { "nic_irqs" },
295 { "nic_avoided_irqs" },
296 { "nic_tx_threshold_hit" }
297};
298
50da859d 299static const struct {
4cafd3f5
MC		 300 const char string[ETH_GSTRING_LEN];
301} ethtool_test_keys[TG3_NUM_TEST] = {
302 { "nvram test (online) " },
303 { "link test (online) " },
304 { "register test (offline)" },
305 { "memory test (offline)" },
306 { "loopback test (offline)" },
307 { "interrupt test (offline)" },
308};
309
b401e9e2
MC		 310static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
311{
312 writel(val, tp->regs + off);
313}
314
315static u32 tg3_read32(struct tg3 *tp, u32 off)
316{
6aa20a22 317 return (readl(tp->regs + off));
b401e9e2
MC		 318}
319
0d3031d9
MC		 320static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
321{
322 writel(val, tp->aperegs + off);
323}
324
325static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
326{
327 return (readl(tp->aperegs + off));
328}
329
1da177e4
LT		 330static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
331{
6892914f
MC		 332 unsigned long flags;
333
334 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 335 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
336 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 337 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 338}
339
340static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
341{
342 writel(val, tp->regs + off);
343 readl(tp->regs + off);
1da177e4
LT		 344}
345
6892914f 346static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 347{
6892914f
MC		 348 unsigned long flags;
349 u32 val;
350
351 spin_lock_irqsave(&tp->indirect_lock, flags);
352 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
353 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
354 spin_unlock_irqrestore(&tp->indirect_lock, flags);
355 return val;
356}
357
358static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
359{
360 unsigned long flags;
361
362 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
363 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
364 TG3_64BIT_REG_LOW, val);
365 return;
366 }
367 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
369 TG3_64BIT_REG_LOW, val);
370 return;
1da177e4 371 }
6892914f
MC		 372
373 spin_lock_irqsave(&tp->indirect_lock, flags);
374 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
375 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
376 spin_unlock_irqrestore(&tp->indirect_lock, flags);
377
378 /* In indirect mode when disabling interrupts, we also need
379 * to clear the interrupt bit in the GRC local ctrl register.
380 */
381 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
382 (val == 0x1)) {
383 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
384 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
385 }
386}
387
388static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
389{
390 unsigned long flags;
391 u32 val;
392
393 spin_lock_irqsave(&tp->indirect_lock, flags);
394 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
395 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
396 spin_unlock_irqrestore(&tp->indirect_lock, flags);
397 return val;
398}
399
b401e9e2
MC		 400/* usec_wait specifies the wait time in usec when writing to certain registers
401 * where it is unsafe to read back the register without some delay.
402 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
403 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
404 */
405static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 406{
b401e9e2
MC		 407 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
408 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
409 /* Non-posted methods */
410 tp->write32(tp, off, val);
411 else {
412 /* Posted method */
413 tg3_write32(tp, off, val);
414 if (usec_wait)
415 udelay(usec_wait);
416 tp->read32(tp, off);
417 }
418 /* Wait again after the read for the posted method to guarantee that
419 * the wait time is met.
420 */
421 if (usec_wait)
422 udelay(usec_wait);
1da177e4
LT		 423}
424
09ee929c
MC		 425static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
426{
427 tp->write32_mbox(tp, off, val);
6892914f
MC		 428 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
429 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 tp->read32_mbox(tp, off);
09ee929c
MC		 431}
432
20094930 433static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 434{
435 void __iomem *mbox = tp->regs + off;
436 writel(val, mbox);
437 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
438 writel(val, mbox);
439 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
440 readl(mbox);
441}
442
b5d3772c
MC		 443static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
444{
445 return (readl(tp->regs + off + GRCMBOX_BASE));
446}
447
448static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
449{
450 writel(val, tp->regs + off + GRCMBOX_BASE);
451}
452
20094930 453#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 454#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 455#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
456#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 457#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 458
459#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 460#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
461#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 462#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 463
464static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
465{
6892914f
MC		 466 unsigned long flags;
467
b5d3772c
MC		 468 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
469 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
470 return;
471
6892914f 472 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 473 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
475 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 476
bbadf503
MC		 477 /* Always leave this as zero. */
478 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
479 } else {
480 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
481 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 482
bbadf503
MC		 483 /* Always leave this as zero. */
484 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
485 }
486 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 487}
488
1da177e4
LT		 489static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
490{
6892914f
MC		 491 unsigned long flags;
492
b5d3772c
MC		 493 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
494 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
495 *val = 0;
496 return;
497 }
498
6892914f 499 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 500 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 503
bbadf503
MC		 504 /* Always leave this as zero. */
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 } else {
507 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508 *val = tr32(TG3PCI_MEM_WIN_DATA);
509
510 /* Always leave this as zero. */
511 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
512 }
6892914f 513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 514}
515
0d3031d9
MC		 516static void tg3_ape_lock_init(struct tg3 *tp)
517{
518 int i;
519
520 /* Make sure the driver hasn't any stale locks. */
521 for (i = 0; i < 8; i++)
522 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
523 APE_LOCK_GRANT_DRIVER);
524}
525
526static int tg3_ape_lock(struct tg3 *tp, int locknum)
527{
528 int i, off;
529 int ret = 0;
530 u32 status;
531
532 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
533 return 0;
534
535 switch (locknum) {
536 case TG3_APE_LOCK_MEM:
537 break;
538 default:
539 return -EINVAL;
540 }
541
542 off = 4 * locknum;
543
544 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
545
546 /* Wait for up to 1 millisecond to acquire lock. */
547 for (i = 0; i < 100; i++) {
548 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
549 if (status == APE_LOCK_GRANT_DRIVER)
550 break;
551 udelay(10);
552 }
553
554 if (status != APE_LOCK_GRANT_DRIVER) {
555 /* Revoke the lock request. */
556 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
557 APE_LOCK_GRANT_DRIVER);
558
559 ret = -EBUSY;
560 }
561
562 return ret;
563}
564
565static void tg3_ape_unlock(struct tg3 *tp, int locknum)
566{
567 int off;
568
569 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
570 return;
571
572 switch (locknum) {
573 case TG3_APE_LOCK_MEM:
574 break;
575 default:
576 return;
577 }
578
579 off = 4 * locknum;
580 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
581}
582
1da177e4
LT		 583static void tg3_disable_ints(struct tg3 *tp)
584{
585 tw32(TG3PCI_MISC_HOST_CTRL,
586 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 587 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 588}
589
590static inline void tg3_cond_int(struct tg3 *tp)
591{
38f3843e
MC		 592 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
593 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 594 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 595 else
596 tw32(HOSTCC_MODE, tp->coalesce_mode |
597 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 598}
599
600static void tg3_enable_ints(struct tg3 *tp)
601{
bbe832c0
MC		 602 tp->irq_sync = 0;
603 wmb();
604
1da177e4
LT		 605 tw32(TG3PCI_MISC_HOST_CTRL,
606 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 607 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
608 (tp->last_tag << 24));
fcfa0a32
MC		 609 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
611 (tp->last_tag << 24));
1da177e4
LT		 612 tg3_cond_int(tp);
613}
614
04237ddd
MC		 615static inline unsigned int tg3_has_work(struct tg3 *tp)
616{
617 struct tg3_hw_status *sblk = tp->hw_status;
618 unsigned int work_exists = 0;
619
620 /* check for phy events */
621 if (!(tp->tg3_flags &
622 (TG3_FLAG_USE_LINKCHG_REG |
623 TG3_FLAG_POLL_SERDES))) {
624 if (sblk->status & SD_STATUS_LINK_CHG)
625 work_exists = 1;
626 }
627 /* check for RX/TX work to do */
628 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
629 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
630 work_exists = 1;
631
632 return work_exists;
633}
634
1da177e4 635/* tg3_restart_ints
04237ddd
MC		 636 * similar to tg3_enable_ints, but it accurately determines whether there
637 * is new work pending and can return without flushing the PIO write
6aa20a22 638 * which reenables interrupts
1da177e4
LT		 639 */
640static void tg3_restart_ints(struct tg3 *tp)
641{
fac9b83e
DM		 642 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
643 tp->last_tag << 24);
1da177e4
LT		 644 mmiowb();
645
fac9b83e
DM		 646 /* When doing tagged status, this work check is unnecessary.
647 * The last_tag we write above tells the chip which piece of
648 * work we've completed.
649 */
650 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
651 tg3_has_work(tp))
04237ddd
MC		 652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 654}
655
656static inline void tg3_netif_stop(struct tg3 *tp)
657{
bbe832c0 658 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 659 napi_disable(&tp->napi);
1da177e4
LT		 660 netif_tx_disable(tp->dev);
661}
662
663static inline void tg3_netif_start(struct tg3 *tp)
664{
665 netif_wake_queue(tp->dev);
666 /* NOTE: unconditional netif_wake_queue is only appropriate
667 * so long as all callers are assured to have free tx slots
668 * (such as after tg3_init_hw)
669 */
bea3348e 670 napi_enable(&tp->napi);
f47c11ee
DM		 671 tp->hw_status->status |= SD_STATUS_UPDATED;
672 tg3_enable_ints(tp);
1da177e4
LT		 673}
674
675static void tg3_switch_clocks(struct tg3 *tp)
676{
677 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
678 u32 orig_clock_ctrl;
679
795d01c5
MC		 680 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
681 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 682 return;
683
1da177e4
LT		 684 orig_clock_ctrl = clock_ctrl;
685 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
686 CLOCK_CTRL_CLKRUN_OENABLE |
687 0x1f);
688 tp->pci_clock_ctrl = clock_ctrl;
689
690 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
691 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 692 tw32_wait_f(TG3PCI_CLOCK_CTRL,
693 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 694 }
695 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 696 tw32_wait_f(TG3PCI_CLOCK_CTRL,
697 clock_ctrl |
698 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
699 40);
700 tw32_wait_f(TG3PCI_CLOCK_CTRL,
701 clock_ctrl | (CLOCK_CTRL_ALTCLK),
702 40);
1da177e4 703 }
b401e9e2 704 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 705}
706
707#define PHY_BUSY_LOOPS 5000
708
709static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
710{
711 u32 frame_val;
712 unsigned int loops;
713 int ret;
714
715 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
716 tw32_f(MAC_MI_MODE,
717 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
718 udelay(80);
719 }
720
721 *val = 0x0;
722
723 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
724 MI_COM_PHY_ADDR_MASK);
725 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
726 MI_COM_REG_ADDR_MASK);
727 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 728
1da177e4
LT		 729 tw32_f(MAC_MI_COM, frame_val);
730
731 loops = PHY_BUSY_LOOPS;
732 while (loops != 0) {
733 udelay(10);
734 frame_val = tr32(MAC_MI_COM);
735
736 if ((frame_val & MI_COM_BUSY) == 0) {
737 udelay(5);
738 frame_val = tr32(MAC_MI_COM);
739 break;
740 }
741 loops -= 1;
742 }
743
744 ret = -EBUSY;
745 if (loops != 0) {
746 *val = frame_val & MI_COM_DATA_MASK;
747 ret = 0;
748 }
749
750 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
751 tw32_f(MAC_MI_MODE, tp->mi_mode);
752 udelay(80);
753 }
754
755 return ret;
756}
757
758static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
759{
760 u32 frame_val;
761 unsigned int loops;
762 int ret;
763
b5d3772c
MC		 764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
765 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
766 return 0;
767
1da177e4
LT		 768 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
769 tw32_f(MAC_MI_MODE,
770 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
771 udelay(80);
772 }
773
774 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
775 MI_COM_PHY_ADDR_MASK);
776 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
777 MI_COM_REG_ADDR_MASK);
778 frame_val |= (val & MI_COM_DATA_MASK);
779 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 780
1da177e4
LT		 781 tw32_f(MAC_MI_COM, frame_val);
782
783 loops = PHY_BUSY_LOOPS;
784 while (loops != 0) {
785 udelay(10);
786 frame_val = tr32(MAC_MI_COM);
787 if ((frame_val & MI_COM_BUSY) == 0) {
788 udelay(5);
789 frame_val = tr32(MAC_MI_COM);
790 break;
791 }
792 loops -= 1;
793 }
794
795 ret = -EBUSY;
796 if (loops != 0)
797 ret = 0;
798
799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE, tp->mi_mode);
801 udelay(80);
802 }
803
804 return ret;
805}
806
9ef8ca99
MC		 807static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
808{
809 u32 phy;
810
811 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
812 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
813 return;
814
815 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
816 u32 ephy;
817
818 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
819 tg3_writephy(tp, MII_TG3_EPHY_TEST,
820 ephy | MII_TG3_EPHY_SHADOW_EN);
821 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
822 if (enable)
823 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
824 else
825 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
826 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
827 }
828 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
829 }
830 } else {
831 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
832 MII_TG3_AUXCTL_SHDWSEL_MISC;
833 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
834 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
835 if (enable)
836 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
837 else
838 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
839 phy |= MII_TG3_AUXCTL_MISC_WREN;
840 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
841 }
842 }
843}
844
1da177e4
LT		 845static void tg3_phy_set_wirespeed(struct tg3 *tp)
846{
847 u32 val;
848
849 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
850 return;
851
852 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
853 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
854 tg3_writephy(tp, MII_TG3_AUX_CTRL,
855 (val | (1 << 15) | (1 << 4)));
856}
857
858static int tg3_bmcr_reset(struct tg3 *tp)
859{
860 u32 phy_control;
861 int limit, err;
862
863 /* OK, reset it, and poll the BMCR_RESET bit until it
864 * clears or we time out.
865 */
866 phy_control = BMCR_RESET;
867 err = tg3_writephy(tp, MII_BMCR, phy_control);
868 if (err != 0)
869 return -EBUSY;
870
871 limit = 5000;
872 while (limit--) {
873 err = tg3_readphy(tp, MII_BMCR, &phy_control);
874 if (err != 0)
875 return -EBUSY;
876
877 if ((phy_control & BMCR_RESET) == 0) {
878 udelay(40);
879 break;
880 }
881 udelay(10);
882 }
883 if (limit <= 0)
884 return -EBUSY;
885
886 return 0;
887}
888
889static int tg3_wait_macro_done(struct tg3 *tp)
890{
891 int limit = 100;
892
893 while (limit--) {
894 u32 tmp32;
895
896 if (!tg3_readphy(tp, 0x16, &tmp32)) {
897 if ((tmp32 & 0x1000) == 0)
898 break;
899 }
900 }
901 if (limit <= 0)
902 return -EBUSY;
903
904 return 0;
905}
906
907static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
908{
909 static const u32 test_pat[4][6] = {
910 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
911 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
912 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
913 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
914 };
915 int chan;
916
917 for (chan = 0; chan < 4; chan++) {
918 int i;
919
920 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
921 (chan * 0x2000) | 0x0200);
922 tg3_writephy(tp, 0x16, 0x0002);
923
924 for (i = 0; i < 6; i++)
925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
926 test_pat[chan][i]);
927
928 tg3_writephy(tp, 0x16, 0x0202);
929 if (tg3_wait_macro_done(tp)) {
930 *resetp = 1;
931 return -EBUSY;
932 }
933
934 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
935 (chan * 0x2000) | 0x0200);
936 tg3_writephy(tp, 0x16, 0x0082);
937 if (tg3_wait_macro_done(tp)) {
938 *resetp = 1;
939 return -EBUSY;
940 }
941
942 tg3_writephy(tp, 0x16, 0x0802);
943 if (tg3_wait_macro_done(tp)) {
944 *resetp = 1;
945 return -EBUSY;
946 }
947
948 for (i = 0; i < 6; i += 2) {
949 u32 low, high;
950
951 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
952 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
953 tg3_wait_macro_done(tp)) {
954 *resetp = 1;
955 return -EBUSY;
956 }
957 low &= 0x7fff;
958 high &= 0x000f;
959 if (low != test_pat[chan][i] ||
960 high != test_pat[chan][i+1]) {
961 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
962 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
964
965 return -EBUSY;
966 }
967 }
968 }
969
970 return 0;
971}
972
973static int tg3_phy_reset_chanpat(struct tg3 *tp)
974{
975 int chan;
976
977 for (chan = 0; chan < 4; chan++) {
978 int i;
979
980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
981 (chan * 0x2000) | 0x0200);
982 tg3_writephy(tp, 0x16, 0x0002);
983 for (i = 0; i < 6; i++)
984 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
985 tg3_writephy(tp, 0x16, 0x0202);
986 if (tg3_wait_macro_done(tp))
987 return -EBUSY;
988 }
989
990 return 0;
991}
992
993static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
994{
995 u32 reg32, phy9_orig;
996 int retries, do_phy_reset, err;
997
998 retries = 10;
999 do_phy_reset = 1;
1000 do {
1001 if (do_phy_reset) {
1002 err = tg3_bmcr_reset(tp);
1003 if (err)
1004 return err;
1005 do_phy_reset = 0;
1006 }
1007
1008 /* Disable transmitter and interrupt. */
1009 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1010 continue;
1011
1012 reg32 |= 0x3000;
1013 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1014
1015 /* Set full-duplex, 1000 mbps. */
1016 tg3_writephy(tp, MII_BMCR,
1017 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1018
1019 /* Set to master mode. */
1020 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1021 continue;
1022
1023 tg3_writephy(tp, MII_TG3_CTRL,
1024 (MII_TG3_CTRL_AS_MASTER |
1025 MII_TG3_CTRL_ENABLE_AS_MASTER));
1026
1027 /* Enable SM_DSP_CLOCK and 6dB. */
1028 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029
1030 /* Block the PHY control access. */
1031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1032 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1033
1034 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1035 if (!err)
1036 break;
1037 } while (--retries);
1038
1039 err = tg3_phy_reset_chanpat(tp);
1040 if (err)
1041 return err;
1042
1043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1044 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1045
1046 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1047 tg3_writephy(tp, 0x16, 0x0000);
1048
1049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1051 /* Set Extended packet length bit for jumbo frames */
1052 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1053 }
1054 else {
1055 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1056 }
1057
1058 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1059
1060 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1061 reg32 &= ~0x3000;
1062 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1063 } else if (!err)
1064 err = -EBUSY;
1065
1066 return err;
1067}
1068
c8e1e82b
MC		 1069static void tg3_link_report(struct tg3 *);
1070
1da177e4
LT		 1071/* This will reset the tigon3 PHY if there is no valid
1072 * link unless the FORCE argument is non-zero.
1073 */
1074static int tg3_phy_reset(struct tg3 *tp)
1075{
1076 u32 phy_status;
1077 int err;
1078
60189ddf
MC		 1079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1080 u32 val;
1081
1082 val = tr32(GRC_MISC_CFG);
1083 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1084 udelay(40);
1085 }
1da177e4
LT		 1086 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1087 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1088 if (err != 0)
1089 return -EBUSY;
1090
c8e1e82b
MC		 1091 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1092 netif_carrier_off(tp->dev);
1093 tg3_link_report(tp);
1094 }
1095
1da177e4
LT		 1096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1099 err = tg3_phy_reset_5703_4_5(tp);
1100 if (err)
1101 return err;
1102 goto out;
1103 }
1104
1105 err = tg3_bmcr_reset(tp);
1106 if (err)
1107 return err;
1108
b5af7126 1109 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
ce057f01
MC		 1110 u32 val;
1111
1112 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1113 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1114 CPMU_LSPD_1000MB_MACCLK_12_5) {
1115 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1116 udelay(40);
1117 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1118 }
662f38d2
MC		 1119
1120 /* Disable GPHY autopowerdown. */
1121 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1122 MII_TG3_MISC_SHDW_WREN |
1123 MII_TG3_MISC_SHDW_APD_SEL |
1124 MII_TG3_MISC_SHDW_APD_WKTM_84MS);
ce057f01
MC		 1125 }
1126
1da177e4
LT		 1127out:
1128 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1129 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1130 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1131 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1132 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1133 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1134 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1135 }
1136 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1137 tg3_writephy(tp, 0x1c, 0x8d68);
1138 tg3_writephy(tp, 0x1c, 0x8d68);
1139 }
1140 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1141 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1142 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1143 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1144 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1145 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1146 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1147 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1148 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1149 }
c424cb24
MC		 1150 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1151 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1152 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1153 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1154 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1155 tg3_writephy(tp, MII_TG3_TEST1,
1156 MII_TG3_TEST1_TRIM_EN | 0x4);
1157 } else
1158 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1159 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1160 }
1da177e4
LT		 1161 /* Set Extended packet length bit (bit 14) on all chips that */
1162 /* support jumbo frames */
1163 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1164 /* Cannot do read-modify-write on 5401 */
1165 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1166 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1167 u32 phy_reg;
1168
1169 /* Set bit 14 with read-modify-write to preserve other bits */
1170 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1171 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1172 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1173 }
1174
1175 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1176 * jumbo frames transmission.
1177 */
0f893dc6 1178 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1179 u32 phy_reg;
1180
1181 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1182 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1183 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1184 }
1185
715116a1 1186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1187 /* adjust output voltage */
1188 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1189 }
1190
9ef8ca99 1191 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1192 tg3_phy_set_wirespeed(tp);
1193 return 0;
1194}
1195
1196static void tg3_frob_aux_power(struct tg3 *tp)
1197{
1198 struct tg3 *tp_peer = tp;
1199
9d26e213 1200 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1201 return;
1202
8c2dc7e1
MC		 1203 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1204 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1205 struct net_device *dev_peer;
1206
1207 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1208 /* remove_one() may have been run on the peer. */
8c2dc7e1 1209 if (!dev_peer)
bc1c7567
MC		 1210 tp_peer = tp;
1211 else
1212 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1213 }
1214
1da177e4 1215 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1216 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1217 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1218 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1221 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1222 (GRC_LCLCTRL_GPIO_OE0 |
1223 GRC_LCLCTRL_GPIO_OE1 |
1224 GRC_LCLCTRL_GPIO_OE2 |
1225 GRC_LCLCTRL_GPIO_OUTPUT0 |
1226 GRC_LCLCTRL_GPIO_OUTPUT1),
1227 100);
1da177e4
LT		 1228 } else {
1229 u32 no_gpio2;
dc56b7d4 1230 u32 grc_local_ctrl = 0;
1da177e4
LT		 1231
1232 if (tp_peer != tp &&
1233 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1234 return;
1235
dc56b7d4
MC		 1236 /* Workaround to prevent overdrawing Amps. */
1237 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1238 ASIC_REV_5714) {
1239 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1240 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1241 grc_local_ctrl, 100);
dc56b7d4
MC		 1242 }
1243
1da177e4
LT		 1244 /* On 5753 and variants, GPIO2 cannot be used. */
1245 no_gpio2 = tp->nic_sram_data_cfg &
1246 NIC_SRAM_DATA_CFG_NO_GPIO2;
1247
dc56b7d4 1248 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1249 GRC_LCLCTRL_GPIO_OE1 |
1250 GRC_LCLCTRL_GPIO_OE2 |
1251 GRC_LCLCTRL_GPIO_OUTPUT1 |
1252 GRC_LCLCTRL_GPIO_OUTPUT2;
1253 if (no_gpio2) {
1254 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1255 GRC_LCLCTRL_GPIO_OUTPUT2);
1256 }
b401e9e2
MC		 1257 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1258 grc_local_ctrl, 100);
1da177e4
LT		 1259
1260 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1261
b401e9e2
MC		 1262 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1263 grc_local_ctrl, 100);
1da177e4
LT		 1264
1265 if (!no_gpio2) {
1266 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1267 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1268 grc_local_ctrl, 100);
1da177e4
LT		 1269 }
1270 }
1271 } else {
1272 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1273 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1274 if (tp_peer != tp &&
1275 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1276 return;
1277
b401e9e2
MC		 1278 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1279 (GRC_LCLCTRL_GPIO_OE1 |
1280 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1281
b401e9e2
MC		 1282 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1283 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1284
b401e9e2
MC		 1285 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1286 (GRC_LCLCTRL_GPIO_OE1 |
1287 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1288 }
1289 }
1290}
1291
e8f3f6ca
MC		 1292static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1293{
1294 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1295 return 1;
1296 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1297 if (speed != SPEED_10)
1298 return 1;
1299 } else if (speed == SPEED_10)
1300 return 1;
1301
1302 return 0;
1303}
1304
1da177e4
LT		 1305static int tg3_setup_phy(struct tg3 *, int);
1306
1307#define RESET_KIND_SHUTDOWN 0
1308#define RESET_KIND_INIT 1
1309#define RESET_KIND_SUSPEND 2
1310
1311static void tg3_write_sig_post_reset(struct tg3 *, int);
1312static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1313static int tg3_nvram_lock(struct tg3 *);
1314static void tg3_nvram_unlock(struct tg3 *);
1da177e4 1315
15c3b696
MC		 1316static void tg3_power_down_phy(struct tg3 *tp)
1317{
ce057f01
MC		 1318 u32 val;
1319
5129724a
MC		 1320 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1322 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1323 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1324
1325 sg_dig_ctrl |=
1326 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1327 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1328 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1329 }
3f7045c1 1330 return;
5129724a 1331 }
3f7045c1 1332
60189ddf 1333 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 1334 tg3_bmcr_reset(tp);
1335 val = tr32(GRC_MISC_CFG);
1336 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1337 udelay(40);
1338 return;
1339 } else {
715116a1
MC		 1340 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1341 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1342 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1343 }
3f7045c1 1344
15c3b696
MC		 1345 /* The PHY should not be powered down on some chips because
1346 * of bugs.
1347 */
1348 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1349 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1350 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1351 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1352 return;
ce057f01 1353
b5af7126 1354 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
ce057f01
MC		 1355 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1356 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1357 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1358 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1359 }
1360
15c3b696
MC		 1361 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1362}
1363
bc1c7567 1364static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 1365{
1366 u32 misc_host_ctrl;
1367 u16 power_control, power_caps;
1368 int pm = tp->pm_cap;
1369
1370 /* Make sure register accesses (indirect or otherwise)
1371 * will function correctly.
1372 */
1373 pci_write_config_dword(tp->pdev,
1374 TG3PCI_MISC_HOST_CTRL,
1375 tp->misc_host_ctrl);
1376
1377 pci_read_config_word(tp->pdev,
1378 pm + PCI_PM_CTRL,
1379 &power_control);
1380 power_control |= PCI_PM_CTRL_PME_STATUS;
1381 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1382 switch (state) {
bc1c7567 1383 case PCI_D0:
1da177e4
LT		 1384 power_control |= 0;
1385 pci_write_config_word(tp->pdev,
1386 pm + PCI_PM_CTRL,
1387 power_control);
8c6bda1a
MC		 1388 udelay(100); /* Delay after power state change */
1389
9d26e213
MC		 1390 /* Switch out of Vaux if it is a NIC */
1391 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 1392 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1393
1394 return 0;
1395
bc1c7567 1396 case PCI_D1:
1da177e4
LT		 1397 power_control |= 1;
1398 break;
1399
bc1c7567 1400 case PCI_D2:
1da177e4
LT		 1401 power_control |= 2;
1402 break;
1403
bc1c7567 1404 case PCI_D3hot:
1da177e4
LT		 1405 power_control |= 3;
1406 break;
1407
1408 default:
1409 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1410 "requested.\n",
1411 tp->dev->name, state);
1412 return -EINVAL;
1413 };
1414
1415 power_control |= PCI_PM_CTRL_PME_ENABLE;
1416
1417 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1418 tw32(TG3PCI_MISC_HOST_CTRL,
1419 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1420
1421 if (tp->link_config.phy_is_low_power == 0) {
1422 tp->link_config.phy_is_low_power = 1;
1423 tp->link_config.orig_speed = tp->link_config.speed;
1424 tp->link_config.orig_duplex = tp->link_config.duplex;
1425 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1426 }
1427
747e8f8b 1428 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1429 tp->link_config.speed = SPEED_10;
1430 tp->link_config.duplex = DUPLEX_HALF;
1431 tp->link_config.autoneg = AUTONEG_ENABLE;
1432 tg3_setup_phy(tp, 0);
1433 }
1434
b5d3772c
MC		 1435 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1436 u32 val;
1437
1438 val = tr32(GRC_VCPU_EXT_CTRL);
1439 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1440 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 1441 int i;
1442 u32 val;
1443
1444 for (i = 0; i < 200; i++) {
1445 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1446 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1447 break;
1448 msleep(1);
1449 }
1450 }
a85feb8c
GZ		 1451 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1452 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1453 WOL_DRV_STATE_SHUTDOWN |
1454 WOL_DRV_WOL |
1455 WOL_SET_MAGIC_PKT);
6921d201 1456
1da177e4
LT		 1457 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1458
1459 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1460 u32 mac_mode;
1461
1462 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1463 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1464 udelay(40);
1465
3f7045c1
MC		 1466 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1467 mac_mode = MAC_MODE_PORT_MODE_GMII;
1468 else
1469 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 1470
e8f3f6ca
MC		 1471 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1472 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1473 ASIC_REV_5700) {
1474 u32 speed = (tp->tg3_flags &
1475 TG3_FLAG_WOL_SPEED_100MB) ?
1476 SPEED_100 : SPEED_10;
1477 if (tg3_5700_link_polarity(tp, speed))
1478 mac_mode |= MAC_MODE_LINK_POLARITY;
1479 else
1480 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1481 }
1da177e4
LT		 1482 } else {
1483 mac_mode = MAC_MODE_PORT_MODE_TBI;
1484 }
1485
cbf46853 1486 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1487 tw32(MAC_LED_CTRL, tp->led_ctrl);
1488
1489 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1490 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1491 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1492
1493 tw32_f(MAC_MODE, mac_mode);
1494 udelay(100);
1495
1496 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1497 udelay(10);
1498 }
1499
1500 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1501 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1502 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1503 u32 base_val;
1504
1505 base_val = tp->pci_clock_ctrl;
1506 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1507 CLOCK_CTRL_TXCLK_DISABLE);
1508
b401e9e2
MC		 1509 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1510 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 1511 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 1512 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 1513 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 1514 /* do nothing */
85e94ced 1515 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1516 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1517 u32 newbits1, newbits2;
1518
1519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1521 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1522 CLOCK_CTRL_TXCLK_DISABLE |
1523 CLOCK_CTRL_ALTCLK);
1524 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1525 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1526 newbits1 = CLOCK_CTRL_625_CORE;
1527 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1528 } else {
1529 newbits1 = CLOCK_CTRL_ALTCLK;
1530 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1531 }
1532
b401e9e2
MC		 1533 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1534 40);
1da177e4 1535
b401e9e2
MC		 1536 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1537 40);
1da177e4
LT		 1538
1539 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1540 u32 newbits3;
1541
1542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1543 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1544 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1545 CLOCK_CTRL_TXCLK_DISABLE |
1546 CLOCK_CTRL_44MHZ_CORE);
1547 } else {
1548 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1549 }
1550
b401e9e2
MC		 1551 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1552 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1553 }
1554 }
1555
6921d201 1556 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
0d3031d9
MC		 1557 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1558 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
3f7045c1 1559 tg3_power_down_phy(tp);
6921d201 1560
1da177e4
LT		 1561 tg3_frob_aux_power(tp);
1562
1563 /* Workaround for unstable PLL clock */
1564 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1565 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1566 u32 val = tr32(0x7d00);
1567
1568 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1569 tw32(0x7d00, val);
6921d201 1570 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1571 int err;
1572
1573 err = tg3_nvram_lock(tp);
1da177e4 1574 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1575 if (!err)
1576 tg3_nvram_unlock(tp);
6921d201 1577 }
1da177e4
LT		 1578 }
1579
bbadf503
MC		 1580 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1581
1da177e4
LT		 1582 /* Finally, set the new power state. */
1583 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1584 udelay(100); /* Delay after power state change */
1da177e4 1585
1da177e4
LT		 1586 return 0;
1587}
1588
1589static void tg3_link_report(struct tg3 *tp)
1590{
1591 if (!netif_carrier_ok(tp->dev)) {
9f88f29f
MC		 1592 if (netif_msg_link(tp))
1593 printk(KERN_INFO PFX "%s: Link is down.\n",
1594 tp->dev->name);
1595 } else if (netif_msg_link(tp)) {
1da177e4
LT		 1596 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1597 tp->dev->name,
1598 (tp->link_config.active_speed == SPEED_1000 ?
1599 1000 :
1600 (tp->link_config.active_speed == SPEED_100 ?
1601 100 : 10)),
1602 (tp->link_config.active_duplex == DUPLEX_FULL ?
1603 "full" : "half"));
1604
8d018621
MC		 1605 printk(KERN_INFO PFX
1606 "%s: Flow control is %s for TX and %s for RX.\n",
1da177e4 1607 tp->dev->name,
8d018621
MC		 1608 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1609 "on" : "off",
1610 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1611 "on" : "off");
1da177e4
LT		 1612 }
1613}
1614
ba4d07a8
MC		 1615static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1616{
1617 u16 miireg;
1618
1619 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1620 miireg = ADVERTISE_PAUSE_CAP;
1621 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1622 miireg = ADVERTISE_PAUSE_ASYM;
1623 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1624 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1625 else
1626 miireg = 0;
1627
1628 return miireg;
1629}
1630
1631static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1632{
1633 u16 miireg;
1634
1635 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1636 miireg = ADVERTISE_1000XPAUSE;
1637 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1638 miireg = ADVERTISE_1000XPSE_ASYM;
1639 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1640 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1641 else
1642 miireg = 0;
1643
1644 return miireg;
1645}
1646
95937268
MC		 1647static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1648{
1649 u8 cap = 0;
1650
1651 if (lcladv & ADVERTISE_PAUSE_CAP) {
1652 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1653 if (rmtadv & LPA_PAUSE_CAP)
1654 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1655 else if (rmtadv & LPA_PAUSE_ASYM)
1656 cap = TG3_FLOW_CTRL_RX;
1657 } else {
1658 if (rmtadv & LPA_PAUSE_CAP)
1659 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1660 }
1661 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1662 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1663 cap = TG3_FLOW_CTRL_TX;
1664 }
1665
1666 return cap;
1667}
1668
1669static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1670{
1671 u8 cap = 0;
1672
1673 if (lcladv & ADVERTISE_1000XPAUSE) {
1674 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1675 if (rmtadv & LPA_1000XPAUSE)
1676 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1677 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1678 cap = TG3_FLOW_CTRL_RX;
1679 } else {
1680 if (rmtadv & LPA_1000XPAUSE)
1681 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1682 }
1683 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1684 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1685 cap = TG3_FLOW_CTRL_TX;
1686 }
1687
1688 return cap;
1689}
1690
1da177e4
LT		 1691static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1692{
8d018621 1693 u8 new_tg3_flags = 0;
1da177e4
LT		 1694 u32 old_rx_mode = tp->rx_mode;
1695 u32 old_tx_mode = tp->tx_mode;
1696
1697 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
5be73b47 1698 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
95937268
MC		 1699 new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1700 remote_adv);
1701 else
1702 new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1703 remote_adv);
1da177e4 1704 } else {
8d018621 1705 new_tg3_flags = tp->link_config.flowctrl;
1da177e4
LT		 1706 }
1707
8d018621
MC		 1708 tp->link_config.active_flowctrl = new_tg3_flags;
1709
1710 if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1da177e4
LT		 1711 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1712 else
1713 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1714
1715 if (old_rx_mode != tp->rx_mode) {
1716 tw32_f(MAC_RX_MODE, tp->rx_mode);
1717 }
6aa20a22 1718
8d018621 1719 if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1da177e4
LT		 1720 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1721 else
1722 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1723
1724 if (old_tx_mode != tp->tx_mode) {
1725 tw32_f(MAC_TX_MODE, tp->tx_mode);
1726 }
1727}
1728
1729static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1730{
1731 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1732 case MII_TG3_AUX_STAT_10HALF:
1733 *speed = SPEED_10;
1734 *duplex = DUPLEX_HALF;
1735 break;
1736
1737 case MII_TG3_AUX_STAT_10FULL:
1738 *speed = SPEED_10;
1739 *duplex = DUPLEX_FULL;
1740 break;
1741
1742 case MII_TG3_AUX_STAT_100HALF:
1743 *speed = SPEED_100;
1744 *duplex = DUPLEX_HALF;
1745 break;
1746
1747 case MII_TG3_AUX_STAT_100FULL:
1748 *speed = SPEED_100;
1749 *duplex = DUPLEX_FULL;
1750 break;
1751
1752 case MII_TG3_AUX_STAT_1000HALF:
1753 *speed = SPEED_1000;
1754 *duplex = DUPLEX_HALF;
1755 break;
1756
1757 case MII_TG3_AUX_STAT_1000FULL:
1758 *speed = SPEED_1000;
1759 *duplex = DUPLEX_FULL;
1760 break;
1761
1762 default:
715116a1
MC		 1763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1764 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1765 SPEED_10;
1766 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1767 DUPLEX_HALF;
1768 break;
1769 }
1da177e4
LT		 1770 *speed = SPEED_INVALID;
1771 *duplex = DUPLEX_INVALID;
1772 break;
1773 };
1774}
1775
1776static void tg3_phy_copper_begin(struct tg3 *tp)
1777{
1778 u32 new_adv;
1779 int i;
1780
1781 if (tp->link_config.phy_is_low_power) {
1782 /* Entering low power mode. Disable gigabit and
1783 * 100baseT advertisements.
1784 */
1785 tg3_writephy(tp, MII_TG3_CTRL, 0);
1786
1787 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1788 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1789 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1790 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1791
1792 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1793 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 1794 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1795 tp->link_config.advertising &=
1796 ~(ADVERTISED_1000baseT_Half |
1797 ADVERTISED_1000baseT_Full);
1798
ba4d07a8 1799 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 1800 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1801 new_adv |= ADVERTISE_10HALF;
1802 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1803 new_adv |= ADVERTISE_10FULL;
1804 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1805 new_adv |= ADVERTISE_100HALF;
1806 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1807 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 1808
1809 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1810
1da177e4
LT		 1811 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1812
1813 if (tp->link_config.advertising &
1814 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1815 new_adv = 0;
1816 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1817 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1818 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1819 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1820 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1821 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1822 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1823 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1824 MII_TG3_CTRL_ENABLE_AS_MASTER);
1825 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1826 } else {
1827 tg3_writephy(tp, MII_TG3_CTRL, 0);
1828 }
1829 } else {
ba4d07a8
MC		 1830 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1831 new_adv |= ADVERTISE_CSMA;
1832
1da177e4
LT		 1833 /* Asking for a specific link mode. */
1834 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 1835 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1836
1837 if (tp->link_config.duplex == DUPLEX_FULL)
1838 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1839 else
1840 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1841 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1842 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1843 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1844 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 1845 } else {
1da177e4
LT		 1846 if (tp->link_config.speed == SPEED_100) {
1847 if (tp->link_config.duplex == DUPLEX_FULL)
1848 new_adv |= ADVERTISE_100FULL;
1849 else
1850 new_adv |= ADVERTISE_100HALF;
1851 } else {
1852 if (tp->link_config.duplex == DUPLEX_FULL)
1853 new_adv |= ADVERTISE_10FULL;
1854 else
1855 new_adv |= ADVERTISE_10HALF;
1856 }
1857 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 1858
1859 new_adv = 0;
1da177e4 1860 }
ba4d07a8
MC		 1861
1862 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 1863 }
1864
1865 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1866 tp->link_config.speed != SPEED_INVALID) {
1867 u32 bmcr, orig_bmcr;
1868
1869 tp->link_config.active_speed = tp->link_config.speed;
1870 tp->link_config.active_duplex = tp->link_config.duplex;
1871
1872 bmcr = 0;
1873 switch (tp->link_config.speed) {
1874 default:
1875 case SPEED_10:
1876 break;
1877
1878 case SPEED_100:
1879 bmcr |= BMCR_SPEED100;
1880 break;
1881
1882 case SPEED_1000:
1883 bmcr |= TG3_BMCR_SPEED1000;
1884 break;
1885 };
1886
1887 if (tp->link_config.duplex == DUPLEX_FULL)
1888 bmcr |= BMCR_FULLDPLX;
1889
1890 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1891 (bmcr != orig_bmcr)) {
1892 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1893 for (i = 0; i < 1500; i++) {
1894 u32 tmp;
1895
1896 udelay(10);
1897 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1898 tg3_readphy(tp, MII_BMSR, &tmp))
1899 continue;
1900 if (!(tmp & BMSR_LSTATUS)) {
1901 udelay(40);
1902 break;
1903 }
1904 }
1905 tg3_writephy(tp, MII_BMCR, bmcr);
1906 udelay(40);
1907 }
1908 } else {
1909 tg3_writephy(tp, MII_BMCR,
1910 BMCR_ANENABLE | BMCR_ANRESTART);
1911 }
1912}
1913
1914static int tg3_init_5401phy_dsp(struct tg3 *tp)
1915{
1916 int err;
1917
1918 /* Turn off tap power management. */
1919 /* Set Extended packet length bit */
1920 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1921
1922 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1923 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1924
1925 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1926 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1927
1928 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1929 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1930
1931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1933
1934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1936
1937 udelay(40);
1938
1939 return err;
1940}
1941
3600d918 1942static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 1943{
3600d918
MC		 1944 u32 adv_reg, all_mask = 0;
1945
1946 if (mask & ADVERTISED_10baseT_Half)
1947 all_mask |= ADVERTISE_10HALF;
1948 if (mask & ADVERTISED_10baseT_Full)
1949 all_mask |= ADVERTISE_10FULL;
1950 if (mask & ADVERTISED_100baseT_Half)
1951 all_mask |= ADVERTISE_100HALF;
1952 if (mask & ADVERTISED_100baseT_Full)
1953 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 1954
1955 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1956 return 0;
1957
1da177e4
LT		 1958 if ((adv_reg & all_mask) != all_mask)
1959 return 0;
1960 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1961 u32 tg3_ctrl;
1962
3600d918
MC		 1963 all_mask = 0;
1964 if (mask & ADVERTISED_1000baseT_Half)
1965 all_mask |= ADVERTISE_1000HALF;
1966 if (mask & ADVERTISED_1000baseT_Full)
1967 all_mask |= ADVERTISE_1000FULL;
1968
1da177e4
LT		 1969 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1970 return 0;
1971
1da177e4
LT		 1972 if ((tg3_ctrl & all_mask) != all_mask)
1973 return 0;
1974 }
1975 return 1;
1976}
1977
1978static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1979{
1980 int current_link_up;
1981 u32 bmsr, dummy;
1982 u16 current_speed;
1983 u8 current_duplex;
1984 int i, err;
1985
1986 tw32(MAC_EVENT, 0);
1987
1988 tw32_f(MAC_STATUS,
1989 (MAC_STATUS_SYNC_CHANGED |
1990 MAC_STATUS_CFG_CHANGED |
1991 MAC_STATUS_MI_COMPLETION |
1992 MAC_STATUS_LNKSTATE_CHANGED));
1993 udelay(40);
1994
1995 tp->mi_mode = MAC_MI_MODE_BASE;
1996 tw32_f(MAC_MI_MODE, tp->mi_mode);
1997 udelay(80);
1998
1999 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2000
2001 /* Some third-party PHYs need to be reset on link going
2002 * down.
2003 */
2004 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2005 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2006 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2007 netif_carrier_ok(tp->dev)) {
2008 tg3_readphy(tp, MII_BMSR, &bmsr);
2009 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2010 !(bmsr & BMSR_LSTATUS))
2011 force_reset = 1;
2012 }
2013 if (force_reset)
2014 tg3_phy_reset(tp);
2015
2016 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2017 tg3_readphy(tp, MII_BMSR, &bmsr);
2018 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2019 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2020 bmsr = 0;
2021
2022 if (!(bmsr & BMSR_LSTATUS)) {
2023 err = tg3_init_5401phy_dsp(tp);
2024 if (err)
2025 return err;
2026
2027 tg3_readphy(tp, MII_BMSR, &bmsr);
2028 for (i = 0; i < 1000; i++) {
2029 udelay(10);
2030 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2031 (bmsr & BMSR_LSTATUS)) {
2032 udelay(40);
2033 break;
2034 }
2035 }
2036
2037 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2038 !(bmsr & BMSR_LSTATUS) &&
2039 tp->link_config.active_speed == SPEED_1000) {
2040 err = tg3_phy_reset(tp);
2041 if (!err)
2042 err = tg3_init_5401phy_dsp(tp);
2043 if (err)
2044 return err;
2045 }
2046 }
2047 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2048 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2049 /* 5701 {A0,B0} CRC bug workaround */
2050 tg3_writephy(tp, 0x15, 0x0a75);
2051 tg3_writephy(tp, 0x1c, 0x8c68);
2052 tg3_writephy(tp, 0x1c, 0x8d68);
2053 tg3_writephy(tp, 0x1c, 0x8c68);
2054 }
2055
2056 /* Clear pending interrupts... */
2057 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2058 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2059
2060 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2061 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2062 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2063 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2064
2065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2067 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2068 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2069 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2070 else
2071 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2072 }
2073
2074 current_link_up = 0;
2075 current_speed = SPEED_INVALID;
2076 current_duplex = DUPLEX_INVALID;
2077
2078 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2079 u32 val;
2080
2081 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2082 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2083 if (!(val & (1 << 10))) {
2084 val |= (1 << 10);
2085 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2086 goto relink;
2087 }
2088 }
2089
2090 bmsr = 0;
2091 for (i = 0; i < 100; i++) {
2092 tg3_readphy(tp, MII_BMSR, &bmsr);
2093 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2094 (bmsr & BMSR_LSTATUS))
2095 break;
2096 udelay(40);
2097 }
2098
2099 if (bmsr & BMSR_LSTATUS) {
2100 u32 aux_stat, bmcr;
2101
2102 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2103 for (i = 0; i < 2000; i++) {
2104 udelay(10);
2105 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2106 aux_stat)
2107 break;
2108 }
2109
2110 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2111 &current_speed,
2112 &current_duplex);
2113
2114 bmcr = 0;
2115 for (i = 0; i < 200; i++) {
2116 tg3_readphy(tp, MII_BMCR, &bmcr);
2117 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2118 continue;
2119 if (bmcr && bmcr != 0x7fff)
2120 break;
2121 udelay(10);
2122 }
2123
2124 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2125 if (bmcr & BMCR_ANENABLE) {
2126 current_link_up = 1;
2127
2128 /* Force autoneg restart if we are exiting
2129 * low power mode.
2130 */
3600d918
MC		 2131 if (!tg3_copper_is_advertising_all(tp,
2132 tp->link_config.advertising))
1da177e4
LT		 2133 current_link_up = 0;
2134 } else {
2135 current_link_up = 0;
2136 }
2137 } else {
2138 if (!(bmcr & BMCR_ANENABLE) &&
2139 tp->link_config.speed == current_speed &&
2140 tp->link_config.duplex == current_duplex) {
2141 current_link_up = 1;
2142 } else {
2143 current_link_up = 0;
2144 }
2145 }
2146
2147 tp->link_config.active_speed = current_speed;
2148 tp->link_config.active_duplex = current_duplex;
2149 }
2150
2151 if (current_link_up == 1 &&
2152 (tp->link_config.active_duplex == DUPLEX_FULL) &&
2153 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2154 u32 local_adv, remote_adv;
2155
2156 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
2157 local_adv = 0;
1da177e4
LT		 2158
2159 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2160 remote_adv = 0;
2161
ba4d07a8
MC		 2162 /* If we are not advertising what has been requested,
2163 * bring the link down and reconfigure.
1da177e4 2164 */
ba4d07a8
MC		 2165 if (local_adv !=
2166 tg3_advert_flowctrl_1000T(tp->link_config.flowctrl)) {
1da177e4
LT		 2167 current_link_up = 0;
2168 } else {
2169 tg3_setup_flow_control(tp, local_adv, remote_adv);
2170 }
2171 }
2172relink:
6921d201 2173 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 2174 u32 tmp;
2175
2176 tg3_phy_copper_begin(tp);
2177
2178 tg3_readphy(tp, MII_BMSR, &tmp);
2179 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2180 (tmp & BMSR_LSTATUS))
2181 current_link_up = 1;
2182 }
2183
2184 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2185 if (current_link_up == 1) {
2186 if (tp->link_config.active_speed == SPEED_100 ||
2187 tp->link_config.active_speed == SPEED_10)
2188 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2189 else
2190 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2191 } else
2192 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2193
2194 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2195 if (tp->link_config.active_duplex == DUPLEX_HALF)
2196 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2197
1da177e4 2198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 2199 if (current_link_up == 1 &&
2200 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 2201 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 2202 else
2203 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 2204 }
2205
2206 /* ??? Without this setting Netgear GA302T PHY does not
2207 * ??? send/receive packets...
2208 */
2209 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2210 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2211 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2212 tw32_f(MAC_MI_MODE, tp->mi_mode);
2213 udelay(80);
2214 }
2215
2216 tw32_f(MAC_MODE, tp->mac_mode);
2217 udelay(40);
2218
2219 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2220 /* Polled via timer. */
2221 tw32_f(MAC_EVENT, 0);
2222 } else {
2223 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2224 }
2225 udelay(40);
2226
2227 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2228 current_link_up == 1 &&
2229 tp->link_config.active_speed == SPEED_1000 &&
2230 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2231 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2232 udelay(120);
2233 tw32_f(MAC_STATUS,
2234 (MAC_STATUS_SYNC_CHANGED |
2235 MAC_STATUS_CFG_CHANGED));
2236 udelay(40);
2237 tg3_write_mem(tp,
2238 NIC_SRAM_FIRMWARE_MBOX,
2239 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2240 }
2241
2242 if (current_link_up != netif_carrier_ok(tp->dev)) {
2243 if (current_link_up)
2244 netif_carrier_on(tp->dev);
2245 else
2246 netif_carrier_off(tp->dev);
2247 tg3_link_report(tp);
2248 }
2249
2250 return 0;
2251}
2252
2253struct tg3_fiber_aneginfo {
2254 int state;
2255#define ANEG_STATE_UNKNOWN 0
2256#define ANEG_STATE_AN_ENABLE 1
2257#define ANEG_STATE_RESTART_INIT 2
2258#define ANEG_STATE_RESTART 3
2259#define ANEG_STATE_DISABLE_LINK_OK 4
2260#define ANEG_STATE_ABILITY_DETECT_INIT 5
2261#define ANEG_STATE_ABILITY_DETECT 6
2262#define ANEG_STATE_ACK_DETECT_INIT 7
2263#define ANEG_STATE_ACK_DETECT 8
2264#define ANEG_STATE_COMPLETE_ACK_INIT 9
2265#define ANEG_STATE_COMPLETE_ACK 10
2266#define ANEG_STATE_IDLE_DETECT_INIT 11
2267#define ANEG_STATE_IDLE_DETECT 12
2268#define ANEG_STATE_LINK_OK 13
2269#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2270#define ANEG_STATE_NEXT_PAGE_WAIT 15
2271
2272 u32 flags;
2273#define MR_AN_ENABLE 0x00000001
2274#define MR_RESTART_AN 0x00000002
2275#define MR_AN_COMPLETE 0x00000004
2276#define MR_PAGE_RX 0x00000008
2277#define MR_NP_LOADED 0x00000010
2278#define MR_TOGGLE_TX 0x00000020
2279#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2280#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2281#define MR_LP_ADV_SYM_PAUSE 0x00000100
2282#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2283#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2284#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2285#define MR_LP_ADV_NEXT_PAGE 0x00001000
2286#define MR_TOGGLE_RX 0x00002000
2287#define MR_NP_RX 0x00004000
2288
2289#define MR_LINK_OK 0x80000000
2290
2291 unsigned long link_time, cur_time;
2292
2293 u32 ability_match_cfg;
2294 int ability_match_count;
2295
2296 char ability_match, idle_match, ack_match;
2297
2298 u32 txconfig, rxconfig;
2299#define ANEG_CFG_NP 0x00000080
2300#define ANEG_CFG_ACK 0x00000040
2301#define ANEG_CFG_RF2 0x00000020
2302#define ANEG_CFG_RF1 0x00000010
2303#define ANEG_CFG_PS2 0x00000001
2304#define ANEG_CFG_PS1 0x00008000
2305#define ANEG_CFG_HD 0x00004000
2306#define ANEG_CFG_FD 0x00002000
2307#define ANEG_CFG_INVAL 0x00001f06
2308
2309};
2310#define ANEG_OK 0
2311#define ANEG_DONE 1
2312#define ANEG_TIMER_ENAB 2
2313#define ANEG_FAILED -1
2314
2315#define ANEG_STATE_SETTLE_TIME 10000
2316
2317static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2318 struct tg3_fiber_aneginfo *ap)
2319{
5be73b47 2320 u16 flowctrl;
1da177e4
LT		 2321 unsigned long delta;
2322 u32 rx_cfg_reg;
2323 int ret;
2324
2325 if (ap->state == ANEG_STATE_UNKNOWN) {
2326 ap->rxconfig = 0;
2327 ap->link_time = 0;
2328 ap->cur_time = 0;
2329 ap->ability_match_cfg = 0;
2330 ap->ability_match_count = 0;
2331 ap->ability_match = 0;
2332 ap->idle_match = 0;
2333 ap->ack_match = 0;
2334 }
2335 ap->cur_time++;
2336
2337 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2338 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2339
2340 if (rx_cfg_reg != ap->ability_match_cfg) {
2341 ap->ability_match_cfg = rx_cfg_reg;
2342 ap->ability_match = 0;
2343 ap->ability_match_count = 0;
2344 } else {
2345 if (++ap->ability_match_count > 1) {
2346 ap->ability_match = 1;
2347 ap->ability_match_cfg = rx_cfg_reg;
2348 }
2349 }
2350 if (rx_cfg_reg & ANEG_CFG_ACK)
2351 ap->ack_match = 1;
2352 else
2353 ap->ack_match = 0;
2354
2355 ap->idle_match = 0;
2356 } else {
2357 ap->idle_match = 1;
2358 ap->ability_match_cfg = 0;
2359 ap->ability_match_count = 0;
2360 ap->ability_match = 0;
2361 ap->ack_match = 0;
2362
2363 rx_cfg_reg = 0;
2364 }
2365
2366 ap->rxconfig = rx_cfg_reg;
2367 ret = ANEG_OK;
2368
2369 switch(ap->state) {
2370 case ANEG_STATE_UNKNOWN:
2371 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2372 ap->state = ANEG_STATE_AN_ENABLE;
2373
2374 /* fallthru */
2375 case ANEG_STATE_AN_ENABLE:
2376 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2377 if (ap->flags & MR_AN_ENABLE) {
2378 ap->link_time = 0;
2379 ap->cur_time = 0;
2380 ap->ability_match_cfg = 0;
2381 ap->ability_match_count = 0;
2382 ap->ability_match = 0;
2383 ap->idle_match = 0;
2384 ap->ack_match = 0;
2385
2386 ap->state = ANEG_STATE_RESTART_INIT;
2387 } else {
2388 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2389 }
2390 break;
2391
2392 case ANEG_STATE_RESTART_INIT:
2393 ap->link_time = ap->cur_time;
2394 ap->flags &= ~(MR_NP_LOADED);
2395 ap->txconfig = 0;
2396 tw32(MAC_TX_AUTO_NEG, 0);
2397 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2398 tw32_f(MAC_MODE, tp->mac_mode);
2399 udelay(40);
2400
2401 ret = ANEG_TIMER_ENAB;
2402 ap->state = ANEG_STATE_RESTART;
2403
2404 /* fallthru */
2405 case ANEG_STATE_RESTART:
2406 delta = ap->cur_time - ap->link_time;
2407 if (delta > ANEG_STATE_SETTLE_TIME) {
2408 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2409 } else {
2410 ret = ANEG_TIMER_ENAB;
2411 }
2412 break;
2413
2414 case ANEG_STATE_DISABLE_LINK_OK:
2415 ret = ANEG_DONE;
2416 break;
2417
2418 case ANEG_STATE_ABILITY_DETECT_INIT:
2419 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 2420 ap->txconfig = ANEG_CFG_FD;
2421 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2422 if (flowctrl & ADVERTISE_1000XPAUSE)
2423 ap->txconfig |= ANEG_CFG_PS1;
2424 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2425 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 2426 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2427 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2428 tw32_f(MAC_MODE, tp->mac_mode);
2429 udelay(40);
2430
2431 ap->state = ANEG_STATE_ABILITY_DETECT;
2432 break;
2433
2434 case ANEG_STATE_ABILITY_DETECT:
2435 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2436 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2437 }
2438 break;
2439
2440 case ANEG_STATE_ACK_DETECT_INIT:
2441 ap->txconfig |= ANEG_CFG_ACK;
2442 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2443 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2444 tw32_f(MAC_MODE, tp->mac_mode);
2445 udelay(40);
2446
2447 ap->state = ANEG_STATE_ACK_DETECT;
2448
2449 /* fallthru */
2450 case ANEG_STATE_ACK_DETECT:
2451 if (ap->ack_match != 0) {
2452 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2453 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2454 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2455 } else {
2456 ap->state = ANEG_STATE_AN_ENABLE;
2457 }
2458 } else if (ap->ability_match != 0 &&
2459 ap->rxconfig == 0) {
2460 ap->state = ANEG_STATE_AN_ENABLE;
2461 }
2462 break;
2463
2464 case ANEG_STATE_COMPLETE_ACK_INIT:
2465 if (ap->rxconfig & ANEG_CFG_INVAL) {
2466 ret = ANEG_FAILED;
2467 break;
2468 }
2469 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2470 MR_LP_ADV_HALF_DUPLEX |
2471 MR_LP_ADV_SYM_PAUSE |
2472 MR_LP_ADV_ASYM_PAUSE |
2473 MR_LP_ADV_REMOTE_FAULT1 |
2474 MR_LP_ADV_REMOTE_FAULT2 |
2475 MR_LP_ADV_NEXT_PAGE |
2476 MR_TOGGLE_RX |
2477 MR_NP_RX);
2478 if (ap->rxconfig & ANEG_CFG_FD)
2479 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2480 if (ap->rxconfig & ANEG_CFG_HD)
2481 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2482 if (ap->rxconfig & ANEG_CFG_PS1)
2483 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2484 if (ap->rxconfig & ANEG_CFG_PS2)
2485 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2486 if (ap->rxconfig & ANEG_CFG_RF1)
2487 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2488 if (ap->rxconfig & ANEG_CFG_RF2)
2489 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2490 if (ap->rxconfig & ANEG_CFG_NP)
2491 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2492
2493 ap->link_time = ap->cur_time;
2494
2495 ap->flags ^= (MR_TOGGLE_TX);
2496 if (ap->rxconfig & 0x0008)
2497 ap->flags |= MR_TOGGLE_RX;
2498 if (ap->rxconfig & ANEG_CFG_NP)
2499 ap->flags |= MR_NP_RX;
2500 ap->flags |= MR_PAGE_RX;
2501
2502 ap->state = ANEG_STATE_COMPLETE_ACK;
2503 ret = ANEG_TIMER_ENAB;
2504 break;
2505
2506 case ANEG_STATE_COMPLETE_ACK:
2507 if (ap->ability_match != 0 &&
2508 ap->rxconfig == 0) {
2509 ap->state = ANEG_STATE_AN_ENABLE;
2510 break;
2511 }
2512 delta = ap->cur_time - ap->link_time;
2513 if (delta > ANEG_STATE_SETTLE_TIME) {
2514 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2515 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2516 } else {
2517 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2518 !(ap->flags & MR_NP_RX)) {
2519 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2520 } else {
2521 ret = ANEG_FAILED;
2522 }
2523 }
2524 }
2525 break;
2526
2527 case ANEG_STATE_IDLE_DETECT_INIT:
2528 ap->link_time = ap->cur_time;
2529 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2530 tw32_f(MAC_MODE, tp->mac_mode);
2531 udelay(40);
2532
2533 ap->state = ANEG_STATE_IDLE_DETECT;
2534 ret = ANEG_TIMER_ENAB;
2535 break;
2536
2537 case ANEG_STATE_IDLE_DETECT:
2538 if (ap->ability_match != 0 &&
2539 ap->rxconfig == 0) {
2540 ap->state = ANEG_STATE_AN_ENABLE;
2541 break;
2542 }
2543 delta = ap->cur_time - ap->link_time;
2544 if (delta > ANEG_STATE_SETTLE_TIME) {
2545 /* XXX another gem from the Broadcom driver :( */
2546 ap->state = ANEG_STATE_LINK_OK;
2547 }
2548 break;
2549
2550 case ANEG_STATE_LINK_OK:
2551 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2552 ret = ANEG_DONE;
2553 break;
2554
2555 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2556 /* ??? unimplemented */
2557 break;
2558
2559 case ANEG_STATE_NEXT_PAGE_WAIT:
2560 /* ??? unimplemented */
2561 break;
2562
2563 default:
2564 ret = ANEG_FAILED;
2565 break;
2566 };
2567
2568 return ret;
2569}
2570
5be73b47 2571static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 2572{
2573 int res = 0;
2574 struct tg3_fiber_aneginfo aninfo;
2575 int status = ANEG_FAILED;
2576 unsigned int tick;
2577 u32 tmp;
2578
2579 tw32_f(MAC_TX_AUTO_NEG, 0);
2580
2581 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2582 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2583 udelay(40);
2584
2585 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2586 udelay(40);
2587
2588 memset(&aninfo, 0, sizeof(aninfo));
2589 aninfo.flags |= MR_AN_ENABLE;
2590 aninfo.state = ANEG_STATE_UNKNOWN;
2591 aninfo.cur_time = 0;
2592 tick = 0;
2593 while (++tick < 195000) {
2594 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2595 if (status == ANEG_DONE || status == ANEG_FAILED)
2596 break;
2597
2598 udelay(1);
2599 }
2600
2601 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2602 tw32_f(MAC_MODE, tp->mac_mode);
2603 udelay(40);
2604
5be73b47
MC		 2605 *txflags = aninfo.txconfig;
2606 *rxflags = aninfo.flags;
1da177e4
LT		 2607
2608 if (status == ANEG_DONE &&
2609 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2610 MR_LP_ADV_FULL_DUPLEX)))
2611 res = 1;
2612
2613 return res;
2614}
2615
2616static void tg3_init_bcm8002(struct tg3 *tp)
2617{
2618 u32 mac_status = tr32(MAC_STATUS);
2619 int i;
2620
2621 /* Reset when initting first time or we have a link. */
2622 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2623 !(mac_status & MAC_STATUS_PCS_SYNCED))
2624 return;
2625
2626 /* Set PLL lock range. */
2627 tg3_writephy(tp, 0x16, 0x8007);
2628
2629 /* SW reset */
2630 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2631
2632 /* Wait for reset to complete. */
2633 /* XXX schedule_timeout() ... */
2634 for (i = 0; i < 500; i++)
2635 udelay(10);
2636
2637 /* Config mode; select PMA/Ch 1 regs. */
2638 tg3_writephy(tp, 0x10, 0x8411);
2639
2640 /* Enable auto-lock and comdet, select txclk for tx. */
2641 tg3_writephy(tp, 0x11, 0x0a10);
2642
2643 tg3_writephy(tp, 0x18, 0x00a0);
2644 tg3_writephy(tp, 0x16, 0x41ff);
2645
2646 /* Assert and deassert POR. */
2647 tg3_writephy(tp, 0x13, 0x0400);
2648 udelay(40);
2649 tg3_writephy(tp, 0x13, 0x0000);
2650
2651 tg3_writephy(tp, 0x11, 0x0a50);
2652 udelay(40);
2653 tg3_writephy(tp, 0x11, 0x0a10);
2654
2655 /* Wait for signal to stabilize */
2656 /* XXX schedule_timeout() ... */
2657 for (i = 0; i < 15000; i++)
2658 udelay(10);
2659
2660 /* Deselect the channel register so we can read the PHYID
2661 * later.
2662 */
2663 tg3_writephy(tp, 0x10, 0x8011);
2664}
2665
2666static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2667{
82cd3d11 2668 u16 flowctrl;
1da177e4
LT		 2669 u32 sg_dig_ctrl, sg_dig_status;
2670 u32 serdes_cfg, expected_sg_dig_ctrl;
2671 int workaround, port_a;
2672 int current_link_up;
2673
2674 serdes_cfg = 0;
2675 expected_sg_dig_ctrl = 0;
2676 workaround = 0;
2677 port_a = 1;
2678 current_link_up = 0;
2679
2680 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2681 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2682 workaround = 1;
2683 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2684 port_a = 0;
2685
2686 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2687 /* preserve bits 20-23 for voltage regulator */
2688 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2689 }
2690
2691 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2692
2693 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 2694 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 2695 if (workaround) {
2696 u32 val = serdes_cfg;
2697
2698 if (port_a)
2699 val |= 0xc010000;
2700 else
2701 val |= 0x4010000;
2702 tw32_f(MAC_SERDES_CFG, val);
2703 }
c98f6e3b
MC		 2704
2705 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 2706 }
2707 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2708 tg3_setup_flow_control(tp, 0, 0);
2709 current_link_up = 1;
2710 }
2711 goto out;
2712 }
2713
2714 /* Want auto-negotiation. */
c98f6e3b 2715 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 2716
82cd3d11
MC		 2717 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2718 if (flowctrl & ADVERTISE_1000XPAUSE)
2719 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
2720 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2721 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 2722
2723 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 2724 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2725 tp->serdes_counter &&
2726 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2727 MAC_STATUS_RCVD_CFG)) ==
2728 MAC_STATUS_PCS_SYNCED)) {
2729 tp->serdes_counter--;
2730 current_link_up = 1;
2731 goto out;
2732 }
2733restart_autoneg:
1da177e4
LT		 2734 if (workaround)
2735 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 2736 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 2737 udelay(5);
2738 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2739
3d3ebe74
MC		 2740 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2741 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2742 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2743 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 2744 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 2745 mac_status = tr32(MAC_STATUS);
2746
c98f6e3b 2747 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 2748 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 2749 u32 local_adv = 0, remote_adv = 0;
2750
2751 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
2752 local_adv |= ADVERTISE_1000XPAUSE;
2753 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
2754 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 2755
c98f6e3b 2756 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 2757 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 2758 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 2759 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 2760
2761 tg3_setup_flow_control(tp, local_adv, remote_adv);
2762 current_link_up = 1;
3d3ebe74
MC		 2763 tp->serdes_counter = 0;
2764 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 2765 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 2766 if (tp->serdes_counter)
2767 tp->serdes_counter--;
1da177e4
LT		 2768 else {
2769 if (workaround) {
2770 u32 val = serdes_cfg;
2771
2772 if (port_a)
2773 val |= 0xc010000;
2774 else
2775 val |= 0x4010000;
2776
2777 tw32_f(MAC_SERDES_CFG, val);
2778 }
2779
c98f6e3b 2780 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 2781 udelay(40);
2782
2783 /* Link parallel detection - link is up */
2784 /* only if we have PCS_SYNC and not */
2785 /* receiving config code words */
2786 mac_status = tr32(MAC_STATUS);
2787 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2788 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2789 tg3_setup_flow_control(tp, 0, 0);
2790 current_link_up = 1;
3d3ebe74
MC		 2791 tp->tg3_flags2 |=
2792 TG3_FLG2_PARALLEL_DETECT;
2793 tp->serdes_counter =
2794 SERDES_PARALLEL_DET_TIMEOUT;
2795 } else
2796 goto restart_autoneg;
1da177e4
LT		 2797 }
2798 }
3d3ebe74
MC		 2799 } else {
2800 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2801 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2802 }
2803
2804out:
2805 return current_link_up;
2806}
2807
2808static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2809{
2810 int current_link_up = 0;
2811
5cf64b8a 2812 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 2813 goto out;
1da177e4
LT		 2814
2815 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 2816 u32 txflags, rxflags;
1da177e4 2817 int i;
6aa20a22 2818
5be73b47
MC		 2819 if (fiber_autoneg(tp, &txflags, &rxflags)) {
2820 u32 local_adv = 0, remote_adv = 0;
1da177e4 2821
5be73b47
MC		 2822 if (txflags & ANEG_CFG_PS1)
2823 local_adv |= ADVERTISE_1000XPAUSE;
2824 if (txflags & ANEG_CFG_PS2)
2825 local_adv |= ADVERTISE_1000XPSE_ASYM;
2826
2827 if (rxflags & MR_LP_ADV_SYM_PAUSE)
2828 remote_adv |= LPA_1000XPAUSE;
2829 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
2830 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 2831
2832 tg3_setup_flow_control(tp, local_adv, remote_adv);
2833
1da177e4
LT		 2834 current_link_up = 1;
2835 }
2836 for (i = 0; i < 30; i++) {
2837 udelay(20);
2838 tw32_f(MAC_STATUS,
2839 (MAC_STATUS_SYNC_CHANGED |
2840 MAC_STATUS_CFG_CHANGED));
2841 udelay(40);
2842 if ((tr32(MAC_STATUS) &
2843 (MAC_STATUS_SYNC_CHANGED |
2844 MAC_STATUS_CFG_CHANGED)) == 0)
2845 break;
2846 }
2847
2848 mac_status = tr32(MAC_STATUS);
2849 if (current_link_up == 0 &&
2850 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2851 !(mac_status & MAC_STATUS_RCVD_CFG))
2852 current_link_up = 1;
2853 } else {
5be73b47
MC		 2854 tg3_setup_flow_control(tp, 0, 0);
2855
1da177e4
LT		 2856 /* Forcing 1000FD link up. */
2857 current_link_up = 1;
1da177e4
LT		 2858
2859 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2860 udelay(40);
e8f3f6ca
MC		 2861
2862 tw32_f(MAC_MODE, tp->mac_mode);
2863 udelay(40);
1da177e4
LT		 2864 }
2865
2866out:
2867 return current_link_up;
2868}
2869
2870static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2871{
2872 u32 orig_pause_cfg;
2873 u16 orig_active_speed;
2874 u8 orig_active_duplex;
2875 u32 mac_status;
2876 int current_link_up;
2877 int i;
2878
8d018621 2879 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 2880 orig_active_speed = tp->link_config.active_speed;
2881 orig_active_duplex = tp->link_config.active_duplex;
2882
2883 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2884 netif_carrier_ok(tp->dev) &&
2885 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2886 mac_status = tr32(MAC_STATUS);
2887 mac_status &= (MAC_STATUS_PCS_SYNCED |
2888 MAC_STATUS_SIGNAL_DET |
2889 MAC_STATUS_CFG_CHANGED |
2890 MAC_STATUS_RCVD_CFG);
2891 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2892 MAC_STATUS_SIGNAL_DET)) {
2893 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2894 MAC_STATUS_CFG_CHANGED));
2895 return 0;
2896 }
2897 }
2898
2899 tw32_f(MAC_TX_AUTO_NEG, 0);
2900
2901 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2902 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2903 tw32_f(MAC_MODE, tp->mac_mode);
2904 udelay(40);
2905
2906 if (tp->phy_id == PHY_ID_BCM8002)
2907 tg3_init_bcm8002(tp);
2908
2909 /* Enable link change event even when serdes polling. */
2910 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2911 udelay(40);
2912
2913 current_link_up = 0;
2914 mac_status = tr32(MAC_STATUS);
2915
2916 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2917 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2918 else
2919 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2920
1da177e4
LT		 2921 tp->hw_status->status =
2922 (SD_STATUS_UPDATED |
2923 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2924
2925 for (i = 0; i < 100; i++) {
2926 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2927 MAC_STATUS_CFG_CHANGED));
2928 udelay(5);
2929 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 2930 MAC_STATUS_CFG_CHANGED |
2931 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 2932 break;
2933 }
2934
2935 mac_status = tr32(MAC_STATUS);
2936 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2937 current_link_up = 0;
3d3ebe74
MC		 2938 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2939 tp->serdes_counter == 0) {
1da177e4
LT		 2940 tw32_f(MAC_MODE, (tp->mac_mode |
2941 MAC_MODE_SEND_CONFIGS));
2942 udelay(1);
2943 tw32_f(MAC_MODE, tp->mac_mode);
2944 }
2945 }
2946
2947 if (current_link_up == 1) {
2948 tp->link_config.active_speed = SPEED_1000;
2949 tp->link_config.active_duplex = DUPLEX_FULL;
2950 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2951 LED_CTRL_LNKLED_OVERRIDE |
2952 LED_CTRL_1000MBPS_ON));
2953 } else {
2954 tp->link_config.active_speed = SPEED_INVALID;
2955 tp->link_config.active_duplex = DUPLEX_INVALID;
2956 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2957 LED_CTRL_LNKLED_OVERRIDE |
2958 LED_CTRL_TRAFFIC_OVERRIDE));
2959 }
2960
2961 if (current_link_up != netif_carrier_ok(tp->dev)) {
2962 if (current_link_up)
2963 netif_carrier_on(tp->dev);
2964 else
2965 netif_carrier_off(tp->dev);
2966 tg3_link_report(tp);
2967 } else {
8d018621 2968 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 2969 if (orig_pause_cfg != now_pause_cfg ||
2970 orig_active_speed != tp->link_config.active_speed ||
2971 orig_active_duplex != tp->link_config.active_duplex)
2972 tg3_link_report(tp);
2973 }
2974
2975 return 0;
2976}
2977
747e8f8b
MC		 2978static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2979{
2980 int current_link_up, err = 0;
2981 u32 bmsr, bmcr;
2982 u16 current_speed;
2983 u8 current_duplex;
2984
2985 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2986 tw32_f(MAC_MODE, tp->mac_mode);
2987 udelay(40);
2988
2989 tw32(MAC_EVENT, 0);
2990
2991 tw32_f(MAC_STATUS,
2992 (MAC_STATUS_SYNC_CHANGED |
2993 MAC_STATUS_CFG_CHANGED |
2994 MAC_STATUS_MI_COMPLETION |
2995 MAC_STATUS_LNKSTATE_CHANGED));
2996 udelay(40);
2997
2998 if (force_reset)
2999 tg3_phy_reset(tp);
3000
3001 current_link_up = 0;
3002 current_speed = SPEED_INVALID;
3003 current_duplex = DUPLEX_INVALID;
3004
3005 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3006 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3008 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3009 bmsr |= BMSR_LSTATUS;
3010 else
3011 bmsr &= ~BMSR_LSTATUS;
3012 }
747e8f8b
MC		 3013
3014 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3015
3016 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3017 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3018 /* do nothing, just check for link up at the end */
3019 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3020 u32 adv, new_adv;
3021
3022 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3023 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3024 ADVERTISE_1000XPAUSE |
3025 ADVERTISE_1000XPSE_ASYM |
3026 ADVERTISE_SLCT);
3027
ba4d07a8 3028 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 3029
3030 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3031 new_adv |= ADVERTISE_1000XHALF;
3032 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3033 new_adv |= ADVERTISE_1000XFULL;
3034
3035 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3036 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3037 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3038 tg3_writephy(tp, MII_BMCR, bmcr);
3039
3040 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 3041 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 3042 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3043
3044 return err;
3045 }
3046 } else {
3047 u32 new_bmcr;
3048
3049 bmcr &= ~BMCR_SPEED1000;
3050 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3051
3052 if (tp->link_config.duplex == DUPLEX_FULL)
3053 new_bmcr |= BMCR_FULLDPLX;
3054
3055 if (new_bmcr != bmcr) {
3056 /* BMCR_SPEED1000 is a reserved bit that needs
3057 * to be set on write.
3058 */
3059 new_bmcr |= BMCR_SPEED1000;
3060
3061 /* Force a linkdown */
3062 if (netif_carrier_ok(tp->dev)) {
3063 u32 adv;
3064
3065 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3066 adv &= ~(ADVERTISE_1000XFULL |
3067 ADVERTISE_1000XHALF |
3068 ADVERTISE_SLCT);
3069 tg3_writephy(tp, MII_ADVERTISE, adv);
3070 tg3_writephy(tp, MII_BMCR, bmcr |
3071 BMCR_ANRESTART |
3072 BMCR_ANENABLE);
3073 udelay(10);
3074 netif_carrier_off(tp->dev);
3075 }
3076 tg3_writephy(tp, MII_BMCR, new_bmcr);
3077 bmcr = new_bmcr;
3078 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3079 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3080 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3081 ASIC_REV_5714) {
3082 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3083 bmsr |= BMSR_LSTATUS;
3084 else
3085 bmsr &= ~BMSR_LSTATUS;
3086 }
747e8f8b
MC		 3087 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3088 }
3089 }
3090
3091 if (bmsr & BMSR_LSTATUS) {
3092 current_speed = SPEED_1000;
3093 current_link_up = 1;
3094 if (bmcr & BMCR_FULLDPLX)
3095 current_duplex = DUPLEX_FULL;
3096 else
3097 current_duplex = DUPLEX_HALF;
3098
3099 if (bmcr & BMCR_ANENABLE) {
3100 u32 local_adv, remote_adv, common;
3101
3102 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3103 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3104 common = local_adv & remote_adv;
3105 if (common & (ADVERTISE_1000XHALF |
3106 ADVERTISE_1000XFULL)) {
3107 if (common & ADVERTISE_1000XFULL)
3108 current_duplex = DUPLEX_FULL;
3109 else
3110 current_duplex = DUPLEX_HALF;
3111
3112 tg3_setup_flow_control(tp, local_adv,
3113 remote_adv);
3114 }
3115 else
3116 current_link_up = 0;
3117 }
3118 }
3119
3120 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3121 if (tp->link_config.active_duplex == DUPLEX_HALF)
3122 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3123
3124 tw32_f(MAC_MODE, tp->mac_mode);
3125 udelay(40);
3126
3127 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3128
3129 tp->link_config.active_speed = current_speed;
3130 tp->link_config.active_duplex = current_duplex;
3131
3132 if (current_link_up != netif_carrier_ok(tp->dev)) {
3133 if (current_link_up)
3134 netif_carrier_on(tp->dev);
3135 else {
3136 netif_carrier_off(tp->dev);
3137 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3138 }
3139 tg3_link_report(tp);
3140 }
3141 return err;
3142}
3143
3144static void tg3_serdes_parallel_detect(struct tg3 *tp)
3145{
3d3ebe74 3146 if (tp->serdes_counter) {
747e8f8b 3147 /* Give autoneg time to complete. */
3d3ebe74 3148 tp->serdes_counter--;
747e8f8b
MC		 3149 return;
3150 }
3151 if (!netif_carrier_ok(tp->dev) &&
3152 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3153 u32 bmcr;
3154
3155 tg3_readphy(tp, MII_BMCR, &bmcr);
3156 if (bmcr & BMCR_ANENABLE) {
3157 u32 phy1, phy2;
3158
3159 /* Select shadow register 0x1f */
3160 tg3_writephy(tp, 0x1c, 0x7c00);
3161 tg3_readphy(tp, 0x1c, &phy1);
3162
3163 /* Select expansion interrupt status register */
3164 tg3_writephy(tp, 0x17, 0x0f01);
3165 tg3_readphy(tp, 0x15, &phy2);
3166 tg3_readphy(tp, 0x15, &phy2);
3167
3168 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3169 /* We have signal detect and not receiving
3170 * config code words, link is up by parallel
3171 * detection.
3172 */
3173
3174 bmcr &= ~BMCR_ANENABLE;
3175 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3176 tg3_writephy(tp, MII_BMCR, bmcr);
3177 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3178 }
3179 }
3180 }
3181 else if (netif_carrier_ok(tp->dev) &&
3182 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3183 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3184 u32 phy2;
3185
3186 /* Select expansion interrupt status register */
3187 tg3_writephy(tp, 0x17, 0x0f01);
3188 tg3_readphy(tp, 0x15, &phy2);
3189 if (phy2 & 0x20) {
3190 u32 bmcr;
3191
3192 /* Config code words received, turn on autoneg. */
3193 tg3_readphy(tp, MII_BMCR, &bmcr);
3194 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3195
3196 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3197
3198 }
3199 }
3200}
3201
1da177e4
LT		 3202static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3203{
3204 int err;
3205
3206 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3207 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 3208 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3209 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 3210 } else {
3211 err = tg3_setup_copper_phy(tp, force_reset);
3212 }
3213
b5af7126
MC		 3214 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3215 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
aa6c91fe
MC		 3216 u32 val, scale;
3217
3218 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3219 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3220 scale = 65;
3221 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3222 scale = 6;
3223 else
3224 scale = 12;
3225
3226 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3227 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3228 tw32(GRC_MISC_CFG, val);
3229 }
3230
1da177e4
LT		 3231 if (tp->link_config.active_speed == SPEED_1000 &&
3232 tp->link_config.active_duplex == DUPLEX_HALF)
3233 tw32(MAC_TX_LENGTHS,
3234 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3235 (6 << TX_LENGTHS_IPG_SHIFT) |
3236 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3237 else
3238 tw32(MAC_TX_LENGTHS,
3239 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3240 (6 << TX_LENGTHS_IPG_SHIFT) |
3241 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3242
3243 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3244 if (netif_carrier_ok(tp->dev)) {
3245 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3246 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3247 } else {
3248 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3249 }
3250 }
3251
8ed5d97e
MC		 3252 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3253 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3254 if (!netif_carrier_ok(tp->dev))
3255 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3256 tp->pwrmgmt_thresh;
3257 else
3258 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3259 tw32(PCIE_PWR_MGMT_THRESH, val);
3260 }
3261
1da177e4
LT		 3262 return err;
3263}
3264
df3e6548
MC		 3265/* This is called whenever we suspect that the system chipset is re-
3266 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3267 * is bogus tx completions. We try to recover by setting the
3268 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3269 * in the workqueue.
3270 */
3271static void tg3_tx_recover(struct tg3 *tp)
3272{
3273 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3274 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3275
3276 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3277 "mapped I/O cycles to the network device, attempting to "
3278 "recover. Please report the problem to the driver maintainer "
3279 "and include system chipset information.\n", tp->dev->name);
3280
3281 spin_lock(&tp->lock);
df3e6548 3282 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 3283 spin_unlock(&tp->lock);
3284}
3285
1b2a7205
MC		 3286static inline u32 tg3_tx_avail(struct tg3 *tp)
3287{
3288 smp_mb();
3289 return (tp->tx_pending -
3290 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3291}
3292
1da177e4
LT		 3293/* Tigon3 never reports partial packet sends. So we do not
3294 * need special logic to handle SKBs that have not had all
3295 * of their frags sent yet, like SunGEM does.
3296 */
3297static void tg3_tx(struct tg3 *tp)
3298{
3299 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3300 u32 sw_idx = tp->tx_cons;
3301
3302 while (sw_idx != hw_idx) {
3303 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3304 struct sk_buff *skb = ri->skb;
df3e6548
MC		 3305 int i, tx_bug = 0;
3306
3307 if (unlikely(skb == NULL)) {
3308 tg3_tx_recover(tp);
3309 return;
3310 }
1da177e4 3311
1da177e4
LT		 3312 pci_unmap_single(tp->pdev,
3313 pci_unmap_addr(ri, mapping),
3314 skb_headlen(skb),
3315 PCI_DMA_TODEVICE);
3316
3317 ri->skb = NULL;
3318
3319 sw_idx = NEXT_TX(sw_idx);
3320
3321 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 3322 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 3323 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3324 tx_bug = 1;
1da177e4
LT		 3325
3326 pci_unmap_page(tp->pdev,
3327 pci_unmap_addr(ri, mapping),
3328 skb_shinfo(skb)->frags[i].size,
3329 PCI_DMA_TODEVICE);
3330
3331 sw_idx = NEXT_TX(sw_idx);
3332 }
3333
f47c11ee 3334 dev_kfree_skb(skb);
df3e6548
MC		 3335
3336 if (unlikely(tx_bug)) {
3337 tg3_tx_recover(tp);
3338 return;
3339 }
1da177e4
LT		 3340 }
3341
3342 tp->tx_cons = sw_idx;
3343
1b2a7205
MC		 3344 /* Need to make the tx_cons update visible to tg3_start_xmit()
3345 * before checking for netif_queue_stopped(). Without the
3346 * memory barrier, there is a small possibility that tg3_start_xmit()
3347 * will miss it and cause the queue to be stopped forever.
3348 */
3349 smp_mb();
3350
3351 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 3352 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 3353 netif_tx_lock(tp->dev);
51b91468 3354 if (netif_queue_stopped(tp->dev) &&
42952231 3355 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 3356 netif_wake_queue(tp->dev);
1b2a7205 3357 netif_tx_unlock(tp->dev);
51b91468 3358 }
1da177e4
LT		 3359}
3360
3361/* Returns size of skb allocated or < 0 on error.
3362 *
3363 * We only need to fill in the address because the other members
3364 * of the RX descriptor are invariant, see tg3_init_rings.
3365 *
3366 * Note the purposeful assymetry of cpu vs. chip accesses. For
3367 * posting buffers we only dirty the first cache line of the RX
3368 * descriptor (containing the address). Whereas for the RX status
3369 * buffers the cpu only reads the last cacheline of the RX descriptor
3370 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3371 */
3372static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3373 int src_idx, u32 dest_idx_unmasked)
3374{
3375 struct tg3_rx_buffer_desc *desc;
3376 struct ring_info *map, *src_map;
3377 struct sk_buff *skb;
3378 dma_addr_t mapping;
3379 int skb_size, dest_idx;
3380
3381 src_map = NULL;
3382 switch (opaque_key) {
3383 case RXD_OPAQUE_RING_STD:
3384 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3385 desc = &tp->rx_std[dest_idx];
3386 map = &tp->rx_std_buffers[dest_idx];
3387 if (src_idx >= 0)
3388 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 3389 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 3390 break;
3391
3392 case RXD_OPAQUE_RING_JUMBO:
3393 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3394 desc = &tp->rx_jumbo[dest_idx];
3395 map = &tp->rx_jumbo_buffers[dest_idx];
3396 if (src_idx >= 0)
3397 src_map = &tp->rx_jumbo_buffers[src_idx];
3398 skb_size = RX_JUMBO_PKT_BUF_SZ;
3399 break;
3400
3401 default:
3402 return -EINVAL;
3403 };
3404
3405 /* Do not overwrite any of the map or rp information
3406 * until we are sure we can commit to a new buffer.
3407 *
3408 * Callers depend upon this behavior and assume that
3409 * we leave everything unchanged if we fail.
3410 */
a20e9c62 3411 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 3412 if (skb == NULL)
3413 return -ENOMEM;
3414
1da177e4
LT		 3415 skb_reserve(skb, tp->rx_offset);
3416
3417 mapping = pci_map_single(tp->pdev, skb->data,
3418 skb_size - tp->rx_offset,
3419 PCI_DMA_FROMDEVICE);
3420
3421 map->skb = skb;
3422 pci_unmap_addr_set(map, mapping, mapping);
3423
3424 if (src_map != NULL)
3425 src_map->skb = NULL;
3426
3427 desc->addr_hi = ((u64)mapping >> 32);
3428 desc->addr_lo = ((u64)mapping & 0xffffffff);
3429
3430 return skb_size;
3431}
3432
3433/* We only need to move over in the address because the other
3434 * members of the RX descriptor are invariant. See notes above
3435 * tg3_alloc_rx_skb for full details.
3436 */
3437static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3438 int src_idx, u32 dest_idx_unmasked)
3439{
3440 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3441 struct ring_info *src_map, *dest_map;
3442 int dest_idx;
3443
3444 switch (opaque_key) {
3445 case RXD_OPAQUE_RING_STD:
3446 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3447 dest_desc = &tp->rx_std[dest_idx];
3448 dest_map = &tp->rx_std_buffers[dest_idx];
3449 src_desc = &tp->rx_std[src_idx];
3450 src_map = &tp->rx_std_buffers[src_idx];
3451 break;
3452
3453 case RXD_OPAQUE_RING_JUMBO:
3454 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3455 dest_desc = &tp->rx_jumbo[dest_idx];
3456 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3457 src_desc = &tp->rx_jumbo[src_idx];
3458 src_map = &tp->rx_jumbo_buffers[src_idx];
3459 break;
3460
3461 default:
3462 return;
3463 };
3464
3465 dest_map->skb = src_map->skb;
3466 pci_unmap_addr_set(dest_map, mapping,
3467 pci_unmap_addr(src_map, mapping));
3468 dest_desc->addr_hi = src_desc->addr_hi;
3469 dest_desc->addr_lo = src_desc->addr_lo;
3470
3471 src_map->skb = NULL;
3472}
3473
3474#if TG3_VLAN_TAG_USED
3475static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3476{
3477 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3478}
3479#endif
3480
3481/* The RX ring scheme is composed of multiple rings which post fresh
3482 * buffers to the chip, and one special ring the chip uses to report
3483 * status back to the host.
3484 *
3485 * The special ring reports the status of received packets to the
3486 * host. The chip does not write into the original descriptor the
3487 * RX buffer was obtained from. The chip simply takes the original
3488 * descriptor as provided by the host, updates the status and length
3489 * field, then writes this into the next status ring entry.
3490 *
3491 * Each ring the host uses to post buffers to the chip is described
3492 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3493 * it is first placed into the on-chip ram. When the packet's length
3494 * is known, it walks down the TG3_BDINFO entries to select the ring.
3495 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3496 * which is within the range of the new packet's length is chosen.
3497 *
3498 * The "separate ring for rx status" scheme may sound queer, but it makes
3499 * sense from a cache coherency perspective. If only the host writes
3500 * to the buffer post rings, and only the chip writes to the rx status
3501 * rings, then cache lines never move beyond shared-modified state.
3502 * If both the host and chip were to write into the same ring, cache line
3503 * eviction could occur since both entities want it in an exclusive state.
3504 */
3505static int tg3_rx(struct tg3 *tp, int budget)
3506{
f92905de 3507 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 3508 u32 sw_idx = tp->rx_rcb_ptr;
3509 u16 hw_idx;
1da177e4
LT		 3510 int received;
3511
3512 hw_idx = tp->hw_status->idx[0].rx_producer;
3513 /*
3514 * We need to order the read of hw_idx and the read of
3515 * the opaque cookie.
3516 */
3517 rmb();
1da177e4
LT		 3518 work_mask = 0;
3519 received = 0;
3520 while (sw_idx != hw_idx && budget > 0) {
3521 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3522 unsigned int len;
3523 struct sk_buff *skb;
3524 dma_addr_t dma_addr;
3525 u32 opaque_key, desc_idx, *post_ptr;
3526
3527 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3528 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3529 if (opaque_key == RXD_OPAQUE_RING_STD) {
3530 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3531 mapping);
3532 skb = tp->rx_std_buffers[desc_idx].skb;
3533 post_ptr = &tp->rx_std_ptr;
f92905de 3534 rx_std_posted++;
1da177e4
LT		 3535 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3536 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3537 mapping);
3538 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3539 post_ptr = &tp->rx_jumbo_ptr;
3540 }
3541 else {
3542 goto next_pkt_nopost;
3543 }
3544
3545 work_mask |= opaque_key;
3546
3547 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3548 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3549 drop_it:
3550 tg3_recycle_rx(tp, opaque_key,
3551 desc_idx, *post_ptr);
3552 drop_it_no_recycle:
3553 /* Other statistics kept track of by card. */
3554 tp->net_stats.rx_dropped++;
3555 goto next_pkt;
3556 }
3557
3558 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3559
6aa20a22 3560 if (len > RX_COPY_THRESHOLD
1da177e4
LT		 3561 && tp->rx_offset == 2
3562 /* rx_offset != 2 iff this is a 5701 card running
3563 * in PCI-X mode [see tg3_get_invariants()] */
3564 ) {
3565 int skb_size;
3566
3567 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3568 desc_idx, *post_ptr);
3569 if (skb_size < 0)
3570 goto drop_it;
3571
3572 pci_unmap_single(tp->pdev, dma_addr,
3573 skb_size - tp->rx_offset,
3574 PCI_DMA_FROMDEVICE);
3575
3576 skb_put(skb, len);
3577 } else {
3578 struct sk_buff *copy_skb;
3579
3580 tg3_recycle_rx(tp, opaque_key,
3581 desc_idx, *post_ptr);
3582
a20e9c62 3583 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
1da177e4
LT		 3584 if (copy_skb == NULL)
3585 goto drop_it_no_recycle;
3586
1da177e4
LT		 3587 skb_reserve(copy_skb, 2);
3588 skb_put(copy_skb, len);
3589 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 3590 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 3591 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3592
3593 /* We'll reuse the original ring buffer. */
3594 skb = copy_skb;
3595 }
3596
3597 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3598 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3599 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3600 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3601 skb->ip_summed = CHECKSUM_UNNECESSARY;
3602 else
3603 skb->ip_summed = CHECKSUM_NONE;
3604
3605 skb->protocol = eth_type_trans(skb, tp->dev);
3606#if TG3_VLAN_TAG_USED
3607 if (tp->vlgrp != NULL &&
3608 desc->type_flags & RXD_FLAG_VLAN) {
3609 tg3_vlan_rx(tp, skb,
3610 desc->err_vlan & RXD_VLAN_MASK);
3611 } else
3612#endif
3613 netif_receive_skb(skb);
3614
3615 tp->dev->last_rx = jiffies;
3616 received++;
3617 budget--;
3618
3619next_pkt:
3620 (*post_ptr)++;
f92905de
MC		 3621
3622 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3623 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3624
3625 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3626 TG3_64BIT_REG_LOW, idx);
3627 work_mask &= ~RXD_OPAQUE_RING_STD;
3628 rx_std_posted = 0;
3629 }
1da177e4 3630next_pkt_nopost:
483ba50b 3631 sw_idx++;
6b31a515 3632 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 3633
3634 /* Refresh hw_idx to see if there is new work */
3635 if (sw_idx == hw_idx) {
3636 hw_idx = tp->hw_status->idx[0].rx_producer;
3637 rmb();
3638 }
1da177e4
LT		 3639 }
3640
3641 /* ACK the status ring. */
483ba50b
MC		 3642 tp->rx_rcb_ptr = sw_idx;
3643 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3644
3645 /* Refill RX ring(s). */
3646 if (work_mask & RXD_OPAQUE_RING_STD) {
3647 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3648 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3649 sw_idx);
3650 }
3651 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3652 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3653 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3654 sw_idx);
3655 }
3656 mmiowb();
3657
3658 return received;
3659}
3660
6f535763 3661static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 3662{
1da177e4 3663 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 3664
1da177e4
LT		 3665 /* handle link change and other phy events */
3666 if (!(tp->tg3_flags &
3667 (TG3_FLAG_USE_LINKCHG_REG |
3668 TG3_FLAG_POLL_SERDES))) {
3669 if (sblk->status & SD_STATUS_LINK_CHG) {
3670 sblk->status = SD_STATUS_UPDATED |
3671 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3672 spin_lock(&tp->lock);
1da177e4 3673 tg3_setup_phy(tp, 0);
f47c11ee 3674 spin_unlock(&tp->lock);
1da177e4
LT		 3675 }
3676 }
3677
3678 /* run TX completion thread */
3679 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3680 tg3_tx(tp);
6f535763 3681 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 3682 return work_done;
1da177e4
LT		 3683 }
3684
1da177e4
LT		 3685 /* run RX thread, within the bounds set by NAPI.
3686 * All RX "locking" is done by ensuring outside
bea3348e 3687 * code synchronizes with tg3->napi.poll()
1da177e4 3688 */
bea3348e 3689 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 3690 work_done += tg3_rx(tp, budget - work_done);
1da177e4 3691
6f535763
DM		 3692 return work_done;
3693}
3694
3695static int tg3_poll(struct napi_struct *napi, int budget)
3696{
3697 struct tg3 *tp = container_of(napi, struct tg3, napi);
3698 int work_done = 0;
4fd7ab59 3699 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 3700
3701 while (1) {
3702 work_done = tg3_poll_work(tp, work_done, budget);
3703
3704 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3705 goto tx_recovery;
3706
3707 if (unlikely(work_done >= budget))
3708 break;
3709
4fd7ab59
MC		 3710 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3711 /* tp->last_tag is used in tg3_restart_ints() below
3712 * to tell the hw how much work has been processed,
3713 * so we must read it before checking for more work.
3714 */
3715 tp->last_tag = sblk->status_tag;
3716 rmb();
3717 } else
3718 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 3719
4fd7ab59 3720 if (likely(!tg3_has_work(tp))) {
6f535763
DM		 3721 netif_rx_complete(tp->dev, napi);
3722 tg3_restart_ints(tp);
3723 break;
3724 }
1da177e4
LT		 3725 }
3726
bea3348e 3727 return work_done;
6f535763
DM		 3728
3729tx_recovery:
4fd7ab59 3730 /* work_done is guaranteed to be less than budget. */
6f535763
DM		 3731 netif_rx_complete(tp->dev, napi);
3732 schedule_work(&tp->reset_task);
4fd7ab59 3733 return work_done;
1da177e4
LT		 3734}
3735
f47c11ee
DM		 3736static void tg3_irq_quiesce(struct tg3 *tp)
3737{
3738 BUG_ON(tp->irq_sync);
3739
3740 tp->irq_sync = 1;
3741 smp_mb();
3742
3743 synchronize_irq(tp->pdev->irq);
3744}
3745
3746static inline int tg3_irq_sync(struct tg3 *tp)
3747{
3748 return tp->irq_sync;
3749}
3750
3751/* Fully shutdown all tg3 driver activity elsewhere in the system.
3752 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3753 * with as well. Most of the time, this is not necessary except when
3754 * shutting down the device.
3755 */
3756static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3757{
46966545 3758 spin_lock_bh(&tp->lock);
f47c11ee
DM		 3759 if (irq_sync)
3760 tg3_irq_quiesce(tp);
f47c11ee
DM		 3761}
3762
3763static inline void tg3_full_unlock(struct tg3 *tp)
3764{
f47c11ee
DM		 3765 spin_unlock_bh(&tp->lock);
3766}
3767
fcfa0a32
MC		 3768/* One-shot MSI handler - Chip automatically disables interrupt
3769 * after sending MSI so driver doesn't have to do it.
3770 */
7d12e780 3771static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 3772{
3773 struct net_device *dev = dev_id;
3774 struct tg3 *tp = netdev_priv(dev);
3775
3776 prefetch(tp->hw_status);
3777 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3778
3779 if (likely(!tg3_irq_sync(tp)))
bea3348e 3780 netif_rx_schedule(dev, &tp->napi);
fcfa0a32
MC		 3781
3782 return IRQ_HANDLED;
3783}
3784
88b06bc2
MC		 3785/* MSI ISR - No need to check for interrupt sharing and no need to
3786 * flush status block and interrupt mailbox. PCI ordering rules
3787 * guarantee that MSI will arrive after the status block.
3788 */
7d12e780 3789static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 3790{
3791 struct net_device *dev = dev_id;
3792 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3793
61487480
MC		 3794 prefetch(tp->hw_status);
3795 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3796 /*
fac9b83e 3797 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3798 * chip-internal interrupt pending events.
fac9b83e 3799 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3800 * NIC to stop sending us irqs, engaging "in-intr-handler"
3801 * event coalescing.
3802 */
3803 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3804 if (likely(!tg3_irq_sync(tp)))
bea3348e 3805 netif_rx_schedule(dev, &tp->napi);
61487480 3806
88b06bc2
MC		 3807 return IRQ_RETVAL(1);
3808}
3809
7d12e780 3810static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 3811{
3812 struct net_device *dev = dev_id;
3813 struct tg3 *tp = netdev_priv(dev);
3814 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3815 unsigned int handled = 1;
3816
1da177e4
LT		 3817 /* In INTx mode, it is possible for the interrupt to arrive at
3818 * the CPU before the status block posted prior to the interrupt.
3819 * Reading the PCI State register will confirm whether the
3820 * interrupt is ours and will flush the status block.
3821 */
d18edcb2
MC		 3822 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3823 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3824 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3825 handled = 0;
f47c11ee 3826 goto out;
fac9b83e 3827 }
d18edcb2
MC		 3828 }
3829
3830 /*
3831 * Writing any value to intr-mbox-0 clears PCI INTA# and
3832 * chip-internal interrupt pending events.
3833 * Writing non-zero to intr-mbox-0 additional tells the
3834 * NIC to stop sending us irqs, engaging "in-intr-handler"
3835 * event coalescing.
c04cb347
MC		 3836 *
3837 * Flush the mailbox to de-assert the IRQ immediately to prevent
3838 * spurious interrupts. The flush impacts performance but
3839 * excessive spurious interrupts can be worse in some cases.
d18edcb2 3840 */
c04cb347 3841 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 3842 if (tg3_irq_sync(tp))
3843 goto out;
3844 sblk->status &= ~SD_STATUS_UPDATED;
3845 if (likely(tg3_has_work(tp))) {
3846 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
bea3348e 3847 netif_rx_schedule(dev, &tp->napi);
d18edcb2
MC		 3848 } else {
3849 /* No work, shared interrupt perhaps? re-enable
3850 * interrupts, and flush that PCI write
3851 */
3852 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3853 0x00000000);
fac9b83e 3854 }
f47c11ee 3855out:
fac9b83e
DM		 3856 return IRQ_RETVAL(handled);
3857}
3858
7d12e780 3859static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 3860{
3861 struct net_device *dev = dev_id;
3862 struct tg3 *tp = netdev_priv(dev);
3863 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3864 unsigned int handled = 1;
3865
fac9b83e
DM		 3866 /* In INTx mode, it is possible for the interrupt to arrive at
3867 * the CPU before the status block posted prior to the interrupt.
3868 * Reading the PCI State register will confirm whether the
3869 * interrupt is ours and will flush the status block.
3870 */
d18edcb2
MC		 3871 if (unlikely(sblk->status_tag == tp->last_tag)) {
3872 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3873 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3874 handled = 0;
f47c11ee 3875 goto out;
1da177e4 3876 }
d18edcb2
MC		 3877 }
3878
3879 /*
3880 * writing any value to intr-mbox-0 clears PCI INTA# and
3881 * chip-internal interrupt pending events.
3882 * writing non-zero to intr-mbox-0 additional tells the
3883 * NIC to stop sending us irqs, engaging "in-intr-handler"
3884 * event coalescing.
c04cb347
MC		 3885 *
3886 * Flush the mailbox to de-assert the IRQ immediately to prevent
3887 * spurious interrupts. The flush impacts performance but
3888 * excessive spurious interrupts can be worse in some cases.
d18edcb2 3889 */
c04cb347 3890 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 3891 if (tg3_irq_sync(tp))
3892 goto out;
bea3348e 3893 if (netif_rx_schedule_prep(dev, &tp->napi)) {
d18edcb2
MC		 3894 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3895 /* Update last_tag to mark that this status has been
3896 * seen. Because interrupt may be shared, we may be
3897 * racing with tg3_poll(), so only update last_tag
3898 * if tg3_poll() is not scheduled.
3899 */
3900 tp->last_tag = sblk->status_tag;
bea3348e 3901 __netif_rx_schedule(dev, &tp->napi);
1da177e4 3902 }
f47c11ee 3903out:
1da177e4
LT		 3904 return IRQ_RETVAL(handled);
3905}
3906
7938109f 3907/* ISR for interrupt test */
7d12e780 3908static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 3909{
3910 struct net_device *dev = dev_id;
3911 struct tg3 *tp = netdev_priv(dev);
3912 struct tg3_hw_status *sblk = tp->hw_status;
3913
f9804ddb
MC		 3914 if ((sblk->status & SD_STATUS_UPDATED) ||
3915 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 3916 tg3_disable_ints(tp);
7938109f
MC		 3917 return IRQ_RETVAL(1);
3918 }
3919 return IRQ_RETVAL(0);
3920}
3921
8e7a22e3 3922static int tg3_init_hw(struct tg3 *, int);
944d980e 3923static int tg3_halt(struct tg3 *, int, int);
1da177e4 3924
b9ec6c1b
MC		 3925/* Restart hardware after configuration changes, self-test, etc.
3926 * Invoked with tp->lock held.
3927 */
3928static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3929{
3930 int err;
3931
3932 err = tg3_init_hw(tp, reset_phy);
3933 if (err) {
3934 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3935 "aborting.\n", tp->dev->name);
3936 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3937 tg3_full_unlock(tp);
3938 del_timer_sync(&tp->timer);
3939 tp->irq_sync = 0;
bea3348e 3940 napi_enable(&tp->napi);
b9ec6c1b
MC		 3941 dev_close(tp->dev);
3942 tg3_full_lock(tp, 0);
3943 }
3944 return err;
3945}
3946
1da177e4
LT		 3947#ifdef CONFIG_NET_POLL_CONTROLLER
3948static void tg3_poll_controller(struct net_device *dev)
3949{
88b06bc2
MC		 3950 struct tg3 *tp = netdev_priv(dev);
3951
7d12e780 3952 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 3953}
3954#endif
3955
c4028958 3956static void tg3_reset_task(struct work_struct *work)
1da177e4 3957{
c4028958 3958 struct tg3 *tp = container_of(work, struct tg3, reset_task);
1da177e4
LT		 3959 unsigned int restart_timer;
3960
7faa006f 3961 tg3_full_lock(tp, 0);
7faa006f
MC		 3962
3963 if (!netif_running(tp->dev)) {
7faa006f
MC		 3964 tg3_full_unlock(tp);
3965 return;
3966 }
3967
3968 tg3_full_unlock(tp);
3969
1da177e4
LT		 3970 tg3_netif_stop(tp);
3971
f47c11ee 3972 tg3_full_lock(tp, 1);
1da177e4
LT		 3973
3974 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3975 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3976
df3e6548
MC		 3977 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3978 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3979 tp->write32_rx_mbox = tg3_write_flush_reg32;
3980 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3981 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3982 }
3983
944d980e 3984 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b9ec6c1b
MC		 3985 if (tg3_init_hw(tp, 1))
3986 goto out;
1da177e4
LT		 3987
3988 tg3_netif_start(tp);
3989
1da177e4
LT		 3990 if (restart_timer)
3991 mod_timer(&tp->timer, jiffies + 1);
7faa006f 3992
b9ec6c1b 3993out:
7faa006f 3994 tg3_full_unlock(tp);
1da177e4
LT		 3995}
3996
b0408751
MC		 3997static void tg3_dump_short_state(struct tg3 *tp)
3998{
3999 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4000 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4001 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4002 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4003}
4004
1da177e4
LT		 4005static void tg3_tx_timeout(struct net_device *dev)
4006{
4007 struct tg3 *tp = netdev_priv(dev);
4008
b0408751 4009 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 4010 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4011 dev->name);
b0408751
MC		 4012 tg3_dump_short_state(tp);
4013 }
1da177e4
LT		 4014
4015 schedule_work(&tp->reset_task);
4016}
4017
c58ec932
MC		 4018/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4019static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4020{
4021 u32 base = (u32) mapping & 0xffffffff;
4022
4023 return ((base > 0xffffdcc0) &&
4024 (base + len + 8 < base));
4025}
4026
72f2afb8
MC		 4027/* Test for DMA addresses > 40-bit */
4028static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4029 int len)
4030{
4031#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 4032 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 4033 return (((u64) mapping + len) > DMA_40BIT_MASK);
4034 return 0;
4035#else
4036 return 0;
4037#endif
4038}
4039
1da177e4
LT		 4040static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4041
72f2afb8
MC		 4042/* Workaround 4GB and 40-bit hardware DMA bugs. */
4043static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 4044 u32 last_plus_one, u32 *start,
4045 u32 base_flags, u32 mss)
1da177e4
LT		 4046{
4047 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 4048 dma_addr_t new_addr = 0;
1da177e4 4049 u32 entry = *start;
c58ec932 4050 int i, ret = 0;
1da177e4
LT		 4051
4052 if (!new_skb) {
c58ec932
MC		 4053 ret = -1;
4054 } else {
4055 /* New SKB is guaranteed to be linear. */
4056 entry = *start;
4057 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4058 PCI_DMA_TODEVICE);
4059 /* Make sure new skb does not cross any 4G boundaries.
4060 * Drop the packet if it does.
4061 */
4062 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4063 ret = -1;
4064 dev_kfree_skb(new_skb);
4065 new_skb = NULL;
4066 } else {
4067 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4068 base_flags, 1 | (mss << 1));
4069 *start = NEXT_TX(entry);
4070 }
1da177e4
LT		 4071 }
4072
1da177e4
LT		 4073 /* Now clean up the sw ring entries. */
4074 i = 0;
4075 while (entry != last_plus_one) {
4076 int len;
4077
4078 if (i == 0)
4079 len = skb_headlen(skb);
4080 else
4081 len = skb_shinfo(skb)->frags[i-1].size;
4082 pci_unmap_single(tp->pdev,
4083 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4084 len, PCI_DMA_TODEVICE);
4085 if (i == 0) {
4086 tp->tx_buffers[entry].skb = new_skb;
4087 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4088 } else {
4089 tp->tx_buffers[entry].skb = NULL;
4090 }
4091 entry = NEXT_TX(entry);
4092 i++;
4093 }
4094
4095 dev_kfree_skb(skb);
4096
c58ec932 4097 return ret;
1da177e4
LT		 4098}
4099
4100static void tg3_set_txd(struct tg3 *tp, int entry,
4101 dma_addr_t mapping, int len, u32 flags,
4102 u32 mss_and_is_end)
4103{
4104 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4105 int is_end = (mss_and_is_end & 0x1);
4106 u32 mss = (mss_and_is_end >> 1);
4107 u32 vlan_tag = 0;
4108
4109 if (is_end)
4110 flags |= TXD_FLAG_END;
4111 if (flags & TXD_FLAG_VLAN) {
4112 vlan_tag = flags >> 16;
4113 flags &= 0xffff;
4114 }
4115 vlan_tag |= (mss << TXD_MSS_SHIFT);
4116
4117 txd->addr_hi = ((u64) mapping >> 32);
4118 txd->addr_lo = ((u64) mapping & 0xffffffff);
4119 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4120 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4121}
4122
5a6f3074
MC		 4123/* hard_start_xmit for devices that don't have any bugs and
4124 * support TG3_FLG2_HW_TSO_2 only.
4125 */
1da177e4 4126static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 4127{
4128 struct tg3 *tp = netdev_priv(dev);
4129 dma_addr_t mapping;
4130 u32 len, entry, base_flags, mss;
4131
4132 len = skb_headlen(skb);
4133
00b70504 4134 /* We are running in BH disabled context with netif_tx_lock
bea3348e 4135 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 4136 * interrupt. Furthermore, IRQ processing runs lockless so we have
4137 * no IRQ context deadlocks to worry about either. Rejoice!
4138 */
1b2a7205 4139 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 4140 if (!netif_queue_stopped(dev)) {
4141 netif_stop_queue(dev);
4142
4143 /* This is a hard error, log it. */
4144 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4145 "queue awake!\n", dev->name);
4146 }
5a6f3074
MC		 4147 return NETDEV_TX_BUSY;
4148 }
4149
4150 entry = tp->tx_prod;
4151 base_flags = 0;
5a6f3074 4152 mss = 0;
c13e3713 4153 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 4154 int tcp_opt_len, ip_tcp_len;
4155
4156 if (skb_header_cloned(skb) &&
4157 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4158 dev_kfree_skb(skb);
4159 goto out_unlock;
4160 }
4161
b0026624
MC		 4162 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4163 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4164 else {
eddc9ec5
ACM		 4165 struct iphdr *iph = ip_hdr(skb);
4166
ab6a5bb6 4167 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4168 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 4169
eddc9ec5
ACM		 4170 iph->check = 0;
4171 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 4172 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4173 }
5a6f3074
MC		 4174
4175 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4176 TXD_FLAG_CPU_POST_DMA);
4177
aa8223c7 4178 tcp_hdr(skb)->check = 0;
5a6f3074 4179
5a6f3074 4180 }
84fa7933 4181 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 4182 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 4183#if TG3_VLAN_TAG_USED
4184 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4185 base_flags |= (TXD_FLAG_VLAN |
4186 (vlan_tx_tag_get(skb) << 16));
4187#endif
4188
4189 /* Queue skb data, a.k.a. the main skb fragment. */
4190 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4191
4192 tp->tx_buffers[entry].skb = skb;
4193 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4194
4195 tg3_set_txd(tp, entry, mapping, len, base_flags,
4196 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4197
4198 entry = NEXT_TX(entry);
4199
4200 /* Now loop through additional data fragments, and queue them. */
4201 if (skb_shinfo(skb)->nr_frags > 0) {
4202 unsigned int i, last;
4203
4204 last = skb_shinfo(skb)->nr_frags - 1;
4205 for (i = 0; i <= last; i++) {
4206 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4207
4208 len = frag->size;
4209 mapping = pci_map_page(tp->pdev,
4210 frag->page,
4211 frag->page_offset,
4212 len, PCI_DMA_TODEVICE);
4213
4214 tp->tx_buffers[entry].skb = NULL;
4215 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4216
4217 tg3_set_txd(tp, entry, mapping, len,
4218 base_flags, (i == last) | (mss << 1));
4219
4220 entry = NEXT_TX(entry);
4221 }
4222 }
4223
4224 /* Packets are ready, update Tx producer idx local and on card. */
4225 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4226
4227 tp->tx_prod = entry;
1b2a7205 4228 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 4229 netif_stop_queue(dev);
42952231 4230 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 4231 netif_wake_queue(tp->dev);
4232 }
4233
4234out_unlock:
4235 mmiowb();
5a6f3074
MC		 4236
4237 dev->trans_start = jiffies;
4238
4239 return NETDEV_TX_OK;
4240}
4241
52c0fd83
MC		 4242static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4243
4244/* Use GSO to workaround a rare TSO bug that may be triggered when the
4245 * TSO header is greater than 80 bytes.
4246 */
4247static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4248{
4249 struct sk_buff *segs, *nskb;
4250
4251 /* Estimate the number of fragments in the worst case */
1b2a7205 4252 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 4253 netif_stop_queue(tp->dev);
7f62ad5d
MC		 4254 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4255 return NETDEV_TX_BUSY;
4256
4257 netif_wake_queue(tp->dev);
52c0fd83
MC		 4258 }
4259
4260 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4261 if (unlikely(IS_ERR(segs)))
4262 goto tg3_tso_bug_end;
4263
4264 do {
4265 nskb = segs;
4266 segs = segs->next;
4267 nskb->next = NULL;
4268 tg3_start_xmit_dma_bug(nskb, tp->dev);
4269 } while (segs);
4270
4271tg3_tso_bug_end:
4272 dev_kfree_skb(skb);
4273
4274 return NETDEV_TX_OK;
4275}
52c0fd83 4276
5a6f3074
MC		 4277/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4278 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4279 */
4280static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 4281{
4282 struct tg3 *tp = netdev_priv(dev);
4283 dma_addr_t mapping;
1da177e4
LT		 4284 u32 len, entry, base_flags, mss;
4285 int would_hit_hwbug;
1da177e4
LT		 4286
4287 len = skb_headlen(skb);
4288
00b70504 4289 /* We are running in BH disabled context with netif_tx_lock
bea3348e 4290 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 4291 * interrupt. Furthermore, IRQ processing runs lockless so we have
4292 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 4293 */
1b2a7205 4294 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 4295 if (!netif_queue_stopped(dev)) {
4296 netif_stop_queue(dev);
4297
4298 /* This is a hard error, log it. */
4299 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4300 "queue awake!\n", dev->name);
4301 }
1da177e4
LT		 4302 return NETDEV_TX_BUSY;
4303 }
4304
4305 entry = tp->tx_prod;
4306 base_flags = 0;
84fa7933 4307 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 4308 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 4309 mss = 0;
c13e3713 4310 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 4311 struct iphdr *iph;
52c0fd83 4312 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 4313
4314 if (skb_header_cloned(skb) &&
4315 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4316 dev_kfree_skb(skb);
4317 goto out_unlock;
4318 }
4319
ab6a5bb6 4320 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4321 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 4322
52c0fd83
MC		 4323 hdr_len = ip_tcp_len + tcp_opt_len;
4324 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 4325 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 4326 return (tg3_tso_bug(tp, skb));
4327
1da177e4
LT		 4328 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4329 TXD_FLAG_CPU_POST_DMA);
4330
eddc9ec5
ACM		 4331 iph = ip_hdr(skb);
4332 iph->check = 0;
4333 iph->tot_len = htons(mss + hdr_len);
1da177e4 4334 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 4335 tcp_hdr(skb)->check = 0;
1da177e4 4336 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 4337 } else
4338 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4339 iph->daddr, 0,
4340 IPPROTO_TCP,
4341 0);
1da177e4
LT		 4342
4343 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4344 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 4345 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4346 int tsflags;
4347
eddc9ec5 4348 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4349 mss |= (tsflags << 11);
4350 }
4351 } else {
eddc9ec5 4352 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4353 int tsflags;
4354
eddc9ec5 4355 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4356 base_flags |= tsflags << 12;
4357 }
4358 }
4359 }
1da177e4
LT		 4360#if TG3_VLAN_TAG_USED
4361 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4362 base_flags |= (TXD_FLAG_VLAN |
4363 (vlan_tx_tag_get(skb) << 16));
4364#endif
4365
4366 /* Queue skb data, a.k.a. the main skb fragment. */
4367 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4368
4369 tp->tx_buffers[entry].skb = skb;
4370 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4371
4372 would_hit_hwbug = 0;
4373
4374 if (tg3_4g_overflow_test(mapping, len))
c58ec932 4375 would_hit_hwbug = 1;
1da177e4
LT		 4376
4377 tg3_set_txd(tp, entry, mapping, len, base_flags,
4378 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4379
4380 entry = NEXT_TX(entry);
4381
4382 /* Now loop through additional data fragments, and queue them. */
4383 if (skb_shinfo(skb)->nr_frags > 0) {
4384 unsigned int i, last;
4385
4386 last = skb_shinfo(skb)->nr_frags - 1;
4387 for (i = 0; i <= last; i++) {
4388 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4389
4390 len = frag->size;
4391 mapping = pci_map_page(tp->pdev,
4392 frag->page,
4393 frag->page_offset,
4394 len, PCI_DMA_TODEVICE);
4395
4396 tp->tx_buffers[entry].skb = NULL;
4397 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4398
c58ec932
MC		 4399 if (tg3_4g_overflow_test(mapping, len))
4400 would_hit_hwbug = 1;
1da177e4 4401
72f2afb8
MC		 4402 if (tg3_40bit_overflow_test(tp, mapping, len))
4403 would_hit_hwbug = 1;
4404
1da177e4
LT		 4405 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4406 tg3_set_txd(tp, entry, mapping, len,
4407 base_flags, (i == last)|(mss << 1));
4408 else
4409 tg3_set_txd(tp, entry, mapping, len,
4410 base_flags, (i == last));
4411
4412 entry = NEXT_TX(entry);
4413 }
4414 }
4415
4416 if (would_hit_hwbug) {
4417 u32 last_plus_one = entry;
4418 u32 start;
1da177e4 4419
c58ec932
MC		 4420 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4421 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 4422
4423 /* If the workaround fails due to memory/mapping
4424 * failure, silently drop this packet.
4425 */
72f2afb8 4426 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 4427 &start, base_flags, mss))
1da177e4
LT		 4428 goto out_unlock;
4429
4430 entry = start;
4431 }
4432
4433 /* Packets are ready, update Tx producer idx local and on card. */
4434 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4435
4436 tp->tx_prod = entry;
1b2a7205 4437 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 4438 netif_stop_queue(dev);
42952231 4439 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 4440 netif_wake_queue(tp->dev);
4441 }
1da177e4
LT		 4442
4443out_unlock:
4444 mmiowb();
1da177e4
LT		 4445
4446 dev->trans_start = jiffies;
4447
4448 return NETDEV_TX_OK;
4449}
4450
4451static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4452 int new_mtu)
4453{
4454 dev->mtu = new_mtu;
4455
ef7f5ec0 4456 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 4457 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 4458 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4459 ethtool_op_set_tso(dev, 0);
4460 }
4461 else
4462 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4463 } else {
a4e2b347 4464 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 4465 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 4466 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 4467 }
1da177e4
LT		 4468}
4469
4470static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4471{
4472 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 4473 int err;
1da177e4
LT		 4474
4475 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4476 return -EINVAL;
4477
4478 if (!netif_running(dev)) {
4479 /* We'll just catch it later when the
4480 * device is up'd.
4481 */
4482 tg3_set_mtu(dev, tp, new_mtu);
4483 return 0;
4484 }
4485
4486 tg3_netif_stop(tp);
f47c11ee
DM		 4487
4488 tg3_full_lock(tp, 1);
1da177e4 4489
944d980e 4490 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 4491
4492 tg3_set_mtu(dev, tp, new_mtu);
4493
b9ec6c1b 4494 err = tg3_restart_hw(tp, 0);
1da177e4 4495
b9ec6c1b
MC		 4496 if (!err)
4497 tg3_netif_start(tp);
1da177e4 4498
f47c11ee 4499 tg3_full_unlock(tp);
1da177e4 4500
b9ec6c1b 4501 return err;
1da177e4
LT		 4502}
4503
4504/* Free up pending packets in all rx/tx rings.
4505 *
4506 * The chip has been shut down and the driver detached from
4507 * the networking, so no interrupts or new tx packets will
4508 * end up in the driver. tp->{tx,}lock is not held and we are not
4509 * in an interrupt context and thus may sleep.
4510 */
4511static void tg3_free_rings(struct tg3 *tp)
4512{
4513 struct ring_info *rxp;
4514 int i;
4515
4516 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4517 rxp = &tp->rx_std_buffers[i];
4518
4519 if (rxp->skb == NULL)
4520 continue;
4521 pci_unmap_single(tp->pdev,
4522 pci_unmap_addr(rxp, mapping),
7e72aad4 4523 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 4524 PCI_DMA_FROMDEVICE);
4525 dev_kfree_skb_any(rxp->skb);
4526 rxp->skb = NULL;
4527 }
4528
4529 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4530 rxp = &tp->rx_jumbo_buffers[i];
4531
4532 if (rxp->skb == NULL)
4533 continue;
4534 pci_unmap_single(tp->pdev,
4535 pci_unmap_addr(rxp, mapping),
4536 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4537 PCI_DMA_FROMDEVICE);
4538 dev_kfree_skb_any(rxp->skb);
4539 rxp->skb = NULL;
4540 }
4541
4542 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4543 struct tx_ring_info *txp;
4544 struct sk_buff *skb;
4545 int j;
4546
4547 txp = &tp->tx_buffers[i];
4548 skb = txp->skb;
4549
4550 if (skb == NULL) {
4551 i++;
4552 continue;
4553 }
4554
4555 pci_unmap_single(tp->pdev,
4556 pci_unmap_addr(txp, mapping),
4557 skb_headlen(skb),
4558 PCI_DMA_TODEVICE);
4559 txp->skb = NULL;
4560
4561 i++;
4562
4563 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4564 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4565 pci_unmap_page(tp->pdev,
4566 pci_unmap_addr(txp, mapping),
4567 skb_shinfo(skb)->frags[j].size,
4568 PCI_DMA_TODEVICE);
4569 i++;
4570 }
4571
4572 dev_kfree_skb_any(skb);
4573 }
4574}
4575
4576/* Initialize tx/rx rings for packet processing.
4577 *
4578 * The chip has been shut down and the driver detached from
4579 * the networking, so no interrupts or new tx packets will
4580 * end up in the driver. tp->{tx,}lock are held and thus
4581 * we may not sleep.
4582 */
32d8c572 4583static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 4584{
4585 u32 i;
4586
4587 /* Free up all the SKBs. */
4588 tg3_free_rings(tp);
4589
4590 /* Zero out all descriptors. */
4591 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4592 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4593 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4594 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4595
7e72aad4 4596 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 4597 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 4598 (tp->dev->mtu > ETH_DATA_LEN))
4599 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4600
1da177e4
LT		 4601 /* Initialize invariants of the rings, we only set this
4602 * stuff once. This works because the card does not
4603 * write into the rx buffer posting rings.
4604 */
4605 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4606 struct tg3_rx_buffer_desc *rxd;
4607
4608 rxd = &tp->rx_std[i];
7e72aad4 4609 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 4610 << RXD_LEN_SHIFT;
4611 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4612 rxd->opaque = (RXD_OPAQUE_RING_STD |
4613 (i << RXD_OPAQUE_INDEX_SHIFT));
4614 }
4615
0f893dc6 4616 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4617 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4618 struct tg3_rx_buffer_desc *rxd;
4619
4620 rxd = &tp->rx_jumbo[i];
4621 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4622 << RXD_LEN_SHIFT;
4623 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4624 RXD_FLAG_JUMBO;
4625 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4626 (i << RXD_OPAQUE_INDEX_SHIFT));
4627 }
4628 }
4629
4630 /* Now allocate fresh SKBs for each rx ring. */
4631 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 4632 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4633 printk(KERN_WARNING PFX
4634 "%s: Using a smaller RX standard ring, "
4635 "only %d out of %d buffers were allocated "
4636 "successfully.\n",
4637 tp->dev->name, i, tp->rx_pending);
4638 if (i == 0)
4639 return -ENOMEM;
4640 tp->rx_pending = i;
1da177e4 4641 break;
32d8c572 4642 }
1da177e4
LT		 4643 }
4644
0f893dc6 4645 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4646 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4647 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 4648 -1, i) < 0) {
4649 printk(KERN_WARNING PFX
4650 "%s: Using a smaller RX jumbo ring, "
4651 "only %d out of %d buffers were "
4652 "allocated successfully.\n",
4653 tp->dev->name, i, tp->rx_jumbo_pending);
4654 if (i == 0) {
4655 tg3_free_rings(tp);
4656 return -ENOMEM;
4657 }
4658 tp->rx_jumbo_pending = i;
1da177e4 4659 break;
32d8c572 4660 }
1da177e4
LT		 4661 }
4662 }
32d8c572 4663 return 0;
1da177e4
LT		 4664}
4665
4666/*
4667 * Must not be invoked with interrupt sources disabled and
4668 * the hardware shutdown down.
4669 */
4670static void tg3_free_consistent(struct tg3 *tp)
4671{
b4558ea9
JJ		 4672 kfree(tp->rx_std_buffers);
4673 tp->rx_std_buffers = NULL;
1da177e4
LT		 4674 if (tp->rx_std) {
4675 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4676 tp->rx_std, tp->rx_std_mapping);
4677 tp->rx_std = NULL;
4678 }
4679 if (tp->rx_jumbo) {
4680 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4681 tp->rx_jumbo, tp->rx_jumbo_mapping);
4682 tp->rx_jumbo = NULL;
4683 }
4684 if (tp->rx_rcb) {
4685 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4686 tp->rx_rcb, tp->rx_rcb_mapping);
4687 tp->rx_rcb = NULL;
4688 }
4689 if (tp->tx_ring) {
4690 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4691 tp->tx_ring, tp->tx_desc_mapping);
4692 tp->tx_ring = NULL;
4693 }
4694 if (tp->hw_status) {
4695 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4696 tp->hw_status, tp->status_mapping);
4697 tp->hw_status = NULL;
4698 }
4699 if (tp->hw_stats) {
4700 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4701 tp->hw_stats, tp->stats_mapping);
4702 tp->hw_stats = NULL;
4703 }
4704}
4705
4706/*
4707 * Must not be invoked with interrupt sources disabled and
4708 * the hardware shutdown down. Can sleep.
4709 */
4710static int tg3_alloc_consistent(struct tg3 *tp)
4711{
bd2b3343 4712 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 4713 (TG3_RX_RING_SIZE +
4714 TG3_RX_JUMBO_RING_SIZE)) +
4715 (sizeof(struct tx_ring_info) *
4716 TG3_TX_RING_SIZE),
4717 GFP_KERNEL);
4718 if (!tp->rx_std_buffers)
4719 return -ENOMEM;
4720
1da177e4
LT		 4721 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4722 tp->tx_buffers = (struct tx_ring_info *)
4723 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4724
4725 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4726 &tp->rx_std_mapping);
4727 if (!tp->rx_std)
4728 goto err_out;
4729
4730 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4731 &tp->rx_jumbo_mapping);
4732
4733 if (!tp->rx_jumbo)
4734 goto err_out;
4735
4736 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4737 &tp->rx_rcb_mapping);
4738 if (!tp->rx_rcb)
4739 goto err_out;
4740
4741 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4742 &tp->tx_desc_mapping);
4743 if (!tp->tx_ring)
4744 goto err_out;
4745
4746 tp->hw_status = pci_alloc_consistent(tp->pdev,
4747 TG3_HW_STATUS_SIZE,
4748 &tp->status_mapping);
4749 if (!tp->hw_status)
4750 goto err_out;
4751
4752 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4753 sizeof(struct tg3_hw_stats),
4754 &tp->stats_mapping);
4755 if (!tp->hw_stats)
4756 goto err_out;
4757
4758 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4759 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4760
4761 return 0;
4762
4763err_out:
4764 tg3_free_consistent(tp);
4765 return -ENOMEM;
4766}
4767
4768#define MAX_WAIT_CNT 1000
4769
4770/* To stop a block, clear the enable bit and poll till it
4771 * clears. tp->lock is held.
4772 */
b3b7d6be 4773static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4774{
4775 unsigned int i;
4776 u32 val;
4777
4778 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4779 switch (ofs) {
4780 case RCVLSC_MODE:
4781 case DMAC_MODE:
4782 case MBFREE_MODE:
4783 case BUFMGR_MODE:
4784 case MEMARB_MODE:
4785 /* We can't enable/disable these bits of the
4786 * 5705/5750, just say success.
4787 */
4788 return 0;
4789
4790 default:
4791 break;
4792 };
4793 }
4794
4795 val = tr32(ofs);
4796 val &= ~enable_bit;
4797 tw32_f(ofs, val);
4798
4799 for (i = 0; i < MAX_WAIT_CNT; i++) {
4800 udelay(100);
4801 val = tr32(ofs);
4802 if ((val & enable_bit) == 0)
4803 break;
4804 }
4805
b3b7d6be 4806 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4807 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4808 "ofs=%lx enable_bit=%x\n",
4809 ofs, enable_bit);
4810 return -ENODEV;
4811 }
4812
4813 return 0;
4814}
4815
4816/* tp->lock is held. */
b3b7d6be 4817static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4818{
4819 int i, err;
4820
4821 tg3_disable_ints(tp);
4822
4823 tp->rx_mode &= ~RX_MODE_ENABLE;
4824 tw32_f(MAC_RX_MODE, tp->rx_mode);
4825 udelay(10);
4826
b3b7d6be
DM		 4827 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4828 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4829 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4830 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4831 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4832 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4833
4834 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4835 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4836 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4837 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4838 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4839 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4840 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4841
4842 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4843 tw32_f(MAC_MODE, tp->mac_mode);
4844 udelay(40);
4845
4846 tp->tx_mode &= ~TX_MODE_ENABLE;
4847 tw32_f(MAC_TX_MODE, tp->tx_mode);
4848
4849 for (i = 0; i < MAX_WAIT_CNT; i++) {
4850 udelay(100);
4851 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4852 break;
4853 }
4854 if (i >= MAX_WAIT_CNT) {
4855 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4856 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4857 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4858 err |= -ENODEV;
1da177e4
LT		 4859 }
4860
e6de8ad1 4861 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4862 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4863 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4864
4865 tw32(FTQ_RESET, 0xffffffff);
4866 tw32(FTQ_RESET, 0x00000000);
4867
b3b7d6be
DM		 4868 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4869 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4870
4871 if (tp->hw_status)
4872 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4873 if (tp->hw_stats)
4874 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4875
1da177e4
LT		 4876 return err;
4877}
4878
4879/* tp->lock is held. */
4880static int tg3_nvram_lock(struct tg3 *tp)
4881{
4882 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4883 int i;
4884
ec41c7df
MC		 4885 if (tp->nvram_lock_cnt == 0) {
4886 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4887 for (i = 0; i < 8000; i++) {
4888 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4889 break;
4890 udelay(20);
4891 }
4892 if (i == 8000) {
4893 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4894 return -ENODEV;
4895 }
1da177e4 4896 }
ec41c7df 4897 tp->nvram_lock_cnt++;
1da177e4
LT		 4898 }
4899 return 0;
4900}
4901
4902/* tp->lock is held. */
4903static void tg3_nvram_unlock(struct tg3 *tp)
4904{
ec41c7df
MC		 4905 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4906 if (tp->nvram_lock_cnt > 0)
4907 tp->nvram_lock_cnt--;
4908 if (tp->nvram_lock_cnt == 0)
4909 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4910 }
1da177e4
LT		 4911}
4912
e6af301b
MC		 4913/* tp->lock is held. */
4914static void tg3_enable_nvram_access(struct tg3 *tp)
4915{
4916 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4917 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4918 u32 nvaccess = tr32(NVRAM_ACCESS);
4919
4920 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4921 }
4922}
4923
4924/* tp->lock is held. */
4925static void tg3_disable_nvram_access(struct tg3 *tp)
4926{
4927 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4928 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4929 u32 nvaccess = tr32(NVRAM_ACCESS);
4930
4931 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4932 }
4933}
4934
0d3031d9
MC		 4935static void tg3_ape_send_event(struct tg3 *tp, u32 event)
4936{
4937 int i;
4938 u32 apedata;
4939
4940 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
4941 if (apedata != APE_SEG_SIG_MAGIC)
4942 return;
4943
4944 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
4945 if (apedata != APE_FW_STATUS_READY)
4946 return;
4947
4948 /* Wait for up to 1 millisecond for APE to service previous event. */
4949 for (i = 0; i < 10; i++) {
4950 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
4951 return;
4952
4953 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
4954
4955 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4956 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
4957 event | APE_EVENT_STATUS_EVENT_PENDING);
4958
4959 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
4960
4961 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4962 break;
4963
4964 udelay(100);
4965 }
4966
4967 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
4968 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
4969}
4970
4971static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
4972{
4973 u32 event;
4974 u32 apedata;
4975
4976 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
4977 return;
4978
4979 switch (kind) {
4980 case RESET_KIND_INIT:
4981 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
4982 APE_HOST_SEG_SIG_MAGIC);
4983 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
4984 APE_HOST_SEG_LEN_MAGIC);
4985 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
4986 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
4987 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
4988 APE_HOST_DRIVER_ID_MAGIC);
4989 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
4990 APE_HOST_BEHAV_NO_PHYLOCK);
4991
4992 event = APE_EVENT_STATUS_STATE_START;
4993 break;
4994 case RESET_KIND_SHUTDOWN:
4995 event = APE_EVENT_STATUS_STATE_UNLOAD;
4996 break;
4997 case RESET_KIND_SUSPEND:
4998 event = APE_EVENT_STATUS_STATE_SUSPEND;
4999 break;
5000 default:
5001 return;
5002 }
5003
5004 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5005
5006 tg3_ape_send_event(tp, event);
5007}
5008
1da177e4
LT		 5009/* tp->lock is held. */
5010static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5011{
f49639e6
DM		 5012 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5013 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5014
5015 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5016 switch (kind) {
5017 case RESET_KIND_INIT:
5018 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5019 DRV_STATE_START);
5020 break;
5021
5022 case RESET_KIND_SHUTDOWN:
5023 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5024 DRV_STATE_UNLOAD);
5025 break;
5026
5027 case RESET_KIND_SUSPEND:
5028 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5029 DRV_STATE_SUSPEND);
5030 break;
5031
5032 default:
5033 break;
5034 };
5035 }
0d3031d9
MC		 5036
5037 if (kind == RESET_KIND_INIT ||
5038 kind == RESET_KIND_SUSPEND)
5039 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5040}
5041
5042/* tp->lock is held. */
5043static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5044{
5045 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5046 switch (kind) {
5047 case RESET_KIND_INIT:
5048 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5049 DRV_STATE_START_DONE);
5050 break;
5051
5052 case RESET_KIND_SHUTDOWN:
5053 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5054 DRV_STATE_UNLOAD_DONE);
5055 break;
5056
5057 default:
5058 break;
5059 };
5060 }
0d3031d9
MC		 5061
5062 if (kind == RESET_KIND_SHUTDOWN)
5063 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5064}
5065
5066/* tp->lock is held. */
5067static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5068{
5069 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5070 switch (kind) {
5071 case RESET_KIND_INIT:
5072 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5073 DRV_STATE_START);
5074 break;
5075
5076 case RESET_KIND_SHUTDOWN:
5077 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5078 DRV_STATE_UNLOAD);
5079 break;
5080
5081 case RESET_KIND_SUSPEND:
5082 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5083 DRV_STATE_SUSPEND);
5084 break;
5085
5086 default:
5087 break;
5088 };
5089 }
5090}
5091
7a6f4369
MC		 5092static int tg3_poll_fw(struct tg3 *tp)
5093{
5094 int i;
5095 u32 val;
5096
b5d3772c 5097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 5098 /* Wait up to 20ms for init done. */
5099 for (i = 0; i < 200; i++) {
b5d3772c
MC		 5100 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5101 return 0;
0ccead18 5102 udelay(100);
b5d3772c
MC		 5103 }
5104 return -ENODEV;
5105 }
5106
7a6f4369
MC		 5107 /* Wait for firmware initialization to complete. */
5108 for (i = 0; i < 100000; i++) {
5109 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5110 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5111 break;
5112 udelay(10);
5113 }
5114
5115 /* Chip might not be fitted with firmware. Some Sun onboard
5116 * parts are configured like that. So don't signal the timeout
5117 * of the above loop as an error, but do report the lack of
5118 * running firmware once.
5119 */
5120 if (i >= 100000 &&
5121 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5122 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5123
5124 printk(KERN_INFO PFX "%s: No firmware running.\n",
5125 tp->dev->name);
5126 }
5127
5128 return 0;
5129}
5130
ee6a99b5
MC		 5131/* Save PCI command register before chip reset */
5132static void tg3_save_pci_state(struct tg3 *tp)
5133{
8a6eac90 5134 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 5135}
5136
5137/* Restore PCI state after chip reset */
5138static void tg3_restore_pci_state(struct tg3 *tp)
5139{
5140 u32 val;
5141
5142 /* Re-enable indirect register accesses. */
5143 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5144 tp->misc_host_ctrl);
5145
5146 /* Set MAX PCI retry to zero. */
5147 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5148 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5149 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5150 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 5151 /* Allow reads and writes to the APE register and memory space. */
5152 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5153 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5154 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 5155 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5156
8a6eac90 5157 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 5158
5f5c51e3
MC		 5159 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5160 pcie_set_readrq(tp->pdev, 4096);
5161 else {
114342f2
MC		 5162 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5163 tp->pci_cacheline_sz);
5164 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5165 tp->pci_lat_timer);
5166 }
5f5c51e3 5167
ee6a99b5 5168 /* Make sure PCI-X relaxed ordering bit is clear. */
9974a356
MC		 5169 if (tp->pcix_cap) {
5170 u16 pcix_cmd;
5171
5172 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5173 &pcix_cmd);
5174 pcix_cmd &= ~PCI_X_CMD_ERO;
5175 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5176 pcix_cmd);
5177 }
ee6a99b5
MC		 5178
5179 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 5180
5181 /* Chip reset on 5780 will reset MSI enable bit,
5182 * so need to restore it.
5183 */
5184 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5185 u16 ctrl;
5186
5187 pci_read_config_word(tp->pdev,
5188 tp->msi_cap + PCI_MSI_FLAGS,
5189 &ctrl);
5190 pci_write_config_word(tp->pdev,
5191 tp->msi_cap + PCI_MSI_FLAGS,
5192 ctrl | PCI_MSI_FLAGS_ENABLE);
5193 val = tr32(MSGINT_MODE);
5194 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5195 }
5196 }
5197}
5198
1da177e4
LT		 5199static void tg3_stop_fw(struct tg3 *);
5200
5201/* tp->lock is held. */
5202static int tg3_chip_reset(struct tg3 *tp)
5203{
5204 u32 val;
1ee582d8 5205 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 5206 int err;
1da177e4 5207
f49639e6
DM		 5208 tg3_nvram_lock(tp);
5209
5210 /* No matching tg3_nvram_unlock() after this because
5211 * chip reset below will undo the nvram lock.
5212 */
5213 tp->nvram_lock_cnt = 0;
1da177e4 5214
ee6a99b5
MC		 5215 /* GRC_MISC_CFG core clock reset will clear the memory
5216 * enable bit in PCI register 4 and the MSI enable bit
5217 * on some chips, so we save relevant registers here.
5218 */
5219 tg3_save_pci_state(tp);
5220
d9ab5ad1 5221 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 5222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 5223 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 5224 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
d9ab5ad1
MC		 5226 tw32(GRC_FASTBOOT_PC, 0);
5227
1da177e4
LT		 5228 /*
5229 * We must avoid the readl() that normally takes place.
5230 * It locks machines, causes machine checks, and other
5231 * fun things. So, temporarily disable the 5701
5232 * hardware workaround, while we do the reset.
5233 */
1ee582d8
MC		 5234 write_op = tp->write32;
5235 if (write_op == tg3_write_flush_reg32)
5236 tp->write32 = tg3_write32;
1da177e4 5237
d18edcb2
MC		 5238 /* Prevent the irq handler from reading or writing PCI registers
5239 * during chip reset when the memory enable bit in the PCI command
5240 * register may be cleared. The chip does not generate interrupt
5241 * at this time, but the irq handler may still be called due to irq
5242 * sharing or irqpoll.
5243 */
5244 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 5245 if (tp->hw_status) {
5246 tp->hw_status->status = 0;
5247 tp->hw_status->status_tag = 0;
5248 }
d18edcb2
MC		 5249 tp->last_tag = 0;
5250 smp_mb();
5251 synchronize_irq(tp->pdev->irq);
5252
1da177e4
LT		 5253 /* do the reset */
5254 val = GRC_MISC_CFG_CORECLK_RESET;
5255
5256 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5257 if (tr32(0x7e2c) == 0x60) {
5258 tw32(0x7e2c, 0x20);
5259 }
5260 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5261 tw32(GRC_MISC_CFG, (1 << 29));
5262 val |= (1 << 29);
5263 }
5264 }
5265
b5d3772c
MC		 5266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5267 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5268 tw32(GRC_VCPU_EXT_CTRL,
5269 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5270 }
5271
1da177e4
LT		 5272 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5273 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5274 tw32(GRC_MISC_CFG, val);
5275
1ee582d8
MC		 5276 /* restore 5701 hardware bug workaround write method */
5277 tp->write32 = write_op;
1da177e4
LT		 5278
5279 /* Unfortunately, we have to delay before the PCI read back.
5280 * Some 575X chips even will not respond to a PCI cfg access
5281 * when the reset command is given to the chip.
5282 *
5283 * How do these hardware designers expect things to work
5284 * properly if the PCI write is posted for a long period
5285 * of time? It is always necessary to have some method by
5286 * which a register read back can occur to push the write
5287 * out which does the reset.
5288 *
5289 * For most tg3 variants the trick below was working.
5290 * Ho hum...
5291 */
5292 udelay(120);
5293
5294 /* Flush PCI posted writes. The normal MMIO registers
5295 * are inaccessible at this time so this is the only
5296 * way to make this reliably (actually, this is no longer
5297 * the case, see above). I tried to use indirect
5298 * register read/write but this upset some 5701 variants.
5299 */
5300 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5301
5302 udelay(120);
5303
5304 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5305 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5306 int i;
5307 u32 cfg_val;
5308
5309 /* Wait for link training to complete. */
5310 for (i = 0; i < 5000; i++)
5311 udelay(100);
5312
5313 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5314 pci_write_config_dword(tp->pdev, 0xc4,
5315 cfg_val | (1 << 15));
5316 }
5317 /* Set PCIE max payload size and clear error status. */
5318 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5319 }
5320
ee6a99b5 5321 tg3_restore_pci_state(tp);
1da177e4 5322
d18edcb2
MC		 5323 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5324
ee6a99b5
MC		 5325 val = 0;
5326 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 5327 val = tr32(MEMARB_MODE);
ee6a99b5 5328 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 5329
5330 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5331 tg3_stop_fw(tp);
5332 tw32(0x5000, 0x400);
5333 }
5334
5335 tw32(GRC_MODE, tp->grc_mode);
5336
5337 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 5338 val = tr32(0xc4);
1da177e4
LT		 5339
5340 tw32(0xc4, val | (1 << 15));
5341 }
5342
5343 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5344 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5345 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5346 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5347 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5348 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5349 }
5350
5351 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5352 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5353 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 5354 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5355 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5356 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 5357 } else
5358 tw32_f(MAC_MODE, 0);
5359 udelay(40);
5360
7a6f4369
MC		 5361 err = tg3_poll_fw(tp);
5362 if (err)
5363 return err;
1da177e4
LT		 5364
5365 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5366 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 5367 val = tr32(0x7c00);
1da177e4
LT		 5368
5369 tw32(0x7c00, val | (1 << 25));
5370 }
5371
5372 /* Reprobe ASF enable state. */
5373 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5374 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5375 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5376 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5377 u32 nic_cfg;
5378
5379 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5380 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5381 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 5382 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 5383 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5384 }
5385 }
5386
5387 return 0;
5388}
5389
5390/* tp->lock is held. */
5391static void tg3_stop_fw(struct tg3 *tp)
5392{
0d3031d9
MC		 5393 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5394 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 5395 u32 val;
5396 int i;
5397
5398 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5399 val = tr32(GRC_RX_CPU_EVENT);
5400 val |= (1 << 14);
5401 tw32(GRC_RX_CPU_EVENT, val);
5402
5403 /* Wait for RX cpu to ACK the event. */
5404 for (i = 0; i < 100; i++) {
5405 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5406 break;
5407 udelay(1);
5408 }
5409 }
5410}
5411
5412/* tp->lock is held. */
944d980e 5413static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 5414{
5415 int err;
5416
5417 tg3_stop_fw(tp);
5418
944d980e 5419 tg3_write_sig_pre_reset(tp, kind);
1da177e4 5420
b3b7d6be 5421 tg3_abort_hw(tp, silent);
1da177e4
LT		 5422 err = tg3_chip_reset(tp);
5423
944d980e
MC		 5424 tg3_write_sig_legacy(tp, kind);
5425 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 5426
5427 if (err)
5428 return err;
5429
5430 return 0;
5431}
5432
5433#define TG3_FW_RELEASE_MAJOR 0x0
5434#define TG3_FW_RELASE_MINOR 0x0
5435#define TG3_FW_RELEASE_FIX 0x0
5436#define TG3_FW_START_ADDR 0x08000000
5437#define TG3_FW_TEXT_ADDR 0x08000000
5438#define TG3_FW_TEXT_LEN 0x9c0
5439#define TG3_FW_RODATA_ADDR 0x080009c0
5440#define TG3_FW_RODATA_LEN 0x60
5441#define TG3_FW_DATA_ADDR 0x08000a40
5442#define TG3_FW_DATA_LEN 0x20
5443#define TG3_FW_SBSS_ADDR 0x08000a60
5444#define TG3_FW_SBSS_LEN 0xc
5445#define TG3_FW_BSS_ADDR 0x08000a70
5446#define TG3_FW_BSS_LEN 0x10
5447
50da859d 5448static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5449 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5450 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5451 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5452 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5453 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5454 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5455 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5456 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5457 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5458 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5459 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5460 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5461 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5462 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5463 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5464 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5465 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5466 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5467 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5468 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5469 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5470 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5471 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5474 0, 0, 0, 0, 0, 0,
5475 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5476 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5477 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5478 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5479 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5480 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5481 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5482 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5483 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5484 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5485 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5489 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5490 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5491 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5492 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5493 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5494 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5495 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5496 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5497 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5498 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5499 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5500 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5501 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5502 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5503 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5504 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5505 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5506 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5507 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5508 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5509 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5510 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5511 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5512 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5513 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5514 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5515 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5516 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5517 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5518 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5519 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5520 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5521 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5522 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5523 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5524 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5525 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5526 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5527 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5528 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5529 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5530 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5531 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5532 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5533 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5534 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5535 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5536 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5537 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5538 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5539 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5540};
5541
50da859d 5542static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5543 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5544 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5545 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5546 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5547 0x00000000
5548};
5549
5550#if 0 /* All zeros, don't eat up space with it. */
5551u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5552 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5553 0x00000000, 0x00000000, 0x00000000, 0x00000000
5554};
5555#endif
5556
5557#define RX_CPU_SCRATCH_BASE 0x30000
5558#define RX_CPU_SCRATCH_SIZE 0x04000
5559#define TX_CPU_SCRATCH_BASE 0x34000
5560#define TX_CPU_SCRATCH_SIZE 0x04000
5561
5562/* tp->lock is held. */
5563static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5564{
5565 int i;
5566
5d9428de
ES		 5567 BUG_ON(offset == TX_CPU_BASE &&
5568 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 5569
b5d3772c
MC		 5570 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5571 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5572
5573 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5574 return 0;
5575 }
1da177e4
LT		 5576 if (offset == RX_CPU_BASE) {
5577 for (i = 0; i < 10000; i++) {
5578 tw32(offset + CPU_STATE, 0xffffffff);
5579 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5580 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5581 break;
5582 }
5583
5584 tw32(offset + CPU_STATE, 0xffffffff);
5585 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5586 udelay(10);
5587 } else {
5588 for (i = 0; i < 10000; i++) {
5589 tw32(offset + CPU_STATE, 0xffffffff);
5590 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5591 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5592 break;
5593 }
5594 }
5595
5596 if (i >= 10000) {
5597 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5598 "and %s CPU\n",
5599 tp->dev->name,
5600 (offset == RX_CPU_BASE ? "RX" : "TX"));
5601 return -ENODEV;
5602 }
ec41c7df
MC		 5603
5604 /* Clear firmware's nvram arbitration. */
5605 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5606 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 5607 return 0;
5608}
5609
5610struct fw_info {
5611 unsigned int text_base;
5612 unsigned int text_len;
50da859d 5613 const u32 *text_data;
1da177e4
LT		 5614 unsigned int rodata_base;
5615 unsigned int rodata_len;
50da859d 5616 const u32 *rodata_data;
1da177e4
LT		 5617 unsigned int data_base;
5618 unsigned int data_len;
50da859d 5619 const u32 *data_data;
1da177e4
LT		 5620};
5621
5622/* tp->lock is held. */
5623static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5624 int cpu_scratch_size, struct fw_info *info)
5625{
ec41c7df 5626 int err, lock_err, i;
1da177e4
LT		 5627 void (*write_op)(struct tg3 *, u32, u32);
5628
5629 if (cpu_base == TX_CPU_BASE &&
5630 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5631 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5632 "TX cpu firmware on %s which is 5705.\n",
5633 tp->dev->name);
5634 return -EINVAL;
5635 }
5636
5637 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5638 write_op = tg3_write_mem;
5639 else
5640 write_op = tg3_write_indirect_reg32;
5641
1b628151
MC		 5642 /* It is possible that bootcode is still loading at this point.
5643 * Get the nvram lock first before halting the cpu.
5644 */
ec41c7df 5645 lock_err = tg3_nvram_lock(tp);
1da177e4 5646 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 5647 if (!lock_err)
5648 tg3_nvram_unlock(tp);
1da177e4
LT		 5649 if (err)
5650 goto out;
5651
5652 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5653 write_op(tp, cpu_scratch_base + i, 0);
5654 tw32(cpu_base + CPU_STATE, 0xffffffff);
5655 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5656 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5657 write_op(tp, (cpu_scratch_base +
5658 (info->text_base & 0xffff) +
5659 (i * sizeof(u32))),
5660 (info->text_data ?
5661 info->text_data[i] : 0));
5662 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5663 write_op(tp, (cpu_scratch_base +
5664 (info->rodata_base & 0xffff) +
5665 (i * sizeof(u32))),
5666 (info->rodata_data ?
5667 info->rodata_data[i] : 0));
5668 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5669 write_op(tp, (cpu_scratch_base +
5670 (info->data_base & 0xffff) +
5671 (i * sizeof(u32))),
5672 (info->data_data ?
5673 info->data_data[i] : 0));
5674
5675 err = 0;
5676
5677out:
1da177e4
LT		 5678 return err;
5679}
5680
5681/* tp->lock is held. */
5682static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5683{
5684 struct fw_info info;
5685 int err, i;
5686
5687 info.text_base = TG3_FW_TEXT_ADDR;
5688 info.text_len = TG3_FW_TEXT_LEN;
5689 info.text_data = &tg3FwText[0];
5690 info.rodata_base = TG3_FW_RODATA_ADDR;
5691 info.rodata_len = TG3_FW_RODATA_LEN;
5692 info.rodata_data = &tg3FwRodata[0];
5693 info.data_base = TG3_FW_DATA_ADDR;
5694 info.data_len = TG3_FW_DATA_LEN;
5695 info.data_data = NULL;
5696
5697 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5698 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5699 &info);
5700 if (err)
5701 return err;
5702
5703 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5704 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5705 &info);
5706 if (err)
5707 return err;
5708
5709 /* Now startup only the RX cpu. */
5710 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5711 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5712
5713 for (i = 0; i < 5; i++) {
5714 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5715 break;
5716 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5717 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5718 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5719 udelay(1000);
5720 }
5721 if (i >= 5) {
5722 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5723 "to set RX CPU PC, is %08x should be %08x\n",
5724 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5725 TG3_FW_TEXT_ADDR);
5726 return -ENODEV;
5727 }
5728 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5729 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5730
5731 return 0;
5732}
5733
1da177e4
LT		 5734
5735#define TG3_TSO_FW_RELEASE_MAJOR 0x1
5736#define TG3_TSO_FW_RELASE_MINOR 0x6
5737#define TG3_TSO_FW_RELEASE_FIX 0x0
5738#define TG3_TSO_FW_START_ADDR 0x08000000
5739#define TG3_TSO_FW_TEXT_ADDR 0x08000000
5740#define TG3_TSO_FW_TEXT_LEN 0x1aa0
5741#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5742#define TG3_TSO_FW_RODATA_LEN 0x60
5743#define TG3_TSO_FW_DATA_ADDR 0x08001b20
5744#define TG3_TSO_FW_DATA_LEN 0x30
5745#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5746#define TG3_TSO_FW_SBSS_LEN 0x2c
5747#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5748#define TG3_TSO_FW_BSS_LEN 0x894
5749
50da859d 5750static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5751 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5752 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5753 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5754 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5755 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5756 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5757 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5758 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5759 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5760 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5761 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5762 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5763 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5764 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5765 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5766 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5767 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5768 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5769 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5770 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5771 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5772 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5773 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5774 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5775 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5776 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5777 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5778 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5779 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5780 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5781 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5782 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5783 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5784 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5785 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5786 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5787 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5788 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5789 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5790 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5791 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5792 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5793 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5794 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5795 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5796 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5797 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5798 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5799 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5800 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5801 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5802 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5803 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5804 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5805 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5806 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5807 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5808 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5809 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5810 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5811 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5812 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5813 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5814 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5815 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5816 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5817 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5818 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5819 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5820 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5821 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5822 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5823 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5824 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5825 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5826 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5827 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5828 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5829 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5830 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5831 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5832 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5833 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5834 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5835 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5836 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5837 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5838 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5839 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5840 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5841 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5842 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5843 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5844 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5845 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5846 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5847 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5848 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5849 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5850 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5851 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5852 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5853 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5854 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5855 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5856 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5857 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5858 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5859 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5860 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5861 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5862 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5863 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5864 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5865 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5866 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5867 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5868 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5869 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5870 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5871 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5872 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5873 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5874 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5875 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5876 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5877 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5878 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5879 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5880 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5881 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5882 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5883 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5884 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5885 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5886 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5887 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5888 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5889 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5890 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5891 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5892 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5893 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5894 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5895 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5896 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5897 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5898 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5899 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5900 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5901 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5902 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5903 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5904 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5905 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5906 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5907 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5908 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5909 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5910 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5911 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5912 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5913 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5914 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5915 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5916 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5917 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5918 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5919 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5920 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5921 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5922 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5923 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5924 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5925 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5926 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5927 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5928 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5929 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5930 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5931 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5932 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5933 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5934 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5935 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5936 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5937 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5938 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5939 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5940 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5941 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5942 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5943 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5944 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5945 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5946 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5947 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5948 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5949 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5950 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5951 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5952 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5953 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5954 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5955 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5956 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5957 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5958 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5959 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5960 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5961 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5962 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5963 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5964 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5965 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5966 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5967 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5968 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5969 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5970 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5971 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5972 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5973 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5974 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5975 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5976 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5977 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5978 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5979 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5980 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5981 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5982 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5983 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5984 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5985 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5986 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5987 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5988 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5989 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5990 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5991 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5992 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5993 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5994 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5995 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5996 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5997 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5998 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5999 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6000 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6001 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6002 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6003 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6004 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6005 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6006 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6007 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6008 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6009 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6010 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6011 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6012 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6013 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6014 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6015 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6016 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6017 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6018 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6019 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6020 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6021 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6022 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6023 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6024 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6025 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6026 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6027 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6028 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6029 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6030 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6031 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6032 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6033 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6034 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6035};
6036
50da859d 6037static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 6038 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6039 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6040 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6041 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6042 0x00000000,
6043};
6044
50da859d 6045static const u32 tg3TsoFwData[] = {
1da177e4
LT		 6046 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6047 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6048 0x00000000,
6049};
6050
6051/* 5705 needs a special version of the TSO firmware. */
6052#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
6053#define TG3_TSO5_FW_RELASE_MINOR 0x2
6054#define TG3_TSO5_FW_RELEASE_FIX 0x0
6055#define TG3_TSO5_FW_START_ADDR 0x00010000
6056#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
6057#define TG3_TSO5_FW_TEXT_LEN 0xe90
6058#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
6059#define TG3_TSO5_FW_RODATA_LEN 0x50
6060#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6061#define TG3_TSO5_FW_DATA_LEN 0x20
6062#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6063#define TG3_TSO5_FW_SBSS_LEN 0x28
6064#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6065#define TG3_TSO5_FW_BSS_LEN 0x88
6066
50da859d 6067static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 6068 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6069 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6070 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6071 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6072 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6073 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6074 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6075 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6076 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6077 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6078 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6079 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6080 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6081 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6082 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6083 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6084 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6085 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6086 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6087 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6088 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6089 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6090 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6091 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6092 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6093 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6094 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6095 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6096 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6097 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6098 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6099 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6100 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6101 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6102 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6103 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6104 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6105 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6106 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6107 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6108 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6109 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6110 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6111 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6112 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6113 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6114 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6115 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6116 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6117 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6118 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6119 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6120 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6121 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6122 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6123 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6124 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6125 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6126 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6127 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6128 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6129 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6130 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6131 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6132 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6133 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6134 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6135 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6136 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6137 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6138 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6139 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6140 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6141 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6142 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6143 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6144 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6145 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6146 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6147 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6148 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6149 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6150 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6151 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6152 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6153 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6154 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6155 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6156 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6157 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6158 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6159 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6160 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6161 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6162 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6163 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6164 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6165 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6166 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6167 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6168 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6169 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6170 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6171 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6172 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6173 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6174 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6175 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6176 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6177 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6178 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6179 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6180 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6181 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6182 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6183 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6184 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6185 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6186 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6187 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6188 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6189 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6190 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6191 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6192 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6193 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6194 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6195 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6196 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6197 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6198 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6199 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6200 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6201 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6202 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6203 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6204 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6205 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6206 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6207 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6208 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6209 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6210 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6211 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6212 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6213 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6214 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6215 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6216 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6217 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6218 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6219 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6220 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6221 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6222 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6223 0x00000000, 0x00000000, 0x00000000,
6224};
6225
50da859d 6226static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 6227 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6228 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6229 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6230 0x00000000, 0x00000000, 0x00000000,
6231};
6232
50da859d 6233static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 6234 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6235 0x00000000, 0x00000000, 0x00000000,
6236};
6237
6238/* tp->lock is held. */
6239static int tg3_load_tso_firmware(struct tg3 *tp)
6240{
6241 struct fw_info info;
6242 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6243 int err, i;
6244
6245 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6246 return 0;
6247
6248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6249 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6250 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6251 info.text_data = &tg3Tso5FwText[0];
6252 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6253 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6254 info.rodata_data = &tg3Tso5FwRodata[0];
6255 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6256 info.data_len = TG3_TSO5_FW_DATA_LEN;
6257 info.data_data = &tg3Tso5FwData[0];
6258 cpu_base = RX_CPU_BASE;
6259 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6260 cpu_scratch_size = (info.text_len +
6261 info.rodata_len +
6262 info.data_len +
6263 TG3_TSO5_FW_SBSS_LEN +
6264 TG3_TSO5_FW_BSS_LEN);
6265 } else {
6266 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6267 info.text_len = TG3_TSO_FW_TEXT_LEN;
6268 info.text_data = &tg3TsoFwText[0];
6269 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6270 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6271 info.rodata_data = &tg3TsoFwRodata[0];
6272 info.data_base = TG3_TSO_FW_DATA_ADDR;
6273 info.data_len = TG3_TSO_FW_DATA_LEN;
6274 info.data_data = &tg3TsoFwData[0];
6275 cpu_base = TX_CPU_BASE;
6276 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6277 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6278 }
6279
6280 err = tg3_load_firmware_cpu(tp, cpu_base,
6281 cpu_scratch_base, cpu_scratch_size,
6282 &info);
6283 if (err)
6284 return err;
6285
6286 /* Now startup the cpu. */
6287 tw32(cpu_base + CPU_STATE, 0xffffffff);
6288 tw32_f(cpu_base + CPU_PC, info.text_base);
6289
6290 for (i = 0; i < 5; i++) {
6291 if (tr32(cpu_base + CPU_PC) == info.text_base)
6292 break;
6293 tw32(cpu_base + CPU_STATE, 0xffffffff);
6294 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6295 tw32_f(cpu_base + CPU_PC, info.text_base);
6296 udelay(1000);
6297 }
6298 if (i >= 5) {
6299 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6300 "to set CPU PC, is %08x should be %08x\n",
6301 tp->dev->name, tr32(cpu_base + CPU_PC),
6302 info.text_base);
6303 return -ENODEV;
6304 }
6305 tw32(cpu_base + CPU_STATE, 0xffffffff);
6306 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6307 return 0;
6308}
6309
1da177e4
LT		 6310
6311/* tp->lock is held. */
986e0aeb 6312static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
1da177e4
LT		 6313{
6314 u32 addr_high, addr_low;
6315 int i;
6316
6317 addr_high = ((tp->dev->dev_addr[0] << 8) |
6318 tp->dev->dev_addr[1]);
6319 addr_low = ((tp->dev->dev_addr[2] << 24) |
6320 (tp->dev->dev_addr[3] << 16) |
6321 (tp->dev->dev_addr[4] << 8) |
6322 (tp->dev->dev_addr[5] << 0));
6323 for (i = 0; i < 4; i++) {
986e0aeb
MC		 6324 if (i == 1 && skip_mac_1)
6325 continue;
1da177e4
LT		 6326 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6327 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6328 }
6329
6330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6331 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6332 for (i = 0; i < 12; i++) {
6333 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6334 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6335 }
6336 }
6337
6338 addr_high = (tp->dev->dev_addr[0] +
6339 tp->dev->dev_addr[1] +
6340 tp->dev->dev_addr[2] +
6341 tp->dev->dev_addr[3] +
6342 tp->dev->dev_addr[4] +
6343 tp->dev->dev_addr[5]) &
6344 TX_BACKOFF_SEED_MASK;
6345 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6346}
6347
6348static int tg3_set_mac_addr(struct net_device *dev, void *p)
6349{
6350 struct tg3 *tp = netdev_priv(dev);
6351 struct sockaddr *addr = p;
986e0aeb 6352 int err = 0, skip_mac_1 = 0;
1da177e4 6353
f9804ddb
MC		 6354 if (!is_valid_ether_addr(addr->sa_data))
6355 return -EINVAL;
6356
1da177e4
LT		 6357 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6358
e75f7c90
MC		 6359 if (!netif_running(dev))
6360 return 0;
6361
58712ef9 6362 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6363 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6364
986e0aeb
MC		 6365 addr0_high = tr32(MAC_ADDR_0_HIGH);
6366 addr0_low = tr32(MAC_ADDR_0_LOW);
6367 addr1_high = tr32(MAC_ADDR_1_HIGH);
6368 addr1_low = tr32(MAC_ADDR_1_LOW);
6369
6370 /* Skip MAC addr 1 if ASF is using it. */
6371 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6372 !(addr1_high == 0 && addr1_low == 0))
6373 skip_mac_1 = 1;
58712ef9 6374 }
986e0aeb
MC		 6375 spin_lock_bh(&tp->lock);
6376 __tg3_set_mac_addr(tp, skip_mac_1);
6377 spin_unlock_bh(&tp->lock);
1da177e4 6378
b9ec6c1b 6379 return err;
1da177e4
LT		 6380}
6381
6382/* tp->lock is held. */
6383static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6384 dma_addr_t mapping, u32 maxlen_flags,
6385 u32 nic_addr)
6386{
6387 tg3_write_mem(tp,
6388 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6389 ((u64) mapping >> 32));
6390 tg3_write_mem(tp,
6391 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6392 ((u64) mapping & 0xffffffff));
6393 tg3_write_mem(tp,
6394 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6395 maxlen_flags);
6396
6397 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6398 tg3_write_mem(tp,
6399 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6400 nic_addr);
6401}
6402
6403static void __tg3_set_rx_mode(struct net_device *);
d244c892 6404static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6405{
6406 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6407 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6408 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6409 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6410 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6411 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6412 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6413 }
6414 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6415 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6416 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6417 u32 val = ec->stats_block_coalesce_usecs;
6418
6419 if (!netif_carrier_ok(tp->dev))
6420 val = 0;
6421
6422 tw32(HOSTCC_STAT_COAL_TICKS, val);
6423 }
6424}
1da177e4
LT		 6425
6426/* tp->lock is held. */
8e7a22e3 6427static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6428{
6429 u32 val, rdmac_mode;
6430 int i, err, limit;
6431
6432 tg3_disable_ints(tp);
6433
6434 tg3_stop_fw(tp);
6435
6436 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6437
6438 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6439 tg3_abort_hw(tp, 1);
1da177e4
LT		 6440 }
6441
36da4d86 6442 if (reset_phy)
d4d2c558
MC		 6443 tg3_phy_reset(tp);
6444
1da177e4
LT		 6445 err = tg3_chip_reset(tp);
6446 if (err)
6447 return err;
6448
6449 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6450
b5af7126
MC		 6451 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
6452 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
d30cdd28
MC		 6453 val = tr32(TG3_CPMU_CTRL);
6454 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6455 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6456
6457 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6458 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6459 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6460 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6461
6462 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6463 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6464 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6465 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6466
6467 val = tr32(TG3_CPMU_HST_ACC);
6468 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6469 val |= CPMU_HST_ACC_MACCLK_6_25;
6470 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6471 }
6472
1da177e4
LT		 6473 /* This works around an issue with Athlon chipsets on
6474 * B3 tigon3 silicon. This bit has no effect on any
6475 * other revision. But do not set this on PCI Express
795d01c5 6476 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6477 */
795d01c5
MC		 6478 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6479 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6480 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6481 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6482 }
1da177e4
LT		 6483
6484 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6485 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6486 val = tr32(TG3PCI_PCISTATE);
6487 val |= PCISTATE_RETRY_SAME_DMA;
6488 tw32(TG3PCI_PCISTATE, val);
6489 }
6490
0d3031d9
MC		 6491 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6492 /* Allow reads and writes to the
6493 * APE register and memory space.
6494 */
6495 val = tr32(TG3PCI_PCISTATE);
6496 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6497 PCISTATE_ALLOW_APE_SHMEM_WR;
6498 tw32(TG3PCI_PCISTATE, val);
6499 }
6500
1da177e4
LT		 6501 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6502 /* Enable some hw fixes. */
6503 val = tr32(TG3PCI_MSI_DATA);
6504 val |= (1 << 26) | (1 << 28) | (1 << 29);
6505 tw32(TG3PCI_MSI_DATA, val);
6506 }
6507
6508 /* Descriptor ring init may make accesses to the
6509 * NIC SRAM area to setup the TX descriptors, so we
6510 * can only do this after the hardware has been
6511 * successfully reset.
6512 */
32d8c572
MC		 6513 err = tg3_init_rings(tp);
6514 if (err)
6515 return err;
1da177e4 6516
9936bcf6
MC		 6517 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6518 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6519 /* This value is determined during the probe time DMA
6520 * engine test, tg3_test_dma.
6521 */
6522 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6523 }
1da177e4
LT		 6524
6525 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6526 GRC_MODE_4X_NIC_SEND_RINGS |
6527 GRC_MODE_NO_TX_PHDR_CSUM |
6528 GRC_MODE_NO_RX_PHDR_CSUM);
6529 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6530
6531 /* Pseudo-header checksum is done by hardware logic and not
6532 * the offload processers, so make the chip do the pseudo-
6533 * header checksums on receive. For transmit it is more
6534 * convenient to do the pseudo-header checksum in software
6535 * as Linux does that on transmit for us in all cases.
6536 */
6537 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6538
6539 tw32(GRC_MODE,
6540 tp->grc_mode |
6541 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6542
6543 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6544 val = tr32(GRC_MISC_CFG);
6545 val &= ~0xff;
6546 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6547 tw32(GRC_MISC_CFG, val);
6548
6549 /* Initialize MBUF/DESC pool. */
cbf46853 6550 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6551 /* Do nothing. */
6552 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6553 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6555 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6556 else
6557 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6558 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6559 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6560 }
1da177e4
LT		 6561 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6562 int fw_len;
6563
6564 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6565 TG3_TSO5_FW_RODATA_LEN +
6566 TG3_TSO5_FW_DATA_LEN +
6567 TG3_TSO5_FW_SBSS_LEN +
6568 TG3_TSO5_FW_BSS_LEN);
6569 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6570 tw32(BUFMGR_MB_POOL_ADDR,
6571 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6572 tw32(BUFMGR_MB_POOL_SIZE,
6573 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6574 }
1da177e4 6575
0f893dc6 6576 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6577 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6578 tp->bufmgr_config.mbuf_read_dma_low_water);
6579 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6580 tp->bufmgr_config.mbuf_mac_rx_low_water);
6581 tw32(BUFMGR_MB_HIGH_WATER,
6582 tp->bufmgr_config.mbuf_high_water);
6583 } else {
6584 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6585 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6586 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6587 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6588 tw32(BUFMGR_MB_HIGH_WATER,
6589 tp->bufmgr_config.mbuf_high_water_jumbo);
6590 }
6591 tw32(BUFMGR_DMA_LOW_WATER,
6592 tp->bufmgr_config.dma_low_water);
6593 tw32(BUFMGR_DMA_HIGH_WATER,
6594 tp->bufmgr_config.dma_high_water);
6595
6596 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6597 for (i = 0; i < 2000; i++) {
6598 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6599 break;
6600 udelay(10);
6601 }
6602 if (i >= 2000) {
6603 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6604 tp->dev->name);
6605 return -ENODEV;
6606 }
6607
6608 /* Setup replenish threshold. */
f92905de
MC		 6609 val = tp->rx_pending / 8;
6610 if (val == 0)
6611 val = 1;
6612 else if (val > tp->rx_std_max_post)
6613 val = tp->rx_std_max_post;
b5d3772c
MC		 6614 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6615 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6616 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6617
6618 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6619 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6620 }
f92905de
MC		 6621
6622 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6623
6624 /* Initialize TG3_BDINFO's at:
6625 * RCVDBDI_STD_BD: standard eth size rx ring
6626 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6627 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6628 *
6629 * like so:
6630 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6631 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6632 * ring attribute flags
6633 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6634 *
6635 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6636 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6637 *
6638 * The size of each ring is fixed in the firmware, but the location is
6639 * configurable.
6640 */
6641 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6642 ((u64) tp->rx_std_mapping >> 32));
6643 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6644 ((u64) tp->rx_std_mapping & 0xffffffff));
6645 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6646 NIC_SRAM_RX_BUFFER_DESC);
6647
6648 /* Don't even try to program the JUMBO/MINI buffer descriptor
6649 * configs on 5705.
6650 */
6651 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6652 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6653 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6654 } else {
6655 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6656 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6657
6658 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6659 BDINFO_FLAGS_DISABLED);
6660
6661 /* Setup replenish threshold. */
6662 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6663
0f893dc6 6664 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6665 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6666 ((u64) tp->rx_jumbo_mapping >> 32));
6667 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6668 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6669 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6670 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6671 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6672 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6673 } else {
6674 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6675 BDINFO_FLAGS_DISABLED);
6676 }
6677
6678 }
6679
6680 /* There is only one send ring on 5705/5750, no need to explicitly
6681 * disable the others.
6682 */
6683 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6684 /* Clear out send RCB ring in SRAM. */
6685 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6686 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6687 BDINFO_FLAGS_DISABLED);
6688 }
6689
6690 tp->tx_prod = 0;
6691 tp->tx_cons = 0;
6692 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6693 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6694
6695 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6696 tp->tx_desc_mapping,
6697 (TG3_TX_RING_SIZE <<
6698 BDINFO_FLAGS_MAXLEN_SHIFT),
6699 NIC_SRAM_TX_BUFFER_DESC);
6700
6701 /* There is only one receive return ring on 5705/5750, no need
6702 * to explicitly disable the others.
6703 */
6704 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6705 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6706 i += TG3_BDINFO_SIZE) {
6707 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6708 BDINFO_FLAGS_DISABLED);
6709 }
6710 }
6711
6712 tp->rx_rcb_ptr = 0;
6713 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6714
6715 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6716 tp->rx_rcb_mapping,
6717 (TG3_RX_RCB_RING_SIZE(tp) <<
6718 BDINFO_FLAGS_MAXLEN_SHIFT),
6719 0);
6720
6721 tp->rx_std_ptr = tp->rx_pending;
6722 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6723 tp->rx_std_ptr);
6724
0f893dc6 6725 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6726 tp->rx_jumbo_pending : 0;
6727 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6728 tp->rx_jumbo_ptr);
6729
6730 /* Initialize MAC address and backoff seed. */
986e0aeb 6731 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6732
6733 /* MTU + ethernet header + FCS + optional VLAN tag */
6734 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6735
6736 /* The slot time is changed by tg3_setup_phy if we
6737 * run at gigabit with half duplex.
6738 */
6739 tw32(MAC_TX_LENGTHS,
6740 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6741 (6 << TX_LENGTHS_IPG_SHIFT) |
6742 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6743
6744 /* Receive rules. */
6745 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6746 tw32(RCVLPC_CONFIG, 0x0181);
6747
6748 /* Calculate RDMAC_MODE setting early, we need it to determine
6749 * the RCVLPC_STATE_ENABLE mask.
6750 */
6751 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6752 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6753 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6754 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6755 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 6756
d30cdd28
MC		 6757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
6758 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6759 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6760 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6761
85e94ced
MC		 6762 /* If statement applies to 5705 and 5750 PCI devices only */
6763 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6764 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6765 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 6766 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 6767 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6768 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6769 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6770 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6771 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6772 }
6773 }
6774
85e94ced
MC		 6775 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6776 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6777
1da177e4
LT		 6778 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6779 rdmac_mode |= (1 << 27);
1da177e4
LT		 6780
6781 /* Receive/send statistics. */
1661394e
MC		 6782 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6783 val = tr32(RCVLPC_STATS_ENABLE);
6784 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6785 tw32(RCVLPC_STATS_ENABLE, val);
6786 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6787 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6788 val = tr32(RCVLPC_STATS_ENABLE);
6789 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6790 tw32(RCVLPC_STATS_ENABLE, val);
6791 } else {
6792 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6793 }
6794 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6795 tw32(SNDDATAI_STATSENAB, 0xffffff);
6796 tw32(SNDDATAI_STATSCTRL,
6797 (SNDDATAI_SCTRL_ENABLE |
6798 SNDDATAI_SCTRL_FASTUPD));
6799
6800 /* Setup host coalescing engine. */
6801 tw32(HOSTCC_MODE, 0);
6802 for (i = 0; i < 2000; i++) {
6803 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6804 break;
6805 udelay(10);
6806 }
6807
d244c892 6808 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6809
6810 /* set status block DMA address */
6811 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6812 ((u64) tp->status_mapping >> 32));
6813 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6814 ((u64) tp->status_mapping & 0xffffffff));
6815
6816 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6817 /* Status/statistics block address. See tg3_timer,
6818 * the tg3_periodic_fetch_stats call there, and
6819 * tg3_get_stats to see how this works for 5705/5750 chips.
6820 */
1da177e4
LT		 6821 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6822 ((u64) tp->stats_mapping >> 32));
6823 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6824 ((u64) tp->stats_mapping & 0xffffffff));
6825 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6826 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6827 }
6828
6829 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6830
6831 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6832 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6833 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6834 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6835
6836 /* Clear statistics/status block in chip, and status block in ram. */
6837 for (i = NIC_SRAM_STATS_BLK;
6838 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6839 i += sizeof(u32)) {
6840 tg3_write_mem(tp, i, 0);
6841 udelay(40);
6842 }
6843 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6844
c94e3941
MC		 6845 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6846 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6847 /* reset to prevent losing 1st rx packet intermittently */
6848 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6849 udelay(10);
6850 }
6851
1da177e4
LT		 6852 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6853 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 6854 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6855 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6856 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6857 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 6858 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6859 udelay(40);
6860
314fba34 6861 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6862 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6863 * register to preserve the GPIO settings for LOMs. The GPIOs,
6864 * whether used as inputs or outputs, are set by boot code after
6865 * reset.
6866 */
9d26e213 6867 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6868 u32 gpio_mask;
6869
9d26e213
MC		 6870 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6871 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6872 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6873
6874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6875 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6876 GRC_LCLCTRL_GPIO_OUTPUT3;
6877
af36e6b6
MC		 6878 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6879 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6880
aaf84465 6881 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 6882 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6883
6884 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6885 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6886 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6887 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6888 }
1da177e4
LT		 6889 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6890 udelay(100);
6891
09ee929c 6892 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 6893 tp->last_tag = 0;
1da177e4
LT		 6894
6895 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6896 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6897 udelay(40);
6898 }
6899
6900 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6901 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6902 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6903 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6904 WDMAC_MODE_LNGREAD_ENAB);
6905
85e94ced
MC		 6906 /* If statement applies to 5705 and 5750 PCI devices only */
6907 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6908 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6909 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 6910 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6911 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6912 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6913 /* nothing */
6914 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6915 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6916 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6917 val |= WDMAC_MODE_RX_ACCEL;
6918 }
6919 }
6920
d9ab5ad1 6921 /* Enable host coalescing bug fix */
af36e6b6 6922 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
d30cdd28 6923 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
9936bcf6
MC		 6924 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
6925 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
d9ab5ad1
MC		 6926 val |= (1 << 29);
6927
1da177e4
LT		 6928 tw32_f(WDMAC_MODE, val);
6929 udelay(40);
6930
9974a356
MC		 6931 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6932 u16 pcix_cmd;
6933
6934 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6935 &pcix_cmd);
1da177e4 6936 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 6937 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
6938 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 6939 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 6940 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
6941 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 6942 }
9974a356
MC		 6943 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6944 pcix_cmd);
1da177e4
LT		 6945 }
6946
6947 tw32_f(RDMAC_MODE, rdmac_mode);
6948 udelay(40);
6949
6950 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6951 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6952 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 6953
6954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
6955 tw32(SNDDATAC_MODE,
6956 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
6957 else
6958 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6959
1da177e4
LT		 6960 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6961 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6962 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6963 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 6964 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6965 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 6966 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6967 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6968
6969 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6970 err = tg3_load_5701_a0_firmware_fix(tp);
6971 if (err)
6972 return err;
6973 }
6974
1da177e4
LT		 6975 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6976 err = tg3_load_tso_firmware(tp);
6977 if (err)
6978 return err;
6979 }
1da177e4
LT		 6980
6981 tp->tx_mode = TX_MODE_ENABLE;
6982 tw32_f(MAC_TX_MODE, tp->tx_mode);
6983 udelay(100);
6984
6985 tp->rx_mode = RX_MODE_ENABLE;
9936bcf6
MC		 6986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
6987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
af36e6b6
MC		 6988 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6989
1da177e4
LT		 6990 tw32_f(MAC_RX_MODE, tp->rx_mode);
6991 udelay(10);
6992
6993 if (tp->link_config.phy_is_low_power) {
6994 tp->link_config.phy_is_low_power = 0;
6995 tp->link_config.speed = tp->link_config.orig_speed;
6996 tp->link_config.duplex = tp->link_config.orig_duplex;
6997 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6998 }
6999
7000 tp->mi_mode = MAC_MI_MODE_BASE;
7001 tw32_f(MAC_MI_MODE, tp->mi_mode);
7002 udelay(80);
7003
7004 tw32(MAC_LED_CTRL, tp->led_ctrl);
7005
7006 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7007 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7008 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7009 udelay(10);
7010 }
7011 tw32_f(MAC_RX_MODE, tp->rx_mode);
7012 udelay(10);
7013
7014 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7015 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7016 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7017 /* Set drive transmission level to 1.2V */
7018 /* only if the signal pre-emphasis bit is not set */
7019 val = tr32(MAC_SERDES_CFG);
7020 val &= 0xfffff000;
7021 val |= 0x880;
7022 tw32(MAC_SERDES_CFG, val);
7023 }
7024 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7025 tw32(MAC_SERDES_CFG, 0x616000);
7026 }
7027
7028 /* Prevent chip from dropping frames when flow control
7029 * is enabled.
7030 */
7031 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7032
7033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7034 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7035 /* Use hardware link auto-negotiation */
7036 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7037 }
7038
d4d2c558
MC		 7039 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7040 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7041 u32 tmp;
7042
7043 tmp = tr32(SERDES_RX_CTRL);
7044 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7045 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7046 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7047 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7048 }
7049
36da4d86 7050 err = tg3_setup_phy(tp, 0);
1da177e4
LT		 7051 if (err)
7052 return err;
7053
715116a1
MC		 7054 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7055 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1da177e4
LT		 7056 u32 tmp;
7057
7058 /* Clear CRC stats. */
569a5df8
MC		 7059 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7060 tg3_writephy(tp, MII_TG3_TEST1,
7061 tmp | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 7062 tg3_readphy(tp, 0x14, &tmp);
7063 }
7064 }
7065
7066 __tg3_set_rx_mode(tp->dev);
7067
7068 /* Initialize receive rules. */
7069 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7070 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7071 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7072 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7073
4cf78e4f 7074 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7075 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7076 limit = 8;
7077 else
7078 limit = 16;
7079 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7080 limit -= 4;
7081 switch (limit) {
7082 case 16:
7083 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7084 case 15:
7085 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7086 case 14:
7087 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7088 case 13:
7089 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7090 case 12:
7091 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7092 case 11:
7093 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7094 case 10:
7095 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7096 case 9:
7097 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7098 case 8:
7099 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7100 case 7:
7101 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7102 case 6:
7103 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7104 case 5:
7105 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7106 case 4:
7107 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7108 case 3:
7109 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7110 case 2:
7111 case 1:
7112
7113 default:
7114 break;
7115 };
7116
9ce768ea
MC		 7117 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7118 /* Write our heartbeat update interval to APE. */
7119 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7120 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7121
1da177e4
LT		 7122 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7123
1da177e4
LT		 7124 return 0;
7125}
7126
7127/* Called at device open time to get the chip ready for
7128 * packet processing. Invoked with tp->lock held.
7129 */
8e7a22e3 7130static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7131{
7132 int err;
7133
7134 /* Force the chip into D0. */
bc1c7567 7135 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 7136 if (err)
7137 goto out;
7138
7139 tg3_switch_clocks(tp);
7140
7141 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7142
8e7a22e3 7143 err = tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7144
7145out:
7146 return err;
7147}
7148
7149#define TG3_STAT_ADD32(PSTAT, REG) \
7150do { u32 __val = tr32(REG); \
7151 (PSTAT)->low += __val; \
7152 if ((PSTAT)->low < __val) \
7153 (PSTAT)->high += 1; \
7154} while (0)
7155
7156static void tg3_periodic_fetch_stats(struct tg3 *tp)
7157{
7158 struct tg3_hw_stats *sp = tp->hw_stats;
7159
7160 if (!netif_carrier_ok(tp->dev))
7161 return;
7162
7163 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7164 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7165 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7166 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7167 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7168 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7169 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7170 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7171 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7172 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7173 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7174 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7175 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7176
7177 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7178 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7179 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7180 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7181 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7182 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7183 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7184 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7185 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7186 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7187 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7188 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7189 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7190 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7191
7192 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7193 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7194 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7195}
7196
7197static void tg3_timer(unsigned long __opaque)
7198{
7199 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7200
f475f163
MC		 7201 if (tp->irq_sync)
7202 goto restart_timer;
7203
f47c11ee 7204 spin_lock(&tp->lock);
1da177e4 7205
fac9b83e
DM		 7206 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7207 /* All of this garbage is because when using non-tagged
7208 * IRQ status the mailbox/status_block protocol the chip
7209 * uses with the cpu is race prone.
7210 */
7211 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7212 tw32(GRC_LOCAL_CTRL,
7213 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7214 } else {
7215 tw32(HOSTCC_MODE, tp->coalesce_mode |
7216 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7217 }
1da177e4 7218
fac9b83e
DM		 7219 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7220 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7221 spin_unlock(&tp->lock);
fac9b83e
DM		 7222 schedule_work(&tp->reset_task);
7223 return;
7224 }
1da177e4
LT		 7225 }
7226
1da177e4
LT		 7227 /* This part only runs once per second. */
7228 if (!--tp->timer_counter) {
fac9b83e
DM		 7229 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7230 tg3_periodic_fetch_stats(tp);
7231
1da177e4
LT		 7232 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7233 u32 mac_stat;
7234 int phy_event;
7235
7236 mac_stat = tr32(MAC_STATUS);
7237
7238 phy_event = 0;
7239 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7240 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7241 phy_event = 1;
7242 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7243 phy_event = 1;
7244
7245 if (phy_event)
7246 tg3_setup_phy(tp, 0);
7247 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7248 u32 mac_stat = tr32(MAC_STATUS);
7249 int need_setup = 0;
7250
7251 if (netif_carrier_ok(tp->dev) &&
7252 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7253 need_setup = 1;
7254 }
7255 if (! netif_carrier_ok(tp->dev) &&
7256 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7257 MAC_STATUS_SIGNAL_DET))) {
7258 need_setup = 1;
7259 }
7260 if (need_setup) {
3d3ebe74
MC		 7261 if (!tp->serdes_counter) {
7262 tw32_f(MAC_MODE,
7263 (tp->mac_mode &
7264 ~MAC_MODE_PORT_MODE_MASK));
7265 udelay(40);
7266 tw32_f(MAC_MODE, tp->mac_mode);
7267 udelay(40);
7268 }
1da177e4
LT		 7269 tg3_setup_phy(tp, 0);
7270 }
747e8f8b
MC		 7271 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7272 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7273
7274 tp->timer_counter = tp->timer_multiplier;
7275 }
7276
130b8e4d
MC		 7277 /* Heartbeat is only sent once every 2 seconds.
7278 *
7279 * The heartbeat is to tell the ASF firmware that the host
7280 * driver is still alive. In the event that the OS crashes,
7281 * ASF needs to reset the hardware to free up the FIFO space
7282 * that may be filled with rx packets destined for the host.
7283 * If the FIFO is full, ASF will no longer function properly.
7284 *
7285 * Unintended resets have been reported on real time kernels
7286 * where the timer doesn't run on time. Netpoll will also have
7287 * same problem.
7288 *
7289 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7290 * to check the ring condition when the heartbeat is expiring
7291 * before doing the reset. This will prevent most unintended
7292 * resets.
7293 */
1da177e4
LT		 7294 if (!--tp->asf_counter) {
7295 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7296 u32 val;
7297
bbadf503 7298 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7299 FWCMD_NICDRV_ALIVE3);
bbadf503 7300 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7301 /* 5 seconds timeout */
bbadf503 7302 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 7303 val = tr32(GRC_RX_CPU_EVENT);
7304 val |= (1 << 14);
7305 tw32(GRC_RX_CPU_EVENT, val);
7306 }
7307 tp->asf_counter = tp->asf_multiplier;
7308 }
7309
f47c11ee 7310 spin_unlock(&tp->lock);
1da177e4 7311
f475f163 7312restart_timer:
1da177e4
LT		 7313 tp->timer.expires = jiffies + tp->timer_offset;
7314 add_timer(&tp->timer);
7315}
7316
81789ef5 7317static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7318{
7d12e780 7319 irq_handler_t fn;
fcfa0a32
MC		 7320 unsigned long flags;
7321 struct net_device *dev = tp->dev;
7322
7323 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7324 fn = tg3_msi;
7325 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7326 fn = tg3_msi_1shot;
1fb9df5d 7327 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7328 } else {
7329 fn = tg3_interrupt;
7330 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7331 fn = tg3_interrupt_tagged;
1fb9df5d 7332 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7333 }
7334 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7335}
7336
7938109f
MC		 7337static int tg3_test_interrupt(struct tg3 *tp)
7338{
7339 struct net_device *dev = tp->dev;
b16250e3 7340 int err, i, intr_ok = 0;
7938109f 7341
d4bc3927
MC		 7342 if (!netif_running(dev))
7343 return -ENODEV;
7344
7938109f
MC		 7345 tg3_disable_ints(tp);
7346
7347 free_irq(tp->pdev->irq, dev);
7348
7349 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7350 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7351 if (err)
7352 return err;
7353
38f3843e 7354 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7355 tg3_enable_ints(tp);
7356
7357 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7358 HOSTCC_MODE_NOW);
7359
7360 for (i = 0; i < 5; i++) {
b16250e3
MC		 7361 u32 int_mbox, misc_host_ctrl;
7362
09ee929c
MC		 7363 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7364 TG3_64BIT_REG_LOW);
b16250e3
MC		 7365 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7366
7367 if ((int_mbox != 0) ||
7368 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7369 intr_ok = 1;
7938109f 7370 break;
b16250e3
MC		 7371 }
7372
7938109f
MC		 7373 msleep(10);
7374 }
7375
7376 tg3_disable_ints(tp);
7377
7378 free_irq(tp->pdev->irq, dev);
6aa20a22 7379
fcfa0a32 7380 err = tg3_request_irq(tp);
7938109f
MC		 7381
7382 if (err)
7383 return err;
7384
b16250e3 7385 if (intr_ok)
7938109f
MC		 7386 return 0;
7387
7388 return -EIO;
7389}
7390
7391/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7392 * successfully restored
7393 */
7394static int tg3_test_msi(struct tg3 *tp)
7395{
7396 struct net_device *dev = tp->dev;
7397 int err;
7398 u16 pci_cmd;
7399
7400 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7401 return 0;
7402
7403 /* Turn off SERR reporting in case MSI terminates with Master
7404 * Abort.
7405 */
7406 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7407 pci_write_config_word(tp->pdev, PCI_COMMAND,
7408 pci_cmd & ~PCI_COMMAND_SERR);
7409
7410 err = tg3_test_interrupt(tp);
7411
7412 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7413
7414 if (!err)
7415 return 0;
7416
7417 /* other failures */
7418 if (err != -EIO)
7419 return err;
7420
7421 /* MSI test failed, go back to INTx mode */
7422 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7423 "switching to INTx mode. Please report this failure to "
7424 "the PCI maintainer and include system chipset information.\n",
7425 tp->dev->name);
7426
7427 free_irq(tp->pdev->irq, dev);
7428 pci_disable_msi(tp->pdev);
7429
7430 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7431
fcfa0a32 7432 err = tg3_request_irq(tp);
7938109f
MC		 7433 if (err)
7434 return err;
7435
7436 /* Need to reset the chip because the MSI cycle may have terminated
7437 * with Master Abort.
7438 */
f47c11ee 7439 tg3_full_lock(tp, 1);
7938109f 7440
944d980e 7441 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7442 err = tg3_init_hw(tp, 1);
7938109f 7443
f47c11ee 7444 tg3_full_unlock(tp);
7938109f
MC		 7445
7446 if (err)
7447 free_irq(tp->pdev->irq, dev);
7448
7449 return err;
7450}
7451
1da177e4
LT		 7452static int tg3_open(struct net_device *dev)
7453{
7454 struct tg3 *tp = netdev_priv(dev);
7455 int err;
7456
c49a1561
MC		 7457 netif_carrier_off(tp->dev);
7458
f47c11ee 7459 tg3_full_lock(tp, 0);
1da177e4 7460
bc1c7567 7461 err = tg3_set_power_state(tp, PCI_D0);
12862086
IS		 7462 if (err) {
7463 tg3_full_unlock(tp);
bc1c7567 7464 return err;
12862086 7465 }
bc1c7567 7466
1da177e4
LT		 7467 tg3_disable_ints(tp);
7468 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7469
f47c11ee 7470 tg3_full_unlock(tp);
1da177e4
LT		 7471
7472 /* The placement of this call is tied
7473 * to the setup and use of Host TX descriptors.
7474 */
7475 err = tg3_alloc_consistent(tp);
7476 if (err)
7477 return err;
7478
7544b097 7479 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7480 /* All MSI supporting chips should support tagged
7481 * status. Assert that this is the case.
7482 */
7483 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7484 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7485 "Not using MSI.\n", tp->dev->name);
7486 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7487 u32 msi_mode;
7488
7489 msi_mode = tr32(MSGINT_MODE);
7490 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7491 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7492 }
7493 }
fcfa0a32 7494 err = tg3_request_irq(tp);
1da177e4
LT		 7495
7496 if (err) {
88b06bc2
MC		 7497 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7498 pci_disable_msi(tp->pdev);
7499 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7500 }
1da177e4
LT		 7501 tg3_free_consistent(tp);
7502 return err;
7503 }
7504
bea3348e
SH		 7505 napi_enable(&tp->napi);
7506
f47c11ee 7507 tg3_full_lock(tp, 0);
1da177e4 7508
8e7a22e3 7509 err = tg3_init_hw(tp, 1);
1da177e4 7510 if (err) {
944d980e 7511 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7512 tg3_free_rings(tp);
7513 } else {
fac9b83e
DM		 7514 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7515 tp->timer_offset = HZ;
7516 else
7517 tp->timer_offset = HZ / 10;
7518
7519 BUG_ON(tp->timer_offset > HZ);
7520 tp->timer_counter = tp->timer_multiplier =
7521 (HZ / tp->timer_offset);
7522 tp->asf_counter = tp->asf_multiplier =
28fbef78 7523 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7524
7525 init_timer(&tp->timer);
7526 tp->timer.expires = jiffies + tp->timer_offset;
7527 tp->timer.data = (unsigned long) tp;
7528 tp->timer.function = tg3_timer;
1da177e4
LT		 7529 }
7530
f47c11ee 7531 tg3_full_unlock(tp);
1da177e4
LT		 7532
7533 if (err) {
bea3348e 7534 napi_disable(&tp->napi);
88b06bc2
MC		 7535 free_irq(tp->pdev->irq, dev);
7536 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7537 pci_disable_msi(tp->pdev);
7538 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7539 }
1da177e4
LT		 7540 tg3_free_consistent(tp);
7541 return err;
7542 }
7543
7938109f
MC		 7544 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7545 err = tg3_test_msi(tp);
fac9b83e 7546
7938109f 7547 if (err) {
f47c11ee 7548 tg3_full_lock(tp, 0);
7938109f
MC		 7549
7550 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7551 pci_disable_msi(tp->pdev);
7552 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7553 }
944d980e 7554 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7555 tg3_free_rings(tp);
7556 tg3_free_consistent(tp);
7557
f47c11ee 7558 tg3_full_unlock(tp);
7938109f 7559
bea3348e
SH		 7560 napi_disable(&tp->napi);
7561
7938109f
MC		 7562 return err;
7563 }
fcfa0a32
MC		 7564
7565 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7566 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7567 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7568
b5d3772c
MC		 7569 tw32(PCIE_TRANSACTION_CFG,
7570 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7571 }
7572 }
7938109f
MC		 7573 }
7574
f47c11ee 7575 tg3_full_lock(tp, 0);
1da177e4 7576
7938109f
MC		 7577 add_timer(&tp->timer);
7578 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7579 tg3_enable_ints(tp);
7580
f47c11ee 7581 tg3_full_unlock(tp);
1da177e4
LT		 7582
7583 netif_start_queue(dev);
7584
7585 return 0;
7586}
7587
7588#if 0
7589/*static*/ void tg3_dump_state(struct tg3 *tp)
7590{
7591 u32 val32, val32_2, val32_3, val32_4, val32_5;
7592 u16 val16;
7593 int i;
7594
7595 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7596 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7597 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7598 val16, val32);
7599
7600 /* MAC block */
7601 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7602 tr32(MAC_MODE), tr32(MAC_STATUS));
7603 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7604 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7605 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7606 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7607 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7608 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7609
7610 /* Send data initiator control block */
7611 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7612 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7613 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7614 tr32(SNDDATAI_STATSCTRL));
7615
7616 /* Send data completion control block */
7617 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7618
7619 /* Send BD ring selector block */
7620 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7621 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7622
7623 /* Send BD initiator control block */
7624 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7625 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7626
7627 /* Send BD completion control block */
7628 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7629
7630 /* Receive list placement control block */
7631 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7632 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7633 printk(" RCVLPC_STATSCTRL[%08x]\n",
7634 tr32(RCVLPC_STATSCTRL));
7635
7636 /* Receive data and receive BD initiator control block */
7637 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7638 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7639
7640 /* Receive data completion control block */
7641 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7642 tr32(RCVDCC_MODE));
7643
7644 /* Receive BD initiator control block */
7645 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7646 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7647
7648 /* Receive BD completion control block */
7649 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7650 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7651
7652 /* Receive list selector control block */
7653 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7654 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7655
7656 /* Mbuf cluster free block */
7657 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7658 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7659
7660 /* Host coalescing control block */
7661 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7662 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7663 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7664 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7665 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7666 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7667 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7668 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7669 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7670 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7671 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7672 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7673
7674 /* Memory arbiter control block */
7675 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7676 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7677
7678 /* Buffer manager control block */
7679 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7680 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7681 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7682 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7683 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7684 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7685 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7686 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7687
7688 /* Read DMA control block */
7689 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7690 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7691
7692 /* Write DMA control block */
7693 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7694 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7695
7696 /* DMA completion block */
7697 printk("DEBUG: DMAC_MODE[%08x]\n",
7698 tr32(DMAC_MODE));
7699
7700 /* GRC block */
7701 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7702 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7703 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7704 tr32(GRC_LOCAL_CTRL));
7705
7706 /* TG3_BDINFOs */
7707 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7708 tr32(RCVDBDI_JUMBO_BD + 0x0),
7709 tr32(RCVDBDI_JUMBO_BD + 0x4),
7710 tr32(RCVDBDI_JUMBO_BD + 0x8),
7711 tr32(RCVDBDI_JUMBO_BD + 0xc));
7712 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7713 tr32(RCVDBDI_STD_BD + 0x0),
7714 tr32(RCVDBDI_STD_BD + 0x4),
7715 tr32(RCVDBDI_STD_BD + 0x8),
7716 tr32(RCVDBDI_STD_BD + 0xc));
7717 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7718 tr32(RCVDBDI_MINI_BD + 0x0),
7719 tr32(RCVDBDI_MINI_BD + 0x4),
7720 tr32(RCVDBDI_MINI_BD + 0x8),
7721 tr32(RCVDBDI_MINI_BD + 0xc));
7722
7723 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7724 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7725 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7726 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7727 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7728 val32, val32_2, val32_3, val32_4);
7729
7730 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7731 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7732 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7733 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7734 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7735 val32, val32_2, val32_3, val32_4);
7736
7737 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7738 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7739 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7740 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7741 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7742 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7743 val32, val32_2, val32_3, val32_4, val32_5);
7744
7745 /* SW status block */
7746 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7747 tp->hw_status->status,
7748 tp->hw_status->status_tag,
7749 tp->hw_status->rx_jumbo_consumer,
7750 tp->hw_status->rx_consumer,
7751 tp->hw_status->rx_mini_consumer,
7752 tp->hw_status->idx[0].rx_producer,
7753 tp->hw_status->idx[0].tx_consumer);
7754
7755 /* SW statistics block */
7756 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7757 ((u32 *)tp->hw_stats)[0],
7758 ((u32 *)tp->hw_stats)[1],
7759 ((u32 *)tp->hw_stats)[2],
7760 ((u32 *)tp->hw_stats)[3]);
7761
7762 /* Mailboxes */
7763 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7764 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7765 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7766 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7767 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7768
7769 /* NIC side send descriptors. */
7770 for (i = 0; i < 6; i++) {
7771 unsigned long txd;
7772
7773 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7774 + (i * sizeof(struct tg3_tx_buffer_desc));
7775 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7776 i,
7777 readl(txd + 0x0), readl(txd + 0x4),
7778 readl(txd + 0x8), readl(txd + 0xc));
7779 }
7780
7781 /* NIC side RX descriptors. */
7782 for (i = 0; i < 6; i++) {
7783 unsigned long rxd;
7784
7785 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7786 + (i * sizeof(struct tg3_rx_buffer_desc));
7787 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7788 i,
7789 readl(rxd + 0x0), readl(rxd + 0x4),
7790 readl(rxd + 0x8), readl(rxd + 0xc));
7791 rxd += (4 * sizeof(u32));
7792 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7793 i,
7794 readl(rxd + 0x0), readl(rxd + 0x4),
7795 readl(rxd + 0x8), readl(rxd + 0xc));
7796 }
7797
7798 for (i = 0; i < 6; i++) {
7799 unsigned long rxd;
7800
7801 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7802 + (i * sizeof(struct tg3_rx_buffer_desc));
7803 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7804 i,
7805 readl(rxd + 0x0), readl(rxd + 0x4),
7806 readl(rxd + 0x8), readl(rxd + 0xc));
7807 rxd += (4 * sizeof(u32));
7808 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7809 i,
7810 readl(rxd + 0x0), readl(rxd + 0x4),
7811 readl(rxd + 0x8), readl(rxd + 0xc));
7812 }
7813}
7814#endif
7815
7816static struct net_device_stats *tg3_get_stats(struct net_device *);
7817static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7818
7819static int tg3_close(struct net_device *dev)
7820{
7821 struct tg3 *tp = netdev_priv(dev);
7822
bea3348e 7823 napi_disable(&tp->napi);
28e53bdd 7824 cancel_work_sync(&tp->reset_task);
7faa006f 7825
1da177e4
LT		 7826 netif_stop_queue(dev);
7827
7828 del_timer_sync(&tp->timer);
7829
f47c11ee 7830 tg3_full_lock(tp, 1);
1da177e4
LT		 7831#if 0
7832 tg3_dump_state(tp);
7833#endif
7834
7835 tg3_disable_ints(tp);
7836
944d980e 7837 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 7838 tg3_free_rings(tp);
5cf64b8a 7839 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 7840
f47c11ee 7841 tg3_full_unlock(tp);
1da177e4 7842
88b06bc2
MC		 7843 free_irq(tp->pdev->irq, dev);
7844 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7845 pci_disable_msi(tp->pdev);
7846 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7847 }
1da177e4
LT		 7848
7849 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7850 sizeof(tp->net_stats_prev));
7851 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7852 sizeof(tp->estats_prev));
7853
7854 tg3_free_consistent(tp);
7855
bc1c7567
MC		 7856 tg3_set_power_state(tp, PCI_D3hot);
7857
7858 netif_carrier_off(tp->dev);
7859
1da177e4
LT		 7860 return 0;
7861}
7862
7863static inline unsigned long get_stat64(tg3_stat64_t *val)
7864{
7865 unsigned long ret;
7866
7867#if (BITS_PER_LONG == 32)
7868 ret = val->low;
7869#else
7870 ret = ((u64)val->high << 32) | ((u64)val->low);
7871#endif
7872 return ret;
7873}
7874
7875static unsigned long calc_crc_errors(struct tg3 *tp)
7876{
7877 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7878
7879 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7880 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7881 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 7882 u32 val;
7883
f47c11ee 7884 spin_lock_bh(&tp->lock);
569a5df8
MC		 7885 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7886 tg3_writephy(tp, MII_TG3_TEST1,
7887 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 7888 tg3_readphy(tp, 0x14, &val);
7889 } else
7890 val = 0;
f47c11ee 7891 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7892
7893 tp->phy_crc_errors += val;
7894
7895 return tp->phy_crc_errors;
7896 }
7897
7898 return get_stat64(&hw_stats->rx_fcs_errors);
7899}
7900
7901#define ESTAT_ADD(member) \
7902 estats->member = old_estats->member + \
7903 get_stat64(&hw_stats->member)
7904
7905static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7906{
7907 struct tg3_ethtool_stats *estats = &tp->estats;
7908 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7909 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7910
7911 if (!hw_stats)
7912 return old_estats;
7913
7914 ESTAT_ADD(rx_octets);
7915 ESTAT_ADD(rx_fragments);
7916 ESTAT_ADD(rx_ucast_packets);
7917 ESTAT_ADD(rx_mcast_packets);
7918 ESTAT_ADD(rx_bcast_packets);
7919 ESTAT_ADD(rx_fcs_errors);
7920 ESTAT_ADD(rx_align_errors);
7921 ESTAT_ADD(rx_xon_pause_rcvd);
7922 ESTAT_ADD(rx_xoff_pause_rcvd);
7923 ESTAT_ADD(rx_mac_ctrl_rcvd);
7924 ESTAT_ADD(rx_xoff_entered);
7925 ESTAT_ADD(rx_frame_too_long_errors);
7926 ESTAT_ADD(rx_jabbers);
7927 ESTAT_ADD(rx_undersize_packets);
7928 ESTAT_ADD(rx_in_length_errors);
7929 ESTAT_ADD(rx_out_length_errors);
7930 ESTAT_ADD(rx_64_or_less_octet_packets);
7931 ESTAT_ADD(rx_65_to_127_octet_packets);
7932 ESTAT_ADD(rx_128_to_255_octet_packets);
7933 ESTAT_ADD(rx_256_to_511_octet_packets);
7934 ESTAT_ADD(rx_512_to_1023_octet_packets);
7935 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7936 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7937 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7938 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7939 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7940
7941 ESTAT_ADD(tx_octets);
7942 ESTAT_ADD(tx_collisions);
7943 ESTAT_ADD(tx_xon_sent);
7944 ESTAT_ADD(tx_xoff_sent);
7945 ESTAT_ADD(tx_flow_control);
7946 ESTAT_ADD(tx_mac_errors);
7947 ESTAT_ADD(tx_single_collisions);
7948 ESTAT_ADD(tx_mult_collisions);
7949 ESTAT_ADD(tx_deferred);
7950 ESTAT_ADD(tx_excessive_collisions);
7951 ESTAT_ADD(tx_late_collisions);
7952 ESTAT_ADD(tx_collide_2times);
7953 ESTAT_ADD(tx_collide_3times);
7954 ESTAT_ADD(tx_collide_4times);
7955 ESTAT_ADD(tx_collide_5times);
7956 ESTAT_ADD(tx_collide_6times);
7957 ESTAT_ADD(tx_collide_7times);
7958 ESTAT_ADD(tx_collide_8times);
7959 ESTAT_ADD(tx_collide_9times);
7960 ESTAT_ADD(tx_collide_10times);
7961 ESTAT_ADD(tx_collide_11times);
7962 ESTAT_ADD(tx_collide_12times);
7963 ESTAT_ADD(tx_collide_13times);
7964 ESTAT_ADD(tx_collide_14times);
7965 ESTAT_ADD(tx_collide_15times);
7966 ESTAT_ADD(tx_ucast_packets);
7967 ESTAT_ADD(tx_mcast_packets);
7968 ESTAT_ADD(tx_bcast_packets);
7969 ESTAT_ADD(tx_carrier_sense_errors);
7970 ESTAT_ADD(tx_discards);
7971 ESTAT_ADD(tx_errors);
7972
7973 ESTAT_ADD(dma_writeq_full);
7974 ESTAT_ADD(dma_write_prioq_full);
7975 ESTAT_ADD(rxbds_empty);
7976 ESTAT_ADD(rx_discards);
7977 ESTAT_ADD(rx_errors);
7978 ESTAT_ADD(rx_threshold_hit);
7979
7980 ESTAT_ADD(dma_readq_full);
7981 ESTAT_ADD(dma_read_prioq_full);
7982 ESTAT_ADD(tx_comp_queue_full);
7983
7984 ESTAT_ADD(ring_set_send_prod_index);
7985 ESTAT_ADD(ring_status_update);
7986 ESTAT_ADD(nic_irqs);
7987 ESTAT_ADD(nic_avoided_irqs);
7988 ESTAT_ADD(nic_tx_threshold_hit);
7989
7990 return estats;
7991}
7992
7993static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7994{
7995 struct tg3 *tp = netdev_priv(dev);
7996 struct net_device_stats *stats = &tp->net_stats;
7997 struct net_device_stats *old_stats = &tp->net_stats_prev;
7998 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7999
8000 if (!hw_stats)
8001 return old_stats;
8002
8003 stats->rx_packets = old_stats->rx_packets +
8004 get_stat64(&hw_stats->rx_ucast_packets) +
8005 get_stat64(&hw_stats->rx_mcast_packets) +
8006 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8007
1da177e4
LT		 8008 stats->tx_packets = old_stats->tx_packets +
8009 get_stat64(&hw_stats->tx_ucast_packets) +
8010 get_stat64(&hw_stats->tx_mcast_packets) +
8011 get_stat64(&hw_stats->tx_bcast_packets);
8012
8013 stats->rx_bytes = old_stats->rx_bytes +
8014 get_stat64(&hw_stats->rx_octets);
8015 stats->tx_bytes = old_stats->tx_bytes +
8016 get_stat64(&hw_stats->tx_octets);
8017
8018 stats->rx_errors = old_stats->rx_errors +
4f63b877 8019 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8020 stats->tx_errors = old_stats->tx_errors +
8021 get_stat64(&hw_stats->tx_errors) +
8022 get_stat64(&hw_stats->tx_mac_errors) +
8023 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8024 get_stat64(&hw_stats->tx_discards);
8025
8026 stats->multicast = old_stats->multicast +
8027 get_stat64(&hw_stats->rx_mcast_packets);
8028 stats->collisions = old_stats->collisions +
8029 get_stat64(&hw_stats->tx_collisions);
8030
8031 stats->rx_length_errors = old_stats->rx_length_errors +
8032 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8033 get_stat64(&hw_stats->rx_undersize_packets);
8034
8035 stats->rx_over_errors = old_stats->rx_over_errors +
8036 get_stat64(&hw_stats->rxbds_empty);
8037 stats->rx_frame_errors = old_stats->rx_frame_errors +
8038 get_stat64(&hw_stats->rx_align_errors);
8039 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8040 get_stat64(&hw_stats->tx_discards);
8041 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8042 get_stat64(&hw_stats->tx_carrier_sense_errors);
8043
8044 stats->rx_crc_errors = old_stats->rx_crc_errors +
8045 calc_crc_errors(tp);
8046
4f63b877
JL		 8047 stats->rx_missed_errors = old_stats->rx_missed_errors +
8048 get_stat64(&hw_stats->rx_discards);
8049
1da177e4
LT		 8050 return stats;
8051}
8052
8053static inline u32 calc_crc(unsigned char *buf, int len)
8054{
8055 u32 reg;
8056 u32 tmp;
8057 int j, k;
8058
8059 reg = 0xffffffff;
8060
8061 for (j = 0; j < len; j++) {
8062 reg ^= buf[j];
8063
8064 for (k = 0; k < 8; k++) {
8065 tmp = reg & 0x01;
8066
8067 reg >>= 1;
8068
8069 if (tmp) {
8070 reg ^= 0xedb88320;
8071 }
8072 }
8073 }
8074
8075 return ~reg;
8076}
8077
8078static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8079{
8080 /* accept or reject all multicast frames */
8081 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8082 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8083 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8084 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8085}
8086
8087static void __tg3_set_rx_mode(struct net_device *dev)
8088{
8089 struct tg3 *tp = netdev_priv(dev);
8090 u32 rx_mode;
8091
8092 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8093 RX_MODE_KEEP_VLAN_TAG);
8094
8095 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8096 * flag clear.
8097 */
8098#if TG3_VLAN_TAG_USED
8099 if (!tp->vlgrp &&
8100 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8101 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8102#else
8103 /* By definition, VLAN is disabled always in this
8104 * case.
8105 */
8106 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8107 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8108#endif
8109
8110 if (dev->flags & IFF_PROMISC) {
8111 /* Promiscuous mode. */
8112 rx_mode |= RX_MODE_PROMISC;
8113 } else if (dev->flags & IFF_ALLMULTI) {
8114 /* Accept all multicast. */
8115 tg3_set_multi (tp, 1);
8116 } else if (dev->mc_count < 1) {
8117 /* Reject all multicast. */
8118 tg3_set_multi (tp, 0);
8119 } else {
8120 /* Accept one or more multicast(s). */
8121 struct dev_mc_list *mclist;
8122 unsigned int i;
8123 u32 mc_filter[4] = { 0, };
8124 u32 regidx;
8125 u32 bit;
8126 u32 crc;
8127
8128 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8129 i++, mclist = mclist->next) {
8130
8131 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8132 bit = ~crc & 0x7f;
8133 regidx = (bit & 0x60) >> 5;
8134 bit &= 0x1f;
8135 mc_filter[regidx] |= (1 << bit);
8136 }
8137
8138 tw32(MAC_HASH_REG_0, mc_filter[0]);
8139 tw32(MAC_HASH_REG_1, mc_filter[1]);
8140 tw32(MAC_HASH_REG_2, mc_filter[2]);
8141 tw32(MAC_HASH_REG_3, mc_filter[3]);
8142 }
8143
8144 if (rx_mode != tp->rx_mode) {
8145 tp->rx_mode = rx_mode;
8146 tw32_f(MAC_RX_MODE, rx_mode);
8147 udelay(10);
8148 }
8149}
8150
8151static void tg3_set_rx_mode(struct net_device *dev)
8152{
8153 struct tg3 *tp = netdev_priv(dev);
8154
e75f7c90
MC		 8155 if (!netif_running(dev))
8156 return;
8157
f47c11ee 8158 tg3_full_lock(tp, 0);
1da177e4 8159 __tg3_set_rx_mode(dev);
f47c11ee 8160 tg3_full_unlock(tp);
1da177e4
LT		 8161}
8162
8163#define TG3_REGDUMP_LEN (32 * 1024)
8164
8165static int tg3_get_regs_len(struct net_device *dev)
8166{
8167 return TG3_REGDUMP_LEN;
8168}
8169
8170static void tg3_get_regs(struct net_device *dev,
8171 struct ethtool_regs *regs, void *_p)
8172{
8173 u32 *p = _p;
8174 struct tg3 *tp = netdev_priv(dev);
8175 u8 *orig_p = _p;
8176 int i;
8177
8178 regs->version = 0;
8179
8180 memset(p, 0, TG3_REGDUMP_LEN);
8181
bc1c7567
MC		 8182 if (tp->link_config.phy_is_low_power)
8183 return;
8184
f47c11ee 8185 tg3_full_lock(tp, 0);
1da177e4
LT		 8186
8187#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8188#define GET_REG32_LOOP(base,len) \
8189do { p = (u32 *)(orig_p + (base)); \
8190 for (i = 0; i < len; i += 4) \
8191 __GET_REG32((base) + i); \
8192} while (0)
8193#define GET_REG32_1(reg) \
8194do { p = (u32 *)(orig_p + (reg)); \
8195 __GET_REG32((reg)); \
8196} while (0)
8197
8198 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8199 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8200 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8201 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8202 GET_REG32_1(SNDDATAC_MODE);
8203 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8204 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8205 GET_REG32_1(SNDBDC_MODE);
8206 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8207 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8208 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8209 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8210 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8211 GET_REG32_1(RCVDCC_MODE);
8212 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8213 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8214 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8215 GET_REG32_1(MBFREE_MODE);
8216 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8217 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8218 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8219 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8220 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8221 GET_REG32_1(RX_CPU_MODE);
8222 GET_REG32_1(RX_CPU_STATE);
8223 GET_REG32_1(RX_CPU_PGMCTR);
8224 GET_REG32_1(RX_CPU_HWBKPT);
8225 GET_REG32_1(TX_CPU_MODE);
8226 GET_REG32_1(TX_CPU_STATE);
8227 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8228 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8229 GET_REG32_LOOP(FTQ_RESET, 0x120);
8230 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8231 GET_REG32_1(DMAC_MODE);
8232 GET_REG32_LOOP(GRC_MODE, 0x4c);
8233 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8234 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8235
8236#undef __GET_REG32
8237#undef GET_REG32_LOOP
8238#undef GET_REG32_1
8239
f47c11ee 8240 tg3_full_unlock(tp);
1da177e4
LT		 8241}
8242
8243static int tg3_get_eeprom_len(struct net_device *dev)
8244{
8245 struct tg3 *tp = netdev_priv(dev);
8246
8247 return tp->nvram_size;
8248}
8249
8250static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
b9fc7dc5 8251static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
1820180b 8252static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 8253
8254static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8255{
8256 struct tg3 *tp = netdev_priv(dev);
8257 int ret;
8258 u8 *pd;
b9fc7dc5
AV		 8259 u32 i, offset, len, b_offset, b_count;
8260 __le32 val;
1da177e4 8261
bc1c7567
MC		 8262 if (tp->link_config.phy_is_low_power)
8263 return -EAGAIN;
8264
1da177e4
LT		 8265 offset = eeprom->offset;
8266 len = eeprom->len;
8267 eeprom->len = 0;
8268
8269 eeprom->magic = TG3_EEPROM_MAGIC;
8270
8271 if (offset & 3) {
8272 /* adjustments to start on required 4 byte boundary */
8273 b_offset = offset & 3;
8274 b_count = 4 - b_offset;
8275 if (b_count > len) {
8276 /* i.e. offset=1 len=2 */
8277 b_count = len;
8278 }
b9fc7dc5 8279 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
1da177e4
LT		 8280 if (ret)
8281 return ret;
1da177e4
LT		 8282 memcpy(data, ((char*)&val) + b_offset, b_count);
8283 len -= b_count;
8284 offset += b_count;
8285 eeprom->len += b_count;
8286 }
8287
8288 /* read bytes upto the last 4 byte boundary */
8289 pd = &data[eeprom->len];
8290 for (i = 0; i < (len - (len & 3)); i += 4) {
b9fc7dc5 8291 ret = tg3_nvram_read_le(tp, offset + i, &val);
1da177e4
LT		 8292 if (ret) {
8293 eeprom->len += i;
8294 return ret;
8295 }
1da177e4
LT		 8296 memcpy(pd + i, &val, 4);
8297 }
8298 eeprom->len += i;
8299
8300 if (len & 3) {
8301 /* read last bytes not ending on 4 byte boundary */
8302 pd = &data[eeprom->len];
8303 b_count = len & 3;
8304 b_offset = offset + len - b_count;
b9fc7dc5 8305 ret = tg3_nvram_read_le(tp, b_offset, &val);
1da177e4
LT		 8306 if (ret)
8307 return ret;
b9fc7dc5 8308 memcpy(pd, &val, b_count);
1da177e4
LT		 8309 eeprom->len += b_count;
8310 }
8311 return 0;
8312}
8313
6aa20a22 8314static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8315
8316static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8317{
8318 struct tg3 *tp = netdev_priv(dev);
8319 int ret;
b9fc7dc5 8320 u32 offset, len, b_offset, odd_len;
1da177e4 8321 u8 *buf;
b9fc7dc5 8322 __le32 start, end;
1da177e4 8323
bc1c7567
MC		 8324 if (tp->link_config.phy_is_low_power)
8325 return -EAGAIN;
8326
1da177e4
LT		 8327 if (eeprom->magic != TG3_EEPROM_MAGIC)
8328 return -EINVAL;
8329
8330 offset = eeprom->offset;
8331 len = eeprom->len;
8332
8333 if ((b_offset = (offset & 3))) {
8334 /* adjustments to start on required 4 byte boundary */
b9fc7dc5 8335 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
1da177e4
LT		 8336 if (ret)
8337 return ret;
1da177e4
LT		 8338 len += b_offset;
8339 offset &= ~3;
1c8594b4
MC		 8340 if (len < 4)
8341 len = 4;
1da177e4
LT		 8342 }
8343
8344 odd_len = 0;
1c8594b4 8345 if (len & 3) {
1da177e4
LT		 8346 /* adjustments to end on required 4 byte boundary */
8347 odd_len = 1;
8348 len = (len + 3) & ~3;
b9fc7dc5 8349 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
1da177e4
LT		 8350 if (ret)
8351 return ret;
1da177e4
LT		 8352 }
8353
8354 buf = data;
8355 if (b_offset || odd_len) {
8356 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8357 if (!buf)
1da177e4
LT		 8358 return -ENOMEM;
8359 if (b_offset)
8360 memcpy(buf, &start, 4);
8361 if (odd_len)
8362 memcpy(buf+len-4, &end, 4);
8363 memcpy(buf + b_offset, data, eeprom->len);
8364 }
8365
8366 ret = tg3_nvram_write_block(tp, offset, len, buf);
8367
8368 if (buf != data)
8369 kfree(buf);
8370
8371 return ret;
8372}
8373
8374static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8375{
8376 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8377
1da177e4
LT		 8378 cmd->supported = (SUPPORTED_Autoneg);
8379
8380 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8381 cmd->supported |= (SUPPORTED_1000baseT_Half |
8382 SUPPORTED_1000baseT_Full);
8383
ef348144 8384 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8385 cmd->supported |= (SUPPORTED_100baseT_Half |
8386 SUPPORTED_100baseT_Full |
8387 SUPPORTED_10baseT_Half |
8388 SUPPORTED_10baseT_Full |
3bebab59 8389 SUPPORTED_TP);
ef348144
KK		 8390 cmd->port = PORT_TP;
8391 } else {
1da177e4 8392 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8393 cmd->port = PORT_FIBRE;
8394 }
6aa20a22 8395
1da177e4
LT		 8396 cmd->advertising = tp->link_config.advertising;
8397 if (netif_running(dev)) {
8398 cmd->speed = tp->link_config.active_speed;
8399 cmd->duplex = tp->link_config.active_duplex;
8400 }
1da177e4
LT		 8401 cmd->phy_address = PHY_ADDR;
8402 cmd->transceiver = 0;
8403 cmd->autoneg = tp->link_config.autoneg;
8404 cmd->maxtxpkt = 0;
8405 cmd->maxrxpkt = 0;
8406 return 0;
8407}
6aa20a22 8408
1da177e4
LT		 8409static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8410{
8411 struct tg3 *tp = netdev_priv(dev);
6aa20a22
JG		 8412
8413 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 8414 /* These are the only valid advertisement bits allowed. */
8415 if (cmd->autoneg == AUTONEG_ENABLE &&
8416 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8417 ADVERTISED_1000baseT_Full |
8418 ADVERTISED_Autoneg |
8419 ADVERTISED_FIBRE)))
8420 return -EINVAL;
37ff238d
MC		 8421 /* Fiber can only do SPEED_1000. */
8422 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8423 (cmd->speed != SPEED_1000))
8424 return -EINVAL;
8425 /* Copper cannot force SPEED_1000. */
8426 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8427 (cmd->speed == SPEED_1000))
8428 return -EINVAL;
8429 else if ((cmd->speed == SPEED_1000) &&
8430 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8431 return -EINVAL;
1da177e4 8432
f47c11ee 8433 tg3_full_lock(tp, 0);
1da177e4
LT		 8434
8435 tp->link_config.autoneg = cmd->autoneg;
8436 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8437 tp->link_config.advertising = (cmd->advertising |
8438 ADVERTISED_Autoneg);
1da177e4
LT		 8439 tp->link_config.speed = SPEED_INVALID;
8440 tp->link_config.duplex = DUPLEX_INVALID;
8441 } else {
8442 tp->link_config.advertising = 0;
8443 tp->link_config.speed = cmd->speed;
8444 tp->link_config.duplex = cmd->duplex;
8445 }
6aa20a22 8446
24fcad6b
MC		 8447 tp->link_config.orig_speed = tp->link_config.speed;
8448 tp->link_config.orig_duplex = tp->link_config.duplex;
8449 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8450
1da177e4
LT		 8451 if (netif_running(dev))
8452 tg3_setup_phy(tp, 1);
8453
f47c11ee 8454 tg3_full_unlock(tp);
6aa20a22 8455
1da177e4
LT		 8456 return 0;
8457}
6aa20a22 8458
1da177e4
LT		 8459static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8460{
8461 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8462
1da177e4
LT		 8463 strcpy(info->driver, DRV_MODULE_NAME);
8464 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8465 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8466 strcpy(info->bus_info, pci_name(tp->pdev));
8467}
6aa20a22 8468
1da177e4
LT		 8469static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8470{
8471 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8472
a85feb8c
GZ		 8473 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8474 wol->supported = WAKE_MAGIC;
8475 else
8476 wol->supported = 0;
1da177e4
LT		 8477 wol->wolopts = 0;
8478 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8479 wol->wolopts = WAKE_MAGIC;
8480 memset(&wol->sopass, 0, sizeof(wol->sopass));
8481}
6aa20a22 8482
1da177e4
LT		 8483static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8484{
8485 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8486
1da177e4
LT		 8487 if (wol->wolopts & ~WAKE_MAGIC)
8488 return -EINVAL;
8489 if ((wol->wolopts & WAKE_MAGIC) &&
a85feb8c 8490 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
1da177e4 8491 return -EINVAL;
6aa20a22 8492
f47c11ee 8493 spin_lock_bh(&tp->lock);
1da177e4
LT		 8494 if (wol->wolopts & WAKE_MAGIC)
8495 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8496 else
8497 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 8498 spin_unlock_bh(&tp->lock);
6aa20a22 8499
1da177e4
LT		 8500 return 0;
8501}
6aa20a22 8502
1da177e4
LT		 8503static u32 tg3_get_msglevel(struct net_device *dev)
8504{
8505 struct tg3 *tp = netdev_priv(dev);
8506 return tp->msg_enable;
8507}
6aa20a22 8508
1da177e4
LT		 8509static void tg3_set_msglevel(struct net_device *dev, u32 value)
8510{
8511 struct tg3 *tp = netdev_priv(dev);
8512 tp->msg_enable = value;
8513}
6aa20a22 8514
1da177e4
LT		 8515static int tg3_set_tso(struct net_device *dev, u32 value)
8516{
8517 struct tg3 *tp = netdev_priv(dev);
8518
8519 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8520 if (value)
8521 return -EINVAL;
8522 return 0;
8523 }
b5d3772c
MC		 8524 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8525 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9936bcf6 8526 if (value) {
b0026624 8527 dev->features |= NETIF_F_TSO6;
9936bcf6
MC		 8528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8529 dev->features |= NETIF_F_TSO_ECN;
8530 } else
8531 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8532 }
1da177e4
LT		 8533 return ethtool_op_set_tso(dev, value);
8534}
6aa20a22 8535
1da177e4
LT		 8536static int tg3_nway_reset(struct net_device *dev)
8537{
8538 struct tg3 *tp = netdev_priv(dev);
8539 u32 bmcr;
8540 int r;
6aa20a22 8541
1da177e4
LT		 8542 if (!netif_running(dev))
8543 return -EAGAIN;
8544
c94e3941
MC		 8545 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8546 return -EINVAL;
8547
f47c11ee 8548 spin_lock_bh(&tp->lock);
1da177e4
LT		 8549 r = -EINVAL;
8550 tg3_readphy(tp, MII_BMCR, &bmcr);
8551 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 8552 ((bmcr & BMCR_ANENABLE) ||
8553 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8554 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8555 BMCR_ANENABLE);
1da177e4
LT		 8556 r = 0;
8557 }
f47c11ee 8558 spin_unlock_bh(&tp->lock);
6aa20a22 8559
1da177e4
LT		 8560 return r;
8561}
6aa20a22 8562
1da177e4
LT		 8563static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8564{
8565 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8566
1da177e4
LT		 8567 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8568 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8569 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8570 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8571 else
8572 ering->rx_jumbo_max_pending = 0;
8573
8574 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8575
8576 ering->rx_pending = tp->rx_pending;
8577 ering->rx_mini_pending = 0;
4f81c32b
MC		 8578 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8579 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8580 else
8581 ering->rx_jumbo_pending = 0;
8582
1da177e4
LT		 8583 ering->tx_pending = tp->tx_pending;
8584}
6aa20a22 8585
1da177e4
LT		 8586static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8587{
8588 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8589 int irq_sync = 0, err = 0;
6aa20a22 8590
1da177e4
LT		 8591 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8592 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8593 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8594 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8595 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8596 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8597 return -EINVAL;
6aa20a22 8598
bbe832c0 8599 if (netif_running(dev)) {
1da177e4 8600 tg3_netif_stop(tp);
bbe832c0
MC		 8601 irq_sync = 1;
8602 }
1da177e4 8603
bbe832c0 8604 tg3_full_lock(tp, irq_sync);
6aa20a22 8605
1da177e4
LT		 8606 tp->rx_pending = ering->rx_pending;
8607
8608 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8609 tp->rx_pending > 63)
8610 tp->rx_pending = 63;
8611 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8612 tp->tx_pending = ering->tx_pending;
8613
8614 if (netif_running(dev)) {
944d980e 8615 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8616 err = tg3_restart_hw(tp, 1);
8617 if (!err)
8618 tg3_netif_start(tp);
1da177e4
LT		 8619 }
8620
f47c11ee 8621 tg3_full_unlock(tp);
6aa20a22 8622
b9ec6c1b 8623 return err;
1da177e4 8624}
6aa20a22 8625
1da177e4
LT		 8626static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8627{
8628 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8629
1da177e4 8630 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621
MC		 8631
8632 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
8633 epause->rx_pause = 1;
8634 else
8635 epause->rx_pause = 0;
8636
8637 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
8638 epause->tx_pause = 1;
8639 else
8640 epause->tx_pause = 0;
1da177e4 8641}
6aa20a22 8642
1da177e4
LT		 8643static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8644{
8645 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8646 int irq_sync = 0, err = 0;
6aa20a22 8647
bbe832c0 8648 if (netif_running(dev)) {
1da177e4 8649 tg3_netif_stop(tp);
bbe832c0
MC		 8650 irq_sync = 1;
8651 }
1da177e4 8652
bbe832c0 8653 tg3_full_lock(tp, irq_sync);
f47c11ee 8654
1da177e4
LT		 8655 if (epause->autoneg)
8656 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8657 else
8658 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8659 if (epause->rx_pause)
8d018621 8660 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
1da177e4 8661 else
8d018621 8662 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
1da177e4 8663 if (epause->tx_pause)
8d018621 8664 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
1da177e4 8665 else
8d018621 8666 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
1da177e4
LT		 8667
8668 if (netif_running(dev)) {
944d980e 8669 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8670 err = tg3_restart_hw(tp, 1);
8671 if (!err)
8672 tg3_netif_start(tp);
1da177e4 8673 }
f47c11ee
DM		 8674
8675 tg3_full_unlock(tp);
6aa20a22 8676
b9ec6c1b 8677 return err;
1da177e4 8678}
6aa20a22 8679
1da177e4
LT		 8680static u32 tg3_get_rx_csum(struct net_device *dev)
8681{
8682 struct tg3 *tp = netdev_priv(dev);
8683 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8684}
6aa20a22 8685
1da177e4
LT		 8686static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8687{
8688 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8689
1da177e4
LT		 8690 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8691 if (data != 0)
8692 return -EINVAL;
8693 return 0;
8694 }
6aa20a22 8695
f47c11ee 8696 spin_lock_bh(&tp->lock);
1da177e4
LT		 8697 if (data)
8698 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8699 else
8700 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8701 spin_unlock_bh(&tp->lock);
6aa20a22 8702
1da177e4
LT		 8703 return 0;
8704}
6aa20a22 8705
1da177e4
LT		 8706static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8707{
8708 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8709
1da177e4
LT		 8710 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8711 if (data != 0)
8712 return -EINVAL;
8713 return 0;
8714 }
6aa20a22 8715
af36e6b6 8716 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 8717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 8718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8719 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
6460d948 8720 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 8721 else
9c27dbdf 8722 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8723
8724 return 0;
8725}
8726
b9f2c044 8727static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 8728{
b9f2c044
JG		 8729 switch (sset) {
8730 case ETH_SS_TEST:
8731 return TG3_NUM_TEST;
8732 case ETH_SS_STATS:
8733 return TG3_NUM_STATS;
8734 default:
8735 return -EOPNOTSUPP;
8736 }
4cafd3f5
MC		 8737}
8738
1da177e4
LT		 8739static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8740{
8741 switch (stringset) {
8742 case ETH_SS_STATS:
8743 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8744 break;
4cafd3f5
MC		 8745 case ETH_SS_TEST:
8746 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8747 break;
1da177e4
LT		 8748 default:
8749 WARN_ON(1); /* we need a WARN() */
8750 break;
8751 }
8752}
8753
4009a93d
MC		 8754static int tg3_phys_id(struct net_device *dev, u32 data)
8755{
8756 struct tg3 *tp = netdev_priv(dev);
8757 int i;
8758
8759 if (!netif_running(tp->dev))
8760 return -EAGAIN;
8761
8762 if (data == 0)
8763 data = 2;
8764
8765 for (i = 0; i < (data * 2); i++) {
8766 if ((i % 2) == 0)
8767 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8768 LED_CTRL_1000MBPS_ON |
8769 LED_CTRL_100MBPS_ON |
8770 LED_CTRL_10MBPS_ON |
8771 LED_CTRL_TRAFFIC_OVERRIDE |
8772 LED_CTRL_TRAFFIC_BLINK |
8773 LED_CTRL_TRAFFIC_LED);
6aa20a22 8774
4009a93d
MC		 8775 else
8776 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8777 LED_CTRL_TRAFFIC_OVERRIDE);
8778
8779 if (msleep_interruptible(500))
8780 break;
8781 }
8782 tw32(MAC_LED_CTRL, tp->led_ctrl);
8783 return 0;
8784}
8785
1da177e4
LT		 8786static void tg3_get_ethtool_stats (struct net_device *dev,
8787 struct ethtool_stats *estats, u64 *tmp_stats)
8788{
8789 struct tg3 *tp = netdev_priv(dev);
8790 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8791}
8792
566f86ad 8793#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 8794#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
8795#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
8796#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 8797#define NVRAM_SELFBOOT_HW_SIZE 0x20
8798#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 8799
8800static int tg3_test_nvram(struct tg3 *tp)
8801{
b9fc7dc5
AV		 8802 u32 csum, magic;
8803 __le32 *buf;
ab0049b4 8804 int i, j, k, err = 0, size;
566f86ad 8805
1820180b 8806 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 8807 return -EIO;
8808
1b27777a
MC		 8809 if (magic == TG3_EEPROM_MAGIC)
8810 size = NVRAM_TEST_SIZE;
b16250e3 8811 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 8812 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
8813 TG3_EEPROM_SB_FORMAT_1) {
8814 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
8815 case TG3_EEPROM_SB_REVISION_0:
8816 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
8817 break;
8818 case TG3_EEPROM_SB_REVISION_2:
8819 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
8820 break;
8821 case TG3_EEPROM_SB_REVISION_3:
8822 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
8823 break;
8824 default:
8825 return 0;
8826 }
8827 } else
1b27777a 8828 return 0;
b16250e3
MC		 8829 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8830 size = NVRAM_SELFBOOT_HW_SIZE;
8831 else
1b27777a
MC		 8832 return -EIO;
8833
8834 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 8835 if (buf == NULL)
8836 return -ENOMEM;
8837
1b27777a
MC		 8838 err = -EIO;
8839 for (i = 0, j = 0; i < size; i += 4, j++) {
b9fc7dc5 8840 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
566f86ad 8841 break;
566f86ad 8842 }
1b27777a 8843 if (i < size)
566f86ad
MC		 8844 goto out;
8845
1b27777a 8846 /* Selfboot format */
b9fc7dc5
AV		 8847 magic = swab32(le32_to_cpu(buf[0]));
8848 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 8849 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8850 u8 *buf8 = (u8 *) buf, csum8 = 0;
8851
b9fc7dc5 8852 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 8853 TG3_EEPROM_SB_REVISION_2) {
8854 /* For rev 2, the csum doesn't include the MBA. */
8855 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
8856 csum8 += buf8[i];
8857 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
8858 csum8 += buf8[i];
8859 } else {
8860 for (i = 0; i < size; i++)
8861 csum8 += buf8[i];
8862 }
1b27777a 8863
ad96b485
AB		 8864 if (csum8 == 0) {
8865 err = 0;
8866 goto out;
8867 }
8868
8869 err = -EIO;
8870 goto out;
1b27777a 8871 }
566f86ad 8872
b9fc7dc5 8873 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 8874 TG3_EEPROM_MAGIC_HW) {
8875 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8876 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8877 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 8878
8879 /* Separate the parity bits and the data bytes. */
8880 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8881 if ((i == 0) || (i == 8)) {
8882 int l;
8883 u8 msk;
8884
8885 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8886 parity[k++] = buf8[i] & msk;
8887 i++;
8888 }
8889 else if (i == 16) {
8890 int l;
8891 u8 msk;
8892
8893 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8894 parity[k++] = buf8[i] & msk;
8895 i++;
8896
8897 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8898 parity[k++] = buf8[i] & msk;
8899 i++;
8900 }
8901 data[j++] = buf8[i];
8902 }
8903
8904 err = -EIO;
8905 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8906 u8 hw8 = hweight8(data[i]);
8907
8908 if ((hw8 & 0x1) && parity[i])
8909 goto out;
8910 else if (!(hw8 & 0x1) && !parity[i])
8911 goto out;
8912 }
8913 err = 0;
8914 goto out;
8915 }
8916
566f86ad
MC		 8917 /* Bootstrap checksum at offset 0x10 */
8918 csum = calc_crc((unsigned char *) buf, 0x10);
b9fc7dc5 8919 if(csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 8920 goto out;
8921
8922 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8923 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
b9fc7dc5 8924 if (csum != le32_to_cpu(buf[0xfc/4]))
566f86ad
MC		 8925 goto out;
8926
8927 err = 0;
8928
8929out:
8930 kfree(buf);
8931 return err;
8932}
8933
ca43007a
MC		 8934#define TG3_SERDES_TIMEOUT_SEC 2
8935#define TG3_COPPER_TIMEOUT_SEC 6
8936
8937static int tg3_test_link(struct tg3 *tp)
8938{
8939 int i, max;
8940
8941 if (!netif_running(tp->dev))
8942 return -ENODEV;
8943
4c987487 8944 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 8945 max = TG3_SERDES_TIMEOUT_SEC;
8946 else
8947 max = TG3_COPPER_TIMEOUT_SEC;
8948
8949 for (i = 0; i < max; i++) {
8950 if (netif_carrier_ok(tp->dev))
8951 return 0;
8952
8953 if (msleep_interruptible(1000))
8954 break;
8955 }
8956
8957 return -EIO;
8958}
8959
a71116d1 8960/* Only test the commonly used registers */
30ca3e37 8961static int tg3_test_registers(struct tg3 *tp)
a71116d1 8962{
b16250e3 8963 int i, is_5705, is_5750;
a71116d1
MC		 8964 u32 offset, read_mask, write_mask, val, save_val, read_val;
8965 static struct {
8966 u16 offset;
8967 u16 flags;
8968#define TG3_FL_5705 0x1
8969#define TG3_FL_NOT_5705 0x2
8970#define TG3_FL_NOT_5788 0x4
b16250e3 8971#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 8972 u32 read_mask;
8973 u32 write_mask;
8974 } reg_tbl[] = {
8975 /* MAC Control Registers */
8976 { MAC_MODE, TG3_FL_NOT_5705,
8977 0x00000000, 0x00ef6f8c },
8978 { MAC_MODE, TG3_FL_5705,
8979 0x00000000, 0x01ef6b8c },
8980 { MAC_STATUS, TG3_FL_NOT_5705,
8981 0x03800107, 0x00000000 },
8982 { MAC_STATUS, TG3_FL_5705,
8983 0x03800100, 0x00000000 },
8984 { MAC_ADDR_0_HIGH, 0x0000,
8985 0x00000000, 0x0000ffff },
8986 { MAC_ADDR_0_LOW, 0x0000,
8987 0x00000000, 0xffffffff },
8988 { MAC_RX_MTU_SIZE, 0x0000,
8989 0x00000000, 0x0000ffff },
8990 { MAC_TX_MODE, 0x0000,
8991 0x00000000, 0x00000070 },
8992 { MAC_TX_LENGTHS, 0x0000,
8993 0x00000000, 0x00003fff },
8994 { MAC_RX_MODE, TG3_FL_NOT_5705,
8995 0x00000000, 0x000007fc },
8996 { MAC_RX_MODE, TG3_FL_5705,
8997 0x00000000, 0x000007dc },
8998 { MAC_HASH_REG_0, 0x0000,
8999 0x00000000, 0xffffffff },
9000 { MAC_HASH_REG_1, 0x0000,
9001 0x00000000, 0xffffffff },
9002 { MAC_HASH_REG_2, 0x0000,
9003 0x00000000, 0xffffffff },
9004 { MAC_HASH_REG_3, 0x0000,
9005 0x00000000, 0xffffffff },
9006
9007 /* Receive Data and Receive BD Initiator Control Registers. */
9008 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9009 0x00000000, 0xffffffff },
9010 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9011 0x00000000, 0xffffffff },
9012 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9013 0x00000000, 0x00000003 },
9014 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9015 0x00000000, 0xffffffff },
9016 { RCVDBDI_STD_BD+0, 0x0000,
9017 0x00000000, 0xffffffff },
9018 { RCVDBDI_STD_BD+4, 0x0000,
9019 0x00000000, 0xffffffff },
9020 { RCVDBDI_STD_BD+8, 0x0000,
9021 0x00000000, 0xffff0002 },
9022 { RCVDBDI_STD_BD+0xc, 0x0000,
9023 0x00000000, 0xffffffff },
6aa20a22 9024
a71116d1
MC		 9025 /* Receive BD Initiator Control Registers. */
9026 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9027 0x00000000, 0xffffffff },
9028 { RCVBDI_STD_THRESH, TG3_FL_5705,
9029 0x00000000, 0x000003ff },
9030 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9031 0x00000000, 0xffffffff },
6aa20a22 9032
a71116d1
MC		 9033 /* Host Coalescing Control Registers. */
9034 { HOSTCC_MODE, TG3_FL_NOT_5705,
9035 0x00000000, 0x00000004 },
9036 { HOSTCC_MODE, TG3_FL_5705,
9037 0x00000000, 0x000000f6 },
9038 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9039 0x00000000, 0xffffffff },
9040 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9041 0x00000000, 0x000003ff },
9042 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9043 0x00000000, 0xffffffff },
9044 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9045 0x00000000, 0x000003ff },
9046 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9047 0x00000000, 0xffffffff },
9048 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9049 0x00000000, 0x000000ff },
9050 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9051 0x00000000, 0xffffffff },
9052 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9053 0x00000000, 0x000000ff },
9054 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9055 0x00000000, 0xffffffff },
9056 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9057 0x00000000, 0xffffffff },
9058 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9059 0x00000000, 0xffffffff },
9060 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9061 0x00000000, 0x000000ff },
9062 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9063 0x00000000, 0xffffffff },
9064 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9065 0x00000000, 0x000000ff },
9066 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9067 0x00000000, 0xffffffff },
9068 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9069 0x00000000, 0xffffffff },
9070 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9071 0x00000000, 0xffffffff },
9072 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9073 0x00000000, 0xffffffff },
9074 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9075 0x00000000, 0xffffffff },
9076 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9077 0xffffffff, 0x00000000 },
9078 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9079 0xffffffff, 0x00000000 },
9080
9081 /* Buffer Manager Control Registers. */
b16250e3 9082 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9083 0x00000000, 0x007fff80 },
b16250e3 9084 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9085 0x00000000, 0x007fffff },
9086 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9087 0x00000000, 0x0000003f },
9088 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9089 0x00000000, 0x000001ff },
9090 { BUFMGR_MB_HIGH_WATER, 0x0000,
9091 0x00000000, 0x000001ff },
9092 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9093 0xffffffff, 0x00000000 },
9094 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9095 0xffffffff, 0x00000000 },
6aa20a22 9096
a71116d1
MC		 9097 /* Mailbox Registers */
9098 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9099 0x00000000, 0x000001ff },
9100 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9101 0x00000000, 0x000001ff },
9102 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9103 0x00000000, 0x000007ff },
9104 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9105 0x00000000, 0x000001ff },
9106
9107 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9108 };
9109
b16250e3
MC		 9110 is_5705 = is_5750 = 0;
9111 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9112 is_5705 = 1;
b16250e3
MC		 9113 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9114 is_5750 = 1;
9115 }
a71116d1
MC		 9116
9117 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9118 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9119 continue;
9120
9121 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9122 continue;
9123
9124 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9125 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9126 continue;
9127
b16250e3
MC		 9128 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9129 continue;
9130
a71116d1
MC		 9131 offset = (u32) reg_tbl[i].offset;
9132 read_mask = reg_tbl[i].read_mask;
9133 write_mask = reg_tbl[i].write_mask;
9134
9135 /* Save the original register content */
9136 save_val = tr32(offset);
9137
9138 /* Determine the read-only value. */
9139 read_val = save_val & read_mask;
9140
9141 /* Write zero to the register, then make sure the read-only bits
9142 * are not changed and the read/write bits are all zeros.
9143 */
9144 tw32(offset, 0);
9145
9146 val = tr32(offset);
9147
9148 /* Test the read-only and read/write bits. */
9149 if (((val & read_mask) != read_val) || (val & write_mask))
9150 goto out;
9151
9152 /* Write ones to all the bits defined by RdMask and WrMask, then
9153 * make sure the read-only bits are not changed and the
9154 * read/write bits are all ones.
9155 */
9156 tw32(offset, read_mask | write_mask);
9157
9158 val = tr32(offset);
9159
9160 /* Test the read-only bits. */
9161 if ((val & read_mask) != read_val)
9162 goto out;
9163
9164 /* Test the read/write bits. */
9165 if ((val & write_mask) != write_mask)
9166 goto out;
9167
9168 tw32(offset, save_val);
9169 }
9170
9171 return 0;
9172
9173out:
9f88f29f
MC		 9174 if (netif_msg_hw(tp))
9175 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9176 offset);
a71116d1
MC		 9177 tw32(offset, save_val);
9178 return -EIO;
9179}
9180
7942e1db
MC		 9181static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9182{
f71e1309 9183 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9184 int i;
9185 u32 j;
9186
e9edda69 9187 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9188 for (j = 0; j < len; j += 4) {
9189 u32 val;
9190
9191 tg3_write_mem(tp, offset + j, test_pattern[i]);
9192 tg3_read_mem(tp, offset + j, &val);
9193 if (val != test_pattern[i])
9194 return -EIO;
9195 }
9196 }
9197 return 0;
9198}
9199
9200static int tg3_test_memory(struct tg3 *tp)
9201{
9202 static struct mem_entry {
9203 u32 offset;
9204 u32 len;
9205 } mem_tbl_570x[] = {
38690194 9206 { 0x00000000, 0x00b50},
7942e1db
MC		 9207 { 0x00002000, 0x1c000},
9208 { 0xffffffff, 0x00000}
9209 }, mem_tbl_5705[] = {
9210 { 0x00000100, 0x0000c},
9211 { 0x00000200, 0x00008},
7942e1db
MC		 9212 { 0x00004000, 0x00800},
9213 { 0x00006000, 0x01000},
9214 { 0x00008000, 0x02000},
9215 { 0x00010000, 0x0e000},
9216 { 0xffffffff, 0x00000}
79f4d13a
MC		 9217 }, mem_tbl_5755[] = {
9218 { 0x00000200, 0x00008},
9219 { 0x00004000, 0x00800},
9220 { 0x00006000, 0x00800},
9221 { 0x00008000, 0x02000},
9222 { 0x00010000, 0x0c000},
9223 { 0xffffffff, 0x00000}
b16250e3
MC		 9224 }, mem_tbl_5906[] = {
9225 { 0x00000200, 0x00008},
9226 { 0x00004000, 0x00400},
9227 { 0x00006000, 0x00400},
9228 { 0x00008000, 0x01000},
9229 { 0x00010000, 0x01000},
9230 { 0xffffffff, 0x00000}
7942e1db
MC		 9231 };
9232 struct mem_entry *mem_tbl;
9233 int err = 0;
9234 int i;
9235
79f4d13a 9236 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
af36e6b6 9237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 9238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 9239 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9240 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
79f4d13a 9241 mem_tbl = mem_tbl_5755;
b16250e3
MC		 9242 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9243 mem_tbl = mem_tbl_5906;
79f4d13a
MC		 9244 else
9245 mem_tbl = mem_tbl_5705;
9246 } else
7942e1db
MC		 9247 mem_tbl = mem_tbl_570x;
9248
9249 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9250 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9251 mem_tbl[i].len)) != 0)
9252 break;
9253 }
6aa20a22 9254
7942e1db
MC		 9255 return err;
9256}
9257
9f40dead
MC		 9258#define TG3_MAC_LOOPBACK 0
9259#define TG3_PHY_LOOPBACK 1
9260
9261static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9262{
9f40dead 9263 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9264 u32 desc_idx;
9265 struct sk_buff *skb, *rx_skb;
9266 u8 *tx_data;
9267 dma_addr_t map;
9268 int num_pkts, tx_len, rx_len, i, err;
9269 struct tg3_rx_buffer_desc *desc;
9270
9f40dead 9271 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9272 /* HW errata - mac loopback fails in some cases on 5780.
9273 * Normal traffic and PHY loopback are not affected by
9274 * errata.
9275 */
9276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9277 return 0;
9278
9f40dead 9279 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9280 MAC_MODE_PORT_INT_LPBACK;
9281 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9282 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9283 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9284 mac_mode |= MAC_MODE_PORT_MODE_MII;
9285 else
9286 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9287 tw32(MAC_MODE, mac_mode);
9288 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9289 u32 val;
9290
b16250e3
MC		 9291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9292 u32 phytest;
9293
9294 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9295 u32 phy;
9296
9297 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9298 phytest | MII_TG3_EPHY_SHADOW_EN);
9299 if (!tg3_readphy(tp, 0x1b, &phy))
9300 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9301 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9302 }
5d64ad34
MC		 9303 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9304 } else
9305 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9306
9ef8ca99
MC		 9307 tg3_phy_toggle_automdix(tp, 0);
9308
3f7045c1 9309 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9310 udelay(40);
5d64ad34 9311
e8f3f6ca 9312 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9313 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9314 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9315 mac_mode |= MAC_MODE_PORT_MODE_MII;
9316 } else
9317 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9318
c94e3941
MC		 9319 /* reset to prevent losing 1st rx packet intermittently */
9320 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9321 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9322 udelay(10);
9323 tw32_f(MAC_RX_MODE, tp->rx_mode);
9324 }
e8f3f6ca
MC		 9325 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9326 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9327 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9328 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9329 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9330 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9331 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9332 }
9f40dead 9333 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9334 }
9335 else
9336 return -EINVAL;
c76949a6
MC		 9337
9338 err = -EIO;
9339
c76949a6 9340 tx_len = 1514;
a20e9c62 9341 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9342 if (!skb)
9343 return -ENOMEM;
9344
c76949a6
MC		 9345 tx_data = skb_put(skb, tx_len);
9346 memcpy(tx_data, tp->dev->dev_addr, 6);
9347 memset(tx_data + 6, 0x0, 8);
9348
9349 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9350
9351 for (i = 14; i < tx_len; i++)
9352 tx_data[i] = (u8) (i & 0xff);
9353
9354 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9355
9356 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9357 HOSTCC_MODE_NOW);
9358
9359 udelay(10);
9360
9361 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9362
c76949a6
MC		 9363 num_pkts = 0;
9364
9f40dead 9365 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9366
9f40dead 9367 tp->tx_prod++;
c76949a6
MC		 9368 num_pkts++;
9369
9f40dead
MC		 9370 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9371 tp->tx_prod);
09ee929c 9372 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9373
9374 udelay(10);
9375
3f7045c1
MC		 9376 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9377 for (i = 0; i < 25; i++) {
c76949a6
MC		 9378 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9379 HOSTCC_MODE_NOW);
9380
9381 udelay(10);
9382
9383 tx_idx = tp->hw_status->idx[0].tx_consumer;
9384 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9385 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9386 (rx_idx == (rx_start_idx + num_pkts)))
9387 break;
9388 }
9389
9390 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9391 dev_kfree_skb(skb);
9392
9f40dead 9393 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9394 goto out;
9395
9396 if (rx_idx != rx_start_idx + num_pkts)
9397 goto out;
9398
9399 desc = &tp->rx_rcb[rx_start_idx];
9400 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9401 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9402 if (opaque_key != RXD_OPAQUE_RING_STD)
9403 goto out;
9404
9405 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9406 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9407 goto out;
9408
9409 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9410 if (rx_len != tx_len)
9411 goto out;
9412
9413 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9414
9415 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9416 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9417
9418 for (i = 14; i < tx_len; i++) {
9419 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9420 goto out;
9421 }
9422 err = 0;
6aa20a22 9423
c76949a6
MC		 9424 /* tg3_free_rings will unmap and free the rx_skb */
9425out:
9426 return err;
9427}
9428
9f40dead
MC		 9429#define TG3_MAC_LOOPBACK_FAILED 1
9430#define TG3_PHY_LOOPBACK_FAILED 2
9431#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9432 TG3_PHY_LOOPBACK_FAILED)
9433
9434static int tg3_test_loopback(struct tg3 *tp)
9435{
9436 int err = 0;
9936bcf6 9437 u32 cpmuctrl = 0;
9f40dead
MC		 9438
9439 if (!netif_running(tp->dev))
9440 return TG3_LOOPBACK_FAILED;
9441
b9ec6c1b
MC		 9442 err = tg3_reset_hw(tp, 1);
9443 if (err)
9444 return TG3_LOOPBACK_FAILED;
9f40dead 9445
b5af7126 9446 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
9936bcf6
MC		 9447 int i;
9448 u32 status;
9449
9450 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9451
9452 /* Wait for up to 40 microseconds to acquire lock. */
9453 for (i = 0; i < 4; i++) {
9454 status = tr32(TG3_CPMU_MUTEX_GNT);
9455 if (status == CPMU_MUTEX_GNT_DRIVER)
9456 break;
9457 udelay(10);
9458 }
9459
9460 if (status != CPMU_MUTEX_GNT_DRIVER)
9461 return TG3_LOOPBACK_FAILED;
9462
9936bcf6 9463 /* Turn off power management based on link speed. */
e875093c 9464 cpmuctrl = tr32(TG3_CPMU_CTRL);
9936bcf6 9465 tw32(TG3_CPMU_CTRL,
e875093c
MC		 9466 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9467 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9468 }
9469
9f40dead
MC		 9470 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9471 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9472
b5af7126 9473 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
9936bcf6
MC		 9474 tw32(TG3_CPMU_CTRL, cpmuctrl);
9475
9476 /* Release the mutex */
9477 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9478 }
9479
9f40dead
MC		 9480 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9481 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9482 err |= TG3_PHY_LOOPBACK_FAILED;
9483 }
9484
9485 return err;
9486}
9487
4cafd3f5
MC		 9488static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9489 u64 *data)
9490{
566f86ad
MC		 9491 struct tg3 *tp = netdev_priv(dev);
9492
bc1c7567
MC		 9493 if (tp->link_config.phy_is_low_power)
9494 tg3_set_power_state(tp, PCI_D0);
9495
566f86ad
MC		 9496 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9497
9498 if (tg3_test_nvram(tp) != 0) {
9499 etest->flags |= ETH_TEST_FL_FAILED;
9500 data[0] = 1;
9501 }
ca43007a
MC		 9502 if (tg3_test_link(tp) != 0) {
9503 etest->flags |= ETH_TEST_FL_FAILED;
9504 data[1] = 1;
9505 }
a71116d1 9506 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 9507 int err, irq_sync = 0;
bbe832c0
MC		 9508
9509 if (netif_running(dev)) {
a71116d1 9510 tg3_netif_stop(tp);
bbe832c0
MC		 9511 irq_sync = 1;
9512 }
a71116d1 9513
bbe832c0 9514 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9515
9516 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9517 err = tg3_nvram_lock(tp);
a71116d1
MC		 9518 tg3_halt_cpu(tp, RX_CPU_BASE);
9519 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9520 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9521 if (!err)
9522 tg3_nvram_unlock(tp);
a71116d1 9523
d9ab5ad1
MC		 9524 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9525 tg3_phy_reset(tp);
9526
a71116d1
MC		 9527 if (tg3_test_registers(tp) != 0) {
9528 etest->flags |= ETH_TEST_FL_FAILED;
9529 data[2] = 1;
9530 }
7942e1db
MC		 9531 if (tg3_test_memory(tp) != 0) {
9532 etest->flags |= ETH_TEST_FL_FAILED;
9533 data[3] = 1;
9534 }
9f40dead 9535 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9536 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9537
f47c11ee
DM		 9538 tg3_full_unlock(tp);
9539
d4bc3927
MC		 9540 if (tg3_test_interrupt(tp) != 0) {
9541 etest->flags |= ETH_TEST_FL_FAILED;
9542 data[5] = 1;
9543 }
f47c11ee
DM		 9544
9545 tg3_full_lock(tp, 0);
d4bc3927 9546
a71116d1
MC		 9547 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9548 if (netif_running(dev)) {
9549 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 9550 if (!tg3_restart_hw(tp, 1))
9551 tg3_netif_start(tp);
a71116d1 9552 }
f47c11ee
DM		 9553
9554 tg3_full_unlock(tp);
a71116d1 9555 }
bc1c7567
MC		 9556 if (tp->link_config.phy_is_low_power)
9557 tg3_set_power_state(tp, PCI_D3hot);
9558
4cafd3f5
MC		 9559}
9560
1da177e4
LT		 9561static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9562{
9563 struct mii_ioctl_data *data = if_mii(ifr);
9564 struct tg3 *tp = netdev_priv(dev);
9565 int err;
9566
9567 switch(cmd) {
9568 case SIOCGMIIPHY:
9569 data->phy_id = PHY_ADDR;
9570
9571 /* fallthru */
9572 case SIOCGMIIREG: {
9573 u32 mii_regval;
9574
9575 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9576 break; /* We have no PHY */
9577
bc1c7567
MC		 9578 if (tp->link_config.phy_is_low_power)
9579 return -EAGAIN;
9580
f47c11ee 9581 spin_lock_bh(&tp->lock);
1da177e4 9582 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9583 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9584
9585 data->val_out = mii_regval;
9586
9587 return err;
9588 }
9589
9590 case SIOCSMIIREG:
9591 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9592 break; /* We have no PHY */
9593
9594 if (!capable(CAP_NET_ADMIN))
9595 return -EPERM;
9596
bc1c7567
MC		 9597 if (tp->link_config.phy_is_low_power)
9598 return -EAGAIN;
9599
f47c11ee 9600 spin_lock_bh(&tp->lock);
1da177e4 9601 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9602 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9603
9604 return err;
9605
9606 default:
9607 /* do nothing */
9608 break;
9609 }
9610 return -EOPNOTSUPP;
9611}
9612
9613#if TG3_VLAN_TAG_USED
9614static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9615{
9616 struct tg3 *tp = netdev_priv(dev);
9617
29315e87
MC		 9618 if (netif_running(dev))
9619 tg3_netif_stop(tp);
9620
f47c11ee 9621 tg3_full_lock(tp, 0);
1da177e4
LT		 9622
9623 tp->vlgrp = grp;
9624
9625 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9626 __tg3_set_rx_mode(dev);
9627
29315e87
MC		 9628 if (netif_running(dev))
9629 tg3_netif_start(tp);
46966545
MC		 9630
9631 tg3_full_unlock(tp);
1da177e4 9632}
1da177e4
LT		 9633#endif
9634
15f9850d
DM		 9635static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9636{
9637 struct tg3 *tp = netdev_priv(dev);
9638
9639 memcpy(ec, &tp->coal, sizeof(*ec));
9640 return 0;
9641}
9642
d244c892
MC		 9643static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9644{
9645 struct tg3 *tp = netdev_priv(dev);
9646 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9647 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9648
9649 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9650 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9651 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9652 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9653 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9654 }
9655
9656 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9657 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9658 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9659 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9660 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9661 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9662 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9663 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9664 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9665 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9666 return -EINVAL;
9667
9668 /* No rx interrupts will be generated if both are zero */
9669 if ((ec->rx_coalesce_usecs == 0) &&
9670 (ec->rx_max_coalesced_frames == 0))
9671 return -EINVAL;
9672
9673 /* No tx interrupts will be generated if both are zero */
9674 if ((ec->tx_coalesce_usecs == 0) &&
9675 (ec->tx_max_coalesced_frames == 0))
9676 return -EINVAL;
9677
9678 /* Only copy relevant parameters, ignore all others. */
9679 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9680 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9681 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9682 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9683 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9684 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9685 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9686 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9687 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9688
9689 if (netif_running(dev)) {
9690 tg3_full_lock(tp, 0);
9691 __tg3_set_coalesce(tp, &tp->coal);
9692 tg3_full_unlock(tp);
9693 }
9694 return 0;
9695}
9696
7282d491 9697static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9698 .get_settings = tg3_get_settings,
9699 .set_settings = tg3_set_settings,
9700 .get_drvinfo = tg3_get_drvinfo,
9701 .get_regs_len = tg3_get_regs_len,
9702 .get_regs = tg3_get_regs,
9703 .get_wol = tg3_get_wol,
9704 .set_wol = tg3_set_wol,
9705 .get_msglevel = tg3_get_msglevel,
9706 .set_msglevel = tg3_set_msglevel,
9707 .nway_reset = tg3_nway_reset,
9708 .get_link = ethtool_op_get_link,
9709 .get_eeprom_len = tg3_get_eeprom_len,
9710 .get_eeprom = tg3_get_eeprom,
9711 .set_eeprom = tg3_set_eeprom,
9712 .get_ringparam = tg3_get_ringparam,
9713 .set_ringparam = tg3_set_ringparam,
9714 .get_pauseparam = tg3_get_pauseparam,
9715 .set_pauseparam = tg3_set_pauseparam,
9716 .get_rx_csum = tg3_get_rx_csum,
9717 .set_rx_csum = tg3_set_rx_csum,
1da177e4 9718 .set_tx_csum = tg3_set_tx_csum,
1da177e4 9719 .set_sg = ethtool_op_set_sg,
1da177e4 9720 .set_tso = tg3_set_tso,
4cafd3f5 9721 .self_test = tg3_self_test,
1da177e4 9722 .get_strings = tg3_get_strings,
4009a93d 9723 .phys_id = tg3_phys_id,
1da177e4 9724 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 9725 .get_coalesce = tg3_get_coalesce,
d244c892 9726 .set_coalesce = tg3_set_coalesce,
b9f2c044 9727 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 9728};
9729
9730static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9731{
1b27777a 9732 u32 cursize, val, magic;
1da177e4
LT		 9733
9734 tp->nvram_size = EEPROM_CHIP_SIZE;
9735
1820180b 9736 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 9737 return;
9738
b16250e3
MC		 9739 if ((magic != TG3_EEPROM_MAGIC) &&
9740 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9741 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 9742 return;
9743
9744 /*
9745 * Size the chip by reading offsets at increasing powers of two.
9746 * When we encounter our validation signature, we know the addressing
9747 * has wrapped around, and thus have our chip size.
9748 */
1b27777a 9749 cursize = 0x10;
1da177e4
LT		 9750
9751 while (cursize < tp->nvram_size) {
1820180b 9752 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 9753 return;
9754
1820180b 9755 if (val == magic)
1da177e4
LT		 9756 break;
9757
9758 cursize <<= 1;
9759 }
9760
9761 tp->nvram_size = cursize;
9762}
6aa20a22 9763
1da177e4
LT		 9764static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9765{
9766 u32 val;
9767
1820180b 9768 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 9769 return;
9770
9771 /* Selfboot format */
1820180b 9772 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 9773 tg3_get_eeprom_size(tp);
9774 return;
9775 }
9776
1da177e4
LT		 9777 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9778 if (val != 0) {
9779 tp->nvram_size = (val >> 16) * 1024;
9780 return;
9781 }
9782 }
989a9d23 9783 tp->nvram_size = 0x80000;
1da177e4
LT		 9784}
9785
9786static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9787{
9788 u32 nvcfg1;
9789
9790 nvcfg1 = tr32(NVRAM_CFG1);
9791 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9792 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9793 }
9794 else {
9795 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9796 tw32(NVRAM_CFG1, nvcfg1);
9797 }
9798
4c987487 9799 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 9800 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9801 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9802 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9803 tp->nvram_jedecnum = JEDEC_ATMEL;
9804 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9805 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9806 break;
9807 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9808 tp->nvram_jedecnum = JEDEC_ATMEL;
9809 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9810 break;
9811 case FLASH_VENDOR_ATMEL_EEPROM:
9812 tp->nvram_jedecnum = JEDEC_ATMEL;
9813 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9814 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9815 break;
9816 case FLASH_VENDOR_ST:
9817 tp->nvram_jedecnum = JEDEC_ST;
9818 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9819 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9820 break;
9821 case FLASH_VENDOR_SAIFUN:
9822 tp->nvram_jedecnum = JEDEC_SAIFUN;
9823 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9824 break;
9825 case FLASH_VENDOR_SST_SMALL:
9826 case FLASH_VENDOR_SST_LARGE:
9827 tp->nvram_jedecnum = JEDEC_SST;
9828 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9829 break;
9830 }
9831 }
9832 else {
9833 tp->nvram_jedecnum = JEDEC_ATMEL;
9834 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9835 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9836 }
9837}
9838
361b4ac2
MC		 9839static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9840{
9841 u32 nvcfg1;
9842
9843 nvcfg1 = tr32(NVRAM_CFG1);
9844
e6af301b
MC		 9845 /* NVRAM protection for TPM */
9846 if (nvcfg1 & (1 << 27))
9847 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9848
361b4ac2
MC		 9849 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9850 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9851 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9852 tp->nvram_jedecnum = JEDEC_ATMEL;
9853 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9854 break;
9855 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9856 tp->nvram_jedecnum = JEDEC_ATMEL;
9857 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9858 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9859 break;
9860 case FLASH_5752VENDOR_ST_M45PE10:
9861 case FLASH_5752VENDOR_ST_M45PE20:
9862 case FLASH_5752VENDOR_ST_M45PE40:
9863 tp->nvram_jedecnum = JEDEC_ST;
9864 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9865 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9866 break;
9867 }
9868
9869 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9870 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9871 case FLASH_5752PAGE_SIZE_256:
9872 tp->nvram_pagesize = 256;
9873 break;
9874 case FLASH_5752PAGE_SIZE_512:
9875 tp->nvram_pagesize = 512;
9876 break;
9877 case FLASH_5752PAGE_SIZE_1K:
9878 tp->nvram_pagesize = 1024;
9879 break;
9880 case FLASH_5752PAGE_SIZE_2K:
9881 tp->nvram_pagesize = 2048;
9882 break;
9883 case FLASH_5752PAGE_SIZE_4K:
9884 tp->nvram_pagesize = 4096;
9885 break;
9886 case FLASH_5752PAGE_SIZE_264:
9887 tp->nvram_pagesize = 264;
9888 break;
9889 }
9890 }
9891 else {
9892 /* For eeprom, set pagesize to maximum eeprom size */
9893 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9894
9895 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9896 tw32(NVRAM_CFG1, nvcfg1);
9897 }
9898}
9899
d3c7b886
MC		 9900static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9901{
989a9d23 9902 u32 nvcfg1, protect = 0;
d3c7b886
MC		 9903
9904 nvcfg1 = tr32(NVRAM_CFG1);
9905
9906 /* NVRAM protection for TPM */
989a9d23 9907 if (nvcfg1 & (1 << 27)) {
d3c7b886 9908 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 9909 protect = 1;
9910 }
d3c7b886 9911
989a9d23
MC		 9912 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9913 switch (nvcfg1) {
d3c7b886
MC		 9914 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9915 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9916 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 9917 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 9918 tp->nvram_jedecnum = JEDEC_ATMEL;
9919 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9920 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9921 tp->nvram_pagesize = 264;
70b65a2d
MC		 9922 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
9923 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
989a9d23
MC		 9924 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9925 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9926 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9927 else
9928 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
d3c7b886
MC		 9929 break;
9930 case FLASH_5752VENDOR_ST_M45PE10:
9931 case FLASH_5752VENDOR_ST_M45PE20:
9932 case FLASH_5752VENDOR_ST_M45PE40:
9933 tp->nvram_jedecnum = JEDEC_ST;
9934 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9935 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9936 tp->nvram_pagesize = 256;
989a9d23
MC		 9937 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9938 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9939 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9940 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9941 else
9942 tp->nvram_size = (protect ? 0x20000 : 0x80000);
d3c7b886
MC		 9943 break;
9944 }
9945}
9946
1b27777a
MC		 9947static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9948{
9949 u32 nvcfg1;
9950
9951 nvcfg1 = tr32(NVRAM_CFG1);
9952
9953 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9954 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9955 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9956 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9957 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9958 tp->nvram_jedecnum = JEDEC_ATMEL;
9959 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9960 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9961
9962 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9963 tw32(NVRAM_CFG1, nvcfg1);
9964 break;
9965 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9966 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9967 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9968 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9969 tp->nvram_jedecnum = JEDEC_ATMEL;
9970 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9971 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9972 tp->nvram_pagesize = 264;
9973 break;
9974 case FLASH_5752VENDOR_ST_M45PE10:
9975 case FLASH_5752VENDOR_ST_M45PE20:
9976 case FLASH_5752VENDOR_ST_M45PE40:
9977 tp->nvram_jedecnum = JEDEC_ST;
9978 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9979 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9980 tp->nvram_pagesize = 256;
9981 break;
9982 }
9983}
9984
6b91fa02
MC		 9985static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
9986{
9987 u32 nvcfg1, protect = 0;
9988
9989 nvcfg1 = tr32(NVRAM_CFG1);
9990
9991 /* NVRAM protection for TPM */
9992 if (nvcfg1 & (1 << 27)) {
9993 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9994 protect = 1;
9995 }
9996
9997 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9998 switch (nvcfg1) {
9999 case FLASH_5761VENDOR_ATMEL_ADB021D:
10000 case FLASH_5761VENDOR_ATMEL_ADB041D:
10001 case FLASH_5761VENDOR_ATMEL_ADB081D:
10002 case FLASH_5761VENDOR_ATMEL_ADB161D:
10003 case FLASH_5761VENDOR_ATMEL_MDB021D:
10004 case FLASH_5761VENDOR_ATMEL_MDB041D:
10005 case FLASH_5761VENDOR_ATMEL_MDB081D:
10006 case FLASH_5761VENDOR_ATMEL_MDB161D:
10007 tp->nvram_jedecnum = JEDEC_ATMEL;
10008 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10009 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10010 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10011 tp->nvram_pagesize = 256;
10012 break;
10013 case FLASH_5761VENDOR_ST_A_M45PE20:
10014 case FLASH_5761VENDOR_ST_A_M45PE40:
10015 case FLASH_5761VENDOR_ST_A_M45PE80:
10016 case FLASH_5761VENDOR_ST_A_M45PE16:
10017 case FLASH_5761VENDOR_ST_M_M45PE20:
10018 case FLASH_5761VENDOR_ST_M_M45PE40:
10019 case FLASH_5761VENDOR_ST_M_M45PE80:
10020 case FLASH_5761VENDOR_ST_M_M45PE16:
10021 tp->nvram_jedecnum = JEDEC_ST;
10022 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10023 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10024 tp->nvram_pagesize = 256;
10025 break;
10026 }
10027
10028 if (protect) {
10029 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10030 } else {
10031 switch (nvcfg1) {
10032 case FLASH_5761VENDOR_ATMEL_ADB161D:
10033 case FLASH_5761VENDOR_ATMEL_MDB161D:
10034 case FLASH_5761VENDOR_ST_A_M45PE16:
10035 case FLASH_5761VENDOR_ST_M_M45PE16:
10036 tp->nvram_size = 0x100000;
10037 break;
10038 case FLASH_5761VENDOR_ATMEL_ADB081D:
10039 case FLASH_5761VENDOR_ATMEL_MDB081D:
10040 case FLASH_5761VENDOR_ST_A_M45PE80:
10041 case FLASH_5761VENDOR_ST_M_M45PE80:
10042 tp->nvram_size = 0x80000;
10043 break;
10044 case FLASH_5761VENDOR_ATMEL_ADB041D:
10045 case FLASH_5761VENDOR_ATMEL_MDB041D:
10046 case FLASH_5761VENDOR_ST_A_M45PE40:
10047 case FLASH_5761VENDOR_ST_M_M45PE40:
10048 tp->nvram_size = 0x40000;
10049 break;
10050 case FLASH_5761VENDOR_ATMEL_ADB021D:
10051 case FLASH_5761VENDOR_ATMEL_MDB021D:
10052 case FLASH_5761VENDOR_ST_A_M45PE20:
10053 case FLASH_5761VENDOR_ST_M_M45PE20:
10054 tp->nvram_size = 0x20000;
10055 break;
10056 }
10057 }
10058}
10059
b5d3772c
MC		 10060static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10061{
10062 tp->nvram_jedecnum = JEDEC_ATMEL;
10063 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10064 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10065}
10066
1da177e4
LT		 10067/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10068static void __devinit tg3_nvram_init(struct tg3 *tp)
10069{
1da177e4
LT		 10070 tw32_f(GRC_EEPROM_ADDR,
10071 (EEPROM_ADDR_FSM_RESET |
10072 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10073 EEPROM_ADDR_CLKPERD_SHIFT)));
10074
9d57f01c 10075 msleep(1);
1da177e4
LT		 10076
10077 /* Enable seeprom accesses. */
10078 tw32_f(GRC_LOCAL_CTRL,
10079 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10080 udelay(100);
10081
10082 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10083 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10084 tp->tg3_flags |= TG3_FLAG_NVRAM;
10085
ec41c7df
MC		 10086 if (tg3_nvram_lock(tp)) {
10087 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10088 "tg3_nvram_init failed.\n", tp->dev->name);
10089 return;
10090 }
e6af301b 10091 tg3_enable_nvram_access(tp);
1da177e4 10092
989a9d23
MC		 10093 tp->nvram_size = 0;
10094
361b4ac2
MC		 10095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10096 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10097 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10098 tg3_get_5755_nvram_info(tp);
d30cdd28
MC		 10099 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
1b27777a 10101 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10102 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10103 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10104 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10105 tg3_get_5906_nvram_info(tp);
361b4ac2
MC		 10106 else
10107 tg3_get_nvram_info(tp);
10108
989a9d23
MC		 10109 if (tp->nvram_size == 0)
10110 tg3_get_nvram_size(tp);
1da177e4 10111
e6af301b 10112 tg3_disable_nvram_access(tp);
381291b7 10113 tg3_nvram_unlock(tp);
1da177e4
LT		 10114
10115 } else {
10116 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10117
10118 tg3_get_eeprom_size(tp);
10119 }
10120}
10121
10122static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10123 u32 offset, u32 *val)
10124{
10125 u32 tmp;
10126 int i;
10127
10128 if (offset > EEPROM_ADDR_ADDR_MASK ||
10129 (offset % 4) != 0)
10130 return -EINVAL;
10131
10132 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10133 EEPROM_ADDR_DEVID_MASK |
10134 EEPROM_ADDR_READ);
10135 tw32(GRC_EEPROM_ADDR,
10136 tmp |
10137 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10138 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10139 EEPROM_ADDR_ADDR_MASK) |
10140 EEPROM_ADDR_READ | EEPROM_ADDR_START);
10141
9d57f01c 10142 for (i = 0; i < 1000; i++) {
1da177e4
LT		 10143 tmp = tr32(GRC_EEPROM_ADDR);
10144
10145 if (tmp & EEPROM_ADDR_COMPLETE)
10146 break;
9d57f01c 10147 msleep(1);
1da177e4
LT		 10148 }
10149 if (!(tmp & EEPROM_ADDR_COMPLETE))
10150 return -EBUSY;
10151
10152 *val = tr32(GRC_EEPROM_DATA);
10153 return 0;
10154}
10155
10156#define NVRAM_CMD_TIMEOUT 10000
10157
10158static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10159{
10160 int i;
10161
10162 tw32(NVRAM_CMD, nvram_cmd);
10163 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10164 udelay(10);
10165 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10166 udelay(10);
10167 break;
10168 }
10169 }
10170 if (i == NVRAM_CMD_TIMEOUT) {
10171 return -EBUSY;
10172 }
10173 return 0;
10174}
10175
1820180b
MC		 10176static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10177{
10178 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10179 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10180 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 10181 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
1820180b
MC		 10182 (tp->nvram_jedecnum == JEDEC_ATMEL))
10183
10184 addr = ((addr / tp->nvram_pagesize) <<
10185 ATMEL_AT45DB0X1B_PAGE_POS) +
10186 (addr % tp->nvram_pagesize);
10187
10188 return addr;
10189}
10190
c4e6575c
MC		 10191static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10192{
10193 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10194 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10195 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 10196 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
c4e6575c
MC		 10197 (tp->nvram_jedecnum == JEDEC_ATMEL))
10198
10199 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10200 tp->nvram_pagesize) +
10201 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10202
10203 return addr;
10204}
10205
1da177e4
LT		 10206static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10207{
10208 int ret;
10209
1da177e4
LT		 10210 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10211 return tg3_nvram_read_using_eeprom(tp, offset, val);
10212
1820180b 10213 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10214
10215 if (offset > NVRAM_ADDR_MSK)
10216 return -EINVAL;
10217
ec41c7df
MC		 10218 ret = tg3_nvram_lock(tp);
10219 if (ret)
10220 return ret;
1da177e4 10221
e6af301b 10222 tg3_enable_nvram_access(tp);
1da177e4
LT		 10223
10224 tw32(NVRAM_ADDR, offset);
10225 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10226 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10227
10228 if (ret == 0)
10229 *val = swab32(tr32(NVRAM_RDDATA));
10230
e6af301b 10231 tg3_disable_nvram_access(tp);
1da177e4 10232
381291b7
MC		 10233 tg3_nvram_unlock(tp);
10234
1da177e4
LT		 10235 return ret;
10236}
10237
b9fc7dc5
AV		 10238static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10239{
10240 u32 v;
10241 int res = tg3_nvram_read(tp, offset, &v);
10242 if (!res)
10243 *val = cpu_to_le32(v);
10244 return res;
10245}
10246
1820180b
MC		 10247static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10248{
10249 int err;
10250 u32 tmp;
10251
10252 err = tg3_nvram_read(tp, offset, &tmp);
10253 *val = swab32(tmp);
10254 return err;
10255}
10256
1da177e4
LT		 10257static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10258 u32 offset, u32 len, u8 *buf)
10259{
10260 int i, j, rc = 0;
10261 u32 val;
10262
10263 for (i = 0; i < len; i += 4) {
b9fc7dc5
AV		 10264 u32 addr;
10265 __le32 data;
1da177e4
LT		 10266
10267 addr = offset + i;
10268
10269 memcpy(&data, buf + i, 4);
10270
b9fc7dc5 10271 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
1da177e4
LT		 10272
10273 val = tr32(GRC_EEPROM_ADDR);
10274 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10275
10276 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10277 EEPROM_ADDR_READ);
10278 tw32(GRC_EEPROM_ADDR, val |
10279 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10280 (addr & EEPROM_ADDR_ADDR_MASK) |
10281 EEPROM_ADDR_START |
10282 EEPROM_ADDR_WRITE);
6aa20a22 10283
9d57f01c 10284 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10285 val = tr32(GRC_EEPROM_ADDR);
10286
10287 if (val & EEPROM_ADDR_COMPLETE)
10288 break;
9d57f01c 10289 msleep(1);
1da177e4
LT		 10290 }
10291 if (!(val & EEPROM_ADDR_COMPLETE)) {
10292 rc = -EBUSY;
10293 break;
10294 }
10295 }
10296
10297 return rc;
10298}
10299
10300/* offset and length are dword aligned */
10301static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10302 u8 *buf)
10303{
10304 int ret = 0;
10305 u32 pagesize = tp->nvram_pagesize;
10306 u32 pagemask = pagesize - 1;
10307 u32 nvram_cmd;
10308 u8 *tmp;
10309
10310 tmp = kmalloc(pagesize, GFP_KERNEL);
10311 if (tmp == NULL)
10312 return -ENOMEM;
10313
10314 while (len) {
10315 int j;
e6af301b 10316 u32 phy_addr, page_off, size;
1da177e4
LT		 10317
10318 phy_addr = offset & ~pagemask;
6aa20a22 10319
1da177e4 10320 for (j = 0; j < pagesize; j += 4) {
286e310f 10321 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
b9fc7dc5 10322 (__le32 *) (tmp + j))))
1da177e4
LT		 10323 break;
10324 }
10325 if (ret)
10326 break;
10327
10328 page_off = offset & pagemask;
10329 size = pagesize;
10330 if (len < size)
10331 size = len;
10332
10333 len -= size;
10334
10335 memcpy(tmp + page_off, buf, size);
10336
10337 offset = offset + (pagesize - page_off);
10338
e6af301b 10339 tg3_enable_nvram_access(tp);
1da177e4
LT		 10340
10341 /*
10342 * Before we can erase the flash page, we need
10343 * to issue a special "write enable" command.
10344 */
10345 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10346
10347 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10348 break;
10349
10350 /* Erase the target page */
10351 tw32(NVRAM_ADDR, phy_addr);
10352
10353 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10354 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10355
10356 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10357 break;
10358
10359 /* Issue another write enable to start the write. */
10360 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10361
10362 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10363 break;
10364
10365 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10366 __be32 data;
1da177e4 10367
b9fc7dc5
AV		 10368 data = *((__be32 *) (tmp + j));
10369 /* swab32(le32_to_cpu(data)), actually */
10370 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10371
10372 tw32(NVRAM_ADDR, phy_addr + j);
10373
10374 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10375 NVRAM_CMD_WR;
10376
10377 if (j == 0)
10378 nvram_cmd |= NVRAM_CMD_FIRST;
10379 else if (j == (pagesize - 4))
10380 nvram_cmd |= NVRAM_CMD_LAST;
10381
10382 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10383 break;
10384 }
10385 if (ret)
10386 break;
10387 }
10388
10389 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10390 tg3_nvram_exec_cmd(tp, nvram_cmd);
10391
10392 kfree(tmp);
10393
10394 return ret;
10395}
10396
10397/* offset and length are dword aligned */
10398static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10399 u8 *buf)
10400{
10401 int i, ret = 0;
10402
10403 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10404 u32 page_off, phy_addr, nvram_cmd;
10405 __be32 data;
1da177e4
LT		 10406
10407 memcpy(&data, buf + i, 4);
b9fc7dc5 10408 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10409
10410 page_off = offset % tp->nvram_pagesize;
10411
1820180b 10412 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10413
10414 tw32(NVRAM_ADDR, phy_addr);
10415
10416 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10417
10418 if ((page_off == 0) || (i == 0))
10419 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10420 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10421 nvram_cmd |= NVRAM_CMD_LAST;
10422
10423 if (i == (len - 4))
10424 nvram_cmd |= NVRAM_CMD_LAST;
10425
4c987487 10426 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
af36e6b6 10427 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
1b27777a 10428 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
d30cdd28 10429 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
9936bcf6 10430 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
4c987487
MC		 10431 (tp->nvram_jedecnum == JEDEC_ST) &&
10432 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10433
10434 if ((ret = tg3_nvram_exec_cmd(tp,
10435 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10436 NVRAM_CMD_DONE)))
10437
10438 break;
10439 }
10440 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10441 /* We always do complete word writes to eeprom. */
10442 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10443 }
10444
10445 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10446 break;
10447 }
10448 return ret;
10449}
10450
10451/* offset and length are dword aligned */
10452static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10453{
10454 int ret;
10455
1da177e4 10456 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10457 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10458 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10459 udelay(40);
10460 }
10461
10462 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10463 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10464 }
10465 else {
10466 u32 grc_mode;
10467
ec41c7df
MC		 10468 ret = tg3_nvram_lock(tp);
10469 if (ret)
10470 return ret;
1da177e4 10471
e6af301b
MC		 10472 tg3_enable_nvram_access(tp);
10473 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10474 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10475 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10476
10477 grc_mode = tr32(GRC_MODE);
10478 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10479
10480 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10481 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10482
10483 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10484 buf);
10485 }
10486 else {
10487 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10488 buf);
10489 }
10490
10491 grc_mode = tr32(GRC_MODE);
10492 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10493
e6af301b 10494 tg3_disable_nvram_access(tp);
1da177e4
LT		 10495 tg3_nvram_unlock(tp);
10496 }
10497
10498 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10499 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10500 udelay(40);
10501 }
10502
10503 return ret;
10504}
10505
10506struct subsys_tbl_ent {
10507 u16 subsys_vendor, subsys_devid;
10508 u32 phy_id;
10509};
10510
10511static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10512 /* Broadcom boards. */
10513 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10514 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10515 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10516 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10517 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10518 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10519 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10520 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10521 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10522 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10523 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10524
10525 /* 3com boards. */
10526 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10527 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10528 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10529 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10530 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10531
10532 /* DELL boards. */
10533 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10534 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10535 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10536 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10537
10538 /* Compaq boards. */
10539 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10540 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10541 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10542 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10543 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10544
10545 /* IBM boards. */
10546 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10547};
10548
10549static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10550{
10551 int i;
10552
10553 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10554 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10555 tp->pdev->subsystem_vendor) &&
10556 (subsys_id_to_phy_id[i].subsys_devid ==
10557 tp->pdev->subsystem_device))
10558 return &subsys_id_to_phy_id[i];
10559 }
10560 return NULL;
10561}
10562
7d0c41ef 10563static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10564{
1da177e4 10565 u32 val;
caf636c7
MC		 10566 u16 pmcsr;
10567
10568 /* On some early chips the SRAM cannot be accessed in D3hot state,
10569 * so need make sure we're in D0.
10570 */
10571 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10572 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10573 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10574 msleep(1);
7d0c41ef
MC		 10575
10576 /* Make sure register accesses (indirect or otherwise)
10577 * will function correctly.
10578 */
10579 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10580 tp->misc_host_ctrl);
1da177e4 10581
f49639e6
DM		 10582 /* The memory arbiter has to be enabled in order for SRAM accesses
10583 * to succeed. Normally on powerup the tg3 chip firmware will make
10584 * sure it is enabled, but other entities such as system netboot
10585 * code might disable it.
10586 */
10587 val = tr32(MEMARB_MODE);
10588 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10589
1da177e4 10590 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 10591 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10592
a85feb8c
GZ		 10593 /* Assume an onboard device and WOL capable by default. */
10594 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 10595
b5d3772c 10596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 10597 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 10598 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10599 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10600 }
0527ba35
MC		 10601 val = tr32(VCPU_CFGSHDW);
10602 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 10603 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35
MC		 10604 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10605 (val & VCPU_CFGSHDW_WOL_MAGPKT))
10606 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
b5d3772c
MC		 10607 return;
10608 }
10609
1da177e4
LT		 10610 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10611 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10612 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 10613 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10614 int eeprom_phy_serdes = 0;
1da177e4
LT		 10615
10616 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10617 tp->nic_sram_data_cfg = nic_cfg;
10618
10619 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10620 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10621 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10622 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10623 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10624 (ver > 0) && (ver < 0x100))
10625 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10626
1da177e4
LT		 10627 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10628 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10629 eeprom_phy_serdes = 1;
10630
10631 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10632 if (nic_phy_id != 0) {
10633 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10634 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10635
10636 eeprom_phy_id = (id1 >> 16) << 10;
10637 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10638 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10639 } else
10640 eeprom_phy_id = 0;
10641
7d0c41ef 10642 tp->phy_id = eeprom_phy_id;
747e8f8b 10643 if (eeprom_phy_serdes) {
a4e2b347 10644 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 10645 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10646 else
10647 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10648 }
7d0c41ef 10649
cbf46853 10650 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10651 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10652 SHASTA_EXT_LED_MODE_MASK);
cbf46853 10653 else
1da177e4
LT		 10654 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10655
10656 switch (led_cfg) {
10657 default:
10658 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10659 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10660 break;
10661
10662 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10663 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10664 break;
10665
10666 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10667 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 10668
10669 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10670 * read on some older 5700/5701 bootcode.
10671 */
10672 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10673 ASIC_REV_5700 ||
10674 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10675 ASIC_REV_5701)
10676 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10677
1da177e4
LT		 10678 break;
10679
10680 case SHASTA_EXT_LED_SHARED:
10681 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10682 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10683 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10684 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10685 LED_CTRL_MODE_PHY_2);
10686 break;
10687
10688 case SHASTA_EXT_LED_MAC:
10689 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10690 break;
10691
10692 case SHASTA_EXT_LED_COMBO:
10693 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10694 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10695 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10696 LED_CTRL_MODE_PHY_2);
10697 break;
10698
10699 };
10700
10701 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10703 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10704 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10705
b5af7126
MC		 10706 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
10707 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1)
5f60891b
MC		 10708 tp->led_ctrl = LED_CTRL_MODE_MAC;
10709
9d26e213 10710 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 10711 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10712 if ((tp->pdev->subsystem_vendor ==
10713 PCI_VENDOR_ID_ARIMA) &&
10714 (tp->pdev->subsystem_device == 0x205a ||
10715 tp->pdev->subsystem_device == 0x2063))
10716 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10717 } else {
f49639e6 10718 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10719 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10720 }
1da177e4
LT		 10721
10722 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10723 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 10724 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10725 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10726 }
0d3031d9
MC		 10727 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
10728 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
a85feb8c
GZ		 10729 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10730 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10731 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 10732
0527ba35
MC		 10733 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
10734 nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
10735 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10736
1da177e4
LT		 10737 if (cfg2 & (1 << 17))
10738 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10739
10740 /* serdes signal pre-emphasis in register 0x590 set by */
10741 /* bootcode if bit 18 is set */
10742 if (cfg2 & (1 << 18))
10743 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e
MC		 10744
10745 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10746 u32 cfg3;
10747
10748 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10749 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10750 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10751 }
1da177e4 10752 }
7d0c41ef
MC		 10753}
10754
10755static int __devinit tg3_phy_probe(struct tg3 *tp)
10756{
10757 u32 hw_phy_id_1, hw_phy_id_2;
10758 u32 hw_phy_id, hw_phy_id_masked;
10759 int err;
1da177e4
LT		 10760
10761 /* Reading the PHY ID register can conflict with ASF
10762 * firwmare access to the PHY hardware.
10763 */
10764 err = 0;
0d3031d9
MC		 10765 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
10766 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 10767 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10768 } else {
10769 /* Now read the physical PHY_ID from the chip and verify
10770 * that it is sane. If it doesn't look good, we fall back
10771 * to either the hard-coded table based PHY_ID and failing
10772 * that the value found in the eeprom area.
10773 */
10774 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10775 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10776
10777 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10778 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10779 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10780
10781 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10782 }
10783
10784 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10785 tp->phy_id = hw_phy_id;
10786 if (hw_phy_id_masked == PHY_ID_BCM8002)
10787 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 10788 else
10789 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 10790 } else {
7d0c41ef
MC		 10791 if (tp->phy_id != PHY_ID_INVALID) {
10792 /* Do nothing, phy ID already set up in
10793 * tg3_get_eeprom_hw_cfg().
10794 */
1da177e4
LT		 10795 } else {
10796 struct subsys_tbl_ent *p;
10797
10798 /* No eeprom signature? Try the hardcoded
10799 * subsys device table.
10800 */
10801 p = lookup_by_subsys(tp);
10802 if (!p)
10803 return -ENODEV;
10804
10805 tp->phy_id = p->phy_id;
10806 if (!tp->phy_id ||
10807 tp->phy_id == PHY_ID_BCM8002)
10808 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10809 }
10810 }
10811
747e8f8b 10812 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 10813 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 10814 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 10815 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 10816
10817 tg3_readphy(tp, MII_BMSR, &bmsr);
10818 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10819 (bmsr & BMSR_LSTATUS))
10820 goto skip_phy_reset;
6aa20a22 10821
1da177e4
LT		 10822 err = tg3_phy_reset(tp);
10823 if (err)
10824 return err;
10825
10826 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10827 ADVERTISE_100HALF | ADVERTISE_100FULL |
10828 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10829 tg3_ctrl = 0;
10830 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10831 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10832 MII_TG3_CTRL_ADV_1000_FULL);
10833 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10834 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10835 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10836 MII_TG3_CTRL_ENABLE_AS_MASTER);
10837 }
10838
3600d918
MC		 10839 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10840 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10841 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10842 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 10843 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10844
10845 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10846 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10847
10848 tg3_writephy(tp, MII_BMCR,
10849 BMCR_ANENABLE | BMCR_ANRESTART);
10850 }
10851 tg3_phy_set_wirespeed(tp);
10852
10853 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10854 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10855 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10856 }
10857
10858skip_phy_reset:
10859 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10860 err = tg3_init_5401phy_dsp(tp);
10861 if (err)
10862 return err;
10863 }
10864
10865 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10866 err = tg3_init_5401phy_dsp(tp);
10867 }
10868
747e8f8b 10869 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 10870 tp->link_config.advertising =
10871 (ADVERTISED_1000baseT_Half |
10872 ADVERTISED_1000baseT_Full |
10873 ADVERTISED_Autoneg |
10874 ADVERTISED_FIBRE);
10875 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10876 tp->link_config.advertising &=
10877 ~(ADVERTISED_1000baseT_Half |
10878 ADVERTISED_1000baseT_Full);
10879
10880 return err;
10881}
10882
10883static void __devinit tg3_read_partno(struct tg3 *tp)
10884{
10885 unsigned char vpd_data[256];
af2c6a4a 10886 unsigned int i;
1b27777a 10887 u32 magic;
1da177e4 10888
1820180b 10889 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 10890 goto out_not_found;
1da177e4 10891
1820180b 10892 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 10893 for (i = 0; i < 256; i += 4) {
10894 u32 tmp;
1da177e4 10895
1b27777a
MC		 10896 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10897 goto out_not_found;
10898
10899 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10900 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10901 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10902 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10903 }
10904 } else {
10905 int vpd_cap;
10906
10907 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10908 for (i = 0; i < 256; i += 4) {
10909 u32 tmp, j = 0;
b9fc7dc5 10910 __le32 v;
1b27777a
MC		 10911 u16 tmp16;
10912
10913 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10914 i);
10915 while (j++ < 100) {
10916 pci_read_config_word(tp->pdev, vpd_cap +
10917 PCI_VPD_ADDR, &tmp16);
10918 if (tmp16 & 0x8000)
10919 break;
10920 msleep(1);
10921 }
f49639e6
DM		 10922 if (!(tmp16 & 0x8000))
10923 goto out_not_found;
10924
1b27777a
MC		 10925 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10926 &tmp);
b9fc7dc5
AV		 10927 v = cpu_to_le32(tmp);
10928 memcpy(&vpd_data[i], &v, 4);
1b27777a 10929 }
1da177e4
LT		 10930 }
10931
10932 /* Now parse and find the part number. */
af2c6a4a 10933 for (i = 0; i < 254; ) {
1da177e4 10934 unsigned char val = vpd_data[i];
af2c6a4a 10935 unsigned int block_end;
1da177e4
LT		 10936
10937 if (val == 0x82 || val == 0x91) {
10938 i = (i + 3 +
10939 (vpd_data[i + 1] +
10940 (vpd_data[i + 2] << 8)));
10941 continue;
10942 }
10943
10944 if (val != 0x90)
10945 goto out_not_found;
10946
10947 block_end = (i + 3 +
10948 (vpd_data[i + 1] +
10949 (vpd_data[i + 2] << 8)));
10950 i += 3;
af2c6a4a
MC		 10951
10952 if (block_end > 256)
10953 goto out_not_found;
10954
10955 while (i < (block_end - 2)) {
1da177e4
LT		 10956 if (vpd_data[i + 0] == 'P' &&
10957 vpd_data[i + 1] == 'N') {
10958 int partno_len = vpd_data[i + 2];
10959
af2c6a4a
MC		 10960 i += 3;
10961 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 10962 goto out_not_found;
10963
10964 memcpy(tp->board_part_number,
af2c6a4a 10965 &vpd_data[i], partno_len);
1da177e4
LT		 10966
10967 /* Success. */
10968 return;
10969 }
af2c6a4a 10970 i += 3 + vpd_data[i + 2];
1da177e4
LT		 10971 }
10972
10973 /* Part number not found. */
10974 goto out_not_found;
10975 }
10976
10977out_not_found:
b5d3772c
MC		 10978 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10979 strcpy(tp->board_part_number, "BCM95906");
10980 else
10981 strcpy(tp->board_part_number, "none");
1da177e4
LT		 10982}
10983
9c8a620e
MC		 10984static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
10985{
10986 u32 val;
10987
10988 if (tg3_nvram_read_swab(tp, offset, &val) ||
10989 (val & 0xfc000000) != 0x0c000000 ||
10990 tg3_nvram_read_swab(tp, offset + 4, &val) ||
10991 val != 0)
10992 return 0;
10993
10994 return 1;
10995}
10996
c4e6575c
MC		 10997static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10998{
10999 u32 val, offset, start;
9c8a620e
MC		 11000 u32 ver_offset;
11001 int i, bcnt;
c4e6575c
MC		 11002
11003 if (tg3_nvram_read_swab(tp, 0, &val))
11004 return;
11005
11006 if (val != TG3_EEPROM_MAGIC)
11007 return;
11008
11009 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11010 tg3_nvram_read_swab(tp, 0x4, &start))
11011 return;
11012
11013 offset = tg3_nvram_logical_addr(tp, offset);
9c8a620e
MC		 11014
11015 if (!tg3_fw_img_is_valid(tp, offset) ||
11016 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
c4e6575c
MC		 11017 return;
11018
9c8a620e
MC		 11019 offset = offset + ver_offset - start;
11020 for (i = 0; i < 16; i += 4) {
b9fc7dc5
AV		 11021 __le32 v;
11022 if (tg3_nvram_read_le(tp, offset + i, &v))
9c8a620e
MC		 11023 return;
11024
b9fc7dc5 11025 memcpy(tp->fw_ver + i, &v, 4);
9c8a620e 11026 }
c4e6575c 11027
9c8a620e 11028 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
84af67fd 11029 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
9c8a620e
MC		 11030 return;
11031
11032 for (offset = TG3_NVM_DIR_START;
11033 offset < TG3_NVM_DIR_END;
11034 offset += TG3_NVM_DIRENT_SIZE) {
11035 if (tg3_nvram_read_swab(tp, offset, &val))
c4e6575c
MC		 11036 return;
11037
9c8a620e
MC		 11038 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11039 break;
11040 }
11041
11042 if (offset == TG3_NVM_DIR_END)
11043 return;
11044
11045 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11046 start = 0x08000000;
11047 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11048 return;
11049
11050 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11051 !tg3_fw_img_is_valid(tp, offset) ||
11052 tg3_nvram_read_swab(tp, offset + 8, &val))
11053 return;
11054
11055 offset += val - start;
11056
11057 bcnt = strlen(tp->fw_ver);
11058
11059 tp->fw_ver[bcnt++] = ',';
11060 tp->fw_ver[bcnt++] = ' ';
11061
11062 for (i = 0; i < 4; i++) {
b9fc7dc5
AV		 11063 __le32 v;
11064 if (tg3_nvram_read_le(tp, offset, &v))
c4e6575c
MC		 11065 return;
11066
b9fc7dc5 11067 offset += sizeof(v);
c4e6575c 11068
b9fc7dc5
AV		 11069 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11070 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
9c8a620e 11071 break;
c4e6575c 11072 }
9c8a620e 11073
b9fc7dc5
AV		 11074 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11075 bcnt += sizeof(v);
c4e6575c 11076 }
9c8a620e
MC		 11077
11078 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11079}
11080
7544b097
MC		 11081static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11082
1da177e4
LT		 11083static int __devinit tg3_get_invariants(struct tg3 *tp)
11084{
11085 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11086 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11087 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11088 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11089 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11090 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11091 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11092 { },
11093 };
11094 u32 misc_ctrl_reg;
11095 u32 cacheline_sz_reg;
11096 u32 pci_state_reg, grc_misc_cfg;
11097 u32 val;
11098 u16 pci_cmd;
c7835a77 11099 int err, pcie_cap;
1da177e4 11100
1da177e4
LT		 11101 /* Force memory write invalidate off. If we leave it on,
11102 * then on 5700_BX chips we have to enable a workaround.
11103 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11104 * to match the cacheline size. The Broadcom driver have this
11105 * workaround but turns MWI off all the times so never uses
11106 * it. This seems to suggest that the workaround is insufficient.
11107 */
11108 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11109 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11110 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11111
11112 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11113 * has the register indirect write enable bit set before
11114 * we try to access any of the MMIO registers. It is also
11115 * critical that the PCI-X hw workaround situation is decided
11116 * before that as well.
11117 */
11118 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11119 &misc_ctrl_reg);
11120
11121 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11122 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11124 u32 prod_id_asic_rev;
11125
11126 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11127 &prod_id_asic_rev);
11128 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11129 }
1da177e4 11130
ff645bec
MC		 11131 /* Wrong chip ID in 5752 A0. This code can be removed later
11132 * as A0 is not in production.
11133 */
11134 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11135 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11136
6892914f
MC		 11137 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11138 * we need to disable memory and use config. cycles
11139 * only to access all registers. The 5702/03 chips
11140 * can mistakenly decode the special cycles from the
11141 * ICH chipsets as memory write cycles, causing corruption
11142 * of register and memory space. Only certain ICH bridges
11143 * will drive special cycles with non-zero data during the
11144 * address phase which can fall within the 5703's address
11145 * range. This is not an ICH bug as the PCI spec allows
11146 * non-zero address during special cycles. However, only
11147 * these ICH bridges are known to drive non-zero addresses
11148 * during special cycles.
11149 *
11150 * Since special cycles do not cross PCI bridges, we only
11151 * enable this workaround if the 5703 is on the secondary
11152 * bus of these ICH bridges.
11153 */
11154 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11155 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11156 static struct tg3_dev_id {
11157 u32 vendor;
11158 u32 device;
11159 u32 rev;
11160 } ich_chipsets[] = {
11161 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11162 PCI_ANY_ID },
11163 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11164 PCI_ANY_ID },
11165 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11166 0xa },
11167 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11168 PCI_ANY_ID },
11169 { },
11170 };
11171 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11172 struct pci_dev *bridge = NULL;
11173
11174 while (pci_id->vendor != 0) {
11175 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11176 bridge);
11177 if (!bridge) {
11178 pci_id++;
11179 continue;
11180 }
11181 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11182 if (bridge->revision > pci_id->rev)
6892914f
MC		 11183 continue;
11184 }
11185 if (bridge->subordinate &&
11186 (bridge->subordinate->number ==
11187 tp->pdev->bus->number)) {
11188
11189 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11190 pci_dev_put(bridge);
11191 break;
11192 }
11193 }
11194 }
11195
4a29cc2e
MC		 11196 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11197 * DMA addresses > 40-bit. This bridge may have other additional
11198 * 57xx devices behind it in some 4-port NIC designs for example.
11199 * Any tg3 device found behind the bridge will also need the 40-bit
11200 * DMA workaround.
11201 */
a4e2b347
MC		 11202 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11204 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11205 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11206 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11207 }
4a29cc2e
MC		 11208 else {
11209 struct pci_dev *bridge = NULL;
11210
11211 do {
11212 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11213 PCI_DEVICE_ID_SERVERWORKS_EPB,
11214 bridge);
11215 if (bridge && bridge->subordinate &&
11216 (bridge->subordinate->number <=
11217 tp->pdev->bus->number) &&
11218 (bridge->subordinate->subordinate >=
11219 tp->pdev->bus->number)) {
11220 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11221 pci_dev_put(bridge);
11222 break;
11223 }
11224 } while (bridge);
11225 }
4cf78e4f 11226
1da177e4
LT		 11227 /* Initialize misc host control in PCI block. */
11228 tp->misc_host_ctrl |= (misc_ctrl_reg &
11229 MISC_HOST_CTRL_CHIPREV);
11230 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11231 tp->misc_host_ctrl);
11232
11233 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11234 &cacheline_sz_reg);
11235
11236 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
11237 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
11238 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
11239 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
11240
7544b097
MC		 11241 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11242 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11243 tp->pdev_peer = tg3_find_peer(tp);
11244
6708e5cc 11245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 11246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 11247 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11251 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
a4e2b347 11252 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11253 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11254
1b440c56
JL		 11255 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11256 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11257 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11258
5a6f3074 11259 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11260 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11261 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11262 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11263 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11264 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11265 tp->pdev_peer == tp->pdev))
11266 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11267
af36e6b6 11268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c 11269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11271 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11272 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11273 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11274 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11275 } else {
7f62ad5d 11276 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11277 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11278 ASIC_REV_5750 &&
11279 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11280 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11281 }
5a6f3074 11282 }
1da177e4 11283
0f893dc6
MC		 11284 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
11285 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
d9ab5ad1 11286 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
af36e6b6 11287 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
b5d3772c 11288 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
d30cdd28 11289 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
9936bcf6 11290 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
b5d3772c 11291 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
0f893dc6
MC		 11292 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11293
c7835a77
MC		 11294 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11295 if (pcie_cap != 0) {
1da177e4 11296 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 11297
11298 pcie_set_readrq(tp->pdev, 4096);
11299
c7835a77
MC		 11300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11301 u16 lnkctl;
11302
11303 pci_read_config_word(tp->pdev,
11304 pcie_cap + PCI_EXP_LNKCTL,
11305 &lnkctl);
11306 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
11307 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11308 }
11309 }
1da177e4 11310
399de50b
MC		 11311 /* If we have an AMD 762 or VIA K8T800 chipset, write
11312 * reordering to the mailbox registers done by the host
11313 * controller can cause major troubles. We read back from
11314 * every mailbox register write to force the writes to be
11315 * posted to the chip in order.
11316 */
11317 if (pci_dev_present(write_reorder_chipsets) &&
11318 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11319 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11320
1da177e4
LT		 11321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11322 tp->pci_lat_timer < 64) {
11323 tp->pci_lat_timer = 64;
11324
11325 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
11326 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
11327 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
11328 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
11329
11330 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11331 cacheline_sz_reg);
11332 }
11333
9974a356
MC		 11334 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11335 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11336 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11337 if (!tp->pcix_cap) {
11338 printk(KERN_ERR PFX "Cannot find PCI-X "
11339 "capability, aborting.\n");
11340 return -EIO;
11341 }
11342 }
11343
1da177e4
LT		 11344 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11345 &pci_state_reg);
11346
9974a356 11347 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
1da177e4
LT		 11348 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11349
11350 /* If this is a 5700 BX chipset, and we are in PCI-X
11351 * mode, enable register write workaround.
11352 *
11353 * The workaround is to use indirect register accesses
11354 * for all chip writes not to mailbox registers.
11355 */
11356 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11357 u32 pm_reg;
1da177e4
LT		 11358
11359 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11360
11361 /* The chip can have it's power management PCI config
11362 * space registers clobbered due to this bug.
11363 * So explicitly force the chip into D0 here.
11364 */
9974a356
MC		 11365 pci_read_config_dword(tp->pdev,
11366 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11367 &pm_reg);
11368 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11369 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 11370 pci_write_config_dword(tp->pdev,
11371 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11372 pm_reg);
11373
11374 /* Also, force SERR#/PERR# in PCI command. */
11375 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11376 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11377 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11378 }
11379 }
11380
087fe256
MC		 11381 /* 5700 BX chips need to have their TX producer index mailboxes
11382 * written twice to workaround a bug.
11383 */
11384 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
11385 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11386
1da177e4
LT		 11387 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11388 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11389 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11390 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11391
11392 /* Chip-specific fixup from Broadcom driver */
11393 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11394 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11395 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11396 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11397 }
11398
1ee582d8 11399 /* Default fast path register access methods */
20094930 11400 tp->read32 = tg3_read32;
1ee582d8 11401 tp->write32 = tg3_write32;
09ee929c 11402 tp->read32_mbox = tg3_read32;
20094930 11403 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 11404 tp->write32_tx_mbox = tg3_write32;
11405 tp->write32_rx_mbox = tg3_write32;
11406
11407 /* Various workaround register access methods */
11408 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11409 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 11410 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11411 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11412 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11413 /*
11414 * Back to back register writes can cause problems on these
11415 * chips, the workaround is to read back all reg writes
11416 * except those to mailbox regs.
11417 *
11418 * See tg3_write_indirect_reg32().
11419 */
1ee582d8 11420 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 11421 }
11422
1ee582d8
MC		 11423
11424 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11425 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11426 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11427 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11428 tp->write32_rx_mbox = tg3_write_flush_reg32;
11429 }
20094930 11430
6892914f
MC		 11431 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11432 tp->read32 = tg3_read_indirect_reg32;
11433 tp->write32 = tg3_write_indirect_reg32;
11434 tp->read32_mbox = tg3_read_indirect_mbox;
11435 tp->write32_mbox = tg3_write_indirect_mbox;
11436 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11437 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11438
11439 iounmap(tp->regs);
22abe310 11440 tp->regs = NULL;
6892914f
MC		 11441
11442 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11443 pci_cmd &= ~PCI_COMMAND_MEMORY;
11444 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11445 }
b5d3772c
MC		 11446 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11447 tp->read32_mbox = tg3_read32_mbox_5906;
11448 tp->write32_mbox = tg3_write32_mbox_5906;
11449 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11450 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11451 }
6892914f 11452
bbadf503
MC		 11453 if (tp->write32 == tg3_write_indirect_reg32 ||
11454 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11455 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 11456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 11457 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
11458
7d0c41ef 11459 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 11460 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 11461 * determined before calling tg3_set_power_state() so that
11462 * we know whether or not to switch out of Vaux power.
11463 * When the flag is set, it means that GPIO1 is used for eeprom
11464 * write protect and also implies that it is a LOM where GPIOs
11465 * are not used to switch power.
6aa20a22 11466 */
7d0c41ef
MC		 11467 tg3_get_eeprom_hw_cfg(tp);
11468
0d3031d9
MC		 11469 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
11470 /* Allow reads and writes to the
11471 * APE register and memory space.
11472 */
11473 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
11474 PCISTATE_ALLOW_APE_SHMEM_WR;
11475 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
11476 pci_state_reg);
11477 }
11478
9936bcf6 11479 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
b5af7126 11480 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d30cdd28
MC		 11481 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11482
b5af7126
MC		 11483 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
11484 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
11485 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
11486 tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
11487 tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
11488 }
11489
314fba34
MC		 11490 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
11491 * GPIO1 driven high will bring 5700's external PHY out of reset.
11492 * It is also used as eeprom write protect on LOMs.
11493 */
11494 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
11495 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11496 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
11497 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
11498 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 11499 /* Unused GPIO3 must be driven as output on 5752 because there
11500 * are no pull-up resistors on unused GPIO pins.
11501 */
11502 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11503 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 11504
af36e6b6
MC		 11505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11506 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11507
1da177e4 11508 /* Force the chip into D0. */
bc1c7567 11509 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 11510 if (err) {
11511 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
11512 pci_name(tp->pdev));
11513 return err;
11514 }
11515
11516 /* 5700 B0 chips do not support checksumming correctly due
11517 * to hardware bugs.
11518 */
11519 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11520 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11521
1da177e4
LT		 11522 /* Derive initial jumbo mode from MTU assigned in
11523 * ether_setup() via the alloc_etherdev() call
11524 */
0f893dc6 11525 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 11526 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 11527 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 11528
11529 /* Determine WakeOnLan speed to use. */
11530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11531 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11532 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
11533 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
11534 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
11535 } else {
11536 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
11537 }
11538
11539 /* A few boards don't want Ethernet@WireSpeed phy feature */
11540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11541 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
11542 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 11543 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 11544 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 11545 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 11546 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
11547
11548 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
11549 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
11550 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
11551 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
11552 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
11553
c424cb24
MC		 11554 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11555 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 11556 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 11557 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11558 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 11559 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
11560 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
11561 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 11562 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
11563 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
11564 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
c424cb24
MC		 11565 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
11566 }
1da177e4 11567
1da177e4 11568 tp->coalesce_mode = 0;
1da177e4
LT		 11569 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
11570 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
11571 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
11572
11573 /* Initialize MAC MI mode, polling disabled. */
11574 tw32_f(MAC_MI_MODE, tp->mi_mode);
11575 udelay(80);
11576
11577 /* Initialize data/descriptor byte/word swapping. */
11578 val = tr32(GRC_MODE);
11579 val &= GRC_MODE_HOST_STACKUP;
11580 tw32(GRC_MODE, val | tp->grc_mode);
11581
11582 tg3_switch_clocks(tp);
11583
11584 /* Clear this out for sanity. */
11585 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
11586
11587 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11588 &pci_state_reg);
11589 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
11590 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
11591 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
11592
11593 if (chiprevid == CHIPREV_ID_5701_A0 ||
11594 chiprevid == CHIPREV_ID_5701_B0 ||
11595 chiprevid == CHIPREV_ID_5701_B2 ||
11596 chiprevid == CHIPREV_ID_5701_B5) {
11597 void __iomem *sram_base;
11598
11599 /* Write some dummy words into the SRAM status block
11600 * area, see if it reads back correctly. If the return
11601 * value is bad, force enable the PCIX workaround.
11602 */
11603 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
11604
11605 writel(0x00000000, sram_base);
11606 writel(0x00000000, sram_base + 4);
11607 writel(0xffffffff, sram_base + 4);
11608 if (readl(sram_base) != 0x00000000)
11609 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11610 }
11611 }
11612
11613 udelay(50);
11614 tg3_nvram_init(tp);
11615
11616 grc_misc_cfg = tr32(GRC_MISC_CFG);
11617 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
11618
1da177e4
LT		 11619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11620 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
11621 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
11622 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
11623
fac9b83e
DM		 11624 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
11625 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
11626 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
11627 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
11628 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
11629 HOSTCC_MODE_CLRTICK_TXBD);
11630
11631 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
11632 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11633 tp->misc_host_ctrl);
11634 }
11635
1da177e4
LT		 11636 /* these are limited to 10/100 only */
11637 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11638 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
11639 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11640 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11641 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
11642 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
11643 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
11644 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11645 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 11646 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11647 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
b5d3772c 11648 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 11649 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11650
11651 err = tg3_phy_probe(tp);
11652 if (err) {
11653 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11654 pci_name(tp->pdev), err);
11655 /* ... but do not return immediately ... */
11656 }
11657
11658 tg3_read_partno(tp);
c4e6575c 11659 tg3_read_fw_ver(tp);
1da177e4
LT		 11660
11661 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11662 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11663 } else {
11664 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11665 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11666 else
11667 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11668 }
11669
11670 /* 5700 {AX,BX} chips have a broken status block link
11671 * change bit implementation, so we must use the
11672 * status register in those cases.
11673 */
11674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11675 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11676 else
11677 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11678
11679 /* The led_ctrl is set during tg3_phy_probe, here we might
11680 * have to force the link status polling mechanism based
11681 * upon subsystem IDs.
11682 */
11683 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 11684 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 11685 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11686 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11687 TG3_FLAG_USE_LINKCHG_REG);
11688 }
11689
11690 /* For all SERDES we poll the MAC status register. */
11691 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11692 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11693 else
11694 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11695
5a6f3074 11696 /* All chips before 5787 can get confused if TX buffers
1da177e4
LT		 11697 * straddle the 4GB address boundary in some cases.
11698 */
af36e6b6 11699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c 11700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11701 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
b5d3772c 11703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5a6f3074
MC		 11704 tp->dev->hard_start_xmit = tg3_start_xmit;
11705 else
11706 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
1da177e4
LT		 11707
11708 tp->rx_offset = 2;
11709 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11710 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11711 tp->rx_offset = 0;
11712
f92905de
MC		 11713 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11714
11715 /* Increment the rx prod index on the rx std ring by at most
11716 * 8 for these chips to workaround hw errata.
11717 */
11718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11719 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11720 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11721 tp->rx_std_max_post = 8;
11722
8ed5d97e
MC		 11723 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11724 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11725 PCIE_PWR_MGMT_L1_THRESH_MSK;
11726
1da177e4
LT		 11727 return err;
11728}
11729
49b6e95f 11730#ifdef CONFIG_SPARC
1da177e4
LT		 11731static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11732{
11733 struct net_device *dev = tp->dev;
11734 struct pci_dev *pdev = tp->pdev;
49b6e95f 11735 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 11736 const unsigned char *addr;
49b6e95f
DM		 11737 int len;
11738
11739 addr = of_get_property(dp, "local-mac-address", &len);
11740 if (addr && len == 6) {
11741 memcpy(dev->dev_addr, addr, 6);
11742 memcpy(dev->perm_addr, dev->dev_addr, 6);
11743 return 0;
1da177e4
LT		 11744 }
11745 return -ENODEV;
11746}
11747
11748static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11749{
11750 struct net_device *dev = tp->dev;
11751
11752 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 11753 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 11754 return 0;
11755}
11756#endif
11757
11758static int __devinit tg3_get_device_address(struct tg3 *tp)
11759{
11760 struct net_device *dev = tp->dev;
11761 u32 hi, lo, mac_offset;
008652b3 11762 int addr_ok = 0;
1da177e4 11763
49b6e95f 11764#ifdef CONFIG_SPARC
1da177e4
LT		 11765 if (!tg3_get_macaddr_sparc(tp))
11766 return 0;
11767#endif
11768
11769 mac_offset = 0x7c;
f49639e6 11770 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 11771 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 11772 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11773 mac_offset = 0xcc;
11774 if (tg3_nvram_lock(tp))
11775 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11776 else
11777 tg3_nvram_unlock(tp);
11778 }
b5d3772c
MC		 11779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11780 mac_offset = 0x10;
1da177e4
LT		 11781
11782 /* First try to get it from MAC address mailbox. */
11783 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11784 if ((hi >> 16) == 0x484b) {
11785 dev->dev_addr[0] = (hi >> 8) & 0xff;
11786 dev->dev_addr[1] = (hi >> 0) & 0xff;
11787
11788 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11789 dev->dev_addr[2] = (lo >> 24) & 0xff;
11790 dev->dev_addr[3] = (lo >> 16) & 0xff;
11791 dev->dev_addr[4] = (lo >> 8) & 0xff;
11792 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 11793
008652b3
MC		 11794 /* Some old bootcode may report a 0 MAC address in SRAM */
11795 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11796 }
11797 if (!addr_ok) {
11798 /* Next, try NVRAM. */
f49639e6 11799 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 11800 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11801 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11802 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11803 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11804 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11805 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11806 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11807 }
11808 /* Finally just fetch it out of the MAC control regs. */
11809 else {
11810 hi = tr32(MAC_ADDR_0_HIGH);
11811 lo = tr32(MAC_ADDR_0_LOW);
11812
11813 dev->dev_addr[5] = lo & 0xff;
11814 dev->dev_addr[4] = (lo >> 8) & 0xff;
11815 dev->dev_addr[3] = (lo >> 16) & 0xff;
11816 dev->dev_addr[2] = (lo >> 24) & 0xff;
11817 dev->dev_addr[1] = hi & 0xff;
11818 dev->dev_addr[0] = (hi >> 8) & 0xff;
11819 }
1da177e4
LT		 11820 }
11821
11822 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11823#ifdef CONFIG_SPARC64
11824 if (!tg3_get_default_macaddr_sparc(tp))
11825 return 0;
11826#endif
11827 return -EINVAL;
11828 }
2ff43697 11829 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 11830 return 0;
11831}
11832
59e6b434
DM		 11833#define BOUNDARY_SINGLE_CACHELINE 1
11834#define BOUNDARY_MULTI_CACHELINE 2
11835
11836static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11837{
11838 int cacheline_size;
11839 u8 byte;
11840 int goal;
11841
11842 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11843 if (byte == 0)
11844 cacheline_size = 1024;
11845 else
11846 cacheline_size = (int) byte * 4;
11847
11848 /* On 5703 and later chips, the boundary bits have no
11849 * effect.
11850 */
11851 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11852 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11853 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11854 goto out;
11855
11856#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11857 goal = BOUNDARY_MULTI_CACHELINE;
11858#else
11859#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11860 goal = BOUNDARY_SINGLE_CACHELINE;
11861#else
11862 goal = 0;
11863#endif
11864#endif
11865
11866 if (!goal)
11867 goto out;
11868
11869 /* PCI controllers on most RISC systems tend to disconnect
11870 * when a device tries to burst across a cache-line boundary.
11871 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11872 *
11873 * Unfortunately, for PCI-E there are only limited
11874 * write-side controls for this, and thus for reads
11875 * we will still get the disconnects. We'll also waste
11876 * these PCI cycles for both read and write for chips
11877 * other than 5700 and 5701 which do not implement the
11878 * boundary bits.
11879 */
11880 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11881 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11882 switch (cacheline_size) {
11883 case 16:
11884 case 32:
11885 case 64:
11886 case 128:
11887 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11888 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11889 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11890 } else {
11891 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11892 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11893 }
11894 break;
11895
11896 case 256:
11897 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11898 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11899 break;
11900
11901 default:
11902 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11903 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11904 break;
11905 };
11906 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11907 switch (cacheline_size) {
11908 case 16:
11909 case 32:
11910 case 64:
11911 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11912 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11913 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11914 break;
11915 }
11916 /* fallthrough */
11917 case 128:
11918 default:
11919 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11920 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11921 break;
11922 };
11923 } else {
11924 switch (cacheline_size) {
11925 case 16:
11926 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11927 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11928 DMA_RWCTRL_WRITE_BNDRY_16);
11929 break;
11930 }
11931 /* fallthrough */
11932 case 32:
11933 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11934 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11935 DMA_RWCTRL_WRITE_BNDRY_32);
11936 break;
11937 }
11938 /* fallthrough */
11939 case 64:
11940 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11941 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11942 DMA_RWCTRL_WRITE_BNDRY_64);
11943 break;
11944 }
11945 /* fallthrough */
11946 case 128:
11947 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11948 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11949 DMA_RWCTRL_WRITE_BNDRY_128);
11950 break;
11951 }
11952 /* fallthrough */
11953 case 256:
11954 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11955 DMA_RWCTRL_WRITE_BNDRY_256);
11956 break;
11957 case 512:
11958 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11959 DMA_RWCTRL_WRITE_BNDRY_512);
11960 break;
11961 case 1024:
11962 default:
11963 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11964 DMA_RWCTRL_WRITE_BNDRY_1024);
11965 break;
11966 };
11967 }
11968
11969out:
11970 return val;
11971}
11972
1da177e4
LT		 11973static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11974{
11975 struct tg3_internal_buffer_desc test_desc;
11976 u32 sram_dma_descs;
11977 int i, ret;
11978
11979 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11980
11981 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11982 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11983 tw32(RDMAC_STATUS, 0);
11984 tw32(WDMAC_STATUS, 0);
11985
11986 tw32(BUFMGR_MODE, 0);
11987 tw32(FTQ_RESET, 0);
11988
11989 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11990 test_desc.addr_lo = buf_dma & 0xffffffff;
11991 test_desc.nic_mbuf = 0x00002100;
11992 test_desc.len = size;
11993
11994 /*
11995 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11996 * the *second* time the tg3 driver was getting loaded after an
11997 * initial scan.
11998 *
11999 * Broadcom tells me:
12000 * ...the DMA engine is connected to the GRC block and a DMA
12001 * reset may affect the GRC block in some unpredictable way...
12002 * The behavior of resets to individual blocks has not been tested.
12003 *
12004 * Broadcom noted the GRC reset will also reset all sub-components.
12005 */
12006 if (to_device) {
12007 test_desc.cqid_sqid = (13 << 8) | 2;
12008
12009 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12010 udelay(40);
12011 } else {
12012 test_desc.cqid_sqid = (16 << 8) | 7;
12013
12014 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12015 udelay(40);
12016 }
12017 test_desc.flags = 0x00000005;
12018
12019 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12020 u32 val;
12021
12022 val = *(((u32 *)&test_desc) + i);
12023 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12024 sram_dma_descs + (i * sizeof(u32)));
12025 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12026 }
12027 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12028
12029 if (to_device) {
12030 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12031 } else {
12032 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12033 }
12034
12035 ret = -ENODEV;
12036 for (i = 0; i < 40; i++) {
12037 u32 val;
12038
12039 if (to_device)
12040 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12041 else
12042 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12043 if ((val & 0xffff) == sram_dma_descs) {
12044 ret = 0;
12045 break;
12046 }
12047
12048 udelay(100);
12049 }
12050
12051 return ret;
12052}
12053
ded7340d 12054#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12055
12056static int __devinit tg3_test_dma(struct tg3 *tp)
12057{
12058 dma_addr_t buf_dma;
59e6b434 12059 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12060 int ret;
12061
12062 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12063 if (!buf) {
12064 ret = -ENOMEM;
12065 goto out_nofree;
12066 }
12067
12068 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12069 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12070
59e6b434 12071 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12072
12073 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12074 /* DMA read watermark not used on PCIE */
12075 tp->dma_rwctrl |= 0x00180000;
12076 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12077 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12079 tp->dma_rwctrl |= 0x003f0000;
12080 else
12081 tp->dma_rwctrl |= 0x003f000f;
12082 } else {
12083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12085 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12086 u32 read_water = 0x7;
1da177e4 12087
4a29cc2e
MC		 12088 /* If the 5704 is behind the EPB bridge, we can
12089 * do the less restrictive ONE_DMA workaround for
12090 * better performance.
12091 */
12092 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12094 tp->dma_rwctrl |= 0x8000;
12095 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12096 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12097
49afdeb6
MC		 12098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12099 read_water = 4;
59e6b434 12100 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12101 tp->dma_rwctrl |=
12102 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12103 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12104 (1 << 23);
4cf78e4f
MC		 12105 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12106 /* 5780 always in PCIX mode */
12107 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12108 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12109 /* 5714 always in PCIX mode */
12110 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12111 } else {
12112 tp->dma_rwctrl |= 0x001b000f;
12113 }
12114 }
12115
12116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12117 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12118 tp->dma_rwctrl &= 0xfffffff0;
12119
12120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12121 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12122 /* Remove this if it causes problems for some boards. */
12123 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12124
12125 /* On 5700/5701 chips, we need to set this bit.
12126 * Otherwise the chip will issue cacheline transactions
12127 * to streamable DMA memory with not all the byte
12128 * enables turned on. This is an error on several
12129 * RISC PCI controllers, in particular sparc64.
12130 *
12131 * On 5703/5704 chips, this bit has been reassigned
12132 * a different meaning. In particular, it is used
12133 * on those chips to enable a PCI-X workaround.
12134 */
12135 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12136 }
12137
12138 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12139
12140#if 0
12141 /* Unneeded, already done by tg3_get_invariants. */
12142 tg3_switch_clocks(tp);
12143#endif
12144
12145 ret = 0;
12146 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12147 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12148 goto out;
12149
59e6b434
DM		 12150 /* It is best to perform DMA test with maximum write burst size
12151 * to expose the 5700/5701 write DMA bug.
12152 */
12153 saved_dma_rwctrl = tp->dma_rwctrl;
12154 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12155 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12156
1da177e4
LT		 12157 while (1) {
12158 u32 *p = buf, i;
12159
12160 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12161 p[i] = i;
12162
12163 /* Send the buffer to the chip. */
12164 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12165 if (ret) {
12166 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12167 break;
12168 }
12169
12170#if 0
12171 /* validate data reached card RAM correctly. */
12172 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12173 u32 val;
12174 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12175 if (le32_to_cpu(val) != p[i]) {
12176 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12177 /* ret = -ENODEV here? */
12178 }
12179 p[i] = 0;
12180 }
12181#endif
12182 /* Now read it back. */
12183 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12184 if (ret) {
12185 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12186
12187 break;
12188 }
12189
12190 /* Verify it. */
12191 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12192 if (p[i] == i)
12193 continue;
12194
59e6b434
DM		 12195 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12196 DMA_RWCTRL_WRITE_BNDRY_16) {
12197 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12198 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12199 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12200 break;
12201 } else {
12202 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12203 ret = -ENODEV;
12204 goto out;
12205 }
12206 }
12207
12208 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12209 /* Success. */
12210 ret = 0;
12211 break;
12212 }
12213 }
59e6b434
DM		 12214 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12215 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12216 static struct pci_device_id dma_wait_state_chipsets[] = {
12217 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12218 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12219 { },
12220 };
12221
59e6b434 12222 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12223 * now look for chipsets that are known to expose the
12224 * DMA bug without failing the test.
59e6b434 12225 */
6d1cfbab
MC		 12226 if (pci_dev_present(dma_wait_state_chipsets)) {
12227 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12228 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12229 }
12230 else
12231 /* Safe to use the calculated DMA boundary. */
12232 tp->dma_rwctrl = saved_dma_rwctrl;
12233
59e6b434
DM		 12234 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12235 }
1da177e4
LT		 12236
12237out:
12238 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12239out_nofree:
12240 return ret;
12241}
12242
12243static void __devinit tg3_init_link_config(struct tg3 *tp)
12244{
12245 tp->link_config.advertising =
12246 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12247 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12248 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12249 ADVERTISED_Autoneg | ADVERTISED_MII);
12250 tp->link_config.speed = SPEED_INVALID;
12251 tp->link_config.duplex = DUPLEX_INVALID;
12252 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12253 tp->link_config.active_speed = SPEED_INVALID;
12254 tp->link_config.active_duplex = DUPLEX_INVALID;
12255 tp->link_config.phy_is_low_power = 0;
12256 tp->link_config.orig_speed = SPEED_INVALID;
12257 tp->link_config.orig_duplex = DUPLEX_INVALID;
12258 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12259}
12260
12261static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12262{
fdfec172
MC		 12263 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12264 tp->bufmgr_config.mbuf_read_dma_low_water =
12265 DEFAULT_MB_RDMA_LOW_WATER_5705;
12266 tp->bufmgr_config.mbuf_mac_rx_low_water =
12267 DEFAULT_MB_MACRX_LOW_WATER_5705;
12268 tp->bufmgr_config.mbuf_high_water =
12269 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12270 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12271 tp->bufmgr_config.mbuf_mac_rx_low_water =
12272 DEFAULT_MB_MACRX_LOW_WATER_5906;
12273 tp->bufmgr_config.mbuf_high_water =
12274 DEFAULT_MB_HIGH_WATER_5906;
12275 }
fdfec172
MC		 12276
12277 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12278 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12279 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12280 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12281 tp->bufmgr_config.mbuf_high_water_jumbo =
12282 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12283 } else {
12284 tp->bufmgr_config.mbuf_read_dma_low_water =
12285 DEFAULT_MB_RDMA_LOW_WATER;
12286 tp->bufmgr_config.mbuf_mac_rx_low_water =
12287 DEFAULT_MB_MACRX_LOW_WATER;
12288 tp->bufmgr_config.mbuf_high_water =
12289 DEFAULT_MB_HIGH_WATER;
12290
12291 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12292 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12293 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12294 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12295 tp->bufmgr_config.mbuf_high_water_jumbo =
12296 DEFAULT_MB_HIGH_WATER_JUMBO;
12297 }
1da177e4
LT		 12298
12299 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12300 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12301}
12302
12303static char * __devinit tg3_phy_string(struct tg3 *tp)
12304{
12305 switch (tp->phy_id & PHY_ID_MASK) {
12306 case PHY_ID_BCM5400: return "5400";
12307 case PHY_ID_BCM5401: return "5401";
12308 case PHY_ID_BCM5411: return "5411";
12309 case PHY_ID_BCM5701: return "5701";
12310 case PHY_ID_BCM5703: return "5703";
12311 case PHY_ID_BCM5704: return "5704";
12312 case PHY_ID_BCM5705: return "5705";
12313 case PHY_ID_BCM5750: return "5750";
85e94ced 12314 case PHY_ID_BCM5752: return "5752";
a4e2b347 12315 case PHY_ID_BCM5714: return "5714";
4cf78e4f 12316 case PHY_ID_BCM5780: return "5780";
af36e6b6 12317 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 12318 case PHY_ID_BCM5787: return "5787";
d30cdd28 12319 case PHY_ID_BCM5784: return "5784";
126a3368 12320 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 12321 case PHY_ID_BCM5906: return "5906";
9936bcf6 12322 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 12323 case PHY_ID_BCM8002: return "8002/serdes";
12324 case 0: return "serdes";
12325 default: return "unknown";
12326 };
12327}
12328
f9804ddb
MC		 12329static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12330{
12331 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12332 strcpy(str, "PCI Express");
12333 return str;
12334 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12335 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12336
12337 strcpy(str, "PCIX:");
12338
12339 if ((clock_ctrl == 7) ||
12340 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12341 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12342 strcat(str, "133MHz");
12343 else if (clock_ctrl == 0)
12344 strcat(str, "33MHz");
12345 else if (clock_ctrl == 2)
12346 strcat(str, "50MHz");
12347 else if (clock_ctrl == 4)
12348 strcat(str, "66MHz");
12349 else if (clock_ctrl == 6)
12350 strcat(str, "100MHz");
f9804ddb
MC		 12351 } else {
12352 strcpy(str, "PCI:");
12353 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12354 strcat(str, "66MHz");
12355 else
12356 strcat(str, "33MHz");
12357 }
12358 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12359 strcat(str, ":32-bit");
12360 else
12361 strcat(str, ":64-bit");
12362 return str;
12363}
12364
8c2dc7e1 12365static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 12366{
12367 struct pci_dev *peer;
12368 unsigned int func, devnr = tp->pdev->devfn & ~7;
12369
12370 for (func = 0; func < 8; func++) {
12371 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12372 if (peer && peer != tp->pdev)
12373 break;
12374 pci_dev_put(peer);
12375 }
16fe9d74
MC		 12376 /* 5704 can be configured in single-port mode, set peer to
12377 * tp->pdev in that case.
12378 */
12379 if (!peer) {
12380 peer = tp->pdev;
12381 return peer;
12382 }
1da177e4
LT		 12383
12384 /*
12385 * We don't need to keep the refcount elevated; there's no way
12386 * to remove one half of this device without removing the other
12387 */
12388 pci_dev_put(peer);
12389
12390 return peer;
12391}
12392
15f9850d
DM		 12393static void __devinit tg3_init_coal(struct tg3 *tp)
12394{
12395 struct ethtool_coalesce *ec = &tp->coal;
12396
12397 memset(ec, 0, sizeof(*ec));
12398 ec->cmd = ETHTOOL_GCOALESCE;
12399 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12400 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12401 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12402 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12403 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12404 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12405 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12406 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12407 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12408
12409 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12410 HOSTCC_MODE_CLRTICK_TXBD)) {
12411 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12412 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12413 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12414 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12415 }
d244c892
MC		 12416
12417 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12418 ec->rx_coalesce_usecs_irq = 0;
12419 ec->tx_coalesce_usecs_irq = 0;
12420 ec->stats_block_coalesce_usecs = 0;
12421 }
15f9850d
DM		 12422}
12423
1da177e4
LT		 12424static int __devinit tg3_init_one(struct pci_dev *pdev,
12425 const struct pci_device_id *ent)
12426{
12427 static int tg3_version_printed = 0;
12428 unsigned long tg3reg_base, tg3reg_len;
12429 struct net_device *dev;
12430 struct tg3 *tp;
d6645372 12431 int err, pm_cap;
f9804ddb 12432 char str[40];
72f2afb8 12433 u64 dma_mask, persist_dma_mask;
d6645372 12434 DECLARE_MAC_BUF(mac);
1da177e4
LT		 12435
12436 if (tg3_version_printed++ == 0)
12437 printk(KERN_INFO "%s", version);
12438
12439 err = pci_enable_device(pdev);
12440 if (err) {
12441 printk(KERN_ERR PFX "Cannot enable PCI device, "
12442 "aborting.\n");
12443 return err;
12444 }
12445
12446 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12447 printk(KERN_ERR PFX "Cannot find proper PCI device "
12448 "base address, aborting.\n");
12449 err = -ENODEV;
12450 goto err_out_disable_pdev;
12451 }
12452
12453 err = pci_request_regions(pdev, DRV_MODULE_NAME);
12454 if (err) {
12455 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
12456 "aborting.\n");
12457 goto err_out_disable_pdev;
12458 }
12459
12460 pci_set_master(pdev);
12461
12462 /* Find power-management capability. */
12463 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12464 if (pm_cap == 0) {
12465 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
12466 "aborting.\n");
12467 err = -EIO;
12468 goto err_out_free_res;
12469 }
12470
1da177e4
LT		 12471 tg3reg_base = pci_resource_start(pdev, 0);
12472 tg3reg_len = pci_resource_len(pdev, 0);
12473
12474 dev = alloc_etherdev(sizeof(*tp));
12475 if (!dev) {
12476 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
12477 err = -ENOMEM;
12478 goto err_out_free_res;
12479 }
12480
1da177e4
LT		 12481 SET_NETDEV_DEV(dev, &pdev->dev);
12482
1da177e4
LT		 12483#if TG3_VLAN_TAG_USED
12484 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
12485 dev->vlan_rx_register = tg3_vlan_rx_register;
1da177e4
LT		 12486#endif
12487
12488 tp = netdev_priv(dev);
12489 tp->pdev = pdev;
12490 tp->dev = dev;
12491 tp->pm_cap = pm_cap;
12492 tp->mac_mode = TG3_DEF_MAC_MODE;
12493 tp->rx_mode = TG3_DEF_RX_MODE;
12494 tp->tx_mode = TG3_DEF_TX_MODE;
12495 tp->mi_mode = MAC_MI_MODE_BASE;
12496 if (tg3_debug > 0)
12497 tp->msg_enable = tg3_debug;
12498 else
12499 tp->msg_enable = TG3_DEF_MSG_ENABLE;
12500
12501 /* The word/byte swap controls here control register access byte
12502 * swapping. DMA data byte swapping is controlled in the GRC_MODE
12503 * setting below.
12504 */
12505 tp->misc_host_ctrl =
12506 MISC_HOST_CTRL_MASK_PCI_INT |
12507 MISC_HOST_CTRL_WORD_SWAP |
12508 MISC_HOST_CTRL_INDIR_ACCESS |
12509 MISC_HOST_CTRL_PCISTATE_RW;
12510
12511 /* The NONFRM (non-frame) byte/word swap controls take effect
12512 * on descriptor entries, anything which isn't packet data.
12513 *
12514 * The StrongARM chips on the board (one for tx, one for rx)
12515 * are running in big-endian mode.
12516 */
12517 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
12518 GRC_MODE_WSWAP_NONFRM_DATA);
12519#ifdef __BIG_ENDIAN
12520 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
12521#endif
12522 spin_lock_init(&tp->lock);
1da177e4 12523 spin_lock_init(&tp->indirect_lock);
c4028958 12524 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4
LT		 12525
12526 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
ab0049b4 12527 if (!tp->regs) {
1da177e4
LT		 12528 printk(KERN_ERR PFX "Cannot map device registers, "
12529 "aborting.\n");
12530 err = -ENOMEM;
12531 goto err_out_free_dev;
12532 }
12533
12534 tg3_init_link_config(tp);
12535
1da177e4
LT		 12536 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
12537 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
12538 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
12539
12540 dev->open = tg3_open;
12541 dev->stop = tg3_close;
12542 dev->get_stats = tg3_get_stats;
12543 dev->set_multicast_list = tg3_set_rx_mode;
12544 dev->set_mac_address = tg3_set_mac_addr;
12545 dev->do_ioctl = tg3_ioctl;
12546 dev->tx_timeout = tg3_tx_timeout;
bea3348e 12547 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 12548 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4
LT		 12549 dev->watchdog_timeo = TG3_TX_TIMEOUT;
12550 dev->change_mtu = tg3_change_mtu;
12551 dev->irq = pdev->irq;
12552#ifdef CONFIG_NET_POLL_CONTROLLER
12553 dev->poll_controller = tg3_poll_controller;
12554#endif
12555
12556 err = tg3_get_invariants(tp);
12557 if (err) {
12558 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
12559 "aborting.\n");
12560 goto err_out_iounmap;
12561 }
12562
4a29cc2e
MC		 12563 /* The EPB bridge inside 5714, 5715, and 5780 and any
12564 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 12565 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
12566 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
12567 * do DMA address check in tg3_start_xmit().
12568 */
4a29cc2e
MC		 12569 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
12570 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
12571 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 12572 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
12573#ifdef CONFIG_HIGHMEM
12574 dma_mask = DMA_64BIT_MASK;
12575#endif
4a29cc2e 12576 } else
72f2afb8
MC		 12577 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
12578
12579 /* Configure DMA attributes. */
12580 if (dma_mask > DMA_32BIT_MASK) {
12581 err = pci_set_dma_mask(pdev, dma_mask);
12582 if (!err) {
12583 dev->features |= NETIF_F_HIGHDMA;
12584 err = pci_set_consistent_dma_mask(pdev,
12585 persist_dma_mask);
12586 if (err < 0) {
12587 printk(KERN_ERR PFX "Unable to obtain 64 bit "
12588 "DMA for consistent allocations\n");
12589 goto err_out_iounmap;
12590 }
12591 }
12592 }
12593 if (err || dma_mask == DMA_32BIT_MASK) {
12594 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
12595 if (err) {
12596 printk(KERN_ERR PFX "No usable DMA configuration, "
12597 "aborting.\n");
12598 goto err_out_iounmap;
12599 }
12600 }
12601
fdfec172 12602 tg3_init_bufmgr_config(tp);
1da177e4 12603
1da177e4
LT		 12604 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12605 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
12606 }
12607 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12608 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12609 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 12610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 12611 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
12612 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
12613 } else {
7f62ad5d 12614 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
1da177e4
LT		 12615 }
12616
4e3a7aaa
MC		 12617 /* TSO is on by default on chips that support hardware TSO.
12618 * Firmware TSO on older chips gives lower performance, so it
12619 * is off by default, but can be enabled using ethtool.
12620 */
b0026624 12621 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 12622 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 12623 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
12624 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624 12625 dev->features |= NETIF_F_TSO6;
9936bcf6
MC		 12626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12627 dev->features |= NETIF_F_TSO_ECN;
b0026624 12628 }
1da177e4 12629
1da177e4
LT		 12630
12631 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
12632 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
12633 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
12634 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
12635 tp->rx_pending = 63;
12636 }
12637
1da177e4
LT		 12638 err = tg3_get_device_address(tp);
12639 if (err) {
12640 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
12641 "aborting.\n");
12642 goto err_out_iounmap;
12643 }
12644
c88864df
MC		 12645 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12646 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12647 printk(KERN_ERR PFX "Cannot find proper PCI device "
12648 "base address for APE, aborting.\n");
12649 err = -ENODEV;
12650 goto err_out_iounmap;
12651 }
12652
12653 tg3reg_base = pci_resource_start(pdev, 2);
12654 tg3reg_len = pci_resource_len(pdev, 2);
12655
12656 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
12657 if (tp->aperegs == 0UL) {
12658 printk(KERN_ERR PFX "Cannot map APE registers, "
12659 "aborting.\n");
12660 err = -ENOMEM;
12661 goto err_out_iounmap;
12662 }
12663
12664 tg3_ape_lock_init(tp);
12665 }
12666
1da177e4
LT		 12667 /*
12668 * Reset chip in case UNDI or EFI driver did not shutdown
12669 * DMA self test will enable WDMAC and we'll see (spurious)
12670 * pending DMA on the PCI bus at that point.
12671 */
12672 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12673 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 12674 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 12675 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 12676 }
12677
12678 err = tg3_test_dma(tp);
12679 if (err) {
12680 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 12681 goto err_out_apeunmap;
1da177e4
LT		 12682 }
12683
12684 /* Tigon3 can do ipv4 only... and some chips have buggy
12685 * checksumming.
12686 */
12687 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
d212f87b 12688 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
af36e6b6 12689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12690 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12692 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
d212f87b
SH		 12693 dev->features |= NETIF_F_IPV6_CSUM;
12694
1da177e4
LT		 12695 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12696 } else
12697 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12698
1da177e4
LT		 12699 /* flow control autonegotiation is default behavior */
12700 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8d018621 12701 tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1da177e4 12702
15f9850d
DM		 12703 tg3_init_coal(tp);
12704
c49a1561
MC		 12705 pci_set_drvdata(pdev, dev);
12706
1da177e4
LT		 12707 err = register_netdev(dev);
12708 if (err) {
12709 printk(KERN_ERR PFX "Cannot register net device, "
12710 "aborting.\n");
0d3031d9 12711 goto err_out_apeunmap;
1da177e4
LT		 12712 }
12713
d6645372
JP		 12714 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
12715 "(%s) %s Ethernet %s\n",
1da177e4
LT		 12716 dev->name,
12717 tp->board_part_number,
12718 tp->pci_chip_rev_id,
12719 tg3_phy_string(tp),
f9804ddb 12720 tg3_bus_string(tp, str),
cbb45d21
MC		 12721 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12722 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
d6645372
JP		 12723 "10/100/1000Base-T")),
12724 print_mac(mac, dev->dev_addr));
1da177e4
LT		 12725
12726 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
1c46ae05 12727 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
1da177e4
LT		 12728 dev->name,
12729 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12730 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12731 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12732 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4
LT		 12733 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12734 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 12735 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12736 dev->name, tp->dma_rwctrl,
12737 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12738 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 12739
12740 return 0;
12741
0d3031d9
MC		 12742err_out_apeunmap:
12743 if (tp->aperegs) {
12744 iounmap(tp->aperegs);
12745 tp->aperegs = NULL;
12746 }
12747
1da177e4 12748err_out_iounmap:
6892914f
MC		 12749 if (tp->regs) {
12750 iounmap(tp->regs);
22abe310 12751 tp->regs = NULL;
6892914f 12752 }
1da177e4
LT		 12753
12754err_out_free_dev:
12755 free_netdev(dev);
12756
12757err_out_free_res:
12758 pci_release_regions(pdev);
12759
12760err_out_disable_pdev:
12761 pci_disable_device(pdev);
12762 pci_set_drvdata(pdev, NULL);
12763 return err;
12764}
12765
12766static void __devexit tg3_remove_one(struct pci_dev *pdev)
12767{
12768 struct net_device *dev = pci_get_drvdata(pdev);
12769
12770 if (dev) {
12771 struct tg3 *tp = netdev_priv(dev);
12772
7faa006f 12773 flush_scheduled_work();
1da177e4 12774 unregister_netdev(dev);
0d3031d9
MC		 12775 if (tp->aperegs) {
12776 iounmap(tp->aperegs);
12777 tp->aperegs = NULL;
12778 }
6892914f
MC		 12779 if (tp->regs) {
12780 iounmap(tp->regs);
22abe310 12781 tp->regs = NULL;
6892914f 12782 }
1da177e4
LT		 12783 free_netdev(dev);
12784 pci_release_regions(pdev);
12785 pci_disable_device(pdev);
12786 pci_set_drvdata(pdev, NULL);
12787 }
12788}
12789
12790static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12791{
12792 struct net_device *dev = pci_get_drvdata(pdev);
12793 struct tg3 *tp = netdev_priv(dev);
12794 int err;
12795
3e0c95fd
MC		 12796 /* PCI register 4 needs to be saved whether netif_running() or not.
12797 * MSI address and data need to be saved if using MSI and
12798 * netif_running().
12799 */
12800 pci_save_state(pdev);
12801
1da177e4
LT		 12802 if (!netif_running(dev))
12803 return 0;
12804
7faa006f 12805 flush_scheduled_work();
1da177e4
LT		 12806 tg3_netif_stop(tp);
12807
12808 del_timer_sync(&tp->timer);
12809
f47c11ee 12810 tg3_full_lock(tp, 1);
1da177e4 12811 tg3_disable_ints(tp);
f47c11ee 12812 tg3_full_unlock(tp);
1da177e4
LT		 12813
12814 netif_device_detach(dev);
12815
f47c11ee 12816 tg3_full_lock(tp, 0);
944d980e 12817 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 12818 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 12819 tg3_full_unlock(tp);
1da177e4
LT		 12820
12821 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12822 if (err) {
f47c11ee 12823 tg3_full_lock(tp, 0);
1da177e4 12824
6a9eba15 12825 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12826 if (tg3_restart_hw(tp, 1))
12827 goto out;
1da177e4
LT		 12828
12829 tp->timer.expires = jiffies + tp->timer_offset;
12830 add_timer(&tp->timer);
12831
12832 netif_device_attach(dev);
12833 tg3_netif_start(tp);
12834
b9ec6c1b 12835out:
f47c11ee 12836 tg3_full_unlock(tp);
1da177e4
LT		 12837 }
12838
12839 return err;
12840}
12841
12842static int tg3_resume(struct pci_dev *pdev)
12843{
12844 struct net_device *dev = pci_get_drvdata(pdev);
12845 struct tg3 *tp = netdev_priv(dev);
12846 int err;
12847
3e0c95fd
MC		 12848 pci_restore_state(tp->pdev);
12849
1da177e4
LT		 12850 if (!netif_running(dev))
12851 return 0;
12852
bc1c7567 12853 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12854 if (err)
12855 return err;
12856
12857 netif_device_attach(dev);
12858
f47c11ee 12859 tg3_full_lock(tp, 0);
1da177e4 12860
6a9eba15 12861 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12862 err = tg3_restart_hw(tp, 1);
12863 if (err)
12864 goto out;
1da177e4
LT		 12865
12866 tp->timer.expires = jiffies + tp->timer_offset;
12867 add_timer(&tp->timer);
12868
1da177e4
LT		 12869 tg3_netif_start(tp);
12870
b9ec6c1b 12871out:
f47c11ee 12872 tg3_full_unlock(tp);
1da177e4 12873
b9ec6c1b 12874 return err;
1da177e4
LT		 12875}
12876
12877static struct pci_driver tg3_driver = {
12878 .name = DRV_MODULE_NAME,
12879 .id_table = tg3_pci_tbl,
12880 .probe = tg3_init_one,
12881 .remove = __devexit_p(tg3_remove_one),
12882 .suspend = tg3_suspend,
12883 .resume = tg3_resume
12884};
12885
12886static int __init tg3_init(void)
12887{
29917620 12888 return pci_register_driver(&tg3_driver);
1da177e4
LT		 12889}
12890
12891static void __exit tg3_cleanup(void)
12892{
12893 pci_unregister_driver(&tg3_driver);
12894}
12895
12896module_init(tg3_init);
12897module_exit(tg3_cleanup);
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