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[TG3]: Add ASPM workaround.
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
61487480 39#include <linux/prefetch.h>
f9a5f7d3 40#include <linux/dma-mapping.h>
1da177e4
LT		 41
42#include <net/checksum.h>
c9bdd4b5 43#include <net/ip.h>
1da177e4
LT		 44
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/byteorder.h>
48#include <asm/uaccess.h>
49
49b6e95f 50#ifdef CONFIG_SPARC
1da177e4 51#include <asm/idprom.h>
49b6e95f 52#include <asm/prom.h>
1da177e4
LT		 53#endif
54
55#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56#define TG3_VLAN_TAG_USED 1
57#else
58#define TG3_VLAN_TAG_USED 0
59#endif
60
1da177e4 61#define TG3_TSO_SUPPORT 1
1da177e4
LT		 62
63#include "tg3.h"
64
65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": "
20bd7dd4
MC		 67#define DRV_MODULE_VERSION "3.75"
68#define DRV_MODULE_RELDATE "March 23, 2007"
1da177e4
LT		 69
70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0
72#define TG3_DEF_TX_MODE 0
73#define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83/* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86#define TG3_TX_TIMEOUT (5 * HZ)
87
88/* hardware minimum and maximum for a single frame's data payload */
89#define TG3_MIN_MTU 60
90#define TG3_MAX_MTU(tp) \
0f893dc6 91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 92
93/* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97#define TG3_RX_RING_SIZE 512
98#define TG3_DEF_RX_RING_PENDING 200
99#define TG3_RX_JUMBO_RING_SIZE 256
100#define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102/* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108#define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111#define TG3_TX_RING_SIZE 512
112#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
1da177e4
LT		 122#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127/* minimum number of free TX descriptors required to wake up TX process */
42952231 128#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4
LT		 129
130/* number of ETHTOOL_GSTATS u64's */
131#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
4cafd3f5
MC		 133#define TG3_NUM_TEST 6
134
1da177e4
LT		 135static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_MODULE_VERSION);
142
143static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144module_param(tg3_debug, int, 0);
145MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
13185217
HK		 201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
1da177e4
LT		 209};
210
211MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
50da859d 213static const struct {
1da177e4
LT		 214 const char string[ETH_GSTRING_LEN];
215} ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292};
293
50da859d 294static const struct {
4cafd3f5
MC		 295 const char string[ETH_GSTRING_LEN];
296} ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303};
304
b401e9e2
MC		 305static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306{
307 writel(val, tp->regs + off);
308}
309
310static u32 tg3_read32(struct tg3 *tp, u32 off)
311{
6aa20a22 312 return (readl(tp->regs + off));
b401e9e2
MC		 313}
314
1da177e4
LT		 315static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316{
6892914f
MC		 317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 323}
324
325static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326{
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
1da177e4
LT		 329}
330
6892914f 331static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 332{
6892914f
MC		 333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341}
342
343static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344{
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
1da177e4 356 }
6892914f
MC		 357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371}
372
373static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374{
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383}
384
b401e9e2
MC		 385/* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 391{
b401e9e2
MC		 392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
1da177e4
LT		 408}
409
09ee929c
MC		 410static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411{
412 tp->write32_mbox(tp, off, val);
6892914f
MC		 413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
09ee929c
MC		 416}
417
20094930 418static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 419{
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426}
427
b5d3772c
MC		 428static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429{
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431}
432
433static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434{
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436}
437
20094930 438#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 439#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 440#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 442#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 443
444#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 445#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 447#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 448
449static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450{
6892914f
MC		 451 unsigned long flags;
452
b5d3772c
MC		 453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
6892914f 457 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 461
bbadf503
MC		 462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 467
bbadf503
MC		 468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 472}
473
1da177e4
LT		 474static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475{
6892914f
MC		 476 unsigned long flags;
477
b5d3772c
MC		 478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
6892914f 484 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 488
bbadf503
MC		 489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 499}
500
501static void tg3_disable_ints(struct tg3 *tp)
502{
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 506}
507
508static inline void tg3_cond_int(struct tg3 *tp)
509{
38f3843e
MC		 510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 516}
517
518static void tg3_enable_ints(struct tg3 *tp)
519{
bbe832c0
MC		 520 tp->irq_sync = 0;
521 wmb();
522
1da177e4
LT		 523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
fcfa0a32
MC		 527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
1da177e4
LT		 530 tg3_cond_int(tp);
531}
532
04237ddd
MC		 533static inline unsigned int tg3_has_work(struct tg3 *tp)
534{
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551}
552
1da177e4 553/* tg3_restart_ints
04237ddd
MC		 554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
6aa20a22 556 * which reenables interrupts
1da177e4
LT		 557 */
558static void tg3_restart_ints(struct tg3 *tp)
559{
fac9b83e
DM		 560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
1da177e4
LT		 562 mmiowb();
563
fac9b83e
DM		 564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
04237ddd
MC		 570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 572}
573
574static inline void tg3_netif_stop(struct tg3 *tp)
575{
bbe832c0 576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579}
580
581static inline void tg3_netif_start(struct tg3 *tp)
582{
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
f47c11ee
DM		 589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
1da177e4
LT		 591}
592
593static void tg3_switch_clocks(struct tg3 *tp)
594{
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
a4e2b347 598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f
MC		 599 return;
600
1da177e4
LT		 601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
1da177e4 620 }
b401e9e2 621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 622}
623
624#define PHY_BUSY_LOOPS 5000
625
626static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627{
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 645
1da177e4
LT		 646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673}
674
675static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676{
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
b5d3772c
MC		 681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
1da177e4
LT		 685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 697
1da177e4
LT		 698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722}
723
724static void tg3_phy_set_wirespeed(struct tg3 *tp)
725{
726 u32 val;
727
728 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
729 return;
730
731 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
732 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
733 tg3_writephy(tp, MII_TG3_AUX_CTRL,
734 (val | (1 << 15) | (1 << 4)));
735}
736
737static int tg3_bmcr_reset(struct tg3 *tp)
738{
739 u32 phy_control;
740 int limit, err;
741
742 /* OK, reset it, and poll the BMCR_RESET bit until it
743 * clears or we time out.
744 */
745 phy_control = BMCR_RESET;
746 err = tg3_writephy(tp, MII_BMCR, phy_control);
747 if (err != 0)
748 return -EBUSY;
749
750 limit = 5000;
751 while (limit--) {
752 err = tg3_readphy(tp, MII_BMCR, &phy_control);
753 if (err != 0)
754 return -EBUSY;
755
756 if ((phy_control & BMCR_RESET) == 0) {
757 udelay(40);
758 break;
759 }
760 udelay(10);
761 }
762 if (limit <= 0)
763 return -EBUSY;
764
765 return 0;
766}
767
768static int tg3_wait_macro_done(struct tg3 *tp)
769{
770 int limit = 100;
771
772 while (limit--) {
773 u32 tmp32;
774
775 if (!tg3_readphy(tp, 0x16, &tmp32)) {
776 if ((tmp32 & 0x1000) == 0)
777 break;
778 }
779 }
780 if (limit <= 0)
781 return -EBUSY;
782
783 return 0;
784}
785
786static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
787{
788 static const u32 test_pat[4][6] = {
789 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
790 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
791 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
792 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
793 };
794 int chan;
795
796 for (chan = 0; chan < 4; chan++) {
797 int i;
798
799 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
800 (chan * 0x2000) | 0x0200);
801 tg3_writephy(tp, 0x16, 0x0002);
802
803 for (i = 0; i < 6; i++)
804 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
805 test_pat[chan][i]);
806
807 tg3_writephy(tp, 0x16, 0x0202);
808 if (tg3_wait_macro_done(tp)) {
809 *resetp = 1;
810 return -EBUSY;
811 }
812
813 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
814 (chan * 0x2000) | 0x0200);
815 tg3_writephy(tp, 0x16, 0x0082);
816 if (tg3_wait_macro_done(tp)) {
817 *resetp = 1;
818 return -EBUSY;
819 }
820
821 tg3_writephy(tp, 0x16, 0x0802);
822 if (tg3_wait_macro_done(tp)) {
823 *resetp = 1;
824 return -EBUSY;
825 }
826
827 for (i = 0; i < 6; i += 2) {
828 u32 low, high;
829
830 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
831 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
832 tg3_wait_macro_done(tp)) {
833 *resetp = 1;
834 return -EBUSY;
835 }
836 low &= 0x7fff;
837 high &= 0x000f;
838 if (low != test_pat[chan][i] ||
839 high != test_pat[chan][i+1]) {
840 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
841 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
843
844 return -EBUSY;
845 }
846 }
847 }
848
849 return 0;
850}
851
852static int tg3_phy_reset_chanpat(struct tg3 *tp)
853{
854 int chan;
855
856 for (chan = 0; chan < 4; chan++) {
857 int i;
858
859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
860 (chan * 0x2000) | 0x0200);
861 tg3_writephy(tp, 0x16, 0x0002);
862 for (i = 0; i < 6; i++)
863 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
864 tg3_writephy(tp, 0x16, 0x0202);
865 if (tg3_wait_macro_done(tp))
866 return -EBUSY;
867 }
868
869 return 0;
870}
871
872static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
873{
874 u32 reg32, phy9_orig;
875 int retries, do_phy_reset, err;
876
877 retries = 10;
878 do_phy_reset = 1;
879 do {
880 if (do_phy_reset) {
881 err = tg3_bmcr_reset(tp);
882 if (err)
883 return err;
884 do_phy_reset = 0;
885 }
886
887 /* Disable transmitter and interrupt. */
888 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
889 continue;
890
891 reg32 |= 0x3000;
892 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
893
894 /* Set full-duplex, 1000 mbps. */
895 tg3_writephy(tp, MII_BMCR,
896 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
897
898 /* Set to master mode. */
899 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
900 continue;
901
902 tg3_writephy(tp, MII_TG3_CTRL,
903 (MII_TG3_CTRL_AS_MASTER |
904 MII_TG3_CTRL_ENABLE_AS_MASTER));
905
906 /* Enable SM_DSP_CLOCK and 6dB. */
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
908
909 /* Block the PHY control access. */
910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
912
913 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
914 if (!err)
915 break;
916 } while (--retries);
917
918 err = tg3_phy_reset_chanpat(tp);
919 if (err)
920 return err;
921
922 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
926 tg3_writephy(tp, 0x16, 0x0000);
927
928 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
930 /* Set Extended packet length bit for jumbo frames */
931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
932 }
933 else {
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
935 }
936
937 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
938
939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940 reg32 &= ~0x3000;
941 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
942 } else if (!err)
943 err = -EBUSY;
944
945 return err;
946}
947
c8e1e82b
MC		 948static void tg3_link_report(struct tg3 *);
949
1da177e4
LT		 950/* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
952 */
953static int tg3_phy_reset(struct tg3 *tp)
954{
955 u32 phy_status;
956 int err;
957
60189ddf
MC		 958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
959 u32 val;
960
961 val = tr32(GRC_MISC_CFG);
962 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
963 udelay(40);
964 }
1da177e4
LT		 965 err = tg3_readphy(tp, MII_BMSR, &phy_status);
966 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
967 if (err != 0)
968 return -EBUSY;
969
c8e1e82b
MC		 970 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
971 netif_carrier_off(tp->dev);
972 tg3_link_report(tp);
973 }
974
1da177e4
LT		 975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
978 err = tg3_phy_reset_5703_4_5(tp);
979 if (err)
980 return err;
981 goto out;
982 }
983
984 err = tg3_bmcr_reset(tp);
985 if (err)
986 return err;
987
988out:
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
995 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
996 }
997 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
998 tg3_writephy(tp, 0x1c, 0x8d68);
999 tg3_writephy(tp, 0x1c, 0x8d68);
1000 }
1001 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010 }
c424cb24
MC		 1011 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1014 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016 tg3_writephy(tp, MII_TG3_TEST1,
1017 MII_TG3_TEST1_TRIM_EN | 0x4);
1018 } else
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1020 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021 }
1da177e4
LT		 1022 /* Set Extended packet length bit (bit 14) on all chips that */
1023 /* support jumbo frames */
1024 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025 /* Cannot do read-modify-write on 5401 */
1026 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1027 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1028 u32 phy_reg;
1029
1030 /* Set bit 14 with read-modify-write to preserve other bits */
1031 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034 }
1035
1036 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037 * jumbo frames transmission.
1038 */
0f893dc6 1039 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1040 u32 phy_reg;
1041
1042 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045 }
1046
715116a1
MC		 1047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048 u32 phy_reg;
1049
1050 /* adjust output voltage */
1051 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054 u32 phy_reg2;
1055
1056 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057 phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058 /* Enable auto-MDIX */
1059 if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061 tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062 }
1063 }
1064
1da177e4
LT		 1065 tg3_phy_set_wirespeed(tp);
1066 return 0;
1067}
1068
1069static void tg3_frob_aux_power(struct tg3 *tp)
1070{
1071 struct tg3 *tp_peer = tp;
1072
9d26e213 1073 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1074 return;
1075
8c2dc7e1
MC		 1076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078 struct net_device *dev_peer;
1079
1080 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1081 /* remove_one() may have been run on the peer. */
8c2dc7e1 1082 if (!dev_peer)
bc1c7567
MC		 1083 tp_peer = tp;
1084 else
1085 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1086 }
1087
1da177e4 1088 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1089 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095 (GRC_LCLCTRL_GPIO_OE0 |
1096 GRC_LCLCTRL_GPIO_OE1 |
1097 GRC_LCLCTRL_GPIO_OE2 |
1098 GRC_LCLCTRL_GPIO_OUTPUT0 |
1099 GRC_LCLCTRL_GPIO_OUTPUT1),
1100 100);
1da177e4
LT		 1101 } else {
1102 u32 no_gpio2;
dc56b7d4 1103 u32 grc_local_ctrl = 0;
1da177e4
LT		 1104
1105 if (tp_peer != tp &&
1106 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107 return;
1108
dc56b7d4
MC		 1109 /* Workaround to prevent overdrawing Amps. */
1110 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111 ASIC_REV_5714) {
1112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 grc_local_ctrl, 100);
dc56b7d4
MC		 1115 }
1116
1da177e4
LT		 1117 /* On 5753 and variants, GPIO2 cannot be used. */
1118 no_gpio2 = tp->nic_sram_data_cfg &
1119 NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
dc56b7d4 1121 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT1 |
1125 GRC_LCLCTRL_GPIO_OUTPUT2;
1126 if (no_gpio2) {
1127 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128 GRC_LCLCTRL_GPIO_OUTPUT2);
1129 }
b401e9e2
MC		 1130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131 grc_local_ctrl, 100);
1da177e4
LT		 1132
1133 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
b401e9e2
MC		 1135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136 grc_local_ctrl, 100);
1da177e4
LT		 1137
1138 if (!no_gpio2) {
1139 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 1140 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141 grc_local_ctrl, 100);
1da177e4
LT		 1142 }
1143 }
1144 } else {
1145 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147 if (tp_peer != tp &&
1148 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149 return;
1150
b401e9e2
MC		 1151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152 (GRC_LCLCTRL_GPIO_OE1 |
1153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 1154
b401e9e2
MC		 1155 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 1157
b401e9e2
MC		 1158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159 (GRC_LCLCTRL_GPIO_OE1 |
1160 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 1161 }
1162 }
1163}
1164
1165static int tg3_setup_phy(struct tg3 *, int);
1166
1167#define RESET_KIND_SHUTDOWN 0
1168#define RESET_KIND_INIT 1
1169#define RESET_KIND_SUSPEND 2
1170
1171static void tg3_write_sig_post_reset(struct tg3 *, int);
1172static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 1173static int tg3_nvram_lock(struct tg3 *);
1174static void tg3_nvram_unlock(struct tg3 *);
1da177e4 1175
15c3b696
MC		 1176static void tg3_power_down_phy(struct tg3 *tp)
1177{
5129724a
MC		 1178 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183 sg_dig_ctrl |=
1184 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187 }
3f7045c1 1188 return;
5129724a 1189 }
3f7045c1 1190
60189ddf
MC		 1191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192 u32 val;
1193
1194 tg3_bmcr_reset(tp);
1195 val = tr32(GRC_MISC_CFG);
1196 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197 udelay(40);
1198 return;
1199 } else {
715116a1
MC		 1200 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203 }
3f7045c1 1204
15c3b696
MC		 1205 /* The PHY should not be powered down on some chips because
1206 * of bugs.
1207 */
1208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212 return;
1213 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214}
1215
bc1c7567 1216static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 1217{
1218 u32 misc_host_ctrl;
1219 u16 power_control, power_caps;
1220 int pm = tp->pm_cap;
1221
1222 /* Make sure register accesses (indirect or otherwise)
1223 * will function correctly.
1224 */
1225 pci_write_config_dword(tp->pdev,
1226 TG3PCI_MISC_HOST_CTRL,
1227 tp->misc_host_ctrl);
1228
1229 pci_read_config_word(tp->pdev,
1230 pm + PCI_PM_CTRL,
1231 &power_control);
1232 power_control |= PCI_PM_CTRL_PME_STATUS;
1233 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234 switch (state) {
bc1c7567 1235 case PCI_D0:
1da177e4
LT		 1236 power_control |= 0;
1237 pci_write_config_word(tp->pdev,
1238 pm + PCI_PM_CTRL,
1239 power_control);
8c6bda1a
MC		 1240 udelay(100); /* Delay after power state change */
1241
9d26e213
MC		 1242 /* Switch out of Vaux if it is a NIC */
1243 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 1244 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 1245
1246 return 0;
1247
bc1c7567 1248 case PCI_D1:
1da177e4
LT		 1249 power_control |= 1;
1250 break;
1251
bc1c7567 1252 case PCI_D2:
1da177e4
LT		 1253 power_control |= 2;
1254 break;
1255
bc1c7567 1256 case PCI_D3hot:
1da177e4
LT		 1257 power_control |= 3;
1258 break;
1259
1260 default:
1261 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262 "requested.\n",
1263 tp->dev->name, state);
1264 return -EINVAL;
1265 };
1266
1267 power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270 tw32(TG3PCI_MISC_HOST_CTRL,
1271 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273 if (tp->link_config.phy_is_low_power == 0) {
1274 tp->link_config.phy_is_low_power = 1;
1275 tp->link_config.orig_speed = tp->link_config.speed;
1276 tp->link_config.orig_duplex = tp->link_config.duplex;
1277 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278 }
1279
747e8f8b 1280 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1281 tp->link_config.speed = SPEED_10;
1282 tp->link_config.duplex = DUPLEX_HALF;
1283 tp->link_config.autoneg = AUTONEG_ENABLE;
1284 tg3_setup_phy(tp, 0);
1285 }
1286
b5d3772c
MC		 1287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288 u32 val;
1289
1290 val = tr32(GRC_VCPU_EXT_CTRL);
1291 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 1293 int i;
1294 u32 val;
1295
1296 for (i = 0; i < 200; i++) {
1297 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299 break;
1300 msleep(1);
1301 }
1302 }
a85feb8c
GZ		 1303 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1304 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305 WOL_DRV_STATE_SHUTDOWN |
1306 WOL_DRV_WOL |
1307 WOL_SET_MAGIC_PKT);
6921d201 1308
1da177e4
LT		 1309 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1310
1311 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1312 u32 mac_mode;
1313
1314 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1315 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1316 udelay(40);
1317
3f7045c1
MC		 1318 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1319 mac_mode = MAC_MODE_PORT_MODE_GMII;
1320 else
1321 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4
LT		 1322
1323 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1324 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1325 mac_mode |= MAC_MODE_LINK_POLARITY;
1326 } else {
1327 mac_mode = MAC_MODE_PORT_MODE_TBI;
1328 }
1329
cbf46853 1330 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1331 tw32(MAC_LED_CTRL, tp->led_ctrl);
1332
1333 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1334 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1335 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1336
1337 tw32_f(MAC_MODE, mac_mode);
1338 udelay(100);
1339
1340 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1341 udelay(10);
1342 }
1343
1344 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1345 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1347 u32 base_val;
1348
1349 base_val = tp->pci_clock_ctrl;
1350 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1351 CLOCK_CTRL_TXCLK_DISABLE);
1352
b401e9e2
MC		 1353 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1354 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857
MC		 1355 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1356 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 1357 /* do nothing */
85e94ced 1358 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1359 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1360 u32 newbits1, newbits2;
1361
1362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1364 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1365 CLOCK_CTRL_TXCLK_DISABLE |
1366 CLOCK_CTRL_ALTCLK);
1367 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1368 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1369 newbits1 = CLOCK_CTRL_625_CORE;
1370 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1371 } else {
1372 newbits1 = CLOCK_CTRL_ALTCLK;
1373 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1374 }
1375
b401e9e2
MC		 1376 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1377 40);
1da177e4 1378
b401e9e2
MC		 1379 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1380 40);
1da177e4
LT		 1381
1382 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1383 u32 newbits3;
1384
1385 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1386 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1387 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1388 CLOCK_CTRL_TXCLK_DISABLE |
1389 CLOCK_CTRL_44MHZ_CORE);
1390 } else {
1391 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1392 }
1393
b401e9e2
MC		 1394 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1395 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 1396 }
1397 }
1398
6921d201 1399 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
3f7045c1
MC		 1400 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1401 tg3_power_down_phy(tp);
6921d201 1402
1da177e4
LT		 1403 tg3_frob_aux_power(tp);
1404
1405 /* Workaround for unstable PLL clock */
1406 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1407 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1408 u32 val = tr32(0x7d00);
1409
1410 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1411 tw32(0x7d00, val);
6921d201 1412 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 1413 int err;
1414
1415 err = tg3_nvram_lock(tp);
1da177e4 1416 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 1417 if (!err)
1418 tg3_nvram_unlock(tp);
6921d201 1419 }
1da177e4
LT		 1420 }
1421
bbadf503
MC		 1422 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1423
1da177e4
LT		 1424 /* Finally, set the new power state. */
1425 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1426 udelay(100); /* Delay after power state change */
1da177e4 1427
1da177e4
LT		 1428 return 0;
1429}
1430
1431static void tg3_link_report(struct tg3 *tp)
1432{
1433 if (!netif_carrier_ok(tp->dev)) {
9f88f29f
MC		 1434 if (netif_msg_link(tp))
1435 printk(KERN_INFO PFX "%s: Link is down.\n",
1436 tp->dev->name);
1437 } else if (netif_msg_link(tp)) {
1da177e4
LT		 1438 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1439 tp->dev->name,
1440 (tp->link_config.active_speed == SPEED_1000 ?
1441 1000 :
1442 (tp->link_config.active_speed == SPEED_100 ?
1443 100 : 10)),
1444 (tp->link_config.active_duplex == DUPLEX_FULL ?
1445 "full" : "half"));
1446
1447 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1448 "%s for RX.\n",
1449 tp->dev->name,
1450 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1451 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1452 }
1453}
1454
1455static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1456{
1457 u32 new_tg3_flags = 0;
1458 u32 old_rx_mode = tp->rx_mode;
1459 u32 old_tx_mode = tp->tx_mode;
1460
1461 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1462
1463 /* Convert 1000BaseX flow control bits to 1000BaseT
1464 * bits before resolving flow control.
1465 */
1466 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1467 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1468 ADVERTISE_PAUSE_ASYM);
1469 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1470
1471 if (local_adv & ADVERTISE_1000XPAUSE)
1472 local_adv |= ADVERTISE_PAUSE_CAP;
1473 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1474 local_adv |= ADVERTISE_PAUSE_ASYM;
1475 if (remote_adv & LPA_1000XPAUSE)
1476 remote_adv |= LPA_PAUSE_CAP;
1477 if (remote_adv & LPA_1000XPAUSE_ASYM)
1478 remote_adv |= LPA_PAUSE_ASYM;
1479 }
1480
1da177e4
LT		 1481 if (local_adv & ADVERTISE_PAUSE_CAP) {
1482 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1483 if (remote_adv & LPA_PAUSE_CAP)
1484 new_tg3_flags |=
1485 (TG3_FLAG_RX_PAUSE |
1486 TG3_FLAG_TX_PAUSE);
1487 else if (remote_adv & LPA_PAUSE_ASYM)
1488 new_tg3_flags |=
1489 (TG3_FLAG_RX_PAUSE);
1490 } else {
1491 if (remote_adv & LPA_PAUSE_CAP)
1492 new_tg3_flags |=
1493 (TG3_FLAG_RX_PAUSE |
1494 TG3_FLAG_TX_PAUSE);
1495 }
1496 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1497 if ((remote_adv & LPA_PAUSE_CAP) &&
1498 (remote_adv & LPA_PAUSE_ASYM))
1499 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1500 }
1501
1502 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1503 tp->tg3_flags |= new_tg3_flags;
1504 } else {
1505 new_tg3_flags = tp->tg3_flags;
1506 }
1507
1508 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1509 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1510 else
1511 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1512
1513 if (old_rx_mode != tp->rx_mode) {
1514 tw32_f(MAC_RX_MODE, tp->rx_mode);
1515 }
6aa20a22 1516
1da177e4
LT		 1517 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1518 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1519 else
1520 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1521
1522 if (old_tx_mode != tp->tx_mode) {
1523 tw32_f(MAC_TX_MODE, tp->tx_mode);
1524 }
1525}
1526
1527static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1528{
1529 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1530 case MII_TG3_AUX_STAT_10HALF:
1531 *speed = SPEED_10;
1532 *duplex = DUPLEX_HALF;
1533 break;
1534
1535 case MII_TG3_AUX_STAT_10FULL:
1536 *speed = SPEED_10;
1537 *duplex = DUPLEX_FULL;
1538 break;
1539
1540 case MII_TG3_AUX_STAT_100HALF:
1541 *speed = SPEED_100;
1542 *duplex = DUPLEX_HALF;
1543 break;
1544
1545 case MII_TG3_AUX_STAT_100FULL:
1546 *speed = SPEED_100;
1547 *duplex = DUPLEX_FULL;
1548 break;
1549
1550 case MII_TG3_AUX_STAT_1000HALF:
1551 *speed = SPEED_1000;
1552 *duplex = DUPLEX_HALF;
1553 break;
1554
1555 case MII_TG3_AUX_STAT_1000FULL:
1556 *speed = SPEED_1000;
1557 *duplex = DUPLEX_FULL;
1558 break;
1559
1560 default:
715116a1
MC		 1561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1562 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1563 SPEED_10;
1564 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1565 DUPLEX_HALF;
1566 break;
1567 }
1da177e4
LT		 1568 *speed = SPEED_INVALID;
1569 *duplex = DUPLEX_INVALID;
1570 break;
1571 };
1572}
1573
1574static void tg3_phy_copper_begin(struct tg3 *tp)
1575{
1576 u32 new_adv;
1577 int i;
1578
1579 if (tp->link_config.phy_is_low_power) {
1580 /* Entering low power mode. Disable gigabit and
1581 * 100baseT advertisements.
1582 */
1583 tg3_writephy(tp, MII_TG3_CTRL, 0);
1584
1585 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1586 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1587 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1588 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1589
1590 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1591 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 1592 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1593 tp->link_config.advertising &=
1594 ~(ADVERTISED_1000baseT_Half |
1595 ADVERTISED_1000baseT_Full);
1596
1597 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1598 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1599 new_adv |= ADVERTISE_10HALF;
1600 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1601 new_adv |= ADVERTISE_10FULL;
1602 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1603 new_adv |= ADVERTISE_100HALF;
1604 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1605 new_adv |= ADVERTISE_100FULL;
1606 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1607
1608 if (tp->link_config.advertising &
1609 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1610 new_adv = 0;
1611 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1612 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1613 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1614 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1615 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1616 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1617 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1618 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1619 MII_TG3_CTRL_ENABLE_AS_MASTER);
1620 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1621 } else {
1622 tg3_writephy(tp, MII_TG3_CTRL, 0);
1623 }
1624 } else {
1625 /* Asking for a specific link mode. */
1626 if (tp->link_config.speed == SPEED_1000) {
1627 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1628 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629
1630 if (tp->link_config.duplex == DUPLEX_FULL)
1631 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1632 else
1633 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1634 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1635 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1636 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1637 MII_TG3_CTRL_ENABLE_AS_MASTER);
1638 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1639 } else {
1640 tg3_writephy(tp, MII_TG3_CTRL, 0);
1641
1642 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1643 if (tp->link_config.speed == SPEED_100) {
1644 if (tp->link_config.duplex == DUPLEX_FULL)
1645 new_adv |= ADVERTISE_100FULL;
1646 else
1647 new_adv |= ADVERTISE_100HALF;
1648 } else {
1649 if (tp->link_config.duplex == DUPLEX_FULL)
1650 new_adv |= ADVERTISE_10FULL;
1651 else
1652 new_adv |= ADVERTISE_10HALF;
1653 }
1654 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1655 }
1656 }
1657
1658 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1659 tp->link_config.speed != SPEED_INVALID) {
1660 u32 bmcr, orig_bmcr;
1661
1662 tp->link_config.active_speed = tp->link_config.speed;
1663 tp->link_config.active_duplex = tp->link_config.duplex;
1664
1665 bmcr = 0;
1666 switch (tp->link_config.speed) {
1667 default:
1668 case SPEED_10:
1669 break;
1670
1671 case SPEED_100:
1672 bmcr |= BMCR_SPEED100;
1673 break;
1674
1675 case SPEED_1000:
1676 bmcr |= TG3_BMCR_SPEED1000;
1677 break;
1678 };
1679
1680 if (tp->link_config.duplex == DUPLEX_FULL)
1681 bmcr |= BMCR_FULLDPLX;
1682
1683 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1684 (bmcr != orig_bmcr)) {
1685 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1686 for (i = 0; i < 1500; i++) {
1687 u32 tmp;
1688
1689 udelay(10);
1690 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1691 tg3_readphy(tp, MII_BMSR, &tmp))
1692 continue;
1693 if (!(tmp & BMSR_LSTATUS)) {
1694 udelay(40);
1695 break;
1696 }
1697 }
1698 tg3_writephy(tp, MII_BMCR, bmcr);
1699 udelay(40);
1700 }
1701 } else {
1702 tg3_writephy(tp, MII_BMCR,
1703 BMCR_ANENABLE | BMCR_ANRESTART);
1704 }
1705}
1706
1707static int tg3_init_5401phy_dsp(struct tg3 *tp)
1708{
1709 int err;
1710
1711 /* Turn off tap power management. */
1712 /* Set Extended packet length bit */
1713 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1714
1715 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1716 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1717
1718 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1719 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1720
1721 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1722 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1723
1724 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1725 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1726
1727 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1728 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1729
1730 udelay(40);
1731
1732 return err;
1733}
1734
3600d918 1735static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 1736{
3600d918
MC		 1737 u32 adv_reg, all_mask = 0;
1738
1739 if (mask & ADVERTISED_10baseT_Half)
1740 all_mask |= ADVERTISE_10HALF;
1741 if (mask & ADVERTISED_10baseT_Full)
1742 all_mask |= ADVERTISE_10FULL;
1743 if (mask & ADVERTISED_100baseT_Half)
1744 all_mask |= ADVERTISE_100HALF;
1745 if (mask & ADVERTISED_100baseT_Full)
1746 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 1747
1748 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1749 return 0;
1750
1da177e4
LT		 1751 if ((adv_reg & all_mask) != all_mask)
1752 return 0;
1753 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1754 u32 tg3_ctrl;
1755
3600d918
MC		 1756 all_mask = 0;
1757 if (mask & ADVERTISED_1000baseT_Half)
1758 all_mask |= ADVERTISE_1000HALF;
1759 if (mask & ADVERTISED_1000baseT_Full)
1760 all_mask |= ADVERTISE_1000FULL;
1761
1da177e4
LT		 1762 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1763 return 0;
1764
1da177e4
LT		 1765 if ((tg3_ctrl & all_mask) != all_mask)
1766 return 0;
1767 }
1768 return 1;
1769}
1770
1771static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1772{
1773 int current_link_up;
1774 u32 bmsr, dummy;
1775 u16 current_speed;
1776 u8 current_duplex;
1777 int i, err;
1778
1779 tw32(MAC_EVENT, 0);
1780
1781 tw32_f(MAC_STATUS,
1782 (MAC_STATUS_SYNC_CHANGED |
1783 MAC_STATUS_CFG_CHANGED |
1784 MAC_STATUS_MI_COMPLETION |
1785 MAC_STATUS_LNKSTATE_CHANGED));
1786 udelay(40);
1787
1788 tp->mi_mode = MAC_MI_MODE_BASE;
1789 tw32_f(MAC_MI_MODE, tp->mi_mode);
1790 udelay(80);
1791
1792 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1793
1794 /* Some third-party PHYs need to be reset on link going
1795 * down.
1796 */
1797 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1800 netif_carrier_ok(tp->dev)) {
1801 tg3_readphy(tp, MII_BMSR, &bmsr);
1802 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1803 !(bmsr & BMSR_LSTATUS))
1804 force_reset = 1;
1805 }
1806 if (force_reset)
1807 tg3_phy_reset(tp);
1808
1809 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1810 tg3_readphy(tp, MII_BMSR, &bmsr);
1811 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1812 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1813 bmsr = 0;
1814
1815 if (!(bmsr & BMSR_LSTATUS)) {
1816 err = tg3_init_5401phy_dsp(tp);
1817 if (err)
1818 return err;
1819
1820 tg3_readphy(tp, MII_BMSR, &bmsr);
1821 for (i = 0; i < 1000; i++) {
1822 udelay(10);
1823 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1824 (bmsr & BMSR_LSTATUS)) {
1825 udelay(40);
1826 break;
1827 }
1828 }
1829
1830 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1831 !(bmsr & BMSR_LSTATUS) &&
1832 tp->link_config.active_speed == SPEED_1000) {
1833 err = tg3_phy_reset(tp);
1834 if (!err)
1835 err = tg3_init_5401phy_dsp(tp);
1836 if (err)
1837 return err;
1838 }
1839 }
1840 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1841 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1842 /* 5701 {A0,B0} CRC bug workaround */
1843 tg3_writephy(tp, 0x15, 0x0a75);
1844 tg3_writephy(tp, 0x1c, 0x8c68);
1845 tg3_writephy(tp, 0x1c, 0x8d68);
1846 tg3_writephy(tp, 0x1c, 0x8c68);
1847 }
1848
1849 /* Clear pending interrupts... */
1850 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1852
1853 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 1855 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 1856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1857
1858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1863 else
1864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1865 }
1866
1867 current_link_up = 0;
1868 current_speed = SPEED_INVALID;
1869 current_duplex = DUPLEX_INVALID;
1870
1871 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1872 u32 val;
1873
1874 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1875 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1876 if (!(val & (1 << 10))) {
1877 val |= (1 << 10);
1878 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1879 goto relink;
1880 }
1881 }
1882
1883 bmsr = 0;
1884 for (i = 0; i < 100; i++) {
1885 tg3_readphy(tp, MII_BMSR, &bmsr);
1886 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1887 (bmsr & BMSR_LSTATUS))
1888 break;
1889 udelay(40);
1890 }
1891
1892 if (bmsr & BMSR_LSTATUS) {
1893 u32 aux_stat, bmcr;
1894
1895 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1896 for (i = 0; i < 2000; i++) {
1897 udelay(10);
1898 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1899 aux_stat)
1900 break;
1901 }
1902
1903 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1904 &current_speed,
1905 &current_duplex);
1906
1907 bmcr = 0;
1908 for (i = 0; i < 200; i++) {
1909 tg3_readphy(tp, MII_BMCR, &bmcr);
1910 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1911 continue;
1912 if (bmcr && bmcr != 0x7fff)
1913 break;
1914 udelay(10);
1915 }
1916
1917 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1918 if (bmcr & BMCR_ANENABLE) {
1919 current_link_up = 1;
1920
1921 /* Force autoneg restart if we are exiting
1922 * low power mode.
1923 */
3600d918
MC		 1924 if (!tg3_copper_is_advertising_all(tp,
1925 tp->link_config.advertising))
1da177e4
LT		 1926 current_link_up = 0;
1927 } else {
1928 current_link_up = 0;
1929 }
1930 } else {
1931 if (!(bmcr & BMCR_ANENABLE) &&
1932 tp->link_config.speed == current_speed &&
1933 tp->link_config.duplex == current_duplex) {
1934 current_link_up = 1;
1935 } else {
1936 current_link_up = 0;
1937 }
1938 }
1939
1940 tp->link_config.active_speed = current_speed;
1941 tp->link_config.active_duplex = current_duplex;
1942 }
1943
1944 if (current_link_up == 1 &&
1945 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1946 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1947 u32 local_adv, remote_adv;
1948
1949 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1950 local_adv = 0;
1951 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1952
1953 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1954 remote_adv = 0;
1955
1956 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1957
1958 /* If we are not advertising full pause capability,
1959 * something is wrong. Bring the link down and reconfigure.
1960 */
1961 if (local_adv != ADVERTISE_PAUSE_CAP) {
1962 current_link_up = 0;
1963 } else {
1964 tg3_setup_flow_control(tp, local_adv, remote_adv);
1965 }
1966 }
1967relink:
6921d201 1968 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 1969 u32 tmp;
1970
1971 tg3_phy_copper_begin(tp);
1972
1973 tg3_readphy(tp, MII_BMSR, &tmp);
1974 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1975 (tmp & BMSR_LSTATUS))
1976 current_link_up = 1;
1977 }
1978
1979 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1980 if (current_link_up == 1) {
1981 if (tp->link_config.active_speed == SPEED_100 ||
1982 tp->link_config.active_speed == SPEED_10)
1983 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1984 else
1985 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986 } else
1987 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1988
1989 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1990 if (tp->link_config.active_duplex == DUPLEX_HALF)
1991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1992
1993 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1995 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1996 (current_link_up == 1 &&
1997 tp->link_config.active_speed == SPEED_10))
1998 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1999 } else {
2000 if (current_link_up == 1)
2001 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2002 }
2003
2004 /* ??? Without this setting Netgear GA302T PHY does not
2005 * ??? send/receive packets...
2006 */
2007 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2008 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2009 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2010 tw32_f(MAC_MI_MODE, tp->mi_mode);
2011 udelay(80);
2012 }
2013
2014 tw32_f(MAC_MODE, tp->mac_mode);
2015 udelay(40);
2016
2017 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2018 /* Polled via timer. */
2019 tw32_f(MAC_EVENT, 0);
2020 } else {
2021 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2022 }
2023 udelay(40);
2024
2025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2026 current_link_up == 1 &&
2027 tp->link_config.active_speed == SPEED_1000 &&
2028 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2029 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2030 udelay(120);
2031 tw32_f(MAC_STATUS,
2032 (MAC_STATUS_SYNC_CHANGED |
2033 MAC_STATUS_CFG_CHANGED));
2034 udelay(40);
2035 tg3_write_mem(tp,
2036 NIC_SRAM_FIRMWARE_MBOX,
2037 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2038 }
2039
2040 if (current_link_up != netif_carrier_ok(tp->dev)) {
2041 if (current_link_up)
2042 netif_carrier_on(tp->dev);
2043 else
2044 netif_carrier_off(tp->dev);
2045 tg3_link_report(tp);
2046 }
2047
2048 return 0;
2049}
2050
2051struct tg3_fiber_aneginfo {
2052 int state;
2053#define ANEG_STATE_UNKNOWN 0
2054#define ANEG_STATE_AN_ENABLE 1
2055#define ANEG_STATE_RESTART_INIT 2
2056#define ANEG_STATE_RESTART 3
2057#define ANEG_STATE_DISABLE_LINK_OK 4
2058#define ANEG_STATE_ABILITY_DETECT_INIT 5
2059#define ANEG_STATE_ABILITY_DETECT 6
2060#define ANEG_STATE_ACK_DETECT_INIT 7
2061#define ANEG_STATE_ACK_DETECT 8
2062#define ANEG_STATE_COMPLETE_ACK_INIT 9
2063#define ANEG_STATE_COMPLETE_ACK 10
2064#define ANEG_STATE_IDLE_DETECT_INIT 11
2065#define ANEG_STATE_IDLE_DETECT 12
2066#define ANEG_STATE_LINK_OK 13
2067#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2068#define ANEG_STATE_NEXT_PAGE_WAIT 15
2069
2070 u32 flags;
2071#define MR_AN_ENABLE 0x00000001
2072#define MR_RESTART_AN 0x00000002
2073#define MR_AN_COMPLETE 0x00000004
2074#define MR_PAGE_RX 0x00000008
2075#define MR_NP_LOADED 0x00000010
2076#define MR_TOGGLE_TX 0x00000020
2077#define MR_LP_ADV_FULL_DUPLEX 0x00000040
2078#define MR_LP_ADV_HALF_DUPLEX 0x00000080
2079#define MR_LP_ADV_SYM_PAUSE 0x00000100
2080#define MR_LP_ADV_ASYM_PAUSE 0x00000200
2081#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2082#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2083#define MR_LP_ADV_NEXT_PAGE 0x00001000
2084#define MR_TOGGLE_RX 0x00002000
2085#define MR_NP_RX 0x00004000
2086
2087#define MR_LINK_OK 0x80000000
2088
2089 unsigned long link_time, cur_time;
2090
2091 u32 ability_match_cfg;
2092 int ability_match_count;
2093
2094 char ability_match, idle_match, ack_match;
2095
2096 u32 txconfig, rxconfig;
2097#define ANEG_CFG_NP 0x00000080
2098#define ANEG_CFG_ACK 0x00000040
2099#define ANEG_CFG_RF2 0x00000020
2100#define ANEG_CFG_RF1 0x00000010
2101#define ANEG_CFG_PS2 0x00000001
2102#define ANEG_CFG_PS1 0x00008000
2103#define ANEG_CFG_HD 0x00004000
2104#define ANEG_CFG_FD 0x00002000
2105#define ANEG_CFG_INVAL 0x00001f06
2106
2107};
2108#define ANEG_OK 0
2109#define ANEG_DONE 1
2110#define ANEG_TIMER_ENAB 2
2111#define ANEG_FAILED -1
2112
2113#define ANEG_STATE_SETTLE_TIME 10000
2114
2115static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2116 struct tg3_fiber_aneginfo *ap)
2117{
2118 unsigned long delta;
2119 u32 rx_cfg_reg;
2120 int ret;
2121
2122 if (ap->state == ANEG_STATE_UNKNOWN) {
2123 ap->rxconfig = 0;
2124 ap->link_time = 0;
2125 ap->cur_time = 0;
2126 ap->ability_match_cfg = 0;
2127 ap->ability_match_count = 0;
2128 ap->ability_match = 0;
2129 ap->idle_match = 0;
2130 ap->ack_match = 0;
2131 }
2132 ap->cur_time++;
2133
2134 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2135 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2136
2137 if (rx_cfg_reg != ap->ability_match_cfg) {
2138 ap->ability_match_cfg = rx_cfg_reg;
2139 ap->ability_match = 0;
2140 ap->ability_match_count = 0;
2141 } else {
2142 if (++ap->ability_match_count > 1) {
2143 ap->ability_match = 1;
2144 ap->ability_match_cfg = rx_cfg_reg;
2145 }
2146 }
2147 if (rx_cfg_reg & ANEG_CFG_ACK)
2148 ap->ack_match = 1;
2149 else
2150 ap->ack_match = 0;
2151
2152 ap->idle_match = 0;
2153 } else {
2154 ap->idle_match = 1;
2155 ap->ability_match_cfg = 0;
2156 ap->ability_match_count = 0;
2157 ap->ability_match = 0;
2158 ap->ack_match = 0;
2159
2160 rx_cfg_reg = 0;
2161 }
2162
2163 ap->rxconfig = rx_cfg_reg;
2164 ret = ANEG_OK;
2165
2166 switch(ap->state) {
2167 case ANEG_STATE_UNKNOWN:
2168 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2169 ap->state = ANEG_STATE_AN_ENABLE;
2170
2171 /* fallthru */
2172 case ANEG_STATE_AN_ENABLE:
2173 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2174 if (ap->flags & MR_AN_ENABLE) {
2175 ap->link_time = 0;
2176 ap->cur_time = 0;
2177 ap->ability_match_cfg = 0;
2178 ap->ability_match_count = 0;
2179 ap->ability_match = 0;
2180 ap->idle_match = 0;
2181 ap->ack_match = 0;
2182
2183 ap->state = ANEG_STATE_RESTART_INIT;
2184 } else {
2185 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2186 }
2187 break;
2188
2189 case ANEG_STATE_RESTART_INIT:
2190 ap->link_time = ap->cur_time;
2191 ap->flags &= ~(MR_NP_LOADED);
2192 ap->txconfig = 0;
2193 tw32(MAC_TX_AUTO_NEG, 0);
2194 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2195 tw32_f(MAC_MODE, tp->mac_mode);
2196 udelay(40);
2197
2198 ret = ANEG_TIMER_ENAB;
2199 ap->state = ANEG_STATE_RESTART;
2200
2201 /* fallthru */
2202 case ANEG_STATE_RESTART:
2203 delta = ap->cur_time - ap->link_time;
2204 if (delta > ANEG_STATE_SETTLE_TIME) {
2205 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2206 } else {
2207 ret = ANEG_TIMER_ENAB;
2208 }
2209 break;
2210
2211 case ANEG_STATE_DISABLE_LINK_OK:
2212 ret = ANEG_DONE;
2213 break;
2214
2215 case ANEG_STATE_ABILITY_DETECT_INIT:
2216 ap->flags &= ~(MR_TOGGLE_TX);
2217 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2218 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2219 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2220 tw32_f(MAC_MODE, tp->mac_mode);
2221 udelay(40);
2222
2223 ap->state = ANEG_STATE_ABILITY_DETECT;
2224 break;
2225
2226 case ANEG_STATE_ABILITY_DETECT:
2227 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2228 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2229 }
2230 break;
2231
2232 case ANEG_STATE_ACK_DETECT_INIT:
2233 ap->txconfig |= ANEG_CFG_ACK;
2234 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2235 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2236 tw32_f(MAC_MODE, tp->mac_mode);
2237 udelay(40);
2238
2239 ap->state = ANEG_STATE_ACK_DETECT;
2240
2241 /* fallthru */
2242 case ANEG_STATE_ACK_DETECT:
2243 if (ap->ack_match != 0) {
2244 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2245 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2246 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2247 } else {
2248 ap->state = ANEG_STATE_AN_ENABLE;
2249 }
2250 } else if (ap->ability_match != 0 &&
2251 ap->rxconfig == 0) {
2252 ap->state = ANEG_STATE_AN_ENABLE;
2253 }
2254 break;
2255
2256 case ANEG_STATE_COMPLETE_ACK_INIT:
2257 if (ap->rxconfig & ANEG_CFG_INVAL) {
2258 ret = ANEG_FAILED;
2259 break;
2260 }
2261 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2262 MR_LP_ADV_HALF_DUPLEX |
2263 MR_LP_ADV_SYM_PAUSE |
2264 MR_LP_ADV_ASYM_PAUSE |
2265 MR_LP_ADV_REMOTE_FAULT1 |
2266 MR_LP_ADV_REMOTE_FAULT2 |
2267 MR_LP_ADV_NEXT_PAGE |
2268 MR_TOGGLE_RX |
2269 MR_NP_RX);
2270 if (ap->rxconfig & ANEG_CFG_FD)
2271 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2272 if (ap->rxconfig & ANEG_CFG_HD)
2273 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2274 if (ap->rxconfig & ANEG_CFG_PS1)
2275 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2276 if (ap->rxconfig & ANEG_CFG_PS2)
2277 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2278 if (ap->rxconfig & ANEG_CFG_RF1)
2279 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2280 if (ap->rxconfig & ANEG_CFG_RF2)
2281 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2282 if (ap->rxconfig & ANEG_CFG_NP)
2283 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2284
2285 ap->link_time = ap->cur_time;
2286
2287 ap->flags ^= (MR_TOGGLE_TX);
2288 if (ap->rxconfig & 0x0008)
2289 ap->flags |= MR_TOGGLE_RX;
2290 if (ap->rxconfig & ANEG_CFG_NP)
2291 ap->flags |= MR_NP_RX;
2292 ap->flags |= MR_PAGE_RX;
2293
2294 ap->state = ANEG_STATE_COMPLETE_ACK;
2295 ret = ANEG_TIMER_ENAB;
2296 break;
2297
2298 case ANEG_STATE_COMPLETE_ACK:
2299 if (ap->ability_match != 0 &&
2300 ap->rxconfig == 0) {
2301 ap->state = ANEG_STATE_AN_ENABLE;
2302 break;
2303 }
2304 delta = ap->cur_time - ap->link_time;
2305 if (delta > ANEG_STATE_SETTLE_TIME) {
2306 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2307 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2308 } else {
2309 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2310 !(ap->flags & MR_NP_RX)) {
2311 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2312 } else {
2313 ret = ANEG_FAILED;
2314 }
2315 }
2316 }
2317 break;
2318
2319 case ANEG_STATE_IDLE_DETECT_INIT:
2320 ap->link_time = ap->cur_time;
2321 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2322 tw32_f(MAC_MODE, tp->mac_mode);
2323 udelay(40);
2324
2325 ap->state = ANEG_STATE_IDLE_DETECT;
2326 ret = ANEG_TIMER_ENAB;
2327 break;
2328
2329 case ANEG_STATE_IDLE_DETECT:
2330 if (ap->ability_match != 0 &&
2331 ap->rxconfig == 0) {
2332 ap->state = ANEG_STATE_AN_ENABLE;
2333 break;
2334 }
2335 delta = ap->cur_time - ap->link_time;
2336 if (delta > ANEG_STATE_SETTLE_TIME) {
2337 /* XXX another gem from the Broadcom driver :( */
2338 ap->state = ANEG_STATE_LINK_OK;
2339 }
2340 break;
2341
2342 case ANEG_STATE_LINK_OK:
2343 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2344 ret = ANEG_DONE;
2345 break;
2346
2347 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2348 /* ??? unimplemented */
2349 break;
2350
2351 case ANEG_STATE_NEXT_PAGE_WAIT:
2352 /* ??? unimplemented */
2353 break;
2354
2355 default:
2356 ret = ANEG_FAILED;
2357 break;
2358 };
2359
2360 return ret;
2361}
2362
2363static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2364{
2365 int res = 0;
2366 struct tg3_fiber_aneginfo aninfo;
2367 int status = ANEG_FAILED;
2368 unsigned int tick;
2369 u32 tmp;
2370
2371 tw32_f(MAC_TX_AUTO_NEG, 0);
2372
2373 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2374 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2375 udelay(40);
2376
2377 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2378 udelay(40);
2379
2380 memset(&aninfo, 0, sizeof(aninfo));
2381 aninfo.flags |= MR_AN_ENABLE;
2382 aninfo.state = ANEG_STATE_UNKNOWN;
2383 aninfo.cur_time = 0;
2384 tick = 0;
2385 while (++tick < 195000) {
2386 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2387 if (status == ANEG_DONE || status == ANEG_FAILED)
2388 break;
2389
2390 udelay(1);
2391 }
2392
2393 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2394 tw32_f(MAC_MODE, tp->mac_mode);
2395 udelay(40);
2396
2397 *flags = aninfo.flags;
2398
2399 if (status == ANEG_DONE &&
2400 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2401 MR_LP_ADV_FULL_DUPLEX)))
2402 res = 1;
2403
2404 return res;
2405}
2406
2407static void tg3_init_bcm8002(struct tg3 *tp)
2408{
2409 u32 mac_status = tr32(MAC_STATUS);
2410 int i;
2411
2412 /* Reset when initting first time or we have a link. */
2413 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2414 !(mac_status & MAC_STATUS_PCS_SYNCED))
2415 return;
2416
2417 /* Set PLL lock range. */
2418 tg3_writephy(tp, 0x16, 0x8007);
2419
2420 /* SW reset */
2421 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2422
2423 /* Wait for reset to complete. */
2424 /* XXX schedule_timeout() ... */
2425 for (i = 0; i < 500; i++)
2426 udelay(10);
2427
2428 /* Config mode; select PMA/Ch 1 regs. */
2429 tg3_writephy(tp, 0x10, 0x8411);
2430
2431 /* Enable auto-lock and comdet, select txclk for tx. */
2432 tg3_writephy(tp, 0x11, 0x0a10);
2433
2434 tg3_writephy(tp, 0x18, 0x00a0);
2435 tg3_writephy(tp, 0x16, 0x41ff);
2436
2437 /* Assert and deassert POR. */
2438 tg3_writephy(tp, 0x13, 0x0400);
2439 udelay(40);
2440 tg3_writephy(tp, 0x13, 0x0000);
2441
2442 tg3_writephy(tp, 0x11, 0x0a50);
2443 udelay(40);
2444 tg3_writephy(tp, 0x11, 0x0a10);
2445
2446 /* Wait for signal to stabilize */
2447 /* XXX schedule_timeout() ... */
2448 for (i = 0; i < 15000; i++)
2449 udelay(10);
2450
2451 /* Deselect the channel register so we can read the PHYID
2452 * later.
2453 */
2454 tg3_writephy(tp, 0x10, 0x8011);
2455}
2456
2457static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2458{
2459 u32 sg_dig_ctrl, sg_dig_status;
2460 u32 serdes_cfg, expected_sg_dig_ctrl;
2461 int workaround, port_a;
2462 int current_link_up;
2463
2464 serdes_cfg = 0;
2465 expected_sg_dig_ctrl = 0;
2466 workaround = 0;
2467 port_a = 1;
2468 current_link_up = 0;
2469
2470 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2471 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2472 workaround = 1;
2473 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2474 port_a = 0;
2475
2476 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2477 /* preserve bits 20-23 for voltage regulator */
2478 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2479 }
2480
2481 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2482
2483 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2484 if (sg_dig_ctrl & (1 << 31)) {
2485 if (workaround) {
2486 u32 val = serdes_cfg;
2487
2488 if (port_a)
2489 val |= 0xc010000;
2490 else
2491 val |= 0x4010000;
2492 tw32_f(MAC_SERDES_CFG, val);
2493 }
2494 tw32_f(SG_DIG_CTRL, 0x01388400);
2495 }
2496 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2497 tg3_setup_flow_control(tp, 0, 0);
2498 current_link_up = 1;
2499 }
2500 goto out;
2501 }
2502
2503 /* Want auto-negotiation. */
2504 expected_sg_dig_ctrl = 0x81388400;
2505
2506 /* Pause capability */
2507 expected_sg_dig_ctrl |= (1 << 11);
2508
2509 /* Asymettric pause */
2510 expected_sg_dig_ctrl |= (1 << 12);
2511
2512 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 2513 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2514 tp->serdes_counter &&
2515 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2516 MAC_STATUS_RCVD_CFG)) ==
2517 MAC_STATUS_PCS_SYNCED)) {
2518 tp->serdes_counter--;
2519 current_link_up = 1;
2520 goto out;
2521 }
2522restart_autoneg:
1da177e4
LT		 2523 if (workaround)
2524 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2525 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2526 udelay(5);
2527 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2528
3d3ebe74
MC		 2529 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2530 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2531 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2532 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 2533 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 2534 mac_status = tr32(MAC_STATUS);
2535
2536 if ((sg_dig_status & (1 << 1)) &&
2537 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2538 u32 local_adv, remote_adv;
2539
2540 local_adv = ADVERTISE_PAUSE_CAP;
2541 remote_adv = 0;
2542 if (sg_dig_status & (1 << 19))
2543 remote_adv |= LPA_PAUSE_CAP;
2544 if (sg_dig_status & (1 << 20))
2545 remote_adv |= LPA_PAUSE_ASYM;
2546
2547 tg3_setup_flow_control(tp, local_adv, remote_adv);
2548 current_link_up = 1;
3d3ebe74
MC		 2549 tp->serdes_counter = 0;
2550 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4 2551 } else if (!(sg_dig_status & (1 << 1))) {
3d3ebe74
MC		 2552 if (tp->serdes_counter)
2553 tp->serdes_counter--;
1da177e4
LT		 2554 else {
2555 if (workaround) {
2556 u32 val = serdes_cfg;
2557
2558 if (port_a)
2559 val |= 0xc010000;
2560 else
2561 val |= 0x4010000;
2562
2563 tw32_f(MAC_SERDES_CFG, val);
2564 }
2565
2566 tw32_f(SG_DIG_CTRL, 0x01388400);
2567 udelay(40);
2568
2569 /* Link parallel detection - link is up */
2570 /* only if we have PCS_SYNC and not */
2571 /* receiving config code words */
2572 mac_status = tr32(MAC_STATUS);
2573 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2574 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2575 tg3_setup_flow_control(tp, 0, 0);
2576 current_link_up = 1;
3d3ebe74
MC		 2577 tp->tg3_flags2 |=
2578 TG3_FLG2_PARALLEL_DETECT;
2579 tp->serdes_counter =
2580 SERDES_PARALLEL_DET_TIMEOUT;
2581 } else
2582 goto restart_autoneg;
1da177e4
LT		 2583 }
2584 }
3d3ebe74
MC		 2585 } else {
2586 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2587 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 2588 }
2589
2590out:
2591 return current_link_up;
2592}
2593
2594static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2595{
2596 int current_link_up = 0;
2597
5cf64b8a 2598 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 2599 goto out;
1da177e4
LT		 2600
2601 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602 u32 flags;
2603 int i;
6aa20a22 2604
1da177e4
LT		 2605 if (fiber_autoneg(tp, &flags)) {
2606 u32 local_adv, remote_adv;
2607
2608 local_adv = ADVERTISE_PAUSE_CAP;
2609 remote_adv = 0;
2610 if (flags & MR_LP_ADV_SYM_PAUSE)
2611 remote_adv |= LPA_PAUSE_CAP;
2612 if (flags & MR_LP_ADV_ASYM_PAUSE)
2613 remote_adv |= LPA_PAUSE_ASYM;
2614
2615 tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
1da177e4
LT		 2617 current_link_up = 1;
2618 }
2619 for (i = 0; i < 30; i++) {
2620 udelay(20);
2621 tw32_f(MAC_STATUS,
2622 (MAC_STATUS_SYNC_CHANGED |
2623 MAC_STATUS_CFG_CHANGED));
2624 udelay(40);
2625 if ((tr32(MAC_STATUS) &
2626 (MAC_STATUS_SYNC_CHANGED |
2627 MAC_STATUS_CFG_CHANGED)) == 0)
2628 break;
2629 }
2630
2631 mac_status = tr32(MAC_STATUS);
2632 if (current_link_up == 0 &&
2633 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2634 !(mac_status & MAC_STATUS_RCVD_CFG))
2635 current_link_up = 1;
2636 } else {
2637 /* Forcing 1000FD link up. */
2638 current_link_up = 1;
1da177e4
LT		 2639
2640 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2641 udelay(40);
2642 }
2643
2644out:
2645 return current_link_up;
2646}
2647
2648static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2649{
2650 u32 orig_pause_cfg;
2651 u16 orig_active_speed;
2652 u8 orig_active_duplex;
2653 u32 mac_status;
2654 int current_link_up;
2655 int i;
2656
2657 orig_pause_cfg =
2658 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2659 TG3_FLAG_TX_PAUSE));
2660 orig_active_speed = tp->link_config.active_speed;
2661 orig_active_duplex = tp->link_config.active_duplex;
2662
2663 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2664 netif_carrier_ok(tp->dev) &&
2665 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2666 mac_status = tr32(MAC_STATUS);
2667 mac_status &= (MAC_STATUS_PCS_SYNCED |
2668 MAC_STATUS_SIGNAL_DET |
2669 MAC_STATUS_CFG_CHANGED |
2670 MAC_STATUS_RCVD_CFG);
2671 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2672 MAC_STATUS_SIGNAL_DET)) {
2673 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2674 MAC_STATUS_CFG_CHANGED));
2675 return 0;
2676 }
2677 }
2678
2679 tw32_f(MAC_TX_AUTO_NEG, 0);
2680
2681 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2682 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2683 tw32_f(MAC_MODE, tp->mac_mode);
2684 udelay(40);
2685
2686 if (tp->phy_id == PHY_ID_BCM8002)
2687 tg3_init_bcm8002(tp);
2688
2689 /* Enable link change event even when serdes polling. */
2690 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2691 udelay(40);
2692
2693 current_link_up = 0;
2694 mac_status = tr32(MAC_STATUS);
2695
2696 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2697 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2698 else
2699 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2700
2701 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2702 tw32_f(MAC_MODE, tp->mac_mode);
2703 udelay(40);
2704
2705 tp->hw_status->status =
2706 (SD_STATUS_UPDATED |
2707 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2708
2709 for (i = 0; i < 100; i++) {
2710 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2711 MAC_STATUS_CFG_CHANGED));
2712 udelay(5);
2713 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 2714 MAC_STATUS_CFG_CHANGED |
2715 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 2716 break;
2717 }
2718
2719 mac_status = tr32(MAC_STATUS);
2720 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2721 current_link_up = 0;
3d3ebe74
MC		 2722 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2723 tp->serdes_counter == 0) {
1da177e4
LT		 2724 tw32_f(MAC_MODE, (tp->mac_mode |
2725 MAC_MODE_SEND_CONFIGS));
2726 udelay(1);
2727 tw32_f(MAC_MODE, tp->mac_mode);
2728 }
2729 }
2730
2731 if (current_link_up == 1) {
2732 tp->link_config.active_speed = SPEED_1000;
2733 tp->link_config.active_duplex = DUPLEX_FULL;
2734 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2735 LED_CTRL_LNKLED_OVERRIDE |
2736 LED_CTRL_1000MBPS_ON));
2737 } else {
2738 tp->link_config.active_speed = SPEED_INVALID;
2739 tp->link_config.active_duplex = DUPLEX_INVALID;
2740 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2741 LED_CTRL_LNKLED_OVERRIDE |
2742 LED_CTRL_TRAFFIC_OVERRIDE));
2743 }
2744
2745 if (current_link_up != netif_carrier_ok(tp->dev)) {
2746 if (current_link_up)
2747 netif_carrier_on(tp->dev);
2748 else
2749 netif_carrier_off(tp->dev);
2750 tg3_link_report(tp);
2751 } else {
2752 u32 now_pause_cfg =
2753 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2754 TG3_FLAG_TX_PAUSE);
2755 if (orig_pause_cfg != now_pause_cfg ||
2756 orig_active_speed != tp->link_config.active_speed ||
2757 orig_active_duplex != tp->link_config.active_duplex)
2758 tg3_link_report(tp);
2759 }
2760
2761 return 0;
2762}
2763
747e8f8b
MC		 2764static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2765{
2766 int current_link_up, err = 0;
2767 u32 bmsr, bmcr;
2768 u16 current_speed;
2769 u8 current_duplex;
2770
2771 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2772 tw32_f(MAC_MODE, tp->mac_mode);
2773 udelay(40);
2774
2775 tw32(MAC_EVENT, 0);
2776
2777 tw32_f(MAC_STATUS,
2778 (MAC_STATUS_SYNC_CHANGED |
2779 MAC_STATUS_CFG_CHANGED |
2780 MAC_STATUS_MI_COMPLETION |
2781 MAC_STATUS_LNKSTATE_CHANGED));
2782 udelay(40);
2783
2784 if (force_reset)
2785 tg3_phy_reset(tp);
2786
2787 current_link_up = 0;
2788 current_speed = SPEED_INVALID;
2789 current_duplex = DUPLEX_INVALID;
2790
2791 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2792 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2794 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2795 bmsr |= BMSR_LSTATUS;
2796 else
2797 bmsr &= ~BMSR_LSTATUS;
2798 }
747e8f8b
MC		 2799
2800 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2801
2802 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2803 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2804 /* do nothing, just check for link up at the end */
2805 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2806 u32 adv, new_adv;
2807
2808 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2809 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2810 ADVERTISE_1000XPAUSE |
2811 ADVERTISE_1000XPSE_ASYM |
2812 ADVERTISE_SLCT);
2813
2814 /* Always advertise symmetric PAUSE just like copper */
2815 new_adv |= ADVERTISE_1000XPAUSE;
2816
2817 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2818 new_adv |= ADVERTISE_1000XHALF;
2819 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2820 new_adv |= ADVERTISE_1000XFULL;
2821
2822 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2823 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2824 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2825 tg3_writephy(tp, MII_BMCR, bmcr);
2826
2827 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 2828 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 2829 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2830
2831 return err;
2832 }
2833 } else {
2834 u32 new_bmcr;
2835
2836 bmcr &= ~BMCR_SPEED1000;
2837 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2838
2839 if (tp->link_config.duplex == DUPLEX_FULL)
2840 new_bmcr |= BMCR_FULLDPLX;
2841
2842 if (new_bmcr != bmcr) {
2843 /* BMCR_SPEED1000 is a reserved bit that needs
2844 * to be set on write.
2845 */
2846 new_bmcr |= BMCR_SPEED1000;
2847
2848 /* Force a linkdown */
2849 if (netif_carrier_ok(tp->dev)) {
2850 u32 adv;
2851
2852 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2853 adv &= ~(ADVERTISE_1000XFULL |
2854 ADVERTISE_1000XHALF |
2855 ADVERTISE_SLCT);
2856 tg3_writephy(tp, MII_ADVERTISE, adv);
2857 tg3_writephy(tp, MII_BMCR, bmcr |
2858 BMCR_ANRESTART |
2859 BMCR_ANENABLE);
2860 udelay(10);
2861 netif_carrier_off(tp->dev);
2862 }
2863 tg3_writephy(tp, MII_BMCR, new_bmcr);
2864 bmcr = new_bmcr;
2865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2866 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 2867 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2868 ASIC_REV_5714) {
2869 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2870 bmsr |= BMSR_LSTATUS;
2871 else
2872 bmsr &= ~BMSR_LSTATUS;
2873 }
747e8f8b
MC		 2874 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2875 }
2876 }
2877
2878 if (bmsr & BMSR_LSTATUS) {
2879 current_speed = SPEED_1000;
2880 current_link_up = 1;
2881 if (bmcr & BMCR_FULLDPLX)
2882 current_duplex = DUPLEX_FULL;
2883 else
2884 current_duplex = DUPLEX_HALF;
2885
2886 if (bmcr & BMCR_ANENABLE) {
2887 u32 local_adv, remote_adv, common;
2888
2889 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2890 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2891 common = local_adv & remote_adv;
2892 if (common & (ADVERTISE_1000XHALF |
2893 ADVERTISE_1000XFULL)) {
2894 if (common & ADVERTISE_1000XFULL)
2895 current_duplex = DUPLEX_FULL;
2896 else
2897 current_duplex = DUPLEX_HALF;
2898
2899 tg3_setup_flow_control(tp, local_adv,
2900 remote_adv);
2901 }
2902 else
2903 current_link_up = 0;
2904 }
2905 }
2906
2907 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2908 if (tp->link_config.active_duplex == DUPLEX_HALF)
2909 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2910
2911 tw32_f(MAC_MODE, tp->mac_mode);
2912 udelay(40);
2913
2914 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2915
2916 tp->link_config.active_speed = current_speed;
2917 tp->link_config.active_duplex = current_duplex;
2918
2919 if (current_link_up != netif_carrier_ok(tp->dev)) {
2920 if (current_link_up)
2921 netif_carrier_on(tp->dev);
2922 else {
2923 netif_carrier_off(tp->dev);
2924 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2925 }
2926 tg3_link_report(tp);
2927 }
2928 return err;
2929}
2930
2931static void tg3_serdes_parallel_detect(struct tg3 *tp)
2932{
3d3ebe74 2933 if (tp->serdes_counter) {
747e8f8b 2934 /* Give autoneg time to complete. */
3d3ebe74 2935 tp->serdes_counter--;
747e8f8b
MC		 2936 return;
2937 }
2938 if (!netif_carrier_ok(tp->dev) &&
2939 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2940 u32 bmcr;
2941
2942 tg3_readphy(tp, MII_BMCR, &bmcr);
2943 if (bmcr & BMCR_ANENABLE) {
2944 u32 phy1, phy2;
2945
2946 /* Select shadow register 0x1f */
2947 tg3_writephy(tp, 0x1c, 0x7c00);
2948 tg3_readphy(tp, 0x1c, &phy1);
2949
2950 /* Select expansion interrupt status register */
2951 tg3_writephy(tp, 0x17, 0x0f01);
2952 tg3_readphy(tp, 0x15, &phy2);
2953 tg3_readphy(tp, 0x15, &phy2);
2954
2955 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2956 /* We have signal detect and not receiving
2957 * config code words, link is up by parallel
2958 * detection.
2959 */
2960
2961 bmcr &= ~BMCR_ANENABLE;
2962 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2963 tg3_writephy(tp, MII_BMCR, bmcr);
2964 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2965 }
2966 }
2967 }
2968 else if (netif_carrier_ok(tp->dev) &&
2969 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2970 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2971 u32 phy2;
2972
2973 /* Select expansion interrupt status register */
2974 tg3_writephy(tp, 0x17, 0x0f01);
2975 tg3_readphy(tp, 0x15, &phy2);
2976 if (phy2 & 0x20) {
2977 u32 bmcr;
2978
2979 /* Config code words received, turn on autoneg. */
2980 tg3_readphy(tp, MII_BMCR, &bmcr);
2981 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2982
2983 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2984
2985 }
2986 }
2987}
2988
1da177e4
LT		 2989static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2990{
2991 int err;
2992
2993 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2994 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2995 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2996 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2997 } else {
2998 err = tg3_setup_copper_phy(tp, force_reset);
2999 }
3000
3001 if (tp->link_config.active_speed == SPEED_1000 &&
3002 tp->link_config.active_duplex == DUPLEX_HALF)
3003 tw32(MAC_TX_LENGTHS,
3004 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3005 (6 << TX_LENGTHS_IPG_SHIFT) |
3006 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3007 else
3008 tw32(MAC_TX_LENGTHS,
3009 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3010 (6 << TX_LENGTHS_IPG_SHIFT) |
3011 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3012
3013 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3014 if (netif_carrier_ok(tp->dev)) {
3015 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3016 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3017 } else {
3018 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3019 }
3020 }
3021
8ed5d97e
MC		 3022 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3023 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3024 if (!netif_carrier_ok(tp->dev))
3025 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3026 tp->pwrmgmt_thresh;
3027 else
3028 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3029 tw32(PCIE_PWR_MGMT_THRESH, val);
3030 }
3031
1da177e4
LT		 3032 return err;
3033}
3034
df3e6548
MC		 3035/* This is called whenever we suspect that the system chipset is re-
3036 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3037 * is bogus tx completions. We try to recover by setting the
3038 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3039 * in the workqueue.
3040 */
3041static void tg3_tx_recover(struct tg3 *tp)
3042{
3043 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3044 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3045
3046 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3047 "mapped I/O cycles to the network device, attempting to "
3048 "recover. Please report the problem to the driver maintainer "
3049 "and include system chipset information.\n", tp->dev->name);
3050
3051 spin_lock(&tp->lock);
df3e6548 3052 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 3053 spin_unlock(&tp->lock);
3054}
3055
1b2a7205
MC		 3056static inline u32 tg3_tx_avail(struct tg3 *tp)
3057{
3058 smp_mb();
3059 return (tp->tx_pending -
3060 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3061}
3062
1da177e4
LT		 3063/* Tigon3 never reports partial packet sends. So we do not
3064 * need special logic to handle SKBs that have not had all
3065 * of their frags sent yet, like SunGEM does.
3066 */
3067static void tg3_tx(struct tg3 *tp)
3068{
3069 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3070 u32 sw_idx = tp->tx_cons;
3071
3072 while (sw_idx != hw_idx) {
3073 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3074 struct sk_buff *skb = ri->skb;
df3e6548
MC		 3075 int i, tx_bug = 0;
3076
3077 if (unlikely(skb == NULL)) {
3078 tg3_tx_recover(tp);
3079 return;
3080 }
1da177e4 3081
1da177e4
LT		 3082 pci_unmap_single(tp->pdev,
3083 pci_unmap_addr(ri, mapping),
3084 skb_headlen(skb),
3085 PCI_DMA_TODEVICE);
3086
3087 ri->skb = NULL;
3088
3089 sw_idx = NEXT_TX(sw_idx);
3090
3091 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 3092 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 3093 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3094 tx_bug = 1;
1da177e4
LT		 3095
3096 pci_unmap_page(tp->pdev,
3097 pci_unmap_addr(ri, mapping),
3098 skb_shinfo(skb)->frags[i].size,
3099 PCI_DMA_TODEVICE);
3100
3101 sw_idx = NEXT_TX(sw_idx);
3102 }
3103
f47c11ee 3104 dev_kfree_skb(skb);
df3e6548
MC		 3105
3106 if (unlikely(tx_bug)) {
3107 tg3_tx_recover(tp);
3108 return;
3109 }
1da177e4
LT		 3110 }
3111
3112 tp->tx_cons = sw_idx;
3113
1b2a7205
MC		 3114 /* Need to make the tx_cons update visible to tg3_start_xmit()
3115 * before checking for netif_queue_stopped(). Without the
3116 * memory barrier, there is a small possibility that tg3_start_xmit()
3117 * will miss it and cause the queue to be stopped forever.
3118 */
3119 smp_mb();
3120
3121 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 3122 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 3123 netif_tx_lock(tp->dev);
51b91468 3124 if (netif_queue_stopped(tp->dev) &&
42952231 3125 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 3126 netif_wake_queue(tp->dev);
1b2a7205 3127 netif_tx_unlock(tp->dev);
51b91468 3128 }
1da177e4
LT		 3129}
3130
3131/* Returns size of skb allocated or < 0 on error.
3132 *
3133 * We only need to fill in the address because the other members
3134 * of the RX descriptor are invariant, see tg3_init_rings.
3135 *
3136 * Note the purposeful assymetry of cpu vs. chip accesses. For
3137 * posting buffers we only dirty the first cache line of the RX
3138 * descriptor (containing the address). Whereas for the RX status
3139 * buffers the cpu only reads the last cacheline of the RX descriptor
3140 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3141 */
3142static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3143 int src_idx, u32 dest_idx_unmasked)
3144{
3145 struct tg3_rx_buffer_desc *desc;
3146 struct ring_info *map, *src_map;
3147 struct sk_buff *skb;
3148 dma_addr_t mapping;
3149 int skb_size, dest_idx;
3150
3151 src_map = NULL;
3152 switch (opaque_key) {
3153 case RXD_OPAQUE_RING_STD:
3154 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3155 desc = &tp->rx_std[dest_idx];
3156 map = &tp->rx_std_buffers[dest_idx];
3157 if (src_idx >= 0)
3158 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 3159 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 3160 break;
3161
3162 case RXD_OPAQUE_RING_JUMBO:
3163 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3164 desc = &tp->rx_jumbo[dest_idx];
3165 map = &tp->rx_jumbo_buffers[dest_idx];
3166 if (src_idx >= 0)
3167 src_map = &tp->rx_jumbo_buffers[src_idx];
3168 skb_size = RX_JUMBO_PKT_BUF_SZ;
3169 break;
3170
3171 default:
3172 return -EINVAL;
3173 };
3174
3175 /* Do not overwrite any of the map or rp information
3176 * until we are sure we can commit to a new buffer.
3177 *
3178 * Callers depend upon this behavior and assume that
3179 * we leave everything unchanged if we fail.
3180 */
a20e9c62 3181 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 3182 if (skb == NULL)
3183 return -ENOMEM;
3184
1da177e4
LT		 3185 skb_reserve(skb, tp->rx_offset);
3186
3187 mapping = pci_map_single(tp->pdev, skb->data,
3188 skb_size - tp->rx_offset,
3189 PCI_DMA_FROMDEVICE);
3190
3191 map->skb = skb;
3192 pci_unmap_addr_set(map, mapping, mapping);
3193
3194 if (src_map != NULL)
3195 src_map->skb = NULL;
3196
3197 desc->addr_hi = ((u64)mapping >> 32);
3198 desc->addr_lo = ((u64)mapping & 0xffffffff);
3199
3200 return skb_size;
3201}
3202
3203/* We only need to move over in the address because the other
3204 * members of the RX descriptor are invariant. See notes above
3205 * tg3_alloc_rx_skb for full details.
3206 */
3207static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3208 int src_idx, u32 dest_idx_unmasked)
3209{
3210 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3211 struct ring_info *src_map, *dest_map;
3212 int dest_idx;
3213
3214 switch (opaque_key) {
3215 case RXD_OPAQUE_RING_STD:
3216 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3217 dest_desc = &tp->rx_std[dest_idx];
3218 dest_map = &tp->rx_std_buffers[dest_idx];
3219 src_desc = &tp->rx_std[src_idx];
3220 src_map = &tp->rx_std_buffers[src_idx];
3221 break;
3222
3223 case RXD_OPAQUE_RING_JUMBO:
3224 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3225 dest_desc = &tp->rx_jumbo[dest_idx];
3226 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3227 src_desc = &tp->rx_jumbo[src_idx];
3228 src_map = &tp->rx_jumbo_buffers[src_idx];
3229 break;
3230
3231 default:
3232 return;
3233 };
3234
3235 dest_map->skb = src_map->skb;
3236 pci_unmap_addr_set(dest_map, mapping,
3237 pci_unmap_addr(src_map, mapping));
3238 dest_desc->addr_hi = src_desc->addr_hi;
3239 dest_desc->addr_lo = src_desc->addr_lo;
3240
3241 src_map->skb = NULL;
3242}
3243
3244#if TG3_VLAN_TAG_USED
3245static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3246{
3247 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3248}
3249#endif
3250
3251/* The RX ring scheme is composed of multiple rings which post fresh
3252 * buffers to the chip, and one special ring the chip uses to report
3253 * status back to the host.
3254 *
3255 * The special ring reports the status of received packets to the
3256 * host. The chip does not write into the original descriptor the
3257 * RX buffer was obtained from. The chip simply takes the original
3258 * descriptor as provided by the host, updates the status and length
3259 * field, then writes this into the next status ring entry.
3260 *
3261 * Each ring the host uses to post buffers to the chip is described
3262 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3263 * it is first placed into the on-chip ram. When the packet's length
3264 * is known, it walks down the TG3_BDINFO entries to select the ring.
3265 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3266 * which is within the range of the new packet's length is chosen.
3267 *
3268 * The "separate ring for rx status" scheme may sound queer, but it makes
3269 * sense from a cache coherency perspective. If only the host writes
3270 * to the buffer post rings, and only the chip writes to the rx status
3271 * rings, then cache lines never move beyond shared-modified state.
3272 * If both the host and chip were to write into the same ring, cache line
3273 * eviction could occur since both entities want it in an exclusive state.
3274 */
3275static int tg3_rx(struct tg3 *tp, int budget)
3276{
f92905de 3277 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 3278 u32 sw_idx = tp->rx_rcb_ptr;
3279 u16 hw_idx;
1da177e4
LT		 3280 int received;
3281
3282 hw_idx = tp->hw_status->idx[0].rx_producer;
3283 /*
3284 * We need to order the read of hw_idx and the read of
3285 * the opaque cookie.
3286 */
3287 rmb();
1da177e4
LT		 3288 work_mask = 0;
3289 received = 0;
3290 while (sw_idx != hw_idx && budget > 0) {
3291 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3292 unsigned int len;
3293 struct sk_buff *skb;
3294 dma_addr_t dma_addr;
3295 u32 opaque_key, desc_idx, *post_ptr;
3296
3297 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3298 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3299 if (opaque_key == RXD_OPAQUE_RING_STD) {
3300 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3301 mapping);
3302 skb = tp->rx_std_buffers[desc_idx].skb;
3303 post_ptr = &tp->rx_std_ptr;
f92905de 3304 rx_std_posted++;
1da177e4
LT		 3305 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3306 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3307 mapping);
3308 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3309 post_ptr = &tp->rx_jumbo_ptr;
3310 }
3311 else {
3312 goto next_pkt_nopost;
3313 }
3314
3315 work_mask |= opaque_key;
3316
3317 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3318 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3319 drop_it:
3320 tg3_recycle_rx(tp, opaque_key,
3321 desc_idx, *post_ptr);
3322 drop_it_no_recycle:
3323 /* Other statistics kept track of by card. */
3324 tp->net_stats.rx_dropped++;
3325 goto next_pkt;
3326 }
3327
3328 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3329
6aa20a22 3330 if (len > RX_COPY_THRESHOLD
1da177e4
LT		 3331 && tp->rx_offset == 2
3332 /* rx_offset != 2 iff this is a 5701 card running
3333 * in PCI-X mode [see tg3_get_invariants()] */
3334 ) {
3335 int skb_size;
3336
3337 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3338 desc_idx, *post_ptr);
3339 if (skb_size < 0)
3340 goto drop_it;
3341
3342 pci_unmap_single(tp->pdev, dma_addr,
3343 skb_size - tp->rx_offset,
3344 PCI_DMA_FROMDEVICE);
3345
3346 skb_put(skb, len);
3347 } else {
3348 struct sk_buff *copy_skb;
3349
3350 tg3_recycle_rx(tp, opaque_key,
3351 desc_idx, *post_ptr);
3352
a20e9c62 3353 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
1da177e4
LT		 3354 if (copy_skb == NULL)
3355 goto drop_it_no_recycle;
3356
1da177e4
LT		 3357 skb_reserve(copy_skb, 2);
3358 skb_put(copy_skb, len);
3359 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 3360 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 3361 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3362
3363 /* We'll reuse the original ring buffer. */
3364 skb = copy_skb;
3365 }
3366
3367 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3368 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3369 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3370 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3371 skb->ip_summed = CHECKSUM_UNNECESSARY;
3372 else
3373 skb->ip_summed = CHECKSUM_NONE;
3374
3375 skb->protocol = eth_type_trans(skb, tp->dev);
3376#if TG3_VLAN_TAG_USED
3377 if (tp->vlgrp != NULL &&
3378 desc->type_flags & RXD_FLAG_VLAN) {
3379 tg3_vlan_rx(tp, skb,
3380 desc->err_vlan & RXD_VLAN_MASK);
3381 } else
3382#endif
3383 netif_receive_skb(skb);
3384
3385 tp->dev->last_rx = jiffies;
3386 received++;
3387 budget--;
3388
3389next_pkt:
3390 (*post_ptr)++;
f92905de
MC		 3391
3392 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3393 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3394
3395 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3396 TG3_64BIT_REG_LOW, idx);
3397 work_mask &= ~RXD_OPAQUE_RING_STD;
3398 rx_std_posted = 0;
3399 }
1da177e4 3400next_pkt_nopost:
483ba50b 3401 sw_idx++;
6b31a515 3402 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 3403
3404 /* Refresh hw_idx to see if there is new work */
3405 if (sw_idx == hw_idx) {
3406 hw_idx = tp->hw_status->idx[0].rx_producer;
3407 rmb();
3408 }
1da177e4
LT		 3409 }
3410
3411 /* ACK the status ring. */
483ba50b
MC		 3412 tp->rx_rcb_ptr = sw_idx;
3413 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3414
3415 /* Refill RX ring(s). */
3416 if (work_mask & RXD_OPAQUE_RING_STD) {
3417 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3418 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3419 sw_idx);
3420 }
3421 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3422 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3423 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3424 sw_idx);
3425 }
3426 mmiowb();
3427
3428 return received;
3429}
3430
3431static int tg3_poll(struct net_device *netdev, int *budget)
3432{
3433 struct tg3 *tp = netdev_priv(netdev);
3434 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3435 int done;
3436
1da177e4
LT		 3437 /* handle link change and other phy events */
3438 if (!(tp->tg3_flags &
3439 (TG3_FLAG_USE_LINKCHG_REG |
3440 TG3_FLAG_POLL_SERDES))) {
3441 if (sblk->status & SD_STATUS_LINK_CHG) {
3442 sblk->status = SD_STATUS_UPDATED |
3443 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3444 spin_lock(&tp->lock);
1da177e4 3445 tg3_setup_phy(tp, 0);
f47c11ee 3446 spin_unlock(&tp->lock);
1da177e4
LT		 3447 }
3448 }
3449
3450 /* run TX completion thread */
3451 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 3452 tg3_tx(tp);
df3e6548
MC		 3453 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3454 netif_rx_complete(netdev);
3455 schedule_work(&tp->reset_task);
3456 return 0;
3457 }
1da177e4
LT		 3458 }
3459
1da177e4
LT		 3460 /* run RX thread, within the bounds set by NAPI.
3461 * All RX "locking" is done by ensuring outside
3462 * code synchronizes with dev->poll()
3463 */
1da177e4
LT		 3464 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3465 int orig_budget = *budget;
3466 int work_done;
3467
3468 if (orig_budget > netdev->quota)
3469 orig_budget = netdev->quota;
3470
3471 work_done = tg3_rx(tp, orig_budget);
3472
3473 *budget -= work_done;
3474 netdev->quota -= work_done;
1da177e4
LT		 3475 }
3476
38f3843e 3477 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
f7383c22 3478 tp->last_tag = sblk->status_tag;
38f3843e
MC		 3479 rmb();
3480 } else
3481 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3482
1da177e4 3483 /* if no more work, tell net stack and NIC we're done */
f7383c22 3484 done = !tg3_has_work(tp);
1da177e4 3485 if (done) {
f47c11ee 3486 netif_rx_complete(netdev);
1da177e4 3487 tg3_restart_ints(tp);
1da177e4
LT		 3488 }
3489
3490 return (done ? 0 : 1);
3491}
3492
f47c11ee
DM		 3493static void tg3_irq_quiesce(struct tg3 *tp)
3494{
3495 BUG_ON(tp->irq_sync);
3496
3497 tp->irq_sync = 1;
3498 smp_mb();
3499
3500 synchronize_irq(tp->pdev->irq);
3501}
3502
3503static inline int tg3_irq_sync(struct tg3 *tp)
3504{
3505 return tp->irq_sync;
3506}
3507
3508/* Fully shutdown all tg3 driver activity elsewhere in the system.
3509 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3510 * with as well. Most of the time, this is not necessary except when
3511 * shutting down the device.
3512 */
3513static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3514{
3515 if (irq_sync)
3516 tg3_irq_quiesce(tp);
3517 spin_lock_bh(&tp->lock);
f47c11ee
DM		 3518}
3519
3520static inline void tg3_full_unlock(struct tg3 *tp)
3521{
f47c11ee
DM		 3522 spin_unlock_bh(&tp->lock);
3523}
3524
fcfa0a32
MC		 3525/* One-shot MSI handler - Chip automatically disables interrupt
3526 * after sending MSI so driver doesn't have to do it.
3527 */
7d12e780 3528static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 3529{
3530 struct net_device *dev = dev_id;
3531 struct tg3 *tp = netdev_priv(dev);
3532
3533 prefetch(tp->hw_status);
3534 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3535
3536 if (likely(!tg3_irq_sync(tp)))
3537 netif_rx_schedule(dev); /* schedule NAPI poll */
3538
3539 return IRQ_HANDLED;
3540}
3541
88b06bc2
MC		 3542/* MSI ISR - No need to check for interrupt sharing and no need to
3543 * flush status block and interrupt mailbox. PCI ordering rules
3544 * guarantee that MSI will arrive after the status block.
3545 */
7d12e780 3546static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 3547{
3548 struct net_device *dev = dev_id;
3549 struct tg3 *tp = netdev_priv(dev);
88b06bc2 3550
61487480
MC		 3551 prefetch(tp->hw_status);
3552 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 3553 /*
fac9b83e 3554 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3555 * chip-internal interrupt pending events.
fac9b83e 3556 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3557 * NIC to stop sending us irqs, engaging "in-intr-handler"
3558 * event coalescing.
3559 */
3560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 3561 if (likely(!tg3_irq_sync(tp)))
88b06bc2 3562 netif_rx_schedule(dev); /* schedule NAPI poll */
61487480 3563
88b06bc2
MC		 3564 return IRQ_RETVAL(1);
3565}
3566
7d12e780 3567static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 3568{
3569 struct net_device *dev = dev_id;
3570 struct tg3 *tp = netdev_priv(dev);
3571 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3572 unsigned int handled = 1;
3573
1da177e4
LT		 3574 /* In INTx mode, it is possible for the interrupt to arrive at
3575 * the CPU before the status block posted prior to the interrupt.
3576 * Reading the PCI State register will confirm whether the
3577 * interrupt is ours and will flush the status block.
3578 */
d18edcb2
MC		 3579 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3580 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3581 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3582 handled = 0;
f47c11ee 3583 goto out;
fac9b83e 3584 }
d18edcb2
MC		 3585 }
3586
3587 /*
3588 * Writing any value to intr-mbox-0 clears PCI INTA# and
3589 * chip-internal interrupt pending events.
3590 * Writing non-zero to intr-mbox-0 additional tells the
3591 * NIC to stop sending us irqs, engaging "in-intr-handler"
3592 * event coalescing.
3593 */
3594 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3595 if (tg3_irq_sync(tp))
3596 goto out;
3597 sblk->status &= ~SD_STATUS_UPDATED;
3598 if (likely(tg3_has_work(tp))) {
3599 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3600 netif_rx_schedule(dev); /* schedule NAPI poll */
3601 } else {
3602 /* No work, shared interrupt perhaps? re-enable
3603 * interrupts, and flush that PCI write
3604 */
3605 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3606 0x00000000);
fac9b83e 3607 }
f47c11ee 3608out:
fac9b83e
DM		 3609 return IRQ_RETVAL(handled);
3610}
3611
7d12e780 3612static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 3613{
3614 struct net_device *dev = dev_id;
3615 struct tg3 *tp = netdev_priv(dev);
3616 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3617 unsigned int handled = 1;
3618
fac9b83e
DM		 3619 /* In INTx mode, it is possible for the interrupt to arrive at
3620 * the CPU before the status block posted prior to the interrupt.
3621 * Reading the PCI State register will confirm whether the
3622 * interrupt is ours and will flush the status block.
3623 */
d18edcb2
MC		 3624 if (unlikely(sblk->status_tag == tp->last_tag)) {
3625 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3626 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3627 handled = 0;
f47c11ee 3628 goto out;
1da177e4 3629 }
d18edcb2
MC		 3630 }
3631
3632 /*
3633 * writing any value to intr-mbox-0 clears PCI INTA# and
3634 * chip-internal interrupt pending events.
3635 * writing non-zero to intr-mbox-0 additional tells the
3636 * NIC to stop sending us irqs, engaging "in-intr-handler"
3637 * event coalescing.
3638 */
3639 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3640 if (tg3_irq_sync(tp))
3641 goto out;
3642 if (netif_rx_schedule_prep(dev)) {
3643 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3644 /* Update last_tag to mark that this status has been
3645 * seen. Because interrupt may be shared, we may be
3646 * racing with tg3_poll(), so only update last_tag
3647 * if tg3_poll() is not scheduled.
3648 */
3649 tp->last_tag = sblk->status_tag;
3650 __netif_rx_schedule(dev);
1da177e4 3651 }
f47c11ee 3652out:
1da177e4
LT		 3653 return IRQ_RETVAL(handled);
3654}
3655
7938109f 3656/* ISR for interrupt test */
7d12e780 3657static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 3658{
3659 struct net_device *dev = dev_id;
3660 struct tg3 *tp = netdev_priv(dev);
3661 struct tg3_hw_status *sblk = tp->hw_status;
3662
f9804ddb
MC		 3663 if ((sblk->status & SD_STATUS_UPDATED) ||
3664 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 3665 tg3_disable_ints(tp);
7938109f
MC		 3666 return IRQ_RETVAL(1);
3667 }
3668 return IRQ_RETVAL(0);
3669}
3670
8e7a22e3 3671static int tg3_init_hw(struct tg3 *, int);
944d980e 3672static int tg3_halt(struct tg3 *, int, int);
1da177e4 3673
b9ec6c1b
MC		 3674/* Restart hardware after configuration changes, self-test, etc.
3675 * Invoked with tp->lock held.
3676 */
3677static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3678{
3679 int err;
3680
3681 err = tg3_init_hw(tp, reset_phy);
3682 if (err) {
3683 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3684 "aborting.\n", tp->dev->name);
3685 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3686 tg3_full_unlock(tp);
3687 del_timer_sync(&tp->timer);
3688 tp->irq_sync = 0;
3689 netif_poll_enable(tp->dev);
3690 dev_close(tp->dev);
3691 tg3_full_lock(tp, 0);
3692 }
3693 return err;
3694}
3695
1da177e4
LT		 3696#ifdef CONFIG_NET_POLL_CONTROLLER
3697static void tg3_poll_controller(struct net_device *dev)
3698{
88b06bc2
MC		 3699 struct tg3 *tp = netdev_priv(dev);
3700
7d12e780 3701 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 3702}
3703#endif
3704
c4028958 3705static void tg3_reset_task(struct work_struct *work)
1da177e4 3706{
c4028958 3707 struct tg3 *tp = container_of(work, struct tg3, reset_task);
1da177e4
LT		 3708 unsigned int restart_timer;
3709
7faa006f
MC		 3710 tg3_full_lock(tp, 0);
3711 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3712
3713 if (!netif_running(tp->dev)) {
3714 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3715 tg3_full_unlock(tp);
3716 return;
3717 }
3718
3719 tg3_full_unlock(tp);
3720
1da177e4
LT		 3721 tg3_netif_stop(tp);
3722
f47c11ee 3723 tg3_full_lock(tp, 1);
1da177e4
LT		 3724
3725 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3726 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3727
df3e6548
MC		 3728 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3729 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3730 tp->write32_rx_mbox = tg3_write_flush_reg32;
3731 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3732 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3733 }
3734
944d980e 3735 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b9ec6c1b
MC		 3736 if (tg3_init_hw(tp, 1))
3737 goto out;
1da177e4
LT		 3738
3739 tg3_netif_start(tp);
3740
1da177e4
LT		 3741 if (restart_timer)
3742 mod_timer(&tp->timer, jiffies + 1);
7faa006f 3743
b9ec6c1b 3744out:
7faa006f
MC		 3745 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3746
3747 tg3_full_unlock(tp);
1da177e4
LT		 3748}
3749
b0408751
MC		 3750static void tg3_dump_short_state(struct tg3 *tp)
3751{
3752 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3753 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3754 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3755 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3756}
3757
1da177e4
LT		 3758static void tg3_tx_timeout(struct net_device *dev)
3759{
3760 struct tg3 *tp = netdev_priv(dev);
3761
b0408751 3762 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 3763 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3764 dev->name);
b0408751
MC		 3765 tg3_dump_short_state(tp);
3766 }
1da177e4
LT		 3767
3768 schedule_work(&tp->reset_task);
3769}
3770
c58ec932
MC		 3771/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3772static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3773{
3774 u32 base = (u32) mapping & 0xffffffff;
3775
3776 return ((base > 0xffffdcc0) &&
3777 (base + len + 8 < base));
3778}
3779
72f2afb8
MC		 3780/* Test for DMA addresses > 40-bit */
3781static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3782 int len)
3783{
3784#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 3785 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 3786 return (((u64) mapping + len) > DMA_40BIT_MASK);
3787 return 0;
3788#else
3789 return 0;
3790#endif
3791}
3792
1da177e4
LT		 3793static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3794
72f2afb8
MC		 3795/* Workaround 4GB and 40-bit hardware DMA bugs. */
3796static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 3797 u32 last_plus_one, u32 *start,
3798 u32 base_flags, u32 mss)
1da177e4
LT		 3799{
3800 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
c58ec932 3801 dma_addr_t new_addr = 0;
1da177e4 3802 u32 entry = *start;
c58ec932 3803 int i, ret = 0;
1da177e4
LT		 3804
3805 if (!new_skb) {
c58ec932
MC		 3806 ret = -1;
3807 } else {
3808 /* New SKB is guaranteed to be linear. */
3809 entry = *start;
3810 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3811 PCI_DMA_TODEVICE);
3812 /* Make sure new skb does not cross any 4G boundaries.
3813 * Drop the packet if it does.
3814 */
3815 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3816 ret = -1;
3817 dev_kfree_skb(new_skb);
3818 new_skb = NULL;
3819 } else {
3820 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3821 base_flags, 1 | (mss << 1));
3822 *start = NEXT_TX(entry);
3823 }
1da177e4
LT		 3824 }
3825
1da177e4
LT		 3826 /* Now clean up the sw ring entries. */
3827 i = 0;
3828 while (entry != last_plus_one) {
3829 int len;
3830
3831 if (i == 0)
3832 len = skb_headlen(skb);
3833 else
3834 len = skb_shinfo(skb)->frags[i-1].size;
3835 pci_unmap_single(tp->pdev,
3836 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3837 len, PCI_DMA_TODEVICE);
3838 if (i == 0) {
3839 tp->tx_buffers[entry].skb = new_skb;
3840 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3841 } else {
3842 tp->tx_buffers[entry].skb = NULL;
3843 }
3844 entry = NEXT_TX(entry);
3845 i++;
3846 }
3847
3848 dev_kfree_skb(skb);
3849
c58ec932 3850 return ret;
1da177e4
LT		 3851}
3852
3853static void tg3_set_txd(struct tg3 *tp, int entry,
3854 dma_addr_t mapping, int len, u32 flags,
3855 u32 mss_and_is_end)
3856{
3857 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3858 int is_end = (mss_and_is_end & 0x1);
3859 u32 mss = (mss_and_is_end >> 1);
3860 u32 vlan_tag = 0;
3861
3862 if (is_end)
3863 flags |= TXD_FLAG_END;
3864 if (flags & TXD_FLAG_VLAN) {
3865 vlan_tag = flags >> 16;
3866 flags &= 0xffff;
3867 }
3868 vlan_tag |= (mss << TXD_MSS_SHIFT);
3869
3870 txd->addr_hi = ((u64) mapping >> 32);
3871 txd->addr_lo = ((u64) mapping & 0xffffffff);
3872 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3873 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3874}
3875
5a6f3074
MC		 3876/* hard_start_xmit for devices that don't have any bugs and
3877 * support TG3_FLG2_HW_TSO_2 only.
3878 */
1da177e4 3879static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 3880{
3881 struct tg3 *tp = netdev_priv(dev);
3882 dma_addr_t mapping;
3883 u32 len, entry, base_flags, mss;
3884
3885 len = skb_headlen(skb);
3886
00b70504
MC		 3887 /* We are running in BH disabled context with netif_tx_lock
3888 * and TX reclaim runs via tp->poll inside of a software
5a6f3074
MC		 3889 * interrupt. Furthermore, IRQ processing runs lockless so we have
3890 * no IRQ context deadlocks to worry about either. Rejoice!
3891 */
1b2a7205 3892 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 3893 if (!netif_queue_stopped(dev)) {
3894 netif_stop_queue(dev);
3895
3896 /* This is a hard error, log it. */
3897 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3898 "queue awake!\n", dev->name);
3899 }
5a6f3074
MC		 3900 return NETDEV_TX_BUSY;
3901 }
3902
3903 entry = tp->tx_prod;
3904 base_flags = 0;
5a6f3074 3905 mss = 0;
c13e3713 3906 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 3907 int tcp_opt_len, ip_tcp_len;
3908
3909 if (skb_header_cloned(skb) &&
3910 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3911 dev_kfree_skb(skb);
3912 goto out_unlock;
3913 }
3914
b0026624
MC		 3915 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3916 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3917 else {
eddc9ec5
ACM		 3918 struct iphdr *iph = ip_hdr(skb);
3919
ab6a5bb6 3920 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 3921 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 3922
eddc9ec5
ACM		 3923 iph->check = 0;
3924 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 3925 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3926 }
5a6f3074
MC		 3927
3928 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3929 TXD_FLAG_CPU_POST_DMA);
3930
aa8223c7 3931 tcp_hdr(skb)->check = 0;
5a6f3074 3932
5a6f3074 3933 }
84fa7933 3934 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 3935 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 3936#if TG3_VLAN_TAG_USED
3937 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3938 base_flags |= (TXD_FLAG_VLAN |
3939 (vlan_tx_tag_get(skb) << 16));
3940#endif
3941
3942 /* Queue skb data, a.k.a. the main skb fragment. */
3943 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3944
3945 tp->tx_buffers[entry].skb = skb;
3946 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3947
3948 tg3_set_txd(tp, entry, mapping, len, base_flags,
3949 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3950
3951 entry = NEXT_TX(entry);
3952
3953 /* Now loop through additional data fragments, and queue them. */
3954 if (skb_shinfo(skb)->nr_frags > 0) {
3955 unsigned int i, last;
3956
3957 last = skb_shinfo(skb)->nr_frags - 1;
3958 for (i = 0; i <= last; i++) {
3959 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3960
3961 len = frag->size;
3962 mapping = pci_map_page(tp->pdev,
3963 frag->page,
3964 frag->page_offset,
3965 len, PCI_DMA_TODEVICE);
3966
3967 tp->tx_buffers[entry].skb = NULL;
3968 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3969
3970 tg3_set_txd(tp, entry, mapping, len,
3971 base_flags, (i == last) | (mss << 1));
3972
3973 entry = NEXT_TX(entry);
3974 }
3975 }
3976
3977 /* Packets are ready, update Tx producer idx local and on card. */
3978 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3979
3980 tp->tx_prod = entry;
1b2a7205 3981 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 3982 netif_stop_queue(dev);
42952231 3983 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 3984 netif_wake_queue(tp->dev);
3985 }
3986
3987out_unlock:
3988 mmiowb();
5a6f3074
MC		 3989
3990 dev->trans_start = jiffies;
3991
3992 return NETDEV_TX_OK;
3993}
3994
52c0fd83
MC		 3995static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3996
3997/* Use GSO to workaround a rare TSO bug that may be triggered when the
3998 * TSO header is greater than 80 bytes.
3999 */
4000static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4001{
4002 struct sk_buff *segs, *nskb;
4003
4004 /* Estimate the number of fragments in the worst case */
1b2a7205 4005 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 4006 netif_stop_queue(tp->dev);
7f62ad5d
MC		 4007 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4008 return NETDEV_TX_BUSY;
4009
4010 netif_wake_queue(tp->dev);
52c0fd83
MC		 4011 }
4012
4013 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4014 if (unlikely(IS_ERR(segs)))
4015 goto tg3_tso_bug_end;
4016
4017 do {
4018 nskb = segs;
4019 segs = segs->next;
4020 nskb->next = NULL;
4021 tg3_start_xmit_dma_bug(nskb, tp->dev);
4022 } while (segs);
4023
4024tg3_tso_bug_end:
4025 dev_kfree_skb(skb);
4026
4027 return NETDEV_TX_OK;
4028}
52c0fd83 4029
5a6f3074
MC		 4030/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4031 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4032 */
4033static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 4034{
4035 struct tg3 *tp = netdev_priv(dev);
4036 dma_addr_t mapping;
1da177e4
LT		 4037 u32 len, entry, base_flags, mss;
4038 int would_hit_hwbug;
1da177e4
LT		 4039
4040 len = skb_headlen(skb);
4041
00b70504
MC		 4042 /* We are running in BH disabled context with netif_tx_lock
4043 * and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 4044 * interrupt. Furthermore, IRQ processing runs lockless so we have
4045 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 4046 */
1b2a7205 4047 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 4048 if (!netif_queue_stopped(dev)) {
4049 netif_stop_queue(dev);
4050
4051 /* This is a hard error, log it. */
4052 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4053 "queue awake!\n", dev->name);
4054 }
1da177e4
LT		 4055 return NETDEV_TX_BUSY;
4056 }
4057
4058 entry = tp->tx_prod;
4059 base_flags = 0;
84fa7933 4060 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 4061 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 4062 mss = 0;
c13e3713 4063 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 4064 struct iphdr *iph;
52c0fd83 4065 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 4066
4067 if (skb_header_cloned(skb) &&
4068 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4069 dev_kfree_skb(skb);
4070 goto out_unlock;
4071 }
4072
ab6a5bb6 4073 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4074 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 4075
52c0fd83
MC		 4076 hdr_len = ip_tcp_len + tcp_opt_len;
4077 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 4078 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 4079 return (tg3_tso_bug(tp, skb));
4080
1da177e4
LT		 4081 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4082 TXD_FLAG_CPU_POST_DMA);
4083
eddc9ec5
ACM		 4084 iph = ip_hdr(skb);
4085 iph->check = 0;
4086 iph->tot_len = htons(mss + hdr_len);
1da177e4 4087 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 4088 tcp_hdr(skb)->check = 0;
1da177e4 4089 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 4090 } else
4091 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4092 iph->daddr, 0,
4093 IPPROTO_TCP,
4094 0);
1da177e4
LT		 4095
4096 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4097 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 4098 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4099 int tsflags;
4100
eddc9ec5 4101 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4102 mss |= (tsflags << 11);
4103 }
4104 } else {
eddc9ec5 4105 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 4106 int tsflags;
4107
eddc9ec5 4108 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 4109 base_flags |= tsflags << 12;
4110 }
4111 }
4112 }
1da177e4
LT		 4113#if TG3_VLAN_TAG_USED
4114 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4115 base_flags |= (TXD_FLAG_VLAN |
4116 (vlan_tx_tag_get(skb) << 16));
4117#endif
4118
4119 /* Queue skb data, a.k.a. the main skb fragment. */
4120 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4121
4122 tp->tx_buffers[entry].skb = skb;
4123 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4124
4125 would_hit_hwbug = 0;
4126
4127 if (tg3_4g_overflow_test(mapping, len))
c58ec932 4128 would_hit_hwbug = 1;
1da177e4
LT		 4129
4130 tg3_set_txd(tp, entry, mapping, len, base_flags,
4131 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4132
4133 entry = NEXT_TX(entry);
4134
4135 /* Now loop through additional data fragments, and queue them. */
4136 if (skb_shinfo(skb)->nr_frags > 0) {
4137 unsigned int i, last;
4138
4139 last = skb_shinfo(skb)->nr_frags - 1;
4140 for (i = 0; i <= last; i++) {
4141 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4142
4143 len = frag->size;
4144 mapping = pci_map_page(tp->pdev,
4145 frag->page,
4146 frag->page_offset,
4147 len, PCI_DMA_TODEVICE);
4148
4149 tp->tx_buffers[entry].skb = NULL;
4150 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4151
c58ec932
MC		 4152 if (tg3_4g_overflow_test(mapping, len))
4153 would_hit_hwbug = 1;
1da177e4 4154
72f2afb8
MC		 4155 if (tg3_40bit_overflow_test(tp, mapping, len))
4156 would_hit_hwbug = 1;
4157
1da177e4
LT		 4158 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4159 tg3_set_txd(tp, entry, mapping, len,
4160 base_flags, (i == last)|(mss << 1));
4161 else
4162 tg3_set_txd(tp, entry, mapping, len,
4163 base_flags, (i == last));
4164
4165 entry = NEXT_TX(entry);
4166 }
4167 }
4168
4169 if (would_hit_hwbug) {
4170 u32 last_plus_one = entry;
4171 u32 start;
1da177e4 4172
c58ec932
MC		 4173 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4174 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 4175
4176 /* If the workaround fails due to memory/mapping
4177 * failure, silently drop this packet.
4178 */
72f2afb8 4179 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 4180 &start, base_flags, mss))
1da177e4
LT		 4181 goto out_unlock;
4182
4183 entry = start;
4184 }
4185
4186 /* Packets are ready, update Tx producer idx local and on card. */
4187 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4188
4189 tp->tx_prod = entry;
1b2a7205 4190 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 4191 netif_stop_queue(dev);
42952231 4192 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 4193 netif_wake_queue(tp->dev);
4194 }
1da177e4
LT		 4195
4196out_unlock:
4197 mmiowb();
1da177e4
LT		 4198
4199 dev->trans_start = jiffies;
4200
4201 return NETDEV_TX_OK;
4202}
4203
4204static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4205 int new_mtu)
4206{
4207 dev->mtu = new_mtu;
4208
ef7f5ec0 4209 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 4210 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 4211 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4212 ethtool_op_set_tso(dev, 0);
4213 }
4214 else
4215 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4216 } else {
a4e2b347 4217 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 4218 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 4219 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 4220 }
1da177e4
LT		 4221}
4222
4223static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4224{
4225 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 4226 int err;
1da177e4
LT		 4227
4228 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4229 return -EINVAL;
4230
4231 if (!netif_running(dev)) {
4232 /* We'll just catch it later when the
4233 * device is up'd.
4234 */
4235 tg3_set_mtu(dev, tp, new_mtu);
4236 return 0;
4237 }
4238
4239 tg3_netif_stop(tp);
f47c11ee
DM		 4240
4241 tg3_full_lock(tp, 1);
1da177e4 4242
944d980e 4243 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 4244
4245 tg3_set_mtu(dev, tp, new_mtu);
4246
b9ec6c1b 4247 err = tg3_restart_hw(tp, 0);
1da177e4 4248
b9ec6c1b
MC		 4249 if (!err)
4250 tg3_netif_start(tp);
1da177e4 4251
f47c11ee 4252 tg3_full_unlock(tp);
1da177e4 4253
b9ec6c1b 4254 return err;
1da177e4
LT		 4255}
4256
4257/* Free up pending packets in all rx/tx rings.
4258 *
4259 * The chip has been shut down and the driver detached from
4260 * the networking, so no interrupts or new tx packets will
4261 * end up in the driver. tp->{tx,}lock is not held and we are not
4262 * in an interrupt context and thus may sleep.
4263 */
4264static void tg3_free_rings(struct tg3 *tp)
4265{
4266 struct ring_info *rxp;
4267 int i;
4268
4269 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4270 rxp = &tp->rx_std_buffers[i];
4271
4272 if (rxp->skb == NULL)
4273 continue;
4274 pci_unmap_single(tp->pdev,
4275 pci_unmap_addr(rxp, mapping),
7e72aad4 4276 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 4277 PCI_DMA_FROMDEVICE);
4278 dev_kfree_skb_any(rxp->skb);
4279 rxp->skb = NULL;
4280 }
4281
4282 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4283 rxp = &tp->rx_jumbo_buffers[i];
4284
4285 if (rxp->skb == NULL)
4286 continue;
4287 pci_unmap_single(tp->pdev,
4288 pci_unmap_addr(rxp, mapping),
4289 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4290 PCI_DMA_FROMDEVICE);
4291 dev_kfree_skb_any(rxp->skb);
4292 rxp->skb = NULL;
4293 }
4294
4295 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4296 struct tx_ring_info *txp;
4297 struct sk_buff *skb;
4298 int j;
4299
4300 txp = &tp->tx_buffers[i];
4301 skb = txp->skb;
4302
4303 if (skb == NULL) {
4304 i++;
4305 continue;
4306 }
4307
4308 pci_unmap_single(tp->pdev,
4309 pci_unmap_addr(txp, mapping),
4310 skb_headlen(skb),
4311 PCI_DMA_TODEVICE);
4312 txp->skb = NULL;
4313
4314 i++;
4315
4316 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4317 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4318 pci_unmap_page(tp->pdev,
4319 pci_unmap_addr(txp, mapping),
4320 skb_shinfo(skb)->frags[j].size,
4321 PCI_DMA_TODEVICE);
4322 i++;
4323 }
4324
4325 dev_kfree_skb_any(skb);
4326 }
4327}
4328
4329/* Initialize tx/rx rings for packet processing.
4330 *
4331 * The chip has been shut down and the driver detached from
4332 * the networking, so no interrupts or new tx packets will
4333 * end up in the driver. tp->{tx,}lock are held and thus
4334 * we may not sleep.
4335 */
32d8c572 4336static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 4337{
4338 u32 i;
4339
4340 /* Free up all the SKBs. */
4341 tg3_free_rings(tp);
4342
4343 /* Zero out all descriptors. */
4344 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4345 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4346 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4347 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4348
7e72aad4 4349 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 4350 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 4351 (tp->dev->mtu > ETH_DATA_LEN))
4352 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4353
1da177e4
LT		 4354 /* Initialize invariants of the rings, we only set this
4355 * stuff once. This works because the card does not
4356 * write into the rx buffer posting rings.
4357 */
4358 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4359 struct tg3_rx_buffer_desc *rxd;
4360
4361 rxd = &tp->rx_std[i];
7e72aad4 4362 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 4363 << RXD_LEN_SHIFT;
4364 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4365 rxd->opaque = (RXD_OPAQUE_RING_STD |
4366 (i << RXD_OPAQUE_INDEX_SHIFT));
4367 }
4368
0f893dc6 4369 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4370 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4371 struct tg3_rx_buffer_desc *rxd;
4372
4373 rxd = &tp->rx_jumbo[i];
4374 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4375 << RXD_LEN_SHIFT;
4376 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4377 RXD_FLAG_JUMBO;
4378 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4379 (i << RXD_OPAQUE_INDEX_SHIFT));
4380 }
4381 }
4382
4383 /* Now allocate fresh SKBs for each rx ring. */
4384 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 4385 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4386 printk(KERN_WARNING PFX
4387 "%s: Using a smaller RX standard ring, "
4388 "only %d out of %d buffers were allocated "
4389 "successfully.\n",
4390 tp->dev->name, i, tp->rx_pending);
4391 if (i == 0)
4392 return -ENOMEM;
4393 tp->rx_pending = i;
1da177e4 4394 break;
32d8c572 4395 }
1da177e4
LT		 4396 }
4397
0f893dc6 4398 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 4399 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4400 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 4401 -1, i) < 0) {
4402 printk(KERN_WARNING PFX
4403 "%s: Using a smaller RX jumbo ring, "
4404 "only %d out of %d buffers were "
4405 "allocated successfully.\n",
4406 tp->dev->name, i, tp->rx_jumbo_pending);
4407 if (i == 0) {
4408 tg3_free_rings(tp);
4409 return -ENOMEM;
4410 }
4411 tp->rx_jumbo_pending = i;
1da177e4 4412 break;
32d8c572 4413 }
1da177e4
LT		 4414 }
4415 }
32d8c572 4416 return 0;
1da177e4
LT		 4417}
4418
4419/*
4420 * Must not be invoked with interrupt sources disabled and
4421 * the hardware shutdown down.
4422 */
4423static void tg3_free_consistent(struct tg3 *tp)
4424{
b4558ea9
JJ		 4425 kfree(tp->rx_std_buffers);
4426 tp->rx_std_buffers = NULL;
1da177e4
LT		 4427 if (tp->rx_std) {
4428 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4429 tp->rx_std, tp->rx_std_mapping);
4430 tp->rx_std = NULL;
4431 }
4432 if (tp->rx_jumbo) {
4433 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4434 tp->rx_jumbo, tp->rx_jumbo_mapping);
4435 tp->rx_jumbo = NULL;
4436 }
4437 if (tp->rx_rcb) {
4438 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4439 tp->rx_rcb, tp->rx_rcb_mapping);
4440 tp->rx_rcb = NULL;
4441 }
4442 if (tp->tx_ring) {
4443 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4444 tp->tx_ring, tp->tx_desc_mapping);
4445 tp->tx_ring = NULL;
4446 }
4447 if (tp->hw_status) {
4448 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4449 tp->hw_status, tp->status_mapping);
4450 tp->hw_status = NULL;
4451 }
4452 if (tp->hw_stats) {
4453 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4454 tp->hw_stats, tp->stats_mapping);
4455 tp->hw_stats = NULL;
4456 }
4457}
4458
4459/*
4460 * Must not be invoked with interrupt sources disabled and
4461 * the hardware shutdown down. Can sleep.
4462 */
4463static int tg3_alloc_consistent(struct tg3 *tp)
4464{
bd2b3343 4465 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 4466 (TG3_RX_RING_SIZE +
4467 TG3_RX_JUMBO_RING_SIZE)) +
4468 (sizeof(struct tx_ring_info) *
4469 TG3_TX_RING_SIZE),
4470 GFP_KERNEL);
4471 if (!tp->rx_std_buffers)
4472 return -ENOMEM;
4473
1da177e4
LT		 4474 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4475 tp->tx_buffers = (struct tx_ring_info *)
4476 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4477
4478 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4479 &tp->rx_std_mapping);
4480 if (!tp->rx_std)
4481 goto err_out;
4482
4483 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4484 &tp->rx_jumbo_mapping);
4485
4486 if (!tp->rx_jumbo)
4487 goto err_out;
4488
4489 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4490 &tp->rx_rcb_mapping);
4491 if (!tp->rx_rcb)
4492 goto err_out;
4493
4494 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4495 &tp->tx_desc_mapping);
4496 if (!tp->tx_ring)
4497 goto err_out;
4498
4499 tp->hw_status = pci_alloc_consistent(tp->pdev,
4500 TG3_HW_STATUS_SIZE,
4501 &tp->status_mapping);
4502 if (!tp->hw_status)
4503 goto err_out;
4504
4505 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4506 sizeof(struct tg3_hw_stats),
4507 &tp->stats_mapping);
4508 if (!tp->hw_stats)
4509 goto err_out;
4510
4511 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4512 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4513
4514 return 0;
4515
4516err_out:
4517 tg3_free_consistent(tp);
4518 return -ENOMEM;
4519}
4520
4521#define MAX_WAIT_CNT 1000
4522
4523/* To stop a block, clear the enable bit and poll till it
4524 * clears. tp->lock is held.
4525 */
b3b7d6be 4526static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4527{
4528 unsigned int i;
4529 u32 val;
4530
4531 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4532 switch (ofs) {
4533 case RCVLSC_MODE:
4534 case DMAC_MODE:
4535 case MBFREE_MODE:
4536 case BUFMGR_MODE:
4537 case MEMARB_MODE:
4538 /* We can't enable/disable these bits of the
4539 * 5705/5750, just say success.
4540 */
4541 return 0;
4542
4543 default:
4544 break;
4545 };
4546 }
4547
4548 val = tr32(ofs);
4549 val &= ~enable_bit;
4550 tw32_f(ofs, val);
4551
4552 for (i = 0; i < MAX_WAIT_CNT; i++) {
4553 udelay(100);
4554 val = tr32(ofs);
4555 if ((val & enable_bit) == 0)
4556 break;
4557 }
4558
b3b7d6be 4559 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4560 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4561 "ofs=%lx enable_bit=%x\n",
4562 ofs, enable_bit);
4563 return -ENODEV;
4564 }
4565
4566 return 0;
4567}
4568
4569/* tp->lock is held. */
b3b7d6be 4570static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4571{
4572 int i, err;
4573
4574 tg3_disable_ints(tp);
4575
4576 tp->rx_mode &= ~RX_MODE_ENABLE;
4577 tw32_f(MAC_RX_MODE, tp->rx_mode);
4578 udelay(10);
4579
b3b7d6be
DM		 4580 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4581 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4582 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4583 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4584 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4585 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4586
4587 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4588 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4589 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4590 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4591 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4592 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4593 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4594
4595 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4596 tw32_f(MAC_MODE, tp->mac_mode);
4597 udelay(40);
4598
4599 tp->tx_mode &= ~TX_MODE_ENABLE;
4600 tw32_f(MAC_TX_MODE, tp->tx_mode);
4601
4602 for (i = 0; i < MAX_WAIT_CNT; i++) {
4603 udelay(100);
4604 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4605 break;
4606 }
4607 if (i >= MAX_WAIT_CNT) {
4608 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4609 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4610 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4611 err |= -ENODEV;
1da177e4
LT		 4612 }
4613
e6de8ad1 4614 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4615 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4616 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4617
4618 tw32(FTQ_RESET, 0xffffffff);
4619 tw32(FTQ_RESET, 0x00000000);
4620
b3b7d6be
DM		 4621 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4622 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4623
4624 if (tp->hw_status)
4625 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4626 if (tp->hw_stats)
4627 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4628
1da177e4
LT		 4629 return err;
4630}
4631
4632/* tp->lock is held. */
4633static int tg3_nvram_lock(struct tg3 *tp)
4634{
4635 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4636 int i;
4637
ec41c7df
MC		 4638 if (tp->nvram_lock_cnt == 0) {
4639 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4640 for (i = 0; i < 8000; i++) {
4641 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4642 break;
4643 udelay(20);
4644 }
4645 if (i == 8000) {
4646 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4647 return -ENODEV;
4648 }
1da177e4 4649 }
ec41c7df 4650 tp->nvram_lock_cnt++;
1da177e4
LT		 4651 }
4652 return 0;
4653}
4654
4655/* tp->lock is held. */
4656static void tg3_nvram_unlock(struct tg3 *tp)
4657{
ec41c7df
MC		 4658 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4659 if (tp->nvram_lock_cnt > 0)
4660 tp->nvram_lock_cnt--;
4661 if (tp->nvram_lock_cnt == 0)
4662 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4663 }
1da177e4
LT		 4664}
4665
e6af301b
MC		 4666/* tp->lock is held. */
4667static void tg3_enable_nvram_access(struct tg3 *tp)
4668{
4669 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4670 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4671 u32 nvaccess = tr32(NVRAM_ACCESS);
4672
4673 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4674 }
4675}
4676
4677/* tp->lock is held. */
4678static void tg3_disable_nvram_access(struct tg3 *tp)
4679{
4680 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4681 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4682 u32 nvaccess = tr32(NVRAM_ACCESS);
4683
4684 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4685 }
4686}
4687
1da177e4
LT		 4688/* tp->lock is held. */
4689static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4690{
f49639e6
DM		 4691 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4692 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 4693
4694 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4695 switch (kind) {
4696 case RESET_KIND_INIT:
4697 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4698 DRV_STATE_START);
4699 break;
4700
4701 case RESET_KIND_SHUTDOWN:
4702 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4703 DRV_STATE_UNLOAD);
4704 break;
4705
4706 case RESET_KIND_SUSPEND:
4707 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4708 DRV_STATE_SUSPEND);
4709 break;
4710
4711 default:
4712 break;
4713 };
4714 }
4715}
4716
4717/* tp->lock is held. */
4718static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4719{
4720 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4721 switch (kind) {
4722 case RESET_KIND_INIT:
4723 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4724 DRV_STATE_START_DONE);
4725 break;
4726
4727 case RESET_KIND_SHUTDOWN:
4728 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4729 DRV_STATE_UNLOAD_DONE);
4730 break;
4731
4732 default:
4733 break;
4734 };
4735 }
4736}
4737
4738/* tp->lock is held. */
4739static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4740{
4741 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4742 switch (kind) {
4743 case RESET_KIND_INIT:
4744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4745 DRV_STATE_START);
4746 break;
4747
4748 case RESET_KIND_SHUTDOWN:
4749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4750 DRV_STATE_UNLOAD);
4751 break;
4752
4753 case RESET_KIND_SUSPEND:
4754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4755 DRV_STATE_SUSPEND);
4756 break;
4757
4758 default:
4759 break;
4760 };
4761 }
4762}
4763
7a6f4369
MC		 4764static int tg3_poll_fw(struct tg3 *tp)
4765{
4766 int i;
4767 u32 val;
4768
b5d3772c 4769 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 4770 /* Wait up to 20ms for init done. */
4771 for (i = 0; i < 200; i++) {
b5d3772c
MC		 4772 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4773 return 0;
0ccead18 4774 udelay(100);
b5d3772c
MC		 4775 }
4776 return -ENODEV;
4777 }
4778
7a6f4369
MC		 4779 /* Wait for firmware initialization to complete. */
4780 for (i = 0; i < 100000; i++) {
4781 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4782 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4783 break;
4784 udelay(10);
4785 }
4786
4787 /* Chip might not be fitted with firmware. Some Sun onboard
4788 * parts are configured like that. So don't signal the timeout
4789 * of the above loop as an error, but do report the lack of
4790 * running firmware once.
4791 */
4792 if (i >= 100000 &&
4793 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4794 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4795
4796 printk(KERN_INFO PFX "%s: No firmware running.\n",
4797 tp->dev->name);
4798 }
4799
4800 return 0;
4801}
4802
1da177e4
LT		 4803static void tg3_stop_fw(struct tg3 *);
4804
4805/* tp->lock is held. */
4806static int tg3_chip_reset(struct tg3 *tp)
4807{
4808 u32 val;
1ee582d8 4809 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 4810 int err;
1da177e4 4811
f49639e6
DM		 4812 tg3_nvram_lock(tp);
4813
4814 /* No matching tg3_nvram_unlock() after this because
4815 * chip reset below will undo the nvram lock.
4816 */
4817 tp->nvram_lock_cnt = 0;
1da177e4 4818
d9ab5ad1 4819 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 4820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1
MC		 4821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4822 tw32(GRC_FASTBOOT_PC, 0);
4823
1da177e4
LT		 4824 /*
4825 * We must avoid the readl() that normally takes place.
4826 * It locks machines, causes machine checks, and other
4827 * fun things. So, temporarily disable the 5701
4828 * hardware workaround, while we do the reset.
4829 */
1ee582d8
MC		 4830 write_op = tp->write32;
4831 if (write_op == tg3_write_flush_reg32)
4832 tp->write32 = tg3_write32;
1da177e4 4833
d18edcb2
MC		 4834 /* Prevent the irq handler from reading or writing PCI registers
4835 * during chip reset when the memory enable bit in the PCI command
4836 * register may be cleared. The chip does not generate interrupt
4837 * at this time, but the irq handler may still be called due to irq
4838 * sharing or irqpoll.
4839 */
4840 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 4841 if (tp->hw_status) {
4842 tp->hw_status->status = 0;
4843 tp->hw_status->status_tag = 0;
4844 }
d18edcb2
MC		 4845 tp->last_tag = 0;
4846 smp_mb();
4847 synchronize_irq(tp->pdev->irq);
4848
1da177e4
LT		 4849 /* do the reset */
4850 val = GRC_MISC_CFG_CORECLK_RESET;
4851
4852 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4853 if (tr32(0x7e2c) == 0x60) {
4854 tw32(0x7e2c, 0x20);
4855 }
4856 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4857 tw32(GRC_MISC_CFG, (1 << 29));
4858 val |= (1 << 29);
4859 }
4860 }
4861
b5d3772c
MC		 4862 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4863 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4864 tw32(GRC_VCPU_EXT_CTRL,
4865 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4866 }
4867
1da177e4
LT		 4868 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4869 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4870 tw32(GRC_MISC_CFG, val);
4871
1ee582d8
MC		 4872 /* restore 5701 hardware bug workaround write method */
4873 tp->write32 = write_op;
1da177e4
LT		 4874
4875 /* Unfortunately, we have to delay before the PCI read back.
4876 * Some 575X chips even will not respond to a PCI cfg access
4877 * when the reset command is given to the chip.
4878 *
4879 * How do these hardware designers expect things to work
4880 * properly if the PCI write is posted for a long period
4881 * of time? It is always necessary to have some method by
4882 * which a register read back can occur to push the write
4883 * out which does the reset.
4884 *
4885 * For most tg3 variants the trick below was working.
4886 * Ho hum...
4887 */
4888 udelay(120);
4889
4890 /* Flush PCI posted writes. The normal MMIO registers
4891 * are inaccessible at this time so this is the only
4892 * way to make this reliably (actually, this is no longer
4893 * the case, see above). I tried to use indirect
4894 * register read/write but this upset some 5701 variants.
4895 */
4896 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4897
4898 udelay(120);
4899
4900 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4901 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4902 int i;
4903 u32 cfg_val;
4904
4905 /* Wait for link training to complete. */
4906 for (i = 0; i < 5000; i++)
4907 udelay(100);
4908
4909 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4910 pci_write_config_dword(tp->pdev, 0xc4,
4911 cfg_val | (1 << 15));
4912 }
4913 /* Set PCIE max payload size and clear error status. */
4914 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4915 }
4916
4917 /* Re-enable indirect register accesses. */
4918 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4919 tp->misc_host_ctrl);
4920
4921 /* Set MAX PCI retry to zero. */
4922 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4923 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4924 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4925 val |= PCISTATE_RETRY_SAME_DMA;
4926 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4927
4928 pci_restore_state(tp->pdev);
4929
d18edcb2
MC		 4930 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4931
1da177e4
LT		 4932 /* Make sure PCI-X relaxed ordering bit is clear. */
4933 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4934 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4935 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4936
a4e2b347 4937 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4cf78e4f
MC		 4938 u32 val;
4939
4940 /* Chip reset on 5780 will reset MSI enable bit,
4941 * so need to restore it.
4942 */
4943 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4944 u16 ctrl;
4945
4946 pci_read_config_word(tp->pdev,
4947 tp->msi_cap + PCI_MSI_FLAGS,
4948 &ctrl);
4949 pci_write_config_word(tp->pdev,
4950 tp->msi_cap + PCI_MSI_FLAGS,
4951 ctrl | PCI_MSI_FLAGS_ENABLE);
4952 val = tr32(MSGINT_MODE);
4953 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4954 }
4955
4956 val = tr32(MEMARB_MODE);
4957 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4958
4959 } else
4960 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4961
4962 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4963 tg3_stop_fw(tp);
4964 tw32(0x5000, 0x400);
4965 }
4966
4967 tw32(GRC_MODE, tp->grc_mode);
4968
4969 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4970 u32 val = tr32(0xc4);
4971
4972 tw32(0xc4, val | (1 << 15));
4973 }
4974
4975 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4977 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4978 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4979 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4980 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4981 }
4982
4983 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4984 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4985 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4986 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4987 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4988 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4989 } else
4990 tw32_f(MAC_MODE, 0);
4991 udelay(40);
4992
7a6f4369
MC		 4993 err = tg3_poll_fw(tp);
4994 if (err)
4995 return err;
1da177e4
LT		 4996
4997 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4998 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4999 u32 val = tr32(0x7c00);
5000
5001 tw32(0x7c00, val | (1 << 25));
5002 }
5003
5004 /* Reprobe ASF enable state. */
5005 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5006 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5007 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5008 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5009 u32 nic_cfg;
5010
5011 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5012 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5013 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 5014 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 5015 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5016 }
5017 }
5018
5019 return 0;
5020}
5021
5022/* tp->lock is held. */
5023static void tg3_stop_fw(struct tg3 *tp)
5024{
5025 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5026 u32 val;
5027 int i;
5028
5029 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5030 val = tr32(GRC_RX_CPU_EVENT);
5031 val |= (1 << 14);
5032 tw32(GRC_RX_CPU_EVENT, val);
5033
5034 /* Wait for RX cpu to ACK the event. */
5035 for (i = 0; i < 100; i++) {
5036 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5037 break;
5038 udelay(1);
5039 }
5040 }
5041}
5042
5043/* tp->lock is held. */
944d980e 5044static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 5045{
5046 int err;
5047
5048 tg3_stop_fw(tp);
5049
944d980e 5050 tg3_write_sig_pre_reset(tp, kind);
1da177e4 5051
b3b7d6be 5052 tg3_abort_hw(tp, silent);
1da177e4
LT		 5053 err = tg3_chip_reset(tp);
5054
944d980e
MC		 5055 tg3_write_sig_legacy(tp, kind);
5056 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 5057
5058 if (err)
5059 return err;
5060
5061 return 0;
5062}
5063
5064#define TG3_FW_RELEASE_MAJOR 0x0
5065#define TG3_FW_RELASE_MINOR 0x0
5066#define TG3_FW_RELEASE_FIX 0x0
5067#define TG3_FW_START_ADDR 0x08000000
5068#define TG3_FW_TEXT_ADDR 0x08000000
5069#define TG3_FW_TEXT_LEN 0x9c0
5070#define TG3_FW_RODATA_ADDR 0x080009c0
5071#define TG3_FW_RODATA_LEN 0x60
5072#define TG3_FW_DATA_ADDR 0x08000a40
5073#define TG3_FW_DATA_LEN 0x20
5074#define TG3_FW_SBSS_ADDR 0x08000a60
5075#define TG3_FW_SBSS_LEN 0xc
5076#define TG3_FW_BSS_ADDR 0x08000a70
5077#define TG3_FW_BSS_LEN 0x10
5078
50da859d 5079static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5080 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5081 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5082 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5083 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5084 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5085 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5086 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5087 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5088 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5089 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5090 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5091 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5092 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5093 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5094 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5095 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5096 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5097 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5098 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5099 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5100 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5101 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5102 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5103 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5104 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5105 0, 0, 0, 0, 0, 0,
5106 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5107 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5108 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5109 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5110 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5111 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5112 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5113 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5114 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5115 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5116 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5117 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5118 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5119 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5120 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5121 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5122 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5123 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5124 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5125 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5126 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5127 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5128 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5129 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5130 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5131 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5132 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5133 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5134 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5135 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5136 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5137 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5138 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5139 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5140 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5141 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5142 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5143 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5144 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5145 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5146 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5147 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5148 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5149 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5150 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5151 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5152 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5153 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5154 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5155 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5156 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5157 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5158 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5159 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5160 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5161 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5162 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5163 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5164 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5165 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5166 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5167 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5168 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5169 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5170 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5171};
5172
50da859d 5173static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
1da177e4
LT		 5174 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5175 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5176 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5177 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5178 0x00000000
5179};
5180
5181#if 0 /* All zeros, don't eat up space with it. */
5182u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5183 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5184 0x00000000, 0x00000000, 0x00000000, 0x00000000
5185};
5186#endif
5187
5188#define RX_CPU_SCRATCH_BASE 0x30000
5189#define RX_CPU_SCRATCH_SIZE 0x04000
5190#define TX_CPU_SCRATCH_BASE 0x34000
5191#define TX_CPU_SCRATCH_SIZE 0x04000
5192
5193/* tp->lock is held. */
5194static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5195{
5196 int i;
5197
5d9428de
ES		 5198 BUG_ON(offset == TX_CPU_BASE &&
5199 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 5200
b5d3772c
MC		 5201 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5202 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5203
5204 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5205 return 0;
5206 }
1da177e4
LT		 5207 if (offset == RX_CPU_BASE) {
5208 for (i = 0; i < 10000; i++) {
5209 tw32(offset + CPU_STATE, 0xffffffff);
5210 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5211 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5212 break;
5213 }
5214
5215 tw32(offset + CPU_STATE, 0xffffffff);
5216 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5217 udelay(10);
5218 } else {
5219 for (i = 0; i < 10000; i++) {
5220 tw32(offset + CPU_STATE, 0xffffffff);
5221 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5222 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5223 break;
5224 }
5225 }
5226
5227 if (i >= 10000) {
5228 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5229 "and %s CPU\n",
5230 tp->dev->name,
5231 (offset == RX_CPU_BASE ? "RX" : "TX"));
5232 return -ENODEV;
5233 }
ec41c7df
MC		 5234
5235 /* Clear firmware's nvram arbitration. */
5236 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5237 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 5238 return 0;
5239}
5240
5241struct fw_info {
5242 unsigned int text_base;
5243 unsigned int text_len;
50da859d 5244 const u32 *text_data;
1da177e4
LT		 5245 unsigned int rodata_base;
5246 unsigned int rodata_len;
50da859d 5247 const u32 *rodata_data;
1da177e4
LT		 5248 unsigned int data_base;
5249 unsigned int data_len;
50da859d 5250 const u32 *data_data;
1da177e4
LT		 5251};
5252
5253/* tp->lock is held. */
5254static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5255 int cpu_scratch_size, struct fw_info *info)
5256{
ec41c7df 5257 int err, lock_err, i;
1da177e4
LT		 5258 void (*write_op)(struct tg3 *, u32, u32);
5259
5260 if (cpu_base == TX_CPU_BASE &&
5261 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5262 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5263 "TX cpu firmware on %s which is 5705.\n",
5264 tp->dev->name);
5265 return -EINVAL;
5266 }
5267
5268 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5269 write_op = tg3_write_mem;
5270 else
5271 write_op = tg3_write_indirect_reg32;
5272
1b628151
MC		 5273 /* It is possible that bootcode is still loading at this point.
5274 * Get the nvram lock first before halting the cpu.
5275 */
ec41c7df 5276 lock_err = tg3_nvram_lock(tp);
1da177e4 5277 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 5278 if (!lock_err)
5279 tg3_nvram_unlock(tp);
1da177e4
LT		 5280 if (err)
5281 goto out;
5282
5283 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5284 write_op(tp, cpu_scratch_base + i, 0);
5285 tw32(cpu_base + CPU_STATE, 0xffffffff);
5286 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5287 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5288 write_op(tp, (cpu_scratch_base +
5289 (info->text_base & 0xffff) +
5290 (i * sizeof(u32))),
5291 (info->text_data ?
5292 info->text_data[i] : 0));
5293 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5294 write_op(tp, (cpu_scratch_base +
5295 (info->rodata_base & 0xffff) +
5296 (i * sizeof(u32))),
5297 (info->rodata_data ?
5298 info->rodata_data[i] : 0));
5299 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5300 write_op(tp, (cpu_scratch_base +
5301 (info->data_base & 0xffff) +
5302 (i * sizeof(u32))),
5303 (info->data_data ?
5304 info->data_data[i] : 0));
5305
5306 err = 0;
5307
5308out:
1da177e4
LT		 5309 return err;
5310}
5311
5312/* tp->lock is held. */
5313static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5314{
5315 struct fw_info info;
5316 int err, i;
5317
5318 info.text_base = TG3_FW_TEXT_ADDR;
5319 info.text_len = TG3_FW_TEXT_LEN;
5320 info.text_data = &tg3FwText[0];
5321 info.rodata_base = TG3_FW_RODATA_ADDR;
5322 info.rodata_len = TG3_FW_RODATA_LEN;
5323 info.rodata_data = &tg3FwRodata[0];
5324 info.data_base = TG3_FW_DATA_ADDR;
5325 info.data_len = TG3_FW_DATA_LEN;
5326 info.data_data = NULL;
5327
5328 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5329 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5330 &info);
5331 if (err)
5332 return err;
5333
5334 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5335 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5336 &info);
5337 if (err)
5338 return err;
5339
5340 /* Now startup only the RX cpu. */
5341 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5342 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5343
5344 for (i = 0; i < 5; i++) {
5345 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5346 break;
5347 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5348 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5349 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5350 udelay(1000);
5351 }
5352 if (i >= 5) {
5353 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5354 "to set RX CPU PC, is %08x should be %08x\n",
5355 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5356 TG3_FW_TEXT_ADDR);
5357 return -ENODEV;
5358 }
5359 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5360 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5361
5362 return 0;
5363}
5364
1da177e4
LT		 5365
5366#define TG3_TSO_FW_RELEASE_MAJOR 0x1
5367#define TG3_TSO_FW_RELASE_MINOR 0x6
5368#define TG3_TSO_FW_RELEASE_FIX 0x0
5369#define TG3_TSO_FW_START_ADDR 0x08000000
5370#define TG3_TSO_FW_TEXT_ADDR 0x08000000
5371#define TG3_TSO_FW_TEXT_LEN 0x1aa0
5372#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5373#define TG3_TSO_FW_RODATA_LEN 0x60
5374#define TG3_TSO_FW_DATA_ADDR 0x08001b20
5375#define TG3_TSO_FW_DATA_LEN 0x30
5376#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5377#define TG3_TSO_FW_SBSS_LEN 0x2c
5378#define TG3_TSO_FW_BSS_ADDR 0x08001b80
5379#define TG3_TSO_FW_BSS_LEN 0x894
5380
50da859d 5381static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5382 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5383 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5384 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5385 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5386 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5387 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5388 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5389 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5390 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5391 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5392 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5393 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5394 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5395 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5396 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5397 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5398 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5399 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5400 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5401 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5402 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5403 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5404 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5405 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5406 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5407 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5408 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5409 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5410 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5411 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5412 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5413 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5414 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5415 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5416 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5417 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5418 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5419 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5420 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5421 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5422 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5423 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5424 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5425 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5426 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5427 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5428 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5429 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5430 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5431 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5432 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5433 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5434 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5435 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5436 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5437 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5438 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5439 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5440 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5441 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5442 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5443 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5444 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5445 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5446 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5447 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5448 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5449 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5450 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5451 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5452 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5453 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5454 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5455 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5456 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5457 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5458 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5459 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5460 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5461 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5462 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5463 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5464 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5465 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5466 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5467 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5468 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5469 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5470 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5471 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5472 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5473 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5474 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5475 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5476 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5477 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5478 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5479 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5480 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5481 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5482 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5483 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5484 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5485 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5486 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5487 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5488 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5489 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5490 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5491 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5492 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5493 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5494 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5495 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5496 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5497 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5498 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5499 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5500 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5501 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5502 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5503 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5504 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5505 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5506 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5507 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5508 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5509 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5510 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5511 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5512 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5513 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5514 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5515 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5516 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5517 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5518 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5519 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5520 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5521 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5522 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5523 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5524 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5525 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5526 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5527 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5528 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5529 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5530 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5531 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5532 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5533 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5534 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5535 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5536 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5537 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5538 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5539 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5540 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5541 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5542 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5543 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5544 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5545 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5546 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5547 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5548 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5549 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5550 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5551 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5552 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5553 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5554 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5555 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5556 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5557 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5558 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5559 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5560 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5561 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5562 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5563 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5564 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5565 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5566 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5567 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5568 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5569 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5570 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5571 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5572 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5573 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5574 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5575 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5576 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5577 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5578 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5579 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5580 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5581 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5582 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5583 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5584 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5585 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5586 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5587 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5588 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5589 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5590 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5591 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5592 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5593 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5594 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5595 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5596 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5597 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5598 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5599 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5600 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5601 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5602 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5603 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5604 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5605 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5606 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5607 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5608 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5609 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5610 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5611 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5612 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5613 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5614 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5615 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5616 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5617 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5618 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5619 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5620 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5621 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5622 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5623 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5624 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5625 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5626 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5627 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5628 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5629 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5630 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5631 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5632 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5633 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5634 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5635 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5636 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5637 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5638 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5639 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5640 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5641 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5642 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5643 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5644 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5645 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5646 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5647 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5648 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5649 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5650 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5651 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5652 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5653 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5654 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5655 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5656 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5657 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5658 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5659 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5660 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5661 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5662 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5663 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5664 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5665 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5666};
5667
50da859d 5668static const u32 tg3TsoFwRodata[] = {
1da177e4
LT		 5669 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5670 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5671 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5672 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5673 0x00000000,
5674};
5675
50da859d 5676static const u32 tg3TsoFwData[] = {
1da177e4
LT		 5677 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5678 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5679 0x00000000,
5680};
5681
5682/* 5705 needs a special version of the TSO firmware. */
5683#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5684#define TG3_TSO5_FW_RELASE_MINOR 0x2
5685#define TG3_TSO5_FW_RELEASE_FIX 0x0
5686#define TG3_TSO5_FW_START_ADDR 0x00010000
5687#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5688#define TG3_TSO5_FW_TEXT_LEN 0xe90
5689#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5690#define TG3_TSO5_FW_RODATA_LEN 0x50
5691#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5692#define TG3_TSO5_FW_DATA_LEN 0x20
5693#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5694#define TG3_TSO5_FW_SBSS_LEN 0x28
5695#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5696#define TG3_TSO5_FW_BSS_LEN 0x88
5697
50da859d 5698static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
1da177e4
LT		 5699 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5700 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5701 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5702 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5703 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5704 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5705 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5706 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5707 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5708 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5709 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5710 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5711 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5712 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5713 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5714 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5715 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5716 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5717 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5718 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5719 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5720 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5721 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5722 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5723 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5724 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5725 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5726 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5727 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5728 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5729 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5730 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5731 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5732 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5733 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5734 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5735 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5736 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5737 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5738 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5739 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5740 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5741 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5742 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5743 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5744 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5745 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5746 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5747 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5748 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5749 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5750 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5751 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5752 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5753 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5754 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5755 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5756 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5757 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5758 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5759 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5760 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5761 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5762 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5763 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5764 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5765 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5766 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5767 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5768 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5769 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5770 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5771 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5772 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5773 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5774 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5775 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5776 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5777 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5778 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5779 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5780 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5781 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5782 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5783 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5784 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5785 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5786 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5787 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5788 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5789 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5790 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5791 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5792 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5793 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5794 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5795 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5796 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5797 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5798 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5799 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5800 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5801 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5802 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5803 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5804 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5805 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5806 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5807 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5808 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5809 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5810 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5811 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5812 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5813 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5814 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5815 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5816 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5817 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5818 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5819 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5820 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5821 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5822 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5823 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5824 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5825 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5826 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5827 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5828 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5829 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5830 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5831 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5832 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5833 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5834 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5835 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5836 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5837 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5838 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5839 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5840 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5841 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5842 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5843 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5844 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5845 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5846 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5847 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5848 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5849 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5850 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5851 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5852 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5853 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5854 0x00000000, 0x00000000, 0x00000000,
5855};
5856
50da859d 5857static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
1da177e4
LT		 5858 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5859 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5860 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5861 0x00000000, 0x00000000, 0x00000000,
5862};
5863
50da859d 5864static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
1da177e4
LT		 5865 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5866 0x00000000, 0x00000000, 0x00000000,
5867};
5868
5869/* tp->lock is held. */
5870static int tg3_load_tso_firmware(struct tg3 *tp)
5871{
5872 struct fw_info info;
5873 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5874 int err, i;
5875
5876 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5877 return 0;
5878
5879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5880 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5881 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5882 info.text_data = &tg3Tso5FwText[0];
5883 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5884 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5885 info.rodata_data = &tg3Tso5FwRodata[0];
5886 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5887 info.data_len = TG3_TSO5_FW_DATA_LEN;
5888 info.data_data = &tg3Tso5FwData[0];
5889 cpu_base = RX_CPU_BASE;
5890 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5891 cpu_scratch_size = (info.text_len +
5892 info.rodata_len +
5893 info.data_len +
5894 TG3_TSO5_FW_SBSS_LEN +
5895 TG3_TSO5_FW_BSS_LEN);
5896 } else {
5897 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5898 info.text_len = TG3_TSO_FW_TEXT_LEN;
5899 info.text_data = &tg3TsoFwText[0];
5900 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5901 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5902 info.rodata_data = &tg3TsoFwRodata[0];
5903 info.data_base = TG3_TSO_FW_DATA_ADDR;
5904 info.data_len = TG3_TSO_FW_DATA_LEN;
5905 info.data_data = &tg3TsoFwData[0];
5906 cpu_base = TX_CPU_BASE;
5907 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5908 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5909 }
5910
5911 err = tg3_load_firmware_cpu(tp, cpu_base,
5912 cpu_scratch_base, cpu_scratch_size,
5913 &info);
5914 if (err)
5915 return err;
5916
5917 /* Now startup the cpu. */
5918 tw32(cpu_base + CPU_STATE, 0xffffffff);
5919 tw32_f(cpu_base + CPU_PC, info.text_base);
5920
5921 for (i = 0; i < 5; i++) {
5922 if (tr32(cpu_base + CPU_PC) == info.text_base)
5923 break;
5924 tw32(cpu_base + CPU_STATE, 0xffffffff);
5925 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5926 tw32_f(cpu_base + CPU_PC, info.text_base);
5927 udelay(1000);
5928 }
5929 if (i >= 5) {
5930 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5931 "to set CPU PC, is %08x should be %08x\n",
5932 tp->dev->name, tr32(cpu_base + CPU_PC),
5933 info.text_base);
5934 return -ENODEV;
5935 }
5936 tw32(cpu_base + CPU_STATE, 0xffffffff);
5937 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5938 return 0;
5939}
5940
1da177e4
LT		 5941
5942/* tp->lock is held. */
986e0aeb 5943static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
1da177e4
LT		 5944{
5945 u32 addr_high, addr_low;
5946 int i;
5947
5948 addr_high = ((tp->dev->dev_addr[0] << 8) |
5949 tp->dev->dev_addr[1]);
5950 addr_low = ((tp->dev->dev_addr[2] << 24) |
5951 (tp->dev->dev_addr[3] << 16) |
5952 (tp->dev->dev_addr[4] << 8) |
5953 (tp->dev->dev_addr[5] << 0));
5954 for (i = 0; i < 4; i++) {
986e0aeb
MC		 5955 if (i == 1 && skip_mac_1)
5956 continue;
1da177e4
LT		 5957 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5958 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5959 }
5960
5961 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5963 for (i = 0; i < 12; i++) {
5964 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5965 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5966 }
5967 }
5968
5969 addr_high = (tp->dev->dev_addr[0] +
5970 tp->dev->dev_addr[1] +
5971 tp->dev->dev_addr[2] +
5972 tp->dev->dev_addr[3] +
5973 tp->dev->dev_addr[4] +
5974 tp->dev->dev_addr[5]) &
5975 TX_BACKOFF_SEED_MASK;
5976 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5977}
5978
5979static int tg3_set_mac_addr(struct net_device *dev, void *p)
5980{
5981 struct tg3 *tp = netdev_priv(dev);
5982 struct sockaddr *addr = p;
986e0aeb 5983 int err = 0, skip_mac_1 = 0;
1da177e4 5984
f9804ddb
MC		 5985 if (!is_valid_ether_addr(addr->sa_data))
5986 return -EINVAL;
5987
1da177e4
LT		 5988 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5989
e75f7c90
MC		 5990 if (!netif_running(dev))
5991 return 0;
5992
58712ef9 5993 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 5994 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 5995
986e0aeb
MC		 5996 addr0_high = tr32(MAC_ADDR_0_HIGH);
5997 addr0_low = tr32(MAC_ADDR_0_LOW);
5998 addr1_high = tr32(MAC_ADDR_1_HIGH);
5999 addr1_low = tr32(MAC_ADDR_1_LOW);
6000
6001 /* Skip MAC addr 1 if ASF is using it. */
6002 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6003 !(addr1_high == 0 && addr1_low == 0))
6004 skip_mac_1 = 1;
58712ef9 6005 }
986e0aeb
MC		 6006 spin_lock_bh(&tp->lock);
6007 __tg3_set_mac_addr(tp, skip_mac_1);
6008 spin_unlock_bh(&tp->lock);
1da177e4 6009
b9ec6c1b 6010 return err;
1da177e4
LT		 6011}
6012
6013/* tp->lock is held. */
6014static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6015 dma_addr_t mapping, u32 maxlen_flags,
6016 u32 nic_addr)
6017{
6018 tg3_write_mem(tp,
6019 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6020 ((u64) mapping >> 32));
6021 tg3_write_mem(tp,
6022 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6023 ((u64) mapping & 0xffffffff));
6024 tg3_write_mem(tp,
6025 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6026 maxlen_flags);
6027
6028 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6029 tg3_write_mem(tp,
6030 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6031 nic_addr);
6032}
6033
6034static void __tg3_set_rx_mode(struct net_device *);
d244c892 6035static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6036{
6037 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6038 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6039 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6040 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6041 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6042 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6043 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6044 }
6045 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6046 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6047 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6048 u32 val = ec->stats_block_coalesce_usecs;
6049
6050 if (!netif_carrier_ok(tp->dev))
6051 val = 0;
6052
6053 tw32(HOSTCC_STAT_COAL_TICKS, val);
6054 }
6055}
1da177e4
LT		 6056
6057/* tp->lock is held. */
8e7a22e3 6058static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6059{
6060 u32 val, rdmac_mode;
6061 int i, err, limit;
6062
6063 tg3_disable_ints(tp);
6064
6065 tg3_stop_fw(tp);
6066
6067 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6068
6069 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6070 tg3_abort_hw(tp, 1);
1da177e4
LT		 6071 }
6072
36da4d86 6073 if (reset_phy)
d4d2c558
MC		 6074 tg3_phy_reset(tp);
6075
1da177e4
LT		 6076 err = tg3_chip_reset(tp);
6077 if (err)
6078 return err;
6079
6080 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6081
6082 /* This works around an issue with Athlon chipsets on
6083 * B3 tigon3 silicon. This bit has no effect on any
6084 * other revision. But do not set this on PCI Express
6085 * chips.
6086 */
6087 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6088 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6089 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6090
6091 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6092 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6093 val = tr32(TG3PCI_PCISTATE);
6094 val |= PCISTATE_RETRY_SAME_DMA;
6095 tw32(TG3PCI_PCISTATE, val);
6096 }
6097
6098 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6099 /* Enable some hw fixes. */
6100 val = tr32(TG3PCI_MSI_DATA);
6101 val |= (1 << 26) | (1 << 28) | (1 << 29);
6102 tw32(TG3PCI_MSI_DATA, val);
6103 }
6104
6105 /* Descriptor ring init may make accesses to the
6106 * NIC SRAM area to setup the TX descriptors, so we
6107 * can only do this after the hardware has been
6108 * successfully reset.
6109 */
32d8c572
MC		 6110 err = tg3_init_rings(tp);
6111 if (err)
6112 return err;
1da177e4
LT		 6113
6114 /* This value is determined during the probe time DMA
6115 * engine test, tg3_test_dma.
6116 */
6117 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6118
6119 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6120 GRC_MODE_4X_NIC_SEND_RINGS |
6121 GRC_MODE_NO_TX_PHDR_CSUM |
6122 GRC_MODE_NO_RX_PHDR_CSUM);
6123 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6124
6125 /* Pseudo-header checksum is done by hardware logic and not
6126 * the offload processers, so make the chip do the pseudo-
6127 * header checksums on receive. For transmit it is more
6128 * convenient to do the pseudo-header checksum in software
6129 * as Linux does that on transmit for us in all cases.
6130 */
6131 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6132
6133 tw32(GRC_MODE,
6134 tp->grc_mode |
6135 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6136
6137 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6138 val = tr32(GRC_MISC_CFG);
6139 val &= ~0xff;
6140 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6141 tw32(GRC_MISC_CFG, val);
6142
6143 /* Initialize MBUF/DESC pool. */
cbf46853 6144 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6145 /* Do nothing. */
6146 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6147 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6149 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6150 else
6151 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6152 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6153 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6154 }
1da177e4
LT		 6155 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6156 int fw_len;
6157
6158 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6159 TG3_TSO5_FW_RODATA_LEN +
6160 TG3_TSO5_FW_DATA_LEN +
6161 TG3_TSO5_FW_SBSS_LEN +
6162 TG3_TSO5_FW_BSS_LEN);
6163 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6164 tw32(BUFMGR_MB_POOL_ADDR,
6165 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6166 tw32(BUFMGR_MB_POOL_SIZE,
6167 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6168 }
1da177e4 6169
0f893dc6 6170 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6171 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6172 tp->bufmgr_config.mbuf_read_dma_low_water);
6173 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6174 tp->bufmgr_config.mbuf_mac_rx_low_water);
6175 tw32(BUFMGR_MB_HIGH_WATER,
6176 tp->bufmgr_config.mbuf_high_water);
6177 } else {
6178 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6179 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6180 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6181 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6182 tw32(BUFMGR_MB_HIGH_WATER,
6183 tp->bufmgr_config.mbuf_high_water_jumbo);
6184 }
6185 tw32(BUFMGR_DMA_LOW_WATER,
6186 tp->bufmgr_config.dma_low_water);
6187 tw32(BUFMGR_DMA_HIGH_WATER,
6188 tp->bufmgr_config.dma_high_water);
6189
6190 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6191 for (i = 0; i < 2000; i++) {
6192 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6193 break;
6194 udelay(10);
6195 }
6196 if (i >= 2000) {
6197 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6198 tp->dev->name);
6199 return -ENODEV;
6200 }
6201
6202 /* Setup replenish threshold. */
f92905de
MC		 6203 val = tp->rx_pending / 8;
6204 if (val == 0)
6205 val = 1;
6206 else if (val > tp->rx_std_max_post)
6207 val = tp->rx_std_max_post;
b5d3772c
MC		 6208 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6209 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6210 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6211
6212 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6213 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6214 }
f92905de
MC		 6215
6216 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6217
6218 /* Initialize TG3_BDINFO's at:
6219 * RCVDBDI_STD_BD: standard eth size rx ring
6220 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6221 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6222 *
6223 * like so:
6224 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6225 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6226 * ring attribute flags
6227 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6228 *
6229 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6230 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6231 *
6232 * The size of each ring is fixed in the firmware, but the location is
6233 * configurable.
6234 */
6235 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6236 ((u64) tp->rx_std_mapping >> 32));
6237 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6238 ((u64) tp->rx_std_mapping & 0xffffffff));
6239 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6240 NIC_SRAM_RX_BUFFER_DESC);
6241
6242 /* Don't even try to program the JUMBO/MINI buffer descriptor
6243 * configs on 5705.
6244 */
6245 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6246 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6247 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6248 } else {
6249 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6250 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6251
6252 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6253 BDINFO_FLAGS_DISABLED);
6254
6255 /* Setup replenish threshold. */
6256 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6257
0f893dc6 6258 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6259 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6260 ((u64) tp->rx_jumbo_mapping >> 32));
6261 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6262 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6263 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6264 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6265 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6266 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6267 } else {
6268 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6269 BDINFO_FLAGS_DISABLED);
6270 }
6271
6272 }
6273
6274 /* There is only one send ring on 5705/5750, no need to explicitly
6275 * disable the others.
6276 */
6277 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6278 /* Clear out send RCB ring in SRAM. */
6279 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6280 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6281 BDINFO_FLAGS_DISABLED);
6282 }
6283
6284 tp->tx_prod = 0;
6285 tp->tx_cons = 0;
6286 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6287 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6288
6289 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6290 tp->tx_desc_mapping,
6291 (TG3_TX_RING_SIZE <<
6292 BDINFO_FLAGS_MAXLEN_SHIFT),
6293 NIC_SRAM_TX_BUFFER_DESC);
6294
6295 /* There is only one receive return ring on 5705/5750, no need
6296 * to explicitly disable the others.
6297 */
6298 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6299 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6300 i += TG3_BDINFO_SIZE) {
6301 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6302 BDINFO_FLAGS_DISABLED);
6303 }
6304 }
6305
6306 tp->rx_rcb_ptr = 0;
6307 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6308
6309 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6310 tp->rx_rcb_mapping,
6311 (TG3_RX_RCB_RING_SIZE(tp) <<
6312 BDINFO_FLAGS_MAXLEN_SHIFT),
6313 0);
6314
6315 tp->rx_std_ptr = tp->rx_pending;
6316 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6317 tp->rx_std_ptr);
6318
0f893dc6 6319 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6320 tp->rx_jumbo_pending : 0;
6321 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6322 tp->rx_jumbo_ptr);
6323
6324 /* Initialize MAC address and backoff seed. */
986e0aeb 6325 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6326
6327 /* MTU + ethernet header + FCS + optional VLAN tag */
6328 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6329
6330 /* The slot time is changed by tg3_setup_phy if we
6331 * run at gigabit with half duplex.
6332 */
6333 tw32(MAC_TX_LENGTHS,
6334 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6335 (6 << TX_LENGTHS_IPG_SHIFT) |
6336 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6337
6338 /* Receive rules. */
6339 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6340 tw32(RCVLPC_CONFIG, 0x0181);
6341
6342 /* Calculate RDMAC_MODE setting early, we need it to determine
6343 * the RCVLPC_STATE_ENABLE mask.
6344 */
6345 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6346 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6347 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6348 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6349 RDMAC_MODE_LNGREAD_ENAB);
85e94ced
MC		 6350
6351 /* If statement applies to 5705 and 5750 PCI devices only */
6352 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6353 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6354 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 6355 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 6356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6357 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6358 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6359 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6360 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6361 }
6362 }
6363
85e94ced
MC		 6364 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6365 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6366
1da177e4
LT		 6367 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6368 rdmac_mode |= (1 << 27);
1da177e4
LT		 6369
6370 /* Receive/send statistics. */
1661394e
MC		 6371 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6372 val = tr32(RCVLPC_STATS_ENABLE);
6373 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6374 tw32(RCVLPC_STATS_ENABLE, val);
6375 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6376 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6377 val = tr32(RCVLPC_STATS_ENABLE);
6378 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6379 tw32(RCVLPC_STATS_ENABLE, val);
6380 } else {
6381 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6382 }
6383 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6384 tw32(SNDDATAI_STATSENAB, 0xffffff);
6385 tw32(SNDDATAI_STATSCTRL,
6386 (SNDDATAI_SCTRL_ENABLE |
6387 SNDDATAI_SCTRL_FASTUPD));
6388
6389 /* Setup host coalescing engine. */
6390 tw32(HOSTCC_MODE, 0);
6391 for (i = 0; i < 2000; i++) {
6392 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6393 break;
6394 udelay(10);
6395 }
6396
d244c892 6397 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6398
6399 /* set status block DMA address */
6400 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6401 ((u64) tp->status_mapping >> 32));
6402 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6403 ((u64) tp->status_mapping & 0xffffffff));
6404
6405 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6406 /* Status/statistics block address. See tg3_timer,
6407 * the tg3_periodic_fetch_stats call there, and
6408 * tg3_get_stats to see how this works for 5705/5750 chips.
6409 */
1da177e4
LT		 6410 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6411 ((u64) tp->stats_mapping >> 32));
6412 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6413 ((u64) tp->stats_mapping & 0xffffffff));
6414 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6415 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6416 }
6417
6418 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6419
6420 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6421 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6422 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6423 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6424
6425 /* Clear statistics/status block in chip, and status block in ram. */
6426 for (i = NIC_SRAM_STATS_BLK;
6427 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6428 i += sizeof(u32)) {
6429 tg3_write_mem(tp, i, 0);
6430 udelay(40);
6431 }
6432 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6433
c94e3941
MC		 6434 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6435 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6436 /* reset to prevent losing 1st rx packet intermittently */
6437 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6438 udelay(10);
6439 }
6440
1da177e4
LT		 6441 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6442 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6443 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6444 udelay(40);
6445
314fba34 6446 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6447 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6448 * register to preserve the GPIO settings for LOMs. The GPIOs,
6449 * whether used as inputs or outputs, are set by boot code after
6450 * reset.
6451 */
9d26e213 6452 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6453 u32 gpio_mask;
6454
9d26e213
MC		 6455 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6456 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6457 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6458
6459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6460 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6461 GRC_LCLCTRL_GPIO_OUTPUT3;
6462
af36e6b6
MC		 6463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6464 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6465
aaf84465 6466 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 6467 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6468
6469 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6470 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6471 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6472 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6473 }
1da177e4
LT		 6474 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6475 udelay(100);
6476
09ee929c 6477 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 6478 tp->last_tag = 0;
1da177e4
LT		 6479
6480 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6481 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6482 udelay(40);
6483 }
6484
6485 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6486 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6487 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6488 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6489 WDMAC_MODE_LNGREAD_ENAB);
6490
85e94ced
MC		 6491 /* If statement applies to 5705 and 5750 PCI devices only */
6492 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6493 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6494 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 6495 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6496 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6497 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6498 /* nothing */
6499 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6500 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6501 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6502 val |= WDMAC_MODE_RX_ACCEL;
6503 }
6504 }
6505
d9ab5ad1 6506 /* Enable host coalescing bug fix */
af36e6b6
MC		 6507 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6508 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
d9ab5ad1
MC		 6509 val |= (1 << 29);
6510
1da177e4
LT		 6511 tw32_f(WDMAC_MODE, val);
6512 udelay(40);
6513
6514 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6515 val = tr32(TG3PCI_X_CAPS);
6516 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6517 val &= ~PCIX_CAPS_BURST_MASK;
6518 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6519 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6520 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6521 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
1da177e4
LT		 6522 }
6523 tw32(TG3PCI_X_CAPS, val);
6524 }
6525
6526 tw32_f(RDMAC_MODE, rdmac_mode);
6527 udelay(40);
6528
6529 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6530 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6531 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6532 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6533 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6534 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6535 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6536 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 6537 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6538 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 6539 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6540 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6541
6542 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6543 err = tg3_load_5701_a0_firmware_fix(tp);
6544 if (err)
6545 return err;
6546 }
6547
1da177e4
LT		 6548 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6549 err = tg3_load_tso_firmware(tp);
6550 if (err)
6551 return err;
6552 }
1da177e4
LT		 6553
6554 tp->tx_mode = TX_MODE_ENABLE;
6555 tw32_f(MAC_TX_MODE, tp->tx_mode);
6556 udelay(100);
6557
6558 tp->rx_mode = RX_MODE_ENABLE;
af36e6b6
MC		 6559 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6560 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6561
1da177e4
LT		 6562 tw32_f(MAC_RX_MODE, tp->rx_mode);
6563 udelay(10);
6564
6565 if (tp->link_config.phy_is_low_power) {
6566 tp->link_config.phy_is_low_power = 0;
6567 tp->link_config.speed = tp->link_config.orig_speed;
6568 tp->link_config.duplex = tp->link_config.orig_duplex;
6569 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6570 }
6571
6572 tp->mi_mode = MAC_MI_MODE_BASE;
6573 tw32_f(MAC_MI_MODE, tp->mi_mode);
6574 udelay(80);
6575
6576 tw32(MAC_LED_CTRL, tp->led_ctrl);
6577
6578 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 6579 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 6580 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6581 udelay(10);
6582 }
6583 tw32_f(MAC_RX_MODE, tp->rx_mode);
6584 udelay(10);
6585
6586 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6587 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6588 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6589 /* Set drive transmission level to 1.2V */
6590 /* only if the signal pre-emphasis bit is not set */
6591 val = tr32(MAC_SERDES_CFG);
6592 val &= 0xfffff000;
6593 val |= 0x880;
6594 tw32(MAC_SERDES_CFG, val);
6595 }
6596 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6597 tw32(MAC_SERDES_CFG, 0x616000);
6598 }
6599
6600 /* Prevent chip from dropping frames when flow control
6601 * is enabled.
6602 */
6603 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6604
6605 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6606 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6607 /* Use hardware link auto-negotiation */
6608 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6609 }
6610
d4d2c558
MC		 6611 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6612 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6613 u32 tmp;
6614
6615 tmp = tr32(SERDES_RX_CTRL);
6616 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6617 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6618 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6619 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6620 }
6621
36da4d86 6622 err = tg3_setup_phy(tp, 0);
1da177e4
LT		 6623 if (err)
6624 return err;
6625
715116a1
MC		 6626 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6627 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1da177e4
LT		 6628 u32 tmp;
6629
6630 /* Clear CRC stats. */
569a5df8
MC		 6631 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6632 tg3_writephy(tp, MII_TG3_TEST1,
6633 tmp | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 6634 tg3_readphy(tp, 0x14, &tmp);
6635 }
6636 }
6637
6638 __tg3_set_rx_mode(tp->dev);
6639
6640 /* Initialize receive rules. */
6641 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6642 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6643 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6644 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6645
4cf78e4f 6646 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 6647 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 6648 limit = 8;
6649 else
6650 limit = 16;
6651 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6652 limit -= 4;
6653 switch (limit) {
6654 case 16:
6655 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6656 case 15:
6657 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6658 case 14:
6659 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6660 case 13:
6661 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6662 case 12:
6663 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6664 case 11:
6665 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6666 case 10:
6667 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6668 case 9:
6669 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6670 case 8:
6671 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6672 case 7:
6673 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6674 case 6:
6675 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6676 case 5:
6677 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6678 case 4:
6679 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6680 case 3:
6681 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6682 case 2:
6683 case 1:
6684
6685 default:
6686 break;
6687 };
6688
6689 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6690
1da177e4
LT		 6691 return 0;
6692}
6693
6694/* Called at device open time to get the chip ready for
6695 * packet processing. Invoked with tp->lock held.
6696 */
8e7a22e3 6697static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6698{
6699 int err;
6700
6701 /* Force the chip into D0. */
bc1c7567 6702 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 6703 if (err)
6704 goto out;
6705
6706 tg3_switch_clocks(tp);
6707
6708 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6709
8e7a22e3 6710 err = tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 6711
6712out:
6713 return err;
6714}
6715
6716#define TG3_STAT_ADD32(PSTAT, REG) \
6717do { u32 __val = tr32(REG); \
6718 (PSTAT)->low += __val; \
6719 if ((PSTAT)->low < __val) \
6720 (PSTAT)->high += 1; \
6721} while (0)
6722
6723static void tg3_periodic_fetch_stats(struct tg3 *tp)
6724{
6725 struct tg3_hw_stats *sp = tp->hw_stats;
6726
6727 if (!netif_carrier_ok(tp->dev))
6728 return;
6729
6730 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6731 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6732 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6733 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6734 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6735 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6736 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6737 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6738 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6739 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6740 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6741 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6742 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6743
6744 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6745 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6746 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6747 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6748 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6749 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6750 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6751 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6752 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6753 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6754 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6755 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6756 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6757 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 6758
6759 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6760 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6761 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 6762}
6763
6764static void tg3_timer(unsigned long __opaque)
6765{
6766 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6767
f475f163
MC		 6768 if (tp->irq_sync)
6769 goto restart_timer;
6770
f47c11ee 6771 spin_lock(&tp->lock);
1da177e4 6772
fac9b83e
DM		 6773 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6774 /* All of this garbage is because when using non-tagged
6775 * IRQ status the mailbox/status_block protocol the chip
6776 * uses with the cpu is race prone.
6777 */
6778 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6779 tw32(GRC_LOCAL_CTRL,
6780 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6781 } else {
6782 tw32(HOSTCC_MODE, tp->coalesce_mode |
6783 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6784 }
1da177e4 6785
fac9b83e
DM		 6786 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6787 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6788 spin_unlock(&tp->lock);
fac9b83e
DM		 6789 schedule_work(&tp->reset_task);
6790 return;
6791 }
1da177e4
LT		 6792 }
6793
1da177e4
LT		 6794 /* This part only runs once per second. */
6795 if (!--tp->timer_counter) {
fac9b83e
DM		 6796 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6797 tg3_periodic_fetch_stats(tp);
6798
1da177e4
LT		 6799 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6800 u32 mac_stat;
6801 int phy_event;
6802
6803 mac_stat = tr32(MAC_STATUS);
6804
6805 phy_event = 0;
6806 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6807 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6808 phy_event = 1;
6809 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6810 phy_event = 1;
6811
6812 if (phy_event)
6813 tg3_setup_phy(tp, 0);
6814 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6815 u32 mac_stat = tr32(MAC_STATUS);
6816 int need_setup = 0;
6817
6818 if (netif_carrier_ok(tp->dev) &&
6819 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6820 need_setup = 1;
6821 }
6822 if (! netif_carrier_ok(tp->dev) &&
6823 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6824 MAC_STATUS_SIGNAL_DET))) {
6825 need_setup = 1;
6826 }
6827 if (need_setup) {
3d3ebe74
MC		 6828 if (!tp->serdes_counter) {
6829 tw32_f(MAC_MODE,
6830 (tp->mac_mode &
6831 ~MAC_MODE_PORT_MODE_MASK));
6832 udelay(40);
6833 tw32_f(MAC_MODE, tp->mac_mode);
6834 udelay(40);
6835 }
1da177e4
LT		 6836 tg3_setup_phy(tp, 0);
6837 }
747e8f8b
MC		 6838 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6839 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6840
6841 tp->timer_counter = tp->timer_multiplier;
6842 }
6843
130b8e4d
MC		 6844 /* Heartbeat is only sent once every 2 seconds.
6845 *
6846 * The heartbeat is to tell the ASF firmware that the host
6847 * driver is still alive. In the event that the OS crashes,
6848 * ASF needs to reset the hardware to free up the FIFO space
6849 * that may be filled with rx packets destined for the host.
6850 * If the FIFO is full, ASF will no longer function properly.
6851 *
6852 * Unintended resets have been reported on real time kernels
6853 * where the timer doesn't run on time. Netpoll will also have
6854 * same problem.
6855 *
6856 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6857 * to check the ring condition when the heartbeat is expiring
6858 * before doing the reset. This will prevent most unintended
6859 * resets.
6860 */
1da177e4
LT		 6861 if (!--tp->asf_counter) {
6862 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6863 u32 val;
6864
bbadf503 6865 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 6866 FWCMD_NICDRV_ALIVE3);
bbadf503 6867 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 6868 /* 5 seconds timeout */
bbadf503 6869 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
1da177e4
LT		 6870 val = tr32(GRC_RX_CPU_EVENT);
6871 val |= (1 << 14);
6872 tw32(GRC_RX_CPU_EVENT, val);
6873 }
6874 tp->asf_counter = tp->asf_multiplier;
6875 }
6876
f47c11ee 6877 spin_unlock(&tp->lock);
1da177e4 6878
f475f163 6879restart_timer:
1da177e4
LT		 6880 tp->timer.expires = jiffies + tp->timer_offset;
6881 add_timer(&tp->timer);
6882}
6883
81789ef5 6884static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 6885{
7d12e780 6886 irq_handler_t fn;
fcfa0a32
MC		 6887 unsigned long flags;
6888 struct net_device *dev = tp->dev;
6889
6890 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6891 fn = tg3_msi;
6892 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6893 fn = tg3_msi_1shot;
1fb9df5d 6894 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6895 } else {
6896 fn = tg3_interrupt;
6897 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6898 fn = tg3_interrupt_tagged;
1fb9df5d 6899 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 6900 }
6901 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6902}
6903
7938109f
MC		 6904static int tg3_test_interrupt(struct tg3 *tp)
6905{
6906 struct net_device *dev = tp->dev;
b16250e3 6907 int err, i, intr_ok = 0;
7938109f 6908
d4bc3927
MC		 6909 if (!netif_running(dev))
6910 return -ENODEV;
6911
7938109f
MC		 6912 tg3_disable_ints(tp);
6913
6914 free_irq(tp->pdev->irq, dev);
6915
6916 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 6917 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6918 if (err)
6919 return err;
6920
38f3843e 6921 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 6922 tg3_enable_ints(tp);
6923
6924 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6925 HOSTCC_MODE_NOW);
6926
6927 for (i = 0; i < 5; i++) {
b16250e3
MC		 6928 u32 int_mbox, misc_host_ctrl;
6929
09ee929c
MC		 6930 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6931 TG3_64BIT_REG_LOW);
b16250e3
MC		 6932 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6933
6934 if ((int_mbox != 0) ||
6935 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6936 intr_ok = 1;
7938109f 6937 break;
b16250e3
MC		 6938 }
6939
7938109f
MC		 6940 msleep(10);
6941 }
6942
6943 tg3_disable_ints(tp);
6944
6945 free_irq(tp->pdev->irq, dev);
6aa20a22 6946
fcfa0a32 6947 err = tg3_request_irq(tp);
7938109f
MC		 6948
6949 if (err)
6950 return err;
6951
b16250e3 6952 if (intr_ok)
7938109f
MC		 6953 return 0;
6954
6955 return -EIO;
6956}
6957
6958/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6959 * successfully restored
6960 */
6961static int tg3_test_msi(struct tg3 *tp)
6962{
6963 struct net_device *dev = tp->dev;
6964 int err;
6965 u16 pci_cmd;
6966
6967 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6968 return 0;
6969
6970 /* Turn off SERR reporting in case MSI terminates with Master
6971 * Abort.
6972 */
6973 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6974 pci_write_config_word(tp->pdev, PCI_COMMAND,
6975 pci_cmd & ~PCI_COMMAND_SERR);
6976
6977 err = tg3_test_interrupt(tp);
6978
6979 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6980
6981 if (!err)
6982 return 0;
6983
6984 /* other failures */
6985 if (err != -EIO)
6986 return err;
6987
6988 /* MSI test failed, go back to INTx mode */
6989 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6990 "switching to INTx mode. Please report this failure to "
6991 "the PCI maintainer and include system chipset information.\n",
6992 tp->dev->name);
6993
6994 free_irq(tp->pdev->irq, dev);
6995 pci_disable_msi(tp->pdev);
6996
6997 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6998
fcfa0a32 6999 err = tg3_request_irq(tp);
7938109f
MC		 7000 if (err)
7001 return err;
7002
7003 /* Need to reset the chip because the MSI cycle may have terminated
7004 * with Master Abort.
7005 */
f47c11ee 7006 tg3_full_lock(tp, 1);
7938109f 7007
944d980e 7008 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7009 err = tg3_init_hw(tp, 1);
7938109f 7010
f47c11ee 7011 tg3_full_unlock(tp);
7938109f
MC		 7012
7013 if (err)
7014 free_irq(tp->pdev->irq, dev);
7015
7016 return err;
7017}
7018
1da177e4
LT		 7019static int tg3_open(struct net_device *dev)
7020{
7021 struct tg3 *tp = netdev_priv(dev);
7022 int err;
7023
c49a1561
MC		 7024 netif_carrier_off(tp->dev);
7025
f47c11ee 7026 tg3_full_lock(tp, 0);
1da177e4 7027
bc1c7567 7028 err = tg3_set_power_state(tp, PCI_D0);
12862086
IS		 7029 if (err) {
7030 tg3_full_unlock(tp);
bc1c7567 7031 return err;
12862086 7032 }
bc1c7567 7033
1da177e4
LT		 7034 tg3_disable_ints(tp);
7035 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7036
f47c11ee 7037 tg3_full_unlock(tp);
1da177e4
LT		 7038
7039 /* The placement of this call is tied
7040 * to the setup and use of Host TX descriptors.
7041 */
7042 err = tg3_alloc_consistent(tp);
7043 if (err)
7044 return err;
7045
7544b097 7046 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7047 /* All MSI supporting chips should support tagged
7048 * status. Assert that this is the case.
7049 */
7050 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7051 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7052 "Not using MSI.\n", tp->dev->name);
7053 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7054 u32 msi_mode;
7055
7056 msi_mode = tr32(MSGINT_MODE);
7057 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7058 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7059 }
7060 }
fcfa0a32 7061 err = tg3_request_irq(tp);
1da177e4
LT		 7062
7063 if (err) {
88b06bc2
MC		 7064 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7065 pci_disable_msi(tp->pdev);
7066 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7067 }
1da177e4
LT		 7068 tg3_free_consistent(tp);
7069 return err;
7070 }
7071
f47c11ee 7072 tg3_full_lock(tp, 0);
1da177e4 7073
8e7a22e3 7074 err = tg3_init_hw(tp, 1);
1da177e4 7075 if (err) {
944d980e 7076 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7077 tg3_free_rings(tp);
7078 } else {
fac9b83e
DM		 7079 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7080 tp->timer_offset = HZ;
7081 else
7082 tp->timer_offset = HZ / 10;
7083
7084 BUG_ON(tp->timer_offset > HZ);
7085 tp->timer_counter = tp->timer_multiplier =
7086 (HZ / tp->timer_offset);
7087 tp->asf_counter = tp->asf_multiplier =
28fbef78 7088 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7089
7090 init_timer(&tp->timer);
7091 tp->timer.expires = jiffies + tp->timer_offset;
7092 tp->timer.data = (unsigned long) tp;
7093 tp->timer.function = tg3_timer;
1da177e4
LT		 7094 }
7095
f47c11ee 7096 tg3_full_unlock(tp);
1da177e4
LT		 7097
7098 if (err) {
88b06bc2
MC		 7099 free_irq(tp->pdev->irq, dev);
7100 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7101 pci_disable_msi(tp->pdev);
7102 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7103 }
1da177e4
LT		 7104 tg3_free_consistent(tp);
7105 return err;
7106 }
7107
7938109f
MC		 7108 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7109 err = tg3_test_msi(tp);
fac9b83e 7110
7938109f 7111 if (err) {
f47c11ee 7112 tg3_full_lock(tp, 0);
7938109f
MC		 7113
7114 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7115 pci_disable_msi(tp->pdev);
7116 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7117 }
944d980e 7118 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7119 tg3_free_rings(tp);
7120 tg3_free_consistent(tp);
7121
f47c11ee 7122 tg3_full_unlock(tp);
7938109f
MC		 7123
7124 return err;
7125 }
fcfa0a32
MC		 7126
7127 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7128 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7129 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7130
b5d3772c
MC		 7131 tw32(PCIE_TRANSACTION_CFG,
7132 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7133 }
7134 }
7938109f
MC		 7135 }
7136
f47c11ee 7137 tg3_full_lock(tp, 0);
1da177e4 7138
7938109f
MC		 7139 add_timer(&tp->timer);
7140 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7141 tg3_enable_ints(tp);
7142
f47c11ee 7143 tg3_full_unlock(tp);
1da177e4
LT		 7144
7145 netif_start_queue(dev);
7146
7147 return 0;
7148}
7149
7150#if 0
7151/*static*/ void tg3_dump_state(struct tg3 *tp)
7152{
7153 u32 val32, val32_2, val32_3, val32_4, val32_5;
7154 u16 val16;
7155 int i;
7156
7157 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7158 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7159 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7160 val16, val32);
7161
7162 /* MAC block */
7163 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7164 tr32(MAC_MODE), tr32(MAC_STATUS));
7165 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7166 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7167 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7168 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7169 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7170 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7171
7172 /* Send data initiator control block */
7173 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7174 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7175 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7176 tr32(SNDDATAI_STATSCTRL));
7177
7178 /* Send data completion control block */
7179 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7180
7181 /* Send BD ring selector block */
7182 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7183 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7184
7185 /* Send BD initiator control block */
7186 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7187 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7188
7189 /* Send BD completion control block */
7190 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7191
7192 /* Receive list placement control block */
7193 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7194 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7195 printk(" RCVLPC_STATSCTRL[%08x]\n",
7196 tr32(RCVLPC_STATSCTRL));
7197
7198 /* Receive data and receive BD initiator control block */
7199 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7200 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7201
7202 /* Receive data completion control block */
7203 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7204 tr32(RCVDCC_MODE));
7205
7206 /* Receive BD initiator control block */
7207 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7208 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7209
7210 /* Receive BD completion control block */
7211 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7212 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7213
7214 /* Receive list selector control block */
7215 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7216 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7217
7218 /* Mbuf cluster free block */
7219 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7220 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7221
7222 /* Host coalescing control block */
7223 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7224 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7225 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7226 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7227 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7228 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7229 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7230 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7231 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7232 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7233 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7234 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7235
7236 /* Memory arbiter control block */
7237 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7238 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7239
7240 /* Buffer manager control block */
7241 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7242 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7243 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7244 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7245 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7246 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7247 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7248 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7249
7250 /* Read DMA control block */
7251 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7252 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7253
7254 /* Write DMA control block */
7255 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7256 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7257
7258 /* DMA completion block */
7259 printk("DEBUG: DMAC_MODE[%08x]\n",
7260 tr32(DMAC_MODE));
7261
7262 /* GRC block */
7263 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7264 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7265 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7266 tr32(GRC_LOCAL_CTRL));
7267
7268 /* TG3_BDINFOs */
7269 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7270 tr32(RCVDBDI_JUMBO_BD + 0x0),
7271 tr32(RCVDBDI_JUMBO_BD + 0x4),
7272 tr32(RCVDBDI_JUMBO_BD + 0x8),
7273 tr32(RCVDBDI_JUMBO_BD + 0xc));
7274 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7275 tr32(RCVDBDI_STD_BD + 0x0),
7276 tr32(RCVDBDI_STD_BD + 0x4),
7277 tr32(RCVDBDI_STD_BD + 0x8),
7278 tr32(RCVDBDI_STD_BD + 0xc));
7279 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7280 tr32(RCVDBDI_MINI_BD + 0x0),
7281 tr32(RCVDBDI_MINI_BD + 0x4),
7282 tr32(RCVDBDI_MINI_BD + 0x8),
7283 tr32(RCVDBDI_MINI_BD + 0xc));
7284
7285 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7286 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7287 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7288 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7289 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7290 val32, val32_2, val32_3, val32_4);
7291
7292 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7293 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7294 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7295 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7296 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7297 val32, val32_2, val32_3, val32_4);
7298
7299 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7300 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7301 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7302 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7303 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7304 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7305 val32, val32_2, val32_3, val32_4, val32_5);
7306
7307 /* SW status block */
7308 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7309 tp->hw_status->status,
7310 tp->hw_status->status_tag,
7311 tp->hw_status->rx_jumbo_consumer,
7312 tp->hw_status->rx_consumer,
7313 tp->hw_status->rx_mini_consumer,
7314 tp->hw_status->idx[0].rx_producer,
7315 tp->hw_status->idx[0].tx_consumer);
7316
7317 /* SW statistics block */
7318 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7319 ((u32 *)tp->hw_stats)[0],
7320 ((u32 *)tp->hw_stats)[1],
7321 ((u32 *)tp->hw_stats)[2],
7322 ((u32 *)tp->hw_stats)[3]);
7323
7324 /* Mailboxes */
7325 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7326 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7327 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7328 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7329 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7330
7331 /* NIC side send descriptors. */
7332 for (i = 0; i < 6; i++) {
7333 unsigned long txd;
7334
7335 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7336 + (i * sizeof(struct tg3_tx_buffer_desc));
7337 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7338 i,
7339 readl(txd + 0x0), readl(txd + 0x4),
7340 readl(txd + 0x8), readl(txd + 0xc));
7341 }
7342
7343 /* NIC side RX descriptors. */
7344 for (i = 0; i < 6; i++) {
7345 unsigned long rxd;
7346
7347 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7348 + (i * sizeof(struct tg3_rx_buffer_desc));
7349 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7350 i,
7351 readl(rxd + 0x0), readl(rxd + 0x4),
7352 readl(rxd + 0x8), readl(rxd + 0xc));
7353 rxd += (4 * sizeof(u32));
7354 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7355 i,
7356 readl(rxd + 0x0), readl(rxd + 0x4),
7357 readl(rxd + 0x8), readl(rxd + 0xc));
7358 }
7359
7360 for (i = 0; i < 6; i++) {
7361 unsigned long rxd;
7362
7363 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7364 + (i * sizeof(struct tg3_rx_buffer_desc));
7365 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7366 i,
7367 readl(rxd + 0x0), readl(rxd + 0x4),
7368 readl(rxd + 0x8), readl(rxd + 0xc));
7369 rxd += (4 * sizeof(u32));
7370 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7371 i,
7372 readl(rxd + 0x0), readl(rxd + 0x4),
7373 readl(rxd + 0x8), readl(rxd + 0xc));
7374 }
7375}
7376#endif
7377
7378static struct net_device_stats *tg3_get_stats(struct net_device *);
7379static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7380
7381static int tg3_close(struct net_device *dev)
7382{
7383 struct tg3 *tp = netdev_priv(dev);
7384
7faa006f
MC		 7385 /* Calling flush_scheduled_work() may deadlock because
7386 * linkwatch_event() may be on the workqueue and it will try to get
7387 * the rtnl_lock which we are holding.
7388 */
7389 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7390 msleep(1);
7391
1da177e4
LT		 7392 netif_stop_queue(dev);
7393
7394 del_timer_sync(&tp->timer);
7395
f47c11ee 7396 tg3_full_lock(tp, 1);
1da177e4
LT		 7397#if 0
7398 tg3_dump_state(tp);
7399#endif
7400
7401 tg3_disable_ints(tp);
7402
944d980e 7403 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 7404 tg3_free_rings(tp);
5cf64b8a 7405 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 7406
f47c11ee 7407 tg3_full_unlock(tp);
1da177e4 7408
88b06bc2
MC		 7409 free_irq(tp->pdev->irq, dev);
7410 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7411 pci_disable_msi(tp->pdev);
7412 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7413 }
1da177e4
LT		 7414
7415 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7416 sizeof(tp->net_stats_prev));
7417 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7418 sizeof(tp->estats_prev));
7419
7420 tg3_free_consistent(tp);
7421
bc1c7567
MC		 7422 tg3_set_power_state(tp, PCI_D3hot);
7423
7424 netif_carrier_off(tp->dev);
7425
1da177e4
LT		 7426 return 0;
7427}
7428
7429static inline unsigned long get_stat64(tg3_stat64_t *val)
7430{
7431 unsigned long ret;
7432
7433#if (BITS_PER_LONG == 32)
7434 ret = val->low;
7435#else
7436 ret = ((u64)val->high << 32) | ((u64)val->low);
7437#endif
7438 return ret;
7439}
7440
7441static unsigned long calc_crc_errors(struct tg3 *tp)
7442{
7443 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7444
7445 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7446 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7447 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 7448 u32 val;
7449
f47c11ee 7450 spin_lock_bh(&tp->lock);
569a5df8
MC		 7451 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7452 tg3_writephy(tp, MII_TG3_TEST1,
7453 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 7454 tg3_readphy(tp, 0x14, &val);
7455 } else
7456 val = 0;
f47c11ee 7457 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7458
7459 tp->phy_crc_errors += val;
7460
7461 return tp->phy_crc_errors;
7462 }
7463
7464 return get_stat64(&hw_stats->rx_fcs_errors);
7465}
7466
7467#define ESTAT_ADD(member) \
7468 estats->member = old_estats->member + \
7469 get_stat64(&hw_stats->member)
7470
7471static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7472{
7473 struct tg3_ethtool_stats *estats = &tp->estats;
7474 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7475 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7476
7477 if (!hw_stats)
7478 return old_estats;
7479
7480 ESTAT_ADD(rx_octets);
7481 ESTAT_ADD(rx_fragments);
7482 ESTAT_ADD(rx_ucast_packets);
7483 ESTAT_ADD(rx_mcast_packets);
7484 ESTAT_ADD(rx_bcast_packets);
7485 ESTAT_ADD(rx_fcs_errors);
7486 ESTAT_ADD(rx_align_errors);
7487 ESTAT_ADD(rx_xon_pause_rcvd);
7488 ESTAT_ADD(rx_xoff_pause_rcvd);
7489 ESTAT_ADD(rx_mac_ctrl_rcvd);
7490 ESTAT_ADD(rx_xoff_entered);
7491 ESTAT_ADD(rx_frame_too_long_errors);
7492 ESTAT_ADD(rx_jabbers);
7493 ESTAT_ADD(rx_undersize_packets);
7494 ESTAT_ADD(rx_in_length_errors);
7495 ESTAT_ADD(rx_out_length_errors);
7496 ESTAT_ADD(rx_64_or_less_octet_packets);
7497 ESTAT_ADD(rx_65_to_127_octet_packets);
7498 ESTAT_ADD(rx_128_to_255_octet_packets);
7499 ESTAT_ADD(rx_256_to_511_octet_packets);
7500 ESTAT_ADD(rx_512_to_1023_octet_packets);
7501 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7502 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7503 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7504 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7505 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7506
7507 ESTAT_ADD(tx_octets);
7508 ESTAT_ADD(tx_collisions);
7509 ESTAT_ADD(tx_xon_sent);
7510 ESTAT_ADD(tx_xoff_sent);
7511 ESTAT_ADD(tx_flow_control);
7512 ESTAT_ADD(tx_mac_errors);
7513 ESTAT_ADD(tx_single_collisions);
7514 ESTAT_ADD(tx_mult_collisions);
7515 ESTAT_ADD(tx_deferred);
7516 ESTAT_ADD(tx_excessive_collisions);
7517 ESTAT_ADD(tx_late_collisions);
7518 ESTAT_ADD(tx_collide_2times);
7519 ESTAT_ADD(tx_collide_3times);
7520 ESTAT_ADD(tx_collide_4times);
7521 ESTAT_ADD(tx_collide_5times);
7522 ESTAT_ADD(tx_collide_6times);
7523 ESTAT_ADD(tx_collide_7times);
7524 ESTAT_ADD(tx_collide_8times);
7525 ESTAT_ADD(tx_collide_9times);
7526 ESTAT_ADD(tx_collide_10times);
7527 ESTAT_ADD(tx_collide_11times);
7528 ESTAT_ADD(tx_collide_12times);
7529 ESTAT_ADD(tx_collide_13times);
7530 ESTAT_ADD(tx_collide_14times);
7531 ESTAT_ADD(tx_collide_15times);
7532 ESTAT_ADD(tx_ucast_packets);
7533 ESTAT_ADD(tx_mcast_packets);
7534 ESTAT_ADD(tx_bcast_packets);
7535 ESTAT_ADD(tx_carrier_sense_errors);
7536 ESTAT_ADD(tx_discards);
7537 ESTAT_ADD(tx_errors);
7538
7539 ESTAT_ADD(dma_writeq_full);
7540 ESTAT_ADD(dma_write_prioq_full);
7541 ESTAT_ADD(rxbds_empty);
7542 ESTAT_ADD(rx_discards);
7543 ESTAT_ADD(rx_errors);
7544 ESTAT_ADD(rx_threshold_hit);
7545
7546 ESTAT_ADD(dma_readq_full);
7547 ESTAT_ADD(dma_read_prioq_full);
7548 ESTAT_ADD(tx_comp_queue_full);
7549
7550 ESTAT_ADD(ring_set_send_prod_index);
7551 ESTAT_ADD(ring_status_update);
7552 ESTAT_ADD(nic_irqs);
7553 ESTAT_ADD(nic_avoided_irqs);
7554 ESTAT_ADD(nic_tx_threshold_hit);
7555
7556 return estats;
7557}
7558
7559static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7560{
7561 struct tg3 *tp = netdev_priv(dev);
7562 struct net_device_stats *stats = &tp->net_stats;
7563 struct net_device_stats *old_stats = &tp->net_stats_prev;
7564 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7565
7566 if (!hw_stats)
7567 return old_stats;
7568
7569 stats->rx_packets = old_stats->rx_packets +
7570 get_stat64(&hw_stats->rx_ucast_packets) +
7571 get_stat64(&hw_stats->rx_mcast_packets) +
7572 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 7573
1da177e4
LT		 7574 stats->tx_packets = old_stats->tx_packets +
7575 get_stat64(&hw_stats->tx_ucast_packets) +
7576 get_stat64(&hw_stats->tx_mcast_packets) +
7577 get_stat64(&hw_stats->tx_bcast_packets);
7578
7579 stats->rx_bytes = old_stats->rx_bytes +
7580 get_stat64(&hw_stats->rx_octets);
7581 stats->tx_bytes = old_stats->tx_bytes +
7582 get_stat64(&hw_stats->tx_octets);
7583
7584 stats->rx_errors = old_stats->rx_errors +
4f63b877 7585 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 7586 stats->tx_errors = old_stats->tx_errors +
7587 get_stat64(&hw_stats->tx_errors) +
7588 get_stat64(&hw_stats->tx_mac_errors) +
7589 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7590 get_stat64(&hw_stats->tx_discards);
7591
7592 stats->multicast = old_stats->multicast +
7593 get_stat64(&hw_stats->rx_mcast_packets);
7594 stats->collisions = old_stats->collisions +
7595 get_stat64(&hw_stats->tx_collisions);
7596
7597 stats->rx_length_errors = old_stats->rx_length_errors +
7598 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7599 get_stat64(&hw_stats->rx_undersize_packets);
7600
7601 stats->rx_over_errors = old_stats->rx_over_errors +
7602 get_stat64(&hw_stats->rxbds_empty);
7603 stats->rx_frame_errors = old_stats->rx_frame_errors +
7604 get_stat64(&hw_stats->rx_align_errors);
7605 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7606 get_stat64(&hw_stats->tx_discards);
7607 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7608 get_stat64(&hw_stats->tx_carrier_sense_errors);
7609
7610 stats->rx_crc_errors = old_stats->rx_crc_errors +
7611 calc_crc_errors(tp);
7612
4f63b877
JL		 7613 stats->rx_missed_errors = old_stats->rx_missed_errors +
7614 get_stat64(&hw_stats->rx_discards);
7615
1da177e4
LT		 7616 return stats;
7617}
7618
7619static inline u32 calc_crc(unsigned char *buf, int len)
7620{
7621 u32 reg;
7622 u32 tmp;
7623 int j, k;
7624
7625 reg = 0xffffffff;
7626
7627 for (j = 0; j < len; j++) {
7628 reg ^= buf[j];
7629
7630 for (k = 0; k < 8; k++) {
7631 tmp = reg & 0x01;
7632
7633 reg >>= 1;
7634
7635 if (tmp) {
7636 reg ^= 0xedb88320;
7637 }
7638 }
7639 }
7640
7641 return ~reg;
7642}
7643
7644static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7645{
7646 /* accept or reject all multicast frames */
7647 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7648 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7649 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7650 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7651}
7652
7653static void __tg3_set_rx_mode(struct net_device *dev)
7654{
7655 struct tg3 *tp = netdev_priv(dev);
7656 u32 rx_mode;
7657
7658 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7659 RX_MODE_KEEP_VLAN_TAG);
7660
7661 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7662 * flag clear.
7663 */
7664#if TG3_VLAN_TAG_USED
7665 if (!tp->vlgrp &&
7666 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7667 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7668#else
7669 /* By definition, VLAN is disabled always in this
7670 * case.
7671 */
7672 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7673 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7674#endif
7675
7676 if (dev->flags & IFF_PROMISC) {
7677 /* Promiscuous mode. */
7678 rx_mode |= RX_MODE_PROMISC;
7679 } else if (dev->flags & IFF_ALLMULTI) {
7680 /* Accept all multicast. */
7681 tg3_set_multi (tp, 1);
7682 } else if (dev->mc_count < 1) {
7683 /* Reject all multicast. */
7684 tg3_set_multi (tp, 0);
7685 } else {
7686 /* Accept one or more multicast(s). */
7687 struct dev_mc_list *mclist;
7688 unsigned int i;
7689 u32 mc_filter[4] = { 0, };
7690 u32 regidx;
7691 u32 bit;
7692 u32 crc;
7693
7694 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7695 i++, mclist = mclist->next) {
7696
7697 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7698 bit = ~crc & 0x7f;
7699 regidx = (bit & 0x60) >> 5;
7700 bit &= 0x1f;
7701 mc_filter[regidx] |= (1 << bit);
7702 }
7703
7704 tw32(MAC_HASH_REG_0, mc_filter[0]);
7705 tw32(MAC_HASH_REG_1, mc_filter[1]);
7706 tw32(MAC_HASH_REG_2, mc_filter[2]);
7707 tw32(MAC_HASH_REG_3, mc_filter[3]);
7708 }
7709
7710 if (rx_mode != tp->rx_mode) {
7711 tp->rx_mode = rx_mode;
7712 tw32_f(MAC_RX_MODE, rx_mode);
7713 udelay(10);
7714 }
7715}
7716
7717static void tg3_set_rx_mode(struct net_device *dev)
7718{
7719 struct tg3 *tp = netdev_priv(dev);
7720
e75f7c90
MC		 7721 if (!netif_running(dev))
7722 return;
7723
f47c11ee 7724 tg3_full_lock(tp, 0);
1da177e4 7725 __tg3_set_rx_mode(dev);
f47c11ee 7726 tg3_full_unlock(tp);
1da177e4
LT		 7727}
7728
7729#define TG3_REGDUMP_LEN (32 * 1024)
7730
7731static int tg3_get_regs_len(struct net_device *dev)
7732{
7733 return TG3_REGDUMP_LEN;
7734}
7735
7736static void tg3_get_regs(struct net_device *dev,
7737 struct ethtool_regs *regs, void *_p)
7738{
7739 u32 *p = _p;
7740 struct tg3 *tp = netdev_priv(dev);
7741 u8 *orig_p = _p;
7742 int i;
7743
7744 regs->version = 0;
7745
7746 memset(p, 0, TG3_REGDUMP_LEN);
7747
bc1c7567
MC		 7748 if (tp->link_config.phy_is_low_power)
7749 return;
7750
f47c11ee 7751 tg3_full_lock(tp, 0);
1da177e4
LT		 7752
7753#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7754#define GET_REG32_LOOP(base,len) \
7755do { p = (u32 *)(orig_p + (base)); \
7756 for (i = 0; i < len; i += 4) \
7757 __GET_REG32((base) + i); \
7758} while (0)
7759#define GET_REG32_1(reg) \
7760do { p = (u32 *)(orig_p + (reg)); \
7761 __GET_REG32((reg)); \
7762} while (0)
7763
7764 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7765 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7766 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7767 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7768 GET_REG32_1(SNDDATAC_MODE);
7769 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7770 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7771 GET_REG32_1(SNDBDC_MODE);
7772 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7773 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7774 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7775 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7776 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7777 GET_REG32_1(RCVDCC_MODE);
7778 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7779 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7780 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7781 GET_REG32_1(MBFREE_MODE);
7782 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7783 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7784 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7785 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7786 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 7787 GET_REG32_1(RX_CPU_MODE);
7788 GET_REG32_1(RX_CPU_STATE);
7789 GET_REG32_1(RX_CPU_PGMCTR);
7790 GET_REG32_1(RX_CPU_HWBKPT);
7791 GET_REG32_1(TX_CPU_MODE);
7792 GET_REG32_1(TX_CPU_STATE);
7793 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 7794 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7795 GET_REG32_LOOP(FTQ_RESET, 0x120);
7796 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7797 GET_REG32_1(DMAC_MODE);
7798 GET_REG32_LOOP(GRC_MODE, 0x4c);
7799 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7800 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7801
7802#undef __GET_REG32
7803#undef GET_REG32_LOOP
7804#undef GET_REG32_1
7805
f47c11ee 7806 tg3_full_unlock(tp);
1da177e4
LT		 7807}
7808
7809static int tg3_get_eeprom_len(struct net_device *dev)
7810{
7811 struct tg3 *tp = netdev_priv(dev);
7812
7813 return tp->nvram_size;
7814}
7815
7816static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
1820180b 7817static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 7818
7819static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7820{
7821 struct tg3 *tp = netdev_priv(dev);
7822 int ret;
7823 u8 *pd;
7824 u32 i, offset, len, val, b_offset, b_count;
7825
bc1c7567
MC		 7826 if (tp->link_config.phy_is_low_power)
7827 return -EAGAIN;
7828
1da177e4
LT		 7829 offset = eeprom->offset;
7830 len = eeprom->len;
7831 eeprom->len = 0;
7832
7833 eeprom->magic = TG3_EEPROM_MAGIC;
7834
7835 if (offset & 3) {
7836 /* adjustments to start on required 4 byte boundary */
7837 b_offset = offset & 3;
7838 b_count = 4 - b_offset;
7839 if (b_count > len) {
7840 /* i.e. offset=1 len=2 */
7841 b_count = len;
7842 }
7843 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7844 if (ret)
7845 return ret;
7846 val = cpu_to_le32(val);
7847 memcpy(data, ((char*)&val) + b_offset, b_count);
7848 len -= b_count;
7849 offset += b_count;
7850 eeprom->len += b_count;
7851 }
7852
7853 /* read bytes upto the last 4 byte boundary */
7854 pd = &data[eeprom->len];
7855 for (i = 0; i < (len - (len & 3)); i += 4) {
7856 ret = tg3_nvram_read(tp, offset + i, &val);
7857 if (ret) {
7858 eeprom->len += i;
7859 return ret;
7860 }
7861 val = cpu_to_le32(val);
7862 memcpy(pd + i, &val, 4);
7863 }
7864 eeprom->len += i;
7865
7866 if (len & 3) {
7867 /* read last bytes not ending on 4 byte boundary */
7868 pd = &data[eeprom->len];
7869 b_count = len & 3;
7870 b_offset = offset + len - b_count;
7871 ret = tg3_nvram_read(tp, b_offset, &val);
7872 if (ret)
7873 return ret;
7874 val = cpu_to_le32(val);
7875 memcpy(pd, ((char*)&val), b_count);
7876 eeprom->len += b_count;
7877 }
7878 return 0;
7879}
7880
6aa20a22 7881static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 7882
7883static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7884{
7885 struct tg3 *tp = netdev_priv(dev);
7886 int ret;
7887 u32 offset, len, b_offset, odd_len, start, end;
7888 u8 *buf;
7889
bc1c7567
MC		 7890 if (tp->link_config.phy_is_low_power)
7891 return -EAGAIN;
7892
1da177e4
LT		 7893 if (eeprom->magic != TG3_EEPROM_MAGIC)
7894 return -EINVAL;
7895
7896 offset = eeprom->offset;
7897 len = eeprom->len;
7898
7899 if ((b_offset = (offset & 3))) {
7900 /* adjustments to start on required 4 byte boundary */
7901 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7902 if (ret)
7903 return ret;
7904 start = cpu_to_le32(start);
7905 len += b_offset;
7906 offset &= ~3;
1c8594b4
MC		 7907 if (len < 4)
7908 len = 4;
1da177e4
LT		 7909 }
7910
7911 odd_len = 0;
1c8594b4 7912 if (len & 3) {
1da177e4
LT		 7913 /* adjustments to end on required 4 byte boundary */
7914 odd_len = 1;
7915 len = (len + 3) & ~3;
7916 ret = tg3_nvram_read(tp, offset+len-4, &end);
7917 if (ret)
7918 return ret;
7919 end = cpu_to_le32(end);
7920 }
7921
7922 buf = data;
7923 if (b_offset || odd_len) {
7924 buf = kmalloc(len, GFP_KERNEL);
7925 if (buf == 0)
7926 return -ENOMEM;
7927 if (b_offset)
7928 memcpy(buf, &start, 4);
7929 if (odd_len)
7930 memcpy(buf+len-4, &end, 4);
7931 memcpy(buf + b_offset, data, eeprom->len);
7932 }
7933
7934 ret = tg3_nvram_write_block(tp, offset, len, buf);
7935
7936 if (buf != data)
7937 kfree(buf);
7938
7939 return ret;
7940}
7941
7942static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7943{
7944 struct tg3 *tp = netdev_priv(dev);
6aa20a22 7945
1da177e4
LT		 7946 cmd->supported = (SUPPORTED_Autoneg);
7947
7948 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7949 cmd->supported |= (SUPPORTED_1000baseT_Half |
7950 SUPPORTED_1000baseT_Full);
7951
ef348144 7952 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 7953 cmd->supported |= (SUPPORTED_100baseT_Half |
7954 SUPPORTED_100baseT_Full |
7955 SUPPORTED_10baseT_Half |
7956 SUPPORTED_10baseT_Full |
7957 SUPPORTED_MII);
ef348144
KK		 7958 cmd->port = PORT_TP;
7959 } else {
1da177e4 7960 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 7961 cmd->port = PORT_FIBRE;
7962 }
6aa20a22 7963
1da177e4
LT		 7964 cmd->advertising = tp->link_config.advertising;
7965 if (netif_running(dev)) {
7966 cmd->speed = tp->link_config.active_speed;
7967 cmd->duplex = tp->link_config.active_duplex;
7968 }
1da177e4
LT		 7969 cmd->phy_address = PHY_ADDR;
7970 cmd->transceiver = 0;
7971 cmd->autoneg = tp->link_config.autoneg;
7972 cmd->maxtxpkt = 0;
7973 cmd->maxrxpkt = 0;
7974 return 0;
7975}
6aa20a22 7976
1da177e4
LT		 7977static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7978{
7979 struct tg3 *tp = netdev_priv(dev);
6aa20a22
JG		 7980
7981 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
1da177e4
LT		 7982 /* These are the only valid advertisement bits allowed. */
7983 if (cmd->autoneg == AUTONEG_ENABLE &&
7984 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7985 ADVERTISED_1000baseT_Full |
7986 ADVERTISED_Autoneg |
7987 ADVERTISED_FIBRE)))
7988 return -EINVAL;
37ff238d
MC		 7989 /* Fiber can only do SPEED_1000. */
7990 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7991 (cmd->speed != SPEED_1000))
7992 return -EINVAL;
7993 /* Copper cannot force SPEED_1000. */
7994 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7995 (cmd->speed == SPEED_1000))
7996 return -EINVAL;
7997 else if ((cmd->speed == SPEED_1000) &&
7998 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7999 return -EINVAL;
1da177e4 8000
f47c11ee 8001 tg3_full_lock(tp, 0);
1da177e4
LT		 8002
8003 tp->link_config.autoneg = cmd->autoneg;
8004 if (cmd->autoneg == AUTONEG_ENABLE) {
8005 tp->link_config.advertising = cmd->advertising;
8006 tp->link_config.speed = SPEED_INVALID;
8007 tp->link_config.duplex = DUPLEX_INVALID;
8008 } else {
8009 tp->link_config.advertising = 0;
8010 tp->link_config.speed = cmd->speed;
8011 tp->link_config.duplex = cmd->duplex;
8012 }
6aa20a22 8013
24fcad6b
MC		 8014 tp->link_config.orig_speed = tp->link_config.speed;
8015 tp->link_config.orig_duplex = tp->link_config.duplex;
8016 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8017
1da177e4
LT		 8018 if (netif_running(dev))
8019 tg3_setup_phy(tp, 1);
8020
f47c11ee 8021 tg3_full_unlock(tp);
6aa20a22 8022
1da177e4
LT		 8023 return 0;
8024}
6aa20a22 8025
1da177e4
LT		 8026static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8027{
8028 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8029
1da177e4
LT		 8030 strcpy(info->driver, DRV_MODULE_NAME);
8031 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8032 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8033 strcpy(info->bus_info, pci_name(tp->pdev));
8034}
6aa20a22 8035
1da177e4
LT		 8036static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8037{
8038 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8039
a85feb8c
GZ		 8040 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8041 wol->supported = WAKE_MAGIC;
8042 else
8043 wol->supported = 0;
1da177e4
LT		 8044 wol->wolopts = 0;
8045 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8046 wol->wolopts = WAKE_MAGIC;
8047 memset(&wol->sopass, 0, sizeof(wol->sopass));
8048}
6aa20a22 8049
1da177e4
LT		 8050static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8051{
8052 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8053
1da177e4
LT		 8054 if (wol->wolopts & ~WAKE_MAGIC)
8055 return -EINVAL;
8056 if ((wol->wolopts & WAKE_MAGIC) &&
a85feb8c 8057 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
1da177e4 8058 return -EINVAL;
6aa20a22 8059
f47c11ee 8060 spin_lock_bh(&tp->lock);
1da177e4
LT		 8061 if (wol->wolopts & WAKE_MAGIC)
8062 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8063 else
8064 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 8065 spin_unlock_bh(&tp->lock);
6aa20a22 8066
1da177e4
LT		 8067 return 0;
8068}
6aa20a22 8069
1da177e4
LT		 8070static u32 tg3_get_msglevel(struct net_device *dev)
8071{
8072 struct tg3 *tp = netdev_priv(dev);
8073 return tp->msg_enable;
8074}
6aa20a22 8075
1da177e4
LT		 8076static void tg3_set_msglevel(struct net_device *dev, u32 value)
8077{
8078 struct tg3 *tp = netdev_priv(dev);
8079 tp->msg_enable = value;
8080}
6aa20a22 8081
1da177e4
LT		 8082static int tg3_set_tso(struct net_device *dev, u32 value)
8083{
8084 struct tg3 *tp = netdev_priv(dev);
8085
8086 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8087 if (value)
8088 return -EINVAL;
8089 return 0;
8090 }
b5d3772c
MC		 8091 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8092 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
b0026624
MC		 8093 if (value)
8094 dev->features |= NETIF_F_TSO6;
8095 else
8096 dev->features &= ~NETIF_F_TSO6;
8097 }
1da177e4
LT		 8098 return ethtool_op_set_tso(dev, value);
8099}
6aa20a22 8100
1da177e4
LT		 8101static int tg3_nway_reset(struct net_device *dev)
8102{
8103 struct tg3 *tp = netdev_priv(dev);
8104 u32 bmcr;
8105 int r;
6aa20a22 8106
1da177e4
LT		 8107 if (!netif_running(dev))
8108 return -EAGAIN;
8109
c94e3941
MC		 8110 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8111 return -EINVAL;
8112
f47c11ee 8113 spin_lock_bh(&tp->lock);
1da177e4
LT		 8114 r = -EINVAL;
8115 tg3_readphy(tp, MII_BMCR, &bmcr);
8116 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
c94e3941
MC		 8117 ((bmcr & BMCR_ANENABLE) ||
8118 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8119 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8120 BMCR_ANENABLE);
1da177e4
LT		 8121 r = 0;
8122 }
f47c11ee 8123 spin_unlock_bh(&tp->lock);
6aa20a22 8124
1da177e4
LT		 8125 return r;
8126}
6aa20a22 8127
1da177e4
LT		 8128static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8129{
8130 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8131
1da177e4
LT		 8132 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8133 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8134 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8135 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8136 else
8137 ering->rx_jumbo_max_pending = 0;
8138
8139 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8140
8141 ering->rx_pending = tp->rx_pending;
8142 ering->rx_mini_pending = 0;
4f81c32b
MC		 8143 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8144 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8145 else
8146 ering->rx_jumbo_pending = 0;
8147
1da177e4
LT		 8148 ering->tx_pending = tp->tx_pending;
8149}
6aa20a22 8150
1da177e4
LT		 8151static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8152{
8153 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8154 int irq_sync = 0, err = 0;
6aa20a22 8155
1da177e4
LT		 8156 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8157 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8158 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8159 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8160 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8161 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8162 return -EINVAL;
6aa20a22 8163
bbe832c0 8164 if (netif_running(dev)) {
1da177e4 8165 tg3_netif_stop(tp);
bbe832c0
MC		 8166 irq_sync = 1;
8167 }
1da177e4 8168
bbe832c0 8169 tg3_full_lock(tp, irq_sync);
6aa20a22 8170
1da177e4
LT		 8171 tp->rx_pending = ering->rx_pending;
8172
8173 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8174 tp->rx_pending > 63)
8175 tp->rx_pending = 63;
8176 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8177 tp->tx_pending = ering->tx_pending;
8178
8179 if (netif_running(dev)) {
944d980e 8180 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8181 err = tg3_restart_hw(tp, 1);
8182 if (!err)
8183 tg3_netif_start(tp);
1da177e4
LT		 8184 }
8185
f47c11ee 8186 tg3_full_unlock(tp);
6aa20a22 8187
b9ec6c1b 8188 return err;
1da177e4 8189}
6aa20a22 8190
1da177e4
LT		 8191static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8192{
8193 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8194
1da177e4
LT		 8195 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8196 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8197 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8198}
6aa20a22 8199
1da177e4
LT		 8200static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8201{
8202 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8203 int irq_sync = 0, err = 0;
6aa20a22 8204
bbe832c0 8205 if (netif_running(dev)) {
1da177e4 8206 tg3_netif_stop(tp);
bbe832c0
MC		 8207 irq_sync = 1;
8208 }
1da177e4 8209
bbe832c0 8210 tg3_full_lock(tp, irq_sync);
f47c11ee 8211
1da177e4
LT		 8212 if (epause->autoneg)
8213 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8214 else
8215 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8216 if (epause->rx_pause)
8217 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8218 else
8219 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8220 if (epause->tx_pause)
8221 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8222 else
8223 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8224
8225 if (netif_running(dev)) {
944d980e 8226 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8227 err = tg3_restart_hw(tp, 1);
8228 if (!err)
8229 tg3_netif_start(tp);
1da177e4 8230 }
f47c11ee
DM		 8231
8232 tg3_full_unlock(tp);
6aa20a22 8233
b9ec6c1b 8234 return err;
1da177e4 8235}
6aa20a22 8236
1da177e4
LT		 8237static u32 tg3_get_rx_csum(struct net_device *dev)
8238{
8239 struct tg3 *tp = netdev_priv(dev);
8240 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8241}
6aa20a22 8242
1da177e4
LT		 8243static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8244{
8245 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8246
1da177e4
LT		 8247 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8248 if (data != 0)
8249 return -EINVAL;
8250 return 0;
8251 }
6aa20a22 8252
f47c11ee 8253 spin_lock_bh(&tp->lock);
1da177e4
LT		 8254 if (data)
8255 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8256 else
8257 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8258 spin_unlock_bh(&tp->lock);
6aa20a22 8259
1da177e4
LT		 8260 return 0;
8261}
6aa20a22 8262
1da177e4
LT		 8263static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8264{
8265 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8266
1da177e4
LT		 8267 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8268 if (data != 0)
8269 return -EINVAL;
8270 return 0;
8271 }
6aa20a22 8272
af36e6b6
MC		 8273 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8274 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf 8275 ethtool_op_set_tx_hw_csum(dev, data);
1da177e4 8276 else
9c27dbdf 8277 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8278
8279 return 0;
8280}
8281
8282static int tg3_get_stats_count (struct net_device *dev)
8283{
8284 return TG3_NUM_STATS;
8285}
8286
4cafd3f5
MC		 8287static int tg3_get_test_count (struct net_device *dev)
8288{
8289 return TG3_NUM_TEST;
8290}
8291
1da177e4
LT		 8292static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8293{
8294 switch (stringset) {
8295 case ETH_SS_STATS:
8296 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8297 break;
4cafd3f5
MC		 8298 case ETH_SS_TEST:
8299 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8300 break;
1da177e4
LT		 8301 default:
8302 WARN_ON(1); /* we need a WARN() */
8303 break;
8304 }
8305}
8306
4009a93d
MC		 8307static int tg3_phys_id(struct net_device *dev, u32 data)
8308{
8309 struct tg3 *tp = netdev_priv(dev);
8310 int i;
8311
8312 if (!netif_running(tp->dev))
8313 return -EAGAIN;
8314
8315 if (data == 0)
8316 data = 2;
8317
8318 for (i = 0; i < (data * 2); i++) {
8319 if ((i % 2) == 0)
8320 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8321 LED_CTRL_1000MBPS_ON |
8322 LED_CTRL_100MBPS_ON |
8323 LED_CTRL_10MBPS_ON |
8324 LED_CTRL_TRAFFIC_OVERRIDE |
8325 LED_CTRL_TRAFFIC_BLINK |
8326 LED_CTRL_TRAFFIC_LED);
6aa20a22 8327
4009a93d
MC		 8328 else
8329 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8330 LED_CTRL_TRAFFIC_OVERRIDE);
8331
8332 if (msleep_interruptible(500))
8333 break;
8334 }
8335 tw32(MAC_LED_CTRL, tp->led_ctrl);
8336 return 0;
8337}
8338
1da177e4
LT		 8339static void tg3_get_ethtool_stats (struct net_device *dev,
8340 struct ethtool_stats *estats, u64 *tmp_stats)
8341{
8342 struct tg3 *tp = netdev_priv(dev);
8343 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8344}
8345
566f86ad 8346#define NVRAM_TEST_SIZE 0x100
1b27777a 8347#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
b16250e3
MC		 8348#define NVRAM_SELFBOOT_HW_SIZE 0x20
8349#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 8350
8351static int tg3_test_nvram(struct tg3 *tp)
8352{
1b27777a
MC		 8353 u32 *buf, csum, magic;
8354 int i, j, err = 0, size;
566f86ad 8355
1820180b 8356 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 8357 return -EIO;
8358
1b27777a
MC		 8359 if (magic == TG3_EEPROM_MAGIC)
8360 size = NVRAM_TEST_SIZE;
b16250e3 8361 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8362 if ((magic & 0xe00000) == 0x200000)
8363 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8364 else
8365 return 0;
b16250e3
MC		 8366 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8367 size = NVRAM_SELFBOOT_HW_SIZE;
8368 else
1b27777a
MC		 8369 return -EIO;
8370
8371 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 8372 if (buf == NULL)
8373 return -ENOMEM;
8374
1b27777a
MC		 8375 err = -EIO;
8376 for (i = 0, j = 0; i < size; i += 4, j++) {
566f86ad
MC		 8377 u32 val;
8378
8379 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8380 break;
8381 buf[j] = cpu_to_le32(val);
8382 }
1b27777a 8383 if (i < size)
566f86ad
MC		 8384 goto out;
8385
1b27777a 8386 /* Selfboot format */
b16250e3
MC		 8387 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8388 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 8389 u8 *buf8 = (u8 *) buf, csum8 = 0;
8390
8391 for (i = 0; i < size; i++)
8392 csum8 += buf8[i];
8393
ad96b485
AB		 8394 if (csum8 == 0) {
8395 err = 0;
8396 goto out;
8397 }
8398
8399 err = -EIO;
8400 goto out;
1b27777a 8401 }
566f86ad 8402
b16250e3
MC		 8403 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8404 TG3_EEPROM_MAGIC_HW) {
8405 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8406 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8407 u8 *buf8 = (u8 *) buf;
8408 int j, k;
8409
8410 /* Separate the parity bits and the data bytes. */
8411 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8412 if ((i == 0) || (i == 8)) {
8413 int l;
8414 u8 msk;
8415
8416 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8417 parity[k++] = buf8[i] & msk;
8418 i++;
8419 }
8420 else if (i == 16) {
8421 int l;
8422 u8 msk;
8423
8424 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8425 parity[k++] = buf8[i] & msk;
8426 i++;
8427
8428 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8429 parity[k++] = buf8[i] & msk;
8430 i++;
8431 }
8432 data[j++] = buf8[i];
8433 }
8434
8435 err = -EIO;
8436 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8437 u8 hw8 = hweight8(data[i]);
8438
8439 if ((hw8 & 0x1) && parity[i])
8440 goto out;
8441 else if (!(hw8 & 0x1) && !parity[i])
8442 goto out;
8443 }
8444 err = 0;
8445 goto out;
8446 }
8447
566f86ad
MC		 8448 /* Bootstrap checksum at offset 0x10 */
8449 csum = calc_crc((unsigned char *) buf, 0x10);
8450 if(csum != cpu_to_le32(buf[0x10/4]))
8451 goto out;
8452
8453 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8454 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8455 if (csum != cpu_to_le32(buf[0xfc/4]))
8456 goto out;
8457
8458 err = 0;
8459
8460out:
8461 kfree(buf);
8462 return err;
8463}
8464
ca43007a
MC		 8465#define TG3_SERDES_TIMEOUT_SEC 2
8466#define TG3_COPPER_TIMEOUT_SEC 6
8467
8468static int tg3_test_link(struct tg3 *tp)
8469{
8470 int i, max;
8471
8472 if (!netif_running(tp->dev))
8473 return -ENODEV;
8474
4c987487 8475 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 8476 max = TG3_SERDES_TIMEOUT_SEC;
8477 else
8478 max = TG3_COPPER_TIMEOUT_SEC;
8479
8480 for (i = 0; i < max; i++) {
8481 if (netif_carrier_ok(tp->dev))
8482 return 0;
8483
8484 if (msleep_interruptible(1000))
8485 break;
8486 }
8487
8488 return -EIO;
8489}
8490
a71116d1 8491/* Only test the commonly used registers */
30ca3e37 8492static int tg3_test_registers(struct tg3 *tp)
a71116d1 8493{
b16250e3 8494 int i, is_5705, is_5750;
a71116d1
MC		 8495 u32 offset, read_mask, write_mask, val, save_val, read_val;
8496 static struct {
8497 u16 offset;
8498 u16 flags;
8499#define TG3_FL_5705 0x1
8500#define TG3_FL_NOT_5705 0x2
8501#define TG3_FL_NOT_5788 0x4
b16250e3 8502#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 8503 u32 read_mask;
8504 u32 write_mask;
8505 } reg_tbl[] = {
8506 /* MAC Control Registers */
8507 { MAC_MODE, TG3_FL_NOT_5705,
8508 0x00000000, 0x00ef6f8c },
8509 { MAC_MODE, TG3_FL_5705,
8510 0x00000000, 0x01ef6b8c },
8511 { MAC_STATUS, TG3_FL_NOT_5705,
8512 0x03800107, 0x00000000 },
8513 { MAC_STATUS, TG3_FL_5705,
8514 0x03800100, 0x00000000 },
8515 { MAC_ADDR_0_HIGH, 0x0000,
8516 0x00000000, 0x0000ffff },
8517 { MAC_ADDR_0_LOW, 0x0000,
8518 0x00000000, 0xffffffff },
8519 { MAC_RX_MTU_SIZE, 0x0000,
8520 0x00000000, 0x0000ffff },
8521 { MAC_TX_MODE, 0x0000,
8522 0x00000000, 0x00000070 },
8523 { MAC_TX_LENGTHS, 0x0000,
8524 0x00000000, 0x00003fff },
8525 { MAC_RX_MODE, TG3_FL_NOT_5705,
8526 0x00000000, 0x000007fc },
8527 { MAC_RX_MODE, TG3_FL_5705,
8528 0x00000000, 0x000007dc },
8529 { MAC_HASH_REG_0, 0x0000,
8530 0x00000000, 0xffffffff },
8531 { MAC_HASH_REG_1, 0x0000,
8532 0x00000000, 0xffffffff },
8533 { MAC_HASH_REG_2, 0x0000,
8534 0x00000000, 0xffffffff },
8535 { MAC_HASH_REG_3, 0x0000,
8536 0x00000000, 0xffffffff },
8537
8538 /* Receive Data and Receive BD Initiator Control Registers. */
8539 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8540 0x00000000, 0xffffffff },
8541 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8542 0x00000000, 0xffffffff },
8543 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8544 0x00000000, 0x00000003 },
8545 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8546 0x00000000, 0xffffffff },
8547 { RCVDBDI_STD_BD+0, 0x0000,
8548 0x00000000, 0xffffffff },
8549 { RCVDBDI_STD_BD+4, 0x0000,
8550 0x00000000, 0xffffffff },
8551 { RCVDBDI_STD_BD+8, 0x0000,
8552 0x00000000, 0xffff0002 },
8553 { RCVDBDI_STD_BD+0xc, 0x0000,
8554 0x00000000, 0xffffffff },
6aa20a22 8555
a71116d1
MC		 8556 /* Receive BD Initiator Control Registers. */
8557 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8558 0x00000000, 0xffffffff },
8559 { RCVBDI_STD_THRESH, TG3_FL_5705,
8560 0x00000000, 0x000003ff },
8561 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8562 0x00000000, 0xffffffff },
6aa20a22 8563
a71116d1
MC		 8564 /* Host Coalescing Control Registers. */
8565 { HOSTCC_MODE, TG3_FL_NOT_5705,
8566 0x00000000, 0x00000004 },
8567 { HOSTCC_MODE, TG3_FL_5705,
8568 0x00000000, 0x000000f6 },
8569 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8570 0x00000000, 0xffffffff },
8571 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8572 0x00000000, 0x000003ff },
8573 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8574 0x00000000, 0xffffffff },
8575 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8576 0x00000000, 0x000003ff },
8577 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8578 0x00000000, 0xffffffff },
8579 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8580 0x00000000, 0x000000ff },
8581 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8582 0x00000000, 0xffffffff },
8583 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8584 0x00000000, 0x000000ff },
8585 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8586 0x00000000, 0xffffffff },
8587 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8588 0x00000000, 0xffffffff },
8589 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8590 0x00000000, 0xffffffff },
8591 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8592 0x00000000, 0x000000ff },
8593 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8594 0x00000000, 0xffffffff },
8595 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8596 0x00000000, 0x000000ff },
8597 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8598 0x00000000, 0xffffffff },
8599 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8600 0x00000000, 0xffffffff },
8601 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8602 0x00000000, 0xffffffff },
8603 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8604 0x00000000, 0xffffffff },
8605 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8606 0x00000000, 0xffffffff },
8607 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8608 0xffffffff, 0x00000000 },
8609 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8610 0xffffffff, 0x00000000 },
8611
8612 /* Buffer Manager Control Registers. */
b16250e3 8613 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 8614 0x00000000, 0x007fff80 },
b16250e3 8615 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 8616 0x00000000, 0x007fffff },
8617 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8618 0x00000000, 0x0000003f },
8619 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8620 0x00000000, 0x000001ff },
8621 { BUFMGR_MB_HIGH_WATER, 0x0000,
8622 0x00000000, 0x000001ff },
8623 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8624 0xffffffff, 0x00000000 },
8625 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8626 0xffffffff, 0x00000000 },
6aa20a22 8627
a71116d1
MC		 8628 /* Mailbox Registers */
8629 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8630 0x00000000, 0x000001ff },
8631 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8632 0x00000000, 0x000001ff },
8633 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8634 0x00000000, 0x000007ff },
8635 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8636 0x00000000, 0x000001ff },
8637
8638 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8639 };
8640
b16250e3
MC		 8641 is_5705 = is_5750 = 0;
8642 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 8643 is_5705 = 1;
b16250e3
MC		 8644 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8645 is_5750 = 1;
8646 }
a71116d1
MC		 8647
8648 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8649 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8650 continue;
8651
8652 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8653 continue;
8654
8655 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8656 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8657 continue;
8658
b16250e3
MC		 8659 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8660 continue;
8661
a71116d1
MC		 8662 offset = (u32) reg_tbl[i].offset;
8663 read_mask = reg_tbl[i].read_mask;
8664 write_mask = reg_tbl[i].write_mask;
8665
8666 /* Save the original register content */
8667 save_val = tr32(offset);
8668
8669 /* Determine the read-only value. */
8670 read_val = save_val & read_mask;
8671
8672 /* Write zero to the register, then make sure the read-only bits
8673 * are not changed and the read/write bits are all zeros.
8674 */
8675 tw32(offset, 0);
8676
8677 val = tr32(offset);
8678
8679 /* Test the read-only and read/write bits. */
8680 if (((val & read_mask) != read_val) || (val & write_mask))
8681 goto out;
8682
8683 /* Write ones to all the bits defined by RdMask and WrMask, then
8684 * make sure the read-only bits are not changed and the
8685 * read/write bits are all ones.
8686 */
8687 tw32(offset, read_mask | write_mask);
8688
8689 val = tr32(offset);
8690
8691 /* Test the read-only bits. */
8692 if ((val & read_mask) != read_val)
8693 goto out;
8694
8695 /* Test the read/write bits. */
8696 if ((val & write_mask) != write_mask)
8697 goto out;
8698
8699 tw32(offset, save_val);
8700 }
8701
8702 return 0;
8703
8704out:
9f88f29f
MC		 8705 if (netif_msg_hw(tp))
8706 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8707 offset);
a71116d1
MC		 8708 tw32(offset, save_val);
8709 return -EIO;
8710}
8711
7942e1db
MC		 8712static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8713{
f71e1309 8714 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 8715 int i;
8716 u32 j;
8717
8718 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8719 for (j = 0; j < len; j += 4) {
8720 u32 val;
8721
8722 tg3_write_mem(tp, offset + j, test_pattern[i]);
8723 tg3_read_mem(tp, offset + j, &val);
8724 if (val != test_pattern[i])
8725 return -EIO;
8726 }
8727 }
8728 return 0;
8729}
8730
8731static int tg3_test_memory(struct tg3 *tp)
8732{
8733 static struct mem_entry {
8734 u32 offset;
8735 u32 len;
8736 } mem_tbl_570x[] = {
38690194 8737 { 0x00000000, 0x00b50},
7942e1db
MC		 8738 { 0x00002000, 0x1c000},
8739 { 0xffffffff, 0x00000}
8740 }, mem_tbl_5705[] = {
8741 { 0x00000100, 0x0000c},
8742 { 0x00000200, 0x00008},
7942e1db
MC		 8743 { 0x00004000, 0x00800},
8744 { 0x00006000, 0x01000},
8745 { 0x00008000, 0x02000},
8746 { 0x00010000, 0x0e000},
8747 { 0xffffffff, 0x00000}
79f4d13a
MC		 8748 }, mem_tbl_5755[] = {
8749 { 0x00000200, 0x00008},
8750 { 0x00004000, 0x00800},
8751 { 0x00006000, 0x00800},
8752 { 0x00008000, 0x02000},
8753 { 0x00010000, 0x0c000},
8754 { 0xffffffff, 0x00000}
b16250e3
MC		 8755 }, mem_tbl_5906[] = {
8756 { 0x00000200, 0x00008},
8757 { 0x00004000, 0x00400},
8758 { 0x00006000, 0x00400},
8759 { 0x00008000, 0x01000},
8760 { 0x00010000, 0x01000},
8761 { 0xffffffff, 0x00000}
7942e1db
MC		 8762 };
8763 struct mem_entry *mem_tbl;
8764 int err = 0;
8765 int i;
8766
79f4d13a 8767 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
af36e6b6
MC		 8768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8769 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
79f4d13a 8770 mem_tbl = mem_tbl_5755;
b16250e3
MC		 8771 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8772 mem_tbl = mem_tbl_5906;
79f4d13a
MC		 8773 else
8774 mem_tbl = mem_tbl_5705;
8775 } else
7942e1db
MC		 8776 mem_tbl = mem_tbl_570x;
8777
8778 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8779 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8780 mem_tbl[i].len)) != 0)
8781 break;
8782 }
6aa20a22 8783
7942e1db
MC		 8784 return err;
8785}
8786
9f40dead
MC		 8787#define TG3_MAC_LOOPBACK 0
8788#define TG3_PHY_LOOPBACK 1
8789
8790static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 8791{
9f40dead 8792 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 8793 u32 desc_idx;
8794 struct sk_buff *skb, *rx_skb;
8795 u8 *tx_data;
8796 dma_addr_t map;
8797 int num_pkts, tx_len, rx_len, i, err;
8798 struct tg3_rx_buffer_desc *desc;
8799
9f40dead 8800 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 8801 /* HW errata - mac loopback fails in some cases on 5780.
8802 * Normal traffic and PHY loopback are not affected by
8803 * errata.
8804 */
8805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8806 return 0;
8807
9f40dead 8808 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
3f7045c1
MC		 8809 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8810 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8811 mac_mode |= MAC_MODE_PORT_MODE_MII;
8812 else
8813 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 8814 tw32(MAC_MODE, mac_mode);
8815 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 8816 u32 val;
8817
b16250e3
MC		 8818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8819 u32 phytest;
8820
8821 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8822 u32 phy;
8823
8824 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8825 phytest | MII_TG3_EPHY_SHADOW_EN);
8826 if (!tg3_readphy(tp, 0x1b, &phy))
8827 tg3_writephy(tp, 0x1b, phy & ~0x20);
8828 if (!tg3_readphy(tp, 0x10, &phy))
8829 tg3_writephy(tp, 0x10, phy & ~0x4000);
8830 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8831 }
5d64ad34
MC		 8832 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8833 } else
8834 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1
MC		 8835
8836 tg3_writephy(tp, MII_BMCR, val);
c94e3941 8837 udelay(40);
5d64ad34
MC		 8838
8839 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8840 MAC_MODE_LINK_POLARITY;
8841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 8842 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 8843 mac_mode |= MAC_MODE_PORT_MODE_MII;
8844 } else
8845 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 8846
c94e3941
MC		 8847 /* reset to prevent losing 1st rx packet intermittently */
8848 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8849 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8850 udelay(10);
8851 tw32_f(MAC_RX_MODE, tp->rx_mode);
8852 }
ff18ff02 8853 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9f40dead 8854 mac_mode &= ~MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 8855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8857 }
9f40dead 8858 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 8859 }
8860 else
8861 return -EINVAL;
c76949a6
MC		 8862
8863 err = -EIO;
8864
c76949a6 8865 tx_len = 1514;
a20e9c62 8866 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 8867 if (!skb)
8868 return -ENOMEM;
8869
c76949a6
MC		 8870 tx_data = skb_put(skb, tx_len);
8871 memcpy(tx_data, tp->dev->dev_addr, 6);
8872 memset(tx_data + 6, 0x0, 8);
8873
8874 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8875
8876 for (i = 14; i < tx_len; i++)
8877 tx_data[i] = (u8) (i & 0xff);
8878
8879 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8880
8881 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8882 HOSTCC_MODE_NOW);
8883
8884 udelay(10);
8885
8886 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8887
c76949a6
MC		 8888 num_pkts = 0;
8889
9f40dead 8890 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 8891
9f40dead 8892 tp->tx_prod++;
c76949a6
MC		 8893 num_pkts++;
8894
9f40dead
MC		 8895 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8896 tp->tx_prod);
09ee929c 8897 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 8898
8899 udelay(10);
8900
3f7045c1
MC		 8901 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8902 for (i = 0; i < 25; i++) {
c76949a6
MC		 8903 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8904 HOSTCC_MODE_NOW);
8905
8906 udelay(10);
8907
8908 tx_idx = tp->hw_status->idx[0].tx_consumer;
8909 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 8910 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 8911 (rx_idx == (rx_start_idx + num_pkts)))
8912 break;
8913 }
8914
8915 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8916 dev_kfree_skb(skb);
8917
9f40dead 8918 if (tx_idx != tp->tx_prod)
c76949a6
MC		 8919 goto out;
8920
8921 if (rx_idx != rx_start_idx + num_pkts)
8922 goto out;
8923
8924 desc = &tp->rx_rcb[rx_start_idx];
8925 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8926 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8927 if (opaque_key != RXD_OPAQUE_RING_STD)
8928 goto out;
8929
8930 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8931 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8932 goto out;
8933
8934 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8935 if (rx_len != tx_len)
8936 goto out;
8937
8938 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8939
8940 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8941 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8942
8943 for (i = 14; i < tx_len; i++) {
8944 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8945 goto out;
8946 }
8947 err = 0;
6aa20a22 8948
c76949a6
MC		 8949 /* tg3_free_rings will unmap and free the rx_skb */
8950out:
8951 return err;
8952}
8953
9f40dead
MC		 8954#define TG3_MAC_LOOPBACK_FAILED 1
8955#define TG3_PHY_LOOPBACK_FAILED 2
8956#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8957 TG3_PHY_LOOPBACK_FAILED)
8958
8959static int tg3_test_loopback(struct tg3 *tp)
8960{
8961 int err = 0;
8962
8963 if (!netif_running(tp->dev))
8964 return TG3_LOOPBACK_FAILED;
8965
b9ec6c1b
MC		 8966 err = tg3_reset_hw(tp, 1);
8967 if (err)
8968 return TG3_LOOPBACK_FAILED;
9f40dead
MC		 8969
8970 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8971 err |= TG3_MAC_LOOPBACK_FAILED;
8972 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8973 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8974 err |= TG3_PHY_LOOPBACK_FAILED;
8975 }
8976
8977 return err;
8978}
8979
4cafd3f5
MC		 8980static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8981 u64 *data)
8982{
566f86ad
MC		 8983 struct tg3 *tp = netdev_priv(dev);
8984
bc1c7567
MC		 8985 if (tp->link_config.phy_is_low_power)
8986 tg3_set_power_state(tp, PCI_D0);
8987
566f86ad
MC		 8988 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8989
8990 if (tg3_test_nvram(tp) != 0) {
8991 etest->flags |= ETH_TEST_FL_FAILED;
8992 data[0] = 1;
8993 }
ca43007a
MC		 8994 if (tg3_test_link(tp) != 0) {
8995 etest->flags |= ETH_TEST_FL_FAILED;
8996 data[1] = 1;
8997 }
a71116d1 8998 if (etest->flags & ETH_TEST_FL_OFFLINE) {
ec41c7df 8999 int err, irq_sync = 0;
bbe832c0
MC		 9000
9001 if (netif_running(dev)) {
a71116d1 9002 tg3_netif_stop(tp);
bbe832c0
MC		 9003 irq_sync = 1;
9004 }
a71116d1 9005
bbe832c0 9006 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9007
9008 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9009 err = tg3_nvram_lock(tp);
a71116d1
MC		 9010 tg3_halt_cpu(tp, RX_CPU_BASE);
9011 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9012 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9013 if (!err)
9014 tg3_nvram_unlock(tp);
a71116d1 9015
d9ab5ad1
MC		 9016 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9017 tg3_phy_reset(tp);
9018
a71116d1
MC		 9019 if (tg3_test_registers(tp) != 0) {
9020 etest->flags |= ETH_TEST_FL_FAILED;
9021 data[2] = 1;
9022 }
7942e1db
MC		 9023 if (tg3_test_memory(tp) != 0) {
9024 etest->flags |= ETH_TEST_FL_FAILED;
9025 data[3] = 1;
9026 }
9f40dead 9027 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9028 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9029
f47c11ee
DM		 9030 tg3_full_unlock(tp);
9031
d4bc3927
MC		 9032 if (tg3_test_interrupt(tp) != 0) {
9033 etest->flags |= ETH_TEST_FL_FAILED;
9034 data[5] = 1;
9035 }
f47c11ee
DM		 9036
9037 tg3_full_lock(tp, 0);
d4bc3927 9038
a71116d1
MC		 9039 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9040 if (netif_running(dev)) {
9041 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 9042 if (!tg3_restart_hw(tp, 1))
9043 tg3_netif_start(tp);
a71116d1 9044 }
f47c11ee
DM		 9045
9046 tg3_full_unlock(tp);
a71116d1 9047 }
bc1c7567
MC		 9048 if (tp->link_config.phy_is_low_power)
9049 tg3_set_power_state(tp, PCI_D3hot);
9050
4cafd3f5
MC		 9051}
9052
1da177e4
LT		 9053static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9054{
9055 struct mii_ioctl_data *data = if_mii(ifr);
9056 struct tg3 *tp = netdev_priv(dev);
9057 int err;
9058
9059 switch(cmd) {
9060 case SIOCGMIIPHY:
9061 data->phy_id = PHY_ADDR;
9062
9063 /* fallthru */
9064 case SIOCGMIIREG: {
9065 u32 mii_regval;
9066
9067 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9068 break; /* We have no PHY */
9069
bc1c7567
MC		 9070 if (tp->link_config.phy_is_low_power)
9071 return -EAGAIN;
9072
f47c11ee 9073 spin_lock_bh(&tp->lock);
1da177e4 9074 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9075 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9076
9077 data->val_out = mii_regval;
9078
9079 return err;
9080 }
9081
9082 case SIOCSMIIREG:
9083 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9084 break; /* We have no PHY */
9085
9086 if (!capable(CAP_NET_ADMIN))
9087 return -EPERM;
9088
bc1c7567
MC		 9089 if (tp->link_config.phy_is_low_power)
9090 return -EAGAIN;
9091
f47c11ee 9092 spin_lock_bh(&tp->lock);
1da177e4 9093 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9094 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9095
9096 return err;
9097
9098 default:
9099 /* do nothing */
9100 break;
9101 }
9102 return -EOPNOTSUPP;
9103}
9104
9105#if TG3_VLAN_TAG_USED
9106static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9107{
9108 struct tg3 *tp = netdev_priv(dev);
9109
29315e87
MC		 9110 if (netif_running(dev))
9111 tg3_netif_stop(tp);
9112
f47c11ee 9113 tg3_full_lock(tp, 0);
1da177e4
LT		 9114
9115 tp->vlgrp = grp;
9116
9117 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9118 __tg3_set_rx_mode(dev);
9119
f47c11ee 9120 tg3_full_unlock(tp);
29315e87
MC		 9121
9122 if (netif_running(dev))
9123 tg3_netif_start(tp);
1da177e4
LT		 9124}
9125
9126static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9127{
9128 struct tg3 *tp = netdev_priv(dev);
9129
29315e87
MC		 9130 if (netif_running(dev))
9131 tg3_netif_stop(tp);
9132
f47c11ee 9133 tg3_full_lock(tp, 0);
5c15bdec 9134 vlan_group_set_device(tp->vlgrp, vid, NULL);
f47c11ee 9135 tg3_full_unlock(tp);
29315e87
MC		 9136
9137 if (netif_running(dev))
9138 tg3_netif_start(tp);
1da177e4
LT		 9139}
9140#endif
9141
15f9850d
DM		 9142static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9143{
9144 struct tg3 *tp = netdev_priv(dev);
9145
9146 memcpy(ec, &tp->coal, sizeof(*ec));
9147 return 0;
9148}
9149
d244c892
MC		 9150static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9151{
9152 struct tg3 *tp = netdev_priv(dev);
9153 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9154 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9155
9156 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9157 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9158 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9159 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9160 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9161 }
9162
9163 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9164 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9165 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9166 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9167 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9168 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9169 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9170 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9171 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9172 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9173 return -EINVAL;
9174
9175 /* No rx interrupts will be generated if both are zero */
9176 if ((ec->rx_coalesce_usecs == 0) &&
9177 (ec->rx_max_coalesced_frames == 0))
9178 return -EINVAL;
9179
9180 /* No tx interrupts will be generated if both are zero */
9181 if ((ec->tx_coalesce_usecs == 0) &&
9182 (ec->tx_max_coalesced_frames == 0))
9183 return -EINVAL;
9184
9185 /* Only copy relevant parameters, ignore all others. */
9186 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9187 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9188 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9189 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9190 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9191 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9192 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9193 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9194 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9195
9196 if (netif_running(dev)) {
9197 tg3_full_lock(tp, 0);
9198 __tg3_set_coalesce(tp, &tp->coal);
9199 tg3_full_unlock(tp);
9200 }
9201 return 0;
9202}
9203
7282d491 9204static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9205 .get_settings = tg3_get_settings,
9206 .set_settings = tg3_set_settings,
9207 .get_drvinfo = tg3_get_drvinfo,
9208 .get_regs_len = tg3_get_regs_len,
9209 .get_regs = tg3_get_regs,
9210 .get_wol = tg3_get_wol,
9211 .set_wol = tg3_set_wol,
9212 .get_msglevel = tg3_get_msglevel,
9213 .set_msglevel = tg3_set_msglevel,
9214 .nway_reset = tg3_nway_reset,
9215 .get_link = ethtool_op_get_link,
9216 .get_eeprom_len = tg3_get_eeprom_len,
9217 .get_eeprom = tg3_get_eeprom,
9218 .set_eeprom = tg3_set_eeprom,
9219 .get_ringparam = tg3_get_ringparam,
9220 .set_ringparam = tg3_set_ringparam,
9221 .get_pauseparam = tg3_get_pauseparam,
9222 .set_pauseparam = tg3_set_pauseparam,
9223 .get_rx_csum = tg3_get_rx_csum,
9224 .set_rx_csum = tg3_set_rx_csum,
9225 .get_tx_csum = ethtool_op_get_tx_csum,
9226 .set_tx_csum = tg3_set_tx_csum,
9227 .get_sg = ethtool_op_get_sg,
9228 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 9229 .get_tso = ethtool_op_get_tso,
9230 .set_tso = tg3_set_tso,
4cafd3f5
MC		 9231 .self_test_count = tg3_get_test_count,
9232 .self_test = tg3_self_test,
1da177e4 9233 .get_strings = tg3_get_strings,
4009a93d 9234 .phys_id = tg3_phys_id,
1da177e4
LT		 9235 .get_stats_count = tg3_get_stats_count,
9236 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 9237 .get_coalesce = tg3_get_coalesce,
d244c892 9238 .set_coalesce = tg3_set_coalesce,
2ff43697 9239 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 9240};
9241
9242static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9243{
1b27777a 9244 u32 cursize, val, magic;
1da177e4
LT		 9245
9246 tp->nvram_size = EEPROM_CHIP_SIZE;
9247
1820180b 9248 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 9249 return;
9250
b16250e3
MC		 9251 if ((magic != TG3_EEPROM_MAGIC) &&
9252 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9253 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 9254 return;
9255
9256 /*
9257 * Size the chip by reading offsets at increasing powers of two.
9258 * When we encounter our validation signature, we know the addressing
9259 * has wrapped around, and thus have our chip size.
9260 */
1b27777a 9261 cursize = 0x10;
1da177e4
LT		 9262
9263 while (cursize < tp->nvram_size) {
1820180b 9264 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 9265 return;
9266
1820180b 9267 if (val == magic)
1da177e4
LT		 9268 break;
9269
9270 cursize <<= 1;
9271 }
9272
9273 tp->nvram_size = cursize;
9274}
6aa20a22 9275
1da177e4
LT		 9276static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9277{
9278 u32 val;
9279
1820180b 9280 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 9281 return;
9282
9283 /* Selfboot format */
1820180b 9284 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 9285 tg3_get_eeprom_size(tp);
9286 return;
9287 }
9288
1da177e4
LT		 9289 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9290 if (val != 0) {
9291 tp->nvram_size = (val >> 16) * 1024;
9292 return;
9293 }
9294 }
989a9d23 9295 tp->nvram_size = 0x80000;
1da177e4
LT		 9296}
9297
9298static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9299{
9300 u32 nvcfg1;
9301
9302 nvcfg1 = tr32(NVRAM_CFG1);
9303 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9304 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9305 }
9306 else {
9307 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9308 tw32(NVRAM_CFG1, nvcfg1);
9309 }
9310
4c987487 9311 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 9312 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 9313 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9314 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9315 tp->nvram_jedecnum = JEDEC_ATMEL;
9316 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9317 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9318 break;
9319 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9320 tp->nvram_jedecnum = JEDEC_ATMEL;
9321 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9322 break;
9323 case FLASH_VENDOR_ATMEL_EEPROM:
9324 tp->nvram_jedecnum = JEDEC_ATMEL;
9325 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9326 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9327 break;
9328 case FLASH_VENDOR_ST:
9329 tp->nvram_jedecnum = JEDEC_ST;
9330 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9331 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9332 break;
9333 case FLASH_VENDOR_SAIFUN:
9334 tp->nvram_jedecnum = JEDEC_SAIFUN;
9335 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9336 break;
9337 case FLASH_VENDOR_SST_SMALL:
9338 case FLASH_VENDOR_SST_LARGE:
9339 tp->nvram_jedecnum = JEDEC_SST;
9340 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9341 break;
9342 }
9343 }
9344 else {
9345 tp->nvram_jedecnum = JEDEC_ATMEL;
9346 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9347 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9348 }
9349}
9350
361b4ac2
MC		 9351static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9352{
9353 u32 nvcfg1;
9354
9355 nvcfg1 = tr32(NVRAM_CFG1);
9356
e6af301b
MC		 9357 /* NVRAM protection for TPM */
9358 if (nvcfg1 & (1 << 27))
9359 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9360
361b4ac2
MC		 9361 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9362 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9363 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9364 tp->nvram_jedecnum = JEDEC_ATMEL;
9365 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9366 break;
9367 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9368 tp->nvram_jedecnum = JEDEC_ATMEL;
9369 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9370 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9371 break;
9372 case FLASH_5752VENDOR_ST_M45PE10:
9373 case FLASH_5752VENDOR_ST_M45PE20:
9374 case FLASH_5752VENDOR_ST_M45PE40:
9375 tp->nvram_jedecnum = JEDEC_ST;
9376 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9377 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9378 break;
9379 }
9380
9381 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9382 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9383 case FLASH_5752PAGE_SIZE_256:
9384 tp->nvram_pagesize = 256;
9385 break;
9386 case FLASH_5752PAGE_SIZE_512:
9387 tp->nvram_pagesize = 512;
9388 break;
9389 case FLASH_5752PAGE_SIZE_1K:
9390 tp->nvram_pagesize = 1024;
9391 break;
9392 case FLASH_5752PAGE_SIZE_2K:
9393 tp->nvram_pagesize = 2048;
9394 break;
9395 case FLASH_5752PAGE_SIZE_4K:
9396 tp->nvram_pagesize = 4096;
9397 break;
9398 case FLASH_5752PAGE_SIZE_264:
9399 tp->nvram_pagesize = 264;
9400 break;
9401 }
9402 }
9403 else {
9404 /* For eeprom, set pagesize to maximum eeprom size */
9405 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9406
9407 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9408 tw32(NVRAM_CFG1, nvcfg1);
9409 }
9410}
9411
d3c7b886
MC		 9412static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9413{
989a9d23 9414 u32 nvcfg1, protect = 0;
d3c7b886
MC		 9415
9416 nvcfg1 = tr32(NVRAM_CFG1);
9417
9418 /* NVRAM protection for TPM */
989a9d23 9419 if (nvcfg1 & (1 << 27)) {
d3c7b886 9420 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 9421 protect = 1;
9422 }
d3c7b886 9423
989a9d23
MC		 9424 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9425 switch (nvcfg1) {
d3c7b886
MC		 9426 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9427 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9428 case FLASH_5755VENDOR_ATMEL_FLASH_3:
d3c7b886
MC		 9429 tp->nvram_jedecnum = JEDEC_ATMEL;
9430 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9431 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9432 tp->nvram_pagesize = 264;
989a9d23
MC		 9433 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
9434 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9435 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9436 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9437 else
9438 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
d3c7b886
MC		 9439 break;
9440 case FLASH_5752VENDOR_ST_M45PE10:
9441 case FLASH_5752VENDOR_ST_M45PE20:
9442 case FLASH_5752VENDOR_ST_M45PE40:
9443 tp->nvram_jedecnum = JEDEC_ST;
9444 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9445 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9446 tp->nvram_pagesize = 256;
989a9d23
MC		 9447 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9448 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9449 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9450 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9451 else
9452 tp->nvram_size = (protect ? 0x20000 : 0x80000);
d3c7b886
MC		 9453 break;
9454 }
9455}
9456
1b27777a
MC		 9457static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9458{
9459 u32 nvcfg1;
9460
9461 nvcfg1 = tr32(NVRAM_CFG1);
9462
9463 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9464 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9465 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9466 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9467 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9468 tp->nvram_jedecnum = JEDEC_ATMEL;
9469 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9470 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9471
9472 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9473 tw32(NVRAM_CFG1, nvcfg1);
9474 break;
9475 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9476 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9477 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9478 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9479 tp->nvram_jedecnum = JEDEC_ATMEL;
9480 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9481 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9482 tp->nvram_pagesize = 264;
9483 break;
9484 case FLASH_5752VENDOR_ST_M45PE10:
9485 case FLASH_5752VENDOR_ST_M45PE20:
9486 case FLASH_5752VENDOR_ST_M45PE40:
9487 tp->nvram_jedecnum = JEDEC_ST;
9488 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9489 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9490 tp->nvram_pagesize = 256;
9491 break;
9492 }
9493}
9494
b5d3772c
MC		 9495static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9496{
9497 tp->nvram_jedecnum = JEDEC_ATMEL;
9498 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9499 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9500}
9501
1da177e4
LT		 9502/* Chips other than 5700/5701 use the NVRAM for fetching info. */
9503static void __devinit tg3_nvram_init(struct tg3 *tp)
9504{
1da177e4
LT		 9505 tw32_f(GRC_EEPROM_ADDR,
9506 (EEPROM_ADDR_FSM_RESET |
9507 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9508 EEPROM_ADDR_CLKPERD_SHIFT)));
9509
9d57f01c 9510 msleep(1);
1da177e4
LT		 9511
9512 /* Enable seeprom accesses. */
9513 tw32_f(GRC_LOCAL_CTRL,
9514 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9515 udelay(100);
9516
9517 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9518 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9519 tp->tg3_flags |= TG3_FLAG_NVRAM;
9520
ec41c7df
MC		 9521 if (tg3_nvram_lock(tp)) {
9522 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9523 "tg3_nvram_init failed.\n", tp->dev->name);
9524 return;
9525 }
e6af301b 9526 tg3_enable_nvram_access(tp);
1da177e4 9527
989a9d23
MC		 9528 tp->nvram_size = 0;
9529
361b4ac2
MC		 9530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9531 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 9532 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9533 tg3_get_5755_nvram_info(tp);
1b27777a
MC		 9534 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9535 tg3_get_5787_nvram_info(tp);
b5d3772c
MC		 9536 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9537 tg3_get_5906_nvram_info(tp);
361b4ac2
MC		 9538 else
9539 tg3_get_nvram_info(tp);
9540
989a9d23
MC		 9541 if (tp->nvram_size == 0)
9542 tg3_get_nvram_size(tp);
1da177e4 9543
e6af301b 9544 tg3_disable_nvram_access(tp);
381291b7 9545 tg3_nvram_unlock(tp);
1da177e4
LT		 9546
9547 } else {
9548 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9549
9550 tg3_get_eeprom_size(tp);
9551 }
9552}
9553
9554static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9555 u32 offset, u32 *val)
9556{
9557 u32 tmp;
9558 int i;
9559
9560 if (offset > EEPROM_ADDR_ADDR_MASK ||
9561 (offset % 4) != 0)
9562 return -EINVAL;
9563
9564 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9565 EEPROM_ADDR_DEVID_MASK |
9566 EEPROM_ADDR_READ);
9567 tw32(GRC_EEPROM_ADDR,
9568 tmp |
9569 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9570 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9571 EEPROM_ADDR_ADDR_MASK) |
9572 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9573
9d57f01c 9574 for (i = 0; i < 1000; i++) {
1da177e4
LT		 9575 tmp = tr32(GRC_EEPROM_ADDR);
9576
9577 if (tmp & EEPROM_ADDR_COMPLETE)
9578 break;
9d57f01c 9579 msleep(1);
1da177e4
LT		 9580 }
9581 if (!(tmp & EEPROM_ADDR_COMPLETE))
9582 return -EBUSY;
9583
9584 *val = tr32(GRC_EEPROM_DATA);
9585 return 0;
9586}
9587
9588#define NVRAM_CMD_TIMEOUT 10000
9589
9590static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9591{
9592 int i;
9593
9594 tw32(NVRAM_CMD, nvram_cmd);
9595 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9596 udelay(10);
9597 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9598 udelay(10);
9599 break;
9600 }
9601 }
9602 if (i == NVRAM_CMD_TIMEOUT) {
9603 return -EBUSY;
9604 }
9605 return 0;
9606}
9607
1820180b
MC		 9608static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9609{
9610 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9611 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9612 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9613 (tp->nvram_jedecnum == JEDEC_ATMEL))
9614
9615 addr = ((addr / tp->nvram_pagesize) <<
9616 ATMEL_AT45DB0X1B_PAGE_POS) +
9617 (addr % tp->nvram_pagesize);
9618
9619 return addr;
9620}
9621
c4e6575c
MC		 9622static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9623{
9624 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9625 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9626 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9627 (tp->nvram_jedecnum == JEDEC_ATMEL))
9628
9629 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9630 tp->nvram_pagesize) +
9631 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9632
9633 return addr;
9634}
9635
1da177e4
LT		 9636static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9637{
9638 int ret;
9639
1da177e4
LT		 9640 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9641 return tg3_nvram_read_using_eeprom(tp, offset, val);
9642
1820180b 9643 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9644
9645 if (offset > NVRAM_ADDR_MSK)
9646 return -EINVAL;
9647
ec41c7df
MC		 9648 ret = tg3_nvram_lock(tp);
9649 if (ret)
9650 return ret;
1da177e4 9651
e6af301b 9652 tg3_enable_nvram_access(tp);
1da177e4
LT		 9653
9654 tw32(NVRAM_ADDR, offset);
9655 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9656 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9657
9658 if (ret == 0)
9659 *val = swab32(tr32(NVRAM_RDDATA));
9660
e6af301b 9661 tg3_disable_nvram_access(tp);
1da177e4 9662
381291b7
MC		 9663 tg3_nvram_unlock(tp);
9664
1da177e4
LT		 9665 return ret;
9666}
9667
1820180b
MC		 9668static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9669{
9670 int err;
9671 u32 tmp;
9672
9673 err = tg3_nvram_read(tp, offset, &tmp);
9674 *val = swab32(tmp);
9675 return err;
9676}
9677
1da177e4
LT		 9678static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9679 u32 offset, u32 len, u8 *buf)
9680{
9681 int i, j, rc = 0;
9682 u32 val;
9683
9684 for (i = 0; i < len; i += 4) {
9685 u32 addr, data;
9686
9687 addr = offset + i;
9688
9689 memcpy(&data, buf + i, 4);
9690
9691 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9692
9693 val = tr32(GRC_EEPROM_ADDR);
9694 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9695
9696 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9697 EEPROM_ADDR_READ);
9698 tw32(GRC_EEPROM_ADDR, val |
9699 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9700 (addr & EEPROM_ADDR_ADDR_MASK) |
9701 EEPROM_ADDR_START |
9702 EEPROM_ADDR_WRITE);
6aa20a22 9703
9d57f01c 9704 for (j = 0; j < 1000; j++) {
1da177e4
LT		 9705 val = tr32(GRC_EEPROM_ADDR);
9706
9707 if (val & EEPROM_ADDR_COMPLETE)
9708 break;
9d57f01c 9709 msleep(1);
1da177e4
LT		 9710 }
9711 if (!(val & EEPROM_ADDR_COMPLETE)) {
9712 rc = -EBUSY;
9713 break;
9714 }
9715 }
9716
9717 return rc;
9718}
9719
9720/* offset and length are dword aligned */
9721static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9722 u8 *buf)
9723{
9724 int ret = 0;
9725 u32 pagesize = tp->nvram_pagesize;
9726 u32 pagemask = pagesize - 1;
9727 u32 nvram_cmd;
9728 u8 *tmp;
9729
9730 tmp = kmalloc(pagesize, GFP_KERNEL);
9731 if (tmp == NULL)
9732 return -ENOMEM;
9733
9734 while (len) {
9735 int j;
e6af301b 9736 u32 phy_addr, page_off, size;
1da177e4
LT		 9737
9738 phy_addr = offset & ~pagemask;
6aa20a22 9739
1da177e4
LT		 9740 for (j = 0; j < pagesize; j += 4) {
9741 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9742 (u32 *) (tmp + j))))
9743 break;
9744 }
9745 if (ret)
9746 break;
9747
9748 page_off = offset & pagemask;
9749 size = pagesize;
9750 if (len < size)
9751 size = len;
9752
9753 len -= size;
9754
9755 memcpy(tmp + page_off, buf, size);
9756
9757 offset = offset + (pagesize - page_off);
9758
e6af301b 9759 tg3_enable_nvram_access(tp);
1da177e4
LT		 9760
9761 /*
9762 * Before we can erase the flash page, we need
9763 * to issue a special "write enable" command.
9764 */
9765 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9766
9767 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9768 break;
9769
9770 /* Erase the target page */
9771 tw32(NVRAM_ADDR, phy_addr);
9772
9773 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9774 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9775
9776 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9777 break;
9778
9779 /* Issue another write enable to start the write. */
9780 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9781
9782 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9783 break;
9784
9785 for (j = 0; j < pagesize; j += 4) {
9786 u32 data;
9787
9788 data = *((u32 *) (tmp + j));
9789 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9790
9791 tw32(NVRAM_ADDR, phy_addr + j);
9792
9793 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9794 NVRAM_CMD_WR;
9795
9796 if (j == 0)
9797 nvram_cmd |= NVRAM_CMD_FIRST;
9798 else if (j == (pagesize - 4))
9799 nvram_cmd |= NVRAM_CMD_LAST;
9800
9801 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9802 break;
9803 }
9804 if (ret)
9805 break;
9806 }
9807
9808 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9809 tg3_nvram_exec_cmd(tp, nvram_cmd);
9810
9811 kfree(tmp);
9812
9813 return ret;
9814}
9815
9816/* offset and length are dword aligned */
9817static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9818 u8 *buf)
9819{
9820 int i, ret = 0;
9821
9822 for (i = 0; i < len; i += 4, offset += 4) {
9823 u32 data, page_off, phy_addr, nvram_cmd;
9824
9825 memcpy(&data, buf + i, 4);
9826 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9827
9828 page_off = offset % tp->nvram_pagesize;
9829
1820180b 9830 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 9831
9832 tw32(NVRAM_ADDR, phy_addr);
9833
9834 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9835
9836 if ((page_off == 0) || (i == 0))
9837 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 9838 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 9839 nvram_cmd |= NVRAM_CMD_LAST;
9840
9841 if (i == (len - 4))
9842 nvram_cmd |= NVRAM_CMD_LAST;
9843
4c987487 9844 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
af36e6b6 9845 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
1b27777a 9846 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
4c987487
MC		 9847 (tp->nvram_jedecnum == JEDEC_ST) &&
9848 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 9849
9850 if ((ret = tg3_nvram_exec_cmd(tp,
9851 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9852 NVRAM_CMD_DONE)))
9853
9854 break;
9855 }
9856 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9857 /* We always do complete word writes to eeprom. */
9858 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9859 }
9860
9861 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9862 break;
9863 }
9864 return ret;
9865}
9866
9867/* offset and length are dword aligned */
9868static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9869{
9870 int ret;
9871
1da177e4 9872 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 9873 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9874 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 9875 udelay(40);
9876 }
9877
9878 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9879 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9880 }
9881 else {
9882 u32 grc_mode;
9883
ec41c7df
MC		 9884 ret = tg3_nvram_lock(tp);
9885 if (ret)
9886 return ret;
1da177e4 9887
e6af301b
MC		 9888 tg3_enable_nvram_access(tp);
9889 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9890 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 9891 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 9892
9893 grc_mode = tr32(GRC_MODE);
9894 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9895
9896 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9897 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9898
9899 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9900 buf);
9901 }
9902 else {
9903 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9904 buf);
9905 }
9906
9907 grc_mode = tr32(GRC_MODE);
9908 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9909
e6af301b 9910 tg3_disable_nvram_access(tp);
1da177e4
LT		 9911 tg3_nvram_unlock(tp);
9912 }
9913
9914 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 9915 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 9916 udelay(40);
9917 }
9918
9919 return ret;
9920}
9921
9922struct subsys_tbl_ent {
9923 u16 subsys_vendor, subsys_devid;
9924 u32 phy_id;
9925};
9926
9927static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9928 /* Broadcom boards. */
9929 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9930 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9931 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9932 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9933 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9934 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9935 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9936 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9937 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9938 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9939 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9940
9941 /* 3com boards. */
9942 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9943 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9944 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9945 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9946 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9947
9948 /* DELL boards. */
9949 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9950 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9951 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9952 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9953
9954 /* Compaq boards. */
9955 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9956 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9957 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9958 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9959 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9960
9961 /* IBM boards. */
9962 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9963};
9964
9965static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9966{
9967 int i;
9968
9969 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9970 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9971 tp->pdev->subsystem_vendor) &&
9972 (subsys_id_to_phy_id[i].subsys_devid ==
9973 tp->pdev->subsystem_device))
9974 return &subsys_id_to_phy_id[i];
9975 }
9976 return NULL;
9977}
9978
7d0c41ef 9979static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 9980{
1da177e4 9981 u32 val;
caf636c7
MC		 9982 u16 pmcsr;
9983
9984 /* On some early chips the SRAM cannot be accessed in D3hot state,
9985 * so need make sure we're in D0.
9986 */
9987 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9988 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9989 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9990 msleep(1);
7d0c41ef
MC		 9991
9992 /* Make sure register accesses (indirect or otherwise)
9993 * will function correctly.
9994 */
9995 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9996 tp->misc_host_ctrl);
1da177e4 9997
f49639e6
DM		 9998 /* The memory arbiter has to be enabled in order for SRAM accesses
9999 * to succeed. Normally on powerup the tg3 chip firmware will make
10000 * sure it is enabled, but other entities such as system netboot
10001 * code might disable it.
10002 */
10003 val = tr32(MEMARB_MODE);
10004 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10005
1da177e4 10006 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 10007 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10008
a85feb8c
GZ		 10009 /* Assume an onboard device and WOL capable by default. */
10010 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 10011
b5d3772c 10012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 10013 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 10014 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10015 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10016 }
8ed5d97e
MC		 10017 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10018 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
b5d3772c
MC		 10019 return;
10020 }
10021
1da177e4
LT		 10022 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10023 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10024 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 10025 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10026 int eeprom_phy_serdes = 0;
1da177e4
LT		 10027
10028 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10029 tp->nic_sram_data_cfg = nic_cfg;
10030
10031 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10032 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10033 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10034 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10035 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10036 (ver > 0) && (ver < 0x100))
10037 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10038
1da177e4
LT		 10039 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10040 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10041 eeprom_phy_serdes = 1;
10042
10043 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10044 if (nic_phy_id != 0) {
10045 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10046 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10047
10048 eeprom_phy_id = (id1 >> 16) << 10;
10049 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10050 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10051 } else
10052 eeprom_phy_id = 0;
10053
7d0c41ef 10054 tp->phy_id = eeprom_phy_id;
747e8f8b 10055 if (eeprom_phy_serdes) {
a4e2b347 10056 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 10057 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10058 else
10059 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10060 }
7d0c41ef 10061
cbf46853 10062 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10063 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10064 SHASTA_EXT_LED_MODE_MASK);
cbf46853 10065 else
1da177e4
LT		 10066 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10067
10068 switch (led_cfg) {
10069 default:
10070 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10071 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10072 break;
10073
10074 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10075 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10076 break;
10077
10078 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10079 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 10080
10081 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10082 * read on some older 5700/5701 bootcode.
10083 */
10084 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10085 ASIC_REV_5700 ||
10086 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10087 ASIC_REV_5701)
10088 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10089
1da177e4
LT		 10090 break;
10091
10092 case SHASTA_EXT_LED_SHARED:
10093 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10094 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10095 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10096 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10097 LED_CTRL_MODE_PHY_2);
10098 break;
10099
10100 case SHASTA_EXT_LED_MAC:
10101 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10102 break;
10103
10104 case SHASTA_EXT_LED_COMBO:
10105 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10106 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10107 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10108 LED_CTRL_MODE_PHY_2);
10109 break;
10110
10111 };
10112
10113 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10115 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10116 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10117
9d26e213 10118 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 10119 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10120 if ((tp->pdev->subsystem_vendor ==
10121 PCI_VENDOR_ID_ARIMA) &&
10122 (tp->pdev->subsystem_device == 0x205a ||
10123 tp->pdev->subsystem_device == 0x2063))
10124 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10125 } else {
f49639e6 10126 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10127 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10128 }
1da177e4
LT		 10129
10130 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10131 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 10132 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 10133 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10134 }
a85feb8c
GZ		 10135 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10136 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10137 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4
LT		 10138
10139 if (cfg2 & (1 << 17))
10140 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10141
10142 /* serdes signal pre-emphasis in register 0x590 set by */
10143 /* bootcode if bit 18 is set */
10144 if (cfg2 & (1 << 18))
10145 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e
MC		 10146
10147 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10148 u32 cfg3;
10149
10150 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10151 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10152 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10153 }
1da177e4 10154 }
7d0c41ef
MC		 10155}
10156
10157static int __devinit tg3_phy_probe(struct tg3 *tp)
10158{
10159 u32 hw_phy_id_1, hw_phy_id_2;
10160 u32 hw_phy_id, hw_phy_id_masked;
10161 int err;
1da177e4
LT		 10162
10163 /* Reading the PHY ID register can conflict with ASF
10164 * firwmare access to the PHY hardware.
10165 */
10166 err = 0;
10167 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10168 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10169 } else {
10170 /* Now read the physical PHY_ID from the chip and verify
10171 * that it is sane. If it doesn't look good, we fall back
10172 * to either the hard-coded table based PHY_ID and failing
10173 * that the value found in the eeprom area.
10174 */
10175 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10176 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10177
10178 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10179 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10180 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10181
10182 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10183 }
10184
10185 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10186 tp->phy_id = hw_phy_id;
10187 if (hw_phy_id_masked == PHY_ID_BCM8002)
10188 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 10189 else
10190 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 10191 } else {
7d0c41ef
MC		 10192 if (tp->phy_id != PHY_ID_INVALID) {
10193 /* Do nothing, phy ID already set up in
10194 * tg3_get_eeprom_hw_cfg().
10195 */
1da177e4
LT		 10196 } else {
10197 struct subsys_tbl_ent *p;
10198
10199 /* No eeprom signature? Try the hardcoded
10200 * subsys device table.
10201 */
10202 p = lookup_by_subsys(tp);
10203 if (!p)
10204 return -ENODEV;
10205
10206 tp->phy_id = p->phy_id;
10207 if (!tp->phy_id ||
10208 tp->phy_id == PHY_ID_BCM8002)
10209 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10210 }
10211 }
10212
747e8f8b 10213 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4 10214 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 10215 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 10216
10217 tg3_readphy(tp, MII_BMSR, &bmsr);
10218 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10219 (bmsr & BMSR_LSTATUS))
10220 goto skip_phy_reset;
6aa20a22 10221
1da177e4
LT		 10222 err = tg3_phy_reset(tp);
10223 if (err)
10224 return err;
10225
10226 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10227 ADVERTISE_100HALF | ADVERTISE_100FULL |
10228 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10229 tg3_ctrl = 0;
10230 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10231 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10232 MII_TG3_CTRL_ADV_1000_FULL);
10233 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10234 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10235 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10236 MII_TG3_CTRL_ENABLE_AS_MASTER);
10237 }
10238
3600d918
MC		 10239 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10240 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10241 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10242 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 10243 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10244
10245 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10246 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10247
10248 tg3_writephy(tp, MII_BMCR,
10249 BMCR_ANENABLE | BMCR_ANRESTART);
10250 }
10251 tg3_phy_set_wirespeed(tp);
10252
10253 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10254 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10255 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10256 }
10257
10258skip_phy_reset:
10259 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10260 err = tg3_init_5401phy_dsp(tp);
10261 if (err)
10262 return err;
10263 }
10264
10265 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10266 err = tg3_init_5401phy_dsp(tp);
10267 }
10268
747e8f8b 10269 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 10270 tp->link_config.advertising =
10271 (ADVERTISED_1000baseT_Half |
10272 ADVERTISED_1000baseT_Full |
10273 ADVERTISED_Autoneg |
10274 ADVERTISED_FIBRE);
10275 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10276 tp->link_config.advertising &=
10277 ~(ADVERTISED_1000baseT_Half |
10278 ADVERTISED_1000baseT_Full);
10279
10280 return err;
10281}
10282
10283static void __devinit tg3_read_partno(struct tg3 *tp)
10284{
10285 unsigned char vpd_data[256];
af2c6a4a 10286 unsigned int i;
1b27777a 10287 u32 magic;
1da177e4 10288
1820180b 10289 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 10290 goto out_not_found;
1da177e4 10291
1820180b 10292 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 10293 for (i = 0; i < 256; i += 4) {
10294 u32 tmp;
1da177e4 10295
1b27777a
MC		 10296 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10297 goto out_not_found;
10298
10299 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10300 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10301 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10302 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10303 }
10304 } else {
10305 int vpd_cap;
10306
10307 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10308 for (i = 0; i < 256; i += 4) {
10309 u32 tmp, j = 0;
10310 u16 tmp16;
10311
10312 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10313 i);
10314 while (j++ < 100) {
10315 pci_read_config_word(tp->pdev, vpd_cap +
10316 PCI_VPD_ADDR, &tmp16);
10317 if (tmp16 & 0x8000)
10318 break;
10319 msleep(1);
10320 }
f49639e6
DM		 10321 if (!(tmp16 & 0x8000))
10322 goto out_not_found;
10323
1b27777a
MC		 10324 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10325 &tmp);
10326 tmp = cpu_to_le32(tmp);
10327 memcpy(&vpd_data[i], &tmp, 4);
10328 }
1da177e4
LT		 10329 }
10330
10331 /* Now parse and find the part number. */
af2c6a4a 10332 for (i = 0; i < 254; ) {
1da177e4 10333 unsigned char val = vpd_data[i];
af2c6a4a 10334 unsigned int block_end;
1da177e4
LT		 10335
10336 if (val == 0x82 || val == 0x91) {
10337 i = (i + 3 +
10338 (vpd_data[i + 1] +
10339 (vpd_data[i + 2] << 8)));
10340 continue;
10341 }
10342
10343 if (val != 0x90)
10344 goto out_not_found;
10345
10346 block_end = (i + 3 +
10347 (vpd_data[i + 1] +
10348 (vpd_data[i + 2] << 8)));
10349 i += 3;
af2c6a4a
MC		 10350
10351 if (block_end > 256)
10352 goto out_not_found;
10353
10354 while (i < (block_end - 2)) {
1da177e4
LT		 10355 if (vpd_data[i + 0] == 'P' &&
10356 vpd_data[i + 1] == 'N') {
10357 int partno_len = vpd_data[i + 2];
10358
af2c6a4a
MC		 10359 i += 3;
10360 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 10361 goto out_not_found;
10362
10363 memcpy(tp->board_part_number,
af2c6a4a 10364 &vpd_data[i], partno_len);
1da177e4
LT		 10365
10366 /* Success. */
10367 return;
10368 }
af2c6a4a 10369 i += 3 + vpd_data[i + 2];
1da177e4
LT		 10370 }
10371
10372 /* Part number not found. */
10373 goto out_not_found;
10374 }
10375
10376out_not_found:
b5d3772c
MC		 10377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10378 strcpy(tp->board_part_number, "BCM95906");
10379 else
10380 strcpy(tp->board_part_number, "none");
1da177e4
LT		 10381}
10382
c4e6575c
MC		 10383static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10384{
10385 u32 val, offset, start;
10386
10387 if (tg3_nvram_read_swab(tp, 0, &val))
10388 return;
10389
10390 if (val != TG3_EEPROM_MAGIC)
10391 return;
10392
10393 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10394 tg3_nvram_read_swab(tp, 0x4, &start))
10395 return;
10396
10397 offset = tg3_nvram_logical_addr(tp, offset);
10398 if (tg3_nvram_read_swab(tp, offset, &val))
10399 return;
10400
10401 if ((val & 0xfc000000) == 0x0c000000) {
10402 u32 ver_offset, addr;
10403 int i;
10404
10405 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10406 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10407 return;
10408
10409 if (val != 0)
10410 return;
10411
10412 addr = offset + ver_offset - start;
10413 for (i = 0; i < 16; i += 4) {
10414 if (tg3_nvram_read(tp, addr + i, &val))
10415 return;
10416
10417 val = cpu_to_le32(val);
10418 memcpy(tp->fw_ver + i, &val, 4);
10419 }
10420 }
10421}
10422
7544b097
MC		 10423static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10424
1da177e4
LT		 10425static int __devinit tg3_get_invariants(struct tg3 *tp)
10426{
10427 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 10428 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10429 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 10430 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10431 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 10432 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10433 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 10434 { },
10435 };
10436 u32 misc_ctrl_reg;
10437 u32 cacheline_sz_reg;
10438 u32 pci_state_reg, grc_misc_cfg;
10439 u32 val;
10440 u16 pci_cmd;
c7835a77 10441 int err, pcie_cap;
1da177e4 10442
1da177e4
LT		 10443 /* Force memory write invalidate off. If we leave it on,
10444 * then on 5700_BX chips we have to enable a workaround.
10445 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10446 * to match the cacheline size. The Broadcom driver have this
10447 * workaround but turns MWI off all the times so never uses
10448 * it. This seems to suggest that the workaround is insufficient.
10449 */
10450 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10451 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10452 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10453
10454 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10455 * has the register indirect write enable bit set before
10456 * we try to access any of the MMIO registers. It is also
10457 * critical that the PCI-X hw workaround situation is decided
10458 * before that as well.
10459 */
10460 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10461 &misc_ctrl_reg);
10462
10463 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10464 MISC_HOST_CTRL_CHIPREV_SHIFT);
10465
ff645bec
MC		 10466 /* Wrong chip ID in 5752 A0. This code can be removed later
10467 * as A0 is not in production.
10468 */
10469 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10470 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10471
6892914f
MC		 10472 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10473 * we need to disable memory and use config. cycles
10474 * only to access all registers. The 5702/03 chips
10475 * can mistakenly decode the special cycles from the
10476 * ICH chipsets as memory write cycles, causing corruption
10477 * of register and memory space. Only certain ICH bridges
10478 * will drive special cycles with non-zero data during the
10479 * address phase which can fall within the 5703's address
10480 * range. This is not an ICH bug as the PCI spec allows
10481 * non-zero address during special cycles. However, only
10482 * these ICH bridges are known to drive non-zero addresses
10483 * during special cycles.
10484 *
10485 * Since special cycles do not cross PCI bridges, we only
10486 * enable this workaround if the 5703 is on the secondary
10487 * bus of these ICH bridges.
10488 */
10489 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10490 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10491 static struct tg3_dev_id {
10492 u32 vendor;
10493 u32 device;
10494 u32 rev;
10495 } ich_chipsets[] = {
10496 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10497 PCI_ANY_ID },
10498 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10499 PCI_ANY_ID },
10500 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10501 0xa },
10502 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10503 PCI_ANY_ID },
10504 { },
10505 };
10506 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10507 struct pci_dev *bridge = NULL;
10508
10509 while (pci_id->vendor != 0) {
10510 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10511 bridge);
10512 if (!bridge) {
10513 pci_id++;
10514 continue;
10515 }
10516 if (pci_id->rev != PCI_ANY_ID) {
10517 u8 rev;
10518
10519 pci_read_config_byte(bridge, PCI_REVISION_ID,
10520 &rev);
10521 if (rev > pci_id->rev)
10522 continue;
10523 }
10524 if (bridge->subordinate &&
10525 (bridge->subordinate->number ==
10526 tp->pdev->bus->number)) {
10527
10528 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10529 pci_dev_put(bridge);
10530 break;
10531 }
10532 }
10533 }
10534
4a29cc2e
MC		 10535 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10536 * DMA addresses > 40-bit. This bridge may have other additional
10537 * 57xx devices behind it in some 4-port NIC designs for example.
10538 * Any tg3 device found behind the bridge will also need the 40-bit
10539 * DMA workaround.
10540 */
a4e2b347
MC		 10541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10542 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10543 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 10544 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 10545 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 10546 }
4a29cc2e
MC		 10547 else {
10548 struct pci_dev *bridge = NULL;
10549
10550 do {
10551 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10552 PCI_DEVICE_ID_SERVERWORKS_EPB,
10553 bridge);
10554 if (bridge && bridge->subordinate &&
10555 (bridge->subordinate->number <=
10556 tp->pdev->bus->number) &&
10557 (bridge->subordinate->subordinate >=
10558 tp->pdev->bus->number)) {
10559 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10560 pci_dev_put(bridge);
10561 break;
10562 }
10563 } while (bridge);
10564 }
4cf78e4f 10565
1da177e4
LT		 10566 /* Initialize misc host control in PCI block. */
10567 tp->misc_host_ctrl |= (misc_ctrl_reg &
10568 MISC_HOST_CTRL_CHIPREV);
10569 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10570 tp->misc_host_ctrl);
10571
10572 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10573 &cacheline_sz_reg);
10574
10575 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10576 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10577 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10578 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10579
7544b097
MC		 10580 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10581 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10582 tp->pdev_peer = tg3_find_peer(tp);
10583
6708e5cc 10584 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f 10585 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
af36e6b6 10586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 10587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
b5d3772c 10588 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
a4e2b347 10589 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 10590 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10591
1b440c56
JL		 10592 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10593 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10594 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10595
5a6f3074 10596 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 10597 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10598 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10599 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10600 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10601 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10602 tp->pdev_peer == tp->pdev))
10603 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10604
af36e6b6 10605 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10606 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10607 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 10608 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 10609 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 10610 } else {
7f62ad5d 10611 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 10612 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10613 ASIC_REV_5750 &&
10614 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 10615 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 10616 }
5a6f3074 10617 }
1da177e4 10618
0f893dc6
MC		 10619 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10620 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
d9ab5ad1 10621 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
af36e6b6 10622 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
b5d3772c
MC		 10623 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10624 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
0f893dc6
MC		 10625 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10626
c7835a77
MC		 10627 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10628 if (pcie_cap != 0) {
1da177e4 10629 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
c7835a77
MC		 10630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10631 u16 lnkctl;
10632
10633 pci_read_config_word(tp->pdev,
10634 pcie_cap + PCI_EXP_LNKCTL,
10635 &lnkctl);
10636 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10637 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10638 }
10639 }
1da177e4 10640
399de50b
MC		 10641 /* If we have an AMD 762 or VIA K8T800 chipset, write
10642 * reordering to the mailbox registers done by the host
10643 * controller can cause major troubles. We read back from
10644 * every mailbox register write to force the writes to be
10645 * posted to the chip in order.
10646 */
10647 if (pci_dev_present(write_reorder_chipsets) &&
10648 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10649 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10650
1da177e4
LT		 10651 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10652 tp->pci_lat_timer < 64) {
10653 tp->pci_lat_timer = 64;
10654
10655 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10656 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10657 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10658 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10659
10660 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10661 cacheline_sz_reg);
10662 }
10663
10664 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10665 &pci_state_reg);
10666
10667 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10668 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10669
10670 /* If this is a 5700 BX chipset, and we are in PCI-X
10671 * mode, enable register write workaround.
10672 *
10673 * The workaround is to use indirect register accesses
10674 * for all chip writes not to mailbox registers.
10675 */
10676 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10677 u32 pm_reg;
10678 u16 pci_cmd;
10679
10680 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10681
10682 /* The chip can have it's power management PCI config
10683 * space registers clobbered due to this bug.
10684 * So explicitly force the chip into D0 here.
10685 */
10686 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10687 &pm_reg);
10688 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10689 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10690 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10691 pm_reg);
10692
10693 /* Also, force SERR#/PERR# in PCI command. */
10694 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10695 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10696 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10697 }
10698 }
10699
087fe256
MC		 10700 /* 5700 BX chips need to have their TX producer index mailboxes
10701 * written twice to workaround a bug.
10702 */
10703 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10704 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10705
1da177e4
LT		 10706 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10707 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10708 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10709 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10710
10711 /* Chip-specific fixup from Broadcom driver */
10712 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10713 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10714 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10715 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10716 }
10717
1ee582d8 10718 /* Default fast path register access methods */
20094930 10719 tp->read32 = tg3_read32;
1ee582d8 10720 tp->write32 = tg3_write32;
09ee929c 10721 tp->read32_mbox = tg3_read32;
20094930 10722 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 10723 tp->write32_tx_mbox = tg3_write32;
10724 tp->write32_rx_mbox = tg3_write32;
10725
10726 /* Various workaround register access methods */
10727 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10728 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 10729 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10730 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10731 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10732 /*
10733 * Back to back register writes can cause problems on these
10734 * chips, the workaround is to read back all reg writes
10735 * except those to mailbox regs.
10736 *
10737 * See tg3_write_indirect_reg32().
10738 */
1ee582d8 10739 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 10740 }
10741
1ee582d8
MC		 10742
10743 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10744 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10745 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10746 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10747 tp->write32_rx_mbox = tg3_write_flush_reg32;
10748 }
20094930 10749
6892914f
MC		 10750 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10751 tp->read32 = tg3_read_indirect_reg32;
10752 tp->write32 = tg3_write_indirect_reg32;
10753 tp->read32_mbox = tg3_read_indirect_mbox;
10754 tp->write32_mbox = tg3_write_indirect_mbox;
10755 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10756 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10757
10758 iounmap(tp->regs);
22abe310 10759 tp->regs = NULL;
6892914f
MC		 10760
10761 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10762 pci_cmd &= ~PCI_COMMAND_MEMORY;
10763 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10764 }
b5d3772c
MC		 10765 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10766 tp->read32_mbox = tg3_read32_mbox_5906;
10767 tp->write32_mbox = tg3_write32_mbox_5906;
10768 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10769 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10770 }
6892914f 10771
bbadf503
MC		 10772 if (tp->write32 == tg3_write_indirect_reg32 ||
10773 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10774 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 10775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 10776 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10777
7d0c41ef 10778 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 10779 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 10780 * determined before calling tg3_set_power_state() so that
10781 * we know whether or not to switch out of Vaux power.
10782 * When the flag is set, it means that GPIO1 is used for eeprom
10783 * write protect and also implies that it is a LOM where GPIOs
10784 * are not used to switch power.
6aa20a22 10785 */
7d0c41ef
MC		 10786 tg3_get_eeprom_hw_cfg(tp);
10787
314fba34
MC		 10788 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10789 * GPIO1 driven high will bring 5700's external PHY out of reset.
10790 * It is also used as eeprom write protect on LOMs.
10791 */
10792 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10793 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10794 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10795 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10796 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 10797 /* Unused GPIO3 must be driven as output on 5752 because there
10798 * are no pull-up resistors on unused GPIO pins.
10799 */
10800 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10801 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 10802
af36e6b6
MC		 10803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10804 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10805
1da177e4 10806 /* Force the chip into D0. */
bc1c7567 10807 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 10808 if (err) {
10809 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10810 pci_name(tp->pdev));
10811 return err;
10812 }
10813
10814 /* 5700 B0 chips do not support checksumming correctly due
10815 * to hardware bugs.
10816 */
10817 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10818 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10819
1da177e4
LT		 10820 /* Derive initial jumbo mode from MTU assigned in
10821 * ether_setup() via the alloc_etherdev() call
10822 */
0f893dc6 10823 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 10824 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 10825 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 10826
10827 /* Determine WakeOnLan speed to use. */
10828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10829 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10830 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10831 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10832 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10833 } else {
10834 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10835 }
10836
10837 /* A few boards don't want Ethernet@WireSpeed phy feature */
10838 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10839 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10840 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 10841 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 10842 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 10843 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 10844 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10845
10846 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10847 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10848 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10849 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10850 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10851
c424cb24
MC		 10852 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
c1d2a196 10854 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
d4011ada
MC		 10855 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10856 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10857 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 10858 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10859 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10860 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
c424cb24
MC		 10861 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10862 }
1da177e4 10863
1da177e4 10864 tp->coalesce_mode = 0;
1da177e4
LT		 10865 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10866 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10867 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10868
10869 /* Initialize MAC MI mode, polling disabled. */
10870 tw32_f(MAC_MI_MODE, tp->mi_mode);
10871 udelay(80);
10872
10873 /* Initialize data/descriptor byte/word swapping. */
10874 val = tr32(GRC_MODE);
10875 val &= GRC_MODE_HOST_STACKUP;
10876 tw32(GRC_MODE, val | tp->grc_mode);
10877
10878 tg3_switch_clocks(tp);
10879
10880 /* Clear this out for sanity. */
10881 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10882
10883 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10884 &pci_state_reg);
10885 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10886 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10887 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10888
10889 if (chiprevid == CHIPREV_ID_5701_A0 ||
10890 chiprevid == CHIPREV_ID_5701_B0 ||
10891 chiprevid == CHIPREV_ID_5701_B2 ||
10892 chiprevid == CHIPREV_ID_5701_B5) {
10893 void __iomem *sram_base;
10894
10895 /* Write some dummy words into the SRAM status block
10896 * area, see if it reads back correctly. If the return
10897 * value is bad, force enable the PCIX workaround.
10898 */
10899 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10900
10901 writel(0x00000000, sram_base);
10902 writel(0x00000000, sram_base + 4);
10903 writel(0xffffffff, sram_base + 4);
10904 if (readl(sram_base) != 0x00000000)
10905 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10906 }
10907 }
10908
10909 udelay(50);
10910 tg3_nvram_init(tp);
10911
10912 grc_misc_cfg = tr32(GRC_MISC_CFG);
10913 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10914
1da177e4
LT		 10915 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10916 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10917 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10918 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10919
fac9b83e
DM		 10920 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10921 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10922 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10923 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10924 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10925 HOSTCC_MODE_CLRTICK_TXBD);
10926
10927 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10928 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10929 tp->misc_host_ctrl);
10930 }
10931
1da177e4
LT		 10932 /* these are limited to 10/100 only */
10933 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10934 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10935 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10936 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10937 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10938 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10939 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10940 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10941 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 10942 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10943 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
b5d3772c 10944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 10945 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10946
10947 err = tg3_phy_probe(tp);
10948 if (err) {
10949 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10950 pci_name(tp->pdev), err);
10951 /* ... but do not return immediately ... */
10952 }
10953
10954 tg3_read_partno(tp);
c4e6575c 10955 tg3_read_fw_ver(tp);
1da177e4
LT		 10956
10957 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10958 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10959 } else {
10960 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10961 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10962 else
10963 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10964 }
10965
10966 /* 5700 {AX,BX} chips have a broken status block link
10967 * change bit implementation, so we must use the
10968 * status register in those cases.
10969 */
10970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10971 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10972 else
10973 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10974
10975 /* The led_ctrl is set during tg3_phy_probe, here we might
10976 * have to force the link status polling mechanism based
10977 * upon subsystem IDs.
10978 */
10979 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10980 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10981 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10982 TG3_FLAG_USE_LINKCHG_REG);
10983 }
10984
10985 /* For all SERDES we poll the MAC status register. */
10986 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10987 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10988 else
10989 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10990
5a6f3074 10991 /* All chips before 5787 can get confused if TX buffers
1da177e4
LT		 10992 * straddle the 4GB address boundary in some cases.
10993 */
af36e6b6 10994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
b5d3772c
MC		 10995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
5a6f3074
MC		 10997 tp->dev->hard_start_xmit = tg3_start_xmit;
10998 else
10999 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
1da177e4
LT		 11000
11001 tp->rx_offset = 2;
11002 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11003 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11004 tp->rx_offset = 0;
11005
f92905de
MC		 11006 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11007
11008 /* Increment the rx prod index on the rx std ring by at most
11009 * 8 for these chips to workaround hw errata.
11010 */
11011 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11012 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11014 tp->rx_std_max_post = 8;
11015
1da177e4
LT		 11016 /* By default, disable wake-on-lan. User can change this
11017 * using ETHTOOL_SWOL.
11018 */
11019 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11020
8ed5d97e
MC		 11021 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11022 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11023 PCIE_PWR_MGMT_L1_THRESH_MSK;
11024
1da177e4
LT		 11025 return err;
11026}
11027
49b6e95f 11028#ifdef CONFIG_SPARC
1da177e4
LT		 11029static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11030{
11031 struct net_device *dev = tp->dev;
11032 struct pci_dev *pdev = tp->pdev;
49b6e95f 11033 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 11034 const unsigned char *addr;
49b6e95f
DM		 11035 int len;
11036
11037 addr = of_get_property(dp, "local-mac-address", &len);
11038 if (addr && len == 6) {
11039 memcpy(dev->dev_addr, addr, 6);
11040 memcpy(dev->perm_addr, dev->dev_addr, 6);
11041 return 0;
1da177e4
LT		 11042 }
11043 return -ENODEV;
11044}
11045
11046static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11047{
11048 struct net_device *dev = tp->dev;
11049
11050 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 11051 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 11052 return 0;
11053}
11054#endif
11055
11056static int __devinit tg3_get_device_address(struct tg3 *tp)
11057{
11058 struct net_device *dev = tp->dev;
11059 u32 hi, lo, mac_offset;
008652b3 11060 int addr_ok = 0;
1da177e4 11061
49b6e95f 11062#ifdef CONFIG_SPARC
1da177e4
LT		 11063 if (!tg3_get_macaddr_sparc(tp))
11064 return 0;
11065#endif
11066
11067 mac_offset = 0x7c;
f49639e6 11068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 11069 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 11070 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11071 mac_offset = 0xcc;
11072 if (tg3_nvram_lock(tp))
11073 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11074 else
11075 tg3_nvram_unlock(tp);
11076 }
b5d3772c
MC		 11077 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11078 mac_offset = 0x10;
1da177e4
LT		 11079
11080 /* First try to get it from MAC address mailbox. */
11081 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11082 if ((hi >> 16) == 0x484b) {
11083 dev->dev_addr[0] = (hi >> 8) & 0xff;
11084 dev->dev_addr[1] = (hi >> 0) & 0xff;
11085
11086 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11087 dev->dev_addr[2] = (lo >> 24) & 0xff;
11088 dev->dev_addr[3] = (lo >> 16) & 0xff;
11089 dev->dev_addr[4] = (lo >> 8) & 0xff;
11090 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 11091
008652b3
MC		 11092 /* Some old bootcode may report a 0 MAC address in SRAM */
11093 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11094 }
11095 if (!addr_ok) {
11096 /* Next, try NVRAM. */
f49639e6 11097 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 11098 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11099 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11100 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11101 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11102 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11103 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11104 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11105 }
11106 /* Finally just fetch it out of the MAC control regs. */
11107 else {
11108 hi = tr32(MAC_ADDR_0_HIGH);
11109 lo = tr32(MAC_ADDR_0_LOW);
11110
11111 dev->dev_addr[5] = lo & 0xff;
11112 dev->dev_addr[4] = (lo >> 8) & 0xff;
11113 dev->dev_addr[3] = (lo >> 16) & 0xff;
11114 dev->dev_addr[2] = (lo >> 24) & 0xff;
11115 dev->dev_addr[1] = hi & 0xff;
11116 dev->dev_addr[0] = (hi >> 8) & 0xff;
11117 }
1da177e4
LT		 11118 }
11119
11120 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11121#ifdef CONFIG_SPARC64
11122 if (!tg3_get_default_macaddr_sparc(tp))
11123 return 0;
11124#endif
11125 return -EINVAL;
11126 }
2ff43697 11127 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 11128 return 0;
11129}
11130
59e6b434
DM		 11131#define BOUNDARY_SINGLE_CACHELINE 1
11132#define BOUNDARY_MULTI_CACHELINE 2
11133
11134static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11135{
11136 int cacheline_size;
11137 u8 byte;
11138 int goal;
11139
11140 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11141 if (byte == 0)
11142 cacheline_size = 1024;
11143 else
11144 cacheline_size = (int) byte * 4;
11145
11146 /* On 5703 and later chips, the boundary bits have no
11147 * effect.
11148 */
11149 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11150 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11151 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11152 goto out;
11153
11154#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11155 goal = BOUNDARY_MULTI_CACHELINE;
11156#else
11157#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11158 goal = BOUNDARY_SINGLE_CACHELINE;
11159#else
11160 goal = 0;
11161#endif
11162#endif
11163
11164 if (!goal)
11165 goto out;
11166
11167 /* PCI controllers on most RISC systems tend to disconnect
11168 * when a device tries to burst across a cache-line boundary.
11169 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11170 *
11171 * Unfortunately, for PCI-E there are only limited
11172 * write-side controls for this, and thus for reads
11173 * we will still get the disconnects. We'll also waste
11174 * these PCI cycles for both read and write for chips
11175 * other than 5700 and 5701 which do not implement the
11176 * boundary bits.
11177 */
11178 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11179 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11180 switch (cacheline_size) {
11181 case 16:
11182 case 32:
11183 case 64:
11184 case 128:
11185 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11186 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11187 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11188 } else {
11189 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11190 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11191 }
11192 break;
11193
11194 case 256:
11195 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11196 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11197 break;
11198
11199 default:
11200 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11201 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11202 break;
11203 };
11204 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11205 switch (cacheline_size) {
11206 case 16:
11207 case 32:
11208 case 64:
11209 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11210 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11211 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11212 break;
11213 }
11214 /* fallthrough */
11215 case 128:
11216 default:
11217 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11218 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11219 break;
11220 };
11221 } else {
11222 switch (cacheline_size) {
11223 case 16:
11224 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11225 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11226 DMA_RWCTRL_WRITE_BNDRY_16);
11227 break;
11228 }
11229 /* fallthrough */
11230 case 32:
11231 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11232 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11233 DMA_RWCTRL_WRITE_BNDRY_32);
11234 break;
11235 }
11236 /* fallthrough */
11237 case 64:
11238 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11239 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11240 DMA_RWCTRL_WRITE_BNDRY_64);
11241 break;
11242 }
11243 /* fallthrough */
11244 case 128:
11245 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11246 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11247 DMA_RWCTRL_WRITE_BNDRY_128);
11248 break;
11249 }
11250 /* fallthrough */
11251 case 256:
11252 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11253 DMA_RWCTRL_WRITE_BNDRY_256);
11254 break;
11255 case 512:
11256 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11257 DMA_RWCTRL_WRITE_BNDRY_512);
11258 break;
11259 case 1024:
11260 default:
11261 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11262 DMA_RWCTRL_WRITE_BNDRY_1024);
11263 break;
11264 };
11265 }
11266
11267out:
11268 return val;
11269}
11270
1da177e4
LT		 11271static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11272{
11273 struct tg3_internal_buffer_desc test_desc;
11274 u32 sram_dma_descs;
11275 int i, ret;
11276
11277 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11278
11279 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11280 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11281 tw32(RDMAC_STATUS, 0);
11282 tw32(WDMAC_STATUS, 0);
11283
11284 tw32(BUFMGR_MODE, 0);
11285 tw32(FTQ_RESET, 0);
11286
11287 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11288 test_desc.addr_lo = buf_dma & 0xffffffff;
11289 test_desc.nic_mbuf = 0x00002100;
11290 test_desc.len = size;
11291
11292 /*
11293 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11294 * the *second* time the tg3 driver was getting loaded after an
11295 * initial scan.
11296 *
11297 * Broadcom tells me:
11298 * ...the DMA engine is connected to the GRC block and a DMA
11299 * reset may affect the GRC block in some unpredictable way...
11300 * The behavior of resets to individual blocks has not been tested.
11301 *
11302 * Broadcom noted the GRC reset will also reset all sub-components.
11303 */
11304 if (to_device) {
11305 test_desc.cqid_sqid = (13 << 8) | 2;
11306
11307 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11308 udelay(40);
11309 } else {
11310 test_desc.cqid_sqid = (16 << 8) | 7;
11311
11312 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11313 udelay(40);
11314 }
11315 test_desc.flags = 0x00000005;
11316
11317 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11318 u32 val;
11319
11320 val = *(((u32 *)&test_desc) + i);
11321 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11322 sram_dma_descs + (i * sizeof(u32)));
11323 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11324 }
11325 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11326
11327 if (to_device) {
11328 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11329 } else {
11330 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11331 }
11332
11333 ret = -ENODEV;
11334 for (i = 0; i < 40; i++) {
11335 u32 val;
11336
11337 if (to_device)
11338 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11339 else
11340 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11341 if ((val & 0xffff) == sram_dma_descs) {
11342 ret = 0;
11343 break;
11344 }
11345
11346 udelay(100);
11347 }
11348
11349 return ret;
11350}
11351
ded7340d 11352#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 11353
11354static int __devinit tg3_test_dma(struct tg3 *tp)
11355{
11356 dma_addr_t buf_dma;
59e6b434 11357 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 11358 int ret;
11359
11360 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11361 if (!buf) {
11362 ret = -ENOMEM;
11363 goto out_nofree;
11364 }
11365
11366 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11367 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11368
59e6b434 11369 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 11370
11371 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11372 /* DMA read watermark not used on PCIE */
11373 tp->dma_rwctrl |= 0x00180000;
11374 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 11375 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 11377 tp->dma_rwctrl |= 0x003f0000;
11378 else
11379 tp->dma_rwctrl |= 0x003f000f;
11380 } else {
11381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11382 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11383 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 11384 u32 read_water = 0x7;
1da177e4 11385
4a29cc2e
MC		 11386 /* If the 5704 is behind the EPB bridge, we can
11387 * do the less restrictive ONE_DMA workaround for
11388 * better performance.
11389 */
11390 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11392 tp->dma_rwctrl |= 0x8000;
11393 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 11394 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11395
49afdeb6
MC		 11396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11397 read_water = 4;
59e6b434 11398 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 11399 tp->dma_rwctrl |=
11400 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11401 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11402 (1 << 23);
4cf78e4f
MC		 11403 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11404 /* 5780 always in PCIX mode */
11405 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 11406 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11407 /* 5714 always in PCIX mode */
11408 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 11409 } else {
11410 tp->dma_rwctrl |= 0x001b000f;
11411 }
11412 }
11413
11414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11415 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11416 tp->dma_rwctrl &= 0xfffffff0;
11417
11418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11420 /* Remove this if it causes problems for some boards. */
11421 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11422
11423 /* On 5700/5701 chips, we need to set this bit.
11424 * Otherwise the chip will issue cacheline transactions
11425 * to streamable DMA memory with not all the byte
11426 * enables turned on. This is an error on several
11427 * RISC PCI controllers, in particular sparc64.
11428 *
11429 * On 5703/5704 chips, this bit has been reassigned
11430 * a different meaning. In particular, it is used
11431 * on those chips to enable a PCI-X workaround.
11432 */
11433 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11434 }
11435
11436 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11437
11438#if 0
11439 /* Unneeded, already done by tg3_get_invariants. */
11440 tg3_switch_clocks(tp);
11441#endif
11442
11443 ret = 0;
11444 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11445 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11446 goto out;
11447
59e6b434
DM		 11448 /* It is best to perform DMA test with maximum write burst size
11449 * to expose the 5700/5701 write DMA bug.
11450 */
11451 saved_dma_rwctrl = tp->dma_rwctrl;
11452 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11453 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11454
1da177e4
LT		 11455 while (1) {
11456 u32 *p = buf, i;
11457
11458 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11459 p[i] = i;
11460
11461 /* Send the buffer to the chip. */
11462 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11463 if (ret) {
11464 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11465 break;
11466 }
11467
11468#if 0
11469 /* validate data reached card RAM correctly. */
11470 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11471 u32 val;
11472 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11473 if (le32_to_cpu(val) != p[i]) {
11474 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11475 /* ret = -ENODEV here? */
11476 }
11477 p[i] = 0;
11478 }
11479#endif
11480 /* Now read it back. */
11481 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11482 if (ret) {
11483 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11484
11485 break;
11486 }
11487
11488 /* Verify it. */
11489 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11490 if (p[i] == i)
11491 continue;
11492
59e6b434
DM		 11493 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11494 DMA_RWCTRL_WRITE_BNDRY_16) {
11495 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 11496 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11497 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11498 break;
11499 } else {
11500 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11501 ret = -ENODEV;
11502 goto out;
11503 }
11504 }
11505
11506 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11507 /* Success. */
11508 ret = 0;
11509 break;
11510 }
11511 }
59e6b434
DM		 11512 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11513 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 11514 static struct pci_device_id dma_wait_state_chipsets[] = {
11515 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11516 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11517 { },
11518 };
11519
59e6b434 11520 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 11521 * now look for chipsets that are known to expose the
11522 * DMA bug without failing the test.
59e6b434 11523 */
6d1cfbab
MC		 11524 if (pci_dev_present(dma_wait_state_chipsets)) {
11525 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11526 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11527 }
11528 else
11529 /* Safe to use the calculated DMA boundary. */
11530 tp->dma_rwctrl = saved_dma_rwctrl;
11531
59e6b434
DM		 11532 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11533 }
1da177e4
LT		 11534
11535out:
11536 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11537out_nofree:
11538 return ret;
11539}
11540
11541static void __devinit tg3_init_link_config(struct tg3 *tp)
11542{
11543 tp->link_config.advertising =
11544 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11545 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11546 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11547 ADVERTISED_Autoneg | ADVERTISED_MII);
11548 tp->link_config.speed = SPEED_INVALID;
11549 tp->link_config.duplex = DUPLEX_INVALID;
11550 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 11551 tp->link_config.active_speed = SPEED_INVALID;
11552 tp->link_config.active_duplex = DUPLEX_INVALID;
11553 tp->link_config.phy_is_low_power = 0;
11554 tp->link_config.orig_speed = SPEED_INVALID;
11555 tp->link_config.orig_duplex = DUPLEX_INVALID;
11556 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11557}
11558
11559static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11560{
fdfec172
MC		 11561 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11562 tp->bufmgr_config.mbuf_read_dma_low_water =
11563 DEFAULT_MB_RDMA_LOW_WATER_5705;
11564 tp->bufmgr_config.mbuf_mac_rx_low_water =
11565 DEFAULT_MB_MACRX_LOW_WATER_5705;
11566 tp->bufmgr_config.mbuf_high_water =
11567 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 11568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11569 tp->bufmgr_config.mbuf_mac_rx_low_water =
11570 DEFAULT_MB_MACRX_LOW_WATER_5906;
11571 tp->bufmgr_config.mbuf_high_water =
11572 DEFAULT_MB_HIGH_WATER_5906;
11573 }
fdfec172
MC		 11574
11575 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11576 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11577 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11578 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11579 tp->bufmgr_config.mbuf_high_water_jumbo =
11580 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11581 } else {
11582 tp->bufmgr_config.mbuf_read_dma_low_water =
11583 DEFAULT_MB_RDMA_LOW_WATER;
11584 tp->bufmgr_config.mbuf_mac_rx_low_water =
11585 DEFAULT_MB_MACRX_LOW_WATER;
11586 tp->bufmgr_config.mbuf_high_water =
11587 DEFAULT_MB_HIGH_WATER;
11588
11589 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11590 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11591 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11592 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11593 tp->bufmgr_config.mbuf_high_water_jumbo =
11594 DEFAULT_MB_HIGH_WATER_JUMBO;
11595 }
1da177e4
LT		 11596
11597 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11598 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11599}
11600
11601static char * __devinit tg3_phy_string(struct tg3 *tp)
11602{
11603 switch (tp->phy_id & PHY_ID_MASK) {
11604 case PHY_ID_BCM5400: return "5400";
11605 case PHY_ID_BCM5401: return "5401";
11606 case PHY_ID_BCM5411: return "5411";
11607 case PHY_ID_BCM5701: return "5701";
11608 case PHY_ID_BCM5703: return "5703";
11609 case PHY_ID_BCM5704: return "5704";
11610 case PHY_ID_BCM5705: return "5705";
11611 case PHY_ID_BCM5750: return "5750";
85e94ced 11612 case PHY_ID_BCM5752: return "5752";
a4e2b347 11613 case PHY_ID_BCM5714: return "5714";
4cf78e4f 11614 case PHY_ID_BCM5780: return "5780";
af36e6b6 11615 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 11616 case PHY_ID_BCM5787: return "5787";
126a3368 11617 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 11618 case PHY_ID_BCM5906: return "5906";
1da177e4
LT		 11619 case PHY_ID_BCM8002: return "8002/serdes";
11620 case 0: return "serdes";
11621 default: return "unknown";
11622 };
11623}
11624
f9804ddb
MC		 11625static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11626{
11627 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11628 strcpy(str, "PCI Express");
11629 return str;
11630 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11631 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11632
11633 strcpy(str, "PCIX:");
11634
11635 if ((clock_ctrl == 7) ||
11636 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11637 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11638 strcat(str, "133MHz");
11639 else if (clock_ctrl == 0)
11640 strcat(str, "33MHz");
11641 else if (clock_ctrl == 2)
11642 strcat(str, "50MHz");
11643 else if (clock_ctrl == 4)
11644 strcat(str, "66MHz");
11645 else if (clock_ctrl == 6)
11646 strcat(str, "100MHz");
f9804ddb
MC		 11647 } else {
11648 strcpy(str, "PCI:");
11649 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11650 strcat(str, "66MHz");
11651 else
11652 strcat(str, "33MHz");
11653 }
11654 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11655 strcat(str, ":32-bit");
11656 else
11657 strcat(str, ":64-bit");
11658 return str;
11659}
11660
8c2dc7e1 11661static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 11662{
11663 struct pci_dev *peer;
11664 unsigned int func, devnr = tp->pdev->devfn & ~7;
11665
11666 for (func = 0; func < 8; func++) {
11667 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11668 if (peer && peer != tp->pdev)
11669 break;
11670 pci_dev_put(peer);
11671 }
16fe9d74
MC		 11672 /* 5704 can be configured in single-port mode, set peer to
11673 * tp->pdev in that case.
11674 */
11675 if (!peer) {
11676 peer = tp->pdev;
11677 return peer;
11678 }
1da177e4
LT		 11679
11680 /*
11681 * We don't need to keep the refcount elevated; there's no way
11682 * to remove one half of this device without removing the other
11683 */
11684 pci_dev_put(peer);
11685
11686 return peer;
11687}
11688
15f9850d
DM		 11689static void __devinit tg3_init_coal(struct tg3 *tp)
11690{
11691 struct ethtool_coalesce *ec = &tp->coal;
11692
11693 memset(ec, 0, sizeof(*ec));
11694 ec->cmd = ETHTOOL_GCOALESCE;
11695 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11696 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11697 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11698 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11699 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11700 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11701 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11702 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11703 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11704
11705 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11706 HOSTCC_MODE_CLRTICK_TXBD)) {
11707 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11708 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11709 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11710 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11711 }
d244c892
MC		 11712
11713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11714 ec->rx_coalesce_usecs_irq = 0;
11715 ec->tx_coalesce_usecs_irq = 0;
11716 ec->stats_block_coalesce_usecs = 0;
11717 }
15f9850d
DM		 11718}
11719
1da177e4
LT		 11720static int __devinit tg3_init_one(struct pci_dev *pdev,
11721 const struct pci_device_id *ent)
11722{
11723 static int tg3_version_printed = 0;
11724 unsigned long tg3reg_base, tg3reg_len;
11725 struct net_device *dev;
11726 struct tg3 *tp;
72f2afb8 11727 int i, err, pm_cap;
f9804ddb 11728 char str[40];
72f2afb8 11729 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 11730
11731 if (tg3_version_printed++ == 0)
11732 printk(KERN_INFO "%s", version);
11733
11734 err = pci_enable_device(pdev);
11735 if (err) {
11736 printk(KERN_ERR PFX "Cannot enable PCI device, "
11737 "aborting.\n");
11738 return err;
11739 }
11740
11741 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11742 printk(KERN_ERR PFX "Cannot find proper PCI device "
11743 "base address, aborting.\n");
11744 err = -ENODEV;
11745 goto err_out_disable_pdev;
11746 }
11747
11748 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11749 if (err) {
11750 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11751 "aborting.\n");
11752 goto err_out_disable_pdev;
11753 }
11754
11755 pci_set_master(pdev);
11756
11757 /* Find power-management capability. */
11758 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11759 if (pm_cap == 0) {
11760 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11761 "aborting.\n");
11762 err = -EIO;
11763 goto err_out_free_res;
11764 }
11765
1da177e4
LT		 11766 tg3reg_base = pci_resource_start(pdev, 0);
11767 tg3reg_len = pci_resource_len(pdev, 0);
11768
11769 dev = alloc_etherdev(sizeof(*tp));
11770 if (!dev) {
11771 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11772 err = -ENOMEM;
11773 goto err_out_free_res;
11774 }
11775
11776 SET_MODULE_OWNER(dev);
11777 SET_NETDEV_DEV(dev, &pdev->dev);
11778
1da177e4
LT		 11779#if TG3_VLAN_TAG_USED
11780 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11781 dev->vlan_rx_register = tg3_vlan_rx_register;
11782 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11783#endif
11784
11785 tp = netdev_priv(dev);
11786 tp->pdev = pdev;
11787 tp->dev = dev;
11788 tp->pm_cap = pm_cap;
11789 tp->mac_mode = TG3_DEF_MAC_MODE;
11790 tp->rx_mode = TG3_DEF_RX_MODE;
11791 tp->tx_mode = TG3_DEF_TX_MODE;
11792 tp->mi_mode = MAC_MI_MODE_BASE;
11793 if (tg3_debug > 0)
11794 tp->msg_enable = tg3_debug;
11795 else
11796 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11797
11798 /* The word/byte swap controls here control register access byte
11799 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11800 * setting below.
11801 */
11802 tp->misc_host_ctrl =
11803 MISC_HOST_CTRL_MASK_PCI_INT |
11804 MISC_HOST_CTRL_WORD_SWAP |
11805 MISC_HOST_CTRL_INDIR_ACCESS |
11806 MISC_HOST_CTRL_PCISTATE_RW;
11807
11808 /* The NONFRM (non-frame) byte/word swap controls take effect
11809 * on descriptor entries, anything which isn't packet data.
11810 *
11811 * The StrongARM chips on the board (one for tx, one for rx)
11812 * are running in big-endian mode.
11813 */
11814 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11815 GRC_MODE_WSWAP_NONFRM_DATA);
11816#ifdef __BIG_ENDIAN
11817 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11818#endif
11819 spin_lock_init(&tp->lock);
1da177e4 11820 spin_lock_init(&tp->indirect_lock);
c4028958 11821 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4
LT		 11822
11823 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11824 if (tp->regs == 0UL) {
11825 printk(KERN_ERR PFX "Cannot map device registers, "
11826 "aborting.\n");
11827 err = -ENOMEM;
11828 goto err_out_free_dev;
11829 }
11830
11831 tg3_init_link_config(tp);
11832
1da177e4
LT		 11833 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11834 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11835 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11836
11837 dev->open = tg3_open;
11838 dev->stop = tg3_close;
11839 dev->get_stats = tg3_get_stats;
11840 dev->set_multicast_list = tg3_set_rx_mode;
11841 dev->set_mac_address = tg3_set_mac_addr;
11842 dev->do_ioctl = tg3_ioctl;
11843 dev->tx_timeout = tg3_tx_timeout;
11844 dev->poll = tg3_poll;
11845 dev->ethtool_ops = &tg3_ethtool_ops;
11846 dev->weight = 64;
11847 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11848 dev->change_mtu = tg3_change_mtu;
11849 dev->irq = pdev->irq;
11850#ifdef CONFIG_NET_POLL_CONTROLLER
11851 dev->poll_controller = tg3_poll_controller;
11852#endif
11853
11854 err = tg3_get_invariants(tp);
11855 if (err) {
11856 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11857 "aborting.\n");
11858 goto err_out_iounmap;
11859 }
11860
4a29cc2e
MC		 11861 /* The EPB bridge inside 5714, 5715, and 5780 and any
11862 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 11863 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11864 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11865 * do DMA address check in tg3_start_xmit().
11866 */
4a29cc2e
MC		 11867 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11868 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11869 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 11870 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11871#ifdef CONFIG_HIGHMEM
11872 dma_mask = DMA_64BIT_MASK;
11873#endif
4a29cc2e 11874 } else
72f2afb8
MC		 11875 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11876
11877 /* Configure DMA attributes. */
11878 if (dma_mask > DMA_32BIT_MASK) {
11879 err = pci_set_dma_mask(pdev, dma_mask);
11880 if (!err) {
11881 dev->features |= NETIF_F_HIGHDMA;
11882 err = pci_set_consistent_dma_mask(pdev,
11883 persist_dma_mask);
11884 if (err < 0) {
11885 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11886 "DMA for consistent allocations\n");
11887 goto err_out_iounmap;
11888 }
11889 }
11890 }
11891 if (err || dma_mask == DMA_32BIT_MASK) {
11892 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11893 if (err) {
11894 printk(KERN_ERR PFX "No usable DMA configuration, "
11895 "aborting.\n");
11896 goto err_out_iounmap;
11897 }
11898 }
11899
fdfec172 11900 tg3_init_bufmgr_config(tp);
1da177e4 11901
1da177e4
LT		 11902 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11903 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11904 }
11905 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11907 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 11908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 11909 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11910 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11911 } else {
7f62ad5d 11912 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
1da177e4
LT		 11913 }
11914
4e3a7aaa
MC		 11915 /* TSO is on by default on chips that support hardware TSO.
11916 * Firmware TSO on older chips gives lower performance, so it
11917 * is off by default, but can be enabled using ethtool.
11918 */
b0026624 11919 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
1da177e4 11920 dev->features |= NETIF_F_TSO;
b5d3772c
MC		 11921 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11922 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
b0026624
MC		 11923 dev->features |= NETIF_F_TSO6;
11924 }
1da177e4 11925
1da177e4
LT		 11926
11927 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11928 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11929 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11930 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11931 tp->rx_pending = 63;
11932 }
11933
1da177e4
LT		 11934 err = tg3_get_device_address(tp);
11935 if (err) {
11936 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11937 "aborting.\n");
11938 goto err_out_iounmap;
11939 }
11940
11941 /*
11942 * Reset chip in case UNDI or EFI driver did not shutdown
11943 * DMA self test will enable WDMAC and we'll see (spurious)
11944 * pending DMA on the PCI bus at that point.
11945 */
11946 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11947 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11948 pci_save_state(tp->pdev);
11949 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 11950 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 11951 }
11952
11953 err = tg3_test_dma(tp);
11954 if (err) {
11955 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11956 goto err_out_iounmap;
11957 }
11958
11959 /* Tigon3 can do ipv4 only... and some chips have buggy
11960 * checksumming.
11961 */
11962 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
af36e6b6
MC		 11963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9c27dbdf
MC		 11965 dev->features |= NETIF_F_HW_CSUM;
11966 else
11967 dev->features |= NETIF_F_IP_CSUM;
11968 dev->features |= NETIF_F_SG;
1da177e4
LT		 11969 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11970 } else
11971 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11972
1da177e4
LT		 11973 /* flow control autonegotiation is default behavior */
11974 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11975
15f9850d
DM		 11976 tg3_init_coal(tp);
11977
7d3f4c97
DM		 11978 /* Now that we have fully setup the chip, save away a snapshot
11979 * of the PCI config space. We need to restore this after
11980 * GRC_MISC_CFG core clock resets and some resume events.
11981 */
11982 pci_save_state(tp->pdev);
11983
c49a1561
MC		 11984 pci_set_drvdata(pdev, dev);
11985
1da177e4
LT		 11986 err = register_netdev(dev);
11987 if (err) {
11988 printk(KERN_ERR PFX "Cannot register net device, "
11989 "aborting.\n");
11990 goto err_out_iounmap;
11991 }
11992
cbb45d21 11993 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
1da177e4
LT		 11994 dev->name,
11995 tp->board_part_number,
11996 tp->pci_chip_rev_id,
11997 tg3_phy_string(tp),
f9804ddb 11998 tg3_bus_string(tp, str),
cbb45d21
MC		 11999 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12000 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12001 "10/100/1000Base-T")));
1da177e4
LT		 12002
12003 for (i = 0; i < 6; i++)
12004 printk("%2.2x%c", dev->dev_addr[i],
12005 i == 5 ? '\n' : ':');
12006
12007 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
1c46ae05 12008 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
1da177e4
LT		 12009 dev->name,
12010 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12011 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12012 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12013 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4
LT		 12014 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12015 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 12016 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12017 dev->name, tp->dma_rwctrl,
12018 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12019 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 12020
12021 return 0;
12022
12023err_out_iounmap:
6892914f
MC		 12024 if (tp->regs) {
12025 iounmap(tp->regs);
22abe310 12026 tp->regs = NULL;
6892914f 12027 }
1da177e4
LT		 12028
12029err_out_free_dev:
12030 free_netdev(dev);
12031
12032err_out_free_res:
12033 pci_release_regions(pdev);
12034
12035err_out_disable_pdev:
12036 pci_disable_device(pdev);
12037 pci_set_drvdata(pdev, NULL);
12038 return err;
12039}
12040
12041static void __devexit tg3_remove_one(struct pci_dev *pdev)
12042{
12043 struct net_device *dev = pci_get_drvdata(pdev);
12044
12045 if (dev) {
12046 struct tg3 *tp = netdev_priv(dev);
12047
7faa006f 12048 flush_scheduled_work();
1da177e4 12049 unregister_netdev(dev);
6892914f
MC		 12050 if (tp->regs) {
12051 iounmap(tp->regs);
22abe310 12052 tp->regs = NULL;
6892914f 12053 }
1da177e4
LT		 12054 free_netdev(dev);
12055 pci_release_regions(pdev);
12056 pci_disable_device(pdev);
12057 pci_set_drvdata(pdev, NULL);
12058 }
12059}
12060
12061static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12062{
12063 struct net_device *dev = pci_get_drvdata(pdev);
12064 struct tg3 *tp = netdev_priv(dev);
12065 int err;
12066
12067 if (!netif_running(dev))
12068 return 0;
12069
7faa006f 12070 flush_scheduled_work();
1da177e4
LT		 12071 tg3_netif_stop(tp);
12072
12073 del_timer_sync(&tp->timer);
12074
f47c11ee 12075 tg3_full_lock(tp, 1);
1da177e4 12076 tg3_disable_ints(tp);
f47c11ee 12077 tg3_full_unlock(tp);
1da177e4
LT		 12078
12079 netif_device_detach(dev);
12080
f47c11ee 12081 tg3_full_lock(tp, 0);
944d980e 12082 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 12083 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 12084 tg3_full_unlock(tp);
1da177e4 12085
436f1379
MC		 12086 /* Save MSI address and data for resume. */
12087 pci_save_state(pdev);
12088
1da177e4
LT		 12089 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12090 if (err) {
f47c11ee 12091 tg3_full_lock(tp, 0);
1da177e4 12092
6a9eba15 12093 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12094 if (tg3_restart_hw(tp, 1))
12095 goto out;
1da177e4
LT		 12096
12097 tp->timer.expires = jiffies + tp->timer_offset;
12098 add_timer(&tp->timer);
12099
12100 netif_device_attach(dev);
12101 tg3_netif_start(tp);
12102
b9ec6c1b 12103out:
f47c11ee 12104 tg3_full_unlock(tp);
1da177e4
LT		 12105 }
12106
12107 return err;
12108}
12109
12110static int tg3_resume(struct pci_dev *pdev)
12111{
12112 struct net_device *dev = pci_get_drvdata(pdev);
12113 struct tg3 *tp = netdev_priv(dev);
12114 int err;
12115
12116 if (!netif_running(dev))
12117 return 0;
12118
12119 pci_restore_state(tp->pdev);
12120
bc1c7567 12121 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12122 if (err)
12123 return err;
12124
12125 netif_device_attach(dev);
12126
f47c11ee 12127 tg3_full_lock(tp, 0);
1da177e4 12128
6a9eba15 12129 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 12130 err = tg3_restart_hw(tp, 1);
12131 if (err)
12132 goto out;
1da177e4
LT		 12133
12134 tp->timer.expires = jiffies + tp->timer_offset;
12135 add_timer(&tp->timer);
12136
1da177e4
LT		 12137 tg3_netif_start(tp);
12138
b9ec6c1b 12139out:
f47c11ee 12140 tg3_full_unlock(tp);
1da177e4 12141
b9ec6c1b 12142 return err;
1da177e4
LT		 12143}
12144
12145static struct pci_driver tg3_driver = {
12146 .name = DRV_MODULE_NAME,
12147 .id_table = tg3_pci_tbl,
12148 .probe = tg3_init_one,
12149 .remove = __devexit_p(tg3_remove_one),
12150 .suspend = tg3_suspend,
12151 .resume = tg3_resume
12152};
12153
12154static int __init tg3_init(void)
12155{
29917620 12156 return pci_register_driver(&tg3_driver);
1da177e4
LT		 12157}
12158
12159static void __exit tg3_cleanup(void)
12160{
12161 pci_unregister_driver(&tg3_driver);
12162}
12163
12164module_init(tg3_init);
12165module_exit(tg3_cleanup);
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