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tg3: Refine tg3_vlan_rx_register()
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
d3d31709
MC		 71#define DRV_MODULE_VERSION "3.97"
72#define DRV_MODULE_RELDATE "December 10, 2008"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
0f893dc6 95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131/* minimum number of free TX descriptors required to wake up TX process */
42952231 132#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 133
ad829268
MC		 134#define TG3_RAW_IP_ALIGN 2
135
1da177e4
LT		 136/* number of ETHTOOL_GSTATS u64's */
137#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
4cafd3f5
MC		 139#define TG3_NUM_TEST 6
140
077f849d
JSR		 141#define FIRMWARE_TG3 "tigon/tg3.bin"
142#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
1da177e4
LT		 145static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150MODULE_LICENSE("GPL");
151MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 152MODULE_FIRMWARE(FIRMWARE_TG3);
153MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
1da177e4
LT		 156
157static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158module_param(tg3_debug, int, 0);
159MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
57e6983c 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
321d32a0
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
13185217
HK		 227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
1da177e4
LT		 235};
236
237MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
50da859d 239static const struct {
1da177e4
LT		 240 const char string[ETH_GSTRING_LEN];
241} ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318};
319
50da859d 320static const struct {
4cafd3f5
MC		 321 const char string[ETH_GSTRING_LEN];
322} ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329};
330
b401e9e2
MC		 331static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332{
333 writel(val, tp->regs + off);
334}
335
336static u32 tg3_read32(struct tg3 *tp, u32 off)
337{
6aa20a22 338 return (readl(tp->regs + off));
b401e9e2
MC		 339}
340
0d3031d9
MC		 341static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342{
343 writel(val, tp->aperegs + off);
344}
345
346static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347{
348 return (readl(tp->aperegs + off));
349}
350
1da177e4
LT		 351static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352{
6892914f
MC		 353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 359}
360
361static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
1da177e4
LT		 365}
366
6892914f 367static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 368{
6892914f
MC		 369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377}
378
379static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380{
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
1da177e4 392 }
6892914f
MC		 393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407}
408
409static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410{
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419}
420
b401e9e2
MC		 421/* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 427{
b401e9e2
MC		 428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
1da177e4
LT		 444}
445
09ee929c
MC		 446static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447{
448 tp->write32_mbox(tp, off, val);
6892914f
MC		 449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
09ee929c
MC		 452}
453
20094930 454static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 455{
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462}
463
b5d3772c
MC		 464static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465{
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467}
468
469static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470{
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472}
473
20094930 474#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 475#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 476#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 478#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 479
480#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 481#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 483#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 484
485static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486{
6892914f
MC		 487 unsigned long flags;
488
b5d3772c
MC		 489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
6892914f 493 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 497
bbadf503
MC		 498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 503
bbadf503
MC		 504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 508}
509
1da177e4
LT		 510static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511{
6892914f
MC		 512 unsigned long flags;
513
b5d3772c
MC		 514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
6892914f 520 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 524
bbadf503
MC		 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
6892914f 534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 535}
536
0d3031d9
MC		 537static void tg3_ape_lock_init(struct tg3 *tp)
538{
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545}
546
547static int tg3_ape_lock(struct tg3 *tp, int locknum)
548{
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
77b483f1 557 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585}
586
587static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588{
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
77b483f1 595 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604}
605
1da177e4
LT		 606static void tg3_disable_ints(struct tg3 *tp)
607{
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 611}
612
613static inline void tg3_cond_int(struct tg3 *tp)
614{
38f3843e
MC		 615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 621}
622
623static void tg3_enable_ints(struct tg3 *tp)
624{
bbe832c0
MC		 625 tp->irq_sync = 0;
626 wmb();
627
1da177e4
LT		 628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
fcfa0a32
MC		 632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
1da177e4
LT		 635 tg3_cond_int(tp);
636}
637
04237ddd
MC		 638static inline unsigned int tg3_has_work(struct tg3 *tp)
639{
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656}
657
1da177e4 658/* tg3_restart_ints
04237ddd
MC		 659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
6aa20a22 661 * which reenables interrupts
1da177e4
LT		 662 */
663static void tg3_restart_ints(struct tg3 *tp)
664{
fac9b83e
DM		 665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
1da177e4
LT		 667 mmiowb();
668
fac9b83e
DM		 669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
04237ddd
MC		 675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 677}
678
679static inline void tg3_netif_stop(struct tg3 *tp)
680{
bbe832c0 681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 682 napi_disable(&tp->napi);
1da177e4
LT		 683 netif_tx_disable(tp->dev);
684}
685
686static inline void tg3_netif_start(struct tg3 *tp)
687{
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
bea3348e 693 napi_enable(&tp->napi);
f47c11ee
DM		 694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
1da177e4
LT		 696}
697
698static void tg3_switch_clocks(struct tg3 *tp)
699{
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
795d01c5
MC		 703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 705 return;
706
1da177e4
LT		 707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
1da177e4 726 }
b401e9e2 727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 728}
729
730#define PHY_BUSY_LOOPS 5000
731
732static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733{
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 751
1da177e4
LT		 752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779}
780
781static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782{
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
b5d3772c
MC		 787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
1da177e4
LT		 791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 803
1da177e4
LT		 804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828}
829
95e2869a
MC		 830static int tg3_bmcr_reset(struct tg3 *tp)
831{
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
d4675b52 855 if (limit < 0)
95e2869a
MC		 856 return -EBUSY;
857
858 return 0;
859}
860
158d7abd
MC		 861static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862{
3d16543d 863 struct tg3 *tp = bp->priv;
158d7abd
MC		 864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873}
874
875static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876{
3d16543d 877 struct tg3 *tp = bp->priv;
158d7abd
MC		 878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886}
887
888static int tg3_mdio_reset(struct mii_bus *bp)
889{
890 return 0;
891}
892
9c61d6bc 893static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 894{
895 u32 val;
fcb389df 896 struct phy_device *phydev;
a9daf367 897
fcb389df
MC		 898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
a9daf367 913 return;
fcb389df
MC		 914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
a9daf367
MC		 935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
a9daf367
MC		 946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
fcb389df 954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966}
967
158d7abd
MC		 968static void tg3_mdio_start(struct tg3 *tp)
969{
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 971 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 973 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
a9daf367 979
9c61d6bc
MC		 980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
158d7abd
MC		 983}
984
985static void tg3_mdio_stop(struct tg3 *tp)
986{
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 988 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 990 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 991 }
992}
993
994static int tg3_mdio_init(struct tg3 *tp)
995{
996 int i;
997 u32 reg;
a9daf367 998 struct phy_device *phydev;
158d7abd
MC		 999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
298cf9be
LB		 1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
158d7abd 1009
298cf9be
LB		 1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1022 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
298cf9be 1032 i = mdiobus_register(tp->mdio_bus);
a9daf367 1033 if (i) {
158d7abd
MC		 1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
9c61d6bc 1036 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1037 return i;
1038 }
158d7abd 1039
298cf9be 1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1041
9c61d6bc
MC		 1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
a9daf367 1053 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1063 break;
fcb389df 1064 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
9c61d6bc
MC		 1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
a9daf367
MC		 1074
1075 return 0;
158d7abd
MC		 1076}
1077
1078static void tg3_mdio_fini(struct tg3 *tp)
1079{
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086}
1087
4ba526ce
MC		 1088/* tp->lock is held. */
1089static inline void tg3_generate_fw_event(struct tg3 *tp)
1090{
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098}
1099
1100#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
95e2869a
MC		 1102/* tp->lock is held. */
1103static void tg3_wait_for_event_ack(struct tg3 *tp)
1104{
1105 int i;
4ba526ce
MC		 1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1121
4ba526ce 1122 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
4ba526ce 1125 udelay(8);
95e2869a
MC		 1126 }
1127}
1128
1129/* tp->lock is held. */
1130static void tg3_ump_link_report(struct tg3 *tp)
1131{
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
4ba526ce 1174 tg3_generate_fw_event(tp);
95e2869a
MC		 1175}
1176
1177static void tg3_link_report(struct tg3 *tp)
1178{
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
e18ce346 1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1198 "on" : "off",
e18ce346 1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203}
1204
1205static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206{
1207 u16 miireg;
1208
e18ce346 1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1210 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1211 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1212 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1213 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219}
1220
1221static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
95e2869a
MC		 1237static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238{
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1246 cap = FLOW_CTRL_RX;
95e2869a
MC		 1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1253 cap = FLOW_CTRL_TX;
95e2869a
MC		 1254 }
1255
1256 return cap;
1257}
1258
f51f3562 1259static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1260{
b02fd9e3 1261 u8 autoneg;
f51f3562 1262 u8 flowctrl = 0;
95e2869a
MC		 1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
b02fd9e3 1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1275 else
bc02ff95 1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1277 } else
1278 flowctrl = tp->link_config.flowctrl;
95e2869a 1279
f51f3562 1280 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1281
e18ce346 1282 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
f51f3562 1287 if (old_rx_mode != tp->rx_mode)
95e2869a 1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1289
e18ce346 1290 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
f51f3562 1295 if (old_tx_mode != tp->tx_mode)
95e2869a 1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1297}
1298
b02fd9e3
MC		 1299static void tg3_adjust_link(struct net_device *dev)
1300{
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
298cf9be 1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
fcb389df
MC		 1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
b02fd9e3
MC		 1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378}
1379
1380static int tg3_phy_init(struct tg3 *tp)
1381{
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
298cf9be 1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1391
1392 /* Attach the MAC to the PHY. */
fb28ad35 1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1394 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
b02fd9e3 1400 /* Mask with MAC supported features. */
9c61d6bc
MC		 1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
9c61d6bc
MC		 1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1422
1423 phydev->advertising = phydev->supported;
1424
b02fd9e3
MC		 1425 return 0;
1426}
1427
1428static void tg3_phy_start(struct tg3 *tp)
1429{
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
298cf9be 1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448}
1449
1450static void tg3_phy_stop(struct tg3 *tp)
1451{
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
298cf9be 1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1456}
1457
1458static void tg3_phy_fini(struct tg3 *tp)
1459{
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464}
1465
b2a5c19c
MC		 1466static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467{
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470}
1471
6833c043
MC		 1472static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473{
1474 u32 reg;
1475
a6435f3a
MC		 1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6833c043
MC		 1478 return;
1479
1480 reg = MII_TG3_MISC_SHDW_WREN |
1481 MII_TG3_MISC_SHDW_SCR5_SEL |
1482 MII_TG3_MISC_SHDW_SCR5_LPED |
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484 MII_TG3_MISC_SHDW_SCR5_SDTL |
1485 MII_TG3_MISC_SHDW_SCR5_C125OE;
1486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492 reg = MII_TG3_MISC_SHDW_WREN |
1493 MII_TG3_MISC_SHDW_APD_SEL |
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495 if (enable)
1496 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499}
1500
9ef8ca99
MC		 1501static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502{
1503 u32 phy;
1504
1505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507 return;
1508
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510 u32 ephy;
1511
1512 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514 ephy | MII_TG3_EPHY_SHADOW_EN);
1515 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516 if (enable)
1517 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518 else
1519 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521 }
1522 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523 }
1524 } else {
1525 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526 MII_TG3_AUXCTL_SHDWSEL_MISC;
1527 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531 else
1532 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533 phy |= MII_TG3_AUXCTL_MISC_WREN;
1534 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535 }
1536 }
1537}
1538
1da177e4
LT		 1539static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540{
1541 u32 val;
1542
1543 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544 return;
1545
1546 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549 (val | (1 << 15) | (1 << 4)));
1550}
1551
b2a5c19c
MC		 1552static void tg3_phy_apply_otp(struct tg3 *tp)
1553{
1554 u32 otp, phy;
1555
1556 if (!tp->phy_otp)
1557 return;
1558
1559 otp = tp->phy_otp;
1560
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564 MII_TG3_AUXCTL_ACTL_TX_6DB;
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589 /* Turn off SM_DSP clock. */
1590 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591 MII_TG3_AUXCTL_ACTL_TX_6DB;
1592 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593}
1594
1da177e4
LT		 1595static int tg3_wait_macro_done(struct tg3 *tp)
1596{
1597 int limit = 100;
1598
1599 while (limit--) {
1600 u32 tmp32;
1601
1602 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603 if ((tmp32 & 0x1000) == 0)
1604 break;
1605 }
1606 }
d4675b52 1607 if (limit < 0)
1da177e4
LT		 1608 return -EBUSY;
1609
1610 return 0;
1611}
1612
1613static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614{
1615 static const u32 test_pat[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620 };
1621 int chan;
1622
1623 for (chan = 0; chan < 4; chan++) {
1624 int i;
1625
1626 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627 (chan * 0x2000) | 0x0200);
1628 tg3_writephy(tp, 0x16, 0x0002);
1629
1630 for (i = 0; i < 6; i++)
1631 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632 test_pat[chan][i]);
1633
1634 tg3_writephy(tp, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641 (chan * 0x2000) | 0x0200);
1642 tg3_writephy(tp, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp)) {
1644 *resetp = 1;
1645 return -EBUSY;
1646 }
1647
1648 tg3_writephy(tp, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp)) {
1650 *resetp = 1;
1651 return -EBUSY;
1652 }
1653
1654 for (i = 0; i < 6; i += 2) {
1655 u32 low, high;
1656
1657 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659 tg3_wait_macro_done(tp)) {
1660 *resetp = 1;
1661 return -EBUSY;
1662 }
1663 low &= 0x7fff;
1664 high &= 0x000f;
1665 if (low != test_pat[chan][i] ||
1666 high != test_pat[chan][i+1]) {
1667 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671 return -EBUSY;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677}
1678
1679static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680{
1681 int chan;
1682
1683 for (chan = 0; chan < 4; chan++) {
1684 int i;
1685
1686 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687 (chan * 0x2000) | 0x0200);
1688 tg3_writephy(tp, 0x16, 0x0002);
1689 for (i = 0; i < 6; i++)
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691 tg3_writephy(tp, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp))
1693 return -EBUSY;
1694 }
1695
1696 return 0;
1697}
1698
1699static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700{
1701 u32 reg32, phy9_orig;
1702 int retries, do_phy_reset, err;
1703
1704 retries = 10;
1705 do_phy_reset = 1;
1706 do {
1707 if (do_phy_reset) {
1708 err = tg3_bmcr_reset(tp);
1709 if (err)
1710 return err;
1711 do_phy_reset = 0;
1712 }
1713
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716 continue;
1717
1718 reg32 |= 0x3000;
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp, MII_BMCR,
1723 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727 continue;
1728
1729 tg3_writephy(tp, MII_TG3_CTRL,
1730 (MII_TG3_CTRL_AS_MASTER |
1731 MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741 if (!err)
1742 break;
1743 } while (--retries);
1744
1745 err = tg3_phy_reset_chanpat(tp);
1746 if (err)
1747 return err;
1748
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753 tg3_writephy(tp, 0x16, 0x0000);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759 }
1760 else {
1761 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762 }
1763
1764 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767 reg32 &= ~0x3000;
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769 } else if (!err)
1770 err = -EBUSY;
1771
1772 return err;
1773}
1774
1775/* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1777 */
1778static int tg3_phy_reset(struct tg3 *tp)
1779{
b2a5c19c 1780 u32 cpmuctrl;
1da177e4
LT		 1781 u32 phy_status;
1782 int err;
1783
60189ddf
MC		 1784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785 u32 val;
1786
1787 val = tr32(GRC_MISC_CFG);
1788 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789 udelay(40);
1790 }
1da177e4
LT		 1791 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1792 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793 if (err != 0)
1794 return -EBUSY;
1795
c8e1e82b
MC		 1796 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797 netif_carrier_off(tp->dev);
1798 tg3_link_report(tp);
1799 }
1800
1da177e4
LT		 1801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804 err = tg3_phy_reset_5703_4_5(tp);
1805 if (err)
1806 return err;
1807 goto out;
1808 }
1809
b2a5c19c
MC		 1810 cpmuctrl = 0;
1811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815 tw32(TG3_CPMU_CTRL,
1816 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817 }
1818
1da177e4
LT		 1819 err = tg3_bmcr_reset(tp);
1820 if (err)
1821 return err;
1822
b2a5c19c
MC		 1823 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824 u32 phy;
1825
1826 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830 }
1831
bcb37f6c
MC		 1832 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1834 u32 val;
1835
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5) {
1839 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840 udelay(40);
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842 }
1843 }
1844
b2a5c19c
MC		 1845 tg3_phy_apply_otp(tp);
1846
6833c043
MC		 1847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848 tg3_phy_toggle_apd(tp, true);
1849 else
1850 tg3_phy_toggle_apd(tp, false);
1851
1da177e4
LT		 1852out:
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860 }
1861 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 tg3_writephy(tp, 0x1c, 0x8d68);
1864 }
1865 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874 }
c424cb24
MC		 1875 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1878 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880 tg3_writephy(tp, MII_TG3_TEST1,
1881 MII_TG3_TEST1_TRIM_EN | 0x4);
1882 } else
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1884 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885 }
1da177e4
LT		 1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1891 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1892 u32 phy_reg;
1893
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898 }
1899
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1902 */
0f893dc6 1903 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1904 u32 phy_reg;
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909 }
1910
715116a1 1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1912 /* adjust output voltage */
1913 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1914 }
1915
9ef8ca99 1916 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1917 tg3_phy_set_wirespeed(tp);
1918 return 0;
1919}
1920
1921static void tg3_frob_aux_power(struct tg3 *tp)
1922{
1923 struct tg3 *tp_peer = tp;
1924
9d26e213 1925 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1926 return;
1927
8c2dc7e1
MC		 1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930 struct net_device *dev_peer;
1931
1932 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1933 /* remove_one() may have been run on the peer. */
8c2dc7e1 1934 if (!dev_peer)
bc1c7567
MC		 1935 tp_peer = tp;
1936 else
1937 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1938 }
1939
1da177e4 1940 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1941 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1946 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947 (GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1),
1952 100);
5f0c4a3c
MC		 1953 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1954 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1956 GRC_LCLCTRL_GPIO_OE1 |
1957 GRC_LCLCTRL_GPIO_OE2 |
1958 GRC_LCLCTRL_GPIO_OUTPUT0 |
1959 GRC_LCLCTRL_GPIO_OUTPUT1 |
1960 tp->grc_local_ctrl;
1961 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1962
1963 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1964 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1965
1966 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1967 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 1968 } else {
1969 u32 no_gpio2;
dc56b7d4 1970 u32 grc_local_ctrl = 0;
1da177e4
LT		 1971
1972 if (tp_peer != tp &&
1973 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1974 return;
1975
dc56b7d4
MC		 1976 /* Workaround to prevent overdrawing Amps. */
1977 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1978 ASIC_REV_5714) {
1979 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1980 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1981 grc_local_ctrl, 100);
dc56b7d4
MC		 1982 }
1983
1da177e4
LT		 1984 /* On 5753 and variants, GPIO2 cannot be used. */
1985 no_gpio2 = tp->nic_sram_data_cfg &
1986 NIC_SRAM_DATA_CFG_NO_GPIO2;
1987
dc56b7d4 1988 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1989 GRC_LCLCTRL_GPIO_OE1 |
1990 GRC_LCLCTRL_GPIO_OE2 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1 |
1992 GRC_LCLCTRL_GPIO_OUTPUT2;
1993 if (no_gpio2) {
1994 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1995 GRC_LCLCTRL_GPIO_OUTPUT2);
1996 }
b401e9e2
MC		 1997 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1998 grc_local_ctrl, 100);
1da177e4
LT		 1999
2000 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2001
b401e9e2
MC		 2002 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2003 grc_local_ctrl, 100);
1da177e4
LT		 2004
2005 if (!no_gpio2) {
2006 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2007 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2008 grc_local_ctrl, 100);
1da177e4
LT		 2009 }
2010 }
2011 } else {
2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2013 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2014 if (tp_peer != tp &&
2015 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2016 return;
2017
b401e9e2
MC		 2018 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019 (GRC_LCLCTRL_GPIO_OE1 |
2020 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2021
b401e9e2
MC		 2022 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2023 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2024
b401e9e2
MC		 2025 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026 (GRC_LCLCTRL_GPIO_OE1 |
2027 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2028 }
2029 }
2030}
2031
e8f3f6ca
MC		 2032static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2033{
2034 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2035 return 1;
2036 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2037 if (speed != SPEED_10)
2038 return 1;
2039 } else if (speed == SPEED_10)
2040 return 1;
2041
2042 return 0;
2043}
2044
1da177e4
LT		 2045static int tg3_setup_phy(struct tg3 *, int);
2046
2047#define RESET_KIND_SHUTDOWN 0
2048#define RESET_KIND_INIT 1
2049#define RESET_KIND_SUSPEND 2
2050
2051static void tg3_write_sig_post_reset(struct tg3 *, int);
2052static int tg3_halt_cpu(struct tg3 *, u32);
6921d201
MC		 2053static int tg3_nvram_lock(struct tg3 *);
2054static void tg3_nvram_unlock(struct tg3 *);
1da177e4 2055
0a459aac 2056static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2057{
ce057f01
MC		 2058 u32 val;
2059
5129724a
MC		 2060 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2061 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2062 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2063 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2064
2065 sg_dig_ctrl |=
2066 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2067 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2068 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2069 }
3f7045c1 2070 return;
5129724a 2071 }
3f7045c1 2072
60189ddf 2073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2074 tg3_bmcr_reset(tp);
2075 val = tr32(GRC_MISC_CFG);
2076 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2077 udelay(40);
2078 return;
0a459aac 2079 } else if (do_low_power) {
715116a1
MC		 2080 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2081 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2082
2083 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2084 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2085 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2086 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2087 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2088 }
3f7045c1 2089
15c3b696
MC		 2090 /* The PHY should not be powered down on some chips because
2091 * of bugs.
2092 */
2093 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2094 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2095 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2096 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2097 return;
ce057f01 2098
bcb37f6c
MC		 2099 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2100 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2101 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2102 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2103 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2104 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2105 }
2106
15c3b696
MC		 2107 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2108}
2109
3f007891
MC		 2110/* tp->lock is held. */
2111static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2112{
2113 u32 addr_high, addr_low;
2114 int i;
2115
2116 addr_high = ((tp->dev->dev_addr[0] << 8) |
2117 tp->dev->dev_addr[1]);
2118 addr_low = ((tp->dev->dev_addr[2] << 24) |
2119 (tp->dev->dev_addr[3] << 16) |
2120 (tp->dev->dev_addr[4] << 8) |
2121 (tp->dev->dev_addr[5] << 0));
2122 for (i = 0; i < 4; i++) {
2123 if (i == 1 && skip_mac_1)
2124 continue;
2125 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2126 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2127 }
2128
2129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2131 for (i = 0; i < 12; i++) {
2132 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2133 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2134 }
2135 }
2136
2137 addr_high = (tp->dev->dev_addr[0] +
2138 tp->dev->dev_addr[1] +
2139 tp->dev->dev_addr[2] +
2140 tp->dev->dev_addr[3] +
2141 tp->dev->dev_addr[4] +
2142 tp->dev->dev_addr[5]) &
2143 TX_BACKOFF_SEED_MASK;
2144 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2145}
2146
bc1c7567 2147static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2148{
2149 u32 misc_host_ctrl;
0a459aac 2150 bool device_should_wake, do_low_power;
1da177e4
LT		 2151
2152 /* Make sure register accesses (indirect or otherwise)
2153 * will function correctly.
2154 */
2155 pci_write_config_dword(tp->pdev,
2156 TG3PCI_MISC_HOST_CTRL,
2157 tp->misc_host_ctrl);
2158
1da177e4 2159 switch (state) {
bc1c7567 2160 case PCI_D0:
12dac075
RW		 2161 pci_enable_wake(tp->pdev, state, false);
2162 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2163
9d26e213
MC		 2164 /* Switch out of Vaux if it is a NIC */
2165 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2166 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2167
2168 return 0;
2169
bc1c7567 2170 case PCI_D1:
bc1c7567 2171 case PCI_D2:
bc1c7567 2172 case PCI_D3hot:
1da177e4
LT		 2173 break;
2174
2175 default:
12dac075
RW		 2176 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2177 tp->dev->name, state);
1da177e4 2178 return -EINVAL;
855e1111 2179 }
5e7dfd0f
MC		 2180
2181 /* Restore the CLKREQ setting. */
2182 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2183 u16 lnkctl;
2184
2185 pci_read_config_word(tp->pdev,
2186 tp->pcie_cap + PCI_EXP_LNKCTL,
2187 &lnkctl);
2188 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2189 pci_write_config_word(tp->pdev,
2190 tp->pcie_cap + PCI_EXP_LNKCTL,
2191 lnkctl);
2192 }
2193
1da177e4
LT		 2194 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2195 tw32(TG3PCI_MISC_HOST_CTRL,
2196 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2197
05ac4cb7
MC		 2198 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2199 device_may_wakeup(&tp->pdev->dev) &&
2200 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2201
dd477003 2202 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2203 do_low_power = false;
b02fd9e3
MC		 2204 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2205 !tp->link_config.phy_is_low_power) {
2206 struct phy_device *phydev;
0a459aac 2207 u32 phyid, advertising;
b02fd9e3 2208
298cf9be 2209 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2210
2211 tp->link_config.phy_is_low_power = 1;
2212
2213 tp->link_config.orig_speed = phydev->speed;
2214 tp->link_config.orig_duplex = phydev->duplex;
2215 tp->link_config.orig_autoneg = phydev->autoneg;
2216 tp->link_config.orig_advertising = phydev->advertising;
2217
2218 advertising = ADVERTISED_TP |
2219 ADVERTISED_Pause |
2220 ADVERTISED_Autoneg |
2221 ADVERTISED_10baseT_Half;
2222
2223 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2224 device_should_wake) {
b02fd9e3
MC		 2225 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2226 advertising |=
2227 ADVERTISED_100baseT_Half |
2228 ADVERTISED_100baseT_Full |
2229 ADVERTISED_10baseT_Full;
2230 else
2231 advertising |= ADVERTISED_10baseT_Full;
2232 }
2233
2234 phydev->advertising = advertising;
2235
2236 phy_start_aneg(phydev);
0a459aac
MC		 2237
2238 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2239 if (phyid != TG3_PHY_ID_BCMAC131) {
2240 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2241 if (phyid == TG3_PHY_OUI_1 ||
2242 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2243 phyid == TG3_PHY_OUI_3)
2244 do_low_power = true;
2245 }
b02fd9e3 2246 }
dd477003 2247 } else {
2023276e 2248 do_low_power = true;
0a459aac 2249
dd477003
MC		 2250 if (tp->link_config.phy_is_low_power == 0) {
2251 tp->link_config.phy_is_low_power = 1;
2252 tp->link_config.orig_speed = tp->link_config.speed;
2253 tp->link_config.orig_duplex = tp->link_config.duplex;
2254 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2255 }
1da177e4 2256
dd477003
MC		 2257 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2258 tp->link_config.speed = SPEED_10;
2259 tp->link_config.duplex = DUPLEX_HALF;
2260 tp->link_config.autoneg = AUTONEG_ENABLE;
2261 tg3_setup_phy(tp, 0);
2262 }
1da177e4
LT		 2263 }
2264
3f007891
MC		 2265 __tg3_set_mac_addr(tp, 0);
2266
b5d3772c
MC		 2267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2268 u32 val;
2269
2270 val = tr32(GRC_VCPU_EXT_CTRL);
2271 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2272 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2273 int i;
2274 u32 val;
2275
2276 for (i = 0; i < 200; i++) {
2277 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2278 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2279 break;
2280 msleep(1);
2281 }
2282 }
a85feb8c
GZ		 2283 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2284 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2285 WOL_DRV_STATE_SHUTDOWN |
2286 WOL_DRV_WOL |
2287 WOL_SET_MAGIC_PKT);
6921d201 2288
05ac4cb7 2289 if (device_should_wake) {
1da177e4
LT		 2290 u32 mac_mode;
2291
2292 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2293 if (do_low_power) {
dd477003
MC		 2294 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2295 udelay(40);
2296 }
1da177e4 2297
3f7045c1
MC		 2298 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2299 mac_mode = MAC_MODE_PORT_MODE_GMII;
2300 else
2301 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2302
e8f3f6ca
MC		 2303 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2304 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2305 ASIC_REV_5700) {
2306 u32 speed = (tp->tg3_flags &
2307 TG3_FLAG_WOL_SPEED_100MB) ?
2308 SPEED_100 : SPEED_10;
2309 if (tg3_5700_link_polarity(tp, speed))
2310 mac_mode |= MAC_MODE_LINK_POLARITY;
2311 else
2312 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2313 }
1da177e4
LT		 2314 } else {
2315 mac_mode = MAC_MODE_PORT_MODE_TBI;
2316 }
2317
cbf46853 2318 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2319 tw32(MAC_LED_CTRL, tp->led_ctrl);
2320
05ac4cb7
MC		 2321 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2322 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2323 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2324 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2325 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2326 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2327
3bda1258
MC		 2328 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2329 mac_mode |= tp->mac_mode &
2330 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2331 if (mac_mode & MAC_MODE_APE_TX_EN)
2332 mac_mode |= MAC_MODE_TDE_ENABLE;
2333 }
2334
1da177e4
LT		 2335 tw32_f(MAC_MODE, mac_mode);
2336 udelay(100);
2337
2338 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2339 udelay(10);
2340 }
2341
2342 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2343 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2344 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2345 u32 base_val;
2346
2347 base_val = tp->pci_clock_ctrl;
2348 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2349 CLOCK_CTRL_TXCLK_DISABLE);
2350
b401e9e2
MC		 2351 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2352 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2353 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2354 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2355 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2356 /* do nothing */
85e94ced 2357 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2358 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2359 u32 newbits1, newbits2;
2360
2361 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2362 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2363 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2364 CLOCK_CTRL_TXCLK_DISABLE |
2365 CLOCK_CTRL_ALTCLK);
2366 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2367 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2368 newbits1 = CLOCK_CTRL_625_CORE;
2369 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2370 } else {
2371 newbits1 = CLOCK_CTRL_ALTCLK;
2372 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2373 }
2374
b401e9e2
MC		 2375 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2376 40);
1da177e4 2377
b401e9e2
MC		 2378 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2379 40);
1da177e4
LT		 2380
2381 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2382 u32 newbits3;
2383
2384 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2385 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2386 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2387 CLOCK_CTRL_TXCLK_DISABLE |
2388 CLOCK_CTRL_44MHZ_CORE);
2389 } else {
2390 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2391 }
2392
b401e9e2
MC		 2393 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2394 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2395 }
2396 }
2397
05ac4cb7 2398 if (!(device_should_wake) &&
22435849 2399 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2400 tg3_power_down_phy(tp, do_low_power);
6921d201 2401
1da177e4
LT		 2402 tg3_frob_aux_power(tp);
2403
2404 /* Workaround for unstable PLL clock */
2405 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2406 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2407 u32 val = tr32(0x7d00);
2408
2409 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2410 tw32(0x7d00, val);
6921d201 2411 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2412 int err;
2413
2414 err = tg3_nvram_lock(tp);
1da177e4 2415 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2416 if (!err)
2417 tg3_nvram_unlock(tp);
6921d201 2418 }
1da177e4
LT		 2419 }
2420
bbadf503
MC		 2421 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2422
05ac4cb7 2423 if (device_should_wake)
12dac075
RW		 2424 pci_enable_wake(tp->pdev, state, true);
2425
1da177e4 2426 /* Finally, set the new power state. */
12dac075 2427 pci_set_power_state(tp->pdev, state);
1da177e4 2428
1da177e4
LT		 2429 return 0;
2430}
2431
1da177e4
LT		 2432static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2433{
2434 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2435 case MII_TG3_AUX_STAT_10HALF:
2436 *speed = SPEED_10;
2437 *duplex = DUPLEX_HALF;
2438 break;
2439
2440 case MII_TG3_AUX_STAT_10FULL:
2441 *speed = SPEED_10;
2442 *duplex = DUPLEX_FULL;
2443 break;
2444
2445 case MII_TG3_AUX_STAT_100HALF:
2446 *speed = SPEED_100;
2447 *duplex = DUPLEX_HALF;
2448 break;
2449
2450 case MII_TG3_AUX_STAT_100FULL:
2451 *speed = SPEED_100;
2452 *duplex = DUPLEX_FULL;
2453 break;
2454
2455 case MII_TG3_AUX_STAT_1000HALF:
2456 *speed = SPEED_1000;
2457 *duplex = DUPLEX_HALF;
2458 break;
2459
2460 case MII_TG3_AUX_STAT_1000FULL:
2461 *speed = SPEED_1000;
2462 *duplex = DUPLEX_FULL;
2463 break;
2464
2465 default:
715116a1
MC		 2466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2467 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2468 SPEED_10;
2469 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2470 DUPLEX_HALF;
2471 break;
2472 }
1da177e4
LT		 2473 *speed = SPEED_INVALID;
2474 *duplex = DUPLEX_INVALID;
2475 break;
855e1111 2476 }
1da177e4
LT		 2477}
2478
2479static void tg3_phy_copper_begin(struct tg3 *tp)
2480{
2481 u32 new_adv;
2482 int i;
2483
2484 if (tp->link_config.phy_is_low_power) {
2485 /* Entering low power mode. Disable gigabit and
2486 * 100baseT advertisements.
2487 */
2488 tg3_writephy(tp, MII_TG3_CTRL, 0);
2489
2490 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2491 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2492 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2493 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2494
2495 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2496 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2497 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2498 tp->link_config.advertising &=
2499 ~(ADVERTISED_1000baseT_Half |
2500 ADVERTISED_1000baseT_Full);
2501
ba4d07a8 2502 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2503 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2504 new_adv |= ADVERTISE_10HALF;
2505 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2506 new_adv |= ADVERTISE_10FULL;
2507 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2508 new_adv |= ADVERTISE_100HALF;
2509 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2510 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2511
2512 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2513
1da177e4
LT		 2514 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2515
2516 if (tp->link_config.advertising &
2517 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2518 new_adv = 0;
2519 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2520 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2521 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2522 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2523 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2524 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2525 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2526 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2527 MII_TG3_CTRL_ENABLE_AS_MASTER);
2528 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2529 } else {
2530 tg3_writephy(tp, MII_TG3_CTRL, 0);
2531 }
2532 } else {
ba4d07a8
MC		 2533 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2534 new_adv |= ADVERTISE_CSMA;
2535
1da177e4
LT		 2536 /* Asking for a specific link mode. */
2537 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2538 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2539
2540 if (tp->link_config.duplex == DUPLEX_FULL)
2541 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2542 else
2543 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2544 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2545 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2546 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2547 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2548 } else {
1da177e4
LT		 2549 if (tp->link_config.speed == SPEED_100) {
2550 if (tp->link_config.duplex == DUPLEX_FULL)
2551 new_adv |= ADVERTISE_100FULL;
2552 else
2553 new_adv |= ADVERTISE_100HALF;
2554 } else {
2555 if (tp->link_config.duplex == DUPLEX_FULL)
2556 new_adv |= ADVERTISE_10FULL;
2557 else
2558 new_adv |= ADVERTISE_10HALF;
2559 }
2560 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2561
2562 new_adv = 0;
1da177e4 2563 }
ba4d07a8
MC		 2564
2565 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2566 }
2567
2568 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2569 tp->link_config.speed != SPEED_INVALID) {
2570 u32 bmcr, orig_bmcr;
2571
2572 tp->link_config.active_speed = tp->link_config.speed;
2573 tp->link_config.active_duplex = tp->link_config.duplex;
2574
2575 bmcr = 0;
2576 switch (tp->link_config.speed) {
2577 default:
2578 case SPEED_10:
2579 break;
2580
2581 case SPEED_100:
2582 bmcr |= BMCR_SPEED100;
2583 break;
2584
2585 case SPEED_1000:
2586 bmcr |= TG3_BMCR_SPEED1000;
2587 break;
855e1111 2588 }
1da177e4
LT		 2589
2590 if (tp->link_config.duplex == DUPLEX_FULL)
2591 bmcr |= BMCR_FULLDPLX;
2592
2593 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2594 (bmcr != orig_bmcr)) {
2595 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2596 for (i = 0; i < 1500; i++) {
2597 u32 tmp;
2598
2599 udelay(10);
2600 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2601 tg3_readphy(tp, MII_BMSR, &tmp))
2602 continue;
2603 if (!(tmp & BMSR_LSTATUS)) {
2604 udelay(40);
2605 break;
2606 }
2607 }
2608 tg3_writephy(tp, MII_BMCR, bmcr);
2609 udelay(40);
2610 }
2611 } else {
2612 tg3_writephy(tp, MII_BMCR,
2613 BMCR_ANENABLE | BMCR_ANRESTART);
2614 }
2615}
2616
2617static int tg3_init_5401phy_dsp(struct tg3 *tp)
2618{
2619 int err;
2620
2621 /* Turn off tap power management. */
2622 /* Set Extended packet length bit */
2623 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2624
2625 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2626 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2627
2628 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2629 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2630
2631 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2632 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2633
2634 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2635 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2636
2637 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2638 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2639
2640 udelay(40);
2641
2642 return err;
2643}
2644
3600d918 2645static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2646{
3600d918
MC		 2647 u32 adv_reg, all_mask = 0;
2648
2649 if (mask & ADVERTISED_10baseT_Half)
2650 all_mask |= ADVERTISE_10HALF;
2651 if (mask & ADVERTISED_10baseT_Full)
2652 all_mask |= ADVERTISE_10FULL;
2653 if (mask & ADVERTISED_100baseT_Half)
2654 all_mask |= ADVERTISE_100HALF;
2655 if (mask & ADVERTISED_100baseT_Full)
2656 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2657
2658 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2659 return 0;
2660
1da177e4
LT		 2661 if ((adv_reg & all_mask) != all_mask)
2662 return 0;
2663 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2664 u32 tg3_ctrl;
2665
3600d918
MC		 2666 all_mask = 0;
2667 if (mask & ADVERTISED_1000baseT_Half)
2668 all_mask |= ADVERTISE_1000HALF;
2669 if (mask & ADVERTISED_1000baseT_Full)
2670 all_mask |= ADVERTISE_1000FULL;
2671
1da177e4
LT		 2672 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2673 return 0;
2674
1da177e4
LT		 2675 if ((tg3_ctrl & all_mask) != all_mask)
2676 return 0;
2677 }
2678 return 1;
2679}
2680
ef167e27
MC		 2681static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2682{
2683 u32 curadv, reqadv;
2684
2685 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2686 return 1;
2687
2688 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2689 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2690
2691 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2692 if (curadv != reqadv)
2693 return 0;
2694
2695 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2696 tg3_readphy(tp, MII_LPA, rmtadv);
2697 } else {
2698 /* Reprogram the advertisement register, even if it
2699 * does not affect the current link. If the link
2700 * gets renegotiated in the future, we can save an
2701 * additional renegotiation cycle by advertising
2702 * it correctly in the first place.
2703 */
2704 if (curadv != reqadv) {
2705 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2706 ADVERTISE_PAUSE_ASYM);
2707 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2708 }
2709 }
2710
2711 return 1;
2712}
2713
1da177e4
LT		 2714static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2715{
2716 int current_link_up;
2717 u32 bmsr, dummy;
ef167e27 2718 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2719 u16 current_speed;
2720 u8 current_duplex;
2721 int i, err;
2722
2723 tw32(MAC_EVENT, 0);
2724
2725 tw32_f(MAC_STATUS,
2726 (MAC_STATUS_SYNC_CHANGED |
2727 MAC_STATUS_CFG_CHANGED |
2728 MAC_STATUS_MI_COMPLETION |
2729 MAC_STATUS_LNKSTATE_CHANGED));
2730 udelay(40);
2731
8ef21428
MC		 2732 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2733 tw32_f(MAC_MI_MODE,
2734 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2735 udelay(80);
2736 }
1da177e4
LT		 2737
2738 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2739
2740 /* Some third-party PHYs need to be reset on link going
2741 * down.
2742 */
2743 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2744 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2745 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2746 netif_carrier_ok(tp->dev)) {
2747 tg3_readphy(tp, MII_BMSR, &bmsr);
2748 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2749 !(bmsr & BMSR_LSTATUS))
2750 force_reset = 1;
2751 }
2752 if (force_reset)
2753 tg3_phy_reset(tp);
2754
2755 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2756 tg3_readphy(tp, MII_BMSR, &bmsr);
2757 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2758 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2759 bmsr = 0;
2760
2761 if (!(bmsr & BMSR_LSTATUS)) {
2762 err = tg3_init_5401phy_dsp(tp);
2763 if (err)
2764 return err;
2765
2766 tg3_readphy(tp, MII_BMSR, &bmsr);
2767 for (i = 0; i < 1000; i++) {
2768 udelay(10);
2769 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2770 (bmsr & BMSR_LSTATUS)) {
2771 udelay(40);
2772 break;
2773 }
2774 }
2775
2776 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2777 !(bmsr & BMSR_LSTATUS) &&
2778 tp->link_config.active_speed == SPEED_1000) {
2779 err = tg3_phy_reset(tp);
2780 if (!err)
2781 err = tg3_init_5401phy_dsp(tp);
2782 if (err)
2783 return err;
2784 }
2785 }
2786 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2787 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2788 /* 5701 {A0,B0} CRC bug workaround */
2789 tg3_writephy(tp, 0x15, 0x0a75);
2790 tg3_writephy(tp, 0x1c, 0x8c68);
2791 tg3_writephy(tp, 0x1c, 0x8d68);
2792 tg3_writephy(tp, 0x1c, 0x8c68);
2793 }
2794
2795 /* Clear pending interrupts... */
2796 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2797 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2798
2799 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2800 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2801 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2802 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2803
2804 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2805 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2806 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2807 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2808 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2809 else
2810 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2811 }
2812
2813 current_link_up = 0;
2814 current_speed = SPEED_INVALID;
2815 current_duplex = DUPLEX_INVALID;
2816
2817 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2818 u32 val;
2819
2820 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2821 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2822 if (!(val & (1 << 10))) {
2823 val |= (1 << 10);
2824 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2825 goto relink;
2826 }
2827 }
2828
2829 bmsr = 0;
2830 for (i = 0; i < 100; i++) {
2831 tg3_readphy(tp, MII_BMSR, &bmsr);
2832 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2833 (bmsr & BMSR_LSTATUS))
2834 break;
2835 udelay(40);
2836 }
2837
2838 if (bmsr & BMSR_LSTATUS) {
2839 u32 aux_stat, bmcr;
2840
2841 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2842 for (i = 0; i < 2000; i++) {
2843 udelay(10);
2844 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2845 aux_stat)
2846 break;
2847 }
2848
2849 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2850 &current_speed,
2851 &current_duplex);
2852
2853 bmcr = 0;
2854 for (i = 0; i < 200; i++) {
2855 tg3_readphy(tp, MII_BMCR, &bmcr);
2856 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2857 continue;
2858 if (bmcr && bmcr != 0x7fff)
2859 break;
2860 udelay(10);
2861 }
2862
ef167e27
MC		 2863 lcl_adv = 0;
2864 rmt_adv = 0;
1da177e4 2865
ef167e27
MC		 2866 tp->link_config.active_speed = current_speed;
2867 tp->link_config.active_duplex = current_duplex;
2868
2869 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2870 if ((bmcr & BMCR_ANENABLE) &&
2871 tg3_copper_is_advertising_all(tp,
2872 tp->link_config.advertising)) {
2873 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2874 &rmt_adv))
2875 current_link_up = 1;
1da177e4
LT		 2876 }
2877 } else {
2878 if (!(bmcr & BMCR_ANENABLE) &&
2879 tp->link_config.speed == current_speed &&
ef167e27
MC		 2880 tp->link_config.duplex == current_duplex &&
2881 tp->link_config.flowctrl ==
2882 tp->link_config.active_flowctrl) {
1da177e4 2883 current_link_up = 1;
1da177e4
LT		 2884 }
2885 }
2886
ef167e27
MC		 2887 if (current_link_up == 1 &&
2888 tp->link_config.active_duplex == DUPLEX_FULL)
2889 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 2890 }
2891
1da177e4 2892relink:
6921d201 2893 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 2894 u32 tmp;
2895
2896 tg3_phy_copper_begin(tp);
2897
2898 tg3_readphy(tp, MII_BMSR, &tmp);
2899 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2900 (tmp & BMSR_LSTATUS))
2901 current_link_up = 1;
2902 }
2903
2904 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2905 if (current_link_up == 1) {
2906 if (tp->link_config.active_speed == SPEED_100 ||
2907 tp->link_config.active_speed == SPEED_10)
2908 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2909 else
2910 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2911 } else
2912 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2913
2914 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2915 if (tp->link_config.active_duplex == DUPLEX_HALF)
2916 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2917
1da177e4 2918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 2919 if (current_link_up == 1 &&
2920 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 2921 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 2922 else
2923 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 2924 }
2925
2926 /* ??? Without this setting Netgear GA302T PHY does not
2927 * ??? send/receive packets...
2928 */
2929 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2930 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2931 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2932 tw32_f(MAC_MI_MODE, tp->mi_mode);
2933 udelay(80);
2934 }
2935
2936 tw32_f(MAC_MODE, tp->mac_mode);
2937 udelay(40);
2938
2939 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2940 /* Polled via timer. */
2941 tw32_f(MAC_EVENT, 0);
2942 } else {
2943 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2944 }
2945 udelay(40);
2946
2947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2948 current_link_up == 1 &&
2949 tp->link_config.active_speed == SPEED_1000 &&
2950 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2951 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2952 udelay(120);
2953 tw32_f(MAC_STATUS,
2954 (MAC_STATUS_SYNC_CHANGED |
2955 MAC_STATUS_CFG_CHANGED));
2956 udelay(40);
2957 tg3_write_mem(tp,
2958 NIC_SRAM_FIRMWARE_MBOX,
2959 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2960 }
2961
5e7dfd0f
MC		 2962 /* Prevent send BD corruption. */
2963 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2964 u16 oldlnkctl, newlnkctl;
2965
2966 pci_read_config_word(tp->pdev,
2967 tp->pcie_cap + PCI_EXP_LNKCTL,
2968 &oldlnkctl);
2969 if (tp->link_config.active_speed == SPEED_100 ||
2970 tp->link_config.active_speed == SPEED_10)
2971 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
2972 else
2973 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
2974 if (newlnkctl != oldlnkctl)
2975 pci_write_config_word(tp->pdev,
2976 tp->pcie_cap + PCI_EXP_LNKCTL,
2977 newlnkctl);
2978 }
2979
1da177e4
LT		 2980 if (current_link_up != netif_carrier_ok(tp->dev)) {
2981 if (current_link_up)
2982 netif_carrier_on(tp->dev);
2983 else
2984 netif_carrier_off(tp->dev);
2985 tg3_link_report(tp);
2986 }
2987
2988 return 0;
2989}
2990
2991struct tg3_fiber_aneginfo {
2992 int state;
2993#define ANEG_STATE_UNKNOWN 0
2994#define ANEG_STATE_AN_ENABLE 1
2995#define ANEG_STATE_RESTART_INIT 2
2996#define ANEG_STATE_RESTART 3
2997#define ANEG_STATE_DISABLE_LINK_OK 4
2998#define ANEG_STATE_ABILITY_DETECT_INIT 5
2999#define ANEG_STATE_ABILITY_DETECT 6
3000#define ANEG_STATE_ACK_DETECT_INIT 7
3001#define ANEG_STATE_ACK_DETECT 8
3002#define ANEG_STATE_COMPLETE_ACK_INIT 9
3003#define ANEG_STATE_COMPLETE_ACK 10
3004#define ANEG_STATE_IDLE_DETECT_INIT 11
3005#define ANEG_STATE_IDLE_DETECT 12
3006#define ANEG_STATE_LINK_OK 13
3007#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3008#define ANEG_STATE_NEXT_PAGE_WAIT 15
3009
3010 u32 flags;
3011#define MR_AN_ENABLE 0x00000001
3012#define MR_RESTART_AN 0x00000002
3013#define MR_AN_COMPLETE 0x00000004
3014#define MR_PAGE_RX 0x00000008
3015#define MR_NP_LOADED 0x00000010
3016#define MR_TOGGLE_TX 0x00000020
3017#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3018#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3019#define MR_LP_ADV_SYM_PAUSE 0x00000100
3020#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3021#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3022#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3023#define MR_LP_ADV_NEXT_PAGE 0x00001000
3024#define MR_TOGGLE_RX 0x00002000
3025#define MR_NP_RX 0x00004000
3026
3027#define MR_LINK_OK 0x80000000
3028
3029 unsigned long link_time, cur_time;
3030
3031 u32 ability_match_cfg;
3032 int ability_match_count;
3033
3034 char ability_match, idle_match, ack_match;
3035
3036 u32 txconfig, rxconfig;
3037#define ANEG_CFG_NP 0x00000080
3038#define ANEG_CFG_ACK 0x00000040
3039#define ANEG_CFG_RF2 0x00000020
3040#define ANEG_CFG_RF1 0x00000010
3041#define ANEG_CFG_PS2 0x00000001
3042#define ANEG_CFG_PS1 0x00008000
3043#define ANEG_CFG_HD 0x00004000
3044#define ANEG_CFG_FD 0x00002000
3045#define ANEG_CFG_INVAL 0x00001f06
3046
3047};
3048#define ANEG_OK 0
3049#define ANEG_DONE 1
3050#define ANEG_TIMER_ENAB 2
3051#define ANEG_FAILED -1
3052
3053#define ANEG_STATE_SETTLE_TIME 10000
3054
3055static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3056 struct tg3_fiber_aneginfo *ap)
3057{
5be73b47 3058 u16 flowctrl;
1da177e4
LT		 3059 unsigned long delta;
3060 u32 rx_cfg_reg;
3061 int ret;
3062
3063 if (ap->state == ANEG_STATE_UNKNOWN) {
3064 ap->rxconfig = 0;
3065 ap->link_time = 0;
3066 ap->cur_time = 0;
3067 ap->ability_match_cfg = 0;
3068 ap->ability_match_count = 0;
3069 ap->ability_match = 0;
3070 ap->idle_match = 0;
3071 ap->ack_match = 0;
3072 }
3073 ap->cur_time++;
3074
3075 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3076 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3077
3078 if (rx_cfg_reg != ap->ability_match_cfg) {
3079 ap->ability_match_cfg = rx_cfg_reg;
3080 ap->ability_match = 0;
3081 ap->ability_match_count = 0;
3082 } else {
3083 if (++ap->ability_match_count > 1) {
3084 ap->ability_match = 1;
3085 ap->ability_match_cfg = rx_cfg_reg;
3086 }
3087 }
3088 if (rx_cfg_reg & ANEG_CFG_ACK)
3089 ap->ack_match = 1;
3090 else
3091 ap->ack_match = 0;
3092
3093 ap->idle_match = 0;
3094 } else {
3095 ap->idle_match = 1;
3096 ap->ability_match_cfg = 0;
3097 ap->ability_match_count = 0;
3098 ap->ability_match = 0;
3099 ap->ack_match = 0;
3100
3101 rx_cfg_reg = 0;
3102 }
3103
3104 ap->rxconfig = rx_cfg_reg;
3105 ret = ANEG_OK;
3106
3107 switch(ap->state) {
3108 case ANEG_STATE_UNKNOWN:
3109 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3110 ap->state = ANEG_STATE_AN_ENABLE;
3111
3112 /* fallthru */
3113 case ANEG_STATE_AN_ENABLE:
3114 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3115 if (ap->flags & MR_AN_ENABLE) {
3116 ap->link_time = 0;
3117 ap->cur_time = 0;
3118 ap->ability_match_cfg = 0;
3119 ap->ability_match_count = 0;
3120 ap->ability_match = 0;
3121 ap->idle_match = 0;
3122 ap->ack_match = 0;
3123
3124 ap->state = ANEG_STATE_RESTART_INIT;
3125 } else {
3126 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3127 }
3128 break;
3129
3130 case ANEG_STATE_RESTART_INIT:
3131 ap->link_time = ap->cur_time;
3132 ap->flags &= ~(MR_NP_LOADED);
3133 ap->txconfig = 0;
3134 tw32(MAC_TX_AUTO_NEG, 0);
3135 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3136 tw32_f(MAC_MODE, tp->mac_mode);
3137 udelay(40);
3138
3139 ret = ANEG_TIMER_ENAB;
3140 ap->state = ANEG_STATE_RESTART;
3141
3142 /* fallthru */
3143 case ANEG_STATE_RESTART:
3144 delta = ap->cur_time - ap->link_time;
3145 if (delta > ANEG_STATE_SETTLE_TIME) {
3146 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3147 } else {
3148 ret = ANEG_TIMER_ENAB;
3149 }
3150 break;
3151
3152 case ANEG_STATE_DISABLE_LINK_OK:
3153 ret = ANEG_DONE;
3154 break;
3155
3156 case ANEG_STATE_ABILITY_DETECT_INIT:
3157 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3158 ap->txconfig = ANEG_CFG_FD;
3159 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3160 if (flowctrl & ADVERTISE_1000XPAUSE)
3161 ap->txconfig |= ANEG_CFG_PS1;
3162 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3163 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3164 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3165 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3166 tw32_f(MAC_MODE, tp->mac_mode);
3167 udelay(40);
3168
3169 ap->state = ANEG_STATE_ABILITY_DETECT;
3170 break;
3171
3172 case ANEG_STATE_ABILITY_DETECT:
3173 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3174 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3175 }
3176 break;
3177
3178 case ANEG_STATE_ACK_DETECT_INIT:
3179 ap->txconfig |= ANEG_CFG_ACK;
3180 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3181 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3182 tw32_f(MAC_MODE, tp->mac_mode);
3183 udelay(40);
3184
3185 ap->state = ANEG_STATE_ACK_DETECT;
3186
3187 /* fallthru */
3188 case ANEG_STATE_ACK_DETECT:
3189 if (ap->ack_match != 0) {
3190 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3191 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3192 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3193 } else {
3194 ap->state = ANEG_STATE_AN_ENABLE;
3195 }
3196 } else if (ap->ability_match != 0 &&
3197 ap->rxconfig == 0) {
3198 ap->state = ANEG_STATE_AN_ENABLE;
3199 }
3200 break;
3201
3202 case ANEG_STATE_COMPLETE_ACK_INIT:
3203 if (ap->rxconfig & ANEG_CFG_INVAL) {
3204 ret = ANEG_FAILED;
3205 break;
3206 }
3207 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3208 MR_LP_ADV_HALF_DUPLEX |
3209 MR_LP_ADV_SYM_PAUSE |
3210 MR_LP_ADV_ASYM_PAUSE |
3211 MR_LP_ADV_REMOTE_FAULT1 |
3212 MR_LP_ADV_REMOTE_FAULT2 |
3213 MR_LP_ADV_NEXT_PAGE |
3214 MR_TOGGLE_RX |
3215 MR_NP_RX);
3216 if (ap->rxconfig & ANEG_CFG_FD)
3217 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3218 if (ap->rxconfig & ANEG_CFG_HD)
3219 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3220 if (ap->rxconfig & ANEG_CFG_PS1)
3221 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3222 if (ap->rxconfig & ANEG_CFG_PS2)
3223 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3224 if (ap->rxconfig & ANEG_CFG_RF1)
3225 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3226 if (ap->rxconfig & ANEG_CFG_RF2)
3227 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3228 if (ap->rxconfig & ANEG_CFG_NP)
3229 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3230
3231 ap->link_time = ap->cur_time;
3232
3233 ap->flags ^= (MR_TOGGLE_TX);
3234 if (ap->rxconfig & 0x0008)
3235 ap->flags |= MR_TOGGLE_RX;
3236 if (ap->rxconfig & ANEG_CFG_NP)
3237 ap->flags |= MR_NP_RX;
3238 ap->flags |= MR_PAGE_RX;
3239
3240 ap->state = ANEG_STATE_COMPLETE_ACK;
3241 ret = ANEG_TIMER_ENAB;
3242 break;
3243
3244 case ANEG_STATE_COMPLETE_ACK:
3245 if (ap->ability_match != 0 &&
3246 ap->rxconfig == 0) {
3247 ap->state = ANEG_STATE_AN_ENABLE;
3248 break;
3249 }
3250 delta = ap->cur_time - ap->link_time;
3251 if (delta > ANEG_STATE_SETTLE_TIME) {
3252 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3253 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3254 } else {
3255 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3256 !(ap->flags & MR_NP_RX)) {
3257 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3258 } else {
3259 ret = ANEG_FAILED;
3260 }
3261 }
3262 }
3263 break;
3264
3265 case ANEG_STATE_IDLE_DETECT_INIT:
3266 ap->link_time = ap->cur_time;
3267 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3268 tw32_f(MAC_MODE, tp->mac_mode);
3269 udelay(40);
3270
3271 ap->state = ANEG_STATE_IDLE_DETECT;
3272 ret = ANEG_TIMER_ENAB;
3273 break;
3274
3275 case ANEG_STATE_IDLE_DETECT:
3276 if (ap->ability_match != 0 &&
3277 ap->rxconfig == 0) {
3278 ap->state = ANEG_STATE_AN_ENABLE;
3279 break;
3280 }
3281 delta = ap->cur_time - ap->link_time;
3282 if (delta > ANEG_STATE_SETTLE_TIME) {
3283 /* XXX another gem from the Broadcom driver :( */
3284 ap->state = ANEG_STATE_LINK_OK;
3285 }
3286 break;
3287
3288 case ANEG_STATE_LINK_OK:
3289 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3290 ret = ANEG_DONE;
3291 break;
3292
3293 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3294 /* ??? unimplemented */
3295 break;
3296
3297 case ANEG_STATE_NEXT_PAGE_WAIT:
3298 /* ??? unimplemented */
3299 break;
3300
3301 default:
3302 ret = ANEG_FAILED;
3303 break;
855e1111 3304 }
1da177e4
LT		 3305
3306 return ret;
3307}
3308
5be73b47 3309static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3310{
3311 int res = 0;
3312 struct tg3_fiber_aneginfo aninfo;
3313 int status = ANEG_FAILED;
3314 unsigned int tick;
3315 u32 tmp;
3316
3317 tw32_f(MAC_TX_AUTO_NEG, 0);
3318
3319 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3320 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3321 udelay(40);
3322
3323 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3324 udelay(40);
3325
3326 memset(&aninfo, 0, sizeof(aninfo));
3327 aninfo.flags |= MR_AN_ENABLE;
3328 aninfo.state = ANEG_STATE_UNKNOWN;
3329 aninfo.cur_time = 0;
3330 tick = 0;
3331 while (++tick < 195000) {
3332 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3333 if (status == ANEG_DONE || status == ANEG_FAILED)
3334 break;
3335
3336 udelay(1);
3337 }
3338
3339 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3340 tw32_f(MAC_MODE, tp->mac_mode);
3341 udelay(40);
3342
5be73b47
MC		 3343 *txflags = aninfo.txconfig;
3344 *rxflags = aninfo.flags;
1da177e4
LT		 3345
3346 if (status == ANEG_DONE &&
3347 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3348 MR_LP_ADV_FULL_DUPLEX)))
3349 res = 1;
3350
3351 return res;
3352}
3353
3354static void tg3_init_bcm8002(struct tg3 *tp)
3355{
3356 u32 mac_status = tr32(MAC_STATUS);
3357 int i;
3358
3359 /* Reset when initting first time or we have a link. */
3360 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3361 !(mac_status & MAC_STATUS_PCS_SYNCED))
3362 return;
3363
3364 /* Set PLL lock range. */
3365 tg3_writephy(tp, 0x16, 0x8007);
3366
3367 /* SW reset */
3368 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3369
3370 /* Wait for reset to complete. */
3371 /* XXX schedule_timeout() ... */
3372 for (i = 0; i < 500; i++)
3373 udelay(10);
3374
3375 /* Config mode; select PMA/Ch 1 regs. */
3376 tg3_writephy(tp, 0x10, 0x8411);
3377
3378 /* Enable auto-lock and comdet, select txclk for tx. */
3379 tg3_writephy(tp, 0x11, 0x0a10);
3380
3381 tg3_writephy(tp, 0x18, 0x00a0);
3382 tg3_writephy(tp, 0x16, 0x41ff);
3383
3384 /* Assert and deassert POR. */
3385 tg3_writephy(tp, 0x13, 0x0400);
3386 udelay(40);
3387 tg3_writephy(tp, 0x13, 0x0000);
3388
3389 tg3_writephy(tp, 0x11, 0x0a50);
3390 udelay(40);
3391 tg3_writephy(tp, 0x11, 0x0a10);
3392
3393 /* Wait for signal to stabilize */
3394 /* XXX schedule_timeout() ... */
3395 for (i = 0; i < 15000; i++)
3396 udelay(10);
3397
3398 /* Deselect the channel register so we can read the PHYID
3399 * later.
3400 */
3401 tg3_writephy(tp, 0x10, 0x8011);
3402}
3403
3404static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3405{
82cd3d11 3406 u16 flowctrl;
1da177e4
LT		 3407 u32 sg_dig_ctrl, sg_dig_status;
3408 u32 serdes_cfg, expected_sg_dig_ctrl;
3409 int workaround, port_a;
3410 int current_link_up;
3411
3412 serdes_cfg = 0;
3413 expected_sg_dig_ctrl = 0;
3414 workaround = 0;
3415 port_a = 1;
3416 current_link_up = 0;
3417
3418 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3419 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3420 workaround = 1;
3421 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3422 port_a = 0;
3423
3424 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3425 /* preserve bits 20-23 for voltage regulator */
3426 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3427 }
3428
3429 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3430
3431 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3432 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3433 if (workaround) {
3434 u32 val = serdes_cfg;
3435
3436 if (port_a)
3437 val |= 0xc010000;
3438 else
3439 val |= 0x4010000;
3440 tw32_f(MAC_SERDES_CFG, val);
3441 }
c98f6e3b
MC		 3442
3443 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3444 }
3445 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3446 tg3_setup_flow_control(tp, 0, 0);
3447 current_link_up = 1;
3448 }
3449 goto out;
3450 }
3451
3452 /* Want auto-negotiation. */
c98f6e3b 3453 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3454
82cd3d11
MC		 3455 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3456 if (flowctrl & ADVERTISE_1000XPAUSE)
3457 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3458 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3459 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3460
3461 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3462 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3463 tp->serdes_counter &&
3464 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3465 MAC_STATUS_RCVD_CFG)) ==
3466 MAC_STATUS_PCS_SYNCED)) {
3467 tp->serdes_counter--;
3468 current_link_up = 1;
3469 goto out;
3470 }
3471restart_autoneg:
1da177e4
LT		 3472 if (workaround)
3473 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3474 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3475 udelay(5);
3476 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3477
3d3ebe74
MC		 3478 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3479 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3480 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3481 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3482 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3483 mac_status = tr32(MAC_STATUS);
3484
c98f6e3b 3485 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3486 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3487 u32 local_adv = 0, remote_adv = 0;
3488
3489 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3490 local_adv |= ADVERTISE_1000XPAUSE;
3491 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3492 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3493
c98f6e3b 3494 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3495 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3496 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3497 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3498
3499 tg3_setup_flow_control(tp, local_adv, remote_adv);
3500 current_link_up = 1;
3d3ebe74
MC		 3501 tp->serdes_counter = 0;
3502 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3503 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3504 if (tp->serdes_counter)
3505 tp->serdes_counter--;
1da177e4
LT		 3506 else {
3507 if (workaround) {
3508 u32 val = serdes_cfg;
3509
3510 if (port_a)
3511 val |= 0xc010000;
3512 else
3513 val |= 0x4010000;
3514
3515 tw32_f(MAC_SERDES_CFG, val);
3516 }
3517
c98f6e3b 3518 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3519 udelay(40);
3520
3521 /* Link parallel detection - link is up */
3522 /* only if we have PCS_SYNC and not */
3523 /* receiving config code words */
3524 mac_status = tr32(MAC_STATUS);
3525 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3526 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3527 tg3_setup_flow_control(tp, 0, 0);
3528 current_link_up = 1;
3d3ebe74
MC		 3529 tp->tg3_flags2 |=
3530 TG3_FLG2_PARALLEL_DETECT;
3531 tp->serdes_counter =
3532 SERDES_PARALLEL_DET_TIMEOUT;
3533 } else
3534 goto restart_autoneg;
1da177e4
LT		 3535 }
3536 }
3d3ebe74
MC		 3537 } else {
3538 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3539 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3540 }
3541
3542out:
3543 return current_link_up;
3544}
3545
3546static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3547{
3548 int current_link_up = 0;
3549
5cf64b8a 3550 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3551 goto out;
1da177e4
LT		 3552
3553 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3554 u32 txflags, rxflags;
1da177e4 3555 int i;
6aa20a22 3556
5be73b47
MC		 3557 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3558 u32 local_adv = 0, remote_adv = 0;
1da177e4 3559
5be73b47
MC		 3560 if (txflags & ANEG_CFG_PS1)
3561 local_adv |= ADVERTISE_1000XPAUSE;
3562 if (txflags & ANEG_CFG_PS2)
3563 local_adv |= ADVERTISE_1000XPSE_ASYM;
3564
3565 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3566 remote_adv |= LPA_1000XPAUSE;
3567 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3568 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3569
3570 tg3_setup_flow_control(tp, local_adv, remote_adv);
3571
1da177e4
LT		 3572 current_link_up = 1;
3573 }
3574 for (i = 0; i < 30; i++) {
3575 udelay(20);
3576 tw32_f(MAC_STATUS,
3577 (MAC_STATUS_SYNC_CHANGED |
3578 MAC_STATUS_CFG_CHANGED));
3579 udelay(40);
3580 if ((tr32(MAC_STATUS) &
3581 (MAC_STATUS_SYNC_CHANGED |
3582 MAC_STATUS_CFG_CHANGED)) == 0)
3583 break;
3584 }
3585
3586 mac_status = tr32(MAC_STATUS);
3587 if (current_link_up == 0 &&
3588 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3589 !(mac_status & MAC_STATUS_RCVD_CFG))
3590 current_link_up = 1;
3591 } else {
5be73b47
MC		 3592 tg3_setup_flow_control(tp, 0, 0);
3593
1da177e4
LT		 3594 /* Forcing 1000FD link up. */
3595 current_link_up = 1;
1da177e4
LT		 3596
3597 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3598 udelay(40);
e8f3f6ca
MC		 3599
3600 tw32_f(MAC_MODE, tp->mac_mode);
3601 udelay(40);
1da177e4
LT		 3602 }
3603
3604out:
3605 return current_link_up;
3606}
3607
3608static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3609{
3610 u32 orig_pause_cfg;
3611 u16 orig_active_speed;
3612 u8 orig_active_duplex;
3613 u32 mac_status;
3614 int current_link_up;
3615 int i;
3616
8d018621 3617 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3618 orig_active_speed = tp->link_config.active_speed;
3619 orig_active_duplex = tp->link_config.active_duplex;
3620
3621 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3622 netif_carrier_ok(tp->dev) &&
3623 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3624 mac_status = tr32(MAC_STATUS);
3625 mac_status &= (MAC_STATUS_PCS_SYNCED |
3626 MAC_STATUS_SIGNAL_DET |
3627 MAC_STATUS_CFG_CHANGED |
3628 MAC_STATUS_RCVD_CFG);
3629 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3630 MAC_STATUS_SIGNAL_DET)) {
3631 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3632 MAC_STATUS_CFG_CHANGED));
3633 return 0;
3634 }
3635 }
3636
3637 tw32_f(MAC_TX_AUTO_NEG, 0);
3638
3639 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3640 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3641 tw32_f(MAC_MODE, tp->mac_mode);
3642 udelay(40);
3643
3644 if (tp->phy_id == PHY_ID_BCM8002)
3645 tg3_init_bcm8002(tp);
3646
3647 /* Enable link change event even when serdes polling. */
3648 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3649 udelay(40);
3650
3651 current_link_up = 0;
3652 mac_status = tr32(MAC_STATUS);
3653
3654 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3655 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3656 else
3657 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3658
1da177e4
LT		 3659 tp->hw_status->status =
3660 (SD_STATUS_UPDATED |
3661 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3662
3663 for (i = 0; i < 100; i++) {
3664 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3665 MAC_STATUS_CFG_CHANGED));
3666 udelay(5);
3667 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3668 MAC_STATUS_CFG_CHANGED |
3669 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3670 break;
3671 }
3672
3673 mac_status = tr32(MAC_STATUS);
3674 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3675 current_link_up = 0;
3d3ebe74
MC		 3676 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3677 tp->serdes_counter == 0) {
1da177e4
LT		 3678 tw32_f(MAC_MODE, (tp->mac_mode |
3679 MAC_MODE_SEND_CONFIGS));
3680 udelay(1);
3681 tw32_f(MAC_MODE, tp->mac_mode);
3682 }
3683 }
3684
3685 if (current_link_up == 1) {
3686 tp->link_config.active_speed = SPEED_1000;
3687 tp->link_config.active_duplex = DUPLEX_FULL;
3688 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3689 LED_CTRL_LNKLED_OVERRIDE |
3690 LED_CTRL_1000MBPS_ON));
3691 } else {
3692 tp->link_config.active_speed = SPEED_INVALID;
3693 tp->link_config.active_duplex = DUPLEX_INVALID;
3694 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3695 LED_CTRL_LNKLED_OVERRIDE |
3696 LED_CTRL_TRAFFIC_OVERRIDE));
3697 }
3698
3699 if (current_link_up != netif_carrier_ok(tp->dev)) {
3700 if (current_link_up)
3701 netif_carrier_on(tp->dev);
3702 else
3703 netif_carrier_off(tp->dev);
3704 tg3_link_report(tp);
3705 } else {
8d018621 3706 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3707 if (orig_pause_cfg != now_pause_cfg ||
3708 orig_active_speed != tp->link_config.active_speed ||
3709 orig_active_duplex != tp->link_config.active_duplex)
3710 tg3_link_report(tp);
3711 }
3712
3713 return 0;
3714}
3715
747e8f8b
MC		 3716static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3717{
3718 int current_link_up, err = 0;
3719 u32 bmsr, bmcr;
3720 u16 current_speed;
3721 u8 current_duplex;
ef167e27 3722 u32 local_adv, remote_adv;
747e8f8b
MC		 3723
3724 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3725 tw32_f(MAC_MODE, tp->mac_mode);
3726 udelay(40);
3727
3728 tw32(MAC_EVENT, 0);
3729
3730 tw32_f(MAC_STATUS,
3731 (MAC_STATUS_SYNC_CHANGED |
3732 MAC_STATUS_CFG_CHANGED |
3733 MAC_STATUS_MI_COMPLETION |
3734 MAC_STATUS_LNKSTATE_CHANGED));
3735 udelay(40);
3736
3737 if (force_reset)
3738 tg3_phy_reset(tp);
3739
3740 current_link_up = 0;
3741 current_speed = SPEED_INVALID;
3742 current_duplex = DUPLEX_INVALID;
3743
3744 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3745 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3746 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3747 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3748 bmsr |= BMSR_LSTATUS;
3749 else
3750 bmsr &= ~BMSR_LSTATUS;
3751 }
747e8f8b
MC		 3752
3753 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3754
3755 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3756 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 3757 /* do nothing, just check for link up at the end */
3758 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3759 u32 adv, new_adv;
3760
3761 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3762 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3763 ADVERTISE_1000XPAUSE |
3764 ADVERTISE_1000XPSE_ASYM |
3765 ADVERTISE_SLCT);
3766
ba4d07a8 3767 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 3768
3769 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3770 new_adv |= ADVERTISE_1000XHALF;
3771 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3772 new_adv |= ADVERTISE_1000XFULL;
3773
3774 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3775 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3776 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3777 tg3_writephy(tp, MII_BMCR, bmcr);
3778
3779 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 3780 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 3781 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3782
3783 return err;
3784 }
3785 } else {
3786 u32 new_bmcr;
3787
3788 bmcr &= ~BMCR_SPEED1000;
3789 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3790
3791 if (tp->link_config.duplex == DUPLEX_FULL)
3792 new_bmcr |= BMCR_FULLDPLX;
3793
3794 if (new_bmcr != bmcr) {
3795 /* BMCR_SPEED1000 is a reserved bit that needs
3796 * to be set on write.
3797 */
3798 new_bmcr |= BMCR_SPEED1000;
3799
3800 /* Force a linkdown */
3801 if (netif_carrier_ok(tp->dev)) {
3802 u32 adv;
3803
3804 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3805 adv &= ~(ADVERTISE_1000XFULL |
3806 ADVERTISE_1000XHALF |
3807 ADVERTISE_SLCT);
3808 tg3_writephy(tp, MII_ADVERTISE, adv);
3809 tg3_writephy(tp, MII_BMCR, bmcr |
3810 BMCR_ANRESTART |
3811 BMCR_ANENABLE);
3812 udelay(10);
3813 netif_carrier_off(tp->dev);
3814 }
3815 tg3_writephy(tp, MII_BMCR, new_bmcr);
3816 bmcr = new_bmcr;
3817 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3818 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3819 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3820 ASIC_REV_5714) {
3821 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3822 bmsr |= BMSR_LSTATUS;
3823 else
3824 bmsr &= ~BMSR_LSTATUS;
3825 }
747e8f8b
MC		 3826 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3827 }
3828 }
3829
3830 if (bmsr & BMSR_LSTATUS) {
3831 current_speed = SPEED_1000;
3832 current_link_up = 1;
3833 if (bmcr & BMCR_FULLDPLX)
3834 current_duplex = DUPLEX_FULL;
3835 else
3836 current_duplex = DUPLEX_HALF;
3837
ef167e27
MC		 3838 local_adv = 0;
3839 remote_adv = 0;
3840
747e8f8b 3841 if (bmcr & BMCR_ANENABLE) {
ef167e27 3842 u32 common;
747e8f8b
MC		 3843
3844 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3845 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3846 common = local_adv & remote_adv;
3847 if (common & (ADVERTISE_1000XHALF |
3848 ADVERTISE_1000XFULL)) {
3849 if (common & ADVERTISE_1000XFULL)
3850 current_duplex = DUPLEX_FULL;
3851 else
3852 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 3853 }
3854 else
3855 current_link_up = 0;
3856 }
3857 }
3858
ef167e27
MC		 3859 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3860 tg3_setup_flow_control(tp, local_adv, remote_adv);
3861
747e8f8b
MC		 3862 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3863 if (tp->link_config.active_duplex == DUPLEX_HALF)
3864 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3865
3866 tw32_f(MAC_MODE, tp->mac_mode);
3867 udelay(40);
3868
3869 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3870
3871 tp->link_config.active_speed = current_speed;
3872 tp->link_config.active_duplex = current_duplex;
3873
3874 if (current_link_up != netif_carrier_ok(tp->dev)) {
3875 if (current_link_up)
3876 netif_carrier_on(tp->dev);
3877 else {
3878 netif_carrier_off(tp->dev);
3879 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3880 }
3881 tg3_link_report(tp);
3882 }
3883 return err;
3884}
3885
3886static void tg3_serdes_parallel_detect(struct tg3 *tp)
3887{
3d3ebe74 3888 if (tp->serdes_counter) {
747e8f8b 3889 /* Give autoneg time to complete. */
3d3ebe74 3890 tp->serdes_counter--;
747e8f8b
MC		 3891 return;
3892 }
3893 if (!netif_carrier_ok(tp->dev) &&
3894 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3895 u32 bmcr;
3896
3897 tg3_readphy(tp, MII_BMCR, &bmcr);
3898 if (bmcr & BMCR_ANENABLE) {
3899 u32 phy1, phy2;
3900
3901 /* Select shadow register 0x1f */
3902 tg3_writephy(tp, 0x1c, 0x7c00);
3903 tg3_readphy(tp, 0x1c, &phy1);
3904
3905 /* Select expansion interrupt status register */
3906 tg3_writephy(tp, 0x17, 0x0f01);
3907 tg3_readphy(tp, 0x15, &phy2);
3908 tg3_readphy(tp, 0x15, &phy2);
3909
3910 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3911 /* We have signal detect and not receiving
3912 * config code words, link is up by parallel
3913 * detection.
3914 */
3915
3916 bmcr &= ~BMCR_ANENABLE;
3917 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3918 tg3_writephy(tp, MII_BMCR, bmcr);
3919 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3920 }
3921 }
3922 }
3923 else if (netif_carrier_ok(tp->dev) &&
3924 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3925 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3926 u32 phy2;
3927
3928 /* Select expansion interrupt status register */
3929 tg3_writephy(tp, 0x17, 0x0f01);
3930 tg3_readphy(tp, 0x15, &phy2);
3931 if (phy2 & 0x20) {
3932 u32 bmcr;
3933
3934 /* Config code words received, turn on autoneg. */
3935 tg3_readphy(tp, MII_BMCR, &bmcr);
3936 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3937
3938 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3939
3940 }
3941 }
3942}
3943
1da177e4
LT		 3944static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3945{
3946 int err;
3947
3948 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3949 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 3950 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3951 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 3952 } else {
3953 err = tg3_setup_copper_phy(tp, force_reset);
3954 }
3955
bcb37f6c 3956 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 3957 u32 val, scale;
3958
3959 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3960 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3961 scale = 65;
3962 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3963 scale = 6;
3964 else
3965 scale = 12;
3966
3967 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3968 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3969 tw32(GRC_MISC_CFG, val);
3970 }
3971
1da177e4
LT		 3972 if (tp->link_config.active_speed == SPEED_1000 &&
3973 tp->link_config.active_duplex == DUPLEX_HALF)
3974 tw32(MAC_TX_LENGTHS,
3975 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3976 (6 << TX_LENGTHS_IPG_SHIFT) |
3977 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3978 else
3979 tw32(MAC_TX_LENGTHS,
3980 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3981 (6 << TX_LENGTHS_IPG_SHIFT) |
3982 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3983
3984 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3985 if (netif_carrier_ok(tp->dev)) {
3986 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 3987 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 3988 } else {
3989 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3990 }
3991 }
3992
8ed5d97e
MC		 3993 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3994 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3995 if (!netif_carrier_ok(tp->dev))
3996 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3997 tp->pwrmgmt_thresh;
3998 else
3999 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4000 tw32(PCIE_PWR_MGMT_THRESH, val);
4001 }
4002
1da177e4
LT		 4003 return err;
4004}
4005
df3e6548
MC		 4006/* This is called whenever we suspect that the system chipset is re-
4007 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4008 * is bogus tx completions. We try to recover by setting the
4009 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4010 * in the workqueue.
4011 */
4012static void tg3_tx_recover(struct tg3 *tp)
4013{
4014 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4015 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4016
4017 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4018 "mapped I/O cycles to the network device, attempting to "
4019 "recover. Please report the problem to the driver maintainer "
4020 "and include system chipset information.\n", tp->dev->name);
4021
4022 spin_lock(&tp->lock);
df3e6548 4023 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4024 spin_unlock(&tp->lock);
4025}
4026
1b2a7205
MC		 4027static inline u32 tg3_tx_avail(struct tg3 *tp)
4028{
4029 smp_mb();
4030 return (tp->tx_pending -
4031 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4032}
4033
1da177e4
LT		 4034/* Tigon3 never reports partial packet sends. So we do not
4035 * need special logic to handle SKBs that have not had all
4036 * of their frags sent yet, like SunGEM does.
4037 */
4038static void tg3_tx(struct tg3 *tp)
4039{
4040 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4041 u32 sw_idx = tp->tx_cons;
4042
4043 while (sw_idx != hw_idx) {
4044 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4045 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4046 int i, tx_bug = 0;
4047
4048 if (unlikely(skb == NULL)) {
4049 tg3_tx_recover(tp);
4050 return;
4051 }
1da177e4 4052
90079ce8 4053 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4054
4055 ri->skb = NULL;
4056
4057 sw_idx = NEXT_TX(sw_idx);
4058
4059 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4060 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4061 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4062 tx_bug = 1;
1da177e4
LT		 4063 sw_idx = NEXT_TX(sw_idx);
4064 }
4065
f47c11ee 4066 dev_kfree_skb(skb);
df3e6548
MC		 4067
4068 if (unlikely(tx_bug)) {
4069 tg3_tx_recover(tp);
4070 return;
4071 }
1da177e4
LT		 4072 }
4073
4074 tp->tx_cons = sw_idx;
4075
1b2a7205
MC		 4076 /* Need to make the tx_cons update visible to tg3_start_xmit()
4077 * before checking for netif_queue_stopped(). Without the
4078 * memory barrier, there is a small possibility that tg3_start_xmit()
4079 * will miss it and cause the queue to be stopped forever.
4080 */
4081 smp_mb();
4082
4083 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4084 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4085 netif_tx_lock(tp->dev);
51b91468 4086 if (netif_queue_stopped(tp->dev) &&
42952231 4087 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4088 netif_wake_queue(tp->dev);
1b2a7205 4089 netif_tx_unlock(tp->dev);
51b91468 4090 }
1da177e4
LT		 4091}
4092
4093/* Returns size of skb allocated or < 0 on error.
4094 *
4095 * We only need to fill in the address because the other members
4096 * of the RX descriptor are invariant, see tg3_init_rings.
4097 *
4098 * Note the purposeful assymetry of cpu vs. chip accesses. For
4099 * posting buffers we only dirty the first cache line of the RX
4100 * descriptor (containing the address). Whereas for the RX status
4101 * buffers the cpu only reads the last cacheline of the RX descriptor
4102 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4103 */
4104static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4105 int src_idx, u32 dest_idx_unmasked)
4106{
4107 struct tg3_rx_buffer_desc *desc;
4108 struct ring_info *map, *src_map;
4109 struct sk_buff *skb;
4110 dma_addr_t mapping;
4111 int skb_size, dest_idx;
4112
4113 src_map = NULL;
4114 switch (opaque_key) {
4115 case RXD_OPAQUE_RING_STD:
4116 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4117 desc = &tp->rx_std[dest_idx];
4118 map = &tp->rx_std_buffers[dest_idx];
4119 if (src_idx >= 0)
4120 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 4121 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 4122 break;
4123
4124 case RXD_OPAQUE_RING_JUMBO:
4125 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4126 desc = &tp->rx_jumbo[dest_idx];
4127 map = &tp->rx_jumbo_buffers[dest_idx];
4128 if (src_idx >= 0)
4129 src_map = &tp->rx_jumbo_buffers[src_idx];
4130 skb_size = RX_JUMBO_PKT_BUF_SZ;
4131 break;
4132
4133 default:
4134 return -EINVAL;
855e1111 4135 }
1da177e4
LT		 4136
4137 /* Do not overwrite any of the map or rp information
4138 * until we are sure we can commit to a new buffer.
4139 *
4140 * Callers depend upon this behavior and assume that
4141 * we leave everything unchanged if we fail.
4142 */
a20e9c62 4143 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 4144 if (skb == NULL)
4145 return -ENOMEM;
4146
1da177e4
LT		 4147 skb_reserve(skb, tp->rx_offset);
4148
4149 mapping = pci_map_single(tp->pdev, skb->data,
4150 skb_size - tp->rx_offset,
4151 PCI_DMA_FROMDEVICE);
4152
4153 map->skb = skb;
4154 pci_unmap_addr_set(map, mapping, mapping);
4155
4156 if (src_map != NULL)
4157 src_map->skb = NULL;
4158
4159 desc->addr_hi = ((u64)mapping >> 32);
4160 desc->addr_lo = ((u64)mapping & 0xffffffff);
4161
4162 return skb_size;
4163}
4164
4165/* We only need to move over in the address because the other
4166 * members of the RX descriptor are invariant. See notes above
4167 * tg3_alloc_rx_skb for full details.
4168 */
4169static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4170 int src_idx, u32 dest_idx_unmasked)
4171{
4172 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4173 struct ring_info *src_map, *dest_map;
4174 int dest_idx;
4175
4176 switch (opaque_key) {
4177 case RXD_OPAQUE_RING_STD:
4178 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4179 dest_desc = &tp->rx_std[dest_idx];
4180 dest_map = &tp->rx_std_buffers[dest_idx];
4181 src_desc = &tp->rx_std[src_idx];
4182 src_map = &tp->rx_std_buffers[src_idx];
4183 break;
4184
4185 case RXD_OPAQUE_RING_JUMBO:
4186 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4187 dest_desc = &tp->rx_jumbo[dest_idx];
4188 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4189 src_desc = &tp->rx_jumbo[src_idx];
4190 src_map = &tp->rx_jumbo_buffers[src_idx];
4191 break;
4192
4193 default:
4194 return;
855e1111 4195 }
1da177e4
LT		 4196
4197 dest_map->skb = src_map->skb;
4198 pci_unmap_addr_set(dest_map, mapping,
4199 pci_unmap_addr(src_map, mapping));
4200 dest_desc->addr_hi = src_desc->addr_hi;
4201 dest_desc->addr_lo = src_desc->addr_lo;
4202
4203 src_map->skb = NULL;
4204}
4205
4206#if TG3_VLAN_TAG_USED
4207static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4208{
4209 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4210}
4211#endif
4212
4213/* The RX ring scheme is composed of multiple rings which post fresh
4214 * buffers to the chip, and one special ring the chip uses to report
4215 * status back to the host.
4216 *
4217 * The special ring reports the status of received packets to the
4218 * host. The chip does not write into the original descriptor the
4219 * RX buffer was obtained from. The chip simply takes the original
4220 * descriptor as provided by the host, updates the status and length
4221 * field, then writes this into the next status ring entry.
4222 *
4223 * Each ring the host uses to post buffers to the chip is described
4224 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4225 * it is first placed into the on-chip ram. When the packet's length
4226 * is known, it walks down the TG3_BDINFO entries to select the ring.
4227 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4228 * which is within the range of the new packet's length is chosen.
4229 *
4230 * The "separate ring for rx status" scheme may sound queer, but it makes
4231 * sense from a cache coherency perspective. If only the host writes
4232 * to the buffer post rings, and only the chip writes to the rx status
4233 * rings, then cache lines never move beyond shared-modified state.
4234 * If both the host and chip were to write into the same ring, cache line
4235 * eviction could occur since both entities want it in an exclusive state.
4236 */
4237static int tg3_rx(struct tg3 *tp, int budget)
4238{
f92905de 4239 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4240 u32 sw_idx = tp->rx_rcb_ptr;
4241 u16 hw_idx;
1da177e4
LT		 4242 int received;
4243
4244 hw_idx = tp->hw_status->idx[0].rx_producer;
4245 /*
4246 * We need to order the read of hw_idx and the read of
4247 * the opaque cookie.
4248 */
4249 rmb();
1da177e4
LT		 4250 work_mask = 0;
4251 received = 0;
4252 while (sw_idx != hw_idx && budget > 0) {
4253 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4254 unsigned int len;
4255 struct sk_buff *skb;
4256 dma_addr_t dma_addr;
4257 u32 opaque_key, desc_idx, *post_ptr;
4258
4259 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4260 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4261 if (opaque_key == RXD_OPAQUE_RING_STD) {
4262 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4263 mapping);
4264 skb = tp->rx_std_buffers[desc_idx].skb;
4265 post_ptr = &tp->rx_std_ptr;
f92905de 4266 rx_std_posted++;
1da177e4
LT		 4267 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4268 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4269 mapping);
4270 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4271 post_ptr = &tp->rx_jumbo_ptr;
4272 }
4273 else {
4274 goto next_pkt_nopost;
4275 }
4276
4277 work_mask |= opaque_key;
4278
4279 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4280 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4281 drop_it:
4282 tg3_recycle_rx(tp, opaque_key,
4283 desc_idx, *post_ptr);
4284 drop_it_no_recycle:
4285 /* Other statistics kept track of by card. */
4286 tp->net_stats.rx_dropped++;
4287 goto next_pkt;
4288 }
4289
ad829268
MC		 4290 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4291 ETH_FCS_LEN;
1da177e4 4292
6aa20a22 4293 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4294 && tp->rx_offset == NET_IP_ALIGN
4295 /* rx_offset will likely not equal NET_IP_ALIGN
4296 * if this is a 5701 card running in PCI-X mode
4297 * [see tg3_get_invariants()]
4298 */
1da177e4
LT		 4299 ) {
4300 int skb_size;
4301
4302 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4303 desc_idx, *post_ptr);
4304 if (skb_size < 0)
4305 goto drop_it;
4306
4307 pci_unmap_single(tp->pdev, dma_addr,
4308 skb_size - tp->rx_offset,
4309 PCI_DMA_FROMDEVICE);
4310
4311 skb_put(skb, len);
4312 } else {
4313 struct sk_buff *copy_skb;
4314
4315 tg3_recycle_rx(tp, opaque_key,
4316 desc_idx, *post_ptr);
4317
ad829268
MC		 4318 copy_skb = netdev_alloc_skb(tp->dev,
4319 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4320 if (copy_skb == NULL)
4321 goto drop_it_no_recycle;
4322
ad829268 4323 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4324 skb_put(copy_skb, len);
4325 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4326 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4327 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4328
4329 /* We'll reuse the original ring buffer. */
4330 skb = copy_skb;
4331 }
4332
4333 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4334 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4335 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4336 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4337 skb->ip_summed = CHECKSUM_UNNECESSARY;
4338 else
4339 skb->ip_summed = CHECKSUM_NONE;
4340
4341 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4342
4343 if (len > (tp->dev->mtu + ETH_HLEN) &&
4344 skb->protocol != htons(ETH_P_8021Q)) {
4345 dev_kfree_skb(skb);
4346 goto next_pkt;
4347 }
4348
1da177e4
LT		 4349#if TG3_VLAN_TAG_USED
4350 if (tp->vlgrp != NULL &&
4351 desc->type_flags & RXD_FLAG_VLAN) {
4352 tg3_vlan_rx(tp, skb,
4353 desc->err_vlan & RXD_VLAN_MASK);
4354 } else
4355#endif
4356 netif_receive_skb(skb);
4357
1da177e4
LT		 4358 received++;
4359 budget--;
4360
4361next_pkt:
4362 (*post_ptr)++;
f92905de
MC		 4363
4364 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4365 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4366
4367 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4368 TG3_64BIT_REG_LOW, idx);
4369 work_mask &= ~RXD_OPAQUE_RING_STD;
4370 rx_std_posted = 0;
4371 }
1da177e4 4372next_pkt_nopost:
483ba50b 4373 sw_idx++;
6b31a515 4374 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4375
4376 /* Refresh hw_idx to see if there is new work */
4377 if (sw_idx == hw_idx) {
4378 hw_idx = tp->hw_status->idx[0].rx_producer;
4379 rmb();
4380 }
1da177e4
LT		 4381 }
4382
4383 /* ACK the status ring. */
483ba50b
MC		 4384 tp->rx_rcb_ptr = sw_idx;
4385 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4386
4387 /* Refill RX ring(s). */
4388 if (work_mask & RXD_OPAQUE_RING_STD) {
4389 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4390 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4391 sw_idx);
4392 }
4393 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4394 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4395 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4396 sw_idx);
4397 }
4398 mmiowb();
4399
4400 return received;
4401}
4402
6f535763 4403static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4404{
1da177e4 4405 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4406
1da177e4
LT		 4407 /* handle link change and other phy events */
4408 if (!(tp->tg3_flags &
4409 (TG3_FLAG_USE_LINKCHG_REG |
4410 TG3_FLAG_POLL_SERDES))) {
4411 if (sblk->status & SD_STATUS_LINK_CHG) {
4412 sblk->status = SD_STATUS_UPDATED |
4413 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4414 spin_lock(&tp->lock);
dd477003
MC		 4415 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4416 tw32_f(MAC_STATUS,
4417 (MAC_STATUS_SYNC_CHANGED |
4418 MAC_STATUS_CFG_CHANGED |
4419 MAC_STATUS_MI_COMPLETION |
4420 MAC_STATUS_LNKSTATE_CHANGED));
4421 udelay(40);
4422 } else
4423 tg3_setup_phy(tp, 0);
f47c11ee 4424 spin_unlock(&tp->lock);
1da177e4
LT		 4425 }
4426 }
4427
4428 /* run TX completion thread */
4429 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4430 tg3_tx(tp);
6f535763 4431 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4432 return work_done;
1da177e4
LT		 4433 }
4434
1da177e4
LT		 4435 /* run RX thread, within the bounds set by NAPI.
4436 * All RX "locking" is done by ensuring outside
bea3348e 4437 * code synchronizes with tg3->napi.poll()
1da177e4 4438 */
bea3348e 4439 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4440 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4441
6f535763
DM		 4442 return work_done;
4443}
4444
4445static int tg3_poll(struct napi_struct *napi, int budget)
4446{
4447 struct tg3 *tp = container_of(napi, struct tg3, napi);
4448 int work_done = 0;
4fd7ab59 4449 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4450
4451 while (1) {
4452 work_done = tg3_poll_work(tp, work_done, budget);
4453
4454 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4455 goto tx_recovery;
4456
4457 if (unlikely(work_done >= budget))
4458 break;
4459
4fd7ab59
MC		 4460 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4461 /* tp->last_tag is used in tg3_restart_ints() below
4462 * to tell the hw how much work has been processed,
4463 * so we must read it before checking for more work.
4464 */
4465 tp->last_tag = sblk->status_tag;
4466 rmb();
4467 } else
4468 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4469
4fd7ab59 4470 if (likely(!tg3_has_work(tp))) {
288379f0 4471 napi_complete(napi);
6f535763
DM		 4472 tg3_restart_ints(tp);
4473 break;
4474 }
1da177e4
LT		 4475 }
4476
bea3348e 4477 return work_done;
6f535763
DM		 4478
4479tx_recovery:
4fd7ab59 4480 /* work_done is guaranteed to be less than budget. */
288379f0 4481 napi_complete(napi);
6f535763 4482 schedule_work(&tp->reset_task);
4fd7ab59 4483 return work_done;
1da177e4
LT		 4484}
4485
f47c11ee
DM		 4486static void tg3_irq_quiesce(struct tg3 *tp)
4487{
4488 BUG_ON(tp->irq_sync);
4489
4490 tp->irq_sync = 1;
4491 smp_mb();
4492
4493 synchronize_irq(tp->pdev->irq);
4494}
4495
4496static inline int tg3_irq_sync(struct tg3 *tp)
4497{
4498 return tp->irq_sync;
4499}
4500
4501/* Fully shutdown all tg3 driver activity elsewhere in the system.
4502 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4503 * with as well. Most of the time, this is not necessary except when
4504 * shutting down the device.
4505 */
4506static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4507{
46966545 4508 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4509 if (irq_sync)
4510 tg3_irq_quiesce(tp);
f47c11ee
DM		 4511}
4512
4513static inline void tg3_full_unlock(struct tg3 *tp)
4514{
f47c11ee
DM		 4515 spin_unlock_bh(&tp->lock);
4516}
4517
fcfa0a32
MC		 4518/* One-shot MSI handler - Chip automatically disables interrupt
4519 * after sending MSI so driver doesn't have to do it.
4520 */
7d12e780 4521static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4522{
4523 struct net_device *dev = dev_id;
4524 struct tg3 *tp = netdev_priv(dev);
4525
4526 prefetch(tp->hw_status);
4527 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4528
4529 if (likely(!tg3_irq_sync(tp)))
288379f0 4530 napi_schedule(&tp->napi);
fcfa0a32
MC		 4531
4532 return IRQ_HANDLED;
4533}
4534
88b06bc2
MC		 4535/* MSI ISR - No need to check for interrupt sharing and no need to
4536 * flush status block and interrupt mailbox. PCI ordering rules
4537 * guarantee that MSI will arrive after the status block.
4538 */
7d12e780 4539static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4540{
4541 struct net_device *dev = dev_id;
4542 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4543
61487480
MC		 4544 prefetch(tp->hw_status);
4545 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4546 /*
fac9b83e 4547 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4548 * chip-internal interrupt pending events.
fac9b83e 4549 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4550 * NIC to stop sending us irqs, engaging "in-intr-handler"
4551 * event coalescing.
4552 */
4553 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4554 if (likely(!tg3_irq_sync(tp)))
288379f0 4555 napi_schedule(&tp->napi);
61487480 4556
88b06bc2
MC		 4557 return IRQ_RETVAL(1);
4558}
4559
7d12e780 4560static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4561{
4562 struct net_device *dev = dev_id;
4563 struct tg3 *tp = netdev_priv(dev);
4564 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4565 unsigned int handled = 1;
4566
1da177e4
LT		 4567 /* In INTx mode, it is possible for the interrupt to arrive at
4568 * the CPU before the status block posted prior to the interrupt.
4569 * Reading the PCI State register will confirm whether the
4570 * interrupt is ours and will flush the status block.
4571 */
d18edcb2
MC		 4572 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4573 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4574 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4575 handled = 0;
f47c11ee 4576 goto out;
fac9b83e 4577 }
d18edcb2
MC		 4578 }
4579
4580 /*
4581 * Writing any value to intr-mbox-0 clears PCI INTA# and
4582 * chip-internal interrupt pending events.
4583 * Writing non-zero to intr-mbox-0 additional tells the
4584 * NIC to stop sending us irqs, engaging "in-intr-handler"
4585 * event coalescing.
c04cb347
MC		 4586 *
4587 * Flush the mailbox to de-assert the IRQ immediately to prevent
4588 * spurious interrupts. The flush impacts performance but
4589 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4590 */
c04cb347 4591 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4592 if (tg3_irq_sync(tp))
4593 goto out;
4594 sblk->status &= ~SD_STATUS_UPDATED;
4595 if (likely(tg3_has_work(tp))) {
4596 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4597 napi_schedule(&tp->napi);
d18edcb2
MC		 4598 } else {
4599 /* No work, shared interrupt perhaps? re-enable
4600 * interrupts, and flush that PCI write
4601 */
4602 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4603 0x00000000);
fac9b83e 4604 }
f47c11ee 4605out:
fac9b83e
DM		 4606 return IRQ_RETVAL(handled);
4607}
4608
7d12e780 4609static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4610{
4611 struct net_device *dev = dev_id;
4612 struct tg3 *tp = netdev_priv(dev);
4613 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4614 unsigned int handled = 1;
4615
fac9b83e
DM		 4616 /* In INTx mode, it is possible for the interrupt to arrive at
4617 * the CPU before the status block posted prior to the interrupt.
4618 * Reading the PCI State register will confirm whether the
4619 * interrupt is ours and will flush the status block.
4620 */
d18edcb2
MC		 4621 if (unlikely(sblk->status_tag == tp->last_tag)) {
4622 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4623 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4624 handled = 0;
f47c11ee 4625 goto out;
1da177e4 4626 }
d18edcb2
MC		 4627 }
4628
4629 /*
4630 * writing any value to intr-mbox-0 clears PCI INTA# and
4631 * chip-internal interrupt pending events.
4632 * writing non-zero to intr-mbox-0 additional tells the
4633 * NIC to stop sending us irqs, engaging "in-intr-handler"
4634 * event coalescing.
c04cb347
MC		 4635 *
4636 * Flush the mailbox to de-assert the IRQ immediately to prevent
4637 * spurious interrupts. The flush impacts performance but
4638 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4639 */
c04cb347 4640 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4641 if (tg3_irq_sync(tp))
4642 goto out;
288379f0 4643 if (napi_schedule_prep(&tp->napi)) {
d18edcb2
MC		 4644 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4645 /* Update last_tag to mark that this status has been
4646 * seen. Because interrupt may be shared, we may be
4647 * racing with tg3_poll(), so only update last_tag
4648 * if tg3_poll() is not scheduled.
4649 */
4650 tp->last_tag = sblk->status_tag;
288379f0 4651 __napi_schedule(&tp->napi);
1da177e4 4652 }
f47c11ee 4653out:
1da177e4
LT		 4654 return IRQ_RETVAL(handled);
4655}
4656
7938109f 4657/* ISR for interrupt test */
7d12e780 4658static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4659{
4660 struct net_device *dev = dev_id;
4661 struct tg3 *tp = netdev_priv(dev);
4662 struct tg3_hw_status *sblk = tp->hw_status;
4663
f9804ddb
MC		 4664 if ((sblk->status & SD_STATUS_UPDATED) ||
4665 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4666 tg3_disable_ints(tp);
7938109f
MC		 4667 return IRQ_RETVAL(1);
4668 }
4669 return IRQ_RETVAL(0);
4670}
4671
8e7a22e3 4672static int tg3_init_hw(struct tg3 *, int);
944d980e 4673static int tg3_halt(struct tg3 *, int, int);
1da177e4 4674
b9ec6c1b
MC		 4675/* Restart hardware after configuration changes, self-test, etc.
4676 * Invoked with tp->lock held.
4677 */
4678static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4679 __releases(tp->lock)
4680 __acquires(tp->lock)
b9ec6c1b
MC		 4681{
4682 int err;
4683
4684 err = tg3_init_hw(tp, reset_phy);
4685 if (err) {
4686 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4687 "aborting.\n", tp->dev->name);
4688 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4689 tg3_full_unlock(tp);
4690 del_timer_sync(&tp->timer);
4691 tp->irq_sync = 0;
bea3348e 4692 napi_enable(&tp->napi);
b9ec6c1b
MC		 4693 dev_close(tp->dev);
4694 tg3_full_lock(tp, 0);
4695 }
4696 return err;
4697}
4698
1da177e4
LT		 4699#ifdef CONFIG_NET_POLL_CONTROLLER
4700static void tg3_poll_controller(struct net_device *dev)
4701{
88b06bc2
MC		 4702 struct tg3 *tp = netdev_priv(dev);
4703
7d12e780 4704 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4705}
4706#endif
4707
c4028958 4708static void tg3_reset_task(struct work_struct *work)
1da177e4 4709{
c4028958 4710 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4711 int err;
1da177e4
LT		 4712 unsigned int restart_timer;
4713
7faa006f 4714 tg3_full_lock(tp, 0);
7faa006f
MC		 4715
4716 if (!netif_running(tp->dev)) {
7faa006f
MC		 4717 tg3_full_unlock(tp);
4718 return;
4719 }
4720
4721 tg3_full_unlock(tp);
4722
b02fd9e3
MC		 4723 tg3_phy_stop(tp);
4724
1da177e4
LT		 4725 tg3_netif_stop(tp);
4726
f47c11ee 4727 tg3_full_lock(tp, 1);
1da177e4
LT		 4728
4729 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4730 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4731
df3e6548
MC		 4732 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4733 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4734 tp->write32_rx_mbox = tg3_write_flush_reg32;
4735 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4736 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4737 }
4738
944d980e 4739 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4740 err = tg3_init_hw(tp, 1);
4741 if (err)
b9ec6c1b 4742 goto out;
1da177e4
LT		 4743
4744 tg3_netif_start(tp);
4745
1da177e4
LT		 4746 if (restart_timer)
4747 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4748
b9ec6c1b 4749out:
7faa006f 4750 tg3_full_unlock(tp);
b02fd9e3
MC		 4751
4752 if (!err)
4753 tg3_phy_start(tp);
1da177e4
LT		 4754}
4755
b0408751
MC		 4756static void tg3_dump_short_state(struct tg3 *tp)
4757{
4758 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4759 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4760 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4761 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4762}
4763
1da177e4
LT		 4764static void tg3_tx_timeout(struct net_device *dev)
4765{
4766 struct tg3 *tp = netdev_priv(dev);
4767
b0408751 4768 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 4769 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4770 dev->name);
b0408751
MC		 4771 tg3_dump_short_state(tp);
4772 }
1da177e4
LT		 4773
4774 schedule_work(&tp->reset_task);
4775}
4776
c58ec932
MC		 4777/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4778static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4779{
4780 u32 base = (u32) mapping & 0xffffffff;
4781
4782 return ((base > 0xffffdcc0) &&
4783 (base + len + 8 < base));
4784}
4785
72f2afb8
MC		 4786/* Test for DMA addresses > 40-bit */
4787static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4788 int len)
4789{
4790#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 4791 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 4792 return (((u64) mapping + len) > DMA_40BIT_MASK);
4793 return 0;
4794#else
4795 return 0;
4796#endif
4797}
4798
1da177e4
LT		 4799static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4800
72f2afb8
MC		 4801/* Workaround 4GB and 40-bit hardware DMA bugs. */
4802static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 4803 u32 last_plus_one, u32 *start,
4804 u32 base_flags, u32 mss)
1da177e4 4805{
41588ba1 4806 struct sk_buff *new_skb;
c58ec932 4807 dma_addr_t new_addr = 0;
1da177e4 4808 u32 entry = *start;
c58ec932 4809 int i, ret = 0;
1da177e4 4810
41588ba1
MC		 4811 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4812 new_skb = skb_copy(skb, GFP_ATOMIC);
4813 else {
4814 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4815
4816 new_skb = skb_copy_expand(skb,
4817 skb_headroom(skb) + more_headroom,
4818 skb_tailroom(skb), GFP_ATOMIC);
4819 }
4820
1da177e4 4821 if (!new_skb) {
c58ec932
MC		 4822 ret = -1;
4823 } else {
4824 /* New SKB is guaranteed to be linear. */
4825 entry = *start;
90079ce8
DM		 4826 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
4827 new_addr = skb_shinfo(new_skb)->dma_maps[0];
4828
c58ec932
MC		 4829 /* Make sure new skb does not cross any 4G boundaries.
4830 * Drop the packet if it does.
4831 */
90079ce8 4832 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 4833 if (!ret)
4834 skb_dma_unmap(&tp->pdev->dev, new_skb,
4835 DMA_TO_DEVICE);
c58ec932
MC		 4836 ret = -1;
4837 dev_kfree_skb(new_skb);
4838 new_skb = NULL;
4839 } else {
4840 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4841 base_flags, 1 | (mss << 1));
4842 *start = NEXT_TX(entry);
4843 }
1da177e4
LT		 4844 }
4845
1da177e4
LT		 4846 /* Now clean up the sw ring entries. */
4847 i = 0;
4848 while (entry != last_plus_one) {
1da177e4
LT		 4849 if (i == 0) {
4850 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 4851 } else {
4852 tp->tx_buffers[entry].skb = NULL;
4853 }
4854 entry = NEXT_TX(entry);
4855 i++;
4856 }
4857
90079ce8 4858 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4859 dev_kfree_skb(skb);
4860
c58ec932 4861 return ret;
1da177e4
LT		 4862}
4863
4864static void tg3_set_txd(struct tg3 *tp, int entry,
4865 dma_addr_t mapping, int len, u32 flags,
4866 u32 mss_and_is_end)
4867{
4868 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4869 int is_end = (mss_and_is_end & 0x1);
4870 u32 mss = (mss_and_is_end >> 1);
4871 u32 vlan_tag = 0;
4872
4873 if (is_end)
4874 flags |= TXD_FLAG_END;
4875 if (flags & TXD_FLAG_VLAN) {
4876 vlan_tag = flags >> 16;
4877 flags &= 0xffff;
4878 }
4879 vlan_tag |= (mss << TXD_MSS_SHIFT);
4880
4881 txd->addr_hi = ((u64) mapping >> 32);
4882 txd->addr_lo = ((u64) mapping & 0xffffffff);
4883 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4884 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4885}
4886
5a6f3074
MC		 4887/* hard_start_xmit for devices that don't have any bugs and
4888 * support TG3_FLG2_HW_TSO_2 only.
4889 */
1da177e4 4890static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 4891{
4892 struct tg3 *tp = netdev_priv(dev);
5a6f3074 4893 u32 len, entry, base_flags, mss;
90079ce8
DM		 4894 struct skb_shared_info *sp;
4895 dma_addr_t mapping;
5a6f3074
MC		 4896
4897 len = skb_headlen(skb);
4898
00b70504 4899 /* We are running in BH disabled context with netif_tx_lock
bea3348e 4900 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 4901 * interrupt. Furthermore, IRQ processing runs lockless so we have
4902 * no IRQ context deadlocks to worry about either. Rejoice!
4903 */
1b2a7205 4904 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 4905 if (!netif_queue_stopped(dev)) {
4906 netif_stop_queue(dev);
4907
4908 /* This is a hard error, log it. */
4909 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4910 "queue awake!\n", dev->name);
4911 }
5a6f3074
MC		 4912 return NETDEV_TX_BUSY;
4913 }
4914
4915 entry = tp->tx_prod;
4916 base_flags = 0;
5a6f3074 4917 mss = 0;
c13e3713 4918 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 4919 int tcp_opt_len, ip_tcp_len;
4920
4921 if (skb_header_cloned(skb) &&
4922 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4923 dev_kfree_skb(skb);
4924 goto out_unlock;
4925 }
4926
b0026624
MC		 4927 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4928 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4929 else {
eddc9ec5
ACM		 4930 struct iphdr *iph = ip_hdr(skb);
4931
ab6a5bb6 4932 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 4933 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 4934
eddc9ec5
ACM		 4935 iph->check = 0;
4936 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 4937 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4938 }
5a6f3074
MC		 4939
4940 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4941 TXD_FLAG_CPU_POST_DMA);
4942
aa8223c7 4943 tcp_hdr(skb)->check = 0;
5a6f3074 4944
5a6f3074 4945 }
84fa7933 4946 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 4947 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 4948#if TG3_VLAN_TAG_USED
4949 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4950 base_flags |= (TXD_FLAG_VLAN |
4951 (vlan_tx_tag_get(skb) << 16));
4952#endif
4953
90079ce8
DM		 4954 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
4955 dev_kfree_skb(skb);
4956 goto out_unlock;
4957 }
4958
4959 sp = skb_shinfo(skb);
4960
4961 mapping = sp->dma_maps[0];
5a6f3074
MC		 4962
4963 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 4964
4965 tg3_set_txd(tp, entry, mapping, len, base_flags,
4966 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4967
4968 entry = NEXT_TX(entry);
4969
4970 /* Now loop through additional data fragments, and queue them. */
4971 if (skb_shinfo(skb)->nr_frags > 0) {
4972 unsigned int i, last;
4973
4974 last = skb_shinfo(skb)->nr_frags - 1;
4975 for (i = 0; i <= last; i++) {
4976 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4977
4978 len = frag->size;
90079ce8 4979 mapping = sp->dma_maps[i + 1];
5a6f3074 4980 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 4981
4982 tg3_set_txd(tp, entry, mapping, len,
4983 base_flags, (i == last) | (mss << 1));
4984
4985 entry = NEXT_TX(entry);
4986 }
4987 }
4988
4989 /* Packets are ready, update Tx producer idx local and on card. */
4990 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4991
4992 tp->tx_prod = entry;
1b2a7205 4993 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 4994 netif_stop_queue(dev);
42952231 4995 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 4996 netif_wake_queue(tp->dev);
4997 }
4998
4999out_unlock:
5000 mmiowb();
5a6f3074
MC		 5001
5002 dev->trans_start = jiffies;
5003
5004 return NETDEV_TX_OK;
5005}
5006
52c0fd83
MC		 5007static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5008
5009/* Use GSO to workaround a rare TSO bug that may be triggered when the
5010 * TSO header is greater than 80 bytes.
5011 */
5012static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5013{
5014 struct sk_buff *segs, *nskb;
5015
5016 /* Estimate the number of fragments in the worst case */
1b2a7205 5017 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5018 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5019 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5020 return NETDEV_TX_BUSY;
5021
5022 netif_wake_queue(tp->dev);
52c0fd83
MC		 5023 }
5024
5025 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5026 if (IS_ERR(segs))
52c0fd83
MC		 5027 goto tg3_tso_bug_end;
5028
5029 do {
5030 nskb = segs;
5031 segs = segs->next;
5032 nskb->next = NULL;
5033 tg3_start_xmit_dma_bug(nskb, tp->dev);
5034 } while (segs);
5035
5036tg3_tso_bug_end:
5037 dev_kfree_skb(skb);
5038
5039 return NETDEV_TX_OK;
5040}
52c0fd83 5041
5a6f3074
MC		 5042/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5043 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5044 */
5045static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5046{
5047 struct tg3 *tp = netdev_priv(dev);
1da177e4 5048 u32 len, entry, base_flags, mss;
90079ce8 5049 struct skb_shared_info *sp;
1da177e4 5050 int would_hit_hwbug;
90079ce8 5051 dma_addr_t mapping;
1da177e4
LT		 5052
5053 len = skb_headlen(skb);
5054
00b70504 5055 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5056 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5057 * interrupt. Furthermore, IRQ processing runs lockless so we have
5058 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5059 */
1b2a7205 5060 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5061 if (!netif_queue_stopped(dev)) {
5062 netif_stop_queue(dev);
5063
5064 /* This is a hard error, log it. */
5065 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5066 "queue awake!\n", dev->name);
5067 }
1da177e4
LT		 5068 return NETDEV_TX_BUSY;
5069 }
5070
5071 entry = tp->tx_prod;
5072 base_flags = 0;
84fa7933 5073 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5074 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5075 mss = 0;
c13e3713 5076 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5077 struct iphdr *iph;
52c0fd83 5078 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5079
5080 if (skb_header_cloned(skb) &&
5081 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5082 dev_kfree_skb(skb);
5083 goto out_unlock;
5084 }
5085
ab6a5bb6 5086 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5087 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5088
52c0fd83
MC		 5089 hdr_len = ip_tcp_len + tcp_opt_len;
5090 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5091 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5092 return (tg3_tso_bug(tp, skb));
5093
1da177e4
LT		 5094 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5095 TXD_FLAG_CPU_POST_DMA);
5096
eddc9ec5
ACM		 5097 iph = ip_hdr(skb);
5098 iph->check = 0;
5099 iph->tot_len = htons(mss + hdr_len);
1da177e4 5100 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5101 tcp_hdr(skb)->check = 0;
1da177e4 5102 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5103 } else
5104 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5105 iph->daddr, 0,
5106 IPPROTO_TCP,
5107 0);
1da177e4
LT		 5108
5109 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5110 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5111 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5112 int tsflags;
5113
eddc9ec5 5114 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5115 mss |= (tsflags << 11);
5116 }
5117 } else {
eddc9ec5 5118 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5119 int tsflags;
5120
eddc9ec5 5121 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5122 base_flags |= tsflags << 12;
5123 }
5124 }
5125 }
1da177e4
LT		 5126#if TG3_VLAN_TAG_USED
5127 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5128 base_flags |= (TXD_FLAG_VLAN |
5129 (vlan_tx_tag_get(skb) << 16));
5130#endif
5131
90079ce8
DM		 5132 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5133 dev_kfree_skb(skb);
5134 goto out_unlock;
5135 }
5136
5137 sp = skb_shinfo(skb);
5138
5139 mapping = sp->dma_maps[0];
1da177e4
LT		 5140
5141 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5142
5143 would_hit_hwbug = 0;
5144
41588ba1
MC		 5145 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5146 would_hit_hwbug = 1;
5147 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5148 would_hit_hwbug = 1;
1da177e4
LT		 5149
5150 tg3_set_txd(tp, entry, mapping, len, base_flags,
5151 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5152
5153 entry = NEXT_TX(entry);
5154
5155 /* Now loop through additional data fragments, and queue them. */
5156 if (skb_shinfo(skb)->nr_frags > 0) {
5157 unsigned int i, last;
5158
5159 last = skb_shinfo(skb)->nr_frags - 1;
5160 for (i = 0; i <= last; i++) {
5161 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5162
5163 len = frag->size;
90079ce8 5164 mapping = sp->dma_maps[i + 1];
1da177e4
LT		 5165
5166 tp->tx_buffers[entry].skb = NULL;
1da177e4 5167
c58ec932
MC		 5168 if (tg3_4g_overflow_test(mapping, len))
5169 would_hit_hwbug = 1;
1da177e4 5170
72f2afb8
MC		 5171 if (tg3_40bit_overflow_test(tp, mapping, len))
5172 would_hit_hwbug = 1;
5173
1da177e4
LT		 5174 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5175 tg3_set_txd(tp, entry, mapping, len,
5176 base_flags, (i == last)|(mss << 1));
5177 else
5178 tg3_set_txd(tp, entry, mapping, len,
5179 base_flags, (i == last));
5180
5181 entry = NEXT_TX(entry);
5182 }
5183 }
5184
5185 if (would_hit_hwbug) {
5186 u32 last_plus_one = entry;
5187 u32 start;
1da177e4 5188
c58ec932
MC		 5189 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5190 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5191
5192 /* If the workaround fails due to memory/mapping
5193 * failure, silently drop this packet.
5194 */
72f2afb8 5195 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5196 &start, base_flags, mss))
1da177e4
LT		 5197 goto out_unlock;
5198
5199 entry = start;
5200 }
5201
5202 /* Packets are ready, update Tx producer idx local and on card. */
5203 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5204
5205 tp->tx_prod = entry;
1b2a7205 5206 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5207 netif_stop_queue(dev);
42952231 5208 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5209 netif_wake_queue(tp->dev);
5210 }
1da177e4
LT		 5211
5212out_unlock:
5213 mmiowb();
1da177e4
LT		 5214
5215 dev->trans_start = jiffies;
5216
5217 return NETDEV_TX_OK;
5218}
5219
5220static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5221 int new_mtu)
5222{
5223 dev->mtu = new_mtu;
5224
ef7f5ec0 5225 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5226 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5227 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5228 ethtool_op_set_tso(dev, 0);
5229 }
5230 else
5231 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5232 } else {
a4e2b347 5233 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5234 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5235 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5236 }
1da177e4
LT		 5237}
5238
5239static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5240{
5241 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5242 int err;
1da177e4
LT		 5243
5244 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5245 return -EINVAL;
5246
5247 if (!netif_running(dev)) {
5248 /* We'll just catch it later when the
5249 * device is up'd.
5250 */
5251 tg3_set_mtu(dev, tp, new_mtu);
5252 return 0;
5253 }
5254
b02fd9e3
MC		 5255 tg3_phy_stop(tp);
5256
1da177e4 5257 tg3_netif_stop(tp);
f47c11ee
DM		 5258
5259 tg3_full_lock(tp, 1);
1da177e4 5260
944d980e 5261 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5262
5263 tg3_set_mtu(dev, tp, new_mtu);
5264
b9ec6c1b 5265 err = tg3_restart_hw(tp, 0);
1da177e4 5266
b9ec6c1b
MC		 5267 if (!err)
5268 tg3_netif_start(tp);
1da177e4 5269
f47c11ee 5270 tg3_full_unlock(tp);
1da177e4 5271
b02fd9e3
MC		 5272 if (!err)
5273 tg3_phy_start(tp);
5274
b9ec6c1b 5275 return err;
1da177e4
LT		 5276}
5277
5278/* Free up pending packets in all rx/tx rings.
5279 *
5280 * The chip has been shut down and the driver detached from
5281 * the networking, so no interrupts or new tx packets will
5282 * end up in the driver. tp->{tx,}lock is not held and we are not
5283 * in an interrupt context and thus may sleep.
5284 */
5285static void tg3_free_rings(struct tg3 *tp)
5286{
5287 struct ring_info *rxp;
5288 int i;
5289
5290 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5291 rxp = &tp->rx_std_buffers[i];
5292
5293 if (rxp->skb == NULL)
5294 continue;
5295 pci_unmap_single(tp->pdev,
5296 pci_unmap_addr(rxp, mapping),
7e72aad4 5297 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 5298 PCI_DMA_FROMDEVICE);
5299 dev_kfree_skb_any(rxp->skb);
5300 rxp->skb = NULL;
5301 }
5302
5303 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5304 rxp = &tp->rx_jumbo_buffers[i];
5305
5306 if (rxp->skb == NULL)
5307 continue;
5308 pci_unmap_single(tp->pdev,
5309 pci_unmap_addr(rxp, mapping),
5310 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5311 PCI_DMA_FROMDEVICE);
5312 dev_kfree_skb_any(rxp->skb);
5313 rxp->skb = NULL;
5314 }
5315
5316 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5317 struct tx_ring_info *txp;
5318 struct sk_buff *skb;
1da177e4
LT		 5319
5320 txp = &tp->tx_buffers[i];
5321 skb = txp->skb;
5322
5323 if (skb == NULL) {
5324 i++;
5325 continue;
5326 }
5327
90079ce8 5328 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5329
90079ce8 5330 txp->skb = NULL;
1da177e4 5331
90079ce8 5332 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5333
5334 dev_kfree_skb_any(skb);
5335 }
5336}
5337
5338/* Initialize tx/rx rings for packet processing.
5339 *
5340 * The chip has been shut down and the driver detached from
5341 * the networking, so no interrupts or new tx packets will
5342 * end up in the driver. tp->{tx,}lock are held and thus
5343 * we may not sleep.
5344 */
32d8c572 5345static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 5346{
5347 u32 i;
5348
5349 /* Free up all the SKBs. */
5350 tg3_free_rings(tp);
5351
5352 /* Zero out all descriptors. */
5353 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5354 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5355 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5356 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5357
7e72aad4 5358 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 5359 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 5360 (tp->dev->mtu > ETH_DATA_LEN))
5361 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5362
1da177e4
LT		 5363 /* Initialize invariants of the rings, we only set this
5364 * stuff once. This works because the card does not
5365 * write into the rx buffer posting rings.
5366 */
5367 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5368 struct tg3_rx_buffer_desc *rxd;
5369
5370 rxd = &tp->rx_std[i];
7e72aad4 5371 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 5372 << RXD_LEN_SHIFT;
5373 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5374 rxd->opaque = (RXD_OPAQUE_RING_STD |
5375 (i << RXD_OPAQUE_INDEX_SHIFT));
5376 }
5377
0f893dc6 5378 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5379 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5380 struct tg3_rx_buffer_desc *rxd;
5381
5382 rxd = &tp->rx_jumbo[i];
5383 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5384 << RXD_LEN_SHIFT;
5385 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5386 RXD_FLAG_JUMBO;
5387 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5388 (i << RXD_OPAQUE_INDEX_SHIFT));
5389 }
5390 }
5391
5392 /* Now allocate fresh SKBs for each rx ring. */
5393 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5394 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5395 printk(KERN_WARNING PFX
5396 "%s: Using a smaller RX standard ring, "
5397 "only %d out of %d buffers were allocated "
5398 "successfully.\n",
5399 tp->dev->name, i, tp->rx_pending);
5400 if (i == 0)
5401 return -ENOMEM;
5402 tp->rx_pending = i;
1da177e4 5403 break;
32d8c572 5404 }
1da177e4
LT		 5405 }
5406
0f893dc6 5407 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5408 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5409 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5410 -1, i) < 0) {
5411 printk(KERN_WARNING PFX
5412 "%s: Using a smaller RX jumbo ring, "
5413 "only %d out of %d buffers were "
5414 "allocated successfully.\n",
5415 tp->dev->name, i, tp->rx_jumbo_pending);
5416 if (i == 0) {
5417 tg3_free_rings(tp);
5418 return -ENOMEM;
5419 }
5420 tp->rx_jumbo_pending = i;
1da177e4 5421 break;
32d8c572 5422 }
1da177e4
LT		 5423 }
5424 }
32d8c572 5425 return 0;
1da177e4
LT		 5426}
5427
5428/*
5429 * Must not be invoked with interrupt sources disabled and
5430 * the hardware shutdown down.
5431 */
5432static void tg3_free_consistent(struct tg3 *tp)
5433{
b4558ea9
JJ		 5434 kfree(tp->rx_std_buffers);
5435 tp->rx_std_buffers = NULL;
1da177e4
LT		 5436 if (tp->rx_std) {
5437 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5438 tp->rx_std, tp->rx_std_mapping);
5439 tp->rx_std = NULL;
5440 }
5441 if (tp->rx_jumbo) {
5442 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5443 tp->rx_jumbo, tp->rx_jumbo_mapping);
5444 tp->rx_jumbo = NULL;
5445 }
5446 if (tp->rx_rcb) {
5447 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5448 tp->rx_rcb, tp->rx_rcb_mapping);
5449 tp->rx_rcb = NULL;
5450 }
5451 if (tp->tx_ring) {
5452 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5453 tp->tx_ring, tp->tx_desc_mapping);
5454 tp->tx_ring = NULL;
5455 }
5456 if (tp->hw_status) {
5457 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5458 tp->hw_status, tp->status_mapping);
5459 tp->hw_status = NULL;
5460 }
5461 if (tp->hw_stats) {
5462 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5463 tp->hw_stats, tp->stats_mapping);
5464 tp->hw_stats = NULL;
5465 }
5466}
5467
5468/*
5469 * Must not be invoked with interrupt sources disabled and
5470 * the hardware shutdown down. Can sleep.
5471 */
5472static int tg3_alloc_consistent(struct tg3 *tp)
5473{
bd2b3343 5474 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5475 (TG3_RX_RING_SIZE +
5476 TG3_RX_JUMBO_RING_SIZE)) +
5477 (sizeof(struct tx_ring_info) *
5478 TG3_TX_RING_SIZE),
5479 GFP_KERNEL);
5480 if (!tp->rx_std_buffers)
5481 return -ENOMEM;
5482
1da177e4
LT		 5483 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5484 tp->tx_buffers = (struct tx_ring_info *)
5485 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5486
5487 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5488 &tp->rx_std_mapping);
5489 if (!tp->rx_std)
5490 goto err_out;
5491
5492 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5493 &tp->rx_jumbo_mapping);
5494
5495 if (!tp->rx_jumbo)
5496 goto err_out;
5497
5498 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5499 &tp->rx_rcb_mapping);
5500 if (!tp->rx_rcb)
5501 goto err_out;
5502
5503 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5504 &tp->tx_desc_mapping);
5505 if (!tp->tx_ring)
5506 goto err_out;
5507
5508 tp->hw_status = pci_alloc_consistent(tp->pdev,
5509 TG3_HW_STATUS_SIZE,
5510 &tp->status_mapping);
5511 if (!tp->hw_status)
5512 goto err_out;
5513
5514 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5515 sizeof(struct tg3_hw_stats),
5516 &tp->stats_mapping);
5517 if (!tp->hw_stats)
5518 goto err_out;
5519
5520 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5521 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5522
5523 return 0;
5524
5525err_out:
5526 tg3_free_consistent(tp);
5527 return -ENOMEM;
5528}
5529
5530#define MAX_WAIT_CNT 1000
5531
5532/* To stop a block, clear the enable bit and poll till it
5533 * clears. tp->lock is held.
5534 */
b3b7d6be 5535static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5536{
5537 unsigned int i;
5538 u32 val;
5539
5540 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5541 switch (ofs) {
5542 case RCVLSC_MODE:
5543 case DMAC_MODE:
5544 case MBFREE_MODE:
5545 case BUFMGR_MODE:
5546 case MEMARB_MODE:
5547 /* We can't enable/disable these bits of the
5548 * 5705/5750, just say success.
5549 */
5550 return 0;
5551
5552 default:
5553 break;
855e1111 5554 }
1da177e4
LT		 5555 }
5556
5557 val = tr32(ofs);
5558 val &= ~enable_bit;
5559 tw32_f(ofs, val);
5560
5561 for (i = 0; i < MAX_WAIT_CNT; i++) {
5562 udelay(100);
5563 val = tr32(ofs);
5564 if ((val & enable_bit) == 0)
5565 break;
5566 }
5567
b3b7d6be 5568 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5569 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5570 "ofs=%lx enable_bit=%x\n",
5571 ofs, enable_bit);
5572 return -ENODEV;
5573 }
5574
5575 return 0;
5576}
5577
5578/* tp->lock is held. */
b3b7d6be 5579static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5580{
5581 int i, err;
5582
5583 tg3_disable_ints(tp);
5584
5585 tp->rx_mode &= ~RX_MODE_ENABLE;
5586 tw32_f(MAC_RX_MODE, tp->rx_mode);
5587 udelay(10);
5588
b3b7d6be
DM		 5589 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5590 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5591 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5592 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5593 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5594 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5595
5596 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5597 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5598 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5599 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5600 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5601 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5602 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5603
5604 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5605 tw32_f(MAC_MODE, tp->mac_mode);
5606 udelay(40);
5607
5608 tp->tx_mode &= ~TX_MODE_ENABLE;
5609 tw32_f(MAC_TX_MODE, tp->tx_mode);
5610
5611 for (i = 0; i < MAX_WAIT_CNT; i++) {
5612 udelay(100);
5613 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5614 break;
5615 }
5616 if (i >= MAX_WAIT_CNT) {
5617 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5618 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5619 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5620 err |= -ENODEV;
1da177e4
LT		 5621 }
5622
e6de8ad1 5623 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5624 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5625 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5626
5627 tw32(FTQ_RESET, 0xffffffff);
5628 tw32(FTQ_RESET, 0x00000000);
5629
b3b7d6be
DM		 5630 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5631 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5632
5633 if (tp->hw_status)
5634 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5635 if (tp->hw_stats)
5636 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5637
1da177e4
LT		 5638 return err;
5639}
5640
5641/* tp->lock is held. */
5642static int tg3_nvram_lock(struct tg3 *tp)
5643{
5644 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5645 int i;
5646
ec41c7df
MC		 5647 if (tp->nvram_lock_cnt == 0) {
5648 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5649 for (i = 0; i < 8000; i++) {
5650 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5651 break;
5652 udelay(20);
5653 }
5654 if (i == 8000) {
5655 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5656 return -ENODEV;
5657 }
1da177e4 5658 }
ec41c7df 5659 tp->nvram_lock_cnt++;
1da177e4
LT		 5660 }
5661 return 0;
5662}
5663
5664/* tp->lock is held. */
5665static void tg3_nvram_unlock(struct tg3 *tp)
5666{
ec41c7df
MC		 5667 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5668 if (tp->nvram_lock_cnt > 0)
5669 tp->nvram_lock_cnt--;
5670 if (tp->nvram_lock_cnt == 0)
5671 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5672 }
1da177e4
LT		 5673}
5674
e6af301b
MC		 5675/* tp->lock is held. */
5676static void tg3_enable_nvram_access(struct tg3 *tp)
5677{
5678 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5679 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5680 u32 nvaccess = tr32(NVRAM_ACCESS);
5681
5682 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5683 }
5684}
5685
5686/* tp->lock is held. */
5687static void tg3_disable_nvram_access(struct tg3 *tp)
5688{
5689 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5690 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5691 u32 nvaccess = tr32(NVRAM_ACCESS);
5692
5693 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5694 }
5695}
5696
0d3031d9
MC		 5697static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5698{
5699 int i;
5700 u32 apedata;
5701
5702 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5703 if (apedata != APE_SEG_SIG_MAGIC)
5704 return;
5705
5706 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5707 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5708 return;
5709
5710 /* Wait for up to 1 millisecond for APE to service previous event. */
5711 for (i = 0; i < 10; i++) {
5712 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5713 return;
5714
5715 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5716
5717 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5718 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5719 event | APE_EVENT_STATUS_EVENT_PENDING);
5720
5721 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5722
5723 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5724 break;
5725
5726 udelay(100);
5727 }
5728
5729 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5730 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5731}
5732
5733static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5734{
5735 u32 event;
5736 u32 apedata;
5737
5738 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5739 return;
5740
5741 switch (kind) {
5742 case RESET_KIND_INIT:
5743 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5744 APE_HOST_SEG_SIG_MAGIC);
5745 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5746 APE_HOST_SEG_LEN_MAGIC);
5747 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5748 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5749 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5750 APE_HOST_DRIVER_ID_MAGIC);
5751 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5752 APE_HOST_BEHAV_NO_PHYLOCK);
5753
5754 event = APE_EVENT_STATUS_STATE_START;
5755 break;
5756 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5757 /* With the interface we are currently using,
5758 * APE does not track driver state. Wiping
5759 * out the HOST SEGMENT SIGNATURE forces
5760 * the APE to assume OS absent status.
5761 */
5762 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5763
0d3031d9
MC		 5764 event = APE_EVENT_STATUS_STATE_UNLOAD;
5765 break;
5766 case RESET_KIND_SUSPEND:
5767 event = APE_EVENT_STATUS_STATE_SUSPEND;
5768 break;
5769 default:
5770 return;
5771 }
5772
5773 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5774
5775 tg3_ape_send_event(tp, event);
5776}
5777
1da177e4
LT		 5778/* tp->lock is held. */
5779static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5780{
f49639e6
DM		 5781 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5782 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5783
5784 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5785 switch (kind) {
5786 case RESET_KIND_INIT:
5787 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5788 DRV_STATE_START);
5789 break;
5790
5791 case RESET_KIND_SHUTDOWN:
5792 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5793 DRV_STATE_UNLOAD);
5794 break;
5795
5796 case RESET_KIND_SUSPEND:
5797 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5798 DRV_STATE_SUSPEND);
5799 break;
5800
5801 default:
5802 break;
855e1111 5803 }
1da177e4 5804 }
0d3031d9
MC		 5805
5806 if (kind == RESET_KIND_INIT ||
5807 kind == RESET_KIND_SUSPEND)
5808 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5809}
5810
5811/* tp->lock is held. */
5812static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5813{
5814 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5815 switch (kind) {
5816 case RESET_KIND_INIT:
5817 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5818 DRV_STATE_START_DONE);
5819 break;
5820
5821 case RESET_KIND_SHUTDOWN:
5822 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5823 DRV_STATE_UNLOAD_DONE);
5824 break;
5825
5826 default:
5827 break;
855e1111 5828 }
1da177e4 5829 }
0d3031d9
MC		 5830
5831 if (kind == RESET_KIND_SHUTDOWN)
5832 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5833}
5834
5835/* tp->lock is held. */
5836static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5837{
5838 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5839 switch (kind) {
5840 case RESET_KIND_INIT:
5841 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5842 DRV_STATE_START);
5843 break;
5844
5845 case RESET_KIND_SHUTDOWN:
5846 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5847 DRV_STATE_UNLOAD);
5848 break;
5849
5850 case RESET_KIND_SUSPEND:
5851 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5852 DRV_STATE_SUSPEND);
5853 break;
5854
5855 default:
5856 break;
855e1111 5857 }
1da177e4
LT		 5858 }
5859}
5860
7a6f4369
MC		 5861static int tg3_poll_fw(struct tg3 *tp)
5862{
5863 int i;
5864 u32 val;
5865
b5d3772c 5866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 5867 /* Wait up to 20ms for init done. */
5868 for (i = 0; i < 200; i++) {
b5d3772c
MC		 5869 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5870 return 0;
0ccead18 5871 udelay(100);
b5d3772c
MC		 5872 }
5873 return -ENODEV;
5874 }
5875
7a6f4369
MC		 5876 /* Wait for firmware initialization to complete. */
5877 for (i = 0; i < 100000; i++) {
5878 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5879 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5880 break;
5881 udelay(10);
5882 }
5883
5884 /* Chip might not be fitted with firmware. Some Sun onboard
5885 * parts are configured like that. So don't signal the timeout
5886 * of the above loop as an error, but do report the lack of
5887 * running firmware once.
5888 */
5889 if (i >= 100000 &&
5890 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5891 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5892
5893 printk(KERN_INFO PFX "%s: No firmware running.\n",
5894 tp->dev->name);
5895 }
5896
5897 return 0;
5898}
5899
ee6a99b5
MC		 5900/* Save PCI command register before chip reset */
5901static void tg3_save_pci_state(struct tg3 *tp)
5902{
8a6eac90 5903 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 5904}
5905
5906/* Restore PCI state after chip reset */
5907static void tg3_restore_pci_state(struct tg3 *tp)
5908{
5909 u32 val;
5910
5911 /* Re-enable indirect register accesses. */
5912 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5913 tp->misc_host_ctrl);
5914
5915 /* Set MAX PCI retry to zero. */
5916 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5917 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5918 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5919 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 5920 /* Allow reads and writes to the APE register and memory space. */
5921 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5922 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5923 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 5924 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5925
8a6eac90 5926 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 5927
fcb389df
MC		 5928 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
5929 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5930 pcie_set_readrq(tp->pdev, 4096);
5931 else {
5932 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5933 tp->pci_cacheline_sz);
5934 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5935 tp->pci_lat_timer);
5936 }
114342f2 5937 }
5f5c51e3 5938
ee6a99b5 5939 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 5940 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 5941 u16 pcix_cmd;
5942
5943 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5944 &pcix_cmd);
5945 pcix_cmd &= ~PCI_X_CMD_ERO;
5946 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5947 pcix_cmd);
5948 }
ee6a99b5
MC		 5949
5950 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 5951
5952 /* Chip reset on 5780 will reset MSI enable bit,
5953 * so need to restore it.
5954 */
5955 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5956 u16 ctrl;
5957
5958 pci_read_config_word(tp->pdev,
5959 tp->msi_cap + PCI_MSI_FLAGS,
5960 &ctrl);
5961 pci_write_config_word(tp->pdev,
5962 tp->msi_cap + PCI_MSI_FLAGS,
5963 ctrl | PCI_MSI_FLAGS_ENABLE);
5964 val = tr32(MSGINT_MODE);
5965 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5966 }
5967 }
5968}
5969
1da177e4
LT		 5970static void tg3_stop_fw(struct tg3 *);
5971
5972/* tp->lock is held. */
5973static int tg3_chip_reset(struct tg3 *tp)
5974{
5975 u32 val;
1ee582d8 5976 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 5977 int err;
1da177e4 5978
f49639e6
DM		 5979 tg3_nvram_lock(tp);
5980
158d7abd
MC		 5981 tg3_mdio_stop(tp);
5982
77b483f1
MC		 5983 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5984
f49639e6
DM		 5985 /* No matching tg3_nvram_unlock() after this because
5986 * chip reset below will undo the nvram lock.
5987 */
5988 tp->nvram_lock_cnt = 0;
1da177e4 5989
ee6a99b5
MC		 5990 /* GRC_MISC_CFG core clock reset will clear the memory
5991 * enable bit in PCI register 4 and the MSI enable bit
5992 * on some chips, so we save relevant registers here.
5993 */
5994 tg3_save_pci_state(tp);
5995
d9ab5ad1 5996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 5997 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 5998 tw32(GRC_FASTBOOT_PC, 0);
5999
1da177e4
LT		 6000 /*
6001 * We must avoid the readl() that normally takes place.
6002 * It locks machines, causes machine checks, and other
6003 * fun things. So, temporarily disable the 5701
6004 * hardware workaround, while we do the reset.
6005 */
1ee582d8
MC		 6006 write_op = tp->write32;
6007 if (write_op == tg3_write_flush_reg32)
6008 tp->write32 = tg3_write32;
1da177e4 6009
d18edcb2
MC		 6010 /* Prevent the irq handler from reading or writing PCI registers
6011 * during chip reset when the memory enable bit in the PCI command
6012 * register may be cleared. The chip does not generate interrupt
6013 * at this time, but the irq handler may still be called due to irq
6014 * sharing or irqpoll.
6015 */
6016 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6017 if (tp->hw_status) {
6018 tp->hw_status->status = 0;
6019 tp->hw_status->status_tag = 0;
6020 }
d18edcb2
MC		 6021 tp->last_tag = 0;
6022 smp_mb();
6023 synchronize_irq(tp->pdev->irq);
6024
1da177e4
LT		 6025 /* do the reset */
6026 val = GRC_MISC_CFG_CORECLK_RESET;
6027
6028 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6029 if (tr32(0x7e2c) == 0x60) {
6030 tw32(0x7e2c, 0x20);
6031 }
6032 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6033 tw32(GRC_MISC_CFG, (1 << 29));
6034 val |= (1 << 29);
6035 }
6036 }
6037
b5d3772c
MC		 6038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6039 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6040 tw32(GRC_VCPU_EXT_CTRL,
6041 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6042 }
6043
1da177e4
LT		 6044 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6045 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6046 tw32(GRC_MISC_CFG, val);
6047
1ee582d8
MC		 6048 /* restore 5701 hardware bug workaround write method */
6049 tp->write32 = write_op;
1da177e4
LT		 6050
6051 /* Unfortunately, we have to delay before the PCI read back.
6052 * Some 575X chips even will not respond to a PCI cfg access
6053 * when the reset command is given to the chip.
6054 *
6055 * How do these hardware designers expect things to work
6056 * properly if the PCI write is posted for a long period
6057 * of time? It is always necessary to have some method by
6058 * which a register read back can occur to push the write
6059 * out which does the reset.
6060 *
6061 * For most tg3 variants the trick below was working.
6062 * Ho hum...
6063 */
6064 udelay(120);
6065
6066 /* Flush PCI posted writes. The normal MMIO registers
6067 * are inaccessible at this time so this is the only
6068 * way to make this reliably (actually, this is no longer
6069 * the case, see above). I tried to use indirect
6070 * register read/write but this upset some 5701 variants.
6071 */
6072 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6073
6074 udelay(120);
6075
5e7dfd0f 6076 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
1da177e4
LT		 6077 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6078 int i;
6079 u32 cfg_val;
6080
6081 /* Wait for link training to complete. */
6082 for (i = 0; i < 5000; i++)
6083 udelay(100);
6084
6085 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6086 pci_write_config_dword(tp->pdev, 0xc4,
6087 cfg_val | (1 << 15));
6088 }
5e7dfd0f
MC		 6089
6090 /* Set PCIE max payload size to 128 bytes and
6091 * clear the "no snoop" and "relaxed ordering" bits.
6092 */
6093 pci_write_config_word(tp->pdev,
6094 tp->pcie_cap + PCI_EXP_DEVCTL,
6095 0);
6096
6097 pcie_set_readrq(tp->pdev, 4096);
6098
6099 /* Clear error status */
6100 pci_write_config_word(tp->pdev,
6101 tp->pcie_cap + PCI_EXP_DEVSTA,
6102 PCI_EXP_DEVSTA_CED |
6103 PCI_EXP_DEVSTA_NFED |
6104 PCI_EXP_DEVSTA_FED |
6105 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6106 }
6107
ee6a99b5 6108 tg3_restore_pci_state(tp);
1da177e4 6109
d18edcb2
MC		 6110 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6111
ee6a99b5
MC		 6112 val = 0;
6113 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6114 val = tr32(MEMARB_MODE);
ee6a99b5 6115 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6116
6117 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6118 tg3_stop_fw(tp);
6119 tw32(0x5000, 0x400);
6120 }
6121
6122 tw32(GRC_MODE, tp->grc_mode);
6123
6124 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6125 val = tr32(0xc4);
1da177e4
LT		 6126
6127 tw32(0xc4, val | (1 << 15));
6128 }
6129
6130 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6131 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6132 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6133 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6134 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6135 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6136 }
6137
6138 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6139 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6140 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6141 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6142 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6143 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6144 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6145 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6146 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6147 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6148 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6149 } else
6150 tw32_f(MAC_MODE, 0);
6151 udelay(40);
6152
158d7abd
MC		 6153 tg3_mdio_start(tp);
6154
77b483f1
MC		 6155 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6156
7a6f4369
MC		 6157 err = tg3_poll_fw(tp);
6158 if (err)
6159 return err;
1da177e4
LT		 6160
6161 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6162 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6163 val = tr32(0x7c00);
1da177e4
LT		 6164
6165 tw32(0x7c00, val | (1 << 25));
6166 }
6167
6168 /* Reprobe ASF enable state. */
6169 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6170 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6171 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6172 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6173 u32 nic_cfg;
6174
6175 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6176 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6177 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6178 tp->last_event_jiffies = jiffies;
cbf46853 6179 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6180 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6181 }
6182 }
6183
6184 return 0;
6185}
6186
6187/* tp->lock is held. */
6188static void tg3_stop_fw(struct tg3 *tp)
6189{
0d3031d9
MC		 6190 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6191 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6192 /* Wait for RX cpu to ACK the previous event. */
6193 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6194
6195 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6196
6197 tg3_generate_fw_event(tp);
1da177e4 6198
7c5026aa
MC		 6199 /* Wait for RX cpu to ACK this event. */
6200 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6201 }
6202}
6203
6204/* tp->lock is held. */
944d980e 6205static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6206{
6207 int err;
6208
6209 tg3_stop_fw(tp);
6210
944d980e 6211 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6212
b3b7d6be 6213 tg3_abort_hw(tp, silent);
1da177e4
LT		 6214 err = tg3_chip_reset(tp);
6215
944d980e
MC		 6216 tg3_write_sig_legacy(tp, kind);
6217 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6218
6219 if (err)
6220 return err;
6221
6222 return 0;
6223}
6224
1da177e4
LT		 6225#define RX_CPU_SCRATCH_BASE 0x30000
6226#define RX_CPU_SCRATCH_SIZE 0x04000
6227#define TX_CPU_SCRATCH_BASE 0x34000
6228#define TX_CPU_SCRATCH_SIZE 0x04000
6229
6230/* tp->lock is held. */
6231static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6232{
6233 int i;
6234
5d9428de
ES		 6235 BUG_ON(offset == TX_CPU_BASE &&
6236 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6237
b5d3772c
MC		 6238 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6239 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6240
6241 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6242 return 0;
6243 }
1da177e4
LT		 6244 if (offset == RX_CPU_BASE) {
6245 for (i = 0; i < 10000; i++) {
6246 tw32(offset + CPU_STATE, 0xffffffff);
6247 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6248 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6249 break;
6250 }
6251
6252 tw32(offset + CPU_STATE, 0xffffffff);
6253 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6254 udelay(10);
6255 } else {
6256 for (i = 0; i < 10000; i++) {
6257 tw32(offset + CPU_STATE, 0xffffffff);
6258 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6259 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6260 break;
6261 }
6262 }
6263
6264 if (i >= 10000) {
6265 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6266 "and %s CPU\n",
6267 tp->dev->name,
6268 (offset == RX_CPU_BASE ? "RX" : "TX"));
6269 return -ENODEV;
6270 }
ec41c7df
MC		 6271
6272 /* Clear firmware's nvram arbitration. */
6273 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6274 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6275 return 0;
6276}
6277
6278struct fw_info {
077f849d
JSR		 6279 unsigned int fw_base;
6280 unsigned int fw_len;
6281 const __be32 *fw_data;
1da177e4
LT		 6282};
6283
6284/* tp->lock is held. */
6285static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6286 int cpu_scratch_size, struct fw_info *info)
6287{
ec41c7df 6288 int err, lock_err, i;
1da177e4
LT		 6289 void (*write_op)(struct tg3 *, u32, u32);
6290
6291 if (cpu_base == TX_CPU_BASE &&
6292 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6293 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6294 "TX cpu firmware on %s which is 5705.\n",
6295 tp->dev->name);
6296 return -EINVAL;
6297 }
6298
6299 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6300 write_op = tg3_write_mem;
6301 else
6302 write_op = tg3_write_indirect_reg32;
6303
1b628151
MC		 6304 /* It is possible that bootcode is still loading at this point.
6305 * Get the nvram lock first before halting the cpu.
6306 */
ec41c7df 6307 lock_err = tg3_nvram_lock(tp);
1da177e4 6308 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6309 if (!lock_err)
6310 tg3_nvram_unlock(tp);
1da177e4
LT		 6311 if (err)
6312 goto out;
6313
6314 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6315 write_op(tp, cpu_scratch_base + i, 0);
6316 tw32(cpu_base + CPU_STATE, 0xffffffff);
6317 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6318 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6319 write_op(tp, (cpu_scratch_base +
077f849d 6320 (info->fw_base & 0xffff) +
1da177e4 6321 (i * sizeof(u32))),
077f849d 6322 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6323
6324 err = 0;
6325
6326out:
1da177e4
LT		 6327 return err;
6328}
6329
6330/* tp->lock is held. */
6331static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6332{
6333 struct fw_info info;
077f849d 6334 const __be32 *fw_data;
1da177e4
LT		 6335 int err, i;
6336
077f849d
JSR		 6337 fw_data = (void *)tp->fw->data;
6338
6339 /* Firmware blob starts with version numbers, followed by
6340 start address and length. We are setting complete length.
6341 length = end_address_of_bss - start_address_of_text.
6342 Remainder is the blob to be loaded contiguously
6343 from start address. */
6344
6345 info.fw_base = be32_to_cpu(fw_data[1]);
6346 info.fw_len = tp->fw->size - 12;
6347 info.fw_data = &fw_data[3];
1da177e4
LT		 6348
6349 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6350 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6351 &info);
6352 if (err)
6353 return err;
6354
6355 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6356 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6357 &info);
6358 if (err)
6359 return err;
6360
6361 /* Now startup only the RX cpu. */
6362 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6363 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6364
6365 for (i = 0; i < 5; i++) {
077f849d 6366 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6367 break;
6368 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6369 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6370 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6371 udelay(1000);
6372 }
6373 if (i >= 5) {
6374 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6375 "to set RX CPU PC, is %08x should be %08x\n",
6376 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6377 info.fw_base);
1da177e4
LT		 6378 return -ENODEV;
6379 }
6380 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6381 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6382
6383 return 0;
6384}
6385
1da177e4 6386/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6387
6388/* tp->lock is held. */
6389static int tg3_load_tso_firmware(struct tg3 *tp)
6390{
6391 struct fw_info info;
077f849d 6392 const __be32 *fw_data;
1da177e4
LT		 6393 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6394 int err, i;
6395
6396 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6397 return 0;
6398
077f849d
JSR		 6399 fw_data = (void *)tp->fw->data;
6400
6401 /* Firmware blob starts with version numbers, followed by
6402 start address and length. We are setting complete length.
6403 length = end_address_of_bss - start_address_of_text.
6404 Remainder is the blob to be loaded contiguously
6405 from start address. */
6406
6407 info.fw_base = be32_to_cpu(fw_data[1]);
6408 cpu_scratch_size = tp->fw_len;
6409 info.fw_len = tp->fw->size - 12;
6410 info.fw_data = &fw_data[3];
6411
1da177e4 6412 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6413 cpu_base = RX_CPU_BASE;
6414 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6415 } else {
1da177e4
LT		 6416 cpu_base = TX_CPU_BASE;
6417 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6418 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6419 }
6420
6421 err = tg3_load_firmware_cpu(tp, cpu_base,
6422 cpu_scratch_base, cpu_scratch_size,
6423 &info);
6424 if (err)
6425 return err;
6426
6427 /* Now startup the cpu. */
6428 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6429 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6430
6431 for (i = 0; i < 5; i++) {
077f849d 6432 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6433 break;
6434 tw32(cpu_base + CPU_STATE, 0xffffffff);
6435 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6436 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6437 udelay(1000);
6438 }
6439 if (i >= 5) {
6440 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6441 "to set CPU PC, is %08x should be %08x\n",
6442 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6443 info.fw_base);
1da177e4
LT		 6444 return -ENODEV;
6445 }
6446 tw32(cpu_base + CPU_STATE, 0xffffffff);
6447 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6448 return 0;
6449}
6450
1da177e4 6451
1da177e4
LT		 6452static int tg3_set_mac_addr(struct net_device *dev, void *p)
6453{
6454 struct tg3 *tp = netdev_priv(dev);
6455 struct sockaddr *addr = p;
986e0aeb 6456 int err = 0, skip_mac_1 = 0;
1da177e4 6457
f9804ddb
MC		 6458 if (!is_valid_ether_addr(addr->sa_data))
6459 return -EINVAL;
6460
1da177e4
LT		 6461 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6462
e75f7c90
MC		 6463 if (!netif_running(dev))
6464 return 0;
6465
58712ef9 6466 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6467 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6468
986e0aeb
MC		 6469 addr0_high = tr32(MAC_ADDR_0_HIGH);
6470 addr0_low = tr32(MAC_ADDR_0_LOW);
6471 addr1_high = tr32(MAC_ADDR_1_HIGH);
6472 addr1_low = tr32(MAC_ADDR_1_LOW);
6473
6474 /* Skip MAC addr 1 if ASF is using it. */
6475 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6476 !(addr1_high == 0 && addr1_low == 0))
6477 skip_mac_1 = 1;
58712ef9 6478 }
986e0aeb
MC		 6479 spin_lock_bh(&tp->lock);
6480 __tg3_set_mac_addr(tp, skip_mac_1);
6481 spin_unlock_bh(&tp->lock);
1da177e4 6482
b9ec6c1b 6483 return err;
1da177e4
LT		 6484}
6485
6486/* tp->lock is held. */
6487static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6488 dma_addr_t mapping, u32 maxlen_flags,
6489 u32 nic_addr)
6490{
6491 tg3_write_mem(tp,
6492 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6493 ((u64) mapping >> 32));
6494 tg3_write_mem(tp,
6495 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6496 ((u64) mapping & 0xffffffff));
6497 tg3_write_mem(tp,
6498 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6499 maxlen_flags);
6500
6501 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6502 tg3_write_mem(tp,
6503 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6504 nic_addr);
6505}
6506
6507static void __tg3_set_rx_mode(struct net_device *);
d244c892 6508static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6509{
6510 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6511 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6512 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6513 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6514 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6515 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6516 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6517 }
6518 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6519 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6520 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6521 u32 val = ec->stats_block_coalesce_usecs;
6522
6523 if (!netif_carrier_ok(tp->dev))
6524 val = 0;
6525
6526 tw32(HOSTCC_STAT_COAL_TICKS, val);
6527 }
6528}
1da177e4
LT		 6529
6530/* tp->lock is held. */
8e7a22e3 6531static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6532{
6533 u32 val, rdmac_mode;
6534 int i, err, limit;
6535
6536 tg3_disable_ints(tp);
6537
6538 tg3_stop_fw(tp);
6539
6540 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6541
6542 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6543 tg3_abort_hw(tp, 1);
1da177e4
LT		 6544 }
6545
dd477003
MC		 6546 if (reset_phy &&
6547 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6548 tg3_phy_reset(tp);
6549
1da177e4
LT		 6550 err = tg3_chip_reset(tp);
6551 if (err)
6552 return err;
6553
6554 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6555
bcb37f6c 6556 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6557 val = tr32(TG3_CPMU_CTRL);
6558 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6559 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6560
6561 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6562 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6563 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6564 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6565
6566 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6567 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6568 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6569 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6570
6571 val = tr32(TG3_CPMU_HST_ACC);
6572 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6573 val |= CPMU_HST_ACC_MACCLK_6_25;
6574 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6575 }
6576
1da177e4
LT		 6577 /* This works around an issue with Athlon chipsets on
6578 * B3 tigon3 silicon. This bit has no effect on any
6579 * other revision. But do not set this on PCI Express
795d01c5 6580 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6581 */
795d01c5
MC		 6582 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6583 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6584 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6585 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6586 }
1da177e4
LT		 6587
6588 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6589 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6590 val = tr32(TG3PCI_PCISTATE);
6591 val |= PCISTATE_RETRY_SAME_DMA;
6592 tw32(TG3PCI_PCISTATE, val);
6593 }
6594
0d3031d9
MC		 6595 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6596 /* Allow reads and writes to the
6597 * APE register and memory space.
6598 */
6599 val = tr32(TG3PCI_PCISTATE);
6600 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6601 PCISTATE_ALLOW_APE_SHMEM_WR;
6602 tw32(TG3PCI_PCISTATE, val);
6603 }
6604
1da177e4
LT		 6605 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6606 /* Enable some hw fixes. */
6607 val = tr32(TG3PCI_MSI_DATA);
6608 val |= (1 << 26) | (1 << 28) | (1 << 29);
6609 tw32(TG3PCI_MSI_DATA, val);
6610 }
6611
6612 /* Descriptor ring init may make accesses to the
6613 * NIC SRAM area to setup the TX descriptors, so we
6614 * can only do this after the hardware has been
6615 * successfully reset.
6616 */
32d8c572
MC		 6617 err = tg3_init_rings(tp);
6618 if (err)
6619 return err;
1da177e4 6620
9936bcf6 6621 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6622 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6623 /* This value is determined during the probe time DMA
6624 * engine test, tg3_test_dma.
6625 */
6626 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6627 }
1da177e4
LT		 6628
6629 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6630 GRC_MODE_4X_NIC_SEND_RINGS |
6631 GRC_MODE_NO_TX_PHDR_CSUM |
6632 GRC_MODE_NO_RX_PHDR_CSUM);
6633 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6634
6635 /* Pseudo-header checksum is done by hardware logic and not
6636 * the offload processers, so make the chip do the pseudo-
6637 * header checksums on receive. For transmit it is more
6638 * convenient to do the pseudo-header checksum in software
6639 * as Linux does that on transmit for us in all cases.
6640 */
6641 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6642
6643 tw32(GRC_MODE,
6644 tp->grc_mode |
6645 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6646
6647 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6648 val = tr32(GRC_MISC_CFG);
6649 val &= ~0xff;
6650 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6651 tw32(GRC_MISC_CFG, val);
6652
6653 /* Initialize MBUF/DESC pool. */
cbf46853 6654 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6655 /* Do nothing. */
6656 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6657 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6659 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6660 else
6661 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6662 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6663 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6664 }
1da177e4
LT		 6665 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6666 int fw_len;
6667
077f849d 6668 fw_len = tp->fw_len;
1da177e4
LT		 6669 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6670 tw32(BUFMGR_MB_POOL_ADDR,
6671 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6672 tw32(BUFMGR_MB_POOL_SIZE,
6673 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6674 }
1da177e4 6675
0f893dc6 6676 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6677 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6678 tp->bufmgr_config.mbuf_read_dma_low_water);
6679 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6680 tp->bufmgr_config.mbuf_mac_rx_low_water);
6681 tw32(BUFMGR_MB_HIGH_WATER,
6682 tp->bufmgr_config.mbuf_high_water);
6683 } else {
6684 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6685 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6686 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6687 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6688 tw32(BUFMGR_MB_HIGH_WATER,
6689 tp->bufmgr_config.mbuf_high_water_jumbo);
6690 }
6691 tw32(BUFMGR_DMA_LOW_WATER,
6692 tp->bufmgr_config.dma_low_water);
6693 tw32(BUFMGR_DMA_HIGH_WATER,
6694 tp->bufmgr_config.dma_high_water);
6695
6696 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6697 for (i = 0; i < 2000; i++) {
6698 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6699 break;
6700 udelay(10);
6701 }
6702 if (i >= 2000) {
6703 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6704 tp->dev->name);
6705 return -ENODEV;
6706 }
6707
6708 /* Setup replenish threshold. */
f92905de
MC		 6709 val = tp->rx_pending / 8;
6710 if (val == 0)
6711 val = 1;
6712 else if (val > tp->rx_std_max_post)
6713 val = tp->rx_std_max_post;
b5d3772c
MC		 6714 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6715 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6716 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6717
6718 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6719 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6720 }
f92905de
MC		 6721
6722 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6723
6724 /* Initialize TG3_BDINFO's at:
6725 * RCVDBDI_STD_BD: standard eth size rx ring
6726 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6727 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6728 *
6729 * like so:
6730 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6731 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6732 * ring attribute flags
6733 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6734 *
6735 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6736 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6737 *
6738 * The size of each ring is fixed in the firmware, but the location is
6739 * configurable.
6740 */
6741 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6742 ((u64) tp->rx_std_mapping >> 32));
6743 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6744 ((u64) tp->rx_std_mapping & 0xffffffff));
6745 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6746 NIC_SRAM_RX_BUFFER_DESC);
6747
6748 /* Don't even try to program the JUMBO/MINI buffer descriptor
6749 * configs on 5705.
6750 */
6751 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6752 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6753 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6754 } else {
6755 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6756 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6757
6758 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6759 BDINFO_FLAGS_DISABLED);
6760
6761 /* Setup replenish threshold. */
6762 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6763
0f893dc6 6764 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6765 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6766 ((u64) tp->rx_jumbo_mapping >> 32));
6767 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6768 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6769 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6770 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6771 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6772 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6773 } else {
6774 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6775 BDINFO_FLAGS_DISABLED);
6776 }
6777
6778 }
6779
6780 /* There is only one send ring on 5705/5750, no need to explicitly
6781 * disable the others.
6782 */
6783 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6784 /* Clear out send RCB ring in SRAM. */
6785 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6786 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6787 BDINFO_FLAGS_DISABLED);
6788 }
6789
6790 tp->tx_prod = 0;
6791 tp->tx_cons = 0;
6792 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6793 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6794
6795 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6796 tp->tx_desc_mapping,
6797 (TG3_TX_RING_SIZE <<
6798 BDINFO_FLAGS_MAXLEN_SHIFT),
6799 NIC_SRAM_TX_BUFFER_DESC);
6800
6801 /* There is only one receive return ring on 5705/5750, no need
6802 * to explicitly disable the others.
6803 */
6804 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6805 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6806 i += TG3_BDINFO_SIZE) {
6807 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6808 BDINFO_FLAGS_DISABLED);
6809 }
6810 }
6811
6812 tp->rx_rcb_ptr = 0;
6813 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6814
6815 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6816 tp->rx_rcb_mapping,
6817 (TG3_RX_RCB_RING_SIZE(tp) <<
6818 BDINFO_FLAGS_MAXLEN_SHIFT),
6819 0);
6820
6821 tp->rx_std_ptr = tp->rx_pending;
6822 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6823 tp->rx_std_ptr);
6824
0f893dc6 6825 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6826 tp->rx_jumbo_pending : 0;
6827 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6828 tp->rx_jumbo_ptr);
6829
6830 /* Initialize MAC address and backoff seed. */
986e0aeb 6831 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6832
6833 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 6834 tw32(MAC_RX_MTU_SIZE,
6835 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 6836
6837 /* The slot time is changed by tg3_setup_phy if we
6838 * run at gigabit with half duplex.
6839 */
6840 tw32(MAC_TX_LENGTHS,
6841 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6842 (6 << TX_LENGTHS_IPG_SHIFT) |
6843 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6844
6845 /* Receive rules. */
6846 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6847 tw32(RCVLPC_CONFIG, 0x0181);
6848
6849 /* Calculate RDMAC_MODE setting early, we need it to determine
6850 * the RCVLPC_STATE_ENABLE mask.
6851 */
6852 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6853 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6854 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6855 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6856 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 6857
57e6983c 6858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 6859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6860 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 6861 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6862 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6863 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6864
85e94ced
MC		 6865 /* If statement applies to 5705 and 5750 PCI devices only */
6866 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6867 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6868 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 6869 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 6870 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6871 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6872 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6873 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6874 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6875 }
6876 }
6877
85e94ced
MC		 6878 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6879 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6880
1da177e4 6881 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 6882 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
6883
6884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
6886 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 6887
6888 /* Receive/send statistics. */
1661394e
MC		 6889 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6890 val = tr32(RCVLPC_STATS_ENABLE);
6891 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6892 tw32(RCVLPC_STATS_ENABLE, val);
6893 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6894 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 6895 val = tr32(RCVLPC_STATS_ENABLE);
6896 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6897 tw32(RCVLPC_STATS_ENABLE, val);
6898 } else {
6899 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6900 }
6901 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6902 tw32(SNDDATAI_STATSENAB, 0xffffff);
6903 tw32(SNDDATAI_STATSCTRL,
6904 (SNDDATAI_SCTRL_ENABLE |
6905 SNDDATAI_SCTRL_FASTUPD));
6906
6907 /* Setup host coalescing engine. */
6908 tw32(HOSTCC_MODE, 0);
6909 for (i = 0; i < 2000; i++) {
6910 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6911 break;
6912 udelay(10);
6913 }
6914
d244c892 6915 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 6916
6917 /* set status block DMA address */
6918 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6919 ((u64) tp->status_mapping >> 32));
6920 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6921 ((u64) tp->status_mapping & 0xffffffff));
6922
6923 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6924 /* Status/statistics block address. See tg3_timer,
6925 * the tg3_periodic_fetch_stats call there, and
6926 * tg3_get_stats to see how this works for 5705/5750 chips.
6927 */
1da177e4
LT		 6928 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6929 ((u64) tp->stats_mapping >> 32));
6930 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6931 ((u64) tp->stats_mapping & 0xffffffff));
6932 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6933 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6934 }
6935
6936 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6937
6938 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6939 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6940 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6941 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6942
6943 /* Clear statistics/status block in chip, and status block in ram. */
6944 for (i = NIC_SRAM_STATS_BLK;
6945 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6946 i += sizeof(u32)) {
6947 tg3_write_mem(tp, i, 0);
6948 udelay(40);
6949 }
6950 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6951
c94e3941
MC		 6952 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6953 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6954 /* reset to prevent losing 1st rx packet intermittently */
6955 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6956 udelay(10);
6957 }
6958
3bda1258
MC		 6959 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6960 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
6961 else
6962 tp->mac_mode = 0;
6963 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 6964 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 6965 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6966 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6967 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6968 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 6969 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6970 udelay(40);
6971
314fba34 6972 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 6973 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 6974 * register to preserve the GPIO settings for LOMs. The GPIOs,
6975 * whether used as inputs or outputs, are set by boot code after
6976 * reset.
6977 */
9d26e213 6978 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 6979 u32 gpio_mask;
6980
9d26e213
MC		 6981 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6982 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6983 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 6984
6985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6986 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6987 GRC_LCLCTRL_GPIO_OUTPUT3;
6988
af36e6b6
MC		 6989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6990 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6991
aaf84465 6992 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 6993 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6994
6995 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 6996 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6997 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6998 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 6999 }
1da177e4
LT		 7000 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7001 udelay(100);
7002
09ee929c 7003 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 7004 tp->last_tag = 0;
1da177e4
LT		 7005
7006 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7007 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7008 udelay(40);
7009 }
7010
7011 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7012 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7013 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7014 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7015 WDMAC_MODE_LNGREAD_ENAB);
7016
85e94ced
MC		 7017 /* If statement applies to 5705 and 5750 PCI devices only */
7018 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7019 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7020 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7021 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7022 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7023 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7024 /* nothing */
7025 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7026 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7027 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7028 val |= WDMAC_MODE_RX_ACCEL;
7029 }
7030 }
7031
d9ab5ad1 7032 /* Enable host coalescing bug fix */
321d32a0 7033 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7034 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7035
1da177e4
LT		 7036 tw32_f(WDMAC_MODE, val);
7037 udelay(40);
7038
9974a356
MC		 7039 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7040 u16 pcix_cmd;
7041
7042 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7043 &pcix_cmd);
1da177e4 7044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7045 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7046 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7047 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7048 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7049 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7050 }
9974a356
MC		 7051 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7052 pcix_cmd);
1da177e4
LT		 7053 }
7054
7055 tw32_f(RDMAC_MODE, rdmac_mode);
7056 udelay(40);
7057
7058 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7059 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7060 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7061
7062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7063 tw32(SNDDATAC_MODE,
7064 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7065 else
7066 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7067
1da177e4
LT		 7068 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7069 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7070 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7071 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7072 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7073 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7074 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7075 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7076
7077 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7078 err = tg3_load_5701_a0_firmware_fix(tp);
7079 if (err)
7080 return err;
7081 }
7082
1da177e4
LT		 7083 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7084 err = tg3_load_tso_firmware(tp);
7085 if (err)
7086 return err;
7087 }
1da177e4
LT		 7088
7089 tp->tx_mode = TX_MODE_ENABLE;
7090 tw32_f(MAC_TX_MODE, tp->tx_mode);
7091 udelay(100);
7092
7093 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7094 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7095 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7096
1da177e4
LT		 7097 tw32_f(MAC_RX_MODE, tp->rx_mode);
7098 udelay(10);
7099
1da177e4
LT		 7100 tw32(MAC_LED_CTRL, tp->led_ctrl);
7101
7102 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7103 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7104 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7105 udelay(10);
7106 }
7107 tw32_f(MAC_RX_MODE, tp->rx_mode);
7108 udelay(10);
7109
7110 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7111 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7112 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7113 /* Set drive transmission level to 1.2V */
7114 /* only if the signal pre-emphasis bit is not set */
7115 val = tr32(MAC_SERDES_CFG);
7116 val &= 0xfffff000;
7117 val |= 0x880;
7118 tw32(MAC_SERDES_CFG, val);
7119 }
7120 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7121 tw32(MAC_SERDES_CFG, 0x616000);
7122 }
7123
7124 /* Prevent chip from dropping frames when flow control
7125 * is enabled.
7126 */
7127 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7128
7129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7130 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7131 /* Use hardware link auto-negotiation */
7132 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7133 }
7134
d4d2c558
MC		 7135 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7137 u32 tmp;
7138
7139 tmp = tr32(SERDES_RX_CTRL);
7140 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7141 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7142 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7143 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7144 }
7145
dd477003
MC		 7146 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7147 if (tp->link_config.phy_is_low_power) {
7148 tp->link_config.phy_is_low_power = 0;
7149 tp->link_config.speed = tp->link_config.orig_speed;
7150 tp->link_config.duplex = tp->link_config.orig_duplex;
7151 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7152 }
1da177e4 7153
dd477003
MC		 7154 err = tg3_setup_phy(tp, 0);
7155 if (err)
7156 return err;
1da177e4 7157
dd477003
MC		 7158 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7159 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7160 u32 tmp;
7161
7162 /* Clear CRC stats. */
7163 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7164 tg3_writephy(tp, MII_TG3_TEST1,
7165 tmp | MII_TG3_TEST1_CRC_EN);
7166 tg3_readphy(tp, 0x14, &tmp);
7167 }
1da177e4
LT		 7168 }
7169 }
7170
7171 __tg3_set_rx_mode(tp->dev);
7172
7173 /* Initialize receive rules. */
7174 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7175 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7176 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7177 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7178
4cf78e4f 7179 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7180 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7181 limit = 8;
7182 else
7183 limit = 16;
7184 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7185 limit -= 4;
7186 switch (limit) {
7187 case 16:
7188 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7189 case 15:
7190 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7191 case 14:
7192 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7193 case 13:
7194 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7195 case 12:
7196 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7197 case 11:
7198 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7199 case 10:
7200 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7201 case 9:
7202 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7203 case 8:
7204 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7205 case 7:
7206 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7207 case 6:
7208 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7209 case 5:
7210 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7211 case 4:
7212 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7213 case 3:
7214 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7215 case 2:
7216 case 1:
7217
7218 default:
7219 break;
855e1111 7220 }
1da177e4 7221
9ce768ea
MC		 7222 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7223 /* Write our heartbeat update interval to APE. */
7224 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7225 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7226
1da177e4
LT		 7227 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7228
1da177e4
LT		 7229 return 0;
7230}
7231
7232/* Called at device open time to get the chip ready for
7233 * packet processing. Invoked with tp->lock held.
7234 */
8e7a22e3 7235static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7236{
1da177e4
LT		 7237 tg3_switch_clocks(tp);
7238
7239 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7240
2f751b67 7241 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7242}
7243
7244#define TG3_STAT_ADD32(PSTAT, REG) \
7245do { u32 __val = tr32(REG); \
7246 (PSTAT)->low += __val; \
7247 if ((PSTAT)->low < __val) \
7248 (PSTAT)->high += 1; \
7249} while (0)
7250
7251static void tg3_periodic_fetch_stats(struct tg3 *tp)
7252{
7253 struct tg3_hw_stats *sp = tp->hw_stats;
7254
7255 if (!netif_carrier_ok(tp->dev))
7256 return;
7257
7258 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7259 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7260 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7261 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7262 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7263 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7264 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7265 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7266 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7267 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7268 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7269 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7270 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7271
7272 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7273 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7274 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7275 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7276 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7277 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7278 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7279 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7280 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7281 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7282 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7283 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7284 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7285 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7286
7287 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7288 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7289 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7290}
7291
7292static void tg3_timer(unsigned long __opaque)
7293{
7294 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7295
f475f163
MC		 7296 if (tp->irq_sync)
7297 goto restart_timer;
7298
f47c11ee 7299 spin_lock(&tp->lock);
1da177e4 7300
fac9b83e
DM		 7301 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7302 /* All of this garbage is because when using non-tagged
7303 * IRQ status the mailbox/status_block protocol the chip
7304 * uses with the cpu is race prone.
7305 */
7306 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7307 tw32(GRC_LOCAL_CTRL,
7308 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7309 } else {
7310 tw32(HOSTCC_MODE, tp->coalesce_mode |
7311 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7312 }
1da177e4 7313
fac9b83e
DM		 7314 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7315 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7316 spin_unlock(&tp->lock);
fac9b83e
DM		 7317 schedule_work(&tp->reset_task);
7318 return;
7319 }
1da177e4
LT		 7320 }
7321
1da177e4
LT		 7322 /* This part only runs once per second. */
7323 if (!--tp->timer_counter) {
fac9b83e
DM		 7324 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7325 tg3_periodic_fetch_stats(tp);
7326
1da177e4
LT		 7327 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7328 u32 mac_stat;
7329 int phy_event;
7330
7331 mac_stat = tr32(MAC_STATUS);
7332
7333 phy_event = 0;
7334 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7335 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7336 phy_event = 1;
7337 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7338 phy_event = 1;
7339
7340 if (phy_event)
7341 tg3_setup_phy(tp, 0);
7342 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7343 u32 mac_stat = tr32(MAC_STATUS);
7344 int need_setup = 0;
7345
7346 if (netif_carrier_ok(tp->dev) &&
7347 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7348 need_setup = 1;
7349 }
7350 if (! netif_carrier_ok(tp->dev) &&
7351 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7352 MAC_STATUS_SIGNAL_DET))) {
7353 need_setup = 1;
7354 }
7355 if (need_setup) {
3d3ebe74
MC		 7356 if (!tp->serdes_counter) {
7357 tw32_f(MAC_MODE,
7358 (tp->mac_mode &
7359 ~MAC_MODE_PORT_MODE_MASK));
7360 udelay(40);
7361 tw32_f(MAC_MODE, tp->mac_mode);
7362 udelay(40);
7363 }
1da177e4
LT		 7364 tg3_setup_phy(tp, 0);
7365 }
747e8f8b
MC		 7366 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7367 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7368
7369 tp->timer_counter = tp->timer_multiplier;
7370 }
7371
130b8e4d
MC		 7372 /* Heartbeat is only sent once every 2 seconds.
7373 *
7374 * The heartbeat is to tell the ASF firmware that the host
7375 * driver is still alive. In the event that the OS crashes,
7376 * ASF needs to reset the hardware to free up the FIFO space
7377 * that may be filled with rx packets destined for the host.
7378 * If the FIFO is full, ASF will no longer function properly.
7379 *
7380 * Unintended resets have been reported on real time kernels
7381 * where the timer doesn't run on time. Netpoll will also have
7382 * same problem.
7383 *
7384 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7385 * to check the ring condition when the heartbeat is expiring
7386 * before doing the reset. This will prevent most unintended
7387 * resets.
7388 */
1da177e4 7389 if (!--tp->asf_counter) {
bc7959b2
MC		 7390 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7391 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7392 tg3_wait_for_event_ack(tp);
7393
bbadf503 7394 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7395 FWCMD_NICDRV_ALIVE3);
bbadf503 7396 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7397 /* 5 seconds timeout */
bbadf503 7398 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7399
7400 tg3_generate_fw_event(tp);
1da177e4
LT		 7401 }
7402 tp->asf_counter = tp->asf_multiplier;
7403 }
7404
f47c11ee 7405 spin_unlock(&tp->lock);
1da177e4 7406
f475f163 7407restart_timer:
1da177e4
LT		 7408 tp->timer.expires = jiffies + tp->timer_offset;
7409 add_timer(&tp->timer);
7410}
7411
81789ef5 7412static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7413{
7d12e780 7414 irq_handler_t fn;
fcfa0a32
MC		 7415 unsigned long flags;
7416 struct net_device *dev = tp->dev;
7417
7418 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7419 fn = tg3_msi;
7420 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7421 fn = tg3_msi_1shot;
1fb9df5d 7422 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7423 } else {
7424 fn = tg3_interrupt;
7425 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7426 fn = tg3_interrupt_tagged;
1fb9df5d 7427 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7428 }
7429 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7430}
7431
7938109f
MC		 7432static int tg3_test_interrupt(struct tg3 *tp)
7433{
7434 struct net_device *dev = tp->dev;
b16250e3 7435 int err, i, intr_ok = 0;
7938109f 7436
d4bc3927
MC		 7437 if (!netif_running(dev))
7438 return -ENODEV;
7439
7938109f
MC		 7440 tg3_disable_ints(tp);
7441
7442 free_irq(tp->pdev->irq, dev);
7443
7444 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7445 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7446 if (err)
7447 return err;
7448
38f3843e 7449 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7450 tg3_enable_ints(tp);
7451
7452 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7453 HOSTCC_MODE_NOW);
7454
7455 for (i = 0; i < 5; i++) {
b16250e3
MC		 7456 u32 int_mbox, misc_host_ctrl;
7457
09ee929c
MC		 7458 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7459 TG3_64BIT_REG_LOW);
b16250e3
MC		 7460 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7461
7462 if ((int_mbox != 0) ||
7463 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7464 intr_ok = 1;
7938109f 7465 break;
b16250e3
MC		 7466 }
7467
7938109f
MC		 7468 msleep(10);
7469 }
7470
7471 tg3_disable_ints(tp);
7472
7473 free_irq(tp->pdev->irq, dev);
6aa20a22 7474
fcfa0a32 7475 err = tg3_request_irq(tp);
7938109f
MC		 7476
7477 if (err)
7478 return err;
7479
b16250e3 7480 if (intr_ok)
7938109f
MC		 7481 return 0;
7482
7483 return -EIO;
7484}
7485
7486/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7487 * successfully restored
7488 */
7489static int tg3_test_msi(struct tg3 *tp)
7490{
7491 struct net_device *dev = tp->dev;
7492 int err;
7493 u16 pci_cmd;
7494
7495 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7496 return 0;
7497
7498 /* Turn off SERR reporting in case MSI terminates with Master
7499 * Abort.
7500 */
7501 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7502 pci_write_config_word(tp->pdev, PCI_COMMAND,
7503 pci_cmd & ~PCI_COMMAND_SERR);
7504
7505 err = tg3_test_interrupt(tp);
7506
7507 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7508
7509 if (!err)
7510 return 0;
7511
7512 /* other failures */
7513 if (err != -EIO)
7514 return err;
7515
7516 /* MSI test failed, go back to INTx mode */
7517 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7518 "switching to INTx mode. Please report this failure to "
7519 "the PCI maintainer and include system chipset information.\n",
7520 tp->dev->name);
7521
7522 free_irq(tp->pdev->irq, dev);
7523 pci_disable_msi(tp->pdev);
7524
7525 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7526
fcfa0a32 7527 err = tg3_request_irq(tp);
7938109f
MC		 7528 if (err)
7529 return err;
7530
7531 /* Need to reset the chip because the MSI cycle may have terminated
7532 * with Master Abort.
7533 */
f47c11ee 7534 tg3_full_lock(tp, 1);
7938109f 7535
944d980e 7536 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7537 err = tg3_init_hw(tp, 1);
7938109f 7538
f47c11ee 7539 tg3_full_unlock(tp);
7938109f
MC		 7540
7541 if (err)
7542 free_irq(tp->pdev->irq, dev);
7543
7544 return err;
7545}
7546
9e9fd12d
MC		 7547static int tg3_request_firmware(struct tg3 *tp)
7548{
7549 const __be32 *fw_data;
7550
7551 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7552 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7553 tp->dev->name, tp->fw_needed);
7554 return -ENOENT;
7555 }
7556
7557 fw_data = (void *)tp->fw->data;
7558
7559 /* Firmware blob starts with version numbers, followed by
7560 * start address and _full_ length including BSS sections
7561 * (which must be longer than the actual data, of course
7562 */
7563
7564 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7565 if (tp->fw_len < (tp->fw->size - 12)) {
7566 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7567 tp->dev->name, tp->fw_len, tp->fw_needed);
7568 release_firmware(tp->fw);
7569 tp->fw = NULL;
7570 return -EINVAL;
7571 }
7572
7573 /* We no longer need firmware; we have it. */
7574 tp->fw_needed = NULL;
7575 return 0;
7576}
7577
1da177e4
LT		 7578static int tg3_open(struct net_device *dev)
7579{
7580 struct tg3 *tp = netdev_priv(dev);
7581 int err;
7582
9e9fd12d
MC		 7583 if (tp->fw_needed) {
7584 err = tg3_request_firmware(tp);
7585 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7586 if (err)
7587 return err;
7588 } else if (err) {
7589 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7590 tp->dev->name);
7591 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7592 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7593 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7594 tp->dev->name);
7595 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7596 }
7597 }
7598
c49a1561
MC		 7599 netif_carrier_off(tp->dev);
7600
bc1c7567 7601 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7602 if (err)
bc1c7567 7603 return err;
2f751b67
MC		 7604
7605 tg3_full_lock(tp, 0);
bc1c7567 7606
1da177e4
LT		 7607 tg3_disable_ints(tp);
7608 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7609
f47c11ee 7610 tg3_full_unlock(tp);
1da177e4
LT		 7611
7612 /* The placement of this call is tied
7613 * to the setup and use of Host TX descriptors.
7614 */
7615 err = tg3_alloc_consistent(tp);
7616 if (err)
7617 return err;
7618
7544b097 7619 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7620 /* All MSI supporting chips should support tagged
7621 * status. Assert that this is the case.
7622 */
7623 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7624 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7625 "Not using MSI.\n", tp->dev->name);
7626 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7627 u32 msi_mode;
7628
7629 msi_mode = tr32(MSGINT_MODE);
7630 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7631 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7632 }
7633 }
fcfa0a32 7634 err = tg3_request_irq(tp);
1da177e4
LT		 7635
7636 if (err) {
88b06bc2
MC		 7637 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7638 pci_disable_msi(tp->pdev);
7639 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7640 }
1da177e4
LT		 7641 tg3_free_consistent(tp);
7642 return err;
7643 }
7644
bea3348e
SH		 7645 napi_enable(&tp->napi);
7646
f47c11ee 7647 tg3_full_lock(tp, 0);
1da177e4 7648
8e7a22e3 7649 err = tg3_init_hw(tp, 1);
1da177e4 7650 if (err) {
944d980e 7651 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7652 tg3_free_rings(tp);
7653 } else {
fac9b83e
DM		 7654 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7655 tp->timer_offset = HZ;
7656 else
7657 tp->timer_offset = HZ / 10;
7658
7659 BUG_ON(tp->timer_offset > HZ);
7660 tp->timer_counter = tp->timer_multiplier =
7661 (HZ / tp->timer_offset);
7662 tp->asf_counter = tp->asf_multiplier =
28fbef78 7663 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7664
7665 init_timer(&tp->timer);
7666 tp->timer.expires = jiffies + tp->timer_offset;
7667 tp->timer.data = (unsigned long) tp;
7668 tp->timer.function = tg3_timer;
1da177e4
LT		 7669 }
7670
f47c11ee 7671 tg3_full_unlock(tp);
1da177e4
LT		 7672
7673 if (err) {
bea3348e 7674 napi_disable(&tp->napi);
88b06bc2
MC		 7675 free_irq(tp->pdev->irq, dev);
7676 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7677 pci_disable_msi(tp->pdev);
7678 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7679 }
1da177e4
LT		 7680 tg3_free_consistent(tp);
7681 return err;
7682 }
7683
7938109f
MC		 7684 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7685 err = tg3_test_msi(tp);
fac9b83e 7686
7938109f 7687 if (err) {
f47c11ee 7688 tg3_full_lock(tp, 0);
7938109f
MC		 7689
7690 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7691 pci_disable_msi(tp->pdev);
7692 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7693 }
944d980e 7694 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7695 tg3_free_rings(tp);
7696 tg3_free_consistent(tp);
7697
f47c11ee 7698 tg3_full_unlock(tp);
7938109f 7699
bea3348e
SH		 7700 napi_disable(&tp->napi);
7701
7938109f
MC		 7702 return err;
7703 }
fcfa0a32
MC		 7704
7705 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7706 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7707 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7708
b5d3772c
MC		 7709 tw32(PCIE_TRANSACTION_CFG,
7710 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7711 }
7712 }
7938109f
MC		 7713 }
7714
b02fd9e3
MC		 7715 tg3_phy_start(tp);
7716
f47c11ee 7717 tg3_full_lock(tp, 0);
1da177e4 7718
7938109f
MC		 7719 add_timer(&tp->timer);
7720 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7721 tg3_enable_ints(tp);
7722
f47c11ee 7723 tg3_full_unlock(tp);
1da177e4
LT		 7724
7725 netif_start_queue(dev);
7726
7727 return 0;
7728}
7729
7730#if 0
7731/*static*/ void tg3_dump_state(struct tg3 *tp)
7732{
7733 u32 val32, val32_2, val32_3, val32_4, val32_5;
7734 u16 val16;
7735 int i;
7736
7737 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7738 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7739 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7740 val16, val32);
7741
7742 /* MAC block */
7743 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7744 tr32(MAC_MODE), tr32(MAC_STATUS));
7745 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7746 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7747 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7748 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7749 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7750 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7751
7752 /* Send data initiator control block */
7753 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7754 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7755 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7756 tr32(SNDDATAI_STATSCTRL));
7757
7758 /* Send data completion control block */
7759 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7760
7761 /* Send BD ring selector block */
7762 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7763 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7764
7765 /* Send BD initiator control block */
7766 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7767 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7768
7769 /* Send BD completion control block */
7770 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7771
7772 /* Receive list placement control block */
7773 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7774 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7775 printk(" RCVLPC_STATSCTRL[%08x]\n",
7776 tr32(RCVLPC_STATSCTRL));
7777
7778 /* Receive data and receive BD initiator control block */
7779 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7780 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7781
7782 /* Receive data completion control block */
7783 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7784 tr32(RCVDCC_MODE));
7785
7786 /* Receive BD initiator control block */
7787 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7788 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7789
7790 /* Receive BD completion control block */
7791 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7792 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7793
7794 /* Receive list selector control block */
7795 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7796 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7797
7798 /* Mbuf cluster free block */
7799 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7800 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7801
7802 /* Host coalescing control block */
7803 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7804 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7805 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7806 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7807 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7808 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7809 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7810 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7811 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7812 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7813 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7814 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7815
7816 /* Memory arbiter control block */
7817 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7818 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7819
7820 /* Buffer manager control block */
7821 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7822 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7823 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7824 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7825 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7826 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7827 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7828 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7829
7830 /* Read DMA control block */
7831 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7832 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7833
7834 /* Write DMA control block */
7835 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7836 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7837
7838 /* DMA completion block */
7839 printk("DEBUG: DMAC_MODE[%08x]\n",
7840 tr32(DMAC_MODE));
7841
7842 /* GRC block */
7843 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7844 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7845 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7846 tr32(GRC_LOCAL_CTRL));
7847
7848 /* TG3_BDINFOs */
7849 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7850 tr32(RCVDBDI_JUMBO_BD + 0x0),
7851 tr32(RCVDBDI_JUMBO_BD + 0x4),
7852 tr32(RCVDBDI_JUMBO_BD + 0x8),
7853 tr32(RCVDBDI_JUMBO_BD + 0xc));
7854 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7855 tr32(RCVDBDI_STD_BD + 0x0),
7856 tr32(RCVDBDI_STD_BD + 0x4),
7857 tr32(RCVDBDI_STD_BD + 0x8),
7858 tr32(RCVDBDI_STD_BD + 0xc));
7859 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7860 tr32(RCVDBDI_MINI_BD + 0x0),
7861 tr32(RCVDBDI_MINI_BD + 0x4),
7862 tr32(RCVDBDI_MINI_BD + 0x8),
7863 tr32(RCVDBDI_MINI_BD + 0xc));
7864
7865 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7866 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7867 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7868 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7869 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7870 val32, val32_2, val32_3, val32_4);
7871
7872 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7873 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7874 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7875 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7876 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7877 val32, val32_2, val32_3, val32_4);
7878
7879 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7880 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7881 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7882 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7883 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7884 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7885 val32, val32_2, val32_3, val32_4, val32_5);
7886
7887 /* SW status block */
7888 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7889 tp->hw_status->status,
7890 tp->hw_status->status_tag,
7891 tp->hw_status->rx_jumbo_consumer,
7892 tp->hw_status->rx_consumer,
7893 tp->hw_status->rx_mini_consumer,
7894 tp->hw_status->idx[0].rx_producer,
7895 tp->hw_status->idx[0].tx_consumer);
7896
7897 /* SW statistics block */
7898 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7899 ((u32 *)tp->hw_stats)[0],
7900 ((u32 *)tp->hw_stats)[1],
7901 ((u32 *)tp->hw_stats)[2],
7902 ((u32 *)tp->hw_stats)[3]);
7903
7904 /* Mailboxes */
7905 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 7906 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7907 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7908 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7909 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 7910
7911 /* NIC side send descriptors. */
7912 for (i = 0; i < 6; i++) {
7913 unsigned long txd;
7914
7915 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7916 + (i * sizeof(struct tg3_tx_buffer_desc));
7917 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7918 i,
7919 readl(txd + 0x0), readl(txd + 0x4),
7920 readl(txd + 0x8), readl(txd + 0xc));
7921 }
7922
7923 /* NIC side RX descriptors. */
7924 for (i = 0; i < 6; i++) {
7925 unsigned long rxd;
7926
7927 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7928 + (i * sizeof(struct tg3_rx_buffer_desc));
7929 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7930 i,
7931 readl(rxd + 0x0), readl(rxd + 0x4),
7932 readl(rxd + 0x8), readl(rxd + 0xc));
7933 rxd += (4 * sizeof(u32));
7934 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7935 i,
7936 readl(rxd + 0x0), readl(rxd + 0x4),
7937 readl(rxd + 0x8), readl(rxd + 0xc));
7938 }
7939
7940 for (i = 0; i < 6; i++) {
7941 unsigned long rxd;
7942
7943 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7944 + (i * sizeof(struct tg3_rx_buffer_desc));
7945 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7946 i,
7947 readl(rxd + 0x0), readl(rxd + 0x4),
7948 readl(rxd + 0x8), readl(rxd + 0xc));
7949 rxd += (4 * sizeof(u32));
7950 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7951 i,
7952 readl(rxd + 0x0), readl(rxd + 0x4),
7953 readl(rxd + 0x8), readl(rxd + 0xc));
7954 }
7955}
7956#endif
7957
7958static struct net_device_stats *tg3_get_stats(struct net_device *);
7959static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7960
7961static int tg3_close(struct net_device *dev)
7962{
7963 struct tg3 *tp = netdev_priv(dev);
7964
bea3348e 7965 napi_disable(&tp->napi);
28e53bdd 7966 cancel_work_sync(&tp->reset_task);
7faa006f 7967
1da177e4
LT		 7968 netif_stop_queue(dev);
7969
7970 del_timer_sync(&tp->timer);
7971
f47c11ee 7972 tg3_full_lock(tp, 1);
1da177e4
LT		 7973#if 0
7974 tg3_dump_state(tp);
7975#endif
7976
7977 tg3_disable_ints(tp);
7978
944d980e 7979 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 7980 tg3_free_rings(tp);
5cf64b8a 7981 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 7982
f47c11ee 7983 tg3_full_unlock(tp);
1da177e4 7984
88b06bc2
MC		 7985 free_irq(tp->pdev->irq, dev);
7986 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7987 pci_disable_msi(tp->pdev);
7988 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7989 }
1da177e4
LT		 7990
7991 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7992 sizeof(tp->net_stats_prev));
7993 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7994 sizeof(tp->estats_prev));
7995
7996 tg3_free_consistent(tp);
7997
bc1c7567
MC		 7998 tg3_set_power_state(tp, PCI_D3hot);
7999
8000 netif_carrier_off(tp->dev);
8001
1da177e4
LT		 8002 return 0;
8003}
8004
8005static inline unsigned long get_stat64(tg3_stat64_t *val)
8006{
8007 unsigned long ret;
8008
8009#if (BITS_PER_LONG == 32)
8010 ret = val->low;
8011#else
8012 ret = ((u64)val->high << 32) | ((u64)val->low);
8013#endif
8014 return ret;
8015}
8016
816f8b86
SB		 8017static inline u64 get_estat64(tg3_stat64_t *val)
8018{
8019 return ((u64)val->high << 32) | ((u64)val->low);
8020}
8021
1da177e4
LT		 8022static unsigned long calc_crc_errors(struct tg3 *tp)
8023{
8024 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8025
8026 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8027 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8029 u32 val;
8030
f47c11ee 8031 spin_lock_bh(&tp->lock);
569a5df8
MC		 8032 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8033 tg3_writephy(tp, MII_TG3_TEST1,
8034 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8035 tg3_readphy(tp, 0x14, &val);
8036 } else
8037 val = 0;
f47c11ee 8038 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8039
8040 tp->phy_crc_errors += val;
8041
8042 return tp->phy_crc_errors;
8043 }
8044
8045 return get_stat64(&hw_stats->rx_fcs_errors);
8046}
8047
8048#define ESTAT_ADD(member) \
8049 estats->member = old_estats->member + \
816f8b86 8050 get_estat64(&hw_stats->member)
1da177e4
LT		 8051
8052static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8053{
8054 struct tg3_ethtool_stats *estats = &tp->estats;
8055 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8056 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8057
8058 if (!hw_stats)
8059 return old_estats;
8060
8061 ESTAT_ADD(rx_octets);
8062 ESTAT_ADD(rx_fragments);
8063 ESTAT_ADD(rx_ucast_packets);
8064 ESTAT_ADD(rx_mcast_packets);
8065 ESTAT_ADD(rx_bcast_packets);
8066 ESTAT_ADD(rx_fcs_errors);
8067 ESTAT_ADD(rx_align_errors);
8068 ESTAT_ADD(rx_xon_pause_rcvd);
8069 ESTAT_ADD(rx_xoff_pause_rcvd);
8070 ESTAT_ADD(rx_mac_ctrl_rcvd);
8071 ESTAT_ADD(rx_xoff_entered);
8072 ESTAT_ADD(rx_frame_too_long_errors);
8073 ESTAT_ADD(rx_jabbers);
8074 ESTAT_ADD(rx_undersize_packets);
8075 ESTAT_ADD(rx_in_length_errors);
8076 ESTAT_ADD(rx_out_length_errors);
8077 ESTAT_ADD(rx_64_or_less_octet_packets);
8078 ESTAT_ADD(rx_65_to_127_octet_packets);
8079 ESTAT_ADD(rx_128_to_255_octet_packets);
8080 ESTAT_ADD(rx_256_to_511_octet_packets);
8081 ESTAT_ADD(rx_512_to_1023_octet_packets);
8082 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8083 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8084 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8085 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8086 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8087
8088 ESTAT_ADD(tx_octets);
8089 ESTAT_ADD(tx_collisions);
8090 ESTAT_ADD(tx_xon_sent);
8091 ESTAT_ADD(tx_xoff_sent);
8092 ESTAT_ADD(tx_flow_control);
8093 ESTAT_ADD(tx_mac_errors);
8094 ESTAT_ADD(tx_single_collisions);
8095 ESTAT_ADD(tx_mult_collisions);
8096 ESTAT_ADD(tx_deferred);
8097 ESTAT_ADD(tx_excessive_collisions);
8098 ESTAT_ADD(tx_late_collisions);
8099 ESTAT_ADD(tx_collide_2times);
8100 ESTAT_ADD(tx_collide_3times);
8101 ESTAT_ADD(tx_collide_4times);
8102 ESTAT_ADD(tx_collide_5times);
8103 ESTAT_ADD(tx_collide_6times);
8104 ESTAT_ADD(tx_collide_7times);
8105 ESTAT_ADD(tx_collide_8times);
8106 ESTAT_ADD(tx_collide_9times);
8107 ESTAT_ADD(tx_collide_10times);
8108 ESTAT_ADD(tx_collide_11times);
8109 ESTAT_ADD(tx_collide_12times);
8110 ESTAT_ADD(tx_collide_13times);
8111 ESTAT_ADD(tx_collide_14times);
8112 ESTAT_ADD(tx_collide_15times);
8113 ESTAT_ADD(tx_ucast_packets);
8114 ESTAT_ADD(tx_mcast_packets);
8115 ESTAT_ADD(tx_bcast_packets);
8116 ESTAT_ADD(tx_carrier_sense_errors);
8117 ESTAT_ADD(tx_discards);
8118 ESTAT_ADD(tx_errors);
8119
8120 ESTAT_ADD(dma_writeq_full);
8121 ESTAT_ADD(dma_write_prioq_full);
8122 ESTAT_ADD(rxbds_empty);
8123 ESTAT_ADD(rx_discards);
8124 ESTAT_ADD(rx_errors);
8125 ESTAT_ADD(rx_threshold_hit);
8126
8127 ESTAT_ADD(dma_readq_full);
8128 ESTAT_ADD(dma_read_prioq_full);
8129 ESTAT_ADD(tx_comp_queue_full);
8130
8131 ESTAT_ADD(ring_set_send_prod_index);
8132 ESTAT_ADD(ring_status_update);
8133 ESTAT_ADD(nic_irqs);
8134 ESTAT_ADD(nic_avoided_irqs);
8135 ESTAT_ADD(nic_tx_threshold_hit);
8136
8137 return estats;
8138}
8139
8140static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8141{
8142 struct tg3 *tp = netdev_priv(dev);
8143 struct net_device_stats *stats = &tp->net_stats;
8144 struct net_device_stats *old_stats = &tp->net_stats_prev;
8145 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8146
8147 if (!hw_stats)
8148 return old_stats;
8149
8150 stats->rx_packets = old_stats->rx_packets +
8151 get_stat64(&hw_stats->rx_ucast_packets) +
8152 get_stat64(&hw_stats->rx_mcast_packets) +
8153 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8154
1da177e4
LT		 8155 stats->tx_packets = old_stats->tx_packets +
8156 get_stat64(&hw_stats->tx_ucast_packets) +
8157 get_stat64(&hw_stats->tx_mcast_packets) +
8158 get_stat64(&hw_stats->tx_bcast_packets);
8159
8160 stats->rx_bytes = old_stats->rx_bytes +
8161 get_stat64(&hw_stats->rx_octets);
8162 stats->tx_bytes = old_stats->tx_bytes +
8163 get_stat64(&hw_stats->tx_octets);
8164
8165 stats->rx_errors = old_stats->rx_errors +
4f63b877 8166 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8167 stats->tx_errors = old_stats->tx_errors +
8168 get_stat64(&hw_stats->tx_errors) +
8169 get_stat64(&hw_stats->tx_mac_errors) +
8170 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8171 get_stat64(&hw_stats->tx_discards);
8172
8173 stats->multicast = old_stats->multicast +
8174 get_stat64(&hw_stats->rx_mcast_packets);
8175 stats->collisions = old_stats->collisions +
8176 get_stat64(&hw_stats->tx_collisions);
8177
8178 stats->rx_length_errors = old_stats->rx_length_errors +
8179 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8180 get_stat64(&hw_stats->rx_undersize_packets);
8181
8182 stats->rx_over_errors = old_stats->rx_over_errors +
8183 get_stat64(&hw_stats->rxbds_empty);
8184 stats->rx_frame_errors = old_stats->rx_frame_errors +
8185 get_stat64(&hw_stats->rx_align_errors);
8186 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8187 get_stat64(&hw_stats->tx_discards);
8188 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8189 get_stat64(&hw_stats->tx_carrier_sense_errors);
8190
8191 stats->rx_crc_errors = old_stats->rx_crc_errors +
8192 calc_crc_errors(tp);
8193
4f63b877
JL		 8194 stats->rx_missed_errors = old_stats->rx_missed_errors +
8195 get_stat64(&hw_stats->rx_discards);
8196
1da177e4
LT		 8197 return stats;
8198}
8199
8200static inline u32 calc_crc(unsigned char *buf, int len)
8201{
8202 u32 reg;
8203 u32 tmp;
8204 int j, k;
8205
8206 reg = 0xffffffff;
8207
8208 for (j = 0; j < len; j++) {
8209 reg ^= buf[j];
8210
8211 for (k = 0; k < 8; k++) {
8212 tmp = reg & 0x01;
8213
8214 reg >>= 1;
8215
8216 if (tmp) {
8217 reg ^= 0xedb88320;
8218 }
8219 }
8220 }
8221
8222 return ~reg;
8223}
8224
8225static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8226{
8227 /* accept or reject all multicast frames */
8228 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8229 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8230 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8231 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8232}
8233
8234static void __tg3_set_rx_mode(struct net_device *dev)
8235{
8236 struct tg3 *tp = netdev_priv(dev);
8237 u32 rx_mode;
8238
8239 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8240 RX_MODE_KEEP_VLAN_TAG);
8241
8242 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8243 * flag clear.
8244 */
8245#if TG3_VLAN_TAG_USED
8246 if (!tp->vlgrp &&
8247 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8248 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8249#else
8250 /* By definition, VLAN is disabled always in this
8251 * case.
8252 */
8253 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8254 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8255#endif
8256
8257 if (dev->flags & IFF_PROMISC) {
8258 /* Promiscuous mode. */
8259 rx_mode |= RX_MODE_PROMISC;
8260 } else if (dev->flags & IFF_ALLMULTI) {
8261 /* Accept all multicast. */
8262 tg3_set_multi (tp, 1);
8263 } else if (dev->mc_count < 1) {
8264 /* Reject all multicast. */
8265 tg3_set_multi (tp, 0);
8266 } else {
8267 /* Accept one or more multicast(s). */
8268 struct dev_mc_list *mclist;
8269 unsigned int i;
8270 u32 mc_filter[4] = { 0, };
8271 u32 regidx;
8272 u32 bit;
8273 u32 crc;
8274
8275 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8276 i++, mclist = mclist->next) {
8277
8278 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8279 bit = ~crc & 0x7f;
8280 regidx = (bit & 0x60) >> 5;
8281 bit &= 0x1f;
8282 mc_filter[regidx] |= (1 << bit);
8283 }
8284
8285 tw32(MAC_HASH_REG_0, mc_filter[0]);
8286 tw32(MAC_HASH_REG_1, mc_filter[1]);
8287 tw32(MAC_HASH_REG_2, mc_filter[2]);
8288 tw32(MAC_HASH_REG_3, mc_filter[3]);
8289 }
8290
8291 if (rx_mode != tp->rx_mode) {
8292 tp->rx_mode = rx_mode;
8293 tw32_f(MAC_RX_MODE, rx_mode);
8294 udelay(10);
8295 }
8296}
8297
8298static void tg3_set_rx_mode(struct net_device *dev)
8299{
8300 struct tg3 *tp = netdev_priv(dev);
8301
e75f7c90
MC		 8302 if (!netif_running(dev))
8303 return;
8304
f47c11ee 8305 tg3_full_lock(tp, 0);
1da177e4 8306 __tg3_set_rx_mode(dev);
f47c11ee 8307 tg3_full_unlock(tp);
1da177e4
LT		 8308}
8309
8310#define TG3_REGDUMP_LEN (32 * 1024)
8311
8312static int tg3_get_regs_len(struct net_device *dev)
8313{
8314 return TG3_REGDUMP_LEN;
8315}
8316
8317static void tg3_get_regs(struct net_device *dev,
8318 struct ethtool_regs *regs, void *_p)
8319{
8320 u32 *p = _p;
8321 struct tg3 *tp = netdev_priv(dev);
8322 u8 *orig_p = _p;
8323 int i;
8324
8325 regs->version = 0;
8326
8327 memset(p, 0, TG3_REGDUMP_LEN);
8328
bc1c7567
MC		 8329 if (tp->link_config.phy_is_low_power)
8330 return;
8331
f47c11ee 8332 tg3_full_lock(tp, 0);
1da177e4
LT		 8333
8334#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8335#define GET_REG32_LOOP(base,len) \
8336do { p = (u32 *)(orig_p + (base)); \
8337 for (i = 0; i < len; i += 4) \
8338 __GET_REG32((base) + i); \
8339} while (0)
8340#define GET_REG32_1(reg) \
8341do { p = (u32 *)(orig_p + (reg)); \
8342 __GET_REG32((reg)); \
8343} while (0)
8344
8345 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8346 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8347 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8348 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8349 GET_REG32_1(SNDDATAC_MODE);
8350 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8351 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8352 GET_REG32_1(SNDBDC_MODE);
8353 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8354 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8355 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8356 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8357 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8358 GET_REG32_1(RCVDCC_MODE);
8359 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8360 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8361 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8362 GET_REG32_1(MBFREE_MODE);
8363 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8364 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8365 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8366 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8367 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8368 GET_REG32_1(RX_CPU_MODE);
8369 GET_REG32_1(RX_CPU_STATE);
8370 GET_REG32_1(RX_CPU_PGMCTR);
8371 GET_REG32_1(RX_CPU_HWBKPT);
8372 GET_REG32_1(TX_CPU_MODE);
8373 GET_REG32_1(TX_CPU_STATE);
8374 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8375 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8376 GET_REG32_LOOP(FTQ_RESET, 0x120);
8377 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8378 GET_REG32_1(DMAC_MODE);
8379 GET_REG32_LOOP(GRC_MODE, 0x4c);
8380 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8381 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8382
8383#undef __GET_REG32
8384#undef GET_REG32_LOOP
8385#undef GET_REG32_1
8386
f47c11ee 8387 tg3_full_unlock(tp);
1da177e4
LT		 8388}
8389
8390static int tg3_get_eeprom_len(struct net_device *dev)
8391{
8392 struct tg3 *tp = netdev_priv(dev);
8393
8394 return tp->nvram_size;
8395}
8396
8397static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
b9fc7dc5 8398static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
1820180b 8399static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
1da177e4
LT		 8400
8401static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8402{
8403 struct tg3 *tp = netdev_priv(dev);
8404 int ret;
8405 u8 *pd;
b9fc7dc5
AV		 8406 u32 i, offset, len, b_offset, b_count;
8407 __le32 val;
1da177e4 8408
bc1c7567
MC		 8409 if (tp->link_config.phy_is_low_power)
8410 return -EAGAIN;
8411
1da177e4
LT		 8412 offset = eeprom->offset;
8413 len = eeprom->len;
8414 eeprom->len = 0;
8415
8416 eeprom->magic = TG3_EEPROM_MAGIC;
8417
8418 if (offset & 3) {
8419 /* adjustments to start on required 4 byte boundary */
8420 b_offset = offset & 3;
8421 b_count = 4 - b_offset;
8422 if (b_count > len) {
8423 /* i.e. offset=1 len=2 */
8424 b_count = len;
8425 }
b9fc7dc5 8426 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
1da177e4
LT		 8427 if (ret)
8428 return ret;
1da177e4
LT		 8429 memcpy(data, ((char*)&val) + b_offset, b_count);
8430 len -= b_count;
8431 offset += b_count;
8432 eeprom->len += b_count;
8433 }
8434
8435 /* read bytes upto the last 4 byte boundary */
8436 pd = &data[eeprom->len];
8437 for (i = 0; i < (len - (len & 3)); i += 4) {
b9fc7dc5 8438 ret = tg3_nvram_read_le(tp, offset + i, &val);
1da177e4
LT		 8439 if (ret) {
8440 eeprom->len += i;
8441 return ret;
8442 }
1da177e4
LT		 8443 memcpy(pd + i, &val, 4);
8444 }
8445 eeprom->len += i;
8446
8447 if (len & 3) {
8448 /* read last bytes not ending on 4 byte boundary */
8449 pd = &data[eeprom->len];
8450 b_count = len & 3;
8451 b_offset = offset + len - b_count;
b9fc7dc5 8452 ret = tg3_nvram_read_le(tp, b_offset, &val);
1da177e4
LT		 8453 if (ret)
8454 return ret;
b9fc7dc5 8455 memcpy(pd, &val, b_count);
1da177e4
LT		 8456 eeprom->len += b_count;
8457 }
8458 return 0;
8459}
8460
6aa20a22 8461static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8462
8463static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8464{
8465 struct tg3 *tp = netdev_priv(dev);
8466 int ret;
b9fc7dc5 8467 u32 offset, len, b_offset, odd_len;
1da177e4 8468 u8 *buf;
b9fc7dc5 8469 __le32 start, end;
1da177e4 8470
bc1c7567
MC		 8471 if (tp->link_config.phy_is_low_power)
8472 return -EAGAIN;
8473
1da177e4
LT		 8474 if (eeprom->magic != TG3_EEPROM_MAGIC)
8475 return -EINVAL;
8476
8477 offset = eeprom->offset;
8478 len = eeprom->len;
8479
8480 if ((b_offset = (offset & 3))) {
8481 /* adjustments to start on required 4 byte boundary */
b9fc7dc5 8482 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
1da177e4
LT		 8483 if (ret)
8484 return ret;
1da177e4
LT		 8485 len += b_offset;
8486 offset &= ~3;
1c8594b4
MC		 8487 if (len < 4)
8488 len = 4;
1da177e4
LT		 8489 }
8490
8491 odd_len = 0;
1c8594b4 8492 if (len & 3) {
1da177e4
LT		 8493 /* adjustments to end on required 4 byte boundary */
8494 odd_len = 1;
8495 len = (len + 3) & ~3;
b9fc7dc5 8496 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
1da177e4
LT		 8497 if (ret)
8498 return ret;
1da177e4
LT		 8499 }
8500
8501 buf = data;
8502 if (b_offset || odd_len) {
8503 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8504 if (!buf)
1da177e4
LT		 8505 return -ENOMEM;
8506 if (b_offset)
8507 memcpy(buf, &start, 4);
8508 if (odd_len)
8509 memcpy(buf+len-4, &end, 4);
8510 memcpy(buf + b_offset, data, eeprom->len);
8511 }
8512
8513 ret = tg3_nvram_write_block(tp, offset, len, buf);
8514
8515 if (buf != data)
8516 kfree(buf);
8517
8518 return ret;
8519}
8520
8521static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8522{
b02fd9e3
MC		 8523 struct tg3 *tp = netdev_priv(dev);
8524
8525 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8526 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8527 return -EAGAIN;
298cf9be 8528 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8529 }
6aa20a22 8530
1da177e4
LT		 8531 cmd->supported = (SUPPORTED_Autoneg);
8532
8533 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8534 cmd->supported |= (SUPPORTED_1000baseT_Half |
8535 SUPPORTED_1000baseT_Full);
8536
ef348144 8537 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8538 cmd->supported |= (SUPPORTED_100baseT_Half |
8539 SUPPORTED_100baseT_Full |
8540 SUPPORTED_10baseT_Half |
8541 SUPPORTED_10baseT_Full |
3bebab59 8542 SUPPORTED_TP);
ef348144
KK		 8543 cmd->port = PORT_TP;
8544 } else {
1da177e4 8545 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8546 cmd->port = PORT_FIBRE;
8547 }
6aa20a22 8548
1da177e4
LT		 8549 cmd->advertising = tp->link_config.advertising;
8550 if (netif_running(dev)) {
8551 cmd->speed = tp->link_config.active_speed;
8552 cmd->duplex = tp->link_config.active_duplex;
8553 }
1da177e4 8554 cmd->phy_address = PHY_ADDR;
7e5856bd 8555 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8556 cmd->autoneg = tp->link_config.autoneg;
8557 cmd->maxtxpkt = 0;
8558 cmd->maxrxpkt = 0;
8559 return 0;
8560}
6aa20a22 8561
1da177e4
LT		 8562static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8563{
8564 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8565
b02fd9e3
MC		 8566 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8567 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8568 return -EAGAIN;
298cf9be 8569 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8570 }
8571
7e5856bd
MC		 8572 if (cmd->autoneg != AUTONEG_ENABLE &&
8573 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8574 return -EINVAL;
7e5856bd
MC		 8575
8576 if (cmd->autoneg == AUTONEG_DISABLE &&
8577 cmd->duplex != DUPLEX_FULL &&
8578 cmd->duplex != DUPLEX_HALF)
37ff238d 8579 return -EINVAL;
1da177e4 8580
7e5856bd
MC		 8581 if (cmd->autoneg == AUTONEG_ENABLE) {
8582 u32 mask = ADVERTISED_Autoneg |
8583 ADVERTISED_Pause |
8584 ADVERTISED_Asym_Pause;
8585
8586 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8587 mask |= ADVERTISED_1000baseT_Half |
8588 ADVERTISED_1000baseT_Full;
8589
8590 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8591 mask |= ADVERTISED_100baseT_Half |
8592 ADVERTISED_100baseT_Full |
8593 ADVERTISED_10baseT_Half |
8594 ADVERTISED_10baseT_Full |
8595 ADVERTISED_TP;
8596 else
8597 mask |= ADVERTISED_FIBRE;
8598
8599 if (cmd->advertising & ~mask)
8600 return -EINVAL;
8601
8602 mask &= (ADVERTISED_1000baseT_Half |
8603 ADVERTISED_1000baseT_Full |
8604 ADVERTISED_100baseT_Half |
8605 ADVERTISED_100baseT_Full |
8606 ADVERTISED_10baseT_Half |
8607 ADVERTISED_10baseT_Full);
8608
8609 cmd->advertising &= mask;
8610 } else {
8611 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8612 if (cmd->speed != SPEED_1000)
8613 return -EINVAL;
8614
8615 if (cmd->duplex != DUPLEX_FULL)
8616 return -EINVAL;
8617 } else {
8618 if (cmd->speed != SPEED_100 &&
8619 cmd->speed != SPEED_10)
8620 return -EINVAL;
8621 }
8622 }
8623
f47c11ee 8624 tg3_full_lock(tp, 0);
1da177e4
LT		 8625
8626 tp->link_config.autoneg = cmd->autoneg;
8627 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8628 tp->link_config.advertising = (cmd->advertising |
8629 ADVERTISED_Autoneg);
1da177e4
LT		 8630 tp->link_config.speed = SPEED_INVALID;
8631 tp->link_config.duplex = DUPLEX_INVALID;
8632 } else {
8633 tp->link_config.advertising = 0;
8634 tp->link_config.speed = cmd->speed;
8635 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8636 }
6aa20a22 8637
24fcad6b
MC		 8638 tp->link_config.orig_speed = tp->link_config.speed;
8639 tp->link_config.orig_duplex = tp->link_config.duplex;
8640 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8641
1da177e4
LT		 8642 if (netif_running(dev))
8643 tg3_setup_phy(tp, 1);
8644
f47c11ee 8645 tg3_full_unlock(tp);
6aa20a22 8646
1da177e4
LT		 8647 return 0;
8648}
6aa20a22 8649
1da177e4
LT		 8650static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8651{
8652 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8653
1da177e4
LT		 8654 strcpy(info->driver, DRV_MODULE_NAME);
8655 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8656 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8657 strcpy(info->bus_info, pci_name(tp->pdev));
8658}
6aa20a22 8659
1da177e4
LT		 8660static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8661{
8662 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8663
12dac075
RW		 8664 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8665 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8666 wol->supported = WAKE_MAGIC;
8667 else
8668 wol->supported = 0;
1da177e4 8669 wol->wolopts = 0;
05ac4cb7
MC		 8670 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8671 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8672 wol->wolopts = WAKE_MAGIC;
8673 memset(&wol->sopass, 0, sizeof(wol->sopass));
8674}
6aa20a22 8675
1da177e4
LT		 8676static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8677{
8678 struct tg3 *tp = netdev_priv(dev);
12dac075 8679 struct device *dp = &tp->pdev->dev;
6aa20a22 8680
1da177e4
LT		 8681 if (wol->wolopts & ~WAKE_MAGIC)
8682 return -EINVAL;
8683 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8684 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8685 return -EINVAL;
6aa20a22 8686
f47c11ee 8687 spin_lock_bh(&tp->lock);
12dac075 8688 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8689 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8690 device_set_wakeup_enable(dp, true);
8691 } else {
1da177e4 8692 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8693 device_set_wakeup_enable(dp, false);
8694 }
f47c11ee 8695 spin_unlock_bh(&tp->lock);
6aa20a22 8696
1da177e4
LT		 8697 return 0;
8698}
6aa20a22 8699
1da177e4
LT		 8700static u32 tg3_get_msglevel(struct net_device *dev)
8701{
8702 struct tg3 *tp = netdev_priv(dev);
8703 return tp->msg_enable;
8704}
6aa20a22 8705
1da177e4
LT		 8706static void tg3_set_msglevel(struct net_device *dev, u32 value)
8707{
8708 struct tg3 *tp = netdev_priv(dev);
8709 tp->msg_enable = value;
8710}
6aa20a22 8711
1da177e4
LT		 8712static int tg3_set_tso(struct net_device *dev, u32 value)
8713{
8714 struct tg3 *tp = netdev_priv(dev);
8715
8716 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8717 if (value)
8718 return -EINVAL;
8719 return 0;
8720 }
027455ad
MC		 8721 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8722 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 8723 if (value) {
b0026624 8724 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 8725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8726 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8727 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 8728 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8729 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 8730 dev->features |= NETIF_F_TSO_ECN;
8731 } else
8732 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8733 }
1da177e4
LT		 8734 return ethtool_op_set_tso(dev, value);
8735}
6aa20a22 8736
1da177e4
LT		 8737static int tg3_nway_reset(struct net_device *dev)
8738{
8739 struct tg3 *tp = netdev_priv(dev);
1da177e4 8740 int r;
6aa20a22 8741
1da177e4
LT		 8742 if (!netif_running(dev))
8743 return -EAGAIN;
8744
c94e3941
MC		 8745 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8746 return -EINVAL;
8747
b02fd9e3
MC		 8748 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8749 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8750 return -EAGAIN;
298cf9be 8751 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 8752 } else {
8753 u32 bmcr;
8754
8755 spin_lock_bh(&tp->lock);
8756 r = -EINVAL;
8757 tg3_readphy(tp, MII_BMCR, &bmcr);
8758 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8759 ((bmcr & BMCR_ANENABLE) ||
8760 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8761 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8762 BMCR_ANENABLE);
8763 r = 0;
8764 }
8765 spin_unlock_bh(&tp->lock);
1da177e4 8766 }
6aa20a22 8767
1da177e4
LT		 8768 return r;
8769}
6aa20a22 8770
1da177e4
LT		 8771static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8772{
8773 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8774
1da177e4
LT		 8775 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8776 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8777 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8778 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8779 else
8780 ering->rx_jumbo_max_pending = 0;
8781
8782 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8783
8784 ering->rx_pending = tp->rx_pending;
8785 ering->rx_mini_pending = 0;
4f81c32b
MC		 8786 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8787 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8788 else
8789 ering->rx_jumbo_pending = 0;
8790
1da177e4
LT		 8791 ering->tx_pending = tp->tx_pending;
8792}
6aa20a22 8793
1da177e4
LT		 8794static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8795{
8796 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8797 int irq_sync = 0, err = 0;
6aa20a22 8798
1da177e4
LT		 8799 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8800 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8801 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8802 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8803 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8804 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8805 return -EINVAL;
6aa20a22 8806
bbe832c0 8807 if (netif_running(dev)) {
b02fd9e3 8808 tg3_phy_stop(tp);
1da177e4 8809 tg3_netif_stop(tp);
bbe832c0
MC		 8810 irq_sync = 1;
8811 }
1da177e4 8812
bbe832c0 8813 tg3_full_lock(tp, irq_sync);
6aa20a22 8814
1da177e4
LT		 8815 tp->rx_pending = ering->rx_pending;
8816
8817 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8818 tp->rx_pending > 63)
8819 tp->rx_pending = 63;
8820 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8821 tp->tx_pending = ering->tx_pending;
8822
8823 if (netif_running(dev)) {
944d980e 8824 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8825 err = tg3_restart_hw(tp, 1);
8826 if (!err)
8827 tg3_netif_start(tp);
1da177e4
LT		 8828 }
8829
f47c11ee 8830 tg3_full_unlock(tp);
6aa20a22 8831
b02fd9e3
MC		 8832 if (irq_sync && !err)
8833 tg3_phy_start(tp);
8834
b9ec6c1b 8835 return err;
1da177e4 8836}
6aa20a22 8837
1da177e4
LT		 8838static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8839{
8840 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8841
1da177e4 8842 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 8843
e18ce346 8844 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 8845 epause->rx_pause = 1;
8846 else
8847 epause->rx_pause = 0;
8848
e18ce346 8849 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 8850 epause->tx_pause = 1;
8851 else
8852 epause->tx_pause = 0;
1da177e4 8853}
6aa20a22 8854
1da177e4
LT		 8855static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8856{
8857 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 8858 int err = 0;
6aa20a22 8859
b02fd9e3
MC		 8860 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8861 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8862 return -EAGAIN;
1da177e4 8863
b02fd9e3
MC		 8864 if (epause->autoneg) {
8865 u32 newadv;
8866 struct phy_device *phydev;
f47c11ee 8867
298cf9be 8868 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 8869
b02fd9e3
MC		 8870 if (epause->rx_pause) {
8871 if (epause->tx_pause)
8872 newadv = ADVERTISED_Pause;
8873 else
8874 newadv = ADVERTISED_Pause |
8875 ADVERTISED_Asym_Pause;
8876 } else if (epause->tx_pause) {
8877 newadv = ADVERTISED_Asym_Pause;
8878 } else
8879 newadv = 0;
8880
8881 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
8882 u32 oldadv = phydev->advertising &
8883 (ADVERTISED_Pause |
8884 ADVERTISED_Asym_Pause);
8885 if (oldadv != newadv) {
8886 phydev->advertising &=
8887 ~(ADVERTISED_Pause |
8888 ADVERTISED_Asym_Pause);
8889 phydev->advertising |= newadv;
8890 err = phy_start_aneg(phydev);
8891 }
8892 } else {
8893 tp->link_config.advertising &=
8894 ~(ADVERTISED_Pause |
8895 ADVERTISED_Asym_Pause);
8896 tp->link_config.advertising |= newadv;
8897 }
8898 } else {
8899 if (epause->rx_pause)
e18ce346 8900 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 8901 else
e18ce346 8902 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 8903
b02fd9e3 8904 if (epause->tx_pause)
e18ce346 8905 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 8906 else
e18ce346 8907 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 8908
8909 if (netif_running(dev))
8910 tg3_setup_flow_control(tp, 0, 0);
8911 }
8912 } else {
8913 int irq_sync = 0;
8914
8915 if (netif_running(dev)) {
8916 tg3_netif_stop(tp);
8917 irq_sync = 1;
8918 }
8919
8920 tg3_full_lock(tp, irq_sync);
8921
8922 if (epause->autoneg)
8923 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8924 else
8925 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8926 if (epause->rx_pause)
e18ce346 8927 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 8928 else
e18ce346 8929 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 8930 if (epause->tx_pause)
e18ce346 8931 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 8932 else
e18ce346 8933 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 8934
8935 if (netif_running(dev)) {
8936 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8937 err = tg3_restart_hw(tp, 1);
8938 if (!err)
8939 tg3_netif_start(tp);
8940 }
8941
8942 tg3_full_unlock(tp);
8943 }
6aa20a22 8944
b9ec6c1b 8945 return err;
1da177e4 8946}
6aa20a22 8947
1da177e4
LT		 8948static u32 tg3_get_rx_csum(struct net_device *dev)
8949{
8950 struct tg3 *tp = netdev_priv(dev);
8951 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8952}
6aa20a22 8953
1da177e4
LT		 8954static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8955{
8956 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8957
1da177e4
LT		 8958 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8959 if (data != 0)
8960 return -EINVAL;
8961 return 0;
8962 }
6aa20a22 8963
f47c11ee 8964 spin_lock_bh(&tp->lock);
1da177e4
LT		 8965 if (data)
8966 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8967 else
8968 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 8969 spin_unlock_bh(&tp->lock);
6aa20a22 8970
1da177e4
LT		 8971 return 0;
8972}
6aa20a22 8973
1da177e4
LT		 8974static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8975{
8976 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8977
1da177e4
LT		 8978 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8979 if (data != 0)
8980 return -EINVAL;
8981 return 0;
8982 }
6aa20a22 8983
321d32a0 8984 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 8985 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 8986 else
9c27dbdf 8987 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 8988
8989 return 0;
8990}
8991
b9f2c044 8992static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 8993{
b9f2c044
JG		 8994 switch (sset) {
8995 case ETH_SS_TEST:
8996 return TG3_NUM_TEST;
8997 case ETH_SS_STATS:
8998 return TG3_NUM_STATS;
8999 default:
9000 return -EOPNOTSUPP;
9001 }
4cafd3f5
MC		 9002}
9003
1da177e4
LT		 9004static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9005{
9006 switch (stringset) {
9007 case ETH_SS_STATS:
9008 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9009 break;
4cafd3f5
MC		 9010 case ETH_SS_TEST:
9011 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9012 break;
1da177e4
LT		 9013 default:
9014 WARN_ON(1); /* we need a WARN() */
9015 break;
9016 }
9017}
9018
4009a93d
MC		 9019static int tg3_phys_id(struct net_device *dev, u32 data)
9020{
9021 struct tg3 *tp = netdev_priv(dev);
9022 int i;
9023
9024 if (!netif_running(tp->dev))
9025 return -EAGAIN;
9026
9027 if (data == 0)
759afc31 9028 data = UINT_MAX / 2;
4009a93d
MC		 9029
9030 for (i = 0; i < (data * 2); i++) {
9031 if ((i % 2) == 0)
9032 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9033 LED_CTRL_1000MBPS_ON |
9034 LED_CTRL_100MBPS_ON |
9035 LED_CTRL_10MBPS_ON |
9036 LED_CTRL_TRAFFIC_OVERRIDE |
9037 LED_CTRL_TRAFFIC_BLINK |
9038 LED_CTRL_TRAFFIC_LED);
6aa20a22 9039
4009a93d
MC		 9040 else
9041 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9042 LED_CTRL_TRAFFIC_OVERRIDE);
9043
9044 if (msleep_interruptible(500))
9045 break;
9046 }
9047 tw32(MAC_LED_CTRL, tp->led_ctrl);
9048 return 0;
9049}
9050
1da177e4
LT		 9051static void tg3_get_ethtool_stats (struct net_device *dev,
9052 struct ethtool_stats *estats, u64 *tmp_stats)
9053{
9054 struct tg3 *tp = netdev_priv(dev);
9055 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9056}
9057
566f86ad 9058#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9059#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9060#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9061#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9062#define NVRAM_SELFBOOT_HW_SIZE 0x20
9063#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9064
9065static int tg3_test_nvram(struct tg3 *tp)
9066{
b9fc7dc5
AV		 9067 u32 csum, magic;
9068 __le32 *buf;
ab0049b4 9069 int i, j, k, err = 0, size;
566f86ad 9070
1820180b 9071 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 9072 return -EIO;
9073
1b27777a
MC		 9074 if (magic == TG3_EEPROM_MAGIC)
9075 size = NVRAM_TEST_SIZE;
b16250e3 9076 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9077 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9078 TG3_EEPROM_SB_FORMAT_1) {
9079 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9080 case TG3_EEPROM_SB_REVISION_0:
9081 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9082 break;
9083 case TG3_EEPROM_SB_REVISION_2:
9084 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9085 break;
9086 case TG3_EEPROM_SB_REVISION_3:
9087 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9088 break;
9089 default:
9090 return 0;
9091 }
9092 } else
1b27777a 9093 return 0;
b16250e3
MC		 9094 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9095 size = NVRAM_SELFBOOT_HW_SIZE;
9096 else
1b27777a
MC		 9097 return -EIO;
9098
9099 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9100 if (buf == NULL)
9101 return -ENOMEM;
9102
1b27777a
MC		 9103 err = -EIO;
9104 for (i = 0, j = 0; i < size; i += 4, j++) {
b9fc7dc5 9105 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
566f86ad 9106 break;
566f86ad 9107 }
1b27777a 9108 if (i < size)
566f86ad
MC		 9109 goto out;
9110
1b27777a 9111 /* Selfboot format */
b9fc7dc5
AV		 9112 magic = swab32(le32_to_cpu(buf[0]));
9113 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9114 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9115 u8 *buf8 = (u8 *) buf, csum8 = 0;
9116
b9fc7dc5 9117 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9118 TG3_EEPROM_SB_REVISION_2) {
9119 /* For rev 2, the csum doesn't include the MBA. */
9120 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9121 csum8 += buf8[i];
9122 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9123 csum8 += buf8[i];
9124 } else {
9125 for (i = 0; i < size; i++)
9126 csum8 += buf8[i];
9127 }
1b27777a 9128
ad96b485
AB		 9129 if (csum8 == 0) {
9130 err = 0;
9131 goto out;
9132 }
9133
9134 err = -EIO;
9135 goto out;
1b27777a 9136 }
566f86ad 9137
b9fc7dc5 9138 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9139 TG3_EEPROM_MAGIC_HW) {
9140 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9141 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9142 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9143
9144 /* Separate the parity bits and the data bytes. */
9145 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9146 if ((i == 0) || (i == 8)) {
9147 int l;
9148 u8 msk;
9149
9150 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9151 parity[k++] = buf8[i] & msk;
9152 i++;
9153 }
9154 else if (i == 16) {
9155 int l;
9156 u8 msk;
9157
9158 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9159 parity[k++] = buf8[i] & msk;
9160 i++;
9161
9162 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9163 parity[k++] = buf8[i] & msk;
9164 i++;
9165 }
9166 data[j++] = buf8[i];
9167 }
9168
9169 err = -EIO;
9170 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9171 u8 hw8 = hweight8(data[i]);
9172
9173 if ((hw8 & 0x1) && parity[i])
9174 goto out;
9175 else if (!(hw8 & 0x1) && !parity[i])
9176 goto out;
9177 }
9178 err = 0;
9179 goto out;
9180 }
9181
566f86ad
MC		 9182 /* Bootstrap checksum at offset 0x10 */
9183 csum = calc_crc((unsigned char *) buf, 0x10);
b9fc7dc5 9184 if(csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9185 goto out;
9186
9187 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9188 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
b9fc7dc5 9189 if (csum != le32_to_cpu(buf[0xfc/4]))
566f86ad
MC		 9190 goto out;
9191
9192 err = 0;
9193
9194out:
9195 kfree(buf);
9196 return err;
9197}
9198
ca43007a
MC		 9199#define TG3_SERDES_TIMEOUT_SEC 2
9200#define TG3_COPPER_TIMEOUT_SEC 6
9201
9202static int tg3_test_link(struct tg3 *tp)
9203{
9204 int i, max;
9205
9206 if (!netif_running(tp->dev))
9207 return -ENODEV;
9208
4c987487 9209 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9210 max = TG3_SERDES_TIMEOUT_SEC;
9211 else
9212 max = TG3_COPPER_TIMEOUT_SEC;
9213
9214 for (i = 0; i < max; i++) {
9215 if (netif_carrier_ok(tp->dev))
9216 return 0;
9217
9218 if (msleep_interruptible(1000))
9219 break;
9220 }
9221
9222 return -EIO;
9223}
9224
a71116d1 9225/* Only test the commonly used registers */
30ca3e37 9226static int tg3_test_registers(struct tg3 *tp)
a71116d1 9227{
b16250e3 9228 int i, is_5705, is_5750;
a71116d1
MC		 9229 u32 offset, read_mask, write_mask, val, save_val, read_val;
9230 static struct {
9231 u16 offset;
9232 u16 flags;
9233#define TG3_FL_5705 0x1
9234#define TG3_FL_NOT_5705 0x2
9235#define TG3_FL_NOT_5788 0x4
b16250e3 9236#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9237 u32 read_mask;
9238 u32 write_mask;
9239 } reg_tbl[] = {
9240 /* MAC Control Registers */
9241 { MAC_MODE, TG3_FL_NOT_5705,
9242 0x00000000, 0x00ef6f8c },
9243 { MAC_MODE, TG3_FL_5705,
9244 0x00000000, 0x01ef6b8c },
9245 { MAC_STATUS, TG3_FL_NOT_5705,
9246 0x03800107, 0x00000000 },
9247 { MAC_STATUS, TG3_FL_5705,
9248 0x03800100, 0x00000000 },
9249 { MAC_ADDR_0_HIGH, 0x0000,
9250 0x00000000, 0x0000ffff },
9251 { MAC_ADDR_0_LOW, 0x0000,
9252 0x00000000, 0xffffffff },
9253 { MAC_RX_MTU_SIZE, 0x0000,
9254 0x00000000, 0x0000ffff },
9255 { MAC_TX_MODE, 0x0000,
9256 0x00000000, 0x00000070 },
9257 { MAC_TX_LENGTHS, 0x0000,
9258 0x00000000, 0x00003fff },
9259 { MAC_RX_MODE, TG3_FL_NOT_5705,
9260 0x00000000, 0x000007fc },
9261 { MAC_RX_MODE, TG3_FL_5705,
9262 0x00000000, 0x000007dc },
9263 { MAC_HASH_REG_0, 0x0000,
9264 0x00000000, 0xffffffff },
9265 { MAC_HASH_REG_1, 0x0000,
9266 0x00000000, 0xffffffff },
9267 { MAC_HASH_REG_2, 0x0000,
9268 0x00000000, 0xffffffff },
9269 { MAC_HASH_REG_3, 0x0000,
9270 0x00000000, 0xffffffff },
9271
9272 /* Receive Data and Receive BD Initiator Control Registers. */
9273 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9274 0x00000000, 0xffffffff },
9275 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9276 0x00000000, 0xffffffff },
9277 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9278 0x00000000, 0x00000003 },
9279 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9280 0x00000000, 0xffffffff },
9281 { RCVDBDI_STD_BD+0, 0x0000,
9282 0x00000000, 0xffffffff },
9283 { RCVDBDI_STD_BD+4, 0x0000,
9284 0x00000000, 0xffffffff },
9285 { RCVDBDI_STD_BD+8, 0x0000,
9286 0x00000000, 0xffff0002 },
9287 { RCVDBDI_STD_BD+0xc, 0x0000,
9288 0x00000000, 0xffffffff },
6aa20a22 9289
a71116d1
MC		 9290 /* Receive BD Initiator Control Registers. */
9291 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9292 0x00000000, 0xffffffff },
9293 { RCVBDI_STD_THRESH, TG3_FL_5705,
9294 0x00000000, 0x000003ff },
9295 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9296 0x00000000, 0xffffffff },
6aa20a22 9297
a71116d1
MC		 9298 /* Host Coalescing Control Registers. */
9299 { HOSTCC_MODE, TG3_FL_NOT_5705,
9300 0x00000000, 0x00000004 },
9301 { HOSTCC_MODE, TG3_FL_5705,
9302 0x00000000, 0x000000f6 },
9303 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9304 0x00000000, 0xffffffff },
9305 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9306 0x00000000, 0x000003ff },
9307 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9308 0x00000000, 0xffffffff },
9309 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9310 0x00000000, 0x000003ff },
9311 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9312 0x00000000, 0xffffffff },
9313 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9314 0x00000000, 0x000000ff },
9315 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9316 0x00000000, 0xffffffff },
9317 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9318 0x00000000, 0x000000ff },
9319 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9320 0x00000000, 0xffffffff },
9321 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9322 0x00000000, 0xffffffff },
9323 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9324 0x00000000, 0xffffffff },
9325 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9326 0x00000000, 0x000000ff },
9327 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9328 0x00000000, 0xffffffff },
9329 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9330 0x00000000, 0x000000ff },
9331 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9332 0x00000000, 0xffffffff },
9333 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9334 0x00000000, 0xffffffff },
9335 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9336 0x00000000, 0xffffffff },
9337 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9338 0x00000000, 0xffffffff },
9339 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9340 0x00000000, 0xffffffff },
9341 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9342 0xffffffff, 0x00000000 },
9343 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9344 0xffffffff, 0x00000000 },
9345
9346 /* Buffer Manager Control Registers. */
b16250e3 9347 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9348 0x00000000, 0x007fff80 },
b16250e3 9349 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9350 0x00000000, 0x007fffff },
9351 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9352 0x00000000, 0x0000003f },
9353 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9354 0x00000000, 0x000001ff },
9355 { BUFMGR_MB_HIGH_WATER, 0x0000,
9356 0x00000000, 0x000001ff },
9357 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9358 0xffffffff, 0x00000000 },
9359 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9360 0xffffffff, 0x00000000 },
6aa20a22 9361
a71116d1
MC		 9362 /* Mailbox Registers */
9363 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9364 0x00000000, 0x000001ff },
9365 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9366 0x00000000, 0x000001ff },
9367 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9368 0x00000000, 0x000007ff },
9369 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9370 0x00000000, 0x000001ff },
9371
9372 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9373 };
9374
b16250e3
MC		 9375 is_5705 = is_5750 = 0;
9376 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9377 is_5705 = 1;
b16250e3
MC		 9378 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9379 is_5750 = 1;
9380 }
a71116d1
MC		 9381
9382 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9383 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9384 continue;
9385
9386 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9387 continue;
9388
9389 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9390 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9391 continue;
9392
b16250e3
MC		 9393 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9394 continue;
9395
a71116d1
MC		 9396 offset = (u32) reg_tbl[i].offset;
9397 read_mask = reg_tbl[i].read_mask;
9398 write_mask = reg_tbl[i].write_mask;
9399
9400 /* Save the original register content */
9401 save_val = tr32(offset);
9402
9403 /* Determine the read-only value. */
9404 read_val = save_val & read_mask;
9405
9406 /* Write zero to the register, then make sure the read-only bits
9407 * are not changed and the read/write bits are all zeros.
9408 */
9409 tw32(offset, 0);
9410
9411 val = tr32(offset);
9412
9413 /* Test the read-only and read/write bits. */
9414 if (((val & read_mask) != read_val) || (val & write_mask))
9415 goto out;
9416
9417 /* Write ones to all the bits defined by RdMask and WrMask, then
9418 * make sure the read-only bits are not changed and the
9419 * read/write bits are all ones.
9420 */
9421 tw32(offset, read_mask | write_mask);
9422
9423 val = tr32(offset);
9424
9425 /* Test the read-only bits. */
9426 if ((val & read_mask) != read_val)
9427 goto out;
9428
9429 /* Test the read/write bits. */
9430 if ((val & write_mask) != write_mask)
9431 goto out;
9432
9433 tw32(offset, save_val);
9434 }
9435
9436 return 0;
9437
9438out:
9f88f29f
MC		 9439 if (netif_msg_hw(tp))
9440 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9441 offset);
a71116d1
MC		 9442 tw32(offset, save_val);
9443 return -EIO;
9444}
9445
7942e1db
MC		 9446static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9447{
f71e1309 9448 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9449 int i;
9450 u32 j;
9451
e9edda69 9452 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9453 for (j = 0; j < len; j += 4) {
9454 u32 val;
9455
9456 tg3_write_mem(tp, offset + j, test_pattern[i]);
9457 tg3_read_mem(tp, offset + j, &val);
9458 if (val != test_pattern[i])
9459 return -EIO;
9460 }
9461 }
9462 return 0;
9463}
9464
9465static int tg3_test_memory(struct tg3 *tp)
9466{
9467 static struct mem_entry {
9468 u32 offset;
9469 u32 len;
9470 } mem_tbl_570x[] = {
38690194 9471 { 0x00000000, 0x00b50},
7942e1db
MC		 9472 { 0x00002000, 0x1c000},
9473 { 0xffffffff, 0x00000}
9474 }, mem_tbl_5705[] = {
9475 { 0x00000100, 0x0000c},
9476 { 0x00000200, 0x00008},
7942e1db
MC		 9477 { 0x00004000, 0x00800},
9478 { 0x00006000, 0x01000},
9479 { 0x00008000, 0x02000},
9480 { 0x00010000, 0x0e000},
9481 { 0xffffffff, 0x00000}
79f4d13a
MC		 9482 }, mem_tbl_5755[] = {
9483 { 0x00000200, 0x00008},
9484 { 0x00004000, 0x00800},
9485 { 0x00006000, 0x00800},
9486 { 0x00008000, 0x02000},
9487 { 0x00010000, 0x0c000},
9488 { 0xffffffff, 0x00000}
b16250e3
MC		 9489 }, mem_tbl_5906[] = {
9490 { 0x00000200, 0x00008},
9491 { 0x00004000, 0x00400},
9492 { 0x00006000, 0x00400},
9493 { 0x00008000, 0x01000},
9494 { 0x00010000, 0x01000},
9495 { 0xffffffff, 0x00000}
7942e1db
MC		 9496 };
9497 struct mem_entry *mem_tbl;
9498 int err = 0;
9499 int i;
9500
321d32a0
MC		 9501 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9502 mem_tbl = mem_tbl_5755;
9503 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9504 mem_tbl = mem_tbl_5906;
9505 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9506 mem_tbl = mem_tbl_5705;
9507 else
7942e1db
MC		 9508 mem_tbl = mem_tbl_570x;
9509
9510 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9511 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9512 mem_tbl[i].len)) != 0)
9513 break;
9514 }
6aa20a22 9515
7942e1db
MC		 9516 return err;
9517}
9518
9f40dead
MC		 9519#define TG3_MAC_LOOPBACK 0
9520#define TG3_PHY_LOOPBACK 1
9521
9522static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9523{
9f40dead 9524 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9525 u32 desc_idx;
9526 struct sk_buff *skb, *rx_skb;
9527 u8 *tx_data;
9528 dma_addr_t map;
9529 int num_pkts, tx_len, rx_len, i, err;
9530 struct tg3_rx_buffer_desc *desc;
9531
9f40dead 9532 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9533 /* HW errata - mac loopback fails in some cases on 5780.
9534 * Normal traffic and PHY loopback are not affected by
9535 * errata.
9536 */
9537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9538 return 0;
9539
9f40dead 9540 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9541 MAC_MODE_PORT_INT_LPBACK;
9542 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9543 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9544 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9545 mac_mode |= MAC_MODE_PORT_MODE_MII;
9546 else
9547 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9548 tw32(MAC_MODE, mac_mode);
9549 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9550 u32 val;
9551
b16250e3
MC		 9552 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9553 u32 phytest;
9554
9555 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9556 u32 phy;
9557
9558 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9559 phytest | MII_TG3_EPHY_SHADOW_EN);
9560 if (!tg3_readphy(tp, 0x1b, &phy))
9561 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9562 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9563 }
5d64ad34
MC		 9564 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9565 } else
9566 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9567
9ef8ca99
MC		 9568 tg3_phy_toggle_automdix(tp, 0);
9569
3f7045c1 9570 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9571 udelay(40);
5d64ad34 9572
e8f3f6ca 9573 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9574 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9575 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9576 mac_mode |= MAC_MODE_PORT_MODE_MII;
9577 } else
9578 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9579
c94e3941
MC		 9580 /* reset to prevent losing 1st rx packet intermittently */
9581 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9582 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9583 udelay(10);
9584 tw32_f(MAC_RX_MODE, tp->rx_mode);
9585 }
e8f3f6ca
MC		 9586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9587 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9588 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9589 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9590 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9591 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9592 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9593 }
9f40dead 9594 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9595 }
9596 else
9597 return -EINVAL;
c76949a6
MC		 9598
9599 err = -EIO;
9600
c76949a6 9601 tx_len = 1514;
a20e9c62 9602 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9603 if (!skb)
9604 return -ENOMEM;
9605
c76949a6
MC		 9606 tx_data = skb_put(skb, tx_len);
9607 memcpy(tx_data, tp->dev->dev_addr, 6);
9608 memset(tx_data + 6, 0x0, 8);
9609
9610 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9611
9612 for (i = 14; i < tx_len; i++)
9613 tx_data[i] = (u8) (i & 0xff);
9614
9615 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9616
9617 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9618 HOSTCC_MODE_NOW);
9619
9620 udelay(10);
9621
9622 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9623
c76949a6
MC		 9624 num_pkts = 0;
9625
9f40dead 9626 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9627
9f40dead 9628 tp->tx_prod++;
c76949a6
MC		 9629 num_pkts++;
9630
9f40dead
MC		 9631 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9632 tp->tx_prod);
09ee929c 9633 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9634
9635 udelay(10);
9636
3f7045c1
MC		 9637 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9638 for (i = 0; i < 25; i++) {
c76949a6
MC		 9639 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9640 HOSTCC_MODE_NOW);
9641
9642 udelay(10);
9643
9644 tx_idx = tp->hw_status->idx[0].tx_consumer;
9645 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9646 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9647 (rx_idx == (rx_start_idx + num_pkts)))
9648 break;
9649 }
9650
9651 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9652 dev_kfree_skb(skb);
9653
9f40dead 9654 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9655 goto out;
9656
9657 if (rx_idx != rx_start_idx + num_pkts)
9658 goto out;
9659
9660 desc = &tp->rx_rcb[rx_start_idx];
9661 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9662 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9663 if (opaque_key != RXD_OPAQUE_RING_STD)
9664 goto out;
9665
9666 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9667 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9668 goto out;
9669
9670 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9671 if (rx_len != tx_len)
9672 goto out;
9673
9674 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9675
9676 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9677 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9678
9679 for (i = 14; i < tx_len; i++) {
9680 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9681 goto out;
9682 }
9683 err = 0;
6aa20a22 9684
c76949a6
MC		 9685 /* tg3_free_rings will unmap and free the rx_skb */
9686out:
9687 return err;
9688}
9689
9f40dead
MC		 9690#define TG3_MAC_LOOPBACK_FAILED 1
9691#define TG3_PHY_LOOPBACK_FAILED 2
9692#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9693 TG3_PHY_LOOPBACK_FAILED)
9694
9695static int tg3_test_loopback(struct tg3 *tp)
9696{
9697 int err = 0;
9936bcf6 9698 u32 cpmuctrl = 0;
9f40dead
MC		 9699
9700 if (!netif_running(tp->dev))
9701 return TG3_LOOPBACK_FAILED;
9702
b9ec6c1b
MC		 9703 err = tg3_reset_hw(tp, 1);
9704 if (err)
9705 return TG3_LOOPBACK_FAILED;
9f40dead 9706
6833c043
MC		 9707 /* Turn off gphy autopowerdown. */
9708 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9709 tg3_phy_toggle_apd(tp, false);
9710
321d32a0 9711 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9712 int i;
9713 u32 status;
9714
9715 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9716
9717 /* Wait for up to 40 microseconds to acquire lock. */
9718 for (i = 0; i < 4; i++) {
9719 status = tr32(TG3_CPMU_MUTEX_GNT);
9720 if (status == CPMU_MUTEX_GNT_DRIVER)
9721 break;
9722 udelay(10);
9723 }
9724
9725 if (status != CPMU_MUTEX_GNT_DRIVER)
9726 return TG3_LOOPBACK_FAILED;
9727
b2a5c19c 9728 /* Turn off link-based power management. */
e875093c 9729 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 9730 tw32(TG3_CPMU_CTRL,
9731 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9732 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9733 }
9734
9f40dead
MC		 9735 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9736 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9737
321d32a0 9738 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9739 tw32(TG3_CPMU_CTRL, cpmuctrl);
9740
9741 /* Release the mutex */
9742 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9743 }
9744
dd477003
MC		 9745 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9746 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 9747 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9748 err |= TG3_PHY_LOOPBACK_FAILED;
9749 }
9750
6833c043
MC		 9751 /* Re-enable gphy autopowerdown. */
9752 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9753 tg3_phy_toggle_apd(tp, true);
9754
9f40dead
MC		 9755 return err;
9756}
9757
4cafd3f5
MC		 9758static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9759 u64 *data)
9760{
566f86ad
MC		 9761 struct tg3 *tp = netdev_priv(dev);
9762
bc1c7567
MC		 9763 if (tp->link_config.phy_is_low_power)
9764 tg3_set_power_state(tp, PCI_D0);
9765
566f86ad
MC		 9766 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9767
9768 if (tg3_test_nvram(tp) != 0) {
9769 etest->flags |= ETH_TEST_FL_FAILED;
9770 data[0] = 1;
9771 }
ca43007a
MC		 9772 if (tg3_test_link(tp) != 0) {
9773 etest->flags |= ETH_TEST_FL_FAILED;
9774 data[1] = 1;
9775 }
a71116d1 9776 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 9777 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 9778
9779 if (netif_running(dev)) {
b02fd9e3 9780 tg3_phy_stop(tp);
a71116d1 9781 tg3_netif_stop(tp);
bbe832c0
MC		 9782 irq_sync = 1;
9783 }
a71116d1 9784
bbe832c0 9785 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9786
9787 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9788 err = tg3_nvram_lock(tp);
a71116d1
MC		 9789 tg3_halt_cpu(tp, RX_CPU_BASE);
9790 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9791 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9792 if (!err)
9793 tg3_nvram_unlock(tp);
a71116d1 9794
d9ab5ad1
MC		 9795 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9796 tg3_phy_reset(tp);
9797
a71116d1
MC		 9798 if (tg3_test_registers(tp) != 0) {
9799 etest->flags |= ETH_TEST_FL_FAILED;
9800 data[2] = 1;
9801 }
7942e1db
MC		 9802 if (tg3_test_memory(tp) != 0) {
9803 etest->flags |= ETH_TEST_FL_FAILED;
9804 data[3] = 1;
9805 }
9f40dead 9806 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9807 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9808
f47c11ee
DM		 9809 tg3_full_unlock(tp);
9810
d4bc3927
MC		 9811 if (tg3_test_interrupt(tp) != 0) {
9812 etest->flags |= ETH_TEST_FL_FAILED;
9813 data[5] = 1;
9814 }
f47c11ee
DM		 9815
9816 tg3_full_lock(tp, 0);
d4bc3927 9817
a71116d1
MC		 9818 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9819 if (netif_running(dev)) {
9820 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 9821 err2 = tg3_restart_hw(tp, 1);
9822 if (!err2)
b9ec6c1b 9823 tg3_netif_start(tp);
a71116d1 9824 }
f47c11ee
DM		 9825
9826 tg3_full_unlock(tp);
b02fd9e3
MC		 9827
9828 if (irq_sync && !err2)
9829 tg3_phy_start(tp);
a71116d1 9830 }
bc1c7567
MC		 9831 if (tp->link_config.phy_is_low_power)
9832 tg3_set_power_state(tp, PCI_D3hot);
9833
4cafd3f5
MC		 9834}
9835
1da177e4
LT		 9836static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9837{
9838 struct mii_ioctl_data *data = if_mii(ifr);
9839 struct tg3 *tp = netdev_priv(dev);
9840 int err;
9841
b02fd9e3
MC		 9842 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9843 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9844 return -EAGAIN;
298cf9be 9845 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 9846 }
9847
1da177e4
LT		 9848 switch(cmd) {
9849 case SIOCGMIIPHY:
9850 data->phy_id = PHY_ADDR;
9851
9852 /* fallthru */
9853 case SIOCGMIIREG: {
9854 u32 mii_regval;
9855
9856 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9857 break; /* We have no PHY */
9858
bc1c7567
MC		 9859 if (tp->link_config.phy_is_low_power)
9860 return -EAGAIN;
9861
f47c11ee 9862 spin_lock_bh(&tp->lock);
1da177e4 9863 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9864 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9865
9866 data->val_out = mii_regval;
9867
9868 return err;
9869 }
9870
9871 case SIOCSMIIREG:
9872 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9873 break; /* We have no PHY */
9874
9875 if (!capable(CAP_NET_ADMIN))
9876 return -EPERM;
9877
bc1c7567
MC		 9878 if (tp->link_config.phy_is_low_power)
9879 return -EAGAIN;
9880
f47c11ee 9881 spin_lock_bh(&tp->lock);
1da177e4 9882 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 9883 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9884
9885 return err;
9886
9887 default:
9888 /* do nothing */
9889 break;
9890 }
9891 return -EOPNOTSUPP;
9892}
9893
9894#if TG3_VLAN_TAG_USED
9895static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9896{
9897 struct tg3 *tp = netdev_priv(dev);
9898
844b3eed
MC		 9899 if (!netif_running(dev)) {
9900 tp->vlgrp = grp;
9901 return;
9902 }
9903
9904 tg3_netif_stop(tp);
29315e87 9905
f47c11ee 9906 tg3_full_lock(tp, 0);
1da177e4
LT		 9907
9908 tp->vlgrp = grp;
9909
9910 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9911 __tg3_set_rx_mode(dev);
9912
844b3eed 9913 tg3_netif_start(tp);
46966545
MC		 9914
9915 tg3_full_unlock(tp);
1da177e4 9916}
1da177e4
LT		 9917#endif
9918
15f9850d
DM		 9919static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9920{
9921 struct tg3 *tp = netdev_priv(dev);
9922
9923 memcpy(ec, &tp->coal, sizeof(*ec));
9924 return 0;
9925}
9926
d244c892
MC		 9927static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9928{
9929 struct tg3 *tp = netdev_priv(dev);
9930 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9931 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9932
9933 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9934 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9935 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9936 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9937 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9938 }
9939
9940 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9941 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9942 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9943 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9944 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9945 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9946 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9947 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9948 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9949 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9950 return -EINVAL;
9951
9952 /* No rx interrupts will be generated if both are zero */
9953 if ((ec->rx_coalesce_usecs == 0) &&
9954 (ec->rx_max_coalesced_frames == 0))
9955 return -EINVAL;
9956
9957 /* No tx interrupts will be generated if both are zero */
9958 if ((ec->tx_coalesce_usecs == 0) &&
9959 (ec->tx_max_coalesced_frames == 0))
9960 return -EINVAL;
9961
9962 /* Only copy relevant parameters, ignore all others. */
9963 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9964 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9965 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9966 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9967 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9968 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9969 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9970 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9971 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9972
9973 if (netif_running(dev)) {
9974 tg3_full_lock(tp, 0);
9975 __tg3_set_coalesce(tp, &tp->coal);
9976 tg3_full_unlock(tp);
9977 }
9978 return 0;
9979}
9980
7282d491 9981static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 9982 .get_settings = tg3_get_settings,
9983 .set_settings = tg3_set_settings,
9984 .get_drvinfo = tg3_get_drvinfo,
9985 .get_regs_len = tg3_get_regs_len,
9986 .get_regs = tg3_get_regs,
9987 .get_wol = tg3_get_wol,
9988 .set_wol = tg3_set_wol,
9989 .get_msglevel = tg3_get_msglevel,
9990 .set_msglevel = tg3_set_msglevel,
9991 .nway_reset = tg3_nway_reset,
9992 .get_link = ethtool_op_get_link,
9993 .get_eeprom_len = tg3_get_eeprom_len,
9994 .get_eeprom = tg3_get_eeprom,
9995 .set_eeprom = tg3_set_eeprom,
9996 .get_ringparam = tg3_get_ringparam,
9997 .set_ringparam = tg3_set_ringparam,
9998 .get_pauseparam = tg3_get_pauseparam,
9999 .set_pauseparam = tg3_set_pauseparam,
10000 .get_rx_csum = tg3_get_rx_csum,
10001 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10002 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10003 .set_sg = ethtool_op_set_sg,
1da177e4 10004 .set_tso = tg3_set_tso,
4cafd3f5 10005 .self_test = tg3_self_test,
1da177e4 10006 .get_strings = tg3_get_strings,
4009a93d 10007 .phys_id = tg3_phys_id,
1da177e4 10008 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10009 .get_coalesce = tg3_get_coalesce,
d244c892 10010 .set_coalesce = tg3_set_coalesce,
b9f2c044 10011 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10012};
10013
10014static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10015{
1b27777a 10016 u32 cursize, val, magic;
1da177e4
LT		 10017
10018 tp->nvram_size = EEPROM_CHIP_SIZE;
10019
1820180b 10020 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 10021 return;
10022
b16250e3
MC		 10023 if ((magic != TG3_EEPROM_MAGIC) &&
10024 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10025 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10026 return;
10027
10028 /*
10029 * Size the chip by reading offsets at increasing powers of two.
10030 * When we encounter our validation signature, we know the addressing
10031 * has wrapped around, and thus have our chip size.
10032 */
1b27777a 10033 cursize = 0x10;
1da177e4
LT		 10034
10035 while (cursize < tp->nvram_size) {
1820180b 10036 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 10037 return;
10038
1820180b 10039 if (val == magic)
1da177e4
LT		 10040 break;
10041
10042 cursize <<= 1;
10043 }
10044
10045 tp->nvram_size = cursize;
10046}
6aa20a22 10047
1da177e4
LT		 10048static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10049{
10050 u32 val;
10051
1820180b 10052 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 10053 return;
10054
10055 /* Selfboot format */
1820180b 10056 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10057 tg3_get_eeprom_size(tp);
10058 return;
10059 }
10060
1da177e4
LT		 10061 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10062 if (val != 0) {
10063 tp->nvram_size = (val >> 16) * 1024;
10064 return;
10065 }
10066 }
fd1122a2 10067 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10068}
10069
10070static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10071{
10072 u32 nvcfg1;
10073
10074 nvcfg1 = tr32(NVRAM_CFG1);
10075 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10076 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10077 }
10078 else {
10079 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10080 tw32(NVRAM_CFG1, nvcfg1);
10081 }
10082
4c987487 10083 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10084 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 10085 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10086 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10087 tp->nvram_jedecnum = JEDEC_ATMEL;
10088 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10089 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10090 break;
10091 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10092 tp->nvram_jedecnum = JEDEC_ATMEL;
10093 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10094 break;
10095 case FLASH_VENDOR_ATMEL_EEPROM:
10096 tp->nvram_jedecnum = JEDEC_ATMEL;
10097 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10098 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10099 break;
10100 case FLASH_VENDOR_ST:
10101 tp->nvram_jedecnum = JEDEC_ST;
10102 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10103 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10104 break;
10105 case FLASH_VENDOR_SAIFUN:
10106 tp->nvram_jedecnum = JEDEC_SAIFUN;
10107 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10108 break;
10109 case FLASH_VENDOR_SST_SMALL:
10110 case FLASH_VENDOR_SST_LARGE:
10111 tp->nvram_jedecnum = JEDEC_SST;
10112 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10113 break;
10114 }
10115 }
10116 else {
10117 tp->nvram_jedecnum = JEDEC_ATMEL;
10118 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10119 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10120 }
10121}
10122
361b4ac2
MC		 10123static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10124{
10125 u32 nvcfg1;
10126
10127 nvcfg1 = tr32(NVRAM_CFG1);
10128
e6af301b
MC		 10129 /* NVRAM protection for TPM */
10130 if (nvcfg1 & (1 << 27))
10131 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10132
361b4ac2
MC		 10133 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10134 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10135 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10136 tp->nvram_jedecnum = JEDEC_ATMEL;
10137 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10138 break;
10139 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10140 tp->nvram_jedecnum = JEDEC_ATMEL;
10141 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10142 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10143 break;
10144 case FLASH_5752VENDOR_ST_M45PE10:
10145 case FLASH_5752VENDOR_ST_M45PE20:
10146 case FLASH_5752VENDOR_ST_M45PE40:
10147 tp->nvram_jedecnum = JEDEC_ST;
10148 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10149 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10150 break;
10151 }
10152
10153 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10154 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10155 case FLASH_5752PAGE_SIZE_256:
10156 tp->nvram_pagesize = 256;
10157 break;
10158 case FLASH_5752PAGE_SIZE_512:
10159 tp->nvram_pagesize = 512;
10160 break;
10161 case FLASH_5752PAGE_SIZE_1K:
10162 tp->nvram_pagesize = 1024;
10163 break;
10164 case FLASH_5752PAGE_SIZE_2K:
10165 tp->nvram_pagesize = 2048;
10166 break;
10167 case FLASH_5752PAGE_SIZE_4K:
10168 tp->nvram_pagesize = 4096;
10169 break;
10170 case FLASH_5752PAGE_SIZE_264:
10171 tp->nvram_pagesize = 264;
10172 break;
10173 }
10174 }
10175 else {
10176 /* For eeprom, set pagesize to maximum eeprom size */
10177 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10178
10179 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10180 tw32(NVRAM_CFG1, nvcfg1);
10181 }
10182}
10183
d3c7b886
MC		 10184static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10185{
989a9d23 10186 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10187
10188 nvcfg1 = tr32(NVRAM_CFG1);
10189
10190 /* NVRAM protection for TPM */
989a9d23 10191 if (nvcfg1 & (1 << 27)) {
d3c7b886 10192 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10193 protect = 1;
10194 }
d3c7b886 10195
989a9d23
MC		 10196 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10197 switch (nvcfg1) {
d3c7b886
MC		 10198 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10199 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10200 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 10201 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 10202 tp->nvram_jedecnum = JEDEC_ATMEL;
10203 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10204 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10205 tp->nvram_pagesize = 264;
70b65a2d
MC		 10206 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10207 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
fd1122a2
MC		 10208 tp->nvram_size = (protect ? 0x3e200 :
10209 TG3_NVRAM_SIZE_512KB);
989a9d23 10210 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
fd1122a2
MC		 10211 tp->nvram_size = (protect ? 0x1f200 :
10212 TG3_NVRAM_SIZE_256KB);
989a9d23 10213 else
fd1122a2
MC		 10214 tp->nvram_size = (protect ? 0x1f200 :
10215 TG3_NVRAM_SIZE_128KB);
d3c7b886
MC		 10216 break;
10217 case FLASH_5752VENDOR_ST_M45PE10:
10218 case FLASH_5752VENDOR_ST_M45PE20:
10219 case FLASH_5752VENDOR_ST_M45PE40:
10220 tp->nvram_jedecnum = JEDEC_ST;
10221 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10222 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10223 tp->nvram_pagesize = 256;
989a9d23 10224 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
fd1122a2
MC		 10225 tp->nvram_size = (protect ?
10226 TG3_NVRAM_SIZE_64KB :
10227 TG3_NVRAM_SIZE_128KB);
989a9d23 10228 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
fd1122a2
MC		 10229 tp->nvram_size = (protect ?
10230 TG3_NVRAM_SIZE_64KB :
10231 TG3_NVRAM_SIZE_256KB);
989a9d23 10232 else
fd1122a2
MC		 10233 tp->nvram_size = (protect ?
10234 TG3_NVRAM_SIZE_128KB :
10235 TG3_NVRAM_SIZE_512KB);
d3c7b886
MC		 10236 break;
10237 }
10238}
10239
1b27777a
MC		 10240static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10241{
10242 u32 nvcfg1;
10243
10244 nvcfg1 = tr32(NVRAM_CFG1);
10245
10246 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10247 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10248 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10249 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10250 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10251 tp->nvram_jedecnum = JEDEC_ATMEL;
10252 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10253 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10254
10255 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10256 tw32(NVRAM_CFG1, nvcfg1);
10257 break;
10258 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10259 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10260 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10261 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10262 tp->nvram_jedecnum = JEDEC_ATMEL;
10263 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10264 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10265 tp->nvram_pagesize = 264;
10266 break;
10267 case FLASH_5752VENDOR_ST_M45PE10:
10268 case FLASH_5752VENDOR_ST_M45PE20:
10269 case FLASH_5752VENDOR_ST_M45PE40:
10270 tp->nvram_jedecnum = JEDEC_ST;
10271 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10272 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10273 tp->nvram_pagesize = 256;
10274 break;
10275 }
10276}
10277
6b91fa02
MC		 10278static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10279{
10280 u32 nvcfg1, protect = 0;
10281
10282 nvcfg1 = tr32(NVRAM_CFG1);
10283
10284 /* NVRAM protection for TPM */
10285 if (nvcfg1 & (1 << 27)) {
10286 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10287 protect = 1;
10288 }
10289
10290 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10291 switch (nvcfg1) {
10292 case FLASH_5761VENDOR_ATMEL_ADB021D:
10293 case FLASH_5761VENDOR_ATMEL_ADB041D:
10294 case FLASH_5761VENDOR_ATMEL_ADB081D:
10295 case FLASH_5761VENDOR_ATMEL_ADB161D:
10296 case FLASH_5761VENDOR_ATMEL_MDB021D:
10297 case FLASH_5761VENDOR_ATMEL_MDB041D:
10298 case FLASH_5761VENDOR_ATMEL_MDB081D:
10299 case FLASH_5761VENDOR_ATMEL_MDB161D:
10300 tp->nvram_jedecnum = JEDEC_ATMEL;
10301 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10302 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10303 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10304 tp->nvram_pagesize = 256;
10305 break;
10306 case FLASH_5761VENDOR_ST_A_M45PE20:
10307 case FLASH_5761VENDOR_ST_A_M45PE40:
10308 case FLASH_5761VENDOR_ST_A_M45PE80:
10309 case FLASH_5761VENDOR_ST_A_M45PE16:
10310 case FLASH_5761VENDOR_ST_M_M45PE20:
10311 case FLASH_5761VENDOR_ST_M_M45PE40:
10312 case FLASH_5761VENDOR_ST_M_M45PE80:
10313 case FLASH_5761VENDOR_ST_M_M45PE16:
10314 tp->nvram_jedecnum = JEDEC_ST;
10315 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10316 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10317 tp->nvram_pagesize = 256;
10318 break;
10319 }
10320
10321 if (protect) {
10322 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10323 } else {
10324 switch (nvcfg1) {
10325 case FLASH_5761VENDOR_ATMEL_ADB161D:
10326 case FLASH_5761VENDOR_ATMEL_MDB161D:
10327 case FLASH_5761VENDOR_ST_A_M45PE16:
10328 case FLASH_5761VENDOR_ST_M_M45PE16:
fd1122a2 10329 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
6b91fa02
MC		 10330 break;
10331 case FLASH_5761VENDOR_ATMEL_ADB081D:
10332 case FLASH_5761VENDOR_ATMEL_MDB081D:
10333 case FLASH_5761VENDOR_ST_A_M45PE80:
10334 case FLASH_5761VENDOR_ST_M_M45PE80:
fd1122a2 10335 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
6b91fa02
MC		 10336 break;
10337 case FLASH_5761VENDOR_ATMEL_ADB041D:
10338 case FLASH_5761VENDOR_ATMEL_MDB041D:
10339 case FLASH_5761VENDOR_ST_A_M45PE40:
10340 case FLASH_5761VENDOR_ST_M_M45PE40:
fd1122a2 10341 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
6b91fa02
MC		 10342 break;
10343 case FLASH_5761VENDOR_ATMEL_ADB021D:
10344 case FLASH_5761VENDOR_ATMEL_MDB021D:
10345 case FLASH_5761VENDOR_ST_A_M45PE20:
10346 case FLASH_5761VENDOR_ST_M_M45PE20:
fd1122a2 10347 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
6b91fa02
MC		 10348 break;
10349 }
10350 }
10351}
10352
b5d3772c
MC		 10353static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10354{
10355 tp->nvram_jedecnum = JEDEC_ATMEL;
10356 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10357 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10358}
10359
321d32a0
MC		 10360static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10361{
10362 u32 nvcfg1;
10363
10364 nvcfg1 = tr32(NVRAM_CFG1);
10365
10366 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10367 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10368 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10369 tp->nvram_jedecnum = JEDEC_ATMEL;
10370 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10371 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10372
10373 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10374 tw32(NVRAM_CFG1, nvcfg1);
10375 return;
10376 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10377 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10378 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10379 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10380 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10381 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10382 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10383 tp->nvram_jedecnum = JEDEC_ATMEL;
10384 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10385 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10386
10387 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10388 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10389 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10390 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10391 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10392 break;
10393 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10394 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10395 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10396 break;
10397 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10398 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10399 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10400 break;
10401 }
10402 break;
10403 case FLASH_5752VENDOR_ST_M45PE10:
10404 case FLASH_5752VENDOR_ST_M45PE20:
10405 case FLASH_5752VENDOR_ST_M45PE40:
10406 tp->nvram_jedecnum = JEDEC_ST;
10407 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10408 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10409
10410 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10411 case FLASH_5752VENDOR_ST_M45PE10:
10412 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10413 break;
10414 case FLASH_5752VENDOR_ST_M45PE20:
10415 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10416 break;
10417 case FLASH_5752VENDOR_ST_M45PE40:
10418 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10419 break;
10420 }
10421 break;
10422 default:
10423 return;
10424 }
10425
10426 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10427 case FLASH_5752PAGE_SIZE_256:
10428 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10429 tp->nvram_pagesize = 256;
10430 break;
10431 case FLASH_5752PAGE_SIZE_512:
10432 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10433 tp->nvram_pagesize = 512;
10434 break;
10435 case FLASH_5752PAGE_SIZE_1K:
10436 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10437 tp->nvram_pagesize = 1024;
10438 break;
10439 case FLASH_5752PAGE_SIZE_2K:
10440 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10441 tp->nvram_pagesize = 2048;
10442 break;
10443 case FLASH_5752PAGE_SIZE_4K:
10444 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10445 tp->nvram_pagesize = 4096;
10446 break;
10447 case FLASH_5752PAGE_SIZE_264:
10448 tp->nvram_pagesize = 264;
10449 break;
10450 case FLASH_5752PAGE_SIZE_528:
10451 tp->nvram_pagesize = 528;
10452 break;
10453 }
10454}
10455
1da177e4
LT		 10456/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10457static void __devinit tg3_nvram_init(struct tg3 *tp)
10458{
1da177e4
LT		 10459 tw32_f(GRC_EEPROM_ADDR,
10460 (EEPROM_ADDR_FSM_RESET |
10461 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10462 EEPROM_ADDR_CLKPERD_SHIFT)));
10463
9d57f01c 10464 msleep(1);
1da177e4
LT		 10465
10466 /* Enable seeprom accesses. */
10467 tw32_f(GRC_LOCAL_CTRL,
10468 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10469 udelay(100);
10470
10471 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10472 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10473 tp->tg3_flags |= TG3_FLAG_NVRAM;
10474
ec41c7df
MC		 10475 if (tg3_nvram_lock(tp)) {
10476 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10477 "tg3_nvram_init failed.\n", tp->dev->name);
10478 return;
10479 }
e6af301b 10480 tg3_enable_nvram_access(tp);
1da177e4 10481
989a9d23
MC		 10482 tp->nvram_size = 0;
10483
361b4ac2
MC		 10484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10485 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10486 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10487 tg3_get_5755_nvram_info(tp);
d30cdd28 10488 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10489 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10490 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10491 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10492 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10493 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10494 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10495 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10496 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10497 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10498 else
10499 tg3_get_nvram_info(tp);
10500
989a9d23
MC		 10501 if (tp->nvram_size == 0)
10502 tg3_get_nvram_size(tp);
1da177e4 10503
e6af301b 10504 tg3_disable_nvram_access(tp);
381291b7 10505 tg3_nvram_unlock(tp);
1da177e4
LT		 10506
10507 } else {
10508 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10509
10510 tg3_get_eeprom_size(tp);
10511 }
10512}
10513
10514static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10515 u32 offset, u32 *val)
10516{
10517 u32 tmp;
10518 int i;
10519
10520 if (offset > EEPROM_ADDR_ADDR_MASK ||
10521 (offset % 4) != 0)
10522 return -EINVAL;
10523
10524 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10525 EEPROM_ADDR_DEVID_MASK |
10526 EEPROM_ADDR_READ);
10527 tw32(GRC_EEPROM_ADDR,
10528 tmp |
10529 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10530 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10531 EEPROM_ADDR_ADDR_MASK) |
10532 EEPROM_ADDR_READ | EEPROM_ADDR_START);
10533
9d57f01c 10534 for (i = 0; i < 1000; i++) {
1da177e4
LT		 10535 tmp = tr32(GRC_EEPROM_ADDR);
10536
10537 if (tmp & EEPROM_ADDR_COMPLETE)
10538 break;
9d57f01c 10539 msleep(1);
1da177e4
LT		 10540 }
10541 if (!(tmp & EEPROM_ADDR_COMPLETE))
10542 return -EBUSY;
10543
10544 *val = tr32(GRC_EEPROM_DATA);
10545 return 0;
10546}
10547
10548#define NVRAM_CMD_TIMEOUT 10000
10549
10550static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10551{
10552 int i;
10553
10554 tw32(NVRAM_CMD, nvram_cmd);
10555 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10556 udelay(10);
10557 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10558 udelay(10);
10559 break;
10560 }
10561 }
10562 if (i == NVRAM_CMD_TIMEOUT) {
10563 return -EBUSY;
10564 }
10565 return 0;
10566}
10567
1820180b
MC		 10568static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10569{
10570 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10571 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10572 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 10573 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
1820180b
MC		 10574 (tp->nvram_jedecnum == JEDEC_ATMEL))
10575
10576 addr = ((addr / tp->nvram_pagesize) <<
10577 ATMEL_AT45DB0X1B_PAGE_POS) +
10578 (addr % tp->nvram_pagesize);
10579
10580 return addr;
10581}
10582
c4e6575c
MC		 10583static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10584{
10585 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10586 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10587 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
6b91fa02 10588 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
c4e6575c
MC		 10589 (tp->nvram_jedecnum == JEDEC_ATMEL))
10590
10591 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10592 tp->nvram_pagesize) +
10593 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10594
10595 return addr;
10596}
10597
1da177e4
LT		 10598static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10599{
10600 int ret;
10601
1da177e4
LT		 10602 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10603 return tg3_nvram_read_using_eeprom(tp, offset, val);
10604
1820180b 10605 offset = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10606
10607 if (offset > NVRAM_ADDR_MSK)
10608 return -EINVAL;
10609
ec41c7df
MC		 10610 ret = tg3_nvram_lock(tp);
10611 if (ret)
10612 return ret;
1da177e4 10613
e6af301b 10614 tg3_enable_nvram_access(tp);
1da177e4
LT		 10615
10616 tw32(NVRAM_ADDR, offset);
10617 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10618 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10619
10620 if (ret == 0)
10621 *val = swab32(tr32(NVRAM_RDDATA));
10622
e6af301b 10623 tg3_disable_nvram_access(tp);
1da177e4 10624
381291b7
MC		 10625 tg3_nvram_unlock(tp);
10626
1da177e4
LT		 10627 return ret;
10628}
10629
b9fc7dc5
AV		 10630static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10631{
10632 u32 v;
10633 int res = tg3_nvram_read(tp, offset, &v);
10634 if (!res)
10635 *val = cpu_to_le32(v);
10636 return res;
10637}
10638
1820180b
MC		 10639static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10640{
10641 int err;
10642 u32 tmp;
10643
10644 err = tg3_nvram_read(tp, offset, &tmp);
10645 *val = swab32(tmp);
10646 return err;
10647}
10648
1da177e4
LT		 10649static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10650 u32 offset, u32 len, u8 *buf)
10651{
10652 int i, j, rc = 0;
10653 u32 val;
10654
10655 for (i = 0; i < len; i += 4) {
b9fc7dc5
AV		 10656 u32 addr;
10657 __le32 data;
1da177e4
LT		 10658
10659 addr = offset + i;
10660
10661 memcpy(&data, buf + i, 4);
10662
b9fc7dc5 10663 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
1da177e4
LT		 10664
10665 val = tr32(GRC_EEPROM_ADDR);
10666 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10667
10668 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10669 EEPROM_ADDR_READ);
10670 tw32(GRC_EEPROM_ADDR, val |
10671 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10672 (addr & EEPROM_ADDR_ADDR_MASK) |
10673 EEPROM_ADDR_START |
10674 EEPROM_ADDR_WRITE);
6aa20a22 10675
9d57f01c 10676 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10677 val = tr32(GRC_EEPROM_ADDR);
10678
10679 if (val & EEPROM_ADDR_COMPLETE)
10680 break;
9d57f01c 10681 msleep(1);
1da177e4
LT		 10682 }
10683 if (!(val & EEPROM_ADDR_COMPLETE)) {
10684 rc = -EBUSY;
10685 break;
10686 }
10687 }
10688
10689 return rc;
10690}
10691
10692/* offset and length are dword aligned */
10693static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10694 u8 *buf)
10695{
10696 int ret = 0;
10697 u32 pagesize = tp->nvram_pagesize;
10698 u32 pagemask = pagesize - 1;
10699 u32 nvram_cmd;
10700 u8 *tmp;
10701
10702 tmp = kmalloc(pagesize, GFP_KERNEL);
10703 if (tmp == NULL)
10704 return -ENOMEM;
10705
10706 while (len) {
10707 int j;
e6af301b 10708 u32 phy_addr, page_off, size;
1da177e4
LT		 10709
10710 phy_addr = offset & ~pagemask;
6aa20a22 10711
1da177e4 10712 for (j = 0; j < pagesize; j += 4) {
286e310f 10713 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
b9fc7dc5 10714 (__le32 *) (tmp + j))))
1da177e4
LT		 10715 break;
10716 }
10717 if (ret)
10718 break;
10719
10720 page_off = offset & pagemask;
10721 size = pagesize;
10722 if (len < size)
10723 size = len;
10724
10725 len -= size;
10726
10727 memcpy(tmp + page_off, buf, size);
10728
10729 offset = offset + (pagesize - page_off);
10730
e6af301b 10731 tg3_enable_nvram_access(tp);
1da177e4
LT		 10732
10733 /*
10734 * Before we can erase the flash page, we need
10735 * to issue a special "write enable" command.
10736 */
10737 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10738
10739 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10740 break;
10741
10742 /* Erase the target page */
10743 tw32(NVRAM_ADDR, phy_addr);
10744
10745 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10746 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10747
10748 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10749 break;
10750
10751 /* Issue another write enable to start the write. */
10752 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10753
10754 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10755 break;
10756
10757 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10758 __be32 data;
1da177e4 10759
b9fc7dc5
AV		 10760 data = *((__be32 *) (tmp + j));
10761 /* swab32(le32_to_cpu(data)), actually */
10762 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10763
10764 tw32(NVRAM_ADDR, phy_addr + j);
10765
10766 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10767 NVRAM_CMD_WR;
10768
10769 if (j == 0)
10770 nvram_cmd |= NVRAM_CMD_FIRST;
10771 else if (j == (pagesize - 4))
10772 nvram_cmd |= NVRAM_CMD_LAST;
10773
10774 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10775 break;
10776 }
10777 if (ret)
10778 break;
10779 }
10780
10781 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10782 tg3_nvram_exec_cmd(tp, nvram_cmd);
10783
10784 kfree(tmp);
10785
10786 return ret;
10787}
10788
10789/* offset and length are dword aligned */
10790static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10791 u8 *buf)
10792{
10793 int i, ret = 0;
10794
10795 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10796 u32 page_off, phy_addr, nvram_cmd;
10797 __be32 data;
1da177e4
LT		 10798
10799 memcpy(&data, buf + i, 4);
b9fc7dc5 10800 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10801
10802 page_off = offset % tp->nvram_pagesize;
10803
1820180b 10804 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10805
10806 tw32(NVRAM_ADDR, phy_addr);
10807
10808 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10809
10810 if ((page_off == 0) || (i == 0))
10811 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10812 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10813 nvram_cmd |= NVRAM_CMD_LAST;
10814
10815 if (i == (len - 4))
10816 nvram_cmd |= NVRAM_CMD_LAST;
10817
321d32a0
MC		 10818 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10819 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10820 (tp->nvram_jedecnum == JEDEC_ST) &&
10821 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10822
10823 if ((ret = tg3_nvram_exec_cmd(tp,
10824 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10825 NVRAM_CMD_DONE)))
10826
10827 break;
10828 }
10829 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10830 /* We always do complete word writes to eeprom. */
10831 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10832 }
10833
10834 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10835 break;
10836 }
10837 return ret;
10838}
10839
10840/* offset and length are dword aligned */
10841static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10842{
10843 int ret;
10844
1da177e4 10845 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10846 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10847 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10848 udelay(40);
10849 }
10850
10851 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10852 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10853 }
10854 else {
10855 u32 grc_mode;
10856
ec41c7df
MC		 10857 ret = tg3_nvram_lock(tp);
10858 if (ret)
10859 return ret;
1da177e4 10860
e6af301b
MC		 10861 tg3_enable_nvram_access(tp);
10862 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10863 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10864 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10865
10866 grc_mode = tr32(GRC_MODE);
10867 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10868
10869 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10870 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10871
10872 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10873 buf);
10874 }
10875 else {
10876 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10877 buf);
10878 }
10879
10880 grc_mode = tr32(GRC_MODE);
10881 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10882
e6af301b 10883 tg3_disable_nvram_access(tp);
1da177e4
LT		 10884 tg3_nvram_unlock(tp);
10885 }
10886
10887 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10888 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10889 udelay(40);
10890 }
10891
10892 return ret;
10893}
10894
10895struct subsys_tbl_ent {
10896 u16 subsys_vendor, subsys_devid;
10897 u32 phy_id;
10898};
10899
10900static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10901 /* Broadcom boards. */
10902 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10903 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10904 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10905 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10906 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10907 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10908 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10909 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10910 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10911 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10912 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10913
10914 /* 3com boards. */
10915 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10916 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10917 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10918 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10919 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10920
10921 /* DELL boards. */
10922 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10923 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10924 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10925 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10926
10927 /* Compaq boards. */
10928 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10929 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10930 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10931 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10932 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10933
10934 /* IBM boards. */
10935 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10936};
10937
10938static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10939{
10940 int i;
10941
10942 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10943 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10944 tp->pdev->subsystem_vendor) &&
10945 (subsys_id_to_phy_id[i].subsys_devid ==
10946 tp->pdev->subsystem_device))
10947 return &subsys_id_to_phy_id[i];
10948 }
10949 return NULL;
10950}
10951
7d0c41ef 10952static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10953{
1da177e4 10954 u32 val;
caf636c7
MC		 10955 u16 pmcsr;
10956
10957 /* On some early chips the SRAM cannot be accessed in D3hot state,
10958 * so need make sure we're in D0.
10959 */
10960 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10961 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10962 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10963 msleep(1);
7d0c41ef
MC		 10964
10965 /* Make sure register accesses (indirect or otherwise)
10966 * will function correctly.
10967 */
10968 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10969 tp->misc_host_ctrl);
1da177e4 10970
f49639e6
DM		 10971 /* The memory arbiter has to be enabled in order for SRAM accesses
10972 * to succeed. Normally on powerup the tg3 chip firmware will make
10973 * sure it is enabled, but other entities such as system netboot
10974 * code might disable it.
10975 */
10976 val = tr32(MEMARB_MODE);
10977 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10978
1da177e4 10979 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 10980 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10981
a85feb8c
GZ		 10982 /* Assume an onboard device and WOL capable by default. */
10983 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 10984
b5d3772c 10985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 10986 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 10987 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10988 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10989 }
0527ba35
MC		 10990 val = tr32(VCPU_CFGSHDW);
10991 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 10992 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 10993 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 10994 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 10995 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 10996 goto done;
b5d3772c
MC		 10997 }
10998
1da177e4
LT		 10999 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11000 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11001 u32 nic_cfg, led_cfg;
a9daf367 11002 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11003 int eeprom_phy_serdes = 0;
1da177e4
LT		 11004
11005 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11006 tp->nic_sram_data_cfg = nic_cfg;
11007
11008 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11009 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11010 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11011 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11012 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11013 (ver > 0) && (ver < 0x100))
11014 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11015
a9daf367
MC		 11016 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11017 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11018
1da177e4
LT		 11019 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11020 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11021 eeprom_phy_serdes = 1;
11022
11023 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11024 if (nic_phy_id != 0) {
11025 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11026 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11027
11028 eeprom_phy_id = (id1 >> 16) << 10;
11029 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11030 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11031 } else
11032 eeprom_phy_id = 0;
11033
7d0c41ef 11034 tp->phy_id = eeprom_phy_id;
747e8f8b 11035 if (eeprom_phy_serdes) {
a4e2b347 11036 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11037 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11038 else
11039 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11040 }
7d0c41ef 11041
cbf46853 11042 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11043 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11044 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11045 else
1da177e4
LT		 11046 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11047
11048 switch (led_cfg) {
11049 default:
11050 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11051 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11052 break;
11053
11054 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11055 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11056 break;
11057
11058 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11059 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11060
11061 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11062 * read on some older 5700/5701 bootcode.
11063 */
11064 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11065 ASIC_REV_5700 ||
11066 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11067 ASIC_REV_5701)
11068 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11069
1da177e4
LT		 11070 break;
11071
11072 case SHASTA_EXT_LED_SHARED:
11073 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11074 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11075 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11076 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11077 LED_CTRL_MODE_PHY_2);
11078 break;
11079
11080 case SHASTA_EXT_LED_MAC:
11081 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11082 break;
11083
11084 case SHASTA_EXT_LED_COMBO:
11085 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11086 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11087 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11088 LED_CTRL_MODE_PHY_2);
11089 break;
11090
855e1111 11091 }
1da177e4
LT		 11092
11093 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11094 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11095 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11096 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11097
b2a5c19c
MC		 11098 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11099 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11100
9d26e213 11101 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11102 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11103 if ((tp->pdev->subsystem_vendor ==
11104 PCI_VENDOR_ID_ARIMA) &&
11105 (tp->pdev->subsystem_device == 0x205a ||
11106 tp->pdev->subsystem_device == 0x2063))
11107 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11108 } else {
f49639e6 11109 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11110 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11111 }
1da177e4
LT		 11112
11113 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11114 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11115 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11116 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11117 }
b2b98d4a
MC		 11118
11119 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11120 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11121 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11122
a85feb8c
GZ		 11123 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11124 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11125 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11126
12dac075 11127 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11128 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11129 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11130
1da177e4
LT		 11131 if (cfg2 & (1 << 17))
11132 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11133
11134 /* serdes signal pre-emphasis in register 0x590 set by */
11135 /* bootcode if bit 18 is set */
11136 if (cfg2 & (1 << 18))
11137 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11138
321d32a0
MC		 11139 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11140 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11141 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11142 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11143
8ed5d97e
MC		 11144 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11145 u32 cfg3;
11146
11147 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11148 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11149 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11150 }
a9daf367
MC		 11151
11152 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11153 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11154 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11155 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11156 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11157 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11158 }
05ac4cb7
MC		 11159done:
11160 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11161 device_set_wakeup_enable(&tp->pdev->dev,
11162 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11163}
11164
b2a5c19c
MC		 11165static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11166{
11167 int i;
11168 u32 val;
11169
11170 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11171 tw32(OTP_CTRL, cmd);
11172
11173 /* Wait for up to 1 ms for command to execute. */
11174 for (i = 0; i < 100; i++) {
11175 val = tr32(OTP_STATUS);
11176 if (val & OTP_STATUS_CMD_DONE)
11177 break;
11178 udelay(10);
11179 }
11180
11181 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11182}
11183
11184/* Read the gphy configuration from the OTP region of the chip. The gphy
11185 * configuration is a 32-bit value that straddles the alignment boundary.
11186 * We do two 32-bit reads and then shift and merge the results.
11187 */
11188static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11189{
11190 u32 bhalf_otp, thalf_otp;
11191
11192 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11193
11194 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11195 return 0;
11196
11197 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11198
11199 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11200 return 0;
11201
11202 thalf_otp = tr32(OTP_READ_DATA);
11203
11204 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11205
11206 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11207 return 0;
11208
11209 bhalf_otp = tr32(OTP_READ_DATA);
11210
11211 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11212}
11213
7d0c41ef
MC		 11214static int __devinit tg3_phy_probe(struct tg3 *tp)
11215{
11216 u32 hw_phy_id_1, hw_phy_id_2;
11217 u32 hw_phy_id, hw_phy_id_masked;
11218 int err;
1da177e4 11219
b02fd9e3
MC		 11220 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11221 return tg3_phy_init(tp);
11222
1da177e4
LT		 11223 /* Reading the PHY ID register can conflict with ASF
11224 * firwmare access to the PHY hardware.
11225 */
11226 err = 0;
0d3031d9
MC		 11227 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11228 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11229 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11230 } else {
11231 /* Now read the physical PHY_ID from the chip and verify
11232 * that it is sane. If it doesn't look good, we fall back
11233 * to either the hard-coded table based PHY_ID and failing
11234 * that the value found in the eeprom area.
11235 */
11236 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11237 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11238
11239 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11240 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11241 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11242
11243 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11244 }
11245
11246 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11247 tp->phy_id = hw_phy_id;
11248 if (hw_phy_id_masked == PHY_ID_BCM8002)
11249 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11250 else
11251 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11252 } else {
7d0c41ef
MC		 11253 if (tp->phy_id != PHY_ID_INVALID) {
11254 /* Do nothing, phy ID already set up in
11255 * tg3_get_eeprom_hw_cfg().
11256 */
1da177e4
LT		 11257 } else {
11258 struct subsys_tbl_ent *p;
11259
11260 /* No eeprom signature? Try the hardcoded
11261 * subsys device table.
11262 */
11263 p = lookup_by_subsys(tp);
11264 if (!p)
11265 return -ENODEV;
11266
11267 tp->phy_id = p->phy_id;
11268 if (!tp->phy_id ||
11269 tp->phy_id == PHY_ID_BCM8002)
11270 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11271 }
11272 }
11273
747e8f8b 11274 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11275 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11276 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11277 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11278
11279 tg3_readphy(tp, MII_BMSR, &bmsr);
11280 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11281 (bmsr & BMSR_LSTATUS))
11282 goto skip_phy_reset;
6aa20a22 11283
1da177e4
LT		 11284 err = tg3_phy_reset(tp);
11285 if (err)
11286 return err;
11287
11288 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11289 ADVERTISE_100HALF | ADVERTISE_100FULL |
11290 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11291 tg3_ctrl = 0;
11292 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11293 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11294 MII_TG3_CTRL_ADV_1000_FULL);
11295 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11296 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11297 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11298 MII_TG3_CTRL_ENABLE_AS_MASTER);
11299 }
11300
3600d918
MC		 11301 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11302 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11303 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11304 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11305 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11306
11307 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11308 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11309
11310 tg3_writephy(tp, MII_BMCR,
11311 BMCR_ANENABLE | BMCR_ANRESTART);
11312 }
11313 tg3_phy_set_wirespeed(tp);
11314
11315 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11316 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11317 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11318 }
11319
11320skip_phy_reset:
11321 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11322 err = tg3_init_5401phy_dsp(tp);
11323 if (err)
11324 return err;
11325 }
11326
11327 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11328 err = tg3_init_5401phy_dsp(tp);
11329 }
11330
747e8f8b 11331 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11332 tp->link_config.advertising =
11333 (ADVERTISED_1000baseT_Half |
11334 ADVERTISED_1000baseT_Full |
11335 ADVERTISED_Autoneg |
11336 ADVERTISED_FIBRE);
11337 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11338 tp->link_config.advertising &=
11339 ~(ADVERTISED_1000baseT_Half |
11340 ADVERTISED_1000baseT_Full);
11341
11342 return err;
11343}
11344
11345static void __devinit tg3_read_partno(struct tg3 *tp)
11346{
11347 unsigned char vpd_data[256];
af2c6a4a 11348 unsigned int i;
1b27777a 11349 u32 magic;
1da177e4 11350
1820180b 11351 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 11352 goto out_not_found;
1da177e4 11353
1820180b 11354 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11355 for (i = 0; i < 256; i += 4) {
11356 u32 tmp;
1da177e4 11357
1b27777a
MC		 11358 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11359 goto out_not_found;
11360
11361 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11362 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11363 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11364 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11365 }
11366 } else {
11367 int vpd_cap;
11368
11369 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11370 for (i = 0; i < 256; i += 4) {
11371 u32 tmp, j = 0;
b9fc7dc5 11372 __le32 v;
1b27777a
MC		 11373 u16 tmp16;
11374
11375 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11376 i);
11377 while (j++ < 100) {
11378 pci_read_config_word(tp->pdev, vpd_cap +
11379 PCI_VPD_ADDR, &tmp16);
11380 if (tmp16 & 0x8000)
11381 break;
11382 msleep(1);
11383 }
f49639e6
DM		 11384 if (!(tmp16 & 0x8000))
11385 goto out_not_found;
11386
1b27777a
MC		 11387 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11388 &tmp);
b9fc7dc5
AV		 11389 v = cpu_to_le32(tmp);
11390 memcpy(&vpd_data[i], &v, 4);
1b27777a 11391 }
1da177e4
LT		 11392 }
11393
11394 /* Now parse and find the part number. */
af2c6a4a 11395 for (i = 0; i < 254; ) {
1da177e4 11396 unsigned char val = vpd_data[i];
af2c6a4a 11397 unsigned int block_end;
1da177e4
LT		 11398
11399 if (val == 0x82 || val == 0x91) {
11400 i = (i + 3 +
11401 (vpd_data[i + 1] +
11402 (vpd_data[i + 2] << 8)));
11403 continue;
11404 }
11405
11406 if (val != 0x90)
11407 goto out_not_found;
11408
11409 block_end = (i + 3 +
11410 (vpd_data[i + 1] +
11411 (vpd_data[i + 2] << 8)));
11412 i += 3;
af2c6a4a
MC		 11413
11414 if (block_end > 256)
11415 goto out_not_found;
11416
11417 while (i < (block_end - 2)) {
1da177e4
LT		 11418 if (vpd_data[i + 0] == 'P' &&
11419 vpd_data[i + 1] == 'N') {
11420 int partno_len = vpd_data[i + 2];
11421
af2c6a4a
MC		 11422 i += 3;
11423 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11424 goto out_not_found;
11425
11426 memcpy(tp->board_part_number,
af2c6a4a 11427 &vpd_data[i], partno_len);
1da177e4
LT		 11428
11429 /* Success. */
11430 return;
11431 }
af2c6a4a 11432 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11433 }
11434
11435 /* Part number not found. */
11436 goto out_not_found;
11437 }
11438
11439out_not_found:
b5d3772c
MC		 11440 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11441 strcpy(tp->board_part_number, "BCM95906");
11442 else
11443 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11444}
11445
9c8a620e
MC		 11446static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11447{
11448 u32 val;
11449
11450 if (tg3_nvram_read_swab(tp, offset, &val) ||
11451 (val & 0xfc000000) != 0x0c000000 ||
11452 tg3_nvram_read_swab(tp, offset + 4, &val) ||
11453 val != 0)
11454 return 0;
11455
11456 return 1;
11457}
11458
dfe00d7d
MC		 11459static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11460{
11461 u32 offset, major, minor, build;
11462
11463 tp->fw_ver[0] = 's';
11464 tp->fw_ver[1] = 'b';
11465 tp->fw_ver[2] = '\0';
11466
11467 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11468 return;
11469
11470 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11471 case TG3_EEPROM_SB_REVISION_0:
11472 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11473 break;
11474 case TG3_EEPROM_SB_REVISION_2:
11475 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11476 break;
11477 case TG3_EEPROM_SB_REVISION_3:
11478 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11479 break;
11480 default:
11481 return;
11482 }
11483
11484 if (tg3_nvram_read_swab(tp, offset, &val))
11485 return;
11486
11487 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11488 TG3_EEPROM_SB_EDH_BLD_SHFT;
11489 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11490 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11491 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11492
11493 if (minor > 99 || build > 26)
11494 return;
11495
11496 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11497
11498 if (build > 0) {
11499 tp->fw_ver[8] = 'a' + build - 1;
11500 tp->fw_ver[9] = '\0';
11501 }
11502}
11503
c4e6575c
MC		 11504static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11505{
11506 u32 val, offset, start;
9c8a620e
MC		 11507 u32 ver_offset;
11508 int i, bcnt;
c4e6575c
MC		 11509
11510 if (tg3_nvram_read_swab(tp, 0, &val))
11511 return;
11512
dfe00d7d
MC		 11513 if (val != TG3_EEPROM_MAGIC) {
11514 if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11515 tg3_read_sb_ver(tp, val);
11516
c4e6575c 11517 return;
dfe00d7d 11518 }
c4e6575c
MC		 11519
11520 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11521 tg3_nvram_read_swab(tp, 0x4, &start))
11522 return;
11523
11524 offset = tg3_nvram_logical_addr(tp, offset);
9c8a620e
MC		 11525
11526 if (!tg3_fw_img_is_valid(tp, offset) ||
11527 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
c4e6575c
MC		 11528 return;
11529
9c8a620e
MC		 11530 offset = offset + ver_offset - start;
11531 for (i = 0; i < 16; i += 4) {
b9fc7dc5
AV		 11532 __le32 v;
11533 if (tg3_nvram_read_le(tp, offset + i, &v))
9c8a620e
MC		 11534 return;
11535
b9fc7dc5 11536 memcpy(tp->fw_ver + i, &v, 4);
9c8a620e 11537 }
c4e6575c 11538
9c8a620e 11539 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
84af67fd 11540 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
9c8a620e
MC		 11541 return;
11542
11543 for (offset = TG3_NVM_DIR_START;
11544 offset < TG3_NVM_DIR_END;
11545 offset += TG3_NVM_DIRENT_SIZE) {
11546 if (tg3_nvram_read_swab(tp, offset, &val))
c4e6575c
MC		 11547 return;
11548
9c8a620e
MC		 11549 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11550 break;
11551 }
11552
11553 if (offset == TG3_NVM_DIR_END)
11554 return;
11555
11556 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11557 start = 0x08000000;
11558 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11559 return;
11560
11561 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11562 !tg3_fw_img_is_valid(tp, offset) ||
11563 tg3_nvram_read_swab(tp, offset + 8, &val))
11564 return;
11565
11566 offset += val - start;
11567
11568 bcnt = strlen(tp->fw_ver);
11569
11570 tp->fw_ver[bcnt++] = ',';
11571 tp->fw_ver[bcnt++] = ' ';
11572
11573 for (i = 0; i < 4; i++) {
b9fc7dc5
AV		 11574 __le32 v;
11575 if (tg3_nvram_read_le(tp, offset, &v))
c4e6575c
MC		 11576 return;
11577
b9fc7dc5 11578 offset += sizeof(v);
c4e6575c 11579
b9fc7dc5
AV		 11580 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11581 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
9c8a620e 11582 break;
c4e6575c 11583 }
9c8a620e 11584
b9fc7dc5
AV		 11585 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11586 bcnt += sizeof(v);
c4e6575c 11587 }
9c8a620e
MC		 11588
11589 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11590}
11591
7544b097
MC		 11592static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11593
1da177e4
LT		 11594static int __devinit tg3_get_invariants(struct tg3 *tp)
11595{
11596 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11597 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11598 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11599 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11600 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11601 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11602 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11603 { },
11604 };
11605 u32 misc_ctrl_reg;
1da177e4
LT		 11606 u32 pci_state_reg, grc_misc_cfg;
11607 u32 val;
11608 u16 pci_cmd;
5e7dfd0f 11609 int err;
1da177e4 11610
1da177e4
LT		 11611 /* Force memory write invalidate off. If we leave it on,
11612 * then on 5700_BX chips we have to enable a workaround.
11613 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11614 * to match the cacheline size. The Broadcom driver have this
11615 * workaround but turns MWI off all the times so never uses
11616 * it. This seems to suggest that the workaround is insufficient.
11617 */
11618 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11619 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11620 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11621
11622 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11623 * has the register indirect write enable bit set before
11624 * we try to access any of the MMIO registers. It is also
11625 * critical that the PCI-X hw workaround situation is decided
11626 * before that as well.
11627 */
11628 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11629 &misc_ctrl_reg);
11630
11631 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11632 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11634 u32 prod_id_asic_rev;
11635
11636 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11637 &prod_id_asic_rev);
321d32a0 11638 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11639 }
1da177e4 11640
ff645bec
MC		 11641 /* Wrong chip ID in 5752 A0. This code can be removed later
11642 * as A0 is not in production.
11643 */
11644 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11645 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11646
6892914f
MC		 11647 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11648 * we need to disable memory and use config. cycles
11649 * only to access all registers. The 5702/03 chips
11650 * can mistakenly decode the special cycles from the
11651 * ICH chipsets as memory write cycles, causing corruption
11652 * of register and memory space. Only certain ICH bridges
11653 * will drive special cycles with non-zero data during the
11654 * address phase which can fall within the 5703's address
11655 * range. This is not an ICH bug as the PCI spec allows
11656 * non-zero address during special cycles. However, only
11657 * these ICH bridges are known to drive non-zero addresses
11658 * during special cycles.
11659 *
11660 * Since special cycles do not cross PCI bridges, we only
11661 * enable this workaround if the 5703 is on the secondary
11662 * bus of these ICH bridges.
11663 */
11664 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11665 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11666 static struct tg3_dev_id {
11667 u32 vendor;
11668 u32 device;
11669 u32 rev;
11670 } ich_chipsets[] = {
11671 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11672 PCI_ANY_ID },
11673 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11674 PCI_ANY_ID },
11675 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11676 0xa },
11677 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11678 PCI_ANY_ID },
11679 { },
11680 };
11681 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11682 struct pci_dev *bridge = NULL;
11683
11684 while (pci_id->vendor != 0) {
11685 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11686 bridge);
11687 if (!bridge) {
11688 pci_id++;
11689 continue;
11690 }
11691 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11692 if (bridge->revision > pci_id->rev)
6892914f
MC		 11693 continue;
11694 }
11695 if (bridge->subordinate &&
11696 (bridge->subordinate->number ==
11697 tp->pdev->bus->number)) {
11698
11699 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11700 pci_dev_put(bridge);
11701 break;
11702 }
11703 }
11704 }
11705
41588ba1
MC		 11706 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11707 static struct tg3_dev_id {
11708 u32 vendor;
11709 u32 device;
11710 } bridge_chipsets[] = {
11711 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11712 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11713 { },
11714 };
11715 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11716 struct pci_dev *bridge = NULL;
11717
11718 while (pci_id->vendor != 0) {
11719 bridge = pci_get_device(pci_id->vendor,
11720 pci_id->device,
11721 bridge);
11722 if (!bridge) {
11723 pci_id++;
11724 continue;
11725 }
11726 if (bridge->subordinate &&
11727 (bridge->subordinate->number <=
11728 tp->pdev->bus->number) &&
11729 (bridge->subordinate->subordinate >=
11730 tp->pdev->bus->number)) {
11731 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11732 pci_dev_put(bridge);
11733 break;
11734 }
11735 }
11736 }
11737
4a29cc2e
MC		 11738 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11739 * DMA addresses > 40-bit. This bridge may have other additional
11740 * 57xx devices behind it in some 4-port NIC designs for example.
11741 * Any tg3 device found behind the bridge will also need the 40-bit
11742 * DMA workaround.
11743 */
a4e2b347
MC		 11744 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11745 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11746 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11747 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11748 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11749 }
4a29cc2e
MC		 11750 else {
11751 struct pci_dev *bridge = NULL;
11752
11753 do {
11754 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11755 PCI_DEVICE_ID_SERVERWORKS_EPB,
11756 bridge);
11757 if (bridge && bridge->subordinate &&
11758 (bridge->subordinate->number <=
11759 tp->pdev->bus->number) &&
11760 (bridge->subordinate->subordinate >=
11761 tp->pdev->bus->number)) {
11762 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11763 pci_dev_put(bridge);
11764 break;
11765 }
11766 } while (bridge);
11767 }
4cf78e4f 11768
1da177e4
LT		 11769 /* Initialize misc host control in PCI block. */
11770 tp->misc_host_ctrl |= (misc_ctrl_reg &
11771 MISC_HOST_CTRL_CHIPREV);
11772 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11773 tp->misc_host_ctrl);
11774
7544b097
MC		 11775 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11776 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11777 tp->pdev_peer = tg3_find_peer(tp);
11778
321d32a0
MC		 11779 /* Intentionally exclude ASIC_REV_5906 */
11780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11782 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11783 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 11784 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 11785 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11786 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11787
11788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11789 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 11790 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 11791 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 11792 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11793 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11794
1b440c56
JL		 11795 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11796 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11797 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11798
027455ad
MC		 11799 /* 5700 B0 chips do not support checksumming correctly due
11800 * to hardware bugs.
11801 */
11802 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11803 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11804 else {
11805 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11806 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11807 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11808 tp->dev->features |= NETIF_F_IPV6_CSUM;
11809 }
11810
5a6f3074 11811 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11812 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11813 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11814 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11815 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11816 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11817 tp->pdev_peer == tp->pdev))
11818 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11819
321d32a0 11820 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 11821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11822 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11823 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11824 } else {
7f62ad5d 11825 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11826 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11827 ASIC_REV_5750 &&
11828 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11829 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11830 }
5a6f3074 11831 }
1da177e4 11832
f51f3562
MC		 11833 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11834 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6
MC		 11835 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11836
52f4490c
MC		 11837 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11838 &pci_state_reg);
11839
5e7dfd0f
MC		 11840 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11841 if (tp->pcie_cap != 0) {
11842 u16 lnkctl;
11843
1da177e4 11844 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 11845
11846 pcie_set_readrq(tp->pdev, 4096);
11847
5e7dfd0f
MC		 11848 pci_read_config_word(tp->pdev,
11849 tp->pcie_cap + PCI_EXP_LNKCTL,
11850 &lnkctl);
11851 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 11853 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 11854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 11855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11856 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
5e7dfd0f 11857 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 11858 }
52f4490c 11859 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 11860 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 11861 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11862 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11863 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11864 if (!tp->pcix_cap) {
11865 printk(KERN_ERR PFX "Cannot find PCI-X "
11866 "capability, aborting.\n");
11867 return -EIO;
11868 }
11869
11870 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
11871 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11872 }
1da177e4 11873
399de50b
MC		 11874 /* If we have an AMD 762 or VIA K8T800 chipset, write
11875 * reordering to the mailbox registers done by the host
11876 * controller can cause major troubles. We read back from
11877 * every mailbox register write to force the writes to be
11878 * posted to the chip in order.
11879 */
11880 if (pci_dev_present(write_reorder_chipsets) &&
11881 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11882 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11883
69fc4053
MC		 11884 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
11885 &tp->pci_cacheline_sz);
11886 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11887 &tp->pci_lat_timer);
1da177e4
LT		 11888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11889 tp->pci_lat_timer < 64) {
11890 tp->pci_lat_timer = 64;
69fc4053
MC		 11891 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11892 tp->pci_lat_timer);
1da177e4
LT		 11893 }
11894
52f4490c
MC		 11895 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11896 /* 5700 BX chips need to have their TX producer index
11897 * mailboxes written twice to workaround a bug.
11898 */
11899 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 11900
52f4490c 11901 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 11902 *
11903 * The workaround is to use indirect register accesses
11904 * for all chip writes not to mailbox registers.
11905 */
52f4490c 11906 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 11907 u32 pm_reg;
1da177e4
LT		 11908
11909 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11910
11911 /* The chip can have it's power management PCI config
11912 * space registers clobbered due to this bug.
11913 * So explicitly force the chip into D0 here.
11914 */
9974a356
MC		 11915 pci_read_config_dword(tp->pdev,
11916 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11917 &pm_reg);
11918 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11919 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 11920 pci_write_config_dword(tp->pdev,
11921 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11922 pm_reg);
11923
11924 /* Also, force SERR#/PERR# in PCI command. */
11925 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11926 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11927 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11928 }
11929 }
11930
1da177e4
LT		 11931 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11932 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11933 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11934 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11935
11936 /* Chip-specific fixup from Broadcom driver */
11937 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11938 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11939 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11940 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11941 }
11942
1ee582d8 11943 /* Default fast path register access methods */
20094930 11944 tp->read32 = tg3_read32;
1ee582d8 11945 tp->write32 = tg3_write32;
09ee929c 11946 tp->read32_mbox = tg3_read32;
20094930 11947 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 11948 tp->write32_tx_mbox = tg3_write32;
11949 tp->write32_rx_mbox = tg3_write32;
11950
11951 /* Various workaround register access methods */
11952 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11953 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 11954 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11955 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11956 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11957 /*
11958 * Back to back register writes can cause problems on these
11959 * chips, the workaround is to read back all reg writes
11960 * except those to mailbox regs.
11961 *
11962 * See tg3_write_indirect_reg32().
11963 */
1ee582d8 11964 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 11965 }
11966
1ee582d8
MC		 11967
11968 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11969 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11970 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11971 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11972 tp->write32_rx_mbox = tg3_write_flush_reg32;
11973 }
20094930 11974
6892914f
MC		 11975 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11976 tp->read32 = tg3_read_indirect_reg32;
11977 tp->write32 = tg3_write_indirect_reg32;
11978 tp->read32_mbox = tg3_read_indirect_mbox;
11979 tp->write32_mbox = tg3_write_indirect_mbox;
11980 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11981 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11982
11983 iounmap(tp->regs);
22abe310 11984 tp->regs = NULL;
6892914f
MC		 11985
11986 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11987 pci_cmd &= ~PCI_COMMAND_MEMORY;
11988 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11989 }
b5d3772c
MC		 11990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11991 tp->read32_mbox = tg3_read32_mbox_5906;
11992 tp->write32_mbox = tg3_write32_mbox_5906;
11993 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11994 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11995 }
6892914f 11996
bbadf503
MC		 11997 if (tp->write32 == tg3_write_indirect_reg32 ||
11998 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11999 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12001 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12002
7d0c41ef 12003 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12004 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12005 * determined before calling tg3_set_power_state() so that
12006 * we know whether or not to switch out of Vaux power.
12007 * When the flag is set, it means that GPIO1 is used for eeprom
12008 * write protect and also implies that it is a LOM where GPIOs
12009 * are not used to switch power.
6aa20a22 12010 */
7d0c41ef
MC		 12011 tg3_get_eeprom_hw_cfg(tp);
12012
0d3031d9
MC		 12013 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12014 /* Allow reads and writes to the
12015 * APE register and memory space.
12016 */
12017 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12018 PCISTATE_ALLOW_APE_SHMEM_WR;
12019 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12020 pci_state_reg);
12021 }
12022
9936bcf6 12023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12027 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12028
314fba34
MC		 12029 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12030 * GPIO1 driven high will bring 5700's external PHY out of reset.
12031 * It is also used as eeprom write protect on LOMs.
12032 */
12033 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12034 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12035 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12036 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12037 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12038 /* Unused GPIO3 must be driven as output on 5752 because there
12039 * are no pull-up resistors on unused GPIO pins.
12040 */
12041 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12042 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12043
321d32a0
MC		 12044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12046 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12047
5f0c4a3c
MC		 12048 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12049 /* Turn off the debug UART. */
12050 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12051 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12052 /* Keep VMain power. */
12053 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12054 GRC_LCLCTRL_GPIO_OUTPUT0;
12055 }
12056
1da177e4 12057 /* Force the chip into D0. */
bc1c7567 12058 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12059 if (err) {
12060 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12061 pci_name(tp->pdev));
12062 return err;
12063 }
12064
1da177e4
LT		 12065 /* Derive initial jumbo mode from MTU assigned in
12066 * ether_setup() via the alloc_etherdev() call
12067 */
0f893dc6 12068 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12069 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12070 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12071
12072 /* Determine WakeOnLan speed to use. */
12073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12074 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12075 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12076 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12077 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12078 } else {
12079 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12080 }
12081
12082 /* A few boards don't want Ethernet@WireSpeed phy feature */
12083 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12084 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12085 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12086 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 12087 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 12088 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12089 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12090
12091 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12092 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12093 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12094 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12095 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12096
321d32a0
MC		 12097 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12098 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12099 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12100 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12105 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12106 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12107 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12108 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12109 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12110 } else
c424cb24
MC		 12111 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12112 }
1da177e4 12113
b2a5c19c
MC		 12114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12115 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12116 tp->phy_otp = tg3_read_otp_phycfg(tp);
12117 if (tp->phy_otp == 0)
12118 tp->phy_otp = TG3_OTP_DEFAULT;
12119 }
12120
f51f3562 12121 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12122 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12123 else
12124 tp->mi_mode = MAC_MI_MODE_BASE;
12125
1da177e4 12126 tp->coalesce_mode = 0;
1da177e4
LT		 12127 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12128 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12129 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12130
321d32a0
MC		 12131 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12132 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12133 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12134
158d7abd
MC		 12135 err = tg3_mdio_init(tp);
12136 if (err)
12137 return err;
1da177e4
LT		 12138
12139 /* Initialize data/descriptor byte/word swapping. */
12140 val = tr32(GRC_MODE);
12141 val &= GRC_MODE_HOST_STACKUP;
12142 tw32(GRC_MODE, val | tp->grc_mode);
12143
12144 tg3_switch_clocks(tp);
12145
12146 /* Clear this out for sanity. */
12147 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12148
12149 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12150 &pci_state_reg);
12151 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12152 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12153 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12154
12155 if (chiprevid == CHIPREV_ID_5701_A0 ||
12156 chiprevid == CHIPREV_ID_5701_B0 ||
12157 chiprevid == CHIPREV_ID_5701_B2 ||
12158 chiprevid == CHIPREV_ID_5701_B5) {
12159 void __iomem *sram_base;
12160
12161 /* Write some dummy words into the SRAM status block
12162 * area, see if it reads back correctly. If the return
12163 * value is bad, force enable the PCIX workaround.
12164 */
12165 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12166
12167 writel(0x00000000, sram_base);
12168 writel(0x00000000, sram_base + 4);
12169 writel(0xffffffff, sram_base + 4);
12170 if (readl(sram_base) != 0x00000000)
12171 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12172 }
12173 }
12174
12175 udelay(50);
12176 tg3_nvram_init(tp);
12177
12178 grc_misc_cfg = tr32(GRC_MISC_CFG);
12179 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12180
1da177e4
LT		 12181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12182 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12183 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12184 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12185
fac9b83e
DM		 12186 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12187 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12188 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12189 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12190 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12191 HOSTCC_MODE_CLRTICK_TXBD);
12192
12193 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12194 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12195 tp->misc_host_ctrl);
12196 }
12197
3bda1258
MC		 12198 /* Preserve the APE MAC_MODE bits */
12199 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12200 tp->mac_mode = tr32(MAC_MODE) |
12201 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12202 else
12203 tp->mac_mode = TG3_DEF_MAC_MODE;
12204
1da177e4
LT		 12205 /* these are limited to 10/100 only */
12206 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12207 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12208 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12209 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12210 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12211 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12212 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12213 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12214 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12215 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12216 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12217 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
b5d3772c 12218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 12219 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12220
12221 err = tg3_phy_probe(tp);
12222 if (err) {
12223 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12224 pci_name(tp->pdev), err);
12225 /* ... but do not return immediately ... */
b02fd9e3 12226 tg3_mdio_fini(tp);
1da177e4
LT		 12227 }
12228
12229 tg3_read_partno(tp);
c4e6575c 12230 tg3_read_fw_ver(tp);
1da177e4
LT		 12231
12232 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12233 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12234 } else {
12235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12236 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12237 else
12238 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12239 }
12240
12241 /* 5700 {AX,BX} chips have a broken status block link
12242 * change bit implementation, so we must use the
12243 * status register in those cases.
12244 */
12245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12246 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12247 else
12248 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12249
12250 /* The led_ctrl is set during tg3_phy_probe, here we might
12251 * have to force the link status polling mechanism based
12252 * upon subsystem IDs.
12253 */
12254 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12255 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12256 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12257 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12258 TG3_FLAG_USE_LINKCHG_REG);
12259 }
12260
12261 /* For all SERDES we poll the MAC status register. */
12262 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12263 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12264 else
12265 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12266
ad829268 12267 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12269 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12270 tp->rx_offset = 0;
12271
f92905de
MC		 12272 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12273
12274 /* Increment the rx prod index on the rx std ring by at most
12275 * 8 for these chips to workaround hw errata.
12276 */
12277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12278 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12279 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12280 tp->rx_std_max_post = 8;
12281
8ed5d97e
MC		 12282 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12283 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12284 PCIE_PWR_MGMT_L1_THRESH_MSK;
12285
1da177e4
LT		 12286 return err;
12287}
12288
49b6e95f 12289#ifdef CONFIG_SPARC
1da177e4
LT		 12290static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12291{
12292 struct net_device *dev = tp->dev;
12293 struct pci_dev *pdev = tp->pdev;
49b6e95f 12294 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12295 const unsigned char *addr;
49b6e95f
DM		 12296 int len;
12297
12298 addr = of_get_property(dp, "local-mac-address", &len);
12299 if (addr && len == 6) {
12300 memcpy(dev->dev_addr, addr, 6);
12301 memcpy(dev->perm_addr, dev->dev_addr, 6);
12302 return 0;
1da177e4
LT		 12303 }
12304 return -ENODEV;
12305}
12306
12307static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12308{
12309 struct net_device *dev = tp->dev;
12310
12311 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12312 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12313 return 0;
12314}
12315#endif
12316
12317static int __devinit tg3_get_device_address(struct tg3 *tp)
12318{
12319 struct net_device *dev = tp->dev;
12320 u32 hi, lo, mac_offset;
008652b3 12321 int addr_ok = 0;
1da177e4 12322
49b6e95f 12323#ifdef CONFIG_SPARC
1da177e4
LT		 12324 if (!tg3_get_macaddr_sparc(tp))
12325 return 0;
12326#endif
12327
12328 mac_offset = 0x7c;
f49639e6 12329 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12330 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12331 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12332 mac_offset = 0xcc;
12333 if (tg3_nvram_lock(tp))
12334 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12335 else
12336 tg3_nvram_unlock(tp);
12337 }
b5d3772c
MC		 12338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12339 mac_offset = 0x10;
1da177e4
LT		 12340
12341 /* First try to get it from MAC address mailbox. */
12342 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12343 if ((hi >> 16) == 0x484b) {
12344 dev->dev_addr[0] = (hi >> 8) & 0xff;
12345 dev->dev_addr[1] = (hi >> 0) & 0xff;
12346
12347 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12348 dev->dev_addr[2] = (lo >> 24) & 0xff;
12349 dev->dev_addr[3] = (lo >> 16) & 0xff;
12350 dev->dev_addr[4] = (lo >> 8) & 0xff;
12351 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12352
008652b3
MC		 12353 /* Some old bootcode may report a 0 MAC address in SRAM */
12354 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12355 }
12356 if (!addr_ok) {
12357 /* Next, try NVRAM. */
f49639e6 12358 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 12359 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12360 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12361 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12362 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12363 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12364 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12365 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12366 }
12367 /* Finally just fetch it out of the MAC control regs. */
12368 else {
12369 hi = tr32(MAC_ADDR_0_HIGH);
12370 lo = tr32(MAC_ADDR_0_LOW);
12371
12372 dev->dev_addr[5] = lo & 0xff;
12373 dev->dev_addr[4] = (lo >> 8) & 0xff;
12374 dev->dev_addr[3] = (lo >> 16) & 0xff;
12375 dev->dev_addr[2] = (lo >> 24) & 0xff;
12376 dev->dev_addr[1] = hi & 0xff;
12377 dev->dev_addr[0] = (hi >> 8) & 0xff;
12378 }
1da177e4
LT		 12379 }
12380
12381 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12382#ifdef CONFIG_SPARC
1da177e4
LT		 12383 if (!tg3_get_default_macaddr_sparc(tp))
12384 return 0;
12385#endif
12386 return -EINVAL;
12387 }
2ff43697 12388 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12389 return 0;
12390}
12391
59e6b434
DM		 12392#define BOUNDARY_SINGLE_CACHELINE 1
12393#define BOUNDARY_MULTI_CACHELINE 2
12394
12395static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12396{
12397 int cacheline_size;
12398 u8 byte;
12399 int goal;
12400
12401 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12402 if (byte == 0)
12403 cacheline_size = 1024;
12404 else
12405 cacheline_size = (int) byte * 4;
12406
12407 /* On 5703 and later chips, the boundary bits have no
12408 * effect.
12409 */
12410 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12411 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12412 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12413 goto out;
12414
12415#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12416 goal = BOUNDARY_MULTI_CACHELINE;
12417#else
12418#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12419 goal = BOUNDARY_SINGLE_CACHELINE;
12420#else
12421 goal = 0;
12422#endif
12423#endif
12424
12425 if (!goal)
12426 goto out;
12427
12428 /* PCI controllers on most RISC systems tend to disconnect
12429 * when a device tries to burst across a cache-line boundary.
12430 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12431 *
12432 * Unfortunately, for PCI-E there are only limited
12433 * write-side controls for this, and thus for reads
12434 * we will still get the disconnects. We'll also waste
12435 * these PCI cycles for both read and write for chips
12436 * other than 5700 and 5701 which do not implement the
12437 * boundary bits.
12438 */
12439 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12440 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12441 switch (cacheline_size) {
12442 case 16:
12443 case 32:
12444 case 64:
12445 case 128:
12446 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12447 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12448 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12449 } else {
12450 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12451 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12452 }
12453 break;
12454
12455 case 256:
12456 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12457 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12458 break;
12459
12460 default:
12461 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12462 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12463 break;
855e1111 12464 }
59e6b434
DM		 12465 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12466 switch (cacheline_size) {
12467 case 16:
12468 case 32:
12469 case 64:
12470 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12471 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12472 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12473 break;
12474 }
12475 /* fallthrough */
12476 case 128:
12477 default:
12478 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12479 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12480 break;
855e1111 12481 }
59e6b434
DM		 12482 } else {
12483 switch (cacheline_size) {
12484 case 16:
12485 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12486 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12487 DMA_RWCTRL_WRITE_BNDRY_16);
12488 break;
12489 }
12490 /* fallthrough */
12491 case 32:
12492 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12493 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12494 DMA_RWCTRL_WRITE_BNDRY_32);
12495 break;
12496 }
12497 /* fallthrough */
12498 case 64:
12499 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12500 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12501 DMA_RWCTRL_WRITE_BNDRY_64);
12502 break;
12503 }
12504 /* fallthrough */
12505 case 128:
12506 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12507 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12508 DMA_RWCTRL_WRITE_BNDRY_128);
12509 break;
12510 }
12511 /* fallthrough */
12512 case 256:
12513 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12514 DMA_RWCTRL_WRITE_BNDRY_256);
12515 break;
12516 case 512:
12517 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12518 DMA_RWCTRL_WRITE_BNDRY_512);
12519 break;
12520 case 1024:
12521 default:
12522 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12523 DMA_RWCTRL_WRITE_BNDRY_1024);
12524 break;
855e1111 12525 }
59e6b434
DM		 12526 }
12527
12528out:
12529 return val;
12530}
12531
1da177e4
LT		 12532static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12533{
12534 struct tg3_internal_buffer_desc test_desc;
12535 u32 sram_dma_descs;
12536 int i, ret;
12537
12538 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12539
12540 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12541 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12542 tw32(RDMAC_STATUS, 0);
12543 tw32(WDMAC_STATUS, 0);
12544
12545 tw32(BUFMGR_MODE, 0);
12546 tw32(FTQ_RESET, 0);
12547
12548 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12549 test_desc.addr_lo = buf_dma & 0xffffffff;
12550 test_desc.nic_mbuf = 0x00002100;
12551 test_desc.len = size;
12552
12553 /*
12554 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12555 * the *second* time the tg3 driver was getting loaded after an
12556 * initial scan.
12557 *
12558 * Broadcom tells me:
12559 * ...the DMA engine is connected to the GRC block and a DMA
12560 * reset may affect the GRC block in some unpredictable way...
12561 * The behavior of resets to individual blocks has not been tested.
12562 *
12563 * Broadcom noted the GRC reset will also reset all sub-components.
12564 */
12565 if (to_device) {
12566 test_desc.cqid_sqid = (13 << 8) | 2;
12567
12568 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12569 udelay(40);
12570 } else {
12571 test_desc.cqid_sqid = (16 << 8) | 7;
12572
12573 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12574 udelay(40);
12575 }
12576 test_desc.flags = 0x00000005;
12577
12578 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12579 u32 val;
12580
12581 val = *(((u32 *)&test_desc) + i);
12582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12583 sram_dma_descs + (i * sizeof(u32)));
12584 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12585 }
12586 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12587
12588 if (to_device) {
12589 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12590 } else {
12591 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12592 }
12593
12594 ret = -ENODEV;
12595 for (i = 0; i < 40; i++) {
12596 u32 val;
12597
12598 if (to_device)
12599 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12600 else
12601 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12602 if ((val & 0xffff) == sram_dma_descs) {
12603 ret = 0;
12604 break;
12605 }
12606
12607 udelay(100);
12608 }
12609
12610 return ret;
12611}
12612
ded7340d 12613#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12614
12615static int __devinit tg3_test_dma(struct tg3 *tp)
12616{
12617 dma_addr_t buf_dma;
59e6b434 12618 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12619 int ret;
12620
12621 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12622 if (!buf) {
12623 ret = -ENOMEM;
12624 goto out_nofree;
12625 }
12626
12627 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12628 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12629
59e6b434 12630 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12631
12632 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12633 /* DMA read watermark not used on PCIE */
12634 tp->dma_rwctrl |= 0x00180000;
12635 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12638 tp->dma_rwctrl |= 0x003f0000;
12639 else
12640 tp->dma_rwctrl |= 0x003f000f;
12641 } else {
12642 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12643 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12644 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12645 u32 read_water = 0x7;
1da177e4 12646
4a29cc2e
MC		 12647 /* If the 5704 is behind the EPB bridge, we can
12648 * do the less restrictive ONE_DMA workaround for
12649 * better performance.
12650 */
12651 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12653 tp->dma_rwctrl |= 0x8000;
12654 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12655 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12656
49afdeb6
MC		 12657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12658 read_water = 4;
59e6b434 12659 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12660 tp->dma_rwctrl |=
12661 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12662 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12663 (1 << 23);
4cf78e4f
MC		 12664 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12665 /* 5780 always in PCIX mode */
12666 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12667 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12668 /* 5714 always in PCIX mode */
12669 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12670 } else {
12671 tp->dma_rwctrl |= 0x001b000f;
12672 }
12673 }
12674
12675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12676 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12677 tp->dma_rwctrl &= 0xfffffff0;
12678
12679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12680 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12681 /* Remove this if it causes problems for some boards. */
12682 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12683
12684 /* On 5700/5701 chips, we need to set this bit.
12685 * Otherwise the chip will issue cacheline transactions
12686 * to streamable DMA memory with not all the byte
12687 * enables turned on. This is an error on several
12688 * RISC PCI controllers, in particular sparc64.
12689 *
12690 * On 5703/5704 chips, this bit has been reassigned
12691 * a different meaning. In particular, it is used
12692 * on those chips to enable a PCI-X workaround.
12693 */
12694 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12695 }
12696
12697 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12698
12699#if 0
12700 /* Unneeded, already done by tg3_get_invariants. */
12701 tg3_switch_clocks(tp);
12702#endif
12703
12704 ret = 0;
12705 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12706 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12707 goto out;
12708
59e6b434
DM		 12709 /* It is best to perform DMA test with maximum write burst size
12710 * to expose the 5700/5701 write DMA bug.
12711 */
12712 saved_dma_rwctrl = tp->dma_rwctrl;
12713 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12714 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12715
1da177e4
LT		 12716 while (1) {
12717 u32 *p = buf, i;
12718
12719 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12720 p[i] = i;
12721
12722 /* Send the buffer to the chip. */
12723 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12724 if (ret) {
12725 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12726 break;
12727 }
12728
12729#if 0
12730 /* validate data reached card RAM correctly. */
12731 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12732 u32 val;
12733 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12734 if (le32_to_cpu(val) != p[i]) {
12735 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12736 /* ret = -ENODEV here? */
12737 }
12738 p[i] = 0;
12739 }
12740#endif
12741 /* Now read it back. */
12742 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12743 if (ret) {
12744 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12745
12746 break;
12747 }
12748
12749 /* Verify it. */
12750 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12751 if (p[i] == i)
12752 continue;
12753
59e6b434
DM		 12754 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12755 DMA_RWCTRL_WRITE_BNDRY_16) {
12756 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12757 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12758 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12759 break;
12760 } else {
12761 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12762 ret = -ENODEV;
12763 goto out;
12764 }
12765 }
12766
12767 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12768 /* Success. */
12769 ret = 0;
12770 break;
12771 }
12772 }
59e6b434
DM		 12773 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12774 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12775 static struct pci_device_id dma_wait_state_chipsets[] = {
12776 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12777 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12778 { },
12779 };
12780
59e6b434 12781 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12782 * now look for chipsets that are known to expose the
12783 * DMA bug without failing the test.
59e6b434 12784 */
6d1cfbab
MC		 12785 if (pci_dev_present(dma_wait_state_chipsets)) {
12786 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12787 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12788 }
12789 else
12790 /* Safe to use the calculated DMA boundary. */
12791 tp->dma_rwctrl = saved_dma_rwctrl;
12792
59e6b434
DM		 12793 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12794 }
1da177e4
LT		 12795
12796out:
12797 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12798out_nofree:
12799 return ret;
12800}
12801
12802static void __devinit tg3_init_link_config(struct tg3 *tp)
12803{
12804 tp->link_config.advertising =
12805 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12806 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12807 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12808 ADVERTISED_Autoneg | ADVERTISED_MII);
12809 tp->link_config.speed = SPEED_INVALID;
12810 tp->link_config.duplex = DUPLEX_INVALID;
12811 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12812 tp->link_config.active_speed = SPEED_INVALID;
12813 tp->link_config.active_duplex = DUPLEX_INVALID;
12814 tp->link_config.phy_is_low_power = 0;
12815 tp->link_config.orig_speed = SPEED_INVALID;
12816 tp->link_config.orig_duplex = DUPLEX_INVALID;
12817 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12818}
12819
12820static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12821{
fdfec172
MC		 12822 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12823 tp->bufmgr_config.mbuf_read_dma_low_water =
12824 DEFAULT_MB_RDMA_LOW_WATER_5705;
12825 tp->bufmgr_config.mbuf_mac_rx_low_water =
12826 DEFAULT_MB_MACRX_LOW_WATER_5705;
12827 tp->bufmgr_config.mbuf_high_water =
12828 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12829 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12830 tp->bufmgr_config.mbuf_mac_rx_low_water =
12831 DEFAULT_MB_MACRX_LOW_WATER_5906;
12832 tp->bufmgr_config.mbuf_high_water =
12833 DEFAULT_MB_HIGH_WATER_5906;
12834 }
fdfec172
MC		 12835
12836 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12837 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12838 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12839 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12840 tp->bufmgr_config.mbuf_high_water_jumbo =
12841 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12842 } else {
12843 tp->bufmgr_config.mbuf_read_dma_low_water =
12844 DEFAULT_MB_RDMA_LOW_WATER;
12845 tp->bufmgr_config.mbuf_mac_rx_low_water =
12846 DEFAULT_MB_MACRX_LOW_WATER;
12847 tp->bufmgr_config.mbuf_high_water =
12848 DEFAULT_MB_HIGH_WATER;
12849
12850 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12851 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12852 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12853 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12854 tp->bufmgr_config.mbuf_high_water_jumbo =
12855 DEFAULT_MB_HIGH_WATER_JUMBO;
12856 }
1da177e4
LT		 12857
12858 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12859 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12860}
12861
12862static char * __devinit tg3_phy_string(struct tg3 *tp)
12863{
12864 switch (tp->phy_id & PHY_ID_MASK) {
12865 case PHY_ID_BCM5400: return "5400";
12866 case PHY_ID_BCM5401: return "5401";
12867 case PHY_ID_BCM5411: return "5411";
12868 case PHY_ID_BCM5701: return "5701";
12869 case PHY_ID_BCM5703: return "5703";
12870 case PHY_ID_BCM5704: return "5704";
12871 case PHY_ID_BCM5705: return "5705";
12872 case PHY_ID_BCM5750: return "5750";
85e94ced 12873 case PHY_ID_BCM5752: return "5752";
a4e2b347 12874 case PHY_ID_BCM5714: return "5714";
4cf78e4f 12875 case PHY_ID_BCM5780: return "5780";
af36e6b6 12876 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 12877 case PHY_ID_BCM5787: return "5787";
d30cdd28 12878 case PHY_ID_BCM5784: return "5784";
126a3368 12879 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 12880 case PHY_ID_BCM5906: return "5906";
9936bcf6 12881 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 12882 case PHY_ID_BCM8002: return "8002/serdes";
12883 case 0: return "serdes";
12884 default: return "unknown";
855e1111 12885 }
1da177e4
LT		 12886}
12887
f9804ddb
MC		 12888static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12889{
12890 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12891 strcpy(str, "PCI Express");
12892 return str;
12893 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12894 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12895
12896 strcpy(str, "PCIX:");
12897
12898 if ((clock_ctrl == 7) ||
12899 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12900 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12901 strcat(str, "133MHz");
12902 else if (clock_ctrl == 0)
12903 strcat(str, "33MHz");
12904 else if (clock_ctrl == 2)
12905 strcat(str, "50MHz");
12906 else if (clock_ctrl == 4)
12907 strcat(str, "66MHz");
12908 else if (clock_ctrl == 6)
12909 strcat(str, "100MHz");
f9804ddb
MC		 12910 } else {
12911 strcpy(str, "PCI:");
12912 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12913 strcat(str, "66MHz");
12914 else
12915 strcat(str, "33MHz");
12916 }
12917 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12918 strcat(str, ":32-bit");
12919 else
12920 strcat(str, ":64-bit");
12921 return str;
12922}
12923
8c2dc7e1 12924static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 12925{
12926 struct pci_dev *peer;
12927 unsigned int func, devnr = tp->pdev->devfn & ~7;
12928
12929 for (func = 0; func < 8; func++) {
12930 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12931 if (peer && peer != tp->pdev)
12932 break;
12933 pci_dev_put(peer);
12934 }
16fe9d74
MC		 12935 /* 5704 can be configured in single-port mode, set peer to
12936 * tp->pdev in that case.
12937 */
12938 if (!peer) {
12939 peer = tp->pdev;
12940 return peer;
12941 }
1da177e4
LT		 12942
12943 /*
12944 * We don't need to keep the refcount elevated; there's no way
12945 * to remove one half of this device without removing the other
12946 */
12947 pci_dev_put(peer);
12948
12949 return peer;
12950}
12951
15f9850d
DM		 12952static void __devinit tg3_init_coal(struct tg3 *tp)
12953{
12954 struct ethtool_coalesce *ec = &tp->coal;
12955
12956 memset(ec, 0, sizeof(*ec));
12957 ec->cmd = ETHTOOL_GCOALESCE;
12958 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12959 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12960 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12961 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12962 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12963 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12964 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12965 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12966 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12967
12968 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12969 HOSTCC_MODE_CLRTICK_TXBD)) {
12970 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12971 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12972 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12973 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12974 }
d244c892
MC		 12975
12976 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12977 ec->rx_coalesce_usecs_irq = 0;
12978 ec->tx_coalesce_usecs_irq = 0;
12979 ec->stats_block_coalesce_usecs = 0;
12980 }
15f9850d
DM		 12981}
12982
7c7d64b8
SH		 12983static const struct net_device_ops tg3_netdev_ops = {
12984 .ndo_open = tg3_open,
12985 .ndo_stop = tg3_close,
00829823
SH		 12986 .ndo_start_xmit = tg3_start_xmit,
12987 .ndo_get_stats = tg3_get_stats,
12988 .ndo_validate_addr = eth_validate_addr,
12989 .ndo_set_multicast_list = tg3_set_rx_mode,
12990 .ndo_set_mac_address = tg3_set_mac_addr,
12991 .ndo_do_ioctl = tg3_ioctl,
12992 .ndo_tx_timeout = tg3_tx_timeout,
12993 .ndo_change_mtu = tg3_change_mtu,
12994#if TG3_VLAN_TAG_USED
12995 .ndo_vlan_rx_register = tg3_vlan_rx_register,
12996#endif
12997#ifdef CONFIG_NET_POLL_CONTROLLER
12998 .ndo_poll_controller = tg3_poll_controller,
12999#endif
13000};
13001
13002static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13003 .ndo_open = tg3_open,
13004 .ndo_stop = tg3_close,
13005 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13006 .ndo_get_stats = tg3_get_stats,
13007 .ndo_validate_addr = eth_validate_addr,
13008 .ndo_set_multicast_list = tg3_set_rx_mode,
13009 .ndo_set_mac_address = tg3_set_mac_addr,
13010 .ndo_do_ioctl = tg3_ioctl,
13011 .ndo_tx_timeout = tg3_tx_timeout,
13012 .ndo_change_mtu = tg3_change_mtu,
13013#if TG3_VLAN_TAG_USED
13014 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13015#endif
13016#ifdef CONFIG_NET_POLL_CONTROLLER
13017 .ndo_poll_controller = tg3_poll_controller,
13018#endif
13019};
13020
1da177e4
LT		 13021static int __devinit tg3_init_one(struct pci_dev *pdev,
13022 const struct pci_device_id *ent)
13023{
13024 static int tg3_version_printed = 0;
1da177e4
LT		 13025 struct net_device *dev;
13026 struct tg3 *tp;
d6645372 13027 int err, pm_cap;
f9804ddb 13028 char str[40];
72f2afb8 13029 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13030
13031 if (tg3_version_printed++ == 0)
13032 printk(KERN_INFO "%s", version);
13033
13034 err = pci_enable_device(pdev);
13035 if (err) {
13036 printk(KERN_ERR PFX "Cannot enable PCI device, "
13037 "aborting.\n");
13038 return err;
13039 }
13040
1da177e4
LT		 13041 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13042 if (err) {
13043 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13044 "aborting.\n");
13045 goto err_out_disable_pdev;
13046 }
13047
13048 pci_set_master(pdev);
13049
13050 /* Find power-management capability. */
13051 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13052 if (pm_cap == 0) {
13053 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13054 "aborting.\n");
13055 err = -EIO;
13056 goto err_out_free_res;
13057 }
13058
1da177e4
LT		 13059 dev = alloc_etherdev(sizeof(*tp));
13060 if (!dev) {
13061 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13062 err = -ENOMEM;
13063 goto err_out_free_res;
13064 }
13065
1da177e4
LT		 13066 SET_NETDEV_DEV(dev, &pdev->dev);
13067
1da177e4
LT		 13068#if TG3_VLAN_TAG_USED
13069 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13070#endif
13071
13072 tp = netdev_priv(dev);
13073 tp->pdev = pdev;
13074 tp->dev = dev;
13075 tp->pm_cap = pm_cap;
1da177e4
LT		 13076 tp->rx_mode = TG3_DEF_RX_MODE;
13077 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13078
1da177e4
LT		 13079 if (tg3_debug > 0)
13080 tp->msg_enable = tg3_debug;
13081 else
13082 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13083
13084 /* The word/byte swap controls here control register access byte
13085 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13086 * setting below.
13087 */
13088 tp->misc_host_ctrl =
13089 MISC_HOST_CTRL_MASK_PCI_INT |
13090 MISC_HOST_CTRL_WORD_SWAP |
13091 MISC_HOST_CTRL_INDIR_ACCESS |
13092 MISC_HOST_CTRL_PCISTATE_RW;
13093
13094 /* The NONFRM (non-frame) byte/word swap controls take effect
13095 * on descriptor entries, anything which isn't packet data.
13096 *
13097 * The StrongARM chips on the board (one for tx, one for rx)
13098 * are running in big-endian mode.
13099 */
13100 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13101 GRC_MODE_WSWAP_NONFRM_DATA);
13102#ifdef __BIG_ENDIAN
13103 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13104#endif
13105 spin_lock_init(&tp->lock);
1da177e4 13106 spin_lock_init(&tp->indirect_lock);
c4028958 13107 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13108
d5fe488a 13109 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13110 if (!tp->regs) {
1da177e4
LT		 13111 printk(KERN_ERR PFX "Cannot map device registers, "
13112 "aborting.\n");
13113 err = -ENOMEM;
13114 goto err_out_free_dev;
13115 }
13116
13117 tg3_init_link_config(tp);
13118
1da177e4
LT		 13119 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13120 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13121 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13122
bea3348e 13123 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13124 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13125 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13126 dev->irq = pdev->irq;
1da177e4
LT		 13127
13128 err = tg3_get_invariants(tp);
13129 if (err) {
13130 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13131 "aborting.\n");
13132 goto err_out_iounmap;
13133 }
13134
321d32a0 13135 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13137 dev->netdev_ops = &tg3_netdev_ops;
13138 else
13139 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13140
13141
4a29cc2e
MC		 13142 /* The EPB bridge inside 5714, 5715, and 5780 and any
13143 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13144 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13145 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13146 * do DMA address check in tg3_start_xmit().
13147 */
4a29cc2e
MC		 13148 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13149 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13150 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 13151 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13152#ifdef CONFIG_HIGHMEM
13153 dma_mask = DMA_64BIT_MASK;
13154#endif
4a29cc2e 13155 } else
72f2afb8
MC		 13156 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13157
13158 /* Configure DMA attributes. */
13159 if (dma_mask > DMA_32BIT_MASK) {
13160 err = pci_set_dma_mask(pdev, dma_mask);
13161 if (!err) {
13162 dev->features |= NETIF_F_HIGHDMA;
13163 err = pci_set_consistent_dma_mask(pdev,
13164 persist_dma_mask);
13165 if (err < 0) {
13166 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13167 "DMA for consistent allocations\n");
13168 goto err_out_iounmap;
13169 }
13170 }
13171 }
13172 if (err || dma_mask == DMA_32BIT_MASK) {
13173 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13174 if (err) {
13175 printk(KERN_ERR PFX "No usable DMA configuration, "
13176 "aborting.\n");
13177 goto err_out_iounmap;
13178 }
13179 }
13180
fdfec172 13181 tg3_init_bufmgr_config(tp);
1da177e4 13182
077f849d 13183 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13184 tp->fw_needed = FIRMWARE_TG3;
077f849d 13185
1da177e4
LT		 13186 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13187 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13188 }
13189 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13191 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13193 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13194 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13195 } else {
7f62ad5d 13196 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13198 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13199 else
9e9fd12d 13200 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13201 }
1da177e4 13202
4e3a7aaa
MC		 13203 /* TSO is on by default on chips that support hardware TSO.
13204 * Firmware TSO on older chips gives lower performance, so it
13205 * is off by default, but can be enabled using ethtool.
13206 */
b0026624 13207 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13208 if (dev->features & NETIF_F_IP_CSUM)
13209 dev->features |= NETIF_F_TSO;
13210 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13211 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13212 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13214 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13215 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13216 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13217 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13218 dev->features |= NETIF_F_TSO_ECN;
b0026624 13219 }
1da177e4 13220
1da177e4
LT		 13221
13222 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13223 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13224 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13225 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13226 tp->rx_pending = 63;
13227 }
13228
1da177e4
LT		 13229 err = tg3_get_device_address(tp);
13230 if (err) {
13231 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13232 "aborting.\n");
077f849d 13233 goto err_out_fw;
1da177e4
LT		 13234 }
13235
c88864df 13236 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13237 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13238 if (!tp->aperegs) {
c88864df
MC		 13239 printk(KERN_ERR PFX "Cannot map APE registers, "
13240 "aborting.\n");
13241 err = -ENOMEM;
077f849d 13242 goto err_out_fw;
c88864df
MC		 13243 }
13244
13245 tg3_ape_lock_init(tp);
13246 }
13247
1da177e4
LT		 13248 /*
13249 * Reset chip in case UNDI or EFI driver did not shutdown
13250 * DMA self test will enable WDMAC and we'll see (spurious)
13251 * pending DMA on the PCI bus at that point.
13252 */
13253 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13254 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13255 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13256 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13257 }
13258
13259 err = tg3_test_dma(tp);
13260 if (err) {
13261 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13262 goto err_out_apeunmap;
1da177e4
LT		 13263 }
13264
1da177e4
LT		 13265 /* flow control autonegotiation is default behavior */
13266 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13267 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13268
15f9850d
DM		 13269 tg3_init_coal(tp);
13270
c49a1561
MC		 13271 pci_set_drvdata(pdev, dev);
13272
1da177e4
LT		 13273 err = register_netdev(dev);
13274 if (err) {
13275 printk(KERN_ERR PFX "Cannot register net device, "
13276 "aborting.\n");
0d3031d9 13277 goto err_out_apeunmap;
1da177e4
LT		 13278 }
13279
df59c940 13280 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13281 dev->name,
13282 tp->board_part_number,
13283 tp->pci_chip_rev_id,
f9804ddb 13284 tg3_bus_string(tp, str),
e174961c 13285 dev->dev_addr);
1da177e4 13286
df59c940
MC		 13287 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13288 printk(KERN_INFO
13289 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13290 tp->dev->name,
13291 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13292 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13293 else
13294 printk(KERN_INFO
13295 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13296 tp->dev->name, tg3_phy_string(tp),
13297 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13298 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13299 "10/100/1000Base-T")),
13300 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13301
13302 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13303 dev->name,
13304 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13305 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13306 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13307 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13308 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13309 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13310 dev->name, tp->dma_rwctrl,
13311 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13312 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 13313
13314 return 0;
13315
0d3031d9
MC		 13316err_out_apeunmap:
13317 if (tp->aperegs) {
13318 iounmap(tp->aperegs);
13319 tp->aperegs = NULL;
13320 }
13321
077f849d
JSR		 13322err_out_fw:
13323 if (tp->fw)
13324 release_firmware(tp->fw);
13325
1da177e4 13326err_out_iounmap:
6892914f
MC		 13327 if (tp->regs) {
13328 iounmap(tp->regs);
22abe310 13329 tp->regs = NULL;
6892914f 13330 }
1da177e4
LT		 13331
13332err_out_free_dev:
13333 free_netdev(dev);
13334
13335err_out_free_res:
13336 pci_release_regions(pdev);
13337
13338err_out_disable_pdev:
13339 pci_disable_device(pdev);
13340 pci_set_drvdata(pdev, NULL);
13341 return err;
13342}
13343
13344static void __devexit tg3_remove_one(struct pci_dev *pdev)
13345{
13346 struct net_device *dev = pci_get_drvdata(pdev);
13347
13348 if (dev) {
13349 struct tg3 *tp = netdev_priv(dev);
13350
077f849d
JSR		 13351 if (tp->fw)
13352 release_firmware(tp->fw);
13353
7faa006f 13354 flush_scheduled_work();
158d7abd 13355
b02fd9e3
MC		 13356 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13357 tg3_phy_fini(tp);
158d7abd 13358 tg3_mdio_fini(tp);
b02fd9e3 13359 }
158d7abd 13360
1da177e4 13361 unregister_netdev(dev);
0d3031d9
MC		 13362 if (tp->aperegs) {
13363 iounmap(tp->aperegs);
13364 tp->aperegs = NULL;
13365 }
6892914f
MC		 13366 if (tp->regs) {
13367 iounmap(tp->regs);
22abe310 13368 tp->regs = NULL;
6892914f 13369 }
1da177e4
LT		 13370 free_netdev(dev);
13371 pci_release_regions(pdev);
13372 pci_disable_device(pdev);
13373 pci_set_drvdata(pdev, NULL);
13374 }
13375}
13376
13377static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13378{
13379 struct net_device *dev = pci_get_drvdata(pdev);
13380 struct tg3 *tp = netdev_priv(dev);
12dac075 13381 pci_power_t target_state;
1da177e4
LT		 13382 int err;
13383
3e0c95fd
MC		 13384 /* PCI register 4 needs to be saved whether netif_running() or not.
13385 * MSI address and data need to be saved if using MSI and
13386 * netif_running().
13387 */
13388 pci_save_state(pdev);
13389
1da177e4
LT		 13390 if (!netif_running(dev))
13391 return 0;
13392
7faa006f 13393 flush_scheduled_work();
b02fd9e3 13394 tg3_phy_stop(tp);
1da177e4
LT		 13395 tg3_netif_stop(tp);
13396
13397 del_timer_sync(&tp->timer);
13398
f47c11ee 13399 tg3_full_lock(tp, 1);
1da177e4 13400 tg3_disable_ints(tp);
f47c11ee 13401 tg3_full_unlock(tp);
1da177e4
LT		 13402
13403 netif_device_detach(dev);
13404
f47c11ee 13405 tg3_full_lock(tp, 0);
944d980e 13406 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13407 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13408 tg3_full_unlock(tp);
1da177e4 13409
12dac075
RW		 13410 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13411
13412 err = tg3_set_power_state(tp, target_state);
1da177e4 13413 if (err) {
b02fd9e3
MC		 13414 int err2;
13415
f47c11ee 13416 tg3_full_lock(tp, 0);
1da177e4 13417
6a9eba15 13418 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13419 err2 = tg3_restart_hw(tp, 1);
13420 if (err2)
b9ec6c1b 13421 goto out;
1da177e4
LT		 13422
13423 tp->timer.expires = jiffies + tp->timer_offset;
13424 add_timer(&tp->timer);
13425
13426 netif_device_attach(dev);
13427 tg3_netif_start(tp);
13428
b9ec6c1b 13429out:
f47c11ee 13430 tg3_full_unlock(tp);
b02fd9e3
MC		 13431
13432 if (!err2)
13433 tg3_phy_start(tp);
1da177e4
LT		 13434 }
13435
13436 return err;
13437}
13438
13439static int tg3_resume(struct pci_dev *pdev)
13440{
13441 struct net_device *dev = pci_get_drvdata(pdev);
13442 struct tg3 *tp = netdev_priv(dev);
13443 int err;
13444
3e0c95fd
MC		 13445 pci_restore_state(tp->pdev);
13446
1da177e4
LT		 13447 if (!netif_running(dev))
13448 return 0;
13449
bc1c7567 13450 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13451 if (err)
13452 return err;
13453
13454 netif_device_attach(dev);
13455
f47c11ee 13456 tg3_full_lock(tp, 0);
1da177e4 13457
6a9eba15 13458 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13459 err = tg3_restart_hw(tp, 1);
13460 if (err)
13461 goto out;
1da177e4
LT		 13462
13463 tp->timer.expires = jiffies + tp->timer_offset;
13464 add_timer(&tp->timer);
13465
1da177e4
LT		 13466 tg3_netif_start(tp);
13467
b9ec6c1b 13468out:
f47c11ee 13469 tg3_full_unlock(tp);
1da177e4 13470
b02fd9e3
MC		 13471 if (!err)
13472 tg3_phy_start(tp);
13473
b9ec6c1b 13474 return err;
1da177e4
LT		 13475}
13476
13477static struct pci_driver tg3_driver = {
13478 .name = DRV_MODULE_NAME,
13479 .id_table = tg3_pci_tbl,
13480 .probe = tg3_init_one,
13481 .remove = __devexit_p(tg3_remove_one),
13482 .suspend = tg3_suspend,
13483 .resume = tg3_resume
13484};
13485
13486static int __init tg3_init(void)
13487{
29917620 13488 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13489}
13490
13491static void __exit tg3_cleanup(void)
13492{
13493 pci_unregister_driver(&tg3_driver);
13494}
13495
13496module_init(tg3_init);
13497module_exit(tg3_cleanup);
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