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tg3: Eliminate nvram routine forward declarations
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
65610fba 7 * Copyright (C) 2005-2007 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
d3d31709
MC		 71#define DRV_MODULE_VERSION "3.97"
72#define DRV_MODULE_RELDATE "December 10, 2008"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
0f893dc6 95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131/* minimum number of free TX descriptors required to wake up TX process */
42952231 132#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 133
ad829268
MC		 134#define TG3_RAW_IP_ALIGN 2
135
1da177e4
LT		 136/* number of ETHTOOL_GSTATS u64's */
137#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
4cafd3f5
MC		 139#define TG3_NUM_TEST 6
140
077f849d
JSR		 141#define FIRMWARE_TG3 "tigon/tg3.bin"
142#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
1da177e4
LT		 145static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150MODULE_LICENSE("GPL");
151MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 152MODULE_FIRMWARE(FIRMWARE_TG3);
153MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
1da177e4
LT		 156
157static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158module_param(tg3_debug, int, 0);
159MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
57e6983c 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
321d32a0
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
13185217
HK		 227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
1da177e4
LT		 235};
236
237MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
50da859d 239static const struct {
1da177e4
LT		 240 const char string[ETH_GSTRING_LEN];
241} ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318};
319
50da859d 320static const struct {
4cafd3f5
MC		 321 const char string[ETH_GSTRING_LEN];
322} ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329};
330
b401e9e2
MC		 331static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332{
333 writel(val, tp->regs + off);
334}
335
336static u32 tg3_read32(struct tg3 *tp, u32 off)
337{
6aa20a22 338 return (readl(tp->regs + off));
b401e9e2
MC		 339}
340
0d3031d9
MC		 341static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342{
343 writel(val, tp->aperegs + off);
344}
345
346static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347{
348 return (readl(tp->aperegs + off));
349}
350
1da177e4
LT		 351static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352{
6892914f
MC		 353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 359}
360
361static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
1da177e4
LT		 365}
366
6892914f 367static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 368{
6892914f
MC		 369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377}
378
379static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380{
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
1da177e4 392 }
6892914f
MC		 393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407}
408
409static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410{
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419}
420
b401e9e2
MC		 421/* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 427{
b401e9e2
MC		 428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
1da177e4
LT		 444}
445
09ee929c
MC		 446static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447{
448 tp->write32_mbox(tp, off, val);
6892914f
MC		 449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
09ee929c
MC		 452}
453
20094930 454static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 455{
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462}
463
b5d3772c
MC		 464static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465{
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467}
468
469static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470{
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472}
473
20094930 474#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 475#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 476#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 478#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 479
480#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 481#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 483#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 484
485static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486{
6892914f
MC		 487 unsigned long flags;
488
b5d3772c
MC		 489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
6892914f 493 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 497
bbadf503
MC		 498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 503
bbadf503
MC		 504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 508}
509
1da177e4
LT		 510static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511{
6892914f
MC		 512 unsigned long flags;
513
b5d3772c
MC		 514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
6892914f 520 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 524
bbadf503
MC		 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
6892914f 534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 535}
536
0d3031d9
MC		 537static void tg3_ape_lock_init(struct tg3 *tp)
538{
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545}
546
547static int tg3_ape_lock(struct tg3 *tp, int locknum)
548{
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
77b483f1 557 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585}
586
587static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588{
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
77b483f1 595 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604}
605
1da177e4
LT		 606static void tg3_disable_ints(struct tg3 *tp)
607{
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 611}
612
613static inline void tg3_cond_int(struct tg3 *tp)
614{
38f3843e
MC		 615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 621}
622
623static void tg3_enable_ints(struct tg3 *tp)
624{
bbe832c0
MC		 625 tp->irq_sync = 0;
626 wmb();
627
1da177e4
LT		 628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
fcfa0a32
MC		 632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
1da177e4
LT		 635 tg3_cond_int(tp);
636}
637
04237ddd
MC		 638static inline unsigned int tg3_has_work(struct tg3 *tp)
639{
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656}
657
1da177e4 658/* tg3_restart_ints
04237ddd
MC		 659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
6aa20a22 661 * which reenables interrupts
1da177e4
LT		 662 */
663static void tg3_restart_ints(struct tg3 *tp)
664{
fac9b83e
DM		 665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
1da177e4
LT		 667 mmiowb();
668
fac9b83e
DM		 669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
04237ddd
MC		 675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 677}
678
679static inline void tg3_netif_stop(struct tg3 *tp)
680{
bbe832c0 681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 682 napi_disable(&tp->napi);
1da177e4
LT		 683 netif_tx_disable(tp->dev);
684}
685
686static inline void tg3_netif_start(struct tg3 *tp)
687{
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
bea3348e 693 napi_enable(&tp->napi);
f47c11ee
DM		 694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
1da177e4
LT		 696}
697
698static void tg3_switch_clocks(struct tg3 *tp)
699{
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
795d01c5
MC		 703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 705 return;
706
1da177e4
LT		 707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
1da177e4 726 }
b401e9e2 727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 728}
729
730#define PHY_BUSY_LOOPS 5000
731
732static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733{
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 751
1da177e4
LT		 752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779}
780
781static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782{
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
b5d3772c
MC		 787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
1da177e4
LT		 791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 803
1da177e4
LT		 804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828}
829
95e2869a
MC		 830static int tg3_bmcr_reset(struct tg3 *tp)
831{
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
d4675b52 855 if (limit < 0)
95e2869a
MC		 856 return -EBUSY;
857
858 return 0;
859}
860
158d7abd
MC		 861static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862{
3d16543d 863 struct tg3 *tp = bp->priv;
158d7abd
MC		 864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873}
874
875static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876{
3d16543d 877 struct tg3 *tp = bp->priv;
158d7abd
MC		 878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886}
887
888static int tg3_mdio_reset(struct mii_bus *bp)
889{
890 return 0;
891}
892
9c61d6bc 893static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 894{
895 u32 val;
fcb389df 896 struct phy_device *phydev;
a9daf367 897
fcb389df
MC		 898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
a9daf367 913 return;
fcb389df
MC		 914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
a9daf367
MC		 935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
a9daf367
MC		 946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
fcb389df 954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966}
967
158d7abd
MC		 968static void tg3_mdio_start(struct tg3 *tp)
969{
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 971 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 973 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
a9daf367 979
9c61d6bc
MC		 980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
158d7abd
MC		 983}
984
985static void tg3_mdio_stop(struct tg3 *tp)
986{
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 988 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 990 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 991 }
992}
993
994static int tg3_mdio_init(struct tg3 *tp)
995{
996 int i;
997 u32 reg;
a9daf367 998 struct phy_device *phydev;
158d7abd
MC		 999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
298cf9be
LB		 1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
158d7abd 1009
298cf9be
LB		 1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1022 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
298cf9be 1032 i = mdiobus_register(tp->mdio_bus);
a9daf367 1033 if (i) {
158d7abd
MC		 1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
9c61d6bc 1036 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1037 return i;
1038 }
158d7abd 1039
298cf9be 1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1041
9c61d6bc
MC		 1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
a9daf367 1053 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1063 break;
fcb389df 1064 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
9c61d6bc
MC		 1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
a9daf367
MC		 1074
1075 return 0;
158d7abd
MC		 1076}
1077
1078static void tg3_mdio_fini(struct tg3 *tp)
1079{
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086}
1087
4ba526ce
MC		 1088/* tp->lock is held. */
1089static inline void tg3_generate_fw_event(struct tg3 *tp)
1090{
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098}
1099
1100#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
95e2869a
MC		 1102/* tp->lock is held. */
1103static void tg3_wait_for_event_ack(struct tg3 *tp)
1104{
1105 int i;
4ba526ce
MC		 1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1121
4ba526ce 1122 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
4ba526ce 1125 udelay(8);
95e2869a
MC		 1126 }
1127}
1128
1129/* tp->lock is held. */
1130static void tg3_ump_link_report(struct tg3 *tp)
1131{
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
4ba526ce 1174 tg3_generate_fw_event(tp);
95e2869a
MC		 1175}
1176
1177static void tg3_link_report(struct tg3 *tp)
1178{
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
e18ce346 1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1198 "on" : "off",
e18ce346 1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203}
1204
1205static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206{
1207 u16 miireg;
1208
e18ce346 1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1210 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1211 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1212 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1213 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219}
1220
1221static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
95e2869a
MC		 1237static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238{
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1246 cap = FLOW_CTRL_RX;
95e2869a
MC		 1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1253 cap = FLOW_CTRL_TX;
95e2869a
MC		 1254 }
1255
1256 return cap;
1257}
1258
f51f3562 1259static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1260{
b02fd9e3 1261 u8 autoneg;
f51f3562 1262 u8 flowctrl = 0;
95e2869a
MC		 1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
b02fd9e3 1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1275 else
bc02ff95 1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1277 } else
1278 flowctrl = tp->link_config.flowctrl;
95e2869a 1279
f51f3562 1280 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1281
e18ce346 1282 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
f51f3562 1287 if (old_rx_mode != tp->rx_mode)
95e2869a 1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1289
e18ce346 1290 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
f51f3562 1295 if (old_tx_mode != tp->tx_mode)
95e2869a 1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1297}
1298
b02fd9e3
MC		 1299static void tg3_adjust_link(struct net_device *dev)
1300{
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
298cf9be 1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
fcb389df
MC		 1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
b02fd9e3
MC		 1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378}
1379
1380static int tg3_phy_init(struct tg3 *tp)
1381{
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
298cf9be 1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1391
1392 /* Attach the MAC to the PHY. */
fb28ad35 1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1394 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
b02fd9e3 1400 /* Mask with MAC supported features. */
9c61d6bc
MC		 1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
9c61d6bc
MC		 1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1422
1423 phydev->advertising = phydev->supported;
1424
b02fd9e3
MC		 1425 return 0;
1426}
1427
1428static void tg3_phy_start(struct tg3 *tp)
1429{
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
298cf9be 1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448}
1449
1450static void tg3_phy_stop(struct tg3 *tp)
1451{
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
298cf9be 1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1456}
1457
1458static void tg3_phy_fini(struct tg3 *tp)
1459{
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464}
1465
b2a5c19c
MC		 1466static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467{
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470}
1471
6833c043
MC		 1472static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473{
1474 u32 reg;
1475
a6435f3a
MC		 1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6833c043
MC		 1478 return;
1479
1480 reg = MII_TG3_MISC_SHDW_WREN |
1481 MII_TG3_MISC_SHDW_SCR5_SEL |
1482 MII_TG3_MISC_SHDW_SCR5_LPED |
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484 MII_TG3_MISC_SHDW_SCR5_SDTL |
1485 MII_TG3_MISC_SHDW_SCR5_C125OE;
1486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492 reg = MII_TG3_MISC_SHDW_WREN |
1493 MII_TG3_MISC_SHDW_APD_SEL |
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495 if (enable)
1496 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499}
1500
9ef8ca99
MC		 1501static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502{
1503 u32 phy;
1504
1505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507 return;
1508
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510 u32 ephy;
1511
1512 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514 ephy | MII_TG3_EPHY_SHADOW_EN);
1515 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516 if (enable)
1517 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518 else
1519 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521 }
1522 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523 }
1524 } else {
1525 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526 MII_TG3_AUXCTL_SHDWSEL_MISC;
1527 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531 else
1532 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533 phy |= MII_TG3_AUXCTL_MISC_WREN;
1534 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535 }
1536 }
1537}
1538
1da177e4
LT		 1539static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540{
1541 u32 val;
1542
1543 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544 return;
1545
1546 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549 (val | (1 << 15) | (1 << 4)));
1550}
1551
b2a5c19c
MC		 1552static void tg3_phy_apply_otp(struct tg3 *tp)
1553{
1554 u32 otp, phy;
1555
1556 if (!tp->phy_otp)
1557 return;
1558
1559 otp = tp->phy_otp;
1560
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564 MII_TG3_AUXCTL_ACTL_TX_6DB;
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589 /* Turn off SM_DSP clock. */
1590 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591 MII_TG3_AUXCTL_ACTL_TX_6DB;
1592 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593}
1594
1da177e4
LT		 1595static int tg3_wait_macro_done(struct tg3 *tp)
1596{
1597 int limit = 100;
1598
1599 while (limit--) {
1600 u32 tmp32;
1601
1602 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603 if ((tmp32 & 0x1000) == 0)
1604 break;
1605 }
1606 }
d4675b52 1607 if (limit < 0)
1da177e4
LT		 1608 return -EBUSY;
1609
1610 return 0;
1611}
1612
1613static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614{
1615 static const u32 test_pat[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620 };
1621 int chan;
1622
1623 for (chan = 0; chan < 4; chan++) {
1624 int i;
1625
1626 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627 (chan * 0x2000) | 0x0200);
1628 tg3_writephy(tp, 0x16, 0x0002);
1629
1630 for (i = 0; i < 6; i++)
1631 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632 test_pat[chan][i]);
1633
1634 tg3_writephy(tp, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641 (chan * 0x2000) | 0x0200);
1642 tg3_writephy(tp, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp)) {
1644 *resetp = 1;
1645 return -EBUSY;
1646 }
1647
1648 tg3_writephy(tp, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp)) {
1650 *resetp = 1;
1651 return -EBUSY;
1652 }
1653
1654 for (i = 0; i < 6; i += 2) {
1655 u32 low, high;
1656
1657 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659 tg3_wait_macro_done(tp)) {
1660 *resetp = 1;
1661 return -EBUSY;
1662 }
1663 low &= 0x7fff;
1664 high &= 0x000f;
1665 if (low != test_pat[chan][i] ||
1666 high != test_pat[chan][i+1]) {
1667 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671 return -EBUSY;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677}
1678
1679static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680{
1681 int chan;
1682
1683 for (chan = 0; chan < 4; chan++) {
1684 int i;
1685
1686 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687 (chan * 0x2000) | 0x0200);
1688 tg3_writephy(tp, 0x16, 0x0002);
1689 for (i = 0; i < 6; i++)
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691 tg3_writephy(tp, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp))
1693 return -EBUSY;
1694 }
1695
1696 return 0;
1697}
1698
1699static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700{
1701 u32 reg32, phy9_orig;
1702 int retries, do_phy_reset, err;
1703
1704 retries = 10;
1705 do_phy_reset = 1;
1706 do {
1707 if (do_phy_reset) {
1708 err = tg3_bmcr_reset(tp);
1709 if (err)
1710 return err;
1711 do_phy_reset = 0;
1712 }
1713
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716 continue;
1717
1718 reg32 |= 0x3000;
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp, MII_BMCR,
1723 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727 continue;
1728
1729 tg3_writephy(tp, MII_TG3_CTRL,
1730 (MII_TG3_CTRL_AS_MASTER |
1731 MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741 if (!err)
1742 break;
1743 } while (--retries);
1744
1745 err = tg3_phy_reset_chanpat(tp);
1746 if (err)
1747 return err;
1748
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753 tg3_writephy(tp, 0x16, 0x0000);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759 }
1760 else {
1761 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762 }
1763
1764 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767 reg32 &= ~0x3000;
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769 } else if (!err)
1770 err = -EBUSY;
1771
1772 return err;
1773}
1774
1775/* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1777 */
1778static int tg3_phy_reset(struct tg3 *tp)
1779{
b2a5c19c 1780 u32 cpmuctrl;
1da177e4
LT		 1781 u32 phy_status;
1782 int err;
1783
60189ddf
MC		 1784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785 u32 val;
1786
1787 val = tr32(GRC_MISC_CFG);
1788 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789 udelay(40);
1790 }
1da177e4
LT		 1791 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1792 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793 if (err != 0)
1794 return -EBUSY;
1795
c8e1e82b
MC		 1796 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797 netif_carrier_off(tp->dev);
1798 tg3_link_report(tp);
1799 }
1800
1da177e4
LT		 1801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804 err = tg3_phy_reset_5703_4_5(tp);
1805 if (err)
1806 return err;
1807 goto out;
1808 }
1809
b2a5c19c
MC		 1810 cpmuctrl = 0;
1811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815 tw32(TG3_CPMU_CTRL,
1816 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817 }
1818
1da177e4
LT		 1819 err = tg3_bmcr_reset(tp);
1820 if (err)
1821 return err;
1822
b2a5c19c
MC		 1823 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824 u32 phy;
1825
1826 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830 }
1831
bcb37f6c
MC		 1832 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1834 u32 val;
1835
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5) {
1839 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840 udelay(40);
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842 }
1843 }
1844
b2a5c19c
MC		 1845 tg3_phy_apply_otp(tp);
1846
6833c043
MC		 1847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848 tg3_phy_toggle_apd(tp, true);
1849 else
1850 tg3_phy_toggle_apd(tp, false);
1851
1da177e4
LT		 1852out:
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860 }
1861 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 tg3_writephy(tp, 0x1c, 0x8d68);
1864 }
1865 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874 }
c424cb24
MC		 1875 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1878 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880 tg3_writephy(tp, MII_TG3_TEST1,
1881 MII_TG3_TEST1_TRIM_EN | 0x4);
1882 } else
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1884 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885 }
1da177e4
LT		 1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1891 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1892 u32 phy_reg;
1893
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898 }
1899
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1902 */
0f893dc6 1903 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1904 u32 phy_reg;
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909 }
1910
715116a1 1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1912 /* adjust output voltage */
1913 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1914 }
1915
9ef8ca99 1916 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1917 tg3_phy_set_wirespeed(tp);
1918 return 0;
1919}
1920
1921static void tg3_frob_aux_power(struct tg3 *tp)
1922{
1923 struct tg3 *tp_peer = tp;
1924
9d26e213 1925 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1926 return;
1927
8c2dc7e1
MC		 1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930 struct net_device *dev_peer;
1931
1932 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1933 /* remove_one() may have been run on the peer. */
8c2dc7e1 1934 if (!dev_peer)
bc1c7567
MC		 1935 tp_peer = tp;
1936 else
1937 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1938 }
1939
1da177e4 1940 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1941 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1946 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947 (GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1),
1952 100);
5f0c4a3c
MC		 1953 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1954 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1956 GRC_LCLCTRL_GPIO_OE1 |
1957 GRC_LCLCTRL_GPIO_OE2 |
1958 GRC_LCLCTRL_GPIO_OUTPUT0 |
1959 GRC_LCLCTRL_GPIO_OUTPUT1 |
1960 tp->grc_local_ctrl;
1961 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1962
1963 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1964 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1965
1966 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1967 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 1968 } else {
1969 u32 no_gpio2;
dc56b7d4 1970 u32 grc_local_ctrl = 0;
1da177e4
LT		 1971
1972 if (tp_peer != tp &&
1973 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1974 return;
1975
dc56b7d4
MC		 1976 /* Workaround to prevent overdrawing Amps. */
1977 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1978 ASIC_REV_5714) {
1979 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1980 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1981 grc_local_ctrl, 100);
dc56b7d4
MC		 1982 }
1983
1da177e4
LT		 1984 /* On 5753 and variants, GPIO2 cannot be used. */
1985 no_gpio2 = tp->nic_sram_data_cfg &
1986 NIC_SRAM_DATA_CFG_NO_GPIO2;
1987
dc56b7d4 1988 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1989 GRC_LCLCTRL_GPIO_OE1 |
1990 GRC_LCLCTRL_GPIO_OE2 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1 |
1992 GRC_LCLCTRL_GPIO_OUTPUT2;
1993 if (no_gpio2) {
1994 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1995 GRC_LCLCTRL_GPIO_OUTPUT2);
1996 }
b401e9e2
MC		 1997 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1998 grc_local_ctrl, 100);
1da177e4
LT		 1999
2000 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2001
b401e9e2
MC		 2002 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2003 grc_local_ctrl, 100);
1da177e4
LT		 2004
2005 if (!no_gpio2) {
2006 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2007 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2008 grc_local_ctrl, 100);
1da177e4
LT		 2009 }
2010 }
2011 } else {
2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2013 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2014 if (tp_peer != tp &&
2015 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2016 return;
2017
b401e9e2
MC		 2018 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019 (GRC_LCLCTRL_GPIO_OE1 |
2020 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2021
b401e9e2
MC		 2022 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2023 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2024
b401e9e2
MC		 2025 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026 (GRC_LCLCTRL_GPIO_OE1 |
2027 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2028 }
2029 }
2030}
2031
e8f3f6ca
MC		 2032static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2033{
2034 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2035 return 1;
2036 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2037 if (speed != SPEED_10)
2038 return 1;
2039 } else if (speed == SPEED_10)
2040 return 1;
2041
2042 return 0;
2043}
2044
1da177e4
LT		 2045static int tg3_setup_phy(struct tg3 *, int);
2046
2047#define RESET_KIND_SHUTDOWN 0
2048#define RESET_KIND_INIT 1
2049#define RESET_KIND_SUSPEND 2
2050
2051static void tg3_write_sig_post_reset(struct tg3 *, int);
2052static int tg3_halt_cpu(struct tg3 *, u32);
2053
0a459aac 2054static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2055{
ce057f01
MC		 2056 u32 val;
2057
5129724a
MC		 2058 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2060 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2061 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2062
2063 sg_dig_ctrl |=
2064 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2065 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2066 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2067 }
3f7045c1 2068 return;
5129724a 2069 }
3f7045c1 2070
60189ddf 2071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2072 tg3_bmcr_reset(tp);
2073 val = tr32(GRC_MISC_CFG);
2074 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2075 udelay(40);
2076 return;
0a459aac 2077 } else if (do_low_power) {
715116a1
MC		 2078 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2079 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2080
2081 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2082 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2083 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2084 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2085 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2086 }
3f7045c1 2087
15c3b696
MC		 2088 /* The PHY should not be powered down on some chips because
2089 * of bugs.
2090 */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2093 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2094 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2095 return;
ce057f01 2096
bcb37f6c
MC		 2097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2098 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2099 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2100 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2101 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2102 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2103 }
2104
15c3b696
MC		 2105 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2106}
2107
ffbcfed4
MC		 2108/* tp->lock is held. */
2109static int tg3_nvram_lock(struct tg3 *tp)
2110{
2111 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2112 int i;
2113
2114 if (tp->nvram_lock_cnt == 0) {
2115 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2116 for (i = 0; i < 8000; i++) {
2117 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2118 break;
2119 udelay(20);
2120 }
2121 if (i == 8000) {
2122 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2123 return -ENODEV;
2124 }
2125 }
2126 tp->nvram_lock_cnt++;
2127 }
2128 return 0;
2129}
2130
2131/* tp->lock is held. */
2132static void tg3_nvram_unlock(struct tg3 *tp)
2133{
2134 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2135 if (tp->nvram_lock_cnt > 0)
2136 tp->nvram_lock_cnt--;
2137 if (tp->nvram_lock_cnt == 0)
2138 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2139 }
2140}
2141
2142/* tp->lock is held. */
2143static void tg3_enable_nvram_access(struct tg3 *tp)
2144{
2145 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2146 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2147 u32 nvaccess = tr32(NVRAM_ACCESS);
2148
2149 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2150 }
2151}
2152
2153/* tp->lock is held. */
2154static void tg3_disable_nvram_access(struct tg3 *tp)
2155{
2156 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2157 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2158 u32 nvaccess = tr32(NVRAM_ACCESS);
2159
2160 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2161 }
2162}
2163
2164static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2165 u32 offset, u32 *val)
2166{
2167 u32 tmp;
2168 int i;
2169
2170 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2171 return -EINVAL;
2172
2173 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2174 EEPROM_ADDR_DEVID_MASK |
2175 EEPROM_ADDR_READ);
2176 tw32(GRC_EEPROM_ADDR,
2177 tmp |
2178 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2179 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2180 EEPROM_ADDR_ADDR_MASK) |
2181 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2182
2183 for (i = 0; i < 1000; i++) {
2184 tmp = tr32(GRC_EEPROM_ADDR);
2185
2186 if (tmp & EEPROM_ADDR_COMPLETE)
2187 break;
2188 msleep(1);
2189 }
2190 if (!(tmp & EEPROM_ADDR_COMPLETE))
2191 return -EBUSY;
2192
2193 *val = tr32(GRC_EEPROM_DATA);
2194 return 0;
2195}
2196
2197#define NVRAM_CMD_TIMEOUT 10000
2198
2199static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2200{
2201 int i;
2202
2203 tw32(NVRAM_CMD, nvram_cmd);
2204 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2205 udelay(10);
2206 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2207 udelay(10);
2208 break;
2209 }
2210 }
2211
2212 if (i == NVRAM_CMD_TIMEOUT)
2213 return -EBUSY;
2214
2215 return 0;
2216}
2217
2218static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2219{
2220 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2221 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2222 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2223 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2224 (tp->nvram_jedecnum == JEDEC_ATMEL))
2225
2226 addr = ((addr / tp->nvram_pagesize) <<
2227 ATMEL_AT45DB0X1B_PAGE_POS) +
2228 (addr % tp->nvram_pagesize);
2229
2230 return addr;
2231}
2232
2233static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2234{
2235 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2236 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2237 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2238 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2239 (tp->nvram_jedecnum == JEDEC_ATMEL))
2240
2241 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2242 tp->nvram_pagesize) +
2243 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2244
2245 return addr;
2246}
2247
2248static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2249{
2250 int ret;
2251
2252 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2253 return tg3_nvram_read_using_eeprom(tp, offset, val);
2254
2255 offset = tg3_nvram_phys_addr(tp, offset);
2256
2257 if (offset > NVRAM_ADDR_MSK)
2258 return -EINVAL;
2259
2260 ret = tg3_nvram_lock(tp);
2261 if (ret)
2262 return ret;
2263
2264 tg3_enable_nvram_access(tp);
2265
2266 tw32(NVRAM_ADDR, offset);
2267 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2268 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2269
2270 if (ret == 0)
2271 *val = swab32(tr32(NVRAM_RDDATA));
2272
2273 tg3_disable_nvram_access(tp);
2274
2275 tg3_nvram_unlock(tp);
2276
2277 return ret;
2278}
2279
2280static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
2281{
2282 int err;
2283 u32 tmp;
2284
2285 err = tg3_nvram_read(tp, offset, &tmp);
2286 *val = swab32(tmp);
2287 return err;
2288}
2289
2290static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
2291{
2292 u32 v;
2293 int res = tg3_nvram_read(tp, offset, &v);
2294 if (!res)
2295 *val = cpu_to_le32(v);
2296 return res;
2297}
2298
3f007891
MC		 2299/* tp->lock is held. */
2300static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2301{
2302 u32 addr_high, addr_low;
2303 int i;
2304
2305 addr_high = ((tp->dev->dev_addr[0] << 8) |
2306 tp->dev->dev_addr[1]);
2307 addr_low = ((tp->dev->dev_addr[2] << 24) |
2308 (tp->dev->dev_addr[3] << 16) |
2309 (tp->dev->dev_addr[4] << 8) |
2310 (tp->dev->dev_addr[5] << 0));
2311 for (i = 0; i < 4; i++) {
2312 if (i == 1 && skip_mac_1)
2313 continue;
2314 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2315 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2316 }
2317
2318 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2319 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2320 for (i = 0; i < 12; i++) {
2321 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2322 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2323 }
2324 }
2325
2326 addr_high = (tp->dev->dev_addr[0] +
2327 tp->dev->dev_addr[1] +
2328 tp->dev->dev_addr[2] +
2329 tp->dev->dev_addr[3] +
2330 tp->dev->dev_addr[4] +
2331 tp->dev->dev_addr[5]) &
2332 TX_BACKOFF_SEED_MASK;
2333 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2334}
2335
bc1c7567 2336static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2337{
2338 u32 misc_host_ctrl;
0a459aac 2339 bool device_should_wake, do_low_power;
1da177e4
LT		 2340
2341 /* Make sure register accesses (indirect or otherwise)
2342 * will function correctly.
2343 */
2344 pci_write_config_dword(tp->pdev,
2345 TG3PCI_MISC_HOST_CTRL,
2346 tp->misc_host_ctrl);
2347
1da177e4 2348 switch (state) {
bc1c7567 2349 case PCI_D0:
12dac075
RW		 2350 pci_enable_wake(tp->pdev, state, false);
2351 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2352
9d26e213
MC		 2353 /* Switch out of Vaux if it is a NIC */
2354 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2355 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2356
2357 return 0;
2358
bc1c7567 2359 case PCI_D1:
bc1c7567 2360 case PCI_D2:
bc1c7567 2361 case PCI_D3hot:
1da177e4
LT		 2362 break;
2363
2364 default:
12dac075
RW		 2365 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2366 tp->dev->name, state);
1da177e4 2367 return -EINVAL;
855e1111 2368 }
5e7dfd0f
MC		 2369
2370 /* Restore the CLKREQ setting. */
2371 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2372 u16 lnkctl;
2373
2374 pci_read_config_word(tp->pdev,
2375 tp->pcie_cap + PCI_EXP_LNKCTL,
2376 &lnkctl);
2377 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2378 pci_write_config_word(tp->pdev,
2379 tp->pcie_cap + PCI_EXP_LNKCTL,
2380 lnkctl);
2381 }
2382
1da177e4
LT		 2383 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2384 tw32(TG3PCI_MISC_HOST_CTRL,
2385 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2386
05ac4cb7
MC		 2387 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2388 device_may_wakeup(&tp->pdev->dev) &&
2389 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2390
dd477003 2391 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2392 do_low_power = false;
b02fd9e3
MC		 2393 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2394 !tp->link_config.phy_is_low_power) {
2395 struct phy_device *phydev;
0a459aac 2396 u32 phyid, advertising;
b02fd9e3 2397
298cf9be 2398 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2399
2400 tp->link_config.phy_is_low_power = 1;
2401
2402 tp->link_config.orig_speed = phydev->speed;
2403 tp->link_config.orig_duplex = phydev->duplex;
2404 tp->link_config.orig_autoneg = phydev->autoneg;
2405 tp->link_config.orig_advertising = phydev->advertising;
2406
2407 advertising = ADVERTISED_TP |
2408 ADVERTISED_Pause |
2409 ADVERTISED_Autoneg |
2410 ADVERTISED_10baseT_Half;
2411
2412 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2413 device_should_wake) {
b02fd9e3
MC		 2414 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2415 advertising |=
2416 ADVERTISED_100baseT_Half |
2417 ADVERTISED_100baseT_Full |
2418 ADVERTISED_10baseT_Full;
2419 else
2420 advertising |= ADVERTISED_10baseT_Full;
2421 }
2422
2423 phydev->advertising = advertising;
2424
2425 phy_start_aneg(phydev);
0a459aac
MC		 2426
2427 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2428 if (phyid != TG3_PHY_ID_BCMAC131) {
2429 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2430 if (phyid == TG3_PHY_OUI_1 ||
2431 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2432 phyid == TG3_PHY_OUI_3)
2433 do_low_power = true;
2434 }
b02fd9e3 2435 }
dd477003 2436 } else {
2023276e 2437 do_low_power = true;
0a459aac 2438
dd477003
MC		 2439 if (tp->link_config.phy_is_low_power == 0) {
2440 tp->link_config.phy_is_low_power = 1;
2441 tp->link_config.orig_speed = tp->link_config.speed;
2442 tp->link_config.orig_duplex = tp->link_config.duplex;
2443 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2444 }
1da177e4 2445
dd477003
MC		 2446 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2447 tp->link_config.speed = SPEED_10;
2448 tp->link_config.duplex = DUPLEX_HALF;
2449 tp->link_config.autoneg = AUTONEG_ENABLE;
2450 tg3_setup_phy(tp, 0);
2451 }
1da177e4
LT		 2452 }
2453
3f007891
MC		 2454 __tg3_set_mac_addr(tp, 0);
2455
b5d3772c
MC		 2456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2457 u32 val;
2458
2459 val = tr32(GRC_VCPU_EXT_CTRL);
2460 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2461 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2462 int i;
2463 u32 val;
2464
2465 for (i = 0; i < 200; i++) {
2466 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2467 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2468 break;
2469 msleep(1);
2470 }
2471 }
a85feb8c
GZ		 2472 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2473 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2474 WOL_DRV_STATE_SHUTDOWN |
2475 WOL_DRV_WOL |
2476 WOL_SET_MAGIC_PKT);
6921d201 2477
05ac4cb7 2478 if (device_should_wake) {
1da177e4
LT		 2479 u32 mac_mode;
2480
2481 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2482 if (do_low_power) {
dd477003
MC		 2483 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2484 udelay(40);
2485 }
1da177e4 2486
3f7045c1
MC		 2487 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2488 mac_mode = MAC_MODE_PORT_MODE_GMII;
2489 else
2490 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2491
e8f3f6ca
MC		 2492 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2493 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2494 ASIC_REV_5700) {
2495 u32 speed = (tp->tg3_flags &
2496 TG3_FLAG_WOL_SPEED_100MB) ?
2497 SPEED_100 : SPEED_10;
2498 if (tg3_5700_link_polarity(tp, speed))
2499 mac_mode |= MAC_MODE_LINK_POLARITY;
2500 else
2501 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2502 }
1da177e4
LT		 2503 } else {
2504 mac_mode = MAC_MODE_PORT_MODE_TBI;
2505 }
2506
cbf46853 2507 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2508 tw32(MAC_LED_CTRL, tp->led_ctrl);
2509
05ac4cb7
MC		 2510 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2511 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2512 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2513 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2514 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2515 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2516
3bda1258
MC		 2517 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2518 mac_mode |= tp->mac_mode &
2519 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2520 if (mac_mode & MAC_MODE_APE_TX_EN)
2521 mac_mode |= MAC_MODE_TDE_ENABLE;
2522 }
2523
1da177e4
LT		 2524 tw32_f(MAC_MODE, mac_mode);
2525 udelay(100);
2526
2527 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2528 udelay(10);
2529 }
2530
2531 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2532 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2534 u32 base_val;
2535
2536 base_val = tp->pci_clock_ctrl;
2537 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2538 CLOCK_CTRL_TXCLK_DISABLE);
2539
b401e9e2
MC		 2540 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2541 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2542 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2543 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2544 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2545 /* do nothing */
85e94ced 2546 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2547 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2548 u32 newbits1, newbits2;
2549
2550 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2551 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2552 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2553 CLOCK_CTRL_TXCLK_DISABLE |
2554 CLOCK_CTRL_ALTCLK);
2555 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2556 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2557 newbits1 = CLOCK_CTRL_625_CORE;
2558 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2559 } else {
2560 newbits1 = CLOCK_CTRL_ALTCLK;
2561 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2562 }
2563
b401e9e2
MC		 2564 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2565 40);
1da177e4 2566
b401e9e2
MC		 2567 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2568 40);
1da177e4
LT		 2569
2570 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2571 u32 newbits3;
2572
2573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2575 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2576 CLOCK_CTRL_TXCLK_DISABLE |
2577 CLOCK_CTRL_44MHZ_CORE);
2578 } else {
2579 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2580 }
2581
b401e9e2
MC		 2582 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2583 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2584 }
2585 }
2586
05ac4cb7 2587 if (!(device_should_wake) &&
22435849 2588 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2589 tg3_power_down_phy(tp, do_low_power);
6921d201 2590
1da177e4
LT		 2591 tg3_frob_aux_power(tp);
2592
2593 /* Workaround for unstable PLL clock */
2594 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2595 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2596 u32 val = tr32(0x7d00);
2597
2598 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2599 tw32(0x7d00, val);
6921d201 2600 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2601 int err;
2602
2603 err = tg3_nvram_lock(tp);
1da177e4 2604 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2605 if (!err)
2606 tg3_nvram_unlock(tp);
6921d201 2607 }
1da177e4
LT		 2608 }
2609
bbadf503
MC		 2610 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2611
05ac4cb7 2612 if (device_should_wake)
12dac075
RW		 2613 pci_enable_wake(tp->pdev, state, true);
2614
1da177e4 2615 /* Finally, set the new power state. */
12dac075 2616 pci_set_power_state(tp->pdev, state);
1da177e4 2617
1da177e4
LT		 2618 return 0;
2619}
2620
1da177e4
LT		 2621static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2622{
2623 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2624 case MII_TG3_AUX_STAT_10HALF:
2625 *speed = SPEED_10;
2626 *duplex = DUPLEX_HALF;
2627 break;
2628
2629 case MII_TG3_AUX_STAT_10FULL:
2630 *speed = SPEED_10;
2631 *duplex = DUPLEX_FULL;
2632 break;
2633
2634 case MII_TG3_AUX_STAT_100HALF:
2635 *speed = SPEED_100;
2636 *duplex = DUPLEX_HALF;
2637 break;
2638
2639 case MII_TG3_AUX_STAT_100FULL:
2640 *speed = SPEED_100;
2641 *duplex = DUPLEX_FULL;
2642 break;
2643
2644 case MII_TG3_AUX_STAT_1000HALF:
2645 *speed = SPEED_1000;
2646 *duplex = DUPLEX_HALF;
2647 break;
2648
2649 case MII_TG3_AUX_STAT_1000FULL:
2650 *speed = SPEED_1000;
2651 *duplex = DUPLEX_FULL;
2652 break;
2653
2654 default:
715116a1
MC		 2655 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2656 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2657 SPEED_10;
2658 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2659 DUPLEX_HALF;
2660 break;
2661 }
1da177e4
LT		 2662 *speed = SPEED_INVALID;
2663 *duplex = DUPLEX_INVALID;
2664 break;
855e1111 2665 }
1da177e4
LT		 2666}
2667
2668static void tg3_phy_copper_begin(struct tg3 *tp)
2669{
2670 u32 new_adv;
2671 int i;
2672
2673 if (tp->link_config.phy_is_low_power) {
2674 /* Entering low power mode. Disable gigabit and
2675 * 100baseT advertisements.
2676 */
2677 tg3_writephy(tp, MII_TG3_CTRL, 0);
2678
2679 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2680 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2681 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2682 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2683
2684 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2685 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2686 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2687 tp->link_config.advertising &=
2688 ~(ADVERTISED_1000baseT_Half |
2689 ADVERTISED_1000baseT_Full);
2690
ba4d07a8 2691 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2692 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2693 new_adv |= ADVERTISE_10HALF;
2694 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2695 new_adv |= ADVERTISE_10FULL;
2696 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2697 new_adv |= ADVERTISE_100HALF;
2698 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2699 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2700
2701 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2702
1da177e4
LT		 2703 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2704
2705 if (tp->link_config.advertising &
2706 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2707 new_adv = 0;
2708 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2709 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2710 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2711 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2712 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2713 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2714 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2715 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2716 MII_TG3_CTRL_ENABLE_AS_MASTER);
2717 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2718 } else {
2719 tg3_writephy(tp, MII_TG3_CTRL, 0);
2720 }
2721 } else {
ba4d07a8
MC		 2722 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2723 new_adv |= ADVERTISE_CSMA;
2724
1da177e4
LT		 2725 /* Asking for a specific link mode. */
2726 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2727 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2728
2729 if (tp->link_config.duplex == DUPLEX_FULL)
2730 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2731 else
2732 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2733 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2734 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2735 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2736 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2737 } else {
1da177e4
LT		 2738 if (tp->link_config.speed == SPEED_100) {
2739 if (tp->link_config.duplex == DUPLEX_FULL)
2740 new_adv |= ADVERTISE_100FULL;
2741 else
2742 new_adv |= ADVERTISE_100HALF;
2743 } else {
2744 if (tp->link_config.duplex == DUPLEX_FULL)
2745 new_adv |= ADVERTISE_10FULL;
2746 else
2747 new_adv |= ADVERTISE_10HALF;
2748 }
2749 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2750
2751 new_adv = 0;
1da177e4 2752 }
ba4d07a8
MC		 2753
2754 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2755 }
2756
2757 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2758 tp->link_config.speed != SPEED_INVALID) {
2759 u32 bmcr, orig_bmcr;
2760
2761 tp->link_config.active_speed = tp->link_config.speed;
2762 tp->link_config.active_duplex = tp->link_config.duplex;
2763
2764 bmcr = 0;
2765 switch (tp->link_config.speed) {
2766 default:
2767 case SPEED_10:
2768 break;
2769
2770 case SPEED_100:
2771 bmcr |= BMCR_SPEED100;
2772 break;
2773
2774 case SPEED_1000:
2775 bmcr |= TG3_BMCR_SPEED1000;
2776 break;
855e1111 2777 }
1da177e4
LT		 2778
2779 if (tp->link_config.duplex == DUPLEX_FULL)
2780 bmcr |= BMCR_FULLDPLX;
2781
2782 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2783 (bmcr != orig_bmcr)) {
2784 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2785 for (i = 0; i < 1500; i++) {
2786 u32 tmp;
2787
2788 udelay(10);
2789 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2790 tg3_readphy(tp, MII_BMSR, &tmp))
2791 continue;
2792 if (!(tmp & BMSR_LSTATUS)) {
2793 udelay(40);
2794 break;
2795 }
2796 }
2797 tg3_writephy(tp, MII_BMCR, bmcr);
2798 udelay(40);
2799 }
2800 } else {
2801 tg3_writephy(tp, MII_BMCR,
2802 BMCR_ANENABLE | BMCR_ANRESTART);
2803 }
2804}
2805
2806static int tg3_init_5401phy_dsp(struct tg3 *tp)
2807{
2808 int err;
2809
2810 /* Turn off tap power management. */
2811 /* Set Extended packet length bit */
2812 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2813
2814 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2815 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2816
2817 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2818 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2819
2820 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2821 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2822
2823 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2824 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2825
2826 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2827 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2828
2829 udelay(40);
2830
2831 return err;
2832}
2833
3600d918 2834static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2835{
3600d918
MC		 2836 u32 adv_reg, all_mask = 0;
2837
2838 if (mask & ADVERTISED_10baseT_Half)
2839 all_mask |= ADVERTISE_10HALF;
2840 if (mask & ADVERTISED_10baseT_Full)
2841 all_mask |= ADVERTISE_10FULL;
2842 if (mask & ADVERTISED_100baseT_Half)
2843 all_mask |= ADVERTISE_100HALF;
2844 if (mask & ADVERTISED_100baseT_Full)
2845 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2846
2847 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2848 return 0;
2849
1da177e4
LT		 2850 if ((adv_reg & all_mask) != all_mask)
2851 return 0;
2852 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2853 u32 tg3_ctrl;
2854
3600d918
MC		 2855 all_mask = 0;
2856 if (mask & ADVERTISED_1000baseT_Half)
2857 all_mask |= ADVERTISE_1000HALF;
2858 if (mask & ADVERTISED_1000baseT_Full)
2859 all_mask |= ADVERTISE_1000FULL;
2860
1da177e4
LT		 2861 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2862 return 0;
2863
1da177e4
LT		 2864 if ((tg3_ctrl & all_mask) != all_mask)
2865 return 0;
2866 }
2867 return 1;
2868}
2869
ef167e27
MC		 2870static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2871{
2872 u32 curadv, reqadv;
2873
2874 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2875 return 1;
2876
2877 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2878 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2879
2880 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2881 if (curadv != reqadv)
2882 return 0;
2883
2884 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2885 tg3_readphy(tp, MII_LPA, rmtadv);
2886 } else {
2887 /* Reprogram the advertisement register, even if it
2888 * does not affect the current link. If the link
2889 * gets renegotiated in the future, we can save an
2890 * additional renegotiation cycle by advertising
2891 * it correctly in the first place.
2892 */
2893 if (curadv != reqadv) {
2894 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2895 ADVERTISE_PAUSE_ASYM);
2896 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2897 }
2898 }
2899
2900 return 1;
2901}
2902
1da177e4
LT		 2903static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2904{
2905 int current_link_up;
2906 u32 bmsr, dummy;
ef167e27 2907 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2908 u16 current_speed;
2909 u8 current_duplex;
2910 int i, err;
2911
2912 tw32(MAC_EVENT, 0);
2913
2914 tw32_f(MAC_STATUS,
2915 (MAC_STATUS_SYNC_CHANGED |
2916 MAC_STATUS_CFG_CHANGED |
2917 MAC_STATUS_MI_COMPLETION |
2918 MAC_STATUS_LNKSTATE_CHANGED));
2919 udelay(40);
2920
8ef21428
MC		 2921 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2922 tw32_f(MAC_MI_MODE,
2923 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2924 udelay(80);
2925 }
1da177e4
LT		 2926
2927 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2928
2929 /* Some third-party PHYs need to be reset on link going
2930 * down.
2931 */
2932 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2935 netif_carrier_ok(tp->dev)) {
2936 tg3_readphy(tp, MII_BMSR, &bmsr);
2937 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2938 !(bmsr & BMSR_LSTATUS))
2939 force_reset = 1;
2940 }
2941 if (force_reset)
2942 tg3_phy_reset(tp);
2943
2944 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2945 tg3_readphy(tp, MII_BMSR, &bmsr);
2946 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2947 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2948 bmsr = 0;
2949
2950 if (!(bmsr & BMSR_LSTATUS)) {
2951 err = tg3_init_5401phy_dsp(tp);
2952 if (err)
2953 return err;
2954
2955 tg3_readphy(tp, MII_BMSR, &bmsr);
2956 for (i = 0; i < 1000; i++) {
2957 udelay(10);
2958 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2959 (bmsr & BMSR_LSTATUS)) {
2960 udelay(40);
2961 break;
2962 }
2963 }
2964
2965 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2966 !(bmsr & BMSR_LSTATUS) &&
2967 tp->link_config.active_speed == SPEED_1000) {
2968 err = tg3_phy_reset(tp);
2969 if (!err)
2970 err = tg3_init_5401phy_dsp(tp);
2971 if (err)
2972 return err;
2973 }
2974 }
2975 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2976 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2977 /* 5701 {A0,B0} CRC bug workaround */
2978 tg3_writephy(tp, 0x15, 0x0a75);
2979 tg3_writephy(tp, 0x1c, 0x8c68);
2980 tg3_writephy(tp, 0x1c, 0x8d68);
2981 tg3_writephy(tp, 0x1c, 0x8c68);
2982 }
2983
2984 /* Clear pending interrupts... */
2985 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2986 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2987
2988 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2989 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2990 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2991 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2992
2993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2995 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2996 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2997 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2998 else
2999 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3000 }
3001
3002 current_link_up = 0;
3003 current_speed = SPEED_INVALID;
3004 current_duplex = DUPLEX_INVALID;
3005
3006 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3007 u32 val;
3008
3009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3010 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3011 if (!(val & (1 << 10))) {
3012 val |= (1 << 10);
3013 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3014 goto relink;
3015 }
3016 }
3017
3018 bmsr = 0;
3019 for (i = 0; i < 100; i++) {
3020 tg3_readphy(tp, MII_BMSR, &bmsr);
3021 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3022 (bmsr & BMSR_LSTATUS))
3023 break;
3024 udelay(40);
3025 }
3026
3027 if (bmsr & BMSR_LSTATUS) {
3028 u32 aux_stat, bmcr;
3029
3030 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3031 for (i = 0; i < 2000; i++) {
3032 udelay(10);
3033 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3034 aux_stat)
3035 break;
3036 }
3037
3038 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3039 &current_speed,
3040 &current_duplex);
3041
3042 bmcr = 0;
3043 for (i = 0; i < 200; i++) {
3044 tg3_readphy(tp, MII_BMCR, &bmcr);
3045 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3046 continue;
3047 if (bmcr && bmcr != 0x7fff)
3048 break;
3049 udelay(10);
3050 }
3051
ef167e27
MC		 3052 lcl_adv = 0;
3053 rmt_adv = 0;
1da177e4 3054
ef167e27
MC		 3055 tp->link_config.active_speed = current_speed;
3056 tp->link_config.active_duplex = current_duplex;
3057
3058 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3059 if ((bmcr & BMCR_ANENABLE) &&
3060 tg3_copper_is_advertising_all(tp,
3061 tp->link_config.advertising)) {
3062 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3063 &rmt_adv))
3064 current_link_up = 1;
1da177e4
LT		 3065 }
3066 } else {
3067 if (!(bmcr & BMCR_ANENABLE) &&
3068 tp->link_config.speed == current_speed &&
ef167e27
MC		 3069 tp->link_config.duplex == current_duplex &&
3070 tp->link_config.flowctrl ==
3071 tp->link_config.active_flowctrl) {
1da177e4 3072 current_link_up = 1;
1da177e4
LT		 3073 }
3074 }
3075
ef167e27
MC		 3076 if (current_link_up == 1 &&
3077 tp->link_config.active_duplex == DUPLEX_FULL)
3078 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3079 }
3080
1da177e4 3081relink:
6921d201 3082 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3083 u32 tmp;
3084
3085 tg3_phy_copper_begin(tp);
3086
3087 tg3_readphy(tp, MII_BMSR, &tmp);
3088 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3089 (tmp & BMSR_LSTATUS))
3090 current_link_up = 1;
3091 }
3092
3093 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3094 if (current_link_up == 1) {
3095 if (tp->link_config.active_speed == SPEED_100 ||
3096 tp->link_config.active_speed == SPEED_10)
3097 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3098 else
3099 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3100 } else
3101 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3102
3103 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3104 if (tp->link_config.active_duplex == DUPLEX_HALF)
3105 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3106
1da177e4 3107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3108 if (current_link_up == 1 &&
3109 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3110 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3111 else
3112 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3113 }
3114
3115 /* ??? Without this setting Netgear GA302T PHY does not
3116 * ??? send/receive packets...
3117 */
3118 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3119 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3120 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3121 tw32_f(MAC_MI_MODE, tp->mi_mode);
3122 udelay(80);
3123 }
3124
3125 tw32_f(MAC_MODE, tp->mac_mode);
3126 udelay(40);
3127
3128 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3129 /* Polled via timer. */
3130 tw32_f(MAC_EVENT, 0);
3131 } else {
3132 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3133 }
3134 udelay(40);
3135
3136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3137 current_link_up == 1 &&
3138 tp->link_config.active_speed == SPEED_1000 &&
3139 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3140 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3141 udelay(120);
3142 tw32_f(MAC_STATUS,
3143 (MAC_STATUS_SYNC_CHANGED |
3144 MAC_STATUS_CFG_CHANGED));
3145 udelay(40);
3146 tg3_write_mem(tp,
3147 NIC_SRAM_FIRMWARE_MBOX,
3148 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3149 }
3150
5e7dfd0f
MC		 3151 /* Prevent send BD corruption. */
3152 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3153 u16 oldlnkctl, newlnkctl;
3154
3155 pci_read_config_word(tp->pdev,
3156 tp->pcie_cap + PCI_EXP_LNKCTL,
3157 &oldlnkctl);
3158 if (tp->link_config.active_speed == SPEED_100 ||
3159 tp->link_config.active_speed == SPEED_10)
3160 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3161 else
3162 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3163 if (newlnkctl != oldlnkctl)
3164 pci_write_config_word(tp->pdev,
3165 tp->pcie_cap + PCI_EXP_LNKCTL,
3166 newlnkctl);
3167 }
3168
1da177e4
LT		 3169 if (current_link_up != netif_carrier_ok(tp->dev)) {
3170 if (current_link_up)
3171 netif_carrier_on(tp->dev);
3172 else
3173 netif_carrier_off(tp->dev);
3174 tg3_link_report(tp);
3175 }
3176
3177 return 0;
3178}
3179
3180struct tg3_fiber_aneginfo {
3181 int state;
3182#define ANEG_STATE_UNKNOWN 0
3183#define ANEG_STATE_AN_ENABLE 1
3184#define ANEG_STATE_RESTART_INIT 2
3185#define ANEG_STATE_RESTART 3
3186#define ANEG_STATE_DISABLE_LINK_OK 4
3187#define ANEG_STATE_ABILITY_DETECT_INIT 5
3188#define ANEG_STATE_ABILITY_DETECT 6
3189#define ANEG_STATE_ACK_DETECT_INIT 7
3190#define ANEG_STATE_ACK_DETECT 8
3191#define ANEG_STATE_COMPLETE_ACK_INIT 9
3192#define ANEG_STATE_COMPLETE_ACK 10
3193#define ANEG_STATE_IDLE_DETECT_INIT 11
3194#define ANEG_STATE_IDLE_DETECT 12
3195#define ANEG_STATE_LINK_OK 13
3196#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3197#define ANEG_STATE_NEXT_PAGE_WAIT 15
3198
3199 u32 flags;
3200#define MR_AN_ENABLE 0x00000001
3201#define MR_RESTART_AN 0x00000002
3202#define MR_AN_COMPLETE 0x00000004
3203#define MR_PAGE_RX 0x00000008
3204#define MR_NP_LOADED 0x00000010
3205#define MR_TOGGLE_TX 0x00000020
3206#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3207#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3208#define MR_LP_ADV_SYM_PAUSE 0x00000100
3209#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3210#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3211#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3212#define MR_LP_ADV_NEXT_PAGE 0x00001000
3213#define MR_TOGGLE_RX 0x00002000
3214#define MR_NP_RX 0x00004000
3215
3216#define MR_LINK_OK 0x80000000
3217
3218 unsigned long link_time, cur_time;
3219
3220 u32 ability_match_cfg;
3221 int ability_match_count;
3222
3223 char ability_match, idle_match, ack_match;
3224
3225 u32 txconfig, rxconfig;
3226#define ANEG_CFG_NP 0x00000080
3227#define ANEG_CFG_ACK 0x00000040
3228#define ANEG_CFG_RF2 0x00000020
3229#define ANEG_CFG_RF1 0x00000010
3230#define ANEG_CFG_PS2 0x00000001
3231#define ANEG_CFG_PS1 0x00008000
3232#define ANEG_CFG_HD 0x00004000
3233#define ANEG_CFG_FD 0x00002000
3234#define ANEG_CFG_INVAL 0x00001f06
3235
3236};
3237#define ANEG_OK 0
3238#define ANEG_DONE 1
3239#define ANEG_TIMER_ENAB 2
3240#define ANEG_FAILED -1
3241
3242#define ANEG_STATE_SETTLE_TIME 10000
3243
3244static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3245 struct tg3_fiber_aneginfo *ap)
3246{
5be73b47 3247 u16 flowctrl;
1da177e4
LT		 3248 unsigned long delta;
3249 u32 rx_cfg_reg;
3250 int ret;
3251
3252 if (ap->state == ANEG_STATE_UNKNOWN) {
3253 ap->rxconfig = 0;
3254 ap->link_time = 0;
3255 ap->cur_time = 0;
3256 ap->ability_match_cfg = 0;
3257 ap->ability_match_count = 0;
3258 ap->ability_match = 0;
3259 ap->idle_match = 0;
3260 ap->ack_match = 0;
3261 }
3262 ap->cur_time++;
3263
3264 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3265 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3266
3267 if (rx_cfg_reg != ap->ability_match_cfg) {
3268 ap->ability_match_cfg = rx_cfg_reg;
3269 ap->ability_match = 0;
3270 ap->ability_match_count = 0;
3271 } else {
3272 if (++ap->ability_match_count > 1) {
3273 ap->ability_match = 1;
3274 ap->ability_match_cfg = rx_cfg_reg;
3275 }
3276 }
3277 if (rx_cfg_reg & ANEG_CFG_ACK)
3278 ap->ack_match = 1;
3279 else
3280 ap->ack_match = 0;
3281
3282 ap->idle_match = 0;
3283 } else {
3284 ap->idle_match = 1;
3285 ap->ability_match_cfg = 0;
3286 ap->ability_match_count = 0;
3287 ap->ability_match = 0;
3288 ap->ack_match = 0;
3289
3290 rx_cfg_reg = 0;
3291 }
3292
3293 ap->rxconfig = rx_cfg_reg;
3294 ret = ANEG_OK;
3295
3296 switch(ap->state) {
3297 case ANEG_STATE_UNKNOWN:
3298 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3299 ap->state = ANEG_STATE_AN_ENABLE;
3300
3301 /* fallthru */
3302 case ANEG_STATE_AN_ENABLE:
3303 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3304 if (ap->flags & MR_AN_ENABLE) {
3305 ap->link_time = 0;
3306 ap->cur_time = 0;
3307 ap->ability_match_cfg = 0;
3308 ap->ability_match_count = 0;
3309 ap->ability_match = 0;
3310 ap->idle_match = 0;
3311 ap->ack_match = 0;
3312
3313 ap->state = ANEG_STATE_RESTART_INIT;
3314 } else {
3315 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3316 }
3317 break;
3318
3319 case ANEG_STATE_RESTART_INIT:
3320 ap->link_time = ap->cur_time;
3321 ap->flags &= ~(MR_NP_LOADED);
3322 ap->txconfig = 0;
3323 tw32(MAC_TX_AUTO_NEG, 0);
3324 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3325 tw32_f(MAC_MODE, tp->mac_mode);
3326 udelay(40);
3327
3328 ret = ANEG_TIMER_ENAB;
3329 ap->state = ANEG_STATE_RESTART;
3330
3331 /* fallthru */
3332 case ANEG_STATE_RESTART:
3333 delta = ap->cur_time - ap->link_time;
3334 if (delta > ANEG_STATE_SETTLE_TIME) {
3335 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3336 } else {
3337 ret = ANEG_TIMER_ENAB;
3338 }
3339 break;
3340
3341 case ANEG_STATE_DISABLE_LINK_OK:
3342 ret = ANEG_DONE;
3343 break;
3344
3345 case ANEG_STATE_ABILITY_DETECT_INIT:
3346 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3347 ap->txconfig = ANEG_CFG_FD;
3348 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3349 if (flowctrl & ADVERTISE_1000XPAUSE)
3350 ap->txconfig |= ANEG_CFG_PS1;
3351 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3352 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3353 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3354 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3355 tw32_f(MAC_MODE, tp->mac_mode);
3356 udelay(40);
3357
3358 ap->state = ANEG_STATE_ABILITY_DETECT;
3359 break;
3360
3361 case ANEG_STATE_ABILITY_DETECT:
3362 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3363 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3364 }
3365 break;
3366
3367 case ANEG_STATE_ACK_DETECT_INIT:
3368 ap->txconfig |= ANEG_CFG_ACK;
3369 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3370 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3371 tw32_f(MAC_MODE, tp->mac_mode);
3372 udelay(40);
3373
3374 ap->state = ANEG_STATE_ACK_DETECT;
3375
3376 /* fallthru */
3377 case ANEG_STATE_ACK_DETECT:
3378 if (ap->ack_match != 0) {
3379 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3380 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3381 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3382 } else {
3383 ap->state = ANEG_STATE_AN_ENABLE;
3384 }
3385 } else if (ap->ability_match != 0 &&
3386 ap->rxconfig == 0) {
3387 ap->state = ANEG_STATE_AN_ENABLE;
3388 }
3389 break;
3390
3391 case ANEG_STATE_COMPLETE_ACK_INIT:
3392 if (ap->rxconfig & ANEG_CFG_INVAL) {
3393 ret = ANEG_FAILED;
3394 break;
3395 }
3396 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3397 MR_LP_ADV_HALF_DUPLEX |
3398 MR_LP_ADV_SYM_PAUSE |
3399 MR_LP_ADV_ASYM_PAUSE |
3400 MR_LP_ADV_REMOTE_FAULT1 |
3401 MR_LP_ADV_REMOTE_FAULT2 |
3402 MR_LP_ADV_NEXT_PAGE |
3403 MR_TOGGLE_RX |
3404 MR_NP_RX);
3405 if (ap->rxconfig & ANEG_CFG_FD)
3406 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3407 if (ap->rxconfig & ANEG_CFG_HD)
3408 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3409 if (ap->rxconfig & ANEG_CFG_PS1)
3410 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3411 if (ap->rxconfig & ANEG_CFG_PS2)
3412 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3413 if (ap->rxconfig & ANEG_CFG_RF1)
3414 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3415 if (ap->rxconfig & ANEG_CFG_RF2)
3416 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3417 if (ap->rxconfig & ANEG_CFG_NP)
3418 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3419
3420 ap->link_time = ap->cur_time;
3421
3422 ap->flags ^= (MR_TOGGLE_TX);
3423 if (ap->rxconfig & 0x0008)
3424 ap->flags |= MR_TOGGLE_RX;
3425 if (ap->rxconfig & ANEG_CFG_NP)
3426 ap->flags |= MR_NP_RX;
3427 ap->flags |= MR_PAGE_RX;
3428
3429 ap->state = ANEG_STATE_COMPLETE_ACK;
3430 ret = ANEG_TIMER_ENAB;
3431 break;
3432
3433 case ANEG_STATE_COMPLETE_ACK:
3434 if (ap->ability_match != 0 &&
3435 ap->rxconfig == 0) {
3436 ap->state = ANEG_STATE_AN_ENABLE;
3437 break;
3438 }
3439 delta = ap->cur_time - ap->link_time;
3440 if (delta > ANEG_STATE_SETTLE_TIME) {
3441 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3442 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3443 } else {
3444 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3445 !(ap->flags & MR_NP_RX)) {
3446 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3447 } else {
3448 ret = ANEG_FAILED;
3449 }
3450 }
3451 }
3452 break;
3453
3454 case ANEG_STATE_IDLE_DETECT_INIT:
3455 ap->link_time = ap->cur_time;
3456 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3457 tw32_f(MAC_MODE, tp->mac_mode);
3458 udelay(40);
3459
3460 ap->state = ANEG_STATE_IDLE_DETECT;
3461 ret = ANEG_TIMER_ENAB;
3462 break;
3463
3464 case ANEG_STATE_IDLE_DETECT:
3465 if (ap->ability_match != 0 &&
3466 ap->rxconfig == 0) {
3467 ap->state = ANEG_STATE_AN_ENABLE;
3468 break;
3469 }
3470 delta = ap->cur_time - ap->link_time;
3471 if (delta > ANEG_STATE_SETTLE_TIME) {
3472 /* XXX another gem from the Broadcom driver :( */
3473 ap->state = ANEG_STATE_LINK_OK;
3474 }
3475 break;
3476
3477 case ANEG_STATE_LINK_OK:
3478 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3479 ret = ANEG_DONE;
3480 break;
3481
3482 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3483 /* ??? unimplemented */
3484 break;
3485
3486 case ANEG_STATE_NEXT_PAGE_WAIT:
3487 /* ??? unimplemented */
3488 break;
3489
3490 default:
3491 ret = ANEG_FAILED;
3492 break;
855e1111 3493 }
1da177e4
LT		 3494
3495 return ret;
3496}
3497
5be73b47 3498static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3499{
3500 int res = 0;
3501 struct tg3_fiber_aneginfo aninfo;
3502 int status = ANEG_FAILED;
3503 unsigned int tick;
3504 u32 tmp;
3505
3506 tw32_f(MAC_TX_AUTO_NEG, 0);
3507
3508 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3509 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3510 udelay(40);
3511
3512 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3513 udelay(40);
3514
3515 memset(&aninfo, 0, sizeof(aninfo));
3516 aninfo.flags |= MR_AN_ENABLE;
3517 aninfo.state = ANEG_STATE_UNKNOWN;
3518 aninfo.cur_time = 0;
3519 tick = 0;
3520 while (++tick < 195000) {
3521 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3522 if (status == ANEG_DONE || status == ANEG_FAILED)
3523 break;
3524
3525 udelay(1);
3526 }
3527
3528 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3529 tw32_f(MAC_MODE, tp->mac_mode);
3530 udelay(40);
3531
5be73b47
MC		 3532 *txflags = aninfo.txconfig;
3533 *rxflags = aninfo.flags;
1da177e4
LT		 3534
3535 if (status == ANEG_DONE &&
3536 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3537 MR_LP_ADV_FULL_DUPLEX)))
3538 res = 1;
3539
3540 return res;
3541}
3542
3543static void tg3_init_bcm8002(struct tg3 *tp)
3544{
3545 u32 mac_status = tr32(MAC_STATUS);
3546 int i;
3547
3548 /* Reset when initting first time or we have a link. */
3549 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3550 !(mac_status & MAC_STATUS_PCS_SYNCED))
3551 return;
3552
3553 /* Set PLL lock range. */
3554 tg3_writephy(tp, 0x16, 0x8007);
3555
3556 /* SW reset */
3557 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3558
3559 /* Wait for reset to complete. */
3560 /* XXX schedule_timeout() ... */
3561 for (i = 0; i < 500; i++)
3562 udelay(10);
3563
3564 /* Config mode; select PMA/Ch 1 regs. */
3565 tg3_writephy(tp, 0x10, 0x8411);
3566
3567 /* Enable auto-lock and comdet, select txclk for tx. */
3568 tg3_writephy(tp, 0x11, 0x0a10);
3569
3570 tg3_writephy(tp, 0x18, 0x00a0);
3571 tg3_writephy(tp, 0x16, 0x41ff);
3572
3573 /* Assert and deassert POR. */
3574 tg3_writephy(tp, 0x13, 0x0400);
3575 udelay(40);
3576 tg3_writephy(tp, 0x13, 0x0000);
3577
3578 tg3_writephy(tp, 0x11, 0x0a50);
3579 udelay(40);
3580 tg3_writephy(tp, 0x11, 0x0a10);
3581
3582 /* Wait for signal to stabilize */
3583 /* XXX schedule_timeout() ... */
3584 for (i = 0; i < 15000; i++)
3585 udelay(10);
3586
3587 /* Deselect the channel register so we can read the PHYID
3588 * later.
3589 */
3590 tg3_writephy(tp, 0x10, 0x8011);
3591}
3592
3593static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3594{
82cd3d11 3595 u16 flowctrl;
1da177e4
LT		 3596 u32 sg_dig_ctrl, sg_dig_status;
3597 u32 serdes_cfg, expected_sg_dig_ctrl;
3598 int workaround, port_a;
3599 int current_link_up;
3600
3601 serdes_cfg = 0;
3602 expected_sg_dig_ctrl = 0;
3603 workaround = 0;
3604 port_a = 1;
3605 current_link_up = 0;
3606
3607 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3608 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3609 workaround = 1;
3610 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3611 port_a = 0;
3612
3613 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3614 /* preserve bits 20-23 for voltage regulator */
3615 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3616 }
3617
3618 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3619
3620 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3621 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3622 if (workaround) {
3623 u32 val = serdes_cfg;
3624
3625 if (port_a)
3626 val |= 0xc010000;
3627 else
3628 val |= 0x4010000;
3629 tw32_f(MAC_SERDES_CFG, val);
3630 }
c98f6e3b
MC		 3631
3632 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3633 }
3634 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3635 tg3_setup_flow_control(tp, 0, 0);
3636 current_link_up = 1;
3637 }
3638 goto out;
3639 }
3640
3641 /* Want auto-negotiation. */
c98f6e3b 3642 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3643
82cd3d11
MC		 3644 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3645 if (flowctrl & ADVERTISE_1000XPAUSE)
3646 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3647 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3648 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3649
3650 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3651 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3652 tp->serdes_counter &&
3653 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3654 MAC_STATUS_RCVD_CFG)) ==
3655 MAC_STATUS_PCS_SYNCED)) {
3656 tp->serdes_counter--;
3657 current_link_up = 1;
3658 goto out;
3659 }
3660restart_autoneg:
1da177e4
LT		 3661 if (workaround)
3662 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3663 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3664 udelay(5);
3665 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3666
3d3ebe74
MC		 3667 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3668 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3669 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3670 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3671 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3672 mac_status = tr32(MAC_STATUS);
3673
c98f6e3b 3674 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3675 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3676 u32 local_adv = 0, remote_adv = 0;
3677
3678 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3679 local_adv |= ADVERTISE_1000XPAUSE;
3680 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3681 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3682
c98f6e3b 3683 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3684 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3685 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3686 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3687
3688 tg3_setup_flow_control(tp, local_adv, remote_adv);
3689 current_link_up = 1;
3d3ebe74
MC		 3690 tp->serdes_counter = 0;
3691 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3692 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3693 if (tp->serdes_counter)
3694 tp->serdes_counter--;
1da177e4
LT		 3695 else {
3696 if (workaround) {
3697 u32 val = serdes_cfg;
3698
3699 if (port_a)
3700 val |= 0xc010000;
3701 else
3702 val |= 0x4010000;
3703
3704 tw32_f(MAC_SERDES_CFG, val);
3705 }
3706
c98f6e3b 3707 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3708 udelay(40);
3709
3710 /* Link parallel detection - link is up */
3711 /* only if we have PCS_SYNC and not */
3712 /* receiving config code words */
3713 mac_status = tr32(MAC_STATUS);
3714 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3715 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3716 tg3_setup_flow_control(tp, 0, 0);
3717 current_link_up = 1;
3d3ebe74
MC		 3718 tp->tg3_flags2 |=
3719 TG3_FLG2_PARALLEL_DETECT;
3720 tp->serdes_counter =
3721 SERDES_PARALLEL_DET_TIMEOUT;
3722 } else
3723 goto restart_autoneg;
1da177e4
LT		 3724 }
3725 }
3d3ebe74
MC		 3726 } else {
3727 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3728 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3729 }
3730
3731out:
3732 return current_link_up;
3733}
3734
3735static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3736{
3737 int current_link_up = 0;
3738
5cf64b8a 3739 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3740 goto out;
1da177e4
LT		 3741
3742 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3743 u32 txflags, rxflags;
1da177e4 3744 int i;
6aa20a22 3745
5be73b47
MC		 3746 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3747 u32 local_adv = 0, remote_adv = 0;
1da177e4 3748
5be73b47
MC		 3749 if (txflags & ANEG_CFG_PS1)
3750 local_adv |= ADVERTISE_1000XPAUSE;
3751 if (txflags & ANEG_CFG_PS2)
3752 local_adv |= ADVERTISE_1000XPSE_ASYM;
3753
3754 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3755 remote_adv |= LPA_1000XPAUSE;
3756 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3757 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3758
3759 tg3_setup_flow_control(tp, local_adv, remote_adv);
3760
1da177e4
LT		 3761 current_link_up = 1;
3762 }
3763 for (i = 0; i < 30; i++) {
3764 udelay(20);
3765 tw32_f(MAC_STATUS,
3766 (MAC_STATUS_SYNC_CHANGED |
3767 MAC_STATUS_CFG_CHANGED));
3768 udelay(40);
3769 if ((tr32(MAC_STATUS) &
3770 (MAC_STATUS_SYNC_CHANGED |
3771 MAC_STATUS_CFG_CHANGED)) == 0)
3772 break;
3773 }
3774
3775 mac_status = tr32(MAC_STATUS);
3776 if (current_link_up == 0 &&
3777 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3778 !(mac_status & MAC_STATUS_RCVD_CFG))
3779 current_link_up = 1;
3780 } else {
5be73b47
MC		 3781 tg3_setup_flow_control(tp, 0, 0);
3782
1da177e4
LT		 3783 /* Forcing 1000FD link up. */
3784 current_link_up = 1;
1da177e4
LT		 3785
3786 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3787 udelay(40);
e8f3f6ca
MC		 3788
3789 tw32_f(MAC_MODE, tp->mac_mode);
3790 udelay(40);
1da177e4
LT		 3791 }
3792
3793out:
3794 return current_link_up;
3795}
3796
3797static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3798{
3799 u32 orig_pause_cfg;
3800 u16 orig_active_speed;
3801 u8 orig_active_duplex;
3802 u32 mac_status;
3803 int current_link_up;
3804 int i;
3805
8d018621 3806 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3807 orig_active_speed = tp->link_config.active_speed;
3808 orig_active_duplex = tp->link_config.active_duplex;
3809
3810 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3811 netif_carrier_ok(tp->dev) &&
3812 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3813 mac_status = tr32(MAC_STATUS);
3814 mac_status &= (MAC_STATUS_PCS_SYNCED |
3815 MAC_STATUS_SIGNAL_DET |
3816 MAC_STATUS_CFG_CHANGED |
3817 MAC_STATUS_RCVD_CFG);
3818 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3819 MAC_STATUS_SIGNAL_DET)) {
3820 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3821 MAC_STATUS_CFG_CHANGED));
3822 return 0;
3823 }
3824 }
3825
3826 tw32_f(MAC_TX_AUTO_NEG, 0);
3827
3828 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3829 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3830 tw32_f(MAC_MODE, tp->mac_mode);
3831 udelay(40);
3832
3833 if (tp->phy_id == PHY_ID_BCM8002)
3834 tg3_init_bcm8002(tp);
3835
3836 /* Enable link change event even when serdes polling. */
3837 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3838 udelay(40);
3839
3840 current_link_up = 0;
3841 mac_status = tr32(MAC_STATUS);
3842
3843 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3844 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3845 else
3846 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3847
1da177e4
LT		 3848 tp->hw_status->status =
3849 (SD_STATUS_UPDATED |
3850 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3851
3852 for (i = 0; i < 100; i++) {
3853 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3854 MAC_STATUS_CFG_CHANGED));
3855 udelay(5);
3856 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3857 MAC_STATUS_CFG_CHANGED |
3858 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3859 break;
3860 }
3861
3862 mac_status = tr32(MAC_STATUS);
3863 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3864 current_link_up = 0;
3d3ebe74
MC		 3865 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3866 tp->serdes_counter == 0) {
1da177e4
LT		 3867 tw32_f(MAC_MODE, (tp->mac_mode |
3868 MAC_MODE_SEND_CONFIGS));
3869 udelay(1);
3870 tw32_f(MAC_MODE, tp->mac_mode);
3871 }
3872 }
3873
3874 if (current_link_up == 1) {
3875 tp->link_config.active_speed = SPEED_1000;
3876 tp->link_config.active_duplex = DUPLEX_FULL;
3877 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3878 LED_CTRL_LNKLED_OVERRIDE |
3879 LED_CTRL_1000MBPS_ON));
3880 } else {
3881 tp->link_config.active_speed = SPEED_INVALID;
3882 tp->link_config.active_duplex = DUPLEX_INVALID;
3883 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3884 LED_CTRL_LNKLED_OVERRIDE |
3885 LED_CTRL_TRAFFIC_OVERRIDE));
3886 }
3887
3888 if (current_link_up != netif_carrier_ok(tp->dev)) {
3889 if (current_link_up)
3890 netif_carrier_on(tp->dev);
3891 else
3892 netif_carrier_off(tp->dev);
3893 tg3_link_report(tp);
3894 } else {
8d018621 3895 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3896 if (orig_pause_cfg != now_pause_cfg ||
3897 orig_active_speed != tp->link_config.active_speed ||
3898 orig_active_duplex != tp->link_config.active_duplex)
3899 tg3_link_report(tp);
3900 }
3901
3902 return 0;
3903}
3904
747e8f8b
MC		 3905static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3906{
3907 int current_link_up, err = 0;
3908 u32 bmsr, bmcr;
3909 u16 current_speed;
3910 u8 current_duplex;
ef167e27 3911 u32 local_adv, remote_adv;
747e8f8b
MC		 3912
3913 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3914 tw32_f(MAC_MODE, tp->mac_mode);
3915 udelay(40);
3916
3917 tw32(MAC_EVENT, 0);
3918
3919 tw32_f(MAC_STATUS,
3920 (MAC_STATUS_SYNC_CHANGED |
3921 MAC_STATUS_CFG_CHANGED |
3922 MAC_STATUS_MI_COMPLETION |
3923 MAC_STATUS_LNKSTATE_CHANGED));
3924 udelay(40);
3925
3926 if (force_reset)
3927 tg3_phy_reset(tp);
3928
3929 current_link_up = 0;
3930 current_speed = SPEED_INVALID;
3931 current_duplex = DUPLEX_INVALID;
3932
3933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3937 bmsr |= BMSR_LSTATUS;
3938 else
3939 bmsr &= ~BMSR_LSTATUS;
3940 }
747e8f8b
MC		 3941
3942 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3943
3944 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3945 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 3946 /* do nothing, just check for link up at the end */
3947 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3948 u32 adv, new_adv;
3949
3950 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3951 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3952 ADVERTISE_1000XPAUSE |
3953 ADVERTISE_1000XPSE_ASYM |
3954 ADVERTISE_SLCT);
3955
ba4d07a8 3956 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 3957
3958 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3959 new_adv |= ADVERTISE_1000XHALF;
3960 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3961 new_adv |= ADVERTISE_1000XFULL;
3962
3963 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3964 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3965 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3966 tg3_writephy(tp, MII_BMCR, bmcr);
3967
3968 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 3969 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 3970 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3971
3972 return err;
3973 }
3974 } else {
3975 u32 new_bmcr;
3976
3977 bmcr &= ~BMCR_SPEED1000;
3978 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3979
3980 if (tp->link_config.duplex == DUPLEX_FULL)
3981 new_bmcr |= BMCR_FULLDPLX;
3982
3983 if (new_bmcr != bmcr) {
3984 /* BMCR_SPEED1000 is a reserved bit that needs
3985 * to be set on write.
3986 */
3987 new_bmcr |= BMCR_SPEED1000;
3988
3989 /* Force a linkdown */
3990 if (netif_carrier_ok(tp->dev)) {
3991 u32 adv;
3992
3993 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3994 adv &= ~(ADVERTISE_1000XFULL |
3995 ADVERTISE_1000XHALF |
3996 ADVERTISE_SLCT);
3997 tg3_writephy(tp, MII_ADVERTISE, adv);
3998 tg3_writephy(tp, MII_BMCR, bmcr |
3999 BMCR_ANRESTART |
4000 BMCR_ANENABLE);
4001 udelay(10);
4002 netif_carrier_off(tp->dev);
4003 }
4004 tg3_writephy(tp, MII_BMCR, new_bmcr);
4005 bmcr = new_bmcr;
4006 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4007 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4008 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4009 ASIC_REV_5714) {
4010 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4011 bmsr |= BMSR_LSTATUS;
4012 else
4013 bmsr &= ~BMSR_LSTATUS;
4014 }
747e8f8b
MC		 4015 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4016 }
4017 }
4018
4019 if (bmsr & BMSR_LSTATUS) {
4020 current_speed = SPEED_1000;
4021 current_link_up = 1;
4022 if (bmcr & BMCR_FULLDPLX)
4023 current_duplex = DUPLEX_FULL;
4024 else
4025 current_duplex = DUPLEX_HALF;
4026
ef167e27
MC		 4027 local_adv = 0;
4028 remote_adv = 0;
4029
747e8f8b 4030 if (bmcr & BMCR_ANENABLE) {
ef167e27 4031 u32 common;
747e8f8b
MC		 4032
4033 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4034 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4035 common = local_adv & remote_adv;
4036 if (common & (ADVERTISE_1000XHALF |
4037 ADVERTISE_1000XFULL)) {
4038 if (common & ADVERTISE_1000XFULL)
4039 current_duplex = DUPLEX_FULL;
4040 else
4041 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4042 }
4043 else
4044 current_link_up = 0;
4045 }
4046 }
4047
ef167e27
MC		 4048 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4049 tg3_setup_flow_control(tp, local_adv, remote_adv);
4050
747e8f8b
MC		 4051 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4052 if (tp->link_config.active_duplex == DUPLEX_HALF)
4053 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4054
4055 tw32_f(MAC_MODE, tp->mac_mode);
4056 udelay(40);
4057
4058 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4059
4060 tp->link_config.active_speed = current_speed;
4061 tp->link_config.active_duplex = current_duplex;
4062
4063 if (current_link_up != netif_carrier_ok(tp->dev)) {
4064 if (current_link_up)
4065 netif_carrier_on(tp->dev);
4066 else {
4067 netif_carrier_off(tp->dev);
4068 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4069 }
4070 tg3_link_report(tp);
4071 }
4072 return err;
4073}
4074
4075static void tg3_serdes_parallel_detect(struct tg3 *tp)
4076{
3d3ebe74 4077 if (tp->serdes_counter) {
747e8f8b 4078 /* Give autoneg time to complete. */
3d3ebe74 4079 tp->serdes_counter--;
747e8f8b
MC		 4080 return;
4081 }
4082 if (!netif_carrier_ok(tp->dev) &&
4083 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4084 u32 bmcr;
4085
4086 tg3_readphy(tp, MII_BMCR, &bmcr);
4087 if (bmcr & BMCR_ANENABLE) {
4088 u32 phy1, phy2;
4089
4090 /* Select shadow register 0x1f */
4091 tg3_writephy(tp, 0x1c, 0x7c00);
4092 tg3_readphy(tp, 0x1c, &phy1);
4093
4094 /* Select expansion interrupt status register */
4095 tg3_writephy(tp, 0x17, 0x0f01);
4096 tg3_readphy(tp, 0x15, &phy2);
4097 tg3_readphy(tp, 0x15, &phy2);
4098
4099 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4100 /* We have signal detect and not receiving
4101 * config code words, link is up by parallel
4102 * detection.
4103 */
4104
4105 bmcr &= ~BMCR_ANENABLE;
4106 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4107 tg3_writephy(tp, MII_BMCR, bmcr);
4108 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4109 }
4110 }
4111 }
4112 else if (netif_carrier_ok(tp->dev) &&
4113 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4114 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4115 u32 phy2;
4116
4117 /* Select expansion interrupt status register */
4118 tg3_writephy(tp, 0x17, 0x0f01);
4119 tg3_readphy(tp, 0x15, &phy2);
4120 if (phy2 & 0x20) {
4121 u32 bmcr;
4122
4123 /* Config code words received, turn on autoneg. */
4124 tg3_readphy(tp, MII_BMCR, &bmcr);
4125 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4126
4127 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4128
4129 }
4130 }
4131}
4132
1da177e4
LT		 4133static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4134{
4135 int err;
4136
4137 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4138 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4139 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4140 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4141 } else {
4142 err = tg3_setup_copper_phy(tp, force_reset);
4143 }
4144
bcb37f6c 4145 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4146 u32 val, scale;
4147
4148 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4149 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4150 scale = 65;
4151 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4152 scale = 6;
4153 else
4154 scale = 12;
4155
4156 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4157 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4158 tw32(GRC_MISC_CFG, val);
4159 }
4160
1da177e4
LT		 4161 if (tp->link_config.active_speed == SPEED_1000 &&
4162 tp->link_config.active_duplex == DUPLEX_HALF)
4163 tw32(MAC_TX_LENGTHS,
4164 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4165 (6 << TX_LENGTHS_IPG_SHIFT) |
4166 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4167 else
4168 tw32(MAC_TX_LENGTHS,
4169 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4170 (6 << TX_LENGTHS_IPG_SHIFT) |
4171 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4172
4173 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4174 if (netif_carrier_ok(tp->dev)) {
4175 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4176 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4177 } else {
4178 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4179 }
4180 }
4181
8ed5d97e
MC		 4182 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4183 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4184 if (!netif_carrier_ok(tp->dev))
4185 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4186 tp->pwrmgmt_thresh;
4187 else
4188 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4189 tw32(PCIE_PWR_MGMT_THRESH, val);
4190 }
4191
1da177e4
LT		 4192 return err;
4193}
4194
df3e6548
MC		 4195/* This is called whenever we suspect that the system chipset is re-
4196 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4197 * is bogus tx completions. We try to recover by setting the
4198 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4199 * in the workqueue.
4200 */
4201static void tg3_tx_recover(struct tg3 *tp)
4202{
4203 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4204 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4205
4206 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4207 "mapped I/O cycles to the network device, attempting to "
4208 "recover. Please report the problem to the driver maintainer "
4209 "and include system chipset information.\n", tp->dev->name);
4210
4211 spin_lock(&tp->lock);
df3e6548 4212 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4213 spin_unlock(&tp->lock);
4214}
4215
1b2a7205
MC		 4216static inline u32 tg3_tx_avail(struct tg3 *tp)
4217{
4218 smp_mb();
4219 return (tp->tx_pending -
4220 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4221}
4222
1da177e4
LT		 4223/* Tigon3 never reports partial packet sends. So we do not
4224 * need special logic to handle SKBs that have not had all
4225 * of their frags sent yet, like SunGEM does.
4226 */
4227static void tg3_tx(struct tg3 *tp)
4228{
4229 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4230 u32 sw_idx = tp->tx_cons;
4231
4232 while (sw_idx != hw_idx) {
4233 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4234 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4235 int i, tx_bug = 0;
4236
4237 if (unlikely(skb == NULL)) {
4238 tg3_tx_recover(tp);
4239 return;
4240 }
1da177e4 4241
90079ce8 4242 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4243
4244 ri->skb = NULL;
4245
4246 sw_idx = NEXT_TX(sw_idx);
4247
4248 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4249 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4250 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4251 tx_bug = 1;
1da177e4
LT		 4252 sw_idx = NEXT_TX(sw_idx);
4253 }
4254
f47c11ee 4255 dev_kfree_skb(skb);
df3e6548
MC		 4256
4257 if (unlikely(tx_bug)) {
4258 tg3_tx_recover(tp);
4259 return;
4260 }
1da177e4
LT		 4261 }
4262
4263 tp->tx_cons = sw_idx;
4264
1b2a7205
MC		 4265 /* Need to make the tx_cons update visible to tg3_start_xmit()
4266 * before checking for netif_queue_stopped(). Without the
4267 * memory barrier, there is a small possibility that tg3_start_xmit()
4268 * will miss it and cause the queue to be stopped forever.
4269 */
4270 smp_mb();
4271
4272 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4273 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4274 netif_tx_lock(tp->dev);
51b91468 4275 if (netif_queue_stopped(tp->dev) &&
42952231 4276 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4277 netif_wake_queue(tp->dev);
1b2a7205 4278 netif_tx_unlock(tp->dev);
51b91468 4279 }
1da177e4
LT		 4280}
4281
4282/* Returns size of skb allocated or < 0 on error.
4283 *
4284 * We only need to fill in the address because the other members
4285 * of the RX descriptor are invariant, see tg3_init_rings.
4286 *
4287 * Note the purposeful assymetry of cpu vs. chip accesses. For
4288 * posting buffers we only dirty the first cache line of the RX
4289 * descriptor (containing the address). Whereas for the RX status
4290 * buffers the cpu only reads the last cacheline of the RX descriptor
4291 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4292 */
4293static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4294 int src_idx, u32 dest_idx_unmasked)
4295{
4296 struct tg3_rx_buffer_desc *desc;
4297 struct ring_info *map, *src_map;
4298 struct sk_buff *skb;
4299 dma_addr_t mapping;
4300 int skb_size, dest_idx;
4301
4302 src_map = NULL;
4303 switch (opaque_key) {
4304 case RXD_OPAQUE_RING_STD:
4305 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4306 desc = &tp->rx_std[dest_idx];
4307 map = &tp->rx_std_buffers[dest_idx];
4308 if (src_idx >= 0)
4309 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 4310 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 4311 break;
4312
4313 case RXD_OPAQUE_RING_JUMBO:
4314 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4315 desc = &tp->rx_jumbo[dest_idx];
4316 map = &tp->rx_jumbo_buffers[dest_idx];
4317 if (src_idx >= 0)
4318 src_map = &tp->rx_jumbo_buffers[src_idx];
4319 skb_size = RX_JUMBO_PKT_BUF_SZ;
4320 break;
4321
4322 default:
4323 return -EINVAL;
855e1111 4324 }
1da177e4
LT		 4325
4326 /* Do not overwrite any of the map or rp information
4327 * until we are sure we can commit to a new buffer.
4328 *
4329 * Callers depend upon this behavior and assume that
4330 * we leave everything unchanged if we fail.
4331 */
a20e9c62 4332 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 4333 if (skb == NULL)
4334 return -ENOMEM;
4335
1da177e4
LT		 4336 skb_reserve(skb, tp->rx_offset);
4337
4338 mapping = pci_map_single(tp->pdev, skb->data,
4339 skb_size - tp->rx_offset,
4340 PCI_DMA_FROMDEVICE);
4341
4342 map->skb = skb;
4343 pci_unmap_addr_set(map, mapping, mapping);
4344
4345 if (src_map != NULL)
4346 src_map->skb = NULL;
4347
4348 desc->addr_hi = ((u64)mapping >> 32);
4349 desc->addr_lo = ((u64)mapping & 0xffffffff);
4350
4351 return skb_size;
4352}
4353
4354/* We only need to move over in the address because the other
4355 * members of the RX descriptor are invariant. See notes above
4356 * tg3_alloc_rx_skb for full details.
4357 */
4358static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4359 int src_idx, u32 dest_idx_unmasked)
4360{
4361 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4362 struct ring_info *src_map, *dest_map;
4363 int dest_idx;
4364
4365 switch (opaque_key) {
4366 case RXD_OPAQUE_RING_STD:
4367 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4368 dest_desc = &tp->rx_std[dest_idx];
4369 dest_map = &tp->rx_std_buffers[dest_idx];
4370 src_desc = &tp->rx_std[src_idx];
4371 src_map = &tp->rx_std_buffers[src_idx];
4372 break;
4373
4374 case RXD_OPAQUE_RING_JUMBO:
4375 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4376 dest_desc = &tp->rx_jumbo[dest_idx];
4377 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4378 src_desc = &tp->rx_jumbo[src_idx];
4379 src_map = &tp->rx_jumbo_buffers[src_idx];
4380 break;
4381
4382 default:
4383 return;
855e1111 4384 }
1da177e4
LT		 4385
4386 dest_map->skb = src_map->skb;
4387 pci_unmap_addr_set(dest_map, mapping,
4388 pci_unmap_addr(src_map, mapping));
4389 dest_desc->addr_hi = src_desc->addr_hi;
4390 dest_desc->addr_lo = src_desc->addr_lo;
4391
4392 src_map->skb = NULL;
4393}
4394
4395#if TG3_VLAN_TAG_USED
4396static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4397{
4398 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4399}
4400#endif
4401
4402/* The RX ring scheme is composed of multiple rings which post fresh
4403 * buffers to the chip, and one special ring the chip uses to report
4404 * status back to the host.
4405 *
4406 * The special ring reports the status of received packets to the
4407 * host. The chip does not write into the original descriptor the
4408 * RX buffer was obtained from. The chip simply takes the original
4409 * descriptor as provided by the host, updates the status and length
4410 * field, then writes this into the next status ring entry.
4411 *
4412 * Each ring the host uses to post buffers to the chip is described
4413 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4414 * it is first placed into the on-chip ram. When the packet's length
4415 * is known, it walks down the TG3_BDINFO entries to select the ring.
4416 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4417 * which is within the range of the new packet's length is chosen.
4418 *
4419 * The "separate ring for rx status" scheme may sound queer, but it makes
4420 * sense from a cache coherency perspective. If only the host writes
4421 * to the buffer post rings, and only the chip writes to the rx status
4422 * rings, then cache lines never move beyond shared-modified state.
4423 * If both the host and chip were to write into the same ring, cache line
4424 * eviction could occur since both entities want it in an exclusive state.
4425 */
4426static int tg3_rx(struct tg3 *tp, int budget)
4427{
f92905de 4428 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4429 u32 sw_idx = tp->rx_rcb_ptr;
4430 u16 hw_idx;
1da177e4
LT		 4431 int received;
4432
4433 hw_idx = tp->hw_status->idx[0].rx_producer;
4434 /*
4435 * We need to order the read of hw_idx and the read of
4436 * the opaque cookie.
4437 */
4438 rmb();
1da177e4
LT		 4439 work_mask = 0;
4440 received = 0;
4441 while (sw_idx != hw_idx && budget > 0) {
4442 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4443 unsigned int len;
4444 struct sk_buff *skb;
4445 dma_addr_t dma_addr;
4446 u32 opaque_key, desc_idx, *post_ptr;
4447
4448 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4449 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4450 if (opaque_key == RXD_OPAQUE_RING_STD) {
4451 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4452 mapping);
4453 skb = tp->rx_std_buffers[desc_idx].skb;
4454 post_ptr = &tp->rx_std_ptr;
f92905de 4455 rx_std_posted++;
1da177e4
LT		 4456 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4457 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4458 mapping);
4459 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4460 post_ptr = &tp->rx_jumbo_ptr;
4461 }
4462 else {
4463 goto next_pkt_nopost;
4464 }
4465
4466 work_mask |= opaque_key;
4467
4468 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4469 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4470 drop_it:
4471 tg3_recycle_rx(tp, opaque_key,
4472 desc_idx, *post_ptr);
4473 drop_it_no_recycle:
4474 /* Other statistics kept track of by card. */
4475 tp->net_stats.rx_dropped++;
4476 goto next_pkt;
4477 }
4478
ad829268
MC		 4479 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4480 ETH_FCS_LEN;
1da177e4 4481
6aa20a22 4482 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4483 && tp->rx_offset == NET_IP_ALIGN
4484 /* rx_offset will likely not equal NET_IP_ALIGN
4485 * if this is a 5701 card running in PCI-X mode
4486 * [see tg3_get_invariants()]
4487 */
1da177e4
LT		 4488 ) {
4489 int skb_size;
4490
4491 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4492 desc_idx, *post_ptr);
4493 if (skb_size < 0)
4494 goto drop_it;
4495
4496 pci_unmap_single(tp->pdev, dma_addr,
4497 skb_size - tp->rx_offset,
4498 PCI_DMA_FROMDEVICE);
4499
4500 skb_put(skb, len);
4501 } else {
4502 struct sk_buff *copy_skb;
4503
4504 tg3_recycle_rx(tp, opaque_key,
4505 desc_idx, *post_ptr);
4506
ad829268
MC		 4507 copy_skb = netdev_alloc_skb(tp->dev,
4508 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4509 if (copy_skb == NULL)
4510 goto drop_it_no_recycle;
4511
ad829268 4512 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4513 skb_put(copy_skb, len);
4514 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4515 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4516 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4517
4518 /* We'll reuse the original ring buffer. */
4519 skb = copy_skb;
4520 }
4521
4522 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4523 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4524 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4525 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4526 skb->ip_summed = CHECKSUM_UNNECESSARY;
4527 else
4528 skb->ip_summed = CHECKSUM_NONE;
4529
4530 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4531
4532 if (len > (tp->dev->mtu + ETH_HLEN) &&
4533 skb->protocol != htons(ETH_P_8021Q)) {
4534 dev_kfree_skb(skb);
4535 goto next_pkt;
4536 }
4537
1da177e4
LT		 4538#if TG3_VLAN_TAG_USED
4539 if (tp->vlgrp != NULL &&
4540 desc->type_flags & RXD_FLAG_VLAN) {
4541 tg3_vlan_rx(tp, skb,
4542 desc->err_vlan & RXD_VLAN_MASK);
4543 } else
4544#endif
4545 netif_receive_skb(skb);
4546
1da177e4
LT		 4547 received++;
4548 budget--;
4549
4550next_pkt:
4551 (*post_ptr)++;
f92905de
MC		 4552
4553 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4554 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4555
4556 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4557 TG3_64BIT_REG_LOW, idx);
4558 work_mask &= ~RXD_OPAQUE_RING_STD;
4559 rx_std_posted = 0;
4560 }
1da177e4 4561next_pkt_nopost:
483ba50b 4562 sw_idx++;
6b31a515 4563 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4564
4565 /* Refresh hw_idx to see if there is new work */
4566 if (sw_idx == hw_idx) {
4567 hw_idx = tp->hw_status->idx[0].rx_producer;
4568 rmb();
4569 }
1da177e4
LT		 4570 }
4571
4572 /* ACK the status ring. */
483ba50b
MC		 4573 tp->rx_rcb_ptr = sw_idx;
4574 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4575
4576 /* Refill RX ring(s). */
4577 if (work_mask & RXD_OPAQUE_RING_STD) {
4578 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4579 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4580 sw_idx);
4581 }
4582 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4583 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4584 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4585 sw_idx);
4586 }
4587 mmiowb();
4588
4589 return received;
4590}
4591
6f535763 4592static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4593{
1da177e4 4594 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4595
1da177e4
LT		 4596 /* handle link change and other phy events */
4597 if (!(tp->tg3_flags &
4598 (TG3_FLAG_USE_LINKCHG_REG |
4599 TG3_FLAG_POLL_SERDES))) {
4600 if (sblk->status & SD_STATUS_LINK_CHG) {
4601 sblk->status = SD_STATUS_UPDATED |
4602 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4603 spin_lock(&tp->lock);
dd477003
MC		 4604 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4605 tw32_f(MAC_STATUS,
4606 (MAC_STATUS_SYNC_CHANGED |
4607 MAC_STATUS_CFG_CHANGED |
4608 MAC_STATUS_MI_COMPLETION |
4609 MAC_STATUS_LNKSTATE_CHANGED));
4610 udelay(40);
4611 } else
4612 tg3_setup_phy(tp, 0);
f47c11ee 4613 spin_unlock(&tp->lock);
1da177e4
LT		 4614 }
4615 }
4616
4617 /* run TX completion thread */
4618 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4619 tg3_tx(tp);
6f535763 4620 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4621 return work_done;
1da177e4
LT		 4622 }
4623
1da177e4
LT		 4624 /* run RX thread, within the bounds set by NAPI.
4625 * All RX "locking" is done by ensuring outside
bea3348e 4626 * code synchronizes with tg3->napi.poll()
1da177e4 4627 */
bea3348e 4628 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4629 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4630
6f535763
DM		 4631 return work_done;
4632}
4633
4634static int tg3_poll(struct napi_struct *napi, int budget)
4635{
4636 struct tg3 *tp = container_of(napi, struct tg3, napi);
4637 int work_done = 0;
4fd7ab59 4638 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4639
4640 while (1) {
4641 work_done = tg3_poll_work(tp, work_done, budget);
4642
4643 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4644 goto tx_recovery;
4645
4646 if (unlikely(work_done >= budget))
4647 break;
4648
4fd7ab59
MC		 4649 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4650 /* tp->last_tag is used in tg3_restart_ints() below
4651 * to tell the hw how much work has been processed,
4652 * so we must read it before checking for more work.
4653 */
4654 tp->last_tag = sblk->status_tag;
4655 rmb();
4656 } else
4657 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4658
4fd7ab59 4659 if (likely(!tg3_has_work(tp))) {
288379f0 4660 napi_complete(napi);
6f535763
DM		 4661 tg3_restart_ints(tp);
4662 break;
4663 }
1da177e4
LT		 4664 }
4665
bea3348e 4666 return work_done;
6f535763
DM		 4667
4668tx_recovery:
4fd7ab59 4669 /* work_done is guaranteed to be less than budget. */
288379f0 4670 napi_complete(napi);
6f535763 4671 schedule_work(&tp->reset_task);
4fd7ab59 4672 return work_done;
1da177e4
LT		 4673}
4674
f47c11ee
DM		 4675static void tg3_irq_quiesce(struct tg3 *tp)
4676{
4677 BUG_ON(tp->irq_sync);
4678
4679 tp->irq_sync = 1;
4680 smp_mb();
4681
4682 synchronize_irq(tp->pdev->irq);
4683}
4684
4685static inline int tg3_irq_sync(struct tg3 *tp)
4686{
4687 return tp->irq_sync;
4688}
4689
4690/* Fully shutdown all tg3 driver activity elsewhere in the system.
4691 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4692 * with as well. Most of the time, this is not necessary except when
4693 * shutting down the device.
4694 */
4695static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4696{
46966545 4697 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4698 if (irq_sync)
4699 tg3_irq_quiesce(tp);
f47c11ee
DM		 4700}
4701
4702static inline void tg3_full_unlock(struct tg3 *tp)
4703{
f47c11ee
DM		 4704 spin_unlock_bh(&tp->lock);
4705}
4706
fcfa0a32
MC		 4707/* One-shot MSI handler - Chip automatically disables interrupt
4708 * after sending MSI so driver doesn't have to do it.
4709 */
7d12e780 4710static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4711{
4712 struct net_device *dev = dev_id;
4713 struct tg3 *tp = netdev_priv(dev);
4714
4715 prefetch(tp->hw_status);
4716 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4717
4718 if (likely(!tg3_irq_sync(tp)))
288379f0 4719 napi_schedule(&tp->napi);
fcfa0a32
MC		 4720
4721 return IRQ_HANDLED;
4722}
4723
88b06bc2
MC		 4724/* MSI ISR - No need to check for interrupt sharing and no need to
4725 * flush status block and interrupt mailbox. PCI ordering rules
4726 * guarantee that MSI will arrive after the status block.
4727 */
7d12e780 4728static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4729{
4730 struct net_device *dev = dev_id;
4731 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4732
61487480
MC		 4733 prefetch(tp->hw_status);
4734 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4735 /*
fac9b83e 4736 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4737 * chip-internal interrupt pending events.
fac9b83e 4738 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4739 * NIC to stop sending us irqs, engaging "in-intr-handler"
4740 * event coalescing.
4741 */
4742 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4743 if (likely(!tg3_irq_sync(tp)))
288379f0 4744 napi_schedule(&tp->napi);
61487480 4745
88b06bc2
MC		 4746 return IRQ_RETVAL(1);
4747}
4748
7d12e780 4749static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4750{
4751 struct net_device *dev = dev_id;
4752 struct tg3 *tp = netdev_priv(dev);
4753 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4754 unsigned int handled = 1;
4755
1da177e4
LT		 4756 /* In INTx mode, it is possible for the interrupt to arrive at
4757 * the CPU before the status block posted prior to the interrupt.
4758 * Reading the PCI State register will confirm whether the
4759 * interrupt is ours and will flush the status block.
4760 */
d18edcb2
MC		 4761 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4762 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4763 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4764 handled = 0;
f47c11ee 4765 goto out;
fac9b83e 4766 }
d18edcb2
MC		 4767 }
4768
4769 /*
4770 * Writing any value to intr-mbox-0 clears PCI INTA# and
4771 * chip-internal interrupt pending events.
4772 * Writing non-zero to intr-mbox-0 additional tells the
4773 * NIC to stop sending us irqs, engaging "in-intr-handler"
4774 * event coalescing.
c04cb347
MC		 4775 *
4776 * Flush the mailbox to de-assert the IRQ immediately to prevent
4777 * spurious interrupts. The flush impacts performance but
4778 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4779 */
c04cb347 4780 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4781 if (tg3_irq_sync(tp))
4782 goto out;
4783 sblk->status &= ~SD_STATUS_UPDATED;
4784 if (likely(tg3_has_work(tp))) {
4785 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4786 napi_schedule(&tp->napi);
d18edcb2
MC		 4787 } else {
4788 /* No work, shared interrupt perhaps? re-enable
4789 * interrupts, and flush that PCI write
4790 */
4791 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4792 0x00000000);
fac9b83e 4793 }
f47c11ee 4794out:
fac9b83e
DM		 4795 return IRQ_RETVAL(handled);
4796}
4797
7d12e780 4798static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4799{
4800 struct net_device *dev = dev_id;
4801 struct tg3 *tp = netdev_priv(dev);
4802 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4803 unsigned int handled = 1;
4804
fac9b83e
DM		 4805 /* In INTx mode, it is possible for the interrupt to arrive at
4806 * the CPU before the status block posted prior to the interrupt.
4807 * Reading the PCI State register will confirm whether the
4808 * interrupt is ours and will flush the status block.
4809 */
d18edcb2
MC		 4810 if (unlikely(sblk->status_tag == tp->last_tag)) {
4811 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4812 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4813 handled = 0;
f47c11ee 4814 goto out;
1da177e4 4815 }
d18edcb2
MC		 4816 }
4817
4818 /*
4819 * writing any value to intr-mbox-0 clears PCI INTA# and
4820 * chip-internal interrupt pending events.
4821 * writing non-zero to intr-mbox-0 additional tells the
4822 * NIC to stop sending us irqs, engaging "in-intr-handler"
4823 * event coalescing.
c04cb347
MC		 4824 *
4825 * Flush the mailbox to de-assert the IRQ immediately to prevent
4826 * spurious interrupts. The flush impacts performance but
4827 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4828 */
c04cb347 4829 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4830 if (tg3_irq_sync(tp))
4831 goto out;
288379f0 4832 if (napi_schedule_prep(&tp->napi)) {
d18edcb2
MC		 4833 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4834 /* Update last_tag to mark that this status has been
4835 * seen. Because interrupt may be shared, we may be
4836 * racing with tg3_poll(), so only update last_tag
4837 * if tg3_poll() is not scheduled.
4838 */
4839 tp->last_tag = sblk->status_tag;
288379f0 4840 __napi_schedule(&tp->napi);
1da177e4 4841 }
f47c11ee 4842out:
1da177e4
LT		 4843 return IRQ_RETVAL(handled);
4844}
4845
7938109f 4846/* ISR for interrupt test */
7d12e780 4847static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4848{
4849 struct net_device *dev = dev_id;
4850 struct tg3 *tp = netdev_priv(dev);
4851 struct tg3_hw_status *sblk = tp->hw_status;
4852
f9804ddb
MC		 4853 if ((sblk->status & SD_STATUS_UPDATED) ||
4854 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4855 tg3_disable_ints(tp);
7938109f
MC		 4856 return IRQ_RETVAL(1);
4857 }
4858 return IRQ_RETVAL(0);
4859}
4860
8e7a22e3 4861static int tg3_init_hw(struct tg3 *, int);
944d980e 4862static int tg3_halt(struct tg3 *, int, int);
1da177e4 4863
b9ec6c1b
MC		 4864/* Restart hardware after configuration changes, self-test, etc.
4865 * Invoked with tp->lock held.
4866 */
4867static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4868 __releases(tp->lock)
4869 __acquires(tp->lock)
b9ec6c1b
MC		 4870{
4871 int err;
4872
4873 err = tg3_init_hw(tp, reset_phy);
4874 if (err) {
4875 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4876 "aborting.\n", tp->dev->name);
4877 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4878 tg3_full_unlock(tp);
4879 del_timer_sync(&tp->timer);
4880 tp->irq_sync = 0;
bea3348e 4881 napi_enable(&tp->napi);
b9ec6c1b
MC		 4882 dev_close(tp->dev);
4883 tg3_full_lock(tp, 0);
4884 }
4885 return err;
4886}
4887
1da177e4
LT		 4888#ifdef CONFIG_NET_POLL_CONTROLLER
4889static void tg3_poll_controller(struct net_device *dev)
4890{
88b06bc2
MC		 4891 struct tg3 *tp = netdev_priv(dev);
4892
7d12e780 4893 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4894}
4895#endif
4896
c4028958 4897static void tg3_reset_task(struct work_struct *work)
1da177e4 4898{
c4028958 4899 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4900 int err;
1da177e4
LT		 4901 unsigned int restart_timer;
4902
7faa006f 4903 tg3_full_lock(tp, 0);
7faa006f
MC		 4904
4905 if (!netif_running(tp->dev)) {
7faa006f
MC		 4906 tg3_full_unlock(tp);
4907 return;
4908 }
4909
4910 tg3_full_unlock(tp);
4911
b02fd9e3
MC		 4912 tg3_phy_stop(tp);
4913
1da177e4
LT		 4914 tg3_netif_stop(tp);
4915
f47c11ee 4916 tg3_full_lock(tp, 1);
1da177e4
LT		 4917
4918 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4919 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4920
df3e6548
MC		 4921 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4922 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4923 tp->write32_rx_mbox = tg3_write_flush_reg32;
4924 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4925 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4926 }
4927
944d980e 4928 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4929 err = tg3_init_hw(tp, 1);
4930 if (err)
b9ec6c1b 4931 goto out;
1da177e4
LT		 4932
4933 tg3_netif_start(tp);
4934
1da177e4
LT		 4935 if (restart_timer)
4936 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4937
b9ec6c1b 4938out:
7faa006f 4939 tg3_full_unlock(tp);
b02fd9e3
MC		 4940
4941 if (!err)
4942 tg3_phy_start(tp);
1da177e4
LT		 4943}
4944
b0408751
MC		 4945static void tg3_dump_short_state(struct tg3 *tp)
4946{
4947 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4948 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4949 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4950 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4951}
4952
1da177e4
LT		 4953static void tg3_tx_timeout(struct net_device *dev)
4954{
4955 struct tg3 *tp = netdev_priv(dev);
4956
b0408751 4957 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 4958 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4959 dev->name);
b0408751
MC		 4960 tg3_dump_short_state(tp);
4961 }
1da177e4
LT		 4962
4963 schedule_work(&tp->reset_task);
4964}
4965
c58ec932
MC		 4966/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4967static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4968{
4969 u32 base = (u32) mapping & 0xffffffff;
4970
4971 return ((base > 0xffffdcc0) &&
4972 (base + len + 8 < base));
4973}
4974
72f2afb8
MC		 4975/* Test for DMA addresses > 40-bit */
4976static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4977 int len)
4978{
4979#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 4980 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
72f2afb8
MC		 4981 return (((u64) mapping + len) > DMA_40BIT_MASK);
4982 return 0;
4983#else
4984 return 0;
4985#endif
4986}
4987
1da177e4
LT		 4988static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4989
72f2afb8
MC		 4990/* Workaround 4GB and 40-bit hardware DMA bugs. */
4991static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 4992 u32 last_plus_one, u32 *start,
4993 u32 base_flags, u32 mss)
1da177e4 4994{
41588ba1 4995 struct sk_buff *new_skb;
c58ec932 4996 dma_addr_t new_addr = 0;
1da177e4 4997 u32 entry = *start;
c58ec932 4998 int i, ret = 0;
1da177e4 4999
41588ba1
MC		 5000 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5001 new_skb = skb_copy(skb, GFP_ATOMIC);
5002 else {
5003 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5004
5005 new_skb = skb_copy_expand(skb,
5006 skb_headroom(skb) + more_headroom,
5007 skb_tailroom(skb), GFP_ATOMIC);
5008 }
5009
1da177e4 5010 if (!new_skb) {
c58ec932
MC		 5011 ret = -1;
5012 } else {
5013 /* New SKB is guaranteed to be linear. */
5014 entry = *start;
90079ce8
DM		 5015 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5016 new_addr = skb_shinfo(new_skb)->dma_maps[0];
5017
c58ec932
MC		 5018 /* Make sure new skb does not cross any 4G boundaries.
5019 * Drop the packet if it does.
5020 */
90079ce8 5021 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5022 if (!ret)
5023 skb_dma_unmap(&tp->pdev->dev, new_skb,
5024 DMA_TO_DEVICE);
c58ec932
MC		 5025 ret = -1;
5026 dev_kfree_skb(new_skb);
5027 new_skb = NULL;
5028 } else {
5029 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5030 base_flags, 1 | (mss << 1));
5031 *start = NEXT_TX(entry);
5032 }
1da177e4
LT		 5033 }
5034
1da177e4
LT		 5035 /* Now clean up the sw ring entries. */
5036 i = 0;
5037 while (entry != last_plus_one) {
1da177e4
LT		 5038 if (i == 0) {
5039 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5040 } else {
5041 tp->tx_buffers[entry].skb = NULL;
5042 }
5043 entry = NEXT_TX(entry);
5044 i++;
5045 }
5046
90079ce8 5047 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5048 dev_kfree_skb(skb);
5049
c58ec932 5050 return ret;
1da177e4
LT		 5051}
5052
5053static void tg3_set_txd(struct tg3 *tp, int entry,
5054 dma_addr_t mapping, int len, u32 flags,
5055 u32 mss_and_is_end)
5056{
5057 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5058 int is_end = (mss_and_is_end & 0x1);
5059 u32 mss = (mss_and_is_end >> 1);
5060 u32 vlan_tag = 0;
5061
5062 if (is_end)
5063 flags |= TXD_FLAG_END;
5064 if (flags & TXD_FLAG_VLAN) {
5065 vlan_tag = flags >> 16;
5066 flags &= 0xffff;
5067 }
5068 vlan_tag |= (mss << TXD_MSS_SHIFT);
5069
5070 txd->addr_hi = ((u64) mapping >> 32);
5071 txd->addr_lo = ((u64) mapping & 0xffffffff);
5072 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5073 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5074}
5075
5a6f3074
MC		 5076/* hard_start_xmit for devices that don't have any bugs and
5077 * support TG3_FLG2_HW_TSO_2 only.
5078 */
1da177e4 5079static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5080{
5081 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5082 u32 len, entry, base_flags, mss;
90079ce8
DM		 5083 struct skb_shared_info *sp;
5084 dma_addr_t mapping;
5a6f3074
MC		 5085
5086 len = skb_headlen(skb);
5087
00b70504 5088 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5089 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5090 * interrupt. Furthermore, IRQ processing runs lockless so we have
5091 * no IRQ context deadlocks to worry about either. Rejoice!
5092 */
1b2a7205 5093 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5094 if (!netif_queue_stopped(dev)) {
5095 netif_stop_queue(dev);
5096
5097 /* This is a hard error, log it. */
5098 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5099 "queue awake!\n", dev->name);
5100 }
5a6f3074
MC		 5101 return NETDEV_TX_BUSY;
5102 }
5103
5104 entry = tp->tx_prod;
5105 base_flags = 0;
5a6f3074 5106 mss = 0;
c13e3713 5107 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5108 int tcp_opt_len, ip_tcp_len;
5109
5110 if (skb_header_cloned(skb) &&
5111 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5112 dev_kfree_skb(skb);
5113 goto out_unlock;
5114 }
5115
b0026624
MC		 5116 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5117 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5118 else {
eddc9ec5
ACM		 5119 struct iphdr *iph = ip_hdr(skb);
5120
ab6a5bb6 5121 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5122 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5123
eddc9ec5
ACM		 5124 iph->check = 0;
5125 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5126 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5127 }
5a6f3074
MC		 5128
5129 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5130 TXD_FLAG_CPU_POST_DMA);
5131
aa8223c7 5132 tcp_hdr(skb)->check = 0;
5a6f3074 5133
5a6f3074 5134 }
84fa7933 5135 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5136 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5137#if TG3_VLAN_TAG_USED
5138 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5139 base_flags |= (TXD_FLAG_VLAN |
5140 (vlan_tx_tag_get(skb) << 16));
5141#endif
5142
90079ce8
DM		 5143 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5144 dev_kfree_skb(skb);
5145 goto out_unlock;
5146 }
5147
5148 sp = skb_shinfo(skb);
5149
5150 mapping = sp->dma_maps[0];
5a6f3074
MC		 5151
5152 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5153
5154 tg3_set_txd(tp, entry, mapping, len, base_flags,
5155 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5156
5157 entry = NEXT_TX(entry);
5158
5159 /* Now loop through additional data fragments, and queue them. */
5160 if (skb_shinfo(skb)->nr_frags > 0) {
5161 unsigned int i, last;
5162
5163 last = skb_shinfo(skb)->nr_frags - 1;
5164 for (i = 0; i <= last; i++) {
5165 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5166
5167 len = frag->size;
90079ce8 5168 mapping = sp->dma_maps[i + 1];
5a6f3074 5169 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5170
5171 tg3_set_txd(tp, entry, mapping, len,
5172 base_flags, (i == last) | (mss << 1));
5173
5174 entry = NEXT_TX(entry);
5175 }
5176 }
5177
5178 /* Packets are ready, update Tx producer idx local and on card. */
5179 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5180
5181 tp->tx_prod = entry;
1b2a7205 5182 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5183 netif_stop_queue(dev);
42952231 5184 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5185 netif_wake_queue(tp->dev);
5186 }
5187
5188out_unlock:
5189 mmiowb();
5a6f3074
MC		 5190
5191 dev->trans_start = jiffies;
5192
5193 return NETDEV_TX_OK;
5194}
5195
52c0fd83
MC		 5196static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5197
5198/* Use GSO to workaround a rare TSO bug that may be triggered when the
5199 * TSO header is greater than 80 bytes.
5200 */
5201static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5202{
5203 struct sk_buff *segs, *nskb;
5204
5205 /* Estimate the number of fragments in the worst case */
1b2a7205 5206 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5207 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5208 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5209 return NETDEV_TX_BUSY;
5210
5211 netif_wake_queue(tp->dev);
52c0fd83
MC		 5212 }
5213
5214 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5215 if (IS_ERR(segs))
52c0fd83
MC		 5216 goto tg3_tso_bug_end;
5217
5218 do {
5219 nskb = segs;
5220 segs = segs->next;
5221 nskb->next = NULL;
5222 tg3_start_xmit_dma_bug(nskb, tp->dev);
5223 } while (segs);
5224
5225tg3_tso_bug_end:
5226 dev_kfree_skb(skb);
5227
5228 return NETDEV_TX_OK;
5229}
52c0fd83 5230
5a6f3074
MC		 5231/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5232 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5233 */
5234static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5235{
5236 struct tg3 *tp = netdev_priv(dev);
1da177e4 5237 u32 len, entry, base_flags, mss;
90079ce8 5238 struct skb_shared_info *sp;
1da177e4 5239 int would_hit_hwbug;
90079ce8 5240 dma_addr_t mapping;
1da177e4
LT		 5241
5242 len = skb_headlen(skb);
5243
00b70504 5244 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5245 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5246 * interrupt. Furthermore, IRQ processing runs lockless so we have
5247 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5248 */
1b2a7205 5249 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5250 if (!netif_queue_stopped(dev)) {
5251 netif_stop_queue(dev);
5252
5253 /* This is a hard error, log it. */
5254 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5255 "queue awake!\n", dev->name);
5256 }
1da177e4
LT		 5257 return NETDEV_TX_BUSY;
5258 }
5259
5260 entry = tp->tx_prod;
5261 base_flags = 0;
84fa7933 5262 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5263 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5264 mss = 0;
c13e3713 5265 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5266 struct iphdr *iph;
52c0fd83 5267 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5268
5269 if (skb_header_cloned(skb) &&
5270 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5271 dev_kfree_skb(skb);
5272 goto out_unlock;
5273 }
5274
ab6a5bb6 5275 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5276 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5277
52c0fd83
MC		 5278 hdr_len = ip_tcp_len + tcp_opt_len;
5279 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5280 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5281 return (tg3_tso_bug(tp, skb));
5282
1da177e4
LT		 5283 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5284 TXD_FLAG_CPU_POST_DMA);
5285
eddc9ec5
ACM		 5286 iph = ip_hdr(skb);
5287 iph->check = 0;
5288 iph->tot_len = htons(mss + hdr_len);
1da177e4 5289 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5290 tcp_hdr(skb)->check = 0;
1da177e4 5291 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5292 } else
5293 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5294 iph->daddr, 0,
5295 IPPROTO_TCP,
5296 0);
1da177e4
LT		 5297
5298 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5299 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5300 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5301 int tsflags;
5302
eddc9ec5 5303 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5304 mss |= (tsflags << 11);
5305 }
5306 } else {
eddc9ec5 5307 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5308 int tsflags;
5309
eddc9ec5 5310 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5311 base_flags |= tsflags << 12;
5312 }
5313 }
5314 }
1da177e4
LT		 5315#if TG3_VLAN_TAG_USED
5316 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5317 base_flags |= (TXD_FLAG_VLAN |
5318 (vlan_tx_tag_get(skb) << 16));
5319#endif
5320
90079ce8
DM		 5321 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5322 dev_kfree_skb(skb);
5323 goto out_unlock;
5324 }
5325
5326 sp = skb_shinfo(skb);
5327
5328 mapping = sp->dma_maps[0];
1da177e4
LT		 5329
5330 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5331
5332 would_hit_hwbug = 0;
5333
41588ba1
MC		 5334 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5335 would_hit_hwbug = 1;
5336 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5337 would_hit_hwbug = 1;
1da177e4
LT		 5338
5339 tg3_set_txd(tp, entry, mapping, len, base_flags,
5340 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5341
5342 entry = NEXT_TX(entry);
5343
5344 /* Now loop through additional data fragments, and queue them. */
5345 if (skb_shinfo(skb)->nr_frags > 0) {
5346 unsigned int i, last;
5347
5348 last = skb_shinfo(skb)->nr_frags - 1;
5349 for (i = 0; i <= last; i++) {
5350 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5351
5352 len = frag->size;
90079ce8 5353 mapping = sp->dma_maps[i + 1];
1da177e4
LT		 5354
5355 tp->tx_buffers[entry].skb = NULL;
1da177e4 5356
c58ec932
MC		 5357 if (tg3_4g_overflow_test(mapping, len))
5358 would_hit_hwbug = 1;
1da177e4 5359
72f2afb8
MC		 5360 if (tg3_40bit_overflow_test(tp, mapping, len))
5361 would_hit_hwbug = 1;
5362
1da177e4
LT		 5363 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5364 tg3_set_txd(tp, entry, mapping, len,
5365 base_flags, (i == last)|(mss << 1));
5366 else
5367 tg3_set_txd(tp, entry, mapping, len,
5368 base_flags, (i == last));
5369
5370 entry = NEXT_TX(entry);
5371 }
5372 }
5373
5374 if (would_hit_hwbug) {
5375 u32 last_plus_one = entry;
5376 u32 start;
1da177e4 5377
c58ec932
MC		 5378 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5379 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5380
5381 /* If the workaround fails due to memory/mapping
5382 * failure, silently drop this packet.
5383 */
72f2afb8 5384 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5385 &start, base_flags, mss))
1da177e4
LT		 5386 goto out_unlock;
5387
5388 entry = start;
5389 }
5390
5391 /* Packets are ready, update Tx producer idx local and on card. */
5392 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5393
5394 tp->tx_prod = entry;
1b2a7205 5395 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5396 netif_stop_queue(dev);
42952231 5397 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5398 netif_wake_queue(tp->dev);
5399 }
1da177e4
LT		 5400
5401out_unlock:
5402 mmiowb();
1da177e4
LT		 5403
5404 dev->trans_start = jiffies;
5405
5406 return NETDEV_TX_OK;
5407}
5408
5409static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5410 int new_mtu)
5411{
5412 dev->mtu = new_mtu;
5413
ef7f5ec0 5414 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5415 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5416 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5417 ethtool_op_set_tso(dev, 0);
5418 }
5419 else
5420 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5421 } else {
a4e2b347 5422 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5423 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5424 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5425 }
1da177e4
LT		 5426}
5427
5428static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5429{
5430 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5431 int err;
1da177e4
LT		 5432
5433 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5434 return -EINVAL;
5435
5436 if (!netif_running(dev)) {
5437 /* We'll just catch it later when the
5438 * device is up'd.
5439 */
5440 tg3_set_mtu(dev, tp, new_mtu);
5441 return 0;
5442 }
5443
b02fd9e3
MC		 5444 tg3_phy_stop(tp);
5445
1da177e4 5446 tg3_netif_stop(tp);
f47c11ee
DM		 5447
5448 tg3_full_lock(tp, 1);
1da177e4 5449
944d980e 5450 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5451
5452 tg3_set_mtu(dev, tp, new_mtu);
5453
b9ec6c1b 5454 err = tg3_restart_hw(tp, 0);
1da177e4 5455
b9ec6c1b
MC		 5456 if (!err)
5457 tg3_netif_start(tp);
1da177e4 5458
f47c11ee 5459 tg3_full_unlock(tp);
1da177e4 5460
b02fd9e3
MC		 5461 if (!err)
5462 tg3_phy_start(tp);
5463
b9ec6c1b 5464 return err;
1da177e4
LT		 5465}
5466
5467/* Free up pending packets in all rx/tx rings.
5468 *
5469 * The chip has been shut down and the driver detached from
5470 * the networking, so no interrupts or new tx packets will
5471 * end up in the driver. tp->{tx,}lock is not held and we are not
5472 * in an interrupt context and thus may sleep.
5473 */
5474static void tg3_free_rings(struct tg3 *tp)
5475{
5476 struct ring_info *rxp;
5477 int i;
5478
5479 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5480 rxp = &tp->rx_std_buffers[i];
5481
5482 if (rxp->skb == NULL)
5483 continue;
5484 pci_unmap_single(tp->pdev,
5485 pci_unmap_addr(rxp, mapping),
7e72aad4 5486 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 5487 PCI_DMA_FROMDEVICE);
5488 dev_kfree_skb_any(rxp->skb);
5489 rxp->skb = NULL;
5490 }
5491
5492 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5493 rxp = &tp->rx_jumbo_buffers[i];
5494
5495 if (rxp->skb == NULL)
5496 continue;
5497 pci_unmap_single(tp->pdev,
5498 pci_unmap_addr(rxp, mapping),
5499 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5500 PCI_DMA_FROMDEVICE);
5501 dev_kfree_skb_any(rxp->skb);
5502 rxp->skb = NULL;
5503 }
5504
5505 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5506 struct tx_ring_info *txp;
5507 struct sk_buff *skb;
1da177e4
LT		 5508
5509 txp = &tp->tx_buffers[i];
5510 skb = txp->skb;
5511
5512 if (skb == NULL) {
5513 i++;
5514 continue;
5515 }
5516
90079ce8 5517 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5518
90079ce8 5519 txp->skb = NULL;
1da177e4 5520
90079ce8 5521 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5522
5523 dev_kfree_skb_any(skb);
5524 }
5525}
5526
5527/* Initialize tx/rx rings for packet processing.
5528 *
5529 * The chip has been shut down and the driver detached from
5530 * the networking, so no interrupts or new tx packets will
5531 * end up in the driver. tp->{tx,}lock are held and thus
5532 * we may not sleep.
5533 */
32d8c572 5534static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 5535{
5536 u32 i;
5537
5538 /* Free up all the SKBs. */
5539 tg3_free_rings(tp);
5540
5541 /* Zero out all descriptors. */
5542 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5543 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5544 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5545 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5546
7e72aad4 5547 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 5548 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 5549 (tp->dev->mtu > ETH_DATA_LEN))
5550 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5551
1da177e4
LT		 5552 /* Initialize invariants of the rings, we only set this
5553 * stuff once. This works because the card does not
5554 * write into the rx buffer posting rings.
5555 */
5556 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5557 struct tg3_rx_buffer_desc *rxd;
5558
5559 rxd = &tp->rx_std[i];
7e72aad4 5560 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 5561 << RXD_LEN_SHIFT;
5562 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5563 rxd->opaque = (RXD_OPAQUE_RING_STD |
5564 (i << RXD_OPAQUE_INDEX_SHIFT));
5565 }
5566
0f893dc6 5567 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5568 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5569 struct tg3_rx_buffer_desc *rxd;
5570
5571 rxd = &tp->rx_jumbo[i];
5572 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5573 << RXD_LEN_SHIFT;
5574 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5575 RXD_FLAG_JUMBO;
5576 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5577 (i << RXD_OPAQUE_INDEX_SHIFT));
5578 }
5579 }
5580
5581 /* Now allocate fresh SKBs for each rx ring. */
5582 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5583 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5584 printk(KERN_WARNING PFX
5585 "%s: Using a smaller RX standard ring, "
5586 "only %d out of %d buffers were allocated "
5587 "successfully.\n",
5588 tp->dev->name, i, tp->rx_pending);
5589 if (i == 0)
5590 return -ENOMEM;
5591 tp->rx_pending = i;
1da177e4 5592 break;
32d8c572 5593 }
1da177e4
LT		 5594 }
5595
0f893dc6 5596 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5597 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5598 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5599 -1, i) < 0) {
5600 printk(KERN_WARNING PFX
5601 "%s: Using a smaller RX jumbo ring, "
5602 "only %d out of %d buffers were "
5603 "allocated successfully.\n",
5604 tp->dev->name, i, tp->rx_jumbo_pending);
5605 if (i == 0) {
5606 tg3_free_rings(tp);
5607 return -ENOMEM;
5608 }
5609 tp->rx_jumbo_pending = i;
1da177e4 5610 break;
32d8c572 5611 }
1da177e4
LT		 5612 }
5613 }
32d8c572 5614 return 0;
1da177e4
LT		 5615}
5616
5617/*
5618 * Must not be invoked with interrupt sources disabled and
5619 * the hardware shutdown down.
5620 */
5621static void tg3_free_consistent(struct tg3 *tp)
5622{
b4558ea9
JJ		 5623 kfree(tp->rx_std_buffers);
5624 tp->rx_std_buffers = NULL;
1da177e4
LT		 5625 if (tp->rx_std) {
5626 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5627 tp->rx_std, tp->rx_std_mapping);
5628 tp->rx_std = NULL;
5629 }
5630 if (tp->rx_jumbo) {
5631 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5632 tp->rx_jumbo, tp->rx_jumbo_mapping);
5633 tp->rx_jumbo = NULL;
5634 }
5635 if (tp->rx_rcb) {
5636 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5637 tp->rx_rcb, tp->rx_rcb_mapping);
5638 tp->rx_rcb = NULL;
5639 }
5640 if (tp->tx_ring) {
5641 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5642 tp->tx_ring, tp->tx_desc_mapping);
5643 tp->tx_ring = NULL;
5644 }
5645 if (tp->hw_status) {
5646 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5647 tp->hw_status, tp->status_mapping);
5648 tp->hw_status = NULL;
5649 }
5650 if (tp->hw_stats) {
5651 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5652 tp->hw_stats, tp->stats_mapping);
5653 tp->hw_stats = NULL;
5654 }
5655}
5656
5657/*
5658 * Must not be invoked with interrupt sources disabled and
5659 * the hardware shutdown down. Can sleep.
5660 */
5661static int tg3_alloc_consistent(struct tg3 *tp)
5662{
bd2b3343 5663 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5664 (TG3_RX_RING_SIZE +
5665 TG3_RX_JUMBO_RING_SIZE)) +
5666 (sizeof(struct tx_ring_info) *
5667 TG3_TX_RING_SIZE),
5668 GFP_KERNEL);
5669 if (!tp->rx_std_buffers)
5670 return -ENOMEM;
5671
1da177e4
LT		 5672 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5673 tp->tx_buffers = (struct tx_ring_info *)
5674 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5675
5676 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5677 &tp->rx_std_mapping);
5678 if (!tp->rx_std)
5679 goto err_out;
5680
5681 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5682 &tp->rx_jumbo_mapping);
5683
5684 if (!tp->rx_jumbo)
5685 goto err_out;
5686
5687 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5688 &tp->rx_rcb_mapping);
5689 if (!tp->rx_rcb)
5690 goto err_out;
5691
5692 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5693 &tp->tx_desc_mapping);
5694 if (!tp->tx_ring)
5695 goto err_out;
5696
5697 tp->hw_status = pci_alloc_consistent(tp->pdev,
5698 TG3_HW_STATUS_SIZE,
5699 &tp->status_mapping);
5700 if (!tp->hw_status)
5701 goto err_out;
5702
5703 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5704 sizeof(struct tg3_hw_stats),
5705 &tp->stats_mapping);
5706 if (!tp->hw_stats)
5707 goto err_out;
5708
5709 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5710 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5711
5712 return 0;
5713
5714err_out:
5715 tg3_free_consistent(tp);
5716 return -ENOMEM;
5717}
5718
5719#define MAX_WAIT_CNT 1000
5720
5721/* To stop a block, clear the enable bit and poll till it
5722 * clears. tp->lock is held.
5723 */
b3b7d6be 5724static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5725{
5726 unsigned int i;
5727 u32 val;
5728
5729 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5730 switch (ofs) {
5731 case RCVLSC_MODE:
5732 case DMAC_MODE:
5733 case MBFREE_MODE:
5734 case BUFMGR_MODE:
5735 case MEMARB_MODE:
5736 /* We can't enable/disable these bits of the
5737 * 5705/5750, just say success.
5738 */
5739 return 0;
5740
5741 default:
5742 break;
855e1111 5743 }
1da177e4
LT		 5744 }
5745
5746 val = tr32(ofs);
5747 val &= ~enable_bit;
5748 tw32_f(ofs, val);
5749
5750 for (i = 0; i < MAX_WAIT_CNT; i++) {
5751 udelay(100);
5752 val = tr32(ofs);
5753 if ((val & enable_bit) == 0)
5754 break;
5755 }
5756
b3b7d6be 5757 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5758 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5759 "ofs=%lx enable_bit=%x\n",
5760 ofs, enable_bit);
5761 return -ENODEV;
5762 }
5763
5764 return 0;
5765}
5766
5767/* tp->lock is held. */
b3b7d6be 5768static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5769{
5770 int i, err;
5771
5772 tg3_disable_ints(tp);
5773
5774 tp->rx_mode &= ~RX_MODE_ENABLE;
5775 tw32_f(MAC_RX_MODE, tp->rx_mode);
5776 udelay(10);
5777
b3b7d6be
DM		 5778 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5779 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5780 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5781 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5782 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5783 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5784
5785 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5786 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5787 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5788 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5789 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5790 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5791 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5792
5793 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5794 tw32_f(MAC_MODE, tp->mac_mode);
5795 udelay(40);
5796
5797 tp->tx_mode &= ~TX_MODE_ENABLE;
5798 tw32_f(MAC_TX_MODE, tp->tx_mode);
5799
5800 for (i = 0; i < MAX_WAIT_CNT; i++) {
5801 udelay(100);
5802 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5803 break;
5804 }
5805 if (i >= MAX_WAIT_CNT) {
5806 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5807 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5808 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5809 err |= -ENODEV;
1da177e4
LT		 5810 }
5811
e6de8ad1 5812 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5813 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5814 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5815
5816 tw32(FTQ_RESET, 0xffffffff);
5817 tw32(FTQ_RESET, 0x00000000);
5818
b3b7d6be
DM		 5819 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5820 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5821
5822 if (tp->hw_status)
5823 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5824 if (tp->hw_stats)
5825 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5826
1da177e4
LT		 5827 return err;
5828}
5829
0d3031d9
MC		 5830static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5831{
5832 int i;
5833 u32 apedata;
5834
5835 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5836 if (apedata != APE_SEG_SIG_MAGIC)
5837 return;
5838
5839 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5840 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5841 return;
5842
5843 /* Wait for up to 1 millisecond for APE to service previous event. */
5844 for (i = 0; i < 10; i++) {
5845 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5846 return;
5847
5848 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5849
5850 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5851 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5852 event | APE_EVENT_STATUS_EVENT_PENDING);
5853
5854 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5855
5856 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5857 break;
5858
5859 udelay(100);
5860 }
5861
5862 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5863 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5864}
5865
5866static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5867{
5868 u32 event;
5869 u32 apedata;
5870
5871 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5872 return;
5873
5874 switch (kind) {
5875 case RESET_KIND_INIT:
5876 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5877 APE_HOST_SEG_SIG_MAGIC);
5878 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5879 APE_HOST_SEG_LEN_MAGIC);
5880 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5881 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5882 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5883 APE_HOST_DRIVER_ID_MAGIC);
5884 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5885 APE_HOST_BEHAV_NO_PHYLOCK);
5886
5887 event = APE_EVENT_STATUS_STATE_START;
5888 break;
5889 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5890 /* With the interface we are currently using,
5891 * APE does not track driver state. Wiping
5892 * out the HOST SEGMENT SIGNATURE forces
5893 * the APE to assume OS absent status.
5894 */
5895 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5896
0d3031d9
MC		 5897 event = APE_EVENT_STATUS_STATE_UNLOAD;
5898 break;
5899 case RESET_KIND_SUSPEND:
5900 event = APE_EVENT_STATUS_STATE_SUSPEND;
5901 break;
5902 default:
5903 return;
5904 }
5905
5906 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5907
5908 tg3_ape_send_event(tp, event);
5909}
5910
1da177e4
LT		 5911/* tp->lock is held. */
5912static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5913{
f49639e6
DM		 5914 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5915 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5916
5917 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5918 switch (kind) {
5919 case RESET_KIND_INIT:
5920 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5921 DRV_STATE_START);
5922 break;
5923
5924 case RESET_KIND_SHUTDOWN:
5925 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5926 DRV_STATE_UNLOAD);
5927 break;
5928
5929 case RESET_KIND_SUSPEND:
5930 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5931 DRV_STATE_SUSPEND);
5932 break;
5933
5934 default:
5935 break;
855e1111 5936 }
1da177e4 5937 }
0d3031d9
MC		 5938
5939 if (kind == RESET_KIND_INIT ||
5940 kind == RESET_KIND_SUSPEND)
5941 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5942}
5943
5944/* tp->lock is held. */
5945static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5946{
5947 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5948 switch (kind) {
5949 case RESET_KIND_INIT:
5950 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5951 DRV_STATE_START_DONE);
5952 break;
5953
5954 case RESET_KIND_SHUTDOWN:
5955 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5956 DRV_STATE_UNLOAD_DONE);
5957 break;
5958
5959 default:
5960 break;
855e1111 5961 }
1da177e4 5962 }
0d3031d9
MC		 5963
5964 if (kind == RESET_KIND_SHUTDOWN)
5965 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5966}
5967
5968/* tp->lock is held. */
5969static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5970{
5971 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5972 switch (kind) {
5973 case RESET_KIND_INIT:
5974 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5975 DRV_STATE_START);
5976 break;
5977
5978 case RESET_KIND_SHUTDOWN:
5979 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5980 DRV_STATE_UNLOAD);
5981 break;
5982
5983 case RESET_KIND_SUSPEND:
5984 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5985 DRV_STATE_SUSPEND);
5986 break;
5987
5988 default:
5989 break;
855e1111 5990 }
1da177e4
LT		 5991 }
5992}
5993
7a6f4369
MC		 5994static int tg3_poll_fw(struct tg3 *tp)
5995{
5996 int i;
5997 u32 val;
5998
b5d3772c 5999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6000 /* Wait up to 20ms for init done. */
6001 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6002 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6003 return 0;
0ccead18 6004 udelay(100);
b5d3772c
MC		 6005 }
6006 return -ENODEV;
6007 }
6008
7a6f4369
MC		 6009 /* Wait for firmware initialization to complete. */
6010 for (i = 0; i < 100000; i++) {
6011 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6012 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6013 break;
6014 udelay(10);
6015 }
6016
6017 /* Chip might not be fitted with firmware. Some Sun onboard
6018 * parts are configured like that. So don't signal the timeout
6019 * of the above loop as an error, but do report the lack of
6020 * running firmware once.
6021 */
6022 if (i >= 100000 &&
6023 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6024 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6025
6026 printk(KERN_INFO PFX "%s: No firmware running.\n",
6027 tp->dev->name);
6028 }
6029
6030 return 0;
6031}
6032
ee6a99b5
MC		 6033/* Save PCI command register before chip reset */
6034static void tg3_save_pci_state(struct tg3 *tp)
6035{
8a6eac90 6036 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6037}
6038
6039/* Restore PCI state after chip reset */
6040static void tg3_restore_pci_state(struct tg3 *tp)
6041{
6042 u32 val;
6043
6044 /* Re-enable indirect register accesses. */
6045 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6046 tp->misc_host_ctrl);
6047
6048 /* Set MAX PCI retry to zero. */
6049 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6050 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6051 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6052 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6053 /* Allow reads and writes to the APE register and memory space. */
6054 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6055 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6056 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6057 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6058
8a6eac90 6059 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6060
fcb389df
MC		 6061 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6062 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6063 pcie_set_readrq(tp->pdev, 4096);
6064 else {
6065 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6066 tp->pci_cacheline_sz);
6067 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6068 tp->pci_lat_timer);
6069 }
114342f2 6070 }
5f5c51e3 6071
ee6a99b5 6072 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6073 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6074 u16 pcix_cmd;
6075
6076 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6077 &pcix_cmd);
6078 pcix_cmd &= ~PCI_X_CMD_ERO;
6079 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6080 pcix_cmd);
6081 }
ee6a99b5
MC		 6082
6083 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6084
6085 /* Chip reset on 5780 will reset MSI enable bit,
6086 * so need to restore it.
6087 */
6088 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6089 u16 ctrl;
6090
6091 pci_read_config_word(tp->pdev,
6092 tp->msi_cap + PCI_MSI_FLAGS,
6093 &ctrl);
6094 pci_write_config_word(tp->pdev,
6095 tp->msi_cap + PCI_MSI_FLAGS,
6096 ctrl | PCI_MSI_FLAGS_ENABLE);
6097 val = tr32(MSGINT_MODE);
6098 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6099 }
6100 }
6101}
6102
1da177e4
LT		 6103static void tg3_stop_fw(struct tg3 *);
6104
6105/* tp->lock is held. */
6106static int tg3_chip_reset(struct tg3 *tp)
6107{
6108 u32 val;
1ee582d8 6109 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6110 int err;
1da177e4 6111
f49639e6
DM		 6112 tg3_nvram_lock(tp);
6113
158d7abd
MC		 6114 tg3_mdio_stop(tp);
6115
77b483f1
MC		 6116 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6117
f49639e6
DM		 6118 /* No matching tg3_nvram_unlock() after this because
6119 * chip reset below will undo the nvram lock.
6120 */
6121 tp->nvram_lock_cnt = 0;
1da177e4 6122
ee6a99b5
MC		 6123 /* GRC_MISC_CFG core clock reset will clear the memory
6124 * enable bit in PCI register 4 and the MSI enable bit
6125 * on some chips, so we save relevant registers here.
6126 */
6127 tg3_save_pci_state(tp);
6128
d9ab5ad1 6129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6130 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6131 tw32(GRC_FASTBOOT_PC, 0);
6132
1da177e4
LT		 6133 /*
6134 * We must avoid the readl() that normally takes place.
6135 * It locks machines, causes machine checks, and other
6136 * fun things. So, temporarily disable the 5701
6137 * hardware workaround, while we do the reset.
6138 */
1ee582d8
MC		 6139 write_op = tp->write32;
6140 if (write_op == tg3_write_flush_reg32)
6141 tp->write32 = tg3_write32;
1da177e4 6142
d18edcb2
MC		 6143 /* Prevent the irq handler from reading or writing PCI registers
6144 * during chip reset when the memory enable bit in the PCI command
6145 * register may be cleared. The chip does not generate interrupt
6146 * at this time, but the irq handler may still be called due to irq
6147 * sharing or irqpoll.
6148 */
6149 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6150 if (tp->hw_status) {
6151 tp->hw_status->status = 0;
6152 tp->hw_status->status_tag = 0;
6153 }
d18edcb2
MC		 6154 tp->last_tag = 0;
6155 smp_mb();
6156 synchronize_irq(tp->pdev->irq);
6157
1da177e4
LT		 6158 /* do the reset */
6159 val = GRC_MISC_CFG_CORECLK_RESET;
6160
6161 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6162 if (tr32(0x7e2c) == 0x60) {
6163 tw32(0x7e2c, 0x20);
6164 }
6165 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6166 tw32(GRC_MISC_CFG, (1 << 29));
6167 val |= (1 << 29);
6168 }
6169 }
6170
b5d3772c
MC		 6171 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6172 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6173 tw32(GRC_VCPU_EXT_CTRL,
6174 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6175 }
6176
1da177e4
LT		 6177 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6178 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6179 tw32(GRC_MISC_CFG, val);
6180
1ee582d8
MC		 6181 /* restore 5701 hardware bug workaround write method */
6182 tp->write32 = write_op;
1da177e4
LT		 6183
6184 /* Unfortunately, we have to delay before the PCI read back.
6185 * Some 575X chips even will not respond to a PCI cfg access
6186 * when the reset command is given to the chip.
6187 *
6188 * How do these hardware designers expect things to work
6189 * properly if the PCI write is posted for a long period
6190 * of time? It is always necessary to have some method by
6191 * which a register read back can occur to push the write
6192 * out which does the reset.
6193 *
6194 * For most tg3 variants the trick below was working.
6195 * Ho hum...
6196 */
6197 udelay(120);
6198
6199 /* Flush PCI posted writes. The normal MMIO registers
6200 * are inaccessible at this time so this is the only
6201 * way to make this reliably (actually, this is no longer
6202 * the case, see above). I tried to use indirect
6203 * register read/write but this upset some 5701 variants.
6204 */
6205 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6206
6207 udelay(120);
6208
5e7dfd0f 6209 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
1da177e4
LT		 6210 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6211 int i;
6212 u32 cfg_val;
6213
6214 /* Wait for link training to complete. */
6215 for (i = 0; i < 5000; i++)
6216 udelay(100);
6217
6218 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6219 pci_write_config_dword(tp->pdev, 0xc4,
6220 cfg_val | (1 << 15));
6221 }
5e7dfd0f
MC		 6222
6223 /* Set PCIE max payload size to 128 bytes and
6224 * clear the "no snoop" and "relaxed ordering" bits.
6225 */
6226 pci_write_config_word(tp->pdev,
6227 tp->pcie_cap + PCI_EXP_DEVCTL,
6228 0);
6229
6230 pcie_set_readrq(tp->pdev, 4096);
6231
6232 /* Clear error status */
6233 pci_write_config_word(tp->pdev,
6234 tp->pcie_cap + PCI_EXP_DEVSTA,
6235 PCI_EXP_DEVSTA_CED |
6236 PCI_EXP_DEVSTA_NFED |
6237 PCI_EXP_DEVSTA_FED |
6238 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6239 }
6240
ee6a99b5 6241 tg3_restore_pci_state(tp);
1da177e4 6242
d18edcb2
MC		 6243 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6244
ee6a99b5
MC		 6245 val = 0;
6246 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6247 val = tr32(MEMARB_MODE);
ee6a99b5 6248 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6249
6250 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6251 tg3_stop_fw(tp);
6252 tw32(0x5000, 0x400);
6253 }
6254
6255 tw32(GRC_MODE, tp->grc_mode);
6256
6257 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6258 val = tr32(0xc4);
1da177e4
LT		 6259
6260 tw32(0xc4, val | (1 << 15));
6261 }
6262
6263 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6265 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6266 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6267 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6268 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6269 }
6270
6271 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6272 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6273 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6274 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6275 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6276 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6277 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6278 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6279 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6280 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6281 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6282 } else
6283 tw32_f(MAC_MODE, 0);
6284 udelay(40);
6285
158d7abd
MC		 6286 tg3_mdio_start(tp);
6287
77b483f1
MC		 6288 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6289
7a6f4369
MC		 6290 err = tg3_poll_fw(tp);
6291 if (err)
6292 return err;
1da177e4
LT		 6293
6294 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6295 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6296 val = tr32(0x7c00);
1da177e4
LT		 6297
6298 tw32(0x7c00, val | (1 << 25));
6299 }
6300
6301 /* Reprobe ASF enable state. */
6302 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6303 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6304 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6305 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6306 u32 nic_cfg;
6307
6308 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6309 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6310 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6311 tp->last_event_jiffies = jiffies;
cbf46853 6312 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6313 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6314 }
6315 }
6316
6317 return 0;
6318}
6319
6320/* tp->lock is held. */
6321static void tg3_stop_fw(struct tg3 *tp)
6322{
0d3031d9
MC		 6323 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6324 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6325 /* Wait for RX cpu to ACK the previous event. */
6326 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6327
6328 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6329
6330 tg3_generate_fw_event(tp);
1da177e4 6331
7c5026aa
MC		 6332 /* Wait for RX cpu to ACK this event. */
6333 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6334 }
6335}
6336
6337/* tp->lock is held. */
944d980e 6338static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6339{
6340 int err;
6341
6342 tg3_stop_fw(tp);
6343
944d980e 6344 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6345
b3b7d6be 6346 tg3_abort_hw(tp, silent);
1da177e4
LT		 6347 err = tg3_chip_reset(tp);
6348
944d980e
MC		 6349 tg3_write_sig_legacy(tp, kind);
6350 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6351
6352 if (err)
6353 return err;
6354
6355 return 0;
6356}
6357
1da177e4
LT		 6358#define RX_CPU_SCRATCH_BASE 0x30000
6359#define RX_CPU_SCRATCH_SIZE 0x04000
6360#define TX_CPU_SCRATCH_BASE 0x34000
6361#define TX_CPU_SCRATCH_SIZE 0x04000
6362
6363/* tp->lock is held. */
6364static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6365{
6366 int i;
6367
5d9428de
ES		 6368 BUG_ON(offset == TX_CPU_BASE &&
6369 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6370
b5d3772c
MC		 6371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6372 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6373
6374 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6375 return 0;
6376 }
1da177e4
LT		 6377 if (offset == RX_CPU_BASE) {
6378 for (i = 0; i < 10000; i++) {
6379 tw32(offset + CPU_STATE, 0xffffffff);
6380 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6381 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6382 break;
6383 }
6384
6385 tw32(offset + CPU_STATE, 0xffffffff);
6386 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6387 udelay(10);
6388 } else {
6389 for (i = 0; i < 10000; i++) {
6390 tw32(offset + CPU_STATE, 0xffffffff);
6391 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6392 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6393 break;
6394 }
6395 }
6396
6397 if (i >= 10000) {
6398 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6399 "and %s CPU\n",
6400 tp->dev->name,
6401 (offset == RX_CPU_BASE ? "RX" : "TX"));
6402 return -ENODEV;
6403 }
ec41c7df
MC		 6404
6405 /* Clear firmware's nvram arbitration. */
6406 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6407 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6408 return 0;
6409}
6410
6411struct fw_info {
077f849d
JSR		 6412 unsigned int fw_base;
6413 unsigned int fw_len;
6414 const __be32 *fw_data;
1da177e4
LT		 6415};
6416
6417/* tp->lock is held. */
6418static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6419 int cpu_scratch_size, struct fw_info *info)
6420{
ec41c7df 6421 int err, lock_err, i;
1da177e4
LT		 6422 void (*write_op)(struct tg3 *, u32, u32);
6423
6424 if (cpu_base == TX_CPU_BASE &&
6425 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6426 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6427 "TX cpu firmware on %s which is 5705.\n",
6428 tp->dev->name);
6429 return -EINVAL;
6430 }
6431
6432 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6433 write_op = tg3_write_mem;
6434 else
6435 write_op = tg3_write_indirect_reg32;
6436
1b628151
MC		 6437 /* It is possible that bootcode is still loading at this point.
6438 * Get the nvram lock first before halting the cpu.
6439 */
ec41c7df 6440 lock_err = tg3_nvram_lock(tp);
1da177e4 6441 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6442 if (!lock_err)
6443 tg3_nvram_unlock(tp);
1da177e4
LT		 6444 if (err)
6445 goto out;
6446
6447 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6448 write_op(tp, cpu_scratch_base + i, 0);
6449 tw32(cpu_base + CPU_STATE, 0xffffffff);
6450 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6451 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6452 write_op(tp, (cpu_scratch_base +
077f849d 6453 (info->fw_base & 0xffff) +
1da177e4 6454 (i * sizeof(u32))),
077f849d 6455 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6456
6457 err = 0;
6458
6459out:
1da177e4
LT		 6460 return err;
6461}
6462
6463/* tp->lock is held. */
6464static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6465{
6466 struct fw_info info;
077f849d 6467 const __be32 *fw_data;
1da177e4
LT		 6468 int err, i;
6469
077f849d
JSR		 6470 fw_data = (void *)tp->fw->data;
6471
6472 /* Firmware blob starts with version numbers, followed by
6473 start address and length. We are setting complete length.
6474 length = end_address_of_bss - start_address_of_text.
6475 Remainder is the blob to be loaded contiguously
6476 from start address. */
6477
6478 info.fw_base = be32_to_cpu(fw_data[1]);
6479 info.fw_len = tp->fw->size - 12;
6480 info.fw_data = &fw_data[3];
1da177e4
LT		 6481
6482 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6483 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6484 &info);
6485 if (err)
6486 return err;
6487
6488 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6489 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6490 &info);
6491 if (err)
6492 return err;
6493
6494 /* Now startup only the RX cpu. */
6495 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6496 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6497
6498 for (i = 0; i < 5; i++) {
077f849d 6499 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6500 break;
6501 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6502 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6503 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6504 udelay(1000);
6505 }
6506 if (i >= 5) {
6507 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6508 "to set RX CPU PC, is %08x should be %08x\n",
6509 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6510 info.fw_base);
1da177e4
LT		 6511 return -ENODEV;
6512 }
6513 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6514 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6515
6516 return 0;
6517}
6518
1da177e4 6519/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6520
6521/* tp->lock is held. */
6522static int tg3_load_tso_firmware(struct tg3 *tp)
6523{
6524 struct fw_info info;
077f849d 6525 const __be32 *fw_data;
1da177e4
LT		 6526 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6527 int err, i;
6528
6529 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6530 return 0;
6531
077f849d
JSR		 6532 fw_data = (void *)tp->fw->data;
6533
6534 /* Firmware blob starts with version numbers, followed by
6535 start address and length. We are setting complete length.
6536 length = end_address_of_bss - start_address_of_text.
6537 Remainder is the blob to be loaded contiguously
6538 from start address. */
6539
6540 info.fw_base = be32_to_cpu(fw_data[1]);
6541 cpu_scratch_size = tp->fw_len;
6542 info.fw_len = tp->fw->size - 12;
6543 info.fw_data = &fw_data[3];
6544
1da177e4 6545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6546 cpu_base = RX_CPU_BASE;
6547 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6548 } else {
1da177e4
LT		 6549 cpu_base = TX_CPU_BASE;
6550 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6551 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6552 }
6553
6554 err = tg3_load_firmware_cpu(tp, cpu_base,
6555 cpu_scratch_base, cpu_scratch_size,
6556 &info);
6557 if (err)
6558 return err;
6559
6560 /* Now startup the cpu. */
6561 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6562 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6563
6564 for (i = 0; i < 5; i++) {
077f849d 6565 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6566 break;
6567 tw32(cpu_base + CPU_STATE, 0xffffffff);
6568 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6569 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6570 udelay(1000);
6571 }
6572 if (i >= 5) {
6573 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6574 "to set CPU PC, is %08x should be %08x\n",
6575 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6576 info.fw_base);
1da177e4
LT		 6577 return -ENODEV;
6578 }
6579 tw32(cpu_base + CPU_STATE, 0xffffffff);
6580 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6581 return 0;
6582}
6583
1da177e4 6584
1da177e4
LT		 6585static int tg3_set_mac_addr(struct net_device *dev, void *p)
6586{
6587 struct tg3 *tp = netdev_priv(dev);
6588 struct sockaddr *addr = p;
986e0aeb 6589 int err = 0, skip_mac_1 = 0;
1da177e4 6590
f9804ddb
MC		 6591 if (!is_valid_ether_addr(addr->sa_data))
6592 return -EINVAL;
6593
1da177e4
LT		 6594 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6595
e75f7c90
MC		 6596 if (!netif_running(dev))
6597 return 0;
6598
58712ef9 6599 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6600 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6601
986e0aeb
MC		 6602 addr0_high = tr32(MAC_ADDR_0_HIGH);
6603 addr0_low = tr32(MAC_ADDR_0_LOW);
6604 addr1_high = tr32(MAC_ADDR_1_HIGH);
6605 addr1_low = tr32(MAC_ADDR_1_LOW);
6606
6607 /* Skip MAC addr 1 if ASF is using it. */
6608 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6609 !(addr1_high == 0 && addr1_low == 0))
6610 skip_mac_1 = 1;
58712ef9 6611 }
986e0aeb
MC		 6612 spin_lock_bh(&tp->lock);
6613 __tg3_set_mac_addr(tp, skip_mac_1);
6614 spin_unlock_bh(&tp->lock);
1da177e4 6615
b9ec6c1b 6616 return err;
1da177e4
LT		 6617}
6618
6619/* tp->lock is held. */
6620static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6621 dma_addr_t mapping, u32 maxlen_flags,
6622 u32 nic_addr)
6623{
6624 tg3_write_mem(tp,
6625 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6626 ((u64) mapping >> 32));
6627 tg3_write_mem(tp,
6628 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6629 ((u64) mapping & 0xffffffff));
6630 tg3_write_mem(tp,
6631 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6632 maxlen_flags);
6633
6634 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6635 tg3_write_mem(tp,
6636 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6637 nic_addr);
6638}
6639
6640static void __tg3_set_rx_mode(struct net_device *);
d244c892 6641static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6642{
6643 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6644 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6645 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6646 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6647 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6648 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6649 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6650 }
6651 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6652 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6653 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6654 u32 val = ec->stats_block_coalesce_usecs;
6655
6656 if (!netif_carrier_ok(tp->dev))
6657 val = 0;
6658
6659 tw32(HOSTCC_STAT_COAL_TICKS, val);
6660 }
6661}
1da177e4
LT		 6662
6663/* tp->lock is held. */
8e7a22e3 6664static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6665{
6666 u32 val, rdmac_mode;
6667 int i, err, limit;
6668
6669 tg3_disable_ints(tp);
6670
6671 tg3_stop_fw(tp);
6672
6673 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6674
6675 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6676 tg3_abort_hw(tp, 1);
1da177e4
LT		 6677 }
6678
dd477003
MC		 6679 if (reset_phy &&
6680 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6681 tg3_phy_reset(tp);
6682
1da177e4
LT		 6683 err = tg3_chip_reset(tp);
6684 if (err)
6685 return err;
6686
6687 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6688
bcb37f6c 6689 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6690 val = tr32(TG3_CPMU_CTRL);
6691 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6692 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6693
6694 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6695 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6696 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6697 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6698
6699 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6700 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6701 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6702 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6703
6704 val = tr32(TG3_CPMU_HST_ACC);
6705 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6706 val |= CPMU_HST_ACC_MACCLK_6_25;
6707 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6708 }
6709
1da177e4
LT		 6710 /* This works around an issue with Athlon chipsets on
6711 * B3 tigon3 silicon. This bit has no effect on any
6712 * other revision. But do not set this on PCI Express
795d01c5 6713 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6714 */
795d01c5
MC		 6715 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6716 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6717 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6718 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6719 }
1da177e4
LT		 6720
6721 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6722 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6723 val = tr32(TG3PCI_PCISTATE);
6724 val |= PCISTATE_RETRY_SAME_DMA;
6725 tw32(TG3PCI_PCISTATE, val);
6726 }
6727
0d3031d9
MC		 6728 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6729 /* Allow reads and writes to the
6730 * APE register and memory space.
6731 */
6732 val = tr32(TG3PCI_PCISTATE);
6733 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6734 PCISTATE_ALLOW_APE_SHMEM_WR;
6735 tw32(TG3PCI_PCISTATE, val);
6736 }
6737
1da177e4
LT		 6738 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6739 /* Enable some hw fixes. */
6740 val = tr32(TG3PCI_MSI_DATA);
6741 val |= (1 << 26) | (1 << 28) | (1 << 29);
6742 tw32(TG3PCI_MSI_DATA, val);
6743 }
6744
6745 /* Descriptor ring init may make accesses to the
6746 * NIC SRAM area to setup the TX descriptors, so we
6747 * can only do this after the hardware has been
6748 * successfully reset.
6749 */
32d8c572
MC		 6750 err = tg3_init_rings(tp);
6751 if (err)
6752 return err;
1da177e4 6753
9936bcf6 6754 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6755 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6756 /* This value is determined during the probe time DMA
6757 * engine test, tg3_test_dma.
6758 */
6759 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6760 }
1da177e4
LT		 6761
6762 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6763 GRC_MODE_4X_NIC_SEND_RINGS |
6764 GRC_MODE_NO_TX_PHDR_CSUM |
6765 GRC_MODE_NO_RX_PHDR_CSUM);
6766 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6767
6768 /* Pseudo-header checksum is done by hardware logic and not
6769 * the offload processers, so make the chip do the pseudo-
6770 * header checksums on receive. For transmit it is more
6771 * convenient to do the pseudo-header checksum in software
6772 * as Linux does that on transmit for us in all cases.
6773 */
6774 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6775
6776 tw32(GRC_MODE,
6777 tp->grc_mode |
6778 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6779
6780 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6781 val = tr32(GRC_MISC_CFG);
6782 val &= ~0xff;
6783 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6784 tw32(GRC_MISC_CFG, val);
6785
6786 /* Initialize MBUF/DESC pool. */
cbf46853 6787 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6788 /* Do nothing. */
6789 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6790 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6791 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6792 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6793 else
6794 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6795 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6796 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6797 }
1da177e4
LT		 6798 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6799 int fw_len;
6800
077f849d 6801 fw_len = tp->fw_len;
1da177e4
LT		 6802 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6803 tw32(BUFMGR_MB_POOL_ADDR,
6804 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6805 tw32(BUFMGR_MB_POOL_SIZE,
6806 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6807 }
1da177e4 6808
0f893dc6 6809 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6810 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6811 tp->bufmgr_config.mbuf_read_dma_low_water);
6812 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6813 tp->bufmgr_config.mbuf_mac_rx_low_water);
6814 tw32(BUFMGR_MB_HIGH_WATER,
6815 tp->bufmgr_config.mbuf_high_water);
6816 } else {
6817 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6818 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6819 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6820 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6821 tw32(BUFMGR_MB_HIGH_WATER,
6822 tp->bufmgr_config.mbuf_high_water_jumbo);
6823 }
6824 tw32(BUFMGR_DMA_LOW_WATER,
6825 tp->bufmgr_config.dma_low_water);
6826 tw32(BUFMGR_DMA_HIGH_WATER,
6827 tp->bufmgr_config.dma_high_water);
6828
6829 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6830 for (i = 0; i < 2000; i++) {
6831 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6832 break;
6833 udelay(10);
6834 }
6835 if (i >= 2000) {
6836 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6837 tp->dev->name);
6838 return -ENODEV;
6839 }
6840
6841 /* Setup replenish threshold. */
f92905de
MC		 6842 val = tp->rx_pending / 8;
6843 if (val == 0)
6844 val = 1;
6845 else if (val > tp->rx_std_max_post)
6846 val = tp->rx_std_max_post;
b5d3772c
MC		 6847 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6848 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6849 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6850
6851 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6852 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6853 }
f92905de
MC		 6854
6855 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6856
6857 /* Initialize TG3_BDINFO's at:
6858 * RCVDBDI_STD_BD: standard eth size rx ring
6859 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6860 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6861 *
6862 * like so:
6863 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6864 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6865 * ring attribute flags
6866 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6867 *
6868 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6869 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6870 *
6871 * The size of each ring is fixed in the firmware, but the location is
6872 * configurable.
6873 */
6874 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6875 ((u64) tp->rx_std_mapping >> 32));
6876 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6877 ((u64) tp->rx_std_mapping & 0xffffffff));
6878 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6879 NIC_SRAM_RX_BUFFER_DESC);
6880
6881 /* Don't even try to program the JUMBO/MINI buffer descriptor
6882 * configs on 5705.
6883 */
6884 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6885 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6886 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6887 } else {
6888 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6889 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6890
6891 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6892 BDINFO_FLAGS_DISABLED);
6893
6894 /* Setup replenish threshold. */
6895 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6896
0f893dc6 6897 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6898 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6899 ((u64) tp->rx_jumbo_mapping >> 32));
6900 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6901 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6902 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6903 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6904 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6905 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6906 } else {
6907 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6908 BDINFO_FLAGS_DISABLED);
6909 }
6910
6911 }
6912
6913 /* There is only one send ring on 5705/5750, no need to explicitly
6914 * disable the others.
6915 */
6916 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6917 /* Clear out send RCB ring in SRAM. */
6918 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6919 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6920 BDINFO_FLAGS_DISABLED);
6921 }
6922
6923 tp->tx_prod = 0;
6924 tp->tx_cons = 0;
6925 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6926 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6927
6928 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6929 tp->tx_desc_mapping,
6930 (TG3_TX_RING_SIZE <<
6931 BDINFO_FLAGS_MAXLEN_SHIFT),
6932 NIC_SRAM_TX_BUFFER_DESC);
6933
6934 /* There is only one receive return ring on 5705/5750, no need
6935 * to explicitly disable the others.
6936 */
6937 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6938 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6939 i += TG3_BDINFO_SIZE) {
6940 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6941 BDINFO_FLAGS_DISABLED);
6942 }
6943 }
6944
6945 tp->rx_rcb_ptr = 0;
6946 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6947
6948 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6949 tp->rx_rcb_mapping,
6950 (TG3_RX_RCB_RING_SIZE(tp) <<
6951 BDINFO_FLAGS_MAXLEN_SHIFT),
6952 0);
6953
6954 tp->rx_std_ptr = tp->rx_pending;
6955 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6956 tp->rx_std_ptr);
6957
0f893dc6 6958 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6959 tp->rx_jumbo_pending : 0;
6960 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6961 tp->rx_jumbo_ptr);
6962
6963 /* Initialize MAC address and backoff seed. */
986e0aeb 6964 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6965
6966 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 6967 tw32(MAC_RX_MTU_SIZE,
6968 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 6969
6970 /* The slot time is changed by tg3_setup_phy if we
6971 * run at gigabit with half duplex.
6972 */
6973 tw32(MAC_TX_LENGTHS,
6974 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6975 (6 << TX_LENGTHS_IPG_SHIFT) |
6976 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6977
6978 /* Receive rules. */
6979 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6980 tw32(RCVLPC_CONFIG, 0x0181);
6981
6982 /* Calculate RDMAC_MODE setting early, we need it to determine
6983 * the RCVLPC_STATE_ENABLE mask.
6984 */
6985 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6986 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6987 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6988 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6989 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 6990
57e6983c 6991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 6992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 6994 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6995 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6996 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6997
85e94ced
MC		 6998 /* If statement applies to 5705 and 5750 PCI devices only */
6999 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7000 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7001 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7002 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7004 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7005 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7006 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7007 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7008 }
7009 }
7010
85e94ced
MC		 7011 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7012 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7013
1da177e4 7014 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7015 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7016
7017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7019 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7020
7021 /* Receive/send statistics. */
1661394e
MC		 7022 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7023 val = tr32(RCVLPC_STATS_ENABLE);
7024 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7025 tw32(RCVLPC_STATS_ENABLE, val);
7026 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7027 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7028 val = tr32(RCVLPC_STATS_ENABLE);
7029 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7030 tw32(RCVLPC_STATS_ENABLE, val);
7031 } else {
7032 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7033 }
7034 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7035 tw32(SNDDATAI_STATSENAB, 0xffffff);
7036 tw32(SNDDATAI_STATSCTRL,
7037 (SNDDATAI_SCTRL_ENABLE |
7038 SNDDATAI_SCTRL_FASTUPD));
7039
7040 /* Setup host coalescing engine. */
7041 tw32(HOSTCC_MODE, 0);
7042 for (i = 0; i < 2000; i++) {
7043 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7044 break;
7045 udelay(10);
7046 }
7047
d244c892 7048 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7049
7050 /* set status block DMA address */
7051 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7052 ((u64) tp->status_mapping >> 32));
7053 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7054 ((u64) tp->status_mapping & 0xffffffff));
7055
7056 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7057 /* Status/statistics block address. See tg3_timer,
7058 * the tg3_periodic_fetch_stats call there, and
7059 * tg3_get_stats to see how this works for 5705/5750 chips.
7060 */
1da177e4
LT		 7061 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7062 ((u64) tp->stats_mapping >> 32));
7063 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7064 ((u64) tp->stats_mapping & 0xffffffff));
7065 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7066 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7067 }
7068
7069 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7070
7071 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7072 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7073 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7074 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7075
7076 /* Clear statistics/status block in chip, and status block in ram. */
7077 for (i = NIC_SRAM_STATS_BLK;
7078 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7079 i += sizeof(u32)) {
7080 tg3_write_mem(tp, i, 0);
7081 udelay(40);
7082 }
7083 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7084
c94e3941
MC		 7085 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7086 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7087 /* reset to prevent losing 1st rx packet intermittently */
7088 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7089 udelay(10);
7090 }
7091
3bda1258
MC		 7092 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7093 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7094 else
7095 tp->mac_mode = 0;
7096 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7097 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7098 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7099 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7100 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7101 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7102 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7103 udelay(40);
7104
314fba34 7105 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7106 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7107 * register to preserve the GPIO settings for LOMs. The GPIOs,
7108 * whether used as inputs or outputs, are set by boot code after
7109 * reset.
7110 */
9d26e213 7111 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7112 u32 gpio_mask;
7113
9d26e213
MC		 7114 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7115 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7116 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7117
7118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7119 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7120 GRC_LCLCTRL_GPIO_OUTPUT3;
7121
af36e6b6
MC		 7122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7123 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7124
aaf84465 7125 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7126 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7127
7128 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7129 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7130 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7131 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7132 }
1da177e4
LT		 7133 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7134 udelay(100);
7135
09ee929c 7136 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 7137 tp->last_tag = 0;
1da177e4
LT		 7138
7139 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7140 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7141 udelay(40);
7142 }
7143
7144 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7145 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7146 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7147 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7148 WDMAC_MODE_LNGREAD_ENAB);
7149
85e94ced
MC		 7150 /* If statement applies to 5705 and 5750 PCI devices only */
7151 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7152 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7154 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7155 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7156 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7157 /* nothing */
7158 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7159 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7160 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7161 val |= WDMAC_MODE_RX_ACCEL;
7162 }
7163 }
7164
d9ab5ad1 7165 /* Enable host coalescing bug fix */
321d32a0 7166 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7167 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7168
1da177e4
LT		 7169 tw32_f(WDMAC_MODE, val);
7170 udelay(40);
7171
9974a356
MC		 7172 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7173 u16 pcix_cmd;
7174
7175 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7176 &pcix_cmd);
1da177e4 7177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7178 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7179 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7180 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7181 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7182 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7183 }
9974a356
MC		 7184 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7185 pcix_cmd);
1da177e4
LT		 7186 }
7187
7188 tw32_f(RDMAC_MODE, rdmac_mode);
7189 udelay(40);
7190
7191 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7192 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7193 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7194
7195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7196 tw32(SNDDATAC_MODE,
7197 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7198 else
7199 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7200
1da177e4
LT		 7201 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7202 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7203 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7204 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7205 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7206 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7207 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7208 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7209
7210 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7211 err = tg3_load_5701_a0_firmware_fix(tp);
7212 if (err)
7213 return err;
7214 }
7215
1da177e4
LT		 7216 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7217 err = tg3_load_tso_firmware(tp);
7218 if (err)
7219 return err;
7220 }
1da177e4
LT		 7221
7222 tp->tx_mode = TX_MODE_ENABLE;
7223 tw32_f(MAC_TX_MODE, tp->tx_mode);
7224 udelay(100);
7225
7226 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7227 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7228 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7229
1da177e4
LT		 7230 tw32_f(MAC_RX_MODE, tp->rx_mode);
7231 udelay(10);
7232
1da177e4
LT		 7233 tw32(MAC_LED_CTRL, tp->led_ctrl);
7234
7235 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7236 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7237 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7238 udelay(10);
7239 }
7240 tw32_f(MAC_RX_MODE, tp->rx_mode);
7241 udelay(10);
7242
7243 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7244 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7245 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7246 /* Set drive transmission level to 1.2V */
7247 /* only if the signal pre-emphasis bit is not set */
7248 val = tr32(MAC_SERDES_CFG);
7249 val &= 0xfffff000;
7250 val |= 0x880;
7251 tw32(MAC_SERDES_CFG, val);
7252 }
7253 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7254 tw32(MAC_SERDES_CFG, 0x616000);
7255 }
7256
7257 /* Prevent chip from dropping frames when flow control
7258 * is enabled.
7259 */
7260 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7261
7262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7263 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7264 /* Use hardware link auto-negotiation */
7265 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7266 }
7267
d4d2c558
MC		 7268 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7269 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7270 u32 tmp;
7271
7272 tmp = tr32(SERDES_RX_CTRL);
7273 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7274 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7275 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7276 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7277 }
7278
dd477003
MC		 7279 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7280 if (tp->link_config.phy_is_low_power) {
7281 tp->link_config.phy_is_low_power = 0;
7282 tp->link_config.speed = tp->link_config.orig_speed;
7283 tp->link_config.duplex = tp->link_config.orig_duplex;
7284 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7285 }
1da177e4 7286
dd477003
MC		 7287 err = tg3_setup_phy(tp, 0);
7288 if (err)
7289 return err;
1da177e4 7290
dd477003
MC		 7291 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7292 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7293 u32 tmp;
7294
7295 /* Clear CRC stats. */
7296 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7297 tg3_writephy(tp, MII_TG3_TEST1,
7298 tmp | MII_TG3_TEST1_CRC_EN);
7299 tg3_readphy(tp, 0x14, &tmp);
7300 }
1da177e4
LT		 7301 }
7302 }
7303
7304 __tg3_set_rx_mode(tp->dev);
7305
7306 /* Initialize receive rules. */
7307 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7308 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7309 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7310 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7311
4cf78e4f 7312 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7313 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7314 limit = 8;
7315 else
7316 limit = 16;
7317 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7318 limit -= 4;
7319 switch (limit) {
7320 case 16:
7321 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7322 case 15:
7323 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7324 case 14:
7325 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7326 case 13:
7327 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7328 case 12:
7329 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7330 case 11:
7331 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7332 case 10:
7333 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7334 case 9:
7335 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7336 case 8:
7337 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7338 case 7:
7339 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7340 case 6:
7341 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7342 case 5:
7343 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7344 case 4:
7345 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7346 case 3:
7347 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7348 case 2:
7349 case 1:
7350
7351 default:
7352 break;
855e1111 7353 }
1da177e4 7354
9ce768ea
MC		 7355 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7356 /* Write our heartbeat update interval to APE. */
7357 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7358 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7359
1da177e4
LT		 7360 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7361
1da177e4
LT		 7362 return 0;
7363}
7364
7365/* Called at device open time to get the chip ready for
7366 * packet processing. Invoked with tp->lock held.
7367 */
8e7a22e3 7368static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7369{
1da177e4
LT		 7370 tg3_switch_clocks(tp);
7371
7372 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7373
2f751b67 7374 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7375}
7376
7377#define TG3_STAT_ADD32(PSTAT, REG) \
7378do { u32 __val = tr32(REG); \
7379 (PSTAT)->low += __val; \
7380 if ((PSTAT)->low < __val) \
7381 (PSTAT)->high += 1; \
7382} while (0)
7383
7384static void tg3_periodic_fetch_stats(struct tg3 *tp)
7385{
7386 struct tg3_hw_stats *sp = tp->hw_stats;
7387
7388 if (!netif_carrier_ok(tp->dev))
7389 return;
7390
7391 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7392 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7393 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7394 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7395 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7396 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7397 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7398 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7399 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7400 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7401 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7402 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7403 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7404
7405 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7406 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7407 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7408 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7409 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7410 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7411 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7412 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7413 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7414 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7415 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7416 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7417 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7418 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7419
7420 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7421 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7422 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7423}
7424
7425static void tg3_timer(unsigned long __opaque)
7426{
7427 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7428
f475f163
MC		 7429 if (tp->irq_sync)
7430 goto restart_timer;
7431
f47c11ee 7432 spin_lock(&tp->lock);
1da177e4 7433
fac9b83e
DM		 7434 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7435 /* All of this garbage is because when using non-tagged
7436 * IRQ status the mailbox/status_block protocol the chip
7437 * uses with the cpu is race prone.
7438 */
7439 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7440 tw32(GRC_LOCAL_CTRL,
7441 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7442 } else {
7443 tw32(HOSTCC_MODE, tp->coalesce_mode |
7444 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7445 }
1da177e4 7446
fac9b83e
DM		 7447 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7448 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7449 spin_unlock(&tp->lock);
fac9b83e
DM		 7450 schedule_work(&tp->reset_task);
7451 return;
7452 }
1da177e4
LT		 7453 }
7454
1da177e4
LT		 7455 /* This part only runs once per second. */
7456 if (!--tp->timer_counter) {
fac9b83e
DM		 7457 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7458 tg3_periodic_fetch_stats(tp);
7459
1da177e4
LT		 7460 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7461 u32 mac_stat;
7462 int phy_event;
7463
7464 mac_stat = tr32(MAC_STATUS);
7465
7466 phy_event = 0;
7467 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7468 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7469 phy_event = 1;
7470 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7471 phy_event = 1;
7472
7473 if (phy_event)
7474 tg3_setup_phy(tp, 0);
7475 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7476 u32 mac_stat = tr32(MAC_STATUS);
7477 int need_setup = 0;
7478
7479 if (netif_carrier_ok(tp->dev) &&
7480 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7481 need_setup = 1;
7482 }
7483 if (! netif_carrier_ok(tp->dev) &&
7484 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7485 MAC_STATUS_SIGNAL_DET))) {
7486 need_setup = 1;
7487 }
7488 if (need_setup) {
3d3ebe74
MC		 7489 if (!tp->serdes_counter) {
7490 tw32_f(MAC_MODE,
7491 (tp->mac_mode &
7492 ~MAC_MODE_PORT_MODE_MASK));
7493 udelay(40);
7494 tw32_f(MAC_MODE, tp->mac_mode);
7495 udelay(40);
7496 }
1da177e4
LT		 7497 tg3_setup_phy(tp, 0);
7498 }
747e8f8b
MC		 7499 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7500 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7501
7502 tp->timer_counter = tp->timer_multiplier;
7503 }
7504
130b8e4d
MC		 7505 /* Heartbeat is only sent once every 2 seconds.
7506 *
7507 * The heartbeat is to tell the ASF firmware that the host
7508 * driver is still alive. In the event that the OS crashes,
7509 * ASF needs to reset the hardware to free up the FIFO space
7510 * that may be filled with rx packets destined for the host.
7511 * If the FIFO is full, ASF will no longer function properly.
7512 *
7513 * Unintended resets have been reported on real time kernels
7514 * where the timer doesn't run on time. Netpoll will also have
7515 * same problem.
7516 *
7517 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7518 * to check the ring condition when the heartbeat is expiring
7519 * before doing the reset. This will prevent most unintended
7520 * resets.
7521 */
1da177e4 7522 if (!--tp->asf_counter) {
bc7959b2
MC		 7523 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7524 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7525 tg3_wait_for_event_ack(tp);
7526
bbadf503 7527 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7528 FWCMD_NICDRV_ALIVE3);
bbadf503 7529 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7530 /* 5 seconds timeout */
bbadf503 7531 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7532
7533 tg3_generate_fw_event(tp);
1da177e4
LT		 7534 }
7535 tp->asf_counter = tp->asf_multiplier;
7536 }
7537
f47c11ee 7538 spin_unlock(&tp->lock);
1da177e4 7539
f475f163 7540restart_timer:
1da177e4
LT		 7541 tp->timer.expires = jiffies + tp->timer_offset;
7542 add_timer(&tp->timer);
7543}
7544
81789ef5 7545static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7546{
7d12e780 7547 irq_handler_t fn;
fcfa0a32
MC		 7548 unsigned long flags;
7549 struct net_device *dev = tp->dev;
7550
7551 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7552 fn = tg3_msi;
7553 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7554 fn = tg3_msi_1shot;
1fb9df5d 7555 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7556 } else {
7557 fn = tg3_interrupt;
7558 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7559 fn = tg3_interrupt_tagged;
1fb9df5d 7560 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7561 }
7562 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7563}
7564
7938109f
MC		 7565static int tg3_test_interrupt(struct tg3 *tp)
7566{
7567 struct net_device *dev = tp->dev;
b16250e3 7568 int err, i, intr_ok = 0;
7938109f 7569
d4bc3927
MC		 7570 if (!netif_running(dev))
7571 return -ENODEV;
7572
7938109f
MC		 7573 tg3_disable_ints(tp);
7574
7575 free_irq(tp->pdev->irq, dev);
7576
7577 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7578 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7579 if (err)
7580 return err;
7581
38f3843e 7582 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7583 tg3_enable_ints(tp);
7584
7585 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7586 HOSTCC_MODE_NOW);
7587
7588 for (i = 0; i < 5; i++) {
b16250e3
MC		 7589 u32 int_mbox, misc_host_ctrl;
7590
09ee929c
MC		 7591 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7592 TG3_64BIT_REG_LOW);
b16250e3
MC		 7593 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7594
7595 if ((int_mbox != 0) ||
7596 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7597 intr_ok = 1;
7938109f 7598 break;
b16250e3
MC		 7599 }
7600
7938109f
MC		 7601 msleep(10);
7602 }
7603
7604 tg3_disable_ints(tp);
7605
7606 free_irq(tp->pdev->irq, dev);
6aa20a22 7607
fcfa0a32 7608 err = tg3_request_irq(tp);
7938109f
MC		 7609
7610 if (err)
7611 return err;
7612
b16250e3 7613 if (intr_ok)
7938109f
MC		 7614 return 0;
7615
7616 return -EIO;
7617}
7618
7619/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7620 * successfully restored
7621 */
7622static int tg3_test_msi(struct tg3 *tp)
7623{
7624 struct net_device *dev = tp->dev;
7625 int err;
7626 u16 pci_cmd;
7627
7628 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7629 return 0;
7630
7631 /* Turn off SERR reporting in case MSI terminates with Master
7632 * Abort.
7633 */
7634 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7635 pci_write_config_word(tp->pdev, PCI_COMMAND,
7636 pci_cmd & ~PCI_COMMAND_SERR);
7637
7638 err = tg3_test_interrupt(tp);
7639
7640 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7641
7642 if (!err)
7643 return 0;
7644
7645 /* other failures */
7646 if (err != -EIO)
7647 return err;
7648
7649 /* MSI test failed, go back to INTx mode */
7650 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7651 "switching to INTx mode. Please report this failure to "
7652 "the PCI maintainer and include system chipset information.\n",
7653 tp->dev->name);
7654
7655 free_irq(tp->pdev->irq, dev);
7656 pci_disable_msi(tp->pdev);
7657
7658 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7659
fcfa0a32 7660 err = tg3_request_irq(tp);
7938109f
MC		 7661 if (err)
7662 return err;
7663
7664 /* Need to reset the chip because the MSI cycle may have terminated
7665 * with Master Abort.
7666 */
f47c11ee 7667 tg3_full_lock(tp, 1);
7938109f 7668
944d980e 7669 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7670 err = tg3_init_hw(tp, 1);
7938109f 7671
f47c11ee 7672 tg3_full_unlock(tp);
7938109f
MC		 7673
7674 if (err)
7675 free_irq(tp->pdev->irq, dev);
7676
7677 return err;
7678}
7679
9e9fd12d
MC		 7680static int tg3_request_firmware(struct tg3 *tp)
7681{
7682 const __be32 *fw_data;
7683
7684 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7685 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7686 tp->dev->name, tp->fw_needed);
7687 return -ENOENT;
7688 }
7689
7690 fw_data = (void *)tp->fw->data;
7691
7692 /* Firmware blob starts with version numbers, followed by
7693 * start address and _full_ length including BSS sections
7694 * (which must be longer than the actual data, of course
7695 */
7696
7697 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7698 if (tp->fw_len < (tp->fw->size - 12)) {
7699 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7700 tp->dev->name, tp->fw_len, tp->fw_needed);
7701 release_firmware(tp->fw);
7702 tp->fw = NULL;
7703 return -EINVAL;
7704 }
7705
7706 /* We no longer need firmware; we have it. */
7707 tp->fw_needed = NULL;
7708 return 0;
7709}
7710
1da177e4
LT		 7711static int tg3_open(struct net_device *dev)
7712{
7713 struct tg3 *tp = netdev_priv(dev);
7714 int err;
7715
9e9fd12d
MC		 7716 if (tp->fw_needed) {
7717 err = tg3_request_firmware(tp);
7718 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7719 if (err)
7720 return err;
7721 } else if (err) {
7722 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7723 tp->dev->name);
7724 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7725 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7726 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7727 tp->dev->name);
7728 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7729 }
7730 }
7731
c49a1561
MC		 7732 netif_carrier_off(tp->dev);
7733
bc1c7567 7734 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7735 if (err)
bc1c7567 7736 return err;
2f751b67
MC		 7737
7738 tg3_full_lock(tp, 0);
bc1c7567 7739
1da177e4
LT		 7740 tg3_disable_ints(tp);
7741 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7742
f47c11ee 7743 tg3_full_unlock(tp);
1da177e4
LT		 7744
7745 /* The placement of this call is tied
7746 * to the setup and use of Host TX descriptors.
7747 */
7748 err = tg3_alloc_consistent(tp);
7749 if (err)
7750 return err;
7751
7544b097 7752 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7753 /* All MSI supporting chips should support tagged
7754 * status. Assert that this is the case.
7755 */
7756 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7757 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7758 "Not using MSI.\n", tp->dev->name);
7759 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7760 u32 msi_mode;
7761
7762 msi_mode = tr32(MSGINT_MODE);
7763 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7764 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7765 }
7766 }
fcfa0a32 7767 err = tg3_request_irq(tp);
1da177e4
LT		 7768
7769 if (err) {
88b06bc2
MC		 7770 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7771 pci_disable_msi(tp->pdev);
7772 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7773 }
1da177e4
LT		 7774 tg3_free_consistent(tp);
7775 return err;
7776 }
7777
bea3348e
SH		 7778 napi_enable(&tp->napi);
7779
f47c11ee 7780 tg3_full_lock(tp, 0);
1da177e4 7781
8e7a22e3 7782 err = tg3_init_hw(tp, 1);
1da177e4 7783 if (err) {
944d980e 7784 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7785 tg3_free_rings(tp);
7786 } else {
fac9b83e
DM		 7787 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7788 tp->timer_offset = HZ;
7789 else
7790 tp->timer_offset = HZ / 10;
7791
7792 BUG_ON(tp->timer_offset > HZ);
7793 tp->timer_counter = tp->timer_multiplier =
7794 (HZ / tp->timer_offset);
7795 tp->asf_counter = tp->asf_multiplier =
28fbef78 7796 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7797
7798 init_timer(&tp->timer);
7799 tp->timer.expires = jiffies + tp->timer_offset;
7800 tp->timer.data = (unsigned long) tp;
7801 tp->timer.function = tg3_timer;
1da177e4
LT		 7802 }
7803
f47c11ee 7804 tg3_full_unlock(tp);
1da177e4
LT		 7805
7806 if (err) {
bea3348e 7807 napi_disable(&tp->napi);
88b06bc2
MC		 7808 free_irq(tp->pdev->irq, dev);
7809 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7810 pci_disable_msi(tp->pdev);
7811 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7812 }
1da177e4
LT		 7813 tg3_free_consistent(tp);
7814 return err;
7815 }
7816
7938109f
MC		 7817 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7818 err = tg3_test_msi(tp);
fac9b83e 7819
7938109f 7820 if (err) {
f47c11ee 7821 tg3_full_lock(tp, 0);
7938109f
MC		 7822
7823 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7824 pci_disable_msi(tp->pdev);
7825 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7826 }
944d980e 7827 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7828 tg3_free_rings(tp);
7829 tg3_free_consistent(tp);
7830
f47c11ee 7831 tg3_full_unlock(tp);
7938109f 7832
bea3348e
SH		 7833 napi_disable(&tp->napi);
7834
7938109f
MC		 7835 return err;
7836 }
fcfa0a32
MC		 7837
7838 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7839 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7840 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7841
b5d3772c
MC		 7842 tw32(PCIE_TRANSACTION_CFG,
7843 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7844 }
7845 }
7938109f
MC		 7846 }
7847
b02fd9e3
MC		 7848 tg3_phy_start(tp);
7849
f47c11ee 7850 tg3_full_lock(tp, 0);
1da177e4 7851
7938109f
MC		 7852 add_timer(&tp->timer);
7853 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7854 tg3_enable_ints(tp);
7855
f47c11ee 7856 tg3_full_unlock(tp);
1da177e4
LT		 7857
7858 netif_start_queue(dev);
7859
7860 return 0;
7861}
7862
7863#if 0
7864/*static*/ void tg3_dump_state(struct tg3 *tp)
7865{
7866 u32 val32, val32_2, val32_3, val32_4, val32_5;
7867 u16 val16;
7868 int i;
7869
7870 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7871 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7872 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7873 val16, val32);
7874
7875 /* MAC block */
7876 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7877 tr32(MAC_MODE), tr32(MAC_STATUS));
7878 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7879 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7880 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7881 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7882 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7883 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7884
7885 /* Send data initiator control block */
7886 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7887 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7888 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7889 tr32(SNDDATAI_STATSCTRL));
7890
7891 /* Send data completion control block */
7892 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7893
7894 /* Send BD ring selector block */
7895 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7896 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7897
7898 /* Send BD initiator control block */
7899 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7900 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7901
7902 /* Send BD completion control block */
7903 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7904
7905 /* Receive list placement control block */
7906 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7907 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7908 printk(" RCVLPC_STATSCTRL[%08x]\n",
7909 tr32(RCVLPC_STATSCTRL));
7910
7911 /* Receive data and receive BD initiator control block */
7912 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7913 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7914
7915 /* Receive data completion control block */
7916 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7917 tr32(RCVDCC_MODE));
7918
7919 /* Receive BD initiator control block */
7920 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7921 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7922
7923 /* Receive BD completion control block */
7924 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7925 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7926
7927 /* Receive list selector control block */
7928 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7929 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7930
7931 /* Mbuf cluster free block */
7932 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7933 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7934
7935 /* Host coalescing control block */
7936 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7937 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7938 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7939 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7940 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7941 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7942 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7943 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7944 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7945 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7946 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7947 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7948
7949 /* Memory arbiter control block */
7950 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7951 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7952
7953 /* Buffer manager control block */
7954 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7955 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7956 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7957 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7958 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7959 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7960 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7961 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7962
7963 /* Read DMA control block */
7964 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7965 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7966
7967 /* Write DMA control block */
7968 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7969 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7970
7971 /* DMA completion block */
7972 printk("DEBUG: DMAC_MODE[%08x]\n",
7973 tr32(DMAC_MODE));
7974
7975 /* GRC block */
7976 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7977 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7978 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7979 tr32(GRC_LOCAL_CTRL));
7980
7981 /* TG3_BDINFOs */
7982 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7983 tr32(RCVDBDI_JUMBO_BD + 0x0),
7984 tr32(RCVDBDI_JUMBO_BD + 0x4),
7985 tr32(RCVDBDI_JUMBO_BD + 0x8),
7986 tr32(RCVDBDI_JUMBO_BD + 0xc));
7987 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7988 tr32(RCVDBDI_STD_BD + 0x0),
7989 tr32(RCVDBDI_STD_BD + 0x4),
7990 tr32(RCVDBDI_STD_BD + 0x8),
7991 tr32(RCVDBDI_STD_BD + 0xc));
7992 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7993 tr32(RCVDBDI_MINI_BD + 0x0),
7994 tr32(RCVDBDI_MINI_BD + 0x4),
7995 tr32(RCVDBDI_MINI_BD + 0x8),
7996 tr32(RCVDBDI_MINI_BD + 0xc));
7997
7998 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7999 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8000 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8001 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8002 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8003 val32, val32_2, val32_3, val32_4);
8004
8005 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8006 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8007 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8008 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8009 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8010 val32, val32_2, val32_3, val32_4);
8011
8012 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8013 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8014 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8015 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8016 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8017 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8018 val32, val32_2, val32_3, val32_4, val32_5);
8019
8020 /* SW status block */
8021 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8022 tp->hw_status->status,
8023 tp->hw_status->status_tag,
8024 tp->hw_status->rx_jumbo_consumer,
8025 tp->hw_status->rx_consumer,
8026 tp->hw_status->rx_mini_consumer,
8027 tp->hw_status->idx[0].rx_producer,
8028 tp->hw_status->idx[0].tx_consumer);
8029
8030 /* SW statistics block */
8031 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8032 ((u32 *)tp->hw_stats)[0],
8033 ((u32 *)tp->hw_stats)[1],
8034 ((u32 *)tp->hw_stats)[2],
8035 ((u32 *)tp->hw_stats)[3]);
8036
8037 /* Mailboxes */
8038 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8039 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8040 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8041 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8042 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8043
8044 /* NIC side send descriptors. */
8045 for (i = 0; i < 6; i++) {
8046 unsigned long txd;
8047
8048 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8049 + (i * sizeof(struct tg3_tx_buffer_desc));
8050 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8051 i,
8052 readl(txd + 0x0), readl(txd + 0x4),
8053 readl(txd + 0x8), readl(txd + 0xc));
8054 }
8055
8056 /* NIC side RX descriptors. */
8057 for (i = 0; i < 6; i++) {
8058 unsigned long rxd;
8059
8060 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8061 + (i * sizeof(struct tg3_rx_buffer_desc));
8062 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8063 i,
8064 readl(rxd + 0x0), readl(rxd + 0x4),
8065 readl(rxd + 0x8), readl(rxd + 0xc));
8066 rxd += (4 * sizeof(u32));
8067 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8068 i,
8069 readl(rxd + 0x0), readl(rxd + 0x4),
8070 readl(rxd + 0x8), readl(rxd + 0xc));
8071 }
8072
8073 for (i = 0; i < 6; i++) {
8074 unsigned long rxd;
8075
8076 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8077 + (i * sizeof(struct tg3_rx_buffer_desc));
8078 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8079 i,
8080 readl(rxd + 0x0), readl(rxd + 0x4),
8081 readl(rxd + 0x8), readl(rxd + 0xc));
8082 rxd += (4 * sizeof(u32));
8083 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8084 i,
8085 readl(rxd + 0x0), readl(rxd + 0x4),
8086 readl(rxd + 0x8), readl(rxd + 0xc));
8087 }
8088}
8089#endif
8090
8091static struct net_device_stats *tg3_get_stats(struct net_device *);
8092static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8093
8094static int tg3_close(struct net_device *dev)
8095{
8096 struct tg3 *tp = netdev_priv(dev);
8097
bea3348e 8098 napi_disable(&tp->napi);
28e53bdd 8099 cancel_work_sync(&tp->reset_task);
7faa006f 8100
1da177e4
LT		 8101 netif_stop_queue(dev);
8102
8103 del_timer_sync(&tp->timer);
8104
f47c11ee 8105 tg3_full_lock(tp, 1);
1da177e4
LT		 8106#if 0
8107 tg3_dump_state(tp);
8108#endif
8109
8110 tg3_disable_ints(tp);
8111
944d980e 8112 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8113 tg3_free_rings(tp);
5cf64b8a 8114 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8115
f47c11ee 8116 tg3_full_unlock(tp);
1da177e4 8117
88b06bc2
MC		 8118 free_irq(tp->pdev->irq, dev);
8119 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8120 pci_disable_msi(tp->pdev);
8121 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8122 }
1da177e4
LT		 8123
8124 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8125 sizeof(tp->net_stats_prev));
8126 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8127 sizeof(tp->estats_prev));
8128
8129 tg3_free_consistent(tp);
8130
bc1c7567
MC		 8131 tg3_set_power_state(tp, PCI_D3hot);
8132
8133 netif_carrier_off(tp->dev);
8134
1da177e4
LT		 8135 return 0;
8136}
8137
8138static inline unsigned long get_stat64(tg3_stat64_t *val)
8139{
8140 unsigned long ret;
8141
8142#if (BITS_PER_LONG == 32)
8143 ret = val->low;
8144#else
8145 ret = ((u64)val->high << 32) | ((u64)val->low);
8146#endif
8147 return ret;
8148}
8149
816f8b86
SB		 8150static inline u64 get_estat64(tg3_stat64_t *val)
8151{
8152 return ((u64)val->high << 32) | ((u64)val->low);
8153}
8154
1da177e4
LT		 8155static unsigned long calc_crc_errors(struct tg3 *tp)
8156{
8157 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8158
8159 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8160 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8162 u32 val;
8163
f47c11ee 8164 spin_lock_bh(&tp->lock);
569a5df8
MC		 8165 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8166 tg3_writephy(tp, MII_TG3_TEST1,
8167 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8168 tg3_readphy(tp, 0x14, &val);
8169 } else
8170 val = 0;
f47c11ee 8171 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8172
8173 tp->phy_crc_errors += val;
8174
8175 return tp->phy_crc_errors;
8176 }
8177
8178 return get_stat64(&hw_stats->rx_fcs_errors);
8179}
8180
8181#define ESTAT_ADD(member) \
8182 estats->member = old_estats->member + \
816f8b86 8183 get_estat64(&hw_stats->member)
1da177e4
LT		 8184
8185static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8186{
8187 struct tg3_ethtool_stats *estats = &tp->estats;
8188 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8189 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8190
8191 if (!hw_stats)
8192 return old_estats;
8193
8194 ESTAT_ADD(rx_octets);
8195 ESTAT_ADD(rx_fragments);
8196 ESTAT_ADD(rx_ucast_packets);
8197 ESTAT_ADD(rx_mcast_packets);
8198 ESTAT_ADD(rx_bcast_packets);
8199 ESTAT_ADD(rx_fcs_errors);
8200 ESTAT_ADD(rx_align_errors);
8201 ESTAT_ADD(rx_xon_pause_rcvd);
8202 ESTAT_ADD(rx_xoff_pause_rcvd);
8203 ESTAT_ADD(rx_mac_ctrl_rcvd);
8204 ESTAT_ADD(rx_xoff_entered);
8205 ESTAT_ADD(rx_frame_too_long_errors);
8206 ESTAT_ADD(rx_jabbers);
8207 ESTAT_ADD(rx_undersize_packets);
8208 ESTAT_ADD(rx_in_length_errors);
8209 ESTAT_ADD(rx_out_length_errors);
8210 ESTAT_ADD(rx_64_or_less_octet_packets);
8211 ESTAT_ADD(rx_65_to_127_octet_packets);
8212 ESTAT_ADD(rx_128_to_255_octet_packets);
8213 ESTAT_ADD(rx_256_to_511_octet_packets);
8214 ESTAT_ADD(rx_512_to_1023_octet_packets);
8215 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8216 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8217 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8218 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8219 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8220
8221 ESTAT_ADD(tx_octets);
8222 ESTAT_ADD(tx_collisions);
8223 ESTAT_ADD(tx_xon_sent);
8224 ESTAT_ADD(tx_xoff_sent);
8225 ESTAT_ADD(tx_flow_control);
8226 ESTAT_ADD(tx_mac_errors);
8227 ESTAT_ADD(tx_single_collisions);
8228 ESTAT_ADD(tx_mult_collisions);
8229 ESTAT_ADD(tx_deferred);
8230 ESTAT_ADD(tx_excessive_collisions);
8231 ESTAT_ADD(tx_late_collisions);
8232 ESTAT_ADD(tx_collide_2times);
8233 ESTAT_ADD(tx_collide_3times);
8234 ESTAT_ADD(tx_collide_4times);
8235 ESTAT_ADD(tx_collide_5times);
8236 ESTAT_ADD(tx_collide_6times);
8237 ESTAT_ADD(tx_collide_7times);
8238 ESTAT_ADD(tx_collide_8times);
8239 ESTAT_ADD(tx_collide_9times);
8240 ESTAT_ADD(tx_collide_10times);
8241 ESTAT_ADD(tx_collide_11times);
8242 ESTAT_ADD(tx_collide_12times);
8243 ESTAT_ADD(tx_collide_13times);
8244 ESTAT_ADD(tx_collide_14times);
8245 ESTAT_ADD(tx_collide_15times);
8246 ESTAT_ADD(tx_ucast_packets);
8247 ESTAT_ADD(tx_mcast_packets);
8248 ESTAT_ADD(tx_bcast_packets);
8249 ESTAT_ADD(tx_carrier_sense_errors);
8250 ESTAT_ADD(tx_discards);
8251 ESTAT_ADD(tx_errors);
8252
8253 ESTAT_ADD(dma_writeq_full);
8254 ESTAT_ADD(dma_write_prioq_full);
8255 ESTAT_ADD(rxbds_empty);
8256 ESTAT_ADD(rx_discards);
8257 ESTAT_ADD(rx_errors);
8258 ESTAT_ADD(rx_threshold_hit);
8259
8260 ESTAT_ADD(dma_readq_full);
8261 ESTAT_ADD(dma_read_prioq_full);
8262 ESTAT_ADD(tx_comp_queue_full);
8263
8264 ESTAT_ADD(ring_set_send_prod_index);
8265 ESTAT_ADD(ring_status_update);
8266 ESTAT_ADD(nic_irqs);
8267 ESTAT_ADD(nic_avoided_irqs);
8268 ESTAT_ADD(nic_tx_threshold_hit);
8269
8270 return estats;
8271}
8272
8273static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8274{
8275 struct tg3 *tp = netdev_priv(dev);
8276 struct net_device_stats *stats = &tp->net_stats;
8277 struct net_device_stats *old_stats = &tp->net_stats_prev;
8278 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8279
8280 if (!hw_stats)
8281 return old_stats;
8282
8283 stats->rx_packets = old_stats->rx_packets +
8284 get_stat64(&hw_stats->rx_ucast_packets) +
8285 get_stat64(&hw_stats->rx_mcast_packets) +
8286 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8287
1da177e4
LT		 8288 stats->tx_packets = old_stats->tx_packets +
8289 get_stat64(&hw_stats->tx_ucast_packets) +
8290 get_stat64(&hw_stats->tx_mcast_packets) +
8291 get_stat64(&hw_stats->tx_bcast_packets);
8292
8293 stats->rx_bytes = old_stats->rx_bytes +
8294 get_stat64(&hw_stats->rx_octets);
8295 stats->tx_bytes = old_stats->tx_bytes +
8296 get_stat64(&hw_stats->tx_octets);
8297
8298 stats->rx_errors = old_stats->rx_errors +
4f63b877 8299 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8300 stats->tx_errors = old_stats->tx_errors +
8301 get_stat64(&hw_stats->tx_errors) +
8302 get_stat64(&hw_stats->tx_mac_errors) +
8303 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8304 get_stat64(&hw_stats->tx_discards);
8305
8306 stats->multicast = old_stats->multicast +
8307 get_stat64(&hw_stats->rx_mcast_packets);
8308 stats->collisions = old_stats->collisions +
8309 get_stat64(&hw_stats->tx_collisions);
8310
8311 stats->rx_length_errors = old_stats->rx_length_errors +
8312 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8313 get_stat64(&hw_stats->rx_undersize_packets);
8314
8315 stats->rx_over_errors = old_stats->rx_over_errors +
8316 get_stat64(&hw_stats->rxbds_empty);
8317 stats->rx_frame_errors = old_stats->rx_frame_errors +
8318 get_stat64(&hw_stats->rx_align_errors);
8319 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8320 get_stat64(&hw_stats->tx_discards);
8321 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8322 get_stat64(&hw_stats->tx_carrier_sense_errors);
8323
8324 stats->rx_crc_errors = old_stats->rx_crc_errors +
8325 calc_crc_errors(tp);
8326
4f63b877
JL		 8327 stats->rx_missed_errors = old_stats->rx_missed_errors +
8328 get_stat64(&hw_stats->rx_discards);
8329
1da177e4
LT		 8330 return stats;
8331}
8332
8333static inline u32 calc_crc(unsigned char *buf, int len)
8334{
8335 u32 reg;
8336 u32 tmp;
8337 int j, k;
8338
8339 reg = 0xffffffff;
8340
8341 for (j = 0; j < len; j++) {
8342 reg ^= buf[j];
8343
8344 for (k = 0; k < 8; k++) {
8345 tmp = reg & 0x01;
8346
8347 reg >>= 1;
8348
8349 if (tmp) {
8350 reg ^= 0xedb88320;
8351 }
8352 }
8353 }
8354
8355 return ~reg;
8356}
8357
8358static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8359{
8360 /* accept or reject all multicast frames */
8361 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8362 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8363 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8364 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8365}
8366
8367static void __tg3_set_rx_mode(struct net_device *dev)
8368{
8369 struct tg3 *tp = netdev_priv(dev);
8370 u32 rx_mode;
8371
8372 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8373 RX_MODE_KEEP_VLAN_TAG);
8374
8375 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8376 * flag clear.
8377 */
8378#if TG3_VLAN_TAG_USED
8379 if (!tp->vlgrp &&
8380 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8381 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8382#else
8383 /* By definition, VLAN is disabled always in this
8384 * case.
8385 */
8386 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8387 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8388#endif
8389
8390 if (dev->flags & IFF_PROMISC) {
8391 /* Promiscuous mode. */
8392 rx_mode |= RX_MODE_PROMISC;
8393 } else if (dev->flags & IFF_ALLMULTI) {
8394 /* Accept all multicast. */
8395 tg3_set_multi (tp, 1);
8396 } else if (dev->mc_count < 1) {
8397 /* Reject all multicast. */
8398 tg3_set_multi (tp, 0);
8399 } else {
8400 /* Accept one or more multicast(s). */
8401 struct dev_mc_list *mclist;
8402 unsigned int i;
8403 u32 mc_filter[4] = { 0, };
8404 u32 regidx;
8405 u32 bit;
8406 u32 crc;
8407
8408 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8409 i++, mclist = mclist->next) {
8410
8411 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8412 bit = ~crc & 0x7f;
8413 regidx = (bit & 0x60) >> 5;
8414 bit &= 0x1f;
8415 mc_filter[regidx] |= (1 << bit);
8416 }
8417
8418 tw32(MAC_HASH_REG_0, mc_filter[0]);
8419 tw32(MAC_HASH_REG_1, mc_filter[1]);
8420 tw32(MAC_HASH_REG_2, mc_filter[2]);
8421 tw32(MAC_HASH_REG_3, mc_filter[3]);
8422 }
8423
8424 if (rx_mode != tp->rx_mode) {
8425 tp->rx_mode = rx_mode;
8426 tw32_f(MAC_RX_MODE, rx_mode);
8427 udelay(10);
8428 }
8429}
8430
8431static void tg3_set_rx_mode(struct net_device *dev)
8432{
8433 struct tg3 *tp = netdev_priv(dev);
8434
e75f7c90
MC		 8435 if (!netif_running(dev))
8436 return;
8437
f47c11ee 8438 tg3_full_lock(tp, 0);
1da177e4 8439 __tg3_set_rx_mode(dev);
f47c11ee 8440 tg3_full_unlock(tp);
1da177e4
LT		 8441}
8442
8443#define TG3_REGDUMP_LEN (32 * 1024)
8444
8445static int tg3_get_regs_len(struct net_device *dev)
8446{
8447 return TG3_REGDUMP_LEN;
8448}
8449
8450static void tg3_get_regs(struct net_device *dev,
8451 struct ethtool_regs *regs, void *_p)
8452{
8453 u32 *p = _p;
8454 struct tg3 *tp = netdev_priv(dev);
8455 u8 *orig_p = _p;
8456 int i;
8457
8458 regs->version = 0;
8459
8460 memset(p, 0, TG3_REGDUMP_LEN);
8461
bc1c7567
MC		 8462 if (tp->link_config.phy_is_low_power)
8463 return;
8464
f47c11ee 8465 tg3_full_lock(tp, 0);
1da177e4
LT		 8466
8467#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8468#define GET_REG32_LOOP(base,len) \
8469do { p = (u32 *)(orig_p + (base)); \
8470 for (i = 0; i < len; i += 4) \
8471 __GET_REG32((base) + i); \
8472} while (0)
8473#define GET_REG32_1(reg) \
8474do { p = (u32 *)(orig_p + (reg)); \
8475 __GET_REG32((reg)); \
8476} while (0)
8477
8478 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8479 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8480 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8481 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8482 GET_REG32_1(SNDDATAC_MODE);
8483 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8484 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8485 GET_REG32_1(SNDBDC_MODE);
8486 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8487 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8488 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8489 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8490 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8491 GET_REG32_1(RCVDCC_MODE);
8492 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8493 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8494 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8495 GET_REG32_1(MBFREE_MODE);
8496 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8497 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8498 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8499 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8500 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8501 GET_REG32_1(RX_CPU_MODE);
8502 GET_REG32_1(RX_CPU_STATE);
8503 GET_REG32_1(RX_CPU_PGMCTR);
8504 GET_REG32_1(RX_CPU_HWBKPT);
8505 GET_REG32_1(TX_CPU_MODE);
8506 GET_REG32_1(TX_CPU_STATE);
8507 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8508 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8509 GET_REG32_LOOP(FTQ_RESET, 0x120);
8510 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8511 GET_REG32_1(DMAC_MODE);
8512 GET_REG32_LOOP(GRC_MODE, 0x4c);
8513 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8514 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8515
8516#undef __GET_REG32
8517#undef GET_REG32_LOOP
8518#undef GET_REG32_1
8519
f47c11ee 8520 tg3_full_unlock(tp);
1da177e4
LT		 8521}
8522
8523static int tg3_get_eeprom_len(struct net_device *dev)
8524{
8525 struct tg3 *tp = netdev_priv(dev);
8526
8527 return tp->nvram_size;
8528}
8529
1da177e4
LT		 8530static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8531{
8532 struct tg3 *tp = netdev_priv(dev);
8533 int ret;
8534 u8 *pd;
b9fc7dc5
AV		 8535 u32 i, offset, len, b_offset, b_count;
8536 __le32 val;
1da177e4 8537
bc1c7567
MC		 8538 if (tp->link_config.phy_is_low_power)
8539 return -EAGAIN;
8540
1da177e4
LT		 8541 offset = eeprom->offset;
8542 len = eeprom->len;
8543 eeprom->len = 0;
8544
8545 eeprom->magic = TG3_EEPROM_MAGIC;
8546
8547 if (offset & 3) {
8548 /* adjustments to start on required 4 byte boundary */
8549 b_offset = offset & 3;
8550 b_count = 4 - b_offset;
8551 if (b_count > len) {
8552 /* i.e. offset=1 len=2 */
8553 b_count = len;
8554 }
b9fc7dc5 8555 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
1da177e4
LT		 8556 if (ret)
8557 return ret;
1da177e4
LT		 8558 memcpy(data, ((char*)&val) + b_offset, b_count);
8559 len -= b_count;
8560 offset += b_count;
8561 eeprom->len += b_count;
8562 }
8563
8564 /* read bytes upto the last 4 byte boundary */
8565 pd = &data[eeprom->len];
8566 for (i = 0; i < (len - (len & 3)); i += 4) {
b9fc7dc5 8567 ret = tg3_nvram_read_le(tp, offset + i, &val);
1da177e4
LT		 8568 if (ret) {
8569 eeprom->len += i;
8570 return ret;
8571 }
1da177e4
LT		 8572 memcpy(pd + i, &val, 4);
8573 }
8574 eeprom->len += i;
8575
8576 if (len & 3) {
8577 /* read last bytes not ending on 4 byte boundary */
8578 pd = &data[eeprom->len];
8579 b_count = len & 3;
8580 b_offset = offset + len - b_count;
b9fc7dc5 8581 ret = tg3_nvram_read_le(tp, b_offset, &val);
1da177e4
LT		 8582 if (ret)
8583 return ret;
b9fc7dc5 8584 memcpy(pd, &val, b_count);
1da177e4
LT		 8585 eeprom->len += b_count;
8586 }
8587 return 0;
8588}
8589
6aa20a22 8590static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8591
8592static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8593{
8594 struct tg3 *tp = netdev_priv(dev);
8595 int ret;
b9fc7dc5 8596 u32 offset, len, b_offset, odd_len;
1da177e4 8597 u8 *buf;
b9fc7dc5 8598 __le32 start, end;
1da177e4 8599
bc1c7567
MC		 8600 if (tp->link_config.phy_is_low_power)
8601 return -EAGAIN;
8602
1da177e4
LT		 8603 if (eeprom->magic != TG3_EEPROM_MAGIC)
8604 return -EINVAL;
8605
8606 offset = eeprom->offset;
8607 len = eeprom->len;
8608
8609 if ((b_offset = (offset & 3))) {
8610 /* adjustments to start on required 4 byte boundary */
b9fc7dc5 8611 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
1da177e4
LT		 8612 if (ret)
8613 return ret;
1da177e4
LT		 8614 len += b_offset;
8615 offset &= ~3;
1c8594b4
MC		 8616 if (len < 4)
8617 len = 4;
1da177e4
LT		 8618 }
8619
8620 odd_len = 0;
1c8594b4 8621 if (len & 3) {
1da177e4
LT		 8622 /* adjustments to end on required 4 byte boundary */
8623 odd_len = 1;
8624 len = (len + 3) & ~3;
b9fc7dc5 8625 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
1da177e4
LT		 8626 if (ret)
8627 return ret;
1da177e4
LT		 8628 }
8629
8630 buf = data;
8631 if (b_offset || odd_len) {
8632 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8633 if (!buf)
1da177e4
LT		 8634 return -ENOMEM;
8635 if (b_offset)
8636 memcpy(buf, &start, 4);
8637 if (odd_len)
8638 memcpy(buf+len-4, &end, 4);
8639 memcpy(buf + b_offset, data, eeprom->len);
8640 }
8641
8642 ret = tg3_nvram_write_block(tp, offset, len, buf);
8643
8644 if (buf != data)
8645 kfree(buf);
8646
8647 return ret;
8648}
8649
8650static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8651{
b02fd9e3
MC		 8652 struct tg3 *tp = netdev_priv(dev);
8653
8654 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8655 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8656 return -EAGAIN;
298cf9be 8657 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8658 }
6aa20a22 8659
1da177e4
LT		 8660 cmd->supported = (SUPPORTED_Autoneg);
8661
8662 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8663 cmd->supported |= (SUPPORTED_1000baseT_Half |
8664 SUPPORTED_1000baseT_Full);
8665
ef348144 8666 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8667 cmd->supported |= (SUPPORTED_100baseT_Half |
8668 SUPPORTED_100baseT_Full |
8669 SUPPORTED_10baseT_Half |
8670 SUPPORTED_10baseT_Full |
3bebab59 8671 SUPPORTED_TP);
ef348144
KK		 8672 cmd->port = PORT_TP;
8673 } else {
1da177e4 8674 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8675 cmd->port = PORT_FIBRE;
8676 }
6aa20a22 8677
1da177e4
LT		 8678 cmd->advertising = tp->link_config.advertising;
8679 if (netif_running(dev)) {
8680 cmd->speed = tp->link_config.active_speed;
8681 cmd->duplex = tp->link_config.active_duplex;
8682 }
1da177e4 8683 cmd->phy_address = PHY_ADDR;
7e5856bd 8684 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8685 cmd->autoneg = tp->link_config.autoneg;
8686 cmd->maxtxpkt = 0;
8687 cmd->maxrxpkt = 0;
8688 return 0;
8689}
6aa20a22 8690
1da177e4
LT		 8691static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8692{
8693 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8694
b02fd9e3
MC		 8695 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8696 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8697 return -EAGAIN;
298cf9be 8698 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8699 }
8700
7e5856bd
MC		 8701 if (cmd->autoneg != AUTONEG_ENABLE &&
8702 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8703 return -EINVAL;
7e5856bd
MC		 8704
8705 if (cmd->autoneg == AUTONEG_DISABLE &&
8706 cmd->duplex != DUPLEX_FULL &&
8707 cmd->duplex != DUPLEX_HALF)
37ff238d 8708 return -EINVAL;
1da177e4 8709
7e5856bd
MC		 8710 if (cmd->autoneg == AUTONEG_ENABLE) {
8711 u32 mask = ADVERTISED_Autoneg |
8712 ADVERTISED_Pause |
8713 ADVERTISED_Asym_Pause;
8714
8715 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8716 mask |= ADVERTISED_1000baseT_Half |
8717 ADVERTISED_1000baseT_Full;
8718
8719 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8720 mask |= ADVERTISED_100baseT_Half |
8721 ADVERTISED_100baseT_Full |
8722 ADVERTISED_10baseT_Half |
8723 ADVERTISED_10baseT_Full |
8724 ADVERTISED_TP;
8725 else
8726 mask |= ADVERTISED_FIBRE;
8727
8728 if (cmd->advertising & ~mask)
8729 return -EINVAL;
8730
8731 mask &= (ADVERTISED_1000baseT_Half |
8732 ADVERTISED_1000baseT_Full |
8733 ADVERTISED_100baseT_Half |
8734 ADVERTISED_100baseT_Full |
8735 ADVERTISED_10baseT_Half |
8736 ADVERTISED_10baseT_Full);
8737
8738 cmd->advertising &= mask;
8739 } else {
8740 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8741 if (cmd->speed != SPEED_1000)
8742 return -EINVAL;
8743
8744 if (cmd->duplex != DUPLEX_FULL)
8745 return -EINVAL;
8746 } else {
8747 if (cmd->speed != SPEED_100 &&
8748 cmd->speed != SPEED_10)
8749 return -EINVAL;
8750 }
8751 }
8752
f47c11ee 8753 tg3_full_lock(tp, 0);
1da177e4
LT		 8754
8755 tp->link_config.autoneg = cmd->autoneg;
8756 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8757 tp->link_config.advertising = (cmd->advertising |
8758 ADVERTISED_Autoneg);
1da177e4
LT		 8759 tp->link_config.speed = SPEED_INVALID;
8760 tp->link_config.duplex = DUPLEX_INVALID;
8761 } else {
8762 tp->link_config.advertising = 0;
8763 tp->link_config.speed = cmd->speed;
8764 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8765 }
6aa20a22 8766
24fcad6b
MC		 8767 tp->link_config.orig_speed = tp->link_config.speed;
8768 tp->link_config.orig_duplex = tp->link_config.duplex;
8769 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8770
1da177e4
LT		 8771 if (netif_running(dev))
8772 tg3_setup_phy(tp, 1);
8773
f47c11ee 8774 tg3_full_unlock(tp);
6aa20a22 8775
1da177e4
LT		 8776 return 0;
8777}
6aa20a22 8778
1da177e4
LT		 8779static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8780{
8781 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8782
1da177e4
LT		 8783 strcpy(info->driver, DRV_MODULE_NAME);
8784 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8785 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8786 strcpy(info->bus_info, pci_name(tp->pdev));
8787}
6aa20a22 8788
1da177e4
LT		 8789static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8790{
8791 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8792
12dac075
RW		 8793 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8794 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8795 wol->supported = WAKE_MAGIC;
8796 else
8797 wol->supported = 0;
1da177e4 8798 wol->wolopts = 0;
05ac4cb7
MC		 8799 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8800 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8801 wol->wolopts = WAKE_MAGIC;
8802 memset(&wol->sopass, 0, sizeof(wol->sopass));
8803}
6aa20a22 8804
1da177e4
LT		 8805static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8806{
8807 struct tg3 *tp = netdev_priv(dev);
12dac075 8808 struct device *dp = &tp->pdev->dev;
6aa20a22 8809
1da177e4
LT		 8810 if (wol->wolopts & ~WAKE_MAGIC)
8811 return -EINVAL;
8812 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8813 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8814 return -EINVAL;
6aa20a22 8815
f47c11ee 8816 spin_lock_bh(&tp->lock);
12dac075 8817 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8818 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8819 device_set_wakeup_enable(dp, true);
8820 } else {
1da177e4 8821 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8822 device_set_wakeup_enable(dp, false);
8823 }
f47c11ee 8824 spin_unlock_bh(&tp->lock);
6aa20a22 8825
1da177e4
LT		 8826 return 0;
8827}
6aa20a22 8828
1da177e4
LT		 8829static u32 tg3_get_msglevel(struct net_device *dev)
8830{
8831 struct tg3 *tp = netdev_priv(dev);
8832 return tp->msg_enable;
8833}
6aa20a22 8834
1da177e4
LT		 8835static void tg3_set_msglevel(struct net_device *dev, u32 value)
8836{
8837 struct tg3 *tp = netdev_priv(dev);
8838 tp->msg_enable = value;
8839}
6aa20a22 8840
1da177e4
LT		 8841static int tg3_set_tso(struct net_device *dev, u32 value)
8842{
8843 struct tg3 *tp = netdev_priv(dev);
8844
8845 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8846 if (value)
8847 return -EINVAL;
8848 return 0;
8849 }
027455ad
MC		 8850 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8851 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 8852 if (value) {
b0026624 8853 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 8854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8855 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8856 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 8857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 8859 dev->features |= NETIF_F_TSO_ECN;
8860 } else
8861 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8862 }
1da177e4
LT		 8863 return ethtool_op_set_tso(dev, value);
8864}
6aa20a22 8865
1da177e4
LT		 8866static int tg3_nway_reset(struct net_device *dev)
8867{
8868 struct tg3 *tp = netdev_priv(dev);
1da177e4 8869 int r;
6aa20a22 8870
1da177e4
LT		 8871 if (!netif_running(dev))
8872 return -EAGAIN;
8873
c94e3941
MC		 8874 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8875 return -EINVAL;
8876
b02fd9e3
MC		 8877 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8878 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8879 return -EAGAIN;
298cf9be 8880 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 8881 } else {
8882 u32 bmcr;
8883
8884 spin_lock_bh(&tp->lock);
8885 r = -EINVAL;
8886 tg3_readphy(tp, MII_BMCR, &bmcr);
8887 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8888 ((bmcr & BMCR_ANENABLE) ||
8889 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8890 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8891 BMCR_ANENABLE);
8892 r = 0;
8893 }
8894 spin_unlock_bh(&tp->lock);
1da177e4 8895 }
6aa20a22 8896
1da177e4
LT		 8897 return r;
8898}
6aa20a22 8899
1da177e4
LT		 8900static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8901{
8902 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8903
1da177e4
LT		 8904 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8905 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8906 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8907 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8908 else
8909 ering->rx_jumbo_max_pending = 0;
8910
8911 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8912
8913 ering->rx_pending = tp->rx_pending;
8914 ering->rx_mini_pending = 0;
4f81c32b
MC		 8915 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8916 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8917 else
8918 ering->rx_jumbo_pending = 0;
8919
1da177e4
LT		 8920 ering->tx_pending = tp->tx_pending;
8921}
6aa20a22 8922
1da177e4
LT		 8923static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8924{
8925 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8926 int irq_sync = 0, err = 0;
6aa20a22 8927
1da177e4
LT		 8928 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8929 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8930 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8931 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8932 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8933 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8934 return -EINVAL;
6aa20a22 8935
bbe832c0 8936 if (netif_running(dev)) {
b02fd9e3 8937 tg3_phy_stop(tp);
1da177e4 8938 tg3_netif_stop(tp);
bbe832c0
MC		 8939 irq_sync = 1;
8940 }
1da177e4 8941
bbe832c0 8942 tg3_full_lock(tp, irq_sync);
6aa20a22 8943
1da177e4
LT		 8944 tp->rx_pending = ering->rx_pending;
8945
8946 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8947 tp->rx_pending > 63)
8948 tp->rx_pending = 63;
8949 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8950 tp->tx_pending = ering->tx_pending;
8951
8952 if (netif_running(dev)) {
944d980e 8953 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8954 err = tg3_restart_hw(tp, 1);
8955 if (!err)
8956 tg3_netif_start(tp);
1da177e4
LT		 8957 }
8958
f47c11ee 8959 tg3_full_unlock(tp);
6aa20a22 8960
b02fd9e3
MC		 8961 if (irq_sync && !err)
8962 tg3_phy_start(tp);
8963
b9ec6c1b 8964 return err;
1da177e4 8965}
6aa20a22 8966
1da177e4
LT		 8967static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8968{
8969 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8970
1da177e4 8971 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 8972
e18ce346 8973 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 8974 epause->rx_pause = 1;
8975 else
8976 epause->rx_pause = 0;
8977
e18ce346 8978 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 8979 epause->tx_pause = 1;
8980 else
8981 epause->tx_pause = 0;
1da177e4 8982}
6aa20a22 8983
1da177e4
LT		 8984static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8985{
8986 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 8987 int err = 0;
6aa20a22 8988
b02fd9e3
MC		 8989 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8990 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8991 return -EAGAIN;
1da177e4 8992
b02fd9e3
MC		 8993 if (epause->autoneg) {
8994 u32 newadv;
8995 struct phy_device *phydev;
f47c11ee 8996
298cf9be 8997 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 8998
b02fd9e3
MC		 8999 if (epause->rx_pause) {
9000 if (epause->tx_pause)
9001 newadv = ADVERTISED_Pause;
9002 else
9003 newadv = ADVERTISED_Pause |
9004 ADVERTISED_Asym_Pause;
9005 } else if (epause->tx_pause) {
9006 newadv = ADVERTISED_Asym_Pause;
9007 } else
9008 newadv = 0;
9009
9010 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9011 u32 oldadv = phydev->advertising &
9012 (ADVERTISED_Pause |
9013 ADVERTISED_Asym_Pause);
9014 if (oldadv != newadv) {
9015 phydev->advertising &=
9016 ~(ADVERTISED_Pause |
9017 ADVERTISED_Asym_Pause);
9018 phydev->advertising |= newadv;
9019 err = phy_start_aneg(phydev);
9020 }
9021 } else {
9022 tp->link_config.advertising &=
9023 ~(ADVERTISED_Pause |
9024 ADVERTISED_Asym_Pause);
9025 tp->link_config.advertising |= newadv;
9026 }
9027 } else {
9028 if (epause->rx_pause)
e18ce346 9029 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9030 else
e18ce346 9031 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9032
b02fd9e3 9033 if (epause->tx_pause)
e18ce346 9034 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9035 else
e18ce346 9036 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9037
9038 if (netif_running(dev))
9039 tg3_setup_flow_control(tp, 0, 0);
9040 }
9041 } else {
9042 int irq_sync = 0;
9043
9044 if (netif_running(dev)) {
9045 tg3_netif_stop(tp);
9046 irq_sync = 1;
9047 }
9048
9049 tg3_full_lock(tp, irq_sync);
9050
9051 if (epause->autoneg)
9052 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9053 else
9054 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9055 if (epause->rx_pause)
e18ce346 9056 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9057 else
e18ce346 9058 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9059 if (epause->tx_pause)
e18ce346 9060 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9061 else
e18ce346 9062 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9063
9064 if (netif_running(dev)) {
9065 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9066 err = tg3_restart_hw(tp, 1);
9067 if (!err)
9068 tg3_netif_start(tp);
9069 }
9070
9071 tg3_full_unlock(tp);
9072 }
6aa20a22 9073
b9ec6c1b 9074 return err;
1da177e4 9075}
6aa20a22 9076
1da177e4
LT		 9077static u32 tg3_get_rx_csum(struct net_device *dev)
9078{
9079 struct tg3 *tp = netdev_priv(dev);
9080 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9081}
6aa20a22 9082
1da177e4
LT		 9083static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9084{
9085 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9086
1da177e4
LT		 9087 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9088 if (data != 0)
9089 return -EINVAL;
9090 return 0;
9091 }
6aa20a22 9092
f47c11ee 9093 spin_lock_bh(&tp->lock);
1da177e4
LT		 9094 if (data)
9095 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9096 else
9097 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9098 spin_unlock_bh(&tp->lock);
6aa20a22 9099
1da177e4
LT		 9100 return 0;
9101}
6aa20a22 9102
1da177e4
LT		 9103static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9104{
9105 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9106
1da177e4
LT		 9107 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9108 if (data != 0)
9109 return -EINVAL;
9110 return 0;
9111 }
6aa20a22 9112
321d32a0 9113 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9114 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9115 else
9c27dbdf 9116 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9117
9118 return 0;
9119}
9120
b9f2c044 9121static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9122{
b9f2c044
JG		 9123 switch (sset) {
9124 case ETH_SS_TEST:
9125 return TG3_NUM_TEST;
9126 case ETH_SS_STATS:
9127 return TG3_NUM_STATS;
9128 default:
9129 return -EOPNOTSUPP;
9130 }
4cafd3f5
MC		 9131}
9132
1da177e4
LT		 9133static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9134{
9135 switch (stringset) {
9136 case ETH_SS_STATS:
9137 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9138 break;
4cafd3f5
MC		 9139 case ETH_SS_TEST:
9140 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9141 break;
1da177e4
LT		 9142 default:
9143 WARN_ON(1); /* we need a WARN() */
9144 break;
9145 }
9146}
9147
4009a93d
MC		 9148static int tg3_phys_id(struct net_device *dev, u32 data)
9149{
9150 struct tg3 *tp = netdev_priv(dev);
9151 int i;
9152
9153 if (!netif_running(tp->dev))
9154 return -EAGAIN;
9155
9156 if (data == 0)
759afc31 9157 data = UINT_MAX / 2;
4009a93d
MC		 9158
9159 for (i = 0; i < (data * 2); i++) {
9160 if ((i % 2) == 0)
9161 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9162 LED_CTRL_1000MBPS_ON |
9163 LED_CTRL_100MBPS_ON |
9164 LED_CTRL_10MBPS_ON |
9165 LED_CTRL_TRAFFIC_OVERRIDE |
9166 LED_CTRL_TRAFFIC_BLINK |
9167 LED_CTRL_TRAFFIC_LED);
6aa20a22 9168
4009a93d
MC		 9169 else
9170 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9171 LED_CTRL_TRAFFIC_OVERRIDE);
9172
9173 if (msleep_interruptible(500))
9174 break;
9175 }
9176 tw32(MAC_LED_CTRL, tp->led_ctrl);
9177 return 0;
9178}
9179
1da177e4
LT		 9180static void tg3_get_ethtool_stats (struct net_device *dev,
9181 struct ethtool_stats *estats, u64 *tmp_stats)
9182{
9183 struct tg3 *tp = netdev_priv(dev);
9184 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9185}
9186
566f86ad 9187#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9188#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9189#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9190#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9191#define NVRAM_SELFBOOT_HW_SIZE 0x20
9192#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9193
9194static int tg3_test_nvram(struct tg3 *tp)
9195{
b9fc7dc5
AV		 9196 u32 csum, magic;
9197 __le32 *buf;
ab0049b4 9198 int i, j, k, err = 0, size;
566f86ad 9199
1820180b 9200 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1b27777a
MC		 9201 return -EIO;
9202
1b27777a
MC		 9203 if (magic == TG3_EEPROM_MAGIC)
9204 size = NVRAM_TEST_SIZE;
b16250e3 9205 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9206 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9207 TG3_EEPROM_SB_FORMAT_1) {
9208 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9209 case TG3_EEPROM_SB_REVISION_0:
9210 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9211 break;
9212 case TG3_EEPROM_SB_REVISION_2:
9213 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9214 break;
9215 case TG3_EEPROM_SB_REVISION_3:
9216 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9217 break;
9218 default:
9219 return 0;
9220 }
9221 } else
1b27777a 9222 return 0;
b16250e3
MC		 9223 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9224 size = NVRAM_SELFBOOT_HW_SIZE;
9225 else
1b27777a
MC		 9226 return -EIO;
9227
9228 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9229 if (buf == NULL)
9230 return -ENOMEM;
9231
1b27777a
MC		 9232 err = -EIO;
9233 for (i = 0, j = 0; i < size; i += 4, j++) {
b9fc7dc5 9234 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
566f86ad 9235 break;
566f86ad 9236 }
1b27777a 9237 if (i < size)
566f86ad
MC		 9238 goto out;
9239
1b27777a 9240 /* Selfboot format */
b9fc7dc5
AV		 9241 magic = swab32(le32_to_cpu(buf[0]));
9242 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9243 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9244 u8 *buf8 = (u8 *) buf, csum8 = 0;
9245
b9fc7dc5 9246 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9247 TG3_EEPROM_SB_REVISION_2) {
9248 /* For rev 2, the csum doesn't include the MBA. */
9249 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9250 csum8 += buf8[i];
9251 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9252 csum8 += buf8[i];
9253 } else {
9254 for (i = 0; i < size; i++)
9255 csum8 += buf8[i];
9256 }
1b27777a 9257
ad96b485
AB		 9258 if (csum8 == 0) {
9259 err = 0;
9260 goto out;
9261 }
9262
9263 err = -EIO;
9264 goto out;
1b27777a 9265 }
566f86ad 9266
b9fc7dc5 9267 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9268 TG3_EEPROM_MAGIC_HW) {
9269 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9270 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9271 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9272
9273 /* Separate the parity bits and the data bytes. */
9274 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9275 if ((i == 0) || (i == 8)) {
9276 int l;
9277 u8 msk;
9278
9279 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9280 parity[k++] = buf8[i] & msk;
9281 i++;
9282 }
9283 else if (i == 16) {
9284 int l;
9285 u8 msk;
9286
9287 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9288 parity[k++] = buf8[i] & msk;
9289 i++;
9290
9291 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9292 parity[k++] = buf8[i] & msk;
9293 i++;
9294 }
9295 data[j++] = buf8[i];
9296 }
9297
9298 err = -EIO;
9299 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9300 u8 hw8 = hweight8(data[i]);
9301
9302 if ((hw8 & 0x1) && parity[i])
9303 goto out;
9304 else if (!(hw8 & 0x1) && !parity[i])
9305 goto out;
9306 }
9307 err = 0;
9308 goto out;
9309 }
9310
566f86ad
MC		 9311 /* Bootstrap checksum at offset 0x10 */
9312 csum = calc_crc((unsigned char *) buf, 0x10);
b9fc7dc5 9313 if(csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9314 goto out;
9315
9316 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9317 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
b9fc7dc5 9318 if (csum != le32_to_cpu(buf[0xfc/4]))
566f86ad
MC		 9319 goto out;
9320
9321 err = 0;
9322
9323out:
9324 kfree(buf);
9325 return err;
9326}
9327
ca43007a
MC		 9328#define TG3_SERDES_TIMEOUT_SEC 2
9329#define TG3_COPPER_TIMEOUT_SEC 6
9330
9331static int tg3_test_link(struct tg3 *tp)
9332{
9333 int i, max;
9334
9335 if (!netif_running(tp->dev))
9336 return -ENODEV;
9337
4c987487 9338 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9339 max = TG3_SERDES_TIMEOUT_SEC;
9340 else
9341 max = TG3_COPPER_TIMEOUT_SEC;
9342
9343 for (i = 0; i < max; i++) {
9344 if (netif_carrier_ok(tp->dev))
9345 return 0;
9346
9347 if (msleep_interruptible(1000))
9348 break;
9349 }
9350
9351 return -EIO;
9352}
9353
a71116d1 9354/* Only test the commonly used registers */
30ca3e37 9355static int tg3_test_registers(struct tg3 *tp)
a71116d1 9356{
b16250e3 9357 int i, is_5705, is_5750;
a71116d1
MC		 9358 u32 offset, read_mask, write_mask, val, save_val, read_val;
9359 static struct {
9360 u16 offset;
9361 u16 flags;
9362#define TG3_FL_5705 0x1
9363#define TG3_FL_NOT_5705 0x2
9364#define TG3_FL_NOT_5788 0x4
b16250e3 9365#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9366 u32 read_mask;
9367 u32 write_mask;
9368 } reg_tbl[] = {
9369 /* MAC Control Registers */
9370 { MAC_MODE, TG3_FL_NOT_5705,
9371 0x00000000, 0x00ef6f8c },
9372 { MAC_MODE, TG3_FL_5705,
9373 0x00000000, 0x01ef6b8c },
9374 { MAC_STATUS, TG3_FL_NOT_5705,
9375 0x03800107, 0x00000000 },
9376 { MAC_STATUS, TG3_FL_5705,
9377 0x03800100, 0x00000000 },
9378 { MAC_ADDR_0_HIGH, 0x0000,
9379 0x00000000, 0x0000ffff },
9380 { MAC_ADDR_0_LOW, 0x0000,
9381 0x00000000, 0xffffffff },
9382 { MAC_RX_MTU_SIZE, 0x0000,
9383 0x00000000, 0x0000ffff },
9384 { MAC_TX_MODE, 0x0000,
9385 0x00000000, 0x00000070 },
9386 { MAC_TX_LENGTHS, 0x0000,
9387 0x00000000, 0x00003fff },
9388 { MAC_RX_MODE, TG3_FL_NOT_5705,
9389 0x00000000, 0x000007fc },
9390 { MAC_RX_MODE, TG3_FL_5705,
9391 0x00000000, 0x000007dc },
9392 { MAC_HASH_REG_0, 0x0000,
9393 0x00000000, 0xffffffff },
9394 { MAC_HASH_REG_1, 0x0000,
9395 0x00000000, 0xffffffff },
9396 { MAC_HASH_REG_2, 0x0000,
9397 0x00000000, 0xffffffff },
9398 { MAC_HASH_REG_3, 0x0000,
9399 0x00000000, 0xffffffff },
9400
9401 /* Receive Data and Receive BD Initiator Control Registers. */
9402 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9403 0x00000000, 0xffffffff },
9404 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9405 0x00000000, 0xffffffff },
9406 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9407 0x00000000, 0x00000003 },
9408 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9409 0x00000000, 0xffffffff },
9410 { RCVDBDI_STD_BD+0, 0x0000,
9411 0x00000000, 0xffffffff },
9412 { RCVDBDI_STD_BD+4, 0x0000,
9413 0x00000000, 0xffffffff },
9414 { RCVDBDI_STD_BD+8, 0x0000,
9415 0x00000000, 0xffff0002 },
9416 { RCVDBDI_STD_BD+0xc, 0x0000,
9417 0x00000000, 0xffffffff },
6aa20a22 9418
a71116d1
MC		 9419 /* Receive BD Initiator Control Registers. */
9420 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9421 0x00000000, 0xffffffff },
9422 { RCVBDI_STD_THRESH, TG3_FL_5705,
9423 0x00000000, 0x000003ff },
9424 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9425 0x00000000, 0xffffffff },
6aa20a22 9426
a71116d1
MC		 9427 /* Host Coalescing Control Registers. */
9428 { HOSTCC_MODE, TG3_FL_NOT_5705,
9429 0x00000000, 0x00000004 },
9430 { HOSTCC_MODE, TG3_FL_5705,
9431 0x00000000, 0x000000f6 },
9432 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9433 0x00000000, 0xffffffff },
9434 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9435 0x00000000, 0x000003ff },
9436 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9437 0x00000000, 0xffffffff },
9438 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9439 0x00000000, 0x000003ff },
9440 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9441 0x00000000, 0xffffffff },
9442 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9443 0x00000000, 0x000000ff },
9444 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9445 0x00000000, 0xffffffff },
9446 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9447 0x00000000, 0x000000ff },
9448 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9449 0x00000000, 0xffffffff },
9450 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9451 0x00000000, 0xffffffff },
9452 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9453 0x00000000, 0xffffffff },
9454 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9455 0x00000000, 0x000000ff },
9456 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9457 0x00000000, 0xffffffff },
9458 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9459 0x00000000, 0x000000ff },
9460 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9461 0x00000000, 0xffffffff },
9462 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9463 0x00000000, 0xffffffff },
9464 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9465 0x00000000, 0xffffffff },
9466 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9467 0x00000000, 0xffffffff },
9468 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9469 0x00000000, 0xffffffff },
9470 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9471 0xffffffff, 0x00000000 },
9472 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9473 0xffffffff, 0x00000000 },
9474
9475 /* Buffer Manager Control Registers. */
b16250e3 9476 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9477 0x00000000, 0x007fff80 },
b16250e3 9478 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9479 0x00000000, 0x007fffff },
9480 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9481 0x00000000, 0x0000003f },
9482 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9483 0x00000000, 0x000001ff },
9484 { BUFMGR_MB_HIGH_WATER, 0x0000,
9485 0x00000000, 0x000001ff },
9486 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9487 0xffffffff, 0x00000000 },
9488 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9489 0xffffffff, 0x00000000 },
6aa20a22 9490
a71116d1
MC		 9491 /* Mailbox Registers */
9492 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9493 0x00000000, 0x000001ff },
9494 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9495 0x00000000, 0x000001ff },
9496 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9497 0x00000000, 0x000007ff },
9498 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9499 0x00000000, 0x000001ff },
9500
9501 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9502 };
9503
b16250e3
MC		 9504 is_5705 = is_5750 = 0;
9505 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9506 is_5705 = 1;
b16250e3
MC		 9507 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9508 is_5750 = 1;
9509 }
a71116d1
MC		 9510
9511 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9512 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9513 continue;
9514
9515 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9516 continue;
9517
9518 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9519 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9520 continue;
9521
b16250e3
MC		 9522 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9523 continue;
9524
a71116d1
MC		 9525 offset = (u32) reg_tbl[i].offset;
9526 read_mask = reg_tbl[i].read_mask;
9527 write_mask = reg_tbl[i].write_mask;
9528
9529 /* Save the original register content */
9530 save_val = tr32(offset);
9531
9532 /* Determine the read-only value. */
9533 read_val = save_val & read_mask;
9534
9535 /* Write zero to the register, then make sure the read-only bits
9536 * are not changed and the read/write bits are all zeros.
9537 */
9538 tw32(offset, 0);
9539
9540 val = tr32(offset);
9541
9542 /* Test the read-only and read/write bits. */
9543 if (((val & read_mask) != read_val) || (val & write_mask))
9544 goto out;
9545
9546 /* Write ones to all the bits defined by RdMask and WrMask, then
9547 * make sure the read-only bits are not changed and the
9548 * read/write bits are all ones.
9549 */
9550 tw32(offset, read_mask | write_mask);
9551
9552 val = tr32(offset);
9553
9554 /* Test the read-only bits. */
9555 if ((val & read_mask) != read_val)
9556 goto out;
9557
9558 /* Test the read/write bits. */
9559 if ((val & write_mask) != write_mask)
9560 goto out;
9561
9562 tw32(offset, save_val);
9563 }
9564
9565 return 0;
9566
9567out:
9f88f29f
MC		 9568 if (netif_msg_hw(tp))
9569 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9570 offset);
a71116d1
MC		 9571 tw32(offset, save_val);
9572 return -EIO;
9573}
9574
7942e1db
MC		 9575static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9576{
f71e1309 9577 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9578 int i;
9579 u32 j;
9580
e9edda69 9581 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9582 for (j = 0; j < len; j += 4) {
9583 u32 val;
9584
9585 tg3_write_mem(tp, offset + j, test_pattern[i]);
9586 tg3_read_mem(tp, offset + j, &val);
9587 if (val != test_pattern[i])
9588 return -EIO;
9589 }
9590 }
9591 return 0;
9592}
9593
9594static int tg3_test_memory(struct tg3 *tp)
9595{
9596 static struct mem_entry {
9597 u32 offset;
9598 u32 len;
9599 } mem_tbl_570x[] = {
38690194 9600 { 0x00000000, 0x00b50},
7942e1db
MC		 9601 { 0x00002000, 0x1c000},
9602 { 0xffffffff, 0x00000}
9603 }, mem_tbl_5705[] = {
9604 { 0x00000100, 0x0000c},
9605 { 0x00000200, 0x00008},
7942e1db
MC		 9606 { 0x00004000, 0x00800},
9607 { 0x00006000, 0x01000},
9608 { 0x00008000, 0x02000},
9609 { 0x00010000, 0x0e000},
9610 { 0xffffffff, 0x00000}
79f4d13a
MC		 9611 }, mem_tbl_5755[] = {
9612 { 0x00000200, 0x00008},
9613 { 0x00004000, 0x00800},
9614 { 0x00006000, 0x00800},
9615 { 0x00008000, 0x02000},
9616 { 0x00010000, 0x0c000},
9617 { 0xffffffff, 0x00000}
b16250e3
MC		 9618 }, mem_tbl_5906[] = {
9619 { 0x00000200, 0x00008},
9620 { 0x00004000, 0x00400},
9621 { 0x00006000, 0x00400},
9622 { 0x00008000, 0x01000},
9623 { 0x00010000, 0x01000},
9624 { 0xffffffff, 0x00000}
7942e1db
MC		 9625 };
9626 struct mem_entry *mem_tbl;
9627 int err = 0;
9628 int i;
9629
321d32a0
MC		 9630 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9631 mem_tbl = mem_tbl_5755;
9632 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9633 mem_tbl = mem_tbl_5906;
9634 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9635 mem_tbl = mem_tbl_5705;
9636 else
7942e1db
MC		 9637 mem_tbl = mem_tbl_570x;
9638
9639 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9640 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9641 mem_tbl[i].len)) != 0)
9642 break;
9643 }
6aa20a22 9644
7942e1db
MC		 9645 return err;
9646}
9647
9f40dead
MC		 9648#define TG3_MAC_LOOPBACK 0
9649#define TG3_PHY_LOOPBACK 1
9650
9651static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9652{
9f40dead 9653 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9654 u32 desc_idx;
9655 struct sk_buff *skb, *rx_skb;
9656 u8 *tx_data;
9657 dma_addr_t map;
9658 int num_pkts, tx_len, rx_len, i, err;
9659 struct tg3_rx_buffer_desc *desc;
9660
9f40dead 9661 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9662 /* HW errata - mac loopback fails in some cases on 5780.
9663 * Normal traffic and PHY loopback are not affected by
9664 * errata.
9665 */
9666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9667 return 0;
9668
9f40dead 9669 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9670 MAC_MODE_PORT_INT_LPBACK;
9671 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9672 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9673 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9674 mac_mode |= MAC_MODE_PORT_MODE_MII;
9675 else
9676 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9677 tw32(MAC_MODE, mac_mode);
9678 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9679 u32 val;
9680
b16250e3
MC		 9681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9682 u32 phytest;
9683
9684 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9685 u32 phy;
9686
9687 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9688 phytest | MII_TG3_EPHY_SHADOW_EN);
9689 if (!tg3_readphy(tp, 0x1b, &phy))
9690 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9691 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9692 }
5d64ad34
MC		 9693 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9694 } else
9695 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9696
9ef8ca99
MC		 9697 tg3_phy_toggle_automdix(tp, 0);
9698
3f7045c1 9699 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9700 udelay(40);
5d64ad34 9701
e8f3f6ca 9702 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9704 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9705 mac_mode |= MAC_MODE_PORT_MODE_MII;
9706 } else
9707 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9708
c94e3941
MC		 9709 /* reset to prevent losing 1st rx packet intermittently */
9710 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9711 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9712 udelay(10);
9713 tw32_f(MAC_RX_MODE, tp->rx_mode);
9714 }
e8f3f6ca
MC		 9715 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9716 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9717 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9718 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9719 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9720 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9721 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9722 }
9f40dead 9723 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9724 }
9725 else
9726 return -EINVAL;
c76949a6
MC		 9727
9728 err = -EIO;
9729
c76949a6 9730 tx_len = 1514;
a20e9c62 9731 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9732 if (!skb)
9733 return -ENOMEM;
9734
c76949a6
MC		 9735 tx_data = skb_put(skb, tx_len);
9736 memcpy(tx_data, tp->dev->dev_addr, 6);
9737 memset(tx_data + 6, 0x0, 8);
9738
9739 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9740
9741 for (i = 14; i < tx_len; i++)
9742 tx_data[i] = (u8) (i & 0xff);
9743
9744 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9745
9746 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9747 HOSTCC_MODE_NOW);
9748
9749 udelay(10);
9750
9751 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9752
c76949a6
MC		 9753 num_pkts = 0;
9754
9f40dead 9755 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9756
9f40dead 9757 tp->tx_prod++;
c76949a6
MC		 9758 num_pkts++;
9759
9f40dead
MC		 9760 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9761 tp->tx_prod);
09ee929c 9762 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9763
9764 udelay(10);
9765
3f7045c1
MC		 9766 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9767 for (i = 0; i < 25; i++) {
c76949a6
MC		 9768 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9769 HOSTCC_MODE_NOW);
9770
9771 udelay(10);
9772
9773 tx_idx = tp->hw_status->idx[0].tx_consumer;
9774 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9775 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9776 (rx_idx == (rx_start_idx + num_pkts)))
9777 break;
9778 }
9779
9780 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9781 dev_kfree_skb(skb);
9782
9f40dead 9783 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9784 goto out;
9785
9786 if (rx_idx != rx_start_idx + num_pkts)
9787 goto out;
9788
9789 desc = &tp->rx_rcb[rx_start_idx];
9790 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9791 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9792 if (opaque_key != RXD_OPAQUE_RING_STD)
9793 goto out;
9794
9795 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9796 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9797 goto out;
9798
9799 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9800 if (rx_len != tx_len)
9801 goto out;
9802
9803 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9804
9805 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9806 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9807
9808 for (i = 14; i < tx_len; i++) {
9809 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9810 goto out;
9811 }
9812 err = 0;
6aa20a22 9813
c76949a6
MC		 9814 /* tg3_free_rings will unmap and free the rx_skb */
9815out:
9816 return err;
9817}
9818
9f40dead
MC		 9819#define TG3_MAC_LOOPBACK_FAILED 1
9820#define TG3_PHY_LOOPBACK_FAILED 2
9821#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9822 TG3_PHY_LOOPBACK_FAILED)
9823
9824static int tg3_test_loopback(struct tg3 *tp)
9825{
9826 int err = 0;
9936bcf6 9827 u32 cpmuctrl = 0;
9f40dead
MC		 9828
9829 if (!netif_running(tp->dev))
9830 return TG3_LOOPBACK_FAILED;
9831
b9ec6c1b
MC		 9832 err = tg3_reset_hw(tp, 1);
9833 if (err)
9834 return TG3_LOOPBACK_FAILED;
9f40dead 9835
6833c043
MC		 9836 /* Turn off gphy autopowerdown. */
9837 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9838 tg3_phy_toggle_apd(tp, false);
9839
321d32a0 9840 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9841 int i;
9842 u32 status;
9843
9844 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9845
9846 /* Wait for up to 40 microseconds to acquire lock. */
9847 for (i = 0; i < 4; i++) {
9848 status = tr32(TG3_CPMU_MUTEX_GNT);
9849 if (status == CPMU_MUTEX_GNT_DRIVER)
9850 break;
9851 udelay(10);
9852 }
9853
9854 if (status != CPMU_MUTEX_GNT_DRIVER)
9855 return TG3_LOOPBACK_FAILED;
9856
b2a5c19c 9857 /* Turn off link-based power management. */
e875093c 9858 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 9859 tw32(TG3_CPMU_CTRL,
9860 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9861 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9862 }
9863
9f40dead
MC		 9864 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9865 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9866
321d32a0 9867 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9868 tw32(TG3_CPMU_CTRL, cpmuctrl);
9869
9870 /* Release the mutex */
9871 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9872 }
9873
dd477003
MC		 9874 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9875 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 9876 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9877 err |= TG3_PHY_LOOPBACK_FAILED;
9878 }
9879
6833c043
MC		 9880 /* Re-enable gphy autopowerdown. */
9881 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9882 tg3_phy_toggle_apd(tp, true);
9883
9f40dead
MC		 9884 return err;
9885}
9886
4cafd3f5
MC		 9887static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9888 u64 *data)
9889{
566f86ad
MC		 9890 struct tg3 *tp = netdev_priv(dev);
9891
bc1c7567
MC		 9892 if (tp->link_config.phy_is_low_power)
9893 tg3_set_power_state(tp, PCI_D0);
9894
566f86ad
MC		 9895 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9896
9897 if (tg3_test_nvram(tp) != 0) {
9898 etest->flags |= ETH_TEST_FL_FAILED;
9899 data[0] = 1;
9900 }
ca43007a
MC		 9901 if (tg3_test_link(tp) != 0) {
9902 etest->flags |= ETH_TEST_FL_FAILED;
9903 data[1] = 1;
9904 }
a71116d1 9905 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 9906 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 9907
9908 if (netif_running(dev)) {
b02fd9e3 9909 tg3_phy_stop(tp);
a71116d1 9910 tg3_netif_stop(tp);
bbe832c0
MC		 9911 irq_sync = 1;
9912 }
a71116d1 9913
bbe832c0 9914 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9915
9916 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9917 err = tg3_nvram_lock(tp);
a71116d1
MC		 9918 tg3_halt_cpu(tp, RX_CPU_BASE);
9919 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9920 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9921 if (!err)
9922 tg3_nvram_unlock(tp);
a71116d1 9923
d9ab5ad1
MC		 9924 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9925 tg3_phy_reset(tp);
9926
a71116d1
MC		 9927 if (tg3_test_registers(tp) != 0) {
9928 etest->flags |= ETH_TEST_FL_FAILED;
9929 data[2] = 1;
9930 }
7942e1db
MC		 9931 if (tg3_test_memory(tp) != 0) {
9932 etest->flags |= ETH_TEST_FL_FAILED;
9933 data[3] = 1;
9934 }
9f40dead 9935 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9936 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9937
f47c11ee
DM		 9938 tg3_full_unlock(tp);
9939
d4bc3927
MC		 9940 if (tg3_test_interrupt(tp) != 0) {
9941 etest->flags |= ETH_TEST_FL_FAILED;
9942 data[5] = 1;
9943 }
f47c11ee
DM		 9944
9945 tg3_full_lock(tp, 0);
d4bc3927 9946
a71116d1
MC		 9947 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9948 if (netif_running(dev)) {
9949 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 9950 err2 = tg3_restart_hw(tp, 1);
9951 if (!err2)
b9ec6c1b 9952 tg3_netif_start(tp);
a71116d1 9953 }
f47c11ee
DM		 9954
9955 tg3_full_unlock(tp);
b02fd9e3
MC		 9956
9957 if (irq_sync && !err2)
9958 tg3_phy_start(tp);
a71116d1 9959 }
bc1c7567
MC		 9960 if (tp->link_config.phy_is_low_power)
9961 tg3_set_power_state(tp, PCI_D3hot);
9962
4cafd3f5
MC		 9963}
9964
1da177e4
LT		 9965static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9966{
9967 struct mii_ioctl_data *data = if_mii(ifr);
9968 struct tg3 *tp = netdev_priv(dev);
9969 int err;
9970
b02fd9e3
MC		 9971 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9972 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9973 return -EAGAIN;
298cf9be 9974 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 9975 }
9976
1da177e4
LT		 9977 switch(cmd) {
9978 case SIOCGMIIPHY:
9979 data->phy_id = PHY_ADDR;
9980
9981 /* fallthru */
9982 case SIOCGMIIREG: {
9983 u32 mii_regval;
9984
9985 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9986 break; /* We have no PHY */
9987
bc1c7567
MC		 9988 if (tp->link_config.phy_is_low_power)
9989 return -EAGAIN;
9990
f47c11ee 9991 spin_lock_bh(&tp->lock);
1da177e4 9992 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 9993 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9994
9995 data->val_out = mii_regval;
9996
9997 return err;
9998 }
9999
10000 case SIOCSMIIREG:
10001 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10002 break; /* We have no PHY */
10003
10004 if (!capable(CAP_NET_ADMIN))
10005 return -EPERM;
10006
bc1c7567
MC		 10007 if (tp->link_config.phy_is_low_power)
10008 return -EAGAIN;
10009
f47c11ee 10010 spin_lock_bh(&tp->lock);
1da177e4 10011 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10012 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10013
10014 return err;
10015
10016 default:
10017 /* do nothing */
10018 break;
10019 }
10020 return -EOPNOTSUPP;
10021}
10022
10023#if TG3_VLAN_TAG_USED
10024static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10025{
10026 struct tg3 *tp = netdev_priv(dev);
10027
844b3eed
MC		 10028 if (!netif_running(dev)) {
10029 tp->vlgrp = grp;
10030 return;
10031 }
10032
10033 tg3_netif_stop(tp);
29315e87 10034
f47c11ee 10035 tg3_full_lock(tp, 0);
1da177e4
LT		 10036
10037 tp->vlgrp = grp;
10038
10039 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10040 __tg3_set_rx_mode(dev);
10041
844b3eed 10042 tg3_netif_start(tp);
46966545
MC		 10043
10044 tg3_full_unlock(tp);
1da177e4 10045}
1da177e4
LT		 10046#endif
10047
15f9850d
DM		 10048static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10049{
10050 struct tg3 *tp = netdev_priv(dev);
10051
10052 memcpy(ec, &tp->coal, sizeof(*ec));
10053 return 0;
10054}
10055
d244c892
MC		 10056static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10057{
10058 struct tg3 *tp = netdev_priv(dev);
10059 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10060 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10061
10062 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10063 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10064 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10065 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10066 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10067 }
10068
10069 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10070 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10071 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10072 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10073 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10074 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10075 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10076 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10077 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10078 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10079 return -EINVAL;
10080
10081 /* No rx interrupts will be generated if both are zero */
10082 if ((ec->rx_coalesce_usecs == 0) &&
10083 (ec->rx_max_coalesced_frames == 0))
10084 return -EINVAL;
10085
10086 /* No tx interrupts will be generated if both are zero */
10087 if ((ec->tx_coalesce_usecs == 0) &&
10088 (ec->tx_max_coalesced_frames == 0))
10089 return -EINVAL;
10090
10091 /* Only copy relevant parameters, ignore all others. */
10092 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10093 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10094 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10095 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10096 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10097 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10098 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10099 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10100 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10101
10102 if (netif_running(dev)) {
10103 tg3_full_lock(tp, 0);
10104 __tg3_set_coalesce(tp, &tp->coal);
10105 tg3_full_unlock(tp);
10106 }
10107 return 0;
10108}
10109
7282d491 10110static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10111 .get_settings = tg3_get_settings,
10112 .set_settings = tg3_set_settings,
10113 .get_drvinfo = tg3_get_drvinfo,
10114 .get_regs_len = tg3_get_regs_len,
10115 .get_regs = tg3_get_regs,
10116 .get_wol = tg3_get_wol,
10117 .set_wol = tg3_set_wol,
10118 .get_msglevel = tg3_get_msglevel,
10119 .set_msglevel = tg3_set_msglevel,
10120 .nway_reset = tg3_nway_reset,
10121 .get_link = ethtool_op_get_link,
10122 .get_eeprom_len = tg3_get_eeprom_len,
10123 .get_eeprom = tg3_get_eeprom,
10124 .set_eeprom = tg3_set_eeprom,
10125 .get_ringparam = tg3_get_ringparam,
10126 .set_ringparam = tg3_set_ringparam,
10127 .get_pauseparam = tg3_get_pauseparam,
10128 .set_pauseparam = tg3_set_pauseparam,
10129 .get_rx_csum = tg3_get_rx_csum,
10130 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10131 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10132 .set_sg = ethtool_op_set_sg,
1da177e4 10133 .set_tso = tg3_set_tso,
4cafd3f5 10134 .self_test = tg3_self_test,
1da177e4 10135 .get_strings = tg3_get_strings,
4009a93d 10136 .phys_id = tg3_phys_id,
1da177e4 10137 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10138 .get_coalesce = tg3_get_coalesce,
d244c892 10139 .set_coalesce = tg3_set_coalesce,
b9f2c044 10140 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10141};
10142
10143static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10144{
1b27777a 10145 u32 cursize, val, magic;
1da177e4
LT		 10146
10147 tp->nvram_size = EEPROM_CHIP_SIZE;
10148
1820180b 10149 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1da177e4
LT		 10150 return;
10151
b16250e3
MC		 10152 if ((magic != TG3_EEPROM_MAGIC) &&
10153 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10154 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10155 return;
10156
10157 /*
10158 * Size the chip by reading offsets at increasing powers of two.
10159 * When we encounter our validation signature, we know the addressing
10160 * has wrapped around, and thus have our chip size.
10161 */
1b27777a 10162 cursize = 0x10;
1da177e4
LT		 10163
10164 while (cursize < tp->nvram_size) {
1820180b 10165 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
1da177e4
LT		 10166 return;
10167
1820180b 10168 if (val == magic)
1da177e4
LT		 10169 break;
10170
10171 cursize <<= 1;
10172 }
10173
10174 tp->nvram_size = cursize;
10175}
6aa20a22 10176
1da177e4
LT		 10177static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10178{
10179 u32 val;
10180
1820180b 10181 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
1b27777a
MC		 10182 return;
10183
10184 /* Selfboot format */
1820180b 10185 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10186 tg3_get_eeprom_size(tp);
10187 return;
10188 }
10189
1da177e4
LT		 10190 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10191 if (val != 0) {
10192 tp->nvram_size = (val >> 16) * 1024;
10193 return;
10194 }
10195 }
fd1122a2 10196 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10197}
10198
10199static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10200{
10201 u32 nvcfg1;
10202
10203 nvcfg1 = tr32(NVRAM_CFG1);
10204 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10205 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10206 }
10207 else {
10208 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10209 tw32(NVRAM_CFG1, nvcfg1);
10210 }
10211
4c987487 10212 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10213 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 10214 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10215 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10216 tp->nvram_jedecnum = JEDEC_ATMEL;
10217 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10218 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10219 break;
10220 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10221 tp->nvram_jedecnum = JEDEC_ATMEL;
10222 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10223 break;
10224 case FLASH_VENDOR_ATMEL_EEPROM:
10225 tp->nvram_jedecnum = JEDEC_ATMEL;
10226 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10227 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10228 break;
10229 case FLASH_VENDOR_ST:
10230 tp->nvram_jedecnum = JEDEC_ST;
10231 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10232 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10233 break;
10234 case FLASH_VENDOR_SAIFUN:
10235 tp->nvram_jedecnum = JEDEC_SAIFUN;
10236 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10237 break;
10238 case FLASH_VENDOR_SST_SMALL:
10239 case FLASH_VENDOR_SST_LARGE:
10240 tp->nvram_jedecnum = JEDEC_SST;
10241 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10242 break;
10243 }
10244 }
10245 else {
10246 tp->nvram_jedecnum = JEDEC_ATMEL;
10247 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10248 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10249 }
10250}
10251
361b4ac2
MC		 10252static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10253{
10254 u32 nvcfg1;
10255
10256 nvcfg1 = tr32(NVRAM_CFG1);
10257
e6af301b
MC		 10258 /* NVRAM protection for TPM */
10259 if (nvcfg1 & (1 << 27))
10260 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10261
361b4ac2
MC		 10262 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10263 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10264 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10265 tp->nvram_jedecnum = JEDEC_ATMEL;
10266 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10267 break;
10268 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10269 tp->nvram_jedecnum = JEDEC_ATMEL;
10270 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10271 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10272 break;
10273 case FLASH_5752VENDOR_ST_M45PE10:
10274 case FLASH_5752VENDOR_ST_M45PE20:
10275 case FLASH_5752VENDOR_ST_M45PE40:
10276 tp->nvram_jedecnum = JEDEC_ST;
10277 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10278 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10279 break;
10280 }
10281
10282 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10283 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10284 case FLASH_5752PAGE_SIZE_256:
10285 tp->nvram_pagesize = 256;
10286 break;
10287 case FLASH_5752PAGE_SIZE_512:
10288 tp->nvram_pagesize = 512;
10289 break;
10290 case FLASH_5752PAGE_SIZE_1K:
10291 tp->nvram_pagesize = 1024;
10292 break;
10293 case FLASH_5752PAGE_SIZE_2K:
10294 tp->nvram_pagesize = 2048;
10295 break;
10296 case FLASH_5752PAGE_SIZE_4K:
10297 tp->nvram_pagesize = 4096;
10298 break;
10299 case FLASH_5752PAGE_SIZE_264:
10300 tp->nvram_pagesize = 264;
10301 break;
10302 }
10303 }
10304 else {
10305 /* For eeprom, set pagesize to maximum eeprom size */
10306 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10307
10308 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10309 tw32(NVRAM_CFG1, nvcfg1);
10310 }
10311}
10312
d3c7b886
MC		 10313static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10314{
989a9d23 10315 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10316
10317 nvcfg1 = tr32(NVRAM_CFG1);
10318
10319 /* NVRAM protection for TPM */
989a9d23 10320 if (nvcfg1 & (1 << 27)) {
d3c7b886 10321 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10322 protect = 1;
10323 }
d3c7b886 10324
989a9d23
MC		 10325 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10326 switch (nvcfg1) {
d3c7b886
MC		 10327 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10328 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10329 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 10330 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 10331 tp->nvram_jedecnum = JEDEC_ATMEL;
10332 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10333 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10334 tp->nvram_pagesize = 264;
70b65a2d
MC		 10335 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10336 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
fd1122a2
MC		 10337 tp->nvram_size = (protect ? 0x3e200 :
10338 TG3_NVRAM_SIZE_512KB);
989a9d23 10339 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
fd1122a2
MC		 10340 tp->nvram_size = (protect ? 0x1f200 :
10341 TG3_NVRAM_SIZE_256KB);
989a9d23 10342 else
fd1122a2
MC		 10343 tp->nvram_size = (protect ? 0x1f200 :
10344 TG3_NVRAM_SIZE_128KB);
d3c7b886
MC		 10345 break;
10346 case FLASH_5752VENDOR_ST_M45PE10:
10347 case FLASH_5752VENDOR_ST_M45PE20:
10348 case FLASH_5752VENDOR_ST_M45PE40:
10349 tp->nvram_jedecnum = JEDEC_ST;
10350 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10351 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10352 tp->nvram_pagesize = 256;
989a9d23 10353 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
fd1122a2
MC		 10354 tp->nvram_size = (protect ?
10355 TG3_NVRAM_SIZE_64KB :
10356 TG3_NVRAM_SIZE_128KB);
989a9d23 10357 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
fd1122a2
MC		 10358 tp->nvram_size = (protect ?
10359 TG3_NVRAM_SIZE_64KB :
10360 TG3_NVRAM_SIZE_256KB);
989a9d23 10361 else
fd1122a2
MC		 10362 tp->nvram_size = (protect ?
10363 TG3_NVRAM_SIZE_128KB :
10364 TG3_NVRAM_SIZE_512KB);
d3c7b886
MC		 10365 break;
10366 }
10367}
10368
1b27777a
MC		 10369static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10370{
10371 u32 nvcfg1;
10372
10373 nvcfg1 = tr32(NVRAM_CFG1);
10374
10375 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10376 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10377 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10378 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10379 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10380 tp->nvram_jedecnum = JEDEC_ATMEL;
10381 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10382 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10383
10384 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10385 tw32(NVRAM_CFG1, nvcfg1);
10386 break;
10387 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10388 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10389 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10390 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10391 tp->nvram_jedecnum = JEDEC_ATMEL;
10392 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10393 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10394 tp->nvram_pagesize = 264;
10395 break;
10396 case FLASH_5752VENDOR_ST_M45PE10:
10397 case FLASH_5752VENDOR_ST_M45PE20:
10398 case FLASH_5752VENDOR_ST_M45PE40:
10399 tp->nvram_jedecnum = JEDEC_ST;
10400 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10401 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10402 tp->nvram_pagesize = 256;
10403 break;
10404 }
10405}
10406
6b91fa02
MC		 10407static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10408{
10409 u32 nvcfg1, protect = 0;
10410
10411 nvcfg1 = tr32(NVRAM_CFG1);
10412
10413 /* NVRAM protection for TPM */
10414 if (nvcfg1 & (1 << 27)) {
10415 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10416 protect = 1;
10417 }
10418
10419 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10420 switch (nvcfg1) {
10421 case FLASH_5761VENDOR_ATMEL_ADB021D:
10422 case FLASH_5761VENDOR_ATMEL_ADB041D:
10423 case FLASH_5761VENDOR_ATMEL_ADB081D:
10424 case FLASH_5761VENDOR_ATMEL_ADB161D:
10425 case FLASH_5761VENDOR_ATMEL_MDB021D:
10426 case FLASH_5761VENDOR_ATMEL_MDB041D:
10427 case FLASH_5761VENDOR_ATMEL_MDB081D:
10428 case FLASH_5761VENDOR_ATMEL_MDB161D:
10429 tp->nvram_jedecnum = JEDEC_ATMEL;
10430 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10431 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10432 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10433 tp->nvram_pagesize = 256;
10434 break;
10435 case FLASH_5761VENDOR_ST_A_M45PE20:
10436 case FLASH_5761VENDOR_ST_A_M45PE40:
10437 case FLASH_5761VENDOR_ST_A_M45PE80:
10438 case FLASH_5761VENDOR_ST_A_M45PE16:
10439 case FLASH_5761VENDOR_ST_M_M45PE20:
10440 case FLASH_5761VENDOR_ST_M_M45PE40:
10441 case FLASH_5761VENDOR_ST_M_M45PE80:
10442 case FLASH_5761VENDOR_ST_M_M45PE16:
10443 tp->nvram_jedecnum = JEDEC_ST;
10444 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10445 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10446 tp->nvram_pagesize = 256;
10447 break;
10448 }
10449
10450 if (protect) {
10451 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10452 } else {
10453 switch (nvcfg1) {
10454 case FLASH_5761VENDOR_ATMEL_ADB161D:
10455 case FLASH_5761VENDOR_ATMEL_MDB161D:
10456 case FLASH_5761VENDOR_ST_A_M45PE16:
10457 case FLASH_5761VENDOR_ST_M_M45PE16:
fd1122a2 10458 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
6b91fa02
MC		 10459 break;
10460 case FLASH_5761VENDOR_ATMEL_ADB081D:
10461 case FLASH_5761VENDOR_ATMEL_MDB081D:
10462 case FLASH_5761VENDOR_ST_A_M45PE80:
10463 case FLASH_5761VENDOR_ST_M_M45PE80:
fd1122a2 10464 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
6b91fa02
MC		 10465 break;
10466 case FLASH_5761VENDOR_ATMEL_ADB041D:
10467 case FLASH_5761VENDOR_ATMEL_MDB041D:
10468 case FLASH_5761VENDOR_ST_A_M45PE40:
10469 case FLASH_5761VENDOR_ST_M_M45PE40:
fd1122a2 10470 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
6b91fa02
MC		 10471 break;
10472 case FLASH_5761VENDOR_ATMEL_ADB021D:
10473 case FLASH_5761VENDOR_ATMEL_MDB021D:
10474 case FLASH_5761VENDOR_ST_A_M45PE20:
10475 case FLASH_5761VENDOR_ST_M_M45PE20:
fd1122a2 10476 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
6b91fa02
MC		 10477 break;
10478 }
10479 }
10480}
10481
b5d3772c
MC		 10482static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10483{
10484 tp->nvram_jedecnum = JEDEC_ATMEL;
10485 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10486 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10487}
10488
321d32a0
MC		 10489static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10490{
10491 u32 nvcfg1;
10492
10493 nvcfg1 = tr32(NVRAM_CFG1);
10494
10495 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10496 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10497 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10498 tp->nvram_jedecnum = JEDEC_ATMEL;
10499 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10500 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10501
10502 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10503 tw32(NVRAM_CFG1, nvcfg1);
10504 return;
10505 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10506 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10507 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10508 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10509 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10510 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10511 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10512 tp->nvram_jedecnum = JEDEC_ATMEL;
10513 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10514 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10515
10516 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10517 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10518 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10519 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10520 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10521 break;
10522 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10523 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10524 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10525 break;
10526 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10527 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10528 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10529 break;
10530 }
10531 break;
10532 case FLASH_5752VENDOR_ST_M45PE10:
10533 case FLASH_5752VENDOR_ST_M45PE20:
10534 case FLASH_5752VENDOR_ST_M45PE40:
10535 tp->nvram_jedecnum = JEDEC_ST;
10536 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10537 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10538
10539 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10540 case FLASH_5752VENDOR_ST_M45PE10:
10541 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10542 break;
10543 case FLASH_5752VENDOR_ST_M45PE20:
10544 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10545 break;
10546 case FLASH_5752VENDOR_ST_M45PE40:
10547 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10548 break;
10549 }
10550 break;
10551 default:
10552 return;
10553 }
10554
10555 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10556 case FLASH_5752PAGE_SIZE_256:
10557 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10558 tp->nvram_pagesize = 256;
10559 break;
10560 case FLASH_5752PAGE_SIZE_512:
10561 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10562 tp->nvram_pagesize = 512;
10563 break;
10564 case FLASH_5752PAGE_SIZE_1K:
10565 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10566 tp->nvram_pagesize = 1024;
10567 break;
10568 case FLASH_5752PAGE_SIZE_2K:
10569 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10570 tp->nvram_pagesize = 2048;
10571 break;
10572 case FLASH_5752PAGE_SIZE_4K:
10573 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10574 tp->nvram_pagesize = 4096;
10575 break;
10576 case FLASH_5752PAGE_SIZE_264:
10577 tp->nvram_pagesize = 264;
10578 break;
10579 case FLASH_5752PAGE_SIZE_528:
10580 tp->nvram_pagesize = 528;
10581 break;
10582 }
10583}
10584
1da177e4
LT		 10585/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10586static void __devinit tg3_nvram_init(struct tg3 *tp)
10587{
1da177e4
LT		 10588 tw32_f(GRC_EEPROM_ADDR,
10589 (EEPROM_ADDR_FSM_RESET |
10590 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10591 EEPROM_ADDR_CLKPERD_SHIFT)));
10592
9d57f01c 10593 msleep(1);
1da177e4
LT		 10594
10595 /* Enable seeprom accesses. */
10596 tw32_f(GRC_LOCAL_CTRL,
10597 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10598 udelay(100);
10599
10600 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10601 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10602 tp->tg3_flags |= TG3_FLAG_NVRAM;
10603
ec41c7df
MC		 10604 if (tg3_nvram_lock(tp)) {
10605 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10606 "tg3_nvram_init failed.\n", tp->dev->name);
10607 return;
10608 }
e6af301b 10609 tg3_enable_nvram_access(tp);
1da177e4 10610
989a9d23
MC		 10611 tp->nvram_size = 0;
10612
361b4ac2
MC		 10613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10614 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10615 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10616 tg3_get_5755_nvram_info(tp);
d30cdd28 10617 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10618 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10620 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10621 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10622 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10623 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10624 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10625 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10626 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10627 else
10628 tg3_get_nvram_info(tp);
10629
989a9d23
MC		 10630 if (tp->nvram_size == 0)
10631 tg3_get_nvram_size(tp);
1da177e4 10632
e6af301b 10633 tg3_disable_nvram_access(tp);
381291b7 10634 tg3_nvram_unlock(tp);
1da177e4
LT		 10635
10636 } else {
10637 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10638
10639 tg3_get_eeprom_size(tp);
10640 }
10641}
10642
1da177e4
LT		 10643static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10644 u32 offset, u32 len, u8 *buf)
10645{
10646 int i, j, rc = 0;
10647 u32 val;
10648
10649 for (i = 0; i < len; i += 4) {
b9fc7dc5
AV		 10650 u32 addr;
10651 __le32 data;
1da177e4
LT		 10652
10653 addr = offset + i;
10654
10655 memcpy(&data, buf + i, 4);
10656
b9fc7dc5 10657 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
1da177e4
LT		 10658
10659 val = tr32(GRC_EEPROM_ADDR);
10660 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10661
10662 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10663 EEPROM_ADDR_READ);
10664 tw32(GRC_EEPROM_ADDR, val |
10665 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10666 (addr & EEPROM_ADDR_ADDR_MASK) |
10667 EEPROM_ADDR_START |
10668 EEPROM_ADDR_WRITE);
6aa20a22 10669
9d57f01c 10670 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10671 val = tr32(GRC_EEPROM_ADDR);
10672
10673 if (val & EEPROM_ADDR_COMPLETE)
10674 break;
9d57f01c 10675 msleep(1);
1da177e4
LT		 10676 }
10677 if (!(val & EEPROM_ADDR_COMPLETE)) {
10678 rc = -EBUSY;
10679 break;
10680 }
10681 }
10682
10683 return rc;
10684}
10685
10686/* offset and length are dword aligned */
10687static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10688 u8 *buf)
10689{
10690 int ret = 0;
10691 u32 pagesize = tp->nvram_pagesize;
10692 u32 pagemask = pagesize - 1;
10693 u32 nvram_cmd;
10694 u8 *tmp;
10695
10696 tmp = kmalloc(pagesize, GFP_KERNEL);
10697 if (tmp == NULL)
10698 return -ENOMEM;
10699
10700 while (len) {
10701 int j;
e6af301b 10702 u32 phy_addr, page_off, size;
1da177e4
LT		 10703
10704 phy_addr = offset & ~pagemask;
6aa20a22 10705
1da177e4 10706 for (j = 0; j < pagesize; j += 4) {
286e310f 10707 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
b9fc7dc5 10708 (__le32 *) (tmp + j))))
1da177e4
LT		 10709 break;
10710 }
10711 if (ret)
10712 break;
10713
10714 page_off = offset & pagemask;
10715 size = pagesize;
10716 if (len < size)
10717 size = len;
10718
10719 len -= size;
10720
10721 memcpy(tmp + page_off, buf, size);
10722
10723 offset = offset + (pagesize - page_off);
10724
e6af301b 10725 tg3_enable_nvram_access(tp);
1da177e4
LT		 10726
10727 /*
10728 * Before we can erase the flash page, we need
10729 * to issue a special "write enable" command.
10730 */
10731 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10732
10733 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10734 break;
10735
10736 /* Erase the target page */
10737 tw32(NVRAM_ADDR, phy_addr);
10738
10739 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10740 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10741
10742 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10743 break;
10744
10745 /* Issue another write enable to start the write. */
10746 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10747
10748 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10749 break;
10750
10751 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10752 __be32 data;
1da177e4 10753
b9fc7dc5
AV		 10754 data = *((__be32 *) (tmp + j));
10755 /* swab32(le32_to_cpu(data)), actually */
10756 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10757
10758 tw32(NVRAM_ADDR, phy_addr + j);
10759
10760 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10761 NVRAM_CMD_WR;
10762
10763 if (j == 0)
10764 nvram_cmd |= NVRAM_CMD_FIRST;
10765 else if (j == (pagesize - 4))
10766 nvram_cmd |= NVRAM_CMD_LAST;
10767
10768 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10769 break;
10770 }
10771 if (ret)
10772 break;
10773 }
10774
10775 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10776 tg3_nvram_exec_cmd(tp, nvram_cmd);
10777
10778 kfree(tmp);
10779
10780 return ret;
10781}
10782
10783/* offset and length are dword aligned */
10784static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10785 u8 *buf)
10786{
10787 int i, ret = 0;
10788
10789 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10790 u32 page_off, phy_addr, nvram_cmd;
10791 __be32 data;
1da177e4
LT		 10792
10793 memcpy(&data, buf + i, 4);
b9fc7dc5 10794 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10795
10796 page_off = offset % tp->nvram_pagesize;
10797
1820180b 10798 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10799
10800 tw32(NVRAM_ADDR, phy_addr);
10801
10802 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10803
10804 if ((page_off == 0) || (i == 0))
10805 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10806 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10807 nvram_cmd |= NVRAM_CMD_LAST;
10808
10809 if (i == (len - 4))
10810 nvram_cmd |= NVRAM_CMD_LAST;
10811
321d32a0
MC		 10812 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10813 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10814 (tp->nvram_jedecnum == JEDEC_ST) &&
10815 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10816
10817 if ((ret = tg3_nvram_exec_cmd(tp,
10818 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10819 NVRAM_CMD_DONE)))
10820
10821 break;
10822 }
10823 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10824 /* We always do complete word writes to eeprom. */
10825 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10826 }
10827
10828 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10829 break;
10830 }
10831 return ret;
10832}
10833
10834/* offset and length are dword aligned */
10835static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10836{
10837 int ret;
10838
1da177e4 10839 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10840 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10841 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10842 udelay(40);
10843 }
10844
10845 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10846 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10847 }
10848 else {
10849 u32 grc_mode;
10850
ec41c7df
MC		 10851 ret = tg3_nvram_lock(tp);
10852 if (ret)
10853 return ret;
1da177e4 10854
e6af301b
MC		 10855 tg3_enable_nvram_access(tp);
10856 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10857 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10858 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10859
10860 grc_mode = tr32(GRC_MODE);
10861 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10862
10863 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10864 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10865
10866 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10867 buf);
10868 }
10869 else {
10870 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10871 buf);
10872 }
10873
10874 grc_mode = tr32(GRC_MODE);
10875 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10876
e6af301b 10877 tg3_disable_nvram_access(tp);
1da177e4
LT		 10878 tg3_nvram_unlock(tp);
10879 }
10880
10881 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10882 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10883 udelay(40);
10884 }
10885
10886 return ret;
10887}
10888
10889struct subsys_tbl_ent {
10890 u16 subsys_vendor, subsys_devid;
10891 u32 phy_id;
10892};
10893
10894static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10895 /* Broadcom boards. */
10896 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10897 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10898 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10899 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10900 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10901 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10902 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10903 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10904 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10905 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10906 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10907
10908 /* 3com boards. */
10909 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10910 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10911 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10912 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10913 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10914
10915 /* DELL boards. */
10916 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10917 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10918 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10919 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10920
10921 /* Compaq boards. */
10922 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10923 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10924 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10925 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10926 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10927
10928 /* IBM boards. */
10929 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10930};
10931
10932static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10933{
10934 int i;
10935
10936 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10937 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10938 tp->pdev->subsystem_vendor) &&
10939 (subsys_id_to_phy_id[i].subsys_devid ==
10940 tp->pdev->subsystem_device))
10941 return &subsys_id_to_phy_id[i];
10942 }
10943 return NULL;
10944}
10945
7d0c41ef 10946static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10947{
1da177e4 10948 u32 val;
caf636c7
MC		 10949 u16 pmcsr;
10950
10951 /* On some early chips the SRAM cannot be accessed in D3hot state,
10952 * so need make sure we're in D0.
10953 */
10954 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10955 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10956 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10957 msleep(1);
7d0c41ef
MC		 10958
10959 /* Make sure register accesses (indirect or otherwise)
10960 * will function correctly.
10961 */
10962 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10963 tp->misc_host_ctrl);
1da177e4 10964
f49639e6
DM		 10965 /* The memory arbiter has to be enabled in order for SRAM accesses
10966 * to succeed. Normally on powerup the tg3 chip firmware will make
10967 * sure it is enabled, but other entities such as system netboot
10968 * code might disable it.
10969 */
10970 val = tr32(MEMARB_MODE);
10971 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10972
1da177e4 10973 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 10974 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10975
a85feb8c
GZ		 10976 /* Assume an onboard device and WOL capable by default. */
10977 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 10978
b5d3772c 10979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 10980 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 10981 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 10982 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10983 }
0527ba35
MC		 10984 val = tr32(VCPU_CFGSHDW);
10985 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 10986 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 10987 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 10988 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 10989 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 10990 goto done;
b5d3772c
MC		 10991 }
10992
1da177e4
LT		 10993 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10994 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10995 u32 nic_cfg, led_cfg;
a9daf367 10996 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 10997 int eeprom_phy_serdes = 0;
1da177e4
LT		 10998
10999 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11000 tp->nic_sram_data_cfg = nic_cfg;
11001
11002 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11003 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11004 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11005 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11006 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11007 (ver > 0) && (ver < 0x100))
11008 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11009
a9daf367
MC		 11010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11011 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11012
1da177e4
LT		 11013 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11014 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11015 eeprom_phy_serdes = 1;
11016
11017 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11018 if (nic_phy_id != 0) {
11019 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11020 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11021
11022 eeprom_phy_id = (id1 >> 16) << 10;
11023 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11024 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11025 } else
11026 eeprom_phy_id = 0;
11027
7d0c41ef 11028 tp->phy_id = eeprom_phy_id;
747e8f8b 11029 if (eeprom_phy_serdes) {
a4e2b347 11030 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11031 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11032 else
11033 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11034 }
7d0c41ef 11035
cbf46853 11036 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11037 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11038 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11039 else
1da177e4
LT		 11040 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11041
11042 switch (led_cfg) {
11043 default:
11044 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11045 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11046 break;
11047
11048 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11049 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11050 break;
11051
11052 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11053 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11054
11055 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11056 * read on some older 5700/5701 bootcode.
11057 */
11058 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11059 ASIC_REV_5700 ||
11060 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11061 ASIC_REV_5701)
11062 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11063
1da177e4
LT		 11064 break;
11065
11066 case SHASTA_EXT_LED_SHARED:
11067 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11068 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11069 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11070 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11071 LED_CTRL_MODE_PHY_2);
11072 break;
11073
11074 case SHASTA_EXT_LED_MAC:
11075 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11076 break;
11077
11078 case SHASTA_EXT_LED_COMBO:
11079 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11080 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11081 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11082 LED_CTRL_MODE_PHY_2);
11083 break;
11084
855e1111 11085 }
1da177e4
LT		 11086
11087 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11088 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11089 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11090 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11091
b2a5c19c
MC		 11092 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11093 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11094
9d26e213 11095 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11096 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11097 if ((tp->pdev->subsystem_vendor ==
11098 PCI_VENDOR_ID_ARIMA) &&
11099 (tp->pdev->subsystem_device == 0x205a ||
11100 tp->pdev->subsystem_device == 0x2063))
11101 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11102 } else {
f49639e6 11103 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11104 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11105 }
1da177e4
LT		 11106
11107 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11108 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11109 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11110 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11111 }
b2b98d4a
MC		 11112
11113 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11114 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11115 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11116
a85feb8c
GZ		 11117 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11118 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11119 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11120
12dac075 11121 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11122 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11123 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11124
1da177e4
LT		 11125 if (cfg2 & (1 << 17))
11126 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11127
11128 /* serdes signal pre-emphasis in register 0x590 set by */
11129 /* bootcode if bit 18 is set */
11130 if (cfg2 & (1 << 18))
11131 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11132
321d32a0
MC		 11133 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11134 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11135 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11136 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11137
8ed5d97e
MC		 11138 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11139 u32 cfg3;
11140
11141 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11142 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11143 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11144 }
a9daf367
MC		 11145
11146 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11147 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11148 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11149 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11150 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11151 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11152 }
05ac4cb7
MC		 11153done:
11154 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11155 device_set_wakeup_enable(&tp->pdev->dev,
11156 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11157}
11158
b2a5c19c
MC		 11159static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11160{
11161 int i;
11162 u32 val;
11163
11164 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11165 tw32(OTP_CTRL, cmd);
11166
11167 /* Wait for up to 1 ms for command to execute. */
11168 for (i = 0; i < 100; i++) {
11169 val = tr32(OTP_STATUS);
11170 if (val & OTP_STATUS_CMD_DONE)
11171 break;
11172 udelay(10);
11173 }
11174
11175 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11176}
11177
11178/* Read the gphy configuration from the OTP region of the chip. The gphy
11179 * configuration is a 32-bit value that straddles the alignment boundary.
11180 * We do two 32-bit reads and then shift and merge the results.
11181 */
11182static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11183{
11184 u32 bhalf_otp, thalf_otp;
11185
11186 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11187
11188 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11189 return 0;
11190
11191 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11192
11193 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11194 return 0;
11195
11196 thalf_otp = tr32(OTP_READ_DATA);
11197
11198 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11199
11200 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11201 return 0;
11202
11203 bhalf_otp = tr32(OTP_READ_DATA);
11204
11205 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11206}
11207
7d0c41ef
MC		 11208static int __devinit tg3_phy_probe(struct tg3 *tp)
11209{
11210 u32 hw_phy_id_1, hw_phy_id_2;
11211 u32 hw_phy_id, hw_phy_id_masked;
11212 int err;
1da177e4 11213
b02fd9e3
MC		 11214 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11215 return tg3_phy_init(tp);
11216
1da177e4
LT		 11217 /* Reading the PHY ID register can conflict with ASF
11218 * firwmare access to the PHY hardware.
11219 */
11220 err = 0;
0d3031d9
MC		 11221 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11222 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11223 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11224 } else {
11225 /* Now read the physical PHY_ID from the chip and verify
11226 * that it is sane. If it doesn't look good, we fall back
11227 * to either the hard-coded table based PHY_ID and failing
11228 * that the value found in the eeprom area.
11229 */
11230 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11231 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11232
11233 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11234 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11235 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11236
11237 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11238 }
11239
11240 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11241 tp->phy_id = hw_phy_id;
11242 if (hw_phy_id_masked == PHY_ID_BCM8002)
11243 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11244 else
11245 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11246 } else {
7d0c41ef
MC		 11247 if (tp->phy_id != PHY_ID_INVALID) {
11248 /* Do nothing, phy ID already set up in
11249 * tg3_get_eeprom_hw_cfg().
11250 */
1da177e4
LT		 11251 } else {
11252 struct subsys_tbl_ent *p;
11253
11254 /* No eeprom signature? Try the hardcoded
11255 * subsys device table.
11256 */
11257 p = lookup_by_subsys(tp);
11258 if (!p)
11259 return -ENODEV;
11260
11261 tp->phy_id = p->phy_id;
11262 if (!tp->phy_id ||
11263 tp->phy_id == PHY_ID_BCM8002)
11264 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11265 }
11266 }
11267
747e8f8b 11268 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11269 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11270 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11271 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11272
11273 tg3_readphy(tp, MII_BMSR, &bmsr);
11274 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11275 (bmsr & BMSR_LSTATUS))
11276 goto skip_phy_reset;
6aa20a22 11277
1da177e4
LT		 11278 err = tg3_phy_reset(tp);
11279 if (err)
11280 return err;
11281
11282 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11283 ADVERTISE_100HALF | ADVERTISE_100FULL |
11284 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11285 tg3_ctrl = 0;
11286 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11287 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11288 MII_TG3_CTRL_ADV_1000_FULL);
11289 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11290 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11291 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11292 MII_TG3_CTRL_ENABLE_AS_MASTER);
11293 }
11294
3600d918
MC		 11295 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11296 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11297 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11298 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11299 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11300
11301 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11302 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11303
11304 tg3_writephy(tp, MII_BMCR,
11305 BMCR_ANENABLE | BMCR_ANRESTART);
11306 }
11307 tg3_phy_set_wirespeed(tp);
11308
11309 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11310 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11311 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11312 }
11313
11314skip_phy_reset:
11315 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11316 err = tg3_init_5401phy_dsp(tp);
11317 if (err)
11318 return err;
11319 }
11320
11321 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11322 err = tg3_init_5401phy_dsp(tp);
11323 }
11324
747e8f8b 11325 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11326 tp->link_config.advertising =
11327 (ADVERTISED_1000baseT_Half |
11328 ADVERTISED_1000baseT_Full |
11329 ADVERTISED_Autoneg |
11330 ADVERTISED_FIBRE);
11331 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11332 tp->link_config.advertising &=
11333 ~(ADVERTISED_1000baseT_Half |
11334 ADVERTISED_1000baseT_Full);
11335
11336 return err;
11337}
11338
11339static void __devinit tg3_read_partno(struct tg3 *tp)
11340{
11341 unsigned char vpd_data[256];
af2c6a4a 11342 unsigned int i;
1b27777a 11343 u32 magic;
1da177e4 11344
1820180b 11345 if (tg3_nvram_read_swab(tp, 0x0, &magic))
f49639e6 11346 goto out_not_found;
1da177e4 11347
1820180b 11348 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11349 for (i = 0; i < 256; i += 4) {
11350 u32 tmp;
1da177e4 11351
1b27777a
MC		 11352 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11353 goto out_not_found;
11354
11355 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11356 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11357 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11358 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11359 }
11360 } else {
11361 int vpd_cap;
11362
11363 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11364 for (i = 0; i < 256; i += 4) {
11365 u32 tmp, j = 0;
b9fc7dc5 11366 __le32 v;
1b27777a
MC		 11367 u16 tmp16;
11368
11369 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11370 i);
11371 while (j++ < 100) {
11372 pci_read_config_word(tp->pdev, vpd_cap +
11373 PCI_VPD_ADDR, &tmp16);
11374 if (tmp16 & 0x8000)
11375 break;
11376 msleep(1);
11377 }
f49639e6
DM		 11378 if (!(tmp16 & 0x8000))
11379 goto out_not_found;
11380
1b27777a
MC		 11381 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11382 &tmp);
b9fc7dc5
AV		 11383 v = cpu_to_le32(tmp);
11384 memcpy(&vpd_data[i], &v, 4);
1b27777a 11385 }
1da177e4
LT		 11386 }
11387
11388 /* Now parse and find the part number. */
af2c6a4a 11389 for (i = 0; i < 254; ) {
1da177e4 11390 unsigned char val = vpd_data[i];
af2c6a4a 11391 unsigned int block_end;
1da177e4
LT		 11392
11393 if (val == 0x82 || val == 0x91) {
11394 i = (i + 3 +
11395 (vpd_data[i + 1] +
11396 (vpd_data[i + 2] << 8)));
11397 continue;
11398 }
11399
11400 if (val != 0x90)
11401 goto out_not_found;
11402
11403 block_end = (i + 3 +
11404 (vpd_data[i + 1] +
11405 (vpd_data[i + 2] << 8)));
11406 i += 3;
af2c6a4a
MC		 11407
11408 if (block_end > 256)
11409 goto out_not_found;
11410
11411 while (i < (block_end - 2)) {
1da177e4
LT		 11412 if (vpd_data[i + 0] == 'P' &&
11413 vpd_data[i + 1] == 'N') {
11414 int partno_len = vpd_data[i + 2];
11415
af2c6a4a
MC		 11416 i += 3;
11417 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11418 goto out_not_found;
11419
11420 memcpy(tp->board_part_number,
af2c6a4a 11421 &vpd_data[i], partno_len);
1da177e4
LT		 11422
11423 /* Success. */
11424 return;
11425 }
af2c6a4a 11426 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11427 }
11428
11429 /* Part number not found. */
11430 goto out_not_found;
11431 }
11432
11433out_not_found:
b5d3772c
MC		 11434 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11435 strcpy(tp->board_part_number, "BCM95906");
11436 else
11437 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11438}
11439
9c8a620e
MC		 11440static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11441{
11442 u32 val;
11443
11444 if (tg3_nvram_read_swab(tp, offset, &val) ||
11445 (val & 0xfc000000) != 0x0c000000 ||
11446 tg3_nvram_read_swab(tp, offset + 4, &val) ||
11447 val != 0)
11448 return 0;
11449
11450 return 1;
11451}
11452
dfe00d7d
MC		 11453static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11454{
11455 u32 offset, major, minor, build;
11456
11457 tp->fw_ver[0] = 's';
11458 tp->fw_ver[1] = 'b';
11459 tp->fw_ver[2] = '\0';
11460
11461 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11462 return;
11463
11464 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11465 case TG3_EEPROM_SB_REVISION_0:
11466 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11467 break;
11468 case TG3_EEPROM_SB_REVISION_2:
11469 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11470 break;
11471 case TG3_EEPROM_SB_REVISION_3:
11472 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11473 break;
11474 default:
11475 return;
11476 }
11477
11478 if (tg3_nvram_read_swab(tp, offset, &val))
11479 return;
11480
11481 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11482 TG3_EEPROM_SB_EDH_BLD_SHFT;
11483 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11484 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11485 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11486
11487 if (minor > 99 || build > 26)
11488 return;
11489
11490 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11491
11492 if (build > 0) {
11493 tp->fw_ver[8] = 'a' + build - 1;
11494 tp->fw_ver[9] = '\0';
11495 }
11496}
11497
c4e6575c
MC		 11498static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11499{
11500 u32 val, offset, start;
9c8a620e
MC		 11501 u32 ver_offset;
11502 int i, bcnt;
c4e6575c
MC		 11503
11504 if (tg3_nvram_read_swab(tp, 0, &val))
11505 return;
11506
dfe00d7d
MC		 11507 if (val != TG3_EEPROM_MAGIC) {
11508 if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11509 tg3_read_sb_ver(tp, val);
11510
c4e6575c 11511 return;
dfe00d7d 11512 }
c4e6575c
MC		 11513
11514 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11515 tg3_nvram_read_swab(tp, 0x4, &start))
11516 return;
11517
11518 offset = tg3_nvram_logical_addr(tp, offset);
9c8a620e
MC		 11519
11520 if (!tg3_fw_img_is_valid(tp, offset) ||
11521 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
c4e6575c
MC		 11522 return;
11523
9c8a620e
MC		 11524 offset = offset + ver_offset - start;
11525 for (i = 0; i < 16; i += 4) {
b9fc7dc5
AV		 11526 __le32 v;
11527 if (tg3_nvram_read_le(tp, offset + i, &v))
9c8a620e
MC		 11528 return;
11529
b9fc7dc5 11530 memcpy(tp->fw_ver + i, &v, 4);
9c8a620e 11531 }
c4e6575c 11532
9c8a620e 11533 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
84af67fd 11534 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
9c8a620e
MC		 11535 return;
11536
11537 for (offset = TG3_NVM_DIR_START;
11538 offset < TG3_NVM_DIR_END;
11539 offset += TG3_NVM_DIRENT_SIZE) {
11540 if (tg3_nvram_read_swab(tp, offset, &val))
c4e6575c
MC		 11541 return;
11542
9c8a620e
MC		 11543 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11544 break;
11545 }
11546
11547 if (offset == TG3_NVM_DIR_END)
11548 return;
11549
11550 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11551 start = 0x08000000;
11552 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11553 return;
11554
11555 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11556 !tg3_fw_img_is_valid(tp, offset) ||
11557 tg3_nvram_read_swab(tp, offset + 8, &val))
11558 return;
11559
11560 offset += val - start;
11561
11562 bcnt = strlen(tp->fw_ver);
11563
11564 tp->fw_ver[bcnt++] = ',';
11565 tp->fw_ver[bcnt++] = ' ';
11566
11567 for (i = 0; i < 4; i++) {
b9fc7dc5
AV		 11568 __le32 v;
11569 if (tg3_nvram_read_le(tp, offset, &v))
c4e6575c
MC		 11570 return;
11571
b9fc7dc5 11572 offset += sizeof(v);
c4e6575c 11573
b9fc7dc5
AV		 11574 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11575 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
9c8a620e 11576 break;
c4e6575c 11577 }
9c8a620e 11578
b9fc7dc5
AV		 11579 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11580 bcnt += sizeof(v);
c4e6575c 11581 }
9c8a620e
MC		 11582
11583 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11584}
11585
7544b097
MC		 11586static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11587
1da177e4
LT		 11588static int __devinit tg3_get_invariants(struct tg3 *tp)
11589{
11590 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11591 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11592 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11593 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11594 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11595 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11596 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11597 { },
11598 };
11599 u32 misc_ctrl_reg;
1da177e4
LT		 11600 u32 pci_state_reg, grc_misc_cfg;
11601 u32 val;
11602 u16 pci_cmd;
5e7dfd0f 11603 int err;
1da177e4 11604
1da177e4
LT		 11605 /* Force memory write invalidate off. If we leave it on,
11606 * then on 5700_BX chips we have to enable a workaround.
11607 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11608 * to match the cacheline size. The Broadcom driver have this
11609 * workaround but turns MWI off all the times so never uses
11610 * it. This seems to suggest that the workaround is insufficient.
11611 */
11612 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11613 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11614 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11615
11616 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11617 * has the register indirect write enable bit set before
11618 * we try to access any of the MMIO registers. It is also
11619 * critical that the PCI-X hw workaround situation is decided
11620 * before that as well.
11621 */
11622 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11623 &misc_ctrl_reg);
11624
11625 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11626 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11628 u32 prod_id_asic_rev;
11629
11630 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11631 &prod_id_asic_rev);
321d32a0 11632 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11633 }
1da177e4 11634
ff645bec
MC		 11635 /* Wrong chip ID in 5752 A0. This code can be removed later
11636 * as A0 is not in production.
11637 */
11638 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11639 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11640
6892914f
MC		 11641 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11642 * we need to disable memory and use config. cycles
11643 * only to access all registers. The 5702/03 chips
11644 * can mistakenly decode the special cycles from the
11645 * ICH chipsets as memory write cycles, causing corruption
11646 * of register and memory space. Only certain ICH bridges
11647 * will drive special cycles with non-zero data during the
11648 * address phase which can fall within the 5703's address
11649 * range. This is not an ICH bug as the PCI spec allows
11650 * non-zero address during special cycles. However, only
11651 * these ICH bridges are known to drive non-zero addresses
11652 * during special cycles.
11653 *
11654 * Since special cycles do not cross PCI bridges, we only
11655 * enable this workaround if the 5703 is on the secondary
11656 * bus of these ICH bridges.
11657 */
11658 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11659 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11660 static struct tg3_dev_id {
11661 u32 vendor;
11662 u32 device;
11663 u32 rev;
11664 } ich_chipsets[] = {
11665 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11666 PCI_ANY_ID },
11667 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11668 PCI_ANY_ID },
11669 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11670 0xa },
11671 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11672 PCI_ANY_ID },
11673 { },
11674 };
11675 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11676 struct pci_dev *bridge = NULL;
11677
11678 while (pci_id->vendor != 0) {
11679 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11680 bridge);
11681 if (!bridge) {
11682 pci_id++;
11683 continue;
11684 }
11685 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11686 if (bridge->revision > pci_id->rev)
6892914f
MC		 11687 continue;
11688 }
11689 if (bridge->subordinate &&
11690 (bridge->subordinate->number ==
11691 tp->pdev->bus->number)) {
11692
11693 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11694 pci_dev_put(bridge);
11695 break;
11696 }
11697 }
11698 }
11699
41588ba1
MC		 11700 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11701 static struct tg3_dev_id {
11702 u32 vendor;
11703 u32 device;
11704 } bridge_chipsets[] = {
11705 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11706 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11707 { },
11708 };
11709 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11710 struct pci_dev *bridge = NULL;
11711
11712 while (pci_id->vendor != 0) {
11713 bridge = pci_get_device(pci_id->vendor,
11714 pci_id->device,
11715 bridge);
11716 if (!bridge) {
11717 pci_id++;
11718 continue;
11719 }
11720 if (bridge->subordinate &&
11721 (bridge->subordinate->number <=
11722 tp->pdev->bus->number) &&
11723 (bridge->subordinate->subordinate >=
11724 tp->pdev->bus->number)) {
11725 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11726 pci_dev_put(bridge);
11727 break;
11728 }
11729 }
11730 }
11731
4a29cc2e
MC		 11732 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11733 * DMA addresses > 40-bit. This bridge may have other additional
11734 * 57xx devices behind it in some 4-port NIC designs for example.
11735 * Any tg3 device found behind the bridge will also need the 40-bit
11736 * DMA workaround.
11737 */
a4e2b347
MC		 11738 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11739 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11740 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11741 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11742 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11743 }
4a29cc2e
MC		 11744 else {
11745 struct pci_dev *bridge = NULL;
11746
11747 do {
11748 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11749 PCI_DEVICE_ID_SERVERWORKS_EPB,
11750 bridge);
11751 if (bridge && bridge->subordinate &&
11752 (bridge->subordinate->number <=
11753 tp->pdev->bus->number) &&
11754 (bridge->subordinate->subordinate >=
11755 tp->pdev->bus->number)) {
11756 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11757 pci_dev_put(bridge);
11758 break;
11759 }
11760 } while (bridge);
11761 }
4cf78e4f 11762
1da177e4
LT		 11763 /* Initialize misc host control in PCI block. */
11764 tp->misc_host_ctrl |= (misc_ctrl_reg &
11765 MISC_HOST_CTRL_CHIPREV);
11766 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11767 tp->misc_host_ctrl);
11768
7544b097
MC		 11769 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11770 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11771 tp->pdev_peer = tg3_find_peer(tp);
11772
321d32a0
MC		 11773 /* Intentionally exclude ASIC_REV_5906 */
11774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11776 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 11778 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 11779 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11780 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11781
11782 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11783 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 11784 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 11785 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 11786 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11787 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11788
1b440c56
JL		 11789 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11790 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11791 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11792
027455ad
MC		 11793 /* 5700 B0 chips do not support checksumming correctly due
11794 * to hardware bugs.
11795 */
11796 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11797 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11798 else {
11799 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11800 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11801 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11802 tp->dev->features |= NETIF_F_IPV6_CSUM;
11803 }
11804
5a6f3074 11805 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11806 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11807 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11808 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11809 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11810 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11811 tp->pdev_peer == tp->pdev))
11812 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11813
321d32a0 11814 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 11815 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11816 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11817 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11818 } else {
7f62ad5d 11819 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11820 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11821 ASIC_REV_5750 &&
11822 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11823 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11824 }
5a6f3074 11825 }
1da177e4 11826
f51f3562
MC		 11827 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11828 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6
MC		 11829 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11830
52f4490c
MC		 11831 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11832 &pci_state_reg);
11833
5e7dfd0f
MC		 11834 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11835 if (tp->pcie_cap != 0) {
11836 u16 lnkctl;
11837
1da177e4 11838 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 11839
11840 pcie_set_readrq(tp->pdev, 4096);
11841
5e7dfd0f
MC		 11842 pci_read_config_word(tp->pdev,
11843 tp->pcie_cap + PCI_EXP_LNKCTL,
11844 &lnkctl);
11845 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11846 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 11847 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 11848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 11849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11850 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
5e7dfd0f 11851 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 11852 }
52f4490c 11853 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 11854 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 11855 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11856 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11857 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11858 if (!tp->pcix_cap) {
11859 printk(KERN_ERR PFX "Cannot find PCI-X "
11860 "capability, aborting.\n");
11861 return -EIO;
11862 }
11863
11864 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
11865 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11866 }
1da177e4 11867
399de50b
MC		 11868 /* If we have an AMD 762 or VIA K8T800 chipset, write
11869 * reordering to the mailbox registers done by the host
11870 * controller can cause major troubles. We read back from
11871 * every mailbox register write to force the writes to be
11872 * posted to the chip in order.
11873 */
11874 if (pci_dev_present(write_reorder_chipsets) &&
11875 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11876 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11877
69fc4053
MC		 11878 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
11879 &tp->pci_cacheline_sz);
11880 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11881 &tp->pci_lat_timer);
1da177e4
LT		 11882 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11883 tp->pci_lat_timer < 64) {
11884 tp->pci_lat_timer = 64;
69fc4053
MC		 11885 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11886 tp->pci_lat_timer);
1da177e4
LT		 11887 }
11888
52f4490c
MC		 11889 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11890 /* 5700 BX chips need to have their TX producer index
11891 * mailboxes written twice to workaround a bug.
11892 */
11893 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 11894
52f4490c 11895 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 11896 *
11897 * The workaround is to use indirect register accesses
11898 * for all chip writes not to mailbox registers.
11899 */
52f4490c 11900 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 11901 u32 pm_reg;
1da177e4
LT		 11902
11903 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11904
11905 /* The chip can have it's power management PCI config
11906 * space registers clobbered due to this bug.
11907 * So explicitly force the chip into D0 here.
11908 */
9974a356
MC		 11909 pci_read_config_dword(tp->pdev,
11910 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11911 &pm_reg);
11912 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11913 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 11914 pci_write_config_dword(tp->pdev,
11915 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 11916 pm_reg);
11917
11918 /* Also, force SERR#/PERR# in PCI command. */
11919 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11920 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11921 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11922 }
11923 }
11924
1da177e4
LT		 11925 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11926 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11927 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11928 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11929
11930 /* Chip-specific fixup from Broadcom driver */
11931 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11932 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11933 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11934 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11935 }
11936
1ee582d8 11937 /* Default fast path register access methods */
20094930 11938 tp->read32 = tg3_read32;
1ee582d8 11939 tp->write32 = tg3_write32;
09ee929c 11940 tp->read32_mbox = tg3_read32;
20094930 11941 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 11942 tp->write32_tx_mbox = tg3_write32;
11943 tp->write32_rx_mbox = tg3_write32;
11944
11945 /* Various workaround register access methods */
11946 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11947 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 11948 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11949 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11950 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11951 /*
11952 * Back to back register writes can cause problems on these
11953 * chips, the workaround is to read back all reg writes
11954 * except those to mailbox regs.
11955 *
11956 * See tg3_write_indirect_reg32().
11957 */
1ee582d8 11958 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 11959 }
11960
1ee582d8
MC		 11961
11962 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11963 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11964 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11965 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11966 tp->write32_rx_mbox = tg3_write_flush_reg32;
11967 }
20094930 11968
6892914f
MC		 11969 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11970 tp->read32 = tg3_read_indirect_reg32;
11971 tp->write32 = tg3_write_indirect_reg32;
11972 tp->read32_mbox = tg3_read_indirect_mbox;
11973 tp->write32_mbox = tg3_write_indirect_mbox;
11974 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11975 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11976
11977 iounmap(tp->regs);
22abe310 11978 tp->regs = NULL;
6892914f
MC		 11979
11980 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11981 pci_cmd &= ~PCI_COMMAND_MEMORY;
11982 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11983 }
b5d3772c
MC		 11984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11985 tp->read32_mbox = tg3_read32_mbox_5906;
11986 tp->write32_mbox = tg3_write32_mbox_5906;
11987 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11988 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11989 }
6892914f 11990
bbadf503
MC		 11991 if (tp->write32 == tg3_write_indirect_reg32 ||
11992 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11993 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 11994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 11995 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
11996
7d0c41ef 11997 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 11998 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 11999 * determined before calling tg3_set_power_state() so that
12000 * we know whether or not to switch out of Vaux power.
12001 * When the flag is set, it means that GPIO1 is used for eeprom
12002 * write protect and also implies that it is a LOM where GPIOs
12003 * are not used to switch power.
6aa20a22 12004 */
7d0c41ef
MC		 12005 tg3_get_eeprom_hw_cfg(tp);
12006
0d3031d9
MC		 12007 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12008 /* Allow reads and writes to the
12009 * APE register and memory space.
12010 */
12011 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12012 PCISTATE_ALLOW_APE_SHMEM_WR;
12013 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12014 pci_state_reg);
12015 }
12016
9936bcf6 12017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12020 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12021 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12022
314fba34
MC		 12023 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12024 * GPIO1 driven high will bring 5700's external PHY out of reset.
12025 * It is also used as eeprom write protect on LOMs.
12026 */
12027 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12028 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12029 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12030 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12031 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12032 /* Unused GPIO3 must be driven as output on 5752 because there
12033 * are no pull-up resistors on unused GPIO pins.
12034 */
12035 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12036 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12037
321d32a0
MC		 12038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12040 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12041
5f0c4a3c
MC		 12042 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12043 /* Turn off the debug UART. */
12044 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12045 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12046 /* Keep VMain power. */
12047 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12048 GRC_LCLCTRL_GPIO_OUTPUT0;
12049 }
12050
1da177e4 12051 /* Force the chip into D0. */
bc1c7567 12052 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12053 if (err) {
12054 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12055 pci_name(tp->pdev));
12056 return err;
12057 }
12058
1da177e4
LT		 12059 /* Derive initial jumbo mode from MTU assigned in
12060 * ether_setup() via the alloc_etherdev() call
12061 */
0f893dc6 12062 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12063 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12064 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12065
12066 /* Determine WakeOnLan speed to use. */
12067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12068 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12069 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12070 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12071 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12072 } else {
12073 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12074 }
12075
12076 /* A few boards don't want Ethernet@WireSpeed phy feature */
12077 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12078 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12079 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12080 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 12081 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 12082 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12083 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12084
12085 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12086 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12087 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12088 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12089 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12090
321d32a0
MC		 12091 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12092 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12093 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12094 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12099 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12100 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12101 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12102 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12103 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12104 } else
c424cb24
MC		 12105 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12106 }
1da177e4 12107
b2a5c19c
MC		 12108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12109 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12110 tp->phy_otp = tg3_read_otp_phycfg(tp);
12111 if (tp->phy_otp == 0)
12112 tp->phy_otp = TG3_OTP_DEFAULT;
12113 }
12114
f51f3562 12115 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12116 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12117 else
12118 tp->mi_mode = MAC_MI_MODE_BASE;
12119
1da177e4 12120 tp->coalesce_mode = 0;
1da177e4
LT		 12121 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12122 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12123 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12124
321d32a0
MC		 12125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12127 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12128
158d7abd
MC		 12129 err = tg3_mdio_init(tp);
12130 if (err)
12131 return err;
1da177e4
LT		 12132
12133 /* Initialize data/descriptor byte/word swapping. */
12134 val = tr32(GRC_MODE);
12135 val &= GRC_MODE_HOST_STACKUP;
12136 tw32(GRC_MODE, val | tp->grc_mode);
12137
12138 tg3_switch_clocks(tp);
12139
12140 /* Clear this out for sanity. */
12141 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12142
12143 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12144 &pci_state_reg);
12145 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12146 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12147 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12148
12149 if (chiprevid == CHIPREV_ID_5701_A0 ||
12150 chiprevid == CHIPREV_ID_5701_B0 ||
12151 chiprevid == CHIPREV_ID_5701_B2 ||
12152 chiprevid == CHIPREV_ID_5701_B5) {
12153 void __iomem *sram_base;
12154
12155 /* Write some dummy words into the SRAM status block
12156 * area, see if it reads back correctly. If the return
12157 * value is bad, force enable the PCIX workaround.
12158 */
12159 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12160
12161 writel(0x00000000, sram_base);
12162 writel(0x00000000, sram_base + 4);
12163 writel(0xffffffff, sram_base + 4);
12164 if (readl(sram_base) != 0x00000000)
12165 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12166 }
12167 }
12168
12169 udelay(50);
12170 tg3_nvram_init(tp);
12171
12172 grc_misc_cfg = tr32(GRC_MISC_CFG);
12173 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12174
1da177e4
LT		 12175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12176 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12177 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12178 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12179
fac9b83e
DM		 12180 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12181 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12182 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12183 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12184 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12185 HOSTCC_MODE_CLRTICK_TXBD);
12186
12187 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12188 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12189 tp->misc_host_ctrl);
12190 }
12191
3bda1258
MC		 12192 /* Preserve the APE MAC_MODE bits */
12193 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12194 tp->mac_mode = tr32(MAC_MODE) |
12195 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12196 else
12197 tp->mac_mode = TG3_DEF_MAC_MODE;
12198
1da177e4
LT		 12199 /* these are limited to 10/100 only */
12200 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12201 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12202 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12203 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12204 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12205 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12206 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12207 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12208 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12209 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12210 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12211 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
b5d3772c 12212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 12213 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12214
12215 err = tg3_phy_probe(tp);
12216 if (err) {
12217 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12218 pci_name(tp->pdev), err);
12219 /* ... but do not return immediately ... */
b02fd9e3 12220 tg3_mdio_fini(tp);
1da177e4
LT		 12221 }
12222
12223 tg3_read_partno(tp);
c4e6575c 12224 tg3_read_fw_ver(tp);
1da177e4
LT		 12225
12226 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12227 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12228 } else {
12229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12230 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12231 else
12232 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12233 }
12234
12235 /* 5700 {AX,BX} chips have a broken status block link
12236 * change bit implementation, so we must use the
12237 * status register in those cases.
12238 */
12239 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12240 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12241 else
12242 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12243
12244 /* The led_ctrl is set during tg3_phy_probe, here we might
12245 * have to force the link status polling mechanism based
12246 * upon subsystem IDs.
12247 */
12248 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12250 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12251 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12252 TG3_FLAG_USE_LINKCHG_REG);
12253 }
12254
12255 /* For all SERDES we poll the MAC status register. */
12256 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12257 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12258 else
12259 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12260
ad829268 12261 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12262 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12263 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12264 tp->rx_offset = 0;
12265
f92905de
MC		 12266 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12267
12268 /* Increment the rx prod index on the rx std ring by at most
12269 * 8 for these chips to workaround hw errata.
12270 */
12271 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12272 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12273 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12274 tp->rx_std_max_post = 8;
12275
8ed5d97e
MC		 12276 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12277 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12278 PCIE_PWR_MGMT_L1_THRESH_MSK;
12279
1da177e4
LT		 12280 return err;
12281}
12282
49b6e95f 12283#ifdef CONFIG_SPARC
1da177e4
LT		 12284static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12285{
12286 struct net_device *dev = tp->dev;
12287 struct pci_dev *pdev = tp->pdev;
49b6e95f 12288 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12289 const unsigned char *addr;
49b6e95f
DM		 12290 int len;
12291
12292 addr = of_get_property(dp, "local-mac-address", &len);
12293 if (addr && len == 6) {
12294 memcpy(dev->dev_addr, addr, 6);
12295 memcpy(dev->perm_addr, dev->dev_addr, 6);
12296 return 0;
1da177e4
LT		 12297 }
12298 return -ENODEV;
12299}
12300
12301static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12302{
12303 struct net_device *dev = tp->dev;
12304
12305 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12306 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12307 return 0;
12308}
12309#endif
12310
12311static int __devinit tg3_get_device_address(struct tg3 *tp)
12312{
12313 struct net_device *dev = tp->dev;
12314 u32 hi, lo, mac_offset;
008652b3 12315 int addr_ok = 0;
1da177e4 12316
49b6e95f 12317#ifdef CONFIG_SPARC
1da177e4
LT		 12318 if (!tg3_get_macaddr_sparc(tp))
12319 return 0;
12320#endif
12321
12322 mac_offset = 0x7c;
f49639e6 12323 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12324 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12325 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12326 mac_offset = 0xcc;
12327 if (tg3_nvram_lock(tp))
12328 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12329 else
12330 tg3_nvram_unlock(tp);
12331 }
b5d3772c
MC		 12332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12333 mac_offset = 0x10;
1da177e4
LT		 12334
12335 /* First try to get it from MAC address mailbox. */
12336 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12337 if ((hi >> 16) == 0x484b) {
12338 dev->dev_addr[0] = (hi >> 8) & 0xff;
12339 dev->dev_addr[1] = (hi >> 0) & 0xff;
12340
12341 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12342 dev->dev_addr[2] = (lo >> 24) & 0xff;
12343 dev->dev_addr[3] = (lo >> 16) & 0xff;
12344 dev->dev_addr[4] = (lo >> 8) & 0xff;
12345 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12346
008652b3
MC		 12347 /* Some old bootcode may report a 0 MAC address in SRAM */
12348 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12349 }
12350 if (!addr_ok) {
12351 /* Next, try NVRAM. */
f49639e6 12352 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
008652b3
MC		 12353 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12354 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12355 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12356 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12357 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12358 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12359 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12360 }
12361 /* Finally just fetch it out of the MAC control regs. */
12362 else {
12363 hi = tr32(MAC_ADDR_0_HIGH);
12364 lo = tr32(MAC_ADDR_0_LOW);
12365
12366 dev->dev_addr[5] = lo & 0xff;
12367 dev->dev_addr[4] = (lo >> 8) & 0xff;
12368 dev->dev_addr[3] = (lo >> 16) & 0xff;
12369 dev->dev_addr[2] = (lo >> 24) & 0xff;
12370 dev->dev_addr[1] = hi & 0xff;
12371 dev->dev_addr[0] = (hi >> 8) & 0xff;
12372 }
1da177e4
LT		 12373 }
12374
12375 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12376#ifdef CONFIG_SPARC
1da177e4
LT		 12377 if (!tg3_get_default_macaddr_sparc(tp))
12378 return 0;
12379#endif
12380 return -EINVAL;
12381 }
2ff43697 12382 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12383 return 0;
12384}
12385
59e6b434
DM		 12386#define BOUNDARY_SINGLE_CACHELINE 1
12387#define BOUNDARY_MULTI_CACHELINE 2
12388
12389static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12390{
12391 int cacheline_size;
12392 u8 byte;
12393 int goal;
12394
12395 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12396 if (byte == 0)
12397 cacheline_size = 1024;
12398 else
12399 cacheline_size = (int) byte * 4;
12400
12401 /* On 5703 and later chips, the boundary bits have no
12402 * effect.
12403 */
12404 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12405 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12406 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12407 goto out;
12408
12409#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12410 goal = BOUNDARY_MULTI_CACHELINE;
12411#else
12412#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12413 goal = BOUNDARY_SINGLE_CACHELINE;
12414#else
12415 goal = 0;
12416#endif
12417#endif
12418
12419 if (!goal)
12420 goto out;
12421
12422 /* PCI controllers on most RISC systems tend to disconnect
12423 * when a device tries to burst across a cache-line boundary.
12424 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12425 *
12426 * Unfortunately, for PCI-E there are only limited
12427 * write-side controls for this, and thus for reads
12428 * we will still get the disconnects. We'll also waste
12429 * these PCI cycles for both read and write for chips
12430 * other than 5700 and 5701 which do not implement the
12431 * boundary bits.
12432 */
12433 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12434 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12435 switch (cacheline_size) {
12436 case 16:
12437 case 32:
12438 case 64:
12439 case 128:
12440 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12441 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12442 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12443 } else {
12444 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12445 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12446 }
12447 break;
12448
12449 case 256:
12450 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12451 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12452 break;
12453
12454 default:
12455 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12456 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12457 break;
855e1111 12458 }
59e6b434
DM		 12459 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12460 switch (cacheline_size) {
12461 case 16:
12462 case 32:
12463 case 64:
12464 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12465 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12466 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12467 break;
12468 }
12469 /* fallthrough */
12470 case 128:
12471 default:
12472 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12473 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12474 break;
855e1111 12475 }
59e6b434
DM		 12476 } else {
12477 switch (cacheline_size) {
12478 case 16:
12479 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12480 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12481 DMA_RWCTRL_WRITE_BNDRY_16);
12482 break;
12483 }
12484 /* fallthrough */
12485 case 32:
12486 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12487 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12488 DMA_RWCTRL_WRITE_BNDRY_32);
12489 break;
12490 }
12491 /* fallthrough */
12492 case 64:
12493 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12494 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12495 DMA_RWCTRL_WRITE_BNDRY_64);
12496 break;
12497 }
12498 /* fallthrough */
12499 case 128:
12500 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12501 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12502 DMA_RWCTRL_WRITE_BNDRY_128);
12503 break;
12504 }
12505 /* fallthrough */
12506 case 256:
12507 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12508 DMA_RWCTRL_WRITE_BNDRY_256);
12509 break;
12510 case 512:
12511 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12512 DMA_RWCTRL_WRITE_BNDRY_512);
12513 break;
12514 case 1024:
12515 default:
12516 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12517 DMA_RWCTRL_WRITE_BNDRY_1024);
12518 break;
855e1111 12519 }
59e6b434
DM		 12520 }
12521
12522out:
12523 return val;
12524}
12525
1da177e4
LT		 12526static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12527{
12528 struct tg3_internal_buffer_desc test_desc;
12529 u32 sram_dma_descs;
12530 int i, ret;
12531
12532 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12533
12534 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12535 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12536 tw32(RDMAC_STATUS, 0);
12537 tw32(WDMAC_STATUS, 0);
12538
12539 tw32(BUFMGR_MODE, 0);
12540 tw32(FTQ_RESET, 0);
12541
12542 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12543 test_desc.addr_lo = buf_dma & 0xffffffff;
12544 test_desc.nic_mbuf = 0x00002100;
12545 test_desc.len = size;
12546
12547 /*
12548 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12549 * the *second* time the tg3 driver was getting loaded after an
12550 * initial scan.
12551 *
12552 * Broadcom tells me:
12553 * ...the DMA engine is connected to the GRC block and a DMA
12554 * reset may affect the GRC block in some unpredictable way...
12555 * The behavior of resets to individual blocks has not been tested.
12556 *
12557 * Broadcom noted the GRC reset will also reset all sub-components.
12558 */
12559 if (to_device) {
12560 test_desc.cqid_sqid = (13 << 8) | 2;
12561
12562 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12563 udelay(40);
12564 } else {
12565 test_desc.cqid_sqid = (16 << 8) | 7;
12566
12567 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12568 udelay(40);
12569 }
12570 test_desc.flags = 0x00000005;
12571
12572 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12573 u32 val;
12574
12575 val = *(((u32 *)&test_desc) + i);
12576 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12577 sram_dma_descs + (i * sizeof(u32)));
12578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12579 }
12580 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12581
12582 if (to_device) {
12583 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12584 } else {
12585 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12586 }
12587
12588 ret = -ENODEV;
12589 for (i = 0; i < 40; i++) {
12590 u32 val;
12591
12592 if (to_device)
12593 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12594 else
12595 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12596 if ((val & 0xffff) == sram_dma_descs) {
12597 ret = 0;
12598 break;
12599 }
12600
12601 udelay(100);
12602 }
12603
12604 return ret;
12605}
12606
ded7340d 12607#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12608
12609static int __devinit tg3_test_dma(struct tg3 *tp)
12610{
12611 dma_addr_t buf_dma;
59e6b434 12612 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12613 int ret;
12614
12615 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12616 if (!buf) {
12617 ret = -ENOMEM;
12618 goto out_nofree;
12619 }
12620
12621 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12622 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12623
59e6b434 12624 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12625
12626 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12627 /* DMA read watermark not used on PCIE */
12628 tp->dma_rwctrl |= 0x00180000;
12629 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12632 tp->dma_rwctrl |= 0x003f0000;
12633 else
12634 tp->dma_rwctrl |= 0x003f000f;
12635 } else {
12636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12638 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12639 u32 read_water = 0x7;
1da177e4 12640
4a29cc2e
MC		 12641 /* If the 5704 is behind the EPB bridge, we can
12642 * do the less restrictive ONE_DMA workaround for
12643 * better performance.
12644 */
12645 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12646 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12647 tp->dma_rwctrl |= 0x8000;
12648 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12649 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12650
49afdeb6
MC		 12651 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12652 read_water = 4;
59e6b434 12653 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12654 tp->dma_rwctrl |=
12655 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12656 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12657 (1 << 23);
4cf78e4f
MC		 12658 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12659 /* 5780 always in PCIX mode */
12660 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12661 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12662 /* 5714 always in PCIX mode */
12663 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12664 } else {
12665 tp->dma_rwctrl |= 0x001b000f;
12666 }
12667 }
12668
12669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12670 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12671 tp->dma_rwctrl &= 0xfffffff0;
12672
12673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12674 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12675 /* Remove this if it causes problems for some boards. */
12676 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12677
12678 /* On 5700/5701 chips, we need to set this bit.
12679 * Otherwise the chip will issue cacheline transactions
12680 * to streamable DMA memory with not all the byte
12681 * enables turned on. This is an error on several
12682 * RISC PCI controllers, in particular sparc64.
12683 *
12684 * On 5703/5704 chips, this bit has been reassigned
12685 * a different meaning. In particular, it is used
12686 * on those chips to enable a PCI-X workaround.
12687 */
12688 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12689 }
12690
12691 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12692
12693#if 0
12694 /* Unneeded, already done by tg3_get_invariants. */
12695 tg3_switch_clocks(tp);
12696#endif
12697
12698 ret = 0;
12699 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12700 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12701 goto out;
12702
59e6b434
DM		 12703 /* It is best to perform DMA test with maximum write burst size
12704 * to expose the 5700/5701 write DMA bug.
12705 */
12706 saved_dma_rwctrl = tp->dma_rwctrl;
12707 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12708 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12709
1da177e4
LT		 12710 while (1) {
12711 u32 *p = buf, i;
12712
12713 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12714 p[i] = i;
12715
12716 /* Send the buffer to the chip. */
12717 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12718 if (ret) {
12719 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12720 break;
12721 }
12722
12723#if 0
12724 /* validate data reached card RAM correctly. */
12725 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12726 u32 val;
12727 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12728 if (le32_to_cpu(val) != p[i]) {
12729 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12730 /* ret = -ENODEV here? */
12731 }
12732 p[i] = 0;
12733 }
12734#endif
12735 /* Now read it back. */
12736 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12737 if (ret) {
12738 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12739
12740 break;
12741 }
12742
12743 /* Verify it. */
12744 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12745 if (p[i] == i)
12746 continue;
12747
59e6b434
DM		 12748 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12749 DMA_RWCTRL_WRITE_BNDRY_16) {
12750 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12751 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12752 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12753 break;
12754 } else {
12755 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12756 ret = -ENODEV;
12757 goto out;
12758 }
12759 }
12760
12761 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12762 /* Success. */
12763 ret = 0;
12764 break;
12765 }
12766 }
59e6b434
DM		 12767 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12768 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12769 static struct pci_device_id dma_wait_state_chipsets[] = {
12770 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12771 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12772 { },
12773 };
12774
59e6b434 12775 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12776 * now look for chipsets that are known to expose the
12777 * DMA bug without failing the test.
59e6b434 12778 */
6d1cfbab
MC		 12779 if (pci_dev_present(dma_wait_state_chipsets)) {
12780 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12781 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12782 }
12783 else
12784 /* Safe to use the calculated DMA boundary. */
12785 tp->dma_rwctrl = saved_dma_rwctrl;
12786
59e6b434
DM		 12787 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12788 }
1da177e4
LT		 12789
12790out:
12791 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12792out_nofree:
12793 return ret;
12794}
12795
12796static void __devinit tg3_init_link_config(struct tg3 *tp)
12797{
12798 tp->link_config.advertising =
12799 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12800 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12801 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12802 ADVERTISED_Autoneg | ADVERTISED_MII);
12803 tp->link_config.speed = SPEED_INVALID;
12804 tp->link_config.duplex = DUPLEX_INVALID;
12805 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12806 tp->link_config.active_speed = SPEED_INVALID;
12807 tp->link_config.active_duplex = DUPLEX_INVALID;
12808 tp->link_config.phy_is_low_power = 0;
12809 tp->link_config.orig_speed = SPEED_INVALID;
12810 tp->link_config.orig_duplex = DUPLEX_INVALID;
12811 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12812}
12813
12814static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12815{
fdfec172
MC		 12816 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12817 tp->bufmgr_config.mbuf_read_dma_low_water =
12818 DEFAULT_MB_RDMA_LOW_WATER_5705;
12819 tp->bufmgr_config.mbuf_mac_rx_low_water =
12820 DEFAULT_MB_MACRX_LOW_WATER_5705;
12821 tp->bufmgr_config.mbuf_high_water =
12822 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12824 tp->bufmgr_config.mbuf_mac_rx_low_water =
12825 DEFAULT_MB_MACRX_LOW_WATER_5906;
12826 tp->bufmgr_config.mbuf_high_water =
12827 DEFAULT_MB_HIGH_WATER_5906;
12828 }
fdfec172
MC		 12829
12830 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12831 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12832 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12833 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12834 tp->bufmgr_config.mbuf_high_water_jumbo =
12835 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12836 } else {
12837 tp->bufmgr_config.mbuf_read_dma_low_water =
12838 DEFAULT_MB_RDMA_LOW_WATER;
12839 tp->bufmgr_config.mbuf_mac_rx_low_water =
12840 DEFAULT_MB_MACRX_LOW_WATER;
12841 tp->bufmgr_config.mbuf_high_water =
12842 DEFAULT_MB_HIGH_WATER;
12843
12844 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12845 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12846 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12847 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12848 tp->bufmgr_config.mbuf_high_water_jumbo =
12849 DEFAULT_MB_HIGH_WATER_JUMBO;
12850 }
1da177e4
LT		 12851
12852 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12853 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12854}
12855
12856static char * __devinit tg3_phy_string(struct tg3 *tp)
12857{
12858 switch (tp->phy_id & PHY_ID_MASK) {
12859 case PHY_ID_BCM5400: return "5400";
12860 case PHY_ID_BCM5401: return "5401";
12861 case PHY_ID_BCM5411: return "5411";
12862 case PHY_ID_BCM5701: return "5701";
12863 case PHY_ID_BCM5703: return "5703";
12864 case PHY_ID_BCM5704: return "5704";
12865 case PHY_ID_BCM5705: return "5705";
12866 case PHY_ID_BCM5750: return "5750";
85e94ced 12867 case PHY_ID_BCM5752: return "5752";
a4e2b347 12868 case PHY_ID_BCM5714: return "5714";
4cf78e4f 12869 case PHY_ID_BCM5780: return "5780";
af36e6b6 12870 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 12871 case PHY_ID_BCM5787: return "5787";
d30cdd28 12872 case PHY_ID_BCM5784: return "5784";
126a3368 12873 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 12874 case PHY_ID_BCM5906: return "5906";
9936bcf6 12875 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 12876 case PHY_ID_BCM8002: return "8002/serdes";
12877 case 0: return "serdes";
12878 default: return "unknown";
855e1111 12879 }
1da177e4
LT		 12880}
12881
f9804ddb
MC		 12882static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12883{
12884 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12885 strcpy(str, "PCI Express");
12886 return str;
12887 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12888 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12889
12890 strcpy(str, "PCIX:");
12891
12892 if ((clock_ctrl == 7) ||
12893 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12894 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12895 strcat(str, "133MHz");
12896 else if (clock_ctrl == 0)
12897 strcat(str, "33MHz");
12898 else if (clock_ctrl == 2)
12899 strcat(str, "50MHz");
12900 else if (clock_ctrl == 4)
12901 strcat(str, "66MHz");
12902 else if (clock_ctrl == 6)
12903 strcat(str, "100MHz");
f9804ddb
MC		 12904 } else {
12905 strcpy(str, "PCI:");
12906 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12907 strcat(str, "66MHz");
12908 else
12909 strcat(str, "33MHz");
12910 }
12911 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12912 strcat(str, ":32-bit");
12913 else
12914 strcat(str, ":64-bit");
12915 return str;
12916}
12917
8c2dc7e1 12918static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 12919{
12920 struct pci_dev *peer;
12921 unsigned int func, devnr = tp->pdev->devfn & ~7;
12922
12923 for (func = 0; func < 8; func++) {
12924 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12925 if (peer && peer != tp->pdev)
12926 break;
12927 pci_dev_put(peer);
12928 }
16fe9d74
MC		 12929 /* 5704 can be configured in single-port mode, set peer to
12930 * tp->pdev in that case.
12931 */
12932 if (!peer) {
12933 peer = tp->pdev;
12934 return peer;
12935 }
1da177e4
LT		 12936
12937 /*
12938 * We don't need to keep the refcount elevated; there's no way
12939 * to remove one half of this device without removing the other
12940 */
12941 pci_dev_put(peer);
12942
12943 return peer;
12944}
12945
15f9850d
DM		 12946static void __devinit tg3_init_coal(struct tg3 *tp)
12947{
12948 struct ethtool_coalesce *ec = &tp->coal;
12949
12950 memset(ec, 0, sizeof(*ec));
12951 ec->cmd = ETHTOOL_GCOALESCE;
12952 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12953 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12954 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12955 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12956 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12957 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12958 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12959 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12960 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12961
12962 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12963 HOSTCC_MODE_CLRTICK_TXBD)) {
12964 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12965 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12966 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12967 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12968 }
d244c892
MC		 12969
12970 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12971 ec->rx_coalesce_usecs_irq = 0;
12972 ec->tx_coalesce_usecs_irq = 0;
12973 ec->stats_block_coalesce_usecs = 0;
12974 }
15f9850d
DM		 12975}
12976
7c7d64b8
SH		 12977static const struct net_device_ops tg3_netdev_ops = {
12978 .ndo_open = tg3_open,
12979 .ndo_stop = tg3_close,
00829823
SH		 12980 .ndo_start_xmit = tg3_start_xmit,
12981 .ndo_get_stats = tg3_get_stats,
12982 .ndo_validate_addr = eth_validate_addr,
12983 .ndo_set_multicast_list = tg3_set_rx_mode,
12984 .ndo_set_mac_address = tg3_set_mac_addr,
12985 .ndo_do_ioctl = tg3_ioctl,
12986 .ndo_tx_timeout = tg3_tx_timeout,
12987 .ndo_change_mtu = tg3_change_mtu,
12988#if TG3_VLAN_TAG_USED
12989 .ndo_vlan_rx_register = tg3_vlan_rx_register,
12990#endif
12991#ifdef CONFIG_NET_POLL_CONTROLLER
12992 .ndo_poll_controller = tg3_poll_controller,
12993#endif
12994};
12995
12996static const struct net_device_ops tg3_netdev_ops_dma_bug = {
12997 .ndo_open = tg3_open,
12998 .ndo_stop = tg3_close,
12999 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13000 .ndo_get_stats = tg3_get_stats,
13001 .ndo_validate_addr = eth_validate_addr,
13002 .ndo_set_multicast_list = tg3_set_rx_mode,
13003 .ndo_set_mac_address = tg3_set_mac_addr,
13004 .ndo_do_ioctl = tg3_ioctl,
13005 .ndo_tx_timeout = tg3_tx_timeout,
13006 .ndo_change_mtu = tg3_change_mtu,
13007#if TG3_VLAN_TAG_USED
13008 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13009#endif
13010#ifdef CONFIG_NET_POLL_CONTROLLER
13011 .ndo_poll_controller = tg3_poll_controller,
13012#endif
13013};
13014
1da177e4
LT		 13015static int __devinit tg3_init_one(struct pci_dev *pdev,
13016 const struct pci_device_id *ent)
13017{
13018 static int tg3_version_printed = 0;
1da177e4
LT		 13019 struct net_device *dev;
13020 struct tg3 *tp;
d6645372 13021 int err, pm_cap;
f9804ddb 13022 char str[40];
72f2afb8 13023 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13024
13025 if (tg3_version_printed++ == 0)
13026 printk(KERN_INFO "%s", version);
13027
13028 err = pci_enable_device(pdev);
13029 if (err) {
13030 printk(KERN_ERR PFX "Cannot enable PCI device, "
13031 "aborting.\n");
13032 return err;
13033 }
13034
1da177e4
LT		 13035 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13036 if (err) {
13037 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13038 "aborting.\n");
13039 goto err_out_disable_pdev;
13040 }
13041
13042 pci_set_master(pdev);
13043
13044 /* Find power-management capability. */
13045 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13046 if (pm_cap == 0) {
13047 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13048 "aborting.\n");
13049 err = -EIO;
13050 goto err_out_free_res;
13051 }
13052
1da177e4
LT		 13053 dev = alloc_etherdev(sizeof(*tp));
13054 if (!dev) {
13055 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13056 err = -ENOMEM;
13057 goto err_out_free_res;
13058 }
13059
1da177e4
LT		 13060 SET_NETDEV_DEV(dev, &pdev->dev);
13061
1da177e4
LT		 13062#if TG3_VLAN_TAG_USED
13063 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13064#endif
13065
13066 tp = netdev_priv(dev);
13067 tp->pdev = pdev;
13068 tp->dev = dev;
13069 tp->pm_cap = pm_cap;
1da177e4
LT		 13070 tp->rx_mode = TG3_DEF_RX_MODE;
13071 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13072
1da177e4
LT		 13073 if (tg3_debug > 0)
13074 tp->msg_enable = tg3_debug;
13075 else
13076 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13077
13078 /* The word/byte swap controls here control register access byte
13079 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13080 * setting below.
13081 */
13082 tp->misc_host_ctrl =
13083 MISC_HOST_CTRL_MASK_PCI_INT |
13084 MISC_HOST_CTRL_WORD_SWAP |
13085 MISC_HOST_CTRL_INDIR_ACCESS |
13086 MISC_HOST_CTRL_PCISTATE_RW;
13087
13088 /* The NONFRM (non-frame) byte/word swap controls take effect
13089 * on descriptor entries, anything which isn't packet data.
13090 *
13091 * The StrongARM chips on the board (one for tx, one for rx)
13092 * are running in big-endian mode.
13093 */
13094 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13095 GRC_MODE_WSWAP_NONFRM_DATA);
13096#ifdef __BIG_ENDIAN
13097 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13098#endif
13099 spin_lock_init(&tp->lock);
1da177e4 13100 spin_lock_init(&tp->indirect_lock);
c4028958 13101 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13102
d5fe488a 13103 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13104 if (!tp->regs) {
1da177e4
LT		 13105 printk(KERN_ERR PFX "Cannot map device registers, "
13106 "aborting.\n");
13107 err = -ENOMEM;
13108 goto err_out_free_dev;
13109 }
13110
13111 tg3_init_link_config(tp);
13112
1da177e4
LT		 13113 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13114 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13115 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13116
bea3348e 13117 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13118 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13119 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13120 dev->irq = pdev->irq;
1da177e4
LT		 13121
13122 err = tg3_get_invariants(tp);
13123 if (err) {
13124 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13125 "aborting.\n");
13126 goto err_out_iounmap;
13127 }
13128
321d32a0 13129 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13131 dev->netdev_ops = &tg3_netdev_ops;
13132 else
13133 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13134
13135
4a29cc2e
MC		 13136 /* The EPB bridge inside 5714, 5715, and 5780 and any
13137 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13138 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13139 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13140 * do DMA address check in tg3_start_xmit().
13141 */
4a29cc2e
MC		 13142 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13143 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13144 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
72f2afb8
MC		 13145 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13146#ifdef CONFIG_HIGHMEM
13147 dma_mask = DMA_64BIT_MASK;
13148#endif
4a29cc2e 13149 } else
72f2afb8
MC		 13150 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13151
13152 /* Configure DMA attributes. */
13153 if (dma_mask > DMA_32BIT_MASK) {
13154 err = pci_set_dma_mask(pdev, dma_mask);
13155 if (!err) {
13156 dev->features |= NETIF_F_HIGHDMA;
13157 err = pci_set_consistent_dma_mask(pdev,
13158 persist_dma_mask);
13159 if (err < 0) {
13160 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13161 "DMA for consistent allocations\n");
13162 goto err_out_iounmap;
13163 }
13164 }
13165 }
13166 if (err || dma_mask == DMA_32BIT_MASK) {
13167 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13168 if (err) {
13169 printk(KERN_ERR PFX "No usable DMA configuration, "
13170 "aborting.\n");
13171 goto err_out_iounmap;
13172 }
13173 }
13174
fdfec172 13175 tg3_init_bufmgr_config(tp);
1da177e4 13176
077f849d 13177 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13178 tp->fw_needed = FIRMWARE_TG3;
077f849d 13179
1da177e4
LT		 13180 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13181 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13182 }
13183 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13184 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13185 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13186 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13187 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13188 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13189 } else {
7f62ad5d 13190 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13192 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13193 else
9e9fd12d 13194 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13195 }
1da177e4 13196
4e3a7aaa
MC		 13197 /* TSO is on by default on chips that support hardware TSO.
13198 * Firmware TSO on older chips gives lower performance, so it
13199 * is off by default, but can be enabled using ethtool.
13200 */
b0026624 13201 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13202 if (dev->features & NETIF_F_IP_CSUM)
13203 dev->features |= NETIF_F_TSO;
13204 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13205 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13206 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13207 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13208 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13209 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13210 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13211 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13212 dev->features |= NETIF_F_TSO_ECN;
b0026624 13213 }
1da177e4 13214
1da177e4
LT		 13215
13216 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13217 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13218 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13219 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13220 tp->rx_pending = 63;
13221 }
13222
1da177e4
LT		 13223 err = tg3_get_device_address(tp);
13224 if (err) {
13225 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13226 "aborting.\n");
077f849d 13227 goto err_out_fw;
1da177e4
LT		 13228 }
13229
c88864df 13230 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13231 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13232 if (!tp->aperegs) {
c88864df
MC		 13233 printk(KERN_ERR PFX "Cannot map APE registers, "
13234 "aborting.\n");
13235 err = -ENOMEM;
077f849d 13236 goto err_out_fw;
c88864df
MC		 13237 }
13238
13239 tg3_ape_lock_init(tp);
13240 }
13241
1da177e4
LT		 13242 /*
13243 * Reset chip in case UNDI or EFI driver did not shutdown
13244 * DMA self test will enable WDMAC and we'll see (spurious)
13245 * pending DMA on the PCI bus at that point.
13246 */
13247 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13248 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13249 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13250 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13251 }
13252
13253 err = tg3_test_dma(tp);
13254 if (err) {
13255 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13256 goto err_out_apeunmap;
1da177e4
LT		 13257 }
13258
1da177e4
LT		 13259 /* flow control autonegotiation is default behavior */
13260 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13261 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13262
15f9850d
DM		 13263 tg3_init_coal(tp);
13264
c49a1561
MC		 13265 pci_set_drvdata(pdev, dev);
13266
1da177e4
LT		 13267 err = register_netdev(dev);
13268 if (err) {
13269 printk(KERN_ERR PFX "Cannot register net device, "
13270 "aborting.\n");
0d3031d9 13271 goto err_out_apeunmap;
1da177e4
LT		 13272 }
13273
df59c940 13274 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13275 dev->name,
13276 tp->board_part_number,
13277 tp->pci_chip_rev_id,
f9804ddb 13278 tg3_bus_string(tp, str),
e174961c 13279 dev->dev_addr);
1da177e4 13280
df59c940
MC		 13281 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13282 printk(KERN_INFO
13283 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13284 tp->dev->name,
13285 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13286 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13287 else
13288 printk(KERN_INFO
13289 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13290 tp->dev->name, tg3_phy_string(tp),
13291 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13292 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13293 "10/100/1000Base-T")),
13294 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13295
13296 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13297 dev->name,
13298 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13299 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13300 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13301 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13302 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13303 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13304 dev->name, tp->dma_rwctrl,
13305 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13306 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
1da177e4
LT		 13307
13308 return 0;
13309
0d3031d9
MC		 13310err_out_apeunmap:
13311 if (tp->aperegs) {
13312 iounmap(tp->aperegs);
13313 tp->aperegs = NULL;
13314 }
13315
077f849d
JSR		 13316err_out_fw:
13317 if (tp->fw)
13318 release_firmware(tp->fw);
13319
1da177e4 13320err_out_iounmap:
6892914f
MC		 13321 if (tp->regs) {
13322 iounmap(tp->regs);
22abe310 13323 tp->regs = NULL;
6892914f 13324 }
1da177e4
LT		 13325
13326err_out_free_dev:
13327 free_netdev(dev);
13328
13329err_out_free_res:
13330 pci_release_regions(pdev);
13331
13332err_out_disable_pdev:
13333 pci_disable_device(pdev);
13334 pci_set_drvdata(pdev, NULL);
13335 return err;
13336}
13337
13338static void __devexit tg3_remove_one(struct pci_dev *pdev)
13339{
13340 struct net_device *dev = pci_get_drvdata(pdev);
13341
13342 if (dev) {
13343 struct tg3 *tp = netdev_priv(dev);
13344
077f849d
JSR		 13345 if (tp->fw)
13346 release_firmware(tp->fw);
13347
7faa006f 13348 flush_scheduled_work();
158d7abd 13349
b02fd9e3
MC		 13350 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13351 tg3_phy_fini(tp);
158d7abd 13352 tg3_mdio_fini(tp);
b02fd9e3 13353 }
158d7abd 13354
1da177e4 13355 unregister_netdev(dev);
0d3031d9
MC		 13356 if (tp->aperegs) {
13357 iounmap(tp->aperegs);
13358 tp->aperegs = NULL;
13359 }
6892914f
MC		 13360 if (tp->regs) {
13361 iounmap(tp->regs);
22abe310 13362 tp->regs = NULL;
6892914f 13363 }
1da177e4
LT		 13364 free_netdev(dev);
13365 pci_release_regions(pdev);
13366 pci_disable_device(pdev);
13367 pci_set_drvdata(pdev, NULL);
13368 }
13369}
13370
13371static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13372{
13373 struct net_device *dev = pci_get_drvdata(pdev);
13374 struct tg3 *tp = netdev_priv(dev);
12dac075 13375 pci_power_t target_state;
1da177e4
LT		 13376 int err;
13377
3e0c95fd
MC		 13378 /* PCI register 4 needs to be saved whether netif_running() or not.
13379 * MSI address and data need to be saved if using MSI and
13380 * netif_running().
13381 */
13382 pci_save_state(pdev);
13383
1da177e4
LT		 13384 if (!netif_running(dev))
13385 return 0;
13386
7faa006f 13387 flush_scheduled_work();
b02fd9e3 13388 tg3_phy_stop(tp);
1da177e4
LT		 13389 tg3_netif_stop(tp);
13390
13391 del_timer_sync(&tp->timer);
13392
f47c11ee 13393 tg3_full_lock(tp, 1);
1da177e4 13394 tg3_disable_ints(tp);
f47c11ee 13395 tg3_full_unlock(tp);
1da177e4
LT		 13396
13397 netif_device_detach(dev);
13398
f47c11ee 13399 tg3_full_lock(tp, 0);
944d980e 13400 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13401 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13402 tg3_full_unlock(tp);
1da177e4 13403
12dac075
RW		 13404 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13405
13406 err = tg3_set_power_state(tp, target_state);
1da177e4 13407 if (err) {
b02fd9e3
MC		 13408 int err2;
13409
f47c11ee 13410 tg3_full_lock(tp, 0);
1da177e4 13411
6a9eba15 13412 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13413 err2 = tg3_restart_hw(tp, 1);
13414 if (err2)
b9ec6c1b 13415 goto out;
1da177e4
LT		 13416
13417 tp->timer.expires = jiffies + tp->timer_offset;
13418 add_timer(&tp->timer);
13419
13420 netif_device_attach(dev);
13421 tg3_netif_start(tp);
13422
b9ec6c1b 13423out:
f47c11ee 13424 tg3_full_unlock(tp);
b02fd9e3
MC		 13425
13426 if (!err2)
13427 tg3_phy_start(tp);
1da177e4
LT		 13428 }
13429
13430 return err;
13431}
13432
13433static int tg3_resume(struct pci_dev *pdev)
13434{
13435 struct net_device *dev = pci_get_drvdata(pdev);
13436 struct tg3 *tp = netdev_priv(dev);
13437 int err;
13438
3e0c95fd
MC		 13439 pci_restore_state(tp->pdev);
13440
1da177e4
LT		 13441 if (!netif_running(dev))
13442 return 0;
13443
bc1c7567 13444 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13445 if (err)
13446 return err;
13447
13448 netif_device_attach(dev);
13449
f47c11ee 13450 tg3_full_lock(tp, 0);
1da177e4 13451
6a9eba15 13452 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13453 err = tg3_restart_hw(tp, 1);
13454 if (err)
13455 goto out;
1da177e4
LT		 13456
13457 tp->timer.expires = jiffies + tp->timer_offset;
13458 add_timer(&tp->timer);
13459
1da177e4
LT		 13460 tg3_netif_start(tp);
13461
b9ec6c1b 13462out:
f47c11ee 13463 tg3_full_unlock(tp);
1da177e4 13464
b02fd9e3
MC		 13465 if (!err)
13466 tg3_phy_start(tp);
13467
b9ec6c1b 13468 return err;
1da177e4
LT		 13469}
13470
13471static struct pci_driver tg3_driver = {
13472 .name = DRV_MODULE_NAME,
13473 .id_table = tg3_pci_tbl,
13474 .probe = tg3_init_one,
13475 .remove = __devexit_p(tg3_remove_one),
13476 .suspend = tg3_suspend,
13477 .resume = tg3_resume
13478};
13479
13480static int __init tg3_init(void)
13481{
29917620 13482 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13483}
13484
13485static void __exit tg3_cleanup(void)
13486{
13487 pci_unregister_driver(&tg3_driver);
13488}
13489
13490module_init(tg3_init);
13491module_exit(tg3_cleanup);
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