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tg3: Move napi to per-int struct
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
f656f398
MC		 71#define DRV_MODULE_VERSION "3.100"
72#define DRV_MODULE_RELDATE "August 25, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
79ed5ac7
MC		 120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
1da177e4 122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 123 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
287be12e
MC		 128#define TG3_DMA_BYTE_ENAB 64
129
130#define TG3_RX_STD_DMA_SZ 1536
131#define TG3_RX_JMB_DMA_SZ 9046
132
133#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
134
135#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 137
138/* minimum number of free TX descriptors required to wake up TX process */
42952231 139#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 140
ad829268
MC		 141#define TG3_RAW_IP_ALIGN 2
142
1da177e4
LT		 143/* number of ETHTOOL_GSTATS u64's */
144#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
145
4cafd3f5
MC		 146#define TG3_NUM_TEST 6
147
077f849d
JSR		 148#define FIRMWARE_TG3 "tigon/tg3.bin"
149#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
151
1da177e4
LT		 152static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
154
155MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157MODULE_LICENSE("GPL");
158MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 159MODULE_FIRMWARE(FIRMWARE_TG3);
160MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
162
1da177e4
LT		 163
164static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165module_param(tg3_debug, int, 0);
166MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
167
168static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
242 {}
1da177e4
LT		 243};
244
245MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
50da859d 247static const struct {
1da177e4
LT		 248 const char string[ETH_GSTRING_LEN];
249} ethtool_stats_keys[TG3_NUM_STATS] = {
250 { "rx_octets" },
251 { "rx_fragments" },
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
255 { "rx_fcs_errors" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
262 { "rx_jabbers" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
276
277 { "tx_octets" },
278 { "tx_collisions" },
279
280 { "tx_xon_sent" },
281 { "tx_xoff_sent" },
282 { "tx_flow_control" },
283 { "tx_mac_errors" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
286 { "tx_deferred" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
307 { "tx_discards" },
308 { "tx_errors" },
309
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
312 { "rxbds_empty" },
313 { "rx_discards" },
314 { "rx_errors" },
315 { "rx_threshold_hit" },
316
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
320
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
323 { "nic_irqs" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
326};
327
50da859d 328static const struct {
4cafd3f5
MC		 329 const char string[ETH_GSTRING_LEN];
330} ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
337};
338
b401e9e2
MC		 339static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
340{
341 writel(val, tp->regs + off);
342}
343
344static u32 tg3_read32(struct tg3 *tp, u32 off)
345{
6aa20a22 346 return (readl(tp->regs + off));
b401e9e2
MC		 347}
348
0d3031d9
MC		 349static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
350{
351 writel(val, tp->aperegs + off);
352}
353
354static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
355{
356 return (readl(tp->aperegs + off));
357}
358
1da177e4
LT		 359static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
360{
6892914f
MC		 361 unsigned long flags;
362
363 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 364 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
365 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 366 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 367}
368
369static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
370{
371 writel(val, tp->regs + off);
372 readl(tp->regs + off);
1da177e4
LT		 373}
374
6892914f 375static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 376{
6892914f
MC		 377 unsigned long flags;
378 u32 val;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
384 return val;
385}
386
387static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
388{
389 unsigned long flags;
390
391 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
393 TG3_64BIT_REG_LOW, val);
394 return;
395 }
396 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
398 TG3_64BIT_REG_LOW, val);
399 return;
1da177e4 400 }
6892914f
MC		 401
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
409 */
410 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
411 (val == 0x1)) {
412 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
413 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
414 }
415}
416
417static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
418{
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427}
428
b401e9e2
MC		 429/* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
433 */
434static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 435{
b401e9e2
MC		 436 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
437 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
438 /* Non-posted methods */
439 tp->write32(tp, off, val);
440 else {
441 /* Posted method */
442 tg3_write32(tp, off, val);
443 if (usec_wait)
444 udelay(usec_wait);
445 tp->read32(tp, off);
446 }
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
449 */
450 if (usec_wait)
451 udelay(usec_wait);
1da177e4
LT		 452}
453
09ee929c
MC		 454static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
455{
456 tp->write32_mbox(tp, off, val);
6892914f
MC		 457 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
458 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
459 tp->read32_mbox(tp, off);
09ee929c
MC		 460}
461
20094930 462static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 463{
464 void __iomem *mbox = tp->regs + off;
465 writel(val, mbox);
466 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
467 writel(val, mbox);
468 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
469 readl(mbox);
470}
471
b5d3772c
MC		 472static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
473{
474 return (readl(tp->regs + off + GRCMBOX_BASE));
475}
476
477static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
478{
479 writel(val, tp->regs + off + GRCMBOX_BASE);
480}
481
20094930 482#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 483#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 484#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 486#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 487
488#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 489#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 491#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 492
493static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
494{
6892914f
MC		 495 unsigned long flags;
496
b5d3772c
MC		 497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
498 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
499 return;
500
6892914f 501 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 505
bbadf503
MC		 506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508 } else {
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 511
bbadf503
MC		 512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514 }
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 516}
517
1da177e4
LT		 518static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
519{
6892914f
MC		 520 unsigned long flags;
521
b5d3772c
MC		 522 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
523 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
524 *val = 0;
525 return;
526 }
527
6892914f 528 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 529 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
530 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
531 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 532
bbadf503
MC		 533 /* Always leave this as zero. */
534 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
535 } else {
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
537 *val = tr32(TG3PCI_MEM_WIN_DATA);
538
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
541 }
6892914f 542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 543}
544
0d3031d9
MC		 545static void tg3_ape_lock_init(struct tg3 *tp)
546{
547 int i;
548
549 /* Make sure the driver hasn't any stale locks. */
550 for (i = 0; i < 8; i++)
551 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
552 APE_LOCK_GRANT_DRIVER);
553}
554
555static int tg3_ape_lock(struct tg3 *tp, int locknum)
556{
557 int i, off;
558 int ret = 0;
559 u32 status;
560
561 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
562 return 0;
563
564 switch (locknum) {
77b483f1 565 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 566 case TG3_APE_LOCK_MEM:
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 off = 4 * locknum;
573
574 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
575
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i = 0; i < 100; i++) {
578 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
579 if (status == APE_LOCK_GRANT_DRIVER)
580 break;
581 udelay(10);
582 }
583
584 if (status != APE_LOCK_GRANT_DRIVER) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
587 APE_LOCK_GRANT_DRIVER);
588
589 ret = -EBUSY;
590 }
591
592 return ret;
593}
594
595static void tg3_ape_unlock(struct tg3 *tp, int locknum)
596{
597 int off;
598
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
600 return;
601
602 switch (locknum) {
77b483f1 603 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 604 case TG3_APE_LOCK_MEM:
605 break;
606 default:
607 return;
608 }
609
610 off = 4 * locknum;
611 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
612}
613
1da177e4
LT		 614static void tg3_disable_ints(struct tg3 *tp)
615{
616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 618 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 619}
620
621static inline void tg3_cond_int(struct tg3 *tp)
622{
38f3843e
MC		 623 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
624 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 625 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 626 else
627 tw32(HOSTCC_MODE, tp->coalesce_mode |
628 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 629}
630
631static void tg3_enable_ints(struct tg3 *tp)
632{
bbe832c0
MC		 633 tp->irq_sync = 0;
634 wmb();
635
1da177e4
LT		 636 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 638 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
639 (tp->last_tag << 24));
fcfa0a32
MC		 640 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
641 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
642 (tp->last_tag << 24));
1da177e4
LT		 643 tg3_cond_int(tp);
644}
645
04237ddd
MC		 646static inline unsigned int tg3_has_work(struct tg3 *tp)
647{
648 struct tg3_hw_status *sblk = tp->hw_status;
649 unsigned int work_exists = 0;
650
651 /* check for phy events */
652 if (!(tp->tg3_flags &
653 (TG3_FLAG_USE_LINKCHG_REG |
654 TG3_FLAG_POLL_SERDES))) {
655 if (sblk->status & SD_STATUS_LINK_CHG)
656 work_exists = 1;
657 }
658 /* check for RX/TX work to do */
659 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
660 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
661 work_exists = 1;
662
663 return work_exists;
664}
665
1da177e4 666/* tg3_restart_ints
04237ddd
MC		 667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
6aa20a22 669 * which reenables interrupts
1da177e4
LT		 670 */
671static void tg3_restart_ints(struct tg3 *tp)
672{
fac9b83e
DM		 673 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
674 tp->last_tag << 24);
1da177e4
LT		 675 mmiowb();
676
fac9b83e
DM		 677 /* When doing tagged status, this work check is unnecessary.
678 * The last_tag we write above tells the chip which piece of
679 * work we've completed.
680 */
681 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
682 tg3_has_work(tp))
04237ddd
MC		 683 tw32(HOSTCC_MODE, tp->coalesce_mode |
684 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 685}
686
687static inline void tg3_netif_stop(struct tg3 *tp)
688{
bbe832c0 689 tp->dev->trans_start = jiffies; /* prevent tx timeout */
8ef0442f 690 napi_disable(&tp->napi[0].napi);
1da177e4
LT		 691 netif_tx_disable(tp->dev);
692}
693
694static inline void tg3_netif_start(struct tg3 *tp)
695{
696 netif_wake_queue(tp->dev);
697 /* NOTE: unconditional netif_wake_queue is only appropriate
698 * so long as all callers are assured to have free tx slots
699 * (such as after tg3_init_hw)
700 */
8ef0442f 701 napi_enable(&tp->napi[0].napi);
f47c11ee
DM		 702 tp->hw_status->status |= SD_STATUS_UPDATED;
703 tg3_enable_ints(tp);
1da177e4
LT		 704}
705
706static void tg3_switch_clocks(struct tg3 *tp)
707{
708 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
709 u32 orig_clock_ctrl;
710
795d01c5
MC		 711 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
712 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 713 return;
714
1da177e4
LT		 715 orig_clock_ctrl = clock_ctrl;
716 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
717 CLOCK_CTRL_CLKRUN_OENABLE |
718 0x1f);
719 tp->pci_clock_ctrl = clock_ctrl;
720
721 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
722 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 725 }
726 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 727 tw32_wait_f(TG3PCI_CLOCK_CTRL,
728 clock_ctrl |
729 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
730 40);
731 tw32_wait_f(TG3PCI_CLOCK_CTRL,
732 clock_ctrl | (CLOCK_CTRL_ALTCLK),
733 40);
1da177e4 734 }
b401e9e2 735 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 736}
737
738#define PHY_BUSY_LOOPS 5000
739
740static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
741{
742 u32 frame_val;
743 unsigned int loops;
744 int ret;
745
746 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
747 tw32_f(MAC_MI_MODE,
748 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
749 udelay(80);
750 }
751
752 *val = 0x0;
753
754 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
755 MI_COM_PHY_ADDR_MASK);
756 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
757 MI_COM_REG_ADDR_MASK);
758 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 759
1da177e4
LT		 760 tw32_f(MAC_MI_COM, frame_val);
761
762 loops = PHY_BUSY_LOOPS;
763 while (loops != 0) {
764 udelay(10);
765 frame_val = tr32(MAC_MI_COM);
766
767 if ((frame_val & MI_COM_BUSY) == 0) {
768 udelay(5);
769 frame_val = tr32(MAC_MI_COM);
770 break;
771 }
772 loops -= 1;
773 }
774
775 ret = -EBUSY;
776 if (loops != 0) {
777 *val = frame_val & MI_COM_DATA_MASK;
778 ret = 0;
779 }
780
781 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
782 tw32_f(MAC_MI_MODE, tp->mi_mode);
783 udelay(80);
784 }
785
786 return ret;
787}
788
789static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
790{
791 u32 frame_val;
792 unsigned int loops;
793 int ret;
794
7f97a4bd 795 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 796 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
797 return 0;
798
1da177e4
LT		 799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE,
801 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802 udelay(80);
803 }
804
805 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
806 MI_COM_PHY_ADDR_MASK);
807 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
808 MI_COM_REG_ADDR_MASK);
809 frame_val |= (val & MI_COM_DATA_MASK);
810 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 811
1da177e4
LT		 812 tw32_f(MAC_MI_COM, frame_val);
813
814 loops = PHY_BUSY_LOOPS;
815 while (loops != 0) {
816 udelay(10);
817 frame_val = tr32(MAC_MI_COM);
818 if ((frame_val & MI_COM_BUSY) == 0) {
819 udelay(5);
820 frame_val = tr32(MAC_MI_COM);
821 break;
822 }
823 loops -= 1;
824 }
825
826 ret = -EBUSY;
827 if (loops != 0)
828 ret = 0;
829
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE, tp->mi_mode);
832 udelay(80);
833 }
834
835 return ret;
836}
837
95e2869a
MC		 838static int tg3_bmcr_reset(struct tg3 *tp)
839{
840 u32 phy_control;
841 int limit, err;
842
843 /* OK, reset it, and poll the BMCR_RESET bit until it
844 * clears or we time out.
845 */
846 phy_control = BMCR_RESET;
847 err = tg3_writephy(tp, MII_BMCR, phy_control);
848 if (err != 0)
849 return -EBUSY;
850
851 limit = 5000;
852 while (limit--) {
853 err = tg3_readphy(tp, MII_BMCR, &phy_control);
854 if (err != 0)
855 return -EBUSY;
856
857 if ((phy_control & BMCR_RESET) == 0) {
858 udelay(40);
859 break;
860 }
861 udelay(10);
862 }
d4675b52 863 if (limit < 0)
95e2869a
MC		 864 return -EBUSY;
865
866 return 0;
867}
868
158d7abd
MC		 869static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
870{
3d16543d 871 struct tg3 *tp = bp->priv;
158d7abd
MC		 872 u32 val;
873
874 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
875 return -EAGAIN;
876
877 if (tg3_readphy(tp, reg, &val))
878 return -EIO;
879
880 return val;
881}
882
883static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
884{
3d16543d 885 struct tg3 *tp = bp->priv;
158d7abd
MC		 886
887 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
888 return -EAGAIN;
889
890 if (tg3_writephy(tp, reg, val))
891 return -EIO;
892
893 return 0;
894}
895
896static int tg3_mdio_reset(struct mii_bus *bp)
897{
898 return 0;
899}
900
9c61d6bc 901static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 902{
903 u32 val;
fcb389df 904 struct phy_device *phydev;
a9daf367 905
fcb389df
MC		 906 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
907 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
908 case TG3_PHY_ID_BCM50610:
909 val = MAC_PHYCFG2_50610_LED_MODES;
910 break;
911 case TG3_PHY_ID_BCMAC131:
912 val = MAC_PHYCFG2_AC131_LED_MODES;
913 break;
914 case TG3_PHY_ID_RTL8211C:
915 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
916 break;
917 case TG3_PHY_ID_RTL8201E:
918 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
919 break;
920 default:
a9daf367 921 return;
fcb389df
MC		 922 }
923
924 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
925 tw32(MAC_PHYCFG2, val);
926
927 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 928 val &= ~(MAC_PHYCFG1_RGMII_INT |
929 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
930 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 931 tw32(MAC_PHYCFG1, val);
932
933 return;
934 }
935
936 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
937 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
938 MAC_PHYCFG2_FMODE_MASK_MASK |
939 MAC_PHYCFG2_GMODE_MASK_MASK |
940 MAC_PHYCFG2_ACT_MASK_MASK |
941 MAC_PHYCFG2_QUAL_MASK_MASK |
942 MAC_PHYCFG2_INBAND_ENABLE;
943
944 tw32(MAC_PHYCFG2, val);
a9daf367 945
bb85fbb6
MC		 946 val = tr32(MAC_PHYCFG1);
947 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
948 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
949 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 950 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
951 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
952 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
953 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
954 }
bb85fbb6
MC		 955 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
956 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
957 tw32(MAC_PHYCFG1, val);
a9daf367 958
a9daf367
MC		 959 val = tr32(MAC_EXT_RGMII_MODE);
960 val &= ~(MAC_RGMII_MODE_RX_INT_B |
961 MAC_RGMII_MODE_RX_QUALITY |
962 MAC_RGMII_MODE_RX_ACTIVITY |
963 MAC_RGMII_MODE_RX_ENG_DET |
964 MAC_RGMII_MODE_TX_ENABLE |
965 MAC_RGMII_MODE_TX_LOWPWR |
966 MAC_RGMII_MODE_TX_RESET);
fcb389df 967 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 968 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
969 val |= MAC_RGMII_MODE_RX_INT_B |
970 MAC_RGMII_MODE_RX_QUALITY |
971 MAC_RGMII_MODE_RX_ACTIVITY |
972 MAC_RGMII_MODE_RX_ENG_DET;
973 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
974 val |= MAC_RGMII_MODE_TX_ENABLE |
975 MAC_RGMII_MODE_TX_LOWPWR |
976 MAC_RGMII_MODE_TX_RESET;
977 }
978 tw32(MAC_EXT_RGMII_MODE, val);
979}
980
158d7abd
MC		 981static void tg3_mdio_start(struct tg3 *tp)
982{
983 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 984 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 985 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 986 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 987 }
988
989 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
990 tw32_f(MAC_MI_MODE, tp->mi_mode);
991 udelay(80);
a9daf367 992
9c61d6bc
MC		 993 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
995 tg3_mdio_config_5785(tp);
158d7abd
MC		 996}
997
998static void tg3_mdio_stop(struct tg3 *tp)
999{
1000 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 1001 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 1002 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 1003 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 1004 }
1005}
1006
1007static int tg3_mdio_init(struct tg3 *tp)
1008{
1009 int i;
1010 u32 reg;
a9daf367 1011 struct phy_device *phydev;
158d7abd
MC		 1012
1013 tg3_mdio_start(tp);
1014
1015 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1016 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1017 return 0;
1018
298cf9be
LB		 1019 tp->mdio_bus = mdiobus_alloc();
1020 if (tp->mdio_bus == NULL)
1021 return -ENOMEM;
158d7abd 1022
298cf9be
LB		 1023 tp->mdio_bus->name = "tg3 mdio bus";
1024 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1025 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1026 tp->mdio_bus->priv = tp;
1027 tp->mdio_bus->parent = &tp->pdev->dev;
1028 tp->mdio_bus->read = &tg3_mdio_read;
1029 tp->mdio_bus->write = &tg3_mdio_write;
1030 tp->mdio_bus->reset = &tg3_mdio_reset;
1031 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1032 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1033
1034 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1035 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1036
1037 /* The bus registration will look for all the PHYs on the mdio bus.
1038 * Unfortunately, it does not ensure the PHY is powered up before
1039 * accessing the PHY ID registers. A chip reset is the
1040 * quickest way to bring the device back to an operational state..
1041 */
1042 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1043 tg3_bmcr_reset(tp);
1044
298cf9be 1045 i = mdiobus_register(tp->mdio_bus);
a9daf367 1046 if (i) {
158d7abd
MC		 1047 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1048 tp->dev->name, i);
9c61d6bc 1049 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1050 return i;
1051 }
158d7abd 1052
298cf9be 1053 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1054
9c61d6bc
MC		 1055 if (!phydev || !phydev->drv) {
1056 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1057 mdiobus_unregister(tp->mdio_bus);
1058 mdiobus_free(tp->mdio_bus);
1059 return -ENODEV;
1060 }
1061
1062 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1063 case TG3_PHY_ID_BCM57780:
1064 phydev->interface = PHY_INTERFACE_MODE_GMII;
1065 break;
a9daf367 1066 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1067 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1068 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1069 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1070 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1071 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1072 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1073 /* fallthru */
1074 case TG3_PHY_ID_RTL8211C:
1075 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1076 break;
fcb389df 1077 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1078 case TG3_PHY_ID_BCMAC131:
1079 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1080 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1081 break;
1082 }
1083
9c61d6bc
MC		 1084 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1085
1086 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1087 tg3_mdio_config_5785(tp);
a9daf367
MC		 1088
1089 return 0;
158d7abd
MC		 1090}
1091
1092static void tg3_mdio_fini(struct tg3 *tp)
1093{
1094 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1095 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1096 mdiobus_unregister(tp->mdio_bus);
1097 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1098 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1099 }
1100}
1101
4ba526ce
MC		 1102/* tp->lock is held. */
1103static inline void tg3_generate_fw_event(struct tg3 *tp)
1104{
1105 u32 val;
1106
1107 val = tr32(GRC_RX_CPU_EVENT);
1108 val |= GRC_RX_CPU_DRIVER_EVENT;
1109 tw32_f(GRC_RX_CPU_EVENT, val);
1110
1111 tp->last_event_jiffies = jiffies;
1112}
1113
1114#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1115
95e2869a
MC		 1116/* tp->lock is held. */
1117static void tg3_wait_for_event_ack(struct tg3 *tp)
1118{
1119 int i;
4ba526ce
MC		 1120 unsigned int delay_cnt;
1121 long time_remain;
1122
1123 /* If enough time has passed, no wait is necessary. */
1124 time_remain = (long)(tp->last_event_jiffies + 1 +
1125 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1126 (long)jiffies;
1127 if (time_remain < 0)
1128 return;
1129
1130 /* Check if we can shorten the wait time. */
1131 delay_cnt = jiffies_to_usecs(time_remain);
1132 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1133 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1134 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1135
4ba526ce 1136 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1137 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1138 break;
4ba526ce 1139 udelay(8);
95e2869a
MC		 1140 }
1141}
1142
1143/* tp->lock is held. */
1144static void tg3_ump_link_report(struct tg3 *tp)
1145{
1146 u32 reg;
1147 u32 val;
1148
1149 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1150 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1151 return;
1152
1153 tg3_wait_for_event_ack(tp);
1154
1155 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1156
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1158
1159 val = 0;
1160 if (!tg3_readphy(tp, MII_BMCR, &reg))
1161 val = reg << 16;
1162 if (!tg3_readphy(tp, MII_BMSR, &reg))
1163 val |= (reg & 0xffff);
1164 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1165
1166 val = 0;
1167 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1168 val = reg << 16;
1169 if (!tg3_readphy(tp, MII_LPA, &reg))
1170 val |= (reg & 0xffff);
1171 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1172
1173 val = 0;
1174 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1175 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1176 val = reg << 16;
1177 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1178 val |= (reg & 0xffff);
1179 }
1180 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1181
1182 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1183 val = reg << 16;
1184 else
1185 val = 0;
1186 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1187
4ba526ce 1188 tg3_generate_fw_event(tp);
95e2869a
MC		 1189}
1190
1191static void tg3_link_report(struct tg3 *tp)
1192{
1193 if (!netif_carrier_ok(tp->dev)) {
1194 if (netif_msg_link(tp))
1195 printk(KERN_INFO PFX "%s: Link is down.\n",
1196 tp->dev->name);
1197 tg3_ump_link_report(tp);
1198 } else if (netif_msg_link(tp)) {
1199 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1200 tp->dev->name,
1201 (tp->link_config.active_speed == SPEED_1000 ?
1202 1000 :
1203 (tp->link_config.active_speed == SPEED_100 ?
1204 100 : 10)),
1205 (tp->link_config.active_duplex == DUPLEX_FULL ?
1206 "full" : "half"));
1207
1208 printk(KERN_INFO PFX
1209 "%s: Flow control is %s for TX and %s for RX.\n",
1210 tp->dev->name,
e18ce346 1211 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1212 "on" : "off",
e18ce346 1213 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1214 "on" : "off");
1215 tg3_ump_link_report(tp);
1216 }
1217}
1218
1219static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1220{
1221 u16 miireg;
1222
e18ce346 1223 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1224 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1225 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1226 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1228 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1229 else
1230 miireg = 0;
1231
1232 return miireg;
1233}
1234
1235static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1236{
1237 u16 miireg;
1238
e18ce346 1239 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1240 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1241 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1242 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1243 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1244 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1245 else
1246 miireg = 0;
1247
1248 return miireg;
1249}
1250
95e2869a
MC		 1251static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1252{
1253 u8 cap = 0;
1254
1255 if (lcladv & ADVERTISE_1000XPAUSE) {
1256 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1257 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1258 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1259 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1260 cap = FLOW_CTRL_RX;
95e2869a
MC		 1261 } else {
1262 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1263 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1264 }
1265 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1266 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1267 cap = FLOW_CTRL_TX;
95e2869a
MC		 1268 }
1269
1270 return cap;
1271}
1272
f51f3562 1273static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1274{
b02fd9e3 1275 u8 autoneg;
f51f3562 1276 u8 flowctrl = 0;
95e2869a
MC		 1277 u32 old_rx_mode = tp->rx_mode;
1278 u32 old_tx_mode = tp->tx_mode;
1279
b02fd9e3 1280 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1281 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1282 else
1283 autoneg = tp->link_config.autoneg;
1284
1285 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1286 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1287 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1288 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1289 else
bc02ff95 1290 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1291 } else
1292 flowctrl = tp->link_config.flowctrl;
95e2869a 1293
f51f3562 1294 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1295
e18ce346 1296 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1297 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1298 else
1299 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1300
f51f3562 1301 if (old_rx_mode != tp->rx_mode)
95e2869a 1302 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1303
e18ce346 1304 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1305 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1306 else
1307 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1308
f51f3562 1309 if (old_tx_mode != tp->tx_mode)
95e2869a 1310 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1311}
1312
b02fd9e3
MC		 1313static void tg3_adjust_link(struct net_device *dev)
1314{
1315 u8 oldflowctrl, linkmesg = 0;
1316 u32 mac_mode, lcl_adv, rmt_adv;
1317 struct tg3 *tp = netdev_priv(dev);
298cf9be 1318 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1319
1320 spin_lock(&tp->lock);
1321
1322 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1323 MAC_MODE_HALF_DUPLEX);
1324
1325 oldflowctrl = tp->link_config.active_flowctrl;
1326
1327 if (phydev->link) {
1328 lcl_adv = 0;
1329 rmt_adv = 0;
1330
1331 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1332 mac_mode |= MAC_MODE_PORT_MODE_MII;
1333 else
1334 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1335
1336 if (phydev->duplex == DUPLEX_HALF)
1337 mac_mode |= MAC_MODE_HALF_DUPLEX;
1338 else {
1339 lcl_adv = tg3_advert_flowctrl_1000T(
1340 tp->link_config.flowctrl);
1341
1342 if (phydev->pause)
1343 rmt_adv = LPA_PAUSE_CAP;
1344 if (phydev->asym_pause)
1345 rmt_adv |= LPA_PAUSE_ASYM;
1346 }
1347
1348 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1349 } else
1350 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1351
1352 if (mac_mode != tp->mac_mode) {
1353 tp->mac_mode = mac_mode;
1354 tw32_f(MAC_MODE, tp->mac_mode);
1355 udelay(40);
1356 }
1357
fcb389df
MC		 1358 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1359 if (phydev->speed == SPEED_10)
1360 tw32(MAC_MI_STAT,
1361 MAC_MI_STAT_10MBPS_MODE |
1362 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1363 else
1364 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1365 }
1366
b02fd9e3
MC		 1367 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1368 tw32(MAC_TX_LENGTHS,
1369 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1370 (6 << TX_LENGTHS_IPG_SHIFT) |
1371 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1372 else
1373 tw32(MAC_TX_LENGTHS,
1374 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1375 (6 << TX_LENGTHS_IPG_SHIFT) |
1376 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1377
1378 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1379 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1380 phydev->speed != tp->link_config.active_speed ||
1381 phydev->duplex != tp->link_config.active_duplex ||
1382 oldflowctrl != tp->link_config.active_flowctrl)
1383 linkmesg = 1;
1384
1385 tp->link_config.active_speed = phydev->speed;
1386 tp->link_config.active_duplex = phydev->duplex;
1387
1388 spin_unlock(&tp->lock);
1389
1390 if (linkmesg)
1391 tg3_link_report(tp);
1392}
1393
1394static int tg3_phy_init(struct tg3 *tp)
1395{
1396 struct phy_device *phydev;
1397
1398 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1399 return 0;
1400
1401 /* Bring the PHY back to a known state. */
1402 tg3_bmcr_reset(tp);
1403
298cf9be 1404 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1405
1406 /* Attach the MAC to the PHY. */
fb28ad35 1407 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1408 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1409 if (IS_ERR(phydev)) {
1410 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1411 return PTR_ERR(phydev);
1412 }
1413
b02fd9e3 1414 /* Mask with MAC supported features. */
9c61d6bc
MC		 1415 switch (phydev->interface) {
1416 case PHY_INTERFACE_MODE_GMII:
1417 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1418 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1419 phydev->supported &= (PHY_GBIT_FEATURES |
1420 SUPPORTED_Pause |
1421 SUPPORTED_Asym_Pause);
1422 break;
1423 }
1424 /* fallthru */
9c61d6bc
MC		 1425 case PHY_INTERFACE_MODE_MII:
1426 phydev->supported &= (PHY_BASIC_FEATURES |
1427 SUPPORTED_Pause |
1428 SUPPORTED_Asym_Pause);
1429 break;
1430 default:
1431 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1432 return -EINVAL;
1433 }
1434
1435 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1436
1437 phydev->advertising = phydev->supported;
1438
b02fd9e3
MC		 1439 return 0;
1440}
1441
1442static void tg3_phy_start(struct tg3 *tp)
1443{
1444 struct phy_device *phydev;
1445
1446 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1447 return;
1448
298cf9be 1449 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1450
1451 if (tp->link_config.phy_is_low_power) {
1452 tp->link_config.phy_is_low_power = 0;
1453 phydev->speed = tp->link_config.orig_speed;
1454 phydev->duplex = tp->link_config.orig_duplex;
1455 phydev->autoneg = tp->link_config.orig_autoneg;
1456 phydev->advertising = tp->link_config.orig_advertising;
1457 }
1458
1459 phy_start(phydev);
1460
1461 phy_start_aneg(phydev);
1462}
1463
1464static void tg3_phy_stop(struct tg3 *tp)
1465{
1466 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1467 return;
1468
298cf9be 1469 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1470}
1471
1472static void tg3_phy_fini(struct tg3 *tp)
1473{
1474 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1475 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1476 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1477 }
1478}
1479
b2a5c19c
MC		 1480static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1481{
1482 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1483 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1484}
1485
7f97a4bd
MC		 1486static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1487{
1488 u32 phytest;
1489
1490 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1491 u32 phy;
1492
1493 tg3_writephy(tp, MII_TG3_FET_TEST,
1494 phytest | MII_TG3_FET_SHADOW_EN);
1495 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1496 if (enable)
1497 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1498 else
1499 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1500 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1501 }
1502 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1503 }
1504}
1505
6833c043
MC		 1506static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1507{
1508 u32 reg;
1509
7f97a4bd 1510 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1511 return;
1512
7f97a4bd
MC		 1513 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1514 tg3_phy_fet_toggle_apd(tp, enable);
1515 return;
1516 }
1517
6833c043
MC		 1518 reg = MII_TG3_MISC_SHDW_WREN |
1519 MII_TG3_MISC_SHDW_SCR5_SEL |
1520 MII_TG3_MISC_SHDW_SCR5_LPED |
1521 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1522 MII_TG3_MISC_SHDW_SCR5_SDTL |
1523 MII_TG3_MISC_SHDW_SCR5_C125OE;
1524 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1525 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1526
1527 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1528
1529
1530 reg = MII_TG3_MISC_SHDW_WREN |
1531 MII_TG3_MISC_SHDW_APD_SEL |
1532 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1533 if (enable)
1534 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1535
1536 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1537}
1538
9ef8ca99
MC		 1539static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1540{
1541 u32 phy;
1542
1543 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1544 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1545 return;
1546
7f97a4bd 1547 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1548 u32 ephy;
1549
535ef6e1
MC		 1550 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1551 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1552
1553 tg3_writephy(tp, MII_TG3_FET_TEST,
1554 ephy | MII_TG3_FET_SHADOW_EN);
1555 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1556 if (enable)
535ef6e1 1557 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1558 else
535ef6e1
MC		 1559 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1560 tg3_writephy(tp, reg, phy);
9ef8ca99 1561 }
535ef6e1 1562 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1563 }
1564 } else {
1565 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1566 MII_TG3_AUXCTL_SHDWSEL_MISC;
1567 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1568 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1569 if (enable)
1570 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1571 else
1572 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1573 phy |= MII_TG3_AUXCTL_MISC_WREN;
1574 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1575 }
1576 }
1577}
1578
1da177e4
LT		 1579static void tg3_phy_set_wirespeed(struct tg3 *tp)
1580{
1581 u32 val;
1582
1583 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1584 return;
1585
1586 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1587 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1588 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1589 (val | (1 << 15) | (1 << 4)));
1590}
1591
b2a5c19c
MC		 1592static void tg3_phy_apply_otp(struct tg3 *tp)
1593{
1594 u32 otp, phy;
1595
1596 if (!tp->phy_otp)
1597 return;
1598
1599 otp = tp->phy_otp;
1600
1601 /* Enable SM_DSP clock and tx 6dB coding. */
1602 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1603 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1604 MII_TG3_AUXCTL_ACTL_TX_6DB;
1605 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1606
1607 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1608 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1609 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1610
1611 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1612 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1613 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1614
1615 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1616 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1617 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1618
1619 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1620 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1621
1622 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1623 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1624
1625 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1626 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1627 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1628
1629 /* Turn off SM_DSP clock. */
1630 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1631 MII_TG3_AUXCTL_ACTL_TX_6DB;
1632 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1633}
1634
1da177e4
LT		 1635static int tg3_wait_macro_done(struct tg3 *tp)
1636{
1637 int limit = 100;
1638
1639 while (limit--) {
1640 u32 tmp32;
1641
1642 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1643 if ((tmp32 & 0x1000) == 0)
1644 break;
1645 }
1646 }
d4675b52 1647 if (limit < 0)
1da177e4
LT		 1648 return -EBUSY;
1649
1650 return 0;
1651}
1652
1653static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1654{
1655 static const u32 test_pat[4][6] = {
1656 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1657 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1658 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1659 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1660 };
1661 int chan;
1662
1663 for (chan = 0; chan < 4; chan++) {
1664 int i;
1665
1666 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1667 (chan * 0x2000) | 0x0200);
1668 tg3_writephy(tp, 0x16, 0x0002);
1669
1670 for (i = 0; i < 6; i++)
1671 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1672 test_pat[chan][i]);
1673
1674 tg3_writephy(tp, 0x16, 0x0202);
1675 if (tg3_wait_macro_done(tp)) {
1676 *resetp = 1;
1677 return -EBUSY;
1678 }
1679
1680 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1681 (chan * 0x2000) | 0x0200);
1682 tg3_writephy(tp, 0x16, 0x0082);
1683 if (tg3_wait_macro_done(tp)) {
1684 *resetp = 1;
1685 return -EBUSY;
1686 }
1687
1688 tg3_writephy(tp, 0x16, 0x0802);
1689 if (tg3_wait_macro_done(tp)) {
1690 *resetp = 1;
1691 return -EBUSY;
1692 }
1693
1694 for (i = 0; i < 6; i += 2) {
1695 u32 low, high;
1696
1697 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1698 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1699 tg3_wait_macro_done(tp)) {
1700 *resetp = 1;
1701 return -EBUSY;
1702 }
1703 low &= 0x7fff;
1704 high &= 0x000f;
1705 if (low != test_pat[chan][i] ||
1706 high != test_pat[chan][i+1]) {
1707 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1708 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1709 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1710
1711 return -EBUSY;
1712 }
1713 }
1714 }
1715
1716 return 0;
1717}
1718
1719static int tg3_phy_reset_chanpat(struct tg3 *tp)
1720{
1721 int chan;
1722
1723 for (chan = 0; chan < 4; chan++) {
1724 int i;
1725
1726 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1727 (chan * 0x2000) | 0x0200);
1728 tg3_writephy(tp, 0x16, 0x0002);
1729 for (i = 0; i < 6; i++)
1730 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1731 tg3_writephy(tp, 0x16, 0x0202);
1732 if (tg3_wait_macro_done(tp))
1733 return -EBUSY;
1734 }
1735
1736 return 0;
1737}
1738
1739static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1740{
1741 u32 reg32, phy9_orig;
1742 int retries, do_phy_reset, err;
1743
1744 retries = 10;
1745 do_phy_reset = 1;
1746 do {
1747 if (do_phy_reset) {
1748 err = tg3_bmcr_reset(tp);
1749 if (err)
1750 return err;
1751 do_phy_reset = 0;
1752 }
1753
1754 /* Disable transmitter and interrupt. */
1755 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1756 continue;
1757
1758 reg32 |= 0x3000;
1759 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1760
1761 /* Set full-duplex, 1000 mbps. */
1762 tg3_writephy(tp, MII_BMCR,
1763 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1764
1765 /* Set to master mode. */
1766 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1767 continue;
1768
1769 tg3_writephy(tp, MII_TG3_CTRL,
1770 (MII_TG3_CTRL_AS_MASTER |
1771 MII_TG3_CTRL_ENABLE_AS_MASTER));
1772
1773 /* Enable SM_DSP_CLOCK and 6dB. */
1774 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1775
1776 /* Block the PHY control access. */
1777 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1778 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1779
1780 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1781 if (!err)
1782 break;
1783 } while (--retries);
1784
1785 err = tg3_phy_reset_chanpat(tp);
1786 if (err)
1787 return err;
1788
1789 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1790 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1791
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1793 tg3_writephy(tp, 0x16, 0x0000);
1794
1795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1797 /* Set Extended packet length bit for jumbo frames */
1798 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1799 }
1800 else {
1801 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1802 }
1803
1804 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1805
1806 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1807 reg32 &= ~0x3000;
1808 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1809 } else if (!err)
1810 err = -EBUSY;
1811
1812 return err;
1813}
1814
1815/* This will reset the tigon3 PHY if there is no valid
1816 * link unless the FORCE argument is non-zero.
1817 */
1818static int tg3_phy_reset(struct tg3 *tp)
1819{
b2a5c19c 1820 u32 cpmuctrl;
1da177e4
LT		 1821 u32 phy_status;
1822 int err;
1823
60189ddf
MC		 1824 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1825 u32 val;
1826
1827 val = tr32(GRC_MISC_CFG);
1828 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1829 udelay(40);
1830 }
1da177e4
LT		 1831 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1832 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1833 if (err != 0)
1834 return -EBUSY;
1835
c8e1e82b
MC		 1836 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1837 netif_carrier_off(tp->dev);
1838 tg3_link_report(tp);
1839 }
1840
1da177e4
LT		 1841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1843 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1844 err = tg3_phy_reset_5703_4_5(tp);
1845 if (err)
1846 return err;
1847 goto out;
1848 }
1849
b2a5c19c
MC		 1850 cpmuctrl = 0;
1851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1852 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1853 cpmuctrl = tr32(TG3_CPMU_CTRL);
1854 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1855 tw32(TG3_CPMU_CTRL,
1856 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1857 }
1858
1da177e4
LT		 1859 err = tg3_bmcr_reset(tp);
1860 if (err)
1861 return err;
1862
b2a5c19c
MC		 1863 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1864 u32 phy;
1865
1866 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1867 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1868
1869 tw32(TG3_CPMU_CTRL, cpmuctrl);
1870 }
1871
bcb37f6c
MC		 1872 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1873 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1874 u32 val;
1875
1876 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1877 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1878 CPMU_LSPD_1000MB_MACCLK_12_5) {
1879 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1880 udelay(40);
1881 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1882 }
1883 }
1884
b2a5c19c
MC		 1885 tg3_phy_apply_otp(tp);
1886
6833c043
MC		 1887 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1888 tg3_phy_toggle_apd(tp, true);
1889 else
1890 tg3_phy_toggle_apd(tp, false);
1891
1da177e4
LT		 1892out:
1893 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1894 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1895 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1896 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1898 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1899 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1900 }
1901 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1902 tg3_writephy(tp, 0x1c, 0x8d68);
1903 tg3_writephy(tp, 0x1c, 0x8d68);
1904 }
1905 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1906 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1907 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1908 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1910 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1911 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1913 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1914 }
c424cb24
MC		 1915 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1916 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1917 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1918 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1919 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1920 tg3_writephy(tp, MII_TG3_TEST1,
1921 MII_TG3_TEST1_TRIM_EN | 0x4);
1922 } else
1923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1924 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1925 }
1da177e4
LT		 1926 /* Set Extended packet length bit (bit 14) on all chips that */
1927 /* support jumbo frames */
1928 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1929 /* Cannot do read-modify-write on 5401 */
1930 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1931 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1932 u32 phy_reg;
1933
1934 /* Set bit 14 with read-modify-write to preserve other bits */
1935 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1936 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1937 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1938 }
1939
1940 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1941 * jumbo frames transmission.
1942 */
8f666b07 1943 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1944 u32 phy_reg;
1945
1946 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1947 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1948 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1949 }
1950
715116a1 1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1952 /* adjust output voltage */
535ef6e1 1953 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1954 }
1955
9ef8ca99 1956 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1957 tg3_phy_set_wirespeed(tp);
1958 return 0;
1959}
1960
1961static void tg3_frob_aux_power(struct tg3 *tp)
1962{
1963 struct tg3 *tp_peer = tp;
1964
9d26e213 1965 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1966 return;
1967
8c2dc7e1
MC		 1968 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1969 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1970 struct net_device *dev_peer;
1971
1972 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1973 /* remove_one() may have been run on the peer. */
8c2dc7e1 1974 if (!dev_peer)
bc1c7567
MC		 1975 tp_peer = tp;
1976 else
1977 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1978 }
1979
1da177e4 1980 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1981 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1982 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1983 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1986 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1987 (GRC_LCLCTRL_GPIO_OE0 |
1988 GRC_LCLCTRL_GPIO_OE1 |
1989 GRC_LCLCTRL_GPIO_OE2 |
1990 GRC_LCLCTRL_GPIO_OUTPUT0 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1),
1992 100);
8d519ab2
MC		 1993 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1994 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 1995 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1996 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1997 GRC_LCLCTRL_GPIO_OE1 |
1998 GRC_LCLCTRL_GPIO_OE2 |
1999 GRC_LCLCTRL_GPIO_OUTPUT0 |
2000 GRC_LCLCTRL_GPIO_OUTPUT1 |
2001 tp->grc_local_ctrl;
2002 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2003
2004 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2005 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2006
2007 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2008 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2009 } else {
2010 u32 no_gpio2;
dc56b7d4 2011 u32 grc_local_ctrl = 0;
1da177e4
LT		 2012
2013 if (tp_peer != tp &&
2014 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2015 return;
2016
dc56b7d4
MC		 2017 /* Workaround to prevent overdrawing Amps. */
2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2019 ASIC_REV_5714) {
2020 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2021 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2022 grc_local_ctrl, 100);
dc56b7d4
MC		 2023 }
2024
1da177e4
LT		 2025 /* On 5753 and variants, GPIO2 cannot be used. */
2026 no_gpio2 = tp->nic_sram_data_cfg &
2027 NIC_SRAM_DATA_CFG_NO_GPIO2;
2028
dc56b7d4 2029 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2030 GRC_LCLCTRL_GPIO_OE1 |
2031 GRC_LCLCTRL_GPIO_OE2 |
2032 GRC_LCLCTRL_GPIO_OUTPUT1 |
2033 GRC_LCLCTRL_GPIO_OUTPUT2;
2034 if (no_gpio2) {
2035 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2036 GRC_LCLCTRL_GPIO_OUTPUT2);
2037 }
b401e9e2
MC		 2038 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2039 grc_local_ctrl, 100);
1da177e4
LT		 2040
2041 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2042
b401e9e2
MC		 2043 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2044 grc_local_ctrl, 100);
1da177e4
LT		 2045
2046 if (!no_gpio2) {
2047 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2048 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2049 grc_local_ctrl, 100);
1da177e4
LT		 2050 }
2051 }
2052 } else {
2053 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2054 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2055 if (tp_peer != tp &&
2056 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2057 return;
2058
b401e9e2
MC		 2059 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060 (GRC_LCLCTRL_GPIO_OE1 |
2061 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2062
b401e9e2
MC		 2063 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2064 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2065
b401e9e2
MC		 2066 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067 (GRC_LCLCTRL_GPIO_OE1 |
2068 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2069 }
2070 }
2071}
2072
e8f3f6ca
MC		 2073static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2074{
2075 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2076 return 1;
2077 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2078 if (speed != SPEED_10)
2079 return 1;
2080 } else if (speed == SPEED_10)
2081 return 1;
2082
2083 return 0;
2084}
2085
1da177e4
LT		 2086static int tg3_setup_phy(struct tg3 *, int);
2087
2088#define RESET_KIND_SHUTDOWN 0
2089#define RESET_KIND_INIT 1
2090#define RESET_KIND_SUSPEND 2
2091
2092static void tg3_write_sig_post_reset(struct tg3 *, int);
2093static int tg3_halt_cpu(struct tg3 *, u32);
2094
0a459aac 2095static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2096{
ce057f01
MC		 2097 u32 val;
2098
5129724a
MC		 2099 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2101 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2102 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2103
2104 sg_dig_ctrl |=
2105 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2106 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2107 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2108 }
3f7045c1 2109 return;
5129724a 2110 }
3f7045c1 2111
60189ddf 2112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2113 tg3_bmcr_reset(tp);
2114 val = tr32(GRC_MISC_CFG);
2115 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2116 udelay(40);
2117 return;
0a459aac 2118 } else if (do_low_power) {
715116a1
MC		 2119 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2120 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2121
2122 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2123 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2124 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2125 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2126 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2127 }
3f7045c1 2128
15c3b696
MC		 2129 /* The PHY should not be powered down on some chips because
2130 * of bugs.
2131 */
2132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2134 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2135 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2136 return;
ce057f01 2137
bcb37f6c
MC		 2138 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2139 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2140 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2141 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2142 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2143 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2144 }
2145
15c3b696
MC		 2146 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2147}
2148
ffbcfed4
MC		 2149/* tp->lock is held. */
2150static int tg3_nvram_lock(struct tg3 *tp)
2151{
2152 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2153 int i;
2154
2155 if (tp->nvram_lock_cnt == 0) {
2156 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2157 for (i = 0; i < 8000; i++) {
2158 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2159 break;
2160 udelay(20);
2161 }
2162 if (i == 8000) {
2163 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2164 return -ENODEV;
2165 }
2166 }
2167 tp->nvram_lock_cnt++;
2168 }
2169 return 0;
2170}
2171
2172/* tp->lock is held. */
2173static void tg3_nvram_unlock(struct tg3 *tp)
2174{
2175 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2176 if (tp->nvram_lock_cnt > 0)
2177 tp->nvram_lock_cnt--;
2178 if (tp->nvram_lock_cnt == 0)
2179 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2180 }
2181}
2182
2183/* tp->lock is held. */
2184static void tg3_enable_nvram_access(struct tg3 *tp)
2185{
2186 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2187 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2188 u32 nvaccess = tr32(NVRAM_ACCESS);
2189
2190 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2191 }
2192}
2193
2194/* tp->lock is held. */
2195static void tg3_disable_nvram_access(struct tg3 *tp)
2196{
2197 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2198 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2199 u32 nvaccess = tr32(NVRAM_ACCESS);
2200
2201 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2202 }
2203}
2204
2205static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2206 u32 offset, u32 *val)
2207{
2208 u32 tmp;
2209 int i;
2210
2211 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2212 return -EINVAL;
2213
2214 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2215 EEPROM_ADDR_DEVID_MASK |
2216 EEPROM_ADDR_READ);
2217 tw32(GRC_EEPROM_ADDR,
2218 tmp |
2219 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2220 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2221 EEPROM_ADDR_ADDR_MASK) |
2222 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2223
2224 for (i = 0; i < 1000; i++) {
2225 tmp = tr32(GRC_EEPROM_ADDR);
2226
2227 if (tmp & EEPROM_ADDR_COMPLETE)
2228 break;
2229 msleep(1);
2230 }
2231 if (!(tmp & EEPROM_ADDR_COMPLETE))
2232 return -EBUSY;
2233
62cedd11
MC		 2234 tmp = tr32(GRC_EEPROM_DATA);
2235
2236 /*
2237 * The data will always be opposite the native endian
2238 * format. Perform a blind byteswap to compensate.
2239 */
2240 *val = swab32(tmp);
2241
ffbcfed4
MC		 2242 return 0;
2243}
2244
2245#define NVRAM_CMD_TIMEOUT 10000
2246
2247static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2248{
2249 int i;
2250
2251 tw32(NVRAM_CMD, nvram_cmd);
2252 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2253 udelay(10);
2254 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2255 udelay(10);
2256 break;
2257 }
2258 }
2259
2260 if (i == NVRAM_CMD_TIMEOUT)
2261 return -EBUSY;
2262
2263 return 0;
2264}
2265
2266static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2267{
2268 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2269 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2270 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2271 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2272 (tp->nvram_jedecnum == JEDEC_ATMEL))
2273
2274 addr = ((addr / tp->nvram_pagesize) <<
2275 ATMEL_AT45DB0X1B_PAGE_POS) +
2276 (addr % tp->nvram_pagesize);
2277
2278 return addr;
2279}
2280
2281static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2282{
2283 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2284 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2285 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2286 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2287 (tp->nvram_jedecnum == JEDEC_ATMEL))
2288
2289 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2290 tp->nvram_pagesize) +
2291 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2292
2293 return addr;
2294}
2295
e4f34110
MC		 2296/* NOTE: Data read in from NVRAM is byteswapped according to
2297 * the byteswapping settings for all other register accesses.
2298 * tg3 devices are BE devices, so on a BE machine, the data
2299 * returned will be exactly as it is seen in NVRAM. On a LE
2300 * machine, the 32-bit value will be byteswapped.
2301 */
ffbcfed4
MC		 2302static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2303{
2304 int ret;
2305
2306 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2307 return tg3_nvram_read_using_eeprom(tp, offset, val);
2308
2309 offset = tg3_nvram_phys_addr(tp, offset);
2310
2311 if (offset > NVRAM_ADDR_MSK)
2312 return -EINVAL;
2313
2314 ret = tg3_nvram_lock(tp);
2315 if (ret)
2316 return ret;
2317
2318 tg3_enable_nvram_access(tp);
2319
2320 tw32(NVRAM_ADDR, offset);
2321 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2322 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2323
2324 if (ret == 0)
e4f34110 2325 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2326
2327 tg3_disable_nvram_access(tp);
2328
2329 tg3_nvram_unlock(tp);
2330
2331 return ret;
2332}
2333
a9dc529d
MC		 2334/* Ensures NVRAM data is in bytestream format. */
2335static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2336{
2337 u32 v;
a9dc529d 2338 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2339 if (!res)
a9dc529d 2340 *val = cpu_to_be32(v);
ffbcfed4
MC		 2341 return res;
2342}
2343
3f007891
MC		 2344/* tp->lock is held. */
2345static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2346{
2347 u32 addr_high, addr_low;
2348 int i;
2349
2350 addr_high = ((tp->dev->dev_addr[0] << 8) |
2351 tp->dev->dev_addr[1]);
2352 addr_low = ((tp->dev->dev_addr[2] << 24) |
2353 (tp->dev->dev_addr[3] << 16) |
2354 (tp->dev->dev_addr[4] << 8) |
2355 (tp->dev->dev_addr[5] << 0));
2356 for (i = 0; i < 4; i++) {
2357 if (i == 1 && skip_mac_1)
2358 continue;
2359 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2360 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2361 }
2362
2363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2365 for (i = 0; i < 12; i++) {
2366 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2367 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2368 }
2369 }
2370
2371 addr_high = (tp->dev->dev_addr[0] +
2372 tp->dev->dev_addr[1] +
2373 tp->dev->dev_addr[2] +
2374 tp->dev->dev_addr[3] +
2375 tp->dev->dev_addr[4] +
2376 tp->dev->dev_addr[5]) &
2377 TX_BACKOFF_SEED_MASK;
2378 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2379}
2380
bc1c7567 2381static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2382{
2383 u32 misc_host_ctrl;
0a459aac 2384 bool device_should_wake, do_low_power;
1da177e4
LT		 2385
2386 /* Make sure register accesses (indirect or otherwise)
2387 * will function correctly.
2388 */
2389 pci_write_config_dword(tp->pdev,
2390 TG3PCI_MISC_HOST_CTRL,
2391 tp->misc_host_ctrl);
2392
1da177e4 2393 switch (state) {
bc1c7567 2394 case PCI_D0:
12dac075
RW		 2395 pci_enable_wake(tp->pdev, state, false);
2396 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2397
9d26e213
MC		 2398 /* Switch out of Vaux if it is a NIC */
2399 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2400 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2401
2402 return 0;
2403
bc1c7567 2404 case PCI_D1:
bc1c7567 2405 case PCI_D2:
bc1c7567 2406 case PCI_D3hot:
1da177e4
LT		 2407 break;
2408
2409 default:
12dac075
RW		 2410 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2411 tp->dev->name, state);
1da177e4 2412 return -EINVAL;
855e1111 2413 }
5e7dfd0f
MC		 2414
2415 /* Restore the CLKREQ setting. */
2416 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2417 u16 lnkctl;
2418
2419 pci_read_config_word(tp->pdev,
2420 tp->pcie_cap + PCI_EXP_LNKCTL,
2421 &lnkctl);
2422 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2423 pci_write_config_word(tp->pdev,
2424 tp->pcie_cap + PCI_EXP_LNKCTL,
2425 lnkctl);
2426 }
2427
1da177e4
LT		 2428 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2429 tw32(TG3PCI_MISC_HOST_CTRL,
2430 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2431
05ac4cb7
MC		 2432 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2433 device_may_wakeup(&tp->pdev->dev) &&
2434 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2435
dd477003 2436 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2437 do_low_power = false;
b02fd9e3
MC		 2438 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2439 !tp->link_config.phy_is_low_power) {
2440 struct phy_device *phydev;
0a459aac 2441 u32 phyid, advertising;
b02fd9e3 2442
298cf9be 2443 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2444
2445 tp->link_config.phy_is_low_power = 1;
2446
2447 tp->link_config.orig_speed = phydev->speed;
2448 tp->link_config.orig_duplex = phydev->duplex;
2449 tp->link_config.orig_autoneg = phydev->autoneg;
2450 tp->link_config.orig_advertising = phydev->advertising;
2451
2452 advertising = ADVERTISED_TP |
2453 ADVERTISED_Pause |
2454 ADVERTISED_Autoneg |
2455 ADVERTISED_10baseT_Half;
2456
2457 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2458 device_should_wake) {
b02fd9e3
MC		 2459 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2460 advertising |=
2461 ADVERTISED_100baseT_Half |
2462 ADVERTISED_100baseT_Full |
2463 ADVERTISED_10baseT_Full;
2464 else
2465 advertising |= ADVERTISED_10baseT_Full;
2466 }
2467
2468 phydev->advertising = advertising;
2469
2470 phy_start_aneg(phydev);
0a459aac
MC		 2471
2472 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2473 if (phyid != TG3_PHY_ID_BCMAC131) {
2474 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2475 if (phyid == TG3_PHY_OUI_1 ||
2476 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2477 phyid == TG3_PHY_OUI_3)
2478 do_low_power = true;
2479 }
b02fd9e3 2480 }
dd477003 2481 } else {
2023276e 2482 do_low_power = true;
0a459aac 2483
dd477003
MC		 2484 if (tp->link_config.phy_is_low_power == 0) {
2485 tp->link_config.phy_is_low_power = 1;
2486 tp->link_config.orig_speed = tp->link_config.speed;
2487 tp->link_config.orig_duplex = tp->link_config.duplex;
2488 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2489 }
1da177e4 2490
dd477003
MC		 2491 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2492 tp->link_config.speed = SPEED_10;
2493 tp->link_config.duplex = DUPLEX_HALF;
2494 tp->link_config.autoneg = AUTONEG_ENABLE;
2495 tg3_setup_phy(tp, 0);
2496 }
1da177e4
LT		 2497 }
2498
b5d3772c
MC		 2499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2500 u32 val;
2501
2502 val = tr32(GRC_VCPU_EXT_CTRL);
2503 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2504 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2505 int i;
2506 u32 val;
2507
2508 for (i = 0; i < 200; i++) {
2509 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2510 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2511 break;
2512 msleep(1);
2513 }
2514 }
a85feb8c
GZ		 2515 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2516 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2517 WOL_DRV_STATE_SHUTDOWN |
2518 WOL_DRV_WOL |
2519 WOL_SET_MAGIC_PKT);
6921d201 2520
05ac4cb7 2521 if (device_should_wake) {
1da177e4
LT		 2522 u32 mac_mode;
2523
2524 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2525 if (do_low_power) {
dd477003
MC		 2526 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2527 udelay(40);
2528 }
1da177e4 2529
3f7045c1
MC		 2530 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2531 mac_mode = MAC_MODE_PORT_MODE_GMII;
2532 else
2533 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2534
e8f3f6ca
MC		 2535 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2536 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2537 ASIC_REV_5700) {
2538 u32 speed = (tp->tg3_flags &
2539 TG3_FLAG_WOL_SPEED_100MB) ?
2540 SPEED_100 : SPEED_10;
2541 if (tg3_5700_link_polarity(tp, speed))
2542 mac_mode |= MAC_MODE_LINK_POLARITY;
2543 else
2544 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2545 }
1da177e4
LT		 2546 } else {
2547 mac_mode = MAC_MODE_PORT_MODE_TBI;
2548 }
2549
cbf46853 2550 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2551 tw32(MAC_LED_CTRL, tp->led_ctrl);
2552
05ac4cb7
MC		 2553 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2554 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2555 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2556 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2557 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2558 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2559
3bda1258
MC		 2560 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2561 mac_mode |= tp->mac_mode &
2562 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2563 if (mac_mode & MAC_MODE_APE_TX_EN)
2564 mac_mode |= MAC_MODE_TDE_ENABLE;
2565 }
2566
1da177e4
LT		 2567 tw32_f(MAC_MODE, mac_mode);
2568 udelay(100);
2569
2570 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2571 udelay(10);
2572 }
2573
2574 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2575 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2577 u32 base_val;
2578
2579 base_val = tp->pci_clock_ctrl;
2580 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2581 CLOCK_CTRL_TXCLK_DISABLE);
2582
b401e9e2
MC		 2583 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2584 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2585 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2586 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2587 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2588 /* do nothing */
85e94ced 2589 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2590 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2591 u32 newbits1, newbits2;
2592
2593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2594 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2595 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2596 CLOCK_CTRL_TXCLK_DISABLE |
2597 CLOCK_CTRL_ALTCLK);
2598 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2599 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2600 newbits1 = CLOCK_CTRL_625_CORE;
2601 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2602 } else {
2603 newbits1 = CLOCK_CTRL_ALTCLK;
2604 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2605 }
2606
b401e9e2
MC		 2607 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2608 40);
1da177e4 2609
b401e9e2
MC		 2610 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2611 40);
1da177e4
LT		 2612
2613 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2614 u32 newbits3;
2615
2616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2618 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2619 CLOCK_CTRL_TXCLK_DISABLE |
2620 CLOCK_CTRL_44MHZ_CORE);
2621 } else {
2622 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2623 }
2624
b401e9e2
MC		 2625 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2626 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2627 }
2628 }
2629
05ac4cb7 2630 if (!(device_should_wake) &&
22435849 2631 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2632 tg3_power_down_phy(tp, do_low_power);
6921d201 2633
1da177e4
LT		 2634 tg3_frob_aux_power(tp);
2635
2636 /* Workaround for unstable PLL clock */
2637 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2638 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2639 u32 val = tr32(0x7d00);
2640
2641 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2642 tw32(0x7d00, val);
6921d201 2643 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2644 int err;
2645
2646 err = tg3_nvram_lock(tp);
1da177e4 2647 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2648 if (!err)
2649 tg3_nvram_unlock(tp);
6921d201 2650 }
1da177e4
LT		 2651 }
2652
bbadf503
MC		 2653 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2654
05ac4cb7 2655 if (device_should_wake)
12dac075
RW		 2656 pci_enable_wake(tp->pdev, state, true);
2657
1da177e4 2658 /* Finally, set the new power state. */
12dac075 2659 pci_set_power_state(tp->pdev, state);
1da177e4 2660
1da177e4
LT		 2661 return 0;
2662}
2663
1da177e4
LT		 2664static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2665{
2666 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2667 case MII_TG3_AUX_STAT_10HALF:
2668 *speed = SPEED_10;
2669 *duplex = DUPLEX_HALF;
2670 break;
2671
2672 case MII_TG3_AUX_STAT_10FULL:
2673 *speed = SPEED_10;
2674 *duplex = DUPLEX_FULL;
2675 break;
2676
2677 case MII_TG3_AUX_STAT_100HALF:
2678 *speed = SPEED_100;
2679 *duplex = DUPLEX_HALF;
2680 break;
2681
2682 case MII_TG3_AUX_STAT_100FULL:
2683 *speed = SPEED_100;
2684 *duplex = DUPLEX_FULL;
2685 break;
2686
2687 case MII_TG3_AUX_STAT_1000HALF:
2688 *speed = SPEED_1000;
2689 *duplex = DUPLEX_HALF;
2690 break;
2691
2692 case MII_TG3_AUX_STAT_1000FULL:
2693 *speed = SPEED_1000;
2694 *duplex = DUPLEX_FULL;
2695 break;
2696
2697 default:
7f97a4bd 2698 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2699 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2700 SPEED_10;
2701 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2702 DUPLEX_HALF;
2703 break;
2704 }
1da177e4
LT		 2705 *speed = SPEED_INVALID;
2706 *duplex = DUPLEX_INVALID;
2707 break;
855e1111 2708 }
1da177e4
LT		 2709}
2710
2711static void tg3_phy_copper_begin(struct tg3 *tp)
2712{
2713 u32 new_adv;
2714 int i;
2715
2716 if (tp->link_config.phy_is_low_power) {
2717 /* Entering low power mode. Disable gigabit and
2718 * 100baseT advertisements.
2719 */
2720 tg3_writephy(tp, MII_TG3_CTRL, 0);
2721
2722 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2723 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2724 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2725 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2726
2727 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2728 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2729 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2730 tp->link_config.advertising &=
2731 ~(ADVERTISED_1000baseT_Half |
2732 ADVERTISED_1000baseT_Full);
2733
ba4d07a8 2734 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2735 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2736 new_adv |= ADVERTISE_10HALF;
2737 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2738 new_adv |= ADVERTISE_10FULL;
2739 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2740 new_adv |= ADVERTISE_100HALF;
2741 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2742 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2743
2744 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2745
1da177e4
LT		 2746 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2747
2748 if (tp->link_config.advertising &
2749 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2750 new_adv = 0;
2751 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2752 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2753 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2754 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2755 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2756 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2757 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2758 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2759 MII_TG3_CTRL_ENABLE_AS_MASTER);
2760 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2761 } else {
2762 tg3_writephy(tp, MII_TG3_CTRL, 0);
2763 }
2764 } else {
ba4d07a8
MC		 2765 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2766 new_adv |= ADVERTISE_CSMA;
2767
1da177e4
LT		 2768 /* Asking for a specific link mode. */
2769 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2770 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2771
2772 if (tp->link_config.duplex == DUPLEX_FULL)
2773 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2774 else
2775 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2776 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2777 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2778 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2779 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2780 } else {
1da177e4
LT		 2781 if (tp->link_config.speed == SPEED_100) {
2782 if (tp->link_config.duplex == DUPLEX_FULL)
2783 new_adv |= ADVERTISE_100FULL;
2784 else
2785 new_adv |= ADVERTISE_100HALF;
2786 } else {
2787 if (tp->link_config.duplex == DUPLEX_FULL)
2788 new_adv |= ADVERTISE_10FULL;
2789 else
2790 new_adv |= ADVERTISE_10HALF;
2791 }
2792 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2793
2794 new_adv = 0;
1da177e4 2795 }
ba4d07a8
MC		 2796
2797 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2798 }
2799
2800 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2801 tp->link_config.speed != SPEED_INVALID) {
2802 u32 bmcr, orig_bmcr;
2803
2804 tp->link_config.active_speed = tp->link_config.speed;
2805 tp->link_config.active_duplex = tp->link_config.duplex;
2806
2807 bmcr = 0;
2808 switch (tp->link_config.speed) {
2809 default:
2810 case SPEED_10:
2811 break;
2812
2813 case SPEED_100:
2814 bmcr |= BMCR_SPEED100;
2815 break;
2816
2817 case SPEED_1000:
2818 bmcr |= TG3_BMCR_SPEED1000;
2819 break;
855e1111 2820 }
1da177e4
LT		 2821
2822 if (tp->link_config.duplex == DUPLEX_FULL)
2823 bmcr |= BMCR_FULLDPLX;
2824
2825 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2826 (bmcr != orig_bmcr)) {
2827 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2828 for (i = 0; i < 1500; i++) {
2829 u32 tmp;
2830
2831 udelay(10);
2832 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2833 tg3_readphy(tp, MII_BMSR, &tmp))
2834 continue;
2835 if (!(tmp & BMSR_LSTATUS)) {
2836 udelay(40);
2837 break;
2838 }
2839 }
2840 tg3_writephy(tp, MII_BMCR, bmcr);
2841 udelay(40);
2842 }
2843 } else {
2844 tg3_writephy(tp, MII_BMCR,
2845 BMCR_ANENABLE | BMCR_ANRESTART);
2846 }
2847}
2848
2849static int tg3_init_5401phy_dsp(struct tg3 *tp)
2850{
2851 int err;
2852
2853 /* Turn off tap power management. */
2854 /* Set Extended packet length bit */
2855 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2856
2857 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2858 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2859
2860 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2861 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2862
2863 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2864 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2865
2866 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2867 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2868
2869 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2870 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2871
2872 udelay(40);
2873
2874 return err;
2875}
2876
3600d918 2877static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2878{
3600d918
MC		 2879 u32 adv_reg, all_mask = 0;
2880
2881 if (mask & ADVERTISED_10baseT_Half)
2882 all_mask |= ADVERTISE_10HALF;
2883 if (mask & ADVERTISED_10baseT_Full)
2884 all_mask |= ADVERTISE_10FULL;
2885 if (mask & ADVERTISED_100baseT_Half)
2886 all_mask |= ADVERTISE_100HALF;
2887 if (mask & ADVERTISED_100baseT_Full)
2888 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2889
2890 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2891 return 0;
2892
1da177e4
LT		 2893 if ((adv_reg & all_mask) != all_mask)
2894 return 0;
2895 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2896 u32 tg3_ctrl;
2897
3600d918
MC		 2898 all_mask = 0;
2899 if (mask & ADVERTISED_1000baseT_Half)
2900 all_mask |= ADVERTISE_1000HALF;
2901 if (mask & ADVERTISED_1000baseT_Full)
2902 all_mask |= ADVERTISE_1000FULL;
2903
1da177e4
LT		 2904 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2905 return 0;
2906
1da177e4
LT		 2907 if ((tg3_ctrl & all_mask) != all_mask)
2908 return 0;
2909 }
2910 return 1;
2911}
2912
ef167e27
MC		 2913static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2914{
2915 u32 curadv, reqadv;
2916
2917 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2918 return 1;
2919
2920 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2921 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2922
2923 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2924 if (curadv != reqadv)
2925 return 0;
2926
2927 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2928 tg3_readphy(tp, MII_LPA, rmtadv);
2929 } else {
2930 /* Reprogram the advertisement register, even if it
2931 * does not affect the current link. If the link
2932 * gets renegotiated in the future, we can save an
2933 * additional renegotiation cycle by advertising
2934 * it correctly in the first place.
2935 */
2936 if (curadv != reqadv) {
2937 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2938 ADVERTISE_PAUSE_ASYM);
2939 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2940 }
2941 }
2942
2943 return 1;
2944}
2945
1da177e4
LT		 2946static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2947{
2948 int current_link_up;
2949 u32 bmsr, dummy;
ef167e27 2950 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2951 u16 current_speed;
2952 u8 current_duplex;
2953 int i, err;
2954
2955 tw32(MAC_EVENT, 0);
2956
2957 tw32_f(MAC_STATUS,
2958 (MAC_STATUS_SYNC_CHANGED |
2959 MAC_STATUS_CFG_CHANGED |
2960 MAC_STATUS_MI_COMPLETION |
2961 MAC_STATUS_LNKSTATE_CHANGED));
2962 udelay(40);
2963
8ef21428
MC		 2964 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2965 tw32_f(MAC_MI_MODE,
2966 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2967 udelay(80);
2968 }
1da177e4
LT		 2969
2970 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2971
2972 /* Some third-party PHYs need to be reset on link going
2973 * down.
2974 */
2975 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2978 netif_carrier_ok(tp->dev)) {
2979 tg3_readphy(tp, MII_BMSR, &bmsr);
2980 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2981 !(bmsr & BMSR_LSTATUS))
2982 force_reset = 1;
2983 }
2984 if (force_reset)
2985 tg3_phy_reset(tp);
2986
2987 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2988 tg3_readphy(tp, MII_BMSR, &bmsr);
2989 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2990 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2991 bmsr = 0;
2992
2993 if (!(bmsr & BMSR_LSTATUS)) {
2994 err = tg3_init_5401phy_dsp(tp);
2995 if (err)
2996 return err;
2997
2998 tg3_readphy(tp, MII_BMSR, &bmsr);
2999 for (i = 0; i < 1000; i++) {
3000 udelay(10);
3001 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3002 (bmsr & BMSR_LSTATUS)) {
3003 udelay(40);
3004 break;
3005 }
3006 }
3007
3008 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3009 !(bmsr & BMSR_LSTATUS) &&
3010 tp->link_config.active_speed == SPEED_1000) {
3011 err = tg3_phy_reset(tp);
3012 if (!err)
3013 err = tg3_init_5401phy_dsp(tp);
3014 if (err)
3015 return err;
3016 }
3017 }
3018 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3019 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3020 /* 5701 {A0,B0} CRC bug workaround */
3021 tg3_writephy(tp, 0x15, 0x0a75);
3022 tg3_writephy(tp, 0x1c, 0x8c68);
3023 tg3_writephy(tp, 0x1c, 0x8d68);
3024 tg3_writephy(tp, 0x1c, 0x8c68);
3025 }
3026
3027 /* Clear pending interrupts... */
3028 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3029 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3030
3031 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3032 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3033 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3034 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3035
3036 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3038 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3039 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3040 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3041 else
3042 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3043 }
3044
3045 current_link_up = 0;
3046 current_speed = SPEED_INVALID;
3047 current_duplex = DUPLEX_INVALID;
3048
3049 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3050 u32 val;
3051
3052 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3053 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3054 if (!(val & (1 << 10))) {
3055 val |= (1 << 10);
3056 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3057 goto relink;
3058 }
3059 }
3060
3061 bmsr = 0;
3062 for (i = 0; i < 100; i++) {
3063 tg3_readphy(tp, MII_BMSR, &bmsr);
3064 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3065 (bmsr & BMSR_LSTATUS))
3066 break;
3067 udelay(40);
3068 }
3069
3070 if (bmsr & BMSR_LSTATUS) {
3071 u32 aux_stat, bmcr;
3072
3073 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3074 for (i = 0; i < 2000; i++) {
3075 udelay(10);
3076 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3077 aux_stat)
3078 break;
3079 }
3080
3081 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3082 &current_speed,
3083 &current_duplex);
3084
3085 bmcr = 0;
3086 for (i = 0; i < 200; i++) {
3087 tg3_readphy(tp, MII_BMCR, &bmcr);
3088 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3089 continue;
3090 if (bmcr && bmcr != 0x7fff)
3091 break;
3092 udelay(10);
3093 }
3094
ef167e27
MC		 3095 lcl_adv = 0;
3096 rmt_adv = 0;
1da177e4 3097
ef167e27
MC		 3098 tp->link_config.active_speed = current_speed;
3099 tp->link_config.active_duplex = current_duplex;
3100
3101 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3102 if ((bmcr & BMCR_ANENABLE) &&
3103 tg3_copper_is_advertising_all(tp,
3104 tp->link_config.advertising)) {
3105 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3106 &rmt_adv))
3107 current_link_up = 1;
1da177e4
LT		 3108 }
3109 } else {
3110 if (!(bmcr & BMCR_ANENABLE) &&
3111 tp->link_config.speed == current_speed &&
ef167e27
MC		 3112 tp->link_config.duplex == current_duplex &&
3113 tp->link_config.flowctrl ==
3114 tp->link_config.active_flowctrl) {
1da177e4 3115 current_link_up = 1;
1da177e4
LT		 3116 }
3117 }
3118
ef167e27
MC		 3119 if (current_link_up == 1 &&
3120 tp->link_config.active_duplex == DUPLEX_FULL)
3121 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3122 }
3123
1da177e4 3124relink:
6921d201 3125 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3126 u32 tmp;
3127
3128 tg3_phy_copper_begin(tp);
3129
3130 tg3_readphy(tp, MII_BMSR, &tmp);
3131 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3132 (tmp & BMSR_LSTATUS))
3133 current_link_up = 1;
3134 }
3135
3136 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3137 if (current_link_up == 1) {
3138 if (tp->link_config.active_speed == SPEED_100 ||
3139 tp->link_config.active_speed == SPEED_10)
3140 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3141 else
3142 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3143 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3144 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3145 else
1da177e4
LT		 3146 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3147
3148 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3149 if (tp->link_config.active_duplex == DUPLEX_HALF)
3150 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3151
1da177e4 3152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3153 if (current_link_up == 1 &&
3154 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3155 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3156 else
3157 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3158 }
3159
3160 /* ??? Without this setting Netgear GA302T PHY does not
3161 * ??? send/receive packets...
3162 */
3163 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3164 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3165 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3166 tw32_f(MAC_MI_MODE, tp->mi_mode);
3167 udelay(80);
3168 }
3169
3170 tw32_f(MAC_MODE, tp->mac_mode);
3171 udelay(40);
3172
3173 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3174 /* Polled via timer. */
3175 tw32_f(MAC_EVENT, 0);
3176 } else {
3177 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3178 }
3179 udelay(40);
3180
3181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3182 current_link_up == 1 &&
3183 tp->link_config.active_speed == SPEED_1000 &&
3184 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3185 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3186 udelay(120);
3187 tw32_f(MAC_STATUS,
3188 (MAC_STATUS_SYNC_CHANGED |
3189 MAC_STATUS_CFG_CHANGED));
3190 udelay(40);
3191 tg3_write_mem(tp,
3192 NIC_SRAM_FIRMWARE_MBOX,
3193 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3194 }
3195
5e7dfd0f
MC		 3196 /* Prevent send BD corruption. */
3197 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3198 u16 oldlnkctl, newlnkctl;
3199
3200 pci_read_config_word(tp->pdev,
3201 tp->pcie_cap + PCI_EXP_LNKCTL,
3202 &oldlnkctl);
3203 if (tp->link_config.active_speed == SPEED_100 ||
3204 tp->link_config.active_speed == SPEED_10)
3205 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3206 else
3207 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3208 if (newlnkctl != oldlnkctl)
3209 pci_write_config_word(tp->pdev,
3210 tp->pcie_cap + PCI_EXP_LNKCTL,
3211 newlnkctl);
255ca311
MC		 3212 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3213 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3214 if (tp->link_config.active_speed == SPEED_100 ||
3215 tp->link_config.active_speed == SPEED_10)
3216 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3217 else
3218 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3219 if (newreg != oldreg)
3220 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC		 3221 }
3222
1da177e4
LT		 3223 if (current_link_up != netif_carrier_ok(tp->dev)) {
3224 if (current_link_up)
3225 netif_carrier_on(tp->dev);
3226 else
3227 netif_carrier_off(tp->dev);
3228 tg3_link_report(tp);
3229 }
3230
3231 return 0;
3232}
3233
3234struct tg3_fiber_aneginfo {
3235 int state;
3236#define ANEG_STATE_UNKNOWN 0
3237#define ANEG_STATE_AN_ENABLE 1
3238#define ANEG_STATE_RESTART_INIT 2
3239#define ANEG_STATE_RESTART 3
3240#define ANEG_STATE_DISABLE_LINK_OK 4
3241#define ANEG_STATE_ABILITY_DETECT_INIT 5
3242#define ANEG_STATE_ABILITY_DETECT 6
3243#define ANEG_STATE_ACK_DETECT_INIT 7
3244#define ANEG_STATE_ACK_DETECT 8
3245#define ANEG_STATE_COMPLETE_ACK_INIT 9
3246#define ANEG_STATE_COMPLETE_ACK 10
3247#define ANEG_STATE_IDLE_DETECT_INIT 11
3248#define ANEG_STATE_IDLE_DETECT 12
3249#define ANEG_STATE_LINK_OK 13
3250#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3251#define ANEG_STATE_NEXT_PAGE_WAIT 15
3252
3253 u32 flags;
3254#define MR_AN_ENABLE 0x00000001
3255#define MR_RESTART_AN 0x00000002
3256#define MR_AN_COMPLETE 0x00000004
3257#define MR_PAGE_RX 0x00000008
3258#define MR_NP_LOADED 0x00000010
3259#define MR_TOGGLE_TX 0x00000020
3260#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3261#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3262#define MR_LP_ADV_SYM_PAUSE 0x00000100
3263#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3264#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3265#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3266#define MR_LP_ADV_NEXT_PAGE 0x00001000
3267#define MR_TOGGLE_RX 0x00002000
3268#define MR_NP_RX 0x00004000
3269
3270#define MR_LINK_OK 0x80000000
3271
3272 unsigned long link_time, cur_time;
3273
3274 u32 ability_match_cfg;
3275 int ability_match_count;
3276
3277 char ability_match, idle_match, ack_match;
3278
3279 u32 txconfig, rxconfig;
3280#define ANEG_CFG_NP 0x00000080
3281#define ANEG_CFG_ACK 0x00000040
3282#define ANEG_CFG_RF2 0x00000020
3283#define ANEG_CFG_RF1 0x00000010
3284#define ANEG_CFG_PS2 0x00000001
3285#define ANEG_CFG_PS1 0x00008000
3286#define ANEG_CFG_HD 0x00004000
3287#define ANEG_CFG_FD 0x00002000
3288#define ANEG_CFG_INVAL 0x00001f06
3289
3290};
3291#define ANEG_OK 0
3292#define ANEG_DONE 1
3293#define ANEG_TIMER_ENAB 2
3294#define ANEG_FAILED -1
3295
3296#define ANEG_STATE_SETTLE_TIME 10000
3297
3298static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3299 struct tg3_fiber_aneginfo *ap)
3300{
5be73b47 3301 u16 flowctrl;
1da177e4
LT		 3302 unsigned long delta;
3303 u32 rx_cfg_reg;
3304 int ret;
3305
3306 if (ap->state == ANEG_STATE_UNKNOWN) {
3307 ap->rxconfig = 0;
3308 ap->link_time = 0;
3309 ap->cur_time = 0;
3310 ap->ability_match_cfg = 0;
3311 ap->ability_match_count = 0;
3312 ap->ability_match = 0;
3313 ap->idle_match = 0;
3314 ap->ack_match = 0;
3315 }
3316 ap->cur_time++;
3317
3318 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3319 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3320
3321 if (rx_cfg_reg != ap->ability_match_cfg) {
3322 ap->ability_match_cfg = rx_cfg_reg;
3323 ap->ability_match = 0;
3324 ap->ability_match_count = 0;
3325 } else {
3326 if (++ap->ability_match_count > 1) {
3327 ap->ability_match = 1;
3328 ap->ability_match_cfg = rx_cfg_reg;
3329 }
3330 }
3331 if (rx_cfg_reg & ANEG_CFG_ACK)
3332 ap->ack_match = 1;
3333 else
3334 ap->ack_match = 0;
3335
3336 ap->idle_match = 0;
3337 } else {
3338 ap->idle_match = 1;
3339 ap->ability_match_cfg = 0;
3340 ap->ability_match_count = 0;
3341 ap->ability_match = 0;
3342 ap->ack_match = 0;
3343
3344 rx_cfg_reg = 0;
3345 }
3346
3347 ap->rxconfig = rx_cfg_reg;
3348 ret = ANEG_OK;
3349
3350 switch(ap->state) {
3351 case ANEG_STATE_UNKNOWN:
3352 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3353 ap->state = ANEG_STATE_AN_ENABLE;
3354
3355 /* fallthru */
3356 case ANEG_STATE_AN_ENABLE:
3357 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3358 if (ap->flags & MR_AN_ENABLE) {
3359 ap->link_time = 0;
3360 ap->cur_time = 0;
3361 ap->ability_match_cfg = 0;
3362 ap->ability_match_count = 0;
3363 ap->ability_match = 0;
3364 ap->idle_match = 0;
3365 ap->ack_match = 0;
3366
3367 ap->state = ANEG_STATE_RESTART_INIT;
3368 } else {
3369 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3370 }
3371 break;
3372
3373 case ANEG_STATE_RESTART_INIT:
3374 ap->link_time = ap->cur_time;
3375 ap->flags &= ~(MR_NP_LOADED);
3376 ap->txconfig = 0;
3377 tw32(MAC_TX_AUTO_NEG, 0);
3378 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3379 tw32_f(MAC_MODE, tp->mac_mode);
3380 udelay(40);
3381
3382 ret = ANEG_TIMER_ENAB;
3383 ap->state = ANEG_STATE_RESTART;
3384
3385 /* fallthru */
3386 case ANEG_STATE_RESTART:
3387 delta = ap->cur_time - ap->link_time;
3388 if (delta > ANEG_STATE_SETTLE_TIME) {
3389 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3390 } else {
3391 ret = ANEG_TIMER_ENAB;
3392 }
3393 break;
3394
3395 case ANEG_STATE_DISABLE_LINK_OK:
3396 ret = ANEG_DONE;
3397 break;
3398
3399 case ANEG_STATE_ABILITY_DETECT_INIT:
3400 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3401 ap->txconfig = ANEG_CFG_FD;
3402 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3403 if (flowctrl & ADVERTISE_1000XPAUSE)
3404 ap->txconfig |= ANEG_CFG_PS1;
3405 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3406 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3407 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3408 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3409 tw32_f(MAC_MODE, tp->mac_mode);
3410 udelay(40);
3411
3412 ap->state = ANEG_STATE_ABILITY_DETECT;
3413 break;
3414
3415 case ANEG_STATE_ABILITY_DETECT:
3416 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3417 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3418 }
3419 break;
3420
3421 case ANEG_STATE_ACK_DETECT_INIT:
3422 ap->txconfig |= ANEG_CFG_ACK;
3423 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3424 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3425 tw32_f(MAC_MODE, tp->mac_mode);
3426 udelay(40);
3427
3428 ap->state = ANEG_STATE_ACK_DETECT;
3429
3430 /* fallthru */
3431 case ANEG_STATE_ACK_DETECT:
3432 if (ap->ack_match != 0) {
3433 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3434 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3435 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3436 } else {
3437 ap->state = ANEG_STATE_AN_ENABLE;
3438 }
3439 } else if (ap->ability_match != 0 &&
3440 ap->rxconfig == 0) {
3441 ap->state = ANEG_STATE_AN_ENABLE;
3442 }
3443 break;
3444
3445 case ANEG_STATE_COMPLETE_ACK_INIT:
3446 if (ap->rxconfig & ANEG_CFG_INVAL) {
3447 ret = ANEG_FAILED;
3448 break;
3449 }
3450 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3451 MR_LP_ADV_HALF_DUPLEX |
3452 MR_LP_ADV_SYM_PAUSE |
3453 MR_LP_ADV_ASYM_PAUSE |
3454 MR_LP_ADV_REMOTE_FAULT1 |
3455 MR_LP_ADV_REMOTE_FAULT2 |
3456 MR_LP_ADV_NEXT_PAGE |
3457 MR_TOGGLE_RX |
3458 MR_NP_RX);
3459 if (ap->rxconfig & ANEG_CFG_FD)
3460 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3461 if (ap->rxconfig & ANEG_CFG_HD)
3462 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3463 if (ap->rxconfig & ANEG_CFG_PS1)
3464 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3465 if (ap->rxconfig & ANEG_CFG_PS2)
3466 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3467 if (ap->rxconfig & ANEG_CFG_RF1)
3468 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3469 if (ap->rxconfig & ANEG_CFG_RF2)
3470 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3471 if (ap->rxconfig & ANEG_CFG_NP)
3472 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3473
3474 ap->link_time = ap->cur_time;
3475
3476 ap->flags ^= (MR_TOGGLE_TX);
3477 if (ap->rxconfig & 0x0008)
3478 ap->flags |= MR_TOGGLE_RX;
3479 if (ap->rxconfig & ANEG_CFG_NP)
3480 ap->flags |= MR_NP_RX;
3481 ap->flags |= MR_PAGE_RX;
3482
3483 ap->state = ANEG_STATE_COMPLETE_ACK;
3484 ret = ANEG_TIMER_ENAB;
3485 break;
3486
3487 case ANEG_STATE_COMPLETE_ACK:
3488 if (ap->ability_match != 0 &&
3489 ap->rxconfig == 0) {
3490 ap->state = ANEG_STATE_AN_ENABLE;
3491 break;
3492 }
3493 delta = ap->cur_time - ap->link_time;
3494 if (delta > ANEG_STATE_SETTLE_TIME) {
3495 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3496 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3497 } else {
3498 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3499 !(ap->flags & MR_NP_RX)) {
3500 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3501 } else {
3502 ret = ANEG_FAILED;
3503 }
3504 }
3505 }
3506 break;
3507
3508 case ANEG_STATE_IDLE_DETECT_INIT:
3509 ap->link_time = ap->cur_time;
3510 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3511 tw32_f(MAC_MODE, tp->mac_mode);
3512 udelay(40);
3513
3514 ap->state = ANEG_STATE_IDLE_DETECT;
3515 ret = ANEG_TIMER_ENAB;
3516 break;
3517
3518 case ANEG_STATE_IDLE_DETECT:
3519 if (ap->ability_match != 0 &&
3520 ap->rxconfig == 0) {
3521 ap->state = ANEG_STATE_AN_ENABLE;
3522 break;
3523 }
3524 delta = ap->cur_time - ap->link_time;
3525 if (delta > ANEG_STATE_SETTLE_TIME) {
3526 /* XXX another gem from the Broadcom driver :( */
3527 ap->state = ANEG_STATE_LINK_OK;
3528 }
3529 break;
3530
3531 case ANEG_STATE_LINK_OK:
3532 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3533 ret = ANEG_DONE;
3534 break;
3535
3536 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3537 /* ??? unimplemented */
3538 break;
3539
3540 case ANEG_STATE_NEXT_PAGE_WAIT:
3541 /* ??? unimplemented */
3542 break;
3543
3544 default:
3545 ret = ANEG_FAILED;
3546 break;
855e1111 3547 }
1da177e4
LT		 3548
3549 return ret;
3550}
3551
5be73b47 3552static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3553{
3554 int res = 0;
3555 struct tg3_fiber_aneginfo aninfo;
3556 int status = ANEG_FAILED;
3557 unsigned int tick;
3558 u32 tmp;
3559
3560 tw32_f(MAC_TX_AUTO_NEG, 0);
3561
3562 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3563 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3564 udelay(40);
3565
3566 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3567 udelay(40);
3568
3569 memset(&aninfo, 0, sizeof(aninfo));
3570 aninfo.flags |= MR_AN_ENABLE;
3571 aninfo.state = ANEG_STATE_UNKNOWN;
3572 aninfo.cur_time = 0;
3573 tick = 0;
3574 while (++tick < 195000) {
3575 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3576 if (status == ANEG_DONE || status == ANEG_FAILED)
3577 break;
3578
3579 udelay(1);
3580 }
3581
3582 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3583 tw32_f(MAC_MODE, tp->mac_mode);
3584 udelay(40);
3585
5be73b47
MC		 3586 *txflags = aninfo.txconfig;
3587 *rxflags = aninfo.flags;
1da177e4
LT		 3588
3589 if (status == ANEG_DONE &&
3590 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3591 MR_LP_ADV_FULL_DUPLEX)))
3592 res = 1;
3593
3594 return res;
3595}
3596
3597static void tg3_init_bcm8002(struct tg3 *tp)
3598{
3599 u32 mac_status = tr32(MAC_STATUS);
3600 int i;
3601
3602 /* Reset when initting first time or we have a link. */
3603 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3604 !(mac_status & MAC_STATUS_PCS_SYNCED))
3605 return;
3606
3607 /* Set PLL lock range. */
3608 tg3_writephy(tp, 0x16, 0x8007);
3609
3610 /* SW reset */
3611 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3612
3613 /* Wait for reset to complete. */
3614 /* XXX schedule_timeout() ... */
3615 for (i = 0; i < 500; i++)
3616 udelay(10);
3617
3618 /* Config mode; select PMA/Ch 1 regs. */
3619 tg3_writephy(tp, 0x10, 0x8411);
3620
3621 /* Enable auto-lock and comdet, select txclk for tx. */
3622 tg3_writephy(tp, 0x11, 0x0a10);
3623
3624 tg3_writephy(tp, 0x18, 0x00a0);
3625 tg3_writephy(tp, 0x16, 0x41ff);
3626
3627 /* Assert and deassert POR. */
3628 tg3_writephy(tp, 0x13, 0x0400);
3629 udelay(40);
3630 tg3_writephy(tp, 0x13, 0x0000);
3631
3632 tg3_writephy(tp, 0x11, 0x0a50);
3633 udelay(40);
3634 tg3_writephy(tp, 0x11, 0x0a10);
3635
3636 /* Wait for signal to stabilize */
3637 /* XXX schedule_timeout() ... */
3638 for (i = 0; i < 15000; i++)
3639 udelay(10);
3640
3641 /* Deselect the channel register so we can read the PHYID
3642 * later.
3643 */
3644 tg3_writephy(tp, 0x10, 0x8011);
3645}
3646
3647static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3648{
82cd3d11 3649 u16 flowctrl;
1da177e4
LT		 3650 u32 sg_dig_ctrl, sg_dig_status;
3651 u32 serdes_cfg, expected_sg_dig_ctrl;
3652 int workaround, port_a;
3653 int current_link_up;
3654
3655 serdes_cfg = 0;
3656 expected_sg_dig_ctrl = 0;
3657 workaround = 0;
3658 port_a = 1;
3659 current_link_up = 0;
3660
3661 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3662 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3663 workaround = 1;
3664 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3665 port_a = 0;
3666
3667 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3668 /* preserve bits 20-23 for voltage regulator */
3669 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3670 }
3671
3672 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3673
3674 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3675 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3676 if (workaround) {
3677 u32 val = serdes_cfg;
3678
3679 if (port_a)
3680 val |= 0xc010000;
3681 else
3682 val |= 0x4010000;
3683 tw32_f(MAC_SERDES_CFG, val);
3684 }
c98f6e3b
MC		 3685
3686 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3687 }
3688 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3689 tg3_setup_flow_control(tp, 0, 0);
3690 current_link_up = 1;
3691 }
3692 goto out;
3693 }
3694
3695 /* Want auto-negotiation. */
c98f6e3b 3696 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3697
82cd3d11
MC		 3698 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3699 if (flowctrl & ADVERTISE_1000XPAUSE)
3700 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3701 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3702 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3703
3704 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3705 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3706 tp->serdes_counter &&
3707 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3708 MAC_STATUS_RCVD_CFG)) ==
3709 MAC_STATUS_PCS_SYNCED)) {
3710 tp->serdes_counter--;
3711 current_link_up = 1;
3712 goto out;
3713 }
3714restart_autoneg:
1da177e4
LT		 3715 if (workaround)
3716 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3717 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3718 udelay(5);
3719 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3720
3d3ebe74
MC		 3721 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3722 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3723 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3724 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3725 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3726 mac_status = tr32(MAC_STATUS);
3727
c98f6e3b 3728 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3729 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3730 u32 local_adv = 0, remote_adv = 0;
3731
3732 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3733 local_adv |= ADVERTISE_1000XPAUSE;
3734 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3735 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3736
c98f6e3b 3737 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3738 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3739 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3740 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3741
3742 tg3_setup_flow_control(tp, local_adv, remote_adv);
3743 current_link_up = 1;
3d3ebe74
MC		 3744 tp->serdes_counter = 0;
3745 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3746 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3747 if (tp->serdes_counter)
3748 tp->serdes_counter--;
1da177e4
LT		 3749 else {
3750 if (workaround) {
3751 u32 val = serdes_cfg;
3752
3753 if (port_a)
3754 val |= 0xc010000;
3755 else
3756 val |= 0x4010000;
3757
3758 tw32_f(MAC_SERDES_CFG, val);
3759 }
3760
c98f6e3b 3761 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3762 udelay(40);
3763
3764 /* Link parallel detection - link is up */
3765 /* only if we have PCS_SYNC and not */
3766 /* receiving config code words */
3767 mac_status = tr32(MAC_STATUS);
3768 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3769 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3770 tg3_setup_flow_control(tp, 0, 0);
3771 current_link_up = 1;
3d3ebe74
MC		 3772 tp->tg3_flags2 |=
3773 TG3_FLG2_PARALLEL_DETECT;
3774 tp->serdes_counter =
3775 SERDES_PARALLEL_DET_TIMEOUT;
3776 } else
3777 goto restart_autoneg;
1da177e4
LT		 3778 }
3779 }
3d3ebe74
MC		 3780 } else {
3781 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3782 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3783 }
3784
3785out:
3786 return current_link_up;
3787}
3788
3789static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3790{
3791 int current_link_up = 0;
3792
5cf64b8a 3793 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3794 goto out;
1da177e4
LT		 3795
3796 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3797 u32 txflags, rxflags;
1da177e4 3798 int i;
6aa20a22 3799
5be73b47
MC		 3800 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3801 u32 local_adv = 0, remote_adv = 0;
1da177e4 3802
5be73b47
MC		 3803 if (txflags & ANEG_CFG_PS1)
3804 local_adv |= ADVERTISE_1000XPAUSE;
3805 if (txflags & ANEG_CFG_PS2)
3806 local_adv |= ADVERTISE_1000XPSE_ASYM;
3807
3808 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3809 remote_adv |= LPA_1000XPAUSE;
3810 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3812
3813 tg3_setup_flow_control(tp, local_adv, remote_adv);
3814
1da177e4
LT		 3815 current_link_up = 1;
3816 }
3817 for (i = 0; i < 30; i++) {
3818 udelay(20);
3819 tw32_f(MAC_STATUS,
3820 (MAC_STATUS_SYNC_CHANGED |
3821 MAC_STATUS_CFG_CHANGED));
3822 udelay(40);
3823 if ((tr32(MAC_STATUS) &
3824 (MAC_STATUS_SYNC_CHANGED |
3825 MAC_STATUS_CFG_CHANGED)) == 0)
3826 break;
3827 }
3828
3829 mac_status = tr32(MAC_STATUS);
3830 if (current_link_up == 0 &&
3831 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3832 !(mac_status & MAC_STATUS_RCVD_CFG))
3833 current_link_up = 1;
3834 } else {
5be73b47
MC		 3835 tg3_setup_flow_control(tp, 0, 0);
3836
1da177e4
LT		 3837 /* Forcing 1000FD link up. */
3838 current_link_up = 1;
1da177e4
LT		 3839
3840 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3841 udelay(40);
e8f3f6ca
MC		 3842
3843 tw32_f(MAC_MODE, tp->mac_mode);
3844 udelay(40);
1da177e4
LT		 3845 }
3846
3847out:
3848 return current_link_up;
3849}
3850
3851static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3852{
3853 u32 orig_pause_cfg;
3854 u16 orig_active_speed;
3855 u8 orig_active_duplex;
3856 u32 mac_status;
3857 int current_link_up;
3858 int i;
3859
8d018621 3860 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3861 orig_active_speed = tp->link_config.active_speed;
3862 orig_active_duplex = tp->link_config.active_duplex;
3863
3864 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3865 netif_carrier_ok(tp->dev) &&
3866 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3867 mac_status = tr32(MAC_STATUS);
3868 mac_status &= (MAC_STATUS_PCS_SYNCED |
3869 MAC_STATUS_SIGNAL_DET |
3870 MAC_STATUS_CFG_CHANGED |
3871 MAC_STATUS_RCVD_CFG);
3872 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3873 MAC_STATUS_SIGNAL_DET)) {
3874 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3875 MAC_STATUS_CFG_CHANGED));
3876 return 0;
3877 }
3878 }
3879
3880 tw32_f(MAC_TX_AUTO_NEG, 0);
3881
3882 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3883 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3884 tw32_f(MAC_MODE, tp->mac_mode);
3885 udelay(40);
3886
3887 if (tp->phy_id == PHY_ID_BCM8002)
3888 tg3_init_bcm8002(tp);
3889
3890 /* Enable link change event even when serdes polling. */
3891 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3892 udelay(40);
3893
3894 current_link_up = 0;
3895 mac_status = tr32(MAC_STATUS);
3896
3897 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3898 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3899 else
3900 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3901
1da177e4
LT		 3902 tp->hw_status->status =
3903 (SD_STATUS_UPDATED |
3904 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3905
3906 for (i = 0; i < 100; i++) {
3907 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3908 MAC_STATUS_CFG_CHANGED));
3909 udelay(5);
3910 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3911 MAC_STATUS_CFG_CHANGED |
3912 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3913 break;
3914 }
3915
3916 mac_status = tr32(MAC_STATUS);
3917 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3918 current_link_up = 0;
3d3ebe74
MC		 3919 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3920 tp->serdes_counter == 0) {
1da177e4
LT		 3921 tw32_f(MAC_MODE, (tp->mac_mode |
3922 MAC_MODE_SEND_CONFIGS));
3923 udelay(1);
3924 tw32_f(MAC_MODE, tp->mac_mode);
3925 }
3926 }
3927
3928 if (current_link_up == 1) {
3929 tp->link_config.active_speed = SPEED_1000;
3930 tp->link_config.active_duplex = DUPLEX_FULL;
3931 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3932 LED_CTRL_LNKLED_OVERRIDE |
3933 LED_CTRL_1000MBPS_ON));
3934 } else {
3935 tp->link_config.active_speed = SPEED_INVALID;
3936 tp->link_config.active_duplex = DUPLEX_INVALID;
3937 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3938 LED_CTRL_LNKLED_OVERRIDE |
3939 LED_CTRL_TRAFFIC_OVERRIDE));
3940 }
3941
3942 if (current_link_up != netif_carrier_ok(tp->dev)) {
3943 if (current_link_up)
3944 netif_carrier_on(tp->dev);
3945 else
3946 netif_carrier_off(tp->dev);
3947 tg3_link_report(tp);
3948 } else {
8d018621 3949 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3950 if (orig_pause_cfg != now_pause_cfg ||
3951 orig_active_speed != tp->link_config.active_speed ||
3952 orig_active_duplex != tp->link_config.active_duplex)
3953 tg3_link_report(tp);
3954 }
3955
3956 return 0;
3957}
3958
747e8f8b
MC		 3959static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3960{
3961 int current_link_up, err = 0;
3962 u32 bmsr, bmcr;
3963 u16 current_speed;
3964 u8 current_duplex;
ef167e27 3965 u32 local_adv, remote_adv;
747e8f8b
MC		 3966
3967 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3968 tw32_f(MAC_MODE, tp->mac_mode);
3969 udelay(40);
3970
3971 tw32(MAC_EVENT, 0);
3972
3973 tw32_f(MAC_STATUS,
3974 (MAC_STATUS_SYNC_CHANGED |
3975 MAC_STATUS_CFG_CHANGED |
3976 MAC_STATUS_MI_COMPLETION |
3977 MAC_STATUS_LNKSTATE_CHANGED));
3978 udelay(40);
3979
3980 if (force_reset)
3981 tg3_phy_reset(tp);
3982
3983 current_link_up = 0;
3984 current_speed = SPEED_INVALID;
3985 current_duplex = DUPLEX_INVALID;
3986
3987 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3988 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3990 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3991 bmsr |= BMSR_LSTATUS;
3992 else
3993 bmsr &= ~BMSR_LSTATUS;
3994 }
747e8f8b
MC		 3995
3996 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3997
3998 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3999 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4000 /* do nothing, just check for link up at the end */
4001 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4002 u32 adv, new_adv;
4003
4004 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4005 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4006 ADVERTISE_1000XPAUSE |
4007 ADVERTISE_1000XPSE_ASYM |
4008 ADVERTISE_SLCT);
4009
ba4d07a8 4010 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4011
4012 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4013 new_adv |= ADVERTISE_1000XHALF;
4014 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4015 new_adv |= ADVERTISE_1000XFULL;
4016
4017 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4018 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4019 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4020 tg3_writephy(tp, MII_BMCR, bmcr);
4021
4022 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4023 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4024 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4025
4026 return err;
4027 }
4028 } else {
4029 u32 new_bmcr;
4030
4031 bmcr &= ~BMCR_SPEED1000;
4032 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4033
4034 if (tp->link_config.duplex == DUPLEX_FULL)
4035 new_bmcr |= BMCR_FULLDPLX;
4036
4037 if (new_bmcr != bmcr) {
4038 /* BMCR_SPEED1000 is a reserved bit that needs
4039 * to be set on write.
4040 */
4041 new_bmcr |= BMCR_SPEED1000;
4042
4043 /* Force a linkdown */
4044 if (netif_carrier_ok(tp->dev)) {
4045 u32 adv;
4046
4047 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4048 adv &= ~(ADVERTISE_1000XFULL |
4049 ADVERTISE_1000XHALF |
4050 ADVERTISE_SLCT);
4051 tg3_writephy(tp, MII_ADVERTISE, adv);
4052 tg3_writephy(tp, MII_BMCR, bmcr |
4053 BMCR_ANRESTART |
4054 BMCR_ANENABLE);
4055 udelay(10);
4056 netif_carrier_off(tp->dev);
4057 }
4058 tg3_writephy(tp, MII_BMCR, new_bmcr);
4059 bmcr = new_bmcr;
4060 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4061 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4062 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4063 ASIC_REV_5714) {
4064 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4065 bmsr |= BMSR_LSTATUS;
4066 else
4067 bmsr &= ~BMSR_LSTATUS;
4068 }
747e8f8b
MC		 4069 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4070 }
4071 }
4072
4073 if (bmsr & BMSR_LSTATUS) {
4074 current_speed = SPEED_1000;
4075 current_link_up = 1;
4076 if (bmcr & BMCR_FULLDPLX)
4077 current_duplex = DUPLEX_FULL;
4078 else
4079 current_duplex = DUPLEX_HALF;
4080
ef167e27
MC		 4081 local_adv = 0;
4082 remote_adv = 0;
4083
747e8f8b 4084 if (bmcr & BMCR_ANENABLE) {
ef167e27 4085 u32 common;
747e8f8b
MC		 4086
4087 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4088 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4089 common = local_adv & remote_adv;
4090 if (common & (ADVERTISE_1000XHALF |
4091 ADVERTISE_1000XFULL)) {
4092 if (common & ADVERTISE_1000XFULL)
4093 current_duplex = DUPLEX_FULL;
4094 else
4095 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4096 }
4097 else
4098 current_link_up = 0;
4099 }
4100 }
4101
ef167e27
MC		 4102 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4103 tg3_setup_flow_control(tp, local_adv, remote_adv);
4104
747e8f8b
MC		 4105 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4106 if (tp->link_config.active_duplex == DUPLEX_HALF)
4107 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4108
4109 tw32_f(MAC_MODE, tp->mac_mode);
4110 udelay(40);
4111
4112 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4113
4114 tp->link_config.active_speed = current_speed;
4115 tp->link_config.active_duplex = current_duplex;
4116
4117 if (current_link_up != netif_carrier_ok(tp->dev)) {
4118 if (current_link_up)
4119 netif_carrier_on(tp->dev);
4120 else {
4121 netif_carrier_off(tp->dev);
4122 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4123 }
4124 tg3_link_report(tp);
4125 }
4126 return err;
4127}
4128
4129static void tg3_serdes_parallel_detect(struct tg3 *tp)
4130{
3d3ebe74 4131 if (tp->serdes_counter) {
747e8f8b 4132 /* Give autoneg time to complete. */
3d3ebe74 4133 tp->serdes_counter--;
747e8f8b
MC		 4134 return;
4135 }
4136 if (!netif_carrier_ok(tp->dev) &&
4137 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4138 u32 bmcr;
4139
4140 tg3_readphy(tp, MII_BMCR, &bmcr);
4141 if (bmcr & BMCR_ANENABLE) {
4142 u32 phy1, phy2;
4143
4144 /* Select shadow register 0x1f */
4145 tg3_writephy(tp, 0x1c, 0x7c00);
4146 tg3_readphy(tp, 0x1c, &phy1);
4147
4148 /* Select expansion interrupt status register */
4149 tg3_writephy(tp, 0x17, 0x0f01);
4150 tg3_readphy(tp, 0x15, &phy2);
4151 tg3_readphy(tp, 0x15, &phy2);
4152
4153 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4154 /* We have signal detect and not receiving
4155 * config code words, link is up by parallel
4156 * detection.
4157 */
4158
4159 bmcr &= ~BMCR_ANENABLE;
4160 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4161 tg3_writephy(tp, MII_BMCR, bmcr);
4162 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4163 }
4164 }
4165 }
4166 else if (netif_carrier_ok(tp->dev) &&
4167 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4168 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4169 u32 phy2;
4170
4171 /* Select expansion interrupt status register */
4172 tg3_writephy(tp, 0x17, 0x0f01);
4173 tg3_readphy(tp, 0x15, &phy2);
4174 if (phy2 & 0x20) {
4175 u32 bmcr;
4176
4177 /* Config code words received, turn on autoneg. */
4178 tg3_readphy(tp, MII_BMCR, &bmcr);
4179 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4180
4181 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4182
4183 }
4184 }
4185}
4186
1da177e4
LT		 4187static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4188{
4189 int err;
4190
4191 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4192 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4193 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4194 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4195 } else {
4196 err = tg3_setup_copper_phy(tp, force_reset);
4197 }
4198
bcb37f6c 4199 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4200 u32 val, scale;
4201
4202 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4203 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4204 scale = 65;
4205 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4206 scale = 6;
4207 else
4208 scale = 12;
4209
4210 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4211 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4212 tw32(GRC_MISC_CFG, val);
4213 }
4214
1da177e4
LT		 4215 if (tp->link_config.active_speed == SPEED_1000 &&
4216 tp->link_config.active_duplex == DUPLEX_HALF)
4217 tw32(MAC_TX_LENGTHS,
4218 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4219 (6 << TX_LENGTHS_IPG_SHIFT) |
4220 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4221 else
4222 tw32(MAC_TX_LENGTHS,
4223 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4224 (6 << TX_LENGTHS_IPG_SHIFT) |
4225 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4226
4227 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4228 if (netif_carrier_ok(tp->dev)) {
4229 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4230 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4231 } else {
4232 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4233 }
4234 }
4235
8ed5d97e
MC		 4236 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4237 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4238 if (!netif_carrier_ok(tp->dev))
4239 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4240 tp->pwrmgmt_thresh;
4241 else
4242 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4243 tw32(PCIE_PWR_MGMT_THRESH, val);
4244 }
4245
1da177e4
LT		 4246 return err;
4247}
4248
df3e6548
MC		 4249/* This is called whenever we suspect that the system chipset is re-
4250 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4251 * is bogus tx completions. We try to recover by setting the
4252 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4253 * in the workqueue.
4254 */
4255static void tg3_tx_recover(struct tg3 *tp)
4256{
4257 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4258 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4259
4260 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4261 "mapped I/O cycles to the network device, attempting to "
4262 "recover. Please report the problem to the driver maintainer "
4263 "and include system chipset information.\n", tp->dev->name);
4264
4265 spin_lock(&tp->lock);
df3e6548 4266 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4267 spin_unlock(&tp->lock);
4268}
4269
1b2a7205
MC		 4270static inline u32 tg3_tx_avail(struct tg3 *tp)
4271{
4272 smp_mb();
4273 return (tp->tx_pending -
4274 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4275}
4276
1da177e4
LT		 4277/* Tigon3 never reports partial packet sends. So we do not
4278 * need special logic to handle SKBs that have not had all
4279 * of their frags sent yet, like SunGEM does.
4280 */
4281static void tg3_tx(struct tg3 *tp)
4282{
4283 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4284 u32 sw_idx = tp->tx_cons;
4285
4286 while (sw_idx != hw_idx) {
4287 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4288 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4289 int i, tx_bug = 0;
4290
4291 if (unlikely(skb == NULL)) {
4292 tg3_tx_recover(tp);
4293 return;
4294 }
1da177e4 4295
90079ce8 4296 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4297
4298 ri->skb = NULL;
4299
4300 sw_idx = NEXT_TX(sw_idx);
4301
4302 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4303 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4304 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4305 tx_bug = 1;
1da177e4
LT		 4306 sw_idx = NEXT_TX(sw_idx);
4307 }
4308
f47c11ee 4309 dev_kfree_skb(skb);
df3e6548
MC		 4310
4311 if (unlikely(tx_bug)) {
4312 tg3_tx_recover(tp);
4313 return;
4314 }
1da177e4
LT		 4315 }
4316
4317 tp->tx_cons = sw_idx;
4318
1b2a7205
MC		 4319 /* Need to make the tx_cons update visible to tg3_start_xmit()
4320 * before checking for netif_queue_stopped(). Without the
4321 * memory barrier, there is a small possibility that tg3_start_xmit()
4322 * will miss it and cause the queue to be stopped forever.
4323 */
4324 smp_mb();
4325
4326 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4327 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4328 netif_tx_lock(tp->dev);
51b91468 4329 if (netif_queue_stopped(tp->dev) &&
42952231 4330 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4331 netif_wake_queue(tp->dev);
1b2a7205 4332 netif_tx_unlock(tp->dev);
51b91468 4333 }
1da177e4
LT		 4334}
4335
4336/* Returns size of skb allocated or < 0 on error.
4337 *
4338 * We only need to fill in the address because the other members
4339 * of the RX descriptor are invariant, see tg3_init_rings.
4340 *
4341 * Note the purposeful assymetry of cpu vs. chip accesses. For
4342 * posting buffers we only dirty the first cache line of the RX
4343 * descriptor (containing the address). Whereas for the RX status
4344 * buffers the cpu only reads the last cacheline of the RX descriptor
4345 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4346 */
4347static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4348 int src_idx, u32 dest_idx_unmasked)
4349{
4350 struct tg3_rx_buffer_desc *desc;
4351 struct ring_info *map, *src_map;
4352 struct sk_buff *skb;
4353 dma_addr_t mapping;
4354 int skb_size, dest_idx;
21f581a5 4355 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4356
4357 src_map = NULL;
4358 switch (opaque_key) {
4359 case RXD_OPAQUE_RING_STD:
4360 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4361 desc = &tpr->rx_std[dest_idx];
4362 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4363 if (src_idx >= 0)
21f581a5 4364 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4365 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4366 break;
4367
4368 case RXD_OPAQUE_RING_JUMBO:
4369 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4370 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4371 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4372 if (src_idx >= 0)
21f581a5 4373 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4374 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4375 break;
4376
4377 default:
4378 return -EINVAL;
855e1111 4379 }
1da177e4
LT		 4380
4381 /* Do not overwrite any of the map or rp information
4382 * until we are sure we can commit to a new buffer.
4383 *
4384 * Callers depend upon this behavior and assume that
4385 * we leave everything unchanged if we fail.
4386 */
287be12e 4387 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4388 if (skb == NULL)
4389 return -ENOMEM;
4390
1da177e4
LT		 4391 skb_reserve(skb, tp->rx_offset);
4392
287be12e 4393 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4
LT		 4394 PCI_DMA_FROMDEVICE);
4395
4396 map->skb = skb;
4397 pci_unmap_addr_set(map, mapping, mapping);
4398
4399 if (src_map != NULL)
4400 src_map->skb = NULL;
4401
4402 desc->addr_hi = ((u64)mapping >> 32);
4403 desc->addr_lo = ((u64)mapping & 0xffffffff);
4404
4405 return skb_size;
4406}
4407
4408/* We only need to move over in the address because the other
4409 * members of the RX descriptor are invariant. See notes above
4410 * tg3_alloc_rx_skb for full details.
4411 */
4412static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4413 int src_idx, u32 dest_idx_unmasked)
4414{
4415 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4416 struct ring_info *src_map, *dest_map;
4417 int dest_idx;
21f581a5 4418 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4419
4420 switch (opaque_key) {
4421 case RXD_OPAQUE_RING_STD:
4422 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4423 dest_desc = &tpr->rx_std[dest_idx];
4424 dest_map = &tpr->rx_std_buffers[dest_idx];
4425 src_desc = &tpr->rx_std[src_idx];
4426 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4427 break;
4428
4429 case RXD_OPAQUE_RING_JUMBO:
4430 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4431 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4432 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4433 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4434 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4435 break;
4436
4437 default:
4438 return;
855e1111 4439 }
1da177e4
LT		 4440
4441 dest_map->skb = src_map->skb;
4442 pci_unmap_addr_set(dest_map, mapping,
4443 pci_unmap_addr(src_map, mapping));
4444 dest_desc->addr_hi = src_desc->addr_hi;
4445 dest_desc->addr_lo = src_desc->addr_lo;
4446
4447 src_map->skb = NULL;
4448}
4449
1da177e4
LT		 4450/* The RX ring scheme is composed of multiple rings which post fresh
4451 * buffers to the chip, and one special ring the chip uses to report
4452 * status back to the host.
4453 *
4454 * The special ring reports the status of received packets to the
4455 * host. The chip does not write into the original descriptor the
4456 * RX buffer was obtained from. The chip simply takes the original
4457 * descriptor as provided by the host, updates the status and length
4458 * field, then writes this into the next status ring entry.
4459 *
4460 * Each ring the host uses to post buffers to the chip is described
4461 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4462 * it is first placed into the on-chip ram. When the packet's length
4463 * is known, it walks down the TG3_BDINFO entries to select the ring.
4464 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4465 * which is within the range of the new packet's length is chosen.
4466 *
4467 * The "separate ring for rx status" scheme may sound queer, but it makes
4468 * sense from a cache coherency perspective. If only the host writes
4469 * to the buffer post rings, and only the chip writes to the rx status
4470 * rings, then cache lines never move beyond shared-modified state.
4471 * If both the host and chip were to write into the same ring, cache line
4472 * eviction could occur since both entities want it in an exclusive state.
4473 */
4474static int tg3_rx(struct tg3 *tp, int budget)
4475{
f92905de 4476 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4477 u32 sw_idx = tp->rx_rcb_ptr;
4478 u16 hw_idx;
1da177e4 4479 int received;
21f581a5 4480 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4481
4482 hw_idx = tp->hw_status->idx[0].rx_producer;
4483 /*
4484 * We need to order the read of hw_idx and the read of
4485 * the opaque cookie.
4486 */
4487 rmb();
1da177e4
LT		 4488 work_mask = 0;
4489 received = 0;
4490 while (sw_idx != hw_idx && budget > 0) {
4491 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4492 unsigned int len;
4493 struct sk_buff *skb;
4494 dma_addr_t dma_addr;
4495 u32 opaque_key, desc_idx, *post_ptr;
4496
4497 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4498 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4499 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4500 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4501 dma_addr = pci_unmap_addr(ri, mapping);
4502 skb = ri->skb;
4503 post_ptr = &tpr->rx_std_ptr;
f92905de 4504 rx_std_posted++;
1da177e4 4505 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4506 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4507 dma_addr = pci_unmap_addr(ri, mapping);
4508 skb = ri->skb;
4509 post_ptr = &tpr->rx_jmb_ptr;
4510 } else
1da177e4 4511 goto next_pkt_nopost;
1da177e4
LT		 4512
4513 work_mask |= opaque_key;
4514
4515 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4516 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4517 drop_it:
4518 tg3_recycle_rx(tp, opaque_key,
4519 desc_idx, *post_ptr);
4520 drop_it_no_recycle:
4521 /* Other statistics kept track of by card. */
4522 tp->net_stats.rx_dropped++;
4523 goto next_pkt;
4524 }
4525
ad829268
MC		 4526 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4527 ETH_FCS_LEN;
1da177e4 4528
6aa20a22 4529 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4530 && tp->rx_offset == NET_IP_ALIGN
4531 /* rx_offset will likely not equal NET_IP_ALIGN
4532 * if this is a 5701 card running in PCI-X mode
4533 * [see tg3_get_invariants()]
4534 */
1da177e4
LT		 4535 ) {
4536 int skb_size;
4537
4538 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4539 desc_idx, *post_ptr);
4540 if (skb_size < 0)
4541 goto drop_it;
4542
287be12e 4543 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4544 PCI_DMA_FROMDEVICE);
4545
4546 skb_put(skb, len);
4547 } else {
4548 struct sk_buff *copy_skb;
4549
4550 tg3_recycle_rx(tp, opaque_key,
4551 desc_idx, *post_ptr);
4552
ad829268
MC		 4553 copy_skb = netdev_alloc_skb(tp->dev,
4554 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4555 if (copy_skb == NULL)
4556 goto drop_it_no_recycle;
4557
ad829268 4558 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4559 skb_put(copy_skb, len);
4560 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4561 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4562 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4563
4564 /* We'll reuse the original ring buffer. */
4565 skb = copy_skb;
4566 }
4567
4568 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4569 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4570 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4571 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4572 skb->ip_summed = CHECKSUM_UNNECESSARY;
4573 else
4574 skb->ip_summed = CHECKSUM_NONE;
4575
4576 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4577
4578 if (len > (tp->dev->mtu + ETH_HLEN) &&
4579 skb->protocol != htons(ETH_P_8021Q)) {
4580 dev_kfree_skb(skb);
4581 goto next_pkt;
4582 }
4583
1da177e4
LT		 4584#if TG3_VLAN_TAG_USED
4585 if (tp->vlgrp != NULL &&
4586 desc->type_flags & RXD_FLAG_VLAN) {
8ef0442f
MC		 4587 vlan_gro_receive(&tp->napi[0].napi, tp->vlgrp,
4588 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4589 } else
4590#endif
8ef0442f 4591 napi_gro_receive(&tp->napi[0].napi, skb);
1da177e4 4592
1da177e4
LT		 4593 received++;
4594 budget--;
4595
4596next_pkt:
4597 (*post_ptr)++;
f92905de
MC		 4598
4599 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4600 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4601
4602 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4603 TG3_64BIT_REG_LOW, idx);
4604 work_mask &= ~RXD_OPAQUE_RING_STD;
4605 rx_std_posted = 0;
4606 }
1da177e4 4607next_pkt_nopost:
483ba50b 4608 sw_idx++;
6b31a515 4609 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4610
4611 /* Refresh hw_idx to see if there is new work */
4612 if (sw_idx == hw_idx) {
4613 hw_idx = tp->hw_status->idx[0].rx_producer;
4614 rmb();
4615 }
1da177e4
LT		 4616 }
4617
4618 /* ACK the status ring. */
483ba50b
MC		 4619 tp->rx_rcb_ptr = sw_idx;
4620 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4621
4622 /* Refill RX ring(s). */
4623 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4624 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4625 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4626 sw_idx);
4627 }
4628 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4629 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4630 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4631 sw_idx);
4632 }
4633 mmiowb();
4634
4635 return received;
4636}
4637
6f535763 4638static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4639{
1da177e4 4640 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4641
1da177e4
LT		 4642 /* handle link change and other phy events */
4643 if (!(tp->tg3_flags &
4644 (TG3_FLAG_USE_LINKCHG_REG |
4645 TG3_FLAG_POLL_SERDES))) {
4646 if (sblk->status & SD_STATUS_LINK_CHG) {
4647 sblk->status = SD_STATUS_UPDATED |
4648 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4649 spin_lock(&tp->lock);
dd477003
MC		 4650 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4651 tw32_f(MAC_STATUS,
4652 (MAC_STATUS_SYNC_CHANGED |
4653 MAC_STATUS_CFG_CHANGED |
4654 MAC_STATUS_MI_COMPLETION |
4655 MAC_STATUS_LNKSTATE_CHANGED));
4656 udelay(40);
4657 } else
4658 tg3_setup_phy(tp, 0);
f47c11ee 4659 spin_unlock(&tp->lock);
1da177e4
LT		 4660 }
4661 }
4662
4663 /* run TX completion thread */
4664 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4665 tg3_tx(tp);
6f535763 4666 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4667 return work_done;
1da177e4
LT		 4668 }
4669
1da177e4
LT		 4670 /* run RX thread, within the bounds set by NAPI.
4671 * All RX "locking" is done by ensuring outside
bea3348e 4672 * code synchronizes with tg3->napi.poll()
1da177e4 4673 */
bea3348e 4674 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4675 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4676
6f535763
DM		 4677 return work_done;
4678}
4679
4680static int tg3_poll(struct napi_struct *napi, int budget)
4681{
8ef0442f
MC		 4682 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4683 struct tg3 *tp = tnapi->tp;
6f535763 4684 int work_done = 0;
4fd7ab59 4685 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4686
4687 while (1) {
4688 work_done = tg3_poll_work(tp, work_done, budget);
4689
4690 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4691 goto tx_recovery;
4692
4693 if (unlikely(work_done >= budget))
4694 break;
4695
4fd7ab59
MC		 4696 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4697 /* tp->last_tag is used in tg3_restart_ints() below
4698 * to tell the hw how much work has been processed,
4699 * so we must read it before checking for more work.
4700 */
4701 tp->last_tag = sblk->status_tag;
624f8e50 4702 tp->last_irq_tag = tp->last_tag;
4fd7ab59
MC		 4703 rmb();
4704 } else
4705 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4706
4fd7ab59 4707 if (likely(!tg3_has_work(tp))) {
288379f0 4708 napi_complete(napi);
6f535763
DM		 4709 tg3_restart_ints(tp);
4710 break;
4711 }
1da177e4
LT		 4712 }
4713
bea3348e 4714 return work_done;
6f535763
DM		 4715
4716tx_recovery:
4fd7ab59 4717 /* work_done is guaranteed to be less than budget. */
288379f0 4718 napi_complete(napi);
6f535763 4719 schedule_work(&tp->reset_task);
4fd7ab59 4720 return work_done;
1da177e4
LT		 4721}
4722
f47c11ee
DM		 4723static void tg3_irq_quiesce(struct tg3 *tp)
4724{
4725 BUG_ON(tp->irq_sync);
4726
4727 tp->irq_sync = 1;
4728 smp_mb();
4729
4730 synchronize_irq(tp->pdev->irq);
4731}
4732
4733static inline int tg3_irq_sync(struct tg3 *tp)
4734{
4735 return tp->irq_sync;
4736}
4737
4738/* Fully shutdown all tg3 driver activity elsewhere in the system.
4739 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4740 * with as well. Most of the time, this is not necessary except when
4741 * shutting down the device.
4742 */
4743static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4744{
46966545 4745 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4746 if (irq_sync)
4747 tg3_irq_quiesce(tp);
f47c11ee
DM		 4748}
4749
4750static inline void tg3_full_unlock(struct tg3 *tp)
4751{
f47c11ee
DM		 4752 spin_unlock_bh(&tp->lock);
4753}
4754
fcfa0a32
MC		 4755/* One-shot MSI handler - Chip automatically disables interrupt
4756 * after sending MSI so driver doesn't have to do it.
4757 */
7d12e780 4758static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4759{
4760 struct net_device *dev = dev_id;
4761 struct tg3 *tp = netdev_priv(dev);
4762
4763 prefetch(tp->hw_status);
4764 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4765
4766 if (likely(!tg3_irq_sync(tp)))
8ef0442f 4767 napi_schedule(&tp->napi[0].napi);
fcfa0a32
MC		 4768
4769 return IRQ_HANDLED;
4770}
4771
88b06bc2
MC		 4772/* MSI ISR - No need to check for interrupt sharing and no need to
4773 * flush status block and interrupt mailbox. PCI ordering rules
4774 * guarantee that MSI will arrive after the status block.
4775 */
7d12e780 4776static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4777{
4778 struct net_device *dev = dev_id;
4779 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4780
61487480
MC		 4781 prefetch(tp->hw_status);
4782 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4783 /*
fac9b83e 4784 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4785 * chip-internal interrupt pending events.
fac9b83e 4786 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4787 * NIC to stop sending us irqs, engaging "in-intr-handler"
4788 * event coalescing.
4789 */
4790 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4791 if (likely(!tg3_irq_sync(tp)))
8ef0442f 4792 napi_schedule(&tp->napi[0].napi);
61487480 4793
88b06bc2
MC		 4794 return IRQ_RETVAL(1);
4795}
4796
7d12e780 4797static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4798{
4799 struct net_device *dev = dev_id;
4800 struct tg3 *tp = netdev_priv(dev);
4801 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4802 unsigned int handled = 1;
4803
1da177e4
LT		 4804 /* In INTx mode, it is possible for the interrupt to arrive at
4805 * the CPU before the status block posted prior to the interrupt.
4806 * Reading the PCI State register will confirm whether the
4807 * interrupt is ours and will flush the status block.
4808 */
d18edcb2
MC		 4809 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4810 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4811 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4812 handled = 0;
f47c11ee 4813 goto out;
fac9b83e 4814 }
d18edcb2
MC		 4815 }
4816
4817 /*
4818 * Writing any value to intr-mbox-0 clears PCI INTA# and
4819 * chip-internal interrupt pending events.
4820 * Writing non-zero to intr-mbox-0 additional tells the
4821 * NIC to stop sending us irqs, engaging "in-intr-handler"
4822 * event coalescing.
c04cb347
MC		 4823 *
4824 * Flush the mailbox to de-assert the IRQ immediately to prevent
4825 * spurious interrupts. The flush impacts performance but
4826 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4827 */
c04cb347 4828 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4829 if (tg3_irq_sync(tp))
4830 goto out;
4831 sblk->status &= ~SD_STATUS_UPDATED;
4832 if (likely(tg3_has_work(tp))) {
4833 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
8ef0442f 4834 napi_schedule(&tp->napi[0].napi);
d18edcb2
MC		 4835 } else {
4836 /* No work, shared interrupt perhaps? re-enable
4837 * interrupts, and flush that PCI write
4838 */
4839 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4840 0x00000000);
fac9b83e 4841 }
f47c11ee 4842out:
fac9b83e
DM		 4843 return IRQ_RETVAL(handled);
4844}
4845
7d12e780 4846static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4847{
4848 struct net_device *dev = dev_id;
4849 struct tg3 *tp = netdev_priv(dev);
4850 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4851 unsigned int handled = 1;
4852
fac9b83e
DM		 4853 /* In INTx mode, it is possible for the interrupt to arrive at
4854 * the CPU before the status block posted prior to the interrupt.
4855 * Reading the PCI State register will confirm whether the
4856 * interrupt is ours and will flush the status block.
4857 */
624f8e50 4858 if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
d18edcb2
MC		 4859 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4860 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4861 handled = 0;
f47c11ee 4862 goto out;
1da177e4 4863 }
d18edcb2
MC		 4864 }
4865
4866 /*
4867 * writing any value to intr-mbox-0 clears PCI INTA# and
4868 * chip-internal interrupt pending events.
4869 * writing non-zero to intr-mbox-0 additional tells the
4870 * NIC to stop sending us irqs, engaging "in-intr-handler"
4871 * event coalescing.
c04cb347
MC		 4872 *
4873 * Flush the mailbox to de-assert the IRQ immediately to prevent
4874 * spurious interrupts. The flush impacts performance but
4875 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4876 */
c04cb347 4877 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4878
4879 /*
4880 * In a shared interrupt configuration, sometimes other devices'
4881 * interrupts will scream. We record the current status tag here
4882 * so that the above check can report that the screaming interrupts
4883 * are unhandled. Eventually they will be silenced.
4884 */
4885 tp->last_irq_tag = sblk->status_tag;
4886
d18edcb2
MC		 4887 if (tg3_irq_sync(tp))
4888 goto out;
624f8e50
MC		 4889
4890 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4891
8ef0442f 4892 napi_schedule(&tp->napi[0].napi);
624f8e50 4893
f47c11ee 4894out:
1da177e4
LT		 4895 return IRQ_RETVAL(handled);
4896}
4897
7938109f 4898/* ISR for interrupt test */
7d12e780 4899static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4900{
4901 struct net_device *dev = dev_id;
4902 struct tg3 *tp = netdev_priv(dev);
4903 struct tg3_hw_status *sblk = tp->hw_status;
4904
f9804ddb
MC		 4905 if ((sblk->status & SD_STATUS_UPDATED) ||
4906 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4907 tg3_disable_ints(tp);
7938109f
MC		 4908 return IRQ_RETVAL(1);
4909 }
4910 return IRQ_RETVAL(0);
4911}
4912
8e7a22e3 4913static int tg3_init_hw(struct tg3 *, int);
944d980e 4914static int tg3_halt(struct tg3 *, int, int);
1da177e4 4915
b9ec6c1b
MC		 4916/* Restart hardware after configuration changes, self-test, etc.
4917 * Invoked with tp->lock held.
4918 */
4919static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4920 __releases(tp->lock)
4921 __acquires(tp->lock)
b9ec6c1b
MC		 4922{
4923 int err;
4924
4925 err = tg3_init_hw(tp, reset_phy);
4926 if (err) {
4927 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4928 "aborting.\n", tp->dev->name);
4929 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4930 tg3_full_unlock(tp);
4931 del_timer_sync(&tp->timer);
4932 tp->irq_sync = 0;
8ef0442f 4933 napi_enable(&tp->napi[0].napi);
b9ec6c1b
MC		 4934 dev_close(tp->dev);
4935 tg3_full_lock(tp, 0);
4936 }
4937 return err;
4938}
4939
1da177e4
LT		 4940#ifdef CONFIG_NET_POLL_CONTROLLER
4941static void tg3_poll_controller(struct net_device *dev)
4942{
88b06bc2
MC		 4943 struct tg3 *tp = netdev_priv(dev);
4944
7d12e780 4945 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4946}
4947#endif
4948
c4028958 4949static void tg3_reset_task(struct work_struct *work)
1da177e4 4950{
c4028958 4951 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4952 int err;
1da177e4
LT		 4953 unsigned int restart_timer;
4954
7faa006f 4955 tg3_full_lock(tp, 0);
7faa006f
MC		 4956
4957 if (!netif_running(tp->dev)) {
7faa006f
MC		 4958 tg3_full_unlock(tp);
4959 return;
4960 }
4961
4962 tg3_full_unlock(tp);
4963
b02fd9e3
MC		 4964 tg3_phy_stop(tp);
4965
1da177e4
LT		 4966 tg3_netif_stop(tp);
4967
f47c11ee 4968 tg3_full_lock(tp, 1);
1da177e4
LT		 4969
4970 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4971 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4972
df3e6548
MC		 4973 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4974 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4975 tp->write32_rx_mbox = tg3_write_flush_reg32;
4976 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4977 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4978 }
4979
944d980e 4980 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4981 err = tg3_init_hw(tp, 1);
4982 if (err)
b9ec6c1b 4983 goto out;
1da177e4
LT		 4984
4985 tg3_netif_start(tp);
4986
1da177e4
LT		 4987 if (restart_timer)
4988 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4989
b9ec6c1b 4990out:
7faa006f 4991 tg3_full_unlock(tp);
b02fd9e3
MC		 4992
4993 if (!err)
4994 tg3_phy_start(tp);
1da177e4
LT		 4995}
4996
b0408751
MC		 4997static void tg3_dump_short_state(struct tg3 *tp)
4998{
4999 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5000 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5001 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5002 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5003}
5004
1da177e4
LT		 5005static void tg3_tx_timeout(struct net_device *dev)
5006{
5007 struct tg3 *tp = netdev_priv(dev);
5008
b0408751 5009 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5010 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5011 dev->name);
b0408751
MC		 5012 tg3_dump_short_state(tp);
5013 }
1da177e4
LT		 5014
5015 schedule_work(&tp->reset_task);
5016}
5017
c58ec932
MC		 5018/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5019static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5020{
5021 u32 base = (u32) mapping & 0xffffffff;
5022
5023 return ((base > 0xffffdcc0) &&
5024 (base + len + 8 < base));
5025}
5026
72f2afb8
MC		 5027/* Test for DMA addresses > 40-bit */
5028static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5029 int len)
5030{
5031#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5032 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5033 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5034 return 0;
5035#else
5036 return 0;
5037#endif
5038}
5039
1da177e4
LT		 5040static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5041
72f2afb8
MC		 5042/* Workaround 4GB and 40-bit hardware DMA bugs. */
5043static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5044 u32 last_plus_one, u32 *start,
5045 u32 base_flags, u32 mss)
1da177e4 5046{
41588ba1 5047 struct sk_buff *new_skb;
c58ec932 5048 dma_addr_t new_addr = 0;
1da177e4 5049 u32 entry = *start;
c58ec932 5050 int i, ret = 0;
1da177e4 5051
41588ba1
MC		 5052 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5053 new_skb = skb_copy(skb, GFP_ATOMIC);
5054 else {
5055 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5056
5057 new_skb = skb_copy_expand(skb,
5058 skb_headroom(skb) + more_headroom,
5059 skb_tailroom(skb), GFP_ATOMIC);
5060 }
5061
1da177e4 5062 if (!new_skb) {
c58ec932
MC		 5063 ret = -1;
5064 } else {
5065 /* New SKB is guaranteed to be linear. */
5066 entry = *start;
90079ce8 5067 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5068 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5069
c58ec932
MC		 5070 /* Make sure new skb does not cross any 4G boundaries.
5071 * Drop the packet if it does.
5072 */
90079ce8 5073 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5074 if (!ret)
5075 skb_dma_unmap(&tp->pdev->dev, new_skb,
5076 DMA_TO_DEVICE);
c58ec932
MC		 5077 ret = -1;
5078 dev_kfree_skb(new_skb);
5079 new_skb = NULL;
5080 } else {
5081 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5082 base_flags, 1 | (mss << 1));
5083 *start = NEXT_TX(entry);
5084 }
1da177e4
LT		 5085 }
5086
1da177e4
LT		 5087 /* Now clean up the sw ring entries. */
5088 i = 0;
5089 while (entry != last_plus_one) {
1da177e4
LT		 5090 if (i == 0) {
5091 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5092 } else {
5093 tp->tx_buffers[entry].skb = NULL;
5094 }
5095 entry = NEXT_TX(entry);
5096 i++;
5097 }
5098
90079ce8 5099 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5100 dev_kfree_skb(skb);
5101
c58ec932 5102 return ret;
1da177e4
LT		 5103}
5104
5105static void tg3_set_txd(struct tg3 *tp, int entry,
5106 dma_addr_t mapping, int len, u32 flags,
5107 u32 mss_and_is_end)
5108{
5109 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5110 int is_end = (mss_and_is_end & 0x1);
5111 u32 mss = (mss_and_is_end >> 1);
5112 u32 vlan_tag = 0;
5113
5114 if (is_end)
5115 flags |= TXD_FLAG_END;
5116 if (flags & TXD_FLAG_VLAN) {
5117 vlan_tag = flags >> 16;
5118 flags &= 0xffff;
5119 }
5120 vlan_tag |= (mss << TXD_MSS_SHIFT);
5121
5122 txd->addr_hi = ((u64) mapping >> 32);
5123 txd->addr_lo = ((u64) mapping & 0xffffffff);
5124 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5125 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5126}
5127
5a6f3074
MC		 5128/* hard_start_xmit for devices that don't have any bugs and
5129 * support TG3_FLG2_HW_TSO_2 only.
5130 */
1da177e4 5131static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5132{
5133 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5134 u32 len, entry, base_flags, mss;
90079ce8
DM		 5135 struct skb_shared_info *sp;
5136 dma_addr_t mapping;
5a6f3074
MC		 5137
5138 len = skb_headlen(skb);
5139
00b70504 5140 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5141 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5142 * interrupt. Furthermore, IRQ processing runs lockless so we have
5143 * no IRQ context deadlocks to worry about either. Rejoice!
5144 */
1b2a7205 5145 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5146 if (!netif_queue_stopped(dev)) {
5147 netif_stop_queue(dev);
5148
5149 /* This is a hard error, log it. */
5150 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5151 "queue awake!\n", dev->name);
5152 }
5a6f3074
MC		 5153 return NETDEV_TX_BUSY;
5154 }
5155
5156 entry = tp->tx_prod;
5157 base_flags = 0;
5a6f3074 5158 mss = 0;
c13e3713 5159 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5160 int tcp_opt_len, ip_tcp_len;
5161
5162 if (skb_header_cloned(skb) &&
5163 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5164 dev_kfree_skb(skb);
5165 goto out_unlock;
5166 }
5167
b0026624
MC		 5168 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5169 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5170 else {
eddc9ec5
ACM		 5171 struct iphdr *iph = ip_hdr(skb);
5172
ab6a5bb6 5173 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5174 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5175
eddc9ec5
ACM		 5176 iph->check = 0;
5177 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5178 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5179 }
5a6f3074
MC		 5180
5181 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5182 TXD_FLAG_CPU_POST_DMA);
5183
aa8223c7 5184 tcp_hdr(skb)->check = 0;
5a6f3074 5185
5a6f3074 5186 }
84fa7933 5187 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5188 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5189#if TG3_VLAN_TAG_USED
5190 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5191 base_flags |= (TXD_FLAG_VLAN |
5192 (vlan_tx_tag_get(skb) << 16));
5193#endif
5194
90079ce8
DM		 5195 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5196 dev_kfree_skb(skb);
5197 goto out_unlock;
5198 }
5199
5200 sp = skb_shinfo(skb);
5201
042a53a9 5202 mapping = sp->dma_head;
5a6f3074
MC		 5203
5204 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5205
5206 tg3_set_txd(tp, entry, mapping, len, base_flags,
5207 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5208
5209 entry = NEXT_TX(entry);
5210
5211 /* Now loop through additional data fragments, and queue them. */
5212 if (skb_shinfo(skb)->nr_frags > 0) {
5213 unsigned int i, last;
5214
5215 last = skb_shinfo(skb)->nr_frags - 1;
5216 for (i = 0; i <= last; i++) {
5217 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5218
5219 len = frag->size;
042a53a9 5220 mapping = sp->dma_maps[i];
5a6f3074 5221 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5222
5223 tg3_set_txd(tp, entry, mapping, len,
5224 base_flags, (i == last) | (mss << 1));
5225
5226 entry = NEXT_TX(entry);
5227 }
5228 }
5229
5230 /* Packets are ready, update Tx producer idx local and on card. */
5231 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5232
5233 tp->tx_prod = entry;
1b2a7205 5234 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5235 netif_stop_queue(dev);
42952231 5236 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5237 netif_wake_queue(tp->dev);
5238 }
5239
5240out_unlock:
cdd0db05 5241 mmiowb();
5a6f3074
MC		 5242
5243 return NETDEV_TX_OK;
5244}
5245
52c0fd83
MC		 5246static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5247
5248/* Use GSO to workaround a rare TSO bug that may be triggered when the
5249 * TSO header is greater than 80 bytes.
5250 */
5251static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5252{
5253 struct sk_buff *segs, *nskb;
5254
5255 /* Estimate the number of fragments in the worst case */
1b2a7205 5256 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5257 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5258 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5259 return NETDEV_TX_BUSY;
5260
5261 netif_wake_queue(tp->dev);
52c0fd83
MC		 5262 }
5263
5264 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5265 if (IS_ERR(segs))
52c0fd83
MC		 5266 goto tg3_tso_bug_end;
5267
5268 do {
5269 nskb = segs;
5270 segs = segs->next;
5271 nskb->next = NULL;
5272 tg3_start_xmit_dma_bug(nskb, tp->dev);
5273 } while (segs);
5274
5275tg3_tso_bug_end:
5276 dev_kfree_skb(skb);
5277
5278 return NETDEV_TX_OK;
5279}
52c0fd83 5280
5a6f3074
MC		 5281/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5282 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5283 */
5284static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5285{
5286 struct tg3 *tp = netdev_priv(dev);
1da177e4 5287 u32 len, entry, base_flags, mss;
90079ce8 5288 struct skb_shared_info *sp;
1da177e4 5289 int would_hit_hwbug;
90079ce8 5290 dma_addr_t mapping;
1da177e4
LT		 5291
5292 len = skb_headlen(skb);
5293
00b70504 5294 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5295 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5296 * interrupt. Furthermore, IRQ processing runs lockless so we have
5297 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5298 */
1b2a7205 5299 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5300 if (!netif_queue_stopped(dev)) {
5301 netif_stop_queue(dev);
5302
5303 /* This is a hard error, log it. */
5304 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5305 "queue awake!\n", dev->name);
5306 }
1da177e4
LT		 5307 return NETDEV_TX_BUSY;
5308 }
5309
5310 entry = tp->tx_prod;
5311 base_flags = 0;
84fa7933 5312 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5313 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5314 mss = 0;
c13e3713 5315 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5316 struct iphdr *iph;
52c0fd83 5317 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5318
5319 if (skb_header_cloned(skb) &&
5320 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5321 dev_kfree_skb(skb);
5322 goto out_unlock;
5323 }
5324
ab6a5bb6 5325 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5326 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5327
52c0fd83
MC		 5328 hdr_len = ip_tcp_len + tcp_opt_len;
5329 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5330 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5331 return (tg3_tso_bug(tp, skb));
5332
1da177e4
LT		 5333 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5334 TXD_FLAG_CPU_POST_DMA);
5335
eddc9ec5
ACM		 5336 iph = ip_hdr(skb);
5337 iph->check = 0;
5338 iph->tot_len = htons(mss + hdr_len);
1da177e4 5339 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5340 tcp_hdr(skb)->check = 0;
1da177e4 5341 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5342 } else
5343 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5344 iph->daddr, 0,
5345 IPPROTO_TCP,
5346 0);
1da177e4
LT		 5347
5348 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5349 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5350 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5351 int tsflags;
5352
eddc9ec5 5353 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5354 mss |= (tsflags << 11);
5355 }
5356 } else {
eddc9ec5 5357 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5358 int tsflags;
5359
eddc9ec5 5360 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5361 base_flags |= tsflags << 12;
5362 }
5363 }
5364 }
1da177e4
LT		 5365#if TG3_VLAN_TAG_USED
5366 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5367 base_flags |= (TXD_FLAG_VLAN |
5368 (vlan_tx_tag_get(skb) << 16));
5369#endif
5370
90079ce8
DM		 5371 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5372 dev_kfree_skb(skb);
5373 goto out_unlock;
5374 }
5375
5376 sp = skb_shinfo(skb);
5377
042a53a9 5378 mapping = sp->dma_head;
1da177e4
LT		 5379
5380 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5381
5382 would_hit_hwbug = 0;
5383
41588ba1
MC		 5384 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5385 would_hit_hwbug = 1;
5386 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5387 would_hit_hwbug = 1;
1da177e4
LT		 5388
5389 tg3_set_txd(tp, entry, mapping, len, base_flags,
5390 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5391
5392 entry = NEXT_TX(entry);
5393
5394 /* Now loop through additional data fragments, and queue them. */
5395 if (skb_shinfo(skb)->nr_frags > 0) {
5396 unsigned int i, last;
5397
5398 last = skb_shinfo(skb)->nr_frags - 1;
5399 for (i = 0; i <= last; i++) {
5400 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5401
5402 len = frag->size;
042a53a9 5403 mapping = sp->dma_maps[i];
1da177e4
LT		 5404
5405 tp->tx_buffers[entry].skb = NULL;
1da177e4 5406
c58ec932
MC		 5407 if (tg3_4g_overflow_test(mapping, len))
5408 would_hit_hwbug = 1;
1da177e4 5409
72f2afb8
MC		 5410 if (tg3_40bit_overflow_test(tp, mapping, len))
5411 would_hit_hwbug = 1;
5412
1da177e4
LT		 5413 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5414 tg3_set_txd(tp, entry, mapping, len,
5415 base_flags, (i == last)|(mss << 1));
5416 else
5417 tg3_set_txd(tp, entry, mapping, len,
5418 base_flags, (i == last));
5419
5420 entry = NEXT_TX(entry);
5421 }
5422 }
5423
5424 if (would_hit_hwbug) {
5425 u32 last_plus_one = entry;
5426 u32 start;
1da177e4 5427
c58ec932
MC		 5428 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5429 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5430
5431 /* If the workaround fails due to memory/mapping
5432 * failure, silently drop this packet.
5433 */
72f2afb8 5434 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5435 &start, base_flags, mss))
1da177e4
LT		 5436 goto out_unlock;
5437
5438 entry = start;
5439 }
5440
5441 /* Packets are ready, update Tx producer idx local and on card. */
5442 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5443
5444 tp->tx_prod = entry;
1b2a7205 5445 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5446 netif_stop_queue(dev);
42952231 5447 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5448 netif_wake_queue(tp->dev);
5449 }
1da177e4
LT		 5450
5451out_unlock:
cdd0db05 5452 mmiowb();
1da177e4
LT		 5453
5454 return NETDEV_TX_OK;
5455}
5456
5457static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5458 int new_mtu)
5459{
5460 dev->mtu = new_mtu;
5461
ef7f5ec0 5462 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5463 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5464 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5465 ethtool_op_set_tso(dev, 0);
5466 }
5467 else
5468 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5469 } else {
a4e2b347 5470 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5471 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5472 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5473 }
1da177e4
LT		 5474}
5475
5476static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5477{
5478 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5479 int err;
1da177e4
LT		 5480
5481 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5482 return -EINVAL;
5483
5484 if (!netif_running(dev)) {
5485 /* We'll just catch it later when the
5486 * device is up'd.
5487 */
5488 tg3_set_mtu(dev, tp, new_mtu);
5489 return 0;
5490 }
5491
b02fd9e3
MC		 5492 tg3_phy_stop(tp);
5493
1da177e4 5494 tg3_netif_stop(tp);
f47c11ee
DM		 5495
5496 tg3_full_lock(tp, 1);
1da177e4 5497
944d980e 5498 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5499
5500 tg3_set_mtu(dev, tp, new_mtu);
5501
b9ec6c1b 5502 err = tg3_restart_hw(tp, 0);
1da177e4 5503
b9ec6c1b
MC		 5504 if (!err)
5505 tg3_netif_start(tp);
1da177e4 5506
f47c11ee 5507 tg3_full_unlock(tp);
1da177e4 5508
b02fd9e3
MC		 5509 if (!err)
5510 tg3_phy_start(tp);
5511
b9ec6c1b 5512 return err;
1da177e4
LT		 5513}
5514
21f581a5
MC		 5515static void tg3_rx_prodring_free(struct tg3 *tp,
5516 struct tg3_rx_prodring_set *tpr)
1da177e4
LT		 5517{
5518 struct ring_info *rxp;
5519 int i;
5520
5521 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5522 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5523
5524 if (rxp->skb == NULL)
5525 continue;
1da177e4 5526
1da177e4
LT		 5527 pci_unmap_single(tp->pdev,
5528 pci_unmap_addr(rxp, mapping),
cf7a7298 5529 tp->rx_pkt_map_sz,
1da177e4
LT		 5530 PCI_DMA_FROMDEVICE);
5531 dev_kfree_skb_any(rxp->skb);
5532 rxp->skb = NULL;
5533 }
5534
cf7a7298
MC		 5535 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5536 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5537 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5538
cf7a7298
MC		 5539 if (rxp->skb == NULL)
5540 continue;
1da177e4 5541
cf7a7298
MC		 5542 pci_unmap_single(tp->pdev,
5543 pci_unmap_addr(rxp, mapping),
5544 TG3_RX_JMB_MAP_SZ,
5545 PCI_DMA_FROMDEVICE);
5546 dev_kfree_skb_any(rxp->skb);
5547 rxp->skb = NULL;
1da177e4 5548 }
1da177e4
LT		 5549 }
5550}
5551
5552/* Initialize tx/rx rings for packet processing.
5553 *
5554 * The chip has been shut down and the driver detached from
5555 * the networking, so no interrupts or new tx packets will
5556 * end up in the driver. tp->{tx,}lock are held and thus
5557 * we may not sleep.
5558 */
21f581a5
MC		 5559static int tg3_rx_prodring_alloc(struct tg3 *tp,
5560 struct tg3_rx_prodring_set *tpr)
1da177e4 5561{
287be12e 5562 u32 i, rx_pkt_dma_sz;
1da177e4 5563
1da177e4 5564 /* Zero out all descriptors. */
21f581a5 5565 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5566
287be12e 5567 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5568 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5569 tp->dev->mtu > ETH_DATA_LEN)
5570 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5571 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5572
1da177e4
LT		 5573 /* Initialize invariants of the rings, we only set this
5574 * stuff once. This works because the card does not
5575 * write into the rx buffer posting rings.
5576 */
5577 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5578 struct tg3_rx_buffer_desc *rxd;
5579
21f581a5 5580 rxd = &tpr->rx_std[i];
287be12e 5581 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5582 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5583 rxd->opaque = (RXD_OPAQUE_RING_STD |
5584 (i << RXD_OPAQUE_INDEX_SHIFT));
5585 }
5586
1da177e4
LT		 5587 /* Now allocate fresh SKBs for each rx ring. */
5588 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5589 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5590 printk(KERN_WARNING PFX
5591 "%s: Using a smaller RX standard ring, "
5592 "only %d out of %d buffers were allocated "
5593 "successfully.\n",
5594 tp->dev->name, i, tp->rx_pending);
5595 if (i == 0)
cf7a7298 5596 goto initfail;
32d8c572 5597 tp->rx_pending = i;
1da177e4 5598 break;
32d8c572 5599 }
1da177e4
LT		 5600 }
5601
cf7a7298
MC		 5602 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5603 goto done;
5604
21f581a5 5605 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5606
0f893dc6 5607 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5608 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5609 struct tg3_rx_buffer_desc *rxd;
5610
79ed5ac7 5611 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5612 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5613 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5614 RXD_FLAG_JUMBO;
5615 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5616 (i << RXD_OPAQUE_INDEX_SHIFT));
5617 }
5618
1da177e4
LT		 5619 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5620 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5621 -1, i) < 0) {
5622 printk(KERN_WARNING PFX
5623 "%s: Using a smaller RX jumbo ring, "
5624 "only %d out of %d buffers were "
5625 "allocated successfully.\n",
5626 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5627 if (i == 0)
5628 goto initfail;
32d8c572 5629 tp->rx_jumbo_pending = i;
1da177e4 5630 break;
32d8c572 5631 }
1da177e4
LT		 5632 }
5633 }
cf7a7298
MC		 5634
5635done:
32d8c572 5636 return 0;
cf7a7298
MC		 5637
5638initfail:
21f581a5 5639 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5640 return -ENOMEM;
1da177e4
LT		 5641}
5642
21f581a5
MC		 5643static void tg3_rx_prodring_fini(struct tg3 *tp,
5644 struct tg3_rx_prodring_set *tpr)
1da177e4 5645{
21f581a5
MC		 5646 kfree(tpr->rx_std_buffers);
5647 tpr->rx_std_buffers = NULL;
5648 kfree(tpr->rx_jmb_buffers);
5649 tpr->rx_jmb_buffers = NULL;
5650 if (tpr->rx_std) {
1da177e4 5651 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5652 tpr->rx_std, tpr->rx_std_mapping);
5653 tpr->rx_std = NULL;
1da177e4 5654 }
21f581a5 5655 if (tpr->rx_jmb) {
1da177e4 5656 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5657 tpr->rx_jmb, tpr->rx_jmb_mapping);
5658 tpr->rx_jmb = NULL;
1da177e4 5659 }
cf7a7298
MC		 5660}
5661
21f581a5
MC		 5662static int tg3_rx_prodring_init(struct tg3 *tp,
5663 struct tg3_rx_prodring_set *tpr)
cf7a7298 5664{
21f581a5
MC		 5665 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5666 TG3_RX_RING_SIZE, GFP_KERNEL);
5667 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5668 return -ENOMEM;
5669
21f581a5
MC		 5670 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5671 &tpr->rx_std_mapping);
5672 if (!tpr->rx_std)
cf7a7298
MC		 5673 goto err_out;
5674
5675 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5676 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5677 TG3_RX_JUMBO_RING_SIZE,
5678 GFP_KERNEL);
5679 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5680 goto err_out;
5681
21f581a5
MC		 5682 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5683 TG3_RX_JUMBO_RING_BYTES,
5684 &tpr->rx_jmb_mapping);
5685 if (!tpr->rx_jmb)
cf7a7298
MC		 5686 goto err_out;
5687 }
5688
5689 return 0;
5690
5691err_out:
21f581a5 5692 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5693 return -ENOMEM;
5694}
5695
5696/* Free up pending packets in all rx/tx rings.
5697 *
5698 * The chip has been shut down and the driver detached from
5699 * the networking, so no interrupts or new tx packets will
5700 * end up in the driver. tp->{tx,}lock is not held and we are not
5701 * in an interrupt context and thus may sleep.
5702 */
5703static void tg3_free_rings(struct tg3 *tp)
5704{
5705 int i;
5706
5707 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5708 struct tx_ring_info *txp;
5709 struct sk_buff *skb;
5710
5711 txp = &tp->tx_buffers[i];
5712 skb = txp->skb;
5713
5714 if (skb == NULL) {
5715 i++;
5716 continue;
5717 }
5718
5719 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5720
5721 txp->skb = NULL;
5722
5723 i += skb_shinfo(skb)->nr_frags + 1;
5724
5725 dev_kfree_skb_any(skb);
5726 }
5727
21f581a5 5728 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5729}
5730
5731/* Initialize tx/rx rings for packet processing.
5732 *
5733 * The chip has been shut down and the driver detached from
5734 * the networking, so no interrupts or new tx packets will
5735 * end up in the driver. tp->{tx,}lock are held and thus
5736 * we may not sleep.
5737 */
5738static int tg3_init_rings(struct tg3 *tp)
5739{
5740 /* Free up all the SKBs. */
5741 tg3_free_rings(tp);
5742
5743 /* Zero out all descriptors. */
5744 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5745 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5746
21f581a5 5747 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5748}
5749
5750/*
5751 * Must not be invoked with interrupt sources disabled and
5752 * the hardware shutdown down.
5753 */
5754static void tg3_free_consistent(struct tg3 *tp)
5755{
5756 kfree(tp->tx_buffers);
5757 tp->tx_buffers = NULL;
1da177e4
LT		 5758 if (tp->rx_rcb) {
5759 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5760 tp->rx_rcb, tp->rx_rcb_mapping);
5761 tp->rx_rcb = NULL;
5762 }
5763 if (tp->tx_ring) {
5764 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5765 tp->tx_ring, tp->tx_desc_mapping);
5766 tp->tx_ring = NULL;
5767 }
5768 if (tp->hw_status) {
5769 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5770 tp->hw_status, tp->status_mapping);
5771 tp->hw_status = NULL;
5772 }
5773 if (tp->hw_stats) {
5774 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5775 tp->hw_stats, tp->stats_mapping);
5776 tp->hw_stats = NULL;
5777 }
21f581a5 5778 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5779}
5780
5781/*
5782 * Must not be invoked with interrupt sources disabled and
5783 * the hardware shutdown down. Can sleep.
5784 */
5785static int tg3_alloc_consistent(struct tg3 *tp)
5786{
21f581a5 5787 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5788 return -ENOMEM;
5789
cf7a7298
MC		 5790 tp->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5791 TG3_TX_RING_SIZE, GFP_KERNEL);
5792 if (!tp->tx_buffers)
1da177e4
LT		 5793 goto err_out;
5794
5795 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5796 &tp->rx_rcb_mapping);
5797 if (!tp->rx_rcb)
5798 goto err_out;
5799
5800 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5801 &tp->tx_desc_mapping);
5802 if (!tp->tx_ring)
5803 goto err_out;
5804
5805 tp->hw_status = pci_alloc_consistent(tp->pdev,
5806 TG3_HW_STATUS_SIZE,
5807 &tp->status_mapping);
5808 if (!tp->hw_status)
5809 goto err_out;
5810
5811 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5812 sizeof(struct tg3_hw_stats),
5813 &tp->stats_mapping);
5814 if (!tp->hw_stats)
5815 goto err_out;
5816
5817 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5818 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5819
5820 return 0;
5821
5822err_out:
5823 tg3_free_consistent(tp);
5824 return -ENOMEM;
5825}
5826
5827#define MAX_WAIT_CNT 1000
5828
5829/* To stop a block, clear the enable bit and poll till it
5830 * clears. tp->lock is held.
5831 */
b3b7d6be 5832static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5833{
5834 unsigned int i;
5835 u32 val;
5836
5837 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5838 switch (ofs) {
5839 case RCVLSC_MODE:
5840 case DMAC_MODE:
5841 case MBFREE_MODE:
5842 case BUFMGR_MODE:
5843 case MEMARB_MODE:
5844 /* We can't enable/disable these bits of the
5845 * 5705/5750, just say success.
5846 */
5847 return 0;
5848
5849 default:
5850 break;
855e1111 5851 }
1da177e4
LT		 5852 }
5853
5854 val = tr32(ofs);
5855 val &= ~enable_bit;
5856 tw32_f(ofs, val);
5857
5858 for (i = 0; i < MAX_WAIT_CNT; i++) {
5859 udelay(100);
5860 val = tr32(ofs);
5861 if ((val & enable_bit) == 0)
5862 break;
5863 }
5864
b3b7d6be 5865 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5866 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5867 "ofs=%lx enable_bit=%x\n",
5868 ofs, enable_bit);
5869 return -ENODEV;
5870 }
5871
5872 return 0;
5873}
5874
5875/* tp->lock is held. */
b3b7d6be 5876static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5877{
5878 int i, err;
5879
5880 tg3_disable_ints(tp);
5881
5882 tp->rx_mode &= ~RX_MODE_ENABLE;
5883 tw32_f(MAC_RX_MODE, tp->rx_mode);
5884 udelay(10);
5885
b3b7d6be
DM		 5886 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5887 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5888 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5889 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5890 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5891 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5892
5893 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5894 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5895 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5896 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5897 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5898 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5899 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5900
5901 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5902 tw32_f(MAC_MODE, tp->mac_mode);
5903 udelay(40);
5904
5905 tp->tx_mode &= ~TX_MODE_ENABLE;
5906 tw32_f(MAC_TX_MODE, tp->tx_mode);
5907
5908 for (i = 0; i < MAX_WAIT_CNT; i++) {
5909 udelay(100);
5910 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5911 break;
5912 }
5913 if (i >= MAX_WAIT_CNT) {
5914 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5915 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5916 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5917 err |= -ENODEV;
1da177e4
LT		 5918 }
5919
e6de8ad1 5920 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5921 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5922 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5923
5924 tw32(FTQ_RESET, 0xffffffff);
5925 tw32(FTQ_RESET, 0x00000000);
5926
b3b7d6be
DM		 5927 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5928 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5929
5930 if (tp->hw_status)
5931 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5932 if (tp->hw_stats)
5933 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5934
1da177e4
LT		 5935 return err;
5936}
5937
0d3031d9
MC		 5938static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5939{
5940 int i;
5941 u32 apedata;
5942
5943 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5944 if (apedata != APE_SEG_SIG_MAGIC)
5945 return;
5946
5947 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5948 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5949 return;
5950
5951 /* Wait for up to 1 millisecond for APE to service previous event. */
5952 for (i = 0; i < 10; i++) {
5953 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5954 return;
5955
5956 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5957
5958 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5959 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5960 event | APE_EVENT_STATUS_EVENT_PENDING);
5961
5962 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5963
5964 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5965 break;
5966
5967 udelay(100);
5968 }
5969
5970 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5971 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5972}
5973
5974static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5975{
5976 u32 event;
5977 u32 apedata;
5978
5979 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5980 return;
5981
5982 switch (kind) {
5983 case RESET_KIND_INIT:
5984 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5985 APE_HOST_SEG_SIG_MAGIC);
5986 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5987 APE_HOST_SEG_LEN_MAGIC);
5988 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5989 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5990 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5991 APE_HOST_DRIVER_ID_MAGIC);
5992 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5993 APE_HOST_BEHAV_NO_PHYLOCK);
5994
5995 event = APE_EVENT_STATUS_STATE_START;
5996 break;
5997 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5998 /* With the interface we are currently using,
5999 * APE does not track driver state. Wiping
6000 * out the HOST SEGMENT SIGNATURE forces
6001 * the APE to assume OS absent status.
6002 */
6003 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6004
0d3031d9
MC		 6005 event = APE_EVENT_STATUS_STATE_UNLOAD;
6006 break;
6007 case RESET_KIND_SUSPEND:
6008 event = APE_EVENT_STATUS_STATE_SUSPEND;
6009 break;
6010 default:
6011 return;
6012 }
6013
6014 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6015
6016 tg3_ape_send_event(tp, event);
6017}
6018
1da177e4
LT		 6019/* tp->lock is held. */
6020static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6021{
f49639e6
DM		 6022 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6023 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6024
6025 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6026 switch (kind) {
6027 case RESET_KIND_INIT:
6028 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6029 DRV_STATE_START);
6030 break;
6031
6032 case RESET_KIND_SHUTDOWN:
6033 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6034 DRV_STATE_UNLOAD);
6035 break;
6036
6037 case RESET_KIND_SUSPEND:
6038 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6039 DRV_STATE_SUSPEND);
6040 break;
6041
6042 default:
6043 break;
855e1111 6044 }
1da177e4 6045 }
0d3031d9
MC		 6046
6047 if (kind == RESET_KIND_INIT ||
6048 kind == RESET_KIND_SUSPEND)
6049 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6050}
6051
6052/* tp->lock is held. */
6053static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6054{
6055 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6056 switch (kind) {
6057 case RESET_KIND_INIT:
6058 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6059 DRV_STATE_START_DONE);
6060 break;
6061
6062 case RESET_KIND_SHUTDOWN:
6063 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6064 DRV_STATE_UNLOAD_DONE);
6065 break;
6066
6067 default:
6068 break;
855e1111 6069 }
1da177e4 6070 }
0d3031d9
MC		 6071
6072 if (kind == RESET_KIND_SHUTDOWN)
6073 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6074}
6075
6076/* tp->lock is held. */
6077static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6078{
6079 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6080 switch (kind) {
6081 case RESET_KIND_INIT:
6082 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6083 DRV_STATE_START);
6084 break;
6085
6086 case RESET_KIND_SHUTDOWN:
6087 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6088 DRV_STATE_UNLOAD);
6089 break;
6090
6091 case RESET_KIND_SUSPEND:
6092 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6093 DRV_STATE_SUSPEND);
6094 break;
6095
6096 default:
6097 break;
855e1111 6098 }
1da177e4
LT		 6099 }
6100}
6101
7a6f4369
MC		 6102static int tg3_poll_fw(struct tg3 *tp)
6103{
6104 int i;
6105 u32 val;
6106
b5d3772c 6107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6108 /* Wait up to 20ms for init done. */
6109 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6110 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6111 return 0;
0ccead18 6112 udelay(100);
b5d3772c
MC		 6113 }
6114 return -ENODEV;
6115 }
6116
7a6f4369
MC		 6117 /* Wait for firmware initialization to complete. */
6118 for (i = 0; i < 100000; i++) {
6119 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6120 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6121 break;
6122 udelay(10);
6123 }
6124
6125 /* Chip might not be fitted with firmware. Some Sun onboard
6126 * parts are configured like that. So don't signal the timeout
6127 * of the above loop as an error, but do report the lack of
6128 * running firmware once.
6129 */
6130 if (i >= 100000 &&
6131 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6132 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6133
6134 printk(KERN_INFO PFX "%s: No firmware running.\n",
6135 tp->dev->name);
6136 }
6137
6138 return 0;
6139}
6140
ee6a99b5
MC		 6141/* Save PCI command register before chip reset */
6142static void tg3_save_pci_state(struct tg3 *tp)
6143{
8a6eac90 6144 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6145}
6146
6147/* Restore PCI state after chip reset */
6148static void tg3_restore_pci_state(struct tg3 *tp)
6149{
6150 u32 val;
6151
6152 /* Re-enable indirect register accesses. */
6153 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6154 tp->misc_host_ctrl);
6155
6156 /* Set MAX PCI retry to zero. */
6157 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6158 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6159 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6160 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6161 /* Allow reads and writes to the APE register and memory space. */
6162 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6163 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6164 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6165 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6166
8a6eac90 6167 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6168
fcb389df
MC		 6169 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6170 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6171 pcie_set_readrq(tp->pdev, 4096);
6172 else {
6173 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6174 tp->pci_cacheline_sz);
6175 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6176 tp->pci_lat_timer);
6177 }
114342f2 6178 }
5f5c51e3 6179
ee6a99b5 6180 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6181 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6182 u16 pcix_cmd;
6183
6184 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6185 &pcix_cmd);
6186 pcix_cmd &= ~PCI_X_CMD_ERO;
6187 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6188 pcix_cmd);
6189 }
ee6a99b5
MC		 6190
6191 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6192
6193 /* Chip reset on 5780 will reset MSI enable bit,
6194 * so need to restore it.
6195 */
6196 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6197 u16 ctrl;
6198
6199 pci_read_config_word(tp->pdev,
6200 tp->msi_cap + PCI_MSI_FLAGS,
6201 &ctrl);
6202 pci_write_config_word(tp->pdev,
6203 tp->msi_cap + PCI_MSI_FLAGS,
6204 ctrl | PCI_MSI_FLAGS_ENABLE);
6205 val = tr32(MSGINT_MODE);
6206 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6207 }
6208 }
6209}
6210
1da177e4
LT		 6211static void tg3_stop_fw(struct tg3 *);
6212
6213/* tp->lock is held. */
6214static int tg3_chip_reset(struct tg3 *tp)
6215{
6216 u32 val;
1ee582d8 6217 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6218 int err;
1da177e4 6219
f49639e6
DM		 6220 tg3_nvram_lock(tp);
6221
158d7abd
MC		 6222 tg3_mdio_stop(tp);
6223
77b483f1
MC		 6224 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6225
f49639e6
DM		 6226 /* No matching tg3_nvram_unlock() after this because
6227 * chip reset below will undo the nvram lock.
6228 */
6229 tp->nvram_lock_cnt = 0;
1da177e4 6230
ee6a99b5
MC		 6231 /* GRC_MISC_CFG core clock reset will clear the memory
6232 * enable bit in PCI register 4 and the MSI enable bit
6233 * on some chips, so we save relevant registers here.
6234 */
6235 tg3_save_pci_state(tp);
6236
d9ab5ad1 6237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6238 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6239 tw32(GRC_FASTBOOT_PC, 0);
6240
1da177e4
LT		 6241 /*
6242 * We must avoid the readl() that normally takes place.
6243 * It locks machines, causes machine checks, and other
6244 * fun things. So, temporarily disable the 5701
6245 * hardware workaround, while we do the reset.
6246 */
1ee582d8
MC		 6247 write_op = tp->write32;
6248 if (write_op == tg3_write_flush_reg32)
6249 tp->write32 = tg3_write32;
1da177e4 6250
d18edcb2
MC		 6251 /* Prevent the irq handler from reading or writing PCI registers
6252 * during chip reset when the memory enable bit in the PCI command
6253 * register may be cleared. The chip does not generate interrupt
6254 * at this time, but the irq handler may still be called due to irq
6255 * sharing or irqpoll.
6256 */
6257 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6258 if (tp->hw_status) {
6259 tp->hw_status->status = 0;
6260 tp->hw_status->status_tag = 0;
6261 }
d18edcb2 6262 tp->last_tag = 0;
624f8e50 6263 tp->last_irq_tag = 0;
d18edcb2
MC		 6264 smp_mb();
6265 synchronize_irq(tp->pdev->irq);
6266
255ca311
MC		 6267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6268 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6269 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6270 }
6271
1da177e4
LT		 6272 /* do the reset */
6273 val = GRC_MISC_CFG_CORECLK_RESET;
6274
6275 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6276 if (tr32(0x7e2c) == 0x60) {
6277 tw32(0x7e2c, 0x20);
6278 }
6279 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6280 tw32(GRC_MISC_CFG, (1 << 29));
6281 val |= (1 << 29);
6282 }
6283 }
6284
b5d3772c
MC		 6285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6286 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6287 tw32(GRC_VCPU_EXT_CTRL,
6288 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6289 }
6290
1da177e4
LT		 6291 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6292 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6293 tw32(GRC_MISC_CFG, val);
6294
1ee582d8
MC		 6295 /* restore 5701 hardware bug workaround write method */
6296 tp->write32 = write_op;
1da177e4
LT		 6297
6298 /* Unfortunately, we have to delay before the PCI read back.
6299 * Some 575X chips even will not respond to a PCI cfg access
6300 * when the reset command is given to the chip.
6301 *
6302 * How do these hardware designers expect things to work
6303 * properly if the PCI write is posted for a long period
6304 * of time? It is always necessary to have some method by
6305 * which a register read back can occur to push the write
6306 * out which does the reset.
6307 *
6308 * For most tg3 variants the trick below was working.
6309 * Ho hum...
6310 */
6311 udelay(120);
6312
6313 /* Flush PCI posted writes. The normal MMIO registers
6314 * are inaccessible at this time so this is the only
6315 * way to make this reliably (actually, this is no longer
6316 * the case, see above). I tried to use indirect
6317 * register read/write but this upset some 5701 variants.
6318 */
6319 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6320
6321 udelay(120);
6322
5e7dfd0f 6323 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6324 u16 val16;
6325
1da177e4
LT		 6326 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6327 int i;
6328 u32 cfg_val;
6329
6330 /* Wait for link training to complete. */
6331 for (i = 0; i < 5000; i++)
6332 udelay(100);
6333
6334 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6335 pci_write_config_dword(tp->pdev, 0xc4,
6336 cfg_val | (1 << 15));
6337 }
5e7dfd0f 6338
e7126997
MC		 6339 /* Clear the "no snoop" and "relaxed ordering" bits. */
6340 pci_read_config_word(tp->pdev,
6341 tp->pcie_cap + PCI_EXP_DEVCTL,
6342 &val16);
6343 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6344 PCI_EXP_DEVCTL_NOSNOOP_EN);
6345 /*
6346 * Older PCIe devices only support the 128 byte
6347 * MPS setting. Enforce the restriction.
5e7dfd0f 6348 */
e7126997
MC		 6349 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6350 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6351 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6352 pci_write_config_word(tp->pdev,
6353 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6354 val16);
5e7dfd0f
MC		 6355
6356 pcie_set_readrq(tp->pdev, 4096);
6357
6358 /* Clear error status */
6359 pci_write_config_word(tp->pdev,
6360 tp->pcie_cap + PCI_EXP_DEVSTA,
6361 PCI_EXP_DEVSTA_CED |
6362 PCI_EXP_DEVSTA_NFED |
6363 PCI_EXP_DEVSTA_FED |
6364 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6365 }
6366
ee6a99b5 6367 tg3_restore_pci_state(tp);
1da177e4 6368
d18edcb2
MC		 6369 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6370
ee6a99b5
MC		 6371 val = 0;
6372 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6373 val = tr32(MEMARB_MODE);
ee6a99b5 6374 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6375
6376 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6377 tg3_stop_fw(tp);
6378 tw32(0x5000, 0x400);
6379 }
6380
6381 tw32(GRC_MODE, tp->grc_mode);
6382
6383 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6384 val = tr32(0xc4);
1da177e4
LT		 6385
6386 tw32(0xc4, val | (1 << 15));
6387 }
6388
6389 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6390 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6391 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6392 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6393 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6394 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6395 }
6396
6397 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6398 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6399 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6400 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6401 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6402 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6403 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6404 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6405 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6406 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6407 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6408 } else
6409 tw32_f(MAC_MODE, 0);
6410 udelay(40);
6411
77b483f1
MC		 6412 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6413
7a6f4369
MC		 6414 err = tg3_poll_fw(tp);
6415 if (err)
6416 return err;
1da177e4 6417
0a9140cf
MC		 6418 tg3_mdio_start(tp);
6419
1da177e4
LT		 6420 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6421 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6422 val = tr32(0x7c00);
1da177e4
LT		 6423
6424 tw32(0x7c00, val | (1 << 25));
6425 }
6426
6427 /* Reprobe ASF enable state. */
6428 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6429 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6430 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6431 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6432 u32 nic_cfg;
6433
6434 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6435 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6436 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6437 tp->last_event_jiffies = jiffies;
cbf46853 6438 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6439 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6440 }
6441 }
6442
6443 return 0;
6444}
6445
6446/* tp->lock is held. */
6447static void tg3_stop_fw(struct tg3 *tp)
6448{
0d3031d9
MC		 6449 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6450 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6451 /* Wait for RX cpu to ACK the previous event. */
6452 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6453
6454 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6455
6456 tg3_generate_fw_event(tp);
1da177e4 6457
7c5026aa
MC		 6458 /* Wait for RX cpu to ACK this event. */
6459 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6460 }
6461}
6462
6463/* tp->lock is held. */
944d980e 6464static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6465{
6466 int err;
6467
6468 tg3_stop_fw(tp);
6469
944d980e 6470 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6471
b3b7d6be 6472 tg3_abort_hw(tp, silent);
1da177e4
LT		 6473 err = tg3_chip_reset(tp);
6474
daba2a63
MC		 6475 __tg3_set_mac_addr(tp, 0);
6476
944d980e
MC		 6477 tg3_write_sig_legacy(tp, kind);
6478 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6479
6480 if (err)
6481 return err;
6482
6483 return 0;
6484}
6485
1da177e4
LT		 6486#define RX_CPU_SCRATCH_BASE 0x30000
6487#define RX_CPU_SCRATCH_SIZE 0x04000
6488#define TX_CPU_SCRATCH_BASE 0x34000
6489#define TX_CPU_SCRATCH_SIZE 0x04000
6490
6491/* tp->lock is held. */
6492static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6493{
6494 int i;
6495
5d9428de
ES		 6496 BUG_ON(offset == TX_CPU_BASE &&
6497 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6498
b5d3772c
MC		 6499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6500 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6501
6502 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6503 return 0;
6504 }
1da177e4
LT		 6505 if (offset == RX_CPU_BASE) {
6506 for (i = 0; i < 10000; i++) {
6507 tw32(offset + CPU_STATE, 0xffffffff);
6508 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6509 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6510 break;
6511 }
6512
6513 tw32(offset + CPU_STATE, 0xffffffff);
6514 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6515 udelay(10);
6516 } else {
6517 for (i = 0; i < 10000; i++) {
6518 tw32(offset + CPU_STATE, 0xffffffff);
6519 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6520 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6521 break;
6522 }
6523 }
6524
6525 if (i >= 10000) {
6526 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6527 "and %s CPU\n",
6528 tp->dev->name,
6529 (offset == RX_CPU_BASE ? "RX" : "TX"));
6530 return -ENODEV;
6531 }
ec41c7df
MC		 6532
6533 /* Clear firmware's nvram arbitration. */
6534 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6535 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6536 return 0;
6537}
6538
6539struct fw_info {
077f849d
JSR		 6540 unsigned int fw_base;
6541 unsigned int fw_len;
6542 const __be32 *fw_data;
1da177e4
LT		 6543};
6544
6545/* tp->lock is held. */
6546static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6547 int cpu_scratch_size, struct fw_info *info)
6548{
ec41c7df 6549 int err, lock_err, i;
1da177e4
LT		 6550 void (*write_op)(struct tg3 *, u32, u32);
6551
6552 if (cpu_base == TX_CPU_BASE &&
6553 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6554 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6555 "TX cpu firmware on %s which is 5705.\n",
6556 tp->dev->name);
6557 return -EINVAL;
6558 }
6559
6560 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6561 write_op = tg3_write_mem;
6562 else
6563 write_op = tg3_write_indirect_reg32;
6564
1b628151
MC		 6565 /* It is possible that bootcode is still loading at this point.
6566 * Get the nvram lock first before halting the cpu.
6567 */
ec41c7df 6568 lock_err = tg3_nvram_lock(tp);
1da177e4 6569 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6570 if (!lock_err)
6571 tg3_nvram_unlock(tp);
1da177e4
LT		 6572 if (err)
6573 goto out;
6574
6575 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6576 write_op(tp, cpu_scratch_base + i, 0);
6577 tw32(cpu_base + CPU_STATE, 0xffffffff);
6578 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6579 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6580 write_op(tp, (cpu_scratch_base +
077f849d 6581 (info->fw_base & 0xffff) +
1da177e4 6582 (i * sizeof(u32))),
077f849d 6583 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6584
6585 err = 0;
6586
6587out:
1da177e4
LT		 6588 return err;
6589}
6590
6591/* tp->lock is held. */
6592static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6593{
6594 struct fw_info info;
077f849d 6595 const __be32 *fw_data;
1da177e4
LT		 6596 int err, i;
6597
077f849d
JSR		 6598 fw_data = (void *)tp->fw->data;
6599
6600 /* Firmware blob starts with version numbers, followed by
6601 start address and length. We are setting complete length.
6602 length = end_address_of_bss - start_address_of_text.
6603 Remainder is the blob to be loaded contiguously
6604 from start address. */
6605
6606 info.fw_base = be32_to_cpu(fw_data[1]);
6607 info.fw_len = tp->fw->size - 12;
6608 info.fw_data = &fw_data[3];
1da177e4
LT		 6609
6610 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6611 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6612 &info);
6613 if (err)
6614 return err;
6615
6616 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6617 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6618 &info);
6619 if (err)
6620 return err;
6621
6622 /* Now startup only the RX cpu. */
6623 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6624 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6625
6626 for (i = 0; i < 5; i++) {
077f849d 6627 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6628 break;
6629 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6630 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6631 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6632 udelay(1000);
6633 }
6634 if (i >= 5) {
6635 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6636 "to set RX CPU PC, is %08x should be %08x\n",
6637 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6638 info.fw_base);
1da177e4
LT		 6639 return -ENODEV;
6640 }
6641 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6642 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6643
6644 return 0;
6645}
6646
1da177e4 6647/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6648
6649/* tp->lock is held. */
6650static int tg3_load_tso_firmware(struct tg3 *tp)
6651{
6652 struct fw_info info;
077f849d 6653 const __be32 *fw_data;
1da177e4
LT		 6654 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6655 int err, i;
6656
6657 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6658 return 0;
6659
077f849d
JSR		 6660 fw_data = (void *)tp->fw->data;
6661
6662 /* Firmware blob starts with version numbers, followed by
6663 start address and length. We are setting complete length.
6664 length = end_address_of_bss - start_address_of_text.
6665 Remainder is the blob to be loaded contiguously
6666 from start address. */
6667
6668 info.fw_base = be32_to_cpu(fw_data[1]);
6669 cpu_scratch_size = tp->fw_len;
6670 info.fw_len = tp->fw->size - 12;
6671 info.fw_data = &fw_data[3];
6672
1da177e4 6673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6674 cpu_base = RX_CPU_BASE;
6675 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6676 } else {
1da177e4
LT		 6677 cpu_base = TX_CPU_BASE;
6678 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6679 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6680 }
6681
6682 err = tg3_load_firmware_cpu(tp, cpu_base,
6683 cpu_scratch_base, cpu_scratch_size,
6684 &info);
6685 if (err)
6686 return err;
6687
6688 /* Now startup the cpu. */
6689 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6690 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6691
6692 for (i = 0; i < 5; i++) {
077f849d 6693 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6694 break;
6695 tw32(cpu_base + CPU_STATE, 0xffffffff);
6696 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6697 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6698 udelay(1000);
6699 }
6700 if (i >= 5) {
6701 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6702 "to set CPU PC, is %08x should be %08x\n",
6703 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6704 info.fw_base);
1da177e4
LT		 6705 return -ENODEV;
6706 }
6707 tw32(cpu_base + CPU_STATE, 0xffffffff);
6708 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6709 return 0;
6710}
6711
1da177e4 6712
1da177e4
LT		 6713static int tg3_set_mac_addr(struct net_device *dev, void *p)
6714{
6715 struct tg3 *tp = netdev_priv(dev);
6716 struct sockaddr *addr = p;
986e0aeb 6717 int err = 0, skip_mac_1 = 0;
1da177e4 6718
f9804ddb
MC		 6719 if (!is_valid_ether_addr(addr->sa_data))
6720 return -EINVAL;
6721
1da177e4
LT		 6722 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6723
e75f7c90
MC		 6724 if (!netif_running(dev))
6725 return 0;
6726
58712ef9 6727 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6728 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6729
986e0aeb
MC		 6730 addr0_high = tr32(MAC_ADDR_0_HIGH);
6731 addr0_low = tr32(MAC_ADDR_0_LOW);
6732 addr1_high = tr32(MAC_ADDR_1_HIGH);
6733 addr1_low = tr32(MAC_ADDR_1_LOW);
6734
6735 /* Skip MAC addr 1 if ASF is using it. */
6736 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6737 !(addr1_high == 0 && addr1_low == 0))
6738 skip_mac_1 = 1;
58712ef9 6739 }
986e0aeb
MC		 6740 spin_lock_bh(&tp->lock);
6741 __tg3_set_mac_addr(tp, skip_mac_1);
6742 spin_unlock_bh(&tp->lock);
1da177e4 6743
b9ec6c1b 6744 return err;
1da177e4
LT		 6745}
6746
6747/* tp->lock is held. */
6748static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6749 dma_addr_t mapping, u32 maxlen_flags,
6750 u32 nic_addr)
6751{
6752 tg3_write_mem(tp,
6753 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6754 ((u64) mapping >> 32));
6755 tg3_write_mem(tp,
6756 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6757 ((u64) mapping & 0xffffffff));
6758 tg3_write_mem(tp,
6759 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6760 maxlen_flags);
6761
6762 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6763 tg3_write_mem(tp,
6764 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6765 nic_addr);
6766}
6767
6768static void __tg3_set_rx_mode(struct net_device *);
d244c892 6769static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6770{
6771 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6772 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6773 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6774 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6775 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6776 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6777 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6778 }
6779 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6780 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6781 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6782 u32 val = ec->stats_block_coalesce_usecs;
6783
6784 if (!netif_carrier_ok(tp->dev))
6785 val = 0;
6786
6787 tw32(HOSTCC_STAT_COAL_TICKS, val);
6788 }
6789}
1da177e4
LT		 6790
6791/* tp->lock is held. */
8e7a22e3 6792static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6793{
6794 u32 val, rdmac_mode;
6795 int i, err, limit;
21f581a5 6796 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 6797
6798 tg3_disable_ints(tp);
6799
6800 tg3_stop_fw(tp);
6801
6802 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6803
6804 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6805 tg3_abort_hw(tp, 1);
1da177e4
LT		 6806 }
6807
dd477003
MC		 6808 if (reset_phy &&
6809 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6810 tg3_phy_reset(tp);
6811
1da177e4
LT		 6812 err = tg3_chip_reset(tp);
6813 if (err)
6814 return err;
6815
6816 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6817
bcb37f6c 6818 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6819 val = tr32(TG3_CPMU_CTRL);
6820 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6821 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6822
6823 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6824 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6825 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6826 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6827
6828 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6829 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6830 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6831 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6832
6833 val = tr32(TG3_CPMU_HST_ACC);
6834 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6835 val |= CPMU_HST_ACC_MACCLK_6_25;
6836 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6837 }
6838
33466d93
MC		 6839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6840 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6841 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6842 PCIE_PWR_MGMT_L1_THRESH_4MS;
6843 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 6844
6845 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6846 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6847
6848 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC		 6849 }
6850
255ca311
MC		 6851 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6852 val = tr32(TG3_PCIE_LNKCTL);
6853 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6854 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6855 else
6856 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6857 tw32(TG3_PCIE_LNKCTL, val);
6858 }
6859
1da177e4
LT		 6860 /* This works around an issue with Athlon chipsets on
6861 * B3 tigon3 silicon. This bit has no effect on any
6862 * other revision. But do not set this on PCI Express
795d01c5 6863 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6864 */
795d01c5
MC		 6865 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6866 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6867 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6868 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6869 }
1da177e4
LT		 6870
6871 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6872 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6873 val = tr32(TG3PCI_PCISTATE);
6874 val |= PCISTATE_RETRY_SAME_DMA;
6875 tw32(TG3PCI_PCISTATE, val);
6876 }
6877
0d3031d9
MC		 6878 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6879 /* Allow reads and writes to the
6880 * APE register and memory space.
6881 */
6882 val = tr32(TG3PCI_PCISTATE);
6883 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6884 PCISTATE_ALLOW_APE_SHMEM_WR;
6885 tw32(TG3PCI_PCISTATE, val);
6886 }
6887
1da177e4
LT		 6888 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6889 /* Enable some hw fixes. */
6890 val = tr32(TG3PCI_MSI_DATA);
6891 val |= (1 << 26) | (1 << 28) | (1 << 29);
6892 tw32(TG3PCI_MSI_DATA, val);
6893 }
6894
6895 /* Descriptor ring init may make accesses to the
6896 * NIC SRAM area to setup the TX descriptors, so we
6897 * can only do this after the hardware has been
6898 * successfully reset.
6899 */
32d8c572
MC		 6900 err = tg3_init_rings(tp);
6901 if (err)
6902 return err;
1da177e4 6903
9936bcf6 6904 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6905 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6906 /* This value is determined during the probe time DMA
6907 * engine test, tg3_test_dma.
6908 */
6909 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6910 }
1da177e4
LT		 6911
6912 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6913 GRC_MODE_4X_NIC_SEND_RINGS |
6914 GRC_MODE_NO_TX_PHDR_CSUM |
6915 GRC_MODE_NO_RX_PHDR_CSUM);
6916 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6917
6918 /* Pseudo-header checksum is done by hardware logic and not
6919 * the offload processers, so make the chip do the pseudo-
6920 * header checksums on receive. For transmit it is more
6921 * convenient to do the pseudo-header checksum in software
6922 * as Linux does that on transmit for us in all cases.
6923 */
6924 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6925
6926 tw32(GRC_MODE,
6927 tp->grc_mode |
6928 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6929
6930 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6931 val = tr32(GRC_MISC_CFG);
6932 val &= ~0xff;
6933 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6934 tw32(GRC_MISC_CFG, val);
6935
6936 /* Initialize MBUF/DESC pool. */
cbf46853 6937 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6938 /* Do nothing. */
6939 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6940 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6942 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6943 else
6944 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6945 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6946 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6947 }
1da177e4
LT		 6948 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6949 int fw_len;
6950
077f849d 6951 fw_len = tp->fw_len;
1da177e4
LT		 6952 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6953 tw32(BUFMGR_MB_POOL_ADDR,
6954 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6955 tw32(BUFMGR_MB_POOL_SIZE,
6956 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6957 }
1da177e4 6958
0f893dc6 6959 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6960 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6961 tp->bufmgr_config.mbuf_read_dma_low_water);
6962 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6963 tp->bufmgr_config.mbuf_mac_rx_low_water);
6964 tw32(BUFMGR_MB_HIGH_WATER,
6965 tp->bufmgr_config.mbuf_high_water);
6966 } else {
6967 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6968 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6969 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6970 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6971 tw32(BUFMGR_MB_HIGH_WATER,
6972 tp->bufmgr_config.mbuf_high_water_jumbo);
6973 }
6974 tw32(BUFMGR_DMA_LOW_WATER,
6975 tp->bufmgr_config.dma_low_water);
6976 tw32(BUFMGR_DMA_HIGH_WATER,
6977 tp->bufmgr_config.dma_high_water);
6978
6979 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6980 for (i = 0; i < 2000; i++) {
6981 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6982 break;
6983 udelay(10);
6984 }
6985 if (i >= 2000) {
6986 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6987 tp->dev->name);
6988 return -ENODEV;
6989 }
6990
6991 /* Setup replenish threshold. */
f92905de
MC		 6992 val = tp->rx_pending / 8;
6993 if (val == 0)
6994 val = 1;
6995 else if (val > tp->rx_std_max_post)
6996 val = tp->rx_std_max_post;
b5d3772c
MC		 6997 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6998 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6999 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7000
7001 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7002 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7003 }
f92905de
MC		 7004
7005 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7006
7007 /* Initialize TG3_BDINFO's at:
7008 * RCVDBDI_STD_BD: standard eth size rx ring
7009 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7010 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7011 *
7012 * like so:
7013 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7014 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7015 * ring attribute flags
7016 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7017 *
7018 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7019 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7020 *
7021 * The size of each ring is fixed in the firmware, but the location is
7022 * configurable.
7023 */
7024 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7025 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7026 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7027 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7028 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7029 NIC_SRAM_RX_BUFFER_DESC);
7030
fdb72b38
MC		 7031 /* Disable the mini ring */
7032 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7033 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7034 BDINFO_FLAGS_DISABLED);
7035
fdb72b38
MC		 7036 /* Program the jumbo buffer descriptor ring control
7037 * blocks on those devices that have them.
7038 */
8f666b07 7039 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7040 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7041 /* Setup replenish threshold. */
7042 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7043
0f893dc6 7044 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7045 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7046 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7047 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7048 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7049 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7050 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7051 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7052 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7053 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7054 } else {
7055 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7056 BDINFO_FLAGS_DISABLED);
7057 }
7058
fdb72b38
MC		 7059 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7060 } else
7061 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7062
7063 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4
LT		 7064
7065 /* There is only one send ring on 5705/5750, no need to explicitly
7066 * disable the others.
7067 */
7068 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7069 /* Clear out send RCB ring in SRAM. */
7070 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7071 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7072 BDINFO_FLAGS_DISABLED);
7073 }
7074
7075 tp->tx_prod = 0;
7076 tp->tx_cons = 0;
7077 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7078 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7079
7080 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7081 tp->tx_desc_mapping,
7082 (TG3_TX_RING_SIZE <<
7083 BDINFO_FLAGS_MAXLEN_SHIFT),
7084 NIC_SRAM_TX_BUFFER_DESC);
7085
7086 /* There is only one receive return ring on 5705/5750, no need
7087 * to explicitly disable the others.
7088 */
7089 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7090 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7091 i += TG3_BDINFO_SIZE) {
7092 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7093 BDINFO_FLAGS_DISABLED);
7094 }
7095 }
7096
7097 tp->rx_rcb_ptr = 0;
7098 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7099
7100 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7101 tp->rx_rcb_mapping,
7102 (TG3_RX_RCB_RING_SIZE(tp) <<
7103 BDINFO_FLAGS_MAXLEN_SHIFT),
7104 0);
7105
21f581a5 7106 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7107 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7108 tpr->rx_std_ptr);
1da177e4 7109
21f581a5
MC		 7110 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7111 tp->rx_jumbo_pending : 0;
1da177e4 7112 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7113 tpr->rx_jmb_ptr);
1da177e4
LT		 7114
7115 /* Initialize MAC address and backoff seed. */
986e0aeb 7116 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7117
7118 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7119 tw32(MAC_RX_MTU_SIZE,
7120 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7121
7122 /* The slot time is changed by tg3_setup_phy if we
7123 * run at gigabit with half duplex.
7124 */
7125 tw32(MAC_TX_LENGTHS,
7126 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7127 (6 << TX_LENGTHS_IPG_SHIFT) |
7128 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7129
7130 /* Receive rules. */
7131 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7132 tw32(RCVLPC_CONFIG, 0x0181);
7133
7134 /* Calculate RDMAC_MODE setting early, we need it to determine
7135 * the RCVLPC_STATE_ENABLE mask.
7136 */
7137 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7138 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7139 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7140 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7141 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7142
57e6983c 7143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7144 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7146 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7147 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7148 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7149
85e94ced
MC		 7150 /* If statement applies to 5705 and 5750 PCI devices only */
7151 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7152 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7153 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7154 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7155 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7156 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7157 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7158 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7159 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7160 }
7161 }
7162
85e94ced
MC		 7163 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7164 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7165
1da177e4 7166 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7167 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7168
7169 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7171 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7172
7173 /* Receive/send statistics. */
1661394e
MC		 7174 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7175 val = tr32(RCVLPC_STATS_ENABLE);
7176 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7177 tw32(RCVLPC_STATS_ENABLE, val);
7178 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7179 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7180 val = tr32(RCVLPC_STATS_ENABLE);
7181 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7182 tw32(RCVLPC_STATS_ENABLE, val);
7183 } else {
7184 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7185 }
7186 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7187 tw32(SNDDATAI_STATSENAB, 0xffffff);
7188 tw32(SNDDATAI_STATSCTRL,
7189 (SNDDATAI_SCTRL_ENABLE |
7190 SNDDATAI_SCTRL_FASTUPD));
7191
7192 /* Setup host coalescing engine. */
7193 tw32(HOSTCC_MODE, 0);
7194 for (i = 0; i < 2000; i++) {
7195 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7196 break;
7197 udelay(10);
7198 }
7199
d244c892 7200 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7201
7202 /* set status block DMA address */
7203 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7204 ((u64) tp->status_mapping >> 32));
7205 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7206 ((u64) tp->status_mapping & 0xffffffff));
7207
7208 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7209 /* Status/statistics block address. See tg3_timer,
7210 * the tg3_periodic_fetch_stats call there, and
7211 * tg3_get_stats to see how this works for 5705/5750 chips.
7212 */
1da177e4
LT		 7213 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7214 ((u64) tp->stats_mapping >> 32));
7215 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7216 ((u64) tp->stats_mapping & 0xffffffff));
7217 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7218 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7219 }
7220
7221 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7222
7223 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7224 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7225 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7226 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7227
7228 /* Clear statistics/status block in chip, and status block in ram. */
7229 for (i = NIC_SRAM_STATS_BLK;
7230 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7231 i += sizeof(u32)) {
7232 tg3_write_mem(tp, i, 0);
7233 udelay(40);
7234 }
7235 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7236
c94e3941
MC		 7237 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7238 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7239 /* reset to prevent losing 1st rx packet intermittently */
7240 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7241 udelay(10);
7242 }
7243
3bda1258
MC		 7244 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7245 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7246 else
7247 tp->mac_mode = 0;
7248 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7249 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7250 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7251 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7252 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7253 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7254 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7255 udelay(40);
7256
314fba34 7257 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7258 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7259 * register to preserve the GPIO settings for LOMs. The GPIOs,
7260 * whether used as inputs or outputs, are set by boot code after
7261 * reset.
7262 */
9d26e213 7263 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7264 u32 gpio_mask;
7265
9d26e213
MC		 7266 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7267 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7268 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7269
7270 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7271 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7272 GRC_LCLCTRL_GPIO_OUTPUT3;
7273
af36e6b6
MC		 7274 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7275 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7276
aaf84465 7277 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7278 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7279
7280 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7281 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7282 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7283 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7284 }
1da177e4
LT		 7285 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7286 udelay(100);
7287
09ee929c 7288 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
1da177e4
LT		 7289
7290 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7291 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7292 udelay(40);
7293 }
7294
7295 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7296 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7297 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7298 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7299 WDMAC_MODE_LNGREAD_ENAB);
7300
85e94ced
MC		 7301 /* If statement applies to 5705 and 5750 PCI devices only */
7302 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7303 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7304 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7305 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7306 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7307 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7308 /* nothing */
7309 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7310 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7311 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7312 val |= WDMAC_MODE_RX_ACCEL;
7313 }
7314 }
7315
d9ab5ad1 7316 /* Enable host coalescing bug fix */
321d32a0 7317 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7318 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7319
1da177e4
LT		 7320 tw32_f(WDMAC_MODE, val);
7321 udelay(40);
7322
9974a356
MC		 7323 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7324 u16 pcix_cmd;
7325
7326 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7327 &pcix_cmd);
1da177e4 7328 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7329 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7330 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7331 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7332 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7333 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7334 }
9974a356
MC		 7335 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7336 pcix_cmd);
1da177e4
LT		 7337 }
7338
7339 tw32_f(RDMAC_MODE, rdmac_mode);
7340 udelay(40);
7341
7342 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7343 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7344 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7345
7346 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7347 tw32(SNDDATAC_MODE,
7348 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7349 else
7350 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7351
1da177e4
LT		 7352 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7353 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7354 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7355 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7356 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7357 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7358 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7359 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7360
7361 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7362 err = tg3_load_5701_a0_firmware_fix(tp);
7363 if (err)
7364 return err;
7365 }
7366
1da177e4
LT		 7367 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7368 err = tg3_load_tso_firmware(tp);
7369 if (err)
7370 return err;
7371 }
1da177e4
LT		 7372
7373 tp->tx_mode = TX_MODE_ENABLE;
7374 tw32_f(MAC_TX_MODE, tp->tx_mode);
7375 udelay(100);
7376
7377 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7378 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7379 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7380
1da177e4
LT		 7381 tw32_f(MAC_RX_MODE, tp->rx_mode);
7382 udelay(10);
7383
1da177e4
LT		 7384 tw32(MAC_LED_CTRL, tp->led_ctrl);
7385
7386 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7387 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7388 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7389 udelay(10);
7390 }
7391 tw32_f(MAC_RX_MODE, tp->rx_mode);
7392 udelay(10);
7393
7394 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7395 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7396 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7397 /* Set drive transmission level to 1.2V */
7398 /* only if the signal pre-emphasis bit is not set */
7399 val = tr32(MAC_SERDES_CFG);
7400 val &= 0xfffff000;
7401 val |= 0x880;
7402 tw32(MAC_SERDES_CFG, val);
7403 }
7404 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7405 tw32(MAC_SERDES_CFG, 0x616000);
7406 }
7407
7408 /* Prevent chip from dropping frames when flow control
7409 * is enabled.
7410 */
7411 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7412
7413 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7414 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7415 /* Use hardware link auto-negotiation */
7416 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7417 }
7418
d4d2c558
MC		 7419 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7420 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7421 u32 tmp;
7422
7423 tmp = tr32(SERDES_RX_CTRL);
7424 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7425 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7426 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7427 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7428 }
7429
dd477003
MC		 7430 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7431 if (tp->link_config.phy_is_low_power) {
7432 tp->link_config.phy_is_low_power = 0;
7433 tp->link_config.speed = tp->link_config.orig_speed;
7434 tp->link_config.duplex = tp->link_config.orig_duplex;
7435 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7436 }
1da177e4 7437
dd477003
MC		 7438 err = tg3_setup_phy(tp, 0);
7439 if (err)
7440 return err;
1da177e4 7441
dd477003 7442 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7443 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7444 u32 tmp;
7445
7446 /* Clear CRC stats. */
7447 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7448 tg3_writephy(tp, MII_TG3_TEST1,
7449 tmp | MII_TG3_TEST1_CRC_EN);
7450 tg3_readphy(tp, 0x14, &tmp);
7451 }
1da177e4
LT		 7452 }
7453 }
7454
7455 __tg3_set_rx_mode(tp->dev);
7456
7457 /* Initialize receive rules. */
7458 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7459 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7460 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7461 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7462
4cf78e4f 7463 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7464 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7465 limit = 8;
7466 else
7467 limit = 16;
7468 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7469 limit -= 4;
7470 switch (limit) {
7471 case 16:
7472 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7473 case 15:
7474 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7475 case 14:
7476 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7477 case 13:
7478 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7479 case 12:
7480 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7481 case 11:
7482 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7483 case 10:
7484 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7485 case 9:
7486 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7487 case 8:
7488 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7489 case 7:
7490 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7491 case 6:
7492 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7493 case 5:
7494 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7495 case 4:
7496 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7497 case 3:
7498 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7499 case 2:
7500 case 1:
7501
7502 default:
7503 break;
855e1111 7504 }
1da177e4 7505
9ce768ea
MC		 7506 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7507 /* Write our heartbeat update interval to APE. */
7508 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7509 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7510
1da177e4
LT		 7511 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7512
1da177e4
LT		 7513 return 0;
7514}
7515
7516/* Called at device open time to get the chip ready for
7517 * packet processing. Invoked with tp->lock held.
7518 */
8e7a22e3 7519static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7520{
1da177e4
LT		 7521 tg3_switch_clocks(tp);
7522
7523 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7524
2f751b67 7525 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7526}
7527
7528#define TG3_STAT_ADD32(PSTAT, REG) \
7529do { u32 __val = tr32(REG); \
7530 (PSTAT)->low += __val; \
7531 if ((PSTAT)->low < __val) \
7532 (PSTAT)->high += 1; \
7533} while (0)
7534
7535static void tg3_periodic_fetch_stats(struct tg3 *tp)
7536{
7537 struct tg3_hw_stats *sp = tp->hw_stats;
7538
7539 if (!netif_carrier_ok(tp->dev))
7540 return;
7541
7542 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7543 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7544 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7545 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7546 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7547 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7548 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7549 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7550 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7551 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7552 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7553 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7554 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7555
7556 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7557 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7558 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7559 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7560 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7561 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7562 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7563 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7564 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7565 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7566 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7567 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7568 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7569 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7570
7571 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7572 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7573 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7574}
7575
7576static void tg3_timer(unsigned long __opaque)
7577{
7578 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7579
f475f163
MC		 7580 if (tp->irq_sync)
7581 goto restart_timer;
7582
f47c11ee 7583 spin_lock(&tp->lock);
1da177e4 7584
fac9b83e
DM		 7585 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7586 /* All of this garbage is because when using non-tagged
7587 * IRQ status the mailbox/status_block protocol the chip
7588 * uses with the cpu is race prone.
7589 */
7590 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7591 tw32(GRC_LOCAL_CTRL,
7592 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7593 } else {
7594 tw32(HOSTCC_MODE, tp->coalesce_mode |
7595 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7596 }
1da177e4 7597
fac9b83e
DM		 7598 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7599 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7600 spin_unlock(&tp->lock);
fac9b83e
DM		 7601 schedule_work(&tp->reset_task);
7602 return;
7603 }
1da177e4
LT		 7604 }
7605
1da177e4
LT		 7606 /* This part only runs once per second. */
7607 if (!--tp->timer_counter) {
fac9b83e
DM		 7608 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7609 tg3_periodic_fetch_stats(tp);
7610
1da177e4
LT		 7611 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7612 u32 mac_stat;
7613 int phy_event;
7614
7615 mac_stat = tr32(MAC_STATUS);
7616
7617 phy_event = 0;
7618 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7619 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7620 phy_event = 1;
7621 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7622 phy_event = 1;
7623
7624 if (phy_event)
7625 tg3_setup_phy(tp, 0);
7626 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7627 u32 mac_stat = tr32(MAC_STATUS);
7628 int need_setup = 0;
7629
7630 if (netif_carrier_ok(tp->dev) &&
7631 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7632 need_setup = 1;
7633 }
7634 if (! netif_carrier_ok(tp->dev) &&
7635 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7636 MAC_STATUS_SIGNAL_DET))) {
7637 need_setup = 1;
7638 }
7639 if (need_setup) {
3d3ebe74
MC		 7640 if (!tp->serdes_counter) {
7641 tw32_f(MAC_MODE,
7642 (tp->mac_mode &
7643 ~MAC_MODE_PORT_MODE_MASK));
7644 udelay(40);
7645 tw32_f(MAC_MODE, tp->mac_mode);
7646 udelay(40);
7647 }
1da177e4
LT		 7648 tg3_setup_phy(tp, 0);
7649 }
747e8f8b
MC		 7650 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7651 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7652
7653 tp->timer_counter = tp->timer_multiplier;
7654 }
7655
130b8e4d
MC		 7656 /* Heartbeat is only sent once every 2 seconds.
7657 *
7658 * The heartbeat is to tell the ASF firmware that the host
7659 * driver is still alive. In the event that the OS crashes,
7660 * ASF needs to reset the hardware to free up the FIFO space
7661 * that may be filled with rx packets destined for the host.
7662 * If the FIFO is full, ASF will no longer function properly.
7663 *
7664 * Unintended resets have been reported on real time kernels
7665 * where the timer doesn't run on time. Netpoll will also have
7666 * same problem.
7667 *
7668 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7669 * to check the ring condition when the heartbeat is expiring
7670 * before doing the reset. This will prevent most unintended
7671 * resets.
7672 */
1da177e4 7673 if (!--tp->asf_counter) {
bc7959b2
MC		 7674 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7675 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7676 tg3_wait_for_event_ack(tp);
7677
bbadf503 7678 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7679 FWCMD_NICDRV_ALIVE3);
bbadf503 7680 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7681 /* 5 seconds timeout */
bbadf503 7682 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7683
7684 tg3_generate_fw_event(tp);
1da177e4
LT		 7685 }
7686 tp->asf_counter = tp->asf_multiplier;
7687 }
7688
f47c11ee 7689 spin_unlock(&tp->lock);
1da177e4 7690
f475f163 7691restart_timer:
1da177e4
LT		 7692 tp->timer.expires = jiffies + tp->timer_offset;
7693 add_timer(&tp->timer);
7694}
7695
81789ef5 7696static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7697{
7d12e780 7698 irq_handler_t fn;
fcfa0a32
MC		 7699 unsigned long flags;
7700 struct net_device *dev = tp->dev;
7701
7702 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7703 fn = tg3_msi;
7704 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7705 fn = tg3_msi_1shot;
1fb9df5d 7706 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7707 } else {
7708 fn = tg3_interrupt;
7709 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7710 fn = tg3_interrupt_tagged;
1fb9df5d 7711 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7712 }
7713 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7714}
7715
7938109f
MC		 7716static int tg3_test_interrupt(struct tg3 *tp)
7717{
7718 struct net_device *dev = tp->dev;
b16250e3 7719 int err, i, intr_ok = 0;
7938109f 7720
d4bc3927
MC		 7721 if (!netif_running(dev))
7722 return -ENODEV;
7723
7938109f
MC		 7724 tg3_disable_ints(tp);
7725
7726 free_irq(tp->pdev->irq, dev);
7727
7728 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7729 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7730 if (err)
7731 return err;
7732
38f3843e 7733 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7734 tg3_enable_ints(tp);
7735
7736 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7737 HOSTCC_MODE_NOW);
7738
7739 for (i = 0; i < 5; i++) {
b16250e3
MC		 7740 u32 int_mbox, misc_host_ctrl;
7741
09ee929c
MC		 7742 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7743 TG3_64BIT_REG_LOW);
b16250e3
MC		 7744 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7745
7746 if ((int_mbox != 0) ||
7747 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7748 intr_ok = 1;
7938109f 7749 break;
b16250e3
MC		 7750 }
7751
7938109f
MC		 7752 msleep(10);
7753 }
7754
7755 tg3_disable_ints(tp);
7756
7757 free_irq(tp->pdev->irq, dev);
6aa20a22 7758
fcfa0a32 7759 err = tg3_request_irq(tp);
7938109f
MC		 7760
7761 if (err)
7762 return err;
7763
b16250e3 7764 if (intr_ok)
7938109f
MC		 7765 return 0;
7766
7767 return -EIO;
7768}
7769
7770/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7771 * successfully restored
7772 */
7773static int tg3_test_msi(struct tg3 *tp)
7774{
7775 struct net_device *dev = tp->dev;
7776 int err;
7777 u16 pci_cmd;
7778
7779 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7780 return 0;
7781
7782 /* Turn off SERR reporting in case MSI terminates with Master
7783 * Abort.
7784 */
7785 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7786 pci_write_config_word(tp->pdev, PCI_COMMAND,
7787 pci_cmd & ~PCI_COMMAND_SERR);
7788
7789 err = tg3_test_interrupt(tp);
7790
7791 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7792
7793 if (!err)
7794 return 0;
7795
7796 /* other failures */
7797 if (err != -EIO)
7798 return err;
7799
7800 /* MSI test failed, go back to INTx mode */
7801 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7802 "switching to INTx mode. Please report this failure to "
7803 "the PCI maintainer and include system chipset information.\n",
7804 tp->dev->name);
7805
7806 free_irq(tp->pdev->irq, dev);
7807 pci_disable_msi(tp->pdev);
7808
7809 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7810
fcfa0a32 7811 err = tg3_request_irq(tp);
7938109f
MC		 7812 if (err)
7813 return err;
7814
7815 /* Need to reset the chip because the MSI cycle may have terminated
7816 * with Master Abort.
7817 */
f47c11ee 7818 tg3_full_lock(tp, 1);
7938109f 7819
944d980e 7820 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7821 err = tg3_init_hw(tp, 1);
7938109f 7822
f47c11ee 7823 tg3_full_unlock(tp);
7938109f
MC		 7824
7825 if (err)
7826 free_irq(tp->pdev->irq, dev);
7827
7828 return err;
7829}
7830
9e9fd12d
MC		 7831static int tg3_request_firmware(struct tg3 *tp)
7832{
7833 const __be32 *fw_data;
7834
7835 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7836 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7837 tp->dev->name, tp->fw_needed);
7838 return -ENOENT;
7839 }
7840
7841 fw_data = (void *)tp->fw->data;
7842
7843 /* Firmware blob starts with version numbers, followed by
7844 * start address and _full_ length including BSS sections
7845 * (which must be longer than the actual data, of course
7846 */
7847
7848 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7849 if (tp->fw_len < (tp->fw->size - 12)) {
7850 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7851 tp->dev->name, tp->fw_len, tp->fw_needed);
7852 release_firmware(tp->fw);
7853 tp->fw = NULL;
7854 return -EINVAL;
7855 }
7856
7857 /* We no longer need firmware; we have it. */
7858 tp->fw_needed = NULL;
7859 return 0;
7860}
7861
07b0173c
MC		 7862static void tg3_ints_init(struct tg3 *tp)
7863{
7864 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7865 /* All MSI supporting chips should support tagged
7866 * status. Assert that this is the case.
7867 */
7868 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7869 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7870 "Not using MSI.\n", tp->dev->name);
7871 } else if (pci_enable_msi(tp->pdev) == 0) {
7872 u32 msi_mode;
7873
7874 msi_mode = tr32(MSGINT_MODE);
7875 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7876 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7877 }
7878 }
7879}
7880
7881static void tg3_ints_fini(struct tg3 *tp)
7882{
7883 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7884 pci_disable_msi(tp->pdev);
7885 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7886 }
7887}
7888
1da177e4
LT		 7889static int tg3_open(struct net_device *dev)
7890{
7891 struct tg3 *tp = netdev_priv(dev);
7892 int err;
7893
9e9fd12d
MC		 7894 if (tp->fw_needed) {
7895 err = tg3_request_firmware(tp);
7896 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7897 if (err)
7898 return err;
7899 } else if (err) {
7900 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7901 tp->dev->name);
7902 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7903 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7904 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7905 tp->dev->name);
7906 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7907 }
7908 }
7909
c49a1561
MC		 7910 netif_carrier_off(tp->dev);
7911
bc1c7567 7912 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7913 if (err)
bc1c7567 7914 return err;
2f751b67
MC		 7915
7916 tg3_full_lock(tp, 0);
bc1c7567 7917
1da177e4
LT		 7918 tg3_disable_ints(tp);
7919 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7920
f47c11ee 7921 tg3_full_unlock(tp);
1da177e4
LT		 7922
7923 /* The placement of this call is tied
7924 * to the setup and use of Host TX descriptors.
7925 */
7926 err = tg3_alloc_consistent(tp);
7927 if (err)
7928 return err;
7929
07b0173c 7930 tg3_ints_init(tp);
88b06bc2 7931
8ef0442f 7932 napi_enable(&tp->napi[0].napi);
1da177e4 7933
07b0173c 7934 err = tg3_request_irq(tp);
1da177e4 7935
07b0173c
MC		 7936 if (err)
7937 goto err_out1;
bea3348e 7938
f47c11ee 7939 tg3_full_lock(tp, 0);
1da177e4 7940
8e7a22e3 7941 err = tg3_init_hw(tp, 1);
1da177e4 7942 if (err) {
944d980e 7943 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7944 tg3_free_rings(tp);
7945 } else {
fac9b83e
DM		 7946 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7947 tp->timer_offset = HZ;
7948 else
7949 tp->timer_offset = HZ / 10;
7950
7951 BUG_ON(tp->timer_offset > HZ);
7952 tp->timer_counter = tp->timer_multiplier =
7953 (HZ / tp->timer_offset);
7954 tp->asf_counter = tp->asf_multiplier =
28fbef78 7955 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7956
7957 init_timer(&tp->timer);
7958 tp->timer.expires = jiffies + tp->timer_offset;
7959 tp->timer.data = (unsigned long) tp;
7960 tp->timer.function = tg3_timer;
1da177e4
LT		 7961 }
7962
f47c11ee 7963 tg3_full_unlock(tp);
1da177e4 7964
07b0173c
MC		 7965 if (err)
7966 goto err_out2;
1da177e4 7967
7938109f
MC		 7968 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7969 err = tg3_test_msi(tp);
fac9b83e 7970
7938109f 7971 if (err) {
f47c11ee 7972 tg3_full_lock(tp, 0);
944d980e 7973 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 7974 tg3_free_rings(tp);
f47c11ee 7975 tg3_full_unlock(tp);
7938109f 7976
07b0173c 7977 goto err_out1;
7938109f 7978 }
fcfa0a32
MC		 7979
7980 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7981 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7982 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7983
b5d3772c
MC		 7984 tw32(PCIE_TRANSACTION_CFG,
7985 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7986 }
7987 }
7938109f
MC		 7988 }
7989
b02fd9e3
MC		 7990 tg3_phy_start(tp);
7991
f47c11ee 7992 tg3_full_lock(tp, 0);
1da177e4 7993
7938109f
MC		 7994 add_timer(&tp->timer);
7995 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7996 tg3_enable_ints(tp);
7997
f47c11ee 7998 tg3_full_unlock(tp);
1da177e4
LT		 7999
8000 netif_start_queue(dev);
8001
8002 return 0;
07b0173c
MC		 8003
8004err_out2:
8005 free_irq(tp->pdev->irq, dev);
8006
8007err_out1:
8ef0442f 8008 napi_disable(&tp->napi[0].napi);
07b0173c
MC		 8009 tg3_ints_fini(tp);
8010 tg3_free_consistent(tp);
8011 return err;
1da177e4
LT		 8012}
8013
8014#if 0
8015/*static*/ void tg3_dump_state(struct tg3 *tp)
8016{
8017 u32 val32, val32_2, val32_3, val32_4, val32_5;
8018 u16 val16;
8019 int i;
8020
8021 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8022 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8023 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8024 val16, val32);
8025
8026 /* MAC block */
8027 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8028 tr32(MAC_MODE), tr32(MAC_STATUS));
8029 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8030 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8031 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8032 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8033 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8034 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8035
8036 /* Send data initiator control block */
8037 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8038 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8039 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8040 tr32(SNDDATAI_STATSCTRL));
8041
8042 /* Send data completion control block */
8043 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8044
8045 /* Send BD ring selector block */
8046 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8047 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8048
8049 /* Send BD initiator control block */
8050 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8051 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8052
8053 /* Send BD completion control block */
8054 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8055
8056 /* Receive list placement control block */
8057 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8058 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8059 printk(" RCVLPC_STATSCTRL[%08x]\n",
8060 tr32(RCVLPC_STATSCTRL));
8061
8062 /* Receive data and receive BD initiator control block */
8063 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8064 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8065
8066 /* Receive data completion control block */
8067 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8068 tr32(RCVDCC_MODE));
8069
8070 /* Receive BD initiator control block */
8071 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8072 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8073
8074 /* Receive BD completion control block */
8075 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8076 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8077
8078 /* Receive list selector control block */
8079 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8080 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8081
8082 /* Mbuf cluster free block */
8083 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8084 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8085
8086 /* Host coalescing control block */
8087 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8088 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8089 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8090 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8091 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8092 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8093 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8094 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8095 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8096 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8097 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8098 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8099
8100 /* Memory arbiter control block */
8101 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8102 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8103
8104 /* Buffer manager control block */
8105 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8106 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8107 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8108 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8109 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8110 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8111 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8112 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8113
8114 /* Read DMA control block */
8115 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8116 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8117
8118 /* Write DMA control block */
8119 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8120 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8121
8122 /* DMA completion block */
8123 printk("DEBUG: DMAC_MODE[%08x]\n",
8124 tr32(DMAC_MODE));
8125
8126 /* GRC block */
8127 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8128 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8129 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8130 tr32(GRC_LOCAL_CTRL));
8131
8132 /* TG3_BDINFOs */
8133 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8134 tr32(RCVDBDI_JUMBO_BD + 0x0),
8135 tr32(RCVDBDI_JUMBO_BD + 0x4),
8136 tr32(RCVDBDI_JUMBO_BD + 0x8),
8137 tr32(RCVDBDI_JUMBO_BD + 0xc));
8138 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8139 tr32(RCVDBDI_STD_BD + 0x0),
8140 tr32(RCVDBDI_STD_BD + 0x4),
8141 tr32(RCVDBDI_STD_BD + 0x8),
8142 tr32(RCVDBDI_STD_BD + 0xc));
8143 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8144 tr32(RCVDBDI_MINI_BD + 0x0),
8145 tr32(RCVDBDI_MINI_BD + 0x4),
8146 tr32(RCVDBDI_MINI_BD + 0x8),
8147 tr32(RCVDBDI_MINI_BD + 0xc));
8148
8149 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8150 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8151 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8152 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8153 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8154 val32, val32_2, val32_3, val32_4);
8155
8156 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8157 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8158 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8159 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8160 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8161 val32, val32_2, val32_3, val32_4);
8162
8163 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8164 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8165 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8166 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8167 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8168 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8169 val32, val32_2, val32_3, val32_4, val32_5);
8170
8171 /* SW status block */
8172 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8173 tp->hw_status->status,
8174 tp->hw_status->status_tag,
8175 tp->hw_status->rx_jumbo_consumer,
8176 tp->hw_status->rx_consumer,
8177 tp->hw_status->rx_mini_consumer,
8178 tp->hw_status->idx[0].rx_producer,
8179 tp->hw_status->idx[0].tx_consumer);
8180
8181 /* SW statistics block */
8182 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8183 ((u32 *)tp->hw_stats)[0],
8184 ((u32 *)tp->hw_stats)[1],
8185 ((u32 *)tp->hw_stats)[2],
8186 ((u32 *)tp->hw_stats)[3]);
8187
8188 /* Mailboxes */
8189 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8190 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8191 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8192 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8193 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8194
8195 /* NIC side send descriptors. */
8196 for (i = 0; i < 6; i++) {
8197 unsigned long txd;
8198
8199 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8200 + (i * sizeof(struct tg3_tx_buffer_desc));
8201 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8202 i,
8203 readl(txd + 0x0), readl(txd + 0x4),
8204 readl(txd + 0x8), readl(txd + 0xc));
8205 }
8206
8207 /* NIC side RX descriptors. */
8208 for (i = 0; i < 6; i++) {
8209 unsigned long rxd;
8210
8211 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8212 + (i * sizeof(struct tg3_rx_buffer_desc));
8213 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8214 i,
8215 readl(rxd + 0x0), readl(rxd + 0x4),
8216 readl(rxd + 0x8), readl(rxd + 0xc));
8217 rxd += (4 * sizeof(u32));
8218 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8219 i,
8220 readl(rxd + 0x0), readl(rxd + 0x4),
8221 readl(rxd + 0x8), readl(rxd + 0xc));
8222 }
8223
8224 for (i = 0; i < 6; i++) {
8225 unsigned long rxd;
8226
8227 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8228 + (i * sizeof(struct tg3_rx_buffer_desc));
8229 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8230 i,
8231 readl(rxd + 0x0), readl(rxd + 0x4),
8232 readl(rxd + 0x8), readl(rxd + 0xc));
8233 rxd += (4 * sizeof(u32));
8234 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8235 i,
8236 readl(rxd + 0x0), readl(rxd + 0x4),
8237 readl(rxd + 0x8), readl(rxd + 0xc));
8238 }
8239}
8240#endif
8241
8242static struct net_device_stats *tg3_get_stats(struct net_device *);
8243static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8244
8245static int tg3_close(struct net_device *dev)
8246{
8247 struct tg3 *tp = netdev_priv(dev);
8248
8ef0442f 8249 napi_disable(&tp->napi[0].napi);
28e53bdd 8250 cancel_work_sync(&tp->reset_task);
7faa006f 8251
1da177e4
LT		 8252 netif_stop_queue(dev);
8253
8254 del_timer_sync(&tp->timer);
8255
f47c11ee 8256 tg3_full_lock(tp, 1);
1da177e4
LT		 8257#if 0
8258 tg3_dump_state(tp);
8259#endif
8260
8261 tg3_disable_ints(tp);
8262
944d980e 8263 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8264 tg3_free_rings(tp);
5cf64b8a 8265 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8266
f47c11ee 8267 tg3_full_unlock(tp);
1da177e4 8268
88b06bc2 8269 free_irq(tp->pdev->irq, dev);
07b0173c
MC		 8270
8271 tg3_ints_fini(tp);
1da177e4
LT		 8272
8273 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8274 sizeof(tp->net_stats_prev));
8275 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8276 sizeof(tp->estats_prev));
8277
8278 tg3_free_consistent(tp);
8279
bc1c7567
MC		 8280 tg3_set_power_state(tp, PCI_D3hot);
8281
8282 netif_carrier_off(tp->dev);
8283
1da177e4
LT		 8284 return 0;
8285}
8286
8287static inline unsigned long get_stat64(tg3_stat64_t *val)
8288{
8289 unsigned long ret;
8290
8291#if (BITS_PER_LONG == 32)
8292 ret = val->low;
8293#else
8294 ret = ((u64)val->high << 32) | ((u64)val->low);
8295#endif
8296 return ret;
8297}
8298
816f8b86
SB		 8299static inline u64 get_estat64(tg3_stat64_t *val)
8300{
8301 return ((u64)val->high << 32) | ((u64)val->low);
8302}
8303
1da177e4
LT		 8304static unsigned long calc_crc_errors(struct tg3 *tp)
8305{
8306 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8307
8308 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8309 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8311 u32 val;
8312
f47c11ee 8313 spin_lock_bh(&tp->lock);
569a5df8
MC		 8314 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8315 tg3_writephy(tp, MII_TG3_TEST1,
8316 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8317 tg3_readphy(tp, 0x14, &val);
8318 } else
8319 val = 0;
f47c11ee 8320 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8321
8322 tp->phy_crc_errors += val;
8323
8324 return tp->phy_crc_errors;
8325 }
8326
8327 return get_stat64(&hw_stats->rx_fcs_errors);
8328}
8329
8330#define ESTAT_ADD(member) \
8331 estats->member = old_estats->member + \
816f8b86 8332 get_estat64(&hw_stats->member)
1da177e4
LT		 8333
8334static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8335{
8336 struct tg3_ethtool_stats *estats = &tp->estats;
8337 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8338 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8339
8340 if (!hw_stats)
8341 return old_estats;
8342
8343 ESTAT_ADD(rx_octets);
8344 ESTAT_ADD(rx_fragments);
8345 ESTAT_ADD(rx_ucast_packets);
8346 ESTAT_ADD(rx_mcast_packets);
8347 ESTAT_ADD(rx_bcast_packets);
8348 ESTAT_ADD(rx_fcs_errors);
8349 ESTAT_ADD(rx_align_errors);
8350 ESTAT_ADD(rx_xon_pause_rcvd);
8351 ESTAT_ADD(rx_xoff_pause_rcvd);
8352 ESTAT_ADD(rx_mac_ctrl_rcvd);
8353 ESTAT_ADD(rx_xoff_entered);
8354 ESTAT_ADD(rx_frame_too_long_errors);
8355 ESTAT_ADD(rx_jabbers);
8356 ESTAT_ADD(rx_undersize_packets);
8357 ESTAT_ADD(rx_in_length_errors);
8358 ESTAT_ADD(rx_out_length_errors);
8359 ESTAT_ADD(rx_64_or_less_octet_packets);
8360 ESTAT_ADD(rx_65_to_127_octet_packets);
8361 ESTAT_ADD(rx_128_to_255_octet_packets);
8362 ESTAT_ADD(rx_256_to_511_octet_packets);
8363 ESTAT_ADD(rx_512_to_1023_octet_packets);
8364 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8365 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8366 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8367 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8368 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8369
8370 ESTAT_ADD(tx_octets);
8371 ESTAT_ADD(tx_collisions);
8372 ESTAT_ADD(tx_xon_sent);
8373 ESTAT_ADD(tx_xoff_sent);
8374 ESTAT_ADD(tx_flow_control);
8375 ESTAT_ADD(tx_mac_errors);
8376 ESTAT_ADD(tx_single_collisions);
8377 ESTAT_ADD(tx_mult_collisions);
8378 ESTAT_ADD(tx_deferred);
8379 ESTAT_ADD(tx_excessive_collisions);
8380 ESTAT_ADD(tx_late_collisions);
8381 ESTAT_ADD(tx_collide_2times);
8382 ESTAT_ADD(tx_collide_3times);
8383 ESTAT_ADD(tx_collide_4times);
8384 ESTAT_ADD(tx_collide_5times);
8385 ESTAT_ADD(tx_collide_6times);
8386 ESTAT_ADD(tx_collide_7times);
8387 ESTAT_ADD(tx_collide_8times);
8388 ESTAT_ADD(tx_collide_9times);
8389 ESTAT_ADD(tx_collide_10times);
8390 ESTAT_ADD(tx_collide_11times);
8391 ESTAT_ADD(tx_collide_12times);
8392 ESTAT_ADD(tx_collide_13times);
8393 ESTAT_ADD(tx_collide_14times);
8394 ESTAT_ADD(tx_collide_15times);
8395 ESTAT_ADD(tx_ucast_packets);
8396 ESTAT_ADD(tx_mcast_packets);
8397 ESTAT_ADD(tx_bcast_packets);
8398 ESTAT_ADD(tx_carrier_sense_errors);
8399 ESTAT_ADD(tx_discards);
8400 ESTAT_ADD(tx_errors);
8401
8402 ESTAT_ADD(dma_writeq_full);
8403 ESTAT_ADD(dma_write_prioq_full);
8404 ESTAT_ADD(rxbds_empty);
8405 ESTAT_ADD(rx_discards);
8406 ESTAT_ADD(rx_errors);
8407 ESTAT_ADD(rx_threshold_hit);
8408
8409 ESTAT_ADD(dma_readq_full);
8410 ESTAT_ADD(dma_read_prioq_full);
8411 ESTAT_ADD(tx_comp_queue_full);
8412
8413 ESTAT_ADD(ring_set_send_prod_index);
8414 ESTAT_ADD(ring_status_update);
8415 ESTAT_ADD(nic_irqs);
8416 ESTAT_ADD(nic_avoided_irqs);
8417 ESTAT_ADD(nic_tx_threshold_hit);
8418
8419 return estats;
8420}
8421
8422static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8423{
8424 struct tg3 *tp = netdev_priv(dev);
8425 struct net_device_stats *stats = &tp->net_stats;
8426 struct net_device_stats *old_stats = &tp->net_stats_prev;
8427 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8428
8429 if (!hw_stats)
8430 return old_stats;
8431
8432 stats->rx_packets = old_stats->rx_packets +
8433 get_stat64(&hw_stats->rx_ucast_packets) +
8434 get_stat64(&hw_stats->rx_mcast_packets) +
8435 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8436
1da177e4
LT		 8437 stats->tx_packets = old_stats->tx_packets +
8438 get_stat64(&hw_stats->tx_ucast_packets) +
8439 get_stat64(&hw_stats->tx_mcast_packets) +
8440 get_stat64(&hw_stats->tx_bcast_packets);
8441
8442 stats->rx_bytes = old_stats->rx_bytes +
8443 get_stat64(&hw_stats->rx_octets);
8444 stats->tx_bytes = old_stats->tx_bytes +
8445 get_stat64(&hw_stats->tx_octets);
8446
8447 stats->rx_errors = old_stats->rx_errors +
4f63b877 8448 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8449 stats->tx_errors = old_stats->tx_errors +
8450 get_stat64(&hw_stats->tx_errors) +
8451 get_stat64(&hw_stats->tx_mac_errors) +
8452 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8453 get_stat64(&hw_stats->tx_discards);
8454
8455 stats->multicast = old_stats->multicast +
8456 get_stat64(&hw_stats->rx_mcast_packets);
8457 stats->collisions = old_stats->collisions +
8458 get_stat64(&hw_stats->tx_collisions);
8459
8460 stats->rx_length_errors = old_stats->rx_length_errors +
8461 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8462 get_stat64(&hw_stats->rx_undersize_packets);
8463
8464 stats->rx_over_errors = old_stats->rx_over_errors +
8465 get_stat64(&hw_stats->rxbds_empty);
8466 stats->rx_frame_errors = old_stats->rx_frame_errors +
8467 get_stat64(&hw_stats->rx_align_errors);
8468 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8469 get_stat64(&hw_stats->tx_discards);
8470 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8471 get_stat64(&hw_stats->tx_carrier_sense_errors);
8472
8473 stats->rx_crc_errors = old_stats->rx_crc_errors +
8474 calc_crc_errors(tp);
8475
4f63b877
JL		 8476 stats->rx_missed_errors = old_stats->rx_missed_errors +
8477 get_stat64(&hw_stats->rx_discards);
8478
1da177e4
LT		 8479 return stats;
8480}
8481
8482static inline u32 calc_crc(unsigned char *buf, int len)
8483{
8484 u32 reg;
8485 u32 tmp;
8486 int j, k;
8487
8488 reg = 0xffffffff;
8489
8490 for (j = 0; j < len; j++) {
8491 reg ^= buf[j];
8492
8493 for (k = 0; k < 8; k++) {
8494 tmp = reg & 0x01;
8495
8496 reg >>= 1;
8497
8498 if (tmp) {
8499 reg ^= 0xedb88320;
8500 }
8501 }
8502 }
8503
8504 return ~reg;
8505}
8506
8507static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8508{
8509 /* accept or reject all multicast frames */
8510 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8511 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8512 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8513 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8514}
8515
8516static void __tg3_set_rx_mode(struct net_device *dev)
8517{
8518 struct tg3 *tp = netdev_priv(dev);
8519 u32 rx_mode;
8520
8521 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8522 RX_MODE_KEEP_VLAN_TAG);
8523
8524 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8525 * flag clear.
8526 */
8527#if TG3_VLAN_TAG_USED
8528 if (!tp->vlgrp &&
8529 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8530 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8531#else
8532 /* By definition, VLAN is disabled always in this
8533 * case.
8534 */
8535 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8536 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8537#endif
8538
8539 if (dev->flags & IFF_PROMISC) {
8540 /* Promiscuous mode. */
8541 rx_mode |= RX_MODE_PROMISC;
8542 } else if (dev->flags & IFF_ALLMULTI) {
8543 /* Accept all multicast. */
8544 tg3_set_multi (tp, 1);
8545 } else if (dev->mc_count < 1) {
8546 /* Reject all multicast. */
8547 tg3_set_multi (tp, 0);
8548 } else {
8549 /* Accept one or more multicast(s). */
8550 struct dev_mc_list *mclist;
8551 unsigned int i;
8552 u32 mc_filter[4] = { 0, };
8553 u32 regidx;
8554 u32 bit;
8555 u32 crc;
8556
8557 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8558 i++, mclist = mclist->next) {
8559
8560 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8561 bit = ~crc & 0x7f;
8562 regidx = (bit & 0x60) >> 5;
8563 bit &= 0x1f;
8564 mc_filter[regidx] |= (1 << bit);
8565 }
8566
8567 tw32(MAC_HASH_REG_0, mc_filter[0]);
8568 tw32(MAC_HASH_REG_1, mc_filter[1]);
8569 tw32(MAC_HASH_REG_2, mc_filter[2]);
8570 tw32(MAC_HASH_REG_3, mc_filter[3]);
8571 }
8572
8573 if (rx_mode != tp->rx_mode) {
8574 tp->rx_mode = rx_mode;
8575 tw32_f(MAC_RX_MODE, rx_mode);
8576 udelay(10);
8577 }
8578}
8579
8580static void tg3_set_rx_mode(struct net_device *dev)
8581{
8582 struct tg3 *tp = netdev_priv(dev);
8583
e75f7c90
MC		 8584 if (!netif_running(dev))
8585 return;
8586
f47c11ee 8587 tg3_full_lock(tp, 0);
1da177e4 8588 __tg3_set_rx_mode(dev);
f47c11ee 8589 tg3_full_unlock(tp);
1da177e4
LT		 8590}
8591
8592#define TG3_REGDUMP_LEN (32 * 1024)
8593
8594static int tg3_get_regs_len(struct net_device *dev)
8595{
8596 return TG3_REGDUMP_LEN;
8597}
8598
8599static void tg3_get_regs(struct net_device *dev,
8600 struct ethtool_regs *regs, void *_p)
8601{
8602 u32 *p = _p;
8603 struct tg3 *tp = netdev_priv(dev);
8604 u8 *orig_p = _p;
8605 int i;
8606
8607 regs->version = 0;
8608
8609 memset(p, 0, TG3_REGDUMP_LEN);
8610
bc1c7567
MC		 8611 if (tp->link_config.phy_is_low_power)
8612 return;
8613
f47c11ee 8614 tg3_full_lock(tp, 0);
1da177e4
LT		 8615
8616#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8617#define GET_REG32_LOOP(base,len) \
8618do { p = (u32 *)(orig_p + (base)); \
8619 for (i = 0; i < len; i += 4) \
8620 __GET_REG32((base) + i); \
8621} while (0)
8622#define GET_REG32_1(reg) \
8623do { p = (u32 *)(orig_p + (reg)); \
8624 __GET_REG32((reg)); \
8625} while (0)
8626
8627 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8628 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8629 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8630 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8631 GET_REG32_1(SNDDATAC_MODE);
8632 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8633 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8634 GET_REG32_1(SNDBDC_MODE);
8635 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8636 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8637 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8638 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8639 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8640 GET_REG32_1(RCVDCC_MODE);
8641 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8642 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8643 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8644 GET_REG32_1(MBFREE_MODE);
8645 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8646 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8647 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8648 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8649 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8650 GET_REG32_1(RX_CPU_MODE);
8651 GET_REG32_1(RX_CPU_STATE);
8652 GET_REG32_1(RX_CPU_PGMCTR);
8653 GET_REG32_1(RX_CPU_HWBKPT);
8654 GET_REG32_1(TX_CPU_MODE);
8655 GET_REG32_1(TX_CPU_STATE);
8656 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8657 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8658 GET_REG32_LOOP(FTQ_RESET, 0x120);
8659 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8660 GET_REG32_1(DMAC_MODE);
8661 GET_REG32_LOOP(GRC_MODE, 0x4c);
8662 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8663 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8664
8665#undef __GET_REG32
8666#undef GET_REG32_LOOP
8667#undef GET_REG32_1
8668
f47c11ee 8669 tg3_full_unlock(tp);
1da177e4
LT		 8670}
8671
8672static int tg3_get_eeprom_len(struct net_device *dev)
8673{
8674 struct tg3 *tp = netdev_priv(dev);
8675
8676 return tp->nvram_size;
8677}
8678
1da177e4
LT		 8679static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8680{
8681 struct tg3 *tp = netdev_priv(dev);
8682 int ret;
8683 u8 *pd;
b9fc7dc5 8684 u32 i, offset, len, b_offset, b_count;
a9dc529d 8685 __be32 val;
1da177e4 8686
df259d8c
MC		 8687 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8688 return -EINVAL;
8689
bc1c7567
MC		 8690 if (tp->link_config.phy_is_low_power)
8691 return -EAGAIN;
8692
1da177e4
LT		 8693 offset = eeprom->offset;
8694 len = eeprom->len;
8695 eeprom->len = 0;
8696
8697 eeprom->magic = TG3_EEPROM_MAGIC;
8698
8699 if (offset & 3) {
8700 /* adjustments to start on required 4 byte boundary */
8701 b_offset = offset & 3;
8702 b_count = 4 - b_offset;
8703 if (b_count > len) {
8704 /* i.e. offset=1 len=2 */
8705 b_count = len;
8706 }
a9dc529d 8707 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8708 if (ret)
8709 return ret;
1da177e4
LT		 8710 memcpy(data, ((char*)&val) + b_offset, b_count);
8711 len -= b_count;
8712 offset += b_count;
8713 eeprom->len += b_count;
8714 }
8715
8716 /* read bytes upto the last 4 byte boundary */
8717 pd = &data[eeprom->len];
8718 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8719 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8720 if (ret) {
8721 eeprom->len += i;
8722 return ret;
8723 }
1da177e4
LT		 8724 memcpy(pd + i, &val, 4);
8725 }
8726 eeprom->len += i;
8727
8728 if (len & 3) {
8729 /* read last bytes not ending on 4 byte boundary */
8730 pd = &data[eeprom->len];
8731 b_count = len & 3;
8732 b_offset = offset + len - b_count;
a9dc529d 8733 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8734 if (ret)
8735 return ret;
b9fc7dc5 8736 memcpy(pd, &val, b_count);
1da177e4
LT		 8737 eeprom->len += b_count;
8738 }
8739 return 0;
8740}
8741
6aa20a22 8742static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8743
8744static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8745{
8746 struct tg3 *tp = netdev_priv(dev);
8747 int ret;
b9fc7dc5 8748 u32 offset, len, b_offset, odd_len;
1da177e4 8749 u8 *buf;
a9dc529d 8750 __be32 start, end;
1da177e4 8751
bc1c7567
MC		 8752 if (tp->link_config.phy_is_low_power)
8753 return -EAGAIN;
8754
df259d8c
MC		 8755 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8756 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 8757 return -EINVAL;
8758
8759 offset = eeprom->offset;
8760 len = eeprom->len;
8761
8762 if ((b_offset = (offset & 3))) {
8763 /* adjustments to start on required 4 byte boundary */
a9dc529d 8764 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8765 if (ret)
8766 return ret;
1da177e4
LT		 8767 len += b_offset;
8768 offset &= ~3;
1c8594b4
MC		 8769 if (len < 4)
8770 len = 4;
1da177e4
LT		 8771 }
8772
8773 odd_len = 0;
1c8594b4 8774 if (len & 3) {
1da177e4
LT		 8775 /* adjustments to end on required 4 byte boundary */
8776 odd_len = 1;
8777 len = (len + 3) & ~3;
a9dc529d 8778 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8779 if (ret)
8780 return ret;
1da177e4
LT		 8781 }
8782
8783 buf = data;
8784 if (b_offset || odd_len) {
8785 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8786 if (!buf)
1da177e4
LT		 8787 return -ENOMEM;
8788 if (b_offset)
8789 memcpy(buf, &start, 4);
8790 if (odd_len)
8791 memcpy(buf+len-4, &end, 4);
8792 memcpy(buf + b_offset, data, eeprom->len);
8793 }
8794
8795 ret = tg3_nvram_write_block(tp, offset, len, buf);
8796
8797 if (buf != data)
8798 kfree(buf);
8799
8800 return ret;
8801}
8802
8803static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8804{
b02fd9e3
MC		 8805 struct tg3 *tp = netdev_priv(dev);
8806
8807 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8808 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8809 return -EAGAIN;
298cf9be 8810 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8811 }
6aa20a22 8812
1da177e4
LT		 8813 cmd->supported = (SUPPORTED_Autoneg);
8814
8815 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8816 cmd->supported |= (SUPPORTED_1000baseT_Half |
8817 SUPPORTED_1000baseT_Full);
8818
ef348144 8819 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8820 cmd->supported |= (SUPPORTED_100baseT_Half |
8821 SUPPORTED_100baseT_Full |
8822 SUPPORTED_10baseT_Half |
8823 SUPPORTED_10baseT_Full |
3bebab59 8824 SUPPORTED_TP);
ef348144
KK		 8825 cmd->port = PORT_TP;
8826 } else {
1da177e4 8827 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8828 cmd->port = PORT_FIBRE;
8829 }
6aa20a22 8830
1da177e4
LT		 8831 cmd->advertising = tp->link_config.advertising;
8832 if (netif_running(dev)) {
8833 cmd->speed = tp->link_config.active_speed;
8834 cmd->duplex = tp->link_config.active_duplex;
8835 }
1da177e4 8836 cmd->phy_address = PHY_ADDR;
7e5856bd 8837 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8838 cmd->autoneg = tp->link_config.autoneg;
8839 cmd->maxtxpkt = 0;
8840 cmd->maxrxpkt = 0;
8841 return 0;
8842}
6aa20a22 8843
1da177e4
LT		 8844static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8845{
8846 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8847
b02fd9e3
MC		 8848 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8849 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8850 return -EAGAIN;
298cf9be 8851 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8852 }
8853
7e5856bd
MC		 8854 if (cmd->autoneg != AUTONEG_ENABLE &&
8855 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8856 return -EINVAL;
7e5856bd
MC		 8857
8858 if (cmd->autoneg == AUTONEG_DISABLE &&
8859 cmd->duplex != DUPLEX_FULL &&
8860 cmd->duplex != DUPLEX_HALF)
37ff238d 8861 return -EINVAL;
1da177e4 8862
7e5856bd
MC		 8863 if (cmd->autoneg == AUTONEG_ENABLE) {
8864 u32 mask = ADVERTISED_Autoneg |
8865 ADVERTISED_Pause |
8866 ADVERTISED_Asym_Pause;
8867
8868 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8869 mask |= ADVERTISED_1000baseT_Half |
8870 ADVERTISED_1000baseT_Full;
8871
8872 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8873 mask |= ADVERTISED_100baseT_Half |
8874 ADVERTISED_100baseT_Full |
8875 ADVERTISED_10baseT_Half |
8876 ADVERTISED_10baseT_Full |
8877 ADVERTISED_TP;
8878 else
8879 mask |= ADVERTISED_FIBRE;
8880
8881 if (cmd->advertising & ~mask)
8882 return -EINVAL;
8883
8884 mask &= (ADVERTISED_1000baseT_Half |
8885 ADVERTISED_1000baseT_Full |
8886 ADVERTISED_100baseT_Half |
8887 ADVERTISED_100baseT_Full |
8888 ADVERTISED_10baseT_Half |
8889 ADVERTISED_10baseT_Full);
8890
8891 cmd->advertising &= mask;
8892 } else {
8893 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8894 if (cmd->speed != SPEED_1000)
8895 return -EINVAL;
8896
8897 if (cmd->duplex != DUPLEX_FULL)
8898 return -EINVAL;
8899 } else {
8900 if (cmd->speed != SPEED_100 &&
8901 cmd->speed != SPEED_10)
8902 return -EINVAL;
8903 }
8904 }
8905
f47c11ee 8906 tg3_full_lock(tp, 0);
1da177e4
LT		 8907
8908 tp->link_config.autoneg = cmd->autoneg;
8909 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8910 tp->link_config.advertising = (cmd->advertising |
8911 ADVERTISED_Autoneg);
1da177e4
LT		 8912 tp->link_config.speed = SPEED_INVALID;
8913 tp->link_config.duplex = DUPLEX_INVALID;
8914 } else {
8915 tp->link_config.advertising = 0;
8916 tp->link_config.speed = cmd->speed;
8917 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8918 }
6aa20a22 8919
24fcad6b
MC		 8920 tp->link_config.orig_speed = tp->link_config.speed;
8921 tp->link_config.orig_duplex = tp->link_config.duplex;
8922 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8923
1da177e4
LT		 8924 if (netif_running(dev))
8925 tg3_setup_phy(tp, 1);
8926
f47c11ee 8927 tg3_full_unlock(tp);
6aa20a22 8928
1da177e4
LT		 8929 return 0;
8930}
6aa20a22 8931
1da177e4
LT		 8932static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8933{
8934 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8935
1da177e4
LT		 8936 strcpy(info->driver, DRV_MODULE_NAME);
8937 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8938 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8939 strcpy(info->bus_info, pci_name(tp->pdev));
8940}
6aa20a22 8941
1da177e4
LT		 8942static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8943{
8944 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8945
12dac075
RW		 8946 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8947 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8948 wol->supported = WAKE_MAGIC;
8949 else
8950 wol->supported = 0;
1da177e4 8951 wol->wolopts = 0;
05ac4cb7
MC		 8952 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8953 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8954 wol->wolopts = WAKE_MAGIC;
8955 memset(&wol->sopass, 0, sizeof(wol->sopass));
8956}
6aa20a22 8957
1da177e4
LT		 8958static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8959{
8960 struct tg3 *tp = netdev_priv(dev);
12dac075 8961 struct device *dp = &tp->pdev->dev;
6aa20a22 8962
1da177e4
LT		 8963 if (wol->wolopts & ~WAKE_MAGIC)
8964 return -EINVAL;
8965 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8966 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8967 return -EINVAL;
6aa20a22 8968
f47c11ee 8969 spin_lock_bh(&tp->lock);
12dac075 8970 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8971 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8972 device_set_wakeup_enable(dp, true);
8973 } else {
1da177e4 8974 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8975 device_set_wakeup_enable(dp, false);
8976 }
f47c11ee 8977 spin_unlock_bh(&tp->lock);
6aa20a22 8978
1da177e4
LT		 8979 return 0;
8980}
6aa20a22 8981
1da177e4
LT		 8982static u32 tg3_get_msglevel(struct net_device *dev)
8983{
8984 struct tg3 *tp = netdev_priv(dev);
8985 return tp->msg_enable;
8986}
6aa20a22 8987
1da177e4
LT		 8988static void tg3_set_msglevel(struct net_device *dev, u32 value)
8989{
8990 struct tg3 *tp = netdev_priv(dev);
8991 tp->msg_enable = value;
8992}
6aa20a22 8993
1da177e4
LT		 8994static int tg3_set_tso(struct net_device *dev, u32 value)
8995{
8996 struct tg3 *tp = netdev_priv(dev);
8997
8998 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8999 if (value)
9000 return -EINVAL;
9001 return 0;
9002 }
027455ad
MC		 9003 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9004 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9005 if (value) {
b0026624 9006 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9008 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9009 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 9010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9012 dev->features |= NETIF_F_TSO_ECN;
9013 } else
9014 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9015 }
1da177e4
LT		 9016 return ethtool_op_set_tso(dev, value);
9017}
6aa20a22 9018
1da177e4
LT		 9019static int tg3_nway_reset(struct net_device *dev)
9020{
9021 struct tg3 *tp = netdev_priv(dev);
1da177e4 9022 int r;
6aa20a22 9023
1da177e4
LT		 9024 if (!netif_running(dev))
9025 return -EAGAIN;
9026
c94e3941
MC		 9027 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9028 return -EINVAL;
9029
b02fd9e3
MC		 9030 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9031 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9032 return -EAGAIN;
298cf9be 9033 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 9034 } else {
9035 u32 bmcr;
9036
9037 spin_lock_bh(&tp->lock);
9038 r = -EINVAL;
9039 tg3_readphy(tp, MII_BMCR, &bmcr);
9040 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9041 ((bmcr & BMCR_ANENABLE) ||
9042 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9043 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9044 BMCR_ANENABLE);
9045 r = 0;
9046 }
9047 spin_unlock_bh(&tp->lock);
1da177e4 9048 }
6aa20a22 9049
1da177e4
LT		 9050 return r;
9051}
6aa20a22 9052
1da177e4
LT		 9053static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9054{
9055 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9056
1da177e4
LT		 9057 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9058 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9059 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9060 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9061 else
9062 ering->rx_jumbo_max_pending = 0;
9063
9064 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9065
9066 ering->rx_pending = tp->rx_pending;
9067 ering->rx_mini_pending = 0;
4f81c32b
MC		 9068 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9069 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9070 else
9071 ering->rx_jumbo_pending = 0;
9072
1da177e4
LT		 9073 ering->tx_pending = tp->tx_pending;
9074}
6aa20a22 9075
1da177e4
LT		 9076static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9077{
9078 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 9079 int irq_sync = 0, err = 0;
6aa20a22 9080
1da177e4
LT		 9081 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9082 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9083 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9084 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9085 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9086 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9087 return -EINVAL;
6aa20a22 9088
bbe832c0 9089 if (netif_running(dev)) {
b02fd9e3 9090 tg3_phy_stop(tp);
1da177e4 9091 tg3_netif_stop(tp);
bbe832c0
MC		 9092 irq_sync = 1;
9093 }
1da177e4 9094
bbe832c0 9095 tg3_full_lock(tp, irq_sync);
6aa20a22 9096
1da177e4
LT		 9097 tp->rx_pending = ering->rx_pending;
9098
9099 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9100 tp->rx_pending > 63)
9101 tp->rx_pending = 63;
9102 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9103 tp->tx_pending = ering->tx_pending;
9104
9105 if (netif_running(dev)) {
944d980e 9106 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9107 err = tg3_restart_hw(tp, 1);
9108 if (!err)
9109 tg3_netif_start(tp);
1da177e4
LT		 9110 }
9111
f47c11ee 9112 tg3_full_unlock(tp);
6aa20a22 9113
b02fd9e3
MC		 9114 if (irq_sync && !err)
9115 tg3_phy_start(tp);
9116
b9ec6c1b 9117 return err;
1da177e4 9118}
6aa20a22 9119
1da177e4
LT		 9120static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9121{
9122 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9123
1da177e4 9124 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9125
e18ce346 9126 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9127 epause->rx_pause = 1;
9128 else
9129 epause->rx_pause = 0;
9130
e18ce346 9131 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9132 epause->tx_pause = 1;
9133 else
9134 epause->tx_pause = 0;
1da177e4 9135}
6aa20a22 9136
1da177e4
LT		 9137static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9138{
9139 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9140 int err = 0;
6aa20a22 9141
b02fd9e3
MC		 9142 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9143 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9144 return -EAGAIN;
1da177e4 9145
b02fd9e3
MC		 9146 if (epause->autoneg) {
9147 u32 newadv;
9148 struct phy_device *phydev;
f47c11ee 9149
298cf9be 9150 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9151
b02fd9e3
MC		 9152 if (epause->rx_pause) {
9153 if (epause->tx_pause)
9154 newadv = ADVERTISED_Pause;
9155 else
9156 newadv = ADVERTISED_Pause |
9157 ADVERTISED_Asym_Pause;
9158 } else if (epause->tx_pause) {
9159 newadv = ADVERTISED_Asym_Pause;
9160 } else
9161 newadv = 0;
9162
9163 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9164 u32 oldadv = phydev->advertising &
9165 (ADVERTISED_Pause |
9166 ADVERTISED_Asym_Pause);
9167 if (oldadv != newadv) {
9168 phydev->advertising &=
9169 ~(ADVERTISED_Pause |
9170 ADVERTISED_Asym_Pause);
9171 phydev->advertising |= newadv;
9172 err = phy_start_aneg(phydev);
9173 }
9174 } else {
9175 tp->link_config.advertising &=
9176 ~(ADVERTISED_Pause |
9177 ADVERTISED_Asym_Pause);
9178 tp->link_config.advertising |= newadv;
9179 }
9180 } else {
9181 if (epause->rx_pause)
e18ce346 9182 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9183 else
e18ce346 9184 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9185
b02fd9e3 9186 if (epause->tx_pause)
e18ce346 9187 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9188 else
e18ce346 9189 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9190
9191 if (netif_running(dev))
9192 tg3_setup_flow_control(tp, 0, 0);
9193 }
9194 } else {
9195 int irq_sync = 0;
9196
9197 if (netif_running(dev)) {
9198 tg3_netif_stop(tp);
9199 irq_sync = 1;
9200 }
9201
9202 tg3_full_lock(tp, irq_sync);
9203
9204 if (epause->autoneg)
9205 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9206 else
9207 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9208 if (epause->rx_pause)
e18ce346 9209 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9210 else
e18ce346 9211 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9212 if (epause->tx_pause)
e18ce346 9213 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9214 else
e18ce346 9215 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9216
9217 if (netif_running(dev)) {
9218 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9219 err = tg3_restart_hw(tp, 1);
9220 if (!err)
9221 tg3_netif_start(tp);
9222 }
9223
9224 tg3_full_unlock(tp);
9225 }
6aa20a22 9226
b9ec6c1b 9227 return err;
1da177e4 9228}
6aa20a22 9229
1da177e4
LT		 9230static u32 tg3_get_rx_csum(struct net_device *dev)
9231{
9232 struct tg3 *tp = netdev_priv(dev);
9233 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9234}
6aa20a22 9235
1da177e4
LT		 9236static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9237{
9238 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9239
1da177e4
LT		 9240 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9241 if (data != 0)
9242 return -EINVAL;
9243 return 0;
9244 }
6aa20a22 9245
f47c11ee 9246 spin_lock_bh(&tp->lock);
1da177e4
LT		 9247 if (data)
9248 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9249 else
9250 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9251 spin_unlock_bh(&tp->lock);
6aa20a22 9252
1da177e4
LT		 9253 return 0;
9254}
6aa20a22 9255
1da177e4
LT		 9256static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9257{
9258 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9259
1da177e4
LT		 9260 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9261 if (data != 0)
9262 return -EINVAL;
9263 return 0;
9264 }
6aa20a22 9265
321d32a0 9266 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9267 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9268 else
9c27dbdf 9269 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9270
9271 return 0;
9272}
9273
b9f2c044 9274static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9275{
b9f2c044
JG		 9276 switch (sset) {
9277 case ETH_SS_TEST:
9278 return TG3_NUM_TEST;
9279 case ETH_SS_STATS:
9280 return TG3_NUM_STATS;
9281 default:
9282 return -EOPNOTSUPP;
9283 }
4cafd3f5
MC		 9284}
9285
1da177e4
LT		 9286static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9287{
9288 switch (stringset) {
9289 case ETH_SS_STATS:
9290 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9291 break;
4cafd3f5
MC		 9292 case ETH_SS_TEST:
9293 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9294 break;
1da177e4
LT		 9295 default:
9296 WARN_ON(1); /* we need a WARN() */
9297 break;
9298 }
9299}
9300
4009a93d
MC		 9301static int tg3_phys_id(struct net_device *dev, u32 data)
9302{
9303 struct tg3 *tp = netdev_priv(dev);
9304 int i;
9305
9306 if (!netif_running(tp->dev))
9307 return -EAGAIN;
9308
9309 if (data == 0)
759afc31 9310 data = UINT_MAX / 2;
4009a93d
MC		 9311
9312 for (i = 0; i < (data * 2); i++) {
9313 if ((i % 2) == 0)
9314 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9315 LED_CTRL_1000MBPS_ON |
9316 LED_CTRL_100MBPS_ON |
9317 LED_CTRL_10MBPS_ON |
9318 LED_CTRL_TRAFFIC_OVERRIDE |
9319 LED_CTRL_TRAFFIC_BLINK |
9320 LED_CTRL_TRAFFIC_LED);
6aa20a22 9321
4009a93d
MC		 9322 else
9323 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9324 LED_CTRL_TRAFFIC_OVERRIDE);
9325
9326 if (msleep_interruptible(500))
9327 break;
9328 }
9329 tw32(MAC_LED_CTRL, tp->led_ctrl);
9330 return 0;
9331}
9332
1da177e4
LT		 9333static void tg3_get_ethtool_stats (struct net_device *dev,
9334 struct ethtool_stats *estats, u64 *tmp_stats)
9335{
9336 struct tg3 *tp = netdev_priv(dev);
9337 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9338}
9339
566f86ad 9340#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9341#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9342#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9343#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9344#define NVRAM_SELFBOOT_HW_SIZE 0x20
9345#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9346
9347static int tg3_test_nvram(struct tg3 *tp)
9348{
b9fc7dc5 9349 u32 csum, magic;
a9dc529d 9350 __be32 *buf;
ab0049b4 9351 int i, j, k, err = 0, size;
566f86ad 9352
df259d8c
MC		 9353 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9354 return 0;
9355
e4f34110 9356 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9357 return -EIO;
9358
1b27777a
MC		 9359 if (magic == TG3_EEPROM_MAGIC)
9360 size = NVRAM_TEST_SIZE;
b16250e3 9361 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9362 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9363 TG3_EEPROM_SB_FORMAT_1) {
9364 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9365 case TG3_EEPROM_SB_REVISION_0:
9366 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9367 break;
9368 case TG3_EEPROM_SB_REVISION_2:
9369 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9370 break;
9371 case TG3_EEPROM_SB_REVISION_3:
9372 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9373 break;
9374 default:
9375 return 0;
9376 }
9377 } else
1b27777a 9378 return 0;
b16250e3
MC		 9379 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9380 size = NVRAM_SELFBOOT_HW_SIZE;
9381 else
1b27777a
MC		 9382 return -EIO;
9383
9384 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9385 if (buf == NULL)
9386 return -ENOMEM;
9387
1b27777a
MC		 9388 err = -EIO;
9389 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9390 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9391 if (err)
566f86ad 9392 break;
566f86ad 9393 }
1b27777a 9394 if (i < size)
566f86ad
MC		 9395 goto out;
9396
1b27777a 9397 /* Selfboot format */
a9dc529d 9398 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9399 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9400 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9401 u8 *buf8 = (u8 *) buf, csum8 = 0;
9402
b9fc7dc5 9403 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9404 TG3_EEPROM_SB_REVISION_2) {
9405 /* For rev 2, the csum doesn't include the MBA. */
9406 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9407 csum8 += buf8[i];
9408 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9409 csum8 += buf8[i];
9410 } else {
9411 for (i = 0; i < size; i++)
9412 csum8 += buf8[i];
9413 }
1b27777a 9414
ad96b485
AB		 9415 if (csum8 == 0) {
9416 err = 0;
9417 goto out;
9418 }
9419
9420 err = -EIO;
9421 goto out;
1b27777a 9422 }
566f86ad 9423
b9fc7dc5 9424 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9425 TG3_EEPROM_MAGIC_HW) {
9426 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9427 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9428 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9429
9430 /* Separate the parity bits and the data bytes. */
9431 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9432 if ((i == 0) || (i == 8)) {
9433 int l;
9434 u8 msk;
9435
9436 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9437 parity[k++] = buf8[i] & msk;
9438 i++;
9439 }
9440 else if (i == 16) {
9441 int l;
9442 u8 msk;
9443
9444 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9445 parity[k++] = buf8[i] & msk;
9446 i++;
9447
9448 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9449 parity[k++] = buf8[i] & msk;
9450 i++;
9451 }
9452 data[j++] = buf8[i];
9453 }
9454
9455 err = -EIO;
9456 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9457 u8 hw8 = hweight8(data[i]);
9458
9459 if ((hw8 & 0x1) && parity[i])
9460 goto out;
9461 else if (!(hw8 & 0x1) && !parity[i])
9462 goto out;
9463 }
9464 err = 0;
9465 goto out;
9466 }
9467
566f86ad
MC		 9468 /* Bootstrap checksum at offset 0x10 */
9469 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9470 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9471 goto out;
9472
9473 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9474 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9475 if (csum != be32_to_cpu(buf[0xfc/4]))
9476 goto out;
566f86ad
MC		 9477
9478 err = 0;
9479
9480out:
9481 kfree(buf);
9482 return err;
9483}
9484
ca43007a
MC		 9485#define TG3_SERDES_TIMEOUT_SEC 2
9486#define TG3_COPPER_TIMEOUT_SEC 6
9487
9488static int tg3_test_link(struct tg3 *tp)
9489{
9490 int i, max;
9491
9492 if (!netif_running(tp->dev))
9493 return -ENODEV;
9494
4c987487 9495 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9496 max = TG3_SERDES_TIMEOUT_SEC;
9497 else
9498 max = TG3_COPPER_TIMEOUT_SEC;
9499
9500 for (i = 0; i < max; i++) {
9501 if (netif_carrier_ok(tp->dev))
9502 return 0;
9503
9504 if (msleep_interruptible(1000))
9505 break;
9506 }
9507
9508 return -EIO;
9509}
9510
a71116d1 9511/* Only test the commonly used registers */
30ca3e37 9512static int tg3_test_registers(struct tg3 *tp)
a71116d1 9513{
b16250e3 9514 int i, is_5705, is_5750;
a71116d1
MC		 9515 u32 offset, read_mask, write_mask, val, save_val, read_val;
9516 static struct {
9517 u16 offset;
9518 u16 flags;
9519#define TG3_FL_5705 0x1
9520#define TG3_FL_NOT_5705 0x2
9521#define TG3_FL_NOT_5788 0x4
b16250e3 9522#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9523 u32 read_mask;
9524 u32 write_mask;
9525 } reg_tbl[] = {
9526 /* MAC Control Registers */
9527 { MAC_MODE, TG3_FL_NOT_5705,
9528 0x00000000, 0x00ef6f8c },
9529 { MAC_MODE, TG3_FL_5705,
9530 0x00000000, 0x01ef6b8c },
9531 { MAC_STATUS, TG3_FL_NOT_5705,
9532 0x03800107, 0x00000000 },
9533 { MAC_STATUS, TG3_FL_5705,
9534 0x03800100, 0x00000000 },
9535 { MAC_ADDR_0_HIGH, 0x0000,
9536 0x00000000, 0x0000ffff },
9537 { MAC_ADDR_0_LOW, 0x0000,
9538 0x00000000, 0xffffffff },
9539 { MAC_RX_MTU_SIZE, 0x0000,
9540 0x00000000, 0x0000ffff },
9541 { MAC_TX_MODE, 0x0000,
9542 0x00000000, 0x00000070 },
9543 { MAC_TX_LENGTHS, 0x0000,
9544 0x00000000, 0x00003fff },
9545 { MAC_RX_MODE, TG3_FL_NOT_5705,
9546 0x00000000, 0x000007fc },
9547 { MAC_RX_MODE, TG3_FL_5705,
9548 0x00000000, 0x000007dc },
9549 { MAC_HASH_REG_0, 0x0000,
9550 0x00000000, 0xffffffff },
9551 { MAC_HASH_REG_1, 0x0000,
9552 0x00000000, 0xffffffff },
9553 { MAC_HASH_REG_2, 0x0000,
9554 0x00000000, 0xffffffff },
9555 { MAC_HASH_REG_3, 0x0000,
9556 0x00000000, 0xffffffff },
9557
9558 /* Receive Data and Receive BD Initiator Control Registers. */
9559 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9560 0x00000000, 0xffffffff },
9561 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9562 0x00000000, 0xffffffff },
9563 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9564 0x00000000, 0x00000003 },
9565 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9566 0x00000000, 0xffffffff },
9567 { RCVDBDI_STD_BD+0, 0x0000,
9568 0x00000000, 0xffffffff },
9569 { RCVDBDI_STD_BD+4, 0x0000,
9570 0x00000000, 0xffffffff },
9571 { RCVDBDI_STD_BD+8, 0x0000,
9572 0x00000000, 0xffff0002 },
9573 { RCVDBDI_STD_BD+0xc, 0x0000,
9574 0x00000000, 0xffffffff },
6aa20a22 9575
a71116d1
MC		 9576 /* Receive BD Initiator Control Registers. */
9577 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9578 0x00000000, 0xffffffff },
9579 { RCVBDI_STD_THRESH, TG3_FL_5705,
9580 0x00000000, 0x000003ff },
9581 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9582 0x00000000, 0xffffffff },
6aa20a22 9583
a71116d1
MC		 9584 /* Host Coalescing Control Registers. */
9585 { HOSTCC_MODE, TG3_FL_NOT_5705,
9586 0x00000000, 0x00000004 },
9587 { HOSTCC_MODE, TG3_FL_5705,
9588 0x00000000, 0x000000f6 },
9589 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9590 0x00000000, 0xffffffff },
9591 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9592 0x00000000, 0x000003ff },
9593 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9594 0x00000000, 0xffffffff },
9595 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9596 0x00000000, 0x000003ff },
9597 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9598 0x00000000, 0xffffffff },
9599 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9600 0x00000000, 0x000000ff },
9601 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9602 0x00000000, 0xffffffff },
9603 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9604 0x00000000, 0x000000ff },
9605 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9606 0x00000000, 0xffffffff },
9607 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9608 0x00000000, 0xffffffff },
9609 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9610 0x00000000, 0xffffffff },
9611 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9612 0x00000000, 0x000000ff },
9613 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9614 0x00000000, 0xffffffff },
9615 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9616 0x00000000, 0x000000ff },
9617 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9618 0x00000000, 0xffffffff },
9619 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9620 0x00000000, 0xffffffff },
9621 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9622 0x00000000, 0xffffffff },
9623 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9624 0x00000000, 0xffffffff },
9625 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9626 0x00000000, 0xffffffff },
9627 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9628 0xffffffff, 0x00000000 },
9629 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9630 0xffffffff, 0x00000000 },
9631
9632 /* Buffer Manager Control Registers. */
b16250e3 9633 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9634 0x00000000, 0x007fff80 },
b16250e3 9635 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9636 0x00000000, 0x007fffff },
9637 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9638 0x00000000, 0x0000003f },
9639 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9640 0x00000000, 0x000001ff },
9641 { BUFMGR_MB_HIGH_WATER, 0x0000,
9642 0x00000000, 0x000001ff },
9643 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9644 0xffffffff, 0x00000000 },
9645 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9646 0xffffffff, 0x00000000 },
6aa20a22 9647
a71116d1
MC		 9648 /* Mailbox Registers */
9649 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9650 0x00000000, 0x000001ff },
9651 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9652 0x00000000, 0x000001ff },
9653 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9654 0x00000000, 0x000007ff },
9655 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9656 0x00000000, 0x000001ff },
9657
9658 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9659 };
9660
b16250e3
MC		 9661 is_5705 = is_5750 = 0;
9662 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9663 is_5705 = 1;
b16250e3
MC		 9664 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9665 is_5750 = 1;
9666 }
a71116d1
MC		 9667
9668 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9669 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9670 continue;
9671
9672 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9673 continue;
9674
9675 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9676 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9677 continue;
9678
b16250e3
MC		 9679 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9680 continue;
9681
a71116d1
MC		 9682 offset = (u32) reg_tbl[i].offset;
9683 read_mask = reg_tbl[i].read_mask;
9684 write_mask = reg_tbl[i].write_mask;
9685
9686 /* Save the original register content */
9687 save_val = tr32(offset);
9688
9689 /* Determine the read-only value. */
9690 read_val = save_val & read_mask;
9691
9692 /* Write zero to the register, then make sure the read-only bits
9693 * are not changed and the read/write bits are all zeros.
9694 */
9695 tw32(offset, 0);
9696
9697 val = tr32(offset);
9698
9699 /* Test the read-only and read/write bits. */
9700 if (((val & read_mask) != read_val) || (val & write_mask))
9701 goto out;
9702
9703 /* Write ones to all the bits defined by RdMask and WrMask, then
9704 * make sure the read-only bits are not changed and the
9705 * read/write bits are all ones.
9706 */
9707 tw32(offset, read_mask | write_mask);
9708
9709 val = tr32(offset);
9710
9711 /* Test the read-only bits. */
9712 if ((val & read_mask) != read_val)
9713 goto out;
9714
9715 /* Test the read/write bits. */
9716 if ((val & write_mask) != write_mask)
9717 goto out;
9718
9719 tw32(offset, save_val);
9720 }
9721
9722 return 0;
9723
9724out:
9f88f29f
MC		 9725 if (netif_msg_hw(tp))
9726 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9727 offset);
a71116d1
MC		 9728 tw32(offset, save_val);
9729 return -EIO;
9730}
9731
7942e1db
MC		 9732static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9733{
f71e1309 9734 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9735 int i;
9736 u32 j;
9737
e9edda69 9738 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9739 for (j = 0; j < len; j += 4) {
9740 u32 val;
9741
9742 tg3_write_mem(tp, offset + j, test_pattern[i]);
9743 tg3_read_mem(tp, offset + j, &val);
9744 if (val != test_pattern[i])
9745 return -EIO;
9746 }
9747 }
9748 return 0;
9749}
9750
9751static int tg3_test_memory(struct tg3 *tp)
9752{
9753 static struct mem_entry {
9754 u32 offset;
9755 u32 len;
9756 } mem_tbl_570x[] = {
38690194 9757 { 0x00000000, 0x00b50},
7942e1db
MC		 9758 { 0x00002000, 0x1c000},
9759 { 0xffffffff, 0x00000}
9760 }, mem_tbl_5705[] = {
9761 { 0x00000100, 0x0000c},
9762 { 0x00000200, 0x00008},
7942e1db
MC		 9763 { 0x00004000, 0x00800},
9764 { 0x00006000, 0x01000},
9765 { 0x00008000, 0x02000},
9766 { 0x00010000, 0x0e000},
9767 { 0xffffffff, 0x00000}
79f4d13a
MC		 9768 }, mem_tbl_5755[] = {
9769 { 0x00000200, 0x00008},
9770 { 0x00004000, 0x00800},
9771 { 0x00006000, 0x00800},
9772 { 0x00008000, 0x02000},
9773 { 0x00010000, 0x0c000},
9774 { 0xffffffff, 0x00000}
b16250e3
MC		 9775 }, mem_tbl_5906[] = {
9776 { 0x00000200, 0x00008},
9777 { 0x00004000, 0x00400},
9778 { 0x00006000, 0x00400},
9779 { 0x00008000, 0x01000},
9780 { 0x00010000, 0x01000},
9781 { 0xffffffff, 0x00000}
7942e1db
MC		 9782 };
9783 struct mem_entry *mem_tbl;
9784 int err = 0;
9785 int i;
9786
321d32a0
MC		 9787 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9788 mem_tbl = mem_tbl_5755;
9789 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9790 mem_tbl = mem_tbl_5906;
9791 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9792 mem_tbl = mem_tbl_5705;
9793 else
7942e1db
MC		 9794 mem_tbl = mem_tbl_570x;
9795
9796 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9797 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9798 mem_tbl[i].len)) != 0)
9799 break;
9800 }
6aa20a22 9801
7942e1db
MC		 9802 return err;
9803}
9804
9f40dead
MC		 9805#define TG3_MAC_LOOPBACK 0
9806#define TG3_PHY_LOOPBACK 1
9807
9808static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9809{
9f40dead 9810 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9811 u32 desc_idx;
9812 struct sk_buff *skb, *rx_skb;
9813 u8 *tx_data;
9814 dma_addr_t map;
9815 int num_pkts, tx_len, rx_len, i, err;
9816 struct tg3_rx_buffer_desc *desc;
21f581a5 9817 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 9818
9f40dead 9819 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9820 /* HW errata - mac loopback fails in some cases on 5780.
9821 * Normal traffic and PHY loopback are not affected by
9822 * errata.
9823 */
9824 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9825 return 0;
9826
9f40dead 9827 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9828 MAC_MODE_PORT_INT_LPBACK;
9829 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9830 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9831 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9832 mac_mode |= MAC_MODE_PORT_MODE_MII;
9833 else
9834 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9835 tw32(MAC_MODE, mac_mode);
9836 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9837 u32 val;
9838
7f97a4bd
MC		 9839 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9840 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 9841 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9842 } else
9843 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9844
9ef8ca99
MC		 9845 tg3_phy_toggle_automdix(tp, 0);
9846
3f7045c1 9847 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9848 udelay(40);
5d64ad34 9849
e8f3f6ca 9850 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 9851 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9853 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 9854 mac_mode |= MAC_MODE_PORT_MODE_MII;
9855 } else
9856 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9857
c94e3941
MC		 9858 /* reset to prevent losing 1st rx packet intermittently */
9859 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9860 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9861 udelay(10);
9862 tw32_f(MAC_RX_MODE, tp->rx_mode);
9863 }
e8f3f6ca
MC		 9864 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9865 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9866 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9867 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9868 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9869 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9870 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9871 }
9f40dead 9872 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9873 }
9874 else
9875 return -EINVAL;
c76949a6
MC		 9876
9877 err = -EIO;
9878
c76949a6 9879 tx_len = 1514;
a20e9c62 9880 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9881 if (!skb)
9882 return -ENOMEM;
9883
c76949a6
MC		 9884 tx_data = skb_put(skb, tx_len);
9885 memcpy(tx_data, tp->dev->dev_addr, 6);
9886 memset(tx_data + 6, 0x0, 8);
9887
9888 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9889
9890 for (i = 14; i < tx_len; i++)
9891 tx_data[i] = (u8) (i & 0xff);
9892
9893 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9894
9895 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9896 HOSTCC_MODE_NOW);
9897
9898 udelay(10);
9899
9900 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9901
c76949a6
MC		 9902 num_pkts = 0;
9903
9f40dead 9904 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9905
9f40dead 9906 tp->tx_prod++;
c76949a6
MC		 9907 num_pkts++;
9908
9f40dead
MC		 9909 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9910 tp->tx_prod);
09ee929c 9911 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9912
9913 udelay(10);
9914
3f7045c1
MC		 9915 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9916 for (i = 0; i < 25; i++) {
c76949a6
MC		 9917 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9918 HOSTCC_MODE_NOW);
9919
9920 udelay(10);
9921
9922 tx_idx = tp->hw_status->idx[0].tx_consumer;
9923 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9924 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9925 (rx_idx == (rx_start_idx + num_pkts)))
9926 break;
9927 }
9928
9929 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9930 dev_kfree_skb(skb);
9931
9f40dead 9932 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9933 goto out;
9934
9935 if (rx_idx != rx_start_idx + num_pkts)
9936 goto out;
9937
9938 desc = &tp->rx_rcb[rx_start_idx];
9939 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9940 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9941 if (opaque_key != RXD_OPAQUE_RING_STD)
9942 goto out;
9943
9944 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9945 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9946 goto out;
9947
9948 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9949 if (rx_len != tx_len)
9950 goto out;
9951
21f581a5 9952 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 9953
21f581a5 9954 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 9955 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9956
9957 for (i = 14; i < tx_len; i++) {
9958 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9959 goto out;
9960 }
9961 err = 0;
6aa20a22 9962
c76949a6
MC		 9963 /* tg3_free_rings will unmap and free the rx_skb */
9964out:
9965 return err;
9966}
9967
9f40dead
MC		 9968#define TG3_MAC_LOOPBACK_FAILED 1
9969#define TG3_PHY_LOOPBACK_FAILED 2
9970#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9971 TG3_PHY_LOOPBACK_FAILED)
9972
9973static int tg3_test_loopback(struct tg3 *tp)
9974{
9975 int err = 0;
9936bcf6 9976 u32 cpmuctrl = 0;
9f40dead
MC		 9977
9978 if (!netif_running(tp->dev))
9979 return TG3_LOOPBACK_FAILED;
9980
b9ec6c1b
MC		 9981 err = tg3_reset_hw(tp, 1);
9982 if (err)
9983 return TG3_LOOPBACK_FAILED;
9f40dead 9984
6833c043
MC		 9985 /* Turn off gphy autopowerdown. */
9986 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9987 tg3_phy_toggle_apd(tp, false);
9988
321d32a0 9989 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9990 int i;
9991 u32 status;
9992
9993 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9994
9995 /* Wait for up to 40 microseconds to acquire lock. */
9996 for (i = 0; i < 4; i++) {
9997 status = tr32(TG3_CPMU_MUTEX_GNT);
9998 if (status == CPMU_MUTEX_GNT_DRIVER)
9999 break;
10000 udelay(10);
10001 }
10002
10003 if (status != CPMU_MUTEX_GNT_DRIVER)
10004 return TG3_LOOPBACK_FAILED;
10005
b2a5c19c 10006 /* Turn off link-based power management. */
e875093c 10007 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10008 tw32(TG3_CPMU_CTRL,
10009 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10010 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10011 }
10012
9f40dead
MC		 10013 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10014 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10015
321d32a0 10016 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10017 tw32(TG3_CPMU_CTRL, cpmuctrl);
10018
10019 /* Release the mutex */
10020 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10021 }
10022
dd477003
MC		 10023 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10024 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10025 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10026 err |= TG3_PHY_LOOPBACK_FAILED;
10027 }
10028
6833c043
MC		 10029 /* Re-enable gphy autopowerdown. */
10030 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10031 tg3_phy_toggle_apd(tp, true);
10032
9f40dead
MC		 10033 return err;
10034}
10035
4cafd3f5
MC		 10036static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10037 u64 *data)
10038{
566f86ad
MC		 10039 struct tg3 *tp = netdev_priv(dev);
10040
bc1c7567
MC		 10041 if (tp->link_config.phy_is_low_power)
10042 tg3_set_power_state(tp, PCI_D0);
10043
566f86ad
MC		 10044 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10045
10046 if (tg3_test_nvram(tp) != 0) {
10047 etest->flags |= ETH_TEST_FL_FAILED;
10048 data[0] = 1;
10049 }
ca43007a
MC		 10050 if (tg3_test_link(tp) != 0) {
10051 etest->flags |= ETH_TEST_FL_FAILED;
10052 data[1] = 1;
10053 }
a71116d1 10054 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10055 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10056
10057 if (netif_running(dev)) {
b02fd9e3 10058 tg3_phy_stop(tp);
a71116d1 10059 tg3_netif_stop(tp);
bbe832c0
MC		 10060 irq_sync = 1;
10061 }
a71116d1 10062
bbe832c0 10063 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10064
10065 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10066 err = tg3_nvram_lock(tp);
a71116d1
MC		 10067 tg3_halt_cpu(tp, RX_CPU_BASE);
10068 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10069 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10070 if (!err)
10071 tg3_nvram_unlock(tp);
a71116d1 10072
d9ab5ad1
MC		 10073 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10074 tg3_phy_reset(tp);
10075
a71116d1
MC		 10076 if (tg3_test_registers(tp) != 0) {
10077 etest->flags |= ETH_TEST_FL_FAILED;
10078 data[2] = 1;
10079 }
7942e1db
MC		 10080 if (tg3_test_memory(tp) != 0) {
10081 etest->flags |= ETH_TEST_FL_FAILED;
10082 data[3] = 1;
10083 }
9f40dead 10084 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10085 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10086
f47c11ee
DM		 10087 tg3_full_unlock(tp);
10088
d4bc3927
MC		 10089 if (tg3_test_interrupt(tp) != 0) {
10090 etest->flags |= ETH_TEST_FL_FAILED;
10091 data[5] = 1;
10092 }
f47c11ee
DM		 10093
10094 tg3_full_lock(tp, 0);
d4bc3927 10095
a71116d1
MC		 10096 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10097 if (netif_running(dev)) {
10098 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10099 err2 = tg3_restart_hw(tp, 1);
10100 if (!err2)
b9ec6c1b 10101 tg3_netif_start(tp);
a71116d1 10102 }
f47c11ee
DM		 10103
10104 tg3_full_unlock(tp);
b02fd9e3
MC		 10105
10106 if (irq_sync && !err2)
10107 tg3_phy_start(tp);
a71116d1 10108 }
bc1c7567
MC		 10109 if (tp->link_config.phy_is_low_power)
10110 tg3_set_power_state(tp, PCI_D3hot);
10111
4cafd3f5
MC		 10112}
10113
1da177e4
LT		 10114static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10115{
10116 struct mii_ioctl_data *data = if_mii(ifr);
10117 struct tg3 *tp = netdev_priv(dev);
10118 int err;
10119
b02fd9e3
MC		 10120 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10121 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10122 return -EAGAIN;
298cf9be 10123 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10124 }
10125
1da177e4
LT		 10126 switch(cmd) {
10127 case SIOCGMIIPHY:
10128 data->phy_id = PHY_ADDR;
10129
10130 /* fallthru */
10131 case SIOCGMIIREG: {
10132 u32 mii_regval;
10133
10134 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10135 break; /* We have no PHY */
10136
bc1c7567
MC		 10137 if (tp->link_config.phy_is_low_power)
10138 return -EAGAIN;
10139
f47c11ee 10140 spin_lock_bh(&tp->lock);
1da177e4 10141 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10142 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10143
10144 data->val_out = mii_regval;
10145
10146 return err;
10147 }
10148
10149 case SIOCSMIIREG:
10150 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10151 break; /* We have no PHY */
10152
10153 if (!capable(CAP_NET_ADMIN))
10154 return -EPERM;
10155
bc1c7567
MC		 10156 if (tp->link_config.phy_is_low_power)
10157 return -EAGAIN;
10158
f47c11ee 10159 spin_lock_bh(&tp->lock);
1da177e4 10160 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10161 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10162
10163 return err;
10164
10165 default:
10166 /* do nothing */
10167 break;
10168 }
10169 return -EOPNOTSUPP;
10170}
10171
10172#if TG3_VLAN_TAG_USED
10173static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10174{
10175 struct tg3 *tp = netdev_priv(dev);
10176
844b3eed
MC		 10177 if (!netif_running(dev)) {
10178 tp->vlgrp = grp;
10179 return;
10180 }
10181
10182 tg3_netif_stop(tp);
29315e87 10183
f47c11ee 10184 tg3_full_lock(tp, 0);
1da177e4
LT		 10185
10186 tp->vlgrp = grp;
10187
10188 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10189 __tg3_set_rx_mode(dev);
10190
844b3eed 10191 tg3_netif_start(tp);
46966545
MC		 10192
10193 tg3_full_unlock(tp);
1da177e4 10194}
1da177e4
LT		 10195#endif
10196
15f9850d
DM		 10197static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10198{
10199 struct tg3 *tp = netdev_priv(dev);
10200
10201 memcpy(ec, &tp->coal, sizeof(*ec));
10202 return 0;
10203}
10204
d244c892
MC		 10205static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10206{
10207 struct tg3 *tp = netdev_priv(dev);
10208 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10209 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10210
10211 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10212 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10213 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10214 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10215 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10216 }
10217
10218 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10219 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10220 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10221 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10222 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10223 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10224 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10225 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10226 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10227 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10228 return -EINVAL;
10229
10230 /* No rx interrupts will be generated if both are zero */
10231 if ((ec->rx_coalesce_usecs == 0) &&
10232 (ec->rx_max_coalesced_frames == 0))
10233 return -EINVAL;
10234
10235 /* No tx interrupts will be generated if both are zero */
10236 if ((ec->tx_coalesce_usecs == 0) &&
10237 (ec->tx_max_coalesced_frames == 0))
10238 return -EINVAL;
10239
10240 /* Only copy relevant parameters, ignore all others. */
10241 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10242 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10243 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10244 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10245 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10246 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10247 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10248 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10249 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10250
10251 if (netif_running(dev)) {
10252 tg3_full_lock(tp, 0);
10253 __tg3_set_coalesce(tp, &tp->coal);
10254 tg3_full_unlock(tp);
10255 }
10256 return 0;
10257}
10258
7282d491 10259static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10260 .get_settings = tg3_get_settings,
10261 .set_settings = tg3_set_settings,
10262 .get_drvinfo = tg3_get_drvinfo,
10263 .get_regs_len = tg3_get_regs_len,
10264 .get_regs = tg3_get_regs,
10265 .get_wol = tg3_get_wol,
10266 .set_wol = tg3_set_wol,
10267 .get_msglevel = tg3_get_msglevel,
10268 .set_msglevel = tg3_set_msglevel,
10269 .nway_reset = tg3_nway_reset,
10270 .get_link = ethtool_op_get_link,
10271 .get_eeprom_len = tg3_get_eeprom_len,
10272 .get_eeprom = tg3_get_eeprom,
10273 .set_eeprom = tg3_set_eeprom,
10274 .get_ringparam = tg3_get_ringparam,
10275 .set_ringparam = tg3_set_ringparam,
10276 .get_pauseparam = tg3_get_pauseparam,
10277 .set_pauseparam = tg3_set_pauseparam,
10278 .get_rx_csum = tg3_get_rx_csum,
10279 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10280 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10281 .set_sg = ethtool_op_set_sg,
1da177e4 10282 .set_tso = tg3_set_tso,
4cafd3f5 10283 .self_test = tg3_self_test,
1da177e4 10284 .get_strings = tg3_get_strings,
4009a93d 10285 .phys_id = tg3_phys_id,
1da177e4 10286 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10287 .get_coalesce = tg3_get_coalesce,
d244c892 10288 .set_coalesce = tg3_set_coalesce,
b9f2c044 10289 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10290};
10291
10292static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10293{
1b27777a 10294 u32 cursize, val, magic;
1da177e4
LT		 10295
10296 tp->nvram_size = EEPROM_CHIP_SIZE;
10297
e4f34110 10298 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10299 return;
10300
b16250e3
MC		 10301 if ((magic != TG3_EEPROM_MAGIC) &&
10302 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10303 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10304 return;
10305
10306 /*
10307 * Size the chip by reading offsets at increasing powers of two.
10308 * When we encounter our validation signature, we know the addressing
10309 * has wrapped around, and thus have our chip size.
10310 */
1b27777a 10311 cursize = 0x10;
1da177e4
LT		 10312
10313 while (cursize < tp->nvram_size) {
e4f34110 10314 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10315 return;
10316
1820180b 10317 if (val == magic)
1da177e4
LT		 10318 break;
10319
10320 cursize <<= 1;
10321 }
10322
10323 tp->nvram_size = cursize;
10324}
6aa20a22 10325
1da177e4
LT		 10326static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10327{
10328 u32 val;
10329
df259d8c
MC		 10330 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10331 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10332 return;
10333
10334 /* Selfboot format */
1820180b 10335 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10336 tg3_get_eeprom_size(tp);
10337 return;
10338 }
10339
6d348f2c 10340 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10341 if (val != 0) {
6d348f2c
MC		 10342 /* This is confusing. We want to operate on the
10343 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10344 * call will read from NVRAM and byteswap the data
10345 * according to the byteswapping settings for all
10346 * other register accesses. This ensures the data we
10347 * want will always reside in the lower 16-bits.
10348 * However, the data in NVRAM is in LE format, which
10349 * means the data from the NVRAM read will always be
10350 * opposite the endianness of the CPU. The 16-bit
10351 * byteswap then brings the data to CPU endianness.
10352 */
10353 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10354 return;
10355 }
10356 }
fd1122a2 10357 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10358}
10359
10360static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10361{
10362 u32 nvcfg1;
10363
10364 nvcfg1 = tr32(NVRAM_CFG1);
10365 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10366 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10367 } else {
1da177e4
LT		 10368 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10369 tw32(NVRAM_CFG1, nvcfg1);
10370 }
10371
4c987487 10372 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10373 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10374 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10375 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10376 tp->nvram_jedecnum = JEDEC_ATMEL;
10377 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10378 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10379 break;
10380 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10381 tp->nvram_jedecnum = JEDEC_ATMEL;
10382 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10383 break;
10384 case FLASH_VENDOR_ATMEL_EEPROM:
10385 tp->nvram_jedecnum = JEDEC_ATMEL;
10386 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10387 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10388 break;
10389 case FLASH_VENDOR_ST:
10390 tp->nvram_jedecnum = JEDEC_ST;
10391 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10392 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10393 break;
10394 case FLASH_VENDOR_SAIFUN:
10395 tp->nvram_jedecnum = JEDEC_SAIFUN;
10396 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10397 break;
10398 case FLASH_VENDOR_SST_SMALL:
10399 case FLASH_VENDOR_SST_LARGE:
10400 tp->nvram_jedecnum = JEDEC_SST;
10401 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10402 break;
1da177e4 10403 }
8590a603 10404 } else {
1da177e4
LT		 10405 tp->nvram_jedecnum = JEDEC_ATMEL;
10406 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10407 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10408 }
10409}
10410
361b4ac2
MC		 10411static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10412{
10413 u32 nvcfg1;
10414
10415 nvcfg1 = tr32(NVRAM_CFG1);
10416
e6af301b
MC		 10417 /* NVRAM protection for TPM */
10418 if (nvcfg1 & (1 << 27))
10419 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10420
361b4ac2 10421 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10422 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10423 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10424 tp->nvram_jedecnum = JEDEC_ATMEL;
10425 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10426 break;
10427 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10428 tp->nvram_jedecnum = JEDEC_ATMEL;
10429 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10430 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10431 break;
10432 case FLASH_5752VENDOR_ST_M45PE10:
10433 case FLASH_5752VENDOR_ST_M45PE20:
10434 case FLASH_5752VENDOR_ST_M45PE40:
10435 tp->nvram_jedecnum = JEDEC_ST;
10436 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10437 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10438 break;
361b4ac2
MC		 10439 }
10440
10441 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10442 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8590a603
MC		 10443 case FLASH_5752PAGE_SIZE_256:
10444 tp->nvram_pagesize = 256;
10445 break;
10446 case FLASH_5752PAGE_SIZE_512:
10447 tp->nvram_pagesize = 512;
10448 break;
10449 case FLASH_5752PAGE_SIZE_1K:
10450 tp->nvram_pagesize = 1024;
10451 break;
10452 case FLASH_5752PAGE_SIZE_2K:
10453 tp->nvram_pagesize = 2048;
10454 break;
10455 case FLASH_5752PAGE_SIZE_4K:
10456 tp->nvram_pagesize = 4096;
10457 break;
10458 case FLASH_5752PAGE_SIZE_264:
10459 tp->nvram_pagesize = 264;
10460 break;
361b4ac2 10461 }
8590a603 10462 } else {
361b4ac2
MC		 10463 /* For eeprom, set pagesize to maximum eeprom size */
10464 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10465
10466 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10467 tw32(NVRAM_CFG1, nvcfg1);
10468 }
10469}
10470
d3c7b886
MC		 10471static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10472{
989a9d23 10473 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10474
10475 nvcfg1 = tr32(NVRAM_CFG1);
10476
10477 /* NVRAM protection for TPM */
989a9d23 10478 if (nvcfg1 & (1 << 27)) {
d3c7b886 10479 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10480 protect = 1;
10481 }
d3c7b886 10482
989a9d23
MC		 10483 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10484 switch (nvcfg1) {
8590a603
MC		 10485 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10486 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10487 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10488 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10489 tp->nvram_jedecnum = JEDEC_ATMEL;
10490 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10491 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10492 tp->nvram_pagesize = 264;
10493 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10494 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10495 tp->nvram_size = (protect ? 0x3e200 :
10496 TG3_NVRAM_SIZE_512KB);
10497 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10498 tp->nvram_size = (protect ? 0x1f200 :
10499 TG3_NVRAM_SIZE_256KB);
10500 else
10501 tp->nvram_size = (protect ? 0x1f200 :
10502 TG3_NVRAM_SIZE_128KB);
10503 break;
10504 case FLASH_5752VENDOR_ST_M45PE10:
10505 case FLASH_5752VENDOR_ST_M45PE20:
10506 case FLASH_5752VENDOR_ST_M45PE40:
10507 tp->nvram_jedecnum = JEDEC_ST;
10508 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10509 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10510 tp->nvram_pagesize = 256;
10511 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10512 tp->nvram_size = (protect ?
10513 TG3_NVRAM_SIZE_64KB :
10514 TG3_NVRAM_SIZE_128KB);
10515 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10516 tp->nvram_size = (protect ?
10517 TG3_NVRAM_SIZE_64KB :
10518 TG3_NVRAM_SIZE_256KB);
10519 else
10520 tp->nvram_size = (protect ?
10521 TG3_NVRAM_SIZE_128KB :
10522 TG3_NVRAM_SIZE_512KB);
10523 break;
d3c7b886
MC		 10524 }
10525}
10526
1b27777a
MC		 10527static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10528{
10529 u32 nvcfg1;
10530
10531 nvcfg1 = tr32(NVRAM_CFG1);
10532
10533 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10534 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10535 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10536 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10537 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10538 tp->nvram_jedecnum = JEDEC_ATMEL;
10539 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10540 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 10541
8590a603
MC		 10542 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10543 tw32(NVRAM_CFG1, nvcfg1);
10544 break;
10545 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10546 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10547 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10548 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10549 tp->nvram_jedecnum = JEDEC_ATMEL;
10550 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10551 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10552 tp->nvram_pagesize = 264;
10553 break;
10554 case FLASH_5752VENDOR_ST_M45PE10:
10555 case FLASH_5752VENDOR_ST_M45PE20:
10556 case FLASH_5752VENDOR_ST_M45PE40:
10557 tp->nvram_jedecnum = JEDEC_ST;
10558 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10559 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10560 tp->nvram_pagesize = 256;
10561 break;
1b27777a
MC		 10562 }
10563}
10564
6b91fa02
MC		 10565static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10566{
10567 u32 nvcfg1, protect = 0;
10568
10569 nvcfg1 = tr32(NVRAM_CFG1);
10570
10571 /* NVRAM protection for TPM */
10572 if (nvcfg1 & (1 << 27)) {
10573 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10574 protect = 1;
10575 }
10576
10577 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10578 switch (nvcfg1) {
8590a603
MC		 10579 case FLASH_5761VENDOR_ATMEL_ADB021D:
10580 case FLASH_5761VENDOR_ATMEL_ADB041D:
10581 case FLASH_5761VENDOR_ATMEL_ADB081D:
10582 case FLASH_5761VENDOR_ATMEL_ADB161D:
10583 case FLASH_5761VENDOR_ATMEL_MDB021D:
10584 case FLASH_5761VENDOR_ATMEL_MDB041D:
10585 case FLASH_5761VENDOR_ATMEL_MDB081D:
10586 case FLASH_5761VENDOR_ATMEL_MDB161D:
10587 tp->nvram_jedecnum = JEDEC_ATMEL;
10588 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10589 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10590 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10591 tp->nvram_pagesize = 256;
10592 break;
10593 case FLASH_5761VENDOR_ST_A_M45PE20:
10594 case FLASH_5761VENDOR_ST_A_M45PE40:
10595 case FLASH_5761VENDOR_ST_A_M45PE80:
10596 case FLASH_5761VENDOR_ST_A_M45PE16:
10597 case FLASH_5761VENDOR_ST_M_M45PE20:
10598 case FLASH_5761VENDOR_ST_M_M45PE40:
10599 case FLASH_5761VENDOR_ST_M_M45PE80:
10600 case FLASH_5761VENDOR_ST_M_M45PE16:
10601 tp->nvram_jedecnum = JEDEC_ST;
10602 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10603 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10604 tp->nvram_pagesize = 256;
10605 break;
6b91fa02
MC		 10606 }
10607
10608 if (protect) {
10609 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10610 } else {
10611 switch (nvcfg1) {
8590a603
MC		 10612 case FLASH_5761VENDOR_ATMEL_ADB161D:
10613 case FLASH_5761VENDOR_ATMEL_MDB161D:
10614 case FLASH_5761VENDOR_ST_A_M45PE16:
10615 case FLASH_5761VENDOR_ST_M_M45PE16:
10616 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10617 break;
10618 case FLASH_5761VENDOR_ATMEL_ADB081D:
10619 case FLASH_5761VENDOR_ATMEL_MDB081D:
10620 case FLASH_5761VENDOR_ST_A_M45PE80:
10621 case FLASH_5761VENDOR_ST_M_M45PE80:
10622 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10623 break;
10624 case FLASH_5761VENDOR_ATMEL_ADB041D:
10625 case FLASH_5761VENDOR_ATMEL_MDB041D:
10626 case FLASH_5761VENDOR_ST_A_M45PE40:
10627 case FLASH_5761VENDOR_ST_M_M45PE40:
10628 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10629 break;
10630 case FLASH_5761VENDOR_ATMEL_ADB021D:
10631 case FLASH_5761VENDOR_ATMEL_MDB021D:
10632 case FLASH_5761VENDOR_ST_A_M45PE20:
10633 case FLASH_5761VENDOR_ST_M_M45PE20:
10634 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10635 break;
6b91fa02
MC		 10636 }
10637 }
10638}
10639
b5d3772c
MC		 10640static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10641{
10642 tp->nvram_jedecnum = JEDEC_ATMEL;
10643 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10644 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10645}
10646
321d32a0
MC		 10647static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10648{
10649 u32 nvcfg1;
10650
10651 nvcfg1 = tr32(NVRAM_CFG1);
10652
10653 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10654 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10655 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10656 tp->nvram_jedecnum = JEDEC_ATMEL;
10657 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10658 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10659
10660 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10661 tw32(NVRAM_CFG1, nvcfg1);
10662 return;
10663 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10664 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10665 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10666 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10667 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10668 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10669 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10670 tp->nvram_jedecnum = JEDEC_ATMEL;
10671 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10672 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10673
10674 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10675 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10676 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10677 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10678 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10679 break;
10680 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10681 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10682 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10683 break;
10684 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10685 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10686 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10687 break;
10688 }
10689 break;
10690 case FLASH_5752VENDOR_ST_M45PE10:
10691 case FLASH_5752VENDOR_ST_M45PE20:
10692 case FLASH_5752VENDOR_ST_M45PE40:
10693 tp->nvram_jedecnum = JEDEC_ST;
10694 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10695 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10696
10697 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10698 case FLASH_5752VENDOR_ST_M45PE10:
10699 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10700 break;
10701 case FLASH_5752VENDOR_ST_M45PE20:
10702 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10703 break;
10704 case FLASH_5752VENDOR_ST_M45PE40:
10705 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10706 break;
10707 }
10708 break;
10709 default:
df259d8c 10710 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 10711 return;
10712 }
10713
10714 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10715 case FLASH_5752PAGE_SIZE_256:
10716 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10717 tp->nvram_pagesize = 256;
10718 break;
10719 case FLASH_5752PAGE_SIZE_512:
10720 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10721 tp->nvram_pagesize = 512;
10722 break;
10723 case FLASH_5752PAGE_SIZE_1K:
10724 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10725 tp->nvram_pagesize = 1024;
10726 break;
10727 case FLASH_5752PAGE_SIZE_2K:
10728 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10729 tp->nvram_pagesize = 2048;
10730 break;
10731 case FLASH_5752PAGE_SIZE_4K:
10732 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10733 tp->nvram_pagesize = 4096;
10734 break;
10735 case FLASH_5752PAGE_SIZE_264:
10736 tp->nvram_pagesize = 264;
10737 break;
10738 case FLASH_5752PAGE_SIZE_528:
10739 tp->nvram_pagesize = 528;
10740 break;
10741 }
10742}
10743
1da177e4
LT		 10744/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10745static void __devinit tg3_nvram_init(struct tg3 *tp)
10746{
1da177e4
LT		 10747 tw32_f(GRC_EEPROM_ADDR,
10748 (EEPROM_ADDR_FSM_RESET |
10749 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10750 EEPROM_ADDR_CLKPERD_SHIFT)));
10751
9d57f01c 10752 msleep(1);
1da177e4
LT		 10753
10754 /* Enable seeprom accesses. */
10755 tw32_f(GRC_LOCAL_CTRL,
10756 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10757 udelay(100);
10758
10759 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10760 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10761 tp->tg3_flags |= TG3_FLAG_NVRAM;
10762
ec41c7df
MC		 10763 if (tg3_nvram_lock(tp)) {
10764 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10765 "tg3_nvram_init failed.\n", tp->dev->name);
10766 return;
10767 }
e6af301b 10768 tg3_enable_nvram_access(tp);
1da177e4 10769
989a9d23
MC		 10770 tp->nvram_size = 0;
10771
361b4ac2
MC		 10772 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10773 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10774 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10775 tg3_get_5755_nvram_info(tp);
d30cdd28 10776 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10778 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10779 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10780 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10781 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10782 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10783 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10784 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10785 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10786 else
10787 tg3_get_nvram_info(tp);
10788
989a9d23
MC		 10789 if (tp->nvram_size == 0)
10790 tg3_get_nvram_size(tp);
1da177e4 10791
e6af301b 10792 tg3_disable_nvram_access(tp);
381291b7 10793 tg3_nvram_unlock(tp);
1da177e4
LT		 10794
10795 } else {
10796 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10797
10798 tg3_get_eeprom_size(tp);
10799 }
10800}
10801
1da177e4
LT		 10802static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10803 u32 offset, u32 len, u8 *buf)
10804{
10805 int i, j, rc = 0;
10806 u32 val;
10807
10808 for (i = 0; i < len; i += 4) {
b9fc7dc5 10809 u32 addr;
a9dc529d 10810 __be32 data;
1da177e4
LT		 10811
10812 addr = offset + i;
10813
10814 memcpy(&data, buf + i, 4);
10815
62cedd11
MC		 10816 /*
10817 * The SEEPROM interface expects the data to always be opposite
10818 * the native endian format. We accomplish this by reversing
10819 * all the operations that would have been performed on the
10820 * data from a call to tg3_nvram_read_be32().
10821 */
10822 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10823
10824 val = tr32(GRC_EEPROM_ADDR);
10825 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10826
10827 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10828 EEPROM_ADDR_READ);
10829 tw32(GRC_EEPROM_ADDR, val |
10830 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10831 (addr & EEPROM_ADDR_ADDR_MASK) |
10832 EEPROM_ADDR_START |
10833 EEPROM_ADDR_WRITE);
6aa20a22 10834
9d57f01c 10835 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10836 val = tr32(GRC_EEPROM_ADDR);
10837
10838 if (val & EEPROM_ADDR_COMPLETE)
10839 break;
9d57f01c 10840 msleep(1);
1da177e4
LT		 10841 }
10842 if (!(val & EEPROM_ADDR_COMPLETE)) {
10843 rc = -EBUSY;
10844 break;
10845 }
10846 }
10847
10848 return rc;
10849}
10850
10851/* offset and length are dword aligned */
10852static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10853 u8 *buf)
10854{
10855 int ret = 0;
10856 u32 pagesize = tp->nvram_pagesize;
10857 u32 pagemask = pagesize - 1;
10858 u32 nvram_cmd;
10859 u8 *tmp;
10860
10861 tmp = kmalloc(pagesize, GFP_KERNEL);
10862 if (tmp == NULL)
10863 return -ENOMEM;
10864
10865 while (len) {
10866 int j;
e6af301b 10867 u32 phy_addr, page_off, size;
1da177e4
LT		 10868
10869 phy_addr = offset & ~pagemask;
6aa20a22 10870
1da177e4 10871 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10872 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10873 (__be32 *) (tmp + j));
10874 if (ret)
1da177e4
LT		 10875 break;
10876 }
10877 if (ret)
10878 break;
10879
10880 page_off = offset & pagemask;
10881 size = pagesize;
10882 if (len < size)
10883 size = len;
10884
10885 len -= size;
10886
10887 memcpy(tmp + page_off, buf, size);
10888
10889 offset = offset + (pagesize - page_off);
10890
e6af301b 10891 tg3_enable_nvram_access(tp);
1da177e4
LT		 10892
10893 /*
10894 * Before we can erase the flash page, we need
10895 * to issue a special "write enable" command.
10896 */
10897 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10898
10899 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10900 break;
10901
10902 /* Erase the target page */
10903 tw32(NVRAM_ADDR, phy_addr);
10904
10905 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10906 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10907
10908 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10909 break;
10910
10911 /* Issue another write enable to start the write. */
10912 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10913
10914 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10915 break;
10916
10917 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10918 __be32 data;
1da177e4 10919
b9fc7dc5 10920 data = *((__be32 *) (tmp + j));
a9dc529d 10921
b9fc7dc5 10922 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10923
10924 tw32(NVRAM_ADDR, phy_addr + j);
10925
10926 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10927 NVRAM_CMD_WR;
10928
10929 if (j == 0)
10930 nvram_cmd |= NVRAM_CMD_FIRST;
10931 else if (j == (pagesize - 4))
10932 nvram_cmd |= NVRAM_CMD_LAST;
10933
10934 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10935 break;
10936 }
10937 if (ret)
10938 break;
10939 }
10940
10941 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10942 tg3_nvram_exec_cmd(tp, nvram_cmd);
10943
10944 kfree(tmp);
10945
10946 return ret;
10947}
10948
10949/* offset and length are dword aligned */
10950static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10951 u8 *buf)
10952{
10953 int i, ret = 0;
10954
10955 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10956 u32 page_off, phy_addr, nvram_cmd;
10957 __be32 data;
1da177e4
LT		 10958
10959 memcpy(&data, buf + i, 4);
b9fc7dc5 10960 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10961
10962 page_off = offset % tp->nvram_pagesize;
10963
1820180b 10964 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10965
10966 tw32(NVRAM_ADDR, phy_addr);
10967
10968 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10969
10970 if ((page_off == 0) || (i == 0))
10971 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10972 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10973 nvram_cmd |= NVRAM_CMD_LAST;
10974
10975 if (i == (len - 4))
10976 nvram_cmd |= NVRAM_CMD_LAST;
10977
321d32a0
MC		 10978 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10979 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10980 (tp->nvram_jedecnum == JEDEC_ST) &&
10981 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10982
10983 if ((ret = tg3_nvram_exec_cmd(tp,
10984 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10985 NVRAM_CMD_DONE)))
10986
10987 break;
10988 }
10989 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10990 /* We always do complete word writes to eeprom. */
10991 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10992 }
10993
10994 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10995 break;
10996 }
10997 return ret;
10998}
10999
11000/* offset and length are dword aligned */
11001static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11002{
11003 int ret;
11004
1da177e4 11005 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11006 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11007 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11008 udelay(40);
11009 }
11010
11011 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11012 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11013 }
11014 else {
11015 u32 grc_mode;
11016
ec41c7df
MC		 11017 ret = tg3_nvram_lock(tp);
11018 if (ret)
11019 return ret;
1da177e4 11020
e6af301b
MC		 11021 tg3_enable_nvram_access(tp);
11022 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11023 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11024 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11025
11026 grc_mode = tr32(GRC_MODE);
11027 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11028
11029 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11030 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11031
11032 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11033 buf);
11034 }
11035 else {
11036 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11037 buf);
11038 }
11039
11040 grc_mode = tr32(GRC_MODE);
11041 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11042
e6af301b 11043 tg3_disable_nvram_access(tp);
1da177e4
LT		 11044 tg3_nvram_unlock(tp);
11045 }
11046
11047 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11048 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11049 udelay(40);
11050 }
11051
11052 return ret;
11053}
11054
11055struct subsys_tbl_ent {
11056 u16 subsys_vendor, subsys_devid;
11057 u32 phy_id;
11058};
11059
11060static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11061 /* Broadcom boards. */
11062 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11063 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11064 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11065 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11066 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11067 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11068 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11069 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11070 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11071 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11072 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11073
11074 /* 3com boards. */
11075 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11076 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11077 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11078 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11079 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11080
11081 /* DELL boards. */
11082 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11083 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11084 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11085 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11086
11087 /* Compaq boards. */
11088 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11089 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11090 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11091 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11092 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11093
11094 /* IBM boards. */
11095 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11096};
11097
11098static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11099{
11100 int i;
11101
11102 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11103 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11104 tp->pdev->subsystem_vendor) &&
11105 (subsys_id_to_phy_id[i].subsys_devid ==
11106 tp->pdev->subsystem_device))
11107 return &subsys_id_to_phy_id[i];
11108 }
11109 return NULL;
11110}
11111
7d0c41ef 11112static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11113{
1da177e4 11114 u32 val;
caf636c7
MC		 11115 u16 pmcsr;
11116
11117 /* On some early chips the SRAM cannot be accessed in D3hot state,
11118 * so need make sure we're in D0.
11119 */
11120 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11121 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11122 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11123 msleep(1);
7d0c41ef
MC		 11124
11125 /* Make sure register accesses (indirect or otherwise)
11126 * will function correctly.
11127 */
11128 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11129 tp->misc_host_ctrl);
1da177e4 11130
f49639e6
DM		 11131 /* The memory arbiter has to be enabled in order for SRAM accesses
11132 * to succeed. Normally on powerup the tg3 chip firmware will make
11133 * sure it is enabled, but other entities such as system netboot
11134 * code might disable it.
11135 */
11136 val = tr32(MEMARB_MODE);
11137 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11138
1da177e4 11139 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11140 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11141
a85feb8c
GZ		 11142 /* Assume an onboard device and WOL capable by default. */
11143 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11144
b5d3772c 11145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11146 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11147 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11148 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11149 }
0527ba35
MC		 11150 val = tr32(VCPU_CFGSHDW);
11151 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11152 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11153 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11154 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11155 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11156 goto done;
b5d3772c
MC		 11157 }
11158
1da177e4
LT		 11159 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11160 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11161 u32 nic_cfg, led_cfg;
a9daf367 11162 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11163 int eeprom_phy_serdes = 0;
1da177e4
LT		 11164
11165 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11166 tp->nic_sram_data_cfg = nic_cfg;
11167
11168 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11169 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11170 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11171 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11172 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11173 (ver > 0) && (ver < 0x100))
11174 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11175
a9daf367
MC		 11176 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11177 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11178
1da177e4
LT		 11179 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11180 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11181 eeprom_phy_serdes = 1;
11182
11183 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11184 if (nic_phy_id != 0) {
11185 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11186 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11187
11188 eeprom_phy_id = (id1 >> 16) << 10;
11189 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11190 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11191 } else
11192 eeprom_phy_id = 0;
11193
7d0c41ef 11194 tp->phy_id = eeprom_phy_id;
747e8f8b 11195 if (eeprom_phy_serdes) {
a4e2b347 11196 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11197 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11198 else
11199 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11200 }
7d0c41ef 11201
cbf46853 11202 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11203 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11204 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11205 else
1da177e4
LT		 11206 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11207
11208 switch (led_cfg) {
11209 default:
11210 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11211 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11212 break;
11213
11214 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11215 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11216 break;
11217
11218 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11219 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11220
11221 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11222 * read on some older 5700/5701 bootcode.
11223 */
11224 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11225 ASIC_REV_5700 ||
11226 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11227 ASIC_REV_5701)
11228 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11229
1da177e4
LT		 11230 break;
11231
11232 case SHASTA_EXT_LED_SHARED:
11233 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11234 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11235 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11236 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11237 LED_CTRL_MODE_PHY_2);
11238 break;
11239
11240 case SHASTA_EXT_LED_MAC:
11241 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11242 break;
11243
11244 case SHASTA_EXT_LED_COMBO:
11245 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11246 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11247 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11248 LED_CTRL_MODE_PHY_2);
11249 break;
11250
855e1111 11251 }
1da177e4
LT		 11252
11253 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11254 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11255 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11256 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11257
b2a5c19c
MC		 11258 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11259 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11260
9d26e213 11261 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11262 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11263 if ((tp->pdev->subsystem_vendor ==
11264 PCI_VENDOR_ID_ARIMA) &&
11265 (tp->pdev->subsystem_device == 0x205a ||
11266 tp->pdev->subsystem_device == 0x2063))
11267 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11268 } else {
f49639e6 11269 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11270 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11271 }
1da177e4
LT		 11272
11273 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11274 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11275 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11276 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11277 }
b2b98d4a
MC		 11278
11279 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11280 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11281 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11282
a85feb8c
GZ		 11283 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11284 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11285 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11286
12dac075 11287 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11288 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11289 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11290
1da177e4
LT		 11291 if (cfg2 & (1 << 17))
11292 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11293
11294 /* serdes signal pre-emphasis in register 0x590 set by */
11295 /* bootcode if bit 18 is set */
11296 if (cfg2 & (1 << 18))
11297 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11298
321d32a0
MC		 11299 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11300 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11301 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11302 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11303
8ed5d97e
MC		 11304 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11305 u32 cfg3;
11306
11307 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11308 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11309 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11310 }
a9daf367
MC		 11311
11312 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11313 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11314 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11315 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11316 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11317 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11318 }
05ac4cb7
MC		 11319done:
11320 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11321 device_set_wakeup_enable(&tp->pdev->dev,
11322 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11323}
11324
b2a5c19c
MC		 11325static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11326{
11327 int i;
11328 u32 val;
11329
11330 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11331 tw32(OTP_CTRL, cmd);
11332
11333 /* Wait for up to 1 ms for command to execute. */
11334 for (i = 0; i < 100; i++) {
11335 val = tr32(OTP_STATUS);
11336 if (val & OTP_STATUS_CMD_DONE)
11337 break;
11338 udelay(10);
11339 }
11340
11341 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11342}
11343
11344/* Read the gphy configuration from the OTP region of the chip. The gphy
11345 * configuration is a 32-bit value that straddles the alignment boundary.
11346 * We do two 32-bit reads and then shift and merge the results.
11347 */
11348static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11349{
11350 u32 bhalf_otp, thalf_otp;
11351
11352 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11353
11354 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11355 return 0;
11356
11357 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11358
11359 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11360 return 0;
11361
11362 thalf_otp = tr32(OTP_READ_DATA);
11363
11364 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11365
11366 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11367 return 0;
11368
11369 bhalf_otp = tr32(OTP_READ_DATA);
11370
11371 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11372}
11373
7d0c41ef
MC		 11374static int __devinit tg3_phy_probe(struct tg3 *tp)
11375{
11376 u32 hw_phy_id_1, hw_phy_id_2;
11377 u32 hw_phy_id, hw_phy_id_masked;
11378 int err;
1da177e4 11379
b02fd9e3
MC		 11380 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11381 return tg3_phy_init(tp);
11382
1da177e4 11383 /* Reading the PHY ID register can conflict with ASF
877d0310 11384 * firmware access to the PHY hardware.
1da177e4
LT		 11385 */
11386 err = 0;
0d3031d9
MC		 11387 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11388 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11389 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11390 } else {
11391 /* Now read the physical PHY_ID from the chip and verify
11392 * that it is sane. If it doesn't look good, we fall back
11393 * to either the hard-coded table based PHY_ID and failing
11394 * that the value found in the eeprom area.
11395 */
11396 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11397 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11398
11399 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11400 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11401 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11402
11403 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11404 }
11405
11406 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11407 tp->phy_id = hw_phy_id;
11408 if (hw_phy_id_masked == PHY_ID_BCM8002)
11409 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11410 else
11411 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11412 } else {
7d0c41ef
MC		 11413 if (tp->phy_id != PHY_ID_INVALID) {
11414 /* Do nothing, phy ID already set up in
11415 * tg3_get_eeprom_hw_cfg().
11416 */
1da177e4
LT		 11417 } else {
11418 struct subsys_tbl_ent *p;
11419
11420 /* No eeprom signature? Try the hardcoded
11421 * subsys device table.
11422 */
11423 p = lookup_by_subsys(tp);
11424 if (!p)
11425 return -ENODEV;
11426
11427 tp->phy_id = p->phy_id;
11428 if (!tp->phy_id ||
11429 tp->phy_id == PHY_ID_BCM8002)
11430 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11431 }
11432 }
11433
747e8f8b 11434 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11435 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11436 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11437 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11438
11439 tg3_readphy(tp, MII_BMSR, &bmsr);
11440 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11441 (bmsr & BMSR_LSTATUS))
11442 goto skip_phy_reset;
6aa20a22 11443
1da177e4
LT		 11444 err = tg3_phy_reset(tp);
11445 if (err)
11446 return err;
11447
11448 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11449 ADVERTISE_100HALF | ADVERTISE_100FULL |
11450 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11451 tg3_ctrl = 0;
11452 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11453 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11454 MII_TG3_CTRL_ADV_1000_FULL);
11455 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11456 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11457 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11458 MII_TG3_CTRL_ENABLE_AS_MASTER);
11459 }
11460
3600d918
MC		 11461 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11462 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11463 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11464 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11465 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11466
11467 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11468 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11469
11470 tg3_writephy(tp, MII_BMCR,
11471 BMCR_ANENABLE | BMCR_ANRESTART);
11472 }
11473 tg3_phy_set_wirespeed(tp);
11474
11475 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11476 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11477 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11478 }
11479
11480skip_phy_reset:
11481 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11482 err = tg3_init_5401phy_dsp(tp);
11483 if (err)
11484 return err;
11485 }
11486
11487 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11488 err = tg3_init_5401phy_dsp(tp);
11489 }
11490
747e8f8b 11491 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11492 tp->link_config.advertising =
11493 (ADVERTISED_1000baseT_Half |
11494 ADVERTISED_1000baseT_Full |
11495 ADVERTISED_Autoneg |
11496 ADVERTISED_FIBRE);
11497 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11498 tp->link_config.advertising &=
11499 ~(ADVERTISED_1000baseT_Half |
11500 ADVERTISED_1000baseT_Full);
11501
11502 return err;
11503}
11504
11505static void __devinit tg3_read_partno(struct tg3 *tp)
11506{
6d348f2c 11507 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11508 unsigned int i;
1b27777a 11509 u32 magic;
1da177e4 11510
df259d8c
MC		 11511 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11512 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11513 goto out_not_found;
1da177e4 11514
1820180b 11515 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11516 for (i = 0; i < 256; i += 4) {
11517 u32 tmp;
1da177e4 11518
6d348f2c
MC		 11519 /* The data is in little-endian format in NVRAM.
11520 * Use the big-endian read routines to preserve
11521 * the byte order as it exists in NVRAM.
11522 */
11523 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11524 goto out_not_found;
11525
6d348f2c 11526 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11527 }
11528 } else {
11529 int vpd_cap;
11530
11531 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11532 for (i = 0; i < 256; i += 4) {
11533 u32 tmp, j = 0;
b9fc7dc5 11534 __le32 v;
1b27777a
MC		 11535 u16 tmp16;
11536
11537 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11538 i);
11539 while (j++ < 100) {
11540 pci_read_config_word(tp->pdev, vpd_cap +
11541 PCI_VPD_ADDR, &tmp16);
11542 if (tmp16 & 0x8000)
11543 break;
11544 msleep(1);
11545 }
f49639e6
DM		 11546 if (!(tmp16 & 0x8000))
11547 goto out_not_found;
11548
1b27777a
MC		 11549 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11550 &tmp);
b9fc7dc5 11551 v = cpu_to_le32(tmp);
6d348f2c 11552 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11553 }
1da177e4
LT		 11554 }
11555
11556 /* Now parse and find the part number. */
af2c6a4a 11557 for (i = 0; i < 254; ) {
1da177e4 11558 unsigned char val = vpd_data[i];
af2c6a4a 11559 unsigned int block_end;
1da177e4
LT		 11560
11561 if (val == 0x82 || val == 0x91) {
11562 i = (i + 3 +
11563 (vpd_data[i + 1] +
11564 (vpd_data[i + 2] << 8)));
11565 continue;
11566 }
11567
11568 if (val != 0x90)
11569 goto out_not_found;
11570
11571 block_end = (i + 3 +
11572 (vpd_data[i + 1] +
11573 (vpd_data[i + 2] << 8)));
11574 i += 3;
af2c6a4a
MC		 11575
11576 if (block_end > 256)
11577 goto out_not_found;
11578
11579 while (i < (block_end - 2)) {
1da177e4
LT		 11580 if (vpd_data[i + 0] == 'P' &&
11581 vpd_data[i + 1] == 'N') {
11582 int partno_len = vpd_data[i + 2];
11583
af2c6a4a
MC		 11584 i += 3;
11585 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11586 goto out_not_found;
11587
11588 memcpy(tp->board_part_number,
af2c6a4a 11589 &vpd_data[i], partno_len);
1da177e4
LT		 11590
11591 /* Success. */
11592 return;
11593 }
af2c6a4a 11594 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11595 }
11596
11597 /* Part number not found. */
11598 goto out_not_found;
11599 }
11600
11601out_not_found:
b5d3772c
MC		 11602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11603 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 11604 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11605 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11606 strcpy(tp->board_part_number, "BCM57780");
11607 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11608 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11609 strcpy(tp->board_part_number, "BCM57760");
11610 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11611 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11612 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 11613 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11614 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11615 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 11616 else
11617 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11618}
11619
9c8a620e
MC		 11620static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11621{
11622 u32 val;
11623
e4f34110 11624 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11625 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11626 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11627 val != 0)
11628 return 0;
11629
11630 return 1;
11631}
11632
acd9c119
MC		 11633static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11634{
ff3a7cb2 11635 u32 val, offset, start, ver_offset;
acd9c119 11636 int i;
ff3a7cb2 11637 bool newver = false;
acd9c119
MC		 11638
11639 if (tg3_nvram_read(tp, 0xc, &offset) ||
11640 tg3_nvram_read(tp, 0x4, &start))
11641 return;
11642
11643 offset = tg3_nvram_logical_addr(tp, offset);
11644
ff3a7cb2 11645 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11646 return;
11647
ff3a7cb2
MC		 11648 if ((val & 0xfc000000) == 0x0c000000) {
11649 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11650 return;
11651
ff3a7cb2
MC		 11652 if (val == 0)
11653 newver = true;
11654 }
11655
11656 if (newver) {
11657 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11658 return;
11659
11660 offset = offset + ver_offset - start;
11661 for (i = 0; i < 16; i += 4) {
11662 __be32 v;
11663 if (tg3_nvram_read_be32(tp, offset + i, &v))
11664 return;
11665
11666 memcpy(tp->fw_ver + i, &v, sizeof(v));
11667 }
11668 } else {
11669 u32 major, minor;
11670
11671 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11672 return;
11673
11674 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11675 TG3_NVM_BCVER_MAJSFT;
11676 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11677 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11678 }
11679}
11680
a6f6cb1c
MC		 11681static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11682{
11683 u32 val, major, minor;
11684
11685 /* Use native endian representation */
11686 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11687 return;
11688
11689 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11690 TG3_NVM_HWSB_CFG1_MAJSFT;
11691 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11692 TG3_NVM_HWSB_CFG1_MINSFT;
11693
11694 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11695}
11696
dfe00d7d
MC		 11697static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11698{
11699 u32 offset, major, minor, build;
11700
11701 tp->fw_ver[0] = 's';
11702 tp->fw_ver[1] = 'b';
11703 tp->fw_ver[2] = '\0';
11704
11705 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11706 return;
11707
11708 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11709 case TG3_EEPROM_SB_REVISION_0:
11710 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11711 break;
11712 case TG3_EEPROM_SB_REVISION_2:
11713 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11714 break;
11715 case TG3_EEPROM_SB_REVISION_3:
11716 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11717 break;
11718 default:
11719 return;
11720 }
11721
e4f34110 11722 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11723 return;
11724
11725 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11726 TG3_EEPROM_SB_EDH_BLD_SHFT;
11727 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11728 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11729 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11730
11731 if (minor > 99 || build > 26)
11732 return;
11733
11734 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11735
11736 if (build > 0) {
11737 tp->fw_ver[8] = 'a' + build - 1;
11738 tp->fw_ver[9] = '\0';
11739 }
11740}
11741
acd9c119 11742static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11743{
11744 u32 val, offset, start;
acd9c119 11745 int i, vlen;
9c8a620e
MC		 11746
11747 for (offset = TG3_NVM_DIR_START;
11748 offset < TG3_NVM_DIR_END;
11749 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11750 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11751 return;
11752
9c8a620e
MC		 11753 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11754 break;
11755 }
11756
11757 if (offset == TG3_NVM_DIR_END)
11758 return;
11759
11760 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11761 start = 0x08000000;
e4f34110 11762 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11763 return;
11764
e4f34110 11765 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11766 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11767 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11768 return;
11769
11770 offset += val - start;
11771
acd9c119 11772 vlen = strlen(tp->fw_ver);
9c8a620e 11773
acd9c119
MC		 11774 tp->fw_ver[vlen++] = ',';
11775 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11776
11777 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11778 __be32 v;
11779 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11780 return;
11781
b9fc7dc5 11782 offset += sizeof(v);
c4e6575c 11783
acd9c119
MC		 11784 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11785 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11786 break;
c4e6575c 11787 }
9c8a620e 11788
acd9c119
MC		 11789 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11790 vlen += sizeof(v);
c4e6575c 11791 }
acd9c119
MC		 11792}
11793
7fd76445
MC		 11794static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11795{
11796 int vlen;
11797 u32 apedata;
11798
11799 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11800 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11801 return;
11802
11803 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11804 if (apedata != APE_SEG_SIG_MAGIC)
11805 return;
11806
11807 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11808 if (!(apedata & APE_FW_STATUS_READY))
11809 return;
11810
11811 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11812
11813 vlen = strlen(tp->fw_ver);
11814
11815 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11816 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11817 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11818 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11819 (apedata & APE_FW_VERSION_BLDMSK));
11820}
11821
acd9c119
MC		 11822static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11823{
11824 u32 val;
11825
df259d8c
MC		 11826 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11827 tp->fw_ver[0] = 's';
11828 tp->fw_ver[1] = 'b';
11829 tp->fw_ver[2] = '\0';
11830
11831 return;
11832 }
11833
acd9c119
MC		 11834 if (tg3_nvram_read(tp, 0, &val))
11835 return;
11836
11837 if (val == TG3_EEPROM_MAGIC)
11838 tg3_read_bc_ver(tp);
11839 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11840 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11841 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11842 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11843 else
11844 return;
11845
11846 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11847 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11848 return;
11849
11850 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11851
11852 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11853}
11854
7544b097
MC		 11855static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11856
1da177e4
LT		 11857static int __devinit tg3_get_invariants(struct tg3 *tp)
11858{
11859 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11860 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11861 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11862 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11863 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11864 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11865 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11866 { },
11867 };
11868 u32 misc_ctrl_reg;
1da177e4
LT		 11869 u32 pci_state_reg, grc_misc_cfg;
11870 u32 val;
11871 u16 pci_cmd;
5e7dfd0f 11872 int err;
1da177e4 11873
1da177e4
LT		 11874 /* Force memory write invalidate off. If we leave it on,
11875 * then on 5700_BX chips we have to enable a workaround.
11876 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11877 * to match the cacheline size. The Broadcom driver have this
11878 * workaround but turns MWI off all the times so never uses
11879 * it. This seems to suggest that the workaround is insufficient.
11880 */
11881 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11882 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11883 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11884
11885 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11886 * has the register indirect write enable bit set before
11887 * we try to access any of the MMIO registers. It is also
11888 * critical that the PCI-X hw workaround situation is decided
11889 * before that as well.
11890 */
11891 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11892 &misc_ctrl_reg);
11893
11894 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11895 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11897 u32 prod_id_asic_rev;
11898
11899 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11900 &prod_id_asic_rev);
321d32a0 11901 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11902 }
1da177e4 11903
ff645bec
MC		 11904 /* Wrong chip ID in 5752 A0. This code can be removed later
11905 * as A0 is not in production.
11906 */
11907 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11908 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11909
6892914f
MC		 11910 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11911 * we need to disable memory and use config. cycles
11912 * only to access all registers. The 5702/03 chips
11913 * can mistakenly decode the special cycles from the
11914 * ICH chipsets as memory write cycles, causing corruption
11915 * of register and memory space. Only certain ICH bridges
11916 * will drive special cycles with non-zero data during the
11917 * address phase which can fall within the 5703's address
11918 * range. This is not an ICH bug as the PCI spec allows
11919 * non-zero address during special cycles. However, only
11920 * these ICH bridges are known to drive non-zero addresses
11921 * during special cycles.
11922 *
11923 * Since special cycles do not cross PCI bridges, we only
11924 * enable this workaround if the 5703 is on the secondary
11925 * bus of these ICH bridges.
11926 */
11927 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11928 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11929 static struct tg3_dev_id {
11930 u32 vendor;
11931 u32 device;
11932 u32 rev;
11933 } ich_chipsets[] = {
11934 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11935 PCI_ANY_ID },
11936 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11937 PCI_ANY_ID },
11938 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11939 0xa },
11940 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11941 PCI_ANY_ID },
11942 { },
11943 };
11944 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11945 struct pci_dev *bridge = NULL;
11946
11947 while (pci_id->vendor != 0) {
11948 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11949 bridge);
11950 if (!bridge) {
11951 pci_id++;
11952 continue;
11953 }
11954 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11955 if (bridge->revision > pci_id->rev)
6892914f
MC		 11956 continue;
11957 }
11958 if (bridge->subordinate &&
11959 (bridge->subordinate->number ==
11960 tp->pdev->bus->number)) {
11961
11962 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11963 pci_dev_put(bridge);
11964 break;
11965 }
11966 }
11967 }
11968
41588ba1
MC		 11969 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11970 static struct tg3_dev_id {
11971 u32 vendor;
11972 u32 device;
11973 } bridge_chipsets[] = {
11974 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11975 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11976 { },
11977 };
11978 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11979 struct pci_dev *bridge = NULL;
11980
11981 while (pci_id->vendor != 0) {
11982 bridge = pci_get_device(pci_id->vendor,
11983 pci_id->device,
11984 bridge);
11985 if (!bridge) {
11986 pci_id++;
11987 continue;
11988 }
11989 if (bridge->subordinate &&
11990 (bridge->subordinate->number <=
11991 tp->pdev->bus->number) &&
11992 (bridge->subordinate->subordinate >=
11993 tp->pdev->bus->number)) {
11994 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11995 pci_dev_put(bridge);
11996 break;
11997 }
11998 }
11999 }
12000
4a29cc2e
MC		 12001 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12002 * DMA addresses > 40-bit. This bridge may have other additional
12003 * 57xx devices behind it in some 4-port NIC designs for example.
12004 * Any tg3 device found behind the bridge will also need the 40-bit
12005 * DMA workaround.
12006 */
a4e2b347
MC		 12007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12009 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12010 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12011 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12012 }
4a29cc2e
MC		 12013 else {
12014 struct pci_dev *bridge = NULL;
12015
12016 do {
12017 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12018 PCI_DEVICE_ID_SERVERWORKS_EPB,
12019 bridge);
12020 if (bridge && bridge->subordinate &&
12021 (bridge->subordinate->number <=
12022 tp->pdev->bus->number) &&
12023 (bridge->subordinate->subordinate >=
12024 tp->pdev->bus->number)) {
12025 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12026 pci_dev_put(bridge);
12027 break;
12028 }
12029 } while (bridge);
12030 }
4cf78e4f 12031
1da177e4
LT		 12032 /* Initialize misc host control in PCI block. */
12033 tp->misc_host_ctrl |= (misc_ctrl_reg &
12034 MISC_HOST_CTRL_CHIPREV);
12035 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12036 tp->misc_host_ctrl);
12037
7544b097
MC		 12038 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12039 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12040 tp->pdev_peer = tg3_find_peer(tp);
12041
321d32a0
MC		 12042 /* Intentionally exclude ASIC_REV_5906 */
12043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 12048 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12049 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12050
12051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12054 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12055 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12056 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12057
1b440c56
JL		 12058 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12059 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12060 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12061
027455ad
MC		 12062 /* 5700 B0 chips do not support checksumming correctly due
12063 * to hardware bugs.
12064 */
12065 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12066 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12067 else {
12068 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12069 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12070 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12071 tp->dev->features |= NETIF_F_IPV6_CSUM;
12072 }
12073
5a6f3074 12074 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12075 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12076 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12077 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12078 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12079 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12080 tp->pdev_peer == tp->pdev))
12081 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12082
321d32a0 12083 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12085 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12086 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12087 } else {
7f62ad5d 12088 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12089 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12090 ASIC_REV_5750 &&
12091 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12092 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12093 }
5a6f3074 12094 }
1da177e4 12095
f51f3562
MC		 12096 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12097 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8f666b07 12098 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12099
52f4490c
MC		 12100 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12101 &pci_state_reg);
12102
5e7dfd0f
MC		 12103 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12104 if (tp->pcie_cap != 0) {
12105 u16 lnkctl;
12106
1da177e4 12107 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12108
12109 pcie_set_readrq(tp->pdev, 4096);
12110
5e7dfd0f
MC		 12111 pci_read_config_word(tp->pdev,
12112 tp->pcie_cap + PCI_EXP_LNKCTL,
12113 &lnkctl);
12114 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12116 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12117 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12118 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12119 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12120 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12121 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12122 }
52f4490c 12123 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12124 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12125 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12126 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12127 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12128 if (!tp->pcix_cap) {
12129 printk(KERN_ERR PFX "Cannot find PCI-X "
12130 "capability, aborting.\n");
12131 return -EIO;
12132 }
12133
12134 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12135 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12136 }
1da177e4 12137
399de50b
MC		 12138 /* If we have an AMD 762 or VIA K8T800 chipset, write
12139 * reordering to the mailbox registers done by the host
12140 * controller can cause major troubles. We read back from
12141 * every mailbox register write to force the writes to be
12142 * posted to the chip in order.
12143 */
12144 if (pci_dev_present(write_reorder_chipsets) &&
12145 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12146 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12147
69fc4053
MC		 12148 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12149 &tp->pci_cacheline_sz);
12150 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12151 &tp->pci_lat_timer);
1da177e4
LT		 12152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12153 tp->pci_lat_timer < 64) {
12154 tp->pci_lat_timer = 64;
69fc4053
MC		 12155 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12156 tp->pci_lat_timer);
1da177e4
LT		 12157 }
12158
52f4490c
MC		 12159 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12160 /* 5700 BX chips need to have their TX producer index
12161 * mailboxes written twice to workaround a bug.
12162 */
12163 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12164
52f4490c 12165 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12166 *
12167 * The workaround is to use indirect register accesses
12168 * for all chip writes not to mailbox registers.
12169 */
52f4490c 12170 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12171 u32 pm_reg;
1da177e4
LT		 12172
12173 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12174
12175 /* The chip can have it's power management PCI config
12176 * space registers clobbered due to this bug.
12177 * So explicitly force the chip into D0 here.
12178 */
9974a356
MC		 12179 pci_read_config_dword(tp->pdev,
12180 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12181 &pm_reg);
12182 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12183 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12184 pci_write_config_dword(tp->pdev,
12185 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12186 pm_reg);
12187
12188 /* Also, force SERR#/PERR# in PCI command. */
12189 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12190 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12191 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12192 }
12193 }
12194
1da177e4
LT		 12195 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12196 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12197 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12198 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12199
12200 /* Chip-specific fixup from Broadcom driver */
12201 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12202 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12203 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12204 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12205 }
12206
1ee582d8 12207 /* Default fast path register access methods */
20094930 12208 tp->read32 = tg3_read32;
1ee582d8 12209 tp->write32 = tg3_write32;
09ee929c 12210 tp->read32_mbox = tg3_read32;
20094930 12211 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12212 tp->write32_tx_mbox = tg3_write32;
12213 tp->write32_rx_mbox = tg3_write32;
12214
12215 /* Various workaround register access methods */
12216 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12217 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12218 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12219 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12220 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12221 /*
12222 * Back to back register writes can cause problems on these
12223 * chips, the workaround is to read back all reg writes
12224 * except those to mailbox regs.
12225 *
12226 * See tg3_write_indirect_reg32().
12227 */
1ee582d8 12228 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12229 }
12230
1ee582d8
MC		 12231
12232 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12233 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12234 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12235 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12236 tp->write32_rx_mbox = tg3_write_flush_reg32;
12237 }
20094930 12238
6892914f
MC		 12239 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12240 tp->read32 = tg3_read_indirect_reg32;
12241 tp->write32 = tg3_write_indirect_reg32;
12242 tp->read32_mbox = tg3_read_indirect_mbox;
12243 tp->write32_mbox = tg3_write_indirect_mbox;
12244 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12245 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12246
12247 iounmap(tp->regs);
22abe310 12248 tp->regs = NULL;
6892914f
MC		 12249
12250 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12251 pci_cmd &= ~PCI_COMMAND_MEMORY;
12252 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12253 }
b5d3772c
MC		 12254 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12255 tp->read32_mbox = tg3_read32_mbox_5906;
12256 tp->write32_mbox = tg3_write32_mbox_5906;
12257 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12258 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12259 }
6892914f 12260
bbadf503
MC		 12261 if (tp->write32 == tg3_write_indirect_reg32 ||
12262 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12263 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12265 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12266
7d0c41ef 12267 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12268 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12269 * determined before calling tg3_set_power_state() so that
12270 * we know whether or not to switch out of Vaux power.
12271 * When the flag is set, it means that GPIO1 is used for eeprom
12272 * write protect and also implies that it is a LOM where GPIOs
12273 * are not used to switch power.
6aa20a22 12274 */
7d0c41ef
MC		 12275 tg3_get_eeprom_hw_cfg(tp);
12276
0d3031d9
MC		 12277 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12278 /* Allow reads and writes to the
12279 * APE register and memory space.
12280 */
12281 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12282 PCISTATE_ALLOW_APE_SHMEM_WR;
12283 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12284 pci_state_reg);
12285 }
12286
9936bcf6 12287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12289 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12291 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12292
314fba34
MC		 12293 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12294 * GPIO1 driven high will bring 5700's external PHY out of reset.
12295 * It is also used as eeprom write protect on LOMs.
12296 */
12297 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12298 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12299 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12300 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12301 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12302 /* Unused GPIO3 must be driven as output on 5752 because there
12303 * are no pull-up resistors on unused GPIO pins.
12304 */
12305 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12306 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12307
321d32a0
MC		 12308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12310 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12311
8d519ab2
MC		 12312 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12313 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12314 /* Turn off the debug UART. */
12315 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12316 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12317 /* Keep VMain power. */
12318 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12319 GRC_LCLCTRL_GPIO_OUTPUT0;
12320 }
12321
1da177e4 12322 /* Force the chip into D0. */
bc1c7567 12323 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12324 if (err) {
12325 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12326 pci_name(tp->pdev));
12327 return err;
12328 }
12329
1da177e4
LT		 12330 /* Derive initial jumbo mode from MTU assigned in
12331 * ether_setup() via the alloc_etherdev() call
12332 */
0f893dc6 12333 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12334 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12335 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12336
12337 /* Determine WakeOnLan speed to use. */
12338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12339 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12340 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12341 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12342 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12343 } else {
12344 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12345 }
12346
7f97a4bd
MC		 12347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12348 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12349
1da177e4
LT		 12350 /* A few boards don't want Ethernet@WireSpeed phy feature */
12351 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12352 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12353 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12354 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12355 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12356 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12357 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12358
12359 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12360 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12361 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12362 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12363 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12364
321d32a0 12365 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12366 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0
MC		 12367 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12368 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12369 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12370 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12372 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12373 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12374 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12375 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12376 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12377 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12378 } else
c424cb24
MC		 12379 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12380 }
1da177e4 12381
b2a5c19c
MC		 12382 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12383 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12384 tp->phy_otp = tg3_read_otp_phycfg(tp);
12385 if (tp->phy_otp == 0)
12386 tp->phy_otp = TG3_OTP_DEFAULT;
12387 }
12388
f51f3562 12389 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12390 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12391 else
12392 tp->mi_mode = MAC_MI_MODE_BASE;
12393
1da177e4 12394 tp->coalesce_mode = 0;
1da177e4
LT		 12395 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12396 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12397 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12398
321d32a0
MC		 12399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12400 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12401 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12402
255ca311
MC		 12403 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12404 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12405 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12406 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12407
158d7abd
MC		 12408 err = tg3_mdio_init(tp);
12409 if (err)
12410 return err;
1da177e4
LT		 12411
12412 /* Initialize data/descriptor byte/word swapping. */
12413 val = tr32(GRC_MODE);
12414 val &= GRC_MODE_HOST_STACKUP;
12415 tw32(GRC_MODE, val | tp->grc_mode);
12416
12417 tg3_switch_clocks(tp);
12418
12419 /* Clear this out for sanity. */
12420 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12421
12422 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12423 &pci_state_reg);
12424 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12425 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12426 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12427
12428 if (chiprevid == CHIPREV_ID_5701_A0 ||
12429 chiprevid == CHIPREV_ID_5701_B0 ||
12430 chiprevid == CHIPREV_ID_5701_B2 ||
12431 chiprevid == CHIPREV_ID_5701_B5) {
12432 void __iomem *sram_base;
12433
12434 /* Write some dummy words into the SRAM status block
12435 * area, see if it reads back correctly. If the return
12436 * value is bad, force enable the PCIX workaround.
12437 */
12438 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12439
12440 writel(0x00000000, sram_base);
12441 writel(0x00000000, sram_base + 4);
12442 writel(0xffffffff, sram_base + 4);
12443 if (readl(sram_base) != 0x00000000)
12444 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12445 }
12446 }
12447
12448 udelay(50);
12449 tg3_nvram_init(tp);
12450
12451 grc_misc_cfg = tr32(GRC_MISC_CFG);
12452 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12453
1da177e4
LT		 12454 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12455 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12456 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12457 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12458
fac9b83e
DM		 12459 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12460 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12461 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12462 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12463 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12464 HOSTCC_MODE_CLRTICK_TXBD);
12465
12466 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12467 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12468 tp->misc_host_ctrl);
12469 }
12470
3bda1258
MC		 12471 /* Preserve the APE MAC_MODE bits */
12472 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12473 tp->mac_mode = tr32(MAC_MODE) |
12474 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12475 else
12476 tp->mac_mode = TG3_DEF_MAC_MODE;
12477
1da177e4
LT		 12478 /* these are limited to 10/100 only */
12479 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12480 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12481 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12482 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12483 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12484 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12485 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12486 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12487 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12488 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12489 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12490 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 12491 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 12492 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12493
12494 err = tg3_phy_probe(tp);
12495 if (err) {
12496 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12497 pci_name(tp->pdev), err);
12498 /* ... but do not return immediately ... */
b02fd9e3 12499 tg3_mdio_fini(tp);
1da177e4
LT		 12500 }
12501
12502 tg3_read_partno(tp);
c4e6575c 12503 tg3_read_fw_ver(tp);
1da177e4
LT		 12504
12505 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12506 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12507 } else {
12508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12509 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12510 else
12511 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12512 }
12513
12514 /* 5700 {AX,BX} chips have a broken status block link
12515 * change bit implementation, so we must use the
12516 * status register in those cases.
12517 */
12518 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12519 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12520 else
12521 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12522
12523 /* The led_ctrl is set during tg3_phy_probe, here we might
12524 * have to force the link status polling mechanism based
12525 * upon subsystem IDs.
12526 */
12527 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12529 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12530 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12531 TG3_FLAG_USE_LINKCHG_REG);
12532 }
12533
12534 /* For all SERDES we poll the MAC status register. */
12535 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12536 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12537 else
12538 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12539
ad829268 12540 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12542 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12543 tp->rx_offset = 0;
12544
f92905de
MC		 12545 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12546
12547 /* Increment the rx prod index on the rx std ring by at most
12548 * 8 for these chips to workaround hw errata.
12549 */
12550 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12551 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12552 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12553 tp->rx_std_max_post = 8;
12554
8ed5d97e
MC		 12555 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12556 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12557 PCIE_PWR_MGMT_L1_THRESH_MSK;
12558
1da177e4
LT		 12559 return err;
12560}
12561
49b6e95f 12562#ifdef CONFIG_SPARC
1da177e4
LT		 12563static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12564{
12565 struct net_device *dev = tp->dev;
12566 struct pci_dev *pdev = tp->pdev;
49b6e95f 12567 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12568 const unsigned char *addr;
49b6e95f
DM		 12569 int len;
12570
12571 addr = of_get_property(dp, "local-mac-address", &len);
12572 if (addr && len == 6) {
12573 memcpy(dev->dev_addr, addr, 6);
12574 memcpy(dev->perm_addr, dev->dev_addr, 6);
12575 return 0;
1da177e4
LT		 12576 }
12577 return -ENODEV;
12578}
12579
12580static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12581{
12582 struct net_device *dev = tp->dev;
12583
12584 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12585 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12586 return 0;
12587}
12588#endif
12589
12590static int __devinit tg3_get_device_address(struct tg3 *tp)
12591{
12592 struct net_device *dev = tp->dev;
12593 u32 hi, lo, mac_offset;
008652b3 12594 int addr_ok = 0;
1da177e4 12595
49b6e95f 12596#ifdef CONFIG_SPARC
1da177e4
LT		 12597 if (!tg3_get_macaddr_sparc(tp))
12598 return 0;
12599#endif
12600
12601 mac_offset = 0x7c;
f49639e6 12602 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12603 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12604 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12605 mac_offset = 0xcc;
12606 if (tg3_nvram_lock(tp))
12607 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12608 else
12609 tg3_nvram_unlock(tp);
12610 }
b5d3772c
MC		 12611 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12612 mac_offset = 0x10;
1da177e4
LT		 12613
12614 /* First try to get it from MAC address mailbox. */
12615 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12616 if ((hi >> 16) == 0x484b) {
12617 dev->dev_addr[0] = (hi >> 8) & 0xff;
12618 dev->dev_addr[1] = (hi >> 0) & 0xff;
12619
12620 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12621 dev->dev_addr[2] = (lo >> 24) & 0xff;
12622 dev->dev_addr[3] = (lo >> 16) & 0xff;
12623 dev->dev_addr[4] = (lo >> 8) & 0xff;
12624 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12625
008652b3
MC		 12626 /* Some old bootcode may report a 0 MAC address in SRAM */
12627 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12628 }
12629 if (!addr_ok) {
12630 /* Next, try NVRAM. */
df259d8c
MC		 12631 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12632 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12633 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12634 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12635 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12636 }
12637 /* Finally just fetch it out of the MAC control regs. */
12638 else {
12639 hi = tr32(MAC_ADDR_0_HIGH);
12640 lo = tr32(MAC_ADDR_0_LOW);
12641
12642 dev->dev_addr[5] = lo & 0xff;
12643 dev->dev_addr[4] = (lo >> 8) & 0xff;
12644 dev->dev_addr[3] = (lo >> 16) & 0xff;
12645 dev->dev_addr[2] = (lo >> 24) & 0xff;
12646 dev->dev_addr[1] = hi & 0xff;
12647 dev->dev_addr[0] = (hi >> 8) & 0xff;
12648 }
1da177e4
LT		 12649 }
12650
12651 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12652#ifdef CONFIG_SPARC
1da177e4
LT		 12653 if (!tg3_get_default_macaddr_sparc(tp))
12654 return 0;
12655#endif
12656 return -EINVAL;
12657 }
2ff43697 12658 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12659 return 0;
12660}
12661
59e6b434
DM		 12662#define BOUNDARY_SINGLE_CACHELINE 1
12663#define BOUNDARY_MULTI_CACHELINE 2
12664
12665static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12666{
12667 int cacheline_size;
12668 u8 byte;
12669 int goal;
12670
12671 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12672 if (byte == 0)
12673 cacheline_size = 1024;
12674 else
12675 cacheline_size = (int) byte * 4;
12676
12677 /* On 5703 and later chips, the boundary bits have no
12678 * effect.
12679 */
12680 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12681 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12682 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12683 goto out;
12684
12685#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12686 goal = BOUNDARY_MULTI_CACHELINE;
12687#else
12688#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12689 goal = BOUNDARY_SINGLE_CACHELINE;
12690#else
12691 goal = 0;
12692#endif
12693#endif
12694
12695 if (!goal)
12696 goto out;
12697
12698 /* PCI controllers on most RISC systems tend to disconnect
12699 * when a device tries to burst across a cache-line boundary.
12700 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12701 *
12702 * Unfortunately, for PCI-E there are only limited
12703 * write-side controls for this, and thus for reads
12704 * we will still get the disconnects. We'll also waste
12705 * these PCI cycles for both read and write for chips
12706 * other than 5700 and 5701 which do not implement the
12707 * boundary bits.
12708 */
12709 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12710 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12711 switch (cacheline_size) {
12712 case 16:
12713 case 32:
12714 case 64:
12715 case 128:
12716 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12717 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12718 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12719 } else {
12720 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12721 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12722 }
12723 break;
12724
12725 case 256:
12726 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12727 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12728 break;
12729
12730 default:
12731 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12732 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12733 break;
855e1111 12734 }
59e6b434
DM		 12735 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12736 switch (cacheline_size) {
12737 case 16:
12738 case 32:
12739 case 64:
12740 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12741 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12742 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12743 break;
12744 }
12745 /* fallthrough */
12746 case 128:
12747 default:
12748 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12749 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12750 break;
855e1111 12751 }
59e6b434
DM		 12752 } else {
12753 switch (cacheline_size) {
12754 case 16:
12755 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12756 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12757 DMA_RWCTRL_WRITE_BNDRY_16);
12758 break;
12759 }
12760 /* fallthrough */
12761 case 32:
12762 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12763 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12764 DMA_RWCTRL_WRITE_BNDRY_32);
12765 break;
12766 }
12767 /* fallthrough */
12768 case 64:
12769 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12770 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12771 DMA_RWCTRL_WRITE_BNDRY_64);
12772 break;
12773 }
12774 /* fallthrough */
12775 case 128:
12776 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12777 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12778 DMA_RWCTRL_WRITE_BNDRY_128);
12779 break;
12780 }
12781 /* fallthrough */
12782 case 256:
12783 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12784 DMA_RWCTRL_WRITE_BNDRY_256);
12785 break;
12786 case 512:
12787 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12788 DMA_RWCTRL_WRITE_BNDRY_512);
12789 break;
12790 case 1024:
12791 default:
12792 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12793 DMA_RWCTRL_WRITE_BNDRY_1024);
12794 break;
855e1111 12795 }
59e6b434
DM		 12796 }
12797
12798out:
12799 return val;
12800}
12801
1da177e4
LT		 12802static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12803{
12804 struct tg3_internal_buffer_desc test_desc;
12805 u32 sram_dma_descs;
12806 int i, ret;
12807
12808 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12809
12810 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12811 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12812 tw32(RDMAC_STATUS, 0);
12813 tw32(WDMAC_STATUS, 0);
12814
12815 tw32(BUFMGR_MODE, 0);
12816 tw32(FTQ_RESET, 0);
12817
12818 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12819 test_desc.addr_lo = buf_dma & 0xffffffff;
12820 test_desc.nic_mbuf = 0x00002100;
12821 test_desc.len = size;
12822
12823 /*
12824 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12825 * the *second* time the tg3 driver was getting loaded after an
12826 * initial scan.
12827 *
12828 * Broadcom tells me:
12829 * ...the DMA engine is connected to the GRC block and a DMA
12830 * reset may affect the GRC block in some unpredictable way...
12831 * The behavior of resets to individual blocks has not been tested.
12832 *
12833 * Broadcom noted the GRC reset will also reset all sub-components.
12834 */
12835 if (to_device) {
12836 test_desc.cqid_sqid = (13 << 8) | 2;
12837
12838 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12839 udelay(40);
12840 } else {
12841 test_desc.cqid_sqid = (16 << 8) | 7;
12842
12843 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12844 udelay(40);
12845 }
12846 test_desc.flags = 0x00000005;
12847
12848 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12849 u32 val;
12850
12851 val = *(((u32 *)&test_desc) + i);
12852 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12853 sram_dma_descs + (i * sizeof(u32)));
12854 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12855 }
12856 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12857
12858 if (to_device) {
12859 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12860 } else {
12861 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12862 }
12863
12864 ret = -ENODEV;
12865 for (i = 0; i < 40; i++) {
12866 u32 val;
12867
12868 if (to_device)
12869 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12870 else
12871 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12872 if ((val & 0xffff) == sram_dma_descs) {
12873 ret = 0;
12874 break;
12875 }
12876
12877 udelay(100);
12878 }
12879
12880 return ret;
12881}
12882
ded7340d 12883#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12884
12885static int __devinit tg3_test_dma(struct tg3 *tp)
12886{
12887 dma_addr_t buf_dma;
59e6b434 12888 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12889 int ret;
12890
12891 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12892 if (!buf) {
12893 ret = -ENOMEM;
12894 goto out_nofree;
12895 }
12896
12897 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12898 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12899
59e6b434 12900 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12901
12902 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12903 /* DMA read watermark not used on PCIE */
12904 tp->dma_rwctrl |= 0x00180000;
12905 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12907 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12908 tp->dma_rwctrl |= 0x003f0000;
12909 else
12910 tp->dma_rwctrl |= 0x003f000f;
12911 } else {
12912 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12913 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12914 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12915 u32 read_water = 0x7;
1da177e4 12916
4a29cc2e
MC		 12917 /* If the 5704 is behind the EPB bridge, we can
12918 * do the less restrictive ONE_DMA workaround for
12919 * better performance.
12920 */
12921 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12923 tp->dma_rwctrl |= 0x8000;
12924 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12925 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12926
49afdeb6
MC		 12927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12928 read_water = 4;
59e6b434 12929 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12930 tp->dma_rwctrl |=
12931 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12932 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12933 (1 << 23);
4cf78e4f
MC		 12934 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12935 /* 5780 always in PCIX mode */
12936 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12937 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12938 /* 5714 always in PCIX mode */
12939 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12940 } else {
12941 tp->dma_rwctrl |= 0x001b000f;
12942 }
12943 }
12944
12945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12947 tp->dma_rwctrl &= 0xfffffff0;
12948
12949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12951 /* Remove this if it causes problems for some boards. */
12952 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12953
12954 /* On 5700/5701 chips, we need to set this bit.
12955 * Otherwise the chip will issue cacheline transactions
12956 * to streamable DMA memory with not all the byte
12957 * enables turned on. This is an error on several
12958 * RISC PCI controllers, in particular sparc64.
12959 *
12960 * On 5703/5704 chips, this bit has been reassigned
12961 * a different meaning. In particular, it is used
12962 * on those chips to enable a PCI-X workaround.
12963 */
12964 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12965 }
12966
12967 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12968
12969#if 0
12970 /* Unneeded, already done by tg3_get_invariants. */
12971 tg3_switch_clocks(tp);
12972#endif
12973
12974 ret = 0;
12975 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12976 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12977 goto out;
12978
59e6b434
DM		 12979 /* It is best to perform DMA test with maximum write burst size
12980 * to expose the 5700/5701 write DMA bug.
12981 */
12982 saved_dma_rwctrl = tp->dma_rwctrl;
12983 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12984 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12985
1da177e4
LT		 12986 while (1) {
12987 u32 *p = buf, i;
12988
12989 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12990 p[i] = i;
12991
12992 /* Send the buffer to the chip. */
12993 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12994 if (ret) {
12995 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12996 break;
12997 }
12998
12999#if 0
13000 /* validate data reached card RAM correctly. */
13001 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13002 u32 val;
13003 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13004 if (le32_to_cpu(val) != p[i]) {
13005 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13006 /* ret = -ENODEV here? */
13007 }
13008 p[i] = 0;
13009 }
13010#endif
13011 /* Now read it back. */
13012 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13013 if (ret) {
13014 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13015
13016 break;
13017 }
13018
13019 /* Verify it. */
13020 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13021 if (p[i] == i)
13022 continue;
13023
59e6b434
DM		 13024 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13025 DMA_RWCTRL_WRITE_BNDRY_16) {
13026 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13027 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13028 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13029 break;
13030 } else {
13031 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13032 ret = -ENODEV;
13033 goto out;
13034 }
13035 }
13036
13037 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13038 /* Success. */
13039 ret = 0;
13040 break;
13041 }
13042 }
59e6b434
DM		 13043 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13044 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13045 static struct pci_device_id dma_wait_state_chipsets[] = {
13046 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13047 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13048 { },
13049 };
13050
59e6b434 13051 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13052 * now look for chipsets that are known to expose the
13053 * DMA bug without failing the test.
59e6b434 13054 */
6d1cfbab
MC		 13055 if (pci_dev_present(dma_wait_state_chipsets)) {
13056 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13057 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13058 }
13059 else
13060 /* Safe to use the calculated DMA boundary. */
13061 tp->dma_rwctrl = saved_dma_rwctrl;
13062
59e6b434
DM		 13063 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13064 }
1da177e4
LT		 13065
13066out:
13067 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13068out_nofree:
13069 return ret;
13070}
13071
13072static void __devinit tg3_init_link_config(struct tg3 *tp)
13073{
13074 tp->link_config.advertising =
13075 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13076 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13077 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13078 ADVERTISED_Autoneg | ADVERTISED_MII);
13079 tp->link_config.speed = SPEED_INVALID;
13080 tp->link_config.duplex = DUPLEX_INVALID;
13081 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13082 tp->link_config.active_speed = SPEED_INVALID;
13083 tp->link_config.active_duplex = DUPLEX_INVALID;
13084 tp->link_config.phy_is_low_power = 0;
13085 tp->link_config.orig_speed = SPEED_INVALID;
13086 tp->link_config.orig_duplex = DUPLEX_INVALID;
13087 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13088}
13089
13090static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13091{
fdfec172
MC		 13092 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13093 tp->bufmgr_config.mbuf_read_dma_low_water =
13094 DEFAULT_MB_RDMA_LOW_WATER_5705;
13095 tp->bufmgr_config.mbuf_mac_rx_low_water =
13096 DEFAULT_MB_MACRX_LOW_WATER_5705;
13097 tp->bufmgr_config.mbuf_high_water =
13098 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13100 tp->bufmgr_config.mbuf_mac_rx_low_water =
13101 DEFAULT_MB_MACRX_LOW_WATER_5906;
13102 tp->bufmgr_config.mbuf_high_water =
13103 DEFAULT_MB_HIGH_WATER_5906;
13104 }
fdfec172
MC		 13105
13106 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13107 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13108 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13109 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13110 tp->bufmgr_config.mbuf_high_water_jumbo =
13111 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13112 } else {
13113 tp->bufmgr_config.mbuf_read_dma_low_water =
13114 DEFAULT_MB_RDMA_LOW_WATER;
13115 tp->bufmgr_config.mbuf_mac_rx_low_water =
13116 DEFAULT_MB_MACRX_LOW_WATER;
13117 tp->bufmgr_config.mbuf_high_water =
13118 DEFAULT_MB_HIGH_WATER;
13119
13120 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13121 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13122 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13123 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13124 tp->bufmgr_config.mbuf_high_water_jumbo =
13125 DEFAULT_MB_HIGH_WATER_JUMBO;
13126 }
1da177e4
LT		 13127
13128 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13129 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13130}
13131
13132static char * __devinit tg3_phy_string(struct tg3 *tp)
13133{
13134 switch (tp->phy_id & PHY_ID_MASK) {
13135 case PHY_ID_BCM5400: return "5400";
13136 case PHY_ID_BCM5401: return "5401";
13137 case PHY_ID_BCM5411: return "5411";
13138 case PHY_ID_BCM5701: return "5701";
13139 case PHY_ID_BCM5703: return "5703";
13140 case PHY_ID_BCM5704: return "5704";
13141 case PHY_ID_BCM5705: return "5705";
13142 case PHY_ID_BCM5750: return "5750";
85e94ced 13143 case PHY_ID_BCM5752: return "5752";
a4e2b347 13144 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13145 case PHY_ID_BCM5780: return "5780";
af36e6b6 13146 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13147 case PHY_ID_BCM5787: return "5787";
d30cdd28 13148 case PHY_ID_BCM5784: return "5784";
126a3368 13149 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13150 case PHY_ID_BCM5906: return "5906";
9936bcf6 13151 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13152 case PHY_ID_BCM8002: return "8002/serdes";
13153 case 0: return "serdes";
13154 default: return "unknown";
855e1111 13155 }
1da177e4
LT		 13156}
13157
f9804ddb
MC		 13158static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13159{
13160 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13161 strcpy(str, "PCI Express");
13162 return str;
13163 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13164 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13165
13166 strcpy(str, "PCIX:");
13167
13168 if ((clock_ctrl == 7) ||
13169 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13170 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13171 strcat(str, "133MHz");
13172 else if (clock_ctrl == 0)
13173 strcat(str, "33MHz");
13174 else if (clock_ctrl == 2)
13175 strcat(str, "50MHz");
13176 else if (clock_ctrl == 4)
13177 strcat(str, "66MHz");
13178 else if (clock_ctrl == 6)
13179 strcat(str, "100MHz");
f9804ddb
MC		 13180 } else {
13181 strcpy(str, "PCI:");
13182 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13183 strcat(str, "66MHz");
13184 else
13185 strcat(str, "33MHz");
13186 }
13187 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13188 strcat(str, ":32-bit");
13189 else
13190 strcat(str, ":64-bit");
13191 return str;
13192}
13193
8c2dc7e1 13194static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13195{
13196 struct pci_dev *peer;
13197 unsigned int func, devnr = tp->pdev->devfn & ~7;
13198
13199 for (func = 0; func < 8; func++) {
13200 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13201 if (peer && peer != tp->pdev)
13202 break;
13203 pci_dev_put(peer);
13204 }
16fe9d74
MC		 13205 /* 5704 can be configured in single-port mode, set peer to
13206 * tp->pdev in that case.
13207 */
13208 if (!peer) {
13209 peer = tp->pdev;
13210 return peer;
13211 }
1da177e4
LT		 13212
13213 /*
13214 * We don't need to keep the refcount elevated; there's no way
13215 * to remove one half of this device without removing the other
13216 */
13217 pci_dev_put(peer);
13218
13219 return peer;
13220}
13221
15f9850d
DM		 13222static void __devinit tg3_init_coal(struct tg3 *tp)
13223{
13224 struct ethtool_coalesce *ec = &tp->coal;
13225
13226 memset(ec, 0, sizeof(*ec));
13227 ec->cmd = ETHTOOL_GCOALESCE;
13228 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13229 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13230 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13231 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13232 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13233 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13234 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13235 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13236 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13237
13238 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13239 HOSTCC_MODE_CLRTICK_TXBD)) {
13240 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13241 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13242 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13243 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13244 }
d244c892
MC		 13245
13246 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13247 ec->rx_coalesce_usecs_irq = 0;
13248 ec->tx_coalesce_usecs_irq = 0;
13249 ec->stats_block_coalesce_usecs = 0;
13250 }
15f9850d
DM		 13251}
13252
7c7d64b8
SH		 13253static const struct net_device_ops tg3_netdev_ops = {
13254 .ndo_open = tg3_open,
13255 .ndo_stop = tg3_close,
00829823
SH		 13256 .ndo_start_xmit = tg3_start_xmit,
13257 .ndo_get_stats = tg3_get_stats,
13258 .ndo_validate_addr = eth_validate_addr,
13259 .ndo_set_multicast_list = tg3_set_rx_mode,
13260 .ndo_set_mac_address = tg3_set_mac_addr,
13261 .ndo_do_ioctl = tg3_ioctl,
13262 .ndo_tx_timeout = tg3_tx_timeout,
13263 .ndo_change_mtu = tg3_change_mtu,
13264#if TG3_VLAN_TAG_USED
13265 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13266#endif
13267#ifdef CONFIG_NET_POLL_CONTROLLER
13268 .ndo_poll_controller = tg3_poll_controller,
13269#endif
13270};
13271
13272static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13273 .ndo_open = tg3_open,
13274 .ndo_stop = tg3_close,
13275 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13276 .ndo_get_stats = tg3_get_stats,
13277 .ndo_validate_addr = eth_validate_addr,
13278 .ndo_set_multicast_list = tg3_set_rx_mode,
13279 .ndo_set_mac_address = tg3_set_mac_addr,
13280 .ndo_do_ioctl = tg3_ioctl,
13281 .ndo_tx_timeout = tg3_tx_timeout,
13282 .ndo_change_mtu = tg3_change_mtu,
13283#if TG3_VLAN_TAG_USED
13284 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13285#endif
13286#ifdef CONFIG_NET_POLL_CONTROLLER
13287 .ndo_poll_controller = tg3_poll_controller,
13288#endif
13289};
13290
1da177e4
LT		 13291static int __devinit tg3_init_one(struct pci_dev *pdev,
13292 const struct pci_device_id *ent)
13293{
13294 static int tg3_version_printed = 0;
1da177e4
LT		 13295 struct net_device *dev;
13296 struct tg3 *tp;
d6645372 13297 int err, pm_cap;
f9804ddb 13298 char str[40];
72f2afb8 13299 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13300
13301 if (tg3_version_printed++ == 0)
13302 printk(KERN_INFO "%s", version);
13303
13304 err = pci_enable_device(pdev);
13305 if (err) {
13306 printk(KERN_ERR PFX "Cannot enable PCI device, "
13307 "aborting.\n");
13308 return err;
13309 }
13310
1da177e4
LT		 13311 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13312 if (err) {
13313 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13314 "aborting.\n");
13315 goto err_out_disable_pdev;
13316 }
13317
13318 pci_set_master(pdev);
13319
13320 /* Find power-management capability. */
13321 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13322 if (pm_cap == 0) {
13323 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13324 "aborting.\n");
13325 err = -EIO;
13326 goto err_out_free_res;
13327 }
13328
1da177e4
LT		 13329 dev = alloc_etherdev(sizeof(*tp));
13330 if (!dev) {
13331 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13332 err = -ENOMEM;
13333 goto err_out_free_res;
13334 }
13335
1da177e4
LT		 13336 SET_NETDEV_DEV(dev, &pdev->dev);
13337
1da177e4
LT		 13338#if TG3_VLAN_TAG_USED
13339 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13340#endif
13341
13342 tp = netdev_priv(dev);
13343 tp->pdev = pdev;
13344 tp->dev = dev;
13345 tp->pm_cap = pm_cap;
1da177e4
LT		 13346 tp->rx_mode = TG3_DEF_RX_MODE;
13347 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13348
1da177e4
LT		 13349 if (tg3_debug > 0)
13350 tp->msg_enable = tg3_debug;
13351 else
13352 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13353
13354 /* The word/byte swap controls here control register access byte
13355 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13356 * setting below.
13357 */
13358 tp->misc_host_ctrl =
13359 MISC_HOST_CTRL_MASK_PCI_INT |
13360 MISC_HOST_CTRL_WORD_SWAP |
13361 MISC_HOST_CTRL_INDIR_ACCESS |
13362 MISC_HOST_CTRL_PCISTATE_RW;
13363
13364 /* The NONFRM (non-frame) byte/word swap controls take effect
13365 * on descriptor entries, anything which isn't packet data.
13366 *
13367 * The StrongARM chips on the board (one for tx, one for rx)
13368 * are running in big-endian mode.
13369 */
13370 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13371 GRC_MODE_WSWAP_NONFRM_DATA);
13372#ifdef __BIG_ENDIAN
13373 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13374#endif
13375 spin_lock_init(&tp->lock);
1da177e4 13376 spin_lock_init(&tp->indirect_lock);
c4028958 13377 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13378
d5fe488a 13379 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13380 if (!tp->regs) {
1da177e4
LT		 13381 printk(KERN_ERR PFX "Cannot map device registers, "
13382 "aborting.\n");
13383 err = -ENOMEM;
13384 goto err_out_free_dev;
13385 }
13386
13387 tg3_init_link_config(tp);
13388
1da177e4
LT		 13389 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13390 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13391 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13392
8ef0442f
MC		 13393 tp->napi[0].tp = tp;
13394 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 13395 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13396 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13397 dev->irq = pdev->irq;
1da177e4
LT		 13398
13399 err = tg3_get_invariants(tp);
13400 if (err) {
13401 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13402 "aborting.\n");
13403 goto err_out_iounmap;
13404 }
13405
321d32a0 13406 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13407 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13408 dev->netdev_ops = &tg3_netdev_ops;
13409 else
13410 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13411
13412
4a29cc2e
MC		 13413 /* The EPB bridge inside 5714, 5715, and 5780 and any
13414 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13415 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13416 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13417 * do DMA address check in tg3_start_xmit().
13418 */
4a29cc2e 13419 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13420 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13421 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13422 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13423#ifdef CONFIG_HIGHMEM
6a35528a 13424 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13425#endif
4a29cc2e 13426 } else
6a35528a 13427 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13428
13429 /* Configure DMA attributes. */
284901a9 13430 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13431 err = pci_set_dma_mask(pdev, dma_mask);
13432 if (!err) {
13433 dev->features |= NETIF_F_HIGHDMA;
13434 err = pci_set_consistent_dma_mask(pdev,
13435 persist_dma_mask);
13436 if (err < 0) {
13437 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13438 "DMA for consistent allocations\n");
13439 goto err_out_iounmap;
13440 }
13441 }
13442 }
284901a9
YH		 13443 if (err || dma_mask == DMA_BIT_MASK(32)) {
13444 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13445 if (err) {
13446 printk(KERN_ERR PFX "No usable DMA configuration, "
13447 "aborting.\n");
13448 goto err_out_iounmap;
13449 }
13450 }
13451
fdfec172 13452 tg3_init_bufmgr_config(tp);
1da177e4 13453
077f849d 13454 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13455 tp->fw_needed = FIRMWARE_TG3;
077f849d 13456
1da177e4
LT		 13457 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13458 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13459 }
13460 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13461 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13462 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13463 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13464 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13465 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13466 } else {
7f62ad5d 13467 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13469 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13470 else
9e9fd12d 13471 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13472 }
1da177e4 13473
4e3a7aaa
MC		 13474 /* TSO is on by default on chips that support hardware TSO.
13475 * Firmware TSO on older chips gives lower performance, so it
13476 * is off by default, but can be enabled using ethtool.
13477 */
b0026624 13478 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13479 if (dev->features & NETIF_F_IP_CSUM)
13480 dev->features |= NETIF_F_TSO;
13481 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13482 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13483 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13485 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13486 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13487 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13488 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13489 dev->features |= NETIF_F_TSO_ECN;
b0026624 13490 }
1da177e4 13491
1da177e4
LT		 13492
13493 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13494 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13495 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13496 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13497 tp->rx_pending = 63;
13498 }
13499
1da177e4
LT		 13500 err = tg3_get_device_address(tp);
13501 if (err) {
13502 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13503 "aborting.\n");
077f849d 13504 goto err_out_fw;
1da177e4
LT		 13505 }
13506
c88864df 13507 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13508 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13509 if (!tp->aperegs) {
c88864df
MC		 13510 printk(KERN_ERR PFX "Cannot map APE registers, "
13511 "aborting.\n");
13512 err = -ENOMEM;
077f849d 13513 goto err_out_fw;
c88864df
MC		 13514 }
13515
13516 tg3_ape_lock_init(tp);
7fd76445
MC		 13517
13518 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13519 tg3_read_dash_ver(tp);
c88864df
MC		 13520 }
13521
1da177e4
LT		 13522 /*
13523 * Reset chip in case UNDI or EFI driver did not shutdown
13524 * DMA self test will enable WDMAC and we'll see (spurious)
13525 * pending DMA on the PCI bus at that point.
13526 */
13527 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13528 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13529 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13530 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13531 }
13532
13533 err = tg3_test_dma(tp);
13534 if (err) {
13535 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13536 goto err_out_apeunmap;
1da177e4
LT		 13537 }
13538
1da177e4
LT		 13539 /* flow control autonegotiation is default behavior */
13540 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13541 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13542
15f9850d
DM		 13543 tg3_init_coal(tp);
13544
c49a1561
MC		 13545 pci_set_drvdata(pdev, dev);
13546
1da177e4
LT		 13547 err = register_netdev(dev);
13548 if (err) {
13549 printk(KERN_ERR PFX "Cannot register net device, "
13550 "aborting.\n");
0d3031d9 13551 goto err_out_apeunmap;
1da177e4
LT		 13552 }
13553
df59c940 13554 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13555 dev->name,
13556 tp->board_part_number,
13557 tp->pci_chip_rev_id,
f9804ddb 13558 tg3_bus_string(tp, str),
e174961c 13559 dev->dev_addr);
1da177e4 13560
df59c940
MC		 13561 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13562 printk(KERN_INFO
13563 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13564 tp->dev->name,
13565 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13566 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13567 else
13568 printk(KERN_INFO
13569 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13570 tp->dev->name, tg3_phy_string(tp),
13571 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13572 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13573 "10/100/1000Base-T")),
13574 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13575
13576 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13577 dev->name,
13578 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13579 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13580 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13581 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13582 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13583 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13584 dev->name, tp->dma_rwctrl,
284901a9 13585 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13586 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13587
13588 return 0;
13589
0d3031d9
MC		 13590err_out_apeunmap:
13591 if (tp->aperegs) {
13592 iounmap(tp->aperegs);
13593 tp->aperegs = NULL;
13594 }
13595
077f849d
JSR		 13596err_out_fw:
13597 if (tp->fw)
13598 release_firmware(tp->fw);
13599
1da177e4 13600err_out_iounmap:
6892914f
MC		 13601 if (tp->regs) {
13602 iounmap(tp->regs);
22abe310 13603 tp->regs = NULL;
6892914f 13604 }
1da177e4
LT		 13605
13606err_out_free_dev:
13607 free_netdev(dev);
13608
13609err_out_free_res:
13610 pci_release_regions(pdev);
13611
13612err_out_disable_pdev:
13613 pci_disable_device(pdev);
13614 pci_set_drvdata(pdev, NULL);
13615 return err;
13616}
13617
13618static void __devexit tg3_remove_one(struct pci_dev *pdev)
13619{
13620 struct net_device *dev = pci_get_drvdata(pdev);
13621
13622 if (dev) {
13623 struct tg3 *tp = netdev_priv(dev);
13624
077f849d
JSR		 13625 if (tp->fw)
13626 release_firmware(tp->fw);
13627
7faa006f 13628 flush_scheduled_work();
158d7abd 13629
b02fd9e3
MC		 13630 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13631 tg3_phy_fini(tp);
158d7abd 13632 tg3_mdio_fini(tp);
b02fd9e3 13633 }
158d7abd 13634
1da177e4 13635 unregister_netdev(dev);
0d3031d9
MC		 13636 if (tp->aperegs) {
13637 iounmap(tp->aperegs);
13638 tp->aperegs = NULL;
13639 }
6892914f
MC		 13640 if (tp->regs) {
13641 iounmap(tp->regs);
22abe310 13642 tp->regs = NULL;
6892914f 13643 }
1da177e4
LT		 13644 free_netdev(dev);
13645 pci_release_regions(pdev);
13646 pci_disable_device(pdev);
13647 pci_set_drvdata(pdev, NULL);
13648 }
13649}
13650
13651static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13652{
13653 struct net_device *dev = pci_get_drvdata(pdev);
13654 struct tg3 *tp = netdev_priv(dev);
12dac075 13655 pci_power_t target_state;
1da177e4
LT		 13656 int err;
13657
3e0c95fd
MC		 13658 /* PCI register 4 needs to be saved whether netif_running() or not.
13659 * MSI address and data need to be saved if using MSI and
13660 * netif_running().
13661 */
13662 pci_save_state(pdev);
13663
1da177e4
LT		 13664 if (!netif_running(dev))
13665 return 0;
13666
7faa006f 13667 flush_scheduled_work();
b02fd9e3 13668 tg3_phy_stop(tp);
1da177e4
LT		 13669 tg3_netif_stop(tp);
13670
13671 del_timer_sync(&tp->timer);
13672
f47c11ee 13673 tg3_full_lock(tp, 1);
1da177e4 13674 tg3_disable_ints(tp);
f47c11ee 13675 tg3_full_unlock(tp);
1da177e4
LT		 13676
13677 netif_device_detach(dev);
13678
f47c11ee 13679 tg3_full_lock(tp, 0);
944d980e 13680 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13681 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13682 tg3_full_unlock(tp);
1da177e4 13683
12dac075
RW		 13684 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13685
13686 err = tg3_set_power_state(tp, target_state);
1da177e4 13687 if (err) {
b02fd9e3
MC		 13688 int err2;
13689
f47c11ee 13690 tg3_full_lock(tp, 0);
1da177e4 13691
6a9eba15 13692 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13693 err2 = tg3_restart_hw(tp, 1);
13694 if (err2)
b9ec6c1b 13695 goto out;
1da177e4
LT		 13696
13697 tp->timer.expires = jiffies + tp->timer_offset;
13698 add_timer(&tp->timer);
13699
13700 netif_device_attach(dev);
13701 tg3_netif_start(tp);
13702
b9ec6c1b 13703out:
f47c11ee 13704 tg3_full_unlock(tp);
b02fd9e3
MC		 13705
13706 if (!err2)
13707 tg3_phy_start(tp);
1da177e4
LT		 13708 }
13709
13710 return err;
13711}
13712
13713static int tg3_resume(struct pci_dev *pdev)
13714{
13715 struct net_device *dev = pci_get_drvdata(pdev);
13716 struct tg3 *tp = netdev_priv(dev);
13717 int err;
13718
3e0c95fd
MC		 13719 pci_restore_state(tp->pdev);
13720
1da177e4
LT		 13721 if (!netif_running(dev))
13722 return 0;
13723
bc1c7567 13724 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13725 if (err)
13726 return err;
13727
13728 netif_device_attach(dev);
13729
f47c11ee 13730 tg3_full_lock(tp, 0);
1da177e4 13731
6a9eba15 13732 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13733 err = tg3_restart_hw(tp, 1);
13734 if (err)
13735 goto out;
1da177e4
LT		 13736
13737 tp->timer.expires = jiffies + tp->timer_offset;
13738 add_timer(&tp->timer);
13739
1da177e4
LT		 13740 tg3_netif_start(tp);
13741
b9ec6c1b 13742out:
f47c11ee 13743 tg3_full_unlock(tp);
1da177e4 13744
b02fd9e3
MC		 13745 if (!err)
13746 tg3_phy_start(tp);
13747
b9ec6c1b 13748 return err;
1da177e4
LT		 13749}
13750
13751static struct pci_driver tg3_driver = {
13752 .name = DRV_MODULE_NAME,
13753 .id_table = tg3_pci_tbl,
13754 .probe = tg3_init_one,
13755 .remove = __devexit_p(tg3_remove_one),
13756 .suspend = tg3_suspend,
13757 .resume = tg3_resume
13758};
13759
13760static int __init tg3_init(void)
13761{
29917620 13762 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13763}
13764
13765static void __exit tg3_cleanup(void)
13766{
13767 pci_unregister_driver(&tg3_driver);
13768}
13769
13770module_init(tg3_init);
13771module_exit(tg3_cleanup);
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