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tg3: Limit CLKREQ fix to A[01] of 57780 asic rev
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
0d2a5068
MC		 71#define DRV_MODULE_VERSION "3.98"
72#define DRV_MODULE_RELDATE "February 25, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
0f893dc6 95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131/* minimum number of free TX descriptors required to wake up TX process */
42952231 132#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 133
ad829268
MC		 134#define TG3_RAW_IP_ALIGN 2
135
1da177e4
LT		 136/* number of ETHTOOL_GSTATS u64's */
137#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
4cafd3f5
MC		 139#define TG3_NUM_TEST 6
140
077f849d
JSR		 141#define FIRMWARE_TG3 "tigon/tg3.bin"
142#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
1da177e4
LT		 145static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150MODULE_LICENSE("GPL");
151MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 152MODULE_FIRMWARE(FIRMWARE_TG3);
153MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
1da177e4
LT		 156
157static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158module_param(tg3_debug, int, 0);
159MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
57e6983c 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
321d32a0
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
13185217
HK		 227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
1da177e4
LT		 235};
236
237MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
50da859d 239static const struct {
1da177e4
LT		 240 const char string[ETH_GSTRING_LEN];
241} ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318};
319
50da859d 320static const struct {
4cafd3f5
MC		 321 const char string[ETH_GSTRING_LEN];
322} ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329};
330
b401e9e2
MC		 331static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332{
333 writel(val, tp->regs + off);
334}
335
336static u32 tg3_read32(struct tg3 *tp, u32 off)
337{
6aa20a22 338 return (readl(tp->regs + off));
b401e9e2
MC		 339}
340
0d3031d9
MC		 341static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342{
343 writel(val, tp->aperegs + off);
344}
345
346static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347{
348 return (readl(tp->aperegs + off));
349}
350
1da177e4
LT		 351static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352{
6892914f
MC		 353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 359}
360
361static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
1da177e4
LT		 365}
366
6892914f 367static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 368{
6892914f
MC		 369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377}
378
379static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380{
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
1da177e4 392 }
6892914f
MC		 393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407}
408
409static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410{
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419}
420
b401e9e2
MC		 421/* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 427{
b401e9e2
MC		 428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
1da177e4
LT		 444}
445
09ee929c
MC		 446static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447{
448 tp->write32_mbox(tp, off, val);
6892914f
MC		 449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
09ee929c
MC		 452}
453
20094930 454static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 455{
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462}
463
b5d3772c
MC		 464static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465{
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467}
468
469static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470{
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472}
473
20094930 474#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 475#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 476#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 478#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 479
480#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 481#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 483#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 484
485static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486{
6892914f
MC		 487 unsigned long flags;
488
b5d3772c
MC		 489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
6892914f 493 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 497
bbadf503
MC		 498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 503
bbadf503
MC		 504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 508}
509
1da177e4
LT		 510static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511{
6892914f
MC		 512 unsigned long flags;
513
b5d3772c
MC		 514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
6892914f 520 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 524
bbadf503
MC		 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
6892914f 534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 535}
536
0d3031d9
MC		 537static void tg3_ape_lock_init(struct tg3 *tp)
538{
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545}
546
547static int tg3_ape_lock(struct tg3 *tp, int locknum)
548{
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
77b483f1 557 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585}
586
587static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588{
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
77b483f1 595 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604}
605
1da177e4
LT		 606static void tg3_disable_ints(struct tg3 *tp)
607{
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 611}
612
613static inline void tg3_cond_int(struct tg3 *tp)
614{
38f3843e
MC		 615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 621}
622
623static void tg3_enable_ints(struct tg3 *tp)
624{
bbe832c0
MC		 625 tp->irq_sync = 0;
626 wmb();
627
1da177e4
LT		 628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
fcfa0a32
MC		 632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
1da177e4
LT		 635 tg3_cond_int(tp);
636}
637
04237ddd
MC		 638static inline unsigned int tg3_has_work(struct tg3 *tp)
639{
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656}
657
1da177e4 658/* tg3_restart_ints
04237ddd
MC		 659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
6aa20a22 661 * which reenables interrupts
1da177e4
LT		 662 */
663static void tg3_restart_ints(struct tg3 *tp)
664{
fac9b83e
DM		 665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
1da177e4
LT		 667 mmiowb();
668
fac9b83e
DM		 669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
04237ddd
MC		 675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 677}
678
679static inline void tg3_netif_stop(struct tg3 *tp)
680{
bbe832c0 681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 682 napi_disable(&tp->napi);
1da177e4
LT		 683 netif_tx_disable(tp->dev);
684}
685
686static inline void tg3_netif_start(struct tg3 *tp)
687{
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
bea3348e 693 napi_enable(&tp->napi);
f47c11ee
DM		 694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
1da177e4
LT		 696}
697
698static void tg3_switch_clocks(struct tg3 *tp)
699{
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
795d01c5
MC		 703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 705 return;
706
1da177e4
LT		 707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
1da177e4 726 }
b401e9e2 727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 728}
729
730#define PHY_BUSY_LOOPS 5000
731
732static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733{
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 751
1da177e4
LT		 752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779}
780
781static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782{
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
b5d3772c
MC		 787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
1da177e4
LT		 791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 803
1da177e4
LT		 804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828}
829
95e2869a
MC		 830static int tg3_bmcr_reset(struct tg3 *tp)
831{
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
d4675b52 855 if (limit < 0)
95e2869a
MC		 856 return -EBUSY;
857
858 return 0;
859}
860
158d7abd
MC		 861static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862{
3d16543d 863 struct tg3 *tp = bp->priv;
158d7abd
MC		 864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873}
874
875static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876{
3d16543d 877 struct tg3 *tp = bp->priv;
158d7abd
MC		 878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886}
887
888static int tg3_mdio_reset(struct mii_bus *bp)
889{
890 return 0;
891}
892
9c61d6bc 893static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 894{
895 u32 val;
fcb389df 896 struct phy_device *phydev;
a9daf367 897
fcb389df
MC		 898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
a9daf367 913 return;
fcb389df
MC		 914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
a9daf367
MC		 935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
a9daf367
MC		 946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
fcb389df 954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966}
967
158d7abd
MC		 968static void tg3_mdio_start(struct tg3 *tp)
969{
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 971 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 973 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
a9daf367 979
9c61d6bc
MC		 980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
158d7abd
MC		 983}
984
985static void tg3_mdio_stop(struct tg3 *tp)
986{
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 988 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 990 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 991 }
992}
993
994static int tg3_mdio_init(struct tg3 *tp)
995{
996 int i;
997 u32 reg;
a9daf367 998 struct phy_device *phydev;
158d7abd
MC		 999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
298cf9be
LB		 1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
158d7abd 1009
298cf9be
LB		 1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1022 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
298cf9be 1032 i = mdiobus_register(tp->mdio_bus);
a9daf367 1033 if (i) {
158d7abd
MC		 1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
9c61d6bc 1036 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1037 return i;
1038 }
158d7abd 1039
298cf9be 1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1041
9c61d6bc
MC		 1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
a9daf367 1053 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1063 break;
fcb389df 1064 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
9c61d6bc
MC		 1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
a9daf367
MC		 1074
1075 return 0;
158d7abd
MC		 1076}
1077
1078static void tg3_mdio_fini(struct tg3 *tp)
1079{
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086}
1087
4ba526ce
MC		 1088/* tp->lock is held. */
1089static inline void tg3_generate_fw_event(struct tg3 *tp)
1090{
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098}
1099
1100#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
95e2869a
MC		 1102/* tp->lock is held. */
1103static void tg3_wait_for_event_ack(struct tg3 *tp)
1104{
1105 int i;
4ba526ce
MC		 1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1121
4ba526ce 1122 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
4ba526ce 1125 udelay(8);
95e2869a
MC		 1126 }
1127}
1128
1129/* tp->lock is held. */
1130static void tg3_ump_link_report(struct tg3 *tp)
1131{
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
4ba526ce 1174 tg3_generate_fw_event(tp);
95e2869a
MC		 1175}
1176
1177static void tg3_link_report(struct tg3 *tp)
1178{
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
e18ce346 1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1198 "on" : "off",
e18ce346 1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203}
1204
1205static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206{
1207 u16 miireg;
1208
e18ce346 1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1210 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1211 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1212 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1213 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219}
1220
1221static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
95e2869a
MC		 1237static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238{
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1246 cap = FLOW_CTRL_RX;
95e2869a
MC		 1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1253 cap = FLOW_CTRL_TX;
95e2869a
MC		 1254 }
1255
1256 return cap;
1257}
1258
f51f3562 1259static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1260{
b02fd9e3 1261 u8 autoneg;
f51f3562 1262 u8 flowctrl = 0;
95e2869a
MC		 1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
b02fd9e3 1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1275 else
bc02ff95 1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1277 } else
1278 flowctrl = tp->link_config.flowctrl;
95e2869a 1279
f51f3562 1280 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1281
e18ce346 1282 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
f51f3562 1287 if (old_rx_mode != tp->rx_mode)
95e2869a 1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1289
e18ce346 1290 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
f51f3562 1295 if (old_tx_mode != tp->tx_mode)
95e2869a 1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1297}
1298
b02fd9e3
MC		 1299static void tg3_adjust_link(struct net_device *dev)
1300{
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
298cf9be 1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
fcb389df
MC		 1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
b02fd9e3
MC		 1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378}
1379
1380static int tg3_phy_init(struct tg3 *tp)
1381{
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
298cf9be 1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1391
1392 /* Attach the MAC to the PHY. */
fb28ad35 1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1394 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
b02fd9e3 1400 /* Mask with MAC supported features. */
9c61d6bc
MC		 1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
9c61d6bc
MC		 1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1422
1423 phydev->advertising = phydev->supported;
1424
b02fd9e3
MC		 1425 return 0;
1426}
1427
1428static void tg3_phy_start(struct tg3 *tp)
1429{
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
298cf9be 1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448}
1449
1450static void tg3_phy_stop(struct tg3 *tp)
1451{
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
298cf9be 1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1456}
1457
1458static void tg3_phy_fini(struct tg3 *tp)
1459{
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464}
1465
b2a5c19c
MC		 1466static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467{
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470}
1471
6833c043
MC		 1472static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473{
1474 u32 reg;
1475
a6435f3a
MC		 1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
6833c043
MC		 1478 return;
1479
1480 reg = MII_TG3_MISC_SHDW_WREN |
1481 MII_TG3_MISC_SHDW_SCR5_SEL |
1482 MII_TG3_MISC_SHDW_SCR5_LPED |
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484 MII_TG3_MISC_SHDW_SCR5_SDTL |
1485 MII_TG3_MISC_SHDW_SCR5_C125OE;
1486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492 reg = MII_TG3_MISC_SHDW_WREN |
1493 MII_TG3_MISC_SHDW_APD_SEL |
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495 if (enable)
1496 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499}
1500
9ef8ca99
MC		 1501static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502{
1503 u32 phy;
1504
1505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507 return;
1508
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510 u32 ephy;
1511
1512 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514 ephy | MII_TG3_EPHY_SHADOW_EN);
1515 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516 if (enable)
1517 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518 else
1519 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521 }
1522 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523 }
1524 } else {
1525 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526 MII_TG3_AUXCTL_SHDWSEL_MISC;
1527 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531 else
1532 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533 phy |= MII_TG3_AUXCTL_MISC_WREN;
1534 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535 }
1536 }
1537}
1538
1da177e4
LT		 1539static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540{
1541 u32 val;
1542
1543 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544 return;
1545
1546 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549 (val | (1 << 15) | (1 << 4)));
1550}
1551
b2a5c19c
MC		 1552static void tg3_phy_apply_otp(struct tg3 *tp)
1553{
1554 u32 otp, phy;
1555
1556 if (!tp->phy_otp)
1557 return;
1558
1559 otp = tp->phy_otp;
1560
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564 MII_TG3_AUXCTL_ACTL_TX_6DB;
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589 /* Turn off SM_DSP clock. */
1590 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591 MII_TG3_AUXCTL_ACTL_TX_6DB;
1592 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593}
1594
1da177e4
LT		 1595static int tg3_wait_macro_done(struct tg3 *tp)
1596{
1597 int limit = 100;
1598
1599 while (limit--) {
1600 u32 tmp32;
1601
1602 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603 if ((tmp32 & 0x1000) == 0)
1604 break;
1605 }
1606 }
d4675b52 1607 if (limit < 0)
1da177e4
LT		 1608 return -EBUSY;
1609
1610 return 0;
1611}
1612
1613static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614{
1615 static const u32 test_pat[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620 };
1621 int chan;
1622
1623 for (chan = 0; chan < 4; chan++) {
1624 int i;
1625
1626 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627 (chan * 0x2000) | 0x0200);
1628 tg3_writephy(tp, 0x16, 0x0002);
1629
1630 for (i = 0; i < 6; i++)
1631 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632 test_pat[chan][i]);
1633
1634 tg3_writephy(tp, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641 (chan * 0x2000) | 0x0200);
1642 tg3_writephy(tp, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp)) {
1644 *resetp = 1;
1645 return -EBUSY;
1646 }
1647
1648 tg3_writephy(tp, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp)) {
1650 *resetp = 1;
1651 return -EBUSY;
1652 }
1653
1654 for (i = 0; i < 6; i += 2) {
1655 u32 low, high;
1656
1657 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659 tg3_wait_macro_done(tp)) {
1660 *resetp = 1;
1661 return -EBUSY;
1662 }
1663 low &= 0x7fff;
1664 high &= 0x000f;
1665 if (low != test_pat[chan][i] ||
1666 high != test_pat[chan][i+1]) {
1667 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671 return -EBUSY;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677}
1678
1679static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680{
1681 int chan;
1682
1683 for (chan = 0; chan < 4; chan++) {
1684 int i;
1685
1686 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687 (chan * 0x2000) | 0x0200);
1688 tg3_writephy(tp, 0x16, 0x0002);
1689 for (i = 0; i < 6; i++)
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691 tg3_writephy(tp, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp))
1693 return -EBUSY;
1694 }
1695
1696 return 0;
1697}
1698
1699static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700{
1701 u32 reg32, phy9_orig;
1702 int retries, do_phy_reset, err;
1703
1704 retries = 10;
1705 do_phy_reset = 1;
1706 do {
1707 if (do_phy_reset) {
1708 err = tg3_bmcr_reset(tp);
1709 if (err)
1710 return err;
1711 do_phy_reset = 0;
1712 }
1713
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716 continue;
1717
1718 reg32 |= 0x3000;
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp, MII_BMCR,
1723 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727 continue;
1728
1729 tg3_writephy(tp, MII_TG3_CTRL,
1730 (MII_TG3_CTRL_AS_MASTER |
1731 MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741 if (!err)
1742 break;
1743 } while (--retries);
1744
1745 err = tg3_phy_reset_chanpat(tp);
1746 if (err)
1747 return err;
1748
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753 tg3_writephy(tp, 0x16, 0x0000);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759 }
1760 else {
1761 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762 }
1763
1764 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767 reg32 &= ~0x3000;
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769 } else if (!err)
1770 err = -EBUSY;
1771
1772 return err;
1773}
1774
1775/* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1777 */
1778static int tg3_phy_reset(struct tg3 *tp)
1779{
b2a5c19c 1780 u32 cpmuctrl;
1da177e4
LT		 1781 u32 phy_status;
1782 int err;
1783
60189ddf
MC		 1784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785 u32 val;
1786
1787 val = tr32(GRC_MISC_CFG);
1788 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789 udelay(40);
1790 }
1da177e4
LT		 1791 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1792 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793 if (err != 0)
1794 return -EBUSY;
1795
c8e1e82b
MC		 1796 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797 netif_carrier_off(tp->dev);
1798 tg3_link_report(tp);
1799 }
1800
1da177e4
LT		 1801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804 err = tg3_phy_reset_5703_4_5(tp);
1805 if (err)
1806 return err;
1807 goto out;
1808 }
1809
b2a5c19c
MC		 1810 cpmuctrl = 0;
1811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815 tw32(TG3_CPMU_CTRL,
1816 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817 }
1818
1da177e4
LT		 1819 err = tg3_bmcr_reset(tp);
1820 if (err)
1821 return err;
1822
b2a5c19c
MC		 1823 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824 u32 phy;
1825
1826 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830 }
1831
bcb37f6c
MC		 1832 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1834 u32 val;
1835
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5) {
1839 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840 udelay(40);
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842 }
1843 }
1844
b2a5c19c
MC		 1845 tg3_phy_apply_otp(tp);
1846
6833c043
MC		 1847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848 tg3_phy_toggle_apd(tp, true);
1849 else
1850 tg3_phy_toggle_apd(tp, false);
1851
1da177e4
LT		 1852out:
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860 }
1861 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 tg3_writephy(tp, 0x1c, 0x8d68);
1864 }
1865 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874 }
c424cb24
MC		 1875 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1878 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880 tg3_writephy(tp, MII_TG3_TEST1,
1881 MII_TG3_TEST1_TRIM_EN | 0x4);
1882 } else
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1884 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885 }
1da177e4
LT		 1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 1891 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1892 u32 phy_reg;
1893
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898 }
1899
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1902 */
0f893dc6 1903 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 1904 u32 phy_reg;
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909 }
1910
715116a1 1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1
MC		 1912 /* adjust output voltage */
1913 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
715116a1
MC		 1914 }
1915
9ef8ca99 1916 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1917 tg3_phy_set_wirespeed(tp);
1918 return 0;
1919}
1920
1921static void tg3_frob_aux_power(struct tg3 *tp)
1922{
1923 struct tg3 *tp_peer = tp;
1924
9d26e213 1925 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1926 return;
1927
8c2dc7e1
MC		 1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930 struct net_device *dev_peer;
1931
1932 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1933 /* remove_one() may have been run on the peer. */
8c2dc7e1 1934 if (!dev_peer)
bc1c7567
MC		 1935 tp_peer = tp;
1936 else
1937 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1938 }
1939
1da177e4 1940 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1941 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1946 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947 (GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1),
1952 100);
8d519ab2
MC		 1953 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1954 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 1955 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1956 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1957 GRC_LCLCTRL_GPIO_OE1 |
1958 GRC_LCLCTRL_GPIO_OE2 |
1959 GRC_LCLCTRL_GPIO_OUTPUT0 |
1960 GRC_LCLCTRL_GPIO_OUTPUT1 |
1961 tp->grc_local_ctrl;
1962 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1963
1964 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1965 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1966
1967 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1968 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 1969 } else {
1970 u32 no_gpio2;
dc56b7d4 1971 u32 grc_local_ctrl = 0;
1da177e4
LT		 1972
1973 if (tp_peer != tp &&
1974 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1975 return;
1976
dc56b7d4
MC		 1977 /* Workaround to prevent overdrawing Amps. */
1978 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1979 ASIC_REV_5714) {
1980 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 1981 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1982 grc_local_ctrl, 100);
dc56b7d4
MC		 1983 }
1984
1da177e4
LT		 1985 /* On 5753 and variants, GPIO2 cannot be used. */
1986 no_gpio2 = tp->nic_sram_data_cfg &
1987 NIC_SRAM_DATA_CFG_NO_GPIO2;
1988
dc56b7d4 1989 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 1990 GRC_LCLCTRL_GPIO_OE1 |
1991 GRC_LCLCTRL_GPIO_OE2 |
1992 GRC_LCLCTRL_GPIO_OUTPUT1 |
1993 GRC_LCLCTRL_GPIO_OUTPUT2;
1994 if (no_gpio2) {
1995 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1996 GRC_LCLCTRL_GPIO_OUTPUT2);
1997 }
b401e9e2
MC		 1998 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1999 grc_local_ctrl, 100);
1da177e4
LT		 2000
2001 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2002
b401e9e2
MC		 2003 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2004 grc_local_ctrl, 100);
1da177e4
LT		 2005
2006 if (!no_gpio2) {
2007 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2008 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2009 grc_local_ctrl, 100);
1da177e4
LT		 2010 }
2011 }
2012 } else {
2013 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2014 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2015 if (tp_peer != tp &&
2016 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017 return;
2018
b401e9e2
MC		 2019 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2020 (GRC_LCLCTRL_GPIO_OE1 |
2021 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2022
b401e9e2
MC		 2023 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2025
b401e9e2
MC		 2026 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2027 (GRC_LCLCTRL_GPIO_OE1 |
2028 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2029 }
2030 }
2031}
2032
e8f3f6ca
MC		 2033static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2034{
2035 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2036 return 1;
2037 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2038 if (speed != SPEED_10)
2039 return 1;
2040 } else if (speed == SPEED_10)
2041 return 1;
2042
2043 return 0;
2044}
2045
1da177e4
LT		 2046static int tg3_setup_phy(struct tg3 *, int);
2047
2048#define RESET_KIND_SHUTDOWN 0
2049#define RESET_KIND_INIT 1
2050#define RESET_KIND_SUSPEND 2
2051
2052static void tg3_write_sig_post_reset(struct tg3 *, int);
2053static int tg3_halt_cpu(struct tg3 *, u32);
2054
0a459aac 2055static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2056{
ce057f01
MC		 2057 u32 val;
2058
5129724a
MC		 2059 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2061 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2062 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2063
2064 sg_dig_ctrl |=
2065 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2066 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2067 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2068 }
3f7045c1 2069 return;
5129724a 2070 }
3f7045c1 2071
60189ddf 2072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2073 tg3_bmcr_reset(tp);
2074 val = tr32(GRC_MISC_CFG);
2075 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2076 udelay(40);
2077 return;
0a459aac 2078 } else if (do_low_power) {
715116a1
MC		 2079 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2080 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2081
2082 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2083 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2084 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2085 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2086 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2087 }
3f7045c1 2088
15c3b696
MC		 2089 /* The PHY should not be powered down on some chips because
2090 * of bugs.
2091 */
2092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2094 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2095 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2096 return;
ce057f01 2097
bcb37f6c
MC		 2098 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2099 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2100 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2101 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2102 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2103 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2104 }
2105
15c3b696
MC		 2106 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2107}
2108
ffbcfed4
MC		 2109/* tp->lock is held. */
2110static int tg3_nvram_lock(struct tg3 *tp)
2111{
2112 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2113 int i;
2114
2115 if (tp->nvram_lock_cnt == 0) {
2116 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2117 for (i = 0; i < 8000; i++) {
2118 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2119 break;
2120 udelay(20);
2121 }
2122 if (i == 8000) {
2123 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2124 return -ENODEV;
2125 }
2126 }
2127 tp->nvram_lock_cnt++;
2128 }
2129 return 0;
2130}
2131
2132/* tp->lock is held. */
2133static void tg3_nvram_unlock(struct tg3 *tp)
2134{
2135 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2136 if (tp->nvram_lock_cnt > 0)
2137 tp->nvram_lock_cnt--;
2138 if (tp->nvram_lock_cnt == 0)
2139 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2140 }
2141}
2142
2143/* tp->lock is held. */
2144static void tg3_enable_nvram_access(struct tg3 *tp)
2145{
2146 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2147 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2148 u32 nvaccess = tr32(NVRAM_ACCESS);
2149
2150 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2151 }
2152}
2153
2154/* tp->lock is held. */
2155static void tg3_disable_nvram_access(struct tg3 *tp)
2156{
2157 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2158 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2159 u32 nvaccess = tr32(NVRAM_ACCESS);
2160
2161 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2162 }
2163}
2164
2165static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2166 u32 offset, u32 *val)
2167{
2168 u32 tmp;
2169 int i;
2170
2171 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2172 return -EINVAL;
2173
2174 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2175 EEPROM_ADDR_DEVID_MASK |
2176 EEPROM_ADDR_READ);
2177 tw32(GRC_EEPROM_ADDR,
2178 tmp |
2179 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2180 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2181 EEPROM_ADDR_ADDR_MASK) |
2182 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2183
2184 for (i = 0; i < 1000; i++) {
2185 tmp = tr32(GRC_EEPROM_ADDR);
2186
2187 if (tmp & EEPROM_ADDR_COMPLETE)
2188 break;
2189 msleep(1);
2190 }
2191 if (!(tmp & EEPROM_ADDR_COMPLETE))
2192 return -EBUSY;
2193
62cedd11
MC		 2194 tmp = tr32(GRC_EEPROM_DATA);
2195
2196 /*
2197 * The data will always be opposite the native endian
2198 * format. Perform a blind byteswap to compensate.
2199 */
2200 *val = swab32(tmp);
2201
ffbcfed4
MC		 2202 return 0;
2203}
2204
2205#define NVRAM_CMD_TIMEOUT 10000
2206
2207static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2208{
2209 int i;
2210
2211 tw32(NVRAM_CMD, nvram_cmd);
2212 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2213 udelay(10);
2214 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2215 udelay(10);
2216 break;
2217 }
2218 }
2219
2220 if (i == NVRAM_CMD_TIMEOUT)
2221 return -EBUSY;
2222
2223 return 0;
2224}
2225
2226static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2227{
2228 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2229 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2230 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2231 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2232 (tp->nvram_jedecnum == JEDEC_ATMEL))
2233
2234 addr = ((addr / tp->nvram_pagesize) <<
2235 ATMEL_AT45DB0X1B_PAGE_POS) +
2236 (addr % tp->nvram_pagesize);
2237
2238 return addr;
2239}
2240
2241static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2242{
2243 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2244 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2245 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2246 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2247 (tp->nvram_jedecnum == JEDEC_ATMEL))
2248
2249 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2250 tp->nvram_pagesize) +
2251 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2252
2253 return addr;
2254}
2255
e4f34110
MC		 2256/* NOTE: Data read in from NVRAM is byteswapped according to
2257 * the byteswapping settings for all other register accesses.
2258 * tg3 devices are BE devices, so on a BE machine, the data
2259 * returned will be exactly as it is seen in NVRAM. On a LE
2260 * machine, the 32-bit value will be byteswapped.
2261 */
ffbcfed4
MC		 2262static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2263{
2264 int ret;
2265
2266 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2267 return tg3_nvram_read_using_eeprom(tp, offset, val);
2268
2269 offset = tg3_nvram_phys_addr(tp, offset);
2270
2271 if (offset > NVRAM_ADDR_MSK)
2272 return -EINVAL;
2273
2274 ret = tg3_nvram_lock(tp);
2275 if (ret)
2276 return ret;
2277
2278 tg3_enable_nvram_access(tp);
2279
2280 tw32(NVRAM_ADDR, offset);
2281 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2282 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2283
2284 if (ret == 0)
e4f34110 2285 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2286
2287 tg3_disable_nvram_access(tp);
2288
2289 tg3_nvram_unlock(tp);
2290
2291 return ret;
2292}
2293
a9dc529d
MC		 2294/* Ensures NVRAM data is in bytestream format. */
2295static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2296{
2297 u32 v;
a9dc529d 2298 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2299 if (!res)
a9dc529d 2300 *val = cpu_to_be32(v);
ffbcfed4
MC		 2301 return res;
2302}
2303
3f007891
MC		 2304/* tp->lock is held. */
2305static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2306{
2307 u32 addr_high, addr_low;
2308 int i;
2309
2310 addr_high = ((tp->dev->dev_addr[0] << 8) |
2311 tp->dev->dev_addr[1]);
2312 addr_low = ((tp->dev->dev_addr[2] << 24) |
2313 (tp->dev->dev_addr[3] << 16) |
2314 (tp->dev->dev_addr[4] << 8) |
2315 (tp->dev->dev_addr[5] << 0));
2316 for (i = 0; i < 4; i++) {
2317 if (i == 1 && skip_mac_1)
2318 continue;
2319 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2320 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2321 }
2322
2323 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2325 for (i = 0; i < 12; i++) {
2326 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2327 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2328 }
2329 }
2330
2331 addr_high = (tp->dev->dev_addr[0] +
2332 tp->dev->dev_addr[1] +
2333 tp->dev->dev_addr[2] +
2334 tp->dev->dev_addr[3] +
2335 tp->dev->dev_addr[4] +
2336 tp->dev->dev_addr[5]) &
2337 TX_BACKOFF_SEED_MASK;
2338 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2339}
2340
bc1c7567 2341static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2342{
2343 u32 misc_host_ctrl;
0a459aac 2344 bool device_should_wake, do_low_power;
1da177e4
LT		 2345
2346 /* Make sure register accesses (indirect or otherwise)
2347 * will function correctly.
2348 */
2349 pci_write_config_dword(tp->pdev,
2350 TG3PCI_MISC_HOST_CTRL,
2351 tp->misc_host_ctrl);
2352
1da177e4 2353 switch (state) {
bc1c7567 2354 case PCI_D0:
12dac075
RW		 2355 pci_enable_wake(tp->pdev, state, false);
2356 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2357
9d26e213
MC		 2358 /* Switch out of Vaux if it is a NIC */
2359 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2360 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2361
2362 return 0;
2363
bc1c7567 2364 case PCI_D1:
bc1c7567 2365 case PCI_D2:
bc1c7567 2366 case PCI_D3hot:
1da177e4
LT		 2367 break;
2368
2369 default:
12dac075
RW		 2370 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2371 tp->dev->name, state);
1da177e4 2372 return -EINVAL;
855e1111 2373 }
5e7dfd0f
MC		 2374
2375 /* Restore the CLKREQ setting. */
2376 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2377 u16 lnkctl;
2378
2379 pci_read_config_word(tp->pdev,
2380 tp->pcie_cap + PCI_EXP_LNKCTL,
2381 &lnkctl);
2382 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2383 pci_write_config_word(tp->pdev,
2384 tp->pcie_cap + PCI_EXP_LNKCTL,
2385 lnkctl);
2386 }
2387
1da177e4
LT		 2388 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2389 tw32(TG3PCI_MISC_HOST_CTRL,
2390 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2391
05ac4cb7
MC		 2392 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2393 device_may_wakeup(&tp->pdev->dev) &&
2394 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2395
dd477003 2396 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2397 do_low_power = false;
b02fd9e3
MC		 2398 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2399 !tp->link_config.phy_is_low_power) {
2400 struct phy_device *phydev;
0a459aac 2401 u32 phyid, advertising;
b02fd9e3 2402
298cf9be 2403 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2404
2405 tp->link_config.phy_is_low_power = 1;
2406
2407 tp->link_config.orig_speed = phydev->speed;
2408 tp->link_config.orig_duplex = phydev->duplex;
2409 tp->link_config.orig_autoneg = phydev->autoneg;
2410 tp->link_config.orig_advertising = phydev->advertising;
2411
2412 advertising = ADVERTISED_TP |
2413 ADVERTISED_Pause |
2414 ADVERTISED_Autoneg |
2415 ADVERTISED_10baseT_Half;
2416
2417 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2418 device_should_wake) {
b02fd9e3
MC		 2419 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2420 advertising |=
2421 ADVERTISED_100baseT_Half |
2422 ADVERTISED_100baseT_Full |
2423 ADVERTISED_10baseT_Full;
2424 else
2425 advertising |= ADVERTISED_10baseT_Full;
2426 }
2427
2428 phydev->advertising = advertising;
2429
2430 phy_start_aneg(phydev);
0a459aac
MC		 2431
2432 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2433 if (phyid != TG3_PHY_ID_BCMAC131) {
2434 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2435 if (phyid == TG3_PHY_OUI_1 ||
2436 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2437 phyid == TG3_PHY_OUI_3)
2438 do_low_power = true;
2439 }
b02fd9e3 2440 }
dd477003 2441 } else {
2023276e 2442 do_low_power = true;
0a459aac 2443
dd477003
MC		 2444 if (tp->link_config.phy_is_low_power == 0) {
2445 tp->link_config.phy_is_low_power = 1;
2446 tp->link_config.orig_speed = tp->link_config.speed;
2447 tp->link_config.orig_duplex = tp->link_config.duplex;
2448 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2449 }
1da177e4 2450
dd477003
MC		 2451 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2452 tp->link_config.speed = SPEED_10;
2453 tp->link_config.duplex = DUPLEX_HALF;
2454 tp->link_config.autoneg = AUTONEG_ENABLE;
2455 tg3_setup_phy(tp, 0);
2456 }
1da177e4
LT		 2457 }
2458
3f007891
MC		 2459 __tg3_set_mac_addr(tp, 0);
2460
b5d3772c
MC		 2461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2462 u32 val;
2463
2464 val = tr32(GRC_VCPU_EXT_CTRL);
2465 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2466 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2467 int i;
2468 u32 val;
2469
2470 for (i = 0; i < 200; i++) {
2471 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2472 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2473 break;
2474 msleep(1);
2475 }
2476 }
a85feb8c
GZ		 2477 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2478 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2479 WOL_DRV_STATE_SHUTDOWN |
2480 WOL_DRV_WOL |
2481 WOL_SET_MAGIC_PKT);
6921d201 2482
05ac4cb7 2483 if (device_should_wake) {
1da177e4
LT		 2484 u32 mac_mode;
2485
2486 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2487 if (do_low_power) {
dd477003
MC		 2488 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2489 udelay(40);
2490 }
1da177e4 2491
3f7045c1
MC		 2492 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2493 mac_mode = MAC_MODE_PORT_MODE_GMII;
2494 else
2495 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2496
e8f3f6ca
MC		 2497 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2498 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2499 ASIC_REV_5700) {
2500 u32 speed = (tp->tg3_flags &
2501 TG3_FLAG_WOL_SPEED_100MB) ?
2502 SPEED_100 : SPEED_10;
2503 if (tg3_5700_link_polarity(tp, speed))
2504 mac_mode |= MAC_MODE_LINK_POLARITY;
2505 else
2506 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2507 }
1da177e4
LT		 2508 } else {
2509 mac_mode = MAC_MODE_PORT_MODE_TBI;
2510 }
2511
cbf46853 2512 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2513 tw32(MAC_LED_CTRL, tp->led_ctrl);
2514
05ac4cb7
MC		 2515 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2516 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2517 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2518 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2519 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2520 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2521
3bda1258
MC		 2522 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2523 mac_mode |= tp->mac_mode &
2524 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2525 if (mac_mode & MAC_MODE_APE_TX_EN)
2526 mac_mode |= MAC_MODE_TDE_ENABLE;
2527 }
2528
1da177e4
LT		 2529 tw32_f(MAC_MODE, mac_mode);
2530 udelay(100);
2531
2532 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2533 udelay(10);
2534 }
2535
2536 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2537 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2538 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2539 u32 base_val;
2540
2541 base_val = tp->pci_clock_ctrl;
2542 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2543 CLOCK_CTRL_TXCLK_DISABLE);
2544
b401e9e2
MC		 2545 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2546 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2547 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2548 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2549 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2550 /* do nothing */
85e94ced 2551 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2552 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2553 u32 newbits1, newbits2;
2554
2555 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2556 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2557 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2558 CLOCK_CTRL_TXCLK_DISABLE |
2559 CLOCK_CTRL_ALTCLK);
2560 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2561 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2562 newbits1 = CLOCK_CTRL_625_CORE;
2563 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2564 } else {
2565 newbits1 = CLOCK_CTRL_ALTCLK;
2566 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2567 }
2568
b401e9e2
MC		 2569 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2570 40);
1da177e4 2571
b401e9e2
MC		 2572 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2573 40);
1da177e4
LT		 2574
2575 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2576 u32 newbits3;
2577
2578 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2580 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2581 CLOCK_CTRL_TXCLK_DISABLE |
2582 CLOCK_CTRL_44MHZ_CORE);
2583 } else {
2584 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2585 }
2586
b401e9e2
MC		 2587 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2588 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2589 }
2590 }
2591
05ac4cb7 2592 if (!(device_should_wake) &&
22435849 2593 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2594 tg3_power_down_phy(tp, do_low_power);
6921d201 2595
1da177e4
LT		 2596 tg3_frob_aux_power(tp);
2597
2598 /* Workaround for unstable PLL clock */
2599 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2600 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2601 u32 val = tr32(0x7d00);
2602
2603 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2604 tw32(0x7d00, val);
6921d201 2605 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2606 int err;
2607
2608 err = tg3_nvram_lock(tp);
1da177e4 2609 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2610 if (!err)
2611 tg3_nvram_unlock(tp);
6921d201 2612 }
1da177e4
LT		 2613 }
2614
bbadf503
MC		 2615 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2616
05ac4cb7 2617 if (device_should_wake)
12dac075
RW		 2618 pci_enable_wake(tp->pdev, state, true);
2619
1da177e4 2620 /* Finally, set the new power state. */
12dac075 2621 pci_set_power_state(tp->pdev, state);
1da177e4 2622
1da177e4
LT		 2623 return 0;
2624}
2625
1da177e4
LT		 2626static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2627{
2628 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2629 case MII_TG3_AUX_STAT_10HALF:
2630 *speed = SPEED_10;
2631 *duplex = DUPLEX_HALF;
2632 break;
2633
2634 case MII_TG3_AUX_STAT_10FULL:
2635 *speed = SPEED_10;
2636 *duplex = DUPLEX_FULL;
2637 break;
2638
2639 case MII_TG3_AUX_STAT_100HALF:
2640 *speed = SPEED_100;
2641 *duplex = DUPLEX_HALF;
2642 break;
2643
2644 case MII_TG3_AUX_STAT_100FULL:
2645 *speed = SPEED_100;
2646 *duplex = DUPLEX_FULL;
2647 break;
2648
2649 case MII_TG3_AUX_STAT_1000HALF:
2650 *speed = SPEED_1000;
2651 *duplex = DUPLEX_HALF;
2652 break;
2653
2654 case MII_TG3_AUX_STAT_1000FULL:
2655 *speed = SPEED_1000;
2656 *duplex = DUPLEX_FULL;
2657 break;
2658
2659 default:
715116a1
MC		 2660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2661 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2662 SPEED_10;
2663 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2664 DUPLEX_HALF;
2665 break;
2666 }
1da177e4
LT		 2667 *speed = SPEED_INVALID;
2668 *duplex = DUPLEX_INVALID;
2669 break;
855e1111 2670 }
1da177e4
LT		 2671}
2672
2673static void tg3_phy_copper_begin(struct tg3 *tp)
2674{
2675 u32 new_adv;
2676 int i;
2677
2678 if (tp->link_config.phy_is_low_power) {
2679 /* Entering low power mode. Disable gigabit and
2680 * 100baseT advertisements.
2681 */
2682 tg3_writephy(tp, MII_TG3_CTRL, 0);
2683
2684 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2685 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2686 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2687 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2688
2689 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2690 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2691 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2692 tp->link_config.advertising &=
2693 ~(ADVERTISED_1000baseT_Half |
2694 ADVERTISED_1000baseT_Full);
2695
ba4d07a8 2696 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2697 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2698 new_adv |= ADVERTISE_10HALF;
2699 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2700 new_adv |= ADVERTISE_10FULL;
2701 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2702 new_adv |= ADVERTISE_100HALF;
2703 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2704 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2705
2706 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2707
1da177e4
LT		 2708 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2709
2710 if (tp->link_config.advertising &
2711 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2712 new_adv = 0;
2713 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2714 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2715 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2716 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2717 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2718 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2719 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2720 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2721 MII_TG3_CTRL_ENABLE_AS_MASTER);
2722 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2723 } else {
2724 tg3_writephy(tp, MII_TG3_CTRL, 0);
2725 }
2726 } else {
ba4d07a8
MC		 2727 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2728 new_adv |= ADVERTISE_CSMA;
2729
1da177e4
LT		 2730 /* Asking for a specific link mode. */
2731 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2732 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2733
2734 if (tp->link_config.duplex == DUPLEX_FULL)
2735 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2736 else
2737 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2738 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2739 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2740 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2741 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2742 } else {
1da177e4
LT		 2743 if (tp->link_config.speed == SPEED_100) {
2744 if (tp->link_config.duplex == DUPLEX_FULL)
2745 new_adv |= ADVERTISE_100FULL;
2746 else
2747 new_adv |= ADVERTISE_100HALF;
2748 } else {
2749 if (tp->link_config.duplex == DUPLEX_FULL)
2750 new_adv |= ADVERTISE_10FULL;
2751 else
2752 new_adv |= ADVERTISE_10HALF;
2753 }
2754 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2755
2756 new_adv = 0;
1da177e4 2757 }
ba4d07a8
MC		 2758
2759 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2760 }
2761
2762 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2763 tp->link_config.speed != SPEED_INVALID) {
2764 u32 bmcr, orig_bmcr;
2765
2766 tp->link_config.active_speed = tp->link_config.speed;
2767 tp->link_config.active_duplex = tp->link_config.duplex;
2768
2769 bmcr = 0;
2770 switch (tp->link_config.speed) {
2771 default:
2772 case SPEED_10:
2773 break;
2774
2775 case SPEED_100:
2776 bmcr |= BMCR_SPEED100;
2777 break;
2778
2779 case SPEED_1000:
2780 bmcr |= TG3_BMCR_SPEED1000;
2781 break;
855e1111 2782 }
1da177e4
LT		 2783
2784 if (tp->link_config.duplex == DUPLEX_FULL)
2785 bmcr |= BMCR_FULLDPLX;
2786
2787 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2788 (bmcr != orig_bmcr)) {
2789 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2790 for (i = 0; i < 1500; i++) {
2791 u32 tmp;
2792
2793 udelay(10);
2794 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2795 tg3_readphy(tp, MII_BMSR, &tmp))
2796 continue;
2797 if (!(tmp & BMSR_LSTATUS)) {
2798 udelay(40);
2799 break;
2800 }
2801 }
2802 tg3_writephy(tp, MII_BMCR, bmcr);
2803 udelay(40);
2804 }
2805 } else {
2806 tg3_writephy(tp, MII_BMCR,
2807 BMCR_ANENABLE | BMCR_ANRESTART);
2808 }
2809}
2810
2811static int tg3_init_5401phy_dsp(struct tg3 *tp)
2812{
2813 int err;
2814
2815 /* Turn off tap power management. */
2816 /* Set Extended packet length bit */
2817 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2818
2819 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2820 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2821
2822 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2823 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2824
2825 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2826 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2827
2828 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2829 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2830
2831 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2832 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2833
2834 udelay(40);
2835
2836 return err;
2837}
2838
3600d918 2839static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2840{
3600d918
MC		 2841 u32 adv_reg, all_mask = 0;
2842
2843 if (mask & ADVERTISED_10baseT_Half)
2844 all_mask |= ADVERTISE_10HALF;
2845 if (mask & ADVERTISED_10baseT_Full)
2846 all_mask |= ADVERTISE_10FULL;
2847 if (mask & ADVERTISED_100baseT_Half)
2848 all_mask |= ADVERTISE_100HALF;
2849 if (mask & ADVERTISED_100baseT_Full)
2850 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2851
2852 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2853 return 0;
2854
1da177e4
LT		 2855 if ((adv_reg & all_mask) != all_mask)
2856 return 0;
2857 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2858 u32 tg3_ctrl;
2859
3600d918
MC		 2860 all_mask = 0;
2861 if (mask & ADVERTISED_1000baseT_Half)
2862 all_mask |= ADVERTISE_1000HALF;
2863 if (mask & ADVERTISED_1000baseT_Full)
2864 all_mask |= ADVERTISE_1000FULL;
2865
1da177e4
LT		 2866 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2867 return 0;
2868
1da177e4
LT		 2869 if ((tg3_ctrl & all_mask) != all_mask)
2870 return 0;
2871 }
2872 return 1;
2873}
2874
ef167e27
MC		 2875static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2876{
2877 u32 curadv, reqadv;
2878
2879 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2880 return 1;
2881
2882 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2883 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2884
2885 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2886 if (curadv != reqadv)
2887 return 0;
2888
2889 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2890 tg3_readphy(tp, MII_LPA, rmtadv);
2891 } else {
2892 /* Reprogram the advertisement register, even if it
2893 * does not affect the current link. If the link
2894 * gets renegotiated in the future, we can save an
2895 * additional renegotiation cycle by advertising
2896 * it correctly in the first place.
2897 */
2898 if (curadv != reqadv) {
2899 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2900 ADVERTISE_PAUSE_ASYM);
2901 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2902 }
2903 }
2904
2905 return 1;
2906}
2907
1da177e4
LT		 2908static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2909{
2910 int current_link_up;
2911 u32 bmsr, dummy;
ef167e27 2912 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2913 u16 current_speed;
2914 u8 current_duplex;
2915 int i, err;
2916
2917 tw32(MAC_EVENT, 0);
2918
2919 tw32_f(MAC_STATUS,
2920 (MAC_STATUS_SYNC_CHANGED |
2921 MAC_STATUS_CFG_CHANGED |
2922 MAC_STATUS_MI_COMPLETION |
2923 MAC_STATUS_LNKSTATE_CHANGED));
2924 udelay(40);
2925
8ef21428
MC		 2926 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2927 tw32_f(MAC_MI_MODE,
2928 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2929 udelay(80);
2930 }
1da177e4
LT		 2931
2932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2933
2934 /* Some third-party PHYs need to be reset on link going
2935 * down.
2936 */
2937 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2940 netif_carrier_ok(tp->dev)) {
2941 tg3_readphy(tp, MII_BMSR, &bmsr);
2942 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2943 !(bmsr & BMSR_LSTATUS))
2944 force_reset = 1;
2945 }
2946 if (force_reset)
2947 tg3_phy_reset(tp);
2948
2949 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2950 tg3_readphy(tp, MII_BMSR, &bmsr);
2951 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2952 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2953 bmsr = 0;
2954
2955 if (!(bmsr & BMSR_LSTATUS)) {
2956 err = tg3_init_5401phy_dsp(tp);
2957 if (err)
2958 return err;
2959
2960 tg3_readphy(tp, MII_BMSR, &bmsr);
2961 for (i = 0; i < 1000; i++) {
2962 udelay(10);
2963 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2964 (bmsr & BMSR_LSTATUS)) {
2965 udelay(40);
2966 break;
2967 }
2968 }
2969
2970 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2971 !(bmsr & BMSR_LSTATUS) &&
2972 tp->link_config.active_speed == SPEED_1000) {
2973 err = tg3_phy_reset(tp);
2974 if (!err)
2975 err = tg3_init_5401phy_dsp(tp);
2976 if (err)
2977 return err;
2978 }
2979 }
2980 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2981 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2982 /* 5701 {A0,B0} CRC bug workaround */
2983 tg3_writephy(tp, 0x15, 0x0a75);
2984 tg3_writephy(tp, 0x1c, 0x8c68);
2985 tg3_writephy(tp, 0x1c, 0x8d68);
2986 tg3_writephy(tp, 0x1c, 0x8c68);
2987 }
2988
2989 /* Clear pending interrupts... */
2990 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2991 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2992
2993 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2994 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
715116a1 2995 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1da177e4
LT		 2996 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2997
2998 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3000 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3001 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3002 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3003 else
3004 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3005 }
3006
3007 current_link_up = 0;
3008 current_speed = SPEED_INVALID;
3009 current_duplex = DUPLEX_INVALID;
3010
3011 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3012 u32 val;
3013
3014 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3015 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3016 if (!(val & (1 << 10))) {
3017 val |= (1 << 10);
3018 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3019 goto relink;
3020 }
3021 }
3022
3023 bmsr = 0;
3024 for (i = 0; i < 100; i++) {
3025 tg3_readphy(tp, MII_BMSR, &bmsr);
3026 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3027 (bmsr & BMSR_LSTATUS))
3028 break;
3029 udelay(40);
3030 }
3031
3032 if (bmsr & BMSR_LSTATUS) {
3033 u32 aux_stat, bmcr;
3034
3035 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3036 for (i = 0; i < 2000; i++) {
3037 udelay(10);
3038 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3039 aux_stat)
3040 break;
3041 }
3042
3043 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3044 &current_speed,
3045 &current_duplex);
3046
3047 bmcr = 0;
3048 for (i = 0; i < 200; i++) {
3049 tg3_readphy(tp, MII_BMCR, &bmcr);
3050 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3051 continue;
3052 if (bmcr && bmcr != 0x7fff)
3053 break;
3054 udelay(10);
3055 }
3056
ef167e27
MC		 3057 lcl_adv = 0;
3058 rmt_adv = 0;
1da177e4 3059
ef167e27
MC		 3060 tp->link_config.active_speed = current_speed;
3061 tp->link_config.active_duplex = current_duplex;
3062
3063 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3064 if ((bmcr & BMCR_ANENABLE) &&
3065 tg3_copper_is_advertising_all(tp,
3066 tp->link_config.advertising)) {
3067 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3068 &rmt_adv))
3069 current_link_up = 1;
1da177e4
LT		 3070 }
3071 } else {
3072 if (!(bmcr & BMCR_ANENABLE) &&
3073 tp->link_config.speed == current_speed &&
ef167e27
MC		 3074 tp->link_config.duplex == current_duplex &&
3075 tp->link_config.flowctrl ==
3076 tp->link_config.active_flowctrl) {
1da177e4 3077 current_link_up = 1;
1da177e4
LT		 3078 }
3079 }
3080
ef167e27
MC		 3081 if (current_link_up == 1 &&
3082 tp->link_config.active_duplex == DUPLEX_FULL)
3083 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3084 }
3085
1da177e4 3086relink:
6921d201 3087 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3088 u32 tmp;
3089
3090 tg3_phy_copper_begin(tp);
3091
3092 tg3_readphy(tp, MII_BMSR, &tmp);
3093 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3094 (tmp & BMSR_LSTATUS))
3095 current_link_up = 1;
3096 }
3097
3098 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3099 if (current_link_up == 1) {
3100 if (tp->link_config.active_speed == SPEED_100 ||
3101 tp->link_config.active_speed == SPEED_10)
3102 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3103 else
3104 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3105 } else
3106 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3107
3108 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3109 if (tp->link_config.active_duplex == DUPLEX_HALF)
3110 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3111
1da177e4 3112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3113 if (current_link_up == 1 &&
3114 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3115 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3116 else
3117 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3118 }
3119
3120 /* ??? Without this setting Netgear GA302T PHY does not
3121 * ??? send/receive packets...
3122 */
3123 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3124 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3125 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3126 tw32_f(MAC_MI_MODE, tp->mi_mode);
3127 udelay(80);
3128 }
3129
3130 tw32_f(MAC_MODE, tp->mac_mode);
3131 udelay(40);
3132
3133 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3134 /* Polled via timer. */
3135 tw32_f(MAC_EVENT, 0);
3136 } else {
3137 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3138 }
3139 udelay(40);
3140
3141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3142 current_link_up == 1 &&
3143 tp->link_config.active_speed == SPEED_1000 &&
3144 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3145 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3146 udelay(120);
3147 tw32_f(MAC_STATUS,
3148 (MAC_STATUS_SYNC_CHANGED |
3149 MAC_STATUS_CFG_CHANGED));
3150 udelay(40);
3151 tg3_write_mem(tp,
3152 NIC_SRAM_FIRMWARE_MBOX,
3153 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3154 }
3155
5e7dfd0f
MC		 3156 /* Prevent send BD corruption. */
3157 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3158 u16 oldlnkctl, newlnkctl;
3159
3160 pci_read_config_word(tp->pdev,
3161 tp->pcie_cap + PCI_EXP_LNKCTL,
3162 &oldlnkctl);
3163 if (tp->link_config.active_speed == SPEED_100 ||
3164 tp->link_config.active_speed == SPEED_10)
3165 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3166 else
3167 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3168 if (newlnkctl != oldlnkctl)
3169 pci_write_config_word(tp->pdev,
3170 tp->pcie_cap + PCI_EXP_LNKCTL,
3171 newlnkctl);
3172 }
3173
1da177e4
LT		 3174 if (current_link_up != netif_carrier_ok(tp->dev)) {
3175 if (current_link_up)
3176 netif_carrier_on(tp->dev);
3177 else
3178 netif_carrier_off(tp->dev);
3179 tg3_link_report(tp);
3180 }
3181
3182 return 0;
3183}
3184
3185struct tg3_fiber_aneginfo {
3186 int state;
3187#define ANEG_STATE_UNKNOWN 0
3188#define ANEG_STATE_AN_ENABLE 1
3189#define ANEG_STATE_RESTART_INIT 2
3190#define ANEG_STATE_RESTART 3
3191#define ANEG_STATE_DISABLE_LINK_OK 4
3192#define ANEG_STATE_ABILITY_DETECT_INIT 5
3193#define ANEG_STATE_ABILITY_DETECT 6
3194#define ANEG_STATE_ACK_DETECT_INIT 7
3195#define ANEG_STATE_ACK_DETECT 8
3196#define ANEG_STATE_COMPLETE_ACK_INIT 9
3197#define ANEG_STATE_COMPLETE_ACK 10
3198#define ANEG_STATE_IDLE_DETECT_INIT 11
3199#define ANEG_STATE_IDLE_DETECT 12
3200#define ANEG_STATE_LINK_OK 13
3201#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3202#define ANEG_STATE_NEXT_PAGE_WAIT 15
3203
3204 u32 flags;
3205#define MR_AN_ENABLE 0x00000001
3206#define MR_RESTART_AN 0x00000002
3207#define MR_AN_COMPLETE 0x00000004
3208#define MR_PAGE_RX 0x00000008
3209#define MR_NP_LOADED 0x00000010
3210#define MR_TOGGLE_TX 0x00000020
3211#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3212#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3213#define MR_LP_ADV_SYM_PAUSE 0x00000100
3214#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3215#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3216#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3217#define MR_LP_ADV_NEXT_PAGE 0x00001000
3218#define MR_TOGGLE_RX 0x00002000
3219#define MR_NP_RX 0x00004000
3220
3221#define MR_LINK_OK 0x80000000
3222
3223 unsigned long link_time, cur_time;
3224
3225 u32 ability_match_cfg;
3226 int ability_match_count;
3227
3228 char ability_match, idle_match, ack_match;
3229
3230 u32 txconfig, rxconfig;
3231#define ANEG_CFG_NP 0x00000080
3232#define ANEG_CFG_ACK 0x00000040
3233#define ANEG_CFG_RF2 0x00000020
3234#define ANEG_CFG_RF1 0x00000010
3235#define ANEG_CFG_PS2 0x00000001
3236#define ANEG_CFG_PS1 0x00008000
3237#define ANEG_CFG_HD 0x00004000
3238#define ANEG_CFG_FD 0x00002000
3239#define ANEG_CFG_INVAL 0x00001f06
3240
3241};
3242#define ANEG_OK 0
3243#define ANEG_DONE 1
3244#define ANEG_TIMER_ENAB 2
3245#define ANEG_FAILED -1
3246
3247#define ANEG_STATE_SETTLE_TIME 10000
3248
3249static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3250 struct tg3_fiber_aneginfo *ap)
3251{
5be73b47 3252 u16 flowctrl;
1da177e4
LT		 3253 unsigned long delta;
3254 u32 rx_cfg_reg;
3255 int ret;
3256
3257 if (ap->state == ANEG_STATE_UNKNOWN) {
3258 ap->rxconfig = 0;
3259 ap->link_time = 0;
3260 ap->cur_time = 0;
3261 ap->ability_match_cfg = 0;
3262 ap->ability_match_count = 0;
3263 ap->ability_match = 0;
3264 ap->idle_match = 0;
3265 ap->ack_match = 0;
3266 }
3267 ap->cur_time++;
3268
3269 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3270 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3271
3272 if (rx_cfg_reg != ap->ability_match_cfg) {
3273 ap->ability_match_cfg = rx_cfg_reg;
3274 ap->ability_match = 0;
3275 ap->ability_match_count = 0;
3276 } else {
3277 if (++ap->ability_match_count > 1) {
3278 ap->ability_match = 1;
3279 ap->ability_match_cfg = rx_cfg_reg;
3280 }
3281 }
3282 if (rx_cfg_reg & ANEG_CFG_ACK)
3283 ap->ack_match = 1;
3284 else
3285 ap->ack_match = 0;
3286
3287 ap->idle_match = 0;
3288 } else {
3289 ap->idle_match = 1;
3290 ap->ability_match_cfg = 0;
3291 ap->ability_match_count = 0;
3292 ap->ability_match = 0;
3293 ap->ack_match = 0;
3294
3295 rx_cfg_reg = 0;
3296 }
3297
3298 ap->rxconfig = rx_cfg_reg;
3299 ret = ANEG_OK;
3300
3301 switch(ap->state) {
3302 case ANEG_STATE_UNKNOWN:
3303 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3304 ap->state = ANEG_STATE_AN_ENABLE;
3305
3306 /* fallthru */
3307 case ANEG_STATE_AN_ENABLE:
3308 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3309 if (ap->flags & MR_AN_ENABLE) {
3310 ap->link_time = 0;
3311 ap->cur_time = 0;
3312 ap->ability_match_cfg = 0;
3313 ap->ability_match_count = 0;
3314 ap->ability_match = 0;
3315 ap->idle_match = 0;
3316 ap->ack_match = 0;
3317
3318 ap->state = ANEG_STATE_RESTART_INIT;
3319 } else {
3320 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3321 }
3322 break;
3323
3324 case ANEG_STATE_RESTART_INIT:
3325 ap->link_time = ap->cur_time;
3326 ap->flags &= ~(MR_NP_LOADED);
3327 ap->txconfig = 0;
3328 tw32(MAC_TX_AUTO_NEG, 0);
3329 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3330 tw32_f(MAC_MODE, tp->mac_mode);
3331 udelay(40);
3332
3333 ret = ANEG_TIMER_ENAB;
3334 ap->state = ANEG_STATE_RESTART;
3335
3336 /* fallthru */
3337 case ANEG_STATE_RESTART:
3338 delta = ap->cur_time - ap->link_time;
3339 if (delta > ANEG_STATE_SETTLE_TIME) {
3340 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3341 } else {
3342 ret = ANEG_TIMER_ENAB;
3343 }
3344 break;
3345
3346 case ANEG_STATE_DISABLE_LINK_OK:
3347 ret = ANEG_DONE;
3348 break;
3349
3350 case ANEG_STATE_ABILITY_DETECT_INIT:
3351 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3352 ap->txconfig = ANEG_CFG_FD;
3353 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3354 if (flowctrl & ADVERTISE_1000XPAUSE)
3355 ap->txconfig |= ANEG_CFG_PS1;
3356 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3357 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3358 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3359 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3360 tw32_f(MAC_MODE, tp->mac_mode);
3361 udelay(40);
3362
3363 ap->state = ANEG_STATE_ABILITY_DETECT;
3364 break;
3365
3366 case ANEG_STATE_ABILITY_DETECT:
3367 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3368 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3369 }
3370 break;
3371
3372 case ANEG_STATE_ACK_DETECT_INIT:
3373 ap->txconfig |= ANEG_CFG_ACK;
3374 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3375 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3376 tw32_f(MAC_MODE, tp->mac_mode);
3377 udelay(40);
3378
3379 ap->state = ANEG_STATE_ACK_DETECT;
3380
3381 /* fallthru */
3382 case ANEG_STATE_ACK_DETECT:
3383 if (ap->ack_match != 0) {
3384 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3385 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3386 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3387 } else {
3388 ap->state = ANEG_STATE_AN_ENABLE;
3389 }
3390 } else if (ap->ability_match != 0 &&
3391 ap->rxconfig == 0) {
3392 ap->state = ANEG_STATE_AN_ENABLE;
3393 }
3394 break;
3395
3396 case ANEG_STATE_COMPLETE_ACK_INIT:
3397 if (ap->rxconfig & ANEG_CFG_INVAL) {
3398 ret = ANEG_FAILED;
3399 break;
3400 }
3401 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3402 MR_LP_ADV_HALF_DUPLEX |
3403 MR_LP_ADV_SYM_PAUSE |
3404 MR_LP_ADV_ASYM_PAUSE |
3405 MR_LP_ADV_REMOTE_FAULT1 |
3406 MR_LP_ADV_REMOTE_FAULT2 |
3407 MR_LP_ADV_NEXT_PAGE |
3408 MR_TOGGLE_RX |
3409 MR_NP_RX);
3410 if (ap->rxconfig & ANEG_CFG_FD)
3411 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3412 if (ap->rxconfig & ANEG_CFG_HD)
3413 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3414 if (ap->rxconfig & ANEG_CFG_PS1)
3415 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3416 if (ap->rxconfig & ANEG_CFG_PS2)
3417 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3418 if (ap->rxconfig & ANEG_CFG_RF1)
3419 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3420 if (ap->rxconfig & ANEG_CFG_RF2)
3421 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3422 if (ap->rxconfig & ANEG_CFG_NP)
3423 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3424
3425 ap->link_time = ap->cur_time;
3426
3427 ap->flags ^= (MR_TOGGLE_TX);
3428 if (ap->rxconfig & 0x0008)
3429 ap->flags |= MR_TOGGLE_RX;
3430 if (ap->rxconfig & ANEG_CFG_NP)
3431 ap->flags |= MR_NP_RX;
3432 ap->flags |= MR_PAGE_RX;
3433
3434 ap->state = ANEG_STATE_COMPLETE_ACK;
3435 ret = ANEG_TIMER_ENAB;
3436 break;
3437
3438 case ANEG_STATE_COMPLETE_ACK:
3439 if (ap->ability_match != 0 &&
3440 ap->rxconfig == 0) {
3441 ap->state = ANEG_STATE_AN_ENABLE;
3442 break;
3443 }
3444 delta = ap->cur_time - ap->link_time;
3445 if (delta > ANEG_STATE_SETTLE_TIME) {
3446 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3447 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3448 } else {
3449 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3450 !(ap->flags & MR_NP_RX)) {
3451 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3452 } else {
3453 ret = ANEG_FAILED;
3454 }
3455 }
3456 }
3457 break;
3458
3459 case ANEG_STATE_IDLE_DETECT_INIT:
3460 ap->link_time = ap->cur_time;
3461 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3462 tw32_f(MAC_MODE, tp->mac_mode);
3463 udelay(40);
3464
3465 ap->state = ANEG_STATE_IDLE_DETECT;
3466 ret = ANEG_TIMER_ENAB;
3467 break;
3468
3469 case ANEG_STATE_IDLE_DETECT:
3470 if (ap->ability_match != 0 &&
3471 ap->rxconfig == 0) {
3472 ap->state = ANEG_STATE_AN_ENABLE;
3473 break;
3474 }
3475 delta = ap->cur_time - ap->link_time;
3476 if (delta > ANEG_STATE_SETTLE_TIME) {
3477 /* XXX another gem from the Broadcom driver :( */
3478 ap->state = ANEG_STATE_LINK_OK;
3479 }
3480 break;
3481
3482 case ANEG_STATE_LINK_OK:
3483 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3484 ret = ANEG_DONE;
3485 break;
3486
3487 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3488 /* ??? unimplemented */
3489 break;
3490
3491 case ANEG_STATE_NEXT_PAGE_WAIT:
3492 /* ??? unimplemented */
3493 break;
3494
3495 default:
3496 ret = ANEG_FAILED;
3497 break;
855e1111 3498 }
1da177e4
LT		 3499
3500 return ret;
3501}
3502
5be73b47 3503static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3504{
3505 int res = 0;
3506 struct tg3_fiber_aneginfo aninfo;
3507 int status = ANEG_FAILED;
3508 unsigned int tick;
3509 u32 tmp;
3510
3511 tw32_f(MAC_TX_AUTO_NEG, 0);
3512
3513 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3514 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3515 udelay(40);
3516
3517 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3518 udelay(40);
3519
3520 memset(&aninfo, 0, sizeof(aninfo));
3521 aninfo.flags |= MR_AN_ENABLE;
3522 aninfo.state = ANEG_STATE_UNKNOWN;
3523 aninfo.cur_time = 0;
3524 tick = 0;
3525 while (++tick < 195000) {
3526 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3527 if (status == ANEG_DONE || status == ANEG_FAILED)
3528 break;
3529
3530 udelay(1);
3531 }
3532
3533 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3534 tw32_f(MAC_MODE, tp->mac_mode);
3535 udelay(40);
3536
5be73b47
MC		 3537 *txflags = aninfo.txconfig;
3538 *rxflags = aninfo.flags;
1da177e4
LT		 3539
3540 if (status == ANEG_DONE &&
3541 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3542 MR_LP_ADV_FULL_DUPLEX)))
3543 res = 1;
3544
3545 return res;
3546}
3547
3548static void tg3_init_bcm8002(struct tg3 *tp)
3549{
3550 u32 mac_status = tr32(MAC_STATUS);
3551 int i;
3552
3553 /* Reset when initting first time or we have a link. */
3554 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3555 !(mac_status & MAC_STATUS_PCS_SYNCED))
3556 return;
3557
3558 /* Set PLL lock range. */
3559 tg3_writephy(tp, 0x16, 0x8007);
3560
3561 /* SW reset */
3562 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3563
3564 /* Wait for reset to complete. */
3565 /* XXX schedule_timeout() ... */
3566 for (i = 0; i < 500; i++)
3567 udelay(10);
3568
3569 /* Config mode; select PMA/Ch 1 regs. */
3570 tg3_writephy(tp, 0x10, 0x8411);
3571
3572 /* Enable auto-lock and comdet, select txclk for tx. */
3573 tg3_writephy(tp, 0x11, 0x0a10);
3574
3575 tg3_writephy(tp, 0x18, 0x00a0);
3576 tg3_writephy(tp, 0x16, 0x41ff);
3577
3578 /* Assert and deassert POR. */
3579 tg3_writephy(tp, 0x13, 0x0400);
3580 udelay(40);
3581 tg3_writephy(tp, 0x13, 0x0000);
3582
3583 tg3_writephy(tp, 0x11, 0x0a50);
3584 udelay(40);
3585 tg3_writephy(tp, 0x11, 0x0a10);
3586
3587 /* Wait for signal to stabilize */
3588 /* XXX schedule_timeout() ... */
3589 for (i = 0; i < 15000; i++)
3590 udelay(10);
3591
3592 /* Deselect the channel register so we can read the PHYID
3593 * later.
3594 */
3595 tg3_writephy(tp, 0x10, 0x8011);
3596}
3597
3598static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3599{
82cd3d11 3600 u16 flowctrl;
1da177e4
LT		 3601 u32 sg_dig_ctrl, sg_dig_status;
3602 u32 serdes_cfg, expected_sg_dig_ctrl;
3603 int workaround, port_a;
3604 int current_link_up;
3605
3606 serdes_cfg = 0;
3607 expected_sg_dig_ctrl = 0;
3608 workaround = 0;
3609 port_a = 1;
3610 current_link_up = 0;
3611
3612 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3613 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3614 workaround = 1;
3615 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3616 port_a = 0;
3617
3618 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3619 /* preserve bits 20-23 for voltage regulator */
3620 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3621 }
3622
3623 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3624
3625 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3626 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3627 if (workaround) {
3628 u32 val = serdes_cfg;
3629
3630 if (port_a)
3631 val |= 0xc010000;
3632 else
3633 val |= 0x4010000;
3634 tw32_f(MAC_SERDES_CFG, val);
3635 }
c98f6e3b
MC		 3636
3637 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3638 }
3639 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3640 tg3_setup_flow_control(tp, 0, 0);
3641 current_link_up = 1;
3642 }
3643 goto out;
3644 }
3645
3646 /* Want auto-negotiation. */
c98f6e3b 3647 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3648
82cd3d11
MC		 3649 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3650 if (flowctrl & ADVERTISE_1000XPAUSE)
3651 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3652 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3653 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3654
3655 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3656 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3657 tp->serdes_counter &&
3658 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3659 MAC_STATUS_RCVD_CFG)) ==
3660 MAC_STATUS_PCS_SYNCED)) {
3661 tp->serdes_counter--;
3662 current_link_up = 1;
3663 goto out;
3664 }
3665restart_autoneg:
1da177e4
LT		 3666 if (workaround)
3667 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3668 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3669 udelay(5);
3670 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3671
3d3ebe74
MC		 3672 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3673 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3674 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3675 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3676 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3677 mac_status = tr32(MAC_STATUS);
3678
c98f6e3b 3679 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3680 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3681 u32 local_adv = 0, remote_adv = 0;
3682
3683 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3684 local_adv |= ADVERTISE_1000XPAUSE;
3685 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3686 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3687
c98f6e3b 3688 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3689 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3690 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3691 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3692
3693 tg3_setup_flow_control(tp, local_adv, remote_adv);
3694 current_link_up = 1;
3d3ebe74
MC		 3695 tp->serdes_counter = 0;
3696 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3697 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3698 if (tp->serdes_counter)
3699 tp->serdes_counter--;
1da177e4
LT		 3700 else {
3701 if (workaround) {
3702 u32 val = serdes_cfg;
3703
3704 if (port_a)
3705 val |= 0xc010000;
3706 else
3707 val |= 0x4010000;
3708
3709 tw32_f(MAC_SERDES_CFG, val);
3710 }
3711
c98f6e3b 3712 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3713 udelay(40);
3714
3715 /* Link parallel detection - link is up */
3716 /* only if we have PCS_SYNC and not */
3717 /* receiving config code words */
3718 mac_status = tr32(MAC_STATUS);
3719 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3720 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3721 tg3_setup_flow_control(tp, 0, 0);
3722 current_link_up = 1;
3d3ebe74
MC		 3723 tp->tg3_flags2 |=
3724 TG3_FLG2_PARALLEL_DETECT;
3725 tp->serdes_counter =
3726 SERDES_PARALLEL_DET_TIMEOUT;
3727 } else
3728 goto restart_autoneg;
1da177e4
LT		 3729 }
3730 }
3d3ebe74
MC		 3731 } else {
3732 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3733 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3734 }
3735
3736out:
3737 return current_link_up;
3738}
3739
3740static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3741{
3742 int current_link_up = 0;
3743
5cf64b8a 3744 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3745 goto out;
1da177e4
LT		 3746
3747 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3748 u32 txflags, rxflags;
1da177e4 3749 int i;
6aa20a22 3750
5be73b47
MC		 3751 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3752 u32 local_adv = 0, remote_adv = 0;
1da177e4 3753
5be73b47
MC		 3754 if (txflags & ANEG_CFG_PS1)
3755 local_adv |= ADVERTISE_1000XPAUSE;
3756 if (txflags & ANEG_CFG_PS2)
3757 local_adv |= ADVERTISE_1000XPSE_ASYM;
3758
3759 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3760 remote_adv |= LPA_1000XPAUSE;
3761 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3762 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3763
3764 tg3_setup_flow_control(tp, local_adv, remote_adv);
3765
1da177e4
LT		 3766 current_link_up = 1;
3767 }
3768 for (i = 0; i < 30; i++) {
3769 udelay(20);
3770 tw32_f(MAC_STATUS,
3771 (MAC_STATUS_SYNC_CHANGED |
3772 MAC_STATUS_CFG_CHANGED));
3773 udelay(40);
3774 if ((tr32(MAC_STATUS) &
3775 (MAC_STATUS_SYNC_CHANGED |
3776 MAC_STATUS_CFG_CHANGED)) == 0)
3777 break;
3778 }
3779
3780 mac_status = tr32(MAC_STATUS);
3781 if (current_link_up == 0 &&
3782 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3783 !(mac_status & MAC_STATUS_RCVD_CFG))
3784 current_link_up = 1;
3785 } else {
5be73b47
MC		 3786 tg3_setup_flow_control(tp, 0, 0);
3787
1da177e4
LT		 3788 /* Forcing 1000FD link up. */
3789 current_link_up = 1;
1da177e4
LT		 3790
3791 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3792 udelay(40);
e8f3f6ca
MC		 3793
3794 tw32_f(MAC_MODE, tp->mac_mode);
3795 udelay(40);
1da177e4
LT		 3796 }
3797
3798out:
3799 return current_link_up;
3800}
3801
3802static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3803{
3804 u32 orig_pause_cfg;
3805 u16 orig_active_speed;
3806 u8 orig_active_duplex;
3807 u32 mac_status;
3808 int current_link_up;
3809 int i;
3810
8d018621 3811 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3812 orig_active_speed = tp->link_config.active_speed;
3813 orig_active_duplex = tp->link_config.active_duplex;
3814
3815 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3816 netif_carrier_ok(tp->dev) &&
3817 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3818 mac_status = tr32(MAC_STATUS);
3819 mac_status &= (MAC_STATUS_PCS_SYNCED |
3820 MAC_STATUS_SIGNAL_DET |
3821 MAC_STATUS_CFG_CHANGED |
3822 MAC_STATUS_RCVD_CFG);
3823 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3824 MAC_STATUS_SIGNAL_DET)) {
3825 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3826 MAC_STATUS_CFG_CHANGED));
3827 return 0;
3828 }
3829 }
3830
3831 tw32_f(MAC_TX_AUTO_NEG, 0);
3832
3833 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3834 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3835 tw32_f(MAC_MODE, tp->mac_mode);
3836 udelay(40);
3837
3838 if (tp->phy_id == PHY_ID_BCM8002)
3839 tg3_init_bcm8002(tp);
3840
3841 /* Enable link change event even when serdes polling. */
3842 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3843 udelay(40);
3844
3845 current_link_up = 0;
3846 mac_status = tr32(MAC_STATUS);
3847
3848 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3849 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3850 else
3851 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3852
1da177e4
LT		 3853 tp->hw_status->status =
3854 (SD_STATUS_UPDATED |
3855 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3856
3857 for (i = 0; i < 100; i++) {
3858 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3859 MAC_STATUS_CFG_CHANGED));
3860 udelay(5);
3861 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3862 MAC_STATUS_CFG_CHANGED |
3863 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3864 break;
3865 }
3866
3867 mac_status = tr32(MAC_STATUS);
3868 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3869 current_link_up = 0;
3d3ebe74
MC		 3870 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3871 tp->serdes_counter == 0) {
1da177e4
LT		 3872 tw32_f(MAC_MODE, (tp->mac_mode |
3873 MAC_MODE_SEND_CONFIGS));
3874 udelay(1);
3875 tw32_f(MAC_MODE, tp->mac_mode);
3876 }
3877 }
3878
3879 if (current_link_up == 1) {
3880 tp->link_config.active_speed = SPEED_1000;
3881 tp->link_config.active_duplex = DUPLEX_FULL;
3882 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3883 LED_CTRL_LNKLED_OVERRIDE |
3884 LED_CTRL_1000MBPS_ON));
3885 } else {
3886 tp->link_config.active_speed = SPEED_INVALID;
3887 tp->link_config.active_duplex = DUPLEX_INVALID;
3888 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3889 LED_CTRL_LNKLED_OVERRIDE |
3890 LED_CTRL_TRAFFIC_OVERRIDE));
3891 }
3892
3893 if (current_link_up != netif_carrier_ok(tp->dev)) {
3894 if (current_link_up)
3895 netif_carrier_on(tp->dev);
3896 else
3897 netif_carrier_off(tp->dev);
3898 tg3_link_report(tp);
3899 } else {
8d018621 3900 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3901 if (orig_pause_cfg != now_pause_cfg ||
3902 orig_active_speed != tp->link_config.active_speed ||
3903 orig_active_duplex != tp->link_config.active_duplex)
3904 tg3_link_report(tp);
3905 }
3906
3907 return 0;
3908}
3909
747e8f8b
MC		 3910static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3911{
3912 int current_link_up, err = 0;
3913 u32 bmsr, bmcr;
3914 u16 current_speed;
3915 u8 current_duplex;
ef167e27 3916 u32 local_adv, remote_adv;
747e8f8b
MC		 3917
3918 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3919 tw32_f(MAC_MODE, tp->mac_mode);
3920 udelay(40);
3921
3922 tw32(MAC_EVENT, 0);
3923
3924 tw32_f(MAC_STATUS,
3925 (MAC_STATUS_SYNC_CHANGED |
3926 MAC_STATUS_CFG_CHANGED |
3927 MAC_STATUS_MI_COMPLETION |
3928 MAC_STATUS_LNKSTATE_CHANGED));
3929 udelay(40);
3930
3931 if (force_reset)
3932 tg3_phy_reset(tp);
3933
3934 current_link_up = 0;
3935 current_speed = SPEED_INVALID;
3936 current_duplex = DUPLEX_INVALID;
3937
3938 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3939 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3941 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3942 bmsr |= BMSR_LSTATUS;
3943 else
3944 bmsr &= ~BMSR_LSTATUS;
3945 }
747e8f8b
MC		 3946
3947 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3948
3949 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3950 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 3951 /* do nothing, just check for link up at the end */
3952 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3953 u32 adv, new_adv;
3954
3955 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3956 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3957 ADVERTISE_1000XPAUSE |
3958 ADVERTISE_1000XPSE_ASYM |
3959 ADVERTISE_SLCT);
3960
ba4d07a8 3961 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 3962
3963 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3964 new_adv |= ADVERTISE_1000XHALF;
3965 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3966 new_adv |= ADVERTISE_1000XFULL;
3967
3968 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3969 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3970 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3971 tg3_writephy(tp, MII_BMCR, bmcr);
3972
3973 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 3974 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 3975 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3976
3977 return err;
3978 }
3979 } else {
3980 u32 new_bmcr;
3981
3982 bmcr &= ~BMCR_SPEED1000;
3983 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3984
3985 if (tp->link_config.duplex == DUPLEX_FULL)
3986 new_bmcr |= BMCR_FULLDPLX;
3987
3988 if (new_bmcr != bmcr) {
3989 /* BMCR_SPEED1000 is a reserved bit that needs
3990 * to be set on write.
3991 */
3992 new_bmcr |= BMCR_SPEED1000;
3993
3994 /* Force a linkdown */
3995 if (netif_carrier_ok(tp->dev)) {
3996 u32 adv;
3997
3998 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3999 adv &= ~(ADVERTISE_1000XFULL |
4000 ADVERTISE_1000XHALF |
4001 ADVERTISE_SLCT);
4002 tg3_writephy(tp, MII_ADVERTISE, adv);
4003 tg3_writephy(tp, MII_BMCR, bmcr |
4004 BMCR_ANRESTART |
4005 BMCR_ANENABLE);
4006 udelay(10);
4007 netif_carrier_off(tp->dev);
4008 }
4009 tg3_writephy(tp, MII_BMCR, new_bmcr);
4010 bmcr = new_bmcr;
4011 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4012 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4013 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4014 ASIC_REV_5714) {
4015 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4016 bmsr |= BMSR_LSTATUS;
4017 else
4018 bmsr &= ~BMSR_LSTATUS;
4019 }
747e8f8b
MC		 4020 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4021 }
4022 }
4023
4024 if (bmsr & BMSR_LSTATUS) {
4025 current_speed = SPEED_1000;
4026 current_link_up = 1;
4027 if (bmcr & BMCR_FULLDPLX)
4028 current_duplex = DUPLEX_FULL;
4029 else
4030 current_duplex = DUPLEX_HALF;
4031
ef167e27
MC		 4032 local_adv = 0;
4033 remote_adv = 0;
4034
747e8f8b 4035 if (bmcr & BMCR_ANENABLE) {
ef167e27 4036 u32 common;
747e8f8b
MC		 4037
4038 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4039 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4040 common = local_adv & remote_adv;
4041 if (common & (ADVERTISE_1000XHALF |
4042 ADVERTISE_1000XFULL)) {
4043 if (common & ADVERTISE_1000XFULL)
4044 current_duplex = DUPLEX_FULL;
4045 else
4046 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4047 }
4048 else
4049 current_link_up = 0;
4050 }
4051 }
4052
ef167e27
MC		 4053 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4054 tg3_setup_flow_control(tp, local_adv, remote_adv);
4055
747e8f8b
MC		 4056 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4057 if (tp->link_config.active_duplex == DUPLEX_HALF)
4058 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4059
4060 tw32_f(MAC_MODE, tp->mac_mode);
4061 udelay(40);
4062
4063 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4064
4065 tp->link_config.active_speed = current_speed;
4066 tp->link_config.active_duplex = current_duplex;
4067
4068 if (current_link_up != netif_carrier_ok(tp->dev)) {
4069 if (current_link_up)
4070 netif_carrier_on(tp->dev);
4071 else {
4072 netif_carrier_off(tp->dev);
4073 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4074 }
4075 tg3_link_report(tp);
4076 }
4077 return err;
4078}
4079
4080static void tg3_serdes_parallel_detect(struct tg3 *tp)
4081{
3d3ebe74 4082 if (tp->serdes_counter) {
747e8f8b 4083 /* Give autoneg time to complete. */
3d3ebe74 4084 tp->serdes_counter--;
747e8f8b
MC		 4085 return;
4086 }
4087 if (!netif_carrier_ok(tp->dev) &&
4088 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4089 u32 bmcr;
4090
4091 tg3_readphy(tp, MII_BMCR, &bmcr);
4092 if (bmcr & BMCR_ANENABLE) {
4093 u32 phy1, phy2;
4094
4095 /* Select shadow register 0x1f */
4096 tg3_writephy(tp, 0x1c, 0x7c00);
4097 tg3_readphy(tp, 0x1c, &phy1);
4098
4099 /* Select expansion interrupt status register */
4100 tg3_writephy(tp, 0x17, 0x0f01);
4101 tg3_readphy(tp, 0x15, &phy2);
4102 tg3_readphy(tp, 0x15, &phy2);
4103
4104 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4105 /* We have signal detect and not receiving
4106 * config code words, link is up by parallel
4107 * detection.
4108 */
4109
4110 bmcr &= ~BMCR_ANENABLE;
4111 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4112 tg3_writephy(tp, MII_BMCR, bmcr);
4113 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4114 }
4115 }
4116 }
4117 else if (netif_carrier_ok(tp->dev) &&
4118 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4119 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4120 u32 phy2;
4121
4122 /* Select expansion interrupt status register */
4123 tg3_writephy(tp, 0x17, 0x0f01);
4124 tg3_readphy(tp, 0x15, &phy2);
4125 if (phy2 & 0x20) {
4126 u32 bmcr;
4127
4128 /* Config code words received, turn on autoneg. */
4129 tg3_readphy(tp, MII_BMCR, &bmcr);
4130 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4131
4132 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4133
4134 }
4135 }
4136}
4137
1da177e4
LT		 4138static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4139{
4140 int err;
4141
4142 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4143 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4144 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4145 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4146 } else {
4147 err = tg3_setup_copper_phy(tp, force_reset);
4148 }
4149
bcb37f6c 4150 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4151 u32 val, scale;
4152
4153 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4154 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4155 scale = 65;
4156 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4157 scale = 6;
4158 else
4159 scale = 12;
4160
4161 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4162 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4163 tw32(GRC_MISC_CFG, val);
4164 }
4165
1da177e4
LT		 4166 if (tp->link_config.active_speed == SPEED_1000 &&
4167 tp->link_config.active_duplex == DUPLEX_HALF)
4168 tw32(MAC_TX_LENGTHS,
4169 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4170 (6 << TX_LENGTHS_IPG_SHIFT) |
4171 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4172 else
4173 tw32(MAC_TX_LENGTHS,
4174 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4175 (6 << TX_LENGTHS_IPG_SHIFT) |
4176 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4177
4178 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4179 if (netif_carrier_ok(tp->dev)) {
4180 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4181 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4182 } else {
4183 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4184 }
4185 }
4186
8ed5d97e
MC		 4187 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4188 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4189 if (!netif_carrier_ok(tp->dev))
4190 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4191 tp->pwrmgmt_thresh;
4192 else
4193 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4194 tw32(PCIE_PWR_MGMT_THRESH, val);
4195 }
4196
1da177e4
LT		 4197 return err;
4198}
4199
df3e6548
MC		 4200/* This is called whenever we suspect that the system chipset is re-
4201 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4202 * is bogus tx completions. We try to recover by setting the
4203 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4204 * in the workqueue.
4205 */
4206static void tg3_tx_recover(struct tg3 *tp)
4207{
4208 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4209 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4210
4211 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4212 "mapped I/O cycles to the network device, attempting to "
4213 "recover. Please report the problem to the driver maintainer "
4214 "and include system chipset information.\n", tp->dev->name);
4215
4216 spin_lock(&tp->lock);
df3e6548 4217 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4218 spin_unlock(&tp->lock);
4219}
4220
1b2a7205
MC		 4221static inline u32 tg3_tx_avail(struct tg3 *tp)
4222{
4223 smp_mb();
4224 return (tp->tx_pending -
4225 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4226}
4227
1da177e4
LT		 4228/* Tigon3 never reports partial packet sends. So we do not
4229 * need special logic to handle SKBs that have not had all
4230 * of their frags sent yet, like SunGEM does.
4231 */
4232static void tg3_tx(struct tg3 *tp)
4233{
4234 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4235 u32 sw_idx = tp->tx_cons;
4236
4237 while (sw_idx != hw_idx) {
4238 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4239 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4240 int i, tx_bug = 0;
4241
4242 if (unlikely(skb == NULL)) {
4243 tg3_tx_recover(tp);
4244 return;
4245 }
1da177e4 4246
90079ce8 4247 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4248
4249 ri->skb = NULL;
4250
4251 sw_idx = NEXT_TX(sw_idx);
4252
4253 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4254 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4255 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4256 tx_bug = 1;
1da177e4
LT		 4257 sw_idx = NEXT_TX(sw_idx);
4258 }
4259
f47c11ee 4260 dev_kfree_skb(skb);
df3e6548
MC		 4261
4262 if (unlikely(tx_bug)) {
4263 tg3_tx_recover(tp);
4264 return;
4265 }
1da177e4
LT		 4266 }
4267
4268 tp->tx_cons = sw_idx;
4269
1b2a7205
MC		 4270 /* Need to make the tx_cons update visible to tg3_start_xmit()
4271 * before checking for netif_queue_stopped(). Without the
4272 * memory barrier, there is a small possibility that tg3_start_xmit()
4273 * will miss it and cause the queue to be stopped forever.
4274 */
4275 smp_mb();
4276
4277 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4278 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4279 netif_tx_lock(tp->dev);
51b91468 4280 if (netif_queue_stopped(tp->dev) &&
42952231 4281 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4282 netif_wake_queue(tp->dev);
1b2a7205 4283 netif_tx_unlock(tp->dev);
51b91468 4284 }
1da177e4
LT		 4285}
4286
4287/* Returns size of skb allocated or < 0 on error.
4288 *
4289 * We only need to fill in the address because the other members
4290 * of the RX descriptor are invariant, see tg3_init_rings.
4291 *
4292 * Note the purposeful assymetry of cpu vs. chip accesses. For
4293 * posting buffers we only dirty the first cache line of the RX
4294 * descriptor (containing the address). Whereas for the RX status
4295 * buffers the cpu only reads the last cacheline of the RX descriptor
4296 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4297 */
4298static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4299 int src_idx, u32 dest_idx_unmasked)
4300{
4301 struct tg3_rx_buffer_desc *desc;
4302 struct ring_info *map, *src_map;
4303 struct sk_buff *skb;
4304 dma_addr_t mapping;
4305 int skb_size, dest_idx;
4306
4307 src_map = NULL;
4308 switch (opaque_key) {
4309 case RXD_OPAQUE_RING_STD:
4310 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4311 desc = &tp->rx_std[dest_idx];
4312 map = &tp->rx_std_buffers[dest_idx];
4313 if (src_idx >= 0)
4314 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 4315 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 4316 break;
4317
4318 case RXD_OPAQUE_RING_JUMBO:
4319 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4320 desc = &tp->rx_jumbo[dest_idx];
4321 map = &tp->rx_jumbo_buffers[dest_idx];
4322 if (src_idx >= 0)
4323 src_map = &tp->rx_jumbo_buffers[src_idx];
4324 skb_size = RX_JUMBO_PKT_BUF_SZ;
4325 break;
4326
4327 default:
4328 return -EINVAL;
855e1111 4329 }
1da177e4
LT		 4330
4331 /* Do not overwrite any of the map or rp information
4332 * until we are sure we can commit to a new buffer.
4333 *
4334 * Callers depend upon this behavior and assume that
4335 * we leave everything unchanged if we fail.
4336 */
a20e9c62 4337 skb = netdev_alloc_skb(tp->dev, skb_size);
1da177e4
LT		 4338 if (skb == NULL)
4339 return -ENOMEM;
4340
1da177e4
LT		 4341 skb_reserve(skb, tp->rx_offset);
4342
4343 mapping = pci_map_single(tp->pdev, skb->data,
4344 skb_size - tp->rx_offset,
4345 PCI_DMA_FROMDEVICE);
4346
4347 map->skb = skb;
4348 pci_unmap_addr_set(map, mapping, mapping);
4349
4350 if (src_map != NULL)
4351 src_map->skb = NULL;
4352
4353 desc->addr_hi = ((u64)mapping >> 32);
4354 desc->addr_lo = ((u64)mapping & 0xffffffff);
4355
4356 return skb_size;
4357}
4358
4359/* We only need to move over in the address because the other
4360 * members of the RX descriptor are invariant. See notes above
4361 * tg3_alloc_rx_skb for full details.
4362 */
4363static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4364 int src_idx, u32 dest_idx_unmasked)
4365{
4366 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4367 struct ring_info *src_map, *dest_map;
4368 int dest_idx;
4369
4370 switch (opaque_key) {
4371 case RXD_OPAQUE_RING_STD:
4372 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4373 dest_desc = &tp->rx_std[dest_idx];
4374 dest_map = &tp->rx_std_buffers[dest_idx];
4375 src_desc = &tp->rx_std[src_idx];
4376 src_map = &tp->rx_std_buffers[src_idx];
4377 break;
4378
4379 case RXD_OPAQUE_RING_JUMBO:
4380 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4381 dest_desc = &tp->rx_jumbo[dest_idx];
4382 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4383 src_desc = &tp->rx_jumbo[src_idx];
4384 src_map = &tp->rx_jumbo_buffers[src_idx];
4385 break;
4386
4387 default:
4388 return;
855e1111 4389 }
1da177e4
LT		 4390
4391 dest_map->skb = src_map->skb;
4392 pci_unmap_addr_set(dest_map, mapping,
4393 pci_unmap_addr(src_map, mapping));
4394 dest_desc->addr_hi = src_desc->addr_hi;
4395 dest_desc->addr_lo = src_desc->addr_lo;
4396
4397 src_map->skb = NULL;
4398}
4399
4400#if TG3_VLAN_TAG_USED
4401static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4402{
1383bdb9 4403 return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
1da177e4
LT		 4404}
4405#endif
4406
4407/* The RX ring scheme is composed of multiple rings which post fresh
4408 * buffers to the chip, and one special ring the chip uses to report
4409 * status back to the host.
4410 *
4411 * The special ring reports the status of received packets to the
4412 * host. The chip does not write into the original descriptor the
4413 * RX buffer was obtained from. The chip simply takes the original
4414 * descriptor as provided by the host, updates the status and length
4415 * field, then writes this into the next status ring entry.
4416 *
4417 * Each ring the host uses to post buffers to the chip is described
4418 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4419 * it is first placed into the on-chip ram. When the packet's length
4420 * is known, it walks down the TG3_BDINFO entries to select the ring.
4421 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4422 * which is within the range of the new packet's length is chosen.
4423 *
4424 * The "separate ring for rx status" scheme may sound queer, but it makes
4425 * sense from a cache coherency perspective. If only the host writes
4426 * to the buffer post rings, and only the chip writes to the rx status
4427 * rings, then cache lines never move beyond shared-modified state.
4428 * If both the host and chip were to write into the same ring, cache line
4429 * eviction could occur since both entities want it in an exclusive state.
4430 */
4431static int tg3_rx(struct tg3 *tp, int budget)
4432{
f92905de 4433 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4434 u32 sw_idx = tp->rx_rcb_ptr;
4435 u16 hw_idx;
1da177e4
LT		 4436 int received;
4437
4438 hw_idx = tp->hw_status->idx[0].rx_producer;
4439 /*
4440 * We need to order the read of hw_idx and the read of
4441 * the opaque cookie.
4442 */
4443 rmb();
1da177e4
LT		 4444 work_mask = 0;
4445 received = 0;
4446 while (sw_idx != hw_idx && budget > 0) {
4447 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4448 unsigned int len;
4449 struct sk_buff *skb;
4450 dma_addr_t dma_addr;
4451 u32 opaque_key, desc_idx, *post_ptr;
4452
4453 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4454 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4455 if (opaque_key == RXD_OPAQUE_RING_STD) {
4456 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4457 mapping);
4458 skb = tp->rx_std_buffers[desc_idx].skb;
4459 post_ptr = &tp->rx_std_ptr;
f92905de 4460 rx_std_posted++;
1da177e4
LT		 4461 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4462 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4463 mapping);
4464 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4465 post_ptr = &tp->rx_jumbo_ptr;
4466 }
4467 else {
4468 goto next_pkt_nopost;
4469 }
4470
4471 work_mask |= opaque_key;
4472
4473 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4474 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4475 drop_it:
4476 tg3_recycle_rx(tp, opaque_key,
4477 desc_idx, *post_ptr);
4478 drop_it_no_recycle:
4479 /* Other statistics kept track of by card. */
4480 tp->net_stats.rx_dropped++;
4481 goto next_pkt;
4482 }
4483
ad829268
MC		 4484 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4485 ETH_FCS_LEN;
1da177e4 4486
6aa20a22 4487 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4488 && tp->rx_offset == NET_IP_ALIGN
4489 /* rx_offset will likely not equal NET_IP_ALIGN
4490 * if this is a 5701 card running in PCI-X mode
4491 * [see tg3_get_invariants()]
4492 */
1da177e4
LT		 4493 ) {
4494 int skb_size;
4495
4496 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4497 desc_idx, *post_ptr);
4498 if (skb_size < 0)
4499 goto drop_it;
4500
4501 pci_unmap_single(tp->pdev, dma_addr,
4502 skb_size - tp->rx_offset,
4503 PCI_DMA_FROMDEVICE);
4504
4505 skb_put(skb, len);
4506 } else {
4507 struct sk_buff *copy_skb;
4508
4509 tg3_recycle_rx(tp, opaque_key,
4510 desc_idx, *post_ptr);
4511
ad829268
MC		 4512 copy_skb = netdev_alloc_skb(tp->dev,
4513 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4514 if (copy_skb == NULL)
4515 goto drop_it_no_recycle;
4516
ad829268 4517 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4518 skb_put(copy_skb, len);
4519 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4520 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4521 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4522
4523 /* We'll reuse the original ring buffer. */
4524 skb = copy_skb;
4525 }
4526
4527 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4528 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4529 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4530 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4531 skb->ip_summed = CHECKSUM_UNNECESSARY;
4532 else
4533 skb->ip_summed = CHECKSUM_NONE;
4534
4535 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4536
4537 if (len > (tp->dev->mtu + ETH_HLEN) &&
4538 skb->protocol != htons(ETH_P_8021Q)) {
4539 dev_kfree_skb(skb);
4540 goto next_pkt;
4541 }
4542
1da177e4
LT		 4543#if TG3_VLAN_TAG_USED
4544 if (tp->vlgrp != NULL &&
4545 desc->type_flags & RXD_FLAG_VLAN) {
4546 tg3_vlan_rx(tp, skb,
4547 desc->err_vlan & RXD_VLAN_MASK);
4548 } else
4549#endif
1383bdb9 4550 napi_gro_receive(&tp->napi, skb);
1da177e4 4551
1da177e4
LT		 4552 received++;
4553 budget--;
4554
4555next_pkt:
4556 (*post_ptr)++;
f92905de
MC		 4557
4558 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4559 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4560
4561 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4562 TG3_64BIT_REG_LOW, idx);
4563 work_mask &= ~RXD_OPAQUE_RING_STD;
4564 rx_std_posted = 0;
4565 }
1da177e4 4566next_pkt_nopost:
483ba50b 4567 sw_idx++;
6b31a515 4568 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4569
4570 /* Refresh hw_idx to see if there is new work */
4571 if (sw_idx == hw_idx) {
4572 hw_idx = tp->hw_status->idx[0].rx_producer;
4573 rmb();
4574 }
1da177e4
LT		 4575 }
4576
4577 /* ACK the status ring. */
483ba50b
MC		 4578 tp->rx_rcb_ptr = sw_idx;
4579 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4580
4581 /* Refill RX ring(s). */
4582 if (work_mask & RXD_OPAQUE_RING_STD) {
4583 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4584 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4585 sw_idx);
4586 }
4587 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4588 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4589 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4590 sw_idx);
4591 }
4592 mmiowb();
4593
4594 return received;
4595}
4596
6f535763 4597static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4598{
1da177e4 4599 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4600
1da177e4
LT		 4601 /* handle link change and other phy events */
4602 if (!(tp->tg3_flags &
4603 (TG3_FLAG_USE_LINKCHG_REG |
4604 TG3_FLAG_POLL_SERDES))) {
4605 if (sblk->status & SD_STATUS_LINK_CHG) {
4606 sblk->status = SD_STATUS_UPDATED |
4607 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4608 spin_lock(&tp->lock);
dd477003
MC		 4609 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4610 tw32_f(MAC_STATUS,
4611 (MAC_STATUS_SYNC_CHANGED |
4612 MAC_STATUS_CFG_CHANGED |
4613 MAC_STATUS_MI_COMPLETION |
4614 MAC_STATUS_LNKSTATE_CHANGED));
4615 udelay(40);
4616 } else
4617 tg3_setup_phy(tp, 0);
f47c11ee 4618 spin_unlock(&tp->lock);
1da177e4
LT		 4619 }
4620 }
4621
4622 /* run TX completion thread */
4623 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4624 tg3_tx(tp);
6f535763 4625 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4626 return work_done;
1da177e4
LT		 4627 }
4628
1da177e4
LT		 4629 /* run RX thread, within the bounds set by NAPI.
4630 * All RX "locking" is done by ensuring outside
bea3348e 4631 * code synchronizes with tg3->napi.poll()
1da177e4 4632 */
bea3348e 4633 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4634 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4635
6f535763
DM		 4636 return work_done;
4637}
4638
4639static int tg3_poll(struct napi_struct *napi, int budget)
4640{
4641 struct tg3 *tp = container_of(napi, struct tg3, napi);
4642 int work_done = 0;
4fd7ab59 4643 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4644
4645 while (1) {
4646 work_done = tg3_poll_work(tp, work_done, budget);
4647
4648 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4649 goto tx_recovery;
4650
4651 if (unlikely(work_done >= budget))
4652 break;
4653
4fd7ab59
MC		 4654 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4655 /* tp->last_tag is used in tg3_restart_ints() below
4656 * to tell the hw how much work has been processed,
4657 * so we must read it before checking for more work.
4658 */
4659 tp->last_tag = sblk->status_tag;
624f8e50 4660 tp->last_irq_tag = tp->last_tag;
4fd7ab59
MC		 4661 rmb();
4662 } else
4663 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4664
4fd7ab59 4665 if (likely(!tg3_has_work(tp))) {
288379f0 4666 napi_complete(napi);
6f535763
DM		 4667 tg3_restart_ints(tp);
4668 break;
4669 }
1da177e4
LT		 4670 }
4671
bea3348e 4672 return work_done;
6f535763
DM		 4673
4674tx_recovery:
4fd7ab59 4675 /* work_done is guaranteed to be less than budget. */
288379f0 4676 napi_complete(napi);
6f535763 4677 schedule_work(&tp->reset_task);
4fd7ab59 4678 return work_done;
1da177e4
LT		 4679}
4680
f47c11ee
DM		 4681static void tg3_irq_quiesce(struct tg3 *tp)
4682{
4683 BUG_ON(tp->irq_sync);
4684
4685 tp->irq_sync = 1;
4686 smp_mb();
4687
4688 synchronize_irq(tp->pdev->irq);
4689}
4690
4691static inline int tg3_irq_sync(struct tg3 *tp)
4692{
4693 return tp->irq_sync;
4694}
4695
4696/* Fully shutdown all tg3 driver activity elsewhere in the system.
4697 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4698 * with as well. Most of the time, this is not necessary except when
4699 * shutting down the device.
4700 */
4701static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4702{
46966545 4703 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4704 if (irq_sync)
4705 tg3_irq_quiesce(tp);
f47c11ee
DM		 4706}
4707
4708static inline void tg3_full_unlock(struct tg3 *tp)
4709{
f47c11ee
DM		 4710 spin_unlock_bh(&tp->lock);
4711}
4712
fcfa0a32
MC		 4713/* One-shot MSI handler - Chip automatically disables interrupt
4714 * after sending MSI so driver doesn't have to do it.
4715 */
7d12e780 4716static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4717{
4718 struct net_device *dev = dev_id;
4719 struct tg3 *tp = netdev_priv(dev);
4720
4721 prefetch(tp->hw_status);
4722 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4723
4724 if (likely(!tg3_irq_sync(tp)))
288379f0 4725 napi_schedule(&tp->napi);
fcfa0a32
MC		 4726
4727 return IRQ_HANDLED;
4728}
4729
88b06bc2
MC		 4730/* MSI ISR - No need to check for interrupt sharing and no need to
4731 * flush status block and interrupt mailbox. PCI ordering rules
4732 * guarantee that MSI will arrive after the status block.
4733 */
7d12e780 4734static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4735{
4736 struct net_device *dev = dev_id;
4737 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4738
61487480
MC		 4739 prefetch(tp->hw_status);
4740 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4741 /*
fac9b83e 4742 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4743 * chip-internal interrupt pending events.
fac9b83e 4744 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4745 * NIC to stop sending us irqs, engaging "in-intr-handler"
4746 * event coalescing.
4747 */
4748 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4749 if (likely(!tg3_irq_sync(tp)))
288379f0 4750 napi_schedule(&tp->napi);
61487480 4751
88b06bc2
MC		 4752 return IRQ_RETVAL(1);
4753}
4754
7d12e780 4755static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4756{
4757 struct net_device *dev = dev_id;
4758 struct tg3 *tp = netdev_priv(dev);
4759 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4760 unsigned int handled = 1;
4761
1da177e4
LT		 4762 /* In INTx mode, it is possible for the interrupt to arrive at
4763 * the CPU before the status block posted prior to the interrupt.
4764 * Reading the PCI State register will confirm whether the
4765 * interrupt is ours and will flush the status block.
4766 */
d18edcb2
MC		 4767 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4768 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4769 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4770 handled = 0;
f47c11ee 4771 goto out;
fac9b83e 4772 }
d18edcb2
MC		 4773 }
4774
4775 /*
4776 * Writing any value to intr-mbox-0 clears PCI INTA# and
4777 * chip-internal interrupt pending events.
4778 * Writing non-zero to intr-mbox-0 additional tells the
4779 * NIC to stop sending us irqs, engaging "in-intr-handler"
4780 * event coalescing.
c04cb347
MC		 4781 *
4782 * Flush the mailbox to de-assert the IRQ immediately to prevent
4783 * spurious interrupts. The flush impacts performance but
4784 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4785 */
c04cb347 4786 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4787 if (tg3_irq_sync(tp))
4788 goto out;
4789 sblk->status &= ~SD_STATUS_UPDATED;
4790 if (likely(tg3_has_work(tp))) {
4791 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4792 napi_schedule(&tp->napi);
d18edcb2
MC		 4793 } else {
4794 /* No work, shared interrupt perhaps? re-enable
4795 * interrupts, and flush that PCI write
4796 */
4797 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4798 0x00000000);
fac9b83e 4799 }
f47c11ee 4800out:
fac9b83e
DM		 4801 return IRQ_RETVAL(handled);
4802}
4803
7d12e780 4804static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4805{
4806 struct net_device *dev = dev_id;
4807 struct tg3 *tp = netdev_priv(dev);
4808 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4809 unsigned int handled = 1;
4810
fac9b83e
DM		 4811 /* In INTx mode, it is possible for the interrupt to arrive at
4812 * the CPU before the status block posted prior to the interrupt.
4813 * Reading the PCI State register will confirm whether the
4814 * interrupt is ours and will flush the status block.
4815 */
624f8e50 4816 if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
d18edcb2
MC		 4817 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4818 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4819 handled = 0;
f47c11ee 4820 goto out;
1da177e4 4821 }
d18edcb2
MC		 4822 }
4823
4824 /*
4825 * writing any value to intr-mbox-0 clears PCI INTA# and
4826 * chip-internal interrupt pending events.
4827 * writing non-zero to intr-mbox-0 additional tells the
4828 * NIC to stop sending us irqs, engaging "in-intr-handler"
4829 * event coalescing.
c04cb347
MC		 4830 *
4831 * Flush the mailbox to de-assert the IRQ immediately to prevent
4832 * spurious interrupts. The flush impacts performance but
4833 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4834 */
c04cb347 4835 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4836
4837 /*
4838 * In a shared interrupt configuration, sometimes other devices'
4839 * interrupts will scream. We record the current status tag here
4840 * so that the above check can report that the screaming interrupts
4841 * are unhandled. Eventually they will be silenced.
4842 */
4843 tp->last_irq_tag = sblk->status_tag;
4844
d18edcb2
MC		 4845 if (tg3_irq_sync(tp))
4846 goto out;
624f8e50
MC		 4847
4848 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4849
4850 napi_schedule(&tp->napi);
4851
f47c11ee 4852out:
1da177e4
LT		 4853 return IRQ_RETVAL(handled);
4854}
4855
7938109f 4856/* ISR for interrupt test */
7d12e780 4857static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4858{
4859 struct net_device *dev = dev_id;
4860 struct tg3 *tp = netdev_priv(dev);
4861 struct tg3_hw_status *sblk = tp->hw_status;
4862
f9804ddb
MC		 4863 if ((sblk->status & SD_STATUS_UPDATED) ||
4864 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4865 tg3_disable_ints(tp);
7938109f
MC		 4866 return IRQ_RETVAL(1);
4867 }
4868 return IRQ_RETVAL(0);
4869}
4870
8e7a22e3 4871static int tg3_init_hw(struct tg3 *, int);
944d980e 4872static int tg3_halt(struct tg3 *, int, int);
1da177e4 4873
b9ec6c1b
MC		 4874/* Restart hardware after configuration changes, self-test, etc.
4875 * Invoked with tp->lock held.
4876 */
4877static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4878 __releases(tp->lock)
4879 __acquires(tp->lock)
b9ec6c1b
MC		 4880{
4881 int err;
4882
4883 err = tg3_init_hw(tp, reset_phy);
4884 if (err) {
4885 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4886 "aborting.\n", tp->dev->name);
4887 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4888 tg3_full_unlock(tp);
4889 del_timer_sync(&tp->timer);
4890 tp->irq_sync = 0;
bea3348e 4891 napi_enable(&tp->napi);
b9ec6c1b
MC		 4892 dev_close(tp->dev);
4893 tg3_full_lock(tp, 0);
4894 }
4895 return err;
4896}
4897
1da177e4
LT		 4898#ifdef CONFIG_NET_POLL_CONTROLLER
4899static void tg3_poll_controller(struct net_device *dev)
4900{
88b06bc2
MC		 4901 struct tg3 *tp = netdev_priv(dev);
4902
7d12e780 4903 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4904}
4905#endif
4906
c4028958 4907static void tg3_reset_task(struct work_struct *work)
1da177e4 4908{
c4028958 4909 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4910 int err;
1da177e4
LT		 4911 unsigned int restart_timer;
4912
7faa006f 4913 tg3_full_lock(tp, 0);
7faa006f
MC		 4914
4915 if (!netif_running(tp->dev)) {
7faa006f
MC		 4916 tg3_full_unlock(tp);
4917 return;
4918 }
4919
4920 tg3_full_unlock(tp);
4921
b02fd9e3
MC		 4922 tg3_phy_stop(tp);
4923
1da177e4
LT		 4924 tg3_netif_stop(tp);
4925
f47c11ee 4926 tg3_full_lock(tp, 1);
1da177e4
LT		 4927
4928 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4929 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4930
df3e6548
MC		 4931 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4932 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4933 tp->write32_rx_mbox = tg3_write_flush_reg32;
4934 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4935 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4936 }
4937
944d980e 4938 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4939 err = tg3_init_hw(tp, 1);
4940 if (err)
b9ec6c1b 4941 goto out;
1da177e4
LT		 4942
4943 tg3_netif_start(tp);
4944
1da177e4
LT		 4945 if (restart_timer)
4946 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4947
b9ec6c1b 4948out:
7faa006f 4949 tg3_full_unlock(tp);
b02fd9e3
MC		 4950
4951 if (!err)
4952 tg3_phy_start(tp);
1da177e4
LT		 4953}
4954
b0408751
MC		 4955static void tg3_dump_short_state(struct tg3 *tp)
4956{
4957 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4958 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4959 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4960 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4961}
4962
1da177e4
LT		 4963static void tg3_tx_timeout(struct net_device *dev)
4964{
4965 struct tg3 *tp = netdev_priv(dev);
4966
b0408751 4967 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 4968 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4969 dev->name);
b0408751
MC		 4970 tg3_dump_short_state(tp);
4971 }
1da177e4
LT		 4972
4973 schedule_work(&tp->reset_task);
4974}
4975
c58ec932
MC		 4976/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4977static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4978{
4979 u32 base = (u32) mapping & 0xffffffff;
4980
4981 return ((base > 0xffffdcc0) &&
4982 (base + len + 8 < base));
4983}
4984
72f2afb8
MC		 4985/* Test for DMA addresses > 40-bit */
4986static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4987 int len)
4988{
4989#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 4990 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 4991 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 4992 return 0;
4993#else
4994 return 0;
4995#endif
4996}
4997
1da177e4
LT		 4998static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4999
72f2afb8
MC		 5000/* Workaround 4GB and 40-bit hardware DMA bugs. */
5001static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5002 u32 last_plus_one, u32 *start,
5003 u32 base_flags, u32 mss)
1da177e4 5004{
41588ba1 5005 struct sk_buff *new_skb;
c58ec932 5006 dma_addr_t new_addr = 0;
1da177e4 5007 u32 entry = *start;
c58ec932 5008 int i, ret = 0;
1da177e4 5009
41588ba1
MC		 5010 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5011 new_skb = skb_copy(skb, GFP_ATOMIC);
5012 else {
5013 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5014
5015 new_skb = skb_copy_expand(skb,
5016 skb_headroom(skb) + more_headroom,
5017 skb_tailroom(skb), GFP_ATOMIC);
5018 }
5019
1da177e4 5020 if (!new_skb) {
c58ec932
MC		 5021 ret = -1;
5022 } else {
5023 /* New SKB is guaranteed to be linear. */
5024 entry = *start;
90079ce8
DM		 5025 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5026 new_addr = skb_shinfo(new_skb)->dma_maps[0];
5027
c58ec932
MC		 5028 /* Make sure new skb does not cross any 4G boundaries.
5029 * Drop the packet if it does.
5030 */
90079ce8 5031 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5032 if (!ret)
5033 skb_dma_unmap(&tp->pdev->dev, new_skb,
5034 DMA_TO_DEVICE);
c58ec932
MC		 5035 ret = -1;
5036 dev_kfree_skb(new_skb);
5037 new_skb = NULL;
5038 } else {
5039 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5040 base_flags, 1 | (mss << 1));
5041 *start = NEXT_TX(entry);
5042 }
1da177e4
LT		 5043 }
5044
1da177e4
LT		 5045 /* Now clean up the sw ring entries. */
5046 i = 0;
5047 while (entry != last_plus_one) {
1da177e4
LT		 5048 if (i == 0) {
5049 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5050 } else {
5051 tp->tx_buffers[entry].skb = NULL;
5052 }
5053 entry = NEXT_TX(entry);
5054 i++;
5055 }
5056
90079ce8 5057 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5058 dev_kfree_skb(skb);
5059
c58ec932 5060 return ret;
1da177e4
LT		 5061}
5062
5063static void tg3_set_txd(struct tg3 *tp, int entry,
5064 dma_addr_t mapping, int len, u32 flags,
5065 u32 mss_and_is_end)
5066{
5067 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5068 int is_end = (mss_and_is_end & 0x1);
5069 u32 mss = (mss_and_is_end >> 1);
5070 u32 vlan_tag = 0;
5071
5072 if (is_end)
5073 flags |= TXD_FLAG_END;
5074 if (flags & TXD_FLAG_VLAN) {
5075 vlan_tag = flags >> 16;
5076 flags &= 0xffff;
5077 }
5078 vlan_tag |= (mss << TXD_MSS_SHIFT);
5079
5080 txd->addr_hi = ((u64) mapping >> 32);
5081 txd->addr_lo = ((u64) mapping & 0xffffffff);
5082 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5083 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5084}
5085
5a6f3074
MC		 5086/* hard_start_xmit for devices that don't have any bugs and
5087 * support TG3_FLG2_HW_TSO_2 only.
5088 */
1da177e4 5089static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5090{
5091 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5092 u32 len, entry, base_flags, mss;
90079ce8
DM		 5093 struct skb_shared_info *sp;
5094 dma_addr_t mapping;
5a6f3074
MC		 5095
5096 len = skb_headlen(skb);
5097
00b70504 5098 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5099 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5100 * interrupt. Furthermore, IRQ processing runs lockless so we have
5101 * no IRQ context deadlocks to worry about either. Rejoice!
5102 */
1b2a7205 5103 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5104 if (!netif_queue_stopped(dev)) {
5105 netif_stop_queue(dev);
5106
5107 /* This is a hard error, log it. */
5108 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5109 "queue awake!\n", dev->name);
5110 }
5a6f3074
MC		 5111 return NETDEV_TX_BUSY;
5112 }
5113
5114 entry = tp->tx_prod;
5115 base_flags = 0;
5a6f3074 5116 mss = 0;
c13e3713 5117 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5118 int tcp_opt_len, ip_tcp_len;
5119
5120 if (skb_header_cloned(skb) &&
5121 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5122 dev_kfree_skb(skb);
5123 goto out_unlock;
5124 }
5125
b0026624
MC		 5126 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5127 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5128 else {
eddc9ec5
ACM		 5129 struct iphdr *iph = ip_hdr(skb);
5130
ab6a5bb6 5131 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5132 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5133
eddc9ec5
ACM		 5134 iph->check = 0;
5135 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5136 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5137 }
5a6f3074
MC		 5138
5139 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5140 TXD_FLAG_CPU_POST_DMA);
5141
aa8223c7 5142 tcp_hdr(skb)->check = 0;
5a6f3074 5143
5a6f3074 5144 }
84fa7933 5145 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5146 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5147#if TG3_VLAN_TAG_USED
5148 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5149 base_flags |= (TXD_FLAG_VLAN |
5150 (vlan_tx_tag_get(skb) << 16));
5151#endif
5152
90079ce8
DM		 5153 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5154 dev_kfree_skb(skb);
5155 goto out_unlock;
5156 }
5157
5158 sp = skb_shinfo(skb);
5159
5160 mapping = sp->dma_maps[0];
5a6f3074
MC		 5161
5162 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5163
5164 tg3_set_txd(tp, entry, mapping, len, base_flags,
5165 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5166
5167 entry = NEXT_TX(entry);
5168
5169 /* Now loop through additional data fragments, and queue them. */
5170 if (skb_shinfo(skb)->nr_frags > 0) {
5171 unsigned int i, last;
5172
5173 last = skb_shinfo(skb)->nr_frags - 1;
5174 for (i = 0; i <= last; i++) {
5175 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5176
5177 len = frag->size;
90079ce8 5178 mapping = sp->dma_maps[i + 1];
5a6f3074 5179 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5180
5181 tg3_set_txd(tp, entry, mapping, len,
5182 base_flags, (i == last) | (mss << 1));
5183
5184 entry = NEXT_TX(entry);
5185 }
5186 }
5187
5188 /* Packets are ready, update Tx producer idx local and on card. */
5189 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5190
5191 tp->tx_prod = entry;
1b2a7205 5192 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5193 netif_stop_queue(dev);
42952231 5194 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5195 netif_wake_queue(tp->dev);
5196 }
5197
5198out_unlock:
5199 mmiowb();
5a6f3074
MC		 5200
5201 dev->trans_start = jiffies;
5202
5203 return NETDEV_TX_OK;
5204}
5205
52c0fd83
MC		 5206static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5207
5208/* Use GSO to workaround a rare TSO bug that may be triggered when the
5209 * TSO header is greater than 80 bytes.
5210 */
5211static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5212{
5213 struct sk_buff *segs, *nskb;
5214
5215 /* Estimate the number of fragments in the worst case */
1b2a7205 5216 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5217 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5218 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5219 return NETDEV_TX_BUSY;
5220
5221 netif_wake_queue(tp->dev);
52c0fd83
MC		 5222 }
5223
5224 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5225 if (IS_ERR(segs))
52c0fd83
MC		 5226 goto tg3_tso_bug_end;
5227
5228 do {
5229 nskb = segs;
5230 segs = segs->next;
5231 nskb->next = NULL;
5232 tg3_start_xmit_dma_bug(nskb, tp->dev);
5233 } while (segs);
5234
5235tg3_tso_bug_end:
5236 dev_kfree_skb(skb);
5237
5238 return NETDEV_TX_OK;
5239}
52c0fd83 5240
5a6f3074
MC		 5241/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5242 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5243 */
5244static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5245{
5246 struct tg3 *tp = netdev_priv(dev);
1da177e4 5247 u32 len, entry, base_flags, mss;
90079ce8 5248 struct skb_shared_info *sp;
1da177e4 5249 int would_hit_hwbug;
90079ce8 5250 dma_addr_t mapping;
1da177e4
LT		 5251
5252 len = skb_headlen(skb);
5253
00b70504 5254 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5255 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5256 * interrupt. Furthermore, IRQ processing runs lockless so we have
5257 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5258 */
1b2a7205 5259 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5260 if (!netif_queue_stopped(dev)) {
5261 netif_stop_queue(dev);
5262
5263 /* This is a hard error, log it. */
5264 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5265 "queue awake!\n", dev->name);
5266 }
1da177e4
LT		 5267 return NETDEV_TX_BUSY;
5268 }
5269
5270 entry = tp->tx_prod;
5271 base_flags = 0;
84fa7933 5272 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5273 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5274 mss = 0;
c13e3713 5275 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5276 struct iphdr *iph;
52c0fd83 5277 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5278
5279 if (skb_header_cloned(skb) &&
5280 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5281 dev_kfree_skb(skb);
5282 goto out_unlock;
5283 }
5284
ab6a5bb6 5285 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5286 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5287
52c0fd83
MC		 5288 hdr_len = ip_tcp_len + tcp_opt_len;
5289 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5290 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5291 return (tg3_tso_bug(tp, skb));
5292
1da177e4
LT		 5293 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5294 TXD_FLAG_CPU_POST_DMA);
5295
eddc9ec5
ACM		 5296 iph = ip_hdr(skb);
5297 iph->check = 0;
5298 iph->tot_len = htons(mss + hdr_len);
1da177e4 5299 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5300 tcp_hdr(skb)->check = 0;
1da177e4 5301 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5302 } else
5303 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5304 iph->daddr, 0,
5305 IPPROTO_TCP,
5306 0);
1da177e4
LT		 5307
5308 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5309 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5310 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5311 int tsflags;
5312
eddc9ec5 5313 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5314 mss |= (tsflags << 11);
5315 }
5316 } else {
eddc9ec5 5317 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5318 int tsflags;
5319
eddc9ec5 5320 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5321 base_flags |= tsflags << 12;
5322 }
5323 }
5324 }
1da177e4
LT		 5325#if TG3_VLAN_TAG_USED
5326 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5327 base_flags |= (TXD_FLAG_VLAN |
5328 (vlan_tx_tag_get(skb) << 16));
5329#endif
5330
90079ce8
DM		 5331 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5332 dev_kfree_skb(skb);
5333 goto out_unlock;
5334 }
5335
5336 sp = skb_shinfo(skb);
5337
5338 mapping = sp->dma_maps[0];
1da177e4
LT		 5339
5340 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5341
5342 would_hit_hwbug = 0;
5343
41588ba1
MC		 5344 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5345 would_hit_hwbug = 1;
5346 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5347 would_hit_hwbug = 1;
1da177e4
LT		 5348
5349 tg3_set_txd(tp, entry, mapping, len, base_flags,
5350 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5351
5352 entry = NEXT_TX(entry);
5353
5354 /* Now loop through additional data fragments, and queue them. */
5355 if (skb_shinfo(skb)->nr_frags > 0) {
5356 unsigned int i, last;
5357
5358 last = skb_shinfo(skb)->nr_frags - 1;
5359 for (i = 0; i <= last; i++) {
5360 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5361
5362 len = frag->size;
90079ce8 5363 mapping = sp->dma_maps[i + 1];
1da177e4
LT		 5364
5365 tp->tx_buffers[entry].skb = NULL;
1da177e4 5366
c58ec932
MC		 5367 if (tg3_4g_overflow_test(mapping, len))
5368 would_hit_hwbug = 1;
1da177e4 5369
72f2afb8
MC		 5370 if (tg3_40bit_overflow_test(tp, mapping, len))
5371 would_hit_hwbug = 1;
5372
1da177e4
LT		 5373 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5374 tg3_set_txd(tp, entry, mapping, len,
5375 base_flags, (i == last)|(mss << 1));
5376 else
5377 tg3_set_txd(tp, entry, mapping, len,
5378 base_flags, (i == last));
5379
5380 entry = NEXT_TX(entry);
5381 }
5382 }
5383
5384 if (would_hit_hwbug) {
5385 u32 last_plus_one = entry;
5386 u32 start;
1da177e4 5387
c58ec932
MC		 5388 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5389 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5390
5391 /* If the workaround fails due to memory/mapping
5392 * failure, silently drop this packet.
5393 */
72f2afb8 5394 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5395 &start, base_flags, mss))
1da177e4
LT		 5396 goto out_unlock;
5397
5398 entry = start;
5399 }
5400
5401 /* Packets are ready, update Tx producer idx local and on card. */
5402 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5403
5404 tp->tx_prod = entry;
1b2a7205 5405 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5406 netif_stop_queue(dev);
42952231 5407 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5408 netif_wake_queue(tp->dev);
5409 }
1da177e4
LT		 5410
5411out_unlock:
5412 mmiowb();
1da177e4
LT		 5413
5414 dev->trans_start = jiffies;
5415
5416 return NETDEV_TX_OK;
5417}
5418
5419static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5420 int new_mtu)
5421{
5422 dev->mtu = new_mtu;
5423
ef7f5ec0 5424 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5425 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5426 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5427 ethtool_op_set_tso(dev, 0);
5428 }
5429 else
5430 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5431 } else {
a4e2b347 5432 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5433 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5434 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5435 }
1da177e4
LT		 5436}
5437
5438static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5439{
5440 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5441 int err;
1da177e4
LT		 5442
5443 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5444 return -EINVAL;
5445
5446 if (!netif_running(dev)) {
5447 /* We'll just catch it later when the
5448 * device is up'd.
5449 */
5450 tg3_set_mtu(dev, tp, new_mtu);
5451 return 0;
5452 }
5453
b02fd9e3
MC		 5454 tg3_phy_stop(tp);
5455
1da177e4 5456 tg3_netif_stop(tp);
f47c11ee
DM		 5457
5458 tg3_full_lock(tp, 1);
1da177e4 5459
944d980e 5460 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5461
5462 tg3_set_mtu(dev, tp, new_mtu);
5463
b9ec6c1b 5464 err = tg3_restart_hw(tp, 0);
1da177e4 5465
b9ec6c1b
MC		 5466 if (!err)
5467 tg3_netif_start(tp);
1da177e4 5468
f47c11ee 5469 tg3_full_unlock(tp);
1da177e4 5470
b02fd9e3
MC		 5471 if (!err)
5472 tg3_phy_start(tp);
5473
b9ec6c1b 5474 return err;
1da177e4
LT		 5475}
5476
5477/* Free up pending packets in all rx/tx rings.
5478 *
5479 * The chip has been shut down and the driver detached from
5480 * the networking, so no interrupts or new tx packets will
5481 * end up in the driver. tp->{tx,}lock is not held and we are not
5482 * in an interrupt context and thus may sleep.
5483 */
5484static void tg3_free_rings(struct tg3 *tp)
5485{
5486 struct ring_info *rxp;
5487 int i;
5488
5489 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5490 rxp = &tp->rx_std_buffers[i];
5491
5492 if (rxp->skb == NULL)
5493 continue;
5494 pci_unmap_single(tp->pdev,
5495 pci_unmap_addr(rxp, mapping),
7e72aad4 5496 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 5497 PCI_DMA_FROMDEVICE);
5498 dev_kfree_skb_any(rxp->skb);
5499 rxp->skb = NULL;
5500 }
5501
5502 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5503 rxp = &tp->rx_jumbo_buffers[i];
5504
5505 if (rxp->skb == NULL)
5506 continue;
5507 pci_unmap_single(tp->pdev,
5508 pci_unmap_addr(rxp, mapping),
5509 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5510 PCI_DMA_FROMDEVICE);
5511 dev_kfree_skb_any(rxp->skb);
5512 rxp->skb = NULL;
5513 }
5514
5515 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5516 struct tx_ring_info *txp;
5517 struct sk_buff *skb;
1da177e4
LT		 5518
5519 txp = &tp->tx_buffers[i];
5520 skb = txp->skb;
5521
5522 if (skb == NULL) {
5523 i++;
5524 continue;
5525 }
5526
90079ce8 5527 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5528
90079ce8 5529 txp->skb = NULL;
1da177e4 5530
90079ce8 5531 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5532
5533 dev_kfree_skb_any(skb);
5534 }
5535}
5536
5537/* Initialize tx/rx rings for packet processing.
5538 *
5539 * The chip has been shut down and the driver detached from
5540 * the networking, so no interrupts or new tx packets will
5541 * end up in the driver. tp->{tx,}lock are held and thus
5542 * we may not sleep.
5543 */
32d8c572 5544static int tg3_init_rings(struct tg3 *tp)
1da177e4
LT		 5545{
5546 u32 i;
5547
5548 /* Free up all the SKBs. */
5549 tg3_free_rings(tp);
5550
5551 /* Zero out all descriptors. */
5552 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5553 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5554 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5555 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5556
7e72aad4 5557 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
a4e2b347 5558 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
7e72aad4
MC		 5559 (tp->dev->mtu > ETH_DATA_LEN))
5560 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5561
1da177e4
LT		 5562 /* Initialize invariants of the rings, we only set this
5563 * stuff once. This works because the card does not
5564 * write into the rx buffer posting rings.
5565 */
5566 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5567 struct tg3_rx_buffer_desc *rxd;
5568
5569 rxd = &tp->rx_std[i];
7e72aad4 5570 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 5571 << RXD_LEN_SHIFT;
5572 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5573 rxd->opaque = (RXD_OPAQUE_RING_STD |
5574 (i << RXD_OPAQUE_INDEX_SHIFT));
5575 }
5576
0f893dc6 5577 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5578 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5579 struct tg3_rx_buffer_desc *rxd;
5580
5581 rxd = &tp->rx_jumbo[i];
5582 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5583 << RXD_LEN_SHIFT;
5584 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5585 RXD_FLAG_JUMBO;
5586 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5587 (i << RXD_OPAQUE_INDEX_SHIFT));
5588 }
5589 }
5590
5591 /* Now allocate fresh SKBs for each rx ring. */
5592 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5593 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5594 printk(KERN_WARNING PFX
5595 "%s: Using a smaller RX standard ring, "
5596 "only %d out of %d buffers were allocated "
5597 "successfully.\n",
5598 tp->dev->name, i, tp->rx_pending);
5599 if (i == 0)
5600 return -ENOMEM;
5601 tp->rx_pending = i;
1da177e4 5602 break;
32d8c572 5603 }
1da177e4
LT		 5604 }
5605
0f893dc6 5606 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5607 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5608 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5609 -1, i) < 0) {
5610 printk(KERN_WARNING PFX
5611 "%s: Using a smaller RX jumbo ring, "
5612 "only %d out of %d buffers were "
5613 "allocated successfully.\n",
5614 tp->dev->name, i, tp->rx_jumbo_pending);
5615 if (i == 0) {
5616 tg3_free_rings(tp);
5617 return -ENOMEM;
5618 }
5619 tp->rx_jumbo_pending = i;
1da177e4 5620 break;
32d8c572 5621 }
1da177e4
LT		 5622 }
5623 }
32d8c572 5624 return 0;
1da177e4
LT		 5625}
5626
5627/*
5628 * Must not be invoked with interrupt sources disabled and
5629 * the hardware shutdown down.
5630 */
5631static void tg3_free_consistent(struct tg3 *tp)
5632{
b4558ea9
JJ		 5633 kfree(tp->rx_std_buffers);
5634 tp->rx_std_buffers = NULL;
1da177e4
LT		 5635 if (tp->rx_std) {
5636 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5637 tp->rx_std, tp->rx_std_mapping);
5638 tp->rx_std = NULL;
5639 }
5640 if (tp->rx_jumbo) {
5641 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5642 tp->rx_jumbo, tp->rx_jumbo_mapping);
5643 tp->rx_jumbo = NULL;
5644 }
5645 if (tp->rx_rcb) {
5646 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5647 tp->rx_rcb, tp->rx_rcb_mapping);
5648 tp->rx_rcb = NULL;
5649 }
5650 if (tp->tx_ring) {
5651 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5652 tp->tx_ring, tp->tx_desc_mapping);
5653 tp->tx_ring = NULL;
5654 }
5655 if (tp->hw_status) {
5656 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5657 tp->hw_status, tp->status_mapping);
5658 tp->hw_status = NULL;
5659 }
5660 if (tp->hw_stats) {
5661 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5662 tp->hw_stats, tp->stats_mapping);
5663 tp->hw_stats = NULL;
5664 }
5665}
5666
5667/*
5668 * Must not be invoked with interrupt sources disabled and
5669 * the hardware shutdown down. Can sleep.
5670 */
5671static int tg3_alloc_consistent(struct tg3 *tp)
5672{
bd2b3343 5673 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5674 (TG3_RX_RING_SIZE +
5675 TG3_RX_JUMBO_RING_SIZE)) +
5676 (sizeof(struct tx_ring_info) *
5677 TG3_TX_RING_SIZE),
5678 GFP_KERNEL);
5679 if (!tp->rx_std_buffers)
5680 return -ENOMEM;
5681
1da177e4
LT		 5682 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5683 tp->tx_buffers = (struct tx_ring_info *)
5684 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5685
5686 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5687 &tp->rx_std_mapping);
5688 if (!tp->rx_std)
5689 goto err_out;
5690
5691 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5692 &tp->rx_jumbo_mapping);
5693
5694 if (!tp->rx_jumbo)
5695 goto err_out;
5696
5697 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5698 &tp->rx_rcb_mapping);
5699 if (!tp->rx_rcb)
5700 goto err_out;
5701
5702 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5703 &tp->tx_desc_mapping);
5704 if (!tp->tx_ring)
5705 goto err_out;
5706
5707 tp->hw_status = pci_alloc_consistent(tp->pdev,
5708 TG3_HW_STATUS_SIZE,
5709 &tp->status_mapping);
5710 if (!tp->hw_status)
5711 goto err_out;
5712
5713 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5714 sizeof(struct tg3_hw_stats),
5715 &tp->stats_mapping);
5716 if (!tp->hw_stats)
5717 goto err_out;
5718
5719 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5720 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5721
5722 return 0;
5723
5724err_out:
5725 tg3_free_consistent(tp);
5726 return -ENOMEM;
5727}
5728
5729#define MAX_WAIT_CNT 1000
5730
5731/* To stop a block, clear the enable bit and poll till it
5732 * clears. tp->lock is held.
5733 */
b3b7d6be 5734static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5735{
5736 unsigned int i;
5737 u32 val;
5738
5739 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5740 switch (ofs) {
5741 case RCVLSC_MODE:
5742 case DMAC_MODE:
5743 case MBFREE_MODE:
5744 case BUFMGR_MODE:
5745 case MEMARB_MODE:
5746 /* We can't enable/disable these bits of the
5747 * 5705/5750, just say success.
5748 */
5749 return 0;
5750
5751 default:
5752 break;
855e1111 5753 }
1da177e4
LT		 5754 }
5755
5756 val = tr32(ofs);
5757 val &= ~enable_bit;
5758 tw32_f(ofs, val);
5759
5760 for (i = 0; i < MAX_WAIT_CNT; i++) {
5761 udelay(100);
5762 val = tr32(ofs);
5763 if ((val & enable_bit) == 0)
5764 break;
5765 }
5766
b3b7d6be 5767 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5768 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5769 "ofs=%lx enable_bit=%x\n",
5770 ofs, enable_bit);
5771 return -ENODEV;
5772 }
5773
5774 return 0;
5775}
5776
5777/* tp->lock is held. */
b3b7d6be 5778static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5779{
5780 int i, err;
5781
5782 tg3_disable_ints(tp);
5783
5784 tp->rx_mode &= ~RX_MODE_ENABLE;
5785 tw32_f(MAC_RX_MODE, tp->rx_mode);
5786 udelay(10);
5787
b3b7d6be
DM		 5788 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5789 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5790 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5791 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5792 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5793 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5794
5795 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5796 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5797 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5798 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5799 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5800 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5801 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5802
5803 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5804 tw32_f(MAC_MODE, tp->mac_mode);
5805 udelay(40);
5806
5807 tp->tx_mode &= ~TX_MODE_ENABLE;
5808 tw32_f(MAC_TX_MODE, tp->tx_mode);
5809
5810 for (i = 0; i < MAX_WAIT_CNT; i++) {
5811 udelay(100);
5812 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5813 break;
5814 }
5815 if (i >= MAX_WAIT_CNT) {
5816 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5817 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5818 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5819 err |= -ENODEV;
1da177e4
LT		 5820 }
5821
e6de8ad1 5822 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5823 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5824 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5825
5826 tw32(FTQ_RESET, 0xffffffff);
5827 tw32(FTQ_RESET, 0x00000000);
5828
b3b7d6be
DM		 5829 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5830 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5831
5832 if (tp->hw_status)
5833 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5834 if (tp->hw_stats)
5835 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5836
1da177e4
LT		 5837 return err;
5838}
5839
0d3031d9
MC		 5840static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5841{
5842 int i;
5843 u32 apedata;
5844
5845 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5846 if (apedata != APE_SEG_SIG_MAGIC)
5847 return;
5848
5849 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5850 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5851 return;
5852
5853 /* Wait for up to 1 millisecond for APE to service previous event. */
5854 for (i = 0; i < 10; i++) {
5855 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5856 return;
5857
5858 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5859
5860 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5861 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5862 event | APE_EVENT_STATUS_EVENT_PENDING);
5863
5864 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5865
5866 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5867 break;
5868
5869 udelay(100);
5870 }
5871
5872 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5873 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5874}
5875
5876static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5877{
5878 u32 event;
5879 u32 apedata;
5880
5881 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5882 return;
5883
5884 switch (kind) {
5885 case RESET_KIND_INIT:
5886 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5887 APE_HOST_SEG_SIG_MAGIC);
5888 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5889 APE_HOST_SEG_LEN_MAGIC);
5890 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5891 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5892 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5893 APE_HOST_DRIVER_ID_MAGIC);
5894 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5895 APE_HOST_BEHAV_NO_PHYLOCK);
5896
5897 event = APE_EVENT_STATUS_STATE_START;
5898 break;
5899 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5900 /* With the interface we are currently using,
5901 * APE does not track driver state. Wiping
5902 * out the HOST SEGMENT SIGNATURE forces
5903 * the APE to assume OS absent status.
5904 */
5905 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5906
0d3031d9
MC		 5907 event = APE_EVENT_STATUS_STATE_UNLOAD;
5908 break;
5909 case RESET_KIND_SUSPEND:
5910 event = APE_EVENT_STATUS_STATE_SUSPEND;
5911 break;
5912 default:
5913 return;
5914 }
5915
5916 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5917
5918 tg3_ape_send_event(tp, event);
5919}
5920
1da177e4
LT		 5921/* tp->lock is held. */
5922static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5923{
f49639e6
DM		 5924 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5925 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5926
5927 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5928 switch (kind) {
5929 case RESET_KIND_INIT:
5930 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5931 DRV_STATE_START);
5932 break;
5933
5934 case RESET_KIND_SHUTDOWN:
5935 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5936 DRV_STATE_UNLOAD);
5937 break;
5938
5939 case RESET_KIND_SUSPEND:
5940 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5941 DRV_STATE_SUSPEND);
5942 break;
5943
5944 default:
5945 break;
855e1111 5946 }
1da177e4 5947 }
0d3031d9
MC		 5948
5949 if (kind == RESET_KIND_INIT ||
5950 kind == RESET_KIND_SUSPEND)
5951 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5952}
5953
5954/* tp->lock is held. */
5955static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5956{
5957 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5958 switch (kind) {
5959 case RESET_KIND_INIT:
5960 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5961 DRV_STATE_START_DONE);
5962 break;
5963
5964 case RESET_KIND_SHUTDOWN:
5965 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5966 DRV_STATE_UNLOAD_DONE);
5967 break;
5968
5969 default:
5970 break;
855e1111 5971 }
1da177e4 5972 }
0d3031d9
MC		 5973
5974 if (kind == RESET_KIND_SHUTDOWN)
5975 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5976}
5977
5978/* tp->lock is held. */
5979static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5980{
5981 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5982 switch (kind) {
5983 case RESET_KIND_INIT:
5984 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5985 DRV_STATE_START);
5986 break;
5987
5988 case RESET_KIND_SHUTDOWN:
5989 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5990 DRV_STATE_UNLOAD);
5991 break;
5992
5993 case RESET_KIND_SUSPEND:
5994 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5995 DRV_STATE_SUSPEND);
5996 break;
5997
5998 default:
5999 break;
855e1111 6000 }
1da177e4
LT		 6001 }
6002}
6003
7a6f4369
MC		 6004static int tg3_poll_fw(struct tg3 *tp)
6005{
6006 int i;
6007 u32 val;
6008
b5d3772c 6009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6010 /* Wait up to 20ms for init done. */
6011 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6012 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6013 return 0;
0ccead18 6014 udelay(100);
b5d3772c
MC		 6015 }
6016 return -ENODEV;
6017 }
6018
7a6f4369
MC		 6019 /* Wait for firmware initialization to complete. */
6020 for (i = 0; i < 100000; i++) {
6021 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6022 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6023 break;
6024 udelay(10);
6025 }
6026
6027 /* Chip might not be fitted with firmware. Some Sun onboard
6028 * parts are configured like that. So don't signal the timeout
6029 * of the above loop as an error, but do report the lack of
6030 * running firmware once.
6031 */
6032 if (i >= 100000 &&
6033 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6034 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6035
6036 printk(KERN_INFO PFX "%s: No firmware running.\n",
6037 tp->dev->name);
6038 }
6039
6040 return 0;
6041}
6042
ee6a99b5
MC		 6043/* Save PCI command register before chip reset */
6044static void tg3_save_pci_state(struct tg3 *tp)
6045{
8a6eac90 6046 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6047}
6048
6049/* Restore PCI state after chip reset */
6050static void tg3_restore_pci_state(struct tg3 *tp)
6051{
6052 u32 val;
6053
6054 /* Re-enable indirect register accesses. */
6055 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6056 tp->misc_host_ctrl);
6057
6058 /* Set MAX PCI retry to zero. */
6059 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6060 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6061 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6062 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6063 /* Allow reads and writes to the APE register and memory space. */
6064 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6065 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6066 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6067 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6068
8a6eac90 6069 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6070
fcb389df
MC		 6071 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6072 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6073 pcie_set_readrq(tp->pdev, 4096);
6074 else {
6075 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6076 tp->pci_cacheline_sz);
6077 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6078 tp->pci_lat_timer);
6079 }
114342f2 6080 }
5f5c51e3 6081
ee6a99b5 6082 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6083 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6084 u16 pcix_cmd;
6085
6086 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6087 &pcix_cmd);
6088 pcix_cmd &= ~PCI_X_CMD_ERO;
6089 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6090 pcix_cmd);
6091 }
ee6a99b5
MC		 6092
6093 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6094
6095 /* Chip reset on 5780 will reset MSI enable bit,
6096 * so need to restore it.
6097 */
6098 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6099 u16 ctrl;
6100
6101 pci_read_config_word(tp->pdev,
6102 tp->msi_cap + PCI_MSI_FLAGS,
6103 &ctrl);
6104 pci_write_config_word(tp->pdev,
6105 tp->msi_cap + PCI_MSI_FLAGS,
6106 ctrl | PCI_MSI_FLAGS_ENABLE);
6107 val = tr32(MSGINT_MODE);
6108 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6109 }
6110 }
6111}
6112
1da177e4
LT		 6113static void tg3_stop_fw(struct tg3 *);
6114
6115/* tp->lock is held. */
6116static int tg3_chip_reset(struct tg3 *tp)
6117{
6118 u32 val;
1ee582d8 6119 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6120 int err;
1da177e4 6121
f49639e6
DM		 6122 tg3_nvram_lock(tp);
6123
158d7abd
MC		 6124 tg3_mdio_stop(tp);
6125
77b483f1
MC		 6126 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6127
f49639e6
DM		 6128 /* No matching tg3_nvram_unlock() after this because
6129 * chip reset below will undo the nvram lock.
6130 */
6131 tp->nvram_lock_cnt = 0;
1da177e4 6132
ee6a99b5
MC		 6133 /* GRC_MISC_CFG core clock reset will clear the memory
6134 * enable bit in PCI register 4 and the MSI enable bit
6135 * on some chips, so we save relevant registers here.
6136 */
6137 tg3_save_pci_state(tp);
6138
d9ab5ad1 6139 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6140 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6141 tw32(GRC_FASTBOOT_PC, 0);
6142
1da177e4
LT		 6143 /*
6144 * We must avoid the readl() that normally takes place.
6145 * It locks machines, causes machine checks, and other
6146 * fun things. So, temporarily disable the 5701
6147 * hardware workaround, while we do the reset.
6148 */
1ee582d8
MC		 6149 write_op = tp->write32;
6150 if (write_op == tg3_write_flush_reg32)
6151 tp->write32 = tg3_write32;
1da177e4 6152
d18edcb2
MC		 6153 /* Prevent the irq handler from reading or writing PCI registers
6154 * during chip reset when the memory enable bit in the PCI command
6155 * register may be cleared. The chip does not generate interrupt
6156 * at this time, but the irq handler may still be called due to irq
6157 * sharing or irqpoll.
6158 */
6159 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6160 if (tp->hw_status) {
6161 tp->hw_status->status = 0;
6162 tp->hw_status->status_tag = 0;
6163 }
d18edcb2 6164 tp->last_tag = 0;
624f8e50 6165 tp->last_irq_tag = 0;
d18edcb2
MC		 6166 smp_mb();
6167 synchronize_irq(tp->pdev->irq);
6168
1da177e4
LT		 6169 /* do the reset */
6170 val = GRC_MISC_CFG_CORECLK_RESET;
6171
6172 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6173 if (tr32(0x7e2c) == 0x60) {
6174 tw32(0x7e2c, 0x20);
6175 }
6176 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6177 tw32(GRC_MISC_CFG, (1 << 29));
6178 val |= (1 << 29);
6179 }
6180 }
6181
b5d3772c
MC		 6182 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6183 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6184 tw32(GRC_VCPU_EXT_CTRL,
6185 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6186 }
6187
1da177e4
LT		 6188 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6189 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6190 tw32(GRC_MISC_CFG, val);
6191
1ee582d8
MC		 6192 /* restore 5701 hardware bug workaround write method */
6193 tp->write32 = write_op;
1da177e4
LT		 6194
6195 /* Unfortunately, we have to delay before the PCI read back.
6196 * Some 575X chips even will not respond to a PCI cfg access
6197 * when the reset command is given to the chip.
6198 *
6199 * How do these hardware designers expect things to work
6200 * properly if the PCI write is posted for a long period
6201 * of time? It is always necessary to have some method by
6202 * which a register read back can occur to push the write
6203 * out which does the reset.
6204 *
6205 * For most tg3 variants the trick below was working.
6206 * Ho hum...
6207 */
6208 udelay(120);
6209
6210 /* Flush PCI posted writes. The normal MMIO registers
6211 * are inaccessible at this time so this is the only
6212 * way to make this reliably (actually, this is no longer
6213 * the case, see above). I tried to use indirect
6214 * register read/write but this upset some 5701 variants.
6215 */
6216 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6217
6218 udelay(120);
6219
5e7dfd0f 6220 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
1da177e4
LT		 6221 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6222 int i;
6223 u32 cfg_val;
6224
6225 /* Wait for link training to complete. */
6226 for (i = 0; i < 5000; i++)
6227 udelay(100);
6228
6229 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6230 pci_write_config_dword(tp->pdev, 0xc4,
6231 cfg_val | (1 << 15));
6232 }
5e7dfd0f
MC		 6233
6234 /* Set PCIE max payload size to 128 bytes and
6235 * clear the "no snoop" and "relaxed ordering" bits.
6236 */
6237 pci_write_config_word(tp->pdev,
6238 tp->pcie_cap + PCI_EXP_DEVCTL,
6239 0);
6240
6241 pcie_set_readrq(tp->pdev, 4096);
6242
6243 /* Clear error status */
6244 pci_write_config_word(tp->pdev,
6245 tp->pcie_cap + PCI_EXP_DEVSTA,
6246 PCI_EXP_DEVSTA_CED |
6247 PCI_EXP_DEVSTA_NFED |
6248 PCI_EXP_DEVSTA_FED |
6249 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6250 }
6251
ee6a99b5 6252 tg3_restore_pci_state(tp);
1da177e4 6253
d18edcb2
MC		 6254 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6255
ee6a99b5
MC		 6256 val = 0;
6257 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6258 val = tr32(MEMARB_MODE);
ee6a99b5 6259 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6260
6261 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6262 tg3_stop_fw(tp);
6263 tw32(0x5000, 0x400);
6264 }
6265
6266 tw32(GRC_MODE, tp->grc_mode);
6267
6268 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6269 val = tr32(0xc4);
1da177e4
LT		 6270
6271 tw32(0xc4, val | (1 << 15));
6272 }
6273
6274 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6275 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6276 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6277 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6278 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6279 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6280 }
6281
6282 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6283 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6284 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6285 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6286 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6287 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6288 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6289 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6290 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6291 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6292 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6293 } else
6294 tw32_f(MAC_MODE, 0);
6295 udelay(40);
6296
158d7abd
MC		 6297 tg3_mdio_start(tp);
6298
77b483f1
MC		 6299 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6300
7a6f4369
MC		 6301 err = tg3_poll_fw(tp);
6302 if (err)
6303 return err;
1da177e4
LT		 6304
6305 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6306 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6307 val = tr32(0x7c00);
1da177e4
LT		 6308
6309 tw32(0x7c00, val | (1 << 25));
6310 }
6311
6312 /* Reprobe ASF enable state. */
6313 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6314 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6315 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6316 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6317 u32 nic_cfg;
6318
6319 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6320 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6321 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6322 tp->last_event_jiffies = jiffies;
cbf46853 6323 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6324 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6325 }
6326 }
6327
6328 return 0;
6329}
6330
6331/* tp->lock is held. */
6332static void tg3_stop_fw(struct tg3 *tp)
6333{
0d3031d9
MC		 6334 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6335 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6336 /* Wait for RX cpu to ACK the previous event. */
6337 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6338
6339 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6340
6341 tg3_generate_fw_event(tp);
1da177e4 6342
7c5026aa
MC		 6343 /* Wait for RX cpu to ACK this event. */
6344 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6345 }
6346}
6347
6348/* tp->lock is held. */
944d980e 6349static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6350{
6351 int err;
6352
6353 tg3_stop_fw(tp);
6354
944d980e 6355 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6356
b3b7d6be 6357 tg3_abort_hw(tp, silent);
1da177e4
LT		 6358 err = tg3_chip_reset(tp);
6359
944d980e
MC		 6360 tg3_write_sig_legacy(tp, kind);
6361 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6362
6363 if (err)
6364 return err;
6365
6366 return 0;
6367}
6368
1da177e4
LT		 6369#define RX_CPU_SCRATCH_BASE 0x30000
6370#define RX_CPU_SCRATCH_SIZE 0x04000
6371#define TX_CPU_SCRATCH_BASE 0x34000
6372#define TX_CPU_SCRATCH_SIZE 0x04000
6373
6374/* tp->lock is held. */
6375static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6376{
6377 int i;
6378
5d9428de
ES		 6379 BUG_ON(offset == TX_CPU_BASE &&
6380 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6381
b5d3772c
MC		 6382 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6383 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6384
6385 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6386 return 0;
6387 }
1da177e4
LT		 6388 if (offset == RX_CPU_BASE) {
6389 for (i = 0; i < 10000; i++) {
6390 tw32(offset + CPU_STATE, 0xffffffff);
6391 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6392 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6393 break;
6394 }
6395
6396 tw32(offset + CPU_STATE, 0xffffffff);
6397 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6398 udelay(10);
6399 } else {
6400 for (i = 0; i < 10000; i++) {
6401 tw32(offset + CPU_STATE, 0xffffffff);
6402 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6403 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6404 break;
6405 }
6406 }
6407
6408 if (i >= 10000) {
6409 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6410 "and %s CPU\n",
6411 tp->dev->name,
6412 (offset == RX_CPU_BASE ? "RX" : "TX"));
6413 return -ENODEV;
6414 }
ec41c7df
MC		 6415
6416 /* Clear firmware's nvram arbitration. */
6417 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6418 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6419 return 0;
6420}
6421
6422struct fw_info {
077f849d
JSR		 6423 unsigned int fw_base;
6424 unsigned int fw_len;
6425 const __be32 *fw_data;
1da177e4
LT		 6426};
6427
6428/* tp->lock is held. */
6429static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6430 int cpu_scratch_size, struct fw_info *info)
6431{
ec41c7df 6432 int err, lock_err, i;
1da177e4
LT		 6433 void (*write_op)(struct tg3 *, u32, u32);
6434
6435 if (cpu_base == TX_CPU_BASE &&
6436 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6437 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6438 "TX cpu firmware on %s which is 5705.\n",
6439 tp->dev->name);
6440 return -EINVAL;
6441 }
6442
6443 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6444 write_op = tg3_write_mem;
6445 else
6446 write_op = tg3_write_indirect_reg32;
6447
1b628151
MC		 6448 /* It is possible that bootcode is still loading at this point.
6449 * Get the nvram lock first before halting the cpu.
6450 */
ec41c7df 6451 lock_err = tg3_nvram_lock(tp);
1da177e4 6452 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6453 if (!lock_err)
6454 tg3_nvram_unlock(tp);
1da177e4
LT		 6455 if (err)
6456 goto out;
6457
6458 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6459 write_op(tp, cpu_scratch_base + i, 0);
6460 tw32(cpu_base + CPU_STATE, 0xffffffff);
6461 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6462 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6463 write_op(tp, (cpu_scratch_base +
077f849d 6464 (info->fw_base & 0xffff) +
1da177e4 6465 (i * sizeof(u32))),
077f849d 6466 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6467
6468 err = 0;
6469
6470out:
1da177e4
LT		 6471 return err;
6472}
6473
6474/* tp->lock is held. */
6475static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6476{
6477 struct fw_info info;
077f849d 6478 const __be32 *fw_data;
1da177e4
LT		 6479 int err, i;
6480
077f849d
JSR		 6481 fw_data = (void *)tp->fw->data;
6482
6483 /* Firmware blob starts with version numbers, followed by
6484 start address and length. We are setting complete length.
6485 length = end_address_of_bss - start_address_of_text.
6486 Remainder is the blob to be loaded contiguously
6487 from start address. */
6488
6489 info.fw_base = be32_to_cpu(fw_data[1]);
6490 info.fw_len = tp->fw->size - 12;
6491 info.fw_data = &fw_data[3];
1da177e4
LT		 6492
6493 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6494 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6495 &info);
6496 if (err)
6497 return err;
6498
6499 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6500 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6501 &info);
6502 if (err)
6503 return err;
6504
6505 /* Now startup only the RX cpu. */
6506 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6507 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6508
6509 for (i = 0; i < 5; i++) {
077f849d 6510 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6511 break;
6512 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6513 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6514 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6515 udelay(1000);
6516 }
6517 if (i >= 5) {
6518 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6519 "to set RX CPU PC, is %08x should be %08x\n",
6520 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6521 info.fw_base);
1da177e4
LT		 6522 return -ENODEV;
6523 }
6524 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6525 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6526
6527 return 0;
6528}
6529
1da177e4 6530/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6531
6532/* tp->lock is held. */
6533static int tg3_load_tso_firmware(struct tg3 *tp)
6534{
6535 struct fw_info info;
077f849d 6536 const __be32 *fw_data;
1da177e4
LT		 6537 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6538 int err, i;
6539
6540 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6541 return 0;
6542
077f849d
JSR		 6543 fw_data = (void *)tp->fw->data;
6544
6545 /* Firmware blob starts with version numbers, followed by
6546 start address and length. We are setting complete length.
6547 length = end_address_of_bss - start_address_of_text.
6548 Remainder is the blob to be loaded contiguously
6549 from start address. */
6550
6551 info.fw_base = be32_to_cpu(fw_data[1]);
6552 cpu_scratch_size = tp->fw_len;
6553 info.fw_len = tp->fw->size - 12;
6554 info.fw_data = &fw_data[3];
6555
1da177e4 6556 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6557 cpu_base = RX_CPU_BASE;
6558 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6559 } else {
1da177e4
LT		 6560 cpu_base = TX_CPU_BASE;
6561 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6562 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6563 }
6564
6565 err = tg3_load_firmware_cpu(tp, cpu_base,
6566 cpu_scratch_base, cpu_scratch_size,
6567 &info);
6568 if (err)
6569 return err;
6570
6571 /* Now startup the cpu. */
6572 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6573 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6574
6575 for (i = 0; i < 5; i++) {
077f849d 6576 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6577 break;
6578 tw32(cpu_base + CPU_STATE, 0xffffffff);
6579 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6580 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6581 udelay(1000);
6582 }
6583 if (i >= 5) {
6584 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6585 "to set CPU PC, is %08x should be %08x\n",
6586 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6587 info.fw_base);
1da177e4
LT		 6588 return -ENODEV;
6589 }
6590 tw32(cpu_base + CPU_STATE, 0xffffffff);
6591 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6592 return 0;
6593}
6594
1da177e4 6595
1da177e4
LT		 6596static int tg3_set_mac_addr(struct net_device *dev, void *p)
6597{
6598 struct tg3 *tp = netdev_priv(dev);
6599 struct sockaddr *addr = p;
986e0aeb 6600 int err = 0, skip_mac_1 = 0;
1da177e4 6601
f9804ddb
MC		 6602 if (!is_valid_ether_addr(addr->sa_data))
6603 return -EINVAL;
6604
1da177e4
LT		 6605 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6606
e75f7c90
MC		 6607 if (!netif_running(dev))
6608 return 0;
6609
58712ef9 6610 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6611 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6612
986e0aeb
MC		 6613 addr0_high = tr32(MAC_ADDR_0_HIGH);
6614 addr0_low = tr32(MAC_ADDR_0_LOW);
6615 addr1_high = tr32(MAC_ADDR_1_HIGH);
6616 addr1_low = tr32(MAC_ADDR_1_LOW);
6617
6618 /* Skip MAC addr 1 if ASF is using it. */
6619 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6620 !(addr1_high == 0 && addr1_low == 0))
6621 skip_mac_1 = 1;
58712ef9 6622 }
986e0aeb
MC		 6623 spin_lock_bh(&tp->lock);
6624 __tg3_set_mac_addr(tp, skip_mac_1);
6625 spin_unlock_bh(&tp->lock);
1da177e4 6626
b9ec6c1b 6627 return err;
1da177e4
LT		 6628}
6629
6630/* tp->lock is held. */
6631static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6632 dma_addr_t mapping, u32 maxlen_flags,
6633 u32 nic_addr)
6634{
6635 tg3_write_mem(tp,
6636 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6637 ((u64) mapping >> 32));
6638 tg3_write_mem(tp,
6639 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6640 ((u64) mapping & 0xffffffff));
6641 tg3_write_mem(tp,
6642 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6643 maxlen_flags);
6644
6645 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6646 tg3_write_mem(tp,
6647 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6648 nic_addr);
6649}
6650
6651static void __tg3_set_rx_mode(struct net_device *);
d244c892 6652static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6653{
6654 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6655 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6656 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6657 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6658 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6659 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6660 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6661 }
6662 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6663 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6664 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6665 u32 val = ec->stats_block_coalesce_usecs;
6666
6667 if (!netif_carrier_ok(tp->dev))
6668 val = 0;
6669
6670 tw32(HOSTCC_STAT_COAL_TICKS, val);
6671 }
6672}
1da177e4
LT		 6673
6674/* tp->lock is held. */
8e7a22e3 6675static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6676{
6677 u32 val, rdmac_mode;
6678 int i, err, limit;
6679
6680 tg3_disable_ints(tp);
6681
6682 tg3_stop_fw(tp);
6683
6684 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6685
6686 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6687 tg3_abort_hw(tp, 1);
1da177e4
LT		 6688 }
6689
dd477003
MC		 6690 if (reset_phy &&
6691 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6692 tg3_phy_reset(tp);
6693
1da177e4
LT		 6694 err = tg3_chip_reset(tp);
6695 if (err)
6696 return err;
6697
6698 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6699
bcb37f6c 6700 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6701 val = tr32(TG3_CPMU_CTRL);
6702 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6703 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6704
6705 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6706 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6707 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6708 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6709
6710 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6711 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6712 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6713 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6714
6715 val = tr32(TG3_CPMU_HST_ACC);
6716 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6717 val |= CPMU_HST_ACC_MACCLK_6_25;
6718 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6719 }
6720
33466d93
MC		 6721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6722 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6723 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6724 PCIE_PWR_MGMT_L1_THRESH_4MS;
6725 tw32(PCIE_PWR_MGMT_THRESH, val);
6726 }
6727
1da177e4
LT		 6728 /* This works around an issue with Athlon chipsets on
6729 * B3 tigon3 silicon. This bit has no effect on any
6730 * other revision. But do not set this on PCI Express
795d01c5 6731 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6732 */
795d01c5
MC		 6733 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6734 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6735 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6736 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6737 }
1da177e4
LT		 6738
6739 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6740 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6741 val = tr32(TG3PCI_PCISTATE);
6742 val |= PCISTATE_RETRY_SAME_DMA;
6743 tw32(TG3PCI_PCISTATE, val);
6744 }
6745
0d3031d9
MC		 6746 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6747 /* Allow reads and writes to the
6748 * APE register and memory space.
6749 */
6750 val = tr32(TG3PCI_PCISTATE);
6751 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6752 PCISTATE_ALLOW_APE_SHMEM_WR;
6753 tw32(TG3PCI_PCISTATE, val);
6754 }
6755
1da177e4
LT		 6756 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6757 /* Enable some hw fixes. */
6758 val = tr32(TG3PCI_MSI_DATA);
6759 val |= (1 << 26) | (1 << 28) | (1 << 29);
6760 tw32(TG3PCI_MSI_DATA, val);
6761 }
6762
6763 /* Descriptor ring init may make accesses to the
6764 * NIC SRAM area to setup the TX descriptors, so we
6765 * can only do this after the hardware has been
6766 * successfully reset.
6767 */
32d8c572
MC		 6768 err = tg3_init_rings(tp);
6769 if (err)
6770 return err;
1da177e4 6771
9936bcf6 6772 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6773 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6774 /* This value is determined during the probe time DMA
6775 * engine test, tg3_test_dma.
6776 */
6777 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6778 }
1da177e4
LT		 6779
6780 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6781 GRC_MODE_4X_NIC_SEND_RINGS |
6782 GRC_MODE_NO_TX_PHDR_CSUM |
6783 GRC_MODE_NO_RX_PHDR_CSUM);
6784 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6785
6786 /* Pseudo-header checksum is done by hardware logic and not
6787 * the offload processers, so make the chip do the pseudo-
6788 * header checksums on receive. For transmit it is more
6789 * convenient to do the pseudo-header checksum in software
6790 * as Linux does that on transmit for us in all cases.
6791 */
6792 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6793
6794 tw32(GRC_MODE,
6795 tp->grc_mode |
6796 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6797
6798 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6799 val = tr32(GRC_MISC_CFG);
6800 val &= ~0xff;
6801 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6802 tw32(GRC_MISC_CFG, val);
6803
6804 /* Initialize MBUF/DESC pool. */
cbf46853 6805 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6806 /* Do nothing. */
6807 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6808 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6810 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6811 else
6812 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6813 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6814 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6815 }
1da177e4
LT		 6816 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6817 int fw_len;
6818
077f849d 6819 fw_len = tp->fw_len;
1da177e4
LT		 6820 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6821 tw32(BUFMGR_MB_POOL_ADDR,
6822 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6823 tw32(BUFMGR_MB_POOL_SIZE,
6824 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6825 }
1da177e4 6826
0f893dc6 6827 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6828 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6829 tp->bufmgr_config.mbuf_read_dma_low_water);
6830 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6831 tp->bufmgr_config.mbuf_mac_rx_low_water);
6832 tw32(BUFMGR_MB_HIGH_WATER,
6833 tp->bufmgr_config.mbuf_high_water);
6834 } else {
6835 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6836 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6837 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6838 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6839 tw32(BUFMGR_MB_HIGH_WATER,
6840 tp->bufmgr_config.mbuf_high_water_jumbo);
6841 }
6842 tw32(BUFMGR_DMA_LOW_WATER,
6843 tp->bufmgr_config.dma_low_water);
6844 tw32(BUFMGR_DMA_HIGH_WATER,
6845 tp->bufmgr_config.dma_high_water);
6846
6847 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6848 for (i = 0; i < 2000; i++) {
6849 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6850 break;
6851 udelay(10);
6852 }
6853 if (i >= 2000) {
6854 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6855 tp->dev->name);
6856 return -ENODEV;
6857 }
6858
6859 /* Setup replenish threshold. */
f92905de
MC		 6860 val = tp->rx_pending / 8;
6861 if (val == 0)
6862 val = 1;
6863 else if (val > tp->rx_std_max_post)
6864 val = tp->rx_std_max_post;
b5d3772c
MC		 6865 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6866 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6867 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6868
6869 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6870 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6871 }
f92905de
MC		 6872
6873 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6874
6875 /* Initialize TG3_BDINFO's at:
6876 * RCVDBDI_STD_BD: standard eth size rx ring
6877 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6878 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6879 *
6880 * like so:
6881 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6882 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6883 * ring attribute flags
6884 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6885 *
6886 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6887 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6888 *
6889 * The size of each ring is fixed in the firmware, but the location is
6890 * configurable.
6891 */
6892 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6893 ((u64) tp->rx_std_mapping >> 32));
6894 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6895 ((u64) tp->rx_std_mapping & 0xffffffff));
6896 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6897 NIC_SRAM_RX_BUFFER_DESC);
6898
6899 /* Don't even try to program the JUMBO/MINI buffer descriptor
6900 * configs on 5705.
6901 */
6902 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6903 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6904 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6905 } else {
6906 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6907 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6908
6909 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6910 BDINFO_FLAGS_DISABLED);
6911
6912 /* Setup replenish threshold. */
6913 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6914
0f893dc6 6915 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6916 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6917 ((u64) tp->rx_jumbo_mapping >> 32));
6918 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6919 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6920 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6921 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6922 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6923 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6924 } else {
6925 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6926 BDINFO_FLAGS_DISABLED);
6927 }
6928
6929 }
6930
6931 /* There is only one send ring on 5705/5750, no need to explicitly
6932 * disable the others.
6933 */
6934 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6935 /* Clear out send RCB ring in SRAM. */
6936 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6937 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6938 BDINFO_FLAGS_DISABLED);
6939 }
6940
6941 tp->tx_prod = 0;
6942 tp->tx_cons = 0;
6943 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6944 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6945
6946 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6947 tp->tx_desc_mapping,
6948 (TG3_TX_RING_SIZE <<
6949 BDINFO_FLAGS_MAXLEN_SHIFT),
6950 NIC_SRAM_TX_BUFFER_DESC);
6951
6952 /* There is only one receive return ring on 5705/5750, no need
6953 * to explicitly disable the others.
6954 */
6955 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6956 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6957 i += TG3_BDINFO_SIZE) {
6958 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6959 BDINFO_FLAGS_DISABLED);
6960 }
6961 }
6962
6963 tp->rx_rcb_ptr = 0;
6964 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6965
6966 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6967 tp->rx_rcb_mapping,
6968 (TG3_RX_RCB_RING_SIZE(tp) <<
6969 BDINFO_FLAGS_MAXLEN_SHIFT),
6970 0);
6971
6972 tp->rx_std_ptr = tp->rx_pending;
6973 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6974 tp->rx_std_ptr);
6975
0f893dc6 6976 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 6977 tp->rx_jumbo_pending : 0;
6978 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6979 tp->rx_jumbo_ptr);
6980
6981 /* Initialize MAC address and backoff seed. */
986e0aeb 6982 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 6983
6984 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 6985 tw32(MAC_RX_MTU_SIZE,
6986 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 6987
6988 /* The slot time is changed by tg3_setup_phy if we
6989 * run at gigabit with half duplex.
6990 */
6991 tw32(MAC_TX_LENGTHS,
6992 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6993 (6 << TX_LENGTHS_IPG_SHIFT) |
6994 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6995
6996 /* Receive rules. */
6997 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6998 tw32(RCVLPC_CONFIG, 0x0181);
6999
7000 /* Calculate RDMAC_MODE setting early, we need it to determine
7001 * the RCVLPC_STATE_ENABLE mask.
7002 */
7003 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7004 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7005 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7006 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7007 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7008
57e6983c 7009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7012 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7013 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7014 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7015
85e94ced
MC		 7016 /* If statement applies to 5705 and 5750 PCI devices only */
7017 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7018 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7019 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7020 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7021 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7022 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7023 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7024 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7025 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7026 }
7027 }
7028
85e94ced
MC		 7029 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7030 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7031
1da177e4 7032 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7033 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7034
7035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7037 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7038
7039 /* Receive/send statistics. */
1661394e
MC		 7040 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7041 val = tr32(RCVLPC_STATS_ENABLE);
7042 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7043 tw32(RCVLPC_STATS_ENABLE, val);
7044 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7045 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7046 val = tr32(RCVLPC_STATS_ENABLE);
7047 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7048 tw32(RCVLPC_STATS_ENABLE, val);
7049 } else {
7050 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7051 }
7052 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7053 tw32(SNDDATAI_STATSENAB, 0xffffff);
7054 tw32(SNDDATAI_STATSCTRL,
7055 (SNDDATAI_SCTRL_ENABLE |
7056 SNDDATAI_SCTRL_FASTUPD));
7057
7058 /* Setup host coalescing engine. */
7059 tw32(HOSTCC_MODE, 0);
7060 for (i = 0; i < 2000; i++) {
7061 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7062 break;
7063 udelay(10);
7064 }
7065
d244c892 7066 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7067
7068 /* set status block DMA address */
7069 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7070 ((u64) tp->status_mapping >> 32));
7071 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7072 ((u64) tp->status_mapping & 0xffffffff));
7073
7074 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7075 /* Status/statistics block address. See tg3_timer,
7076 * the tg3_periodic_fetch_stats call there, and
7077 * tg3_get_stats to see how this works for 5705/5750 chips.
7078 */
1da177e4
LT		 7079 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7080 ((u64) tp->stats_mapping >> 32));
7081 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7082 ((u64) tp->stats_mapping & 0xffffffff));
7083 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7084 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7085 }
7086
7087 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7088
7089 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7090 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7091 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7092 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7093
7094 /* Clear statistics/status block in chip, and status block in ram. */
7095 for (i = NIC_SRAM_STATS_BLK;
7096 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7097 i += sizeof(u32)) {
7098 tg3_write_mem(tp, i, 0);
7099 udelay(40);
7100 }
7101 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7102
c94e3941
MC		 7103 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7104 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7105 /* reset to prevent losing 1st rx packet intermittently */
7106 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7107 udelay(10);
7108 }
7109
3bda1258
MC		 7110 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7111 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7112 else
7113 tp->mac_mode = 0;
7114 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7115 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7116 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7117 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7118 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7119 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7120 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7121 udelay(40);
7122
314fba34 7123 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7124 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7125 * register to preserve the GPIO settings for LOMs. The GPIOs,
7126 * whether used as inputs or outputs, are set by boot code after
7127 * reset.
7128 */
9d26e213 7129 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7130 u32 gpio_mask;
7131
9d26e213
MC		 7132 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7133 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7134 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7135
7136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7137 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7138 GRC_LCLCTRL_GPIO_OUTPUT3;
7139
af36e6b6
MC		 7140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7141 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7142
aaf84465 7143 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7144 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7145
7146 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7147 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7148 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7149 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7150 }
1da177e4
LT		 7151 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7152 udelay(100);
7153
09ee929c 7154 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
1da177e4
LT		 7155
7156 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7157 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7158 udelay(40);
7159 }
7160
7161 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7162 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7163 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7164 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7165 WDMAC_MODE_LNGREAD_ENAB);
7166
85e94ced
MC		 7167 /* If statement applies to 5705 and 5750 PCI devices only */
7168 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7169 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 7171 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7172 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7173 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7174 /* nothing */
7175 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7176 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7177 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7178 val |= WDMAC_MODE_RX_ACCEL;
7179 }
7180 }
7181
d9ab5ad1 7182 /* Enable host coalescing bug fix */
321d32a0 7183 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7184 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7185
1da177e4
LT		 7186 tw32_f(WDMAC_MODE, val);
7187 udelay(40);
7188
9974a356
MC		 7189 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7190 u16 pcix_cmd;
7191
7192 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7193 &pcix_cmd);
1da177e4 7194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7195 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7196 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7197 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7198 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7199 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7200 }
9974a356
MC		 7201 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7202 pcix_cmd);
1da177e4
LT		 7203 }
7204
7205 tw32_f(RDMAC_MODE, rdmac_mode);
7206 udelay(40);
7207
7208 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7209 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7210 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7211
7212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7213 tw32(SNDDATAC_MODE,
7214 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7215 else
7216 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7217
1da177e4
LT		 7218 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7219 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7220 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7221 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7222 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7223 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7224 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7225 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7226
7227 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7228 err = tg3_load_5701_a0_firmware_fix(tp);
7229 if (err)
7230 return err;
7231 }
7232
1da177e4
LT		 7233 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7234 err = tg3_load_tso_firmware(tp);
7235 if (err)
7236 return err;
7237 }
1da177e4
LT		 7238
7239 tp->tx_mode = TX_MODE_ENABLE;
7240 tw32_f(MAC_TX_MODE, tp->tx_mode);
7241 udelay(100);
7242
7243 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7244 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7245 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7246
1da177e4
LT		 7247 tw32_f(MAC_RX_MODE, tp->rx_mode);
7248 udelay(10);
7249
1da177e4
LT		 7250 tw32(MAC_LED_CTRL, tp->led_ctrl);
7251
7252 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7253 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7254 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7255 udelay(10);
7256 }
7257 tw32_f(MAC_RX_MODE, tp->rx_mode);
7258 udelay(10);
7259
7260 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7261 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7262 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7263 /* Set drive transmission level to 1.2V */
7264 /* only if the signal pre-emphasis bit is not set */
7265 val = tr32(MAC_SERDES_CFG);
7266 val &= 0xfffff000;
7267 val |= 0x880;
7268 tw32(MAC_SERDES_CFG, val);
7269 }
7270 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7271 tw32(MAC_SERDES_CFG, 0x616000);
7272 }
7273
7274 /* Prevent chip from dropping frames when flow control
7275 * is enabled.
7276 */
7277 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7278
7279 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7280 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7281 /* Use hardware link auto-negotiation */
7282 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7283 }
7284
d4d2c558
MC		 7285 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7286 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7287 u32 tmp;
7288
7289 tmp = tr32(SERDES_RX_CTRL);
7290 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7291 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7292 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7293 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7294 }
7295
dd477003
MC		 7296 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7297 if (tp->link_config.phy_is_low_power) {
7298 tp->link_config.phy_is_low_power = 0;
7299 tp->link_config.speed = tp->link_config.orig_speed;
7300 tp->link_config.duplex = tp->link_config.orig_duplex;
7301 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7302 }
1da177e4 7303
dd477003
MC		 7304 err = tg3_setup_phy(tp, 0);
7305 if (err)
7306 return err;
1da177e4 7307
dd477003
MC		 7308 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7309 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7310 u32 tmp;
7311
7312 /* Clear CRC stats. */
7313 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7314 tg3_writephy(tp, MII_TG3_TEST1,
7315 tmp | MII_TG3_TEST1_CRC_EN);
7316 tg3_readphy(tp, 0x14, &tmp);
7317 }
1da177e4
LT		 7318 }
7319 }
7320
7321 __tg3_set_rx_mode(tp->dev);
7322
7323 /* Initialize receive rules. */
7324 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7325 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7326 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7327 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7328
4cf78e4f 7329 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7330 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7331 limit = 8;
7332 else
7333 limit = 16;
7334 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7335 limit -= 4;
7336 switch (limit) {
7337 case 16:
7338 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7339 case 15:
7340 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7341 case 14:
7342 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7343 case 13:
7344 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7345 case 12:
7346 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7347 case 11:
7348 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7349 case 10:
7350 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7351 case 9:
7352 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7353 case 8:
7354 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7355 case 7:
7356 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7357 case 6:
7358 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7359 case 5:
7360 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7361 case 4:
7362 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7363 case 3:
7364 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7365 case 2:
7366 case 1:
7367
7368 default:
7369 break;
855e1111 7370 }
1da177e4 7371
9ce768ea
MC		 7372 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7373 /* Write our heartbeat update interval to APE. */
7374 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7375 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7376
1da177e4
LT		 7377 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7378
1da177e4
LT		 7379 return 0;
7380}
7381
7382/* Called at device open time to get the chip ready for
7383 * packet processing. Invoked with tp->lock held.
7384 */
8e7a22e3 7385static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7386{
1da177e4
LT		 7387 tg3_switch_clocks(tp);
7388
7389 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7390
2f751b67 7391 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7392}
7393
7394#define TG3_STAT_ADD32(PSTAT, REG) \
7395do { u32 __val = tr32(REG); \
7396 (PSTAT)->low += __val; \
7397 if ((PSTAT)->low < __val) \
7398 (PSTAT)->high += 1; \
7399} while (0)
7400
7401static void tg3_periodic_fetch_stats(struct tg3 *tp)
7402{
7403 struct tg3_hw_stats *sp = tp->hw_stats;
7404
7405 if (!netif_carrier_ok(tp->dev))
7406 return;
7407
7408 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7409 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7410 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7411 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7412 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7413 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7414 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7415 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7416 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7417 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7418 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7419 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7420 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7421
7422 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7423 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7424 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7425 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7426 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7427 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7428 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7429 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7430 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7431 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7432 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7433 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7434 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7435 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7436
7437 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7438 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7439 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7440}
7441
7442static void tg3_timer(unsigned long __opaque)
7443{
7444 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7445
f475f163
MC		 7446 if (tp->irq_sync)
7447 goto restart_timer;
7448
f47c11ee 7449 spin_lock(&tp->lock);
1da177e4 7450
fac9b83e
DM		 7451 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7452 /* All of this garbage is because when using non-tagged
7453 * IRQ status the mailbox/status_block protocol the chip
7454 * uses with the cpu is race prone.
7455 */
7456 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7457 tw32(GRC_LOCAL_CTRL,
7458 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7459 } else {
7460 tw32(HOSTCC_MODE, tp->coalesce_mode |
7461 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7462 }
1da177e4 7463
fac9b83e
DM		 7464 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7465 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7466 spin_unlock(&tp->lock);
fac9b83e
DM		 7467 schedule_work(&tp->reset_task);
7468 return;
7469 }
1da177e4
LT		 7470 }
7471
1da177e4
LT		 7472 /* This part only runs once per second. */
7473 if (!--tp->timer_counter) {
fac9b83e
DM		 7474 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7475 tg3_periodic_fetch_stats(tp);
7476
1da177e4
LT		 7477 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7478 u32 mac_stat;
7479 int phy_event;
7480
7481 mac_stat = tr32(MAC_STATUS);
7482
7483 phy_event = 0;
7484 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7485 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7486 phy_event = 1;
7487 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7488 phy_event = 1;
7489
7490 if (phy_event)
7491 tg3_setup_phy(tp, 0);
7492 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7493 u32 mac_stat = tr32(MAC_STATUS);
7494 int need_setup = 0;
7495
7496 if (netif_carrier_ok(tp->dev) &&
7497 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7498 need_setup = 1;
7499 }
7500 if (! netif_carrier_ok(tp->dev) &&
7501 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7502 MAC_STATUS_SIGNAL_DET))) {
7503 need_setup = 1;
7504 }
7505 if (need_setup) {
3d3ebe74
MC		 7506 if (!tp->serdes_counter) {
7507 tw32_f(MAC_MODE,
7508 (tp->mac_mode &
7509 ~MAC_MODE_PORT_MODE_MASK));
7510 udelay(40);
7511 tw32_f(MAC_MODE, tp->mac_mode);
7512 udelay(40);
7513 }
1da177e4
LT		 7514 tg3_setup_phy(tp, 0);
7515 }
747e8f8b
MC		 7516 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7517 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7518
7519 tp->timer_counter = tp->timer_multiplier;
7520 }
7521
130b8e4d
MC		 7522 /* Heartbeat is only sent once every 2 seconds.
7523 *
7524 * The heartbeat is to tell the ASF firmware that the host
7525 * driver is still alive. In the event that the OS crashes,
7526 * ASF needs to reset the hardware to free up the FIFO space
7527 * that may be filled with rx packets destined for the host.
7528 * If the FIFO is full, ASF will no longer function properly.
7529 *
7530 * Unintended resets have been reported on real time kernels
7531 * where the timer doesn't run on time. Netpoll will also have
7532 * same problem.
7533 *
7534 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7535 * to check the ring condition when the heartbeat is expiring
7536 * before doing the reset. This will prevent most unintended
7537 * resets.
7538 */
1da177e4 7539 if (!--tp->asf_counter) {
bc7959b2
MC		 7540 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7541 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7542 tg3_wait_for_event_ack(tp);
7543
bbadf503 7544 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7545 FWCMD_NICDRV_ALIVE3);
bbadf503 7546 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7547 /* 5 seconds timeout */
bbadf503 7548 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7549
7550 tg3_generate_fw_event(tp);
1da177e4
LT		 7551 }
7552 tp->asf_counter = tp->asf_multiplier;
7553 }
7554
f47c11ee 7555 spin_unlock(&tp->lock);
1da177e4 7556
f475f163 7557restart_timer:
1da177e4
LT		 7558 tp->timer.expires = jiffies + tp->timer_offset;
7559 add_timer(&tp->timer);
7560}
7561
81789ef5 7562static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7563{
7d12e780 7564 irq_handler_t fn;
fcfa0a32
MC		 7565 unsigned long flags;
7566 struct net_device *dev = tp->dev;
7567
7568 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7569 fn = tg3_msi;
7570 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7571 fn = tg3_msi_1shot;
1fb9df5d 7572 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7573 } else {
7574 fn = tg3_interrupt;
7575 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7576 fn = tg3_interrupt_tagged;
1fb9df5d 7577 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7578 }
7579 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7580}
7581
7938109f
MC		 7582static int tg3_test_interrupt(struct tg3 *tp)
7583{
7584 struct net_device *dev = tp->dev;
b16250e3 7585 int err, i, intr_ok = 0;
7938109f 7586
d4bc3927
MC		 7587 if (!netif_running(dev))
7588 return -ENODEV;
7589
7938109f
MC		 7590 tg3_disable_ints(tp);
7591
7592 free_irq(tp->pdev->irq, dev);
7593
7594 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7595 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7596 if (err)
7597 return err;
7598
38f3843e 7599 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7600 tg3_enable_ints(tp);
7601
7602 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7603 HOSTCC_MODE_NOW);
7604
7605 for (i = 0; i < 5; i++) {
b16250e3
MC		 7606 u32 int_mbox, misc_host_ctrl;
7607
09ee929c
MC		 7608 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7609 TG3_64BIT_REG_LOW);
b16250e3
MC		 7610 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7611
7612 if ((int_mbox != 0) ||
7613 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7614 intr_ok = 1;
7938109f 7615 break;
b16250e3
MC		 7616 }
7617
7938109f
MC		 7618 msleep(10);
7619 }
7620
7621 tg3_disable_ints(tp);
7622
7623 free_irq(tp->pdev->irq, dev);
6aa20a22 7624
fcfa0a32 7625 err = tg3_request_irq(tp);
7938109f
MC		 7626
7627 if (err)
7628 return err;
7629
b16250e3 7630 if (intr_ok)
7938109f
MC		 7631 return 0;
7632
7633 return -EIO;
7634}
7635
7636/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7637 * successfully restored
7638 */
7639static int tg3_test_msi(struct tg3 *tp)
7640{
7641 struct net_device *dev = tp->dev;
7642 int err;
7643 u16 pci_cmd;
7644
7645 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7646 return 0;
7647
7648 /* Turn off SERR reporting in case MSI terminates with Master
7649 * Abort.
7650 */
7651 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7652 pci_write_config_word(tp->pdev, PCI_COMMAND,
7653 pci_cmd & ~PCI_COMMAND_SERR);
7654
7655 err = tg3_test_interrupt(tp);
7656
7657 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7658
7659 if (!err)
7660 return 0;
7661
7662 /* other failures */
7663 if (err != -EIO)
7664 return err;
7665
7666 /* MSI test failed, go back to INTx mode */
7667 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7668 "switching to INTx mode. Please report this failure to "
7669 "the PCI maintainer and include system chipset information.\n",
7670 tp->dev->name);
7671
7672 free_irq(tp->pdev->irq, dev);
7673 pci_disable_msi(tp->pdev);
7674
7675 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7676
fcfa0a32 7677 err = tg3_request_irq(tp);
7938109f
MC		 7678 if (err)
7679 return err;
7680
7681 /* Need to reset the chip because the MSI cycle may have terminated
7682 * with Master Abort.
7683 */
f47c11ee 7684 tg3_full_lock(tp, 1);
7938109f 7685
944d980e 7686 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7687 err = tg3_init_hw(tp, 1);
7938109f 7688
f47c11ee 7689 tg3_full_unlock(tp);
7938109f
MC		 7690
7691 if (err)
7692 free_irq(tp->pdev->irq, dev);
7693
7694 return err;
7695}
7696
9e9fd12d
MC		 7697static int tg3_request_firmware(struct tg3 *tp)
7698{
7699 const __be32 *fw_data;
7700
7701 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7702 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7703 tp->dev->name, tp->fw_needed);
7704 return -ENOENT;
7705 }
7706
7707 fw_data = (void *)tp->fw->data;
7708
7709 /* Firmware blob starts with version numbers, followed by
7710 * start address and _full_ length including BSS sections
7711 * (which must be longer than the actual data, of course
7712 */
7713
7714 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7715 if (tp->fw_len < (tp->fw->size - 12)) {
7716 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7717 tp->dev->name, tp->fw_len, tp->fw_needed);
7718 release_firmware(tp->fw);
7719 tp->fw = NULL;
7720 return -EINVAL;
7721 }
7722
7723 /* We no longer need firmware; we have it. */
7724 tp->fw_needed = NULL;
7725 return 0;
7726}
7727
1da177e4
LT		 7728static int tg3_open(struct net_device *dev)
7729{
7730 struct tg3 *tp = netdev_priv(dev);
7731 int err;
7732
9e9fd12d
MC		 7733 if (tp->fw_needed) {
7734 err = tg3_request_firmware(tp);
7735 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7736 if (err)
7737 return err;
7738 } else if (err) {
7739 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7740 tp->dev->name);
7741 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7742 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7743 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7744 tp->dev->name);
7745 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7746 }
7747 }
7748
c49a1561
MC		 7749 netif_carrier_off(tp->dev);
7750
bc1c7567 7751 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7752 if (err)
bc1c7567 7753 return err;
2f751b67
MC		 7754
7755 tg3_full_lock(tp, 0);
bc1c7567 7756
1da177e4
LT		 7757 tg3_disable_ints(tp);
7758 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7759
f47c11ee 7760 tg3_full_unlock(tp);
1da177e4
LT		 7761
7762 /* The placement of this call is tied
7763 * to the setup and use of Host TX descriptors.
7764 */
7765 err = tg3_alloc_consistent(tp);
7766 if (err)
7767 return err;
7768
7544b097 7769 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7770 /* All MSI supporting chips should support tagged
7771 * status. Assert that this is the case.
7772 */
7773 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7774 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7775 "Not using MSI.\n", tp->dev->name);
7776 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7777 u32 msi_mode;
7778
7779 msi_mode = tr32(MSGINT_MODE);
7780 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7781 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7782 }
7783 }
fcfa0a32 7784 err = tg3_request_irq(tp);
1da177e4
LT		 7785
7786 if (err) {
88b06bc2
MC		 7787 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7788 pci_disable_msi(tp->pdev);
7789 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7790 }
1da177e4
LT		 7791 tg3_free_consistent(tp);
7792 return err;
7793 }
7794
bea3348e
SH		 7795 napi_enable(&tp->napi);
7796
f47c11ee 7797 tg3_full_lock(tp, 0);
1da177e4 7798
8e7a22e3 7799 err = tg3_init_hw(tp, 1);
1da177e4 7800 if (err) {
944d980e 7801 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7802 tg3_free_rings(tp);
7803 } else {
fac9b83e
DM		 7804 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7805 tp->timer_offset = HZ;
7806 else
7807 tp->timer_offset = HZ / 10;
7808
7809 BUG_ON(tp->timer_offset > HZ);
7810 tp->timer_counter = tp->timer_multiplier =
7811 (HZ / tp->timer_offset);
7812 tp->asf_counter = tp->asf_multiplier =
28fbef78 7813 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7814
7815 init_timer(&tp->timer);
7816 tp->timer.expires = jiffies + tp->timer_offset;
7817 tp->timer.data = (unsigned long) tp;
7818 tp->timer.function = tg3_timer;
1da177e4
LT		 7819 }
7820
f47c11ee 7821 tg3_full_unlock(tp);
1da177e4
LT		 7822
7823 if (err) {
bea3348e 7824 napi_disable(&tp->napi);
88b06bc2
MC		 7825 free_irq(tp->pdev->irq, dev);
7826 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7827 pci_disable_msi(tp->pdev);
7828 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7829 }
1da177e4
LT		 7830 tg3_free_consistent(tp);
7831 return err;
7832 }
7833
7938109f
MC		 7834 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7835 err = tg3_test_msi(tp);
fac9b83e 7836
7938109f 7837 if (err) {
f47c11ee 7838 tg3_full_lock(tp, 0);
7938109f
MC		 7839
7840 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7841 pci_disable_msi(tp->pdev);
7842 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7843 }
944d980e 7844 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7845 tg3_free_rings(tp);
7846 tg3_free_consistent(tp);
7847
f47c11ee 7848 tg3_full_unlock(tp);
7938109f 7849
bea3348e
SH		 7850 napi_disable(&tp->napi);
7851
7938109f
MC		 7852 return err;
7853 }
fcfa0a32
MC		 7854
7855 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7856 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7857 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7858
b5d3772c
MC		 7859 tw32(PCIE_TRANSACTION_CFG,
7860 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7861 }
7862 }
7938109f
MC		 7863 }
7864
b02fd9e3
MC		 7865 tg3_phy_start(tp);
7866
f47c11ee 7867 tg3_full_lock(tp, 0);
1da177e4 7868
7938109f
MC		 7869 add_timer(&tp->timer);
7870 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7871 tg3_enable_ints(tp);
7872
f47c11ee 7873 tg3_full_unlock(tp);
1da177e4
LT		 7874
7875 netif_start_queue(dev);
7876
7877 return 0;
7878}
7879
7880#if 0
7881/*static*/ void tg3_dump_state(struct tg3 *tp)
7882{
7883 u32 val32, val32_2, val32_3, val32_4, val32_5;
7884 u16 val16;
7885 int i;
7886
7887 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7888 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7889 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7890 val16, val32);
7891
7892 /* MAC block */
7893 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7894 tr32(MAC_MODE), tr32(MAC_STATUS));
7895 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7896 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7897 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7898 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7899 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7900 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7901
7902 /* Send data initiator control block */
7903 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7904 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7905 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7906 tr32(SNDDATAI_STATSCTRL));
7907
7908 /* Send data completion control block */
7909 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7910
7911 /* Send BD ring selector block */
7912 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7913 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7914
7915 /* Send BD initiator control block */
7916 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7917 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7918
7919 /* Send BD completion control block */
7920 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7921
7922 /* Receive list placement control block */
7923 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7924 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7925 printk(" RCVLPC_STATSCTRL[%08x]\n",
7926 tr32(RCVLPC_STATSCTRL));
7927
7928 /* Receive data and receive BD initiator control block */
7929 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7930 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7931
7932 /* Receive data completion control block */
7933 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7934 tr32(RCVDCC_MODE));
7935
7936 /* Receive BD initiator control block */
7937 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7938 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7939
7940 /* Receive BD completion control block */
7941 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7942 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7943
7944 /* Receive list selector control block */
7945 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7946 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7947
7948 /* Mbuf cluster free block */
7949 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7950 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7951
7952 /* Host coalescing control block */
7953 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7954 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7955 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7956 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7957 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7958 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7959 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7960 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7961 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7962 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7963 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7964 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7965
7966 /* Memory arbiter control block */
7967 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7968 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7969
7970 /* Buffer manager control block */
7971 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7972 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7973 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7974 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7975 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7976 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7977 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7978 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7979
7980 /* Read DMA control block */
7981 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7982 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7983
7984 /* Write DMA control block */
7985 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7986 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7987
7988 /* DMA completion block */
7989 printk("DEBUG: DMAC_MODE[%08x]\n",
7990 tr32(DMAC_MODE));
7991
7992 /* GRC block */
7993 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7994 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7995 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7996 tr32(GRC_LOCAL_CTRL));
7997
7998 /* TG3_BDINFOs */
7999 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8000 tr32(RCVDBDI_JUMBO_BD + 0x0),
8001 tr32(RCVDBDI_JUMBO_BD + 0x4),
8002 tr32(RCVDBDI_JUMBO_BD + 0x8),
8003 tr32(RCVDBDI_JUMBO_BD + 0xc));
8004 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8005 tr32(RCVDBDI_STD_BD + 0x0),
8006 tr32(RCVDBDI_STD_BD + 0x4),
8007 tr32(RCVDBDI_STD_BD + 0x8),
8008 tr32(RCVDBDI_STD_BD + 0xc));
8009 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8010 tr32(RCVDBDI_MINI_BD + 0x0),
8011 tr32(RCVDBDI_MINI_BD + 0x4),
8012 tr32(RCVDBDI_MINI_BD + 0x8),
8013 tr32(RCVDBDI_MINI_BD + 0xc));
8014
8015 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8016 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8017 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8018 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8019 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8020 val32, val32_2, val32_3, val32_4);
8021
8022 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8023 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8024 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8025 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8026 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8027 val32, val32_2, val32_3, val32_4);
8028
8029 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8030 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8031 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8032 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8033 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8034 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8035 val32, val32_2, val32_3, val32_4, val32_5);
8036
8037 /* SW status block */
8038 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8039 tp->hw_status->status,
8040 tp->hw_status->status_tag,
8041 tp->hw_status->rx_jumbo_consumer,
8042 tp->hw_status->rx_consumer,
8043 tp->hw_status->rx_mini_consumer,
8044 tp->hw_status->idx[0].rx_producer,
8045 tp->hw_status->idx[0].tx_consumer);
8046
8047 /* SW statistics block */
8048 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8049 ((u32 *)tp->hw_stats)[0],
8050 ((u32 *)tp->hw_stats)[1],
8051 ((u32 *)tp->hw_stats)[2],
8052 ((u32 *)tp->hw_stats)[3]);
8053
8054 /* Mailboxes */
8055 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8056 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8057 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8058 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8059 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8060
8061 /* NIC side send descriptors. */
8062 for (i = 0; i < 6; i++) {
8063 unsigned long txd;
8064
8065 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8066 + (i * sizeof(struct tg3_tx_buffer_desc));
8067 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8068 i,
8069 readl(txd + 0x0), readl(txd + 0x4),
8070 readl(txd + 0x8), readl(txd + 0xc));
8071 }
8072
8073 /* NIC side RX descriptors. */
8074 for (i = 0; i < 6; i++) {
8075 unsigned long rxd;
8076
8077 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8078 + (i * sizeof(struct tg3_rx_buffer_desc));
8079 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8080 i,
8081 readl(rxd + 0x0), readl(rxd + 0x4),
8082 readl(rxd + 0x8), readl(rxd + 0xc));
8083 rxd += (4 * sizeof(u32));
8084 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8085 i,
8086 readl(rxd + 0x0), readl(rxd + 0x4),
8087 readl(rxd + 0x8), readl(rxd + 0xc));
8088 }
8089
8090 for (i = 0; i < 6; i++) {
8091 unsigned long rxd;
8092
8093 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8094 + (i * sizeof(struct tg3_rx_buffer_desc));
8095 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8096 i,
8097 readl(rxd + 0x0), readl(rxd + 0x4),
8098 readl(rxd + 0x8), readl(rxd + 0xc));
8099 rxd += (4 * sizeof(u32));
8100 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8101 i,
8102 readl(rxd + 0x0), readl(rxd + 0x4),
8103 readl(rxd + 0x8), readl(rxd + 0xc));
8104 }
8105}
8106#endif
8107
8108static struct net_device_stats *tg3_get_stats(struct net_device *);
8109static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8110
8111static int tg3_close(struct net_device *dev)
8112{
8113 struct tg3 *tp = netdev_priv(dev);
8114
bea3348e 8115 napi_disable(&tp->napi);
28e53bdd 8116 cancel_work_sync(&tp->reset_task);
7faa006f 8117
1da177e4
LT		 8118 netif_stop_queue(dev);
8119
8120 del_timer_sync(&tp->timer);
8121
f47c11ee 8122 tg3_full_lock(tp, 1);
1da177e4
LT		 8123#if 0
8124 tg3_dump_state(tp);
8125#endif
8126
8127 tg3_disable_ints(tp);
8128
944d980e 8129 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8130 tg3_free_rings(tp);
5cf64b8a 8131 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8132
f47c11ee 8133 tg3_full_unlock(tp);
1da177e4 8134
88b06bc2
MC		 8135 free_irq(tp->pdev->irq, dev);
8136 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8137 pci_disable_msi(tp->pdev);
8138 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8139 }
1da177e4
LT		 8140
8141 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8142 sizeof(tp->net_stats_prev));
8143 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8144 sizeof(tp->estats_prev));
8145
8146 tg3_free_consistent(tp);
8147
bc1c7567
MC		 8148 tg3_set_power_state(tp, PCI_D3hot);
8149
8150 netif_carrier_off(tp->dev);
8151
1da177e4
LT		 8152 return 0;
8153}
8154
8155static inline unsigned long get_stat64(tg3_stat64_t *val)
8156{
8157 unsigned long ret;
8158
8159#if (BITS_PER_LONG == 32)
8160 ret = val->low;
8161#else
8162 ret = ((u64)val->high << 32) | ((u64)val->low);
8163#endif
8164 return ret;
8165}
8166
816f8b86
SB		 8167static inline u64 get_estat64(tg3_stat64_t *val)
8168{
8169 return ((u64)val->high << 32) | ((u64)val->low);
8170}
8171
1da177e4
LT		 8172static unsigned long calc_crc_errors(struct tg3 *tp)
8173{
8174 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8175
8176 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8177 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8178 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8179 u32 val;
8180
f47c11ee 8181 spin_lock_bh(&tp->lock);
569a5df8
MC		 8182 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8183 tg3_writephy(tp, MII_TG3_TEST1,
8184 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8185 tg3_readphy(tp, 0x14, &val);
8186 } else
8187 val = 0;
f47c11ee 8188 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8189
8190 tp->phy_crc_errors += val;
8191
8192 return tp->phy_crc_errors;
8193 }
8194
8195 return get_stat64(&hw_stats->rx_fcs_errors);
8196}
8197
8198#define ESTAT_ADD(member) \
8199 estats->member = old_estats->member + \
816f8b86 8200 get_estat64(&hw_stats->member)
1da177e4
LT		 8201
8202static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8203{
8204 struct tg3_ethtool_stats *estats = &tp->estats;
8205 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8206 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8207
8208 if (!hw_stats)
8209 return old_estats;
8210
8211 ESTAT_ADD(rx_octets);
8212 ESTAT_ADD(rx_fragments);
8213 ESTAT_ADD(rx_ucast_packets);
8214 ESTAT_ADD(rx_mcast_packets);
8215 ESTAT_ADD(rx_bcast_packets);
8216 ESTAT_ADD(rx_fcs_errors);
8217 ESTAT_ADD(rx_align_errors);
8218 ESTAT_ADD(rx_xon_pause_rcvd);
8219 ESTAT_ADD(rx_xoff_pause_rcvd);
8220 ESTAT_ADD(rx_mac_ctrl_rcvd);
8221 ESTAT_ADD(rx_xoff_entered);
8222 ESTAT_ADD(rx_frame_too_long_errors);
8223 ESTAT_ADD(rx_jabbers);
8224 ESTAT_ADD(rx_undersize_packets);
8225 ESTAT_ADD(rx_in_length_errors);
8226 ESTAT_ADD(rx_out_length_errors);
8227 ESTAT_ADD(rx_64_or_less_octet_packets);
8228 ESTAT_ADD(rx_65_to_127_octet_packets);
8229 ESTAT_ADD(rx_128_to_255_octet_packets);
8230 ESTAT_ADD(rx_256_to_511_octet_packets);
8231 ESTAT_ADD(rx_512_to_1023_octet_packets);
8232 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8233 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8234 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8235 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8236 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8237
8238 ESTAT_ADD(tx_octets);
8239 ESTAT_ADD(tx_collisions);
8240 ESTAT_ADD(tx_xon_sent);
8241 ESTAT_ADD(tx_xoff_sent);
8242 ESTAT_ADD(tx_flow_control);
8243 ESTAT_ADD(tx_mac_errors);
8244 ESTAT_ADD(tx_single_collisions);
8245 ESTAT_ADD(tx_mult_collisions);
8246 ESTAT_ADD(tx_deferred);
8247 ESTAT_ADD(tx_excessive_collisions);
8248 ESTAT_ADD(tx_late_collisions);
8249 ESTAT_ADD(tx_collide_2times);
8250 ESTAT_ADD(tx_collide_3times);
8251 ESTAT_ADD(tx_collide_4times);
8252 ESTAT_ADD(tx_collide_5times);
8253 ESTAT_ADD(tx_collide_6times);
8254 ESTAT_ADD(tx_collide_7times);
8255 ESTAT_ADD(tx_collide_8times);
8256 ESTAT_ADD(tx_collide_9times);
8257 ESTAT_ADD(tx_collide_10times);
8258 ESTAT_ADD(tx_collide_11times);
8259 ESTAT_ADD(tx_collide_12times);
8260 ESTAT_ADD(tx_collide_13times);
8261 ESTAT_ADD(tx_collide_14times);
8262 ESTAT_ADD(tx_collide_15times);
8263 ESTAT_ADD(tx_ucast_packets);
8264 ESTAT_ADD(tx_mcast_packets);
8265 ESTAT_ADD(tx_bcast_packets);
8266 ESTAT_ADD(tx_carrier_sense_errors);
8267 ESTAT_ADD(tx_discards);
8268 ESTAT_ADD(tx_errors);
8269
8270 ESTAT_ADD(dma_writeq_full);
8271 ESTAT_ADD(dma_write_prioq_full);
8272 ESTAT_ADD(rxbds_empty);
8273 ESTAT_ADD(rx_discards);
8274 ESTAT_ADD(rx_errors);
8275 ESTAT_ADD(rx_threshold_hit);
8276
8277 ESTAT_ADD(dma_readq_full);
8278 ESTAT_ADD(dma_read_prioq_full);
8279 ESTAT_ADD(tx_comp_queue_full);
8280
8281 ESTAT_ADD(ring_set_send_prod_index);
8282 ESTAT_ADD(ring_status_update);
8283 ESTAT_ADD(nic_irqs);
8284 ESTAT_ADD(nic_avoided_irqs);
8285 ESTAT_ADD(nic_tx_threshold_hit);
8286
8287 return estats;
8288}
8289
8290static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8291{
8292 struct tg3 *tp = netdev_priv(dev);
8293 struct net_device_stats *stats = &tp->net_stats;
8294 struct net_device_stats *old_stats = &tp->net_stats_prev;
8295 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8296
8297 if (!hw_stats)
8298 return old_stats;
8299
8300 stats->rx_packets = old_stats->rx_packets +
8301 get_stat64(&hw_stats->rx_ucast_packets) +
8302 get_stat64(&hw_stats->rx_mcast_packets) +
8303 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8304
1da177e4
LT		 8305 stats->tx_packets = old_stats->tx_packets +
8306 get_stat64(&hw_stats->tx_ucast_packets) +
8307 get_stat64(&hw_stats->tx_mcast_packets) +
8308 get_stat64(&hw_stats->tx_bcast_packets);
8309
8310 stats->rx_bytes = old_stats->rx_bytes +
8311 get_stat64(&hw_stats->rx_octets);
8312 stats->tx_bytes = old_stats->tx_bytes +
8313 get_stat64(&hw_stats->tx_octets);
8314
8315 stats->rx_errors = old_stats->rx_errors +
4f63b877 8316 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8317 stats->tx_errors = old_stats->tx_errors +
8318 get_stat64(&hw_stats->tx_errors) +
8319 get_stat64(&hw_stats->tx_mac_errors) +
8320 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8321 get_stat64(&hw_stats->tx_discards);
8322
8323 stats->multicast = old_stats->multicast +
8324 get_stat64(&hw_stats->rx_mcast_packets);
8325 stats->collisions = old_stats->collisions +
8326 get_stat64(&hw_stats->tx_collisions);
8327
8328 stats->rx_length_errors = old_stats->rx_length_errors +
8329 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8330 get_stat64(&hw_stats->rx_undersize_packets);
8331
8332 stats->rx_over_errors = old_stats->rx_over_errors +
8333 get_stat64(&hw_stats->rxbds_empty);
8334 stats->rx_frame_errors = old_stats->rx_frame_errors +
8335 get_stat64(&hw_stats->rx_align_errors);
8336 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8337 get_stat64(&hw_stats->tx_discards);
8338 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8339 get_stat64(&hw_stats->tx_carrier_sense_errors);
8340
8341 stats->rx_crc_errors = old_stats->rx_crc_errors +
8342 calc_crc_errors(tp);
8343
4f63b877
JL		 8344 stats->rx_missed_errors = old_stats->rx_missed_errors +
8345 get_stat64(&hw_stats->rx_discards);
8346
1da177e4
LT		 8347 return stats;
8348}
8349
8350static inline u32 calc_crc(unsigned char *buf, int len)
8351{
8352 u32 reg;
8353 u32 tmp;
8354 int j, k;
8355
8356 reg = 0xffffffff;
8357
8358 for (j = 0; j < len; j++) {
8359 reg ^= buf[j];
8360
8361 for (k = 0; k < 8; k++) {
8362 tmp = reg & 0x01;
8363
8364 reg >>= 1;
8365
8366 if (tmp) {
8367 reg ^= 0xedb88320;
8368 }
8369 }
8370 }
8371
8372 return ~reg;
8373}
8374
8375static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8376{
8377 /* accept or reject all multicast frames */
8378 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8379 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8380 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8381 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8382}
8383
8384static void __tg3_set_rx_mode(struct net_device *dev)
8385{
8386 struct tg3 *tp = netdev_priv(dev);
8387 u32 rx_mode;
8388
8389 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8390 RX_MODE_KEEP_VLAN_TAG);
8391
8392 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8393 * flag clear.
8394 */
8395#if TG3_VLAN_TAG_USED
8396 if (!tp->vlgrp &&
8397 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8398 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8399#else
8400 /* By definition, VLAN is disabled always in this
8401 * case.
8402 */
8403 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8404 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8405#endif
8406
8407 if (dev->flags & IFF_PROMISC) {
8408 /* Promiscuous mode. */
8409 rx_mode |= RX_MODE_PROMISC;
8410 } else if (dev->flags & IFF_ALLMULTI) {
8411 /* Accept all multicast. */
8412 tg3_set_multi (tp, 1);
8413 } else if (dev->mc_count < 1) {
8414 /* Reject all multicast. */
8415 tg3_set_multi (tp, 0);
8416 } else {
8417 /* Accept one or more multicast(s). */
8418 struct dev_mc_list *mclist;
8419 unsigned int i;
8420 u32 mc_filter[4] = { 0, };
8421 u32 regidx;
8422 u32 bit;
8423 u32 crc;
8424
8425 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8426 i++, mclist = mclist->next) {
8427
8428 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8429 bit = ~crc & 0x7f;
8430 regidx = (bit & 0x60) >> 5;
8431 bit &= 0x1f;
8432 mc_filter[regidx] |= (1 << bit);
8433 }
8434
8435 tw32(MAC_HASH_REG_0, mc_filter[0]);
8436 tw32(MAC_HASH_REG_1, mc_filter[1]);
8437 tw32(MAC_HASH_REG_2, mc_filter[2]);
8438 tw32(MAC_HASH_REG_3, mc_filter[3]);
8439 }
8440
8441 if (rx_mode != tp->rx_mode) {
8442 tp->rx_mode = rx_mode;
8443 tw32_f(MAC_RX_MODE, rx_mode);
8444 udelay(10);
8445 }
8446}
8447
8448static void tg3_set_rx_mode(struct net_device *dev)
8449{
8450 struct tg3 *tp = netdev_priv(dev);
8451
e75f7c90
MC		 8452 if (!netif_running(dev))
8453 return;
8454
f47c11ee 8455 tg3_full_lock(tp, 0);
1da177e4 8456 __tg3_set_rx_mode(dev);
f47c11ee 8457 tg3_full_unlock(tp);
1da177e4
LT		 8458}
8459
8460#define TG3_REGDUMP_LEN (32 * 1024)
8461
8462static int tg3_get_regs_len(struct net_device *dev)
8463{
8464 return TG3_REGDUMP_LEN;
8465}
8466
8467static void tg3_get_regs(struct net_device *dev,
8468 struct ethtool_regs *regs, void *_p)
8469{
8470 u32 *p = _p;
8471 struct tg3 *tp = netdev_priv(dev);
8472 u8 *orig_p = _p;
8473 int i;
8474
8475 regs->version = 0;
8476
8477 memset(p, 0, TG3_REGDUMP_LEN);
8478
bc1c7567
MC		 8479 if (tp->link_config.phy_is_low_power)
8480 return;
8481
f47c11ee 8482 tg3_full_lock(tp, 0);
1da177e4
LT		 8483
8484#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8485#define GET_REG32_LOOP(base,len) \
8486do { p = (u32 *)(orig_p + (base)); \
8487 for (i = 0; i < len; i += 4) \
8488 __GET_REG32((base) + i); \
8489} while (0)
8490#define GET_REG32_1(reg) \
8491do { p = (u32 *)(orig_p + (reg)); \
8492 __GET_REG32((reg)); \
8493} while (0)
8494
8495 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8496 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8497 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8498 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8499 GET_REG32_1(SNDDATAC_MODE);
8500 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8501 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8502 GET_REG32_1(SNDBDC_MODE);
8503 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8504 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8505 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8506 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8507 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8508 GET_REG32_1(RCVDCC_MODE);
8509 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8510 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8511 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8512 GET_REG32_1(MBFREE_MODE);
8513 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8514 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8515 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8516 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8517 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8518 GET_REG32_1(RX_CPU_MODE);
8519 GET_REG32_1(RX_CPU_STATE);
8520 GET_REG32_1(RX_CPU_PGMCTR);
8521 GET_REG32_1(RX_CPU_HWBKPT);
8522 GET_REG32_1(TX_CPU_MODE);
8523 GET_REG32_1(TX_CPU_STATE);
8524 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8525 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8526 GET_REG32_LOOP(FTQ_RESET, 0x120);
8527 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8528 GET_REG32_1(DMAC_MODE);
8529 GET_REG32_LOOP(GRC_MODE, 0x4c);
8530 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8531 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8532
8533#undef __GET_REG32
8534#undef GET_REG32_LOOP
8535#undef GET_REG32_1
8536
f47c11ee 8537 tg3_full_unlock(tp);
1da177e4
LT		 8538}
8539
8540static int tg3_get_eeprom_len(struct net_device *dev)
8541{
8542 struct tg3 *tp = netdev_priv(dev);
8543
8544 return tp->nvram_size;
8545}
8546
1da177e4
LT		 8547static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8548{
8549 struct tg3 *tp = netdev_priv(dev);
8550 int ret;
8551 u8 *pd;
b9fc7dc5 8552 u32 i, offset, len, b_offset, b_count;
a9dc529d 8553 __be32 val;
1da177e4 8554
df259d8c
MC		 8555 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8556 return -EINVAL;
8557
bc1c7567
MC		 8558 if (tp->link_config.phy_is_low_power)
8559 return -EAGAIN;
8560
1da177e4
LT		 8561 offset = eeprom->offset;
8562 len = eeprom->len;
8563 eeprom->len = 0;
8564
8565 eeprom->magic = TG3_EEPROM_MAGIC;
8566
8567 if (offset & 3) {
8568 /* adjustments to start on required 4 byte boundary */
8569 b_offset = offset & 3;
8570 b_count = 4 - b_offset;
8571 if (b_count > len) {
8572 /* i.e. offset=1 len=2 */
8573 b_count = len;
8574 }
a9dc529d 8575 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8576 if (ret)
8577 return ret;
1da177e4
LT		 8578 memcpy(data, ((char*)&val) + b_offset, b_count);
8579 len -= b_count;
8580 offset += b_count;
8581 eeprom->len += b_count;
8582 }
8583
8584 /* read bytes upto the last 4 byte boundary */
8585 pd = &data[eeprom->len];
8586 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8587 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8588 if (ret) {
8589 eeprom->len += i;
8590 return ret;
8591 }
1da177e4
LT		 8592 memcpy(pd + i, &val, 4);
8593 }
8594 eeprom->len += i;
8595
8596 if (len & 3) {
8597 /* read last bytes not ending on 4 byte boundary */
8598 pd = &data[eeprom->len];
8599 b_count = len & 3;
8600 b_offset = offset + len - b_count;
a9dc529d 8601 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8602 if (ret)
8603 return ret;
b9fc7dc5 8604 memcpy(pd, &val, b_count);
1da177e4
LT		 8605 eeprom->len += b_count;
8606 }
8607 return 0;
8608}
8609
6aa20a22 8610static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8611
8612static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8613{
8614 struct tg3 *tp = netdev_priv(dev);
8615 int ret;
b9fc7dc5 8616 u32 offset, len, b_offset, odd_len;
1da177e4 8617 u8 *buf;
a9dc529d 8618 __be32 start, end;
1da177e4 8619
bc1c7567
MC		 8620 if (tp->link_config.phy_is_low_power)
8621 return -EAGAIN;
8622
df259d8c
MC		 8623 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8624 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 8625 return -EINVAL;
8626
8627 offset = eeprom->offset;
8628 len = eeprom->len;
8629
8630 if ((b_offset = (offset & 3))) {
8631 /* adjustments to start on required 4 byte boundary */
a9dc529d 8632 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8633 if (ret)
8634 return ret;
1da177e4
LT		 8635 len += b_offset;
8636 offset &= ~3;
1c8594b4
MC		 8637 if (len < 4)
8638 len = 4;
1da177e4
LT		 8639 }
8640
8641 odd_len = 0;
1c8594b4 8642 if (len & 3) {
1da177e4
LT		 8643 /* adjustments to end on required 4 byte boundary */
8644 odd_len = 1;
8645 len = (len + 3) & ~3;
a9dc529d 8646 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8647 if (ret)
8648 return ret;
1da177e4
LT		 8649 }
8650
8651 buf = data;
8652 if (b_offset || odd_len) {
8653 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8654 if (!buf)
1da177e4
LT		 8655 return -ENOMEM;
8656 if (b_offset)
8657 memcpy(buf, &start, 4);
8658 if (odd_len)
8659 memcpy(buf+len-4, &end, 4);
8660 memcpy(buf + b_offset, data, eeprom->len);
8661 }
8662
8663 ret = tg3_nvram_write_block(tp, offset, len, buf);
8664
8665 if (buf != data)
8666 kfree(buf);
8667
8668 return ret;
8669}
8670
8671static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8672{
b02fd9e3
MC		 8673 struct tg3 *tp = netdev_priv(dev);
8674
8675 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8676 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8677 return -EAGAIN;
298cf9be 8678 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8679 }
6aa20a22 8680
1da177e4
LT		 8681 cmd->supported = (SUPPORTED_Autoneg);
8682
8683 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8684 cmd->supported |= (SUPPORTED_1000baseT_Half |
8685 SUPPORTED_1000baseT_Full);
8686
ef348144 8687 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8688 cmd->supported |= (SUPPORTED_100baseT_Half |
8689 SUPPORTED_100baseT_Full |
8690 SUPPORTED_10baseT_Half |
8691 SUPPORTED_10baseT_Full |
3bebab59 8692 SUPPORTED_TP);
ef348144
KK		 8693 cmd->port = PORT_TP;
8694 } else {
1da177e4 8695 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8696 cmd->port = PORT_FIBRE;
8697 }
6aa20a22 8698
1da177e4
LT		 8699 cmd->advertising = tp->link_config.advertising;
8700 if (netif_running(dev)) {
8701 cmd->speed = tp->link_config.active_speed;
8702 cmd->duplex = tp->link_config.active_duplex;
8703 }
1da177e4 8704 cmd->phy_address = PHY_ADDR;
7e5856bd 8705 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8706 cmd->autoneg = tp->link_config.autoneg;
8707 cmd->maxtxpkt = 0;
8708 cmd->maxrxpkt = 0;
8709 return 0;
8710}
6aa20a22 8711
1da177e4
LT		 8712static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8713{
8714 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8715
b02fd9e3
MC		 8716 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8717 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8718 return -EAGAIN;
298cf9be 8719 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8720 }
8721
7e5856bd
MC		 8722 if (cmd->autoneg != AUTONEG_ENABLE &&
8723 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8724 return -EINVAL;
7e5856bd
MC		 8725
8726 if (cmd->autoneg == AUTONEG_DISABLE &&
8727 cmd->duplex != DUPLEX_FULL &&
8728 cmd->duplex != DUPLEX_HALF)
37ff238d 8729 return -EINVAL;
1da177e4 8730
7e5856bd
MC		 8731 if (cmd->autoneg == AUTONEG_ENABLE) {
8732 u32 mask = ADVERTISED_Autoneg |
8733 ADVERTISED_Pause |
8734 ADVERTISED_Asym_Pause;
8735
8736 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8737 mask |= ADVERTISED_1000baseT_Half |
8738 ADVERTISED_1000baseT_Full;
8739
8740 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8741 mask |= ADVERTISED_100baseT_Half |
8742 ADVERTISED_100baseT_Full |
8743 ADVERTISED_10baseT_Half |
8744 ADVERTISED_10baseT_Full |
8745 ADVERTISED_TP;
8746 else
8747 mask |= ADVERTISED_FIBRE;
8748
8749 if (cmd->advertising & ~mask)
8750 return -EINVAL;
8751
8752 mask &= (ADVERTISED_1000baseT_Half |
8753 ADVERTISED_1000baseT_Full |
8754 ADVERTISED_100baseT_Half |
8755 ADVERTISED_100baseT_Full |
8756 ADVERTISED_10baseT_Half |
8757 ADVERTISED_10baseT_Full);
8758
8759 cmd->advertising &= mask;
8760 } else {
8761 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8762 if (cmd->speed != SPEED_1000)
8763 return -EINVAL;
8764
8765 if (cmd->duplex != DUPLEX_FULL)
8766 return -EINVAL;
8767 } else {
8768 if (cmd->speed != SPEED_100 &&
8769 cmd->speed != SPEED_10)
8770 return -EINVAL;
8771 }
8772 }
8773
f47c11ee 8774 tg3_full_lock(tp, 0);
1da177e4
LT		 8775
8776 tp->link_config.autoneg = cmd->autoneg;
8777 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8778 tp->link_config.advertising = (cmd->advertising |
8779 ADVERTISED_Autoneg);
1da177e4
LT		 8780 tp->link_config.speed = SPEED_INVALID;
8781 tp->link_config.duplex = DUPLEX_INVALID;
8782 } else {
8783 tp->link_config.advertising = 0;
8784 tp->link_config.speed = cmd->speed;
8785 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8786 }
6aa20a22 8787
24fcad6b
MC		 8788 tp->link_config.orig_speed = tp->link_config.speed;
8789 tp->link_config.orig_duplex = tp->link_config.duplex;
8790 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8791
1da177e4
LT		 8792 if (netif_running(dev))
8793 tg3_setup_phy(tp, 1);
8794
f47c11ee 8795 tg3_full_unlock(tp);
6aa20a22 8796
1da177e4
LT		 8797 return 0;
8798}
6aa20a22 8799
1da177e4
LT		 8800static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8801{
8802 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8803
1da177e4
LT		 8804 strcpy(info->driver, DRV_MODULE_NAME);
8805 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8806 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8807 strcpy(info->bus_info, pci_name(tp->pdev));
8808}
6aa20a22 8809
1da177e4
LT		 8810static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8811{
8812 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8813
12dac075
RW		 8814 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8815 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8816 wol->supported = WAKE_MAGIC;
8817 else
8818 wol->supported = 0;
1da177e4 8819 wol->wolopts = 0;
05ac4cb7
MC		 8820 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8821 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8822 wol->wolopts = WAKE_MAGIC;
8823 memset(&wol->sopass, 0, sizeof(wol->sopass));
8824}
6aa20a22 8825
1da177e4
LT		 8826static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8827{
8828 struct tg3 *tp = netdev_priv(dev);
12dac075 8829 struct device *dp = &tp->pdev->dev;
6aa20a22 8830
1da177e4
LT		 8831 if (wol->wolopts & ~WAKE_MAGIC)
8832 return -EINVAL;
8833 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8834 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8835 return -EINVAL;
6aa20a22 8836
f47c11ee 8837 spin_lock_bh(&tp->lock);
12dac075 8838 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8839 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8840 device_set_wakeup_enable(dp, true);
8841 } else {
1da177e4 8842 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8843 device_set_wakeup_enable(dp, false);
8844 }
f47c11ee 8845 spin_unlock_bh(&tp->lock);
6aa20a22 8846
1da177e4
LT		 8847 return 0;
8848}
6aa20a22 8849
1da177e4
LT		 8850static u32 tg3_get_msglevel(struct net_device *dev)
8851{
8852 struct tg3 *tp = netdev_priv(dev);
8853 return tp->msg_enable;
8854}
6aa20a22 8855
1da177e4
LT		 8856static void tg3_set_msglevel(struct net_device *dev, u32 value)
8857{
8858 struct tg3 *tp = netdev_priv(dev);
8859 tp->msg_enable = value;
8860}
6aa20a22 8861
1da177e4
LT		 8862static int tg3_set_tso(struct net_device *dev, u32 value)
8863{
8864 struct tg3 *tp = netdev_priv(dev);
8865
8866 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8867 if (value)
8868 return -EINVAL;
8869 return 0;
8870 }
027455ad
MC		 8871 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8872 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 8873 if (value) {
b0026624 8874 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 8875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8876 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8877 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 8878 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8879 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 8880 dev->features |= NETIF_F_TSO_ECN;
8881 } else
8882 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8883 }
1da177e4
LT		 8884 return ethtool_op_set_tso(dev, value);
8885}
6aa20a22 8886
1da177e4
LT		 8887static int tg3_nway_reset(struct net_device *dev)
8888{
8889 struct tg3 *tp = netdev_priv(dev);
1da177e4 8890 int r;
6aa20a22 8891
1da177e4
LT		 8892 if (!netif_running(dev))
8893 return -EAGAIN;
8894
c94e3941
MC		 8895 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8896 return -EINVAL;
8897
b02fd9e3
MC		 8898 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8899 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8900 return -EAGAIN;
298cf9be 8901 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 8902 } else {
8903 u32 bmcr;
8904
8905 spin_lock_bh(&tp->lock);
8906 r = -EINVAL;
8907 tg3_readphy(tp, MII_BMCR, &bmcr);
8908 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8909 ((bmcr & BMCR_ANENABLE) ||
8910 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8911 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8912 BMCR_ANENABLE);
8913 r = 0;
8914 }
8915 spin_unlock_bh(&tp->lock);
1da177e4 8916 }
6aa20a22 8917
1da177e4
LT		 8918 return r;
8919}
6aa20a22 8920
1da177e4
LT		 8921static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8922{
8923 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8924
1da177e4
LT		 8925 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8926 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 8927 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8928 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8929 else
8930 ering->rx_jumbo_max_pending = 0;
8931
8932 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 8933
8934 ering->rx_pending = tp->rx_pending;
8935 ering->rx_mini_pending = 0;
4f81c32b
MC		 8936 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8937 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8938 else
8939 ering->rx_jumbo_pending = 0;
8940
1da177e4
LT		 8941 ering->tx_pending = tp->tx_pending;
8942}
6aa20a22 8943
1da177e4
LT		 8944static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8945{
8946 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 8947 int irq_sync = 0, err = 0;
6aa20a22 8948
1da177e4
LT		 8949 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8950 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 8951 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8952 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 8953 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 8954 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 8955 return -EINVAL;
6aa20a22 8956
bbe832c0 8957 if (netif_running(dev)) {
b02fd9e3 8958 tg3_phy_stop(tp);
1da177e4 8959 tg3_netif_stop(tp);
bbe832c0
MC		 8960 irq_sync = 1;
8961 }
1da177e4 8962
bbe832c0 8963 tg3_full_lock(tp, irq_sync);
6aa20a22 8964
1da177e4
LT		 8965 tp->rx_pending = ering->rx_pending;
8966
8967 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8968 tp->rx_pending > 63)
8969 tp->rx_pending = 63;
8970 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8971 tp->tx_pending = ering->tx_pending;
8972
8973 if (netif_running(dev)) {
944d980e 8974 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 8975 err = tg3_restart_hw(tp, 1);
8976 if (!err)
8977 tg3_netif_start(tp);
1da177e4
LT		 8978 }
8979
f47c11ee 8980 tg3_full_unlock(tp);
6aa20a22 8981
b02fd9e3
MC		 8982 if (irq_sync && !err)
8983 tg3_phy_start(tp);
8984
b9ec6c1b 8985 return err;
1da177e4 8986}
6aa20a22 8987
1da177e4
LT		 8988static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8989{
8990 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8991
1da177e4 8992 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 8993
e18ce346 8994 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 8995 epause->rx_pause = 1;
8996 else
8997 epause->rx_pause = 0;
8998
e18ce346 8999 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9000 epause->tx_pause = 1;
9001 else
9002 epause->tx_pause = 0;
1da177e4 9003}
6aa20a22 9004
1da177e4
LT		 9005static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9006{
9007 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9008 int err = 0;
6aa20a22 9009
b02fd9e3
MC		 9010 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9011 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9012 return -EAGAIN;
1da177e4 9013
b02fd9e3
MC		 9014 if (epause->autoneg) {
9015 u32 newadv;
9016 struct phy_device *phydev;
f47c11ee 9017
298cf9be 9018 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9019
b02fd9e3
MC		 9020 if (epause->rx_pause) {
9021 if (epause->tx_pause)
9022 newadv = ADVERTISED_Pause;
9023 else
9024 newadv = ADVERTISED_Pause |
9025 ADVERTISED_Asym_Pause;
9026 } else if (epause->tx_pause) {
9027 newadv = ADVERTISED_Asym_Pause;
9028 } else
9029 newadv = 0;
9030
9031 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9032 u32 oldadv = phydev->advertising &
9033 (ADVERTISED_Pause |
9034 ADVERTISED_Asym_Pause);
9035 if (oldadv != newadv) {
9036 phydev->advertising &=
9037 ~(ADVERTISED_Pause |
9038 ADVERTISED_Asym_Pause);
9039 phydev->advertising |= newadv;
9040 err = phy_start_aneg(phydev);
9041 }
9042 } else {
9043 tp->link_config.advertising &=
9044 ~(ADVERTISED_Pause |
9045 ADVERTISED_Asym_Pause);
9046 tp->link_config.advertising |= newadv;
9047 }
9048 } else {
9049 if (epause->rx_pause)
e18ce346 9050 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9051 else
e18ce346 9052 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9053
b02fd9e3 9054 if (epause->tx_pause)
e18ce346 9055 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9056 else
e18ce346 9057 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9058
9059 if (netif_running(dev))
9060 tg3_setup_flow_control(tp, 0, 0);
9061 }
9062 } else {
9063 int irq_sync = 0;
9064
9065 if (netif_running(dev)) {
9066 tg3_netif_stop(tp);
9067 irq_sync = 1;
9068 }
9069
9070 tg3_full_lock(tp, irq_sync);
9071
9072 if (epause->autoneg)
9073 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9074 else
9075 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9076 if (epause->rx_pause)
e18ce346 9077 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9078 else
e18ce346 9079 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9080 if (epause->tx_pause)
e18ce346 9081 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9082 else
e18ce346 9083 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9084
9085 if (netif_running(dev)) {
9086 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9087 err = tg3_restart_hw(tp, 1);
9088 if (!err)
9089 tg3_netif_start(tp);
9090 }
9091
9092 tg3_full_unlock(tp);
9093 }
6aa20a22 9094
b9ec6c1b 9095 return err;
1da177e4 9096}
6aa20a22 9097
1da177e4
LT		 9098static u32 tg3_get_rx_csum(struct net_device *dev)
9099{
9100 struct tg3 *tp = netdev_priv(dev);
9101 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9102}
6aa20a22 9103
1da177e4
LT		 9104static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9105{
9106 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9107
1da177e4
LT		 9108 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9109 if (data != 0)
9110 return -EINVAL;
9111 return 0;
9112 }
6aa20a22 9113
f47c11ee 9114 spin_lock_bh(&tp->lock);
1da177e4
LT		 9115 if (data)
9116 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9117 else
9118 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9119 spin_unlock_bh(&tp->lock);
6aa20a22 9120
1da177e4
LT		 9121 return 0;
9122}
6aa20a22 9123
1da177e4
LT		 9124static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9125{
9126 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9127
1da177e4
LT		 9128 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9129 if (data != 0)
9130 return -EINVAL;
9131 return 0;
9132 }
6aa20a22 9133
321d32a0 9134 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9135 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9136 else
9c27dbdf 9137 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9138
9139 return 0;
9140}
9141
b9f2c044 9142static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9143{
b9f2c044
JG		 9144 switch (sset) {
9145 case ETH_SS_TEST:
9146 return TG3_NUM_TEST;
9147 case ETH_SS_STATS:
9148 return TG3_NUM_STATS;
9149 default:
9150 return -EOPNOTSUPP;
9151 }
4cafd3f5
MC		 9152}
9153
1da177e4
LT		 9154static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9155{
9156 switch (stringset) {
9157 case ETH_SS_STATS:
9158 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9159 break;
4cafd3f5
MC		 9160 case ETH_SS_TEST:
9161 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9162 break;
1da177e4
LT		 9163 default:
9164 WARN_ON(1); /* we need a WARN() */
9165 break;
9166 }
9167}
9168
4009a93d
MC		 9169static int tg3_phys_id(struct net_device *dev, u32 data)
9170{
9171 struct tg3 *tp = netdev_priv(dev);
9172 int i;
9173
9174 if (!netif_running(tp->dev))
9175 return -EAGAIN;
9176
9177 if (data == 0)
759afc31 9178 data = UINT_MAX / 2;
4009a93d
MC		 9179
9180 for (i = 0; i < (data * 2); i++) {
9181 if ((i % 2) == 0)
9182 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9183 LED_CTRL_1000MBPS_ON |
9184 LED_CTRL_100MBPS_ON |
9185 LED_CTRL_10MBPS_ON |
9186 LED_CTRL_TRAFFIC_OVERRIDE |
9187 LED_CTRL_TRAFFIC_BLINK |
9188 LED_CTRL_TRAFFIC_LED);
6aa20a22 9189
4009a93d
MC		 9190 else
9191 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9192 LED_CTRL_TRAFFIC_OVERRIDE);
9193
9194 if (msleep_interruptible(500))
9195 break;
9196 }
9197 tw32(MAC_LED_CTRL, tp->led_ctrl);
9198 return 0;
9199}
9200
1da177e4
LT		 9201static void tg3_get_ethtool_stats (struct net_device *dev,
9202 struct ethtool_stats *estats, u64 *tmp_stats)
9203{
9204 struct tg3 *tp = netdev_priv(dev);
9205 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9206}
9207
566f86ad 9208#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9209#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9210#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9211#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9212#define NVRAM_SELFBOOT_HW_SIZE 0x20
9213#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9214
9215static int tg3_test_nvram(struct tg3 *tp)
9216{
b9fc7dc5 9217 u32 csum, magic;
a9dc529d 9218 __be32 *buf;
ab0049b4 9219 int i, j, k, err = 0, size;
566f86ad 9220
df259d8c
MC		 9221 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9222 return 0;
9223
e4f34110 9224 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9225 return -EIO;
9226
1b27777a
MC		 9227 if (magic == TG3_EEPROM_MAGIC)
9228 size = NVRAM_TEST_SIZE;
b16250e3 9229 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9230 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9231 TG3_EEPROM_SB_FORMAT_1) {
9232 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9233 case TG3_EEPROM_SB_REVISION_0:
9234 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9235 break;
9236 case TG3_EEPROM_SB_REVISION_2:
9237 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9238 break;
9239 case TG3_EEPROM_SB_REVISION_3:
9240 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9241 break;
9242 default:
9243 return 0;
9244 }
9245 } else
1b27777a 9246 return 0;
b16250e3
MC		 9247 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9248 size = NVRAM_SELFBOOT_HW_SIZE;
9249 else
1b27777a
MC		 9250 return -EIO;
9251
9252 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9253 if (buf == NULL)
9254 return -ENOMEM;
9255
1b27777a
MC		 9256 err = -EIO;
9257 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9258 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9259 if (err)
566f86ad 9260 break;
566f86ad 9261 }
1b27777a 9262 if (i < size)
566f86ad
MC		 9263 goto out;
9264
1b27777a 9265 /* Selfboot format */
a9dc529d 9266 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9267 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9268 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9269 u8 *buf8 = (u8 *) buf, csum8 = 0;
9270
b9fc7dc5 9271 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9272 TG3_EEPROM_SB_REVISION_2) {
9273 /* For rev 2, the csum doesn't include the MBA. */
9274 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9275 csum8 += buf8[i];
9276 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9277 csum8 += buf8[i];
9278 } else {
9279 for (i = 0; i < size; i++)
9280 csum8 += buf8[i];
9281 }
1b27777a 9282
ad96b485
AB		 9283 if (csum8 == 0) {
9284 err = 0;
9285 goto out;
9286 }
9287
9288 err = -EIO;
9289 goto out;
1b27777a 9290 }
566f86ad 9291
b9fc7dc5 9292 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9293 TG3_EEPROM_MAGIC_HW) {
9294 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9295 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9296 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9297
9298 /* Separate the parity bits and the data bytes. */
9299 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9300 if ((i == 0) || (i == 8)) {
9301 int l;
9302 u8 msk;
9303
9304 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9305 parity[k++] = buf8[i] & msk;
9306 i++;
9307 }
9308 else if (i == 16) {
9309 int l;
9310 u8 msk;
9311
9312 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9313 parity[k++] = buf8[i] & msk;
9314 i++;
9315
9316 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9317 parity[k++] = buf8[i] & msk;
9318 i++;
9319 }
9320 data[j++] = buf8[i];
9321 }
9322
9323 err = -EIO;
9324 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9325 u8 hw8 = hweight8(data[i]);
9326
9327 if ((hw8 & 0x1) && parity[i])
9328 goto out;
9329 else if (!(hw8 & 0x1) && !parity[i])
9330 goto out;
9331 }
9332 err = 0;
9333 goto out;
9334 }
9335
566f86ad
MC		 9336 /* Bootstrap checksum at offset 0x10 */
9337 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9338 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9339 goto out;
9340
9341 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9342 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9343 if (csum != be32_to_cpu(buf[0xfc/4]))
9344 goto out;
566f86ad
MC		 9345
9346 err = 0;
9347
9348out:
9349 kfree(buf);
9350 return err;
9351}
9352
ca43007a
MC		 9353#define TG3_SERDES_TIMEOUT_SEC 2
9354#define TG3_COPPER_TIMEOUT_SEC 6
9355
9356static int tg3_test_link(struct tg3 *tp)
9357{
9358 int i, max;
9359
9360 if (!netif_running(tp->dev))
9361 return -ENODEV;
9362
4c987487 9363 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9364 max = TG3_SERDES_TIMEOUT_SEC;
9365 else
9366 max = TG3_COPPER_TIMEOUT_SEC;
9367
9368 for (i = 0; i < max; i++) {
9369 if (netif_carrier_ok(tp->dev))
9370 return 0;
9371
9372 if (msleep_interruptible(1000))
9373 break;
9374 }
9375
9376 return -EIO;
9377}
9378
a71116d1 9379/* Only test the commonly used registers */
30ca3e37 9380static int tg3_test_registers(struct tg3 *tp)
a71116d1 9381{
b16250e3 9382 int i, is_5705, is_5750;
a71116d1
MC		 9383 u32 offset, read_mask, write_mask, val, save_val, read_val;
9384 static struct {
9385 u16 offset;
9386 u16 flags;
9387#define TG3_FL_5705 0x1
9388#define TG3_FL_NOT_5705 0x2
9389#define TG3_FL_NOT_5788 0x4
b16250e3 9390#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9391 u32 read_mask;
9392 u32 write_mask;
9393 } reg_tbl[] = {
9394 /* MAC Control Registers */
9395 { MAC_MODE, TG3_FL_NOT_5705,
9396 0x00000000, 0x00ef6f8c },
9397 { MAC_MODE, TG3_FL_5705,
9398 0x00000000, 0x01ef6b8c },
9399 { MAC_STATUS, TG3_FL_NOT_5705,
9400 0x03800107, 0x00000000 },
9401 { MAC_STATUS, TG3_FL_5705,
9402 0x03800100, 0x00000000 },
9403 { MAC_ADDR_0_HIGH, 0x0000,
9404 0x00000000, 0x0000ffff },
9405 { MAC_ADDR_0_LOW, 0x0000,
9406 0x00000000, 0xffffffff },
9407 { MAC_RX_MTU_SIZE, 0x0000,
9408 0x00000000, 0x0000ffff },
9409 { MAC_TX_MODE, 0x0000,
9410 0x00000000, 0x00000070 },
9411 { MAC_TX_LENGTHS, 0x0000,
9412 0x00000000, 0x00003fff },
9413 { MAC_RX_MODE, TG3_FL_NOT_5705,
9414 0x00000000, 0x000007fc },
9415 { MAC_RX_MODE, TG3_FL_5705,
9416 0x00000000, 0x000007dc },
9417 { MAC_HASH_REG_0, 0x0000,
9418 0x00000000, 0xffffffff },
9419 { MAC_HASH_REG_1, 0x0000,
9420 0x00000000, 0xffffffff },
9421 { MAC_HASH_REG_2, 0x0000,
9422 0x00000000, 0xffffffff },
9423 { MAC_HASH_REG_3, 0x0000,
9424 0x00000000, 0xffffffff },
9425
9426 /* Receive Data and Receive BD Initiator Control Registers. */
9427 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9428 0x00000000, 0xffffffff },
9429 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9430 0x00000000, 0xffffffff },
9431 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9432 0x00000000, 0x00000003 },
9433 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9434 0x00000000, 0xffffffff },
9435 { RCVDBDI_STD_BD+0, 0x0000,
9436 0x00000000, 0xffffffff },
9437 { RCVDBDI_STD_BD+4, 0x0000,
9438 0x00000000, 0xffffffff },
9439 { RCVDBDI_STD_BD+8, 0x0000,
9440 0x00000000, 0xffff0002 },
9441 { RCVDBDI_STD_BD+0xc, 0x0000,
9442 0x00000000, 0xffffffff },
6aa20a22 9443
a71116d1
MC		 9444 /* Receive BD Initiator Control Registers. */
9445 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9446 0x00000000, 0xffffffff },
9447 { RCVBDI_STD_THRESH, TG3_FL_5705,
9448 0x00000000, 0x000003ff },
9449 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9450 0x00000000, 0xffffffff },
6aa20a22 9451
a71116d1
MC		 9452 /* Host Coalescing Control Registers. */
9453 { HOSTCC_MODE, TG3_FL_NOT_5705,
9454 0x00000000, 0x00000004 },
9455 { HOSTCC_MODE, TG3_FL_5705,
9456 0x00000000, 0x000000f6 },
9457 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9458 0x00000000, 0xffffffff },
9459 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9460 0x00000000, 0x000003ff },
9461 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9462 0x00000000, 0xffffffff },
9463 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9464 0x00000000, 0x000003ff },
9465 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9466 0x00000000, 0xffffffff },
9467 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9468 0x00000000, 0x000000ff },
9469 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9470 0x00000000, 0xffffffff },
9471 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9472 0x00000000, 0x000000ff },
9473 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9474 0x00000000, 0xffffffff },
9475 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9476 0x00000000, 0xffffffff },
9477 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9478 0x00000000, 0xffffffff },
9479 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9480 0x00000000, 0x000000ff },
9481 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9482 0x00000000, 0xffffffff },
9483 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9484 0x00000000, 0x000000ff },
9485 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9486 0x00000000, 0xffffffff },
9487 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9488 0x00000000, 0xffffffff },
9489 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9490 0x00000000, 0xffffffff },
9491 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9492 0x00000000, 0xffffffff },
9493 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9494 0x00000000, 0xffffffff },
9495 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9496 0xffffffff, 0x00000000 },
9497 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9498 0xffffffff, 0x00000000 },
9499
9500 /* Buffer Manager Control Registers. */
b16250e3 9501 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9502 0x00000000, 0x007fff80 },
b16250e3 9503 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9504 0x00000000, 0x007fffff },
9505 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9506 0x00000000, 0x0000003f },
9507 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9508 0x00000000, 0x000001ff },
9509 { BUFMGR_MB_HIGH_WATER, 0x0000,
9510 0x00000000, 0x000001ff },
9511 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9512 0xffffffff, 0x00000000 },
9513 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9514 0xffffffff, 0x00000000 },
6aa20a22 9515
a71116d1
MC		 9516 /* Mailbox Registers */
9517 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9518 0x00000000, 0x000001ff },
9519 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9520 0x00000000, 0x000001ff },
9521 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9522 0x00000000, 0x000007ff },
9523 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9524 0x00000000, 0x000001ff },
9525
9526 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9527 };
9528
b16250e3
MC		 9529 is_5705 = is_5750 = 0;
9530 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9531 is_5705 = 1;
b16250e3
MC		 9532 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9533 is_5750 = 1;
9534 }
a71116d1
MC		 9535
9536 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9537 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9538 continue;
9539
9540 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9541 continue;
9542
9543 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9544 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9545 continue;
9546
b16250e3
MC		 9547 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9548 continue;
9549
a71116d1
MC		 9550 offset = (u32) reg_tbl[i].offset;
9551 read_mask = reg_tbl[i].read_mask;
9552 write_mask = reg_tbl[i].write_mask;
9553
9554 /* Save the original register content */
9555 save_val = tr32(offset);
9556
9557 /* Determine the read-only value. */
9558 read_val = save_val & read_mask;
9559
9560 /* Write zero to the register, then make sure the read-only bits
9561 * are not changed and the read/write bits are all zeros.
9562 */
9563 tw32(offset, 0);
9564
9565 val = tr32(offset);
9566
9567 /* Test the read-only and read/write bits. */
9568 if (((val & read_mask) != read_val) || (val & write_mask))
9569 goto out;
9570
9571 /* Write ones to all the bits defined by RdMask and WrMask, then
9572 * make sure the read-only bits are not changed and the
9573 * read/write bits are all ones.
9574 */
9575 tw32(offset, read_mask | write_mask);
9576
9577 val = tr32(offset);
9578
9579 /* Test the read-only bits. */
9580 if ((val & read_mask) != read_val)
9581 goto out;
9582
9583 /* Test the read/write bits. */
9584 if ((val & write_mask) != write_mask)
9585 goto out;
9586
9587 tw32(offset, save_val);
9588 }
9589
9590 return 0;
9591
9592out:
9f88f29f
MC		 9593 if (netif_msg_hw(tp))
9594 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9595 offset);
a71116d1
MC		 9596 tw32(offset, save_val);
9597 return -EIO;
9598}
9599
7942e1db
MC		 9600static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9601{
f71e1309 9602 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9603 int i;
9604 u32 j;
9605
e9edda69 9606 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9607 for (j = 0; j < len; j += 4) {
9608 u32 val;
9609
9610 tg3_write_mem(tp, offset + j, test_pattern[i]);
9611 tg3_read_mem(tp, offset + j, &val);
9612 if (val != test_pattern[i])
9613 return -EIO;
9614 }
9615 }
9616 return 0;
9617}
9618
9619static int tg3_test_memory(struct tg3 *tp)
9620{
9621 static struct mem_entry {
9622 u32 offset;
9623 u32 len;
9624 } mem_tbl_570x[] = {
38690194 9625 { 0x00000000, 0x00b50},
7942e1db
MC		 9626 { 0x00002000, 0x1c000},
9627 { 0xffffffff, 0x00000}
9628 }, mem_tbl_5705[] = {
9629 { 0x00000100, 0x0000c},
9630 { 0x00000200, 0x00008},
7942e1db
MC		 9631 { 0x00004000, 0x00800},
9632 { 0x00006000, 0x01000},
9633 { 0x00008000, 0x02000},
9634 { 0x00010000, 0x0e000},
9635 { 0xffffffff, 0x00000}
79f4d13a
MC		 9636 }, mem_tbl_5755[] = {
9637 { 0x00000200, 0x00008},
9638 { 0x00004000, 0x00800},
9639 { 0x00006000, 0x00800},
9640 { 0x00008000, 0x02000},
9641 { 0x00010000, 0x0c000},
9642 { 0xffffffff, 0x00000}
b16250e3
MC		 9643 }, mem_tbl_5906[] = {
9644 { 0x00000200, 0x00008},
9645 { 0x00004000, 0x00400},
9646 { 0x00006000, 0x00400},
9647 { 0x00008000, 0x01000},
9648 { 0x00010000, 0x01000},
9649 { 0xffffffff, 0x00000}
7942e1db
MC		 9650 };
9651 struct mem_entry *mem_tbl;
9652 int err = 0;
9653 int i;
9654
321d32a0
MC		 9655 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9656 mem_tbl = mem_tbl_5755;
9657 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9658 mem_tbl = mem_tbl_5906;
9659 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9660 mem_tbl = mem_tbl_5705;
9661 else
7942e1db
MC		 9662 mem_tbl = mem_tbl_570x;
9663
9664 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9665 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9666 mem_tbl[i].len)) != 0)
9667 break;
9668 }
6aa20a22 9669
7942e1db
MC		 9670 return err;
9671}
9672
9f40dead
MC		 9673#define TG3_MAC_LOOPBACK 0
9674#define TG3_PHY_LOOPBACK 1
9675
9676static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9677{
9f40dead 9678 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9679 u32 desc_idx;
9680 struct sk_buff *skb, *rx_skb;
9681 u8 *tx_data;
9682 dma_addr_t map;
9683 int num_pkts, tx_len, rx_len, i, err;
9684 struct tg3_rx_buffer_desc *desc;
9685
9f40dead 9686 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9687 /* HW errata - mac loopback fails in some cases on 5780.
9688 * Normal traffic and PHY loopback are not affected by
9689 * errata.
9690 */
9691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9692 return 0;
9693
9f40dead 9694 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9695 MAC_MODE_PORT_INT_LPBACK;
9696 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9697 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9698 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9699 mac_mode |= MAC_MODE_PORT_MODE_MII;
9700 else
9701 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9702 tw32(MAC_MODE, mac_mode);
9703 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9704 u32 val;
9705
b16250e3
MC		 9706 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9707 u32 phytest;
9708
9709 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9710 u32 phy;
9711
9712 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9713 phytest | MII_TG3_EPHY_SHADOW_EN);
9714 if (!tg3_readphy(tp, 0x1b, &phy))
9715 tg3_writephy(tp, 0x1b, phy & ~0x20);
b16250e3
MC		 9716 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9717 }
5d64ad34
MC		 9718 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9719 } else
9720 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9721
9ef8ca99
MC		 9722 tg3_phy_toggle_automdix(tp, 0);
9723
3f7045c1 9724 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9725 udelay(40);
5d64ad34 9726
e8f3f6ca 9727 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5d64ad34 9728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
b16250e3 9729 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
5d64ad34
MC		 9730 mac_mode |= MAC_MODE_PORT_MODE_MII;
9731 } else
9732 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9733
c94e3941
MC		 9734 /* reset to prevent losing 1st rx packet intermittently */
9735 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9736 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9737 udelay(10);
9738 tw32_f(MAC_RX_MODE, tp->rx_mode);
9739 }
e8f3f6ca
MC		 9740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9741 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9742 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9743 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9744 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9745 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9746 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9747 }
9f40dead 9748 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9749 }
9750 else
9751 return -EINVAL;
c76949a6
MC		 9752
9753 err = -EIO;
9754
c76949a6 9755 tx_len = 1514;
a20e9c62 9756 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9757 if (!skb)
9758 return -ENOMEM;
9759
c76949a6
MC		 9760 tx_data = skb_put(skb, tx_len);
9761 memcpy(tx_data, tp->dev->dev_addr, 6);
9762 memset(tx_data + 6, 0x0, 8);
9763
9764 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9765
9766 for (i = 14; i < tx_len; i++)
9767 tx_data[i] = (u8) (i & 0xff);
9768
9769 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9770
9771 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9772 HOSTCC_MODE_NOW);
9773
9774 udelay(10);
9775
9776 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9777
c76949a6
MC		 9778 num_pkts = 0;
9779
9f40dead 9780 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9781
9f40dead 9782 tp->tx_prod++;
c76949a6
MC		 9783 num_pkts++;
9784
9f40dead
MC		 9785 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9786 tp->tx_prod);
09ee929c 9787 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9788
9789 udelay(10);
9790
3f7045c1
MC		 9791 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9792 for (i = 0; i < 25; i++) {
c76949a6
MC		 9793 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9794 HOSTCC_MODE_NOW);
9795
9796 udelay(10);
9797
9798 tx_idx = tp->hw_status->idx[0].tx_consumer;
9799 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9800 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9801 (rx_idx == (rx_start_idx + num_pkts)))
9802 break;
9803 }
9804
9805 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9806 dev_kfree_skb(skb);
9807
9f40dead 9808 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9809 goto out;
9810
9811 if (rx_idx != rx_start_idx + num_pkts)
9812 goto out;
9813
9814 desc = &tp->rx_rcb[rx_start_idx];
9815 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9816 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9817 if (opaque_key != RXD_OPAQUE_RING_STD)
9818 goto out;
9819
9820 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9821 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9822 goto out;
9823
9824 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9825 if (rx_len != tx_len)
9826 goto out;
9827
9828 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9829
9830 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9831 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9832
9833 for (i = 14; i < tx_len; i++) {
9834 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9835 goto out;
9836 }
9837 err = 0;
6aa20a22 9838
c76949a6
MC		 9839 /* tg3_free_rings will unmap and free the rx_skb */
9840out:
9841 return err;
9842}
9843
9f40dead
MC		 9844#define TG3_MAC_LOOPBACK_FAILED 1
9845#define TG3_PHY_LOOPBACK_FAILED 2
9846#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9847 TG3_PHY_LOOPBACK_FAILED)
9848
9849static int tg3_test_loopback(struct tg3 *tp)
9850{
9851 int err = 0;
9936bcf6 9852 u32 cpmuctrl = 0;
9f40dead
MC		 9853
9854 if (!netif_running(tp->dev))
9855 return TG3_LOOPBACK_FAILED;
9856
b9ec6c1b
MC		 9857 err = tg3_reset_hw(tp, 1);
9858 if (err)
9859 return TG3_LOOPBACK_FAILED;
9f40dead 9860
6833c043
MC		 9861 /* Turn off gphy autopowerdown. */
9862 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9863 tg3_phy_toggle_apd(tp, false);
9864
321d32a0 9865 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9866 int i;
9867 u32 status;
9868
9869 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9870
9871 /* Wait for up to 40 microseconds to acquire lock. */
9872 for (i = 0; i < 4; i++) {
9873 status = tr32(TG3_CPMU_MUTEX_GNT);
9874 if (status == CPMU_MUTEX_GNT_DRIVER)
9875 break;
9876 udelay(10);
9877 }
9878
9879 if (status != CPMU_MUTEX_GNT_DRIVER)
9880 return TG3_LOOPBACK_FAILED;
9881
b2a5c19c 9882 /* Turn off link-based power management. */
e875093c 9883 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 9884 tw32(TG3_CPMU_CTRL,
9885 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9886 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9887 }
9888
9f40dead
MC		 9889 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9890 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9891
321d32a0 9892 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9893 tw32(TG3_CPMU_CTRL, cpmuctrl);
9894
9895 /* Release the mutex */
9896 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9897 }
9898
dd477003
MC		 9899 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9900 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 9901 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9902 err |= TG3_PHY_LOOPBACK_FAILED;
9903 }
9904
6833c043
MC		 9905 /* Re-enable gphy autopowerdown. */
9906 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9907 tg3_phy_toggle_apd(tp, true);
9908
9f40dead
MC		 9909 return err;
9910}
9911
4cafd3f5
MC		 9912static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9913 u64 *data)
9914{
566f86ad
MC		 9915 struct tg3 *tp = netdev_priv(dev);
9916
bc1c7567
MC		 9917 if (tp->link_config.phy_is_low_power)
9918 tg3_set_power_state(tp, PCI_D0);
9919
566f86ad
MC		 9920 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9921
9922 if (tg3_test_nvram(tp) != 0) {
9923 etest->flags |= ETH_TEST_FL_FAILED;
9924 data[0] = 1;
9925 }
ca43007a
MC		 9926 if (tg3_test_link(tp) != 0) {
9927 etest->flags |= ETH_TEST_FL_FAILED;
9928 data[1] = 1;
9929 }
a71116d1 9930 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 9931 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 9932
9933 if (netif_running(dev)) {
b02fd9e3 9934 tg3_phy_stop(tp);
a71116d1 9935 tg3_netif_stop(tp);
bbe832c0
MC		 9936 irq_sync = 1;
9937 }
a71116d1 9938
bbe832c0 9939 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 9940
9941 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 9942 err = tg3_nvram_lock(tp);
a71116d1
MC		 9943 tg3_halt_cpu(tp, RX_CPU_BASE);
9944 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9945 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 9946 if (!err)
9947 tg3_nvram_unlock(tp);
a71116d1 9948
d9ab5ad1
MC		 9949 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9950 tg3_phy_reset(tp);
9951
a71116d1
MC		 9952 if (tg3_test_registers(tp) != 0) {
9953 etest->flags |= ETH_TEST_FL_FAILED;
9954 data[2] = 1;
9955 }
7942e1db
MC		 9956 if (tg3_test_memory(tp) != 0) {
9957 etest->flags |= ETH_TEST_FL_FAILED;
9958 data[3] = 1;
9959 }
9f40dead 9960 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 9961 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 9962
f47c11ee
DM		 9963 tg3_full_unlock(tp);
9964
d4bc3927
MC		 9965 if (tg3_test_interrupt(tp) != 0) {
9966 etest->flags |= ETH_TEST_FL_FAILED;
9967 data[5] = 1;
9968 }
f47c11ee
DM		 9969
9970 tg3_full_lock(tp, 0);
d4bc3927 9971
a71116d1
MC		 9972 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9973 if (netif_running(dev)) {
9974 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 9975 err2 = tg3_restart_hw(tp, 1);
9976 if (!err2)
b9ec6c1b 9977 tg3_netif_start(tp);
a71116d1 9978 }
f47c11ee
DM		 9979
9980 tg3_full_unlock(tp);
b02fd9e3
MC		 9981
9982 if (irq_sync && !err2)
9983 tg3_phy_start(tp);
a71116d1 9984 }
bc1c7567
MC		 9985 if (tp->link_config.phy_is_low_power)
9986 tg3_set_power_state(tp, PCI_D3hot);
9987
4cafd3f5
MC		 9988}
9989
1da177e4
LT		 9990static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9991{
9992 struct mii_ioctl_data *data = if_mii(ifr);
9993 struct tg3 *tp = netdev_priv(dev);
9994 int err;
9995
b02fd9e3
MC		 9996 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9997 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9998 return -EAGAIN;
298cf9be 9999 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10000 }
10001
1da177e4
LT		 10002 switch(cmd) {
10003 case SIOCGMIIPHY:
10004 data->phy_id = PHY_ADDR;
10005
10006 /* fallthru */
10007 case SIOCGMIIREG: {
10008 u32 mii_regval;
10009
10010 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10011 break; /* We have no PHY */
10012
bc1c7567
MC		 10013 if (tp->link_config.phy_is_low_power)
10014 return -EAGAIN;
10015
f47c11ee 10016 spin_lock_bh(&tp->lock);
1da177e4 10017 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10018 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10019
10020 data->val_out = mii_regval;
10021
10022 return err;
10023 }
10024
10025 case SIOCSMIIREG:
10026 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10027 break; /* We have no PHY */
10028
10029 if (!capable(CAP_NET_ADMIN))
10030 return -EPERM;
10031
bc1c7567
MC		 10032 if (tp->link_config.phy_is_low_power)
10033 return -EAGAIN;
10034
f47c11ee 10035 spin_lock_bh(&tp->lock);
1da177e4 10036 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10037 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10038
10039 return err;
10040
10041 default:
10042 /* do nothing */
10043 break;
10044 }
10045 return -EOPNOTSUPP;
10046}
10047
10048#if TG3_VLAN_TAG_USED
10049static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10050{
10051 struct tg3 *tp = netdev_priv(dev);
10052
844b3eed
MC		 10053 if (!netif_running(dev)) {
10054 tp->vlgrp = grp;
10055 return;
10056 }
10057
10058 tg3_netif_stop(tp);
29315e87 10059
f47c11ee 10060 tg3_full_lock(tp, 0);
1da177e4
LT		 10061
10062 tp->vlgrp = grp;
10063
10064 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10065 __tg3_set_rx_mode(dev);
10066
844b3eed 10067 tg3_netif_start(tp);
46966545
MC		 10068
10069 tg3_full_unlock(tp);
1da177e4 10070}
1da177e4
LT		 10071#endif
10072
15f9850d
DM		 10073static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10074{
10075 struct tg3 *tp = netdev_priv(dev);
10076
10077 memcpy(ec, &tp->coal, sizeof(*ec));
10078 return 0;
10079}
10080
d244c892
MC		 10081static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10082{
10083 struct tg3 *tp = netdev_priv(dev);
10084 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10085 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10086
10087 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10088 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10089 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10090 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10091 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10092 }
10093
10094 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10095 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10096 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10097 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10098 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10099 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10100 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10101 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10102 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10103 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10104 return -EINVAL;
10105
10106 /* No rx interrupts will be generated if both are zero */
10107 if ((ec->rx_coalesce_usecs == 0) &&
10108 (ec->rx_max_coalesced_frames == 0))
10109 return -EINVAL;
10110
10111 /* No tx interrupts will be generated if both are zero */
10112 if ((ec->tx_coalesce_usecs == 0) &&
10113 (ec->tx_max_coalesced_frames == 0))
10114 return -EINVAL;
10115
10116 /* Only copy relevant parameters, ignore all others. */
10117 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10118 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10119 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10120 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10121 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10122 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10123 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10124 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10125 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10126
10127 if (netif_running(dev)) {
10128 tg3_full_lock(tp, 0);
10129 __tg3_set_coalesce(tp, &tp->coal);
10130 tg3_full_unlock(tp);
10131 }
10132 return 0;
10133}
10134
7282d491 10135static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10136 .get_settings = tg3_get_settings,
10137 .set_settings = tg3_set_settings,
10138 .get_drvinfo = tg3_get_drvinfo,
10139 .get_regs_len = tg3_get_regs_len,
10140 .get_regs = tg3_get_regs,
10141 .get_wol = tg3_get_wol,
10142 .set_wol = tg3_set_wol,
10143 .get_msglevel = tg3_get_msglevel,
10144 .set_msglevel = tg3_set_msglevel,
10145 .nway_reset = tg3_nway_reset,
10146 .get_link = ethtool_op_get_link,
10147 .get_eeprom_len = tg3_get_eeprom_len,
10148 .get_eeprom = tg3_get_eeprom,
10149 .set_eeprom = tg3_set_eeprom,
10150 .get_ringparam = tg3_get_ringparam,
10151 .set_ringparam = tg3_set_ringparam,
10152 .get_pauseparam = tg3_get_pauseparam,
10153 .set_pauseparam = tg3_set_pauseparam,
10154 .get_rx_csum = tg3_get_rx_csum,
10155 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10156 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10157 .set_sg = ethtool_op_set_sg,
1da177e4 10158 .set_tso = tg3_set_tso,
4cafd3f5 10159 .self_test = tg3_self_test,
1da177e4 10160 .get_strings = tg3_get_strings,
4009a93d 10161 .phys_id = tg3_phys_id,
1da177e4 10162 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10163 .get_coalesce = tg3_get_coalesce,
d244c892 10164 .set_coalesce = tg3_set_coalesce,
b9f2c044 10165 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10166};
10167
10168static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10169{
1b27777a 10170 u32 cursize, val, magic;
1da177e4
LT		 10171
10172 tp->nvram_size = EEPROM_CHIP_SIZE;
10173
e4f34110 10174 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10175 return;
10176
b16250e3
MC		 10177 if ((magic != TG3_EEPROM_MAGIC) &&
10178 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10179 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10180 return;
10181
10182 /*
10183 * Size the chip by reading offsets at increasing powers of two.
10184 * When we encounter our validation signature, we know the addressing
10185 * has wrapped around, and thus have our chip size.
10186 */
1b27777a 10187 cursize = 0x10;
1da177e4
LT		 10188
10189 while (cursize < tp->nvram_size) {
e4f34110 10190 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10191 return;
10192
1820180b 10193 if (val == magic)
1da177e4
LT		 10194 break;
10195
10196 cursize <<= 1;
10197 }
10198
10199 tp->nvram_size = cursize;
10200}
6aa20a22 10201
1da177e4
LT		 10202static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10203{
10204 u32 val;
10205
df259d8c
MC		 10206 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10207 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10208 return;
10209
10210 /* Selfboot format */
1820180b 10211 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10212 tg3_get_eeprom_size(tp);
10213 return;
10214 }
10215
6d348f2c 10216 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10217 if (val != 0) {
6d348f2c
MC		 10218 /* This is confusing. We want to operate on the
10219 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10220 * call will read from NVRAM and byteswap the data
10221 * according to the byteswapping settings for all
10222 * other register accesses. This ensures the data we
10223 * want will always reside in the lower 16-bits.
10224 * However, the data in NVRAM is in LE format, which
10225 * means the data from the NVRAM read will always be
10226 * opposite the endianness of the CPU. The 16-bit
10227 * byteswap then brings the data to CPU endianness.
10228 */
10229 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10230 return;
10231 }
10232 }
fd1122a2 10233 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10234}
10235
10236static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10237{
10238 u32 nvcfg1;
10239
10240 nvcfg1 = tr32(NVRAM_CFG1);
10241 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10242 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10243 }
10244 else {
10245 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10246 tw32(NVRAM_CFG1, nvcfg1);
10247 }
10248
4c987487 10249 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10250 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 10251 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10252 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10253 tp->nvram_jedecnum = JEDEC_ATMEL;
10254 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10255 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10256 break;
10257 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10258 tp->nvram_jedecnum = JEDEC_ATMEL;
10259 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10260 break;
10261 case FLASH_VENDOR_ATMEL_EEPROM:
10262 tp->nvram_jedecnum = JEDEC_ATMEL;
10263 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10264 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10265 break;
10266 case FLASH_VENDOR_ST:
10267 tp->nvram_jedecnum = JEDEC_ST;
10268 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10269 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10270 break;
10271 case FLASH_VENDOR_SAIFUN:
10272 tp->nvram_jedecnum = JEDEC_SAIFUN;
10273 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10274 break;
10275 case FLASH_VENDOR_SST_SMALL:
10276 case FLASH_VENDOR_SST_LARGE:
10277 tp->nvram_jedecnum = JEDEC_SST;
10278 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10279 break;
10280 }
10281 }
10282 else {
10283 tp->nvram_jedecnum = JEDEC_ATMEL;
10284 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10285 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10286 }
10287}
10288
361b4ac2
MC		 10289static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10290{
10291 u32 nvcfg1;
10292
10293 nvcfg1 = tr32(NVRAM_CFG1);
10294
e6af301b
MC		 10295 /* NVRAM protection for TPM */
10296 if (nvcfg1 & (1 << 27))
10297 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10298
361b4ac2
MC		 10299 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10300 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10301 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10302 tp->nvram_jedecnum = JEDEC_ATMEL;
10303 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10304 break;
10305 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10306 tp->nvram_jedecnum = JEDEC_ATMEL;
10307 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10308 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10309 break;
10310 case FLASH_5752VENDOR_ST_M45PE10:
10311 case FLASH_5752VENDOR_ST_M45PE20:
10312 case FLASH_5752VENDOR_ST_M45PE40:
10313 tp->nvram_jedecnum = JEDEC_ST;
10314 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10315 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10316 break;
10317 }
10318
10319 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10320 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10321 case FLASH_5752PAGE_SIZE_256:
10322 tp->nvram_pagesize = 256;
10323 break;
10324 case FLASH_5752PAGE_SIZE_512:
10325 tp->nvram_pagesize = 512;
10326 break;
10327 case FLASH_5752PAGE_SIZE_1K:
10328 tp->nvram_pagesize = 1024;
10329 break;
10330 case FLASH_5752PAGE_SIZE_2K:
10331 tp->nvram_pagesize = 2048;
10332 break;
10333 case FLASH_5752PAGE_SIZE_4K:
10334 tp->nvram_pagesize = 4096;
10335 break;
10336 case FLASH_5752PAGE_SIZE_264:
10337 tp->nvram_pagesize = 264;
10338 break;
10339 }
10340 }
10341 else {
10342 /* For eeprom, set pagesize to maximum eeprom size */
10343 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10344
10345 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10346 tw32(NVRAM_CFG1, nvcfg1);
10347 }
10348}
10349
d3c7b886
MC		 10350static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10351{
989a9d23 10352 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10353
10354 nvcfg1 = tr32(NVRAM_CFG1);
10355
10356 /* NVRAM protection for TPM */
989a9d23 10357 if (nvcfg1 & (1 << 27)) {
d3c7b886 10358 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10359 protect = 1;
10360 }
d3c7b886 10361
989a9d23
MC		 10362 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10363 switch (nvcfg1) {
d3c7b886
MC		 10364 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10365 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10366 case FLASH_5755VENDOR_ATMEL_FLASH_3:
70b65a2d 10367 case FLASH_5755VENDOR_ATMEL_FLASH_5:
d3c7b886
MC		 10368 tp->nvram_jedecnum = JEDEC_ATMEL;
10369 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10370 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10371 tp->nvram_pagesize = 264;
70b65a2d
MC		 10372 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10373 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
fd1122a2
MC		 10374 tp->nvram_size = (protect ? 0x3e200 :
10375 TG3_NVRAM_SIZE_512KB);
989a9d23 10376 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
fd1122a2
MC		 10377 tp->nvram_size = (protect ? 0x1f200 :
10378 TG3_NVRAM_SIZE_256KB);
989a9d23 10379 else
fd1122a2
MC		 10380 tp->nvram_size = (protect ? 0x1f200 :
10381 TG3_NVRAM_SIZE_128KB);
d3c7b886
MC		 10382 break;
10383 case FLASH_5752VENDOR_ST_M45PE10:
10384 case FLASH_5752VENDOR_ST_M45PE20:
10385 case FLASH_5752VENDOR_ST_M45PE40:
10386 tp->nvram_jedecnum = JEDEC_ST;
10387 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10388 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10389 tp->nvram_pagesize = 256;
989a9d23 10390 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
fd1122a2
MC		 10391 tp->nvram_size = (protect ?
10392 TG3_NVRAM_SIZE_64KB :
10393 TG3_NVRAM_SIZE_128KB);
989a9d23 10394 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
fd1122a2
MC		 10395 tp->nvram_size = (protect ?
10396 TG3_NVRAM_SIZE_64KB :
10397 TG3_NVRAM_SIZE_256KB);
989a9d23 10398 else
fd1122a2
MC		 10399 tp->nvram_size = (protect ?
10400 TG3_NVRAM_SIZE_128KB :
10401 TG3_NVRAM_SIZE_512KB);
d3c7b886
MC		 10402 break;
10403 }
10404}
10405
1b27777a
MC		 10406static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10407{
10408 u32 nvcfg1;
10409
10410 nvcfg1 = tr32(NVRAM_CFG1);
10411
10412 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10413 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10414 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10415 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10416 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10417 tp->nvram_jedecnum = JEDEC_ATMEL;
10418 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10419 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10420
10421 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10422 tw32(NVRAM_CFG1, nvcfg1);
10423 break;
10424 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10425 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10426 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10427 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10428 tp->nvram_jedecnum = JEDEC_ATMEL;
10429 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10430 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10431 tp->nvram_pagesize = 264;
10432 break;
10433 case FLASH_5752VENDOR_ST_M45PE10:
10434 case FLASH_5752VENDOR_ST_M45PE20:
10435 case FLASH_5752VENDOR_ST_M45PE40:
10436 tp->nvram_jedecnum = JEDEC_ST;
10437 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10438 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10439 tp->nvram_pagesize = 256;
10440 break;
10441 }
10442}
10443
6b91fa02
MC		 10444static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10445{
10446 u32 nvcfg1, protect = 0;
10447
10448 nvcfg1 = tr32(NVRAM_CFG1);
10449
10450 /* NVRAM protection for TPM */
10451 if (nvcfg1 & (1 << 27)) {
10452 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10453 protect = 1;
10454 }
10455
10456 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10457 switch (nvcfg1) {
10458 case FLASH_5761VENDOR_ATMEL_ADB021D:
10459 case FLASH_5761VENDOR_ATMEL_ADB041D:
10460 case FLASH_5761VENDOR_ATMEL_ADB081D:
10461 case FLASH_5761VENDOR_ATMEL_ADB161D:
10462 case FLASH_5761VENDOR_ATMEL_MDB021D:
10463 case FLASH_5761VENDOR_ATMEL_MDB041D:
10464 case FLASH_5761VENDOR_ATMEL_MDB081D:
10465 case FLASH_5761VENDOR_ATMEL_MDB161D:
10466 tp->nvram_jedecnum = JEDEC_ATMEL;
10467 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10468 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10469 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10470 tp->nvram_pagesize = 256;
10471 break;
10472 case FLASH_5761VENDOR_ST_A_M45PE20:
10473 case FLASH_5761VENDOR_ST_A_M45PE40:
10474 case FLASH_5761VENDOR_ST_A_M45PE80:
10475 case FLASH_5761VENDOR_ST_A_M45PE16:
10476 case FLASH_5761VENDOR_ST_M_M45PE20:
10477 case FLASH_5761VENDOR_ST_M_M45PE40:
10478 case FLASH_5761VENDOR_ST_M_M45PE80:
10479 case FLASH_5761VENDOR_ST_M_M45PE16:
10480 tp->nvram_jedecnum = JEDEC_ST;
10481 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10482 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10483 tp->nvram_pagesize = 256;
10484 break;
10485 }
10486
10487 if (protect) {
10488 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10489 } else {
10490 switch (nvcfg1) {
10491 case FLASH_5761VENDOR_ATMEL_ADB161D:
10492 case FLASH_5761VENDOR_ATMEL_MDB161D:
10493 case FLASH_5761VENDOR_ST_A_M45PE16:
10494 case FLASH_5761VENDOR_ST_M_M45PE16:
fd1122a2 10495 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
6b91fa02
MC		 10496 break;
10497 case FLASH_5761VENDOR_ATMEL_ADB081D:
10498 case FLASH_5761VENDOR_ATMEL_MDB081D:
10499 case FLASH_5761VENDOR_ST_A_M45PE80:
10500 case FLASH_5761VENDOR_ST_M_M45PE80:
fd1122a2 10501 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
6b91fa02
MC		 10502 break;
10503 case FLASH_5761VENDOR_ATMEL_ADB041D:
10504 case FLASH_5761VENDOR_ATMEL_MDB041D:
10505 case FLASH_5761VENDOR_ST_A_M45PE40:
10506 case FLASH_5761VENDOR_ST_M_M45PE40:
fd1122a2 10507 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
6b91fa02
MC		 10508 break;
10509 case FLASH_5761VENDOR_ATMEL_ADB021D:
10510 case FLASH_5761VENDOR_ATMEL_MDB021D:
10511 case FLASH_5761VENDOR_ST_A_M45PE20:
10512 case FLASH_5761VENDOR_ST_M_M45PE20:
fd1122a2 10513 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
6b91fa02
MC		 10514 break;
10515 }
10516 }
10517}
10518
b5d3772c
MC		 10519static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10520{
10521 tp->nvram_jedecnum = JEDEC_ATMEL;
10522 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10523 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10524}
10525
321d32a0
MC		 10526static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10527{
10528 u32 nvcfg1;
10529
10530 nvcfg1 = tr32(NVRAM_CFG1);
10531
10532 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10533 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10534 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10535 tp->nvram_jedecnum = JEDEC_ATMEL;
10536 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10537 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10538
10539 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10540 tw32(NVRAM_CFG1, nvcfg1);
10541 return;
10542 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10543 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10544 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10545 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10546 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10547 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10548 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10549 tp->nvram_jedecnum = JEDEC_ATMEL;
10550 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10551 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10552
10553 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10554 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10555 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10556 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10557 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10558 break;
10559 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10560 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10561 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10562 break;
10563 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10564 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10565 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10566 break;
10567 }
10568 break;
10569 case FLASH_5752VENDOR_ST_M45PE10:
10570 case FLASH_5752VENDOR_ST_M45PE20:
10571 case FLASH_5752VENDOR_ST_M45PE40:
10572 tp->nvram_jedecnum = JEDEC_ST;
10573 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10574 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10575
10576 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10577 case FLASH_5752VENDOR_ST_M45PE10:
10578 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10579 break;
10580 case FLASH_5752VENDOR_ST_M45PE20:
10581 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10582 break;
10583 case FLASH_5752VENDOR_ST_M45PE40:
10584 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10585 break;
10586 }
10587 break;
10588 default:
df259d8c 10589 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 10590 return;
10591 }
10592
10593 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10594 case FLASH_5752PAGE_SIZE_256:
10595 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10596 tp->nvram_pagesize = 256;
10597 break;
10598 case FLASH_5752PAGE_SIZE_512:
10599 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10600 tp->nvram_pagesize = 512;
10601 break;
10602 case FLASH_5752PAGE_SIZE_1K:
10603 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10604 tp->nvram_pagesize = 1024;
10605 break;
10606 case FLASH_5752PAGE_SIZE_2K:
10607 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10608 tp->nvram_pagesize = 2048;
10609 break;
10610 case FLASH_5752PAGE_SIZE_4K:
10611 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10612 tp->nvram_pagesize = 4096;
10613 break;
10614 case FLASH_5752PAGE_SIZE_264:
10615 tp->nvram_pagesize = 264;
10616 break;
10617 case FLASH_5752PAGE_SIZE_528:
10618 tp->nvram_pagesize = 528;
10619 break;
10620 }
10621}
10622
1da177e4
LT		 10623/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10624static void __devinit tg3_nvram_init(struct tg3 *tp)
10625{
1da177e4
LT		 10626 tw32_f(GRC_EEPROM_ADDR,
10627 (EEPROM_ADDR_FSM_RESET |
10628 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10629 EEPROM_ADDR_CLKPERD_SHIFT)));
10630
9d57f01c 10631 msleep(1);
1da177e4
LT		 10632
10633 /* Enable seeprom accesses. */
10634 tw32_f(GRC_LOCAL_CTRL,
10635 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10636 udelay(100);
10637
10638 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10639 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10640 tp->tg3_flags |= TG3_FLAG_NVRAM;
10641
ec41c7df
MC		 10642 if (tg3_nvram_lock(tp)) {
10643 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10644 "tg3_nvram_init failed.\n", tp->dev->name);
10645 return;
10646 }
e6af301b 10647 tg3_enable_nvram_access(tp);
1da177e4 10648
989a9d23
MC		 10649 tp->nvram_size = 0;
10650
361b4ac2
MC		 10651 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10652 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10653 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10654 tg3_get_5755_nvram_info(tp);
d30cdd28 10655 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10656 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10657 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10658 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10659 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10660 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10661 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10662 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10663 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10664 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10665 else
10666 tg3_get_nvram_info(tp);
10667
989a9d23
MC		 10668 if (tp->nvram_size == 0)
10669 tg3_get_nvram_size(tp);
1da177e4 10670
e6af301b 10671 tg3_disable_nvram_access(tp);
381291b7 10672 tg3_nvram_unlock(tp);
1da177e4
LT		 10673
10674 } else {
10675 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10676
10677 tg3_get_eeprom_size(tp);
10678 }
10679}
10680
1da177e4
LT		 10681static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10682 u32 offset, u32 len, u8 *buf)
10683{
10684 int i, j, rc = 0;
10685 u32 val;
10686
10687 for (i = 0; i < len; i += 4) {
b9fc7dc5 10688 u32 addr;
a9dc529d 10689 __be32 data;
1da177e4
LT		 10690
10691 addr = offset + i;
10692
10693 memcpy(&data, buf + i, 4);
10694
62cedd11
MC		 10695 /*
10696 * The SEEPROM interface expects the data to always be opposite
10697 * the native endian format. We accomplish this by reversing
10698 * all the operations that would have been performed on the
10699 * data from a call to tg3_nvram_read_be32().
10700 */
10701 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10702
10703 val = tr32(GRC_EEPROM_ADDR);
10704 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10705
10706 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10707 EEPROM_ADDR_READ);
10708 tw32(GRC_EEPROM_ADDR, val |
10709 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10710 (addr & EEPROM_ADDR_ADDR_MASK) |
10711 EEPROM_ADDR_START |
10712 EEPROM_ADDR_WRITE);
6aa20a22 10713
9d57f01c 10714 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10715 val = tr32(GRC_EEPROM_ADDR);
10716
10717 if (val & EEPROM_ADDR_COMPLETE)
10718 break;
9d57f01c 10719 msleep(1);
1da177e4
LT		 10720 }
10721 if (!(val & EEPROM_ADDR_COMPLETE)) {
10722 rc = -EBUSY;
10723 break;
10724 }
10725 }
10726
10727 return rc;
10728}
10729
10730/* offset and length are dword aligned */
10731static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10732 u8 *buf)
10733{
10734 int ret = 0;
10735 u32 pagesize = tp->nvram_pagesize;
10736 u32 pagemask = pagesize - 1;
10737 u32 nvram_cmd;
10738 u8 *tmp;
10739
10740 tmp = kmalloc(pagesize, GFP_KERNEL);
10741 if (tmp == NULL)
10742 return -ENOMEM;
10743
10744 while (len) {
10745 int j;
e6af301b 10746 u32 phy_addr, page_off, size;
1da177e4
LT		 10747
10748 phy_addr = offset & ~pagemask;
6aa20a22 10749
1da177e4 10750 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10751 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10752 (__be32 *) (tmp + j));
10753 if (ret)
1da177e4
LT		 10754 break;
10755 }
10756 if (ret)
10757 break;
10758
10759 page_off = offset & pagemask;
10760 size = pagesize;
10761 if (len < size)
10762 size = len;
10763
10764 len -= size;
10765
10766 memcpy(tmp + page_off, buf, size);
10767
10768 offset = offset + (pagesize - page_off);
10769
e6af301b 10770 tg3_enable_nvram_access(tp);
1da177e4
LT		 10771
10772 /*
10773 * Before we can erase the flash page, we need
10774 * to issue a special "write enable" command.
10775 */
10776 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10777
10778 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10779 break;
10780
10781 /* Erase the target page */
10782 tw32(NVRAM_ADDR, phy_addr);
10783
10784 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10785 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10786
10787 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10788 break;
10789
10790 /* Issue another write enable to start the write. */
10791 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10792
10793 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10794 break;
10795
10796 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10797 __be32 data;
1da177e4 10798
b9fc7dc5 10799 data = *((__be32 *) (tmp + j));
a9dc529d 10800
b9fc7dc5 10801 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10802
10803 tw32(NVRAM_ADDR, phy_addr + j);
10804
10805 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10806 NVRAM_CMD_WR;
10807
10808 if (j == 0)
10809 nvram_cmd |= NVRAM_CMD_FIRST;
10810 else if (j == (pagesize - 4))
10811 nvram_cmd |= NVRAM_CMD_LAST;
10812
10813 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10814 break;
10815 }
10816 if (ret)
10817 break;
10818 }
10819
10820 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10821 tg3_nvram_exec_cmd(tp, nvram_cmd);
10822
10823 kfree(tmp);
10824
10825 return ret;
10826}
10827
10828/* offset and length are dword aligned */
10829static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10830 u8 *buf)
10831{
10832 int i, ret = 0;
10833
10834 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10835 u32 page_off, phy_addr, nvram_cmd;
10836 __be32 data;
1da177e4
LT		 10837
10838 memcpy(&data, buf + i, 4);
b9fc7dc5 10839 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10840
10841 page_off = offset % tp->nvram_pagesize;
10842
1820180b 10843 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10844
10845 tw32(NVRAM_ADDR, phy_addr);
10846
10847 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10848
10849 if ((page_off == 0) || (i == 0))
10850 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10851 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10852 nvram_cmd |= NVRAM_CMD_LAST;
10853
10854 if (i == (len - 4))
10855 nvram_cmd |= NVRAM_CMD_LAST;
10856
321d32a0
MC		 10857 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10858 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10859 (tp->nvram_jedecnum == JEDEC_ST) &&
10860 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10861
10862 if ((ret = tg3_nvram_exec_cmd(tp,
10863 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10864 NVRAM_CMD_DONE)))
10865
10866 break;
10867 }
10868 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10869 /* We always do complete word writes to eeprom. */
10870 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10871 }
10872
10873 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10874 break;
10875 }
10876 return ret;
10877}
10878
10879/* offset and length are dword aligned */
10880static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10881{
10882 int ret;
10883
1da177e4 10884 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10885 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10886 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10887 udelay(40);
10888 }
10889
10890 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10891 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10892 }
10893 else {
10894 u32 grc_mode;
10895
ec41c7df
MC		 10896 ret = tg3_nvram_lock(tp);
10897 if (ret)
10898 return ret;
1da177e4 10899
e6af301b
MC		 10900 tg3_enable_nvram_access(tp);
10901 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10902 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10903 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10904
10905 grc_mode = tr32(GRC_MODE);
10906 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10907
10908 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10909 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10910
10911 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10912 buf);
10913 }
10914 else {
10915 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10916 buf);
10917 }
10918
10919 grc_mode = tr32(GRC_MODE);
10920 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10921
e6af301b 10922 tg3_disable_nvram_access(tp);
1da177e4
LT		 10923 tg3_nvram_unlock(tp);
10924 }
10925
10926 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10927 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10928 udelay(40);
10929 }
10930
10931 return ret;
10932}
10933
10934struct subsys_tbl_ent {
10935 u16 subsys_vendor, subsys_devid;
10936 u32 phy_id;
10937};
10938
10939static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10940 /* Broadcom boards. */
10941 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10942 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10943 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10944 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10945 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10946 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10947 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10948 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10949 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10950 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10951 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10952
10953 /* 3com boards. */
10954 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10955 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10956 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10957 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10958 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10959
10960 /* DELL boards. */
10961 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10962 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10963 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10964 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10965
10966 /* Compaq boards. */
10967 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10968 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10969 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10970 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10971 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10972
10973 /* IBM boards. */
10974 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10975};
10976
10977static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10978{
10979 int i;
10980
10981 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10982 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10983 tp->pdev->subsystem_vendor) &&
10984 (subsys_id_to_phy_id[i].subsys_devid ==
10985 tp->pdev->subsystem_device))
10986 return &subsys_id_to_phy_id[i];
10987 }
10988 return NULL;
10989}
10990
7d0c41ef 10991static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 10992{
1da177e4 10993 u32 val;
caf636c7
MC		 10994 u16 pmcsr;
10995
10996 /* On some early chips the SRAM cannot be accessed in D3hot state,
10997 * so need make sure we're in D0.
10998 */
10999 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11000 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11001 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11002 msleep(1);
7d0c41ef
MC		 11003
11004 /* Make sure register accesses (indirect or otherwise)
11005 * will function correctly.
11006 */
11007 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11008 tp->misc_host_ctrl);
1da177e4 11009
f49639e6
DM		 11010 /* The memory arbiter has to be enabled in order for SRAM accesses
11011 * to succeed. Normally on powerup the tg3 chip firmware will make
11012 * sure it is enabled, but other entities such as system netboot
11013 * code might disable it.
11014 */
11015 val = tr32(MEMARB_MODE);
11016 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11017
1da177e4 11018 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11019 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11020
a85feb8c
GZ		 11021 /* Assume an onboard device and WOL capable by default. */
11022 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11023
b5d3772c 11024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11025 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11026 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11027 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11028 }
0527ba35
MC		 11029 val = tr32(VCPU_CFGSHDW);
11030 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11031 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11032 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11033 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11034 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11035 goto done;
b5d3772c
MC		 11036 }
11037
1da177e4
LT		 11038 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11039 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11040 u32 nic_cfg, led_cfg;
a9daf367 11041 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11042 int eeprom_phy_serdes = 0;
1da177e4
LT		 11043
11044 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11045 tp->nic_sram_data_cfg = nic_cfg;
11046
11047 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11048 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11049 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11050 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11051 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11052 (ver > 0) && (ver < 0x100))
11053 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11054
a9daf367
MC		 11055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11056 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11057
1da177e4
LT		 11058 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11059 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11060 eeprom_phy_serdes = 1;
11061
11062 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11063 if (nic_phy_id != 0) {
11064 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11065 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11066
11067 eeprom_phy_id = (id1 >> 16) << 10;
11068 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11069 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11070 } else
11071 eeprom_phy_id = 0;
11072
7d0c41ef 11073 tp->phy_id = eeprom_phy_id;
747e8f8b 11074 if (eeprom_phy_serdes) {
a4e2b347 11075 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11076 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11077 else
11078 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11079 }
7d0c41ef 11080
cbf46853 11081 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11082 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11083 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11084 else
1da177e4
LT		 11085 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11086
11087 switch (led_cfg) {
11088 default:
11089 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11090 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11091 break;
11092
11093 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11094 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11095 break;
11096
11097 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11098 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11099
11100 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11101 * read on some older 5700/5701 bootcode.
11102 */
11103 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11104 ASIC_REV_5700 ||
11105 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11106 ASIC_REV_5701)
11107 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11108
1da177e4
LT		 11109 break;
11110
11111 case SHASTA_EXT_LED_SHARED:
11112 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11113 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11114 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11115 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11116 LED_CTRL_MODE_PHY_2);
11117 break;
11118
11119 case SHASTA_EXT_LED_MAC:
11120 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11121 break;
11122
11123 case SHASTA_EXT_LED_COMBO:
11124 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11125 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11126 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11127 LED_CTRL_MODE_PHY_2);
11128 break;
11129
855e1111 11130 }
1da177e4
LT		 11131
11132 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11134 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11135 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11136
b2a5c19c
MC		 11137 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11138 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11139
9d26e213 11140 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11141 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11142 if ((tp->pdev->subsystem_vendor ==
11143 PCI_VENDOR_ID_ARIMA) &&
11144 (tp->pdev->subsystem_device == 0x205a ||
11145 tp->pdev->subsystem_device == 0x2063))
11146 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11147 } else {
f49639e6 11148 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11149 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11150 }
1da177e4
LT		 11151
11152 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11153 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11154 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11155 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11156 }
b2b98d4a
MC		 11157
11158 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11159 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11160 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11161
a85feb8c
GZ		 11162 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11163 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11164 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11165
12dac075 11166 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11167 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11168 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11169
1da177e4
LT		 11170 if (cfg2 & (1 << 17))
11171 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11172
11173 /* serdes signal pre-emphasis in register 0x590 set by */
11174 /* bootcode if bit 18 is set */
11175 if (cfg2 & (1 << 18))
11176 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11177
321d32a0
MC		 11178 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11179 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11180 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11181 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11182
8ed5d97e
MC		 11183 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11184 u32 cfg3;
11185
11186 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11187 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11188 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11189 }
a9daf367
MC		 11190
11191 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11192 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11193 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11194 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11195 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11196 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11197 }
05ac4cb7
MC		 11198done:
11199 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11200 device_set_wakeup_enable(&tp->pdev->dev,
11201 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11202}
11203
b2a5c19c
MC		 11204static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11205{
11206 int i;
11207 u32 val;
11208
11209 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11210 tw32(OTP_CTRL, cmd);
11211
11212 /* Wait for up to 1 ms for command to execute. */
11213 for (i = 0; i < 100; i++) {
11214 val = tr32(OTP_STATUS);
11215 if (val & OTP_STATUS_CMD_DONE)
11216 break;
11217 udelay(10);
11218 }
11219
11220 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11221}
11222
11223/* Read the gphy configuration from the OTP region of the chip. The gphy
11224 * configuration is a 32-bit value that straddles the alignment boundary.
11225 * We do two 32-bit reads and then shift and merge the results.
11226 */
11227static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11228{
11229 u32 bhalf_otp, thalf_otp;
11230
11231 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11232
11233 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11234 return 0;
11235
11236 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11237
11238 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11239 return 0;
11240
11241 thalf_otp = tr32(OTP_READ_DATA);
11242
11243 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11244
11245 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11246 return 0;
11247
11248 bhalf_otp = tr32(OTP_READ_DATA);
11249
11250 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11251}
11252
7d0c41ef
MC		 11253static int __devinit tg3_phy_probe(struct tg3 *tp)
11254{
11255 u32 hw_phy_id_1, hw_phy_id_2;
11256 u32 hw_phy_id, hw_phy_id_masked;
11257 int err;
1da177e4 11258
b02fd9e3
MC		 11259 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11260 return tg3_phy_init(tp);
11261
1da177e4 11262 /* Reading the PHY ID register can conflict with ASF
877d0310 11263 * firmware access to the PHY hardware.
1da177e4
LT		 11264 */
11265 err = 0;
0d3031d9
MC		 11266 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11267 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11268 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11269 } else {
11270 /* Now read the physical PHY_ID from the chip and verify
11271 * that it is sane. If it doesn't look good, we fall back
11272 * to either the hard-coded table based PHY_ID and failing
11273 * that the value found in the eeprom area.
11274 */
11275 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11276 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11277
11278 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11279 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11280 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11281
11282 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11283 }
11284
11285 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11286 tp->phy_id = hw_phy_id;
11287 if (hw_phy_id_masked == PHY_ID_BCM8002)
11288 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11289 else
11290 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11291 } else {
7d0c41ef
MC		 11292 if (tp->phy_id != PHY_ID_INVALID) {
11293 /* Do nothing, phy ID already set up in
11294 * tg3_get_eeprom_hw_cfg().
11295 */
1da177e4
LT		 11296 } else {
11297 struct subsys_tbl_ent *p;
11298
11299 /* No eeprom signature? Try the hardcoded
11300 * subsys device table.
11301 */
11302 p = lookup_by_subsys(tp);
11303 if (!p)
11304 return -ENODEV;
11305
11306 tp->phy_id = p->phy_id;
11307 if (!tp->phy_id ||
11308 tp->phy_id == PHY_ID_BCM8002)
11309 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11310 }
11311 }
11312
747e8f8b 11313 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11314 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11315 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11316 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11317
11318 tg3_readphy(tp, MII_BMSR, &bmsr);
11319 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11320 (bmsr & BMSR_LSTATUS))
11321 goto skip_phy_reset;
6aa20a22 11322
1da177e4
LT		 11323 err = tg3_phy_reset(tp);
11324 if (err)
11325 return err;
11326
11327 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11328 ADVERTISE_100HALF | ADVERTISE_100FULL |
11329 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11330 tg3_ctrl = 0;
11331 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11332 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11333 MII_TG3_CTRL_ADV_1000_FULL);
11334 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11335 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11336 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11337 MII_TG3_CTRL_ENABLE_AS_MASTER);
11338 }
11339
3600d918
MC		 11340 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11341 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11342 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11343 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11344 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11345
11346 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11347 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11348
11349 tg3_writephy(tp, MII_BMCR,
11350 BMCR_ANENABLE | BMCR_ANRESTART);
11351 }
11352 tg3_phy_set_wirespeed(tp);
11353
11354 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11355 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11356 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11357 }
11358
11359skip_phy_reset:
11360 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11361 err = tg3_init_5401phy_dsp(tp);
11362 if (err)
11363 return err;
11364 }
11365
11366 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11367 err = tg3_init_5401phy_dsp(tp);
11368 }
11369
747e8f8b 11370 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11371 tp->link_config.advertising =
11372 (ADVERTISED_1000baseT_Half |
11373 ADVERTISED_1000baseT_Full |
11374 ADVERTISED_Autoneg |
11375 ADVERTISED_FIBRE);
11376 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11377 tp->link_config.advertising &=
11378 ~(ADVERTISED_1000baseT_Half |
11379 ADVERTISED_1000baseT_Full);
11380
11381 return err;
11382}
11383
11384static void __devinit tg3_read_partno(struct tg3 *tp)
11385{
6d348f2c 11386 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11387 unsigned int i;
1b27777a 11388 u32 magic;
1da177e4 11389
df259d8c
MC		 11390 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11391 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11392 goto out_not_found;
1da177e4 11393
1820180b 11394 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11395 for (i = 0; i < 256; i += 4) {
11396 u32 tmp;
1da177e4 11397
6d348f2c
MC		 11398 /* The data is in little-endian format in NVRAM.
11399 * Use the big-endian read routines to preserve
11400 * the byte order as it exists in NVRAM.
11401 */
11402 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11403 goto out_not_found;
11404
6d348f2c 11405 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11406 }
11407 } else {
11408 int vpd_cap;
11409
11410 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11411 for (i = 0; i < 256; i += 4) {
11412 u32 tmp, j = 0;
b9fc7dc5 11413 __le32 v;
1b27777a
MC		 11414 u16 tmp16;
11415
11416 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11417 i);
11418 while (j++ < 100) {
11419 pci_read_config_word(tp->pdev, vpd_cap +
11420 PCI_VPD_ADDR, &tmp16);
11421 if (tmp16 & 0x8000)
11422 break;
11423 msleep(1);
11424 }
f49639e6
DM		 11425 if (!(tmp16 & 0x8000))
11426 goto out_not_found;
11427
1b27777a
MC		 11428 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11429 &tmp);
b9fc7dc5 11430 v = cpu_to_le32(tmp);
6d348f2c 11431 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11432 }
1da177e4
LT		 11433 }
11434
11435 /* Now parse and find the part number. */
af2c6a4a 11436 for (i = 0; i < 254; ) {
1da177e4 11437 unsigned char val = vpd_data[i];
af2c6a4a 11438 unsigned int block_end;
1da177e4
LT		 11439
11440 if (val == 0x82 || val == 0x91) {
11441 i = (i + 3 +
11442 (vpd_data[i + 1] +
11443 (vpd_data[i + 2] << 8)));
11444 continue;
11445 }
11446
11447 if (val != 0x90)
11448 goto out_not_found;
11449
11450 block_end = (i + 3 +
11451 (vpd_data[i + 1] +
11452 (vpd_data[i + 2] << 8)));
11453 i += 3;
af2c6a4a
MC		 11454
11455 if (block_end > 256)
11456 goto out_not_found;
11457
11458 while (i < (block_end - 2)) {
1da177e4
LT		 11459 if (vpd_data[i + 0] == 'P' &&
11460 vpd_data[i + 1] == 'N') {
11461 int partno_len = vpd_data[i + 2];
11462
af2c6a4a
MC		 11463 i += 3;
11464 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11465 goto out_not_found;
11466
11467 memcpy(tp->board_part_number,
af2c6a4a 11468 &vpd_data[i], partno_len);
1da177e4
LT		 11469
11470 /* Success. */
11471 return;
11472 }
af2c6a4a 11473 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11474 }
11475
11476 /* Part number not found. */
11477 goto out_not_found;
11478 }
11479
11480out_not_found:
b5d3772c
MC		 11481 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11482 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 11483 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11484 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11485 strcpy(tp->board_part_number, "BCM57780");
11486 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11487 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11488 strcpy(tp->board_part_number, "BCM57760");
11489 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11490 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11491 strcpy(tp->board_part_number, "BCM57790");
b5d3772c
MC		 11492 else
11493 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11494}
11495
9c8a620e
MC		 11496static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11497{
11498 u32 val;
11499
e4f34110 11500 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11501 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11502 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11503 val != 0)
11504 return 0;
11505
11506 return 1;
11507}
11508
acd9c119
MC		 11509static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11510{
ff3a7cb2 11511 u32 val, offset, start, ver_offset;
acd9c119 11512 int i;
ff3a7cb2 11513 bool newver = false;
acd9c119
MC		 11514
11515 if (tg3_nvram_read(tp, 0xc, &offset) ||
11516 tg3_nvram_read(tp, 0x4, &start))
11517 return;
11518
11519 offset = tg3_nvram_logical_addr(tp, offset);
11520
ff3a7cb2 11521 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11522 return;
11523
ff3a7cb2
MC		 11524 if ((val & 0xfc000000) == 0x0c000000) {
11525 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11526 return;
11527
ff3a7cb2
MC		 11528 if (val == 0)
11529 newver = true;
11530 }
11531
11532 if (newver) {
11533 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11534 return;
11535
11536 offset = offset + ver_offset - start;
11537 for (i = 0; i < 16; i += 4) {
11538 __be32 v;
11539 if (tg3_nvram_read_be32(tp, offset + i, &v))
11540 return;
11541
11542 memcpy(tp->fw_ver + i, &v, sizeof(v));
11543 }
11544 } else {
11545 u32 major, minor;
11546
11547 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11548 return;
11549
11550 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11551 TG3_NVM_BCVER_MAJSFT;
11552 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11553 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11554 }
11555}
11556
a6f6cb1c
MC		 11557static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11558{
11559 u32 val, major, minor;
11560
11561 /* Use native endian representation */
11562 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11563 return;
11564
11565 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11566 TG3_NVM_HWSB_CFG1_MAJSFT;
11567 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11568 TG3_NVM_HWSB_CFG1_MINSFT;
11569
11570 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11571}
11572
dfe00d7d
MC		 11573static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11574{
11575 u32 offset, major, minor, build;
11576
11577 tp->fw_ver[0] = 's';
11578 tp->fw_ver[1] = 'b';
11579 tp->fw_ver[2] = '\0';
11580
11581 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11582 return;
11583
11584 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11585 case TG3_EEPROM_SB_REVISION_0:
11586 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11587 break;
11588 case TG3_EEPROM_SB_REVISION_2:
11589 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11590 break;
11591 case TG3_EEPROM_SB_REVISION_3:
11592 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11593 break;
11594 default:
11595 return;
11596 }
11597
e4f34110 11598 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11599 return;
11600
11601 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11602 TG3_EEPROM_SB_EDH_BLD_SHFT;
11603 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11604 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11605 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11606
11607 if (minor > 99 || build > 26)
11608 return;
11609
11610 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11611
11612 if (build > 0) {
11613 tp->fw_ver[8] = 'a' + build - 1;
11614 tp->fw_ver[9] = '\0';
11615 }
11616}
11617
acd9c119 11618static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11619{
11620 u32 val, offset, start;
acd9c119 11621 int i, vlen;
9c8a620e
MC		 11622
11623 for (offset = TG3_NVM_DIR_START;
11624 offset < TG3_NVM_DIR_END;
11625 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11626 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11627 return;
11628
9c8a620e
MC		 11629 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11630 break;
11631 }
11632
11633 if (offset == TG3_NVM_DIR_END)
11634 return;
11635
11636 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11637 start = 0x08000000;
e4f34110 11638 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11639 return;
11640
e4f34110 11641 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11642 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11643 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11644 return;
11645
11646 offset += val - start;
11647
acd9c119 11648 vlen = strlen(tp->fw_ver);
9c8a620e 11649
acd9c119
MC		 11650 tp->fw_ver[vlen++] = ',';
11651 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11652
11653 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11654 __be32 v;
11655 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11656 return;
11657
b9fc7dc5 11658 offset += sizeof(v);
c4e6575c 11659
acd9c119
MC		 11660 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11661 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11662 break;
c4e6575c 11663 }
9c8a620e 11664
acd9c119
MC		 11665 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11666 vlen += sizeof(v);
c4e6575c 11667 }
acd9c119
MC		 11668}
11669
7fd76445
MC		 11670static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11671{
11672 int vlen;
11673 u32 apedata;
11674
11675 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11676 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11677 return;
11678
11679 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11680 if (apedata != APE_SEG_SIG_MAGIC)
11681 return;
11682
11683 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11684 if (!(apedata & APE_FW_STATUS_READY))
11685 return;
11686
11687 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11688
11689 vlen = strlen(tp->fw_ver);
11690
11691 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11692 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11693 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11694 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11695 (apedata & APE_FW_VERSION_BLDMSK));
11696}
11697
acd9c119
MC		 11698static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11699{
11700 u32 val;
11701
df259d8c
MC		 11702 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11703 tp->fw_ver[0] = 's';
11704 tp->fw_ver[1] = 'b';
11705 tp->fw_ver[2] = '\0';
11706
11707 return;
11708 }
11709
acd9c119
MC		 11710 if (tg3_nvram_read(tp, 0, &val))
11711 return;
11712
11713 if (val == TG3_EEPROM_MAGIC)
11714 tg3_read_bc_ver(tp);
11715 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11716 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11717 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11718 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11719 else
11720 return;
11721
11722 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11723 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11724 return;
11725
11726 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11727
11728 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11729}
11730
7544b097
MC		 11731static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11732
1da177e4
LT		 11733static int __devinit tg3_get_invariants(struct tg3 *tp)
11734{
11735 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11736 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11737 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11738 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11739 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11740 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11741 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11742 { },
11743 };
11744 u32 misc_ctrl_reg;
1da177e4
LT		 11745 u32 pci_state_reg, grc_misc_cfg;
11746 u32 val;
11747 u16 pci_cmd;
5e7dfd0f 11748 int err;
1da177e4 11749
1da177e4
LT		 11750 /* Force memory write invalidate off. If we leave it on,
11751 * then on 5700_BX chips we have to enable a workaround.
11752 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11753 * to match the cacheline size. The Broadcom driver have this
11754 * workaround but turns MWI off all the times so never uses
11755 * it. This seems to suggest that the workaround is insufficient.
11756 */
11757 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11758 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11759 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11760
11761 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11762 * has the register indirect write enable bit set before
11763 * we try to access any of the MMIO registers. It is also
11764 * critical that the PCI-X hw workaround situation is decided
11765 * before that as well.
11766 */
11767 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11768 &misc_ctrl_reg);
11769
11770 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11771 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11772 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11773 u32 prod_id_asic_rev;
11774
11775 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11776 &prod_id_asic_rev);
321d32a0 11777 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11778 }
1da177e4 11779
ff645bec
MC		 11780 /* Wrong chip ID in 5752 A0. This code can be removed later
11781 * as A0 is not in production.
11782 */
11783 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11784 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11785
6892914f
MC		 11786 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11787 * we need to disable memory and use config. cycles
11788 * only to access all registers. The 5702/03 chips
11789 * can mistakenly decode the special cycles from the
11790 * ICH chipsets as memory write cycles, causing corruption
11791 * of register and memory space. Only certain ICH bridges
11792 * will drive special cycles with non-zero data during the
11793 * address phase which can fall within the 5703's address
11794 * range. This is not an ICH bug as the PCI spec allows
11795 * non-zero address during special cycles. However, only
11796 * these ICH bridges are known to drive non-zero addresses
11797 * during special cycles.
11798 *
11799 * Since special cycles do not cross PCI bridges, we only
11800 * enable this workaround if the 5703 is on the secondary
11801 * bus of these ICH bridges.
11802 */
11803 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11804 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11805 static struct tg3_dev_id {
11806 u32 vendor;
11807 u32 device;
11808 u32 rev;
11809 } ich_chipsets[] = {
11810 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11811 PCI_ANY_ID },
11812 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11813 PCI_ANY_ID },
11814 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11815 0xa },
11816 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11817 PCI_ANY_ID },
11818 { },
11819 };
11820 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11821 struct pci_dev *bridge = NULL;
11822
11823 while (pci_id->vendor != 0) {
11824 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11825 bridge);
11826 if (!bridge) {
11827 pci_id++;
11828 continue;
11829 }
11830 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11831 if (bridge->revision > pci_id->rev)
6892914f
MC		 11832 continue;
11833 }
11834 if (bridge->subordinate &&
11835 (bridge->subordinate->number ==
11836 tp->pdev->bus->number)) {
11837
11838 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11839 pci_dev_put(bridge);
11840 break;
11841 }
11842 }
11843 }
11844
41588ba1
MC		 11845 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11846 static struct tg3_dev_id {
11847 u32 vendor;
11848 u32 device;
11849 } bridge_chipsets[] = {
11850 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11851 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11852 { },
11853 };
11854 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11855 struct pci_dev *bridge = NULL;
11856
11857 while (pci_id->vendor != 0) {
11858 bridge = pci_get_device(pci_id->vendor,
11859 pci_id->device,
11860 bridge);
11861 if (!bridge) {
11862 pci_id++;
11863 continue;
11864 }
11865 if (bridge->subordinate &&
11866 (bridge->subordinate->number <=
11867 tp->pdev->bus->number) &&
11868 (bridge->subordinate->subordinate >=
11869 tp->pdev->bus->number)) {
11870 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11871 pci_dev_put(bridge);
11872 break;
11873 }
11874 }
11875 }
11876
4a29cc2e
MC		 11877 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11878 * DMA addresses > 40-bit. This bridge may have other additional
11879 * 57xx devices behind it in some 4-port NIC designs for example.
11880 * Any tg3 device found behind the bridge will also need the 40-bit
11881 * DMA workaround.
11882 */
a4e2b347
MC		 11883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11885 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11886 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11887 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11888 }
4a29cc2e
MC		 11889 else {
11890 struct pci_dev *bridge = NULL;
11891
11892 do {
11893 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11894 PCI_DEVICE_ID_SERVERWORKS_EPB,
11895 bridge);
11896 if (bridge && bridge->subordinate &&
11897 (bridge->subordinate->number <=
11898 tp->pdev->bus->number) &&
11899 (bridge->subordinate->subordinate >=
11900 tp->pdev->bus->number)) {
11901 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11902 pci_dev_put(bridge);
11903 break;
11904 }
11905 } while (bridge);
11906 }
4cf78e4f 11907
1da177e4
LT		 11908 /* Initialize misc host control in PCI block. */
11909 tp->misc_host_ctrl |= (misc_ctrl_reg &
11910 MISC_HOST_CTRL_CHIPREV);
11911 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11912 tp->misc_host_ctrl);
11913
7544b097
MC		 11914 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11915 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11916 tp->pdev_peer = tg3_find_peer(tp);
11917
321d32a0
MC		 11918 /* Intentionally exclude ASIC_REV_5906 */
11919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 11923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 11924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11925 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11926
11927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 11929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 11930 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 11931 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11932 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11933
1b440c56
JL		 11934 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11935 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11936 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11937
027455ad
MC		 11938 /* 5700 B0 chips do not support checksumming correctly due
11939 * to hardware bugs.
11940 */
11941 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11942 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11943 else {
11944 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11945 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11946 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11947 tp->dev->features |= NETIF_F_IPV6_CSUM;
11948 }
11949
5a6f3074 11950 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 11951 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11952 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11953 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11954 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11955 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11956 tp->pdev_peer == tp->pdev))
11957 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11958
321d32a0 11959 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 11960 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 11961 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 11962 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 11963 } else {
7f62ad5d 11964 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 11965 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11966 ASIC_REV_5750 &&
11967 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 11968 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 11969 }
5a6f3074 11970 }
1da177e4 11971
f51f3562
MC		 11972 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11973 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6
MC		 11974 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11975
52f4490c
MC		 11976 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11977 &pci_state_reg);
11978
5e7dfd0f
MC		 11979 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11980 if (tp->pcie_cap != 0) {
11981 u16 lnkctl;
11982
1da177e4 11983 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 11984
11985 pcie_set_readrq(tp->pdev, 4096);
11986
5e7dfd0f
MC		 11987 pci_read_config_word(tp->pdev,
11988 tp->pcie_cap + PCI_EXP_LNKCTL,
11989 &lnkctl);
11990 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 11992 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 11993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 11994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 11995 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
11996 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 11997 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 11998 }
52f4490c 11999 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12000 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12001 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12002 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12003 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12004 if (!tp->pcix_cap) {
12005 printk(KERN_ERR PFX "Cannot find PCI-X "
12006 "capability, aborting.\n");
12007 return -EIO;
12008 }
12009
12010 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12011 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12012 }
1da177e4 12013
399de50b
MC		 12014 /* If we have an AMD 762 or VIA K8T800 chipset, write
12015 * reordering to the mailbox registers done by the host
12016 * controller can cause major troubles. We read back from
12017 * every mailbox register write to force the writes to be
12018 * posted to the chip in order.
12019 */
12020 if (pci_dev_present(write_reorder_chipsets) &&
12021 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12022 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12023
69fc4053
MC		 12024 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12025 &tp->pci_cacheline_sz);
12026 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12027 &tp->pci_lat_timer);
1da177e4
LT		 12028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12029 tp->pci_lat_timer < 64) {
12030 tp->pci_lat_timer = 64;
69fc4053
MC		 12031 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12032 tp->pci_lat_timer);
1da177e4
LT		 12033 }
12034
52f4490c
MC		 12035 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12036 /* 5700 BX chips need to have their TX producer index
12037 * mailboxes written twice to workaround a bug.
12038 */
12039 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12040
52f4490c 12041 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12042 *
12043 * The workaround is to use indirect register accesses
12044 * for all chip writes not to mailbox registers.
12045 */
52f4490c 12046 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12047 u32 pm_reg;
1da177e4
LT		 12048
12049 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12050
12051 /* The chip can have it's power management PCI config
12052 * space registers clobbered due to this bug.
12053 * So explicitly force the chip into D0 here.
12054 */
9974a356
MC		 12055 pci_read_config_dword(tp->pdev,
12056 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12057 &pm_reg);
12058 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12059 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12060 pci_write_config_dword(tp->pdev,
12061 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12062 pm_reg);
12063
12064 /* Also, force SERR#/PERR# in PCI command. */
12065 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12066 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12067 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12068 }
12069 }
12070
1da177e4
LT		 12071 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12072 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12073 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12074 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12075
12076 /* Chip-specific fixup from Broadcom driver */
12077 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12078 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12079 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12080 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12081 }
12082
1ee582d8 12083 /* Default fast path register access methods */
20094930 12084 tp->read32 = tg3_read32;
1ee582d8 12085 tp->write32 = tg3_write32;
09ee929c 12086 tp->read32_mbox = tg3_read32;
20094930 12087 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12088 tp->write32_tx_mbox = tg3_write32;
12089 tp->write32_rx_mbox = tg3_write32;
12090
12091 /* Various workaround register access methods */
12092 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12093 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12094 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12095 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12096 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12097 /*
12098 * Back to back register writes can cause problems on these
12099 * chips, the workaround is to read back all reg writes
12100 * except those to mailbox regs.
12101 *
12102 * See tg3_write_indirect_reg32().
12103 */
1ee582d8 12104 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12105 }
12106
1ee582d8
MC		 12107
12108 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12109 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12110 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12111 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12112 tp->write32_rx_mbox = tg3_write_flush_reg32;
12113 }
20094930 12114
6892914f
MC		 12115 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12116 tp->read32 = tg3_read_indirect_reg32;
12117 tp->write32 = tg3_write_indirect_reg32;
12118 tp->read32_mbox = tg3_read_indirect_mbox;
12119 tp->write32_mbox = tg3_write_indirect_mbox;
12120 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12121 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12122
12123 iounmap(tp->regs);
22abe310 12124 tp->regs = NULL;
6892914f
MC		 12125
12126 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12127 pci_cmd &= ~PCI_COMMAND_MEMORY;
12128 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12129 }
b5d3772c
MC		 12130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12131 tp->read32_mbox = tg3_read32_mbox_5906;
12132 tp->write32_mbox = tg3_write32_mbox_5906;
12133 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12134 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12135 }
6892914f 12136
bbadf503
MC		 12137 if (tp->write32 == tg3_write_indirect_reg32 ||
12138 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12139 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12141 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12142
7d0c41ef 12143 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12144 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12145 * determined before calling tg3_set_power_state() so that
12146 * we know whether or not to switch out of Vaux power.
12147 * When the flag is set, it means that GPIO1 is used for eeprom
12148 * write protect and also implies that it is a LOM where GPIOs
12149 * are not used to switch power.
6aa20a22 12150 */
7d0c41ef
MC		 12151 tg3_get_eeprom_hw_cfg(tp);
12152
0d3031d9
MC		 12153 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12154 /* Allow reads and writes to the
12155 * APE register and memory space.
12156 */
12157 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12158 PCISTATE_ALLOW_APE_SHMEM_WR;
12159 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12160 pci_state_reg);
12161 }
12162
9936bcf6 12163 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12164 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12165 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12167 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12168
314fba34
MC		 12169 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12170 * GPIO1 driven high will bring 5700's external PHY out of reset.
12171 * It is also used as eeprom write protect on LOMs.
12172 */
12173 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12174 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12175 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12176 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12177 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12178 /* Unused GPIO3 must be driven as output on 5752 because there
12179 * are no pull-up resistors on unused GPIO pins.
12180 */
12181 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12182 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12183
321d32a0
MC		 12184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12185 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12186 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12187
8d519ab2
MC		 12188 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12189 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12190 /* Turn off the debug UART. */
12191 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12192 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12193 /* Keep VMain power. */
12194 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12195 GRC_LCLCTRL_GPIO_OUTPUT0;
12196 }
12197
1da177e4 12198 /* Force the chip into D0. */
bc1c7567 12199 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12200 if (err) {
12201 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12202 pci_name(tp->pdev));
12203 return err;
12204 }
12205
1da177e4
LT		 12206 /* Derive initial jumbo mode from MTU assigned in
12207 * ether_setup() via the alloc_etherdev() call
12208 */
0f893dc6 12209 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12210 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12211 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12212
12213 /* Determine WakeOnLan speed to use. */
12214 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12215 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12216 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12217 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12218 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12219 } else {
12220 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12221 }
12222
12223 /* A few boards don't want Ethernet@WireSpeed phy feature */
12224 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12225 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12226 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12227 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
b5d3772c 12228 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
747e8f8b 12229 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12230 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12231
12232 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12233 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12234 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12235 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12236 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12237
321d32a0
MC		 12238 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12239 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12240 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12241 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12242 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12243 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12244 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12245 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12246 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12247 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12248 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12249 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12250 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12251 } else
c424cb24
MC		 12252 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12253 }
1da177e4 12254
b2a5c19c
MC		 12255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12256 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12257 tp->phy_otp = tg3_read_otp_phycfg(tp);
12258 if (tp->phy_otp == 0)
12259 tp->phy_otp = TG3_OTP_DEFAULT;
12260 }
12261
f51f3562 12262 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12263 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12264 else
12265 tp->mi_mode = MAC_MI_MODE_BASE;
12266
1da177e4 12267 tp->coalesce_mode = 0;
1da177e4
LT		 12268 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12269 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12270 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12271
321d32a0
MC		 12272 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12273 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12274 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12275
158d7abd
MC		 12276 err = tg3_mdio_init(tp);
12277 if (err)
12278 return err;
1da177e4
LT		 12279
12280 /* Initialize data/descriptor byte/word swapping. */
12281 val = tr32(GRC_MODE);
12282 val &= GRC_MODE_HOST_STACKUP;
12283 tw32(GRC_MODE, val | tp->grc_mode);
12284
12285 tg3_switch_clocks(tp);
12286
12287 /* Clear this out for sanity. */
12288 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12289
12290 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12291 &pci_state_reg);
12292 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12293 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12294 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12295
12296 if (chiprevid == CHIPREV_ID_5701_A0 ||
12297 chiprevid == CHIPREV_ID_5701_B0 ||
12298 chiprevid == CHIPREV_ID_5701_B2 ||
12299 chiprevid == CHIPREV_ID_5701_B5) {
12300 void __iomem *sram_base;
12301
12302 /* Write some dummy words into the SRAM status block
12303 * area, see if it reads back correctly. If the return
12304 * value is bad, force enable the PCIX workaround.
12305 */
12306 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12307
12308 writel(0x00000000, sram_base);
12309 writel(0x00000000, sram_base + 4);
12310 writel(0xffffffff, sram_base + 4);
12311 if (readl(sram_base) != 0x00000000)
12312 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12313 }
12314 }
12315
12316 udelay(50);
12317 tg3_nvram_init(tp);
12318
12319 grc_misc_cfg = tr32(GRC_MISC_CFG);
12320 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12321
1da177e4
LT		 12322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12323 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12324 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12325 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12326
fac9b83e
DM		 12327 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12328 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12329 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12330 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12331 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12332 HOSTCC_MODE_CLRTICK_TXBD);
12333
12334 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12335 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12336 tp->misc_host_ctrl);
12337 }
12338
3bda1258
MC		 12339 /* Preserve the APE MAC_MODE bits */
12340 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12341 tp->mac_mode = tr32(MAC_MODE) |
12342 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12343 else
12344 tp->mac_mode = TG3_DEF_MAC_MODE;
12345
1da177e4
LT		 12346 /* these are limited to 10/100 only */
12347 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12348 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12349 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12350 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12351 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12352 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12353 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12354 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12355 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12356 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12357 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12358 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
b5d3772c 12359 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1da177e4
LT		 12360 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12361
12362 err = tg3_phy_probe(tp);
12363 if (err) {
12364 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12365 pci_name(tp->pdev), err);
12366 /* ... but do not return immediately ... */
b02fd9e3 12367 tg3_mdio_fini(tp);
1da177e4
LT		 12368 }
12369
12370 tg3_read_partno(tp);
c4e6575c 12371 tg3_read_fw_ver(tp);
1da177e4
LT		 12372
12373 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12374 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12375 } else {
12376 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12377 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12378 else
12379 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12380 }
12381
12382 /* 5700 {AX,BX} chips have a broken status block link
12383 * change bit implementation, so we must use the
12384 * status register in those cases.
12385 */
12386 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12387 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12388 else
12389 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12390
12391 /* The led_ctrl is set during tg3_phy_probe, here we might
12392 * have to force the link status polling mechanism based
12393 * upon subsystem IDs.
12394 */
12395 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12397 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12398 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12399 TG3_FLAG_USE_LINKCHG_REG);
12400 }
12401
12402 /* For all SERDES we poll the MAC status register. */
12403 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12404 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12405 else
12406 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12407
ad829268 12408 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12410 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12411 tp->rx_offset = 0;
12412
f92905de
MC		 12413 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12414
12415 /* Increment the rx prod index on the rx std ring by at most
12416 * 8 for these chips to workaround hw errata.
12417 */
12418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12420 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12421 tp->rx_std_max_post = 8;
12422
8ed5d97e
MC		 12423 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12424 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12425 PCIE_PWR_MGMT_L1_THRESH_MSK;
12426
1da177e4
LT		 12427 return err;
12428}
12429
49b6e95f 12430#ifdef CONFIG_SPARC
1da177e4
LT		 12431static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12432{
12433 struct net_device *dev = tp->dev;
12434 struct pci_dev *pdev = tp->pdev;
49b6e95f 12435 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12436 const unsigned char *addr;
49b6e95f
DM		 12437 int len;
12438
12439 addr = of_get_property(dp, "local-mac-address", &len);
12440 if (addr && len == 6) {
12441 memcpy(dev->dev_addr, addr, 6);
12442 memcpy(dev->perm_addr, dev->dev_addr, 6);
12443 return 0;
1da177e4
LT		 12444 }
12445 return -ENODEV;
12446}
12447
12448static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12449{
12450 struct net_device *dev = tp->dev;
12451
12452 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12453 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12454 return 0;
12455}
12456#endif
12457
12458static int __devinit tg3_get_device_address(struct tg3 *tp)
12459{
12460 struct net_device *dev = tp->dev;
12461 u32 hi, lo, mac_offset;
008652b3 12462 int addr_ok = 0;
1da177e4 12463
49b6e95f 12464#ifdef CONFIG_SPARC
1da177e4
LT		 12465 if (!tg3_get_macaddr_sparc(tp))
12466 return 0;
12467#endif
12468
12469 mac_offset = 0x7c;
f49639e6 12470 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12471 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12472 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12473 mac_offset = 0xcc;
12474 if (tg3_nvram_lock(tp))
12475 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12476 else
12477 tg3_nvram_unlock(tp);
12478 }
b5d3772c
MC		 12479 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12480 mac_offset = 0x10;
1da177e4
LT		 12481
12482 /* First try to get it from MAC address mailbox. */
12483 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12484 if ((hi >> 16) == 0x484b) {
12485 dev->dev_addr[0] = (hi >> 8) & 0xff;
12486 dev->dev_addr[1] = (hi >> 0) & 0xff;
12487
12488 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12489 dev->dev_addr[2] = (lo >> 24) & 0xff;
12490 dev->dev_addr[3] = (lo >> 16) & 0xff;
12491 dev->dev_addr[4] = (lo >> 8) & 0xff;
12492 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12493
008652b3
MC		 12494 /* Some old bootcode may report a 0 MAC address in SRAM */
12495 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12496 }
12497 if (!addr_ok) {
12498 /* Next, try NVRAM. */
df259d8c
MC		 12499 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12500 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12501 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12502 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12503 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12504 }
12505 /* Finally just fetch it out of the MAC control regs. */
12506 else {
12507 hi = tr32(MAC_ADDR_0_HIGH);
12508 lo = tr32(MAC_ADDR_0_LOW);
12509
12510 dev->dev_addr[5] = lo & 0xff;
12511 dev->dev_addr[4] = (lo >> 8) & 0xff;
12512 dev->dev_addr[3] = (lo >> 16) & 0xff;
12513 dev->dev_addr[2] = (lo >> 24) & 0xff;
12514 dev->dev_addr[1] = hi & 0xff;
12515 dev->dev_addr[0] = (hi >> 8) & 0xff;
12516 }
1da177e4
LT		 12517 }
12518
12519 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12520#ifdef CONFIG_SPARC
1da177e4
LT		 12521 if (!tg3_get_default_macaddr_sparc(tp))
12522 return 0;
12523#endif
12524 return -EINVAL;
12525 }
2ff43697 12526 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12527 return 0;
12528}
12529
59e6b434
DM		 12530#define BOUNDARY_SINGLE_CACHELINE 1
12531#define BOUNDARY_MULTI_CACHELINE 2
12532
12533static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12534{
12535 int cacheline_size;
12536 u8 byte;
12537 int goal;
12538
12539 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12540 if (byte == 0)
12541 cacheline_size = 1024;
12542 else
12543 cacheline_size = (int) byte * 4;
12544
12545 /* On 5703 and later chips, the boundary bits have no
12546 * effect.
12547 */
12548 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12549 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12550 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12551 goto out;
12552
12553#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12554 goal = BOUNDARY_MULTI_CACHELINE;
12555#else
12556#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12557 goal = BOUNDARY_SINGLE_CACHELINE;
12558#else
12559 goal = 0;
12560#endif
12561#endif
12562
12563 if (!goal)
12564 goto out;
12565
12566 /* PCI controllers on most RISC systems tend to disconnect
12567 * when a device tries to burst across a cache-line boundary.
12568 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12569 *
12570 * Unfortunately, for PCI-E there are only limited
12571 * write-side controls for this, and thus for reads
12572 * we will still get the disconnects. We'll also waste
12573 * these PCI cycles for both read and write for chips
12574 * other than 5700 and 5701 which do not implement the
12575 * boundary bits.
12576 */
12577 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12578 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12579 switch (cacheline_size) {
12580 case 16:
12581 case 32:
12582 case 64:
12583 case 128:
12584 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12585 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12586 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12587 } else {
12588 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12589 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12590 }
12591 break;
12592
12593 case 256:
12594 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12595 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12596 break;
12597
12598 default:
12599 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12600 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12601 break;
855e1111 12602 }
59e6b434
DM		 12603 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12604 switch (cacheline_size) {
12605 case 16:
12606 case 32:
12607 case 64:
12608 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12609 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12610 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12611 break;
12612 }
12613 /* fallthrough */
12614 case 128:
12615 default:
12616 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12617 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12618 break;
855e1111 12619 }
59e6b434
DM		 12620 } else {
12621 switch (cacheline_size) {
12622 case 16:
12623 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12624 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12625 DMA_RWCTRL_WRITE_BNDRY_16);
12626 break;
12627 }
12628 /* fallthrough */
12629 case 32:
12630 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12631 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12632 DMA_RWCTRL_WRITE_BNDRY_32);
12633 break;
12634 }
12635 /* fallthrough */
12636 case 64:
12637 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12638 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12639 DMA_RWCTRL_WRITE_BNDRY_64);
12640 break;
12641 }
12642 /* fallthrough */
12643 case 128:
12644 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12645 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12646 DMA_RWCTRL_WRITE_BNDRY_128);
12647 break;
12648 }
12649 /* fallthrough */
12650 case 256:
12651 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12652 DMA_RWCTRL_WRITE_BNDRY_256);
12653 break;
12654 case 512:
12655 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12656 DMA_RWCTRL_WRITE_BNDRY_512);
12657 break;
12658 case 1024:
12659 default:
12660 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12661 DMA_RWCTRL_WRITE_BNDRY_1024);
12662 break;
855e1111 12663 }
59e6b434
DM		 12664 }
12665
12666out:
12667 return val;
12668}
12669
1da177e4
LT		 12670static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12671{
12672 struct tg3_internal_buffer_desc test_desc;
12673 u32 sram_dma_descs;
12674 int i, ret;
12675
12676 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12677
12678 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12679 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12680 tw32(RDMAC_STATUS, 0);
12681 tw32(WDMAC_STATUS, 0);
12682
12683 tw32(BUFMGR_MODE, 0);
12684 tw32(FTQ_RESET, 0);
12685
12686 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12687 test_desc.addr_lo = buf_dma & 0xffffffff;
12688 test_desc.nic_mbuf = 0x00002100;
12689 test_desc.len = size;
12690
12691 /*
12692 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12693 * the *second* time the tg3 driver was getting loaded after an
12694 * initial scan.
12695 *
12696 * Broadcom tells me:
12697 * ...the DMA engine is connected to the GRC block and a DMA
12698 * reset may affect the GRC block in some unpredictable way...
12699 * The behavior of resets to individual blocks has not been tested.
12700 *
12701 * Broadcom noted the GRC reset will also reset all sub-components.
12702 */
12703 if (to_device) {
12704 test_desc.cqid_sqid = (13 << 8) | 2;
12705
12706 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12707 udelay(40);
12708 } else {
12709 test_desc.cqid_sqid = (16 << 8) | 7;
12710
12711 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12712 udelay(40);
12713 }
12714 test_desc.flags = 0x00000005;
12715
12716 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12717 u32 val;
12718
12719 val = *(((u32 *)&test_desc) + i);
12720 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12721 sram_dma_descs + (i * sizeof(u32)));
12722 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12723 }
12724 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12725
12726 if (to_device) {
12727 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12728 } else {
12729 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12730 }
12731
12732 ret = -ENODEV;
12733 for (i = 0; i < 40; i++) {
12734 u32 val;
12735
12736 if (to_device)
12737 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12738 else
12739 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12740 if ((val & 0xffff) == sram_dma_descs) {
12741 ret = 0;
12742 break;
12743 }
12744
12745 udelay(100);
12746 }
12747
12748 return ret;
12749}
12750
ded7340d 12751#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12752
12753static int __devinit tg3_test_dma(struct tg3 *tp)
12754{
12755 dma_addr_t buf_dma;
59e6b434 12756 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12757 int ret;
12758
12759 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12760 if (!buf) {
12761 ret = -ENOMEM;
12762 goto out_nofree;
12763 }
12764
12765 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12766 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12767
59e6b434 12768 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12769
12770 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12771 /* DMA read watermark not used on PCIE */
12772 tp->dma_rwctrl |= 0x00180000;
12773 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12776 tp->dma_rwctrl |= 0x003f0000;
12777 else
12778 tp->dma_rwctrl |= 0x003f000f;
12779 } else {
12780 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12782 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12783 u32 read_water = 0x7;
1da177e4 12784
4a29cc2e
MC		 12785 /* If the 5704 is behind the EPB bridge, we can
12786 * do the less restrictive ONE_DMA workaround for
12787 * better performance.
12788 */
12789 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12790 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12791 tp->dma_rwctrl |= 0x8000;
12792 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12793 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12794
49afdeb6
MC		 12795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12796 read_water = 4;
59e6b434 12797 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12798 tp->dma_rwctrl |=
12799 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12800 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12801 (1 << 23);
4cf78e4f
MC		 12802 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12803 /* 5780 always in PCIX mode */
12804 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12805 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12806 /* 5714 always in PCIX mode */
12807 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12808 } else {
12809 tp->dma_rwctrl |= 0x001b000f;
12810 }
12811 }
12812
12813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12814 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12815 tp->dma_rwctrl &= 0xfffffff0;
12816
12817 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12818 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12819 /* Remove this if it causes problems for some boards. */
12820 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12821
12822 /* On 5700/5701 chips, we need to set this bit.
12823 * Otherwise the chip will issue cacheline transactions
12824 * to streamable DMA memory with not all the byte
12825 * enables turned on. This is an error on several
12826 * RISC PCI controllers, in particular sparc64.
12827 *
12828 * On 5703/5704 chips, this bit has been reassigned
12829 * a different meaning. In particular, it is used
12830 * on those chips to enable a PCI-X workaround.
12831 */
12832 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12833 }
12834
12835 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12836
12837#if 0
12838 /* Unneeded, already done by tg3_get_invariants. */
12839 tg3_switch_clocks(tp);
12840#endif
12841
12842 ret = 0;
12843 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12844 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12845 goto out;
12846
59e6b434
DM		 12847 /* It is best to perform DMA test with maximum write burst size
12848 * to expose the 5700/5701 write DMA bug.
12849 */
12850 saved_dma_rwctrl = tp->dma_rwctrl;
12851 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12852 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12853
1da177e4
LT		 12854 while (1) {
12855 u32 *p = buf, i;
12856
12857 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12858 p[i] = i;
12859
12860 /* Send the buffer to the chip. */
12861 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12862 if (ret) {
12863 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12864 break;
12865 }
12866
12867#if 0
12868 /* validate data reached card RAM correctly. */
12869 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12870 u32 val;
12871 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12872 if (le32_to_cpu(val) != p[i]) {
12873 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12874 /* ret = -ENODEV here? */
12875 }
12876 p[i] = 0;
12877 }
12878#endif
12879 /* Now read it back. */
12880 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12881 if (ret) {
12882 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12883
12884 break;
12885 }
12886
12887 /* Verify it. */
12888 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12889 if (p[i] == i)
12890 continue;
12891
59e6b434
DM		 12892 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12893 DMA_RWCTRL_WRITE_BNDRY_16) {
12894 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12895 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12896 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12897 break;
12898 } else {
12899 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12900 ret = -ENODEV;
12901 goto out;
12902 }
12903 }
12904
12905 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12906 /* Success. */
12907 ret = 0;
12908 break;
12909 }
12910 }
59e6b434
DM		 12911 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12912 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12913 static struct pci_device_id dma_wait_state_chipsets[] = {
12914 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12915 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12916 { },
12917 };
12918
59e6b434 12919 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12920 * now look for chipsets that are known to expose the
12921 * DMA bug without failing the test.
59e6b434 12922 */
6d1cfbab
MC		 12923 if (pci_dev_present(dma_wait_state_chipsets)) {
12924 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12925 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12926 }
12927 else
12928 /* Safe to use the calculated DMA boundary. */
12929 tp->dma_rwctrl = saved_dma_rwctrl;
12930
59e6b434
DM		 12931 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12932 }
1da177e4
LT		 12933
12934out:
12935 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12936out_nofree:
12937 return ret;
12938}
12939
12940static void __devinit tg3_init_link_config(struct tg3 *tp)
12941{
12942 tp->link_config.advertising =
12943 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12944 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12945 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12946 ADVERTISED_Autoneg | ADVERTISED_MII);
12947 tp->link_config.speed = SPEED_INVALID;
12948 tp->link_config.duplex = DUPLEX_INVALID;
12949 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 12950 tp->link_config.active_speed = SPEED_INVALID;
12951 tp->link_config.active_duplex = DUPLEX_INVALID;
12952 tp->link_config.phy_is_low_power = 0;
12953 tp->link_config.orig_speed = SPEED_INVALID;
12954 tp->link_config.orig_duplex = DUPLEX_INVALID;
12955 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12956}
12957
12958static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12959{
fdfec172
MC		 12960 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12961 tp->bufmgr_config.mbuf_read_dma_low_water =
12962 DEFAULT_MB_RDMA_LOW_WATER_5705;
12963 tp->bufmgr_config.mbuf_mac_rx_low_water =
12964 DEFAULT_MB_MACRX_LOW_WATER_5705;
12965 tp->bufmgr_config.mbuf_high_water =
12966 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 12967 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12968 tp->bufmgr_config.mbuf_mac_rx_low_water =
12969 DEFAULT_MB_MACRX_LOW_WATER_5906;
12970 tp->bufmgr_config.mbuf_high_water =
12971 DEFAULT_MB_HIGH_WATER_5906;
12972 }
fdfec172
MC		 12973
12974 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12975 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12976 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12977 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12978 tp->bufmgr_config.mbuf_high_water_jumbo =
12979 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12980 } else {
12981 tp->bufmgr_config.mbuf_read_dma_low_water =
12982 DEFAULT_MB_RDMA_LOW_WATER;
12983 tp->bufmgr_config.mbuf_mac_rx_low_water =
12984 DEFAULT_MB_MACRX_LOW_WATER;
12985 tp->bufmgr_config.mbuf_high_water =
12986 DEFAULT_MB_HIGH_WATER;
12987
12988 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12989 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12990 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12991 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12992 tp->bufmgr_config.mbuf_high_water_jumbo =
12993 DEFAULT_MB_HIGH_WATER_JUMBO;
12994 }
1da177e4
LT		 12995
12996 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12997 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12998}
12999
13000static char * __devinit tg3_phy_string(struct tg3 *tp)
13001{
13002 switch (tp->phy_id & PHY_ID_MASK) {
13003 case PHY_ID_BCM5400: return "5400";
13004 case PHY_ID_BCM5401: return "5401";
13005 case PHY_ID_BCM5411: return "5411";
13006 case PHY_ID_BCM5701: return "5701";
13007 case PHY_ID_BCM5703: return "5703";
13008 case PHY_ID_BCM5704: return "5704";
13009 case PHY_ID_BCM5705: return "5705";
13010 case PHY_ID_BCM5750: return "5750";
85e94ced 13011 case PHY_ID_BCM5752: return "5752";
a4e2b347 13012 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13013 case PHY_ID_BCM5780: return "5780";
af36e6b6 13014 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13015 case PHY_ID_BCM5787: return "5787";
d30cdd28 13016 case PHY_ID_BCM5784: return "5784";
126a3368 13017 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13018 case PHY_ID_BCM5906: return "5906";
9936bcf6 13019 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13020 case PHY_ID_BCM8002: return "8002/serdes";
13021 case 0: return "serdes";
13022 default: return "unknown";
855e1111 13023 }
1da177e4
LT		 13024}
13025
f9804ddb
MC		 13026static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13027{
13028 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13029 strcpy(str, "PCI Express");
13030 return str;
13031 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13032 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13033
13034 strcpy(str, "PCIX:");
13035
13036 if ((clock_ctrl == 7) ||
13037 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13038 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13039 strcat(str, "133MHz");
13040 else if (clock_ctrl == 0)
13041 strcat(str, "33MHz");
13042 else if (clock_ctrl == 2)
13043 strcat(str, "50MHz");
13044 else if (clock_ctrl == 4)
13045 strcat(str, "66MHz");
13046 else if (clock_ctrl == 6)
13047 strcat(str, "100MHz");
f9804ddb
MC		 13048 } else {
13049 strcpy(str, "PCI:");
13050 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13051 strcat(str, "66MHz");
13052 else
13053 strcat(str, "33MHz");
13054 }
13055 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13056 strcat(str, ":32-bit");
13057 else
13058 strcat(str, ":64-bit");
13059 return str;
13060}
13061
8c2dc7e1 13062static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13063{
13064 struct pci_dev *peer;
13065 unsigned int func, devnr = tp->pdev->devfn & ~7;
13066
13067 for (func = 0; func < 8; func++) {
13068 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13069 if (peer && peer != tp->pdev)
13070 break;
13071 pci_dev_put(peer);
13072 }
16fe9d74
MC		 13073 /* 5704 can be configured in single-port mode, set peer to
13074 * tp->pdev in that case.
13075 */
13076 if (!peer) {
13077 peer = tp->pdev;
13078 return peer;
13079 }
1da177e4
LT		 13080
13081 /*
13082 * We don't need to keep the refcount elevated; there's no way
13083 * to remove one half of this device without removing the other
13084 */
13085 pci_dev_put(peer);
13086
13087 return peer;
13088}
13089
15f9850d
DM		 13090static void __devinit tg3_init_coal(struct tg3 *tp)
13091{
13092 struct ethtool_coalesce *ec = &tp->coal;
13093
13094 memset(ec, 0, sizeof(*ec));
13095 ec->cmd = ETHTOOL_GCOALESCE;
13096 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13097 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13098 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13099 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13100 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13101 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13102 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13103 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13104 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13105
13106 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13107 HOSTCC_MODE_CLRTICK_TXBD)) {
13108 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13109 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13110 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13111 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13112 }
d244c892
MC		 13113
13114 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13115 ec->rx_coalesce_usecs_irq = 0;
13116 ec->tx_coalesce_usecs_irq = 0;
13117 ec->stats_block_coalesce_usecs = 0;
13118 }
15f9850d
DM		 13119}
13120
7c7d64b8
SH		 13121static const struct net_device_ops tg3_netdev_ops = {
13122 .ndo_open = tg3_open,
13123 .ndo_stop = tg3_close,
00829823
SH		 13124 .ndo_start_xmit = tg3_start_xmit,
13125 .ndo_get_stats = tg3_get_stats,
13126 .ndo_validate_addr = eth_validate_addr,
13127 .ndo_set_multicast_list = tg3_set_rx_mode,
13128 .ndo_set_mac_address = tg3_set_mac_addr,
13129 .ndo_do_ioctl = tg3_ioctl,
13130 .ndo_tx_timeout = tg3_tx_timeout,
13131 .ndo_change_mtu = tg3_change_mtu,
13132#if TG3_VLAN_TAG_USED
13133 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13134#endif
13135#ifdef CONFIG_NET_POLL_CONTROLLER
13136 .ndo_poll_controller = tg3_poll_controller,
13137#endif
13138};
13139
13140static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13141 .ndo_open = tg3_open,
13142 .ndo_stop = tg3_close,
13143 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13144 .ndo_get_stats = tg3_get_stats,
13145 .ndo_validate_addr = eth_validate_addr,
13146 .ndo_set_multicast_list = tg3_set_rx_mode,
13147 .ndo_set_mac_address = tg3_set_mac_addr,
13148 .ndo_do_ioctl = tg3_ioctl,
13149 .ndo_tx_timeout = tg3_tx_timeout,
13150 .ndo_change_mtu = tg3_change_mtu,
13151#if TG3_VLAN_TAG_USED
13152 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13153#endif
13154#ifdef CONFIG_NET_POLL_CONTROLLER
13155 .ndo_poll_controller = tg3_poll_controller,
13156#endif
13157};
13158
1da177e4
LT		 13159static int __devinit tg3_init_one(struct pci_dev *pdev,
13160 const struct pci_device_id *ent)
13161{
13162 static int tg3_version_printed = 0;
1da177e4
LT		 13163 struct net_device *dev;
13164 struct tg3 *tp;
d6645372 13165 int err, pm_cap;
f9804ddb 13166 char str[40];
72f2afb8 13167 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13168
13169 if (tg3_version_printed++ == 0)
13170 printk(KERN_INFO "%s", version);
13171
13172 err = pci_enable_device(pdev);
13173 if (err) {
13174 printk(KERN_ERR PFX "Cannot enable PCI device, "
13175 "aborting.\n");
13176 return err;
13177 }
13178
1da177e4
LT		 13179 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13180 if (err) {
13181 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13182 "aborting.\n");
13183 goto err_out_disable_pdev;
13184 }
13185
13186 pci_set_master(pdev);
13187
13188 /* Find power-management capability. */
13189 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13190 if (pm_cap == 0) {
13191 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13192 "aborting.\n");
13193 err = -EIO;
13194 goto err_out_free_res;
13195 }
13196
1da177e4
LT		 13197 dev = alloc_etherdev(sizeof(*tp));
13198 if (!dev) {
13199 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13200 err = -ENOMEM;
13201 goto err_out_free_res;
13202 }
13203
1da177e4
LT		 13204 SET_NETDEV_DEV(dev, &pdev->dev);
13205
1da177e4
LT		 13206#if TG3_VLAN_TAG_USED
13207 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13208#endif
13209
13210 tp = netdev_priv(dev);
13211 tp->pdev = pdev;
13212 tp->dev = dev;
13213 tp->pm_cap = pm_cap;
1da177e4
LT		 13214 tp->rx_mode = TG3_DEF_RX_MODE;
13215 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13216
1da177e4
LT		 13217 if (tg3_debug > 0)
13218 tp->msg_enable = tg3_debug;
13219 else
13220 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13221
13222 /* The word/byte swap controls here control register access byte
13223 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13224 * setting below.
13225 */
13226 tp->misc_host_ctrl =
13227 MISC_HOST_CTRL_MASK_PCI_INT |
13228 MISC_HOST_CTRL_WORD_SWAP |
13229 MISC_HOST_CTRL_INDIR_ACCESS |
13230 MISC_HOST_CTRL_PCISTATE_RW;
13231
13232 /* The NONFRM (non-frame) byte/word swap controls take effect
13233 * on descriptor entries, anything which isn't packet data.
13234 *
13235 * The StrongARM chips on the board (one for tx, one for rx)
13236 * are running in big-endian mode.
13237 */
13238 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13239 GRC_MODE_WSWAP_NONFRM_DATA);
13240#ifdef __BIG_ENDIAN
13241 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13242#endif
13243 spin_lock_init(&tp->lock);
1da177e4 13244 spin_lock_init(&tp->indirect_lock);
c4028958 13245 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13246
d5fe488a 13247 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13248 if (!tp->regs) {
1da177e4
LT		 13249 printk(KERN_ERR PFX "Cannot map device registers, "
13250 "aborting.\n");
13251 err = -ENOMEM;
13252 goto err_out_free_dev;
13253 }
13254
13255 tg3_init_link_config(tp);
13256
1da177e4
LT		 13257 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13258 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13259 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13260
bea3348e 13261 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13262 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13263 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13264 dev->irq = pdev->irq;
1da177e4
LT		 13265
13266 err = tg3_get_invariants(tp);
13267 if (err) {
13268 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13269 "aborting.\n");
13270 goto err_out_iounmap;
13271 }
13272
321d32a0 13273 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13274 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13275 dev->netdev_ops = &tg3_netdev_ops;
13276 else
13277 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13278
13279
4a29cc2e
MC		 13280 /* The EPB bridge inside 5714, 5715, and 5780 and any
13281 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13282 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13283 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13284 * do DMA address check in tg3_start_xmit().
13285 */
4a29cc2e 13286 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13287 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13288 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13289 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13290#ifdef CONFIG_HIGHMEM
6a35528a 13291 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13292#endif
4a29cc2e 13293 } else
6a35528a 13294 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13295
13296 /* Configure DMA attributes. */
284901a9 13297 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13298 err = pci_set_dma_mask(pdev, dma_mask);
13299 if (!err) {
13300 dev->features |= NETIF_F_HIGHDMA;
13301 err = pci_set_consistent_dma_mask(pdev,
13302 persist_dma_mask);
13303 if (err < 0) {
13304 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13305 "DMA for consistent allocations\n");
13306 goto err_out_iounmap;
13307 }
13308 }
13309 }
284901a9
YH		 13310 if (err || dma_mask == DMA_BIT_MASK(32)) {
13311 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13312 if (err) {
13313 printk(KERN_ERR PFX "No usable DMA configuration, "
13314 "aborting.\n");
13315 goto err_out_iounmap;
13316 }
13317 }
13318
fdfec172 13319 tg3_init_bufmgr_config(tp);
1da177e4 13320
077f849d 13321 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13322 tp->fw_needed = FIRMWARE_TG3;
077f849d 13323
1da177e4
LT		 13324 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13325 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13326 }
13327 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13328 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13329 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13330 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13331 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13332 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13333 } else {
7f62ad5d 13334 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13335 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13336 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13337 else
9e9fd12d 13338 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13339 }
1da177e4 13340
4e3a7aaa
MC		 13341 /* TSO is on by default on chips that support hardware TSO.
13342 * Firmware TSO on older chips gives lower performance, so it
13343 * is off by default, but can be enabled using ethtool.
13344 */
b0026624 13345 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13346 if (dev->features & NETIF_F_IP_CSUM)
13347 dev->features |= NETIF_F_TSO;
13348 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13349 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13350 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13352 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13353 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13355 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13356 dev->features |= NETIF_F_TSO_ECN;
b0026624 13357 }
1da177e4 13358
1da177e4
LT		 13359
13360 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13361 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13362 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13363 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13364 tp->rx_pending = 63;
13365 }
13366
1da177e4
LT		 13367 err = tg3_get_device_address(tp);
13368 if (err) {
13369 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13370 "aborting.\n");
077f849d 13371 goto err_out_fw;
1da177e4
LT		 13372 }
13373
c88864df 13374 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13375 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13376 if (!tp->aperegs) {
c88864df
MC		 13377 printk(KERN_ERR PFX "Cannot map APE registers, "
13378 "aborting.\n");
13379 err = -ENOMEM;
077f849d 13380 goto err_out_fw;
c88864df
MC		 13381 }
13382
13383 tg3_ape_lock_init(tp);
7fd76445
MC		 13384
13385 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13386 tg3_read_dash_ver(tp);
c88864df
MC		 13387 }
13388
1da177e4
LT		 13389 /*
13390 * Reset chip in case UNDI or EFI driver did not shutdown
13391 * DMA self test will enable WDMAC and we'll see (spurious)
13392 * pending DMA on the PCI bus at that point.
13393 */
13394 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13395 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13396 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13397 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13398 }
13399
13400 err = tg3_test_dma(tp);
13401 if (err) {
13402 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13403 goto err_out_apeunmap;
1da177e4
LT		 13404 }
13405
1da177e4
LT		 13406 /* flow control autonegotiation is default behavior */
13407 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13408 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13409
15f9850d
DM		 13410 tg3_init_coal(tp);
13411
c49a1561
MC		 13412 pci_set_drvdata(pdev, dev);
13413
1da177e4
LT		 13414 err = register_netdev(dev);
13415 if (err) {
13416 printk(KERN_ERR PFX "Cannot register net device, "
13417 "aborting.\n");
0d3031d9 13418 goto err_out_apeunmap;
1da177e4
LT		 13419 }
13420
df59c940 13421 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13422 dev->name,
13423 tp->board_part_number,
13424 tp->pci_chip_rev_id,
f9804ddb 13425 tg3_bus_string(tp, str),
e174961c 13426 dev->dev_addr);
1da177e4 13427
df59c940
MC		 13428 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13429 printk(KERN_INFO
13430 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13431 tp->dev->name,
13432 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13433 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13434 else
13435 printk(KERN_INFO
13436 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13437 tp->dev->name, tg3_phy_string(tp),
13438 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13439 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13440 "10/100/1000Base-T")),
13441 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13442
13443 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13444 dev->name,
13445 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13446 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13447 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13448 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13449 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13450 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13451 dev->name, tp->dma_rwctrl,
284901a9 13452 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13453 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13454
13455 return 0;
13456
0d3031d9
MC		 13457err_out_apeunmap:
13458 if (tp->aperegs) {
13459 iounmap(tp->aperegs);
13460 tp->aperegs = NULL;
13461 }
13462
077f849d
JSR		 13463err_out_fw:
13464 if (tp->fw)
13465 release_firmware(tp->fw);
13466
1da177e4 13467err_out_iounmap:
6892914f
MC		 13468 if (tp->regs) {
13469 iounmap(tp->regs);
22abe310 13470 tp->regs = NULL;
6892914f 13471 }
1da177e4
LT		 13472
13473err_out_free_dev:
13474 free_netdev(dev);
13475
13476err_out_free_res:
13477 pci_release_regions(pdev);
13478
13479err_out_disable_pdev:
13480 pci_disable_device(pdev);
13481 pci_set_drvdata(pdev, NULL);
13482 return err;
13483}
13484
13485static void __devexit tg3_remove_one(struct pci_dev *pdev)
13486{
13487 struct net_device *dev = pci_get_drvdata(pdev);
13488
13489 if (dev) {
13490 struct tg3 *tp = netdev_priv(dev);
13491
077f849d
JSR		 13492 if (tp->fw)
13493 release_firmware(tp->fw);
13494
7faa006f 13495 flush_scheduled_work();
158d7abd 13496
b02fd9e3
MC		 13497 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13498 tg3_phy_fini(tp);
158d7abd 13499 tg3_mdio_fini(tp);
b02fd9e3 13500 }
158d7abd 13501
1da177e4 13502 unregister_netdev(dev);
0d3031d9
MC		 13503 if (tp->aperegs) {
13504 iounmap(tp->aperegs);
13505 tp->aperegs = NULL;
13506 }
6892914f
MC		 13507 if (tp->regs) {
13508 iounmap(tp->regs);
22abe310 13509 tp->regs = NULL;
6892914f 13510 }
1da177e4
LT		 13511 free_netdev(dev);
13512 pci_release_regions(pdev);
13513 pci_disable_device(pdev);
13514 pci_set_drvdata(pdev, NULL);
13515 }
13516}
13517
13518static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13519{
13520 struct net_device *dev = pci_get_drvdata(pdev);
13521 struct tg3 *tp = netdev_priv(dev);
12dac075 13522 pci_power_t target_state;
1da177e4
LT		 13523 int err;
13524
3e0c95fd
MC		 13525 /* PCI register 4 needs to be saved whether netif_running() or not.
13526 * MSI address and data need to be saved if using MSI and
13527 * netif_running().
13528 */
13529 pci_save_state(pdev);
13530
1da177e4
LT		 13531 if (!netif_running(dev))
13532 return 0;
13533
7faa006f 13534 flush_scheduled_work();
b02fd9e3 13535 tg3_phy_stop(tp);
1da177e4
LT		 13536 tg3_netif_stop(tp);
13537
13538 del_timer_sync(&tp->timer);
13539
f47c11ee 13540 tg3_full_lock(tp, 1);
1da177e4 13541 tg3_disable_ints(tp);
f47c11ee 13542 tg3_full_unlock(tp);
1da177e4
LT		 13543
13544 netif_device_detach(dev);
13545
f47c11ee 13546 tg3_full_lock(tp, 0);
944d980e 13547 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13548 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13549 tg3_full_unlock(tp);
1da177e4 13550
12dac075
RW		 13551 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13552
13553 err = tg3_set_power_state(tp, target_state);
1da177e4 13554 if (err) {
b02fd9e3
MC		 13555 int err2;
13556
f47c11ee 13557 tg3_full_lock(tp, 0);
1da177e4 13558
6a9eba15 13559 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13560 err2 = tg3_restart_hw(tp, 1);
13561 if (err2)
b9ec6c1b 13562 goto out;
1da177e4
LT		 13563
13564 tp->timer.expires = jiffies + tp->timer_offset;
13565 add_timer(&tp->timer);
13566
13567 netif_device_attach(dev);
13568 tg3_netif_start(tp);
13569
b9ec6c1b 13570out:
f47c11ee 13571 tg3_full_unlock(tp);
b02fd9e3
MC		 13572
13573 if (!err2)
13574 tg3_phy_start(tp);
1da177e4
LT		 13575 }
13576
13577 return err;
13578}
13579
13580static int tg3_resume(struct pci_dev *pdev)
13581{
13582 struct net_device *dev = pci_get_drvdata(pdev);
13583 struct tg3 *tp = netdev_priv(dev);
13584 int err;
13585
3e0c95fd
MC		 13586 pci_restore_state(tp->pdev);
13587
1da177e4
LT		 13588 if (!netif_running(dev))
13589 return 0;
13590
bc1c7567 13591 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13592 if (err)
13593 return err;
13594
13595 netif_device_attach(dev);
13596
f47c11ee 13597 tg3_full_lock(tp, 0);
1da177e4 13598
6a9eba15 13599 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13600 err = tg3_restart_hw(tp, 1);
13601 if (err)
13602 goto out;
1da177e4
LT		 13603
13604 tp->timer.expires = jiffies + tp->timer_offset;
13605 add_timer(&tp->timer);
13606
1da177e4
LT		 13607 tg3_netif_start(tp);
13608
b9ec6c1b 13609out:
f47c11ee 13610 tg3_full_unlock(tp);
1da177e4 13611
b02fd9e3
MC		 13612 if (!err)
13613 tg3_phy_start(tp);
13614
b9ec6c1b 13615 return err;
1da177e4
LT		 13616}
13617
13618static struct pci_driver tg3_driver = {
13619 .name = DRV_MODULE_NAME,
13620 .id_table = tg3_pci_tbl,
13621 .probe = tg3_init_one,
13622 .remove = __devexit_p(tg3_remove_one),
13623 .suspend = tg3_suspend,
13624 .resume = tg3_resume
13625};
13626
13627static int __init tg3_init(void)
13628{
29917620 13629 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13630}
13631
13632static void __exit tg3_cleanup(void)
13633{
13634 pci_unregister_driver(&tg3_driver);
13635}
13636
13637module_init(tg3_init);
13638module_exit(tg3_cleanup);
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