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tg3: Clarify rx buffer relationships
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
f656f398
MC		 71#define DRV_MODULE_VERSION "3.100"
72#define DRV_MODULE_RELDATE "August 25, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
287be12e
MC		 128#define TG3_DMA_BYTE_ENAB 64
129
130#define TG3_RX_STD_DMA_SZ 1536
131#define TG3_RX_JMB_DMA_SZ 9046
132
133#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
134
135#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 137
138/* minimum number of free TX descriptors required to wake up TX process */
42952231 139#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
1da177e4 140
ad829268
MC		 141#define TG3_RAW_IP_ALIGN 2
142
1da177e4
LT		 143/* number of ETHTOOL_GSTATS u64's */
144#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
145
4cafd3f5
MC		 146#define TG3_NUM_TEST 6
147
077f849d
JSR		 148#define FIRMWARE_TG3 "tigon/tg3.bin"
149#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
151
1da177e4
LT		 152static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
154
155MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157MODULE_LICENSE("GPL");
158MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 159MODULE_FIRMWARE(FIRMWARE_TG3);
160MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
162
1da177e4
LT		 163
164static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165module_param(tg3_debug, int, 0);
166MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
167
168static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
242 {}
1da177e4
LT		 243};
244
245MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
50da859d 247static const struct {
1da177e4
LT		 248 const char string[ETH_GSTRING_LEN];
249} ethtool_stats_keys[TG3_NUM_STATS] = {
250 { "rx_octets" },
251 { "rx_fragments" },
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
255 { "rx_fcs_errors" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
262 { "rx_jabbers" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
276
277 { "tx_octets" },
278 { "tx_collisions" },
279
280 { "tx_xon_sent" },
281 { "tx_xoff_sent" },
282 { "tx_flow_control" },
283 { "tx_mac_errors" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
286 { "tx_deferred" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
307 { "tx_discards" },
308 { "tx_errors" },
309
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
312 { "rxbds_empty" },
313 { "rx_discards" },
314 { "rx_errors" },
315 { "rx_threshold_hit" },
316
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
320
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
323 { "nic_irqs" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
326};
327
50da859d 328static const struct {
4cafd3f5
MC		 329 const char string[ETH_GSTRING_LEN];
330} ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
337};
338
b401e9e2
MC		 339static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
340{
341 writel(val, tp->regs + off);
342}
343
344static u32 tg3_read32(struct tg3 *tp, u32 off)
345{
6aa20a22 346 return (readl(tp->regs + off));
b401e9e2
MC		 347}
348
0d3031d9
MC		 349static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
350{
351 writel(val, tp->aperegs + off);
352}
353
354static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
355{
356 return (readl(tp->aperegs + off));
357}
358
1da177e4
LT		 359static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
360{
6892914f
MC		 361 unsigned long flags;
362
363 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 364 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
365 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 366 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 367}
368
369static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
370{
371 writel(val, tp->regs + off);
372 readl(tp->regs + off);
1da177e4
LT		 373}
374
6892914f 375static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 376{
6892914f
MC		 377 unsigned long flags;
378 u32 val;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
384 return val;
385}
386
387static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
388{
389 unsigned long flags;
390
391 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
393 TG3_64BIT_REG_LOW, val);
394 return;
395 }
396 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
398 TG3_64BIT_REG_LOW, val);
399 return;
1da177e4 400 }
6892914f
MC		 401
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
409 */
410 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
411 (val == 0x1)) {
412 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
413 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
414 }
415}
416
417static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
418{
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427}
428
b401e9e2
MC		 429/* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
433 */
434static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 435{
b401e9e2
MC		 436 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
437 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
438 /* Non-posted methods */
439 tp->write32(tp, off, val);
440 else {
441 /* Posted method */
442 tg3_write32(tp, off, val);
443 if (usec_wait)
444 udelay(usec_wait);
445 tp->read32(tp, off);
446 }
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
449 */
450 if (usec_wait)
451 udelay(usec_wait);
1da177e4
LT		 452}
453
09ee929c
MC		 454static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
455{
456 tp->write32_mbox(tp, off, val);
6892914f
MC		 457 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
458 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
459 tp->read32_mbox(tp, off);
09ee929c
MC		 460}
461
20094930 462static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 463{
464 void __iomem *mbox = tp->regs + off;
465 writel(val, mbox);
466 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
467 writel(val, mbox);
468 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
469 readl(mbox);
470}
471
b5d3772c
MC		 472static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
473{
474 return (readl(tp->regs + off + GRCMBOX_BASE));
475}
476
477static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
478{
479 writel(val, tp->regs + off + GRCMBOX_BASE);
480}
481
20094930 482#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 483#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 484#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 486#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 487
488#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 489#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 491#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 492
493static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
494{
6892914f
MC		 495 unsigned long flags;
496
b5d3772c
MC		 497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
498 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
499 return;
500
6892914f 501 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 505
bbadf503
MC		 506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508 } else {
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 511
bbadf503
MC		 512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514 }
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 516}
517
1da177e4
LT		 518static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
519{
6892914f
MC		 520 unsigned long flags;
521
b5d3772c
MC		 522 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
523 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
524 *val = 0;
525 return;
526 }
527
6892914f 528 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 529 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
530 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
531 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 532
bbadf503
MC		 533 /* Always leave this as zero. */
534 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
535 } else {
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
537 *val = tr32(TG3PCI_MEM_WIN_DATA);
538
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
541 }
6892914f 542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 543}
544
0d3031d9
MC		 545static void tg3_ape_lock_init(struct tg3 *tp)
546{
547 int i;
548
549 /* Make sure the driver hasn't any stale locks. */
550 for (i = 0; i < 8; i++)
551 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
552 APE_LOCK_GRANT_DRIVER);
553}
554
555static int tg3_ape_lock(struct tg3 *tp, int locknum)
556{
557 int i, off;
558 int ret = 0;
559 u32 status;
560
561 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
562 return 0;
563
564 switch (locknum) {
77b483f1 565 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 566 case TG3_APE_LOCK_MEM:
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 off = 4 * locknum;
573
574 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
575
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i = 0; i < 100; i++) {
578 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
579 if (status == APE_LOCK_GRANT_DRIVER)
580 break;
581 udelay(10);
582 }
583
584 if (status != APE_LOCK_GRANT_DRIVER) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
587 APE_LOCK_GRANT_DRIVER);
588
589 ret = -EBUSY;
590 }
591
592 return ret;
593}
594
595static void tg3_ape_unlock(struct tg3 *tp, int locknum)
596{
597 int off;
598
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
600 return;
601
602 switch (locknum) {
77b483f1 603 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 604 case TG3_APE_LOCK_MEM:
605 break;
606 default:
607 return;
608 }
609
610 off = 4 * locknum;
611 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
612}
613
1da177e4
LT		 614static void tg3_disable_ints(struct tg3 *tp)
615{
616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 618 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 619}
620
621static inline void tg3_cond_int(struct tg3 *tp)
622{
38f3843e
MC		 623 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
624 (tp->hw_status->status & SD_STATUS_UPDATED))
1da177e4 625 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
b5d3772c
MC		 626 else
627 tw32(HOSTCC_MODE, tp->coalesce_mode |
628 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 629}
630
631static void tg3_enable_ints(struct tg3 *tp)
632{
bbe832c0
MC		 633 tp->irq_sync = 0;
634 wmb();
635
1da177e4
LT		 636 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 638 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
639 (tp->last_tag << 24));
fcfa0a32
MC		 640 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
641 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
642 (tp->last_tag << 24));
1da177e4
LT		 643 tg3_cond_int(tp);
644}
645
04237ddd
MC		 646static inline unsigned int tg3_has_work(struct tg3 *tp)
647{
648 struct tg3_hw_status *sblk = tp->hw_status;
649 unsigned int work_exists = 0;
650
651 /* check for phy events */
652 if (!(tp->tg3_flags &
653 (TG3_FLAG_USE_LINKCHG_REG |
654 TG3_FLAG_POLL_SERDES))) {
655 if (sblk->status & SD_STATUS_LINK_CHG)
656 work_exists = 1;
657 }
658 /* check for RX/TX work to do */
659 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
660 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
661 work_exists = 1;
662
663 return work_exists;
664}
665
1da177e4 666/* tg3_restart_ints
04237ddd
MC		 667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
6aa20a22 669 * which reenables interrupts
1da177e4
LT		 670 */
671static void tg3_restart_ints(struct tg3 *tp)
672{
fac9b83e
DM		 673 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
674 tp->last_tag << 24);
1da177e4
LT		 675 mmiowb();
676
fac9b83e
DM		 677 /* When doing tagged status, this work check is unnecessary.
678 * The last_tag we write above tells the chip which piece of
679 * work we've completed.
680 */
681 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
682 tg3_has_work(tp))
04237ddd
MC		 683 tw32(HOSTCC_MODE, tp->coalesce_mode |
684 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 685}
686
687static inline void tg3_netif_stop(struct tg3 *tp)
688{
bbe832c0 689 tp->dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 690 napi_disable(&tp->napi);
1da177e4
LT		 691 netif_tx_disable(tp->dev);
692}
693
694static inline void tg3_netif_start(struct tg3 *tp)
695{
696 netif_wake_queue(tp->dev);
697 /* NOTE: unconditional netif_wake_queue is only appropriate
698 * so long as all callers are assured to have free tx slots
699 * (such as after tg3_init_hw)
700 */
bea3348e 701 napi_enable(&tp->napi);
f47c11ee
DM		 702 tp->hw_status->status |= SD_STATUS_UPDATED;
703 tg3_enable_ints(tp);
1da177e4
LT		 704}
705
706static void tg3_switch_clocks(struct tg3 *tp)
707{
708 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
709 u32 orig_clock_ctrl;
710
795d01c5
MC		 711 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
712 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 713 return;
714
1da177e4
LT		 715 orig_clock_ctrl = clock_ctrl;
716 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
717 CLOCK_CTRL_CLKRUN_OENABLE |
718 0x1f);
719 tp->pci_clock_ctrl = clock_ctrl;
720
721 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
722 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 725 }
726 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 727 tw32_wait_f(TG3PCI_CLOCK_CTRL,
728 clock_ctrl |
729 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
730 40);
731 tw32_wait_f(TG3PCI_CLOCK_CTRL,
732 clock_ctrl | (CLOCK_CTRL_ALTCLK),
733 40);
1da177e4 734 }
b401e9e2 735 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 736}
737
738#define PHY_BUSY_LOOPS 5000
739
740static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
741{
742 u32 frame_val;
743 unsigned int loops;
744 int ret;
745
746 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
747 tw32_f(MAC_MI_MODE,
748 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
749 udelay(80);
750 }
751
752 *val = 0x0;
753
754 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
755 MI_COM_PHY_ADDR_MASK);
756 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
757 MI_COM_REG_ADDR_MASK);
758 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 759
1da177e4
LT		 760 tw32_f(MAC_MI_COM, frame_val);
761
762 loops = PHY_BUSY_LOOPS;
763 while (loops != 0) {
764 udelay(10);
765 frame_val = tr32(MAC_MI_COM);
766
767 if ((frame_val & MI_COM_BUSY) == 0) {
768 udelay(5);
769 frame_val = tr32(MAC_MI_COM);
770 break;
771 }
772 loops -= 1;
773 }
774
775 ret = -EBUSY;
776 if (loops != 0) {
777 *val = frame_val & MI_COM_DATA_MASK;
778 ret = 0;
779 }
780
781 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
782 tw32_f(MAC_MI_MODE, tp->mi_mode);
783 udelay(80);
784 }
785
786 return ret;
787}
788
789static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
790{
791 u32 frame_val;
792 unsigned int loops;
793 int ret;
794
7f97a4bd 795 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 796 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
797 return 0;
798
1da177e4
LT		 799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE,
801 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802 udelay(80);
803 }
804
805 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
806 MI_COM_PHY_ADDR_MASK);
807 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
808 MI_COM_REG_ADDR_MASK);
809 frame_val |= (val & MI_COM_DATA_MASK);
810 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 811
1da177e4
LT		 812 tw32_f(MAC_MI_COM, frame_val);
813
814 loops = PHY_BUSY_LOOPS;
815 while (loops != 0) {
816 udelay(10);
817 frame_val = tr32(MAC_MI_COM);
818 if ((frame_val & MI_COM_BUSY) == 0) {
819 udelay(5);
820 frame_val = tr32(MAC_MI_COM);
821 break;
822 }
823 loops -= 1;
824 }
825
826 ret = -EBUSY;
827 if (loops != 0)
828 ret = 0;
829
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE, tp->mi_mode);
832 udelay(80);
833 }
834
835 return ret;
836}
837
95e2869a
MC		 838static int tg3_bmcr_reset(struct tg3 *tp)
839{
840 u32 phy_control;
841 int limit, err;
842
843 /* OK, reset it, and poll the BMCR_RESET bit until it
844 * clears or we time out.
845 */
846 phy_control = BMCR_RESET;
847 err = tg3_writephy(tp, MII_BMCR, phy_control);
848 if (err != 0)
849 return -EBUSY;
850
851 limit = 5000;
852 while (limit--) {
853 err = tg3_readphy(tp, MII_BMCR, &phy_control);
854 if (err != 0)
855 return -EBUSY;
856
857 if ((phy_control & BMCR_RESET) == 0) {
858 udelay(40);
859 break;
860 }
861 udelay(10);
862 }
d4675b52 863 if (limit < 0)
95e2869a
MC		 864 return -EBUSY;
865
866 return 0;
867}
868
158d7abd
MC		 869static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
870{
3d16543d 871 struct tg3 *tp = bp->priv;
158d7abd
MC		 872 u32 val;
873
874 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
875 return -EAGAIN;
876
877 if (tg3_readphy(tp, reg, &val))
878 return -EIO;
879
880 return val;
881}
882
883static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
884{
3d16543d 885 struct tg3 *tp = bp->priv;
158d7abd
MC		 886
887 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
888 return -EAGAIN;
889
890 if (tg3_writephy(tp, reg, val))
891 return -EIO;
892
893 return 0;
894}
895
896static int tg3_mdio_reset(struct mii_bus *bp)
897{
898 return 0;
899}
900
9c61d6bc 901static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 902{
903 u32 val;
fcb389df 904 struct phy_device *phydev;
a9daf367 905
fcb389df
MC		 906 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
907 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
908 case TG3_PHY_ID_BCM50610:
909 val = MAC_PHYCFG2_50610_LED_MODES;
910 break;
911 case TG3_PHY_ID_BCMAC131:
912 val = MAC_PHYCFG2_AC131_LED_MODES;
913 break;
914 case TG3_PHY_ID_RTL8211C:
915 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
916 break;
917 case TG3_PHY_ID_RTL8201E:
918 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
919 break;
920 default:
a9daf367 921 return;
fcb389df
MC		 922 }
923
924 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
925 tw32(MAC_PHYCFG2, val);
926
927 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 928 val &= ~(MAC_PHYCFG1_RGMII_INT |
929 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
930 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 931 tw32(MAC_PHYCFG1, val);
932
933 return;
934 }
935
936 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
937 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
938 MAC_PHYCFG2_FMODE_MASK_MASK |
939 MAC_PHYCFG2_GMODE_MASK_MASK |
940 MAC_PHYCFG2_ACT_MASK_MASK |
941 MAC_PHYCFG2_QUAL_MASK_MASK |
942 MAC_PHYCFG2_INBAND_ENABLE;
943
944 tw32(MAC_PHYCFG2, val);
a9daf367 945
bb85fbb6
MC		 946 val = tr32(MAC_PHYCFG1);
947 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
948 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
949 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 950 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
951 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
952 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
953 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
954 }
bb85fbb6
MC		 955 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
956 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
957 tw32(MAC_PHYCFG1, val);
a9daf367 958
a9daf367
MC		 959 val = tr32(MAC_EXT_RGMII_MODE);
960 val &= ~(MAC_RGMII_MODE_RX_INT_B |
961 MAC_RGMII_MODE_RX_QUALITY |
962 MAC_RGMII_MODE_RX_ACTIVITY |
963 MAC_RGMII_MODE_RX_ENG_DET |
964 MAC_RGMII_MODE_TX_ENABLE |
965 MAC_RGMII_MODE_TX_LOWPWR |
966 MAC_RGMII_MODE_TX_RESET);
fcb389df 967 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 968 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
969 val |= MAC_RGMII_MODE_RX_INT_B |
970 MAC_RGMII_MODE_RX_QUALITY |
971 MAC_RGMII_MODE_RX_ACTIVITY |
972 MAC_RGMII_MODE_RX_ENG_DET;
973 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
974 val |= MAC_RGMII_MODE_TX_ENABLE |
975 MAC_RGMII_MODE_TX_LOWPWR |
976 MAC_RGMII_MODE_TX_RESET;
977 }
978 tw32(MAC_EXT_RGMII_MODE, val);
979}
980
158d7abd
MC		 981static void tg3_mdio_start(struct tg3 *tp)
982{
983 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 984 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 985 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 986 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 987 }
988
989 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
990 tw32_f(MAC_MI_MODE, tp->mi_mode);
991 udelay(80);
a9daf367 992
9c61d6bc
MC		 993 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
995 tg3_mdio_config_5785(tp);
158d7abd
MC		 996}
997
998static void tg3_mdio_stop(struct tg3 *tp)
999{
1000 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 1001 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 1002 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 1003 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 1004 }
1005}
1006
1007static int tg3_mdio_init(struct tg3 *tp)
1008{
1009 int i;
1010 u32 reg;
a9daf367 1011 struct phy_device *phydev;
158d7abd
MC		 1012
1013 tg3_mdio_start(tp);
1014
1015 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1016 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1017 return 0;
1018
298cf9be
LB		 1019 tp->mdio_bus = mdiobus_alloc();
1020 if (tp->mdio_bus == NULL)
1021 return -ENOMEM;
158d7abd 1022
298cf9be
LB		 1023 tp->mdio_bus->name = "tg3 mdio bus";
1024 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1025 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1026 tp->mdio_bus->priv = tp;
1027 tp->mdio_bus->parent = &tp->pdev->dev;
1028 tp->mdio_bus->read = &tg3_mdio_read;
1029 tp->mdio_bus->write = &tg3_mdio_write;
1030 tp->mdio_bus->reset = &tg3_mdio_reset;
1031 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1032 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1033
1034 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1035 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1036
1037 /* The bus registration will look for all the PHYs on the mdio bus.
1038 * Unfortunately, it does not ensure the PHY is powered up before
1039 * accessing the PHY ID registers. A chip reset is the
1040 * quickest way to bring the device back to an operational state..
1041 */
1042 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1043 tg3_bmcr_reset(tp);
1044
298cf9be 1045 i = mdiobus_register(tp->mdio_bus);
a9daf367 1046 if (i) {
158d7abd
MC		 1047 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1048 tp->dev->name, i);
9c61d6bc 1049 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1050 return i;
1051 }
158d7abd 1052
298cf9be 1053 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1054
9c61d6bc
MC		 1055 if (!phydev || !phydev->drv) {
1056 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1057 mdiobus_unregister(tp->mdio_bus);
1058 mdiobus_free(tp->mdio_bus);
1059 return -ENODEV;
1060 }
1061
1062 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1063 case TG3_PHY_ID_BCM57780:
1064 phydev->interface = PHY_INTERFACE_MODE_GMII;
1065 break;
a9daf367 1066 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1067 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1068 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1069 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1070 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1071 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1072 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1073 /* fallthru */
1074 case TG3_PHY_ID_RTL8211C:
1075 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1076 break;
fcb389df 1077 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1078 case TG3_PHY_ID_BCMAC131:
1079 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1080 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1081 break;
1082 }
1083
9c61d6bc
MC		 1084 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1085
1086 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1087 tg3_mdio_config_5785(tp);
a9daf367
MC		 1088
1089 return 0;
158d7abd
MC		 1090}
1091
1092static void tg3_mdio_fini(struct tg3 *tp)
1093{
1094 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1095 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1096 mdiobus_unregister(tp->mdio_bus);
1097 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1098 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1099 }
1100}
1101
4ba526ce
MC		 1102/* tp->lock is held. */
1103static inline void tg3_generate_fw_event(struct tg3 *tp)
1104{
1105 u32 val;
1106
1107 val = tr32(GRC_RX_CPU_EVENT);
1108 val |= GRC_RX_CPU_DRIVER_EVENT;
1109 tw32_f(GRC_RX_CPU_EVENT, val);
1110
1111 tp->last_event_jiffies = jiffies;
1112}
1113
1114#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1115
95e2869a
MC		 1116/* tp->lock is held. */
1117static void tg3_wait_for_event_ack(struct tg3 *tp)
1118{
1119 int i;
4ba526ce
MC		 1120 unsigned int delay_cnt;
1121 long time_remain;
1122
1123 /* If enough time has passed, no wait is necessary. */
1124 time_remain = (long)(tp->last_event_jiffies + 1 +
1125 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1126 (long)jiffies;
1127 if (time_remain < 0)
1128 return;
1129
1130 /* Check if we can shorten the wait time. */
1131 delay_cnt = jiffies_to_usecs(time_remain);
1132 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1133 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1134 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1135
4ba526ce 1136 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1137 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1138 break;
4ba526ce 1139 udelay(8);
95e2869a
MC		 1140 }
1141}
1142
1143/* tp->lock is held. */
1144static void tg3_ump_link_report(struct tg3 *tp)
1145{
1146 u32 reg;
1147 u32 val;
1148
1149 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1150 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1151 return;
1152
1153 tg3_wait_for_event_ack(tp);
1154
1155 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1156
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1158
1159 val = 0;
1160 if (!tg3_readphy(tp, MII_BMCR, &reg))
1161 val = reg << 16;
1162 if (!tg3_readphy(tp, MII_BMSR, &reg))
1163 val |= (reg & 0xffff);
1164 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1165
1166 val = 0;
1167 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1168 val = reg << 16;
1169 if (!tg3_readphy(tp, MII_LPA, &reg))
1170 val |= (reg & 0xffff);
1171 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1172
1173 val = 0;
1174 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1175 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1176 val = reg << 16;
1177 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1178 val |= (reg & 0xffff);
1179 }
1180 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1181
1182 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1183 val = reg << 16;
1184 else
1185 val = 0;
1186 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1187
4ba526ce 1188 tg3_generate_fw_event(tp);
95e2869a
MC		 1189}
1190
1191static void tg3_link_report(struct tg3 *tp)
1192{
1193 if (!netif_carrier_ok(tp->dev)) {
1194 if (netif_msg_link(tp))
1195 printk(KERN_INFO PFX "%s: Link is down.\n",
1196 tp->dev->name);
1197 tg3_ump_link_report(tp);
1198 } else if (netif_msg_link(tp)) {
1199 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1200 tp->dev->name,
1201 (tp->link_config.active_speed == SPEED_1000 ?
1202 1000 :
1203 (tp->link_config.active_speed == SPEED_100 ?
1204 100 : 10)),
1205 (tp->link_config.active_duplex == DUPLEX_FULL ?
1206 "full" : "half"));
1207
1208 printk(KERN_INFO PFX
1209 "%s: Flow control is %s for TX and %s for RX.\n",
1210 tp->dev->name,
e18ce346 1211 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1212 "on" : "off",
e18ce346 1213 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1214 "on" : "off");
1215 tg3_ump_link_report(tp);
1216 }
1217}
1218
1219static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1220{
1221 u16 miireg;
1222
e18ce346 1223 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1224 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1225 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1226 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1228 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1229 else
1230 miireg = 0;
1231
1232 return miireg;
1233}
1234
1235static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1236{
1237 u16 miireg;
1238
e18ce346 1239 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1240 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1241 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1242 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1243 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1244 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1245 else
1246 miireg = 0;
1247
1248 return miireg;
1249}
1250
95e2869a
MC		 1251static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1252{
1253 u8 cap = 0;
1254
1255 if (lcladv & ADVERTISE_1000XPAUSE) {
1256 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1257 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1258 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1259 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1260 cap = FLOW_CTRL_RX;
95e2869a
MC		 1261 } else {
1262 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1263 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1264 }
1265 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1266 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1267 cap = FLOW_CTRL_TX;
95e2869a
MC		 1268 }
1269
1270 return cap;
1271}
1272
f51f3562 1273static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1274{
b02fd9e3 1275 u8 autoneg;
f51f3562 1276 u8 flowctrl = 0;
95e2869a
MC		 1277 u32 old_rx_mode = tp->rx_mode;
1278 u32 old_tx_mode = tp->tx_mode;
1279
b02fd9e3 1280 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1281 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1282 else
1283 autoneg = tp->link_config.autoneg;
1284
1285 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1286 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1287 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1288 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1289 else
bc02ff95 1290 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1291 } else
1292 flowctrl = tp->link_config.flowctrl;
95e2869a 1293
f51f3562 1294 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1295
e18ce346 1296 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1297 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1298 else
1299 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1300
f51f3562 1301 if (old_rx_mode != tp->rx_mode)
95e2869a 1302 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1303
e18ce346 1304 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1305 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1306 else
1307 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1308
f51f3562 1309 if (old_tx_mode != tp->tx_mode)
95e2869a 1310 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1311}
1312
b02fd9e3
MC		 1313static void tg3_adjust_link(struct net_device *dev)
1314{
1315 u8 oldflowctrl, linkmesg = 0;
1316 u32 mac_mode, lcl_adv, rmt_adv;
1317 struct tg3 *tp = netdev_priv(dev);
298cf9be 1318 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1319
1320 spin_lock(&tp->lock);
1321
1322 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1323 MAC_MODE_HALF_DUPLEX);
1324
1325 oldflowctrl = tp->link_config.active_flowctrl;
1326
1327 if (phydev->link) {
1328 lcl_adv = 0;
1329 rmt_adv = 0;
1330
1331 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1332 mac_mode |= MAC_MODE_PORT_MODE_MII;
1333 else
1334 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1335
1336 if (phydev->duplex == DUPLEX_HALF)
1337 mac_mode |= MAC_MODE_HALF_DUPLEX;
1338 else {
1339 lcl_adv = tg3_advert_flowctrl_1000T(
1340 tp->link_config.flowctrl);
1341
1342 if (phydev->pause)
1343 rmt_adv = LPA_PAUSE_CAP;
1344 if (phydev->asym_pause)
1345 rmt_adv |= LPA_PAUSE_ASYM;
1346 }
1347
1348 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1349 } else
1350 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1351
1352 if (mac_mode != tp->mac_mode) {
1353 tp->mac_mode = mac_mode;
1354 tw32_f(MAC_MODE, tp->mac_mode);
1355 udelay(40);
1356 }
1357
fcb389df
MC		 1358 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1359 if (phydev->speed == SPEED_10)
1360 tw32(MAC_MI_STAT,
1361 MAC_MI_STAT_10MBPS_MODE |
1362 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1363 else
1364 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1365 }
1366
b02fd9e3
MC		 1367 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1368 tw32(MAC_TX_LENGTHS,
1369 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1370 (6 << TX_LENGTHS_IPG_SHIFT) |
1371 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1372 else
1373 tw32(MAC_TX_LENGTHS,
1374 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1375 (6 << TX_LENGTHS_IPG_SHIFT) |
1376 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1377
1378 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1379 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1380 phydev->speed != tp->link_config.active_speed ||
1381 phydev->duplex != tp->link_config.active_duplex ||
1382 oldflowctrl != tp->link_config.active_flowctrl)
1383 linkmesg = 1;
1384
1385 tp->link_config.active_speed = phydev->speed;
1386 tp->link_config.active_duplex = phydev->duplex;
1387
1388 spin_unlock(&tp->lock);
1389
1390 if (linkmesg)
1391 tg3_link_report(tp);
1392}
1393
1394static int tg3_phy_init(struct tg3 *tp)
1395{
1396 struct phy_device *phydev;
1397
1398 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1399 return 0;
1400
1401 /* Bring the PHY back to a known state. */
1402 tg3_bmcr_reset(tp);
1403
298cf9be 1404 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1405
1406 /* Attach the MAC to the PHY. */
fb28ad35 1407 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1408 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1409 if (IS_ERR(phydev)) {
1410 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1411 return PTR_ERR(phydev);
1412 }
1413
b02fd9e3 1414 /* Mask with MAC supported features. */
9c61d6bc
MC		 1415 switch (phydev->interface) {
1416 case PHY_INTERFACE_MODE_GMII:
1417 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1418 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1419 phydev->supported &= (PHY_GBIT_FEATURES |
1420 SUPPORTED_Pause |
1421 SUPPORTED_Asym_Pause);
1422 break;
1423 }
1424 /* fallthru */
9c61d6bc
MC		 1425 case PHY_INTERFACE_MODE_MII:
1426 phydev->supported &= (PHY_BASIC_FEATURES |
1427 SUPPORTED_Pause |
1428 SUPPORTED_Asym_Pause);
1429 break;
1430 default:
1431 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1432 return -EINVAL;
1433 }
1434
1435 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1436
1437 phydev->advertising = phydev->supported;
1438
b02fd9e3
MC		 1439 return 0;
1440}
1441
1442static void tg3_phy_start(struct tg3 *tp)
1443{
1444 struct phy_device *phydev;
1445
1446 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1447 return;
1448
298cf9be 1449 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1450
1451 if (tp->link_config.phy_is_low_power) {
1452 tp->link_config.phy_is_low_power = 0;
1453 phydev->speed = tp->link_config.orig_speed;
1454 phydev->duplex = tp->link_config.orig_duplex;
1455 phydev->autoneg = tp->link_config.orig_autoneg;
1456 phydev->advertising = tp->link_config.orig_advertising;
1457 }
1458
1459 phy_start(phydev);
1460
1461 phy_start_aneg(phydev);
1462}
1463
1464static void tg3_phy_stop(struct tg3 *tp)
1465{
1466 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1467 return;
1468
298cf9be 1469 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1470}
1471
1472static void tg3_phy_fini(struct tg3 *tp)
1473{
1474 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1475 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1476 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1477 }
1478}
1479
b2a5c19c
MC		 1480static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1481{
1482 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1483 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1484}
1485
7f97a4bd
MC		 1486static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1487{
1488 u32 phytest;
1489
1490 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1491 u32 phy;
1492
1493 tg3_writephy(tp, MII_TG3_FET_TEST,
1494 phytest | MII_TG3_FET_SHADOW_EN);
1495 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1496 if (enable)
1497 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1498 else
1499 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1500 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1501 }
1502 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1503 }
1504}
1505
6833c043
MC		 1506static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1507{
1508 u32 reg;
1509
7f97a4bd 1510 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1511 return;
1512
7f97a4bd
MC		 1513 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1514 tg3_phy_fet_toggle_apd(tp, enable);
1515 return;
1516 }
1517
6833c043
MC		 1518 reg = MII_TG3_MISC_SHDW_WREN |
1519 MII_TG3_MISC_SHDW_SCR5_SEL |
1520 MII_TG3_MISC_SHDW_SCR5_LPED |
1521 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1522 MII_TG3_MISC_SHDW_SCR5_SDTL |
1523 MII_TG3_MISC_SHDW_SCR5_C125OE;
1524 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1525 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1526
1527 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1528
1529
1530 reg = MII_TG3_MISC_SHDW_WREN |
1531 MII_TG3_MISC_SHDW_APD_SEL |
1532 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1533 if (enable)
1534 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1535
1536 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1537}
1538
9ef8ca99
MC		 1539static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1540{
1541 u32 phy;
1542
1543 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1544 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1545 return;
1546
7f97a4bd 1547 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1548 u32 ephy;
1549
535ef6e1
MC		 1550 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1551 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1552
1553 tg3_writephy(tp, MII_TG3_FET_TEST,
1554 ephy | MII_TG3_FET_SHADOW_EN);
1555 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1556 if (enable)
535ef6e1 1557 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1558 else
535ef6e1
MC		 1559 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1560 tg3_writephy(tp, reg, phy);
9ef8ca99 1561 }
535ef6e1 1562 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1563 }
1564 } else {
1565 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1566 MII_TG3_AUXCTL_SHDWSEL_MISC;
1567 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1568 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1569 if (enable)
1570 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1571 else
1572 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1573 phy |= MII_TG3_AUXCTL_MISC_WREN;
1574 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1575 }
1576 }
1577}
1578
1da177e4
LT		 1579static void tg3_phy_set_wirespeed(struct tg3 *tp)
1580{
1581 u32 val;
1582
1583 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1584 return;
1585
1586 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1587 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1588 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1589 (val | (1 << 15) | (1 << 4)));
1590}
1591
b2a5c19c
MC		 1592static void tg3_phy_apply_otp(struct tg3 *tp)
1593{
1594 u32 otp, phy;
1595
1596 if (!tp->phy_otp)
1597 return;
1598
1599 otp = tp->phy_otp;
1600
1601 /* Enable SM_DSP clock and tx 6dB coding. */
1602 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1603 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1604 MII_TG3_AUXCTL_ACTL_TX_6DB;
1605 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1606
1607 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1608 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1609 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1610
1611 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1612 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1613 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1614
1615 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1616 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1617 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1618
1619 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1620 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1621
1622 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1623 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1624
1625 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1626 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1627 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1628
1629 /* Turn off SM_DSP clock. */
1630 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1631 MII_TG3_AUXCTL_ACTL_TX_6DB;
1632 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1633}
1634
1da177e4
LT		 1635static int tg3_wait_macro_done(struct tg3 *tp)
1636{
1637 int limit = 100;
1638
1639 while (limit--) {
1640 u32 tmp32;
1641
1642 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1643 if ((tmp32 & 0x1000) == 0)
1644 break;
1645 }
1646 }
d4675b52 1647 if (limit < 0)
1da177e4
LT		 1648 return -EBUSY;
1649
1650 return 0;
1651}
1652
1653static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1654{
1655 static const u32 test_pat[4][6] = {
1656 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1657 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1658 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1659 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1660 };
1661 int chan;
1662
1663 for (chan = 0; chan < 4; chan++) {
1664 int i;
1665
1666 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1667 (chan * 0x2000) | 0x0200);
1668 tg3_writephy(tp, 0x16, 0x0002);
1669
1670 for (i = 0; i < 6; i++)
1671 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1672 test_pat[chan][i]);
1673
1674 tg3_writephy(tp, 0x16, 0x0202);
1675 if (tg3_wait_macro_done(tp)) {
1676 *resetp = 1;
1677 return -EBUSY;
1678 }
1679
1680 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1681 (chan * 0x2000) | 0x0200);
1682 tg3_writephy(tp, 0x16, 0x0082);
1683 if (tg3_wait_macro_done(tp)) {
1684 *resetp = 1;
1685 return -EBUSY;
1686 }
1687
1688 tg3_writephy(tp, 0x16, 0x0802);
1689 if (tg3_wait_macro_done(tp)) {
1690 *resetp = 1;
1691 return -EBUSY;
1692 }
1693
1694 for (i = 0; i < 6; i += 2) {
1695 u32 low, high;
1696
1697 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1698 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1699 tg3_wait_macro_done(tp)) {
1700 *resetp = 1;
1701 return -EBUSY;
1702 }
1703 low &= 0x7fff;
1704 high &= 0x000f;
1705 if (low != test_pat[chan][i] ||
1706 high != test_pat[chan][i+1]) {
1707 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1708 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1709 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1710
1711 return -EBUSY;
1712 }
1713 }
1714 }
1715
1716 return 0;
1717}
1718
1719static int tg3_phy_reset_chanpat(struct tg3 *tp)
1720{
1721 int chan;
1722
1723 for (chan = 0; chan < 4; chan++) {
1724 int i;
1725
1726 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1727 (chan * 0x2000) | 0x0200);
1728 tg3_writephy(tp, 0x16, 0x0002);
1729 for (i = 0; i < 6; i++)
1730 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1731 tg3_writephy(tp, 0x16, 0x0202);
1732 if (tg3_wait_macro_done(tp))
1733 return -EBUSY;
1734 }
1735
1736 return 0;
1737}
1738
1739static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1740{
1741 u32 reg32, phy9_orig;
1742 int retries, do_phy_reset, err;
1743
1744 retries = 10;
1745 do_phy_reset = 1;
1746 do {
1747 if (do_phy_reset) {
1748 err = tg3_bmcr_reset(tp);
1749 if (err)
1750 return err;
1751 do_phy_reset = 0;
1752 }
1753
1754 /* Disable transmitter and interrupt. */
1755 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1756 continue;
1757
1758 reg32 |= 0x3000;
1759 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1760
1761 /* Set full-duplex, 1000 mbps. */
1762 tg3_writephy(tp, MII_BMCR,
1763 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1764
1765 /* Set to master mode. */
1766 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1767 continue;
1768
1769 tg3_writephy(tp, MII_TG3_CTRL,
1770 (MII_TG3_CTRL_AS_MASTER |
1771 MII_TG3_CTRL_ENABLE_AS_MASTER));
1772
1773 /* Enable SM_DSP_CLOCK and 6dB. */
1774 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1775
1776 /* Block the PHY control access. */
1777 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1778 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1779
1780 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1781 if (!err)
1782 break;
1783 } while (--retries);
1784
1785 err = tg3_phy_reset_chanpat(tp);
1786 if (err)
1787 return err;
1788
1789 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1790 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1791
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1793 tg3_writephy(tp, 0x16, 0x0000);
1794
1795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1797 /* Set Extended packet length bit for jumbo frames */
1798 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1799 }
1800 else {
1801 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1802 }
1803
1804 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1805
1806 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1807 reg32 &= ~0x3000;
1808 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1809 } else if (!err)
1810 err = -EBUSY;
1811
1812 return err;
1813}
1814
1815/* This will reset the tigon3 PHY if there is no valid
1816 * link unless the FORCE argument is non-zero.
1817 */
1818static int tg3_phy_reset(struct tg3 *tp)
1819{
b2a5c19c 1820 u32 cpmuctrl;
1da177e4
LT		 1821 u32 phy_status;
1822 int err;
1823
60189ddf
MC		 1824 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1825 u32 val;
1826
1827 val = tr32(GRC_MISC_CFG);
1828 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1829 udelay(40);
1830 }
1da177e4
LT		 1831 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1832 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1833 if (err != 0)
1834 return -EBUSY;
1835
c8e1e82b
MC		 1836 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1837 netif_carrier_off(tp->dev);
1838 tg3_link_report(tp);
1839 }
1840
1da177e4
LT		 1841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1843 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1844 err = tg3_phy_reset_5703_4_5(tp);
1845 if (err)
1846 return err;
1847 goto out;
1848 }
1849
b2a5c19c
MC		 1850 cpmuctrl = 0;
1851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1852 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1853 cpmuctrl = tr32(TG3_CPMU_CTRL);
1854 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1855 tw32(TG3_CPMU_CTRL,
1856 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1857 }
1858
1da177e4
LT		 1859 err = tg3_bmcr_reset(tp);
1860 if (err)
1861 return err;
1862
b2a5c19c
MC		 1863 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1864 u32 phy;
1865
1866 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1867 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1868
1869 tw32(TG3_CPMU_CTRL, cpmuctrl);
1870 }
1871
bcb37f6c
MC		 1872 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1873 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1874 u32 val;
1875
1876 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1877 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1878 CPMU_LSPD_1000MB_MACCLK_12_5) {
1879 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1880 udelay(40);
1881 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1882 }
1883 }
1884
b2a5c19c
MC		 1885 tg3_phy_apply_otp(tp);
1886
6833c043
MC		 1887 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1888 tg3_phy_toggle_apd(tp, true);
1889 else
1890 tg3_phy_toggle_apd(tp, false);
1891
1da177e4
LT		 1892out:
1893 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1894 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1895 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1896 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1898 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1899 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1900 }
1901 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1902 tg3_writephy(tp, 0x1c, 0x8d68);
1903 tg3_writephy(tp, 0x1c, 0x8d68);
1904 }
1905 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1906 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1907 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1908 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1910 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1911 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1913 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1914 }
c424cb24
MC		 1915 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1916 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1917 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1918 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1919 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1920 tg3_writephy(tp, MII_TG3_TEST1,
1921 MII_TG3_TEST1_TRIM_EN | 0x4);
1922 } else
1923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1924 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1925 }
1da177e4
LT		 1926 /* Set Extended packet length bit (bit 14) on all chips that */
1927 /* support jumbo frames */
1928 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1929 /* Cannot do read-modify-write on 5401 */
1930 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1931 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1932 u32 phy_reg;
1933
1934 /* Set bit 14 with read-modify-write to preserve other bits */
1935 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1936 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1937 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1938 }
1939
1940 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1941 * jumbo frames transmission.
1942 */
8f666b07 1943 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1944 u32 phy_reg;
1945
1946 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1947 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1948 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1949 }
1950
715116a1 1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1952 /* adjust output voltage */
535ef6e1 1953 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1954 }
1955
9ef8ca99 1956 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1957 tg3_phy_set_wirespeed(tp);
1958 return 0;
1959}
1960
1961static void tg3_frob_aux_power(struct tg3 *tp)
1962{
1963 struct tg3 *tp_peer = tp;
1964
9d26e213 1965 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1966 return;
1967
8c2dc7e1
MC		 1968 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1969 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1970 struct net_device *dev_peer;
1971
1972 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1973 /* remove_one() may have been run on the peer. */
8c2dc7e1 1974 if (!dev_peer)
bc1c7567
MC		 1975 tp_peer = tp;
1976 else
1977 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1978 }
1979
1da177e4 1980 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1981 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1982 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1983 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1986 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1987 (GRC_LCLCTRL_GPIO_OE0 |
1988 GRC_LCLCTRL_GPIO_OE1 |
1989 GRC_LCLCTRL_GPIO_OE2 |
1990 GRC_LCLCTRL_GPIO_OUTPUT0 |
1991 GRC_LCLCTRL_GPIO_OUTPUT1),
1992 100);
8d519ab2
MC		 1993 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1994 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 1995 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1996 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1997 GRC_LCLCTRL_GPIO_OE1 |
1998 GRC_LCLCTRL_GPIO_OE2 |
1999 GRC_LCLCTRL_GPIO_OUTPUT0 |
2000 GRC_LCLCTRL_GPIO_OUTPUT1 |
2001 tp->grc_local_ctrl;
2002 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2003
2004 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2005 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2006
2007 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2008 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2009 } else {
2010 u32 no_gpio2;
dc56b7d4 2011 u32 grc_local_ctrl = 0;
1da177e4
LT		 2012
2013 if (tp_peer != tp &&
2014 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2015 return;
2016
dc56b7d4
MC		 2017 /* Workaround to prevent overdrawing Amps. */
2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2019 ASIC_REV_5714) {
2020 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2021 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2022 grc_local_ctrl, 100);
dc56b7d4
MC		 2023 }
2024
1da177e4
LT		 2025 /* On 5753 and variants, GPIO2 cannot be used. */
2026 no_gpio2 = tp->nic_sram_data_cfg &
2027 NIC_SRAM_DATA_CFG_NO_GPIO2;
2028
dc56b7d4 2029 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2030 GRC_LCLCTRL_GPIO_OE1 |
2031 GRC_LCLCTRL_GPIO_OE2 |
2032 GRC_LCLCTRL_GPIO_OUTPUT1 |
2033 GRC_LCLCTRL_GPIO_OUTPUT2;
2034 if (no_gpio2) {
2035 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2036 GRC_LCLCTRL_GPIO_OUTPUT2);
2037 }
b401e9e2
MC		 2038 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2039 grc_local_ctrl, 100);
1da177e4
LT		 2040
2041 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2042
b401e9e2
MC		 2043 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2044 grc_local_ctrl, 100);
1da177e4
LT		 2045
2046 if (!no_gpio2) {
2047 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2048 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2049 grc_local_ctrl, 100);
1da177e4
LT		 2050 }
2051 }
2052 } else {
2053 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2054 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2055 if (tp_peer != tp &&
2056 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2057 return;
2058
b401e9e2
MC		 2059 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060 (GRC_LCLCTRL_GPIO_OE1 |
2061 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2062
b401e9e2
MC		 2063 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2064 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2065
b401e9e2
MC		 2066 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067 (GRC_LCLCTRL_GPIO_OE1 |
2068 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2069 }
2070 }
2071}
2072
e8f3f6ca
MC		 2073static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2074{
2075 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2076 return 1;
2077 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2078 if (speed != SPEED_10)
2079 return 1;
2080 } else if (speed == SPEED_10)
2081 return 1;
2082
2083 return 0;
2084}
2085
1da177e4
LT		 2086static int tg3_setup_phy(struct tg3 *, int);
2087
2088#define RESET_KIND_SHUTDOWN 0
2089#define RESET_KIND_INIT 1
2090#define RESET_KIND_SUSPEND 2
2091
2092static void tg3_write_sig_post_reset(struct tg3 *, int);
2093static int tg3_halt_cpu(struct tg3 *, u32);
2094
0a459aac 2095static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2096{
ce057f01
MC		 2097 u32 val;
2098
5129724a
MC		 2099 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2101 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2102 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2103
2104 sg_dig_ctrl |=
2105 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2106 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2107 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2108 }
3f7045c1 2109 return;
5129724a 2110 }
3f7045c1 2111
60189ddf 2112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2113 tg3_bmcr_reset(tp);
2114 val = tr32(GRC_MISC_CFG);
2115 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2116 udelay(40);
2117 return;
0a459aac 2118 } else if (do_low_power) {
715116a1
MC		 2119 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2120 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2121
2122 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2123 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2124 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2125 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2126 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2127 }
3f7045c1 2128
15c3b696
MC		 2129 /* The PHY should not be powered down on some chips because
2130 * of bugs.
2131 */
2132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2134 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2135 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2136 return;
ce057f01 2137
bcb37f6c
MC		 2138 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2139 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2140 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2141 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2142 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2143 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2144 }
2145
15c3b696
MC		 2146 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2147}
2148
ffbcfed4
MC		 2149/* tp->lock is held. */
2150static int tg3_nvram_lock(struct tg3 *tp)
2151{
2152 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2153 int i;
2154
2155 if (tp->nvram_lock_cnt == 0) {
2156 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2157 for (i = 0; i < 8000; i++) {
2158 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2159 break;
2160 udelay(20);
2161 }
2162 if (i == 8000) {
2163 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2164 return -ENODEV;
2165 }
2166 }
2167 tp->nvram_lock_cnt++;
2168 }
2169 return 0;
2170}
2171
2172/* tp->lock is held. */
2173static void tg3_nvram_unlock(struct tg3 *tp)
2174{
2175 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2176 if (tp->nvram_lock_cnt > 0)
2177 tp->nvram_lock_cnt--;
2178 if (tp->nvram_lock_cnt == 0)
2179 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2180 }
2181}
2182
2183/* tp->lock is held. */
2184static void tg3_enable_nvram_access(struct tg3 *tp)
2185{
2186 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2187 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2188 u32 nvaccess = tr32(NVRAM_ACCESS);
2189
2190 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2191 }
2192}
2193
2194/* tp->lock is held. */
2195static void tg3_disable_nvram_access(struct tg3 *tp)
2196{
2197 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2198 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2199 u32 nvaccess = tr32(NVRAM_ACCESS);
2200
2201 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2202 }
2203}
2204
2205static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2206 u32 offset, u32 *val)
2207{
2208 u32 tmp;
2209 int i;
2210
2211 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2212 return -EINVAL;
2213
2214 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2215 EEPROM_ADDR_DEVID_MASK |
2216 EEPROM_ADDR_READ);
2217 tw32(GRC_EEPROM_ADDR,
2218 tmp |
2219 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2220 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2221 EEPROM_ADDR_ADDR_MASK) |
2222 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2223
2224 for (i = 0; i < 1000; i++) {
2225 tmp = tr32(GRC_EEPROM_ADDR);
2226
2227 if (tmp & EEPROM_ADDR_COMPLETE)
2228 break;
2229 msleep(1);
2230 }
2231 if (!(tmp & EEPROM_ADDR_COMPLETE))
2232 return -EBUSY;
2233
62cedd11
MC		 2234 tmp = tr32(GRC_EEPROM_DATA);
2235
2236 /*
2237 * The data will always be opposite the native endian
2238 * format. Perform a blind byteswap to compensate.
2239 */
2240 *val = swab32(tmp);
2241
ffbcfed4
MC		 2242 return 0;
2243}
2244
2245#define NVRAM_CMD_TIMEOUT 10000
2246
2247static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2248{
2249 int i;
2250
2251 tw32(NVRAM_CMD, nvram_cmd);
2252 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2253 udelay(10);
2254 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2255 udelay(10);
2256 break;
2257 }
2258 }
2259
2260 if (i == NVRAM_CMD_TIMEOUT)
2261 return -EBUSY;
2262
2263 return 0;
2264}
2265
2266static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2267{
2268 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2269 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2270 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2271 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2272 (tp->nvram_jedecnum == JEDEC_ATMEL))
2273
2274 addr = ((addr / tp->nvram_pagesize) <<
2275 ATMEL_AT45DB0X1B_PAGE_POS) +
2276 (addr % tp->nvram_pagesize);
2277
2278 return addr;
2279}
2280
2281static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2282{
2283 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2284 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2285 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2286 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2287 (tp->nvram_jedecnum == JEDEC_ATMEL))
2288
2289 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2290 tp->nvram_pagesize) +
2291 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2292
2293 return addr;
2294}
2295
e4f34110
MC		 2296/* NOTE: Data read in from NVRAM is byteswapped according to
2297 * the byteswapping settings for all other register accesses.
2298 * tg3 devices are BE devices, so on a BE machine, the data
2299 * returned will be exactly as it is seen in NVRAM. On a LE
2300 * machine, the 32-bit value will be byteswapped.
2301 */
ffbcfed4
MC		 2302static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2303{
2304 int ret;
2305
2306 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2307 return tg3_nvram_read_using_eeprom(tp, offset, val);
2308
2309 offset = tg3_nvram_phys_addr(tp, offset);
2310
2311 if (offset > NVRAM_ADDR_MSK)
2312 return -EINVAL;
2313
2314 ret = tg3_nvram_lock(tp);
2315 if (ret)
2316 return ret;
2317
2318 tg3_enable_nvram_access(tp);
2319
2320 tw32(NVRAM_ADDR, offset);
2321 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2322 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2323
2324 if (ret == 0)
e4f34110 2325 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2326
2327 tg3_disable_nvram_access(tp);
2328
2329 tg3_nvram_unlock(tp);
2330
2331 return ret;
2332}
2333
a9dc529d
MC		 2334/* Ensures NVRAM data is in bytestream format. */
2335static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2336{
2337 u32 v;
a9dc529d 2338 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2339 if (!res)
a9dc529d 2340 *val = cpu_to_be32(v);
ffbcfed4
MC		 2341 return res;
2342}
2343
3f007891
MC		 2344/* tp->lock is held. */
2345static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2346{
2347 u32 addr_high, addr_low;
2348 int i;
2349
2350 addr_high = ((tp->dev->dev_addr[0] << 8) |
2351 tp->dev->dev_addr[1]);
2352 addr_low = ((tp->dev->dev_addr[2] << 24) |
2353 (tp->dev->dev_addr[3] << 16) |
2354 (tp->dev->dev_addr[4] << 8) |
2355 (tp->dev->dev_addr[5] << 0));
2356 for (i = 0; i < 4; i++) {
2357 if (i == 1 && skip_mac_1)
2358 continue;
2359 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2360 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2361 }
2362
2363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2365 for (i = 0; i < 12; i++) {
2366 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2367 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2368 }
2369 }
2370
2371 addr_high = (tp->dev->dev_addr[0] +
2372 tp->dev->dev_addr[1] +
2373 tp->dev->dev_addr[2] +
2374 tp->dev->dev_addr[3] +
2375 tp->dev->dev_addr[4] +
2376 tp->dev->dev_addr[5]) &
2377 TX_BACKOFF_SEED_MASK;
2378 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2379}
2380
bc1c7567 2381static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2382{
2383 u32 misc_host_ctrl;
0a459aac 2384 bool device_should_wake, do_low_power;
1da177e4
LT		 2385
2386 /* Make sure register accesses (indirect or otherwise)
2387 * will function correctly.
2388 */
2389 pci_write_config_dword(tp->pdev,
2390 TG3PCI_MISC_HOST_CTRL,
2391 tp->misc_host_ctrl);
2392
1da177e4 2393 switch (state) {
bc1c7567 2394 case PCI_D0:
12dac075
RW		 2395 pci_enable_wake(tp->pdev, state, false);
2396 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2397
9d26e213
MC		 2398 /* Switch out of Vaux if it is a NIC */
2399 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2400 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2401
2402 return 0;
2403
bc1c7567 2404 case PCI_D1:
bc1c7567 2405 case PCI_D2:
bc1c7567 2406 case PCI_D3hot:
1da177e4
LT		 2407 break;
2408
2409 default:
12dac075
RW		 2410 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2411 tp->dev->name, state);
1da177e4 2412 return -EINVAL;
855e1111 2413 }
5e7dfd0f
MC		 2414
2415 /* Restore the CLKREQ setting. */
2416 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2417 u16 lnkctl;
2418
2419 pci_read_config_word(tp->pdev,
2420 tp->pcie_cap + PCI_EXP_LNKCTL,
2421 &lnkctl);
2422 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2423 pci_write_config_word(tp->pdev,
2424 tp->pcie_cap + PCI_EXP_LNKCTL,
2425 lnkctl);
2426 }
2427
1da177e4
LT		 2428 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2429 tw32(TG3PCI_MISC_HOST_CTRL,
2430 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2431
05ac4cb7
MC		 2432 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2433 device_may_wakeup(&tp->pdev->dev) &&
2434 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2435
dd477003 2436 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2437 do_low_power = false;
b02fd9e3
MC		 2438 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2439 !tp->link_config.phy_is_low_power) {
2440 struct phy_device *phydev;
0a459aac 2441 u32 phyid, advertising;
b02fd9e3 2442
298cf9be 2443 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2444
2445 tp->link_config.phy_is_low_power = 1;
2446
2447 tp->link_config.orig_speed = phydev->speed;
2448 tp->link_config.orig_duplex = phydev->duplex;
2449 tp->link_config.orig_autoneg = phydev->autoneg;
2450 tp->link_config.orig_advertising = phydev->advertising;
2451
2452 advertising = ADVERTISED_TP |
2453 ADVERTISED_Pause |
2454 ADVERTISED_Autoneg |
2455 ADVERTISED_10baseT_Half;
2456
2457 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2458 device_should_wake) {
b02fd9e3
MC		 2459 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2460 advertising |=
2461 ADVERTISED_100baseT_Half |
2462 ADVERTISED_100baseT_Full |
2463 ADVERTISED_10baseT_Full;
2464 else
2465 advertising |= ADVERTISED_10baseT_Full;
2466 }
2467
2468 phydev->advertising = advertising;
2469
2470 phy_start_aneg(phydev);
0a459aac
MC		 2471
2472 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2473 if (phyid != TG3_PHY_ID_BCMAC131) {
2474 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2475 if (phyid == TG3_PHY_OUI_1 ||
2476 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2477 phyid == TG3_PHY_OUI_3)
2478 do_low_power = true;
2479 }
b02fd9e3 2480 }
dd477003 2481 } else {
2023276e 2482 do_low_power = true;
0a459aac 2483
dd477003
MC		 2484 if (tp->link_config.phy_is_low_power == 0) {
2485 tp->link_config.phy_is_low_power = 1;
2486 tp->link_config.orig_speed = tp->link_config.speed;
2487 tp->link_config.orig_duplex = tp->link_config.duplex;
2488 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2489 }
1da177e4 2490
dd477003
MC		 2491 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2492 tp->link_config.speed = SPEED_10;
2493 tp->link_config.duplex = DUPLEX_HALF;
2494 tp->link_config.autoneg = AUTONEG_ENABLE;
2495 tg3_setup_phy(tp, 0);
2496 }
1da177e4
LT		 2497 }
2498
b5d3772c
MC		 2499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2500 u32 val;
2501
2502 val = tr32(GRC_VCPU_EXT_CTRL);
2503 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2504 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2505 int i;
2506 u32 val;
2507
2508 for (i = 0; i < 200; i++) {
2509 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2510 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2511 break;
2512 msleep(1);
2513 }
2514 }
a85feb8c
GZ		 2515 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2516 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2517 WOL_DRV_STATE_SHUTDOWN |
2518 WOL_DRV_WOL |
2519 WOL_SET_MAGIC_PKT);
6921d201 2520
05ac4cb7 2521 if (device_should_wake) {
1da177e4
LT		 2522 u32 mac_mode;
2523
2524 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2525 if (do_low_power) {
dd477003
MC		 2526 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2527 udelay(40);
2528 }
1da177e4 2529
3f7045c1
MC		 2530 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2531 mac_mode = MAC_MODE_PORT_MODE_GMII;
2532 else
2533 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2534
e8f3f6ca
MC		 2535 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2536 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2537 ASIC_REV_5700) {
2538 u32 speed = (tp->tg3_flags &
2539 TG3_FLAG_WOL_SPEED_100MB) ?
2540 SPEED_100 : SPEED_10;
2541 if (tg3_5700_link_polarity(tp, speed))
2542 mac_mode |= MAC_MODE_LINK_POLARITY;
2543 else
2544 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2545 }
1da177e4
LT		 2546 } else {
2547 mac_mode = MAC_MODE_PORT_MODE_TBI;
2548 }
2549
cbf46853 2550 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2551 tw32(MAC_LED_CTRL, tp->led_ctrl);
2552
05ac4cb7
MC		 2553 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2554 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2555 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2556 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2557 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2558 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2559
3bda1258
MC		 2560 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2561 mac_mode |= tp->mac_mode &
2562 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2563 if (mac_mode & MAC_MODE_APE_TX_EN)
2564 mac_mode |= MAC_MODE_TDE_ENABLE;
2565 }
2566
1da177e4
LT		 2567 tw32_f(MAC_MODE, mac_mode);
2568 udelay(100);
2569
2570 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2571 udelay(10);
2572 }
2573
2574 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2575 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2577 u32 base_val;
2578
2579 base_val = tp->pci_clock_ctrl;
2580 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2581 CLOCK_CTRL_TXCLK_DISABLE);
2582
b401e9e2
MC		 2583 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2584 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2585 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2586 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2587 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2588 /* do nothing */
85e94ced 2589 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2590 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2591 u32 newbits1, newbits2;
2592
2593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2594 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2595 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2596 CLOCK_CTRL_TXCLK_DISABLE |
2597 CLOCK_CTRL_ALTCLK);
2598 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2599 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2600 newbits1 = CLOCK_CTRL_625_CORE;
2601 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2602 } else {
2603 newbits1 = CLOCK_CTRL_ALTCLK;
2604 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2605 }
2606
b401e9e2
MC		 2607 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2608 40);
1da177e4 2609
b401e9e2
MC		 2610 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2611 40);
1da177e4
LT		 2612
2613 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2614 u32 newbits3;
2615
2616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2618 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2619 CLOCK_CTRL_TXCLK_DISABLE |
2620 CLOCK_CTRL_44MHZ_CORE);
2621 } else {
2622 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2623 }
2624
b401e9e2
MC		 2625 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2626 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2627 }
2628 }
2629
05ac4cb7 2630 if (!(device_should_wake) &&
22435849 2631 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2632 tg3_power_down_phy(tp, do_low_power);
6921d201 2633
1da177e4
LT		 2634 tg3_frob_aux_power(tp);
2635
2636 /* Workaround for unstable PLL clock */
2637 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2638 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2639 u32 val = tr32(0x7d00);
2640
2641 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2642 tw32(0x7d00, val);
6921d201 2643 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2644 int err;
2645
2646 err = tg3_nvram_lock(tp);
1da177e4 2647 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2648 if (!err)
2649 tg3_nvram_unlock(tp);
6921d201 2650 }
1da177e4
LT		 2651 }
2652
bbadf503
MC		 2653 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2654
05ac4cb7 2655 if (device_should_wake)
12dac075
RW		 2656 pci_enable_wake(tp->pdev, state, true);
2657
1da177e4 2658 /* Finally, set the new power state. */
12dac075 2659 pci_set_power_state(tp->pdev, state);
1da177e4 2660
1da177e4
LT		 2661 return 0;
2662}
2663
1da177e4
LT		 2664static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2665{
2666 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2667 case MII_TG3_AUX_STAT_10HALF:
2668 *speed = SPEED_10;
2669 *duplex = DUPLEX_HALF;
2670 break;
2671
2672 case MII_TG3_AUX_STAT_10FULL:
2673 *speed = SPEED_10;
2674 *duplex = DUPLEX_FULL;
2675 break;
2676
2677 case MII_TG3_AUX_STAT_100HALF:
2678 *speed = SPEED_100;
2679 *duplex = DUPLEX_HALF;
2680 break;
2681
2682 case MII_TG3_AUX_STAT_100FULL:
2683 *speed = SPEED_100;
2684 *duplex = DUPLEX_FULL;
2685 break;
2686
2687 case MII_TG3_AUX_STAT_1000HALF:
2688 *speed = SPEED_1000;
2689 *duplex = DUPLEX_HALF;
2690 break;
2691
2692 case MII_TG3_AUX_STAT_1000FULL:
2693 *speed = SPEED_1000;
2694 *duplex = DUPLEX_FULL;
2695 break;
2696
2697 default:
7f97a4bd 2698 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2699 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2700 SPEED_10;
2701 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2702 DUPLEX_HALF;
2703 break;
2704 }
1da177e4
LT		 2705 *speed = SPEED_INVALID;
2706 *duplex = DUPLEX_INVALID;
2707 break;
855e1111 2708 }
1da177e4
LT		 2709}
2710
2711static void tg3_phy_copper_begin(struct tg3 *tp)
2712{
2713 u32 new_adv;
2714 int i;
2715
2716 if (tp->link_config.phy_is_low_power) {
2717 /* Entering low power mode. Disable gigabit and
2718 * 100baseT advertisements.
2719 */
2720 tg3_writephy(tp, MII_TG3_CTRL, 0);
2721
2722 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2723 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2724 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2725 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2726
2727 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2728 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2729 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2730 tp->link_config.advertising &=
2731 ~(ADVERTISED_1000baseT_Half |
2732 ADVERTISED_1000baseT_Full);
2733
ba4d07a8 2734 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2735 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2736 new_adv |= ADVERTISE_10HALF;
2737 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2738 new_adv |= ADVERTISE_10FULL;
2739 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2740 new_adv |= ADVERTISE_100HALF;
2741 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2742 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2743
2744 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2745
1da177e4
LT		 2746 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2747
2748 if (tp->link_config.advertising &
2749 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2750 new_adv = 0;
2751 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2752 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2753 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2754 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2755 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2756 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2757 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2758 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2759 MII_TG3_CTRL_ENABLE_AS_MASTER);
2760 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2761 } else {
2762 tg3_writephy(tp, MII_TG3_CTRL, 0);
2763 }
2764 } else {
ba4d07a8
MC		 2765 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2766 new_adv |= ADVERTISE_CSMA;
2767
1da177e4
LT		 2768 /* Asking for a specific link mode. */
2769 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2770 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2771
2772 if (tp->link_config.duplex == DUPLEX_FULL)
2773 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2774 else
2775 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2776 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2777 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2778 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2779 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2780 } else {
1da177e4
LT		 2781 if (tp->link_config.speed == SPEED_100) {
2782 if (tp->link_config.duplex == DUPLEX_FULL)
2783 new_adv |= ADVERTISE_100FULL;
2784 else
2785 new_adv |= ADVERTISE_100HALF;
2786 } else {
2787 if (tp->link_config.duplex == DUPLEX_FULL)
2788 new_adv |= ADVERTISE_10FULL;
2789 else
2790 new_adv |= ADVERTISE_10HALF;
2791 }
2792 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2793
2794 new_adv = 0;
1da177e4 2795 }
ba4d07a8
MC		 2796
2797 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2798 }
2799
2800 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2801 tp->link_config.speed != SPEED_INVALID) {
2802 u32 bmcr, orig_bmcr;
2803
2804 tp->link_config.active_speed = tp->link_config.speed;
2805 tp->link_config.active_duplex = tp->link_config.duplex;
2806
2807 bmcr = 0;
2808 switch (tp->link_config.speed) {
2809 default:
2810 case SPEED_10:
2811 break;
2812
2813 case SPEED_100:
2814 bmcr |= BMCR_SPEED100;
2815 break;
2816
2817 case SPEED_1000:
2818 bmcr |= TG3_BMCR_SPEED1000;
2819 break;
855e1111 2820 }
1da177e4
LT		 2821
2822 if (tp->link_config.duplex == DUPLEX_FULL)
2823 bmcr |= BMCR_FULLDPLX;
2824
2825 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2826 (bmcr != orig_bmcr)) {
2827 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2828 for (i = 0; i < 1500; i++) {
2829 u32 tmp;
2830
2831 udelay(10);
2832 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2833 tg3_readphy(tp, MII_BMSR, &tmp))
2834 continue;
2835 if (!(tmp & BMSR_LSTATUS)) {
2836 udelay(40);
2837 break;
2838 }
2839 }
2840 tg3_writephy(tp, MII_BMCR, bmcr);
2841 udelay(40);
2842 }
2843 } else {
2844 tg3_writephy(tp, MII_BMCR,
2845 BMCR_ANENABLE | BMCR_ANRESTART);
2846 }
2847}
2848
2849static int tg3_init_5401phy_dsp(struct tg3 *tp)
2850{
2851 int err;
2852
2853 /* Turn off tap power management. */
2854 /* Set Extended packet length bit */
2855 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2856
2857 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2858 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2859
2860 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2861 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2862
2863 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2864 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2865
2866 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2867 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2868
2869 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2870 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2871
2872 udelay(40);
2873
2874 return err;
2875}
2876
3600d918 2877static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2878{
3600d918
MC		 2879 u32 adv_reg, all_mask = 0;
2880
2881 if (mask & ADVERTISED_10baseT_Half)
2882 all_mask |= ADVERTISE_10HALF;
2883 if (mask & ADVERTISED_10baseT_Full)
2884 all_mask |= ADVERTISE_10FULL;
2885 if (mask & ADVERTISED_100baseT_Half)
2886 all_mask |= ADVERTISE_100HALF;
2887 if (mask & ADVERTISED_100baseT_Full)
2888 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2889
2890 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2891 return 0;
2892
1da177e4
LT		 2893 if ((adv_reg & all_mask) != all_mask)
2894 return 0;
2895 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2896 u32 tg3_ctrl;
2897
3600d918
MC		 2898 all_mask = 0;
2899 if (mask & ADVERTISED_1000baseT_Half)
2900 all_mask |= ADVERTISE_1000HALF;
2901 if (mask & ADVERTISED_1000baseT_Full)
2902 all_mask |= ADVERTISE_1000FULL;
2903
1da177e4
LT		 2904 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2905 return 0;
2906
1da177e4
LT		 2907 if ((tg3_ctrl & all_mask) != all_mask)
2908 return 0;
2909 }
2910 return 1;
2911}
2912
ef167e27
MC		 2913static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2914{
2915 u32 curadv, reqadv;
2916
2917 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2918 return 1;
2919
2920 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2921 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2922
2923 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2924 if (curadv != reqadv)
2925 return 0;
2926
2927 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2928 tg3_readphy(tp, MII_LPA, rmtadv);
2929 } else {
2930 /* Reprogram the advertisement register, even if it
2931 * does not affect the current link. If the link
2932 * gets renegotiated in the future, we can save an
2933 * additional renegotiation cycle by advertising
2934 * it correctly in the first place.
2935 */
2936 if (curadv != reqadv) {
2937 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2938 ADVERTISE_PAUSE_ASYM);
2939 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2940 }
2941 }
2942
2943 return 1;
2944}
2945
1da177e4
LT		 2946static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2947{
2948 int current_link_up;
2949 u32 bmsr, dummy;
ef167e27 2950 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2951 u16 current_speed;
2952 u8 current_duplex;
2953 int i, err;
2954
2955 tw32(MAC_EVENT, 0);
2956
2957 tw32_f(MAC_STATUS,
2958 (MAC_STATUS_SYNC_CHANGED |
2959 MAC_STATUS_CFG_CHANGED |
2960 MAC_STATUS_MI_COMPLETION |
2961 MAC_STATUS_LNKSTATE_CHANGED));
2962 udelay(40);
2963
8ef21428
MC		 2964 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2965 tw32_f(MAC_MI_MODE,
2966 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2967 udelay(80);
2968 }
1da177e4
LT		 2969
2970 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2971
2972 /* Some third-party PHYs need to be reset on link going
2973 * down.
2974 */
2975 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2978 netif_carrier_ok(tp->dev)) {
2979 tg3_readphy(tp, MII_BMSR, &bmsr);
2980 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2981 !(bmsr & BMSR_LSTATUS))
2982 force_reset = 1;
2983 }
2984 if (force_reset)
2985 tg3_phy_reset(tp);
2986
2987 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2988 tg3_readphy(tp, MII_BMSR, &bmsr);
2989 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2990 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2991 bmsr = 0;
2992
2993 if (!(bmsr & BMSR_LSTATUS)) {
2994 err = tg3_init_5401phy_dsp(tp);
2995 if (err)
2996 return err;
2997
2998 tg3_readphy(tp, MII_BMSR, &bmsr);
2999 for (i = 0; i < 1000; i++) {
3000 udelay(10);
3001 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3002 (bmsr & BMSR_LSTATUS)) {
3003 udelay(40);
3004 break;
3005 }
3006 }
3007
3008 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3009 !(bmsr & BMSR_LSTATUS) &&
3010 tp->link_config.active_speed == SPEED_1000) {
3011 err = tg3_phy_reset(tp);
3012 if (!err)
3013 err = tg3_init_5401phy_dsp(tp);
3014 if (err)
3015 return err;
3016 }
3017 }
3018 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3019 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3020 /* 5701 {A0,B0} CRC bug workaround */
3021 tg3_writephy(tp, 0x15, 0x0a75);
3022 tg3_writephy(tp, 0x1c, 0x8c68);
3023 tg3_writephy(tp, 0x1c, 0x8d68);
3024 tg3_writephy(tp, 0x1c, 0x8c68);
3025 }
3026
3027 /* Clear pending interrupts... */
3028 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3029 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3030
3031 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3032 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3033 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3034 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3035
3036 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3038 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3039 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3040 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3041 else
3042 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3043 }
3044
3045 current_link_up = 0;
3046 current_speed = SPEED_INVALID;
3047 current_duplex = DUPLEX_INVALID;
3048
3049 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3050 u32 val;
3051
3052 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3053 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3054 if (!(val & (1 << 10))) {
3055 val |= (1 << 10);
3056 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3057 goto relink;
3058 }
3059 }
3060
3061 bmsr = 0;
3062 for (i = 0; i < 100; i++) {
3063 tg3_readphy(tp, MII_BMSR, &bmsr);
3064 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3065 (bmsr & BMSR_LSTATUS))
3066 break;
3067 udelay(40);
3068 }
3069
3070 if (bmsr & BMSR_LSTATUS) {
3071 u32 aux_stat, bmcr;
3072
3073 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3074 for (i = 0; i < 2000; i++) {
3075 udelay(10);
3076 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3077 aux_stat)
3078 break;
3079 }
3080
3081 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3082 &current_speed,
3083 &current_duplex);
3084
3085 bmcr = 0;
3086 for (i = 0; i < 200; i++) {
3087 tg3_readphy(tp, MII_BMCR, &bmcr);
3088 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3089 continue;
3090 if (bmcr && bmcr != 0x7fff)
3091 break;
3092 udelay(10);
3093 }
3094
ef167e27
MC		 3095 lcl_adv = 0;
3096 rmt_adv = 0;
1da177e4 3097
ef167e27
MC		 3098 tp->link_config.active_speed = current_speed;
3099 tp->link_config.active_duplex = current_duplex;
3100
3101 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3102 if ((bmcr & BMCR_ANENABLE) &&
3103 tg3_copper_is_advertising_all(tp,
3104 tp->link_config.advertising)) {
3105 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3106 &rmt_adv))
3107 current_link_up = 1;
1da177e4
LT		 3108 }
3109 } else {
3110 if (!(bmcr & BMCR_ANENABLE) &&
3111 tp->link_config.speed == current_speed &&
ef167e27
MC		 3112 tp->link_config.duplex == current_duplex &&
3113 tp->link_config.flowctrl ==
3114 tp->link_config.active_flowctrl) {
1da177e4 3115 current_link_up = 1;
1da177e4
LT		 3116 }
3117 }
3118
ef167e27
MC		 3119 if (current_link_up == 1 &&
3120 tp->link_config.active_duplex == DUPLEX_FULL)
3121 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3122 }
3123
1da177e4 3124relink:
6921d201 3125 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3126 u32 tmp;
3127
3128 tg3_phy_copper_begin(tp);
3129
3130 tg3_readphy(tp, MII_BMSR, &tmp);
3131 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3132 (tmp & BMSR_LSTATUS))
3133 current_link_up = 1;
3134 }
3135
3136 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3137 if (current_link_up == 1) {
3138 if (tp->link_config.active_speed == SPEED_100 ||
3139 tp->link_config.active_speed == SPEED_10)
3140 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3141 else
3142 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3143 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3144 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3145 else
1da177e4
LT		 3146 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3147
3148 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3149 if (tp->link_config.active_duplex == DUPLEX_HALF)
3150 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3151
1da177e4 3152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3153 if (current_link_up == 1 &&
3154 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3155 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3156 else
3157 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3158 }
3159
3160 /* ??? Without this setting Netgear GA302T PHY does not
3161 * ??? send/receive packets...
3162 */
3163 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3164 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3165 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3166 tw32_f(MAC_MI_MODE, tp->mi_mode);
3167 udelay(80);
3168 }
3169
3170 tw32_f(MAC_MODE, tp->mac_mode);
3171 udelay(40);
3172
3173 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3174 /* Polled via timer. */
3175 tw32_f(MAC_EVENT, 0);
3176 } else {
3177 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3178 }
3179 udelay(40);
3180
3181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3182 current_link_up == 1 &&
3183 tp->link_config.active_speed == SPEED_1000 &&
3184 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3185 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3186 udelay(120);
3187 tw32_f(MAC_STATUS,
3188 (MAC_STATUS_SYNC_CHANGED |
3189 MAC_STATUS_CFG_CHANGED));
3190 udelay(40);
3191 tg3_write_mem(tp,
3192 NIC_SRAM_FIRMWARE_MBOX,
3193 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3194 }
3195
5e7dfd0f
MC		 3196 /* Prevent send BD corruption. */
3197 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3198 u16 oldlnkctl, newlnkctl;
3199
3200 pci_read_config_word(tp->pdev,
3201 tp->pcie_cap + PCI_EXP_LNKCTL,
3202 &oldlnkctl);
3203 if (tp->link_config.active_speed == SPEED_100 ||
3204 tp->link_config.active_speed == SPEED_10)
3205 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3206 else
3207 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3208 if (newlnkctl != oldlnkctl)
3209 pci_write_config_word(tp->pdev,
3210 tp->pcie_cap + PCI_EXP_LNKCTL,
3211 newlnkctl);
255ca311
MC		 3212 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3213 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3214 if (tp->link_config.active_speed == SPEED_100 ||
3215 tp->link_config.active_speed == SPEED_10)
3216 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3217 else
3218 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3219 if (newreg != oldreg)
3220 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC		 3221 }
3222
1da177e4
LT		 3223 if (current_link_up != netif_carrier_ok(tp->dev)) {
3224 if (current_link_up)
3225 netif_carrier_on(tp->dev);
3226 else
3227 netif_carrier_off(tp->dev);
3228 tg3_link_report(tp);
3229 }
3230
3231 return 0;
3232}
3233
3234struct tg3_fiber_aneginfo {
3235 int state;
3236#define ANEG_STATE_UNKNOWN 0
3237#define ANEG_STATE_AN_ENABLE 1
3238#define ANEG_STATE_RESTART_INIT 2
3239#define ANEG_STATE_RESTART 3
3240#define ANEG_STATE_DISABLE_LINK_OK 4
3241#define ANEG_STATE_ABILITY_DETECT_INIT 5
3242#define ANEG_STATE_ABILITY_DETECT 6
3243#define ANEG_STATE_ACK_DETECT_INIT 7
3244#define ANEG_STATE_ACK_DETECT 8
3245#define ANEG_STATE_COMPLETE_ACK_INIT 9
3246#define ANEG_STATE_COMPLETE_ACK 10
3247#define ANEG_STATE_IDLE_DETECT_INIT 11
3248#define ANEG_STATE_IDLE_DETECT 12
3249#define ANEG_STATE_LINK_OK 13
3250#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3251#define ANEG_STATE_NEXT_PAGE_WAIT 15
3252
3253 u32 flags;
3254#define MR_AN_ENABLE 0x00000001
3255#define MR_RESTART_AN 0x00000002
3256#define MR_AN_COMPLETE 0x00000004
3257#define MR_PAGE_RX 0x00000008
3258#define MR_NP_LOADED 0x00000010
3259#define MR_TOGGLE_TX 0x00000020
3260#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3261#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3262#define MR_LP_ADV_SYM_PAUSE 0x00000100
3263#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3264#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3265#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3266#define MR_LP_ADV_NEXT_PAGE 0x00001000
3267#define MR_TOGGLE_RX 0x00002000
3268#define MR_NP_RX 0x00004000
3269
3270#define MR_LINK_OK 0x80000000
3271
3272 unsigned long link_time, cur_time;
3273
3274 u32 ability_match_cfg;
3275 int ability_match_count;
3276
3277 char ability_match, idle_match, ack_match;
3278
3279 u32 txconfig, rxconfig;
3280#define ANEG_CFG_NP 0x00000080
3281#define ANEG_CFG_ACK 0x00000040
3282#define ANEG_CFG_RF2 0x00000020
3283#define ANEG_CFG_RF1 0x00000010
3284#define ANEG_CFG_PS2 0x00000001
3285#define ANEG_CFG_PS1 0x00008000
3286#define ANEG_CFG_HD 0x00004000
3287#define ANEG_CFG_FD 0x00002000
3288#define ANEG_CFG_INVAL 0x00001f06
3289
3290};
3291#define ANEG_OK 0
3292#define ANEG_DONE 1
3293#define ANEG_TIMER_ENAB 2
3294#define ANEG_FAILED -1
3295
3296#define ANEG_STATE_SETTLE_TIME 10000
3297
3298static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3299 struct tg3_fiber_aneginfo *ap)
3300{
5be73b47 3301 u16 flowctrl;
1da177e4
LT		 3302 unsigned long delta;
3303 u32 rx_cfg_reg;
3304 int ret;
3305
3306 if (ap->state == ANEG_STATE_UNKNOWN) {
3307 ap->rxconfig = 0;
3308 ap->link_time = 0;
3309 ap->cur_time = 0;
3310 ap->ability_match_cfg = 0;
3311 ap->ability_match_count = 0;
3312 ap->ability_match = 0;
3313 ap->idle_match = 0;
3314 ap->ack_match = 0;
3315 }
3316 ap->cur_time++;
3317
3318 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3319 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3320
3321 if (rx_cfg_reg != ap->ability_match_cfg) {
3322 ap->ability_match_cfg = rx_cfg_reg;
3323 ap->ability_match = 0;
3324 ap->ability_match_count = 0;
3325 } else {
3326 if (++ap->ability_match_count > 1) {
3327 ap->ability_match = 1;
3328 ap->ability_match_cfg = rx_cfg_reg;
3329 }
3330 }
3331 if (rx_cfg_reg & ANEG_CFG_ACK)
3332 ap->ack_match = 1;
3333 else
3334 ap->ack_match = 0;
3335
3336 ap->idle_match = 0;
3337 } else {
3338 ap->idle_match = 1;
3339 ap->ability_match_cfg = 0;
3340 ap->ability_match_count = 0;
3341 ap->ability_match = 0;
3342 ap->ack_match = 0;
3343
3344 rx_cfg_reg = 0;
3345 }
3346
3347 ap->rxconfig = rx_cfg_reg;
3348 ret = ANEG_OK;
3349
3350 switch(ap->state) {
3351 case ANEG_STATE_UNKNOWN:
3352 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3353 ap->state = ANEG_STATE_AN_ENABLE;
3354
3355 /* fallthru */
3356 case ANEG_STATE_AN_ENABLE:
3357 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3358 if (ap->flags & MR_AN_ENABLE) {
3359 ap->link_time = 0;
3360 ap->cur_time = 0;
3361 ap->ability_match_cfg = 0;
3362 ap->ability_match_count = 0;
3363 ap->ability_match = 0;
3364 ap->idle_match = 0;
3365 ap->ack_match = 0;
3366
3367 ap->state = ANEG_STATE_RESTART_INIT;
3368 } else {
3369 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3370 }
3371 break;
3372
3373 case ANEG_STATE_RESTART_INIT:
3374 ap->link_time = ap->cur_time;
3375 ap->flags &= ~(MR_NP_LOADED);
3376 ap->txconfig = 0;
3377 tw32(MAC_TX_AUTO_NEG, 0);
3378 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3379 tw32_f(MAC_MODE, tp->mac_mode);
3380 udelay(40);
3381
3382 ret = ANEG_TIMER_ENAB;
3383 ap->state = ANEG_STATE_RESTART;
3384
3385 /* fallthru */
3386 case ANEG_STATE_RESTART:
3387 delta = ap->cur_time - ap->link_time;
3388 if (delta > ANEG_STATE_SETTLE_TIME) {
3389 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3390 } else {
3391 ret = ANEG_TIMER_ENAB;
3392 }
3393 break;
3394
3395 case ANEG_STATE_DISABLE_LINK_OK:
3396 ret = ANEG_DONE;
3397 break;
3398
3399 case ANEG_STATE_ABILITY_DETECT_INIT:
3400 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3401 ap->txconfig = ANEG_CFG_FD;
3402 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3403 if (flowctrl & ADVERTISE_1000XPAUSE)
3404 ap->txconfig |= ANEG_CFG_PS1;
3405 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3406 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3407 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3408 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3409 tw32_f(MAC_MODE, tp->mac_mode);
3410 udelay(40);
3411
3412 ap->state = ANEG_STATE_ABILITY_DETECT;
3413 break;
3414
3415 case ANEG_STATE_ABILITY_DETECT:
3416 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3417 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3418 }
3419 break;
3420
3421 case ANEG_STATE_ACK_DETECT_INIT:
3422 ap->txconfig |= ANEG_CFG_ACK;
3423 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3424 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3425 tw32_f(MAC_MODE, tp->mac_mode);
3426 udelay(40);
3427
3428 ap->state = ANEG_STATE_ACK_DETECT;
3429
3430 /* fallthru */
3431 case ANEG_STATE_ACK_DETECT:
3432 if (ap->ack_match != 0) {
3433 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3434 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3435 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3436 } else {
3437 ap->state = ANEG_STATE_AN_ENABLE;
3438 }
3439 } else if (ap->ability_match != 0 &&
3440 ap->rxconfig == 0) {
3441 ap->state = ANEG_STATE_AN_ENABLE;
3442 }
3443 break;
3444
3445 case ANEG_STATE_COMPLETE_ACK_INIT:
3446 if (ap->rxconfig & ANEG_CFG_INVAL) {
3447 ret = ANEG_FAILED;
3448 break;
3449 }
3450 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3451 MR_LP_ADV_HALF_DUPLEX |
3452 MR_LP_ADV_SYM_PAUSE |
3453 MR_LP_ADV_ASYM_PAUSE |
3454 MR_LP_ADV_REMOTE_FAULT1 |
3455 MR_LP_ADV_REMOTE_FAULT2 |
3456 MR_LP_ADV_NEXT_PAGE |
3457 MR_TOGGLE_RX |
3458 MR_NP_RX);
3459 if (ap->rxconfig & ANEG_CFG_FD)
3460 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3461 if (ap->rxconfig & ANEG_CFG_HD)
3462 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3463 if (ap->rxconfig & ANEG_CFG_PS1)
3464 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3465 if (ap->rxconfig & ANEG_CFG_PS2)
3466 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3467 if (ap->rxconfig & ANEG_CFG_RF1)
3468 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3469 if (ap->rxconfig & ANEG_CFG_RF2)
3470 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3471 if (ap->rxconfig & ANEG_CFG_NP)
3472 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3473
3474 ap->link_time = ap->cur_time;
3475
3476 ap->flags ^= (MR_TOGGLE_TX);
3477 if (ap->rxconfig & 0x0008)
3478 ap->flags |= MR_TOGGLE_RX;
3479 if (ap->rxconfig & ANEG_CFG_NP)
3480 ap->flags |= MR_NP_RX;
3481 ap->flags |= MR_PAGE_RX;
3482
3483 ap->state = ANEG_STATE_COMPLETE_ACK;
3484 ret = ANEG_TIMER_ENAB;
3485 break;
3486
3487 case ANEG_STATE_COMPLETE_ACK:
3488 if (ap->ability_match != 0 &&
3489 ap->rxconfig == 0) {
3490 ap->state = ANEG_STATE_AN_ENABLE;
3491 break;
3492 }
3493 delta = ap->cur_time - ap->link_time;
3494 if (delta > ANEG_STATE_SETTLE_TIME) {
3495 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3496 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3497 } else {
3498 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3499 !(ap->flags & MR_NP_RX)) {
3500 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3501 } else {
3502 ret = ANEG_FAILED;
3503 }
3504 }
3505 }
3506 break;
3507
3508 case ANEG_STATE_IDLE_DETECT_INIT:
3509 ap->link_time = ap->cur_time;
3510 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3511 tw32_f(MAC_MODE, tp->mac_mode);
3512 udelay(40);
3513
3514 ap->state = ANEG_STATE_IDLE_DETECT;
3515 ret = ANEG_TIMER_ENAB;
3516 break;
3517
3518 case ANEG_STATE_IDLE_DETECT:
3519 if (ap->ability_match != 0 &&
3520 ap->rxconfig == 0) {
3521 ap->state = ANEG_STATE_AN_ENABLE;
3522 break;
3523 }
3524 delta = ap->cur_time - ap->link_time;
3525 if (delta > ANEG_STATE_SETTLE_TIME) {
3526 /* XXX another gem from the Broadcom driver :( */
3527 ap->state = ANEG_STATE_LINK_OK;
3528 }
3529 break;
3530
3531 case ANEG_STATE_LINK_OK:
3532 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3533 ret = ANEG_DONE;
3534 break;
3535
3536 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3537 /* ??? unimplemented */
3538 break;
3539
3540 case ANEG_STATE_NEXT_PAGE_WAIT:
3541 /* ??? unimplemented */
3542 break;
3543
3544 default:
3545 ret = ANEG_FAILED;
3546 break;
855e1111 3547 }
1da177e4
LT		 3548
3549 return ret;
3550}
3551
5be73b47 3552static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3553{
3554 int res = 0;
3555 struct tg3_fiber_aneginfo aninfo;
3556 int status = ANEG_FAILED;
3557 unsigned int tick;
3558 u32 tmp;
3559
3560 tw32_f(MAC_TX_AUTO_NEG, 0);
3561
3562 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3563 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3564 udelay(40);
3565
3566 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3567 udelay(40);
3568
3569 memset(&aninfo, 0, sizeof(aninfo));
3570 aninfo.flags |= MR_AN_ENABLE;
3571 aninfo.state = ANEG_STATE_UNKNOWN;
3572 aninfo.cur_time = 0;
3573 tick = 0;
3574 while (++tick < 195000) {
3575 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3576 if (status == ANEG_DONE || status == ANEG_FAILED)
3577 break;
3578
3579 udelay(1);
3580 }
3581
3582 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3583 tw32_f(MAC_MODE, tp->mac_mode);
3584 udelay(40);
3585
5be73b47
MC		 3586 *txflags = aninfo.txconfig;
3587 *rxflags = aninfo.flags;
1da177e4
LT		 3588
3589 if (status == ANEG_DONE &&
3590 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3591 MR_LP_ADV_FULL_DUPLEX)))
3592 res = 1;
3593
3594 return res;
3595}
3596
3597static void tg3_init_bcm8002(struct tg3 *tp)
3598{
3599 u32 mac_status = tr32(MAC_STATUS);
3600 int i;
3601
3602 /* Reset when initting first time or we have a link. */
3603 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3604 !(mac_status & MAC_STATUS_PCS_SYNCED))
3605 return;
3606
3607 /* Set PLL lock range. */
3608 tg3_writephy(tp, 0x16, 0x8007);
3609
3610 /* SW reset */
3611 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3612
3613 /* Wait for reset to complete. */
3614 /* XXX schedule_timeout() ... */
3615 for (i = 0; i < 500; i++)
3616 udelay(10);
3617
3618 /* Config mode; select PMA/Ch 1 regs. */
3619 tg3_writephy(tp, 0x10, 0x8411);
3620
3621 /* Enable auto-lock and comdet, select txclk for tx. */
3622 tg3_writephy(tp, 0x11, 0x0a10);
3623
3624 tg3_writephy(tp, 0x18, 0x00a0);
3625 tg3_writephy(tp, 0x16, 0x41ff);
3626
3627 /* Assert and deassert POR. */
3628 tg3_writephy(tp, 0x13, 0x0400);
3629 udelay(40);
3630 tg3_writephy(tp, 0x13, 0x0000);
3631
3632 tg3_writephy(tp, 0x11, 0x0a50);
3633 udelay(40);
3634 tg3_writephy(tp, 0x11, 0x0a10);
3635
3636 /* Wait for signal to stabilize */
3637 /* XXX schedule_timeout() ... */
3638 for (i = 0; i < 15000; i++)
3639 udelay(10);
3640
3641 /* Deselect the channel register so we can read the PHYID
3642 * later.
3643 */
3644 tg3_writephy(tp, 0x10, 0x8011);
3645}
3646
3647static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3648{
82cd3d11 3649 u16 flowctrl;
1da177e4
LT		 3650 u32 sg_dig_ctrl, sg_dig_status;
3651 u32 serdes_cfg, expected_sg_dig_ctrl;
3652 int workaround, port_a;
3653 int current_link_up;
3654
3655 serdes_cfg = 0;
3656 expected_sg_dig_ctrl = 0;
3657 workaround = 0;
3658 port_a = 1;
3659 current_link_up = 0;
3660
3661 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3662 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3663 workaround = 1;
3664 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3665 port_a = 0;
3666
3667 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3668 /* preserve bits 20-23 for voltage regulator */
3669 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3670 }
3671
3672 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3673
3674 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3675 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3676 if (workaround) {
3677 u32 val = serdes_cfg;
3678
3679 if (port_a)
3680 val |= 0xc010000;
3681 else
3682 val |= 0x4010000;
3683 tw32_f(MAC_SERDES_CFG, val);
3684 }
c98f6e3b
MC		 3685
3686 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3687 }
3688 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3689 tg3_setup_flow_control(tp, 0, 0);
3690 current_link_up = 1;
3691 }
3692 goto out;
3693 }
3694
3695 /* Want auto-negotiation. */
c98f6e3b 3696 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3697
82cd3d11
MC		 3698 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3699 if (flowctrl & ADVERTISE_1000XPAUSE)
3700 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3701 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3702 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3703
3704 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3705 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3706 tp->serdes_counter &&
3707 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3708 MAC_STATUS_RCVD_CFG)) ==
3709 MAC_STATUS_PCS_SYNCED)) {
3710 tp->serdes_counter--;
3711 current_link_up = 1;
3712 goto out;
3713 }
3714restart_autoneg:
1da177e4
LT		 3715 if (workaround)
3716 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3717 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3718 udelay(5);
3719 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3720
3d3ebe74
MC		 3721 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3722 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3723 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3724 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3725 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3726 mac_status = tr32(MAC_STATUS);
3727
c98f6e3b 3728 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3729 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3730 u32 local_adv = 0, remote_adv = 0;
3731
3732 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3733 local_adv |= ADVERTISE_1000XPAUSE;
3734 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3735 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3736
c98f6e3b 3737 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3738 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3739 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3740 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3741
3742 tg3_setup_flow_control(tp, local_adv, remote_adv);
3743 current_link_up = 1;
3d3ebe74
MC		 3744 tp->serdes_counter = 0;
3745 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3746 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3747 if (tp->serdes_counter)
3748 tp->serdes_counter--;
1da177e4
LT		 3749 else {
3750 if (workaround) {
3751 u32 val = serdes_cfg;
3752
3753 if (port_a)
3754 val |= 0xc010000;
3755 else
3756 val |= 0x4010000;
3757
3758 tw32_f(MAC_SERDES_CFG, val);
3759 }
3760
c98f6e3b 3761 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3762 udelay(40);
3763
3764 /* Link parallel detection - link is up */
3765 /* only if we have PCS_SYNC and not */
3766 /* receiving config code words */
3767 mac_status = tr32(MAC_STATUS);
3768 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3769 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3770 tg3_setup_flow_control(tp, 0, 0);
3771 current_link_up = 1;
3d3ebe74
MC		 3772 tp->tg3_flags2 |=
3773 TG3_FLG2_PARALLEL_DETECT;
3774 tp->serdes_counter =
3775 SERDES_PARALLEL_DET_TIMEOUT;
3776 } else
3777 goto restart_autoneg;
1da177e4
LT		 3778 }
3779 }
3d3ebe74
MC		 3780 } else {
3781 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3782 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3783 }
3784
3785out:
3786 return current_link_up;
3787}
3788
3789static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3790{
3791 int current_link_up = 0;
3792
5cf64b8a 3793 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3794 goto out;
1da177e4
LT		 3795
3796 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3797 u32 txflags, rxflags;
1da177e4 3798 int i;
6aa20a22 3799
5be73b47
MC		 3800 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3801 u32 local_adv = 0, remote_adv = 0;
1da177e4 3802
5be73b47
MC		 3803 if (txflags & ANEG_CFG_PS1)
3804 local_adv |= ADVERTISE_1000XPAUSE;
3805 if (txflags & ANEG_CFG_PS2)
3806 local_adv |= ADVERTISE_1000XPSE_ASYM;
3807
3808 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3809 remote_adv |= LPA_1000XPAUSE;
3810 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3812
3813 tg3_setup_flow_control(tp, local_adv, remote_adv);
3814
1da177e4
LT		 3815 current_link_up = 1;
3816 }
3817 for (i = 0; i < 30; i++) {
3818 udelay(20);
3819 tw32_f(MAC_STATUS,
3820 (MAC_STATUS_SYNC_CHANGED |
3821 MAC_STATUS_CFG_CHANGED));
3822 udelay(40);
3823 if ((tr32(MAC_STATUS) &
3824 (MAC_STATUS_SYNC_CHANGED |
3825 MAC_STATUS_CFG_CHANGED)) == 0)
3826 break;
3827 }
3828
3829 mac_status = tr32(MAC_STATUS);
3830 if (current_link_up == 0 &&
3831 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3832 !(mac_status & MAC_STATUS_RCVD_CFG))
3833 current_link_up = 1;
3834 } else {
5be73b47
MC		 3835 tg3_setup_flow_control(tp, 0, 0);
3836
1da177e4
LT		 3837 /* Forcing 1000FD link up. */
3838 current_link_up = 1;
1da177e4
LT		 3839
3840 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3841 udelay(40);
e8f3f6ca
MC		 3842
3843 tw32_f(MAC_MODE, tp->mac_mode);
3844 udelay(40);
1da177e4
LT		 3845 }
3846
3847out:
3848 return current_link_up;
3849}
3850
3851static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3852{
3853 u32 orig_pause_cfg;
3854 u16 orig_active_speed;
3855 u8 orig_active_duplex;
3856 u32 mac_status;
3857 int current_link_up;
3858 int i;
3859
8d018621 3860 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3861 orig_active_speed = tp->link_config.active_speed;
3862 orig_active_duplex = tp->link_config.active_duplex;
3863
3864 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3865 netif_carrier_ok(tp->dev) &&
3866 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3867 mac_status = tr32(MAC_STATUS);
3868 mac_status &= (MAC_STATUS_PCS_SYNCED |
3869 MAC_STATUS_SIGNAL_DET |
3870 MAC_STATUS_CFG_CHANGED |
3871 MAC_STATUS_RCVD_CFG);
3872 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3873 MAC_STATUS_SIGNAL_DET)) {
3874 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3875 MAC_STATUS_CFG_CHANGED));
3876 return 0;
3877 }
3878 }
3879
3880 tw32_f(MAC_TX_AUTO_NEG, 0);
3881
3882 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3883 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3884 tw32_f(MAC_MODE, tp->mac_mode);
3885 udelay(40);
3886
3887 if (tp->phy_id == PHY_ID_BCM8002)
3888 tg3_init_bcm8002(tp);
3889
3890 /* Enable link change event even when serdes polling. */
3891 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3892 udelay(40);
3893
3894 current_link_up = 0;
3895 mac_status = tr32(MAC_STATUS);
3896
3897 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3898 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3899 else
3900 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3901
1da177e4
LT		 3902 tp->hw_status->status =
3903 (SD_STATUS_UPDATED |
3904 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3905
3906 for (i = 0; i < 100; i++) {
3907 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3908 MAC_STATUS_CFG_CHANGED));
3909 udelay(5);
3910 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3911 MAC_STATUS_CFG_CHANGED |
3912 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3913 break;
3914 }
3915
3916 mac_status = tr32(MAC_STATUS);
3917 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3918 current_link_up = 0;
3d3ebe74
MC		 3919 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3920 tp->serdes_counter == 0) {
1da177e4
LT		 3921 tw32_f(MAC_MODE, (tp->mac_mode |
3922 MAC_MODE_SEND_CONFIGS));
3923 udelay(1);
3924 tw32_f(MAC_MODE, tp->mac_mode);
3925 }
3926 }
3927
3928 if (current_link_up == 1) {
3929 tp->link_config.active_speed = SPEED_1000;
3930 tp->link_config.active_duplex = DUPLEX_FULL;
3931 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3932 LED_CTRL_LNKLED_OVERRIDE |
3933 LED_CTRL_1000MBPS_ON));
3934 } else {
3935 tp->link_config.active_speed = SPEED_INVALID;
3936 tp->link_config.active_duplex = DUPLEX_INVALID;
3937 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3938 LED_CTRL_LNKLED_OVERRIDE |
3939 LED_CTRL_TRAFFIC_OVERRIDE));
3940 }
3941
3942 if (current_link_up != netif_carrier_ok(tp->dev)) {
3943 if (current_link_up)
3944 netif_carrier_on(tp->dev);
3945 else
3946 netif_carrier_off(tp->dev);
3947 tg3_link_report(tp);
3948 } else {
8d018621 3949 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3950 if (orig_pause_cfg != now_pause_cfg ||
3951 orig_active_speed != tp->link_config.active_speed ||
3952 orig_active_duplex != tp->link_config.active_duplex)
3953 tg3_link_report(tp);
3954 }
3955
3956 return 0;
3957}
3958
747e8f8b
MC		 3959static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3960{
3961 int current_link_up, err = 0;
3962 u32 bmsr, bmcr;
3963 u16 current_speed;
3964 u8 current_duplex;
ef167e27 3965 u32 local_adv, remote_adv;
747e8f8b
MC		 3966
3967 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3968 tw32_f(MAC_MODE, tp->mac_mode);
3969 udelay(40);
3970
3971 tw32(MAC_EVENT, 0);
3972
3973 tw32_f(MAC_STATUS,
3974 (MAC_STATUS_SYNC_CHANGED |
3975 MAC_STATUS_CFG_CHANGED |
3976 MAC_STATUS_MI_COMPLETION |
3977 MAC_STATUS_LNKSTATE_CHANGED));
3978 udelay(40);
3979
3980 if (force_reset)
3981 tg3_phy_reset(tp);
3982
3983 current_link_up = 0;
3984 current_speed = SPEED_INVALID;
3985 current_duplex = DUPLEX_INVALID;
3986
3987 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3988 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3990 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3991 bmsr |= BMSR_LSTATUS;
3992 else
3993 bmsr &= ~BMSR_LSTATUS;
3994 }
747e8f8b
MC		 3995
3996 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3997
3998 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 3999 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4000 /* do nothing, just check for link up at the end */
4001 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4002 u32 adv, new_adv;
4003
4004 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4005 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4006 ADVERTISE_1000XPAUSE |
4007 ADVERTISE_1000XPSE_ASYM |
4008 ADVERTISE_SLCT);
4009
ba4d07a8 4010 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4011
4012 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4013 new_adv |= ADVERTISE_1000XHALF;
4014 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4015 new_adv |= ADVERTISE_1000XFULL;
4016
4017 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4018 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4019 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4020 tg3_writephy(tp, MII_BMCR, bmcr);
4021
4022 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4023 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4024 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4025
4026 return err;
4027 }
4028 } else {
4029 u32 new_bmcr;
4030
4031 bmcr &= ~BMCR_SPEED1000;
4032 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4033
4034 if (tp->link_config.duplex == DUPLEX_FULL)
4035 new_bmcr |= BMCR_FULLDPLX;
4036
4037 if (new_bmcr != bmcr) {
4038 /* BMCR_SPEED1000 is a reserved bit that needs
4039 * to be set on write.
4040 */
4041 new_bmcr |= BMCR_SPEED1000;
4042
4043 /* Force a linkdown */
4044 if (netif_carrier_ok(tp->dev)) {
4045 u32 adv;
4046
4047 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4048 adv &= ~(ADVERTISE_1000XFULL |
4049 ADVERTISE_1000XHALF |
4050 ADVERTISE_SLCT);
4051 tg3_writephy(tp, MII_ADVERTISE, adv);
4052 tg3_writephy(tp, MII_BMCR, bmcr |
4053 BMCR_ANRESTART |
4054 BMCR_ANENABLE);
4055 udelay(10);
4056 netif_carrier_off(tp->dev);
4057 }
4058 tg3_writephy(tp, MII_BMCR, new_bmcr);
4059 bmcr = new_bmcr;
4060 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4061 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4062 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4063 ASIC_REV_5714) {
4064 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4065 bmsr |= BMSR_LSTATUS;
4066 else
4067 bmsr &= ~BMSR_LSTATUS;
4068 }
747e8f8b
MC		 4069 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4070 }
4071 }
4072
4073 if (bmsr & BMSR_LSTATUS) {
4074 current_speed = SPEED_1000;
4075 current_link_up = 1;
4076 if (bmcr & BMCR_FULLDPLX)
4077 current_duplex = DUPLEX_FULL;
4078 else
4079 current_duplex = DUPLEX_HALF;
4080
ef167e27
MC		 4081 local_adv = 0;
4082 remote_adv = 0;
4083
747e8f8b 4084 if (bmcr & BMCR_ANENABLE) {
ef167e27 4085 u32 common;
747e8f8b
MC		 4086
4087 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4088 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4089 common = local_adv & remote_adv;
4090 if (common & (ADVERTISE_1000XHALF |
4091 ADVERTISE_1000XFULL)) {
4092 if (common & ADVERTISE_1000XFULL)
4093 current_duplex = DUPLEX_FULL;
4094 else
4095 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4096 }
4097 else
4098 current_link_up = 0;
4099 }
4100 }
4101
ef167e27
MC		 4102 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4103 tg3_setup_flow_control(tp, local_adv, remote_adv);
4104
747e8f8b
MC		 4105 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4106 if (tp->link_config.active_duplex == DUPLEX_HALF)
4107 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4108
4109 tw32_f(MAC_MODE, tp->mac_mode);
4110 udelay(40);
4111
4112 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4113
4114 tp->link_config.active_speed = current_speed;
4115 tp->link_config.active_duplex = current_duplex;
4116
4117 if (current_link_up != netif_carrier_ok(tp->dev)) {
4118 if (current_link_up)
4119 netif_carrier_on(tp->dev);
4120 else {
4121 netif_carrier_off(tp->dev);
4122 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4123 }
4124 tg3_link_report(tp);
4125 }
4126 return err;
4127}
4128
4129static void tg3_serdes_parallel_detect(struct tg3 *tp)
4130{
3d3ebe74 4131 if (tp->serdes_counter) {
747e8f8b 4132 /* Give autoneg time to complete. */
3d3ebe74 4133 tp->serdes_counter--;
747e8f8b
MC		 4134 return;
4135 }
4136 if (!netif_carrier_ok(tp->dev) &&
4137 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4138 u32 bmcr;
4139
4140 tg3_readphy(tp, MII_BMCR, &bmcr);
4141 if (bmcr & BMCR_ANENABLE) {
4142 u32 phy1, phy2;
4143
4144 /* Select shadow register 0x1f */
4145 tg3_writephy(tp, 0x1c, 0x7c00);
4146 tg3_readphy(tp, 0x1c, &phy1);
4147
4148 /* Select expansion interrupt status register */
4149 tg3_writephy(tp, 0x17, 0x0f01);
4150 tg3_readphy(tp, 0x15, &phy2);
4151 tg3_readphy(tp, 0x15, &phy2);
4152
4153 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4154 /* We have signal detect and not receiving
4155 * config code words, link is up by parallel
4156 * detection.
4157 */
4158
4159 bmcr &= ~BMCR_ANENABLE;
4160 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4161 tg3_writephy(tp, MII_BMCR, bmcr);
4162 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4163 }
4164 }
4165 }
4166 else if (netif_carrier_ok(tp->dev) &&
4167 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4168 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4169 u32 phy2;
4170
4171 /* Select expansion interrupt status register */
4172 tg3_writephy(tp, 0x17, 0x0f01);
4173 tg3_readphy(tp, 0x15, &phy2);
4174 if (phy2 & 0x20) {
4175 u32 bmcr;
4176
4177 /* Config code words received, turn on autoneg. */
4178 tg3_readphy(tp, MII_BMCR, &bmcr);
4179 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4180
4181 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4182
4183 }
4184 }
4185}
4186
1da177e4
LT		 4187static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4188{
4189 int err;
4190
4191 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4192 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4193 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4194 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4195 } else {
4196 err = tg3_setup_copper_phy(tp, force_reset);
4197 }
4198
bcb37f6c 4199 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4200 u32 val, scale;
4201
4202 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4203 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4204 scale = 65;
4205 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4206 scale = 6;
4207 else
4208 scale = 12;
4209
4210 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4211 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4212 tw32(GRC_MISC_CFG, val);
4213 }
4214
1da177e4
LT		 4215 if (tp->link_config.active_speed == SPEED_1000 &&
4216 tp->link_config.active_duplex == DUPLEX_HALF)
4217 tw32(MAC_TX_LENGTHS,
4218 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4219 (6 << TX_LENGTHS_IPG_SHIFT) |
4220 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4221 else
4222 tw32(MAC_TX_LENGTHS,
4223 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4224 (6 << TX_LENGTHS_IPG_SHIFT) |
4225 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4226
4227 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4228 if (netif_carrier_ok(tp->dev)) {
4229 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4230 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4231 } else {
4232 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4233 }
4234 }
4235
8ed5d97e
MC		 4236 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4237 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4238 if (!netif_carrier_ok(tp->dev))
4239 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4240 tp->pwrmgmt_thresh;
4241 else
4242 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4243 tw32(PCIE_PWR_MGMT_THRESH, val);
4244 }
4245
1da177e4
LT		 4246 return err;
4247}
4248
df3e6548
MC		 4249/* This is called whenever we suspect that the system chipset is re-
4250 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4251 * is bogus tx completions. We try to recover by setting the
4252 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4253 * in the workqueue.
4254 */
4255static void tg3_tx_recover(struct tg3 *tp)
4256{
4257 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4258 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4259
4260 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4261 "mapped I/O cycles to the network device, attempting to "
4262 "recover. Please report the problem to the driver maintainer "
4263 "and include system chipset information.\n", tp->dev->name);
4264
4265 spin_lock(&tp->lock);
df3e6548 4266 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4267 spin_unlock(&tp->lock);
4268}
4269
1b2a7205
MC		 4270static inline u32 tg3_tx_avail(struct tg3 *tp)
4271{
4272 smp_mb();
4273 return (tp->tx_pending -
4274 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4275}
4276
1da177e4
LT		 4277/* Tigon3 never reports partial packet sends. So we do not
4278 * need special logic to handle SKBs that have not had all
4279 * of their frags sent yet, like SunGEM does.
4280 */
4281static void tg3_tx(struct tg3 *tp)
4282{
4283 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4284 u32 sw_idx = tp->tx_cons;
4285
4286 while (sw_idx != hw_idx) {
4287 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4288 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4289 int i, tx_bug = 0;
4290
4291 if (unlikely(skb == NULL)) {
4292 tg3_tx_recover(tp);
4293 return;
4294 }
1da177e4 4295
90079ce8 4296 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4297
4298 ri->skb = NULL;
4299
4300 sw_idx = NEXT_TX(sw_idx);
4301
4302 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1da177e4 4303 ri = &tp->tx_buffers[sw_idx];
df3e6548
MC		 4304 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4305 tx_bug = 1;
1da177e4
LT		 4306 sw_idx = NEXT_TX(sw_idx);
4307 }
4308
f47c11ee 4309 dev_kfree_skb(skb);
df3e6548
MC		 4310
4311 if (unlikely(tx_bug)) {
4312 tg3_tx_recover(tp);
4313 return;
4314 }
1da177e4
LT		 4315 }
4316
4317 tp->tx_cons = sw_idx;
4318
1b2a7205
MC		 4319 /* Need to make the tx_cons update visible to tg3_start_xmit()
4320 * before checking for netif_queue_stopped(). Without the
4321 * memory barrier, there is a small possibility that tg3_start_xmit()
4322 * will miss it and cause the queue to be stopped forever.
4323 */
4324 smp_mb();
4325
4326 if (unlikely(netif_queue_stopped(tp->dev) &&
42952231 4327 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
1b2a7205 4328 netif_tx_lock(tp->dev);
51b91468 4329 if (netif_queue_stopped(tp->dev) &&
42952231 4330 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
51b91468 4331 netif_wake_queue(tp->dev);
1b2a7205 4332 netif_tx_unlock(tp->dev);
51b91468 4333 }
1da177e4
LT		 4334}
4335
4336/* Returns size of skb allocated or < 0 on error.
4337 *
4338 * We only need to fill in the address because the other members
4339 * of the RX descriptor are invariant, see tg3_init_rings.
4340 *
4341 * Note the purposeful assymetry of cpu vs. chip accesses. For
4342 * posting buffers we only dirty the first cache line of the RX
4343 * descriptor (containing the address). Whereas for the RX status
4344 * buffers the cpu only reads the last cacheline of the RX descriptor
4345 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4346 */
4347static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4348 int src_idx, u32 dest_idx_unmasked)
4349{
4350 struct tg3_rx_buffer_desc *desc;
4351 struct ring_info *map, *src_map;
4352 struct sk_buff *skb;
4353 dma_addr_t mapping;
4354 int skb_size, dest_idx;
4355
4356 src_map = NULL;
4357 switch (opaque_key) {
4358 case RXD_OPAQUE_RING_STD:
4359 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4360 desc = &tp->rx_std[dest_idx];
4361 map = &tp->rx_std_buffers[dest_idx];
4362 if (src_idx >= 0)
4363 src_map = &tp->rx_std_buffers[src_idx];
287be12e 4364 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4365 break;
4366
4367 case RXD_OPAQUE_RING_JUMBO:
4368 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4369 desc = &tp->rx_jumbo[dest_idx];
4370 map = &tp->rx_jumbo_buffers[dest_idx];
4371 if (src_idx >= 0)
4372 src_map = &tp->rx_jumbo_buffers[src_idx];
287be12e 4373 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4374 break;
4375
4376 default:
4377 return -EINVAL;
855e1111 4378 }
1da177e4
LT		 4379
4380 /* Do not overwrite any of the map or rp information
4381 * until we are sure we can commit to a new buffer.
4382 *
4383 * Callers depend upon this behavior and assume that
4384 * we leave everything unchanged if we fail.
4385 */
287be12e 4386 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4387 if (skb == NULL)
4388 return -ENOMEM;
4389
1da177e4
LT		 4390 skb_reserve(skb, tp->rx_offset);
4391
287be12e 4392 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4
LT		 4393 PCI_DMA_FROMDEVICE);
4394
4395 map->skb = skb;
4396 pci_unmap_addr_set(map, mapping, mapping);
4397
4398 if (src_map != NULL)
4399 src_map->skb = NULL;
4400
4401 desc->addr_hi = ((u64)mapping >> 32);
4402 desc->addr_lo = ((u64)mapping & 0xffffffff);
4403
4404 return skb_size;
4405}
4406
4407/* We only need to move over in the address because the other
4408 * members of the RX descriptor are invariant. See notes above
4409 * tg3_alloc_rx_skb for full details.
4410 */
4411static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4412 int src_idx, u32 dest_idx_unmasked)
4413{
4414 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4415 struct ring_info *src_map, *dest_map;
4416 int dest_idx;
4417
4418 switch (opaque_key) {
4419 case RXD_OPAQUE_RING_STD:
4420 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4421 dest_desc = &tp->rx_std[dest_idx];
4422 dest_map = &tp->rx_std_buffers[dest_idx];
4423 src_desc = &tp->rx_std[src_idx];
4424 src_map = &tp->rx_std_buffers[src_idx];
4425 break;
4426
4427 case RXD_OPAQUE_RING_JUMBO:
4428 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4429 dest_desc = &tp->rx_jumbo[dest_idx];
4430 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4431 src_desc = &tp->rx_jumbo[src_idx];
4432 src_map = &tp->rx_jumbo_buffers[src_idx];
4433 break;
4434
4435 default:
4436 return;
855e1111 4437 }
1da177e4
LT		 4438
4439 dest_map->skb = src_map->skb;
4440 pci_unmap_addr_set(dest_map, mapping,
4441 pci_unmap_addr(src_map, mapping));
4442 dest_desc->addr_hi = src_desc->addr_hi;
4443 dest_desc->addr_lo = src_desc->addr_lo;
4444
4445 src_map->skb = NULL;
4446}
4447
4448#if TG3_VLAN_TAG_USED
4449static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4450{
1383bdb9 4451 return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
1da177e4
LT		 4452}
4453#endif
4454
4455/* The RX ring scheme is composed of multiple rings which post fresh
4456 * buffers to the chip, and one special ring the chip uses to report
4457 * status back to the host.
4458 *
4459 * The special ring reports the status of received packets to the
4460 * host. The chip does not write into the original descriptor the
4461 * RX buffer was obtained from. The chip simply takes the original
4462 * descriptor as provided by the host, updates the status and length
4463 * field, then writes this into the next status ring entry.
4464 *
4465 * Each ring the host uses to post buffers to the chip is described
4466 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4467 * it is first placed into the on-chip ram. When the packet's length
4468 * is known, it walks down the TG3_BDINFO entries to select the ring.
4469 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4470 * which is within the range of the new packet's length is chosen.
4471 *
4472 * The "separate ring for rx status" scheme may sound queer, but it makes
4473 * sense from a cache coherency perspective. If only the host writes
4474 * to the buffer post rings, and only the chip writes to the rx status
4475 * rings, then cache lines never move beyond shared-modified state.
4476 * If both the host and chip were to write into the same ring, cache line
4477 * eviction could occur since both entities want it in an exclusive state.
4478 */
4479static int tg3_rx(struct tg3 *tp, int budget)
4480{
f92905de 4481 u32 work_mask, rx_std_posted = 0;
483ba50b
MC		 4482 u32 sw_idx = tp->rx_rcb_ptr;
4483 u16 hw_idx;
1da177e4
LT		 4484 int received;
4485
4486 hw_idx = tp->hw_status->idx[0].rx_producer;
4487 /*
4488 * We need to order the read of hw_idx and the read of
4489 * the opaque cookie.
4490 */
4491 rmb();
1da177e4
LT		 4492 work_mask = 0;
4493 received = 0;
4494 while (sw_idx != hw_idx && budget > 0) {
4495 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4496 unsigned int len;
4497 struct sk_buff *skb;
4498 dma_addr_t dma_addr;
4499 u32 opaque_key, desc_idx, *post_ptr;
4500
4501 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4502 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4503 if (opaque_key == RXD_OPAQUE_RING_STD) {
4504 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4505 mapping);
4506 skb = tp->rx_std_buffers[desc_idx].skb;
4507 post_ptr = &tp->rx_std_ptr;
f92905de 4508 rx_std_posted++;
1da177e4
LT		 4509 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4510 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4511 mapping);
4512 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4513 post_ptr = &tp->rx_jumbo_ptr;
4514 }
4515 else {
4516 goto next_pkt_nopost;
4517 }
4518
4519 work_mask |= opaque_key;
4520
4521 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4522 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4523 drop_it:
4524 tg3_recycle_rx(tp, opaque_key,
4525 desc_idx, *post_ptr);
4526 drop_it_no_recycle:
4527 /* Other statistics kept track of by card. */
4528 tp->net_stats.rx_dropped++;
4529 goto next_pkt;
4530 }
4531
ad829268
MC		 4532 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4533 ETH_FCS_LEN;
1da177e4 4534
6aa20a22 4535 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4536 && tp->rx_offset == NET_IP_ALIGN
4537 /* rx_offset will likely not equal NET_IP_ALIGN
4538 * if this is a 5701 card running in PCI-X mode
4539 * [see tg3_get_invariants()]
4540 */
1da177e4
LT		 4541 ) {
4542 int skb_size;
4543
4544 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4545 desc_idx, *post_ptr);
4546 if (skb_size < 0)
4547 goto drop_it;
4548
287be12e 4549 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4550 PCI_DMA_FROMDEVICE);
4551
4552 skb_put(skb, len);
4553 } else {
4554 struct sk_buff *copy_skb;
4555
4556 tg3_recycle_rx(tp, opaque_key,
4557 desc_idx, *post_ptr);
4558
ad829268
MC		 4559 copy_skb = netdev_alloc_skb(tp->dev,
4560 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4561 if (copy_skb == NULL)
4562 goto drop_it_no_recycle;
4563
ad829268 4564 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4565 skb_put(copy_skb, len);
4566 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4567 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4568 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4569
4570 /* We'll reuse the original ring buffer. */
4571 skb = copy_skb;
4572 }
4573
4574 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4575 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4576 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4577 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4578 skb->ip_summed = CHECKSUM_UNNECESSARY;
4579 else
4580 skb->ip_summed = CHECKSUM_NONE;
4581
4582 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4583
4584 if (len > (tp->dev->mtu + ETH_HLEN) &&
4585 skb->protocol != htons(ETH_P_8021Q)) {
4586 dev_kfree_skb(skb);
4587 goto next_pkt;
4588 }
4589
1da177e4
LT		 4590#if TG3_VLAN_TAG_USED
4591 if (tp->vlgrp != NULL &&
4592 desc->type_flags & RXD_FLAG_VLAN) {
4593 tg3_vlan_rx(tp, skb,
4594 desc->err_vlan & RXD_VLAN_MASK);
4595 } else
4596#endif
1383bdb9 4597 napi_gro_receive(&tp->napi, skb);
1da177e4 4598
1da177e4
LT		 4599 received++;
4600 budget--;
4601
4602next_pkt:
4603 (*post_ptr)++;
f92905de
MC		 4604
4605 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4606 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4607
4608 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4609 TG3_64BIT_REG_LOW, idx);
4610 work_mask &= ~RXD_OPAQUE_RING_STD;
4611 rx_std_posted = 0;
4612 }
1da177e4 4613next_pkt_nopost:
483ba50b 4614 sw_idx++;
6b31a515 4615 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4616
4617 /* Refresh hw_idx to see if there is new work */
4618 if (sw_idx == hw_idx) {
4619 hw_idx = tp->hw_status->idx[0].rx_producer;
4620 rmb();
4621 }
1da177e4
LT		 4622 }
4623
4624 /* ACK the status ring. */
483ba50b
MC		 4625 tp->rx_rcb_ptr = sw_idx;
4626 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 4627
4628 /* Refill RX ring(s). */
4629 if (work_mask & RXD_OPAQUE_RING_STD) {
4630 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4631 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4632 sw_idx);
4633 }
4634 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4635 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4636 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4637 sw_idx);
4638 }
4639 mmiowb();
4640
4641 return received;
4642}
4643
6f535763 4644static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
1da177e4 4645{
1da177e4 4646 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4 4647
1da177e4
LT		 4648 /* handle link change and other phy events */
4649 if (!(tp->tg3_flags &
4650 (TG3_FLAG_USE_LINKCHG_REG |
4651 TG3_FLAG_POLL_SERDES))) {
4652 if (sblk->status & SD_STATUS_LINK_CHG) {
4653 sblk->status = SD_STATUS_UPDATED |
4654 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4655 spin_lock(&tp->lock);
dd477003
MC		 4656 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4657 tw32_f(MAC_STATUS,
4658 (MAC_STATUS_SYNC_CHANGED |
4659 MAC_STATUS_CFG_CHANGED |
4660 MAC_STATUS_MI_COMPLETION |
4661 MAC_STATUS_LNKSTATE_CHANGED));
4662 udelay(40);
4663 } else
4664 tg3_setup_phy(tp, 0);
f47c11ee 4665 spin_unlock(&tp->lock);
1da177e4
LT		 4666 }
4667 }
4668
4669 /* run TX completion thread */
4670 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
1da177e4 4671 tg3_tx(tp);
6f535763 4672 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4673 return work_done;
1da177e4
LT		 4674 }
4675
1da177e4
LT		 4676 /* run RX thread, within the bounds set by NAPI.
4677 * All RX "locking" is done by ensuring outside
bea3348e 4678 * code synchronizes with tg3->napi.poll()
1da177e4 4679 */
bea3348e 4680 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
6f535763 4681 work_done += tg3_rx(tp, budget - work_done);
1da177e4 4682
6f535763
DM		 4683 return work_done;
4684}
4685
4686static int tg3_poll(struct napi_struct *napi, int budget)
4687{
4688 struct tg3 *tp = container_of(napi, struct tg3, napi);
4689 int work_done = 0;
4fd7ab59 4690 struct tg3_hw_status *sblk = tp->hw_status;
6f535763
DM		 4691
4692 while (1) {
4693 work_done = tg3_poll_work(tp, work_done, budget);
4694
4695 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4696 goto tx_recovery;
4697
4698 if (unlikely(work_done >= budget))
4699 break;
4700
4fd7ab59
MC		 4701 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4702 /* tp->last_tag is used in tg3_restart_ints() below
4703 * to tell the hw how much work has been processed,
4704 * so we must read it before checking for more work.
4705 */
4706 tp->last_tag = sblk->status_tag;
624f8e50 4707 tp->last_irq_tag = tp->last_tag;
4fd7ab59
MC		 4708 rmb();
4709 } else
4710 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4711
4fd7ab59 4712 if (likely(!tg3_has_work(tp))) {
288379f0 4713 napi_complete(napi);
6f535763
DM		 4714 tg3_restart_ints(tp);
4715 break;
4716 }
1da177e4
LT		 4717 }
4718
bea3348e 4719 return work_done;
6f535763
DM		 4720
4721tx_recovery:
4fd7ab59 4722 /* work_done is guaranteed to be less than budget. */
288379f0 4723 napi_complete(napi);
6f535763 4724 schedule_work(&tp->reset_task);
4fd7ab59 4725 return work_done;
1da177e4
LT		 4726}
4727
f47c11ee
DM		 4728static void tg3_irq_quiesce(struct tg3 *tp)
4729{
4730 BUG_ON(tp->irq_sync);
4731
4732 tp->irq_sync = 1;
4733 smp_mb();
4734
4735 synchronize_irq(tp->pdev->irq);
4736}
4737
4738static inline int tg3_irq_sync(struct tg3 *tp)
4739{
4740 return tp->irq_sync;
4741}
4742
4743/* Fully shutdown all tg3 driver activity elsewhere in the system.
4744 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4745 * with as well. Most of the time, this is not necessary except when
4746 * shutting down the device.
4747 */
4748static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4749{
46966545 4750 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4751 if (irq_sync)
4752 tg3_irq_quiesce(tp);
f47c11ee
DM		 4753}
4754
4755static inline void tg3_full_unlock(struct tg3 *tp)
4756{
f47c11ee
DM		 4757 spin_unlock_bh(&tp->lock);
4758}
4759
fcfa0a32
MC		 4760/* One-shot MSI handler - Chip automatically disables interrupt
4761 * after sending MSI so driver doesn't have to do it.
4762 */
7d12e780 4763static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32
MC		 4764{
4765 struct net_device *dev = dev_id;
4766 struct tg3 *tp = netdev_priv(dev);
4767
4768 prefetch(tp->hw_status);
4769 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4770
4771 if (likely(!tg3_irq_sync(tp)))
288379f0 4772 napi_schedule(&tp->napi);
fcfa0a32
MC		 4773
4774 return IRQ_HANDLED;
4775}
4776
88b06bc2
MC		 4777/* MSI ISR - No need to check for interrupt sharing and no need to
4778 * flush status block and interrupt mailbox. PCI ordering rules
4779 * guarantee that MSI will arrive after the status block.
4780 */
7d12e780 4781static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2
MC		 4782{
4783 struct net_device *dev = dev_id;
4784 struct tg3 *tp = netdev_priv(dev);
88b06bc2 4785
61487480
MC		 4786 prefetch(tp->hw_status);
4787 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
88b06bc2 4788 /*
fac9b83e 4789 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4790 * chip-internal interrupt pending events.
fac9b83e 4791 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4792 * NIC to stop sending us irqs, engaging "in-intr-handler"
4793 * event coalescing.
4794 */
4795 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4796 if (likely(!tg3_irq_sync(tp)))
288379f0 4797 napi_schedule(&tp->napi);
61487480 4798
88b06bc2
MC		 4799 return IRQ_RETVAL(1);
4800}
4801
7d12e780 4802static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4
LT		 4803{
4804 struct net_device *dev = dev_id;
4805 struct tg3 *tp = netdev_priv(dev);
4806 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 4807 unsigned int handled = 1;
4808
1da177e4
LT		 4809 /* In INTx mode, it is possible for the interrupt to arrive at
4810 * the CPU before the status block posted prior to the interrupt.
4811 * Reading the PCI State register will confirm whether the
4812 * interrupt is ours and will flush the status block.
4813 */
d18edcb2
MC		 4814 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4815 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4816 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4817 handled = 0;
f47c11ee 4818 goto out;
fac9b83e 4819 }
d18edcb2
MC		 4820 }
4821
4822 /*
4823 * Writing any value to intr-mbox-0 clears PCI INTA# and
4824 * chip-internal interrupt pending events.
4825 * Writing non-zero to intr-mbox-0 additional tells the
4826 * NIC to stop sending us irqs, engaging "in-intr-handler"
4827 * event coalescing.
c04cb347
MC		 4828 *
4829 * Flush the mailbox to de-assert the IRQ immediately to prevent
4830 * spurious interrupts. The flush impacts performance but
4831 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4832 */
c04cb347 4833 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4834 if (tg3_irq_sync(tp))
4835 goto out;
4836 sblk->status &= ~SD_STATUS_UPDATED;
4837 if (likely(tg3_has_work(tp))) {
4838 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
288379f0 4839 napi_schedule(&tp->napi);
d18edcb2
MC		 4840 } else {
4841 /* No work, shared interrupt perhaps? re-enable
4842 * interrupts, and flush that PCI write
4843 */
4844 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4845 0x00000000);
fac9b83e 4846 }
f47c11ee 4847out:
fac9b83e
DM		 4848 return IRQ_RETVAL(handled);
4849}
4850
7d12e780 4851static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e
DM		 4852{
4853 struct net_device *dev = dev_id;
4854 struct tg3 *tp = netdev_priv(dev);
4855 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 4856 unsigned int handled = 1;
4857
fac9b83e
DM		 4858 /* In INTx mode, it is possible for the interrupt to arrive at
4859 * the CPU before the status block posted prior to the interrupt.
4860 * Reading the PCI State register will confirm whether the
4861 * interrupt is ours and will flush the status block.
4862 */
624f8e50 4863 if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
d18edcb2
MC		 4864 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4865 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4866 handled = 0;
f47c11ee 4867 goto out;
1da177e4 4868 }
d18edcb2
MC		 4869 }
4870
4871 /*
4872 * writing any value to intr-mbox-0 clears PCI INTA# and
4873 * chip-internal interrupt pending events.
4874 * writing non-zero to intr-mbox-0 additional tells the
4875 * NIC to stop sending us irqs, engaging "in-intr-handler"
4876 * event coalescing.
c04cb347
MC		 4877 *
4878 * Flush the mailbox to de-assert the IRQ immediately to prevent
4879 * spurious interrupts. The flush impacts performance but
4880 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4881 */
c04cb347 4882 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4883
4884 /*
4885 * In a shared interrupt configuration, sometimes other devices'
4886 * interrupts will scream. We record the current status tag here
4887 * so that the above check can report that the screaming interrupts
4888 * are unhandled. Eventually they will be silenced.
4889 */
4890 tp->last_irq_tag = sblk->status_tag;
4891
d18edcb2
MC		 4892 if (tg3_irq_sync(tp))
4893 goto out;
624f8e50
MC		 4894
4895 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4896
4897 napi_schedule(&tp->napi);
4898
f47c11ee 4899out:
1da177e4
LT		 4900 return IRQ_RETVAL(handled);
4901}
4902
7938109f 4903/* ISR for interrupt test */
7d12e780 4904static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f
MC		 4905{
4906 struct net_device *dev = dev_id;
4907 struct tg3 *tp = netdev_priv(dev);
4908 struct tg3_hw_status *sblk = tp->hw_status;
4909
f9804ddb
MC		 4910 if ((sblk->status & SD_STATUS_UPDATED) ||
4911 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4912 tg3_disable_ints(tp);
7938109f
MC		 4913 return IRQ_RETVAL(1);
4914 }
4915 return IRQ_RETVAL(0);
4916}
4917
8e7a22e3 4918static int tg3_init_hw(struct tg3 *, int);
944d980e 4919static int tg3_halt(struct tg3 *, int, int);
1da177e4 4920
b9ec6c1b
MC		 4921/* Restart hardware after configuration changes, self-test, etc.
4922 * Invoked with tp->lock held.
4923 */
4924static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4925 __releases(tp->lock)
4926 __acquires(tp->lock)
b9ec6c1b
MC		 4927{
4928 int err;
4929
4930 err = tg3_init_hw(tp, reset_phy);
4931 if (err) {
4932 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4933 "aborting.\n", tp->dev->name);
4934 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4935 tg3_full_unlock(tp);
4936 del_timer_sync(&tp->timer);
4937 tp->irq_sync = 0;
bea3348e 4938 napi_enable(&tp->napi);
b9ec6c1b
MC		 4939 dev_close(tp->dev);
4940 tg3_full_lock(tp, 0);
4941 }
4942 return err;
4943}
4944
1da177e4
LT		 4945#ifdef CONFIG_NET_POLL_CONTROLLER
4946static void tg3_poll_controller(struct net_device *dev)
4947{
88b06bc2
MC		 4948 struct tg3 *tp = netdev_priv(dev);
4949
7d12e780 4950 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4951}
4952#endif
4953
c4028958 4954static void tg3_reset_task(struct work_struct *work)
1da177e4 4955{
c4028958 4956 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4957 int err;
1da177e4
LT		 4958 unsigned int restart_timer;
4959
7faa006f 4960 tg3_full_lock(tp, 0);
7faa006f
MC		 4961
4962 if (!netif_running(tp->dev)) {
7faa006f
MC		 4963 tg3_full_unlock(tp);
4964 return;
4965 }
4966
4967 tg3_full_unlock(tp);
4968
b02fd9e3
MC		 4969 tg3_phy_stop(tp);
4970
1da177e4
LT		 4971 tg3_netif_stop(tp);
4972
f47c11ee 4973 tg3_full_lock(tp, 1);
1da177e4
LT		 4974
4975 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4976 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4977
df3e6548
MC		 4978 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4979 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4980 tp->write32_rx_mbox = tg3_write_flush_reg32;
4981 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4982 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4983 }
4984
944d980e 4985 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4986 err = tg3_init_hw(tp, 1);
4987 if (err)
b9ec6c1b 4988 goto out;
1da177e4
LT		 4989
4990 tg3_netif_start(tp);
4991
1da177e4
LT		 4992 if (restart_timer)
4993 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4994
b9ec6c1b 4995out:
7faa006f 4996 tg3_full_unlock(tp);
b02fd9e3
MC		 4997
4998 if (!err)
4999 tg3_phy_start(tp);
1da177e4
LT		 5000}
5001
b0408751
MC		 5002static void tg3_dump_short_state(struct tg3 *tp)
5003{
5004 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5005 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5006 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5007 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5008}
5009
1da177e4
LT		 5010static void tg3_tx_timeout(struct net_device *dev)
5011{
5012 struct tg3 *tp = netdev_priv(dev);
5013
b0408751 5014 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5015 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5016 dev->name);
b0408751
MC		 5017 tg3_dump_short_state(tp);
5018 }
1da177e4
LT		 5019
5020 schedule_work(&tp->reset_task);
5021}
5022
c58ec932
MC		 5023/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5024static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5025{
5026 u32 base = (u32) mapping & 0xffffffff;
5027
5028 return ((base > 0xffffdcc0) &&
5029 (base + len + 8 < base));
5030}
5031
72f2afb8
MC		 5032/* Test for DMA addresses > 40-bit */
5033static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5034 int len)
5035{
5036#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5037 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5038 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5039 return 0;
5040#else
5041 return 0;
5042#endif
5043}
5044
1da177e4
LT		 5045static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5046
72f2afb8
MC		 5047/* Workaround 4GB and 40-bit hardware DMA bugs. */
5048static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5049 u32 last_plus_one, u32 *start,
5050 u32 base_flags, u32 mss)
1da177e4 5051{
41588ba1 5052 struct sk_buff *new_skb;
c58ec932 5053 dma_addr_t new_addr = 0;
1da177e4 5054 u32 entry = *start;
c58ec932 5055 int i, ret = 0;
1da177e4 5056
41588ba1
MC		 5057 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5058 new_skb = skb_copy(skb, GFP_ATOMIC);
5059 else {
5060 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5061
5062 new_skb = skb_copy_expand(skb,
5063 skb_headroom(skb) + more_headroom,
5064 skb_tailroom(skb), GFP_ATOMIC);
5065 }
5066
1da177e4 5067 if (!new_skb) {
c58ec932
MC		 5068 ret = -1;
5069 } else {
5070 /* New SKB is guaranteed to be linear. */
5071 entry = *start;
90079ce8 5072 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5073 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5074
c58ec932
MC		 5075 /* Make sure new skb does not cross any 4G boundaries.
5076 * Drop the packet if it does.
5077 */
90079ce8 5078 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5079 if (!ret)
5080 skb_dma_unmap(&tp->pdev->dev, new_skb,
5081 DMA_TO_DEVICE);
c58ec932
MC		 5082 ret = -1;
5083 dev_kfree_skb(new_skb);
5084 new_skb = NULL;
5085 } else {
5086 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5087 base_flags, 1 | (mss << 1));
5088 *start = NEXT_TX(entry);
5089 }
1da177e4
LT		 5090 }
5091
1da177e4
LT		 5092 /* Now clean up the sw ring entries. */
5093 i = 0;
5094 while (entry != last_plus_one) {
1da177e4
LT		 5095 if (i == 0) {
5096 tp->tx_buffers[entry].skb = new_skb;
1da177e4
LT		 5097 } else {
5098 tp->tx_buffers[entry].skb = NULL;
5099 }
5100 entry = NEXT_TX(entry);
5101 i++;
5102 }
5103
90079ce8 5104 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5105 dev_kfree_skb(skb);
5106
c58ec932 5107 return ret;
1da177e4
LT		 5108}
5109
5110static void tg3_set_txd(struct tg3 *tp, int entry,
5111 dma_addr_t mapping, int len, u32 flags,
5112 u32 mss_and_is_end)
5113{
5114 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5115 int is_end = (mss_and_is_end & 0x1);
5116 u32 mss = (mss_and_is_end >> 1);
5117 u32 vlan_tag = 0;
5118
5119 if (is_end)
5120 flags |= TXD_FLAG_END;
5121 if (flags & TXD_FLAG_VLAN) {
5122 vlan_tag = flags >> 16;
5123 flags &= 0xffff;
5124 }
5125 vlan_tag |= (mss << TXD_MSS_SHIFT);
5126
5127 txd->addr_hi = ((u64) mapping >> 32);
5128 txd->addr_lo = ((u64) mapping & 0xffffffff);
5129 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5130 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5131}
5132
5a6f3074
MC		 5133/* hard_start_xmit for devices that don't have any bugs and
5134 * support TG3_FLG2_HW_TSO_2 only.
5135 */
1da177e4 5136static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5a6f3074
MC		 5137{
5138 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5139 u32 len, entry, base_flags, mss;
90079ce8
DM		 5140 struct skb_shared_info *sp;
5141 dma_addr_t mapping;
5a6f3074
MC		 5142
5143 len = skb_headlen(skb);
5144
00b70504 5145 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5146 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5147 * interrupt. Furthermore, IRQ processing runs lockless so we have
5148 * no IRQ context deadlocks to worry about either. Rejoice!
5149 */
1b2a7205 5150 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5151 if (!netif_queue_stopped(dev)) {
5152 netif_stop_queue(dev);
5153
5154 /* This is a hard error, log it. */
5155 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5156 "queue awake!\n", dev->name);
5157 }
5a6f3074
MC		 5158 return NETDEV_TX_BUSY;
5159 }
5160
5161 entry = tp->tx_prod;
5162 base_flags = 0;
5a6f3074 5163 mss = 0;
c13e3713 5164 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5165 int tcp_opt_len, ip_tcp_len;
5166
5167 if (skb_header_cloned(skb) &&
5168 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5169 dev_kfree_skb(skb);
5170 goto out_unlock;
5171 }
5172
b0026624
MC		 5173 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5174 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5175 else {
eddc9ec5
ACM		 5176 struct iphdr *iph = ip_hdr(skb);
5177
ab6a5bb6 5178 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5179 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5180
eddc9ec5
ACM		 5181 iph->check = 0;
5182 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5183 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5184 }
5a6f3074
MC		 5185
5186 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5187 TXD_FLAG_CPU_POST_DMA);
5188
aa8223c7 5189 tcp_hdr(skb)->check = 0;
5a6f3074 5190
5a6f3074 5191 }
84fa7933 5192 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5193 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5194#if TG3_VLAN_TAG_USED
5195 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5196 base_flags |= (TXD_FLAG_VLAN |
5197 (vlan_tx_tag_get(skb) << 16));
5198#endif
5199
90079ce8
DM		 5200 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5201 dev_kfree_skb(skb);
5202 goto out_unlock;
5203 }
5204
5205 sp = skb_shinfo(skb);
5206
042a53a9 5207 mapping = sp->dma_head;
5a6f3074
MC		 5208
5209 tp->tx_buffers[entry].skb = skb;
5a6f3074
MC		 5210
5211 tg3_set_txd(tp, entry, mapping, len, base_flags,
5212 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5213
5214 entry = NEXT_TX(entry);
5215
5216 /* Now loop through additional data fragments, and queue them. */
5217 if (skb_shinfo(skb)->nr_frags > 0) {
5218 unsigned int i, last;
5219
5220 last = skb_shinfo(skb)->nr_frags - 1;
5221 for (i = 0; i <= last; i++) {
5222 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5223
5224 len = frag->size;
042a53a9 5225 mapping = sp->dma_maps[i];
5a6f3074 5226 tp->tx_buffers[entry].skb = NULL;
5a6f3074
MC		 5227
5228 tg3_set_txd(tp, entry, mapping, len,
5229 base_flags, (i == last) | (mss << 1));
5230
5231 entry = NEXT_TX(entry);
5232 }
5233 }
5234
5235 /* Packets are ready, update Tx producer idx local and on card. */
5236 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5237
5238 tp->tx_prod = entry;
1b2a7205 5239 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5240 netif_stop_queue(dev);
42952231 5241 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5a6f3074
MC		 5242 netif_wake_queue(tp->dev);
5243 }
5244
5245out_unlock:
cdd0db05 5246 mmiowb();
5a6f3074
MC		 5247
5248 return NETDEV_TX_OK;
5249}
5250
52c0fd83
MC		 5251static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5252
5253/* Use GSO to workaround a rare TSO bug that may be triggered when the
5254 * TSO header is greater than 80 bytes.
5255 */
5256static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5257{
5258 struct sk_buff *segs, *nskb;
5259
5260 /* Estimate the number of fragments in the worst case */
1b2a7205 5261 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
52c0fd83 5262 netif_stop_queue(tp->dev);
7f62ad5d
MC		 5263 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5264 return NETDEV_TX_BUSY;
5265
5266 netif_wake_queue(tp->dev);
52c0fd83
MC		 5267 }
5268
5269 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5270 if (IS_ERR(segs))
52c0fd83
MC		 5271 goto tg3_tso_bug_end;
5272
5273 do {
5274 nskb = segs;
5275 segs = segs->next;
5276 nskb->next = NULL;
5277 tg3_start_xmit_dma_bug(nskb, tp->dev);
5278 } while (segs);
5279
5280tg3_tso_bug_end:
5281 dev_kfree_skb(skb);
5282
5283 return NETDEV_TX_OK;
5284}
52c0fd83 5285
5a6f3074
MC		 5286/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5287 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5288 */
5289static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 5290{
5291 struct tg3 *tp = netdev_priv(dev);
1da177e4 5292 u32 len, entry, base_flags, mss;
90079ce8 5293 struct skb_shared_info *sp;
1da177e4 5294 int would_hit_hwbug;
90079ce8 5295 dma_addr_t mapping;
1da177e4
LT		 5296
5297 len = skb_headlen(skb);
5298
00b70504 5299 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5300 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5301 * interrupt. Furthermore, IRQ processing runs lockless so we have
5302 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5303 */
1b2a7205 5304 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5305 if (!netif_queue_stopped(dev)) {
5306 netif_stop_queue(dev);
5307
5308 /* This is a hard error, log it. */
5309 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5310 "queue awake!\n", dev->name);
5311 }
1da177e4
LT		 5312 return NETDEV_TX_BUSY;
5313 }
5314
5315 entry = tp->tx_prod;
5316 base_flags = 0;
84fa7933 5317 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5318 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5319 mss = 0;
c13e3713 5320 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5321 struct iphdr *iph;
52c0fd83 5322 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5323
5324 if (skb_header_cloned(skb) &&
5325 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5326 dev_kfree_skb(skb);
5327 goto out_unlock;
5328 }
5329
ab6a5bb6 5330 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5331 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5332
52c0fd83
MC		 5333 hdr_len = ip_tcp_len + tcp_opt_len;
5334 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5335 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5336 return (tg3_tso_bug(tp, skb));
5337
1da177e4
LT		 5338 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5339 TXD_FLAG_CPU_POST_DMA);
5340
eddc9ec5
ACM		 5341 iph = ip_hdr(skb);
5342 iph->check = 0;
5343 iph->tot_len = htons(mss + hdr_len);
1da177e4 5344 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5345 tcp_hdr(skb)->check = 0;
1da177e4 5346 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5347 } else
5348 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5349 iph->daddr, 0,
5350 IPPROTO_TCP,
5351 0);
1da177e4
LT		 5352
5353 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5354 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5355 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5356 int tsflags;
5357
eddc9ec5 5358 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5359 mss |= (tsflags << 11);
5360 }
5361 } else {
eddc9ec5 5362 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5363 int tsflags;
5364
eddc9ec5 5365 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5366 base_flags |= tsflags << 12;
5367 }
5368 }
5369 }
1da177e4
LT		 5370#if TG3_VLAN_TAG_USED
5371 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5372 base_flags |= (TXD_FLAG_VLAN |
5373 (vlan_tx_tag_get(skb) << 16));
5374#endif
5375
90079ce8
DM		 5376 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5377 dev_kfree_skb(skb);
5378 goto out_unlock;
5379 }
5380
5381 sp = skb_shinfo(skb);
5382
042a53a9 5383 mapping = sp->dma_head;
1da177e4
LT		 5384
5385 tp->tx_buffers[entry].skb = skb;
1da177e4
LT		 5386
5387 would_hit_hwbug = 0;
5388
41588ba1
MC		 5389 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5390 would_hit_hwbug = 1;
5391 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5392 would_hit_hwbug = 1;
1da177e4
LT		 5393
5394 tg3_set_txd(tp, entry, mapping, len, base_flags,
5395 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5396
5397 entry = NEXT_TX(entry);
5398
5399 /* Now loop through additional data fragments, and queue them. */
5400 if (skb_shinfo(skb)->nr_frags > 0) {
5401 unsigned int i, last;
5402
5403 last = skb_shinfo(skb)->nr_frags - 1;
5404 for (i = 0; i <= last; i++) {
5405 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5406
5407 len = frag->size;
042a53a9 5408 mapping = sp->dma_maps[i];
1da177e4
LT		 5409
5410 tp->tx_buffers[entry].skb = NULL;
1da177e4 5411
c58ec932
MC		 5412 if (tg3_4g_overflow_test(mapping, len))
5413 would_hit_hwbug = 1;
1da177e4 5414
72f2afb8
MC		 5415 if (tg3_40bit_overflow_test(tp, mapping, len))
5416 would_hit_hwbug = 1;
5417
1da177e4
LT		 5418 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5419 tg3_set_txd(tp, entry, mapping, len,
5420 base_flags, (i == last)|(mss << 1));
5421 else
5422 tg3_set_txd(tp, entry, mapping, len,
5423 base_flags, (i == last));
5424
5425 entry = NEXT_TX(entry);
5426 }
5427 }
5428
5429 if (would_hit_hwbug) {
5430 u32 last_plus_one = entry;
5431 u32 start;
1da177e4 5432
c58ec932
MC		 5433 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5434 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5435
5436 /* If the workaround fails due to memory/mapping
5437 * failure, silently drop this packet.
5438 */
72f2afb8 5439 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5440 &start, base_flags, mss))
1da177e4
LT		 5441 goto out_unlock;
5442
5443 entry = start;
5444 }
5445
5446 /* Packets are ready, update Tx producer idx local and on card. */
5447 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5448
5449 tp->tx_prod = entry;
1b2a7205 5450 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5451 netif_stop_queue(dev);
42952231 5452 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
51b91468
MC		 5453 netif_wake_queue(tp->dev);
5454 }
1da177e4
LT		 5455
5456out_unlock:
cdd0db05 5457 mmiowb();
1da177e4
LT		 5458
5459 return NETDEV_TX_OK;
5460}
5461
5462static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5463 int new_mtu)
5464{
5465 dev->mtu = new_mtu;
5466
ef7f5ec0 5467 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5468 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5469 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5470 ethtool_op_set_tso(dev, 0);
5471 }
5472 else
5473 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5474 } else {
a4e2b347 5475 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5476 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5477 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5478 }
1da177e4
LT		 5479}
5480
5481static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5482{
5483 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5484 int err;
1da177e4
LT		 5485
5486 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5487 return -EINVAL;
5488
5489 if (!netif_running(dev)) {
5490 /* We'll just catch it later when the
5491 * device is up'd.
5492 */
5493 tg3_set_mtu(dev, tp, new_mtu);
5494 return 0;
5495 }
5496
b02fd9e3
MC		 5497 tg3_phy_stop(tp);
5498
1da177e4 5499 tg3_netif_stop(tp);
f47c11ee
DM		 5500
5501 tg3_full_lock(tp, 1);
1da177e4 5502
944d980e 5503 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5504
5505 tg3_set_mtu(dev, tp, new_mtu);
5506
b9ec6c1b 5507 err = tg3_restart_hw(tp, 0);
1da177e4 5508
b9ec6c1b
MC		 5509 if (!err)
5510 tg3_netif_start(tp);
1da177e4 5511
f47c11ee 5512 tg3_full_unlock(tp);
1da177e4 5513
b02fd9e3
MC		 5514 if (!err)
5515 tg3_phy_start(tp);
5516
b9ec6c1b 5517 return err;
1da177e4
LT		 5518}
5519
5520/* Free up pending packets in all rx/tx rings.
5521 *
5522 * The chip has been shut down and the driver detached from
5523 * the networking, so no interrupts or new tx packets will
5524 * end up in the driver. tp->{tx,}lock is not held and we are not
5525 * in an interrupt context and thus may sleep.
5526 */
5527static void tg3_free_rings(struct tg3 *tp)
5528{
5529 struct ring_info *rxp;
5530 int i;
5531
5532 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5533 rxp = &tp->rx_std_buffers[i];
5534
5535 if (rxp->skb == NULL)
5536 continue;
5537 pci_unmap_single(tp->pdev,
5538 pci_unmap_addr(rxp, mapping),
287be12e 5539 tp->rx_pkt_map_sz,
1da177e4
LT		 5540 PCI_DMA_FROMDEVICE);
5541 dev_kfree_skb_any(rxp->skb);
5542 rxp->skb = NULL;
5543 }
5544
5545 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5546 rxp = &tp->rx_jumbo_buffers[i];
5547
5548 if (rxp->skb == NULL)
5549 continue;
5550 pci_unmap_single(tp->pdev,
5551 pci_unmap_addr(rxp, mapping),
287be12e 5552 TG3_RX_JMB_MAP_SZ,
1da177e4
LT		 5553 PCI_DMA_FROMDEVICE);
5554 dev_kfree_skb_any(rxp->skb);
5555 rxp->skb = NULL;
5556 }
5557
5558 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5559 struct tx_ring_info *txp;
5560 struct sk_buff *skb;
1da177e4
LT		 5561
5562 txp = &tp->tx_buffers[i];
5563 skb = txp->skb;
5564
5565 if (skb == NULL) {
5566 i++;
5567 continue;
5568 }
5569
90079ce8 5570 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4 5571
90079ce8 5572 txp->skb = NULL;
1da177e4 5573
90079ce8 5574 i += skb_shinfo(skb)->nr_frags + 1;
1da177e4
LT		 5575
5576 dev_kfree_skb_any(skb);
5577 }
5578}
5579
5580/* Initialize tx/rx rings for packet processing.
5581 *
5582 * The chip has been shut down and the driver detached from
5583 * the networking, so no interrupts or new tx packets will
5584 * end up in the driver. tp->{tx,}lock are held and thus
5585 * we may not sleep.
5586 */
32d8c572 5587static int tg3_init_rings(struct tg3 *tp)
1da177e4 5588{
287be12e 5589 u32 i, rx_pkt_dma_sz;
1da177e4
LT		 5590
5591 /* Free up all the SKBs. */
5592 tg3_free_rings(tp);
5593
5594 /* Zero out all descriptors. */
5595 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5596 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5597 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5598 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5599
287be12e 5600 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5601 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5602 tp->dev->mtu > ETH_DATA_LEN)
5603 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5604 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5605
1da177e4
LT		 5606 /* Initialize invariants of the rings, we only set this
5607 * stuff once. This works because the card does not
5608 * write into the rx buffer posting rings.
5609 */
5610 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5611 struct tg3_rx_buffer_desc *rxd;
5612
5613 rxd = &tp->rx_std[i];
287be12e 5614 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5615 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5616 rxd->opaque = (RXD_OPAQUE_RING_STD |
5617 (i << RXD_OPAQUE_INDEX_SHIFT));
5618 }
5619
0f893dc6 5620 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5621 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5622 struct tg3_rx_buffer_desc *rxd;
5623
5624 rxd = &tp->rx_jumbo[i];
287be12e 5625 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
1da177e4
LT		 5626 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5627 RXD_FLAG_JUMBO;
5628 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5629 (i << RXD_OPAQUE_INDEX_SHIFT));
5630 }
5631 }
5632
5633 /* Now allocate fresh SKBs for each rx ring. */
5634 for (i = 0; i < tp->rx_pending; i++) {
32d8c572
MC		 5635 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5636 printk(KERN_WARNING PFX
5637 "%s: Using a smaller RX standard ring, "
5638 "only %d out of %d buffers were allocated "
5639 "successfully.\n",
5640 tp->dev->name, i, tp->rx_pending);
5641 if (i == 0)
5642 return -ENOMEM;
5643 tp->rx_pending = i;
1da177e4 5644 break;
32d8c572 5645 }
1da177e4
LT		 5646 }
5647
0f893dc6 5648 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5649 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5650 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5651 -1, i) < 0) {
5652 printk(KERN_WARNING PFX
5653 "%s: Using a smaller RX jumbo ring, "
5654 "only %d out of %d buffers were "
5655 "allocated successfully.\n",
5656 tp->dev->name, i, tp->rx_jumbo_pending);
5657 if (i == 0) {
5658 tg3_free_rings(tp);
5659 return -ENOMEM;
5660 }
5661 tp->rx_jumbo_pending = i;
1da177e4 5662 break;
32d8c572 5663 }
1da177e4
LT		 5664 }
5665 }
32d8c572 5666 return 0;
1da177e4
LT		 5667}
5668
5669/*
5670 * Must not be invoked with interrupt sources disabled and
5671 * the hardware shutdown down.
5672 */
5673static void tg3_free_consistent(struct tg3 *tp)
5674{
b4558ea9
JJ		 5675 kfree(tp->rx_std_buffers);
5676 tp->rx_std_buffers = NULL;
1da177e4
LT		 5677 if (tp->rx_std) {
5678 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5679 tp->rx_std, tp->rx_std_mapping);
5680 tp->rx_std = NULL;
5681 }
5682 if (tp->rx_jumbo) {
5683 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5684 tp->rx_jumbo, tp->rx_jumbo_mapping);
5685 tp->rx_jumbo = NULL;
5686 }
5687 if (tp->rx_rcb) {
5688 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5689 tp->rx_rcb, tp->rx_rcb_mapping);
5690 tp->rx_rcb = NULL;
5691 }
5692 if (tp->tx_ring) {
5693 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5694 tp->tx_ring, tp->tx_desc_mapping);
5695 tp->tx_ring = NULL;
5696 }
5697 if (tp->hw_status) {
5698 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5699 tp->hw_status, tp->status_mapping);
5700 tp->hw_status = NULL;
5701 }
5702 if (tp->hw_stats) {
5703 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5704 tp->hw_stats, tp->stats_mapping);
5705 tp->hw_stats = NULL;
5706 }
5707}
5708
5709/*
5710 * Must not be invoked with interrupt sources disabled and
5711 * the hardware shutdown down. Can sleep.
5712 */
5713static int tg3_alloc_consistent(struct tg3 *tp)
5714{
bd2b3343 5715 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
1da177e4
LT		 5716 (TG3_RX_RING_SIZE +
5717 TG3_RX_JUMBO_RING_SIZE)) +
5718 (sizeof(struct tx_ring_info) *
5719 TG3_TX_RING_SIZE),
5720 GFP_KERNEL);
5721 if (!tp->rx_std_buffers)
5722 return -ENOMEM;
5723
1da177e4
LT		 5724 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5725 tp->tx_buffers = (struct tx_ring_info *)
5726 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5727
5728 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5729 &tp->rx_std_mapping);
5730 if (!tp->rx_std)
5731 goto err_out;
5732
5733 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5734 &tp->rx_jumbo_mapping);
5735
5736 if (!tp->rx_jumbo)
5737 goto err_out;
5738
5739 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5740 &tp->rx_rcb_mapping);
5741 if (!tp->rx_rcb)
5742 goto err_out;
5743
5744 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5745 &tp->tx_desc_mapping);
5746 if (!tp->tx_ring)
5747 goto err_out;
5748
5749 tp->hw_status = pci_alloc_consistent(tp->pdev,
5750 TG3_HW_STATUS_SIZE,
5751 &tp->status_mapping);
5752 if (!tp->hw_status)
5753 goto err_out;
5754
5755 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5756 sizeof(struct tg3_hw_stats),
5757 &tp->stats_mapping);
5758 if (!tp->hw_stats)
5759 goto err_out;
5760
5761 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5762 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5763
5764 return 0;
5765
5766err_out:
5767 tg3_free_consistent(tp);
5768 return -ENOMEM;
5769}
5770
5771#define MAX_WAIT_CNT 1000
5772
5773/* To stop a block, clear the enable bit and poll till it
5774 * clears. tp->lock is held.
5775 */
b3b7d6be 5776static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5777{
5778 unsigned int i;
5779 u32 val;
5780
5781 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5782 switch (ofs) {
5783 case RCVLSC_MODE:
5784 case DMAC_MODE:
5785 case MBFREE_MODE:
5786 case BUFMGR_MODE:
5787 case MEMARB_MODE:
5788 /* We can't enable/disable these bits of the
5789 * 5705/5750, just say success.
5790 */
5791 return 0;
5792
5793 default:
5794 break;
855e1111 5795 }
1da177e4
LT		 5796 }
5797
5798 val = tr32(ofs);
5799 val &= ~enable_bit;
5800 tw32_f(ofs, val);
5801
5802 for (i = 0; i < MAX_WAIT_CNT; i++) {
5803 udelay(100);
5804 val = tr32(ofs);
5805 if ((val & enable_bit) == 0)
5806 break;
5807 }
5808
b3b7d6be 5809 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5810 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5811 "ofs=%lx enable_bit=%x\n",
5812 ofs, enable_bit);
5813 return -ENODEV;
5814 }
5815
5816 return 0;
5817}
5818
5819/* tp->lock is held. */
b3b7d6be 5820static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5821{
5822 int i, err;
5823
5824 tg3_disable_ints(tp);
5825
5826 tp->rx_mode &= ~RX_MODE_ENABLE;
5827 tw32_f(MAC_RX_MODE, tp->rx_mode);
5828 udelay(10);
5829
b3b7d6be
DM		 5830 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5831 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5832 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5833 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5834 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5835 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5836
5837 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5838 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5839 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5840 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5841 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5842 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5843 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5844
5845 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5846 tw32_f(MAC_MODE, tp->mac_mode);
5847 udelay(40);
5848
5849 tp->tx_mode &= ~TX_MODE_ENABLE;
5850 tw32_f(MAC_TX_MODE, tp->tx_mode);
5851
5852 for (i = 0; i < MAX_WAIT_CNT; i++) {
5853 udelay(100);
5854 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5855 break;
5856 }
5857 if (i >= MAX_WAIT_CNT) {
5858 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5859 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5860 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5861 err |= -ENODEV;
1da177e4
LT		 5862 }
5863
e6de8ad1 5864 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5865 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5866 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5867
5868 tw32(FTQ_RESET, 0xffffffff);
5869 tw32(FTQ_RESET, 0x00000000);
5870
b3b7d6be
DM		 5871 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5872 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 5873
5874 if (tp->hw_status)
5875 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5876 if (tp->hw_stats)
5877 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5878
1da177e4
LT		 5879 return err;
5880}
5881
0d3031d9
MC		 5882static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5883{
5884 int i;
5885 u32 apedata;
5886
5887 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5888 if (apedata != APE_SEG_SIG_MAGIC)
5889 return;
5890
5891 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5892 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5893 return;
5894
5895 /* Wait for up to 1 millisecond for APE to service previous event. */
5896 for (i = 0; i < 10; i++) {
5897 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5898 return;
5899
5900 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5901
5902 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5903 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5904 event | APE_EVENT_STATUS_EVENT_PENDING);
5905
5906 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5907
5908 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5909 break;
5910
5911 udelay(100);
5912 }
5913
5914 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5915 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5916}
5917
5918static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5919{
5920 u32 event;
5921 u32 apedata;
5922
5923 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5924 return;
5925
5926 switch (kind) {
5927 case RESET_KIND_INIT:
5928 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5929 APE_HOST_SEG_SIG_MAGIC);
5930 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5931 APE_HOST_SEG_LEN_MAGIC);
5932 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5933 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5934 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5935 APE_HOST_DRIVER_ID_MAGIC);
5936 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5937 APE_HOST_BEHAV_NO_PHYLOCK);
5938
5939 event = APE_EVENT_STATUS_STATE_START;
5940 break;
5941 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 5942 /* With the interface we are currently using,
5943 * APE does not track driver state. Wiping
5944 * out the HOST SEGMENT SIGNATURE forces
5945 * the APE to assume OS absent status.
5946 */
5947 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5948
0d3031d9
MC		 5949 event = APE_EVENT_STATUS_STATE_UNLOAD;
5950 break;
5951 case RESET_KIND_SUSPEND:
5952 event = APE_EVENT_STATUS_STATE_SUSPEND;
5953 break;
5954 default:
5955 return;
5956 }
5957
5958 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5959
5960 tg3_ape_send_event(tp, event);
5961}
5962
1da177e4
LT		 5963/* tp->lock is held. */
5964static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5965{
f49639e6
DM		 5966 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5967 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 5968
5969 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5970 switch (kind) {
5971 case RESET_KIND_INIT:
5972 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5973 DRV_STATE_START);
5974 break;
5975
5976 case RESET_KIND_SHUTDOWN:
5977 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5978 DRV_STATE_UNLOAD);
5979 break;
5980
5981 case RESET_KIND_SUSPEND:
5982 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5983 DRV_STATE_SUSPEND);
5984 break;
5985
5986 default:
5987 break;
855e1111 5988 }
1da177e4 5989 }
0d3031d9
MC		 5990
5991 if (kind == RESET_KIND_INIT ||
5992 kind == RESET_KIND_SUSPEND)
5993 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 5994}
5995
5996/* tp->lock is held. */
5997static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5998{
5999 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6000 switch (kind) {
6001 case RESET_KIND_INIT:
6002 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6003 DRV_STATE_START_DONE);
6004 break;
6005
6006 case RESET_KIND_SHUTDOWN:
6007 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6008 DRV_STATE_UNLOAD_DONE);
6009 break;
6010
6011 default:
6012 break;
855e1111 6013 }
1da177e4 6014 }
0d3031d9
MC		 6015
6016 if (kind == RESET_KIND_SHUTDOWN)
6017 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6018}
6019
6020/* tp->lock is held. */
6021static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6022{
6023 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6024 switch (kind) {
6025 case RESET_KIND_INIT:
6026 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6027 DRV_STATE_START);
6028 break;
6029
6030 case RESET_KIND_SHUTDOWN:
6031 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6032 DRV_STATE_UNLOAD);
6033 break;
6034
6035 case RESET_KIND_SUSPEND:
6036 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6037 DRV_STATE_SUSPEND);
6038 break;
6039
6040 default:
6041 break;
855e1111 6042 }
1da177e4
LT		 6043 }
6044}
6045
7a6f4369
MC		 6046static int tg3_poll_fw(struct tg3 *tp)
6047{
6048 int i;
6049 u32 val;
6050
b5d3772c 6051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6052 /* Wait up to 20ms for init done. */
6053 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6054 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6055 return 0;
0ccead18 6056 udelay(100);
b5d3772c
MC		 6057 }
6058 return -ENODEV;
6059 }
6060
7a6f4369
MC		 6061 /* Wait for firmware initialization to complete. */
6062 for (i = 0; i < 100000; i++) {
6063 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6064 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6065 break;
6066 udelay(10);
6067 }
6068
6069 /* Chip might not be fitted with firmware. Some Sun onboard
6070 * parts are configured like that. So don't signal the timeout
6071 * of the above loop as an error, but do report the lack of
6072 * running firmware once.
6073 */
6074 if (i >= 100000 &&
6075 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6076 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6077
6078 printk(KERN_INFO PFX "%s: No firmware running.\n",
6079 tp->dev->name);
6080 }
6081
6082 return 0;
6083}
6084
ee6a99b5
MC		 6085/* Save PCI command register before chip reset */
6086static void tg3_save_pci_state(struct tg3 *tp)
6087{
8a6eac90 6088 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6089}
6090
6091/* Restore PCI state after chip reset */
6092static void tg3_restore_pci_state(struct tg3 *tp)
6093{
6094 u32 val;
6095
6096 /* Re-enable indirect register accesses. */
6097 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6098 tp->misc_host_ctrl);
6099
6100 /* Set MAX PCI retry to zero. */
6101 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6102 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6103 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6104 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6105 /* Allow reads and writes to the APE register and memory space. */
6106 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6107 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6108 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6109 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6110
8a6eac90 6111 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6112
fcb389df
MC		 6113 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6114 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6115 pcie_set_readrq(tp->pdev, 4096);
6116 else {
6117 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6118 tp->pci_cacheline_sz);
6119 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6120 tp->pci_lat_timer);
6121 }
114342f2 6122 }
5f5c51e3 6123
ee6a99b5 6124 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6125 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6126 u16 pcix_cmd;
6127
6128 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6129 &pcix_cmd);
6130 pcix_cmd &= ~PCI_X_CMD_ERO;
6131 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6132 pcix_cmd);
6133 }
ee6a99b5
MC		 6134
6135 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6136
6137 /* Chip reset on 5780 will reset MSI enable bit,
6138 * so need to restore it.
6139 */
6140 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6141 u16 ctrl;
6142
6143 pci_read_config_word(tp->pdev,
6144 tp->msi_cap + PCI_MSI_FLAGS,
6145 &ctrl);
6146 pci_write_config_word(tp->pdev,
6147 tp->msi_cap + PCI_MSI_FLAGS,
6148 ctrl | PCI_MSI_FLAGS_ENABLE);
6149 val = tr32(MSGINT_MODE);
6150 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6151 }
6152 }
6153}
6154
1da177e4
LT		 6155static void tg3_stop_fw(struct tg3 *);
6156
6157/* tp->lock is held. */
6158static int tg3_chip_reset(struct tg3 *tp)
6159{
6160 u32 val;
1ee582d8 6161 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6162 int err;
1da177e4 6163
f49639e6
DM		 6164 tg3_nvram_lock(tp);
6165
158d7abd
MC		 6166 tg3_mdio_stop(tp);
6167
77b483f1
MC		 6168 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6169
f49639e6
DM		 6170 /* No matching tg3_nvram_unlock() after this because
6171 * chip reset below will undo the nvram lock.
6172 */
6173 tp->nvram_lock_cnt = 0;
1da177e4 6174
ee6a99b5
MC		 6175 /* GRC_MISC_CFG core clock reset will clear the memory
6176 * enable bit in PCI register 4 and the MSI enable bit
6177 * on some chips, so we save relevant registers here.
6178 */
6179 tg3_save_pci_state(tp);
6180
d9ab5ad1 6181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6182 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6183 tw32(GRC_FASTBOOT_PC, 0);
6184
1da177e4
LT		 6185 /*
6186 * We must avoid the readl() that normally takes place.
6187 * It locks machines, causes machine checks, and other
6188 * fun things. So, temporarily disable the 5701
6189 * hardware workaround, while we do the reset.
6190 */
1ee582d8
MC		 6191 write_op = tp->write32;
6192 if (write_op == tg3_write_flush_reg32)
6193 tp->write32 = tg3_write32;
1da177e4 6194
d18edcb2
MC		 6195 /* Prevent the irq handler from reading or writing PCI registers
6196 * during chip reset when the memory enable bit in the PCI command
6197 * register may be cleared. The chip does not generate interrupt
6198 * at this time, but the irq handler may still be called due to irq
6199 * sharing or irqpoll.
6200 */
6201 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
b8fa2f3a
MC		 6202 if (tp->hw_status) {
6203 tp->hw_status->status = 0;
6204 tp->hw_status->status_tag = 0;
6205 }
d18edcb2 6206 tp->last_tag = 0;
624f8e50 6207 tp->last_irq_tag = 0;
d18edcb2
MC		 6208 smp_mb();
6209 synchronize_irq(tp->pdev->irq);
6210
255ca311
MC		 6211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6212 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6213 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6214 }
6215
1da177e4
LT		 6216 /* do the reset */
6217 val = GRC_MISC_CFG_CORECLK_RESET;
6218
6219 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6220 if (tr32(0x7e2c) == 0x60) {
6221 tw32(0x7e2c, 0x20);
6222 }
6223 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6224 tw32(GRC_MISC_CFG, (1 << 29));
6225 val |= (1 << 29);
6226 }
6227 }
6228
b5d3772c
MC		 6229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6230 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6231 tw32(GRC_VCPU_EXT_CTRL,
6232 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6233 }
6234
1da177e4
LT		 6235 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6236 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6237 tw32(GRC_MISC_CFG, val);
6238
1ee582d8
MC		 6239 /* restore 5701 hardware bug workaround write method */
6240 tp->write32 = write_op;
1da177e4
LT		 6241
6242 /* Unfortunately, we have to delay before the PCI read back.
6243 * Some 575X chips even will not respond to a PCI cfg access
6244 * when the reset command is given to the chip.
6245 *
6246 * How do these hardware designers expect things to work
6247 * properly if the PCI write is posted for a long period
6248 * of time? It is always necessary to have some method by
6249 * which a register read back can occur to push the write
6250 * out which does the reset.
6251 *
6252 * For most tg3 variants the trick below was working.
6253 * Ho hum...
6254 */
6255 udelay(120);
6256
6257 /* Flush PCI posted writes. The normal MMIO registers
6258 * are inaccessible at this time so this is the only
6259 * way to make this reliably (actually, this is no longer
6260 * the case, see above). I tried to use indirect
6261 * register read/write but this upset some 5701 variants.
6262 */
6263 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6264
6265 udelay(120);
6266
5e7dfd0f 6267 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6268 u16 val16;
6269
1da177e4
LT		 6270 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6271 int i;
6272 u32 cfg_val;
6273
6274 /* Wait for link training to complete. */
6275 for (i = 0; i < 5000; i++)
6276 udelay(100);
6277
6278 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6279 pci_write_config_dword(tp->pdev, 0xc4,
6280 cfg_val | (1 << 15));
6281 }
5e7dfd0f 6282
e7126997
MC		 6283 /* Clear the "no snoop" and "relaxed ordering" bits. */
6284 pci_read_config_word(tp->pdev,
6285 tp->pcie_cap + PCI_EXP_DEVCTL,
6286 &val16);
6287 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6288 PCI_EXP_DEVCTL_NOSNOOP_EN);
6289 /*
6290 * Older PCIe devices only support the 128 byte
6291 * MPS setting. Enforce the restriction.
5e7dfd0f 6292 */
e7126997
MC		 6293 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6294 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6295 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6296 pci_write_config_word(tp->pdev,
6297 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6298 val16);
5e7dfd0f
MC		 6299
6300 pcie_set_readrq(tp->pdev, 4096);
6301
6302 /* Clear error status */
6303 pci_write_config_word(tp->pdev,
6304 tp->pcie_cap + PCI_EXP_DEVSTA,
6305 PCI_EXP_DEVSTA_CED |
6306 PCI_EXP_DEVSTA_NFED |
6307 PCI_EXP_DEVSTA_FED |
6308 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6309 }
6310
ee6a99b5 6311 tg3_restore_pci_state(tp);
1da177e4 6312
d18edcb2
MC		 6313 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6314
ee6a99b5
MC		 6315 val = 0;
6316 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6317 val = tr32(MEMARB_MODE);
ee6a99b5 6318 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6319
6320 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6321 tg3_stop_fw(tp);
6322 tw32(0x5000, 0x400);
6323 }
6324
6325 tw32(GRC_MODE, tp->grc_mode);
6326
6327 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6328 val = tr32(0xc4);
1da177e4
LT		 6329
6330 tw32(0xc4, val | (1 << 15));
6331 }
6332
6333 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6334 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6335 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6336 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6337 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6338 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6339 }
6340
6341 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6342 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6343 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6344 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6345 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6346 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6347 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6348 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6349 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6350 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6351 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6352 } else
6353 tw32_f(MAC_MODE, 0);
6354 udelay(40);
6355
77b483f1
MC		 6356 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6357
7a6f4369
MC		 6358 err = tg3_poll_fw(tp);
6359 if (err)
6360 return err;
1da177e4 6361
0a9140cf
MC		 6362 tg3_mdio_start(tp);
6363
1da177e4
LT		 6364 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6365 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6366 val = tr32(0x7c00);
1da177e4
LT		 6367
6368 tw32(0x7c00, val | (1 << 25));
6369 }
6370
6371 /* Reprobe ASF enable state. */
6372 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6373 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6374 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6375 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6376 u32 nic_cfg;
6377
6378 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6379 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6380 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6381 tp->last_event_jiffies = jiffies;
cbf46853 6382 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6383 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6384 }
6385 }
6386
6387 return 0;
6388}
6389
6390/* tp->lock is held. */
6391static void tg3_stop_fw(struct tg3 *tp)
6392{
0d3031d9
MC		 6393 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6394 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6395 /* Wait for RX cpu to ACK the previous event. */
6396 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6397
6398 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6399
6400 tg3_generate_fw_event(tp);
1da177e4 6401
7c5026aa
MC		 6402 /* Wait for RX cpu to ACK this event. */
6403 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6404 }
6405}
6406
6407/* tp->lock is held. */
944d980e 6408static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6409{
6410 int err;
6411
6412 tg3_stop_fw(tp);
6413
944d980e 6414 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6415
b3b7d6be 6416 tg3_abort_hw(tp, silent);
1da177e4
LT		 6417 err = tg3_chip_reset(tp);
6418
daba2a63
MC		 6419 __tg3_set_mac_addr(tp, 0);
6420
944d980e
MC		 6421 tg3_write_sig_legacy(tp, kind);
6422 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6423
6424 if (err)
6425 return err;
6426
6427 return 0;
6428}
6429
1da177e4
LT		 6430#define RX_CPU_SCRATCH_BASE 0x30000
6431#define RX_CPU_SCRATCH_SIZE 0x04000
6432#define TX_CPU_SCRATCH_BASE 0x34000
6433#define TX_CPU_SCRATCH_SIZE 0x04000
6434
6435/* tp->lock is held. */
6436static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6437{
6438 int i;
6439
5d9428de
ES		 6440 BUG_ON(offset == TX_CPU_BASE &&
6441 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6442
b5d3772c
MC		 6443 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6444 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6445
6446 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6447 return 0;
6448 }
1da177e4
LT		 6449 if (offset == RX_CPU_BASE) {
6450 for (i = 0; i < 10000; i++) {
6451 tw32(offset + CPU_STATE, 0xffffffff);
6452 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6453 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6454 break;
6455 }
6456
6457 tw32(offset + CPU_STATE, 0xffffffff);
6458 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6459 udelay(10);
6460 } else {
6461 for (i = 0; i < 10000; i++) {
6462 tw32(offset + CPU_STATE, 0xffffffff);
6463 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6464 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6465 break;
6466 }
6467 }
6468
6469 if (i >= 10000) {
6470 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6471 "and %s CPU\n",
6472 tp->dev->name,
6473 (offset == RX_CPU_BASE ? "RX" : "TX"));
6474 return -ENODEV;
6475 }
ec41c7df
MC		 6476
6477 /* Clear firmware's nvram arbitration. */
6478 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6479 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6480 return 0;
6481}
6482
6483struct fw_info {
077f849d
JSR		 6484 unsigned int fw_base;
6485 unsigned int fw_len;
6486 const __be32 *fw_data;
1da177e4
LT		 6487};
6488
6489/* tp->lock is held. */
6490static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6491 int cpu_scratch_size, struct fw_info *info)
6492{
ec41c7df 6493 int err, lock_err, i;
1da177e4
LT		 6494 void (*write_op)(struct tg3 *, u32, u32);
6495
6496 if (cpu_base == TX_CPU_BASE &&
6497 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6498 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6499 "TX cpu firmware on %s which is 5705.\n",
6500 tp->dev->name);
6501 return -EINVAL;
6502 }
6503
6504 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6505 write_op = tg3_write_mem;
6506 else
6507 write_op = tg3_write_indirect_reg32;
6508
1b628151
MC		 6509 /* It is possible that bootcode is still loading at this point.
6510 * Get the nvram lock first before halting the cpu.
6511 */
ec41c7df 6512 lock_err = tg3_nvram_lock(tp);
1da177e4 6513 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6514 if (!lock_err)
6515 tg3_nvram_unlock(tp);
1da177e4
LT		 6516 if (err)
6517 goto out;
6518
6519 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6520 write_op(tp, cpu_scratch_base + i, 0);
6521 tw32(cpu_base + CPU_STATE, 0xffffffff);
6522 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6523 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6524 write_op(tp, (cpu_scratch_base +
077f849d 6525 (info->fw_base & 0xffff) +
1da177e4 6526 (i * sizeof(u32))),
077f849d 6527 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6528
6529 err = 0;
6530
6531out:
1da177e4
LT		 6532 return err;
6533}
6534
6535/* tp->lock is held. */
6536static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6537{
6538 struct fw_info info;
077f849d 6539 const __be32 *fw_data;
1da177e4
LT		 6540 int err, i;
6541
077f849d
JSR		 6542 fw_data = (void *)tp->fw->data;
6543
6544 /* Firmware blob starts with version numbers, followed by
6545 start address and length. We are setting complete length.
6546 length = end_address_of_bss - start_address_of_text.
6547 Remainder is the blob to be loaded contiguously
6548 from start address. */
6549
6550 info.fw_base = be32_to_cpu(fw_data[1]);
6551 info.fw_len = tp->fw->size - 12;
6552 info.fw_data = &fw_data[3];
1da177e4
LT		 6553
6554 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6555 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6556 &info);
6557 if (err)
6558 return err;
6559
6560 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6561 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6562 &info);
6563 if (err)
6564 return err;
6565
6566 /* Now startup only the RX cpu. */
6567 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6568 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6569
6570 for (i = 0; i < 5; i++) {
077f849d 6571 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6572 break;
6573 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6574 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6575 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6576 udelay(1000);
6577 }
6578 if (i >= 5) {
6579 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6580 "to set RX CPU PC, is %08x should be %08x\n",
6581 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6582 info.fw_base);
1da177e4
LT		 6583 return -ENODEV;
6584 }
6585 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6586 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6587
6588 return 0;
6589}
6590
1da177e4 6591/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6592
6593/* tp->lock is held. */
6594static int tg3_load_tso_firmware(struct tg3 *tp)
6595{
6596 struct fw_info info;
077f849d 6597 const __be32 *fw_data;
1da177e4
LT		 6598 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6599 int err, i;
6600
6601 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6602 return 0;
6603
077f849d
JSR		 6604 fw_data = (void *)tp->fw->data;
6605
6606 /* Firmware blob starts with version numbers, followed by
6607 start address and length. We are setting complete length.
6608 length = end_address_of_bss - start_address_of_text.
6609 Remainder is the blob to be loaded contiguously
6610 from start address. */
6611
6612 info.fw_base = be32_to_cpu(fw_data[1]);
6613 cpu_scratch_size = tp->fw_len;
6614 info.fw_len = tp->fw->size - 12;
6615 info.fw_data = &fw_data[3];
6616
1da177e4 6617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6618 cpu_base = RX_CPU_BASE;
6619 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6620 } else {
1da177e4
LT		 6621 cpu_base = TX_CPU_BASE;
6622 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6623 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6624 }
6625
6626 err = tg3_load_firmware_cpu(tp, cpu_base,
6627 cpu_scratch_base, cpu_scratch_size,
6628 &info);
6629 if (err)
6630 return err;
6631
6632 /* Now startup the cpu. */
6633 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6634 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6635
6636 for (i = 0; i < 5; i++) {
077f849d 6637 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6638 break;
6639 tw32(cpu_base + CPU_STATE, 0xffffffff);
6640 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6641 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6642 udelay(1000);
6643 }
6644 if (i >= 5) {
6645 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6646 "to set CPU PC, is %08x should be %08x\n",
6647 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6648 info.fw_base);
1da177e4
LT		 6649 return -ENODEV;
6650 }
6651 tw32(cpu_base + CPU_STATE, 0xffffffff);
6652 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6653 return 0;
6654}
6655
1da177e4 6656
1da177e4
LT		 6657static int tg3_set_mac_addr(struct net_device *dev, void *p)
6658{
6659 struct tg3 *tp = netdev_priv(dev);
6660 struct sockaddr *addr = p;
986e0aeb 6661 int err = 0, skip_mac_1 = 0;
1da177e4 6662
f9804ddb
MC		 6663 if (!is_valid_ether_addr(addr->sa_data))
6664 return -EINVAL;
6665
1da177e4
LT		 6666 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6667
e75f7c90
MC		 6668 if (!netif_running(dev))
6669 return 0;
6670
58712ef9 6671 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6672 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6673
986e0aeb
MC		 6674 addr0_high = tr32(MAC_ADDR_0_HIGH);
6675 addr0_low = tr32(MAC_ADDR_0_LOW);
6676 addr1_high = tr32(MAC_ADDR_1_HIGH);
6677 addr1_low = tr32(MAC_ADDR_1_LOW);
6678
6679 /* Skip MAC addr 1 if ASF is using it. */
6680 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6681 !(addr1_high == 0 && addr1_low == 0))
6682 skip_mac_1 = 1;
58712ef9 6683 }
986e0aeb
MC		 6684 spin_lock_bh(&tp->lock);
6685 __tg3_set_mac_addr(tp, skip_mac_1);
6686 spin_unlock_bh(&tp->lock);
1da177e4 6687
b9ec6c1b 6688 return err;
1da177e4
LT		 6689}
6690
6691/* tp->lock is held. */
6692static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6693 dma_addr_t mapping, u32 maxlen_flags,
6694 u32 nic_addr)
6695{
6696 tg3_write_mem(tp,
6697 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6698 ((u64) mapping >> 32));
6699 tg3_write_mem(tp,
6700 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6701 ((u64) mapping & 0xffffffff));
6702 tg3_write_mem(tp,
6703 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6704 maxlen_flags);
6705
6706 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6707 tg3_write_mem(tp,
6708 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6709 nic_addr);
6710}
6711
6712static void __tg3_set_rx_mode(struct net_device *);
d244c892 6713static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6714{
6715 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6716 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6717 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6718 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6719 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6720 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6721 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6722 }
6723 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6724 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6725 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6726 u32 val = ec->stats_block_coalesce_usecs;
6727
6728 if (!netif_carrier_ok(tp->dev))
6729 val = 0;
6730
6731 tw32(HOSTCC_STAT_COAL_TICKS, val);
6732 }
6733}
1da177e4
LT		 6734
6735/* tp->lock is held. */
8e7a22e3 6736static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6737{
6738 u32 val, rdmac_mode;
6739 int i, err, limit;
6740
6741 tg3_disable_ints(tp);
6742
6743 tg3_stop_fw(tp);
6744
6745 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6746
6747 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6748 tg3_abort_hw(tp, 1);
1da177e4
LT		 6749 }
6750
dd477003
MC		 6751 if (reset_phy &&
6752 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6753 tg3_phy_reset(tp);
6754
1da177e4
LT		 6755 err = tg3_chip_reset(tp);
6756 if (err)
6757 return err;
6758
6759 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6760
bcb37f6c 6761 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6762 val = tr32(TG3_CPMU_CTRL);
6763 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6764 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6765
6766 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6767 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6768 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6769 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6770
6771 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6772 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6773 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6774 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6775
6776 val = tr32(TG3_CPMU_HST_ACC);
6777 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6778 val |= CPMU_HST_ACC_MACCLK_6_25;
6779 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6780 }
6781
33466d93
MC		 6782 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6783 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6784 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6785 PCIE_PWR_MGMT_L1_THRESH_4MS;
6786 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 6787
6788 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6789 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6790
6791 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC		 6792 }
6793
255ca311
MC		 6794 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6795 val = tr32(TG3_PCIE_LNKCTL);
6796 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6797 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6798 else
6799 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6800 tw32(TG3_PCIE_LNKCTL, val);
6801 }
6802
1da177e4
LT		 6803 /* This works around an issue with Athlon chipsets on
6804 * B3 tigon3 silicon. This bit has no effect on any
6805 * other revision. But do not set this on PCI Express
795d01c5 6806 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6807 */
795d01c5
MC		 6808 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6809 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6810 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6811 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6812 }
1da177e4
LT		 6813
6814 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6815 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6816 val = tr32(TG3PCI_PCISTATE);
6817 val |= PCISTATE_RETRY_SAME_DMA;
6818 tw32(TG3PCI_PCISTATE, val);
6819 }
6820
0d3031d9
MC		 6821 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6822 /* Allow reads and writes to the
6823 * APE register and memory space.
6824 */
6825 val = tr32(TG3PCI_PCISTATE);
6826 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6827 PCISTATE_ALLOW_APE_SHMEM_WR;
6828 tw32(TG3PCI_PCISTATE, val);
6829 }
6830
1da177e4
LT		 6831 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6832 /* Enable some hw fixes. */
6833 val = tr32(TG3PCI_MSI_DATA);
6834 val |= (1 << 26) | (1 << 28) | (1 << 29);
6835 tw32(TG3PCI_MSI_DATA, val);
6836 }
6837
6838 /* Descriptor ring init may make accesses to the
6839 * NIC SRAM area to setup the TX descriptors, so we
6840 * can only do this after the hardware has been
6841 * successfully reset.
6842 */
32d8c572
MC		 6843 err = tg3_init_rings(tp);
6844 if (err)
6845 return err;
1da177e4 6846
9936bcf6 6847 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 6848 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 6849 /* This value is determined during the probe time DMA
6850 * engine test, tg3_test_dma.
6851 */
6852 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6853 }
1da177e4
LT		 6854
6855 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6856 GRC_MODE_4X_NIC_SEND_RINGS |
6857 GRC_MODE_NO_TX_PHDR_CSUM |
6858 GRC_MODE_NO_RX_PHDR_CSUM);
6859 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 6860
6861 /* Pseudo-header checksum is done by hardware logic and not
6862 * the offload processers, so make the chip do the pseudo-
6863 * header checksums on receive. For transmit it is more
6864 * convenient to do the pseudo-header checksum in software
6865 * as Linux does that on transmit for us in all cases.
6866 */
6867 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 6868
6869 tw32(GRC_MODE,
6870 tp->grc_mode |
6871 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6872
6873 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6874 val = tr32(GRC_MISC_CFG);
6875 val &= ~0xff;
6876 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6877 tw32(GRC_MISC_CFG, val);
6878
6879 /* Initialize MBUF/DESC pool. */
cbf46853 6880 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 6881 /* Do nothing. */
6882 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6883 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6885 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6886 else
6887 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6888 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6889 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6890 }
1da177e4
LT		 6891 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6892 int fw_len;
6893
077f849d 6894 fw_len = tp->fw_len;
1da177e4
LT		 6895 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6896 tw32(BUFMGR_MB_POOL_ADDR,
6897 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6898 tw32(BUFMGR_MB_POOL_SIZE,
6899 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6900 }
1da177e4 6901
0f893dc6 6902 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 6903 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6904 tp->bufmgr_config.mbuf_read_dma_low_water);
6905 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6906 tp->bufmgr_config.mbuf_mac_rx_low_water);
6907 tw32(BUFMGR_MB_HIGH_WATER,
6908 tp->bufmgr_config.mbuf_high_water);
6909 } else {
6910 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6911 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6912 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6913 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6914 tw32(BUFMGR_MB_HIGH_WATER,
6915 tp->bufmgr_config.mbuf_high_water_jumbo);
6916 }
6917 tw32(BUFMGR_DMA_LOW_WATER,
6918 tp->bufmgr_config.dma_low_water);
6919 tw32(BUFMGR_DMA_HIGH_WATER,
6920 tp->bufmgr_config.dma_high_water);
6921
6922 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6923 for (i = 0; i < 2000; i++) {
6924 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6925 break;
6926 udelay(10);
6927 }
6928 if (i >= 2000) {
6929 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6930 tp->dev->name);
6931 return -ENODEV;
6932 }
6933
6934 /* Setup replenish threshold. */
f92905de
MC		 6935 val = tp->rx_pending / 8;
6936 if (val == 0)
6937 val = 1;
6938 else if (val > tp->rx_std_max_post)
6939 val = tp->rx_std_max_post;
b5d3772c
MC		 6940 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6941 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6942 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6943
6944 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6945 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6946 }
f92905de
MC		 6947
6948 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 6949
6950 /* Initialize TG3_BDINFO's at:
6951 * RCVDBDI_STD_BD: standard eth size rx ring
6952 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6953 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6954 *
6955 * like so:
6956 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6957 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6958 * ring attribute flags
6959 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6960 *
6961 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6962 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6963 *
6964 * The size of each ring is fixed in the firmware, but the location is
6965 * configurable.
6966 */
6967 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6968 ((u64) tp->rx_std_mapping >> 32));
6969 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6970 ((u64) tp->rx_std_mapping & 0xffffffff));
6971 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6972 NIC_SRAM_RX_BUFFER_DESC);
6973
fdb72b38
MC		 6974 /* Disable the mini ring */
6975 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 6976 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6977 BDINFO_FLAGS_DISABLED);
6978
fdb72b38
MC		 6979 /* Program the jumbo buffer descriptor ring control
6980 * blocks on those devices that have them.
6981 */
8f666b07 6982 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 6983 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 6984 /* Setup replenish threshold. */
6985 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6986
0f893dc6 6987 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 6988 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6989 ((u64) tp->rx_jumbo_mapping >> 32));
6990 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6991 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6992 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6993 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6994 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6995 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6996 } else {
6997 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6998 BDINFO_FLAGS_DISABLED);
6999 }
7000
fdb72b38
MC		 7001 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7002 } else
7003 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7004
7005 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4
LT		 7006
7007 /* There is only one send ring on 5705/5750, no need to explicitly
7008 * disable the others.
7009 */
7010 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7011 /* Clear out send RCB ring in SRAM. */
7012 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7013 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7014 BDINFO_FLAGS_DISABLED);
7015 }
7016
7017 tp->tx_prod = 0;
7018 tp->tx_cons = 0;
7019 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7020 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7021
7022 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7023 tp->tx_desc_mapping,
7024 (TG3_TX_RING_SIZE <<
7025 BDINFO_FLAGS_MAXLEN_SHIFT),
7026 NIC_SRAM_TX_BUFFER_DESC);
7027
7028 /* There is only one receive return ring on 5705/5750, no need
7029 * to explicitly disable the others.
7030 */
7031 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7032 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7033 i += TG3_BDINFO_SIZE) {
7034 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7035 BDINFO_FLAGS_DISABLED);
7036 }
7037 }
7038
7039 tp->rx_rcb_ptr = 0;
7040 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7041
7042 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7043 tp->rx_rcb_mapping,
7044 (TG3_RX_RCB_RING_SIZE(tp) <<
7045 BDINFO_FLAGS_MAXLEN_SHIFT),
7046 0);
7047
7048 tp->rx_std_ptr = tp->rx_pending;
7049 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7050 tp->rx_std_ptr);
7051
0f893dc6 7052 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 7053 tp->rx_jumbo_pending : 0;
7054 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7055 tp->rx_jumbo_ptr);
7056
7057 /* Initialize MAC address and backoff seed. */
986e0aeb 7058 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7059
7060 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7061 tw32(MAC_RX_MTU_SIZE,
7062 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7063
7064 /* The slot time is changed by tg3_setup_phy if we
7065 * run at gigabit with half duplex.
7066 */
7067 tw32(MAC_TX_LENGTHS,
7068 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7069 (6 << TX_LENGTHS_IPG_SHIFT) |
7070 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7071
7072 /* Receive rules. */
7073 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7074 tw32(RCVLPC_CONFIG, 0x0181);
7075
7076 /* Calculate RDMAC_MODE setting early, we need it to determine
7077 * the RCVLPC_STATE_ENABLE mask.
7078 */
7079 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7080 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7081 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7082 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7083 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7084
57e6983c 7085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7087 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7088 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7089 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7090 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7091
85e94ced
MC		 7092 /* If statement applies to 5705 and 5750 PCI devices only */
7093 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7094 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7095 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7096 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7098 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7099 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7100 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7101 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7102 }
7103 }
7104
85e94ced
MC		 7105 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7106 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7107
1da177e4 7108 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7109 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7110
7111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7113 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7114
7115 /* Receive/send statistics. */
1661394e
MC		 7116 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7117 val = tr32(RCVLPC_STATS_ENABLE);
7118 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7119 tw32(RCVLPC_STATS_ENABLE, val);
7120 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7121 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7122 val = tr32(RCVLPC_STATS_ENABLE);
7123 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7124 tw32(RCVLPC_STATS_ENABLE, val);
7125 } else {
7126 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7127 }
7128 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7129 tw32(SNDDATAI_STATSENAB, 0xffffff);
7130 tw32(SNDDATAI_STATSCTRL,
7131 (SNDDATAI_SCTRL_ENABLE |
7132 SNDDATAI_SCTRL_FASTUPD));
7133
7134 /* Setup host coalescing engine. */
7135 tw32(HOSTCC_MODE, 0);
7136 for (i = 0; i < 2000; i++) {
7137 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7138 break;
7139 udelay(10);
7140 }
7141
d244c892 7142 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 7143
7144 /* set status block DMA address */
7145 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7146 ((u64) tp->status_mapping >> 32));
7147 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7148 ((u64) tp->status_mapping & 0xffffffff));
7149
7150 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7151 /* Status/statistics block address. See tg3_timer,
7152 * the tg3_periodic_fetch_stats call there, and
7153 * tg3_get_stats to see how this works for 5705/5750 chips.
7154 */
1da177e4
LT		 7155 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7156 ((u64) tp->stats_mapping >> 32));
7157 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7158 ((u64) tp->stats_mapping & 0xffffffff));
7159 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7160 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7161 }
7162
7163 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7164
7165 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7166 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7167 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7168 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7169
7170 /* Clear statistics/status block in chip, and status block in ram. */
7171 for (i = NIC_SRAM_STATS_BLK;
7172 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7173 i += sizeof(u32)) {
7174 tg3_write_mem(tp, i, 0);
7175 udelay(40);
7176 }
7177 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7178
c94e3941
MC		 7179 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7180 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7181 /* reset to prevent losing 1st rx packet intermittently */
7182 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7183 udelay(10);
7184 }
7185
3bda1258
MC		 7186 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7187 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7188 else
7189 tp->mac_mode = 0;
7190 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7191 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7192 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7193 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7194 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7195 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7196 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7197 udelay(40);
7198
314fba34 7199 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7200 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7201 * register to preserve the GPIO settings for LOMs. The GPIOs,
7202 * whether used as inputs or outputs, are set by boot code after
7203 * reset.
7204 */
9d26e213 7205 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7206 u32 gpio_mask;
7207
9d26e213
MC		 7208 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7209 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7210 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7211
7212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7213 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7214 GRC_LCLCTRL_GPIO_OUTPUT3;
7215
af36e6b6
MC		 7216 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7217 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7218
aaf84465 7219 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7220 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7221
7222 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7223 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7224 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7225 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7226 }
1da177e4
LT		 7227 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7228 udelay(100);
7229
09ee929c 7230 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
1da177e4
LT		 7231
7232 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7233 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7234 udelay(40);
7235 }
7236
7237 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7238 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7239 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7240 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7241 WDMAC_MODE_LNGREAD_ENAB);
7242
85e94ced
MC		 7243 /* If statement applies to 5705 and 5750 PCI devices only */
7244 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7245 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7247 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7248 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7249 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7250 /* nothing */
7251 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7252 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7253 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7254 val |= WDMAC_MODE_RX_ACCEL;
7255 }
7256 }
7257
d9ab5ad1 7258 /* Enable host coalescing bug fix */
321d32a0 7259 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7260 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7261
1da177e4
LT		 7262 tw32_f(WDMAC_MODE, val);
7263 udelay(40);
7264
9974a356
MC		 7265 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7266 u16 pcix_cmd;
7267
7268 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7269 &pcix_cmd);
1da177e4 7270 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7271 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7272 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7273 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7274 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7275 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7276 }
9974a356
MC		 7277 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7278 pcix_cmd);
1da177e4
LT		 7279 }
7280
7281 tw32_f(RDMAC_MODE, rdmac_mode);
7282 udelay(40);
7283
7284 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7285 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7286 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7287
7288 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7289 tw32(SNDDATAC_MODE,
7290 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7291 else
7292 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7293
1da177e4
LT		 7294 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7295 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7296 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7297 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7298 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7299 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7300 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7301 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7302
7303 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7304 err = tg3_load_5701_a0_firmware_fix(tp);
7305 if (err)
7306 return err;
7307 }
7308
1da177e4
LT		 7309 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7310 err = tg3_load_tso_firmware(tp);
7311 if (err)
7312 return err;
7313 }
1da177e4
LT		 7314
7315 tp->tx_mode = TX_MODE_ENABLE;
7316 tw32_f(MAC_TX_MODE, tp->tx_mode);
7317 udelay(100);
7318
7319 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7320 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7321 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7322
1da177e4
LT		 7323 tw32_f(MAC_RX_MODE, tp->rx_mode);
7324 udelay(10);
7325
1da177e4
LT		 7326 tw32(MAC_LED_CTRL, tp->led_ctrl);
7327
7328 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7329 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7330 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7331 udelay(10);
7332 }
7333 tw32_f(MAC_RX_MODE, tp->rx_mode);
7334 udelay(10);
7335
7336 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7337 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7338 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7339 /* Set drive transmission level to 1.2V */
7340 /* only if the signal pre-emphasis bit is not set */
7341 val = tr32(MAC_SERDES_CFG);
7342 val &= 0xfffff000;
7343 val |= 0x880;
7344 tw32(MAC_SERDES_CFG, val);
7345 }
7346 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7347 tw32(MAC_SERDES_CFG, 0x616000);
7348 }
7349
7350 /* Prevent chip from dropping frames when flow control
7351 * is enabled.
7352 */
7353 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7354
7355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7356 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7357 /* Use hardware link auto-negotiation */
7358 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7359 }
7360
d4d2c558
MC		 7361 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7362 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7363 u32 tmp;
7364
7365 tmp = tr32(SERDES_RX_CTRL);
7366 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7367 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7368 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7369 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7370 }
7371
dd477003
MC		 7372 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7373 if (tp->link_config.phy_is_low_power) {
7374 tp->link_config.phy_is_low_power = 0;
7375 tp->link_config.speed = tp->link_config.orig_speed;
7376 tp->link_config.duplex = tp->link_config.orig_duplex;
7377 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7378 }
1da177e4 7379
dd477003
MC		 7380 err = tg3_setup_phy(tp, 0);
7381 if (err)
7382 return err;
1da177e4 7383
dd477003 7384 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7385 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7386 u32 tmp;
7387
7388 /* Clear CRC stats. */
7389 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7390 tg3_writephy(tp, MII_TG3_TEST1,
7391 tmp | MII_TG3_TEST1_CRC_EN);
7392 tg3_readphy(tp, 0x14, &tmp);
7393 }
1da177e4
LT		 7394 }
7395 }
7396
7397 __tg3_set_rx_mode(tp->dev);
7398
7399 /* Initialize receive rules. */
7400 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7401 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7402 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7403 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7404
4cf78e4f 7405 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7406 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7407 limit = 8;
7408 else
7409 limit = 16;
7410 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7411 limit -= 4;
7412 switch (limit) {
7413 case 16:
7414 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7415 case 15:
7416 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7417 case 14:
7418 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7419 case 13:
7420 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7421 case 12:
7422 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7423 case 11:
7424 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7425 case 10:
7426 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7427 case 9:
7428 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7429 case 8:
7430 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7431 case 7:
7432 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7433 case 6:
7434 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7435 case 5:
7436 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7437 case 4:
7438 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7439 case 3:
7440 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7441 case 2:
7442 case 1:
7443
7444 default:
7445 break;
855e1111 7446 }
1da177e4 7447
9ce768ea
MC		 7448 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7449 /* Write our heartbeat update interval to APE. */
7450 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7451 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7452
1da177e4
LT		 7453 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7454
1da177e4
LT		 7455 return 0;
7456}
7457
7458/* Called at device open time to get the chip ready for
7459 * packet processing. Invoked with tp->lock held.
7460 */
8e7a22e3 7461static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7462{
1da177e4
LT		 7463 tg3_switch_clocks(tp);
7464
7465 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7466
2f751b67 7467 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7468}
7469
7470#define TG3_STAT_ADD32(PSTAT, REG) \
7471do { u32 __val = tr32(REG); \
7472 (PSTAT)->low += __val; \
7473 if ((PSTAT)->low < __val) \
7474 (PSTAT)->high += 1; \
7475} while (0)
7476
7477static void tg3_periodic_fetch_stats(struct tg3 *tp)
7478{
7479 struct tg3_hw_stats *sp = tp->hw_stats;
7480
7481 if (!netif_carrier_ok(tp->dev))
7482 return;
7483
7484 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7485 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7486 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7487 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7488 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7489 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7490 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7491 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7492 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7493 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7494 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7495 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7496 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7497
7498 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7499 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7500 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7501 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7502 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7503 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7504 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7505 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7506 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7507 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7508 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7509 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7510 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7511 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7512
7513 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7514 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7515 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7516}
7517
7518static void tg3_timer(unsigned long __opaque)
7519{
7520 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7521
f475f163
MC		 7522 if (tp->irq_sync)
7523 goto restart_timer;
7524
f47c11ee 7525 spin_lock(&tp->lock);
1da177e4 7526
fac9b83e
DM		 7527 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7528 /* All of this garbage is because when using non-tagged
7529 * IRQ status the mailbox/status_block protocol the chip
7530 * uses with the cpu is race prone.
7531 */
7532 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7533 tw32(GRC_LOCAL_CTRL,
7534 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7535 } else {
7536 tw32(HOSTCC_MODE, tp->coalesce_mode |
7537 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7538 }
1da177e4 7539
fac9b83e
DM		 7540 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7541 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7542 spin_unlock(&tp->lock);
fac9b83e
DM		 7543 schedule_work(&tp->reset_task);
7544 return;
7545 }
1da177e4
LT		 7546 }
7547
1da177e4
LT		 7548 /* This part only runs once per second. */
7549 if (!--tp->timer_counter) {
fac9b83e
DM		 7550 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7551 tg3_periodic_fetch_stats(tp);
7552
1da177e4
LT		 7553 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7554 u32 mac_stat;
7555 int phy_event;
7556
7557 mac_stat = tr32(MAC_STATUS);
7558
7559 phy_event = 0;
7560 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7561 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7562 phy_event = 1;
7563 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7564 phy_event = 1;
7565
7566 if (phy_event)
7567 tg3_setup_phy(tp, 0);
7568 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7569 u32 mac_stat = tr32(MAC_STATUS);
7570 int need_setup = 0;
7571
7572 if (netif_carrier_ok(tp->dev) &&
7573 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7574 need_setup = 1;
7575 }
7576 if (! netif_carrier_ok(tp->dev) &&
7577 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7578 MAC_STATUS_SIGNAL_DET))) {
7579 need_setup = 1;
7580 }
7581 if (need_setup) {
3d3ebe74
MC		 7582 if (!tp->serdes_counter) {
7583 tw32_f(MAC_MODE,
7584 (tp->mac_mode &
7585 ~MAC_MODE_PORT_MODE_MASK));
7586 udelay(40);
7587 tw32_f(MAC_MODE, tp->mac_mode);
7588 udelay(40);
7589 }
1da177e4
LT		 7590 tg3_setup_phy(tp, 0);
7591 }
747e8f8b
MC		 7592 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7593 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7594
7595 tp->timer_counter = tp->timer_multiplier;
7596 }
7597
130b8e4d
MC		 7598 /* Heartbeat is only sent once every 2 seconds.
7599 *
7600 * The heartbeat is to tell the ASF firmware that the host
7601 * driver is still alive. In the event that the OS crashes,
7602 * ASF needs to reset the hardware to free up the FIFO space
7603 * that may be filled with rx packets destined for the host.
7604 * If the FIFO is full, ASF will no longer function properly.
7605 *
7606 * Unintended resets have been reported on real time kernels
7607 * where the timer doesn't run on time. Netpoll will also have
7608 * same problem.
7609 *
7610 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7611 * to check the ring condition when the heartbeat is expiring
7612 * before doing the reset. This will prevent most unintended
7613 * resets.
7614 */
1da177e4 7615 if (!--tp->asf_counter) {
bc7959b2
MC		 7616 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7617 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7618 tg3_wait_for_event_ack(tp);
7619
bbadf503 7620 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7621 FWCMD_NICDRV_ALIVE3);
bbadf503 7622 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7623 /* 5 seconds timeout */
bbadf503 7624 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7625
7626 tg3_generate_fw_event(tp);
1da177e4
LT		 7627 }
7628 tp->asf_counter = tp->asf_multiplier;
7629 }
7630
f47c11ee 7631 spin_unlock(&tp->lock);
1da177e4 7632
f475f163 7633restart_timer:
1da177e4
LT		 7634 tp->timer.expires = jiffies + tp->timer_offset;
7635 add_timer(&tp->timer);
7636}
7637
81789ef5 7638static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7639{
7d12e780 7640 irq_handler_t fn;
fcfa0a32
MC		 7641 unsigned long flags;
7642 struct net_device *dev = tp->dev;
7643
7644 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7645 fn = tg3_msi;
7646 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7647 fn = tg3_msi_1shot;
1fb9df5d 7648 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7649 } else {
7650 fn = tg3_interrupt;
7651 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7652 fn = tg3_interrupt_tagged;
1fb9df5d 7653 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7654 }
7655 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7656}
7657
7938109f
MC		 7658static int tg3_test_interrupt(struct tg3 *tp)
7659{
7660 struct net_device *dev = tp->dev;
b16250e3 7661 int err, i, intr_ok = 0;
7938109f 7662
d4bc3927
MC		 7663 if (!netif_running(dev))
7664 return -ENODEV;
7665
7938109f
MC		 7666 tg3_disable_ints(tp);
7667
7668 free_irq(tp->pdev->irq, dev);
7669
7670 err = request_irq(tp->pdev->irq, tg3_test_isr,
1fb9df5d 7671 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 7672 if (err)
7673 return err;
7674
38f3843e 7675 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7676 tg3_enable_ints(tp);
7677
7678 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7679 HOSTCC_MODE_NOW);
7680
7681 for (i = 0; i < 5; i++) {
b16250e3
MC		 7682 u32 int_mbox, misc_host_ctrl;
7683
09ee929c
MC		 7684 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7685 TG3_64BIT_REG_LOW);
b16250e3
MC		 7686 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7687
7688 if ((int_mbox != 0) ||
7689 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7690 intr_ok = 1;
7938109f 7691 break;
b16250e3
MC		 7692 }
7693
7938109f
MC		 7694 msleep(10);
7695 }
7696
7697 tg3_disable_ints(tp);
7698
7699 free_irq(tp->pdev->irq, dev);
6aa20a22 7700
fcfa0a32 7701 err = tg3_request_irq(tp);
7938109f
MC		 7702
7703 if (err)
7704 return err;
7705
b16250e3 7706 if (intr_ok)
7938109f
MC		 7707 return 0;
7708
7709 return -EIO;
7710}
7711
7712/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7713 * successfully restored
7714 */
7715static int tg3_test_msi(struct tg3 *tp)
7716{
7717 struct net_device *dev = tp->dev;
7718 int err;
7719 u16 pci_cmd;
7720
7721 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7722 return 0;
7723
7724 /* Turn off SERR reporting in case MSI terminates with Master
7725 * Abort.
7726 */
7727 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7728 pci_write_config_word(tp->pdev, PCI_COMMAND,
7729 pci_cmd & ~PCI_COMMAND_SERR);
7730
7731 err = tg3_test_interrupt(tp);
7732
7733 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7734
7735 if (!err)
7736 return 0;
7737
7738 /* other failures */
7739 if (err != -EIO)
7740 return err;
7741
7742 /* MSI test failed, go back to INTx mode */
7743 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7744 "switching to INTx mode. Please report this failure to "
7745 "the PCI maintainer and include system chipset information.\n",
7746 tp->dev->name);
7747
7748 free_irq(tp->pdev->irq, dev);
7749 pci_disable_msi(tp->pdev);
7750
7751 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7752
fcfa0a32 7753 err = tg3_request_irq(tp);
7938109f
MC		 7754 if (err)
7755 return err;
7756
7757 /* Need to reset the chip because the MSI cycle may have terminated
7758 * with Master Abort.
7759 */
f47c11ee 7760 tg3_full_lock(tp, 1);
7938109f 7761
944d980e 7762 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7763 err = tg3_init_hw(tp, 1);
7938109f 7764
f47c11ee 7765 tg3_full_unlock(tp);
7938109f
MC		 7766
7767 if (err)
7768 free_irq(tp->pdev->irq, dev);
7769
7770 return err;
7771}
7772
9e9fd12d
MC		 7773static int tg3_request_firmware(struct tg3 *tp)
7774{
7775 const __be32 *fw_data;
7776
7777 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7778 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7779 tp->dev->name, tp->fw_needed);
7780 return -ENOENT;
7781 }
7782
7783 fw_data = (void *)tp->fw->data;
7784
7785 /* Firmware blob starts with version numbers, followed by
7786 * start address and _full_ length including BSS sections
7787 * (which must be longer than the actual data, of course
7788 */
7789
7790 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7791 if (tp->fw_len < (tp->fw->size - 12)) {
7792 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7793 tp->dev->name, tp->fw_len, tp->fw_needed);
7794 release_firmware(tp->fw);
7795 tp->fw = NULL;
7796 return -EINVAL;
7797 }
7798
7799 /* We no longer need firmware; we have it. */
7800 tp->fw_needed = NULL;
7801 return 0;
7802}
7803
1da177e4
LT		 7804static int tg3_open(struct net_device *dev)
7805{
7806 struct tg3 *tp = netdev_priv(dev);
7807 int err;
7808
9e9fd12d
MC		 7809 if (tp->fw_needed) {
7810 err = tg3_request_firmware(tp);
7811 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7812 if (err)
7813 return err;
7814 } else if (err) {
7815 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7816 tp->dev->name);
7817 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7818 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7819 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7820 tp->dev->name);
7821 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7822 }
7823 }
7824
c49a1561
MC		 7825 netif_carrier_off(tp->dev);
7826
bc1c7567 7827 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7828 if (err)
bc1c7567 7829 return err;
2f751b67
MC		 7830
7831 tg3_full_lock(tp, 0);
bc1c7567 7832
1da177e4
LT		 7833 tg3_disable_ints(tp);
7834 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7835
f47c11ee 7836 tg3_full_unlock(tp);
1da177e4
LT		 7837
7838 /* The placement of this call is tied
7839 * to the setup and use of Host TX descriptors.
7840 */
7841 err = tg3_alloc_consistent(tp);
7842 if (err)
7843 return err;
7844
7544b097 7845 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
fac9b83e
DM		 7846 /* All MSI supporting chips should support tagged
7847 * status. Assert that this is the case.
7848 */
7849 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7850 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7851 "Not using MSI.\n", tp->dev->name);
7852 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 7853 u32 msi_mode;
7854
7855 msi_mode = tr32(MSGINT_MODE);
7856 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7857 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7858 }
7859 }
fcfa0a32 7860 err = tg3_request_irq(tp);
1da177e4
LT		 7861
7862 if (err) {
88b06bc2
MC		 7863 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7864 pci_disable_msi(tp->pdev);
7865 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7866 }
1da177e4
LT		 7867 tg3_free_consistent(tp);
7868 return err;
7869 }
7870
bea3348e
SH		 7871 napi_enable(&tp->napi);
7872
f47c11ee 7873 tg3_full_lock(tp, 0);
1da177e4 7874
8e7a22e3 7875 err = tg3_init_hw(tp, 1);
1da177e4 7876 if (err) {
944d980e 7877 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7878 tg3_free_rings(tp);
7879 } else {
fac9b83e
DM		 7880 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7881 tp->timer_offset = HZ;
7882 else
7883 tp->timer_offset = HZ / 10;
7884
7885 BUG_ON(tp->timer_offset > HZ);
7886 tp->timer_counter = tp->timer_multiplier =
7887 (HZ / tp->timer_offset);
7888 tp->asf_counter = tp->asf_multiplier =
28fbef78 7889 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 7890
7891 init_timer(&tp->timer);
7892 tp->timer.expires = jiffies + tp->timer_offset;
7893 tp->timer.data = (unsigned long) tp;
7894 tp->timer.function = tg3_timer;
1da177e4
LT		 7895 }
7896
f47c11ee 7897 tg3_full_unlock(tp);
1da177e4
LT		 7898
7899 if (err) {
bea3348e 7900 napi_disable(&tp->napi);
88b06bc2
MC		 7901 free_irq(tp->pdev->irq, dev);
7902 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7903 pci_disable_msi(tp->pdev);
7904 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7905 }
1da177e4
LT		 7906 tg3_free_consistent(tp);
7907 return err;
7908 }
7909
7938109f
MC		 7910 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7911 err = tg3_test_msi(tp);
fac9b83e 7912
7938109f 7913 if (err) {
f47c11ee 7914 tg3_full_lock(tp, 0);
7938109f
MC		 7915
7916 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7917 pci_disable_msi(tp->pdev);
7918 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7919 }
944d980e 7920 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 7921 tg3_free_rings(tp);
7922 tg3_free_consistent(tp);
7923
f47c11ee 7924 tg3_full_unlock(tp);
7938109f 7925
bea3348e
SH		 7926 napi_disable(&tp->napi);
7927
7938109f
MC		 7928 return err;
7929 }
fcfa0a32
MC		 7930
7931 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7932 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 7933 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 7934
b5d3772c
MC		 7935 tw32(PCIE_TRANSACTION_CFG,
7936 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 7937 }
7938 }
7938109f
MC		 7939 }
7940
b02fd9e3
MC		 7941 tg3_phy_start(tp);
7942
f47c11ee 7943 tg3_full_lock(tp, 0);
1da177e4 7944
7938109f
MC		 7945 add_timer(&tp->timer);
7946 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 7947 tg3_enable_ints(tp);
7948
f47c11ee 7949 tg3_full_unlock(tp);
1da177e4
LT		 7950
7951 netif_start_queue(dev);
7952
7953 return 0;
7954}
7955
7956#if 0
7957/*static*/ void tg3_dump_state(struct tg3 *tp)
7958{
7959 u32 val32, val32_2, val32_3, val32_4, val32_5;
7960 u16 val16;
7961 int i;
7962
7963 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7964 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7965 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7966 val16, val32);
7967
7968 /* MAC block */
7969 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7970 tr32(MAC_MODE), tr32(MAC_STATUS));
7971 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7972 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7973 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7974 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7975 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7976 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7977
7978 /* Send data initiator control block */
7979 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7980 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7981 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7982 tr32(SNDDATAI_STATSCTRL));
7983
7984 /* Send data completion control block */
7985 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7986
7987 /* Send BD ring selector block */
7988 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7989 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7990
7991 /* Send BD initiator control block */
7992 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7993 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7994
7995 /* Send BD completion control block */
7996 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7997
7998 /* Receive list placement control block */
7999 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8000 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8001 printk(" RCVLPC_STATSCTRL[%08x]\n",
8002 tr32(RCVLPC_STATSCTRL));
8003
8004 /* Receive data and receive BD initiator control block */
8005 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8006 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8007
8008 /* Receive data completion control block */
8009 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8010 tr32(RCVDCC_MODE));
8011
8012 /* Receive BD initiator control block */
8013 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8014 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8015
8016 /* Receive BD completion control block */
8017 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8018 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8019
8020 /* Receive list selector control block */
8021 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8022 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8023
8024 /* Mbuf cluster free block */
8025 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8026 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8027
8028 /* Host coalescing control block */
8029 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8030 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8031 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8032 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8033 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8034 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8035 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8036 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8037 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8038 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8039 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8040 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8041
8042 /* Memory arbiter control block */
8043 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8044 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8045
8046 /* Buffer manager control block */
8047 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8048 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8049 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8050 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8051 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8052 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8053 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8054 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8055
8056 /* Read DMA control block */
8057 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8058 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8059
8060 /* Write DMA control block */
8061 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8062 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8063
8064 /* DMA completion block */
8065 printk("DEBUG: DMAC_MODE[%08x]\n",
8066 tr32(DMAC_MODE));
8067
8068 /* GRC block */
8069 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8070 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8071 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8072 tr32(GRC_LOCAL_CTRL));
8073
8074 /* TG3_BDINFOs */
8075 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8076 tr32(RCVDBDI_JUMBO_BD + 0x0),
8077 tr32(RCVDBDI_JUMBO_BD + 0x4),
8078 tr32(RCVDBDI_JUMBO_BD + 0x8),
8079 tr32(RCVDBDI_JUMBO_BD + 0xc));
8080 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8081 tr32(RCVDBDI_STD_BD + 0x0),
8082 tr32(RCVDBDI_STD_BD + 0x4),
8083 tr32(RCVDBDI_STD_BD + 0x8),
8084 tr32(RCVDBDI_STD_BD + 0xc));
8085 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8086 tr32(RCVDBDI_MINI_BD + 0x0),
8087 tr32(RCVDBDI_MINI_BD + 0x4),
8088 tr32(RCVDBDI_MINI_BD + 0x8),
8089 tr32(RCVDBDI_MINI_BD + 0xc));
8090
8091 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8092 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8093 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8094 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8095 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8096 val32, val32_2, val32_3, val32_4);
8097
8098 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8099 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8100 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8101 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8102 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8103 val32, val32_2, val32_3, val32_4);
8104
8105 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8106 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8107 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8108 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8109 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8110 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8111 val32, val32_2, val32_3, val32_4, val32_5);
8112
8113 /* SW status block */
8114 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8115 tp->hw_status->status,
8116 tp->hw_status->status_tag,
8117 tp->hw_status->rx_jumbo_consumer,
8118 tp->hw_status->rx_consumer,
8119 tp->hw_status->rx_mini_consumer,
8120 tp->hw_status->idx[0].rx_producer,
8121 tp->hw_status->idx[0].tx_consumer);
8122
8123 /* SW statistics block */
8124 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8125 ((u32 *)tp->hw_stats)[0],
8126 ((u32 *)tp->hw_stats)[1],
8127 ((u32 *)tp->hw_stats)[2],
8128 ((u32 *)tp->hw_stats)[3]);
8129
8130 /* Mailboxes */
8131 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8132 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8133 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8134 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8135 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8136
8137 /* NIC side send descriptors. */
8138 for (i = 0; i < 6; i++) {
8139 unsigned long txd;
8140
8141 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8142 + (i * sizeof(struct tg3_tx_buffer_desc));
8143 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8144 i,
8145 readl(txd + 0x0), readl(txd + 0x4),
8146 readl(txd + 0x8), readl(txd + 0xc));
8147 }
8148
8149 /* NIC side RX descriptors. */
8150 for (i = 0; i < 6; i++) {
8151 unsigned long rxd;
8152
8153 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8154 + (i * sizeof(struct tg3_rx_buffer_desc));
8155 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8156 i,
8157 readl(rxd + 0x0), readl(rxd + 0x4),
8158 readl(rxd + 0x8), readl(rxd + 0xc));
8159 rxd += (4 * sizeof(u32));
8160 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8161 i,
8162 readl(rxd + 0x0), readl(rxd + 0x4),
8163 readl(rxd + 0x8), readl(rxd + 0xc));
8164 }
8165
8166 for (i = 0; i < 6; i++) {
8167 unsigned long rxd;
8168
8169 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8170 + (i * sizeof(struct tg3_rx_buffer_desc));
8171 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8172 i,
8173 readl(rxd + 0x0), readl(rxd + 0x4),
8174 readl(rxd + 0x8), readl(rxd + 0xc));
8175 rxd += (4 * sizeof(u32));
8176 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8177 i,
8178 readl(rxd + 0x0), readl(rxd + 0x4),
8179 readl(rxd + 0x8), readl(rxd + 0xc));
8180 }
8181}
8182#endif
8183
8184static struct net_device_stats *tg3_get_stats(struct net_device *);
8185static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8186
8187static int tg3_close(struct net_device *dev)
8188{
8189 struct tg3 *tp = netdev_priv(dev);
8190
bea3348e 8191 napi_disable(&tp->napi);
28e53bdd 8192 cancel_work_sync(&tp->reset_task);
7faa006f 8193
1da177e4
LT		 8194 netif_stop_queue(dev);
8195
8196 del_timer_sync(&tp->timer);
8197
f47c11ee 8198 tg3_full_lock(tp, 1);
1da177e4
LT		 8199#if 0
8200 tg3_dump_state(tp);
8201#endif
8202
8203 tg3_disable_ints(tp);
8204
944d980e 8205 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8206 tg3_free_rings(tp);
5cf64b8a 8207 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8208
f47c11ee 8209 tg3_full_unlock(tp);
1da177e4 8210
88b06bc2
MC		 8211 free_irq(tp->pdev->irq, dev);
8212 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8213 pci_disable_msi(tp->pdev);
8214 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8215 }
1da177e4
LT		 8216
8217 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8218 sizeof(tp->net_stats_prev));
8219 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8220 sizeof(tp->estats_prev));
8221
8222 tg3_free_consistent(tp);
8223
bc1c7567
MC		 8224 tg3_set_power_state(tp, PCI_D3hot);
8225
8226 netif_carrier_off(tp->dev);
8227
1da177e4
LT		 8228 return 0;
8229}
8230
8231static inline unsigned long get_stat64(tg3_stat64_t *val)
8232{
8233 unsigned long ret;
8234
8235#if (BITS_PER_LONG == 32)
8236 ret = val->low;
8237#else
8238 ret = ((u64)val->high << 32) | ((u64)val->low);
8239#endif
8240 return ret;
8241}
8242
816f8b86
SB		 8243static inline u64 get_estat64(tg3_stat64_t *val)
8244{
8245 return ((u64)val->high << 32) | ((u64)val->low);
8246}
8247
1da177e4
LT		 8248static unsigned long calc_crc_errors(struct tg3 *tp)
8249{
8250 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8251
8252 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8253 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8254 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8255 u32 val;
8256
f47c11ee 8257 spin_lock_bh(&tp->lock);
569a5df8
MC		 8258 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8259 tg3_writephy(tp, MII_TG3_TEST1,
8260 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8261 tg3_readphy(tp, 0x14, &val);
8262 } else
8263 val = 0;
f47c11ee 8264 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8265
8266 tp->phy_crc_errors += val;
8267
8268 return tp->phy_crc_errors;
8269 }
8270
8271 return get_stat64(&hw_stats->rx_fcs_errors);
8272}
8273
8274#define ESTAT_ADD(member) \
8275 estats->member = old_estats->member + \
816f8b86 8276 get_estat64(&hw_stats->member)
1da177e4
LT		 8277
8278static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8279{
8280 struct tg3_ethtool_stats *estats = &tp->estats;
8281 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8282 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8283
8284 if (!hw_stats)
8285 return old_estats;
8286
8287 ESTAT_ADD(rx_octets);
8288 ESTAT_ADD(rx_fragments);
8289 ESTAT_ADD(rx_ucast_packets);
8290 ESTAT_ADD(rx_mcast_packets);
8291 ESTAT_ADD(rx_bcast_packets);
8292 ESTAT_ADD(rx_fcs_errors);
8293 ESTAT_ADD(rx_align_errors);
8294 ESTAT_ADD(rx_xon_pause_rcvd);
8295 ESTAT_ADD(rx_xoff_pause_rcvd);
8296 ESTAT_ADD(rx_mac_ctrl_rcvd);
8297 ESTAT_ADD(rx_xoff_entered);
8298 ESTAT_ADD(rx_frame_too_long_errors);
8299 ESTAT_ADD(rx_jabbers);
8300 ESTAT_ADD(rx_undersize_packets);
8301 ESTAT_ADD(rx_in_length_errors);
8302 ESTAT_ADD(rx_out_length_errors);
8303 ESTAT_ADD(rx_64_or_less_octet_packets);
8304 ESTAT_ADD(rx_65_to_127_octet_packets);
8305 ESTAT_ADD(rx_128_to_255_octet_packets);
8306 ESTAT_ADD(rx_256_to_511_octet_packets);
8307 ESTAT_ADD(rx_512_to_1023_octet_packets);
8308 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8309 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8310 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8311 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8312 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8313
8314 ESTAT_ADD(tx_octets);
8315 ESTAT_ADD(tx_collisions);
8316 ESTAT_ADD(tx_xon_sent);
8317 ESTAT_ADD(tx_xoff_sent);
8318 ESTAT_ADD(tx_flow_control);
8319 ESTAT_ADD(tx_mac_errors);
8320 ESTAT_ADD(tx_single_collisions);
8321 ESTAT_ADD(tx_mult_collisions);
8322 ESTAT_ADD(tx_deferred);
8323 ESTAT_ADD(tx_excessive_collisions);
8324 ESTAT_ADD(tx_late_collisions);
8325 ESTAT_ADD(tx_collide_2times);
8326 ESTAT_ADD(tx_collide_3times);
8327 ESTAT_ADD(tx_collide_4times);
8328 ESTAT_ADD(tx_collide_5times);
8329 ESTAT_ADD(tx_collide_6times);
8330 ESTAT_ADD(tx_collide_7times);
8331 ESTAT_ADD(tx_collide_8times);
8332 ESTAT_ADD(tx_collide_9times);
8333 ESTAT_ADD(tx_collide_10times);
8334 ESTAT_ADD(tx_collide_11times);
8335 ESTAT_ADD(tx_collide_12times);
8336 ESTAT_ADD(tx_collide_13times);
8337 ESTAT_ADD(tx_collide_14times);
8338 ESTAT_ADD(tx_collide_15times);
8339 ESTAT_ADD(tx_ucast_packets);
8340 ESTAT_ADD(tx_mcast_packets);
8341 ESTAT_ADD(tx_bcast_packets);
8342 ESTAT_ADD(tx_carrier_sense_errors);
8343 ESTAT_ADD(tx_discards);
8344 ESTAT_ADD(tx_errors);
8345
8346 ESTAT_ADD(dma_writeq_full);
8347 ESTAT_ADD(dma_write_prioq_full);
8348 ESTAT_ADD(rxbds_empty);
8349 ESTAT_ADD(rx_discards);
8350 ESTAT_ADD(rx_errors);
8351 ESTAT_ADD(rx_threshold_hit);
8352
8353 ESTAT_ADD(dma_readq_full);
8354 ESTAT_ADD(dma_read_prioq_full);
8355 ESTAT_ADD(tx_comp_queue_full);
8356
8357 ESTAT_ADD(ring_set_send_prod_index);
8358 ESTAT_ADD(ring_status_update);
8359 ESTAT_ADD(nic_irqs);
8360 ESTAT_ADD(nic_avoided_irqs);
8361 ESTAT_ADD(nic_tx_threshold_hit);
8362
8363 return estats;
8364}
8365
8366static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8367{
8368 struct tg3 *tp = netdev_priv(dev);
8369 struct net_device_stats *stats = &tp->net_stats;
8370 struct net_device_stats *old_stats = &tp->net_stats_prev;
8371 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8372
8373 if (!hw_stats)
8374 return old_stats;
8375
8376 stats->rx_packets = old_stats->rx_packets +
8377 get_stat64(&hw_stats->rx_ucast_packets) +
8378 get_stat64(&hw_stats->rx_mcast_packets) +
8379 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8380
1da177e4
LT		 8381 stats->tx_packets = old_stats->tx_packets +
8382 get_stat64(&hw_stats->tx_ucast_packets) +
8383 get_stat64(&hw_stats->tx_mcast_packets) +
8384 get_stat64(&hw_stats->tx_bcast_packets);
8385
8386 stats->rx_bytes = old_stats->rx_bytes +
8387 get_stat64(&hw_stats->rx_octets);
8388 stats->tx_bytes = old_stats->tx_bytes +
8389 get_stat64(&hw_stats->tx_octets);
8390
8391 stats->rx_errors = old_stats->rx_errors +
4f63b877 8392 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8393 stats->tx_errors = old_stats->tx_errors +
8394 get_stat64(&hw_stats->tx_errors) +
8395 get_stat64(&hw_stats->tx_mac_errors) +
8396 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8397 get_stat64(&hw_stats->tx_discards);
8398
8399 stats->multicast = old_stats->multicast +
8400 get_stat64(&hw_stats->rx_mcast_packets);
8401 stats->collisions = old_stats->collisions +
8402 get_stat64(&hw_stats->tx_collisions);
8403
8404 stats->rx_length_errors = old_stats->rx_length_errors +
8405 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8406 get_stat64(&hw_stats->rx_undersize_packets);
8407
8408 stats->rx_over_errors = old_stats->rx_over_errors +
8409 get_stat64(&hw_stats->rxbds_empty);
8410 stats->rx_frame_errors = old_stats->rx_frame_errors +
8411 get_stat64(&hw_stats->rx_align_errors);
8412 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8413 get_stat64(&hw_stats->tx_discards);
8414 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8415 get_stat64(&hw_stats->tx_carrier_sense_errors);
8416
8417 stats->rx_crc_errors = old_stats->rx_crc_errors +
8418 calc_crc_errors(tp);
8419
4f63b877
JL		 8420 stats->rx_missed_errors = old_stats->rx_missed_errors +
8421 get_stat64(&hw_stats->rx_discards);
8422
1da177e4
LT		 8423 return stats;
8424}
8425
8426static inline u32 calc_crc(unsigned char *buf, int len)
8427{
8428 u32 reg;
8429 u32 tmp;
8430 int j, k;
8431
8432 reg = 0xffffffff;
8433
8434 for (j = 0; j < len; j++) {
8435 reg ^= buf[j];
8436
8437 for (k = 0; k < 8; k++) {
8438 tmp = reg & 0x01;
8439
8440 reg >>= 1;
8441
8442 if (tmp) {
8443 reg ^= 0xedb88320;
8444 }
8445 }
8446 }
8447
8448 return ~reg;
8449}
8450
8451static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8452{
8453 /* accept or reject all multicast frames */
8454 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8455 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8456 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8457 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8458}
8459
8460static void __tg3_set_rx_mode(struct net_device *dev)
8461{
8462 struct tg3 *tp = netdev_priv(dev);
8463 u32 rx_mode;
8464
8465 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8466 RX_MODE_KEEP_VLAN_TAG);
8467
8468 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8469 * flag clear.
8470 */
8471#if TG3_VLAN_TAG_USED
8472 if (!tp->vlgrp &&
8473 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8474 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8475#else
8476 /* By definition, VLAN is disabled always in this
8477 * case.
8478 */
8479 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8480 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8481#endif
8482
8483 if (dev->flags & IFF_PROMISC) {
8484 /* Promiscuous mode. */
8485 rx_mode |= RX_MODE_PROMISC;
8486 } else if (dev->flags & IFF_ALLMULTI) {
8487 /* Accept all multicast. */
8488 tg3_set_multi (tp, 1);
8489 } else if (dev->mc_count < 1) {
8490 /* Reject all multicast. */
8491 tg3_set_multi (tp, 0);
8492 } else {
8493 /* Accept one or more multicast(s). */
8494 struct dev_mc_list *mclist;
8495 unsigned int i;
8496 u32 mc_filter[4] = { 0, };
8497 u32 regidx;
8498 u32 bit;
8499 u32 crc;
8500
8501 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8502 i++, mclist = mclist->next) {
8503
8504 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8505 bit = ~crc & 0x7f;
8506 regidx = (bit & 0x60) >> 5;
8507 bit &= 0x1f;
8508 mc_filter[regidx] |= (1 << bit);
8509 }
8510
8511 tw32(MAC_HASH_REG_0, mc_filter[0]);
8512 tw32(MAC_HASH_REG_1, mc_filter[1]);
8513 tw32(MAC_HASH_REG_2, mc_filter[2]);
8514 tw32(MAC_HASH_REG_3, mc_filter[3]);
8515 }
8516
8517 if (rx_mode != tp->rx_mode) {
8518 tp->rx_mode = rx_mode;
8519 tw32_f(MAC_RX_MODE, rx_mode);
8520 udelay(10);
8521 }
8522}
8523
8524static void tg3_set_rx_mode(struct net_device *dev)
8525{
8526 struct tg3 *tp = netdev_priv(dev);
8527
e75f7c90
MC		 8528 if (!netif_running(dev))
8529 return;
8530
f47c11ee 8531 tg3_full_lock(tp, 0);
1da177e4 8532 __tg3_set_rx_mode(dev);
f47c11ee 8533 tg3_full_unlock(tp);
1da177e4
LT		 8534}
8535
8536#define TG3_REGDUMP_LEN (32 * 1024)
8537
8538static int tg3_get_regs_len(struct net_device *dev)
8539{
8540 return TG3_REGDUMP_LEN;
8541}
8542
8543static void tg3_get_regs(struct net_device *dev,
8544 struct ethtool_regs *regs, void *_p)
8545{
8546 u32 *p = _p;
8547 struct tg3 *tp = netdev_priv(dev);
8548 u8 *orig_p = _p;
8549 int i;
8550
8551 regs->version = 0;
8552
8553 memset(p, 0, TG3_REGDUMP_LEN);
8554
bc1c7567
MC		 8555 if (tp->link_config.phy_is_low_power)
8556 return;
8557
f47c11ee 8558 tg3_full_lock(tp, 0);
1da177e4
LT		 8559
8560#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8561#define GET_REG32_LOOP(base,len) \
8562do { p = (u32 *)(orig_p + (base)); \
8563 for (i = 0; i < len; i += 4) \
8564 __GET_REG32((base) + i); \
8565} while (0)
8566#define GET_REG32_1(reg) \
8567do { p = (u32 *)(orig_p + (reg)); \
8568 __GET_REG32((reg)); \
8569} while (0)
8570
8571 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8572 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8573 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8574 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8575 GET_REG32_1(SNDDATAC_MODE);
8576 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8577 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8578 GET_REG32_1(SNDBDC_MODE);
8579 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8580 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8581 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8582 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8583 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8584 GET_REG32_1(RCVDCC_MODE);
8585 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8586 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8587 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8588 GET_REG32_1(MBFREE_MODE);
8589 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8590 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8591 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8592 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8593 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8594 GET_REG32_1(RX_CPU_MODE);
8595 GET_REG32_1(RX_CPU_STATE);
8596 GET_REG32_1(RX_CPU_PGMCTR);
8597 GET_REG32_1(RX_CPU_HWBKPT);
8598 GET_REG32_1(TX_CPU_MODE);
8599 GET_REG32_1(TX_CPU_STATE);
8600 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8601 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8602 GET_REG32_LOOP(FTQ_RESET, 0x120);
8603 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8604 GET_REG32_1(DMAC_MODE);
8605 GET_REG32_LOOP(GRC_MODE, 0x4c);
8606 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8607 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8608
8609#undef __GET_REG32
8610#undef GET_REG32_LOOP
8611#undef GET_REG32_1
8612
f47c11ee 8613 tg3_full_unlock(tp);
1da177e4
LT		 8614}
8615
8616static int tg3_get_eeprom_len(struct net_device *dev)
8617{
8618 struct tg3 *tp = netdev_priv(dev);
8619
8620 return tp->nvram_size;
8621}
8622
1da177e4
LT		 8623static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8624{
8625 struct tg3 *tp = netdev_priv(dev);
8626 int ret;
8627 u8 *pd;
b9fc7dc5 8628 u32 i, offset, len, b_offset, b_count;
a9dc529d 8629 __be32 val;
1da177e4 8630
df259d8c
MC		 8631 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8632 return -EINVAL;
8633
bc1c7567
MC		 8634 if (tp->link_config.phy_is_low_power)
8635 return -EAGAIN;
8636
1da177e4
LT		 8637 offset = eeprom->offset;
8638 len = eeprom->len;
8639 eeprom->len = 0;
8640
8641 eeprom->magic = TG3_EEPROM_MAGIC;
8642
8643 if (offset & 3) {
8644 /* adjustments to start on required 4 byte boundary */
8645 b_offset = offset & 3;
8646 b_count = 4 - b_offset;
8647 if (b_count > len) {
8648 /* i.e. offset=1 len=2 */
8649 b_count = len;
8650 }
a9dc529d 8651 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8652 if (ret)
8653 return ret;
1da177e4
LT		 8654 memcpy(data, ((char*)&val) + b_offset, b_count);
8655 len -= b_count;
8656 offset += b_count;
8657 eeprom->len += b_count;
8658 }
8659
8660 /* read bytes upto the last 4 byte boundary */
8661 pd = &data[eeprom->len];
8662 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8663 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8664 if (ret) {
8665 eeprom->len += i;
8666 return ret;
8667 }
1da177e4
LT		 8668 memcpy(pd + i, &val, 4);
8669 }
8670 eeprom->len += i;
8671
8672 if (len & 3) {
8673 /* read last bytes not ending on 4 byte boundary */
8674 pd = &data[eeprom->len];
8675 b_count = len & 3;
8676 b_offset = offset + len - b_count;
a9dc529d 8677 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8678 if (ret)
8679 return ret;
b9fc7dc5 8680 memcpy(pd, &val, b_count);
1da177e4
LT		 8681 eeprom->len += b_count;
8682 }
8683 return 0;
8684}
8685
6aa20a22 8686static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8687
8688static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8689{
8690 struct tg3 *tp = netdev_priv(dev);
8691 int ret;
b9fc7dc5 8692 u32 offset, len, b_offset, odd_len;
1da177e4 8693 u8 *buf;
a9dc529d 8694 __be32 start, end;
1da177e4 8695
bc1c7567
MC		 8696 if (tp->link_config.phy_is_low_power)
8697 return -EAGAIN;
8698
df259d8c
MC		 8699 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8700 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 8701 return -EINVAL;
8702
8703 offset = eeprom->offset;
8704 len = eeprom->len;
8705
8706 if ((b_offset = (offset & 3))) {
8707 /* adjustments to start on required 4 byte boundary */
a9dc529d 8708 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8709 if (ret)
8710 return ret;
1da177e4
LT		 8711 len += b_offset;
8712 offset &= ~3;
1c8594b4
MC		 8713 if (len < 4)
8714 len = 4;
1da177e4
LT		 8715 }
8716
8717 odd_len = 0;
1c8594b4 8718 if (len & 3) {
1da177e4
LT		 8719 /* adjustments to end on required 4 byte boundary */
8720 odd_len = 1;
8721 len = (len + 3) & ~3;
a9dc529d 8722 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8723 if (ret)
8724 return ret;
1da177e4
LT		 8725 }
8726
8727 buf = data;
8728 if (b_offset || odd_len) {
8729 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8730 if (!buf)
1da177e4
LT		 8731 return -ENOMEM;
8732 if (b_offset)
8733 memcpy(buf, &start, 4);
8734 if (odd_len)
8735 memcpy(buf+len-4, &end, 4);
8736 memcpy(buf + b_offset, data, eeprom->len);
8737 }
8738
8739 ret = tg3_nvram_write_block(tp, offset, len, buf);
8740
8741 if (buf != data)
8742 kfree(buf);
8743
8744 return ret;
8745}
8746
8747static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8748{
b02fd9e3
MC		 8749 struct tg3 *tp = netdev_priv(dev);
8750
8751 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8752 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8753 return -EAGAIN;
298cf9be 8754 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8755 }
6aa20a22 8756
1da177e4
LT		 8757 cmd->supported = (SUPPORTED_Autoneg);
8758
8759 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8760 cmd->supported |= (SUPPORTED_1000baseT_Half |
8761 SUPPORTED_1000baseT_Full);
8762
ef348144 8763 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8764 cmd->supported |= (SUPPORTED_100baseT_Half |
8765 SUPPORTED_100baseT_Full |
8766 SUPPORTED_10baseT_Half |
8767 SUPPORTED_10baseT_Full |
3bebab59 8768 SUPPORTED_TP);
ef348144
KK		 8769 cmd->port = PORT_TP;
8770 } else {
1da177e4 8771 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8772 cmd->port = PORT_FIBRE;
8773 }
6aa20a22 8774
1da177e4
LT		 8775 cmd->advertising = tp->link_config.advertising;
8776 if (netif_running(dev)) {
8777 cmd->speed = tp->link_config.active_speed;
8778 cmd->duplex = tp->link_config.active_duplex;
8779 }
1da177e4 8780 cmd->phy_address = PHY_ADDR;
7e5856bd 8781 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8782 cmd->autoneg = tp->link_config.autoneg;
8783 cmd->maxtxpkt = 0;
8784 cmd->maxrxpkt = 0;
8785 return 0;
8786}
6aa20a22 8787
1da177e4
LT		 8788static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8789{
8790 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8791
b02fd9e3
MC		 8792 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8793 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8794 return -EAGAIN;
298cf9be 8795 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8796 }
8797
7e5856bd
MC		 8798 if (cmd->autoneg != AUTONEG_ENABLE &&
8799 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8800 return -EINVAL;
7e5856bd
MC		 8801
8802 if (cmd->autoneg == AUTONEG_DISABLE &&
8803 cmd->duplex != DUPLEX_FULL &&
8804 cmd->duplex != DUPLEX_HALF)
37ff238d 8805 return -EINVAL;
1da177e4 8806
7e5856bd
MC		 8807 if (cmd->autoneg == AUTONEG_ENABLE) {
8808 u32 mask = ADVERTISED_Autoneg |
8809 ADVERTISED_Pause |
8810 ADVERTISED_Asym_Pause;
8811
8812 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8813 mask |= ADVERTISED_1000baseT_Half |
8814 ADVERTISED_1000baseT_Full;
8815
8816 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8817 mask |= ADVERTISED_100baseT_Half |
8818 ADVERTISED_100baseT_Full |
8819 ADVERTISED_10baseT_Half |
8820 ADVERTISED_10baseT_Full |
8821 ADVERTISED_TP;
8822 else
8823 mask |= ADVERTISED_FIBRE;
8824
8825 if (cmd->advertising & ~mask)
8826 return -EINVAL;
8827
8828 mask &= (ADVERTISED_1000baseT_Half |
8829 ADVERTISED_1000baseT_Full |
8830 ADVERTISED_100baseT_Half |
8831 ADVERTISED_100baseT_Full |
8832 ADVERTISED_10baseT_Half |
8833 ADVERTISED_10baseT_Full);
8834
8835 cmd->advertising &= mask;
8836 } else {
8837 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8838 if (cmd->speed != SPEED_1000)
8839 return -EINVAL;
8840
8841 if (cmd->duplex != DUPLEX_FULL)
8842 return -EINVAL;
8843 } else {
8844 if (cmd->speed != SPEED_100 &&
8845 cmd->speed != SPEED_10)
8846 return -EINVAL;
8847 }
8848 }
8849
f47c11ee 8850 tg3_full_lock(tp, 0);
1da177e4
LT		 8851
8852 tp->link_config.autoneg = cmd->autoneg;
8853 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8854 tp->link_config.advertising = (cmd->advertising |
8855 ADVERTISED_Autoneg);
1da177e4
LT		 8856 tp->link_config.speed = SPEED_INVALID;
8857 tp->link_config.duplex = DUPLEX_INVALID;
8858 } else {
8859 tp->link_config.advertising = 0;
8860 tp->link_config.speed = cmd->speed;
8861 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8862 }
6aa20a22 8863
24fcad6b
MC		 8864 tp->link_config.orig_speed = tp->link_config.speed;
8865 tp->link_config.orig_duplex = tp->link_config.duplex;
8866 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8867
1da177e4
LT		 8868 if (netif_running(dev))
8869 tg3_setup_phy(tp, 1);
8870
f47c11ee 8871 tg3_full_unlock(tp);
6aa20a22 8872
1da177e4
LT		 8873 return 0;
8874}
6aa20a22 8875
1da177e4
LT		 8876static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8877{
8878 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8879
1da177e4
LT		 8880 strcpy(info->driver, DRV_MODULE_NAME);
8881 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8882 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8883 strcpy(info->bus_info, pci_name(tp->pdev));
8884}
6aa20a22 8885
1da177e4
LT		 8886static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8887{
8888 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8889
12dac075
RW		 8890 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8891 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 8892 wol->supported = WAKE_MAGIC;
8893 else
8894 wol->supported = 0;
1da177e4 8895 wol->wolopts = 0;
05ac4cb7
MC		 8896 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8897 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 8898 wol->wolopts = WAKE_MAGIC;
8899 memset(&wol->sopass, 0, sizeof(wol->sopass));
8900}
6aa20a22 8901
1da177e4
LT		 8902static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8903{
8904 struct tg3 *tp = netdev_priv(dev);
12dac075 8905 struct device *dp = &tp->pdev->dev;
6aa20a22 8906
1da177e4
LT		 8907 if (wol->wolopts & ~WAKE_MAGIC)
8908 return -EINVAL;
8909 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 8910 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 8911 return -EINVAL;
6aa20a22 8912
f47c11ee 8913 spin_lock_bh(&tp->lock);
12dac075 8914 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 8915 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8916 device_set_wakeup_enable(dp, true);
8917 } else {
1da177e4 8918 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 8919 device_set_wakeup_enable(dp, false);
8920 }
f47c11ee 8921 spin_unlock_bh(&tp->lock);
6aa20a22 8922
1da177e4
LT		 8923 return 0;
8924}
6aa20a22 8925
1da177e4
LT		 8926static u32 tg3_get_msglevel(struct net_device *dev)
8927{
8928 struct tg3 *tp = netdev_priv(dev);
8929 return tp->msg_enable;
8930}
6aa20a22 8931
1da177e4
LT		 8932static void tg3_set_msglevel(struct net_device *dev, u32 value)
8933{
8934 struct tg3 *tp = netdev_priv(dev);
8935 tp->msg_enable = value;
8936}
6aa20a22 8937
1da177e4
LT		 8938static int tg3_set_tso(struct net_device *dev, u32 value)
8939{
8940 struct tg3 *tp = netdev_priv(dev);
8941
8942 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8943 if (value)
8944 return -EINVAL;
8945 return 0;
8946 }
027455ad
MC		 8947 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8948 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 8949 if (value) {
b0026624 8950 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 8951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8952 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8953 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 8954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 8956 dev->features |= NETIF_F_TSO_ECN;
8957 } else
8958 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 8959 }
1da177e4
LT		 8960 return ethtool_op_set_tso(dev, value);
8961}
6aa20a22 8962
1da177e4
LT		 8963static int tg3_nway_reset(struct net_device *dev)
8964{
8965 struct tg3 *tp = netdev_priv(dev);
1da177e4 8966 int r;
6aa20a22 8967
1da177e4
LT		 8968 if (!netif_running(dev))
8969 return -EAGAIN;
8970
c94e3941
MC		 8971 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8972 return -EINVAL;
8973
b02fd9e3
MC		 8974 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8975 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8976 return -EAGAIN;
298cf9be 8977 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 8978 } else {
8979 u32 bmcr;
8980
8981 spin_lock_bh(&tp->lock);
8982 r = -EINVAL;
8983 tg3_readphy(tp, MII_BMCR, &bmcr);
8984 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8985 ((bmcr & BMCR_ANENABLE) ||
8986 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8987 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8988 BMCR_ANENABLE);
8989 r = 0;
8990 }
8991 spin_unlock_bh(&tp->lock);
1da177e4 8992 }
6aa20a22 8993
1da177e4
LT		 8994 return r;
8995}
6aa20a22 8996
1da177e4
LT		 8997static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8998{
8999 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9000
1da177e4
LT		 9001 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9002 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9003 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9004 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9005 else
9006 ering->rx_jumbo_max_pending = 0;
9007
9008 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9009
9010 ering->rx_pending = tp->rx_pending;
9011 ering->rx_mini_pending = 0;
4f81c32b
MC		 9012 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9013 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9014 else
9015 ering->rx_jumbo_pending = 0;
9016
1da177e4
LT		 9017 ering->tx_pending = tp->tx_pending;
9018}
6aa20a22 9019
1da177e4
LT		 9020static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9021{
9022 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 9023 int irq_sync = 0, err = 0;
6aa20a22 9024
1da177e4
LT		 9025 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9026 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9027 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9028 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9029 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9030 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9031 return -EINVAL;
6aa20a22 9032
bbe832c0 9033 if (netif_running(dev)) {
b02fd9e3 9034 tg3_phy_stop(tp);
1da177e4 9035 tg3_netif_stop(tp);
bbe832c0
MC		 9036 irq_sync = 1;
9037 }
1da177e4 9038
bbe832c0 9039 tg3_full_lock(tp, irq_sync);
6aa20a22 9040
1da177e4
LT		 9041 tp->rx_pending = ering->rx_pending;
9042
9043 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9044 tp->rx_pending > 63)
9045 tp->rx_pending = 63;
9046 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9047 tp->tx_pending = ering->tx_pending;
9048
9049 if (netif_running(dev)) {
944d980e 9050 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9051 err = tg3_restart_hw(tp, 1);
9052 if (!err)
9053 tg3_netif_start(tp);
1da177e4
LT		 9054 }
9055
f47c11ee 9056 tg3_full_unlock(tp);
6aa20a22 9057
b02fd9e3
MC		 9058 if (irq_sync && !err)
9059 tg3_phy_start(tp);
9060
b9ec6c1b 9061 return err;
1da177e4 9062}
6aa20a22 9063
1da177e4
LT		 9064static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9065{
9066 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9067
1da177e4 9068 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9069
e18ce346 9070 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9071 epause->rx_pause = 1;
9072 else
9073 epause->rx_pause = 0;
9074
e18ce346 9075 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9076 epause->tx_pause = 1;
9077 else
9078 epause->tx_pause = 0;
1da177e4 9079}
6aa20a22 9080
1da177e4
LT		 9081static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9082{
9083 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9084 int err = 0;
6aa20a22 9085
b02fd9e3
MC		 9086 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9087 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9088 return -EAGAIN;
1da177e4 9089
b02fd9e3
MC		 9090 if (epause->autoneg) {
9091 u32 newadv;
9092 struct phy_device *phydev;
f47c11ee 9093
298cf9be 9094 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9095
b02fd9e3
MC		 9096 if (epause->rx_pause) {
9097 if (epause->tx_pause)
9098 newadv = ADVERTISED_Pause;
9099 else
9100 newadv = ADVERTISED_Pause |
9101 ADVERTISED_Asym_Pause;
9102 } else if (epause->tx_pause) {
9103 newadv = ADVERTISED_Asym_Pause;
9104 } else
9105 newadv = 0;
9106
9107 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9108 u32 oldadv = phydev->advertising &
9109 (ADVERTISED_Pause |
9110 ADVERTISED_Asym_Pause);
9111 if (oldadv != newadv) {
9112 phydev->advertising &=
9113 ~(ADVERTISED_Pause |
9114 ADVERTISED_Asym_Pause);
9115 phydev->advertising |= newadv;
9116 err = phy_start_aneg(phydev);
9117 }
9118 } else {
9119 tp->link_config.advertising &=
9120 ~(ADVERTISED_Pause |
9121 ADVERTISED_Asym_Pause);
9122 tp->link_config.advertising |= newadv;
9123 }
9124 } else {
9125 if (epause->rx_pause)
e18ce346 9126 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9127 else
e18ce346 9128 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9129
b02fd9e3 9130 if (epause->tx_pause)
e18ce346 9131 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9132 else
e18ce346 9133 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9134
9135 if (netif_running(dev))
9136 tg3_setup_flow_control(tp, 0, 0);
9137 }
9138 } else {
9139 int irq_sync = 0;
9140
9141 if (netif_running(dev)) {
9142 tg3_netif_stop(tp);
9143 irq_sync = 1;
9144 }
9145
9146 tg3_full_lock(tp, irq_sync);
9147
9148 if (epause->autoneg)
9149 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9150 else
9151 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9152 if (epause->rx_pause)
e18ce346 9153 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9154 else
e18ce346 9155 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9156 if (epause->tx_pause)
e18ce346 9157 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9158 else
e18ce346 9159 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9160
9161 if (netif_running(dev)) {
9162 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9163 err = tg3_restart_hw(tp, 1);
9164 if (!err)
9165 tg3_netif_start(tp);
9166 }
9167
9168 tg3_full_unlock(tp);
9169 }
6aa20a22 9170
b9ec6c1b 9171 return err;
1da177e4 9172}
6aa20a22 9173
1da177e4
LT		 9174static u32 tg3_get_rx_csum(struct net_device *dev)
9175{
9176 struct tg3 *tp = netdev_priv(dev);
9177 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9178}
6aa20a22 9179
1da177e4
LT		 9180static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9181{
9182 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9183
1da177e4
LT		 9184 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9185 if (data != 0)
9186 return -EINVAL;
9187 return 0;
9188 }
6aa20a22 9189
f47c11ee 9190 spin_lock_bh(&tp->lock);
1da177e4
LT		 9191 if (data)
9192 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9193 else
9194 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9195 spin_unlock_bh(&tp->lock);
6aa20a22 9196
1da177e4
LT		 9197 return 0;
9198}
6aa20a22 9199
1da177e4
LT		 9200static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9201{
9202 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9203
1da177e4
LT		 9204 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9205 if (data != 0)
9206 return -EINVAL;
9207 return 0;
9208 }
6aa20a22 9209
321d32a0 9210 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9211 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9212 else
9c27dbdf 9213 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9214
9215 return 0;
9216}
9217
b9f2c044 9218static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9219{
b9f2c044
JG		 9220 switch (sset) {
9221 case ETH_SS_TEST:
9222 return TG3_NUM_TEST;
9223 case ETH_SS_STATS:
9224 return TG3_NUM_STATS;
9225 default:
9226 return -EOPNOTSUPP;
9227 }
4cafd3f5
MC		 9228}
9229
1da177e4
LT		 9230static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9231{
9232 switch (stringset) {
9233 case ETH_SS_STATS:
9234 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9235 break;
4cafd3f5
MC		 9236 case ETH_SS_TEST:
9237 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9238 break;
1da177e4
LT		 9239 default:
9240 WARN_ON(1); /* we need a WARN() */
9241 break;
9242 }
9243}
9244
4009a93d
MC		 9245static int tg3_phys_id(struct net_device *dev, u32 data)
9246{
9247 struct tg3 *tp = netdev_priv(dev);
9248 int i;
9249
9250 if (!netif_running(tp->dev))
9251 return -EAGAIN;
9252
9253 if (data == 0)
759afc31 9254 data = UINT_MAX / 2;
4009a93d
MC		 9255
9256 for (i = 0; i < (data * 2); i++) {
9257 if ((i % 2) == 0)
9258 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9259 LED_CTRL_1000MBPS_ON |
9260 LED_CTRL_100MBPS_ON |
9261 LED_CTRL_10MBPS_ON |
9262 LED_CTRL_TRAFFIC_OVERRIDE |
9263 LED_CTRL_TRAFFIC_BLINK |
9264 LED_CTRL_TRAFFIC_LED);
6aa20a22 9265
4009a93d
MC		 9266 else
9267 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9268 LED_CTRL_TRAFFIC_OVERRIDE);
9269
9270 if (msleep_interruptible(500))
9271 break;
9272 }
9273 tw32(MAC_LED_CTRL, tp->led_ctrl);
9274 return 0;
9275}
9276
1da177e4
LT		 9277static void tg3_get_ethtool_stats (struct net_device *dev,
9278 struct ethtool_stats *estats, u64 *tmp_stats)
9279{
9280 struct tg3 *tp = netdev_priv(dev);
9281 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9282}
9283
566f86ad 9284#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9285#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9286#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9287#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9288#define NVRAM_SELFBOOT_HW_SIZE 0x20
9289#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9290
9291static int tg3_test_nvram(struct tg3 *tp)
9292{
b9fc7dc5 9293 u32 csum, magic;
a9dc529d 9294 __be32 *buf;
ab0049b4 9295 int i, j, k, err = 0, size;
566f86ad 9296
df259d8c
MC		 9297 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9298 return 0;
9299
e4f34110 9300 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9301 return -EIO;
9302
1b27777a
MC		 9303 if (magic == TG3_EEPROM_MAGIC)
9304 size = NVRAM_TEST_SIZE;
b16250e3 9305 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9306 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9307 TG3_EEPROM_SB_FORMAT_1) {
9308 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9309 case TG3_EEPROM_SB_REVISION_0:
9310 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9311 break;
9312 case TG3_EEPROM_SB_REVISION_2:
9313 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9314 break;
9315 case TG3_EEPROM_SB_REVISION_3:
9316 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9317 break;
9318 default:
9319 return 0;
9320 }
9321 } else
1b27777a 9322 return 0;
b16250e3
MC		 9323 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9324 size = NVRAM_SELFBOOT_HW_SIZE;
9325 else
1b27777a
MC		 9326 return -EIO;
9327
9328 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9329 if (buf == NULL)
9330 return -ENOMEM;
9331
1b27777a
MC		 9332 err = -EIO;
9333 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9334 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9335 if (err)
566f86ad 9336 break;
566f86ad 9337 }
1b27777a 9338 if (i < size)
566f86ad
MC		 9339 goto out;
9340
1b27777a 9341 /* Selfboot format */
a9dc529d 9342 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9343 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9344 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9345 u8 *buf8 = (u8 *) buf, csum8 = 0;
9346
b9fc7dc5 9347 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9348 TG3_EEPROM_SB_REVISION_2) {
9349 /* For rev 2, the csum doesn't include the MBA. */
9350 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9351 csum8 += buf8[i];
9352 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9353 csum8 += buf8[i];
9354 } else {
9355 for (i = 0; i < size; i++)
9356 csum8 += buf8[i];
9357 }
1b27777a 9358
ad96b485
AB		 9359 if (csum8 == 0) {
9360 err = 0;
9361 goto out;
9362 }
9363
9364 err = -EIO;
9365 goto out;
1b27777a 9366 }
566f86ad 9367
b9fc7dc5 9368 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9369 TG3_EEPROM_MAGIC_HW) {
9370 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9371 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9372 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9373
9374 /* Separate the parity bits and the data bytes. */
9375 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9376 if ((i == 0) || (i == 8)) {
9377 int l;
9378 u8 msk;
9379
9380 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9381 parity[k++] = buf8[i] & msk;
9382 i++;
9383 }
9384 else if (i == 16) {
9385 int l;
9386 u8 msk;
9387
9388 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9389 parity[k++] = buf8[i] & msk;
9390 i++;
9391
9392 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9393 parity[k++] = buf8[i] & msk;
9394 i++;
9395 }
9396 data[j++] = buf8[i];
9397 }
9398
9399 err = -EIO;
9400 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9401 u8 hw8 = hweight8(data[i]);
9402
9403 if ((hw8 & 0x1) && parity[i])
9404 goto out;
9405 else if (!(hw8 & 0x1) && !parity[i])
9406 goto out;
9407 }
9408 err = 0;
9409 goto out;
9410 }
9411
566f86ad
MC		 9412 /* Bootstrap checksum at offset 0x10 */
9413 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9414 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9415 goto out;
9416
9417 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9418 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9419 if (csum != be32_to_cpu(buf[0xfc/4]))
9420 goto out;
566f86ad
MC		 9421
9422 err = 0;
9423
9424out:
9425 kfree(buf);
9426 return err;
9427}
9428
ca43007a
MC		 9429#define TG3_SERDES_TIMEOUT_SEC 2
9430#define TG3_COPPER_TIMEOUT_SEC 6
9431
9432static int tg3_test_link(struct tg3 *tp)
9433{
9434 int i, max;
9435
9436 if (!netif_running(tp->dev))
9437 return -ENODEV;
9438
4c987487 9439 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9440 max = TG3_SERDES_TIMEOUT_SEC;
9441 else
9442 max = TG3_COPPER_TIMEOUT_SEC;
9443
9444 for (i = 0; i < max; i++) {
9445 if (netif_carrier_ok(tp->dev))
9446 return 0;
9447
9448 if (msleep_interruptible(1000))
9449 break;
9450 }
9451
9452 return -EIO;
9453}
9454
a71116d1 9455/* Only test the commonly used registers */
30ca3e37 9456static int tg3_test_registers(struct tg3 *tp)
a71116d1 9457{
b16250e3 9458 int i, is_5705, is_5750;
a71116d1
MC		 9459 u32 offset, read_mask, write_mask, val, save_val, read_val;
9460 static struct {
9461 u16 offset;
9462 u16 flags;
9463#define TG3_FL_5705 0x1
9464#define TG3_FL_NOT_5705 0x2
9465#define TG3_FL_NOT_5788 0x4
b16250e3 9466#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9467 u32 read_mask;
9468 u32 write_mask;
9469 } reg_tbl[] = {
9470 /* MAC Control Registers */
9471 { MAC_MODE, TG3_FL_NOT_5705,
9472 0x00000000, 0x00ef6f8c },
9473 { MAC_MODE, TG3_FL_5705,
9474 0x00000000, 0x01ef6b8c },
9475 { MAC_STATUS, TG3_FL_NOT_5705,
9476 0x03800107, 0x00000000 },
9477 { MAC_STATUS, TG3_FL_5705,
9478 0x03800100, 0x00000000 },
9479 { MAC_ADDR_0_HIGH, 0x0000,
9480 0x00000000, 0x0000ffff },
9481 { MAC_ADDR_0_LOW, 0x0000,
9482 0x00000000, 0xffffffff },
9483 { MAC_RX_MTU_SIZE, 0x0000,
9484 0x00000000, 0x0000ffff },
9485 { MAC_TX_MODE, 0x0000,
9486 0x00000000, 0x00000070 },
9487 { MAC_TX_LENGTHS, 0x0000,
9488 0x00000000, 0x00003fff },
9489 { MAC_RX_MODE, TG3_FL_NOT_5705,
9490 0x00000000, 0x000007fc },
9491 { MAC_RX_MODE, TG3_FL_5705,
9492 0x00000000, 0x000007dc },
9493 { MAC_HASH_REG_0, 0x0000,
9494 0x00000000, 0xffffffff },
9495 { MAC_HASH_REG_1, 0x0000,
9496 0x00000000, 0xffffffff },
9497 { MAC_HASH_REG_2, 0x0000,
9498 0x00000000, 0xffffffff },
9499 { MAC_HASH_REG_3, 0x0000,
9500 0x00000000, 0xffffffff },
9501
9502 /* Receive Data and Receive BD Initiator Control Registers. */
9503 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9504 0x00000000, 0xffffffff },
9505 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9506 0x00000000, 0xffffffff },
9507 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9508 0x00000000, 0x00000003 },
9509 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9510 0x00000000, 0xffffffff },
9511 { RCVDBDI_STD_BD+0, 0x0000,
9512 0x00000000, 0xffffffff },
9513 { RCVDBDI_STD_BD+4, 0x0000,
9514 0x00000000, 0xffffffff },
9515 { RCVDBDI_STD_BD+8, 0x0000,
9516 0x00000000, 0xffff0002 },
9517 { RCVDBDI_STD_BD+0xc, 0x0000,
9518 0x00000000, 0xffffffff },
6aa20a22 9519
a71116d1
MC		 9520 /* Receive BD Initiator Control Registers. */
9521 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9522 0x00000000, 0xffffffff },
9523 { RCVBDI_STD_THRESH, TG3_FL_5705,
9524 0x00000000, 0x000003ff },
9525 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9526 0x00000000, 0xffffffff },
6aa20a22 9527
a71116d1
MC		 9528 /* Host Coalescing Control Registers. */
9529 { HOSTCC_MODE, TG3_FL_NOT_5705,
9530 0x00000000, 0x00000004 },
9531 { HOSTCC_MODE, TG3_FL_5705,
9532 0x00000000, 0x000000f6 },
9533 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9534 0x00000000, 0xffffffff },
9535 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9536 0x00000000, 0x000003ff },
9537 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9538 0x00000000, 0xffffffff },
9539 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9540 0x00000000, 0x000003ff },
9541 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9542 0x00000000, 0xffffffff },
9543 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9544 0x00000000, 0x000000ff },
9545 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9546 0x00000000, 0xffffffff },
9547 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9548 0x00000000, 0x000000ff },
9549 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9550 0x00000000, 0xffffffff },
9551 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9552 0x00000000, 0xffffffff },
9553 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9554 0x00000000, 0xffffffff },
9555 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9556 0x00000000, 0x000000ff },
9557 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9558 0x00000000, 0xffffffff },
9559 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9560 0x00000000, 0x000000ff },
9561 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9562 0x00000000, 0xffffffff },
9563 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9564 0x00000000, 0xffffffff },
9565 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9566 0x00000000, 0xffffffff },
9567 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9568 0x00000000, 0xffffffff },
9569 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9570 0x00000000, 0xffffffff },
9571 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9572 0xffffffff, 0x00000000 },
9573 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9574 0xffffffff, 0x00000000 },
9575
9576 /* Buffer Manager Control Registers. */
b16250e3 9577 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9578 0x00000000, 0x007fff80 },
b16250e3 9579 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9580 0x00000000, 0x007fffff },
9581 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9582 0x00000000, 0x0000003f },
9583 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9584 0x00000000, 0x000001ff },
9585 { BUFMGR_MB_HIGH_WATER, 0x0000,
9586 0x00000000, 0x000001ff },
9587 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9588 0xffffffff, 0x00000000 },
9589 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9590 0xffffffff, 0x00000000 },
6aa20a22 9591
a71116d1
MC		 9592 /* Mailbox Registers */
9593 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9594 0x00000000, 0x000001ff },
9595 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9596 0x00000000, 0x000001ff },
9597 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9598 0x00000000, 0x000007ff },
9599 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9600 0x00000000, 0x000001ff },
9601
9602 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9603 };
9604
b16250e3
MC		 9605 is_5705 = is_5750 = 0;
9606 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9607 is_5705 = 1;
b16250e3
MC		 9608 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9609 is_5750 = 1;
9610 }
a71116d1
MC		 9611
9612 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9613 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9614 continue;
9615
9616 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9617 continue;
9618
9619 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9620 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9621 continue;
9622
b16250e3
MC		 9623 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9624 continue;
9625
a71116d1
MC		 9626 offset = (u32) reg_tbl[i].offset;
9627 read_mask = reg_tbl[i].read_mask;
9628 write_mask = reg_tbl[i].write_mask;
9629
9630 /* Save the original register content */
9631 save_val = tr32(offset);
9632
9633 /* Determine the read-only value. */
9634 read_val = save_val & read_mask;
9635
9636 /* Write zero to the register, then make sure the read-only bits
9637 * are not changed and the read/write bits are all zeros.
9638 */
9639 tw32(offset, 0);
9640
9641 val = tr32(offset);
9642
9643 /* Test the read-only and read/write bits. */
9644 if (((val & read_mask) != read_val) || (val & write_mask))
9645 goto out;
9646
9647 /* Write ones to all the bits defined by RdMask and WrMask, then
9648 * make sure the read-only bits are not changed and the
9649 * read/write bits are all ones.
9650 */
9651 tw32(offset, read_mask | write_mask);
9652
9653 val = tr32(offset);
9654
9655 /* Test the read-only bits. */
9656 if ((val & read_mask) != read_val)
9657 goto out;
9658
9659 /* Test the read/write bits. */
9660 if ((val & write_mask) != write_mask)
9661 goto out;
9662
9663 tw32(offset, save_val);
9664 }
9665
9666 return 0;
9667
9668out:
9f88f29f
MC		 9669 if (netif_msg_hw(tp))
9670 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9671 offset);
a71116d1
MC		 9672 tw32(offset, save_val);
9673 return -EIO;
9674}
9675
7942e1db
MC		 9676static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9677{
f71e1309 9678 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9679 int i;
9680 u32 j;
9681
e9edda69 9682 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9683 for (j = 0; j < len; j += 4) {
9684 u32 val;
9685
9686 tg3_write_mem(tp, offset + j, test_pattern[i]);
9687 tg3_read_mem(tp, offset + j, &val);
9688 if (val != test_pattern[i])
9689 return -EIO;
9690 }
9691 }
9692 return 0;
9693}
9694
9695static int tg3_test_memory(struct tg3 *tp)
9696{
9697 static struct mem_entry {
9698 u32 offset;
9699 u32 len;
9700 } mem_tbl_570x[] = {
38690194 9701 { 0x00000000, 0x00b50},
7942e1db
MC		 9702 { 0x00002000, 0x1c000},
9703 { 0xffffffff, 0x00000}
9704 }, mem_tbl_5705[] = {
9705 { 0x00000100, 0x0000c},
9706 { 0x00000200, 0x00008},
7942e1db
MC		 9707 { 0x00004000, 0x00800},
9708 { 0x00006000, 0x01000},
9709 { 0x00008000, 0x02000},
9710 { 0x00010000, 0x0e000},
9711 { 0xffffffff, 0x00000}
79f4d13a
MC		 9712 }, mem_tbl_5755[] = {
9713 { 0x00000200, 0x00008},
9714 { 0x00004000, 0x00800},
9715 { 0x00006000, 0x00800},
9716 { 0x00008000, 0x02000},
9717 { 0x00010000, 0x0c000},
9718 { 0xffffffff, 0x00000}
b16250e3
MC		 9719 }, mem_tbl_5906[] = {
9720 { 0x00000200, 0x00008},
9721 { 0x00004000, 0x00400},
9722 { 0x00006000, 0x00400},
9723 { 0x00008000, 0x01000},
9724 { 0x00010000, 0x01000},
9725 { 0xffffffff, 0x00000}
7942e1db
MC		 9726 };
9727 struct mem_entry *mem_tbl;
9728 int err = 0;
9729 int i;
9730
321d32a0
MC		 9731 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9732 mem_tbl = mem_tbl_5755;
9733 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9734 mem_tbl = mem_tbl_5906;
9735 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9736 mem_tbl = mem_tbl_5705;
9737 else
7942e1db
MC		 9738 mem_tbl = mem_tbl_570x;
9739
9740 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9741 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9742 mem_tbl[i].len)) != 0)
9743 break;
9744 }
6aa20a22 9745
7942e1db
MC		 9746 return err;
9747}
9748
9f40dead
MC		 9749#define TG3_MAC_LOOPBACK 0
9750#define TG3_PHY_LOOPBACK 1
9751
9752static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9753{
9f40dead 9754 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
c76949a6
MC		 9755 u32 desc_idx;
9756 struct sk_buff *skb, *rx_skb;
9757 u8 *tx_data;
9758 dma_addr_t map;
9759 int num_pkts, tx_len, rx_len, i, err;
9760 struct tg3_rx_buffer_desc *desc;
9761
9f40dead 9762 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9763 /* HW errata - mac loopback fails in some cases on 5780.
9764 * Normal traffic and PHY loopback are not affected by
9765 * errata.
9766 */
9767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9768 return 0;
9769
9f40dead 9770 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9771 MAC_MODE_PORT_INT_LPBACK;
9772 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9773 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9774 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9775 mac_mode |= MAC_MODE_PORT_MODE_MII;
9776 else
9777 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9778 tw32(MAC_MODE, mac_mode);
9779 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9780 u32 val;
9781
7f97a4bd
MC		 9782 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9783 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 9784 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9785 } else
9786 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9787
9ef8ca99
MC		 9788 tg3_phy_toggle_automdix(tp, 0);
9789
3f7045c1 9790 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9791 udelay(40);
5d64ad34 9792
e8f3f6ca 9793 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 9794 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9796 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 9797 mac_mode |= MAC_MODE_PORT_MODE_MII;
9798 } else
9799 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9800
c94e3941
MC		 9801 /* reset to prevent losing 1st rx packet intermittently */
9802 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9803 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9804 udelay(10);
9805 tw32_f(MAC_RX_MODE, tp->rx_mode);
9806 }
e8f3f6ca
MC		 9807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9808 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9809 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9810 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9811 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9812 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9813 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9814 }
9f40dead 9815 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9816 }
9817 else
9818 return -EINVAL;
c76949a6
MC		 9819
9820 err = -EIO;
9821
c76949a6 9822 tx_len = 1514;
a20e9c62 9823 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9824 if (!skb)
9825 return -ENOMEM;
9826
c76949a6
MC		 9827 tx_data = skb_put(skb, tx_len);
9828 memcpy(tx_data, tp->dev->dev_addr, 6);
9829 memset(tx_data + 6, 0x0, 8);
9830
9831 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9832
9833 for (i = 14; i < tx_len; i++)
9834 tx_data[i] = (u8) (i & 0xff);
9835
9836 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9837
9838 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9839 HOSTCC_MODE_NOW);
9840
9841 udelay(10);
9842
9843 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9844
c76949a6
MC		 9845 num_pkts = 0;
9846
9f40dead 9847 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
c76949a6 9848
9f40dead 9849 tp->tx_prod++;
c76949a6
MC		 9850 num_pkts++;
9851
9f40dead
MC		 9852 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9853 tp->tx_prod);
09ee929c 9854 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 9855
9856 udelay(10);
9857
3f7045c1
MC		 9858 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9859 for (i = 0; i < 25; i++) {
c76949a6
MC		 9860 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9861 HOSTCC_MODE_NOW);
9862
9863 udelay(10);
9864
9865 tx_idx = tp->hw_status->idx[0].tx_consumer;
9866 rx_idx = tp->hw_status->idx[0].rx_producer;
9f40dead 9867 if ((tx_idx == tp->tx_prod) &&
c76949a6
MC		 9868 (rx_idx == (rx_start_idx + num_pkts)))
9869 break;
9870 }
9871
9872 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9873 dev_kfree_skb(skb);
9874
9f40dead 9875 if (tx_idx != tp->tx_prod)
c76949a6
MC		 9876 goto out;
9877
9878 if (rx_idx != rx_start_idx + num_pkts)
9879 goto out;
9880
9881 desc = &tp->rx_rcb[rx_start_idx];
9882 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9883 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9884 if (opaque_key != RXD_OPAQUE_RING_STD)
9885 goto out;
9886
9887 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9888 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9889 goto out;
9890
9891 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9892 if (rx_len != tx_len)
9893 goto out;
9894
9895 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9896
9897 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9898 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9899
9900 for (i = 14; i < tx_len; i++) {
9901 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9902 goto out;
9903 }
9904 err = 0;
6aa20a22 9905
c76949a6
MC		 9906 /* tg3_free_rings will unmap and free the rx_skb */
9907out:
9908 return err;
9909}
9910
9f40dead
MC		 9911#define TG3_MAC_LOOPBACK_FAILED 1
9912#define TG3_PHY_LOOPBACK_FAILED 2
9913#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9914 TG3_PHY_LOOPBACK_FAILED)
9915
9916static int tg3_test_loopback(struct tg3 *tp)
9917{
9918 int err = 0;
9936bcf6 9919 u32 cpmuctrl = 0;
9f40dead
MC		 9920
9921 if (!netif_running(tp->dev))
9922 return TG3_LOOPBACK_FAILED;
9923
b9ec6c1b
MC		 9924 err = tg3_reset_hw(tp, 1);
9925 if (err)
9926 return TG3_LOOPBACK_FAILED;
9f40dead 9927
6833c043
MC		 9928 /* Turn off gphy autopowerdown. */
9929 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9930 tg3_phy_toggle_apd(tp, false);
9931
321d32a0 9932 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9933 int i;
9934 u32 status;
9935
9936 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9937
9938 /* Wait for up to 40 microseconds to acquire lock. */
9939 for (i = 0; i < 4; i++) {
9940 status = tr32(TG3_CPMU_MUTEX_GNT);
9941 if (status == CPMU_MUTEX_GNT_DRIVER)
9942 break;
9943 udelay(10);
9944 }
9945
9946 if (status != CPMU_MUTEX_GNT_DRIVER)
9947 return TG3_LOOPBACK_FAILED;
9948
b2a5c19c 9949 /* Turn off link-based power management. */
e875093c 9950 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 9951 tw32(TG3_CPMU_CTRL,
9952 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9953 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 9954 }
9955
9f40dead
MC		 9956 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9957 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 9958
321d32a0 9959 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 9960 tw32(TG3_CPMU_CTRL, cpmuctrl);
9961
9962 /* Release the mutex */
9963 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9964 }
9965
dd477003
MC		 9966 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9967 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 9968 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9969 err |= TG3_PHY_LOOPBACK_FAILED;
9970 }
9971
6833c043
MC		 9972 /* Re-enable gphy autopowerdown. */
9973 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9974 tg3_phy_toggle_apd(tp, true);
9975
9f40dead
MC		 9976 return err;
9977}
9978
4cafd3f5
MC		 9979static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9980 u64 *data)
9981{
566f86ad
MC		 9982 struct tg3 *tp = netdev_priv(dev);
9983
bc1c7567
MC		 9984 if (tp->link_config.phy_is_low_power)
9985 tg3_set_power_state(tp, PCI_D0);
9986
566f86ad
MC		 9987 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9988
9989 if (tg3_test_nvram(tp) != 0) {
9990 etest->flags |= ETH_TEST_FL_FAILED;
9991 data[0] = 1;
9992 }
ca43007a
MC		 9993 if (tg3_test_link(tp) != 0) {
9994 etest->flags |= ETH_TEST_FL_FAILED;
9995 data[1] = 1;
9996 }
a71116d1 9997 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 9998 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 9999
10000 if (netif_running(dev)) {
b02fd9e3 10001 tg3_phy_stop(tp);
a71116d1 10002 tg3_netif_stop(tp);
bbe832c0
MC		 10003 irq_sync = 1;
10004 }
a71116d1 10005
bbe832c0 10006 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10007
10008 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10009 err = tg3_nvram_lock(tp);
a71116d1
MC		 10010 tg3_halt_cpu(tp, RX_CPU_BASE);
10011 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10012 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10013 if (!err)
10014 tg3_nvram_unlock(tp);
a71116d1 10015
d9ab5ad1
MC		 10016 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10017 tg3_phy_reset(tp);
10018
a71116d1
MC		 10019 if (tg3_test_registers(tp) != 0) {
10020 etest->flags |= ETH_TEST_FL_FAILED;
10021 data[2] = 1;
10022 }
7942e1db
MC		 10023 if (tg3_test_memory(tp) != 0) {
10024 etest->flags |= ETH_TEST_FL_FAILED;
10025 data[3] = 1;
10026 }
9f40dead 10027 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10028 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10029
f47c11ee
DM		 10030 tg3_full_unlock(tp);
10031
d4bc3927
MC		 10032 if (tg3_test_interrupt(tp) != 0) {
10033 etest->flags |= ETH_TEST_FL_FAILED;
10034 data[5] = 1;
10035 }
f47c11ee
DM		 10036
10037 tg3_full_lock(tp, 0);
d4bc3927 10038
a71116d1
MC		 10039 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10040 if (netif_running(dev)) {
10041 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10042 err2 = tg3_restart_hw(tp, 1);
10043 if (!err2)
b9ec6c1b 10044 tg3_netif_start(tp);
a71116d1 10045 }
f47c11ee
DM		 10046
10047 tg3_full_unlock(tp);
b02fd9e3
MC		 10048
10049 if (irq_sync && !err2)
10050 tg3_phy_start(tp);
a71116d1 10051 }
bc1c7567
MC		 10052 if (tp->link_config.phy_is_low_power)
10053 tg3_set_power_state(tp, PCI_D3hot);
10054
4cafd3f5
MC		 10055}
10056
1da177e4
LT		 10057static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10058{
10059 struct mii_ioctl_data *data = if_mii(ifr);
10060 struct tg3 *tp = netdev_priv(dev);
10061 int err;
10062
b02fd9e3
MC		 10063 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10064 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10065 return -EAGAIN;
298cf9be 10066 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10067 }
10068
1da177e4
LT		 10069 switch(cmd) {
10070 case SIOCGMIIPHY:
10071 data->phy_id = PHY_ADDR;
10072
10073 /* fallthru */
10074 case SIOCGMIIREG: {
10075 u32 mii_regval;
10076
10077 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10078 break; /* We have no PHY */
10079
bc1c7567
MC		 10080 if (tp->link_config.phy_is_low_power)
10081 return -EAGAIN;
10082
f47c11ee 10083 spin_lock_bh(&tp->lock);
1da177e4 10084 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10085 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10086
10087 data->val_out = mii_regval;
10088
10089 return err;
10090 }
10091
10092 case SIOCSMIIREG:
10093 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10094 break; /* We have no PHY */
10095
10096 if (!capable(CAP_NET_ADMIN))
10097 return -EPERM;
10098
bc1c7567
MC		 10099 if (tp->link_config.phy_is_low_power)
10100 return -EAGAIN;
10101
f47c11ee 10102 spin_lock_bh(&tp->lock);
1da177e4 10103 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10104 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10105
10106 return err;
10107
10108 default:
10109 /* do nothing */
10110 break;
10111 }
10112 return -EOPNOTSUPP;
10113}
10114
10115#if TG3_VLAN_TAG_USED
10116static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10117{
10118 struct tg3 *tp = netdev_priv(dev);
10119
844b3eed
MC		 10120 if (!netif_running(dev)) {
10121 tp->vlgrp = grp;
10122 return;
10123 }
10124
10125 tg3_netif_stop(tp);
29315e87 10126
f47c11ee 10127 tg3_full_lock(tp, 0);
1da177e4
LT		 10128
10129 tp->vlgrp = grp;
10130
10131 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10132 __tg3_set_rx_mode(dev);
10133
844b3eed 10134 tg3_netif_start(tp);
46966545
MC		 10135
10136 tg3_full_unlock(tp);
1da177e4 10137}
1da177e4
LT		 10138#endif
10139
15f9850d
DM		 10140static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10141{
10142 struct tg3 *tp = netdev_priv(dev);
10143
10144 memcpy(ec, &tp->coal, sizeof(*ec));
10145 return 0;
10146}
10147
d244c892
MC		 10148static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10149{
10150 struct tg3 *tp = netdev_priv(dev);
10151 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10152 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10153
10154 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10155 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10156 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10157 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10158 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10159 }
10160
10161 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10162 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10163 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10164 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10165 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10166 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10167 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10168 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10169 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10170 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10171 return -EINVAL;
10172
10173 /* No rx interrupts will be generated if both are zero */
10174 if ((ec->rx_coalesce_usecs == 0) &&
10175 (ec->rx_max_coalesced_frames == 0))
10176 return -EINVAL;
10177
10178 /* No tx interrupts will be generated if both are zero */
10179 if ((ec->tx_coalesce_usecs == 0) &&
10180 (ec->tx_max_coalesced_frames == 0))
10181 return -EINVAL;
10182
10183 /* Only copy relevant parameters, ignore all others. */
10184 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10185 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10186 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10187 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10188 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10189 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10190 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10191 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10192 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10193
10194 if (netif_running(dev)) {
10195 tg3_full_lock(tp, 0);
10196 __tg3_set_coalesce(tp, &tp->coal);
10197 tg3_full_unlock(tp);
10198 }
10199 return 0;
10200}
10201
7282d491 10202static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10203 .get_settings = tg3_get_settings,
10204 .set_settings = tg3_set_settings,
10205 .get_drvinfo = tg3_get_drvinfo,
10206 .get_regs_len = tg3_get_regs_len,
10207 .get_regs = tg3_get_regs,
10208 .get_wol = tg3_get_wol,
10209 .set_wol = tg3_set_wol,
10210 .get_msglevel = tg3_get_msglevel,
10211 .set_msglevel = tg3_set_msglevel,
10212 .nway_reset = tg3_nway_reset,
10213 .get_link = ethtool_op_get_link,
10214 .get_eeprom_len = tg3_get_eeprom_len,
10215 .get_eeprom = tg3_get_eeprom,
10216 .set_eeprom = tg3_set_eeprom,
10217 .get_ringparam = tg3_get_ringparam,
10218 .set_ringparam = tg3_set_ringparam,
10219 .get_pauseparam = tg3_get_pauseparam,
10220 .set_pauseparam = tg3_set_pauseparam,
10221 .get_rx_csum = tg3_get_rx_csum,
10222 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10223 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10224 .set_sg = ethtool_op_set_sg,
1da177e4 10225 .set_tso = tg3_set_tso,
4cafd3f5 10226 .self_test = tg3_self_test,
1da177e4 10227 .get_strings = tg3_get_strings,
4009a93d 10228 .phys_id = tg3_phys_id,
1da177e4 10229 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10230 .get_coalesce = tg3_get_coalesce,
d244c892 10231 .set_coalesce = tg3_set_coalesce,
b9f2c044 10232 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10233};
10234
10235static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10236{
1b27777a 10237 u32 cursize, val, magic;
1da177e4
LT		 10238
10239 tp->nvram_size = EEPROM_CHIP_SIZE;
10240
e4f34110 10241 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10242 return;
10243
b16250e3
MC		 10244 if ((magic != TG3_EEPROM_MAGIC) &&
10245 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10246 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10247 return;
10248
10249 /*
10250 * Size the chip by reading offsets at increasing powers of two.
10251 * When we encounter our validation signature, we know the addressing
10252 * has wrapped around, and thus have our chip size.
10253 */
1b27777a 10254 cursize = 0x10;
1da177e4
LT		 10255
10256 while (cursize < tp->nvram_size) {
e4f34110 10257 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10258 return;
10259
1820180b 10260 if (val == magic)
1da177e4
LT		 10261 break;
10262
10263 cursize <<= 1;
10264 }
10265
10266 tp->nvram_size = cursize;
10267}
6aa20a22 10268
1da177e4
LT		 10269static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10270{
10271 u32 val;
10272
df259d8c
MC		 10273 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10274 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10275 return;
10276
10277 /* Selfboot format */
1820180b 10278 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10279 tg3_get_eeprom_size(tp);
10280 return;
10281 }
10282
6d348f2c 10283 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10284 if (val != 0) {
6d348f2c
MC		 10285 /* This is confusing. We want to operate on the
10286 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10287 * call will read from NVRAM and byteswap the data
10288 * according to the byteswapping settings for all
10289 * other register accesses. This ensures the data we
10290 * want will always reside in the lower 16-bits.
10291 * However, the data in NVRAM is in LE format, which
10292 * means the data from the NVRAM read will always be
10293 * opposite the endianness of the CPU. The 16-bit
10294 * byteswap then brings the data to CPU endianness.
10295 */
10296 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10297 return;
10298 }
10299 }
fd1122a2 10300 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10301}
10302
10303static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10304{
10305 u32 nvcfg1;
10306
10307 nvcfg1 = tr32(NVRAM_CFG1);
10308 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10309 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10310 } else {
1da177e4
LT		 10311 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10312 tw32(NVRAM_CFG1, nvcfg1);
10313 }
10314
4c987487 10315 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10316 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10317 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10318 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10319 tp->nvram_jedecnum = JEDEC_ATMEL;
10320 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10321 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10322 break;
10323 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10324 tp->nvram_jedecnum = JEDEC_ATMEL;
10325 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10326 break;
10327 case FLASH_VENDOR_ATMEL_EEPROM:
10328 tp->nvram_jedecnum = JEDEC_ATMEL;
10329 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10330 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10331 break;
10332 case FLASH_VENDOR_ST:
10333 tp->nvram_jedecnum = JEDEC_ST;
10334 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10335 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10336 break;
10337 case FLASH_VENDOR_SAIFUN:
10338 tp->nvram_jedecnum = JEDEC_SAIFUN;
10339 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10340 break;
10341 case FLASH_VENDOR_SST_SMALL:
10342 case FLASH_VENDOR_SST_LARGE:
10343 tp->nvram_jedecnum = JEDEC_SST;
10344 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10345 break;
1da177e4 10346 }
8590a603 10347 } else {
1da177e4
LT		 10348 tp->nvram_jedecnum = JEDEC_ATMEL;
10349 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10350 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10351 }
10352}
10353
361b4ac2
MC		 10354static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10355{
10356 u32 nvcfg1;
10357
10358 nvcfg1 = tr32(NVRAM_CFG1);
10359
e6af301b
MC		 10360 /* NVRAM protection for TPM */
10361 if (nvcfg1 & (1 << 27))
10362 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10363
361b4ac2 10364 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10365 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10366 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10367 tp->nvram_jedecnum = JEDEC_ATMEL;
10368 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10369 break;
10370 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10371 tp->nvram_jedecnum = JEDEC_ATMEL;
10372 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10373 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10374 break;
10375 case FLASH_5752VENDOR_ST_M45PE10:
10376 case FLASH_5752VENDOR_ST_M45PE20:
10377 case FLASH_5752VENDOR_ST_M45PE40:
10378 tp->nvram_jedecnum = JEDEC_ST;
10379 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10380 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10381 break;
361b4ac2
MC		 10382 }
10383
10384 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10385 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8590a603
MC		 10386 case FLASH_5752PAGE_SIZE_256:
10387 tp->nvram_pagesize = 256;
10388 break;
10389 case FLASH_5752PAGE_SIZE_512:
10390 tp->nvram_pagesize = 512;
10391 break;
10392 case FLASH_5752PAGE_SIZE_1K:
10393 tp->nvram_pagesize = 1024;
10394 break;
10395 case FLASH_5752PAGE_SIZE_2K:
10396 tp->nvram_pagesize = 2048;
10397 break;
10398 case FLASH_5752PAGE_SIZE_4K:
10399 tp->nvram_pagesize = 4096;
10400 break;
10401 case FLASH_5752PAGE_SIZE_264:
10402 tp->nvram_pagesize = 264;
10403 break;
361b4ac2 10404 }
8590a603 10405 } else {
361b4ac2
MC		 10406 /* For eeprom, set pagesize to maximum eeprom size */
10407 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10408
10409 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10410 tw32(NVRAM_CFG1, nvcfg1);
10411 }
10412}
10413
d3c7b886
MC		 10414static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10415{
989a9d23 10416 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10417
10418 nvcfg1 = tr32(NVRAM_CFG1);
10419
10420 /* NVRAM protection for TPM */
989a9d23 10421 if (nvcfg1 & (1 << 27)) {
d3c7b886 10422 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10423 protect = 1;
10424 }
d3c7b886 10425
989a9d23
MC		 10426 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10427 switch (nvcfg1) {
8590a603
MC		 10428 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10429 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10430 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10431 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10432 tp->nvram_jedecnum = JEDEC_ATMEL;
10433 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10434 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10435 tp->nvram_pagesize = 264;
10436 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10437 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10438 tp->nvram_size = (protect ? 0x3e200 :
10439 TG3_NVRAM_SIZE_512KB);
10440 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10441 tp->nvram_size = (protect ? 0x1f200 :
10442 TG3_NVRAM_SIZE_256KB);
10443 else
10444 tp->nvram_size = (protect ? 0x1f200 :
10445 TG3_NVRAM_SIZE_128KB);
10446 break;
10447 case FLASH_5752VENDOR_ST_M45PE10:
10448 case FLASH_5752VENDOR_ST_M45PE20:
10449 case FLASH_5752VENDOR_ST_M45PE40:
10450 tp->nvram_jedecnum = JEDEC_ST;
10451 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10452 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10453 tp->nvram_pagesize = 256;
10454 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10455 tp->nvram_size = (protect ?
10456 TG3_NVRAM_SIZE_64KB :
10457 TG3_NVRAM_SIZE_128KB);
10458 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10459 tp->nvram_size = (protect ?
10460 TG3_NVRAM_SIZE_64KB :
10461 TG3_NVRAM_SIZE_256KB);
10462 else
10463 tp->nvram_size = (protect ?
10464 TG3_NVRAM_SIZE_128KB :
10465 TG3_NVRAM_SIZE_512KB);
10466 break;
d3c7b886
MC		 10467 }
10468}
10469
1b27777a
MC		 10470static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10471{
10472 u32 nvcfg1;
10473
10474 nvcfg1 = tr32(NVRAM_CFG1);
10475
10476 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10477 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10478 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10479 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10480 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10481 tp->nvram_jedecnum = JEDEC_ATMEL;
10482 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10483 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 10484
8590a603
MC		 10485 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10486 tw32(NVRAM_CFG1, nvcfg1);
10487 break;
10488 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10489 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10490 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10491 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10492 tp->nvram_jedecnum = JEDEC_ATMEL;
10493 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10494 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10495 tp->nvram_pagesize = 264;
10496 break;
10497 case FLASH_5752VENDOR_ST_M45PE10:
10498 case FLASH_5752VENDOR_ST_M45PE20:
10499 case FLASH_5752VENDOR_ST_M45PE40:
10500 tp->nvram_jedecnum = JEDEC_ST;
10501 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10502 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10503 tp->nvram_pagesize = 256;
10504 break;
1b27777a
MC		 10505 }
10506}
10507
6b91fa02
MC		 10508static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10509{
10510 u32 nvcfg1, protect = 0;
10511
10512 nvcfg1 = tr32(NVRAM_CFG1);
10513
10514 /* NVRAM protection for TPM */
10515 if (nvcfg1 & (1 << 27)) {
10516 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10517 protect = 1;
10518 }
10519
10520 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10521 switch (nvcfg1) {
8590a603
MC		 10522 case FLASH_5761VENDOR_ATMEL_ADB021D:
10523 case FLASH_5761VENDOR_ATMEL_ADB041D:
10524 case FLASH_5761VENDOR_ATMEL_ADB081D:
10525 case FLASH_5761VENDOR_ATMEL_ADB161D:
10526 case FLASH_5761VENDOR_ATMEL_MDB021D:
10527 case FLASH_5761VENDOR_ATMEL_MDB041D:
10528 case FLASH_5761VENDOR_ATMEL_MDB081D:
10529 case FLASH_5761VENDOR_ATMEL_MDB161D:
10530 tp->nvram_jedecnum = JEDEC_ATMEL;
10531 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10532 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10533 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10534 tp->nvram_pagesize = 256;
10535 break;
10536 case FLASH_5761VENDOR_ST_A_M45PE20:
10537 case FLASH_5761VENDOR_ST_A_M45PE40:
10538 case FLASH_5761VENDOR_ST_A_M45PE80:
10539 case FLASH_5761VENDOR_ST_A_M45PE16:
10540 case FLASH_5761VENDOR_ST_M_M45PE20:
10541 case FLASH_5761VENDOR_ST_M_M45PE40:
10542 case FLASH_5761VENDOR_ST_M_M45PE80:
10543 case FLASH_5761VENDOR_ST_M_M45PE16:
10544 tp->nvram_jedecnum = JEDEC_ST;
10545 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10546 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10547 tp->nvram_pagesize = 256;
10548 break;
6b91fa02
MC		 10549 }
10550
10551 if (protect) {
10552 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10553 } else {
10554 switch (nvcfg1) {
8590a603
MC		 10555 case FLASH_5761VENDOR_ATMEL_ADB161D:
10556 case FLASH_5761VENDOR_ATMEL_MDB161D:
10557 case FLASH_5761VENDOR_ST_A_M45PE16:
10558 case FLASH_5761VENDOR_ST_M_M45PE16:
10559 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10560 break;
10561 case FLASH_5761VENDOR_ATMEL_ADB081D:
10562 case FLASH_5761VENDOR_ATMEL_MDB081D:
10563 case FLASH_5761VENDOR_ST_A_M45PE80:
10564 case FLASH_5761VENDOR_ST_M_M45PE80:
10565 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10566 break;
10567 case FLASH_5761VENDOR_ATMEL_ADB041D:
10568 case FLASH_5761VENDOR_ATMEL_MDB041D:
10569 case FLASH_5761VENDOR_ST_A_M45PE40:
10570 case FLASH_5761VENDOR_ST_M_M45PE40:
10571 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10572 break;
10573 case FLASH_5761VENDOR_ATMEL_ADB021D:
10574 case FLASH_5761VENDOR_ATMEL_MDB021D:
10575 case FLASH_5761VENDOR_ST_A_M45PE20:
10576 case FLASH_5761VENDOR_ST_M_M45PE20:
10577 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10578 break;
6b91fa02
MC		 10579 }
10580 }
10581}
10582
b5d3772c
MC		 10583static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10584{
10585 tp->nvram_jedecnum = JEDEC_ATMEL;
10586 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10587 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10588}
10589
321d32a0
MC		 10590static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10591{
10592 u32 nvcfg1;
10593
10594 nvcfg1 = tr32(NVRAM_CFG1);
10595
10596 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10597 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10598 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10599 tp->nvram_jedecnum = JEDEC_ATMEL;
10600 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10601 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10602
10603 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10604 tw32(NVRAM_CFG1, nvcfg1);
10605 return;
10606 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10607 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10608 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10609 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10610 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10611 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10612 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10613 tp->nvram_jedecnum = JEDEC_ATMEL;
10614 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10615 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10616
10617 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10618 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10619 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10620 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10621 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10622 break;
10623 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10624 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10625 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10626 break;
10627 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10628 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10629 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10630 break;
10631 }
10632 break;
10633 case FLASH_5752VENDOR_ST_M45PE10:
10634 case FLASH_5752VENDOR_ST_M45PE20:
10635 case FLASH_5752VENDOR_ST_M45PE40:
10636 tp->nvram_jedecnum = JEDEC_ST;
10637 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10638 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10639
10640 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10641 case FLASH_5752VENDOR_ST_M45PE10:
10642 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10643 break;
10644 case FLASH_5752VENDOR_ST_M45PE20:
10645 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10646 break;
10647 case FLASH_5752VENDOR_ST_M45PE40:
10648 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10649 break;
10650 }
10651 break;
10652 default:
df259d8c 10653 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 10654 return;
10655 }
10656
10657 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10658 case FLASH_5752PAGE_SIZE_256:
10659 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10660 tp->nvram_pagesize = 256;
10661 break;
10662 case FLASH_5752PAGE_SIZE_512:
10663 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10664 tp->nvram_pagesize = 512;
10665 break;
10666 case FLASH_5752PAGE_SIZE_1K:
10667 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10668 tp->nvram_pagesize = 1024;
10669 break;
10670 case FLASH_5752PAGE_SIZE_2K:
10671 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10672 tp->nvram_pagesize = 2048;
10673 break;
10674 case FLASH_5752PAGE_SIZE_4K:
10675 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10676 tp->nvram_pagesize = 4096;
10677 break;
10678 case FLASH_5752PAGE_SIZE_264:
10679 tp->nvram_pagesize = 264;
10680 break;
10681 case FLASH_5752PAGE_SIZE_528:
10682 tp->nvram_pagesize = 528;
10683 break;
10684 }
10685}
10686
1da177e4
LT		 10687/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10688static void __devinit tg3_nvram_init(struct tg3 *tp)
10689{
1da177e4
LT		 10690 tw32_f(GRC_EEPROM_ADDR,
10691 (EEPROM_ADDR_FSM_RESET |
10692 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10693 EEPROM_ADDR_CLKPERD_SHIFT)));
10694
9d57f01c 10695 msleep(1);
1da177e4
LT		 10696
10697 /* Enable seeprom accesses. */
10698 tw32_f(GRC_LOCAL_CTRL,
10699 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10700 udelay(100);
10701
10702 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10703 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10704 tp->tg3_flags |= TG3_FLAG_NVRAM;
10705
ec41c7df
MC		 10706 if (tg3_nvram_lock(tp)) {
10707 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10708 "tg3_nvram_init failed.\n", tp->dev->name);
10709 return;
10710 }
e6af301b 10711 tg3_enable_nvram_access(tp);
1da177e4 10712
989a9d23
MC		 10713 tp->nvram_size = 0;
10714
361b4ac2
MC		 10715 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10716 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10717 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10718 tg3_get_5755_nvram_info(tp);
d30cdd28 10719 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10720 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10721 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10722 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10723 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10724 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10725 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10726 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10727 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10728 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10729 else
10730 tg3_get_nvram_info(tp);
10731
989a9d23
MC		 10732 if (tp->nvram_size == 0)
10733 tg3_get_nvram_size(tp);
1da177e4 10734
e6af301b 10735 tg3_disable_nvram_access(tp);
381291b7 10736 tg3_nvram_unlock(tp);
1da177e4
LT		 10737
10738 } else {
10739 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10740
10741 tg3_get_eeprom_size(tp);
10742 }
10743}
10744
1da177e4
LT		 10745static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10746 u32 offset, u32 len, u8 *buf)
10747{
10748 int i, j, rc = 0;
10749 u32 val;
10750
10751 for (i = 0; i < len; i += 4) {
b9fc7dc5 10752 u32 addr;
a9dc529d 10753 __be32 data;
1da177e4
LT		 10754
10755 addr = offset + i;
10756
10757 memcpy(&data, buf + i, 4);
10758
62cedd11
MC		 10759 /*
10760 * The SEEPROM interface expects the data to always be opposite
10761 * the native endian format. We accomplish this by reversing
10762 * all the operations that would have been performed on the
10763 * data from a call to tg3_nvram_read_be32().
10764 */
10765 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10766
10767 val = tr32(GRC_EEPROM_ADDR);
10768 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10769
10770 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10771 EEPROM_ADDR_READ);
10772 tw32(GRC_EEPROM_ADDR, val |
10773 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10774 (addr & EEPROM_ADDR_ADDR_MASK) |
10775 EEPROM_ADDR_START |
10776 EEPROM_ADDR_WRITE);
6aa20a22 10777
9d57f01c 10778 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10779 val = tr32(GRC_EEPROM_ADDR);
10780
10781 if (val & EEPROM_ADDR_COMPLETE)
10782 break;
9d57f01c 10783 msleep(1);
1da177e4
LT		 10784 }
10785 if (!(val & EEPROM_ADDR_COMPLETE)) {
10786 rc = -EBUSY;
10787 break;
10788 }
10789 }
10790
10791 return rc;
10792}
10793
10794/* offset and length are dword aligned */
10795static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10796 u8 *buf)
10797{
10798 int ret = 0;
10799 u32 pagesize = tp->nvram_pagesize;
10800 u32 pagemask = pagesize - 1;
10801 u32 nvram_cmd;
10802 u8 *tmp;
10803
10804 tmp = kmalloc(pagesize, GFP_KERNEL);
10805 if (tmp == NULL)
10806 return -ENOMEM;
10807
10808 while (len) {
10809 int j;
e6af301b 10810 u32 phy_addr, page_off, size;
1da177e4
LT		 10811
10812 phy_addr = offset & ~pagemask;
6aa20a22 10813
1da177e4 10814 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10815 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10816 (__be32 *) (tmp + j));
10817 if (ret)
1da177e4
LT		 10818 break;
10819 }
10820 if (ret)
10821 break;
10822
10823 page_off = offset & pagemask;
10824 size = pagesize;
10825 if (len < size)
10826 size = len;
10827
10828 len -= size;
10829
10830 memcpy(tmp + page_off, buf, size);
10831
10832 offset = offset + (pagesize - page_off);
10833
e6af301b 10834 tg3_enable_nvram_access(tp);
1da177e4
LT		 10835
10836 /*
10837 * Before we can erase the flash page, we need
10838 * to issue a special "write enable" command.
10839 */
10840 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10841
10842 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10843 break;
10844
10845 /* Erase the target page */
10846 tw32(NVRAM_ADDR, phy_addr);
10847
10848 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10849 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10850
10851 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10852 break;
10853
10854 /* Issue another write enable to start the write. */
10855 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10856
10857 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10858 break;
10859
10860 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10861 __be32 data;
1da177e4 10862
b9fc7dc5 10863 data = *((__be32 *) (tmp + j));
a9dc529d 10864
b9fc7dc5 10865 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10866
10867 tw32(NVRAM_ADDR, phy_addr + j);
10868
10869 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10870 NVRAM_CMD_WR;
10871
10872 if (j == 0)
10873 nvram_cmd |= NVRAM_CMD_FIRST;
10874 else if (j == (pagesize - 4))
10875 nvram_cmd |= NVRAM_CMD_LAST;
10876
10877 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10878 break;
10879 }
10880 if (ret)
10881 break;
10882 }
10883
10884 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10885 tg3_nvram_exec_cmd(tp, nvram_cmd);
10886
10887 kfree(tmp);
10888
10889 return ret;
10890}
10891
10892/* offset and length are dword aligned */
10893static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10894 u8 *buf)
10895{
10896 int i, ret = 0;
10897
10898 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 10899 u32 page_off, phy_addr, nvram_cmd;
10900 __be32 data;
1da177e4
LT		 10901
10902 memcpy(&data, buf + i, 4);
b9fc7dc5 10903 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10904
10905 page_off = offset % tp->nvram_pagesize;
10906
1820180b 10907 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 10908
10909 tw32(NVRAM_ADDR, phy_addr);
10910
10911 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10912
10913 if ((page_off == 0) || (i == 0))
10914 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 10915 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 10916 nvram_cmd |= NVRAM_CMD_LAST;
10917
10918 if (i == (len - 4))
10919 nvram_cmd |= NVRAM_CMD_LAST;
10920
321d32a0
MC		 10921 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10922 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 10923 (tp->nvram_jedecnum == JEDEC_ST) &&
10924 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 10925
10926 if ((ret = tg3_nvram_exec_cmd(tp,
10927 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10928 NVRAM_CMD_DONE)))
10929
10930 break;
10931 }
10932 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10933 /* We always do complete word writes to eeprom. */
10934 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10935 }
10936
10937 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10938 break;
10939 }
10940 return ret;
10941}
10942
10943/* offset and length are dword aligned */
10944static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10945{
10946 int ret;
10947
1da177e4 10948 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 10949 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10950 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 10951 udelay(40);
10952 }
10953
10954 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10955 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10956 }
10957 else {
10958 u32 grc_mode;
10959
ec41c7df
MC		 10960 ret = tg3_nvram_lock(tp);
10961 if (ret)
10962 return ret;
1da177e4 10963
e6af301b
MC		 10964 tg3_enable_nvram_access(tp);
10965 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10966 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 10967 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 10968
10969 grc_mode = tr32(GRC_MODE);
10970 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10971
10972 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10973 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10974
10975 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10976 buf);
10977 }
10978 else {
10979 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10980 buf);
10981 }
10982
10983 grc_mode = tr32(GRC_MODE);
10984 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10985
e6af301b 10986 tg3_disable_nvram_access(tp);
1da177e4
LT		 10987 tg3_nvram_unlock(tp);
10988 }
10989
10990 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 10991 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 10992 udelay(40);
10993 }
10994
10995 return ret;
10996}
10997
10998struct subsys_tbl_ent {
10999 u16 subsys_vendor, subsys_devid;
11000 u32 phy_id;
11001};
11002
11003static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11004 /* Broadcom boards. */
11005 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11006 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11007 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11008 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11009 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11010 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11011 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11012 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11013 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11014 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11015 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11016
11017 /* 3com boards. */
11018 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11019 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11020 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11021 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11022 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11023
11024 /* DELL boards. */
11025 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11026 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11027 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11028 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11029
11030 /* Compaq boards. */
11031 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11032 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11033 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11034 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11035 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11036
11037 /* IBM boards. */
11038 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11039};
11040
11041static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11042{
11043 int i;
11044
11045 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11046 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11047 tp->pdev->subsystem_vendor) &&
11048 (subsys_id_to_phy_id[i].subsys_devid ==
11049 tp->pdev->subsystem_device))
11050 return &subsys_id_to_phy_id[i];
11051 }
11052 return NULL;
11053}
11054
7d0c41ef 11055static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11056{
1da177e4 11057 u32 val;
caf636c7
MC		 11058 u16 pmcsr;
11059
11060 /* On some early chips the SRAM cannot be accessed in D3hot state,
11061 * so need make sure we're in D0.
11062 */
11063 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11064 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11065 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11066 msleep(1);
7d0c41ef
MC		 11067
11068 /* Make sure register accesses (indirect or otherwise)
11069 * will function correctly.
11070 */
11071 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11072 tp->misc_host_ctrl);
1da177e4 11073
f49639e6
DM		 11074 /* The memory arbiter has to be enabled in order for SRAM accesses
11075 * to succeed. Normally on powerup the tg3 chip firmware will make
11076 * sure it is enabled, but other entities such as system netboot
11077 * code might disable it.
11078 */
11079 val = tr32(MEMARB_MODE);
11080 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11081
1da177e4 11082 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11083 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11084
a85feb8c
GZ		 11085 /* Assume an onboard device and WOL capable by default. */
11086 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11087
b5d3772c 11088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11089 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11090 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11091 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11092 }
0527ba35
MC		 11093 val = tr32(VCPU_CFGSHDW);
11094 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11095 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11096 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11097 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11098 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11099 goto done;
b5d3772c
MC		 11100 }
11101
1da177e4
LT		 11102 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11103 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11104 u32 nic_cfg, led_cfg;
a9daf367 11105 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11106 int eeprom_phy_serdes = 0;
1da177e4
LT		 11107
11108 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11109 tp->nic_sram_data_cfg = nic_cfg;
11110
11111 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11112 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11113 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11114 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11115 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11116 (ver > 0) && (ver < 0x100))
11117 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11118
a9daf367
MC		 11119 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11120 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11121
1da177e4
LT		 11122 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11123 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11124 eeprom_phy_serdes = 1;
11125
11126 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11127 if (nic_phy_id != 0) {
11128 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11129 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11130
11131 eeprom_phy_id = (id1 >> 16) << 10;
11132 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11133 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11134 } else
11135 eeprom_phy_id = 0;
11136
7d0c41ef 11137 tp->phy_id = eeprom_phy_id;
747e8f8b 11138 if (eeprom_phy_serdes) {
a4e2b347 11139 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11140 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11141 else
11142 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11143 }
7d0c41ef 11144
cbf46853 11145 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11146 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11147 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11148 else
1da177e4
LT		 11149 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11150
11151 switch (led_cfg) {
11152 default:
11153 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11154 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11155 break;
11156
11157 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11158 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11159 break;
11160
11161 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11162 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11163
11164 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11165 * read on some older 5700/5701 bootcode.
11166 */
11167 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11168 ASIC_REV_5700 ||
11169 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11170 ASIC_REV_5701)
11171 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11172
1da177e4
LT		 11173 break;
11174
11175 case SHASTA_EXT_LED_SHARED:
11176 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11177 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11178 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11179 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11180 LED_CTRL_MODE_PHY_2);
11181 break;
11182
11183 case SHASTA_EXT_LED_MAC:
11184 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11185 break;
11186
11187 case SHASTA_EXT_LED_COMBO:
11188 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11189 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11190 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11191 LED_CTRL_MODE_PHY_2);
11192 break;
11193
855e1111 11194 }
1da177e4
LT		 11195
11196 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11197 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11198 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11199 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11200
b2a5c19c
MC		 11201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11202 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11203
9d26e213 11204 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11205 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11206 if ((tp->pdev->subsystem_vendor ==
11207 PCI_VENDOR_ID_ARIMA) &&
11208 (tp->pdev->subsystem_device == 0x205a ||
11209 tp->pdev->subsystem_device == 0x2063))
11210 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11211 } else {
f49639e6 11212 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11213 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11214 }
1da177e4
LT		 11215
11216 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11217 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11218 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11219 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11220 }
b2b98d4a
MC		 11221
11222 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11223 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11224 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11225
a85feb8c
GZ		 11226 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11227 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11228 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11229
12dac075 11230 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11231 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11232 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11233
1da177e4
LT		 11234 if (cfg2 & (1 << 17))
11235 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11236
11237 /* serdes signal pre-emphasis in register 0x590 set by */
11238 /* bootcode if bit 18 is set */
11239 if (cfg2 & (1 << 18))
11240 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11241
321d32a0
MC		 11242 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11243 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11244 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11245 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11246
8ed5d97e
MC		 11247 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11248 u32 cfg3;
11249
11250 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11251 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11252 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11253 }
a9daf367
MC		 11254
11255 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11256 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11257 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11258 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11259 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11260 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11261 }
05ac4cb7
MC		 11262done:
11263 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11264 device_set_wakeup_enable(&tp->pdev->dev,
11265 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11266}
11267
b2a5c19c
MC		 11268static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11269{
11270 int i;
11271 u32 val;
11272
11273 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11274 tw32(OTP_CTRL, cmd);
11275
11276 /* Wait for up to 1 ms for command to execute. */
11277 for (i = 0; i < 100; i++) {
11278 val = tr32(OTP_STATUS);
11279 if (val & OTP_STATUS_CMD_DONE)
11280 break;
11281 udelay(10);
11282 }
11283
11284 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11285}
11286
11287/* Read the gphy configuration from the OTP region of the chip. The gphy
11288 * configuration is a 32-bit value that straddles the alignment boundary.
11289 * We do two 32-bit reads and then shift and merge the results.
11290 */
11291static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11292{
11293 u32 bhalf_otp, thalf_otp;
11294
11295 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11296
11297 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11298 return 0;
11299
11300 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11301
11302 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11303 return 0;
11304
11305 thalf_otp = tr32(OTP_READ_DATA);
11306
11307 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11308
11309 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11310 return 0;
11311
11312 bhalf_otp = tr32(OTP_READ_DATA);
11313
11314 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11315}
11316
7d0c41ef
MC		 11317static int __devinit tg3_phy_probe(struct tg3 *tp)
11318{
11319 u32 hw_phy_id_1, hw_phy_id_2;
11320 u32 hw_phy_id, hw_phy_id_masked;
11321 int err;
1da177e4 11322
b02fd9e3
MC		 11323 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11324 return tg3_phy_init(tp);
11325
1da177e4 11326 /* Reading the PHY ID register can conflict with ASF
877d0310 11327 * firmware access to the PHY hardware.
1da177e4
LT		 11328 */
11329 err = 0;
0d3031d9
MC		 11330 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11331 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11332 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11333 } else {
11334 /* Now read the physical PHY_ID from the chip and verify
11335 * that it is sane. If it doesn't look good, we fall back
11336 * to either the hard-coded table based PHY_ID and failing
11337 * that the value found in the eeprom area.
11338 */
11339 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11340 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11341
11342 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11343 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11344 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11345
11346 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11347 }
11348
11349 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11350 tp->phy_id = hw_phy_id;
11351 if (hw_phy_id_masked == PHY_ID_BCM8002)
11352 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11353 else
11354 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11355 } else {
7d0c41ef
MC		 11356 if (tp->phy_id != PHY_ID_INVALID) {
11357 /* Do nothing, phy ID already set up in
11358 * tg3_get_eeprom_hw_cfg().
11359 */
1da177e4
LT		 11360 } else {
11361 struct subsys_tbl_ent *p;
11362
11363 /* No eeprom signature? Try the hardcoded
11364 * subsys device table.
11365 */
11366 p = lookup_by_subsys(tp);
11367 if (!p)
11368 return -ENODEV;
11369
11370 tp->phy_id = p->phy_id;
11371 if (!tp->phy_id ||
11372 tp->phy_id == PHY_ID_BCM8002)
11373 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11374 }
11375 }
11376
747e8f8b 11377 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11378 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11379 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11380 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11381
11382 tg3_readphy(tp, MII_BMSR, &bmsr);
11383 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11384 (bmsr & BMSR_LSTATUS))
11385 goto skip_phy_reset;
6aa20a22 11386
1da177e4
LT		 11387 err = tg3_phy_reset(tp);
11388 if (err)
11389 return err;
11390
11391 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11392 ADVERTISE_100HALF | ADVERTISE_100FULL |
11393 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11394 tg3_ctrl = 0;
11395 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11396 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11397 MII_TG3_CTRL_ADV_1000_FULL);
11398 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11399 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11400 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11401 MII_TG3_CTRL_ENABLE_AS_MASTER);
11402 }
11403
3600d918
MC		 11404 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11405 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11406 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11407 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11408 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11409
11410 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11411 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11412
11413 tg3_writephy(tp, MII_BMCR,
11414 BMCR_ANENABLE | BMCR_ANRESTART);
11415 }
11416 tg3_phy_set_wirespeed(tp);
11417
11418 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11419 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11420 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11421 }
11422
11423skip_phy_reset:
11424 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11425 err = tg3_init_5401phy_dsp(tp);
11426 if (err)
11427 return err;
11428 }
11429
11430 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11431 err = tg3_init_5401phy_dsp(tp);
11432 }
11433
747e8f8b 11434 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11435 tp->link_config.advertising =
11436 (ADVERTISED_1000baseT_Half |
11437 ADVERTISED_1000baseT_Full |
11438 ADVERTISED_Autoneg |
11439 ADVERTISED_FIBRE);
11440 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11441 tp->link_config.advertising &=
11442 ~(ADVERTISED_1000baseT_Half |
11443 ADVERTISED_1000baseT_Full);
11444
11445 return err;
11446}
11447
11448static void __devinit tg3_read_partno(struct tg3 *tp)
11449{
6d348f2c 11450 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11451 unsigned int i;
1b27777a 11452 u32 magic;
1da177e4 11453
df259d8c
MC		 11454 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11455 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11456 goto out_not_found;
1da177e4 11457
1820180b 11458 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11459 for (i = 0; i < 256; i += 4) {
11460 u32 tmp;
1da177e4 11461
6d348f2c
MC		 11462 /* The data is in little-endian format in NVRAM.
11463 * Use the big-endian read routines to preserve
11464 * the byte order as it exists in NVRAM.
11465 */
11466 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11467 goto out_not_found;
11468
6d348f2c 11469 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11470 }
11471 } else {
11472 int vpd_cap;
11473
11474 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11475 for (i = 0; i < 256; i += 4) {
11476 u32 tmp, j = 0;
b9fc7dc5 11477 __le32 v;
1b27777a
MC		 11478 u16 tmp16;
11479
11480 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11481 i);
11482 while (j++ < 100) {
11483 pci_read_config_word(tp->pdev, vpd_cap +
11484 PCI_VPD_ADDR, &tmp16);
11485 if (tmp16 & 0x8000)
11486 break;
11487 msleep(1);
11488 }
f49639e6
DM		 11489 if (!(tmp16 & 0x8000))
11490 goto out_not_found;
11491
1b27777a
MC		 11492 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11493 &tmp);
b9fc7dc5 11494 v = cpu_to_le32(tmp);
6d348f2c 11495 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11496 }
1da177e4
LT		 11497 }
11498
11499 /* Now parse and find the part number. */
af2c6a4a 11500 for (i = 0; i < 254; ) {
1da177e4 11501 unsigned char val = vpd_data[i];
af2c6a4a 11502 unsigned int block_end;
1da177e4
LT		 11503
11504 if (val == 0x82 || val == 0x91) {
11505 i = (i + 3 +
11506 (vpd_data[i + 1] +
11507 (vpd_data[i + 2] << 8)));
11508 continue;
11509 }
11510
11511 if (val != 0x90)
11512 goto out_not_found;
11513
11514 block_end = (i + 3 +
11515 (vpd_data[i + 1] +
11516 (vpd_data[i + 2] << 8)));
11517 i += 3;
af2c6a4a
MC		 11518
11519 if (block_end > 256)
11520 goto out_not_found;
11521
11522 while (i < (block_end - 2)) {
1da177e4
LT		 11523 if (vpd_data[i + 0] == 'P' &&
11524 vpd_data[i + 1] == 'N') {
11525 int partno_len = vpd_data[i + 2];
11526
af2c6a4a
MC		 11527 i += 3;
11528 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11529 goto out_not_found;
11530
11531 memcpy(tp->board_part_number,
af2c6a4a 11532 &vpd_data[i], partno_len);
1da177e4
LT		 11533
11534 /* Success. */
11535 return;
11536 }
af2c6a4a 11537 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11538 }
11539
11540 /* Part number not found. */
11541 goto out_not_found;
11542 }
11543
11544out_not_found:
b5d3772c
MC		 11545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11546 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 11547 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11548 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11549 strcpy(tp->board_part_number, "BCM57780");
11550 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11551 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11552 strcpy(tp->board_part_number, "BCM57760");
11553 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11554 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11555 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 11556 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11557 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11558 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 11559 else
11560 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11561}
11562
9c8a620e
MC		 11563static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11564{
11565 u32 val;
11566
e4f34110 11567 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11568 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11569 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11570 val != 0)
11571 return 0;
11572
11573 return 1;
11574}
11575
acd9c119
MC		 11576static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11577{
ff3a7cb2 11578 u32 val, offset, start, ver_offset;
acd9c119 11579 int i;
ff3a7cb2 11580 bool newver = false;
acd9c119
MC		 11581
11582 if (tg3_nvram_read(tp, 0xc, &offset) ||
11583 tg3_nvram_read(tp, 0x4, &start))
11584 return;
11585
11586 offset = tg3_nvram_logical_addr(tp, offset);
11587
ff3a7cb2 11588 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11589 return;
11590
ff3a7cb2
MC		 11591 if ((val & 0xfc000000) == 0x0c000000) {
11592 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11593 return;
11594
ff3a7cb2
MC		 11595 if (val == 0)
11596 newver = true;
11597 }
11598
11599 if (newver) {
11600 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11601 return;
11602
11603 offset = offset + ver_offset - start;
11604 for (i = 0; i < 16; i += 4) {
11605 __be32 v;
11606 if (tg3_nvram_read_be32(tp, offset + i, &v))
11607 return;
11608
11609 memcpy(tp->fw_ver + i, &v, sizeof(v));
11610 }
11611 } else {
11612 u32 major, minor;
11613
11614 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11615 return;
11616
11617 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11618 TG3_NVM_BCVER_MAJSFT;
11619 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11620 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11621 }
11622}
11623
a6f6cb1c
MC		 11624static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11625{
11626 u32 val, major, minor;
11627
11628 /* Use native endian representation */
11629 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11630 return;
11631
11632 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11633 TG3_NVM_HWSB_CFG1_MAJSFT;
11634 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11635 TG3_NVM_HWSB_CFG1_MINSFT;
11636
11637 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11638}
11639
dfe00d7d
MC		 11640static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11641{
11642 u32 offset, major, minor, build;
11643
11644 tp->fw_ver[0] = 's';
11645 tp->fw_ver[1] = 'b';
11646 tp->fw_ver[2] = '\0';
11647
11648 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11649 return;
11650
11651 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11652 case TG3_EEPROM_SB_REVISION_0:
11653 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11654 break;
11655 case TG3_EEPROM_SB_REVISION_2:
11656 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11657 break;
11658 case TG3_EEPROM_SB_REVISION_3:
11659 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11660 break;
11661 default:
11662 return;
11663 }
11664
e4f34110 11665 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11666 return;
11667
11668 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11669 TG3_EEPROM_SB_EDH_BLD_SHFT;
11670 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11671 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11672 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11673
11674 if (minor > 99 || build > 26)
11675 return;
11676
11677 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11678
11679 if (build > 0) {
11680 tp->fw_ver[8] = 'a' + build - 1;
11681 tp->fw_ver[9] = '\0';
11682 }
11683}
11684
acd9c119 11685static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11686{
11687 u32 val, offset, start;
acd9c119 11688 int i, vlen;
9c8a620e
MC		 11689
11690 for (offset = TG3_NVM_DIR_START;
11691 offset < TG3_NVM_DIR_END;
11692 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11693 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11694 return;
11695
9c8a620e
MC		 11696 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11697 break;
11698 }
11699
11700 if (offset == TG3_NVM_DIR_END)
11701 return;
11702
11703 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11704 start = 0x08000000;
e4f34110 11705 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11706 return;
11707
e4f34110 11708 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11709 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11710 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11711 return;
11712
11713 offset += val - start;
11714
acd9c119 11715 vlen = strlen(tp->fw_ver);
9c8a620e 11716
acd9c119
MC		 11717 tp->fw_ver[vlen++] = ',';
11718 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11719
11720 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11721 __be32 v;
11722 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11723 return;
11724
b9fc7dc5 11725 offset += sizeof(v);
c4e6575c 11726
acd9c119
MC		 11727 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11728 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11729 break;
c4e6575c 11730 }
9c8a620e 11731
acd9c119
MC		 11732 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11733 vlen += sizeof(v);
c4e6575c 11734 }
acd9c119
MC		 11735}
11736
7fd76445
MC		 11737static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11738{
11739 int vlen;
11740 u32 apedata;
11741
11742 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11743 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11744 return;
11745
11746 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11747 if (apedata != APE_SEG_SIG_MAGIC)
11748 return;
11749
11750 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11751 if (!(apedata & APE_FW_STATUS_READY))
11752 return;
11753
11754 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11755
11756 vlen = strlen(tp->fw_ver);
11757
11758 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11759 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11760 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11761 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11762 (apedata & APE_FW_VERSION_BLDMSK));
11763}
11764
acd9c119
MC		 11765static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11766{
11767 u32 val;
11768
df259d8c
MC		 11769 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11770 tp->fw_ver[0] = 's';
11771 tp->fw_ver[1] = 'b';
11772 tp->fw_ver[2] = '\0';
11773
11774 return;
11775 }
11776
acd9c119
MC		 11777 if (tg3_nvram_read(tp, 0, &val))
11778 return;
11779
11780 if (val == TG3_EEPROM_MAGIC)
11781 tg3_read_bc_ver(tp);
11782 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11783 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11784 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11785 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11786 else
11787 return;
11788
11789 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11790 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11791 return;
11792
11793 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11794
11795 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11796}
11797
7544b097
MC		 11798static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11799
1da177e4
LT		 11800static int __devinit tg3_get_invariants(struct tg3 *tp)
11801{
11802 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11803 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11804 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11805 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11806 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11807 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11808 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11809 { },
11810 };
11811 u32 misc_ctrl_reg;
1da177e4
LT		 11812 u32 pci_state_reg, grc_misc_cfg;
11813 u32 val;
11814 u16 pci_cmd;
5e7dfd0f 11815 int err;
1da177e4 11816
1da177e4
LT		 11817 /* Force memory write invalidate off. If we leave it on,
11818 * then on 5700_BX chips we have to enable a workaround.
11819 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11820 * to match the cacheline size. The Broadcom driver have this
11821 * workaround but turns MWI off all the times so never uses
11822 * it. This seems to suggest that the workaround is insufficient.
11823 */
11824 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11825 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11826 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11827
11828 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11829 * has the register indirect write enable bit set before
11830 * we try to access any of the MMIO registers. It is also
11831 * critical that the PCI-X hw workaround situation is decided
11832 * before that as well.
11833 */
11834 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11835 &misc_ctrl_reg);
11836
11837 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11838 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11840 u32 prod_id_asic_rev;
11841
11842 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11843 &prod_id_asic_rev);
321d32a0 11844 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11845 }
1da177e4 11846
ff645bec
MC		 11847 /* Wrong chip ID in 5752 A0. This code can be removed later
11848 * as A0 is not in production.
11849 */
11850 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11851 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11852
6892914f
MC		 11853 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11854 * we need to disable memory and use config. cycles
11855 * only to access all registers. The 5702/03 chips
11856 * can mistakenly decode the special cycles from the
11857 * ICH chipsets as memory write cycles, causing corruption
11858 * of register and memory space. Only certain ICH bridges
11859 * will drive special cycles with non-zero data during the
11860 * address phase which can fall within the 5703's address
11861 * range. This is not an ICH bug as the PCI spec allows
11862 * non-zero address during special cycles. However, only
11863 * these ICH bridges are known to drive non-zero addresses
11864 * during special cycles.
11865 *
11866 * Since special cycles do not cross PCI bridges, we only
11867 * enable this workaround if the 5703 is on the secondary
11868 * bus of these ICH bridges.
11869 */
11870 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11871 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11872 static struct tg3_dev_id {
11873 u32 vendor;
11874 u32 device;
11875 u32 rev;
11876 } ich_chipsets[] = {
11877 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11878 PCI_ANY_ID },
11879 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11880 PCI_ANY_ID },
11881 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11882 0xa },
11883 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11884 PCI_ANY_ID },
11885 { },
11886 };
11887 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11888 struct pci_dev *bridge = NULL;
11889
11890 while (pci_id->vendor != 0) {
11891 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11892 bridge);
11893 if (!bridge) {
11894 pci_id++;
11895 continue;
11896 }
11897 if (pci_id->rev != PCI_ANY_ID) {
44c10138 11898 if (bridge->revision > pci_id->rev)
6892914f
MC		 11899 continue;
11900 }
11901 if (bridge->subordinate &&
11902 (bridge->subordinate->number ==
11903 tp->pdev->bus->number)) {
11904
11905 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11906 pci_dev_put(bridge);
11907 break;
11908 }
11909 }
11910 }
11911
41588ba1
MC		 11912 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11913 static struct tg3_dev_id {
11914 u32 vendor;
11915 u32 device;
11916 } bridge_chipsets[] = {
11917 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11918 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11919 { },
11920 };
11921 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11922 struct pci_dev *bridge = NULL;
11923
11924 while (pci_id->vendor != 0) {
11925 bridge = pci_get_device(pci_id->vendor,
11926 pci_id->device,
11927 bridge);
11928 if (!bridge) {
11929 pci_id++;
11930 continue;
11931 }
11932 if (bridge->subordinate &&
11933 (bridge->subordinate->number <=
11934 tp->pdev->bus->number) &&
11935 (bridge->subordinate->subordinate >=
11936 tp->pdev->bus->number)) {
11937 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11938 pci_dev_put(bridge);
11939 break;
11940 }
11941 }
11942 }
11943
4a29cc2e
MC		 11944 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11945 * DMA addresses > 40-bit. This bridge may have other additional
11946 * 57xx devices behind it in some 4-port NIC designs for example.
11947 * Any tg3 device found behind the bridge will also need the 40-bit
11948 * DMA workaround.
11949 */
a4e2b347
MC		 11950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11952 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 11953 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 11954 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 11955 }
4a29cc2e
MC		 11956 else {
11957 struct pci_dev *bridge = NULL;
11958
11959 do {
11960 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11961 PCI_DEVICE_ID_SERVERWORKS_EPB,
11962 bridge);
11963 if (bridge && bridge->subordinate &&
11964 (bridge->subordinate->number <=
11965 tp->pdev->bus->number) &&
11966 (bridge->subordinate->subordinate >=
11967 tp->pdev->bus->number)) {
11968 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11969 pci_dev_put(bridge);
11970 break;
11971 }
11972 } while (bridge);
11973 }
4cf78e4f 11974
1da177e4
LT		 11975 /* Initialize misc host control in PCI block. */
11976 tp->misc_host_ctrl |= (misc_ctrl_reg &
11977 MISC_HOST_CTRL_CHIPREV);
11978 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11979 tp->misc_host_ctrl);
11980
7544b097
MC		 11981 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11982 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11983 tp->pdev_peer = tg3_find_peer(tp);
11984
321d32a0
MC		 11985 /* Intentionally exclude ASIC_REV_5906 */
11986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 11987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 11988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 11989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 11990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 11991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11992 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11993
11994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 11996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 11997 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 11998 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 11999 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12000
1b440c56
JL		 12001 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12002 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12003 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12004
027455ad
MC		 12005 /* 5700 B0 chips do not support checksumming correctly due
12006 * to hardware bugs.
12007 */
12008 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12009 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12010 else {
12011 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12012 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12013 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12014 tp->dev->features |= NETIF_F_IPV6_CSUM;
12015 }
12016
5a6f3074 12017 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12018 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12019 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12020 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12021 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12022 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12023 tp->pdev_peer == tp->pdev))
12024 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12025
321d32a0 12026 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12028 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12029 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12030 } else {
7f62ad5d 12031 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12032 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12033 ASIC_REV_5750 &&
12034 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12035 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12036 }
5a6f3074 12037 }
1da177e4 12038
f51f3562
MC		 12039 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12040 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8f666b07 12041 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12042
52f4490c
MC		 12043 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12044 &pci_state_reg);
12045
5e7dfd0f
MC		 12046 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12047 if (tp->pcie_cap != 0) {
12048 u16 lnkctl;
12049
1da177e4 12050 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12051
12052 pcie_set_readrq(tp->pdev, 4096);
12053
5e7dfd0f
MC		 12054 pci_read_config_word(tp->pdev,
12055 tp->pcie_cap + PCI_EXP_LNKCTL,
12056 &lnkctl);
12057 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12059 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12061 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12062 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12063 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12064 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12065 }
52f4490c 12066 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12067 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12068 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12069 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12070 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12071 if (!tp->pcix_cap) {
12072 printk(KERN_ERR PFX "Cannot find PCI-X "
12073 "capability, aborting.\n");
12074 return -EIO;
12075 }
12076
12077 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12078 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12079 }
1da177e4 12080
399de50b
MC		 12081 /* If we have an AMD 762 or VIA K8T800 chipset, write
12082 * reordering to the mailbox registers done by the host
12083 * controller can cause major troubles. We read back from
12084 * every mailbox register write to force the writes to be
12085 * posted to the chip in order.
12086 */
12087 if (pci_dev_present(write_reorder_chipsets) &&
12088 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12089 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12090
69fc4053
MC		 12091 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12092 &tp->pci_cacheline_sz);
12093 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12094 &tp->pci_lat_timer);
1da177e4
LT		 12095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12096 tp->pci_lat_timer < 64) {
12097 tp->pci_lat_timer = 64;
69fc4053
MC		 12098 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12099 tp->pci_lat_timer);
1da177e4
LT		 12100 }
12101
52f4490c
MC		 12102 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12103 /* 5700 BX chips need to have their TX producer index
12104 * mailboxes written twice to workaround a bug.
12105 */
12106 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12107
52f4490c 12108 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12109 *
12110 * The workaround is to use indirect register accesses
12111 * for all chip writes not to mailbox registers.
12112 */
52f4490c 12113 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12114 u32 pm_reg;
1da177e4
LT		 12115
12116 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12117
12118 /* The chip can have it's power management PCI config
12119 * space registers clobbered due to this bug.
12120 * So explicitly force the chip into D0 here.
12121 */
9974a356
MC		 12122 pci_read_config_dword(tp->pdev,
12123 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12124 &pm_reg);
12125 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12126 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12127 pci_write_config_dword(tp->pdev,
12128 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12129 pm_reg);
12130
12131 /* Also, force SERR#/PERR# in PCI command. */
12132 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12133 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12134 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12135 }
12136 }
12137
1da177e4
LT		 12138 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12139 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12140 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12141 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12142
12143 /* Chip-specific fixup from Broadcom driver */
12144 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12145 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12146 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12147 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12148 }
12149
1ee582d8 12150 /* Default fast path register access methods */
20094930 12151 tp->read32 = tg3_read32;
1ee582d8 12152 tp->write32 = tg3_write32;
09ee929c 12153 tp->read32_mbox = tg3_read32;
20094930 12154 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12155 tp->write32_tx_mbox = tg3_write32;
12156 tp->write32_rx_mbox = tg3_write32;
12157
12158 /* Various workaround register access methods */
12159 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12160 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12161 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12162 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12163 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12164 /*
12165 * Back to back register writes can cause problems on these
12166 * chips, the workaround is to read back all reg writes
12167 * except those to mailbox regs.
12168 *
12169 * See tg3_write_indirect_reg32().
12170 */
1ee582d8 12171 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12172 }
12173
1ee582d8
MC		 12174
12175 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12176 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12177 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12178 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12179 tp->write32_rx_mbox = tg3_write_flush_reg32;
12180 }
20094930 12181
6892914f
MC		 12182 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12183 tp->read32 = tg3_read_indirect_reg32;
12184 tp->write32 = tg3_write_indirect_reg32;
12185 tp->read32_mbox = tg3_read_indirect_mbox;
12186 tp->write32_mbox = tg3_write_indirect_mbox;
12187 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12188 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12189
12190 iounmap(tp->regs);
22abe310 12191 tp->regs = NULL;
6892914f
MC		 12192
12193 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12194 pci_cmd &= ~PCI_COMMAND_MEMORY;
12195 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12196 }
b5d3772c
MC		 12197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12198 tp->read32_mbox = tg3_read32_mbox_5906;
12199 tp->write32_mbox = tg3_write32_mbox_5906;
12200 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12201 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12202 }
6892914f 12203
bbadf503
MC		 12204 if (tp->write32 == tg3_write_indirect_reg32 ||
12205 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12206 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12208 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12209
7d0c41ef 12210 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12211 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12212 * determined before calling tg3_set_power_state() so that
12213 * we know whether or not to switch out of Vaux power.
12214 * When the flag is set, it means that GPIO1 is used for eeprom
12215 * write protect and also implies that it is a LOM where GPIOs
12216 * are not used to switch power.
6aa20a22 12217 */
7d0c41ef
MC		 12218 tg3_get_eeprom_hw_cfg(tp);
12219
0d3031d9
MC		 12220 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12221 /* Allow reads and writes to the
12222 * APE register and memory space.
12223 */
12224 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12225 PCISTATE_ALLOW_APE_SHMEM_WR;
12226 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12227 pci_state_reg);
12228 }
12229
9936bcf6 12230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12232 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12233 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12234 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12235
314fba34
MC		 12236 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12237 * GPIO1 driven high will bring 5700's external PHY out of reset.
12238 * It is also used as eeprom write protect on LOMs.
12239 */
12240 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12241 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12242 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12243 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12244 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12245 /* Unused GPIO3 must be driven as output on 5752 because there
12246 * are no pull-up resistors on unused GPIO pins.
12247 */
12248 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12249 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12250
321d32a0
MC		 12251 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12252 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12253 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12254
8d519ab2
MC		 12255 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12256 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12257 /* Turn off the debug UART. */
12258 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12259 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12260 /* Keep VMain power. */
12261 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12262 GRC_LCLCTRL_GPIO_OUTPUT0;
12263 }
12264
1da177e4 12265 /* Force the chip into D0. */
bc1c7567 12266 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12267 if (err) {
12268 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12269 pci_name(tp->pdev));
12270 return err;
12271 }
12272
1da177e4
LT		 12273 /* Derive initial jumbo mode from MTU assigned in
12274 * ether_setup() via the alloc_etherdev() call
12275 */
0f893dc6 12276 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12277 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12278 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12279
12280 /* Determine WakeOnLan speed to use. */
12281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12282 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12283 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12284 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12285 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12286 } else {
12287 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12288 }
12289
7f97a4bd
MC		 12290 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12291 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12292
1da177e4
LT		 12293 /* A few boards don't want Ethernet@WireSpeed phy feature */
12294 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12295 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12296 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12297 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12298 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12299 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12300 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12301
12302 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12303 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12304 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12305 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12306 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12307
321d32a0 12308 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12309 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0
MC		 12310 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12311 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12313 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12314 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12316 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12317 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12318 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12319 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12320 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12321 } else
c424cb24
MC		 12322 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12323 }
1da177e4 12324
b2a5c19c
MC		 12325 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12326 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12327 tp->phy_otp = tg3_read_otp_phycfg(tp);
12328 if (tp->phy_otp == 0)
12329 tp->phy_otp = TG3_OTP_DEFAULT;
12330 }
12331
f51f3562 12332 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12333 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12334 else
12335 tp->mi_mode = MAC_MI_MODE_BASE;
12336
1da177e4 12337 tp->coalesce_mode = 0;
1da177e4
LT		 12338 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12339 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12340 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12341
321d32a0
MC		 12342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12343 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12344 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12345
255ca311
MC		 12346 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12347 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12348 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12349 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12350
158d7abd
MC		 12351 err = tg3_mdio_init(tp);
12352 if (err)
12353 return err;
1da177e4
LT		 12354
12355 /* Initialize data/descriptor byte/word swapping. */
12356 val = tr32(GRC_MODE);
12357 val &= GRC_MODE_HOST_STACKUP;
12358 tw32(GRC_MODE, val | tp->grc_mode);
12359
12360 tg3_switch_clocks(tp);
12361
12362 /* Clear this out for sanity. */
12363 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12364
12365 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12366 &pci_state_reg);
12367 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12368 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12369 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12370
12371 if (chiprevid == CHIPREV_ID_5701_A0 ||
12372 chiprevid == CHIPREV_ID_5701_B0 ||
12373 chiprevid == CHIPREV_ID_5701_B2 ||
12374 chiprevid == CHIPREV_ID_5701_B5) {
12375 void __iomem *sram_base;
12376
12377 /* Write some dummy words into the SRAM status block
12378 * area, see if it reads back correctly. If the return
12379 * value is bad, force enable the PCIX workaround.
12380 */
12381 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12382
12383 writel(0x00000000, sram_base);
12384 writel(0x00000000, sram_base + 4);
12385 writel(0xffffffff, sram_base + 4);
12386 if (readl(sram_base) != 0x00000000)
12387 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12388 }
12389 }
12390
12391 udelay(50);
12392 tg3_nvram_init(tp);
12393
12394 grc_misc_cfg = tr32(GRC_MISC_CFG);
12395 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12396
1da177e4
LT		 12397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12398 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12399 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12400 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12401
fac9b83e
DM		 12402 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12403 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12404 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12405 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12406 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12407 HOSTCC_MODE_CLRTICK_TXBD);
12408
12409 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12410 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12411 tp->misc_host_ctrl);
12412 }
12413
3bda1258
MC		 12414 /* Preserve the APE MAC_MODE bits */
12415 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12416 tp->mac_mode = tr32(MAC_MODE) |
12417 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12418 else
12419 tp->mac_mode = TG3_DEF_MAC_MODE;
12420
1da177e4
LT		 12421 /* these are limited to 10/100 only */
12422 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12423 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12424 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12425 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12426 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12427 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12428 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12429 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12430 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12431 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12432 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12433 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 12434 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 12435 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12436
12437 err = tg3_phy_probe(tp);
12438 if (err) {
12439 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12440 pci_name(tp->pdev), err);
12441 /* ... but do not return immediately ... */
b02fd9e3 12442 tg3_mdio_fini(tp);
1da177e4
LT		 12443 }
12444
12445 tg3_read_partno(tp);
c4e6575c 12446 tg3_read_fw_ver(tp);
1da177e4
LT		 12447
12448 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12449 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12450 } else {
12451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12452 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12453 else
12454 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12455 }
12456
12457 /* 5700 {AX,BX} chips have a broken status block link
12458 * change bit implementation, so we must use the
12459 * status register in those cases.
12460 */
12461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12462 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12463 else
12464 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12465
12466 /* The led_ctrl is set during tg3_phy_probe, here we might
12467 * have to force the link status polling mechanism based
12468 * upon subsystem IDs.
12469 */
12470 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12471 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12472 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12473 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12474 TG3_FLAG_USE_LINKCHG_REG);
12475 }
12476
12477 /* For all SERDES we poll the MAC status register. */
12478 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12479 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12480 else
12481 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12482
ad829268 12483 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12485 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12486 tp->rx_offset = 0;
12487
f92905de
MC		 12488 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12489
12490 /* Increment the rx prod index on the rx std ring by at most
12491 * 8 for these chips to workaround hw errata.
12492 */
12493 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12494 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12495 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12496 tp->rx_std_max_post = 8;
12497
8ed5d97e
MC		 12498 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12499 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12500 PCIE_PWR_MGMT_L1_THRESH_MSK;
12501
1da177e4
LT		 12502 return err;
12503}
12504
49b6e95f 12505#ifdef CONFIG_SPARC
1da177e4
LT		 12506static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12507{
12508 struct net_device *dev = tp->dev;
12509 struct pci_dev *pdev = tp->pdev;
49b6e95f 12510 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12511 const unsigned char *addr;
49b6e95f
DM		 12512 int len;
12513
12514 addr = of_get_property(dp, "local-mac-address", &len);
12515 if (addr && len == 6) {
12516 memcpy(dev->dev_addr, addr, 6);
12517 memcpy(dev->perm_addr, dev->dev_addr, 6);
12518 return 0;
1da177e4
LT		 12519 }
12520 return -ENODEV;
12521}
12522
12523static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12524{
12525 struct net_device *dev = tp->dev;
12526
12527 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12528 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12529 return 0;
12530}
12531#endif
12532
12533static int __devinit tg3_get_device_address(struct tg3 *tp)
12534{
12535 struct net_device *dev = tp->dev;
12536 u32 hi, lo, mac_offset;
008652b3 12537 int addr_ok = 0;
1da177e4 12538
49b6e95f 12539#ifdef CONFIG_SPARC
1da177e4
LT		 12540 if (!tg3_get_macaddr_sparc(tp))
12541 return 0;
12542#endif
12543
12544 mac_offset = 0x7c;
f49639e6 12545 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12546 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12547 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12548 mac_offset = 0xcc;
12549 if (tg3_nvram_lock(tp))
12550 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12551 else
12552 tg3_nvram_unlock(tp);
12553 }
b5d3772c
MC		 12554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12555 mac_offset = 0x10;
1da177e4
LT		 12556
12557 /* First try to get it from MAC address mailbox. */
12558 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12559 if ((hi >> 16) == 0x484b) {
12560 dev->dev_addr[0] = (hi >> 8) & 0xff;
12561 dev->dev_addr[1] = (hi >> 0) & 0xff;
12562
12563 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12564 dev->dev_addr[2] = (lo >> 24) & 0xff;
12565 dev->dev_addr[3] = (lo >> 16) & 0xff;
12566 dev->dev_addr[4] = (lo >> 8) & 0xff;
12567 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12568
008652b3
MC		 12569 /* Some old bootcode may report a 0 MAC address in SRAM */
12570 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12571 }
12572 if (!addr_ok) {
12573 /* Next, try NVRAM. */
df259d8c
MC		 12574 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12575 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12576 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12577 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12578 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12579 }
12580 /* Finally just fetch it out of the MAC control regs. */
12581 else {
12582 hi = tr32(MAC_ADDR_0_HIGH);
12583 lo = tr32(MAC_ADDR_0_LOW);
12584
12585 dev->dev_addr[5] = lo & 0xff;
12586 dev->dev_addr[4] = (lo >> 8) & 0xff;
12587 dev->dev_addr[3] = (lo >> 16) & 0xff;
12588 dev->dev_addr[2] = (lo >> 24) & 0xff;
12589 dev->dev_addr[1] = hi & 0xff;
12590 dev->dev_addr[0] = (hi >> 8) & 0xff;
12591 }
1da177e4
LT		 12592 }
12593
12594 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12595#ifdef CONFIG_SPARC
1da177e4
LT		 12596 if (!tg3_get_default_macaddr_sparc(tp))
12597 return 0;
12598#endif
12599 return -EINVAL;
12600 }
2ff43697 12601 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12602 return 0;
12603}
12604
59e6b434
DM		 12605#define BOUNDARY_SINGLE_CACHELINE 1
12606#define BOUNDARY_MULTI_CACHELINE 2
12607
12608static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12609{
12610 int cacheline_size;
12611 u8 byte;
12612 int goal;
12613
12614 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12615 if (byte == 0)
12616 cacheline_size = 1024;
12617 else
12618 cacheline_size = (int) byte * 4;
12619
12620 /* On 5703 and later chips, the boundary bits have no
12621 * effect.
12622 */
12623 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12624 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12625 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12626 goto out;
12627
12628#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12629 goal = BOUNDARY_MULTI_CACHELINE;
12630#else
12631#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12632 goal = BOUNDARY_SINGLE_CACHELINE;
12633#else
12634 goal = 0;
12635#endif
12636#endif
12637
12638 if (!goal)
12639 goto out;
12640
12641 /* PCI controllers on most RISC systems tend to disconnect
12642 * when a device tries to burst across a cache-line boundary.
12643 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12644 *
12645 * Unfortunately, for PCI-E there are only limited
12646 * write-side controls for this, and thus for reads
12647 * we will still get the disconnects. We'll also waste
12648 * these PCI cycles for both read and write for chips
12649 * other than 5700 and 5701 which do not implement the
12650 * boundary bits.
12651 */
12652 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12653 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12654 switch (cacheline_size) {
12655 case 16:
12656 case 32:
12657 case 64:
12658 case 128:
12659 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12660 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12661 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12662 } else {
12663 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12664 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12665 }
12666 break;
12667
12668 case 256:
12669 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12670 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12671 break;
12672
12673 default:
12674 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12675 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12676 break;
855e1111 12677 }
59e6b434
DM		 12678 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12679 switch (cacheline_size) {
12680 case 16:
12681 case 32:
12682 case 64:
12683 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12684 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12685 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12686 break;
12687 }
12688 /* fallthrough */
12689 case 128:
12690 default:
12691 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12692 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12693 break;
855e1111 12694 }
59e6b434
DM		 12695 } else {
12696 switch (cacheline_size) {
12697 case 16:
12698 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12699 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12700 DMA_RWCTRL_WRITE_BNDRY_16);
12701 break;
12702 }
12703 /* fallthrough */
12704 case 32:
12705 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12706 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12707 DMA_RWCTRL_WRITE_BNDRY_32);
12708 break;
12709 }
12710 /* fallthrough */
12711 case 64:
12712 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12713 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12714 DMA_RWCTRL_WRITE_BNDRY_64);
12715 break;
12716 }
12717 /* fallthrough */
12718 case 128:
12719 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12720 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12721 DMA_RWCTRL_WRITE_BNDRY_128);
12722 break;
12723 }
12724 /* fallthrough */
12725 case 256:
12726 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12727 DMA_RWCTRL_WRITE_BNDRY_256);
12728 break;
12729 case 512:
12730 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12731 DMA_RWCTRL_WRITE_BNDRY_512);
12732 break;
12733 case 1024:
12734 default:
12735 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12736 DMA_RWCTRL_WRITE_BNDRY_1024);
12737 break;
855e1111 12738 }
59e6b434
DM		 12739 }
12740
12741out:
12742 return val;
12743}
12744
1da177e4
LT		 12745static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12746{
12747 struct tg3_internal_buffer_desc test_desc;
12748 u32 sram_dma_descs;
12749 int i, ret;
12750
12751 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12752
12753 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12754 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12755 tw32(RDMAC_STATUS, 0);
12756 tw32(WDMAC_STATUS, 0);
12757
12758 tw32(BUFMGR_MODE, 0);
12759 tw32(FTQ_RESET, 0);
12760
12761 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12762 test_desc.addr_lo = buf_dma & 0xffffffff;
12763 test_desc.nic_mbuf = 0x00002100;
12764 test_desc.len = size;
12765
12766 /*
12767 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12768 * the *second* time the tg3 driver was getting loaded after an
12769 * initial scan.
12770 *
12771 * Broadcom tells me:
12772 * ...the DMA engine is connected to the GRC block and a DMA
12773 * reset may affect the GRC block in some unpredictable way...
12774 * The behavior of resets to individual blocks has not been tested.
12775 *
12776 * Broadcom noted the GRC reset will also reset all sub-components.
12777 */
12778 if (to_device) {
12779 test_desc.cqid_sqid = (13 << 8) | 2;
12780
12781 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12782 udelay(40);
12783 } else {
12784 test_desc.cqid_sqid = (16 << 8) | 7;
12785
12786 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12787 udelay(40);
12788 }
12789 test_desc.flags = 0x00000005;
12790
12791 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12792 u32 val;
12793
12794 val = *(((u32 *)&test_desc) + i);
12795 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12796 sram_dma_descs + (i * sizeof(u32)));
12797 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12798 }
12799 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12800
12801 if (to_device) {
12802 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12803 } else {
12804 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12805 }
12806
12807 ret = -ENODEV;
12808 for (i = 0; i < 40; i++) {
12809 u32 val;
12810
12811 if (to_device)
12812 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12813 else
12814 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12815 if ((val & 0xffff) == sram_dma_descs) {
12816 ret = 0;
12817 break;
12818 }
12819
12820 udelay(100);
12821 }
12822
12823 return ret;
12824}
12825
ded7340d 12826#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12827
12828static int __devinit tg3_test_dma(struct tg3 *tp)
12829{
12830 dma_addr_t buf_dma;
59e6b434 12831 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12832 int ret;
12833
12834 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12835 if (!buf) {
12836 ret = -ENOMEM;
12837 goto out_nofree;
12838 }
12839
12840 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12841 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12842
59e6b434 12843 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12844
12845 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12846 /* DMA read watermark not used on PCIE */
12847 tp->dma_rwctrl |= 0x00180000;
12848 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12850 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12851 tp->dma_rwctrl |= 0x003f0000;
12852 else
12853 tp->dma_rwctrl |= 0x003f000f;
12854 } else {
12855 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12856 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12857 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12858 u32 read_water = 0x7;
1da177e4 12859
4a29cc2e
MC		 12860 /* If the 5704 is behind the EPB bridge, we can
12861 * do the less restrictive ONE_DMA workaround for
12862 * better performance.
12863 */
12864 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12865 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12866 tp->dma_rwctrl |= 0x8000;
12867 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12868 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12869
49afdeb6
MC		 12870 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12871 read_water = 4;
59e6b434 12872 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12873 tp->dma_rwctrl |=
12874 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12875 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12876 (1 << 23);
4cf78e4f
MC		 12877 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12878 /* 5780 always in PCIX mode */
12879 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12880 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12881 /* 5714 always in PCIX mode */
12882 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12883 } else {
12884 tp->dma_rwctrl |= 0x001b000f;
12885 }
12886 }
12887
12888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12890 tp->dma_rwctrl &= 0xfffffff0;
12891
12892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12894 /* Remove this if it causes problems for some boards. */
12895 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12896
12897 /* On 5700/5701 chips, we need to set this bit.
12898 * Otherwise the chip will issue cacheline transactions
12899 * to streamable DMA memory with not all the byte
12900 * enables turned on. This is an error on several
12901 * RISC PCI controllers, in particular sparc64.
12902 *
12903 * On 5703/5704 chips, this bit has been reassigned
12904 * a different meaning. In particular, it is used
12905 * on those chips to enable a PCI-X workaround.
12906 */
12907 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12908 }
12909
12910 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12911
12912#if 0
12913 /* Unneeded, already done by tg3_get_invariants. */
12914 tg3_switch_clocks(tp);
12915#endif
12916
12917 ret = 0;
12918 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12919 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12920 goto out;
12921
59e6b434
DM		 12922 /* It is best to perform DMA test with maximum write burst size
12923 * to expose the 5700/5701 write DMA bug.
12924 */
12925 saved_dma_rwctrl = tp->dma_rwctrl;
12926 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12927 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12928
1da177e4
LT		 12929 while (1) {
12930 u32 *p = buf, i;
12931
12932 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12933 p[i] = i;
12934
12935 /* Send the buffer to the chip. */
12936 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12937 if (ret) {
12938 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12939 break;
12940 }
12941
12942#if 0
12943 /* validate data reached card RAM correctly. */
12944 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12945 u32 val;
12946 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12947 if (le32_to_cpu(val) != p[i]) {
12948 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12949 /* ret = -ENODEV here? */
12950 }
12951 p[i] = 0;
12952 }
12953#endif
12954 /* Now read it back. */
12955 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12956 if (ret) {
12957 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12958
12959 break;
12960 }
12961
12962 /* Verify it. */
12963 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12964 if (p[i] == i)
12965 continue;
12966
59e6b434
DM		 12967 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12968 DMA_RWCTRL_WRITE_BNDRY_16) {
12969 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 12970 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12971 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12972 break;
12973 } else {
12974 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12975 ret = -ENODEV;
12976 goto out;
12977 }
12978 }
12979
12980 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12981 /* Success. */
12982 ret = 0;
12983 break;
12984 }
12985 }
59e6b434
DM		 12986 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12987 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 12988 static struct pci_device_id dma_wait_state_chipsets[] = {
12989 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12990 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12991 { },
12992 };
12993
59e6b434 12994 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 12995 * now look for chipsets that are known to expose the
12996 * DMA bug without failing the test.
59e6b434 12997 */
6d1cfbab
MC		 12998 if (pci_dev_present(dma_wait_state_chipsets)) {
12999 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13000 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13001 }
13002 else
13003 /* Safe to use the calculated DMA boundary. */
13004 tp->dma_rwctrl = saved_dma_rwctrl;
13005
59e6b434
DM		 13006 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13007 }
1da177e4
LT		 13008
13009out:
13010 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13011out_nofree:
13012 return ret;
13013}
13014
13015static void __devinit tg3_init_link_config(struct tg3 *tp)
13016{
13017 tp->link_config.advertising =
13018 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13019 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13020 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13021 ADVERTISED_Autoneg | ADVERTISED_MII);
13022 tp->link_config.speed = SPEED_INVALID;
13023 tp->link_config.duplex = DUPLEX_INVALID;
13024 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13025 tp->link_config.active_speed = SPEED_INVALID;
13026 tp->link_config.active_duplex = DUPLEX_INVALID;
13027 tp->link_config.phy_is_low_power = 0;
13028 tp->link_config.orig_speed = SPEED_INVALID;
13029 tp->link_config.orig_duplex = DUPLEX_INVALID;
13030 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13031}
13032
13033static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13034{
fdfec172
MC		 13035 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13036 tp->bufmgr_config.mbuf_read_dma_low_water =
13037 DEFAULT_MB_RDMA_LOW_WATER_5705;
13038 tp->bufmgr_config.mbuf_mac_rx_low_water =
13039 DEFAULT_MB_MACRX_LOW_WATER_5705;
13040 tp->bufmgr_config.mbuf_high_water =
13041 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13043 tp->bufmgr_config.mbuf_mac_rx_low_water =
13044 DEFAULT_MB_MACRX_LOW_WATER_5906;
13045 tp->bufmgr_config.mbuf_high_water =
13046 DEFAULT_MB_HIGH_WATER_5906;
13047 }
fdfec172
MC		 13048
13049 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13050 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13051 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13052 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13053 tp->bufmgr_config.mbuf_high_water_jumbo =
13054 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13055 } else {
13056 tp->bufmgr_config.mbuf_read_dma_low_water =
13057 DEFAULT_MB_RDMA_LOW_WATER;
13058 tp->bufmgr_config.mbuf_mac_rx_low_water =
13059 DEFAULT_MB_MACRX_LOW_WATER;
13060 tp->bufmgr_config.mbuf_high_water =
13061 DEFAULT_MB_HIGH_WATER;
13062
13063 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13064 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13065 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13066 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13067 tp->bufmgr_config.mbuf_high_water_jumbo =
13068 DEFAULT_MB_HIGH_WATER_JUMBO;
13069 }
1da177e4
LT		 13070
13071 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13072 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13073}
13074
13075static char * __devinit tg3_phy_string(struct tg3 *tp)
13076{
13077 switch (tp->phy_id & PHY_ID_MASK) {
13078 case PHY_ID_BCM5400: return "5400";
13079 case PHY_ID_BCM5401: return "5401";
13080 case PHY_ID_BCM5411: return "5411";
13081 case PHY_ID_BCM5701: return "5701";
13082 case PHY_ID_BCM5703: return "5703";
13083 case PHY_ID_BCM5704: return "5704";
13084 case PHY_ID_BCM5705: return "5705";
13085 case PHY_ID_BCM5750: return "5750";
85e94ced 13086 case PHY_ID_BCM5752: return "5752";
a4e2b347 13087 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13088 case PHY_ID_BCM5780: return "5780";
af36e6b6 13089 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13090 case PHY_ID_BCM5787: return "5787";
d30cdd28 13091 case PHY_ID_BCM5784: return "5784";
126a3368 13092 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13093 case PHY_ID_BCM5906: return "5906";
9936bcf6 13094 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13095 case PHY_ID_BCM8002: return "8002/serdes";
13096 case 0: return "serdes";
13097 default: return "unknown";
855e1111 13098 }
1da177e4
LT		 13099}
13100
f9804ddb
MC		 13101static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13102{
13103 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13104 strcpy(str, "PCI Express");
13105 return str;
13106 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13107 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13108
13109 strcpy(str, "PCIX:");
13110
13111 if ((clock_ctrl == 7) ||
13112 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13113 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13114 strcat(str, "133MHz");
13115 else if (clock_ctrl == 0)
13116 strcat(str, "33MHz");
13117 else if (clock_ctrl == 2)
13118 strcat(str, "50MHz");
13119 else if (clock_ctrl == 4)
13120 strcat(str, "66MHz");
13121 else if (clock_ctrl == 6)
13122 strcat(str, "100MHz");
f9804ddb
MC		 13123 } else {
13124 strcpy(str, "PCI:");
13125 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13126 strcat(str, "66MHz");
13127 else
13128 strcat(str, "33MHz");
13129 }
13130 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13131 strcat(str, ":32-bit");
13132 else
13133 strcat(str, ":64-bit");
13134 return str;
13135}
13136
8c2dc7e1 13137static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13138{
13139 struct pci_dev *peer;
13140 unsigned int func, devnr = tp->pdev->devfn & ~7;
13141
13142 for (func = 0; func < 8; func++) {
13143 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13144 if (peer && peer != tp->pdev)
13145 break;
13146 pci_dev_put(peer);
13147 }
16fe9d74
MC		 13148 /* 5704 can be configured in single-port mode, set peer to
13149 * tp->pdev in that case.
13150 */
13151 if (!peer) {
13152 peer = tp->pdev;
13153 return peer;
13154 }
1da177e4
LT		 13155
13156 /*
13157 * We don't need to keep the refcount elevated; there's no way
13158 * to remove one half of this device without removing the other
13159 */
13160 pci_dev_put(peer);
13161
13162 return peer;
13163}
13164
15f9850d
DM		 13165static void __devinit tg3_init_coal(struct tg3 *tp)
13166{
13167 struct ethtool_coalesce *ec = &tp->coal;
13168
13169 memset(ec, 0, sizeof(*ec));
13170 ec->cmd = ETHTOOL_GCOALESCE;
13171 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13172 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13173 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13174 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13175 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13176 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13177 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13178 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13179 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13180
13181 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13182 HOSTCC_MODE_CLRTICK_TXBD)) {
13183 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13184 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13185 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13186 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13187 }
d244c892
MC		 13188
13189 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13190 ec->rx_coalesce_usecs_irq = 0;
13191 ec->tx_coalesce_usecs_irq = 0;
13192 ec->stats_block_coalesce_usecs = 0;
13193 }
15f9850d
DM		 13194}
13195
7c7d64b8
SH		 13196static const struct net_device_ops tg3_netdev_ops = {
13197 .ndo_open = tg3_open,
13198 .ndo_stop = tg3_close,
00829823
SH		 13199 .ndo_start_xmit = tg3_start_xmit,
13200 .ndo_get_stats = tg3_get_stats,
13201 .ndo_validate_addr = eth_validate_addr,
13202 .ndo_set_multicast_list = tg3_set_rx_mode,
13203 .ndo_set_mac_address = tg3_set_mac_addr,
13204 .ndo_do_ioctl = tg3_ioctl,
13205 .ndo_tx_timeout = tg3_tx_timeout,
13206 .ndo_change_mtu = tg3_change_mtu,
13207#if TG3_VLAN_TAG_USED
13208 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13209#endif
13210#ifdef CONFIG_NET_POLL_CONTROLLER
13211 .ndo_poll_controller = tg3_poll_controller,
13212#endif
13213};
13214
13215static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13216 .ndo_open = tg3_open,
13217 .ndo_stop = tg3_close,
13218 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13219 .ndo_get_stats = tg3_get_stats,
13220 .ndo_validate_addr = eth_validate_addr,
13221 .ndo_set_multicast_list = tg3_set_rx_mode,
13222 .ndo_set_mac_address = tg3_set_mac_addr,
13223 .ndo_do_ioctl = tg3_ioctl,
13224 .ndo_tx_timeout = tg3_tx_timeout,
13225 .ndo_change_mtu = tg3_change_mtu,
13226#if TG3_VLAN_TAG_USED
13227 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13228#endif
13229#ifdef CONFIG_NET_POLL_CONTROLLER
13230 .ndo_poll_controller = tg3_poll_controller,
13231#endif
13232};
13233
1da177e4
LT		 13234static int __devinit tg3_init_one(struct pci_dev *pdev,
13235 const struct pci_device_id *ent)
13236{
13237 static int tg3_version_printed = 0;
1da177e4
LT		 13238 struct net_device *dev;
13239 struct tg3 *tp;
d6645372 13240 int err, pm_cap;
f9804ddb 13241 char str[40];
72f2afb8 13242 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13243
13244 if (tg3_version_printed++ == 0)
13245 printk(KERN_INFO "%s", version);
13246
13247 err = pci_enable_device(pdev);
13248 if (err) {
13249 printk(KERN_ERR PFX "Cannot enable PCI device, "
13250 "aborting.\n");
13251 return err;
13252 }
13253
1da177e4
LT		 13254 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13255 if (err) {
13256 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13257 "aborting.\n");
13258 goto err_out_disable_pdev;
13259 }
13260
13261 pci_set_master(pdev);
13262
13263 /* Find power-management capability. */
13264 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13265 if (pm_cap == 0) {
13266 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13267 "aborting.\n");
13268 err = -EIO;
13269 goto err_out_free_res;
13270 }
13271
1da177e4
LT		 13272 dev = alloc_etherdev(sizeof(*tp));
13273 if (!dev) {
13274 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13275 err = -ENOMEM;
13276 goto err_out_free_res;
13277 }
13278
1da177e4
LT		 13279 SET_NETDEV_DEV(dev, &pdev->dev);
13280
1da177e4
LT		 13281#if TG3_VLAN_TAG_USED
13282 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13283#endif
13284
13285 tp = netdev_priv(dev);
13286 tp->pdev = pdev;
13287 tp->dev = dev;
13288 tp->pm_cap = pm_cap;
1da177e4
LT		 13289 tp->rx_mode = TG3_DEF_RX_MODE;
13290 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13291
1da177e4
LT		 13292 if (tg3_debug > 0)
13293 tp->msg_enable = tg3_debug;
13294 else
13295 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13296
13297 /* The word/byte swap controls here control register access byte
13298 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13299 * setting below.
13300 */
13301 tp->misc_host_ctrl =
13302 MISC_HOST_CTRL_MASK_PCI_INT |
13303 MISC_HOST_CTRL_WORD_SWAP |
13304 MISC_HOST_CTRL_INDIR_ACCESS |
13305 MISC_HOST_CTRL_PCISTATE_RW;
13306
13307 /* The NONFRM (non-frame) byte/word swap controls take effect
13308 * on descriptor entries, anything which isn't packet data.
13309 *
13310 * The StrongARM chips on the board (one for tx, one for rx)
13311 * are running in big-endian mode.
13312 */
13313 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13314 GRC_MODE_WSWAP_NONFRM_DATA);
13315#ifdef __BIG_ENDIAN
13316 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13317#endif
13318 spin_lock_init(&tp->lock);
1da177e4 13319 spin_lock_init(&tp->indirect_lock);
c4028958 13320 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13321
d5fe488a 13322 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13323 if (!tp->regs) {
1da177e4
LT		 13324 printk(KERN_ERR PFX "Cannot map device registers, "
13325 "aborting.\n");
13326 err = -ENOMEM;
13327 goto err_out_free_dev;
13328 }
13329
13330 tg3_init_link_config(tp);
13331
1da177e4
LT		 13332 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13333 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13334 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13335
bea3348e 13336 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
1da177e4 13337 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13338 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13339 dev->irq = pdev->irq;
1da177e4
LT		 13340
13341 err = tg3_get_invariants(tp);
13342 if (err) {
13343 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13344 "aborting.\n");
13345 goto err_out_iounmap;
13346 }
13347
321d32a0 13348 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13349 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13350 dev->netdev_ops = &tg3_netdev_ops;
13351 else
13352 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13353
13354
4a29cc2e
MC		 13355 /* The EPB bridge inside 5714, 5715, and 5780 and any
13356 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13357 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13358 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13359 * do DMA address check in tg3_start_xmit().
13360 */
4a29cc2e 13361 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13362 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13363 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13364 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13365#ifdef CONFIG_HIGHMEM
6a35528a 13366 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13367#endif
4a29cc2e 13368 } else
6a35528a 13369 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13370
13371 /* Configure DMA attributes. */
284901a9 13372 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13373 err = pci_set_dma_mask(pdev, dma_mask);
13374 if (!err) {
13375 dev->features |= NETIF_F_HIGHDMA;
13376 err = pci_set_consistent_dma_mask(pdev,
13377 persist_dma_mask);
13378 if (err < 0) {
13379 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13380 "DMA for consistent allocations\n");
13381 goto err_out_iounmap;
13382 }
13383 }
13384 }
284901a9
YH		 13385 if (err || dma_mask == DMA_BIT_MASK(32)) {
13386 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13387 if (err) {
13388 printk(KERN_ERR PFX "No usable DMA configuration, "
13389 "aborting.\n");
13390 goto err_out_iounmap;
13391 }
13392 }
13393
fdfec172 13394 tg3_init_bufmgr_config(tp);
1da177e4 13395
077f849d 13396 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13397 tp->fw_needed = FIRMWARE_TG3;
077f849d 13398
1da177e4
LT		 13399 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13400 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13401 }
13402 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13403 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13404 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13405 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13406 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13407 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13408 } else {
7f62ad5d 13409 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13410 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13411 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13412 else
9e9fd12d 13413 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13414 }
1da177e4 13415
4e3a7aaa
MC		 13416 /* TSO is on by default on chips that support hardware TSO.
13417 * Firmware TSO on older chips gives lower performance, so it
13418 * is off by default, but can be enabled using ethtool.
13419 */
b0026624 13420 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13421 if (dev->features & NETIF_F_IP_CSUM)
13422 dev->features |= NETIF_F_TSO;
13423 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13424 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13425 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13427 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13428 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13430 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13431 dev->features |= NETIF_F_TSO_ECN;
b0026624 13432 }
1da177e4 13433
1da177e4
LT		 13434
13435 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13436 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13437 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13438 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13439 tp->rx_pending = 63;
13440 }
13441
1da177e4
LT		 13442 err = tg3_get_device_address(tp);
13443 if (err) {
13444 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13445 "aborting.\n");
077f849d 13446 goto err_out_fw;
1da177e4
LT		 13447 }
13448
c88864df 13449 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13450 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13451 if (!tp->aperegs) {
c88864df
MC		 13452 printk(KERN_ERR PFX "Cannot map APE registers, "
13453 "aborting.\n");
13454 err = -ENOMEM;
077f849d 13455 goto err_out_fw;
c88864df
MC		 13456 }
13457
13458 tg3_ape_lock_init(tp);
7fd76445
MC		 13459
13460 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13461 tg3_read_dash_ver(tp);
c88864df
MC		 13462 }
13463
1da177e4
LT		 13464 /*
13465 * Reset chip in case UNDI or EFI driver did not shutdown
13466 * DMA self test will enable WDMAC and we'll see (spurious)
13467 * pending DMA on the PCI bus at that point.
13468 */
13469 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13470 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13471 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13472 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13473 }
13474
13475 err = tg3_test_dma(tp);
13476 if (err) {
13477 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13478 goto err_out_apeunmap;
1da177e4
LT		 13479 }
13480
1da177e4
LT		 13481 /* flow control autonegotiation is default behavior */
13482 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13483 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13484
15f9850d
DM		 13485 tg3_init_coal(tp);
13486
c49a1561
MC		 13487 pci_set_drvdata(pdev, dev);
13488
1da177e4
LT		 13489 err = register_netdev(dev);
13490 if (err) {
13491 printk(KERN_ERR PFX "Cannot register net device, "
13492 "aborting.\n");
0d3031d9 13493 goto err_out_apeunmap;
1da177e4
LT		 13494 }
13495
df59c940 13496 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13497 dev->name,
13498 tp->board_part_number,
13499 tp->pci_chip_rev_id,
f9804ddb 13500 tg3_bus_string(tp, str),
e174961c 13501 dev->dev_addr);
1da177e4 13502
df59c940
MC		 13503 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13504 printk(KERN_INFO
13505 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13506 tp->dev->name,
13507 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13508 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13509 else
13510 printk(KERN_INFO
13511 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13512 tp->dev->name, tg3_phy_string(tp),
13513 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13514 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13515 "10/100/1000Base-T")),
13516 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13517
13518 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13519 dev->name,
13520 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13521 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13522 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13523 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13524 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13525 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13526 dev->name, tp->dma_rwctrl,
284901a9 13527 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13528 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13529
13530 return 0;
13531
0d3031d9
MC		 13532err_out_apeunmap:
13533 if (tp->aperegs) {
13534 iounmap(tp->aperegs);
13535 tp->aperegs = NULL;
13536 }
13537
077f849d
JSR		 13538err_out_fw:
13539 if (tp->fw)
13540 release_firmware(tp->fw);
13541
1da177e4 13542err_out_iounmap:
6892914f
MC		 13543 if (tp->regs) {
13544 iounmap(tp->regs);
22abe310 13545 tp->regs = NULL;
6892914f 13546 }
1da177e4
LT		 13547
13548err_out_free_dev:
13549 free_netdev(dev);
13550
13551err_out_free_res:
13552 pci_release_regions(pdev);
13553
13554err_out_disable_pdev:
13555 pci_disable_device(pdev);
13556 pci_set_drvdata(pdev, NULL);
13557 return err;
13558}
13559
13560static void __devexit tg3_remove_one(struct pci_dev *pdev)
13561{
13562 struct net_device *dev = pci_get_drvdata(pdev);
13563
13564 if (dev) {
13565 struct tg3 *tp = netdev_priv(dev);
13566
077f849d
JSR		 13567 if (tp->fw)
13568 release_firmware(tp->fw);
13569
7faa006f 13570 flush_scheduled_work();
158d7abd 13571
b02fd9e3
MC		 13572 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13573 tg3_phy_fini(tp);
158d7abd 13574 tg3_mdio_fini(tp);
b02fd9e3 13575 }
158d7abd 13576
1da177e4 13577 unregister_netdev(dev);
0d3031d9
MC		 13578 if (tp->aperegs) {
13579 iounmap(tp->aperegs);
13580 tp->aperegs = NULL;
13581 }
6892914f
MC		 13582 if (tp->regs) {
13583 iounmap(tp->regs);
22abe310 13584 tp->regs = NULL;
6892914f 13585 }
1da177e4
LT		 13586 free_netdev(dev);
13587 pci_release_regions(pdev);
13588 pci_disable_device(pdev);
13589 pci_set_drvdata(pdev, NULL);
13590 }
13591}
13592
13593static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13594{
13595 struct net_device *dev = pci_get_drvdata(pdev);
13596 struct tg3 *tp = netdev_priv(dev);
12dac075 13597 pci_power_t target_state;
1da177e4
LT		 13598 int err;
13599
3e0c95fd
MC		 13600 /* PCI register 4 needs to be saved whether netif_running() or not.
13601 * MSI address and data need to be saved if using MSI and
13602 * netif_running().
13603 */
13604 pci_save_state(pdev);
13605
1da177e4
LT		 13606 if (!netif_running(dev))
13607 return 0;
13608
7faa006f 13609 flush_scheduled_work();
b02fd9e3 13610 tg3_phy_stop(tp);
1da177e4
LT		 13611 tg3_netif_stop(tp);
13612
13613 del_timer_sync(&tp->timer);
13614
f47c11ee 13615 tg3_full_lock(tp, 1);
1da177e4 13616 tg3_disable_ints(tp);
f47c11ee 13617 tg3_full_unlock(tp);
1da177e4
LT		 13618
13619 netif_device_detach(dev);
13620
f47c11ee 13621 tg3_full_lock(tp, 0);
944d980e 13622 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13623 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13624 tg3_full_unlock(tp);
1da177e4 13625
12dac075
RW		 13626 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13627
13628 err = tg3_set_power_state(tp, target_state);
1da177e4 13629 if (err) {
b02fd9e3
MC		 13630 int err2;
13631
f47c11ee 13632 tg3_full_lock(tp, 0);
1da177e4 13633
6a9eba15 13634 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13635 err2 = tg3_restart_hw(tp, 1);
13636 if (err2)
b9ec6c1b 13637 goto out;
1da177e4
LT		 13638
13639 tp->timer.expires = jiffies + tp->timer_offset;
13640 add_timer(&tp->timer);
13641
13642 netif_device_attach(dev);
13643 tg3_netif_start(tp);
13644
b9ec6c1b 13645out:
f47c11ee 13646 tg3_full_unlock(tp);
b02fd9e3
MC		 13647
13648 if (!err2)
13649 tg3_phy_start(tp);
1da177e4
LT		 13650 }
13651
13652 return err;
13653}
13654
13655static int tg3_resume(struct pci_dev *pdev)
13656{
13657 struct net_device *dev = pci_get_drvdata(pdev);
13658 struct tg3 *tp = netdev_priv(dev);
13659 int err;
13660
3e0c95fd
MC		 13661 pci_restore_state(tp->pdev);
13662
1da177e4
LT		 13663 if (!netif_running(dev))
13664 return 0;
13665
bc1c7567 13666 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13667 if (err)
13668 return err;
13669
13670 netif_device_attach(dev);
13671
f47c11ee 13672 tg3_full_lock(tp, 0);
1da177e4 13673
6a9eba15 13674 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13675 err = tg3_restart_hw(tp, 1);
13676 if (err)
13677 goto out;
1da177e4
LT		 13678
13679 tp->timer.expires = jiffies + tp->timer_offset;
13680 add_timer(&tp->timer);
13681
1da177e4
LT		 13682 tg3_netif_start(tp);
13683
b9ec6c1b 13684out:
f47c11ee 13685 tg3_full_unlock(tp);
1da177e4 13686
b02fd9e3
MC		 13687 if (!err)
13688 tg3_phy_start(tp);
13689
b9ec6c1b 13690 return err;
1da177e4
LT		 13691}
13692
13693static struct pci_driver tg3_driver = {
13694 .name = DRV_MODULE_NAME,
13695 .id_table = tg3_pci_tbl,
13696 .probe = tg3_init_one,
13697 .remove = __devexit_p(tg3_remove_one),
13698 .suspend = tg3_suspend,
13699 .resume = tg3_resume
13700};
13701
13702static int __init tg3_init(void)
13703{
29917620 13704 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13705}
13706
13707static void __exit tg3_cleanup(void)
13708{
13709 pci_unregister_driver(&tg3_driver);
13710}
13711
13712module_init(tg3_init);
13713module_exit(tg3_cleanup);
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