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tg3: Create tg3_rings_reset()
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
fc57e515
MC		 71#define DRV_MODULE_VERSION "3.101"
72#define DRV_MODULE_RELDATE "August 28, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
79ed5ac7
MC		 120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
1da177e4 122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 123 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
287be12e
MC		 128#define TG3_DMA_BYTE_ENAB 64
129
130#define TG3_RX_STD_DMA_SZ 1536
131#define TG3_RX_JMB_DMA_SZ 9046
132
133#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
134
135#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 137
138/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 139#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 140
ad829268
MC		 141#define TG3_RAW_IP_ALIGN 2
142
1da177e4
LT		 143/* number of ETHTOOL_GSTATS u64's */
144#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
145
4cafd3f5
MC		 146#define TG3_NUM_TEST 6
147
077f849d
JSR		 148#define FIRMWARE_TG3 "tigon/tg3.bin"
149#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
151
1da177e4
LT		 152static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
154
155MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157MODULE_LICENSE("GPL");
158MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 159MODULE_FIRMWARE(FIRMWARE_TG3);
160MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
162
1da177e4
LT		 163
164static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165module_param(tg3_debug, int, 0);
166MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
167
168static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
242 {}
1da177e4
LT		 243};
244
245MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
50da859d 247static const struct {
1da177e4
LT		 248 const char string[ETH_GSTRING_LEN];
249} ethtool_stats_keys[TG3_NUM_STATS] = {
250 { "rx_octets" },
251 { "rx_fragments" },
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
255 { "rx_fcs_errors" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
262 { "rx_jabbers" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
276
277 { "tx_octets" },
278 { "tx_collisions" },
279
280 { "tx_xon_sent" },
281 { "tx_xoff_sent" },
282 { "tx_flow_control" },
283 { "tx_mac_errors" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
286 { "tx_deferred" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
307 { "tx_discards" },
308 { "tx_errors" },
309
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
312 { "rxbds_empty" },
313 { "rx_discards" },
314 { "rx_errors" },
315 { "rx_threshold_hit" },
316
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
320
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
323 { "nic_irqs" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
326};
327
50da859d 328static const struct {
4cafd3f5
MC		 329 const char string[ETH_GSTRING_LEN];
330} ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
337};
338
b401e9e2
MC		 339static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
340{
341 writel(val, tp->regs + off);
342}
343
344static u32 tg3_read32(struct tg3 *tp, u32 off)
345{
6aa20a22 346 return (readl(tp->regs + off));
b401e9e2
MC		 347}
348
0d3031d9
MC		 349static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
350{
351 writel(val, tp->aperegs + off);
352}
353
354static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
355{
356 return (readl(tp->aperegs + off));
357}
358
1da177e4
LT		 359static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
360{
6892914f
MC		 361 unsigned long flags;
362
363 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 364 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
365 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 366 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 367}
368
369static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
370{
371 writel(val, tp->regs + off);
372 readl(tp->regs + off);
1da177e4
LT		 373}
374
6892914f 375static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 376{
6892914f
MC		 377 unsigned long flags;
378 u32 val;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
384 return val;
385}
386
387static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
388{
389 unsigned long flags;
390
391 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
393 TG3_64BIT_REG_LOW, val);
394 return;
395 }
396 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
398 TG3_64BIT_REG_LOW, val);
399 return;
1da177e4 400 }
6892914f
MC		 401
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
409 */
410 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
411 (val == 0x1)) {
412 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
413 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
414 }
415}
416
417static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
418{
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427}
428
b401e9e2
MC		 429/* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
433 */
434static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 435{
b401e9e2
MC		 436 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
437 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
438 /* Non-posted methods */
439 tp->write32(tp, off, val);
440 else {
441 /* Posted method */
442 tg3_write32(tp, off, val);
443 if (usec_wait)
444 udelay(usec_wait);
445 tp->read32(tp, off);
446 }
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
449 */
450 if (usec_wait)
451 udelay(usec_wait);
1da177e4
LT		 452}
453
09ee929c
MC		 454static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
455{
456 tp->write32_mbox(tp, off, val);
6892914f
MC		 457 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
458 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
459 tp->read32_mbox(tp, off);
09ee929c
MC		 460}
461
20094930 462static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 463{
464 void __iomem *mbox = tp->regs + off;
465 writel(val, mbox);
466 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
467 writel(val, mbox);
468 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
469 readl(mbox);
470}
471
b5d3772c
MC		 472static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
473{
474 return (readl(tp->regs + off + GRCMBOX_BASE));
475}
476
477static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
478{
479 writel(val, tp->regs + off + GRCMBOX_BASE);
480}
481
20094930 482#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 483#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 484#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 486#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 487
488#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 489#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 491#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 492
493static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
494{
6892914f
MC		 495 unsigned long flags;
496
b5d3772c
MC		 497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
498 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
499 return;
500
6892914f 501 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 505
bbadf503
MC		 506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508 } else {
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 511
bbadf503
MC		 512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514 }
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 516}
517
1da177e4
LT		 518static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
519{
6892914f
MC		 520 unsigned long flags;
521
b5d3772c
MC		 522 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
523 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
524 *val = 0;
525 return;
526 }
527
6892914f 528 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 529 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
530 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
531 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 532
bbadf503
MC		 533 /* Always leave this as zero. */
534 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
535 } else {
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
537 *val = tr32(TG3PCI_MEM_WIN_DATA);
538
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
541 }
6892914f 542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 543}
544
0d3031d9
MC		 545static void tg3_ape_lock_init(struct tg3 *tp)
546{
547 int i;
548
549 /* Make sure the driver hasn't any stale locks. */
550 for (i = 0; i < 8; i++)
551 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
552 APE_LOCK_GRANT_DRIVER);
553}
554
555static int tg3_ape_lock(struct tg3 *tp, int locknum)
556{
557 int i, off;
558 int ret = 0;
559 u32 status;
560
561 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
562 return 0;
563
564 switch (locknum) {
77b483f1 565 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 566 case TG3_APE_LOCK_MEM:
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 off = 4 * locknum;
573
574 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
575
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i = 0; i < 100; i++) {
578 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
579 if (status == APE_LOCK_GRANT_DRIVER)
580 break;
581 udelay(10);
582 }
583
584 if (status != APE_LOCK_GRANT_DRIVER) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
587 APE_LOCK_GRANT_DRIVER);
588
589 ret = -EBUSY;
590 }
591
592 return ret;
593}
594
595static void tg3_ape_unlock(struct tg3 *tp, int locknum)
596{
597 int off;
598
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
600 return;
601
602 switch (locknum) {
77b483f1 603 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 604 case TG3_APE_LOCK_MEM:
605 break;
606 default:
607 return;
608 }
609
610 off = 4 * locknum;
611 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
612}
613
1da177e4
LT		 614static void tg3_disable_ints(struct tg3 *tp)
615{
616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
898a56f8 618 tw32_mailbox_f(tp->napi[0].int_mbox, 0x00000001);
1da177e4
LT		 619}
620
1da177e4
LT		 621static void tg3_enable_ints(struct tg3 *tp)
622{
f19af9c2 623 u32 coal_now;
898a56f8 624 struct tg3_napi *tnapi = &tp->napi[0];
bbe832c0
MC		 625 tp->irq_sync = 0;
626 wmb();
627
1da177e4
LT		 628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
898a56f8 630 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
fcfa0a32 631 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
898a56f8 632 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 633
fd2ce37f 634 coal_now = tnapi->coal_now;
f19af9c2
MC		 635
636 /* Force an initial interrupt */
637 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
638 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
639 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
640 else
641 tw32(HOSTCC_MODE, tp->coalesce_mode |
642 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 643}
644
17375d25 645static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 646{
17375d25 647 struct tg3 *tp = tnapi->tp;
898a56f8 648 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 649 unsigned int work_exists = 0;
650
651 /* check for phy events */
652 if (!(tp->tg3_flags &
653 (TG3_FLAG_USE_LINKCHG_REG |
654 TG3_FLAG_POLL_SERDES))) {
655 if (sblk->status & SD_STATUS_LINK_CHG)
656 work_exists = 1;
657 }
658 /* check for RX/TX work to do */
f3f3f27e 659 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
72334482 660 sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
04237ddd
MC		 661 work_exists = 1;
662
663 return work_exists;
664}
665
17375d25 666/* tg3_int_reenable
04237ddd
MC		 667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
6aa20a22 669 * which reenables interrupts
1da177e4 670 */
17375d25 671static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 672{
17375d25
MC		 673 struct tg3 *tp = tnapi->tp;
674
898a56f8 675 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 676 mmiowb();
677
fac9b83e
DM		 678 /* When doing tagged status, this work check is unnecessary.
679 * The last_tag we write above tells the chip which piece of
680 * work we've completed.
681 */
682 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 683 tg3_has_work(tnapi))
04237ddd 684 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 685 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 686}
687
688static inline void tg3_netif_stop(struct tg3 *tp)
689{
bbe832c0 690 tp->dev->trans_start = jiffies; /* prevent tx timeout */
8ef0442f 691 napi_disable(&tp->napi[0].napi);
1da177e4
LT		 692 netif_tx_disable(tp->dev);
693}
694
695static inline void tg3_netif_start(struct tg3 *tp)
696{
898a56f8 697 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 698 netif_wake_queue(tp->dev);
699 /* NOTE: unconditional netif_wake_queue is only appropriate
700 * so long as all callers are assured to have free tx slots
701 * (such as after tg3_init_hw)
702 */
898a56f8
MC		 703 napi_enable(&tnapi->napi);
704 tnapi->hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 705 tg3_enable_ints(tp);
1da177e4
LT		 706}
707
708static void tg3_switch_clocks(struct tg3 *tp)
709{
710 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
711 u32 orig_clock_ctrl;
712
795d01c5
MC		 713 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
714 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 715 return;
716
1da177e4
LT		 717 orig_clock_ctrl = clock_ctrl;
718 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
719 CLOCK_CTRL_CLKRUN_OENABLE |
720 0x1f);
721 tp->pci_clock_ctrl = clock_ctrl;
722
723 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
724 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 725 tw32_wait_f(TG3PCI_CLOCK_CTRL,
726 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 727 }
728 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 729 tw32_wait_f(TG3PCI_CLOCK_CTRL,
730 clock_ctrl |
731 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
732 40);
733 tw32_wait_f(TG3PCI_CLOCK_CTRL,
734 clock_ctrl | (CLOCK_CTRL_ALTCLK),
735 40);
1da177e4 736 }
b401e9e2 737 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 738}
739
740#define PHY_BUSY_LOOPS 5000
741
742static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
743{
744 u32 frame_val;
745 unsigned int loops;
746 int ret;
747
748 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
749 tw32_f(MAC_MI_MODE,
750 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
751 udelay(80);
752 }
753
754 *val = 0x0;
755
756 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
757 MI_COM_PHY_ADDR_MASK);
758 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
759 MI_COM_REG_ADDR_MASK);
760 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 761
1da177e4
LT		 762 tw32_f(MAC_MI_COM, frame_val);
763
764 loops = PHY_BUSY_LOOPS;
765 while (loops != 0) {
766 udelay(10);
767 frame_val = tr32(MAC_MI_COM);
768
769 if ((frame_val & MI_COM_BUSY) == 0) {
770 udelay(5);
771 frame_val = tr32(MAC_MI_COM);
772 break;
773 }
774 loops -= 1;
775 }
776
777 ret = -EBUSY;
778 if (loops != 0) {
779 *val = frame_val & MI_COM_DATA_MASK;
780 ret = 0;
781 }
782
783 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
784 tw32_f(MAC_MI_MODE, tp->mi_mode);
785 udelay(80);
786 }
787
788 return ret;
789}
790
791static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
792{
793 u32 frame_val;
794 unsigned int loops;
795 int ret;
796
7f97a4bd 797 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 798 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
799 return 0;
800
1da177e4
LT		 801 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
802 tw32_f(MAC_MI_MODE,
803 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
804 udelay(80);
805 }
806
807 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
808 MI_COM_PHY_ADDR_MASK);
809 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810 MI_COM_REG_ADDR_MASK);
811 frame_val |= (val & MI_COM_DATA_MASK);
812 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 813
1da177e4
LT		 814 tw32_f(MAC_MI_COM, frame_val);
815
816 loops = PHY_BUSY_LOOPS;
817 while (loops != 0) {
818 udelay(10);
819 frame_val = tr32(MAC_MI_COM);
820 if ((frame_val & MI_COM_BUSY) == 0) {
821 udelay(5);
822 frame_val = tr32(MAC_MI_COM);
823 break;
824 }
825 loops -= 1;
826 }
827
828 ret = -EBUSY;
829 if (loops != 0)
830 ret = 0;
831
832 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
833 tw32_f(MAC_MI_MODE, tp->mi_mode);
834 udelay(80);
835 }
836
837 return ret;
838}
839
95e2869a
MC		 840static int tg3_bmcr_reset(struct tg3 *tp)
841{
842 u32 phy_control;
843 int limit, err;
844
845 /* OK, reset it, and poll the BMCR_RESET bit until it
846 * clears or we time out.
847 */
848 phy_control = BMCR_RESET;
849 err = tg3_writephy(tp, MII_BMCR, phy_control);
850 if (err != 0)
851 return -EBUSY;
852
853 limit = 5000;
854 while (limit--) {
855 err = tg3_readphy(tp, MII_BMCR, &phy_control);
856 if (err != 0)
857 return -EBUSY;
858
859 if ((phy_control & BMCR_RESET) == 0) {
860 udelay(40);
861 break;
862 }
863 udelay(10);
864 }
d4675b52 865 if (limit < 0)
95e2869a
MC		 866 return -EBUSY;
867
868 return 0;
869}
870
158d7abd
MC		 871static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
872{
3d16543d 873 struct tg3 *tp = bp->priv;
158d7abd
MC		 874 u32 val;
875
876 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
877 return -EAGAIN;
878
879 if (tg3_readphy(tp, reg, &val))
880 return -EIO;
881
882 return val;
883}
884
885static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
886{
3d16543d 887 struct tg3 *tp = bp->priv;
158d7abd
MC		 888
889 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
890 return -EAGAIN;
891
892 if (tg3_writephy(tp, reg, val))
893 return -EIO;
894
895 return 0;
896}
897
898static int tg3_mdio_reset(struct mii_bus *bp)
899{
900 return 0;
901}
902
9c61d6bc 903static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 904{
905 u32 val;
fcb389df 906 struct phy_device *phydev;
a9daf367 907
fcb389df
MC		 908 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
909 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
910 case TG3_PHY_ID_BCM50610:
911 val = MAC_PHYCFG2_50610_LED_MODES;
912 break;
913 case TG3_PHY_ID_BCMAC131:
914 val = MAC_PHYCFG2_AC131_LED_MODES;
915 break;
916 case TG3_PHY_ID_RTL8211C:
917 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
918 break;
919 case TG3_PHY_ID_RTL8201E:
920 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
921 break;
922 default:
a9daf367 923 return;
fcb389df
MC		 924 }
925
926 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
927 tw32(MAC_PHYCFG2, val);
928
929 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 930 val &= ~(MAC_PHYCFG1_RGMII_INT |
931 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
932 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 933 tw32(MAC_PHYCFG1, val);
934
935 return;
936 }
937
938 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
939 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
940 MAC_PHYCFG2_FMODE_MASK_MASK |
941 MAC_PHYCFG2_GMODE_MASK_MASK |
942 MAC_PHYCFG2_ACT_MASK_MASK |
943 MAC_PHYCFG2_QUAL_MASK_MASK |
944 MAC_PHYCFG2_INBAND_ENABLE;
945
946 tw32(MAC_PHYCFG2, val);
a9daf367 947
bb85fbb6
MC		 948 val = tr32(MAC_PHYCFG1);
949 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
950 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
951 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 952 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
953 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
954 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
955 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
956 }
bb85fbb6
MC		 957 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
958 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
959 tw32(MAC_PHYCFG1, val);
a9daf367 960
a9daf367
MC		 961 val = tr32(MAC_EXT_RGMII_MODE);
962 val &= ~(MAC_RGMII_MODE_RX_INT_B |
963 MAC_RGMII_MODE_RX_QUALITY |
964 MAC_RGMII_MODE_RX_ACTIVITY |
965 MAC_RGMII_MODE_RX_ENG_DET |
966 MAC_RGMII_MODE_TX_ENABLE |
967 MAC_RGMII_MODE_TX_LOWPWR |
968 MAC_RGMII_MODE_TX_RESET);
fcb389df 969 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 970 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
971 val |= MAC_RGMII_MODE_RX_INT_B |
972 MAC_RGMII_MODE_RX_QUALITY |
973 MAC_RGMII_MODE_RX_ACTIVITY |
974 MAC_RGMII_MODE_RX_ENG_DET;
975 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
976 val |= MAC_RGMII_MODE_TX_ENABLE |
977 MAC_RGMII_MODE_TX_LOWPWR |
978 MAC_RGMII_MODE_TX_RESET;
979 }
980 tw32(MAC_EXT_RGMII_MODE, val);
981}
982
158d7abd
MC		 983static void tg3_mdio_start(struct tg3 *tp)
984{
985 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 986 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 987 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 988 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 989 }
990
991 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
992 tw32_f(MAC_MI_MODE, tp->mi_mode);
993 udelay(80);
a9daf367 994
9c61d6bc
MC		 995 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
997 tg3_mdio_config_5785(tp);
158d7abd
MC		 998}
999
1000static void tg3_mdio_stop(struct tg3 *tp)
1001{
1002 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 1003 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 1004 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 1005 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 1006 }
1007}
1008
1009static int tg3_mdio_init(struct tg3 *tp)
1010{
1011 int i;
1012 u32 reg;
a9daf367 1013 struct phy_device *phydev;
158d7abd
MC		 1014
1015 tg3_mdio_start(tp);
1016
1017 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1018 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1019 return 0;
1020
298cf9be
LB		 1021 tp->mdio_bus = mdiobus_alloc();
1022 if (tp->mdio_bus == NULL)
1023 return -ENOMEM;
158d7abd 1024
298cf9be
LB		 1025 tp->mdio_bus->name = "tg3 mdio bus";
1026 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1027 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1028 tp->mdio_bus->priv = tp;
1029 tp->mdio_bus->parent = &tp->pdev->dev;
1030 tp->mdio_bus->read = &tg3_mdio_read;
1031 tp->mdio_bus->write = &tg3_mdio_write;
1032 tp->mdio_bus->reset = &tg3_mdio_reset;
1033 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1034 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1035
1036 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1037 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1038
1039 /* The bus registration will look for all the PHYs on the mdio bus.
1040 * Unfortunately, it does not ensure the PHY is powered up before
1041 * accessing the PHY ID registers. A chip reset is the
1042 * quickest way to bring the device back to an operational state..
1043 */
1044 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1045 tg3_bmcr_reset(tp);
1046
298cf9be 1047 i = mdiobus_register(tp->mdio_bus);
a9daf367 1048 if (i) {
158d7abd
MC		 1049 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1050 tp->dev->name, i);
9c61d6bc 1051 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1052 return i;
1053 }
158d7abd 1054
298cf9be 1055 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1056
9c61d6bc
MC		 1057 if (!phydev || !phydev->drv) {
1058 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1059 mdiobus_unregister(tp->mdio_bus);
1060 mdiobus_free(tp->mdio_bus);
1061 return -ENODEV;
1062 }
1063
1064 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1065 case TG3_PHY_ID_BCM57780:
1066 phydev->interface = PHY_INTERFACE_MODE_GMII;
1067 break;
a9daf367 1068 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1069 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1070 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1071 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1072 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1073 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1074 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1075 /* fallthru */
1076 case TG3_PHY_ID_RTL8211C:
1077 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1078 break;
fcb389df 1079 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1080 case TG3_PHY_ID_BCMAC131:
1081 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1082 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1083 break;
1084 }
1085
9c61d6bc
MC		 1086 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1087
1088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1089 tg3_mdio_config_5785(tp);
a9daf367
MC		 1090
1091 return 0;
158d7abd
MC		 1092}
1093
1094static void tg3_mdio_fini(struct tg3 *tp)
1095{
1096 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1097 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1098 mdiobus_unregister(tp->mdio_bus);
1099 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1100 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1101 }
1102}
1103
4ba526ce
MC		 1104/* tp->lock is held. */
1105static inline void tg3_generate_fw_event(struct tg3 *tp)
1106{
1107 u32 val;
1108
1109 val = tr32(GRC_RX_CPU_EVENT);
1110 val |= GRC_RX_CPU_DRIVER_EVENT;
1111 tw32_f(GRC_RX_CPU_EVENT, val);
1112
1113 tp->last_event_jiffies = jiffies;
1114}
1115
1116#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1117
95e2869a
MC		 1118/* tp->lock is held. */
1119static void tg3_wait_for_event_ack(struct tg3 *tp)
1120{
1121 int i;
4ba526ce
MC		 1122 unsigned int delay_cnt;
1123 long time_remain;
1124
1125 /* If enough time has passed, no wait is necessary. */
1126 time_remain = (long)(tp->last_event_jiffies + 1 +
1127 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1128 (long)jiffies;
1129 if (time_remain < 0)
1130 return;
1131
1132 /* Check if we can shorten the wait time. */
1133 delay_cnt = jiffies_to_usecs(time_remain);
1134 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1135 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1136 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1137
4ba526ce 1138 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1139 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1140 break;
4ba526ce 1141 udelay(8);
95e2869a
MC		 1142 }
1143}
1144
1145/* tp->lock is held. */
1146static void tg3_ump_link_report(struct tg3 *tp)
1147{
1148 u32 reg;
1149 u32 val;
1150
1151 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1152 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1153 return;
1154
1155 tg3_wait_for_event_ack(tp);
1156
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1158
1159 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1160
1161 val = 0;
1162 if (!tg3_readphy(tp, MII_BMCR, &reg))
1163 val = reg << 16;
1164 if (!tg3_readphy(tp, MII_BMSR, &reg))
1165 val |= (reg & 0xffff);
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1167
1168 val = 0;
1169 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1170 val = reg << 16;
1171 if (!tg3_readphy(tp, MII_LPA, &reg))
1172 val |= (reg & 0xffff);
1173 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1174
1175 val = 0;
1176 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1177 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1178 val = reg << 16;
1179 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1180 val |= (reg & 0xffff);
1181 }
1182 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1183
1184 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1185 val = reg << 16;
1186 else
1187 val = 0;
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1189
4ba526ce 1190 tg3_generate_fw_event(tp);
95e2869a
MC		 1191}
1192
1193static void tg3_link_report(struct tg3 *tp)
1194{
1195 if (!netif_carrier_ok(tp->dev)) {
1196 if (netif_msg_link(tp))
1197 printk(KERN_INFO PFX "%s: Link is down.\n",
1198 tp->dev->name);
1199 tg3_ump_link_report(tp);
1200 } else if (netif_msg_link(tp)) {
1201 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1202 tp->dev->name,
1203 (tp->link_config.active_speed == SPEED_1000 ?
1204 1000 :
1205 (tp->link_config.active_speed == SPEED_100 ?
1206 100 : 10)),
1207 (tp->link_config.active_duplex == DUPLEX_FULL ?
1208 "full" : "half"));
1209
1210 printk(KERN_INFO PFX
1211 "%s: Flow control is %s for TX and %s for RX.\n",
1212 tp->dev->name,
e18ce346 1213 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1214 "on" : "off",
e18ce346 1215 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1216 "on" : "off");
1217 tg3_ump_link_report(tp);
1218 }
1219}
1220
1221static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1230 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
1237static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1238{
1239 u16 miireg;
1240
e18ce346 1241 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1242 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1243 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1244 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1245 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1246 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1247 else
1248 miireg = 0;
1249
1250 return miireg;
1251}
1252
95e2869a
MC		 1253static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1254{
1255 u8 cap = 0;
1256
1257 if (lcladv & ADVERTISE_1000XPAUSE) {
1258 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1259 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1260 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1261 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1262 cap = FLOW_CTRL_RX;
95e2869a
MC		 1263 } else {
1264 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1265 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1266 }
1267 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1268 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1269 cap = FLOW_CTRL_TX;
95e2869a
MC		 1270 }
1271
1272 return cap;
1273}
1274
f51f3562 1275static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1276{
b02fd9e3 1277 u8 autoneg;
f51f3562 1278 u8 flowctrl = 0;
95e2869a
MC		 1279 u32 old_rx_mode = tp->rx_mode;
1280 u32 old_tx_mode = tp->tx_mode;
1281
b02fd9e3 1282 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1283 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1284 else
1285 autoneg = tp->link_config.autoneg;
1286
1287 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1288 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1289 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1290 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1291 else
bc02ff95 1292 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1293 } else
1294 flowctrl = tp->link_config.flowctrl;
95e2869a 1295
f51f3562 1296 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1297
e18ce346 1298 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1299 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1300 else
1301 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1302
f51f3562 1303 if (old_rx_mode != tp->rx_mode)
95e2869a 1304 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1305
e18ce346 1306 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1307 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1308 else
1309 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1310
f51f3562 1311 if (old_tx_mode != tp->tx_mode)
95e2869a 1312 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1313}
1314
b02fd9e3
MC		 1315static void tg3_adjust_link(struct net_device *dev)
1316{
1317 u8 oldflowctrl, linkmesg = 0;
1318 u32 mac_mode, lcl_adv, rmt_adv;
1319 struct tg3 *tp = netdev_priv(dev);
298cf9be 1320 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1321
1322 spin_lock(&tp->lock);
1323
1324 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1325 MAC_MODE_HALF_DUPLEX);
1326
1327 oldflowctrl = tp->link_config.active_flowctrl;
1328
1329 if (phydev->link) {
1330 lcl_adv = 0;
1331 rmt_adv = 0;
1332
1333 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1334 mac_mode |= MAC_MODE_PORT_MODE_MII;
1335 else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (phydev->duplex == DUPLEX_HALF)
1339 mac_mode |= MAC_MODE_HALF_DUPLEX;
1340 else {
1341 lcl_adv = tg3_advert_flowctrl_1000T(
1342 tp->link_config.flowctrl);
1343
1344 if (phydev->pause)
1345 rmt_adv = LPA_PAUSE_CAP;
1346 if (phydev->asym_pause)
1347 rmt_adv |= LPA_PAUSE_ASYM;
1348 }
1349
1350 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1351 } else
1352 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1353
1354 if (mac_mode != tp->mac_mode) {
1355 tp->mac_mode = mac_mode;
1356 tw32_f(MAC_MODE, tp->mac_mode);
1357 udelay(40);
1358 }
1359
fcb389df
MC		 1360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1361 if (phydev->speed == SPEED_10)
1362 tw32(MAC_MI_STAT,
1363 MAC_MI_STAT_10MBPS_MODE |
1364 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1365 else
1366 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1367 }
1368
b02fd9e3
MC		 1369 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1370 tw32(MAC_TX_LENGTHS,
1371 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1372 (6 << TX_LENGTHS_IPG_SHIFT) |
1373 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1374 else
1375 tw32(MAC_TX_LENGTHS,
1376 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1377 (6 << TX_LENGTHS_IPG_SHIFT) |
1378 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1379
1380 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1381 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1382 phydev->speed != tp->link_config.active_speed ||
1383 phydev->duplex != tp->link_config.active_duplex ||
1384 oldflowctrl != tp->link_config.active_flowctrl)
1385 linkmesg = 1;
1386
1387 tp->link_config.active_speed = phydev->speed;
1388 tp->link_config.active_duplex = phydev->duplex;
1389
1390 spin_unlock(&tp->lock);
1391
1392 if (linkmesg)
1393 tg3_link_report(tp);
1394}
1395
1396static int tg3_phy_init(struct tg3 *tp)
1397{
1398 struct phy_device *phydev;
1399
1400 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1401 return 0;
1402
1403 /* Bring the PHY back to a known state. */
1404 tg3_bmcr_reset(tp);
1405
298cf9be 1406 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1407
1408 /* Attach the MAC to the PHY. */
fb28ad35 1409 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1410 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1411 if (IS_ERR(phydev)) {
1412 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1413 return PTR_ERR(phydev);
1414 }
1415
b02fd9e3 1416 /* Mask with MAC supported features. */
9c61d6bc
MC		 1417 switch (phydev->interface) {
1418 case PHY_INTERFACE_MODE_GMII:
1419 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1420 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1421 phydev->supported &= (PHY_GBIT_FEATURES |
1422 SUPPORTED_Pause |
1423 SUPPORTED_Asym_Pause);
1424 break;
1425 }
1426 /* fallthru */
9c61d6bc
MC		 1427 case PHY_INTERFACE_MODE_MII:
1428 phydev->supported &= (PHY_BASIC_FEATURES |
1429 SUPPORTED_Pause |
1430 SUPPORTED_Asym_Pause);
1431 break;
1432 default:
1433 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1434 return -EINVAL;
1435 }
1436
1437 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1438
1439 phydev->advertising = phydev->supported;
1440
b02fd9e3
MC		 1441 return 0;
1442}
1443
1444static void tg3_phy_start(struct tg3 *tp)
1445{
1446 struct phy_device *phydev;
1447
1448 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1449 return;
1450
298cf9be 1451 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1452
1453 if (tp->link_config.phy_is_low_power) {
1454 tp->link_config.phy_is_low_power = 0;
1455 phydev->speed = tp->link_config.orig_speed;
1456 phydev->duplex = tp->link_config.orig_duplex;
1457 phydev->autoneg = tp->link_config.orig_autoneg;
1458 phydev->advertising = tp->link_config.orig_advertising;
1459 }
1460
1461 phy_start(phydev);
1462
1463 phy_start_aneg(phydev);
1464}
1465
1466static void tg3_phy_stop(struct tg3 *tp)
1467{
1468 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1469 return;
1470
298cf9be 1471 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1472}
1473
1474static void tg3_phy_fini(struct tg3 *tp)
1475{
1476 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1477 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1478 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1479 }
1480}
1481
b2a5c19c
MC		 1482static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1483{
1484 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1485 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1486}
1487
7f97a4bd
MC		 1488static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1489{
1490 u32 phytest;
1491
1492 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1493 u32 phy;
1494
1495 tg3_writephy(tp, MII_TG3_FET_TEST,
1496 phytest | MII_TG3_FET_SHADOW_EN);
1497 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1498 if (enable)
1499 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1500 else
1501 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1502 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1503 }
1504 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1505 }
1506}
1507
6833c043
MC		 1508static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1509{
1510 u32 reg;
1511
7f97a4bd 1512 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1513 return;
1514
7f97a4bd
MC		 1515 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1516 tg3_phy_fet_toggle_apd(tp, enable);
1517 return;
1518 }
1519
6833c043
MC		 1520 reg = MII_TG3_MISC_SHDW_WREN |
1521 MII_TG3_MISC_SHDW_SCR5_SEL |
1522 MII_TG3_MISC_SHDW_SCR5_LPED |
1523 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1524 MII_TG3_MISC_SHDW_SCR5_SDTL |
1525 MII_TG3_MISC_SHDW_SCR5_C125OE;
1526 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1527 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1528
1529 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1530
1531
1532 reg = MII_TG3_MISC_SHDW_WREN |
1533 MII_TG3_MISC_SHDW_APD_SEL |
1534 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1535 if (enable)
1536 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1537
1538 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1539}
1540
9ef8ca99
MC		 1541static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1542{
1543 u32 phy;
1544
1545 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1546 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1547 return;
1548
7f97a4bd 1549 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1550 u32 ephy;
1551
535ef6e1
MC		 1552 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1553 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1554
1555 tg3_writephy(tp, MII_TG3_FET_TEST,
1556 ephy | MII_TG3_FET_SHADOW_EN);
1557 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1558 if (enable)
535ef6e1 1559 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1560 else
535ef6e1
MC		 1561 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1562 tg3_writephy(tp, reg, phy);
9ef8ca99 1563 }
535ef6e1 1564 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1565 }
1566 } else {
1567 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1568 MII_TG3_AUXCTL_SHDWSEL_MISC;
1569 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1570 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1571 if (enable)
1572 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1573 else
1574 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1575 phy |= MII_TG3_AUXCTL_MISC_WREN;
1576 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1577 }
1578 }
1579}
1580
1da177e4
LT		 1581static void tg3_phy_set_wirespeed(struct tg3 *tp)
1582{
1583 u32 val;
1584
1585 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1586 return;
1587
1588 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1589 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1590 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1591 (val | (1 << 15) | (1 << 4)));
1592}
1593
b2a5c19c
MC		 1594static void tg3_phy_apply_otp(struct tg3 *tp)
1595{
1596 u32 otp, phy;
1597
1598 if (!tp->phy_otp)
1599 return;
1600
1601 otp = tp->phy_otp;
1602
1603 /* Enable SM_DSP clock and tx 6dB coding. */
1604 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1605 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1606 MII_TG3_AUXCTL_ACTL_TX_6DB;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608
1609 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1610 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1611 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1612
1613 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1614 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1615 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1616
1617 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1618 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1619 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1620
1621 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1622 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1623
1624 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1625 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1626
1627 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1628 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1629 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1630
1631 /* Turn off SM_DSP clock. */
1632 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1633 MII_TG3_AUXCTL_ACTL_TX_6DB;
1634 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1635}
1636
1da177e4
LT		 1637static int tg3_wait_macro_done(struct tg3 *tp)
1638{
1639 int limit = 100;
1640
1641 while (limit--) {
1642 u32 tmp32;
1643
1644 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1645 if ((tmp32 & 0x1000) == 0)
1646 break;
1647 }
1648 }
d4675b52 1649 if (limit < 0)
1da177e4
LT		 1650 return -EBUSY;
1651
1652 return 0;
1653}
1654
1655static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1656{
1657 static const u32 test_pat[4][6] = {
1658 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1659 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1660 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1661 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1662 };
1663 int chan;
1664
1665 for (chan = 0; chan < 4; chan++) {
1666 int i;
1667
1668 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1669 (chan * 0x2000) | 0x0200);
1670 tg3_writephy(tp, 0x16, 0x0002);
1671
1672 for (i = 0; i < 6; i++)
1673 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1674 test_pat[chan][i]);
1675
1676 tg3_writephy(tp, 0x16, 0x0202);
1677 if (tg3_wait_macro_done(tp)) {
1678 *resetp = 1;
1679 return -EBUSY;
1680 }
1681
1682 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1683 (chan * 0x2000) | 0x0200);
1684 tg3_writephy(tp, 0x16, 0x0082);
1685 if (tg3_wait_macro_done(tp)) {
1686 *resetp = 1;
1687 return -EBUSY;
1688 }
1689
1690 tg3_writephy(tp, 0x16, 0x0802);
1691 if (tg3_wait_macro_done(tp)) {
1692 *resetp = 1;
1693 return -EBUSY;
1694 }
1695
1696 for (i = 0; i < 6; i += 2) {
1697 u32 low, high;
1698
1699 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1700 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1701 tg3_wait_macro_done(tp)) {
1702 *resetp = 1;
1703 return -EBUSY;
1704 }
1705 low &= 0x7fff;
1706 high &= 0x000f;
1707 if (low != test_pat[chan][i] ||
1708 high != test_pat[chan][i+1]) {
1709 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1710 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1711 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1712
1713 return -EBUSY;
1714 }
1715 }
1716 }
1717
1718 return 0;
1719}
1720
1721static int tg3_phy_reset_chanpat(struct tg3 *tp)
1722{
1723 int chan;
1724
1725 for (chan = 0; chan < 4; chan++) {
1726 int i;
1727
1728 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1729 (chan * 0x2000) | 0x0200);
1730 tg3_writephy(tp, 0x16, 0x0002);
1731 for (i = 0; i < 6; i++)
1732 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1733 tg3_writephy(tp, 0x16, 0x0202);
1734 if (tg3_wait_macro_done(tp))
1735 return -EBUSY;
1736 }
1737
1738 return 0;
1739}
1740
1741static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1742{
1743 u32 reg32, phy9_orig;
1744 int retries, do_phy_reset, err;
1745
1746 retries = 10;
1747 do_phy_reset = 1;
1748 do {
1749 if (do_phy_reset) {
1750 err = tg3_bmcr_reset(tp);
1751 if (err)
1752 return err;
1753 do_phy_reset = 0;
1754 }
1755
1756 /* Disable transmitter and interrupt. */
1757 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1758 continue;
1759
1760 reg32 |= 0x3000;
1761 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1762
1763 /* Set full-duplex, 1000 mbps. */
1764 tg3_writephy(tp, MII_BMCR,
1765 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1766
1767 /* Set to master mode. */
1768 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1769 continue;
1770
1771 tg3_writephy(tp, MII_TG3_CTRL,
1772 (MII_TG3_CTRL_AS_MASTER |
1773 MII_TG3_CTRL_ENABLE_AS_MASTER));
1774
1775 /* Enable SM_DSP_CLOCK and 6dB. */
1776 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1777
1778 /* Block the PHY control access. */
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1780 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1781
1782 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1783 if (!err)
1784 break;
1785 } while (--retries);
1786
1787 err = tg3_phy_reset_chanpat(tp);
1788 if (err)
1789 return err;
1790
1791 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1792 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1793
1794 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1795 tg3_writephy(tp, 0x16, 0x0000);
1796
1797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1799 /* Set Extended packet length bit for jumbo frames */
1800 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1801 }
1802 else {
1803 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1804 }
1805
1806 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1807
1808 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1809 reg32 &= ~0x3000;
1810 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1811 } else if (!err)
1812 err = -EBUSY;
1813
1814 return err;
1815}
1816
1817/* This will reset the tigon3 PHY if there is no valid
1818 * link unless the FORCE argument is non-zero.
1819 */
1820static int tg3_phy_reset(struct tg3 *tp)
1821{
b2a5c19c 1822 u32 cpmuctrl;
1da177e4
LT		 1823 u32 phy_status;
1824 int err;
1825
60189ddf
MC		 1826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1827 u32 val;
1828
1829 val = tr32(GRC_MISC_CFG);
1830 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1831 udelay(40);
1832 }
1da177e4
LT		 1833 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1834 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1835 if (err != 0)
1836 return -EBUSY;
1837
c8e1e82b
MC		 1838 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1839 netif_carrier_off(tp->dev);
1840 tg3_link_report(tp);
1841 }
1842
1da177e4
LT		 1843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1846 err = tg3_phy_reset_5703_4_5(tp);
1847 if (err)
1848 return err;
1849 goto out;
1850 }
1851
b2a5c19c
MC		 1852 cpmuctrl = 0;
1853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1854 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1855 cpmuctrl = tr32(TG3_CPMU_CTRL);
1856 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1857 tw32(TG3_CPMU_CTRL,
1858 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1859 }
1860
1da177e4
LT		 1861 err = tg3_bmcr_reset(tp);
1862 if (err)
1863 return err;
1864
b2a5c19c
MC		 1865 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1866 u32 phy;
1867
1868 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1869 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1870
1871 tw32(TG3_CPMU_CTRL, cpmuctrl);
1872 }
1873
bcb37f6c
MC		 1874 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1875 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1876 u32 val;
1877
1878 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1879 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1880 CPMU_LSPD_1000MB_MACCLK_12_5) {
1881 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1882 udelay(40);
1883 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1884 }
1885 }
1886
b2a5c19c
MC		 1887 tg3_phy_apply_otp(tp);
1888
6833c043
MC		 1889 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1890 tg3_phy_toggle_apd(tp, true);
1891 else
1892 tg3_phy_toggle_apd(tp, false);
1893
1da177e4
LT		 1894out:
1895 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1896 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1898 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1899 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1900 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1901 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902 }
1903 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1904 tg3_writephy(tp, 0x1c, 0x8d68);
1905 tg3_writephy(tp, 0x1c, 0x8d68);
1906 }
1907 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1908 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1910 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1911 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1913 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1914 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1915 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1916 }
c424cb24
MC		 1917 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1918 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1919 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1920 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1921 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1922 tg3_writephy(tp, MII_TG3_TEST1,
1923 MII_TG3_TEST1_TRIM_EN | 0x4);
1924 } else
1925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1926 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1927 }
1da177e4
LT		 1928 /* Set Extended packet length bit (bit 14) on all chips that */
1929 /* support jumbo frames */
1930 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1931 /* Cannot do read-modify-write on 5401 */
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1933 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1934 u32 phy_reg;
1935
1936 /* Set bit 14 with read-modify-write to preserve other bits */
1937 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1938 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1940 }
1941
1942 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1943 * jumbo frames transmission.
1944 */
8f666b07 1945 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1946 u32 phy_reg;
1947
1948 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1949 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1950 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1951 }
1952
715116a1 1953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1954 /* adjust output voltage */
535ef6e1 1955 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1956 }
1957
9ef8ca99 1958 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1959 tg3_phy_set_wirespeed(tp);
1960 return 0;
1961}
1962
1963static void tg3_frob_aux_power(struct tg3 *tp)
1964{
1965 struct tg3 *tp_peer = tp;
1966
9d26e213 1967 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1968 return;
1969
8c2dc7e1
MC		 1970 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1971 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1972 struct net_device *dev_peer;
1973
1974 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1975 /* remove_one() may have been run on the peer. */
8c2dc7e1 1976 if (!dev_peer)
bc1c7567
MC		 1977 tp_peer = tp;
1978 else
1979 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1980 }
1981
1da177e4 1982 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1983 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1984 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1985 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1988 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1989 (GRC_LCLCTRL_GPIO_OE0 |
1990 GRC_LCLCTRL_GPIO_OE1 |
1991 GRC_LCLCTRL_GPIO_OE2 |
1992 GRC_LCLCTRL_GPIO_OUTPUT0 |
1993 GRC_LCLCTRL_GPIO_OUTPUT1),
1994 100);
8d519ab2
MC		 1995 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1996 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 1997 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1998 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1999 GRC_LCLCTRL_GPIO_OE1 |
2000 GRC_LCLCTRL_GPIO_OE2 |
2001 GRC_LCLCTRL_GPIO_OUTPUT0 |
2002 GRC_LCLCTRL_GPIO_OUTPUT1 |
2003 tp->grc_local_ctrl;
2004 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2005
2006 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2007 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2008
2009 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2010 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2011 } else {
2012 u32 no_gpio2;
dc56b7d4 2013 u32 grc_local_ctrl = 0;
1da177e4
LT		 2014
2015 if (tp_peer != tp &&
2016 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017 return;
2018
dc56b7d4
MC		 2019 /* Workaround to prevent overdrawing Amps. */
2020 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2021 ASIC_REV_5714) {
2022 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2023 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024 grc_local_ctrl, 100);
dc56b7d4
MC		 2025 }
2026
1da177e4
LT		 2027 /* On 5753 and variants, GPIO2 cannot be used. */
2028 no_gpio2 = tp->nic_sram_data_cfg &
2029 NIC_SRAM_DATA_CFG_NO_GPIO2;
2030
dc56b7d4 2031 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2032 GRC_LCLCTRL_GPIO_OE1 |
2033 GRC_LCLCTRL_GPIO_OE2 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 GRC_LCLCTRL_GPIO_OUTPUT2;
2036 if (no_gpio2) {
2037 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2038 GRC_LCLCTRL_GPIO_OUTPUT2);
2039 }
b401e9e2
MC		 2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 grc_local_ctrl, 100);
1da177e4
LT		 2042
2043 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2044
b401e9e2
MC		 2045 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2046 grc_local_ctrl, 100);
1da177e4
LT		 2047
2048 if (!no_gpio2) {
2049 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2050 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2051 grc_local_ctrl, 100);
1da177e4
LT		 2052 }
2053 }
2054 } else {
2055 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2056 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2057 if (tp_peer != tp &&
2058 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2059 return;
2060
b401e9e2
MC		 2061 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2062 (GRC_LCLCTRL_GPIO_OE1 |
2063 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2064
b401e9e2
MC		 2065 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2066 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2067
b401e9e2
MC		 2068 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2069 (GRC_LCLCTRL_GPIO_OE1 |
2070 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2071 }
2072 }
2073}
2074
e8f3f6ca
MC		 2075static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2076{
2077 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2078 return 1;
2079 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2080 if (speed != SPEED_10)
2081 return 1;
2082 } else if (speed == SPEED_10)
2083 return 1;
2084
2085 return 0;
2086}
2087
1da177e4
LT		 2088static int tg3_setup_phy(struct tg3 *, int);
2089
2090#define RESET_KIND_SHUTDOWN 0
2091#define RESET_KIND_INIT 1
2092#define RESET_KIND_SUSPEND 2
2093
2094static void tg3_write_sig_post_reset(struct tg3 *, int);
2095static int tg3_halt_cpu(struct tg3 *, u32);
2096
0a459aac 2097static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2098{
ce057f01
MC		 2099 u32 val;
2100
5129724a
MC		 2101 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2103 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2104 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2105
2106 sg_dig_ctrl |=
2107 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2108 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2109 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2110 }
3f7045c1 2111 return;
5129724a 2112 }
3f7045c1 2113
60189ddf 2114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2115 tg3_bmcr_reset(tp);
2116 val = tr32(GRC_MISC_CFG);
2117 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2118 udelay(40);
2119 return;
0a459aac 2120 } else if (do_low_power) {
715116a1
MC		 2121 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2122 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2123
2124 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2125 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2126 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2127 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2128 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2129 }
3f7045c1 2130
15c3b696
MC		 2131 /* The PHY should not be powered down on some chips because
2132 * of bugs.
2133 */
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2137 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2138 return;
ce057f01 2139
bcb37f6c
MC		 2140 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2141 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2142 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2143 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2144 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2145 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2146 }
2147
15c3b696
MC		 2148 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2149}
2150
ffbcfed4
MC		 2151/* tp->lock is held. */
2152static int tg3_nvram_lock(struct tg3 *tp)
2153{
2154 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2155 int i;
2156
2157 if (tp->nvram_lock_cnt == 0) {
2158 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2159 for (i = 0; i < 8000; i++) {
2160 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2161 break;
2162 udelay(20);
2163 }
2164 if (i == 8000) {
2165 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2166 return -ENODEV;
2167 }
2168 }
2169 tp->nvram_lock_cnt++;
2170 }
2171 return 0;
2172}
2173
2174/* tp->lock is held. */
2175static void tg3_nvram_unlock(struct tg3 *tp)
2176{
2177 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2178 if (tp->nvram_lock_cnt > 0)
2179 tp->nvram_lock_cnt--;
2180 if (tp->nvram_lock_cnt == 0)
2181 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2182 }
2183}
2184
2185/* tp->lock is held. */
2186static void tg3_enable_nvram_access(struct tg3 *tp)
2187{
2188 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2189 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2190 u32 nvaccess = tr32(NVRAM_ACCESS);
2191
2192 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2193 }
2194}
2195
2196/* tp->lock is held. */
2197static void tg3_disable_nvram_access(struct tg3 *tp)
2198{
2199 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2200 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2201 u32 nvaccess = tr32(NVRAM_ACCESS);
2202
2203 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2204 }
2205}
2206
2207static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2208 u32 offset, u32 *val)
2209{
2210 u32 tmp;
2211 int i;
2212
2213 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2214 return -EINVAL;
2215
2216 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2217 EEPROM_ADDR_DEVID_MASK |
2218 EEPROM_ADDR_READ);
2219 tw32(GRC_EEPROM_ADDR,
2220 tmp |
2221 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2222 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2223 EEPROM_ADDR_ADDR_MASK) |
2224 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2225
2226 for (i = 0; i < 1000; i++) {
2227 tmp = tr32(GRC_EEPROM_ADDR);
2228
2229 if (tmp & EEPROM_ADDR_COMPLETE)
2230 break;
2231 msleep(1);
2232 }
2233 if (!(tmp & EEPROM_ADDR_COMPLETE))
2234 return -EBUSY;
2235
62cedd11
MC		 2236 tmp = tr32(GRC_EEPROM_DATA);
2237
2238 /*
2239 * The data will always be opposite the native endian
2240 * format. Perform a blind byteswap to compensate.
2241 */
2242 *val = swab32(tmp);
2243
ffbcfed4
MC		 2244 return 0;
2245}
2246
2247#define NVRAM_CMD_TIMEOUT 10000
2248
2249static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2250{
2251 int i;
2252
2253 tw32(NVRAM_CMD, nvram_cmd);
2254 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2255 udelay(10);
2256 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2257 udelay(10);
2258 break;
2259 }
2260 }
2261
2262 if (i == NVRAM_CMD_TIMEOUT)
2263 return -EBUSY;
2264
2265 return 0;
2266}
2267
2268static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2269{
2270 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2271 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2272 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2273 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2274 (tp->nvram_jedecnum == JEDEC_ATMEL))
2275
2276 addr = ((addr / tp->nvram_pagesize) <<
2277 ATMEL_AT45DB0X1B_PAGE_POS) +
2278 (addr % tp->nvram_pagesize);
2279
2280 return addr;
2281}
2282
2283static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2284{
2285 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2286 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2287 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2288 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2289 (tp->nvram_jedecnum == JEDEC_ATMEL))
2290
2291 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2292 tp->nvram_pagesize) +
2293 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2294
2295 return addr;
2296}
2297
e4f34110
MC		 2298/* NOTE: Data read in from NVRAM is byteswapped according to
2299 * the byteswapping settings for all other register accesses.
2300 * tg3 devices are BE devices, so on a BE machine, the data
2301 * returned will be exactly as it is seen in NVRAM. On a LE
2302 * machine, the 32-bit value will be byteswapped.
2303 */
ffbcfed4
MC		 2304static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2305{
2306 int ret;
2307
2308 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2309 return tg3_nvram_read_using_eeprom(tp, offset, val);
2310
2311 offset = tg3_nvram_phys_addr(tp, offset);
2312
2313 if (offset > NVRAM_ADDR_MSK)
2314 return -EINVAL;
2315
2316 ret = tg3_nvram_lock(tp);
2317 if (ret)
2318 return ret;
2319
2320 tg3_enable_nvram_access(tp);
2321
2322 tw32(NVRAM_ADDR, offset);
2323 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2324 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2325
2326 if (ret == 0)
e4f34110 2327 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2328
2329 tg3_disable_nvram_access(tp);
2330
2331 tg3_nvram_unlock(tp);
2332
2333 return ret;
2334}
2335
a9dc529d
MC		 2336/* Ensures NVRAM data is in bytestream format. */
2337static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2338{
2339 u32 v;
a9dc529d 2340 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2341 if (!res)
a9dc529d 2342 *val = cpu_to_be32(v);
ffbcfed4
MC		 2343 return res;
2344}
2345
3f007891
MC		 2346/* tp->lock is held. */
2347static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2348{
2349 u32 addr_high, addr_low;
2350 int i;
2351
2352 addr_high = ((tp->dev->dev_addr[0] << 8) |
2353 tp->dev->dev_addr[1]);
2354 addr_low = ((tp->dev->dev_addr[2] << 24) |
2355 (tp->dev->dev_addr[3] << 16) |
2356 (tp->dev->dev_addr[4] << 8) |
2357 (tp->dev->dev_addr[5] << 0));
2358 for (i = 0; i < 4; i++) {
2359 if (i == 1 && skip_mac_1)
2360 continue;
2361 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2362 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2363 }
2364
2365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2367 for (i = 0; i < 12; i++) {
2368 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2369 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2370 }
2371 }
2372
2373 addr_high = (tp->dev->dev_addr[0] +
2374 tp->dev->dev_addr[1] +
2375 tp->dev->dev_addr[2] +
2376 tp->dev->dev_addr[3] +
2377 tp->dev->dev_addr[4] +
2378 tp->dev->dev_addr[5]) &
2379 TX_BACKOFF_SEED_MASK;
2380 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2381}
2382
bc1c7567 2383static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2384{
2385 u32 misc_host_ctrl;
0a459aac 2386 bool device_should_wake, do_low_power;
1da177e4
LT		 2387
2388 /* Make sure register accesses (indirect or otherwise)
2389 * will function correctly.
2390 */
2391 pci_write_config_dword(tp->pdev,
2392 TG3PCI_MISC_HOST_CTRL,
2393 tp->misc_host_ctrl);
2394
1da177e4 2395 switch (state) {
bc1c7567 2396 case PCI_D0:
12dac075
RW		 2397 pci_enable_wake(tp->pdev, state, false);
2398 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2399
9d26e213
MC		 2400 /* Switch out of Vaux if it is a NIC */
2401 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2402 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2403
2404 return 0;
2405
bc1c7567 2406 case PCI_D1:
bc1c7567 2407 case PCI_D2:
bc1c7567 2408 case PCI_D3hot:
1da177e4
LT		 2409 break;
2410
2411 default:
12dac075
RW		 2412 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2413 tp->dev->name, state);
1da177e4 2414 return -EINVAL;
855e1111 2415 }
5e7dfd0f
MC		 2416
2417 /* Restore the CLKREQ setting. */
2418 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2419 u16 lnkctl;
2420
2421 pci_read_config_word(tp->pdev,
2422 tp->pcie_cap + PCI_EXP_LNKCTL,
2423 &lnkctl);
2424 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2425 pci_write_config_word(tp->pdev,
2426 tp->pcie_cap + PCI_EXP_LNKCTL,
2427 lnkctl);
2428 }
2429
1da177e4
LT		 2430 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2431 tw32(TG3PCI_MISC_HOST_CTRL,
2432 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2433
05ac4cb7
MC		 2434 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2435 device_may_wakeup(&tp->pdev->dev) &&
2436 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2437
dd477003 2438 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2439 do_low_power = false;
b02fd9e3
MC		 2440 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2441 !tp->link_config.phy_is_low_power) {
2442 struct phy_device *phydev;
0a459aac 2443 u32 phyid, advertising;
b02fd9e3 2444
298cf9be 2445 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2446
2447 tp->link_config.phy_is_low_power = 1;
2448
2449 tp->link_config.orig_speed = phydev->speed;
2450 tp->link_config.orig_duplex = phydev->duplex;
2451 tp->link_config.orig_autoneg = phydev->autoneg;
2452 tp->link_config.orig_advertising = phydev->advertising;
2453
2454 advertising = ADVERTISED_TP |
2455 ADVERTISED_Pause |
2456 ADVERTISED_Autoneg |
2457 ADVERTISED_10baseT_Half;
2458
2459 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2460 device_should_wake) {
b02fd9e3
MC		 2461 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2462 advertising |=
2463 ADVERTISED_100baseT_Half |
2464 ADVERTISED_100baseT_Full |
2465 ADVERTISED_10baseT_Full;
2466 else
2467 advertising |= ADVERTISED_10baseT_Full;
2468 }
2469
2470 phydev->advertising = advertising;
2471
2472 phy_start_aneg(phydev);
0a459aac
MC		 2473
2474 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2475 if (phyid != TG3_PHY_ID_BCMAC131) {
2476 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2477 if (phyid == TG3_PHY_OUI_1 ||
2478 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2479 phyid == TG3_PHY_OUI_3)
2480 do_low_power = true;
2481 }
b02fd9e3 2482 }
dd477003 2483 } else {
2023276e 2484 do_low_power = true;
0a459aac 2485
dd477003
MC		 2486 if (tp->link_config.phy_is_low_power == 0) {
2487 tp->link_config.phy_is_low_power = 1;
2488 tp->link_config.orig_speed = tp->link_config.speed;
2489 tp->link_config.orig_duplex = tp->link_config.duplex;
2490 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2491 }
1da177e4 2492
dd477003
MC		 2493 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2494 tp->link_config.speed = SPEED_10;
2495 tp->link_config.duplex = DUPLEX_HALF;
2496 tp->link_config.autoneg = AUTONEG_ENABLE;
2497 tg3_setup_phy(tp, 0);
2498 }
1da177e4
LT		 2499 }
2500
b5d3772c
MC		 2501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2502 u32 val;
2503
2504 val = tr32(GRC_VCPU_EXT_CTRL);
2505 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2506 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2507 int i;
2508 u32 val;
2509
2510 for (i = 0; i < 200; i++) {
2511 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2512 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2513 break;
2514 msleep(1);
2515 }
2516 }
a85feb8c
GZ		 2517 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2518 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2519 WOL_DRV_STATE_SHUTDOWN |
2520 WOL_DRV_WOL |
2521 WOL_SET_MAGIC_PKT);
6921d201 2522
05ac4cb7 2523 if (device_should_wake) {
1da177e4
LT		 2524 u32 mac_mode;
2525
2526 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2527 if (do_low_power) {
dd477003
MC		 2528 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2529 udelay(40);
2530 }
1da177e4 2531
3f7045c1
MC		 2532 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2533 mac_mode = MAC_MODE_PORT_MODE_GMII;
2534 else
2535 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2536
e8f3f6ca
MC		 2537 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2538 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2539 ASIC_REV_5700) {
2540 u32 speed = (tp->tg3_flags &
2541 TG3_FLAG_WOL_SPEED_100MB) ?
2542 SPEED_100 : SPEED_10;
2543 if (tg3_5700_link_polarity(tp, speed))
2544 mac_mode |= MAC_MODE_LINK_POLARITY;
2545 else
2546 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2547 }
1da177e4
LT		 2548 } else {
2549 mac_mode = MAC_MODE_PORT_MODE_TBI;
2550 }
2551
cbf46853 2552 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2553 tw32(MAC_LED_CTRL, tp->led_ctrl);
2554
05ac4cb7
MC		 2555 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2556 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2557 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2558 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2559 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2560 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2561
3bda1258
MC		 2562 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2563 mac_mode |= tp->mac_mode &
2564 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2565 if (mac_mode & MAC_MODE_APE_TX_EN)
2566 mac_mode |= MAC_MODE_TDE_ENABLE;
2567 }
2568
1da177e4
LT		 2569 tw32_f(MAC_MODE, mac_mode);
2570 udelay(100);
2571
2572 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2573 udelay(10);
2574 }
2575
2576 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2577 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2579 u32 base_val;
2580
2581 base_val = tp->pci_clock_ctrl;
2582 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2583 CLOCK_CTRL_TXCLK_DISABLE);
2584
b401e9e2
MC		 2585 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2586 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2587 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2588 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2590 /* do nothing */
85e94ced 2591 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2592 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2593 u32 newbits1, newbits2;
2594
2595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2597 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2598 CLOCK_CTRL_TXCLK_DISABLE |
2599 CLOCK_CTRL_ALTCLK);
2600 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2601 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2602 newbits1 = CLOCK_CTRL_625_CORE;
2603 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2604 } else {
2605 newbits1 = CLOCK_CTRL_ALTCLK;
2606 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2607 }
2608
b401e9e2
MC		 2609 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2610 40);
1da177e4 2611
b401e9e2
MC		 2612 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2613 40);
1da177e4
LT		 2614
2615 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2616 u32 newbits3;
2617
2618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2620 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2621 CLOCK_CTRL_TXCLK_DISABLE |
2622 CLOCK_CTRL_44MHZ_CORE);
2623 } else {
2624 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2625 }
2626
b401e9e2
MC		 2627 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2628 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2629 }
2630 }
2631
05ac4cb7 2632 if (!(device_should_wake) &&
22435849 2633 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2634 tg3_power_down_phy(tp, do_low_power);
6921d201 2635
1da177e4
LT		 2636 tg3_frob_aux_power(tp);
2637
2638 /* Workaround for unstable PLL clock */
2639 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2640 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2641 u32 val = tr32(0x7d00);
2642
2643 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2644 tw32(0x7d00, val);
6921d201 2645 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2646 int err;
2647
2648 err = tg3_nvram_lock(tp);
1da177e4 2649 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2650 if (!err)
2651 tg3_nvram_unlock(tp);
6921d201 2652 }
1da177e4
LT		 2653 }
2654
bbadf503
MC		 2655 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2656
05ac4cb7 2657 if (device_should_wake)
12dac075
RW		 2658 pci_enable_wake(tp->pdev, state, true);
2659
1da177e4 2660 /* Finally, set the new power state. */
12dac075 2661 pci_set_power_state(tp->pdev, state);
1da177e4 2662
1da177e4
LT		 2663 return 0;
2664}
2665
1da177e4
LT		 2666static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2667{
2668 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2669 case MII_TG3_AUX_STAT_10HALF:
2670 *speed = SPEED_10;
2671 *duplex = DUPLEX_HALF;
2672 break;
2673
2674 case MII_TG3_AUX_STAT_10FULL:
2675 *speed = SPEED_10;
2676 *duplex = DUPLEX_FULL;
2677 break;
2678
2679 case MII_TG3_AUX_STAT_100HALF:
2680 *speed = SPEED_100;
2681 *duplex = DUPLEX_HALF;
2682 break;
2683
2684 case MII_TG3_AUX_STAT_100FULL:
2685 *speed = SPEED_100;
2686 *duplex = DUPLEX_FULL;
2687 break;
2688
2689 case MII_TG3_AUX_STAT_1000HALF:
2690 *speed = SPEED_1000;
2691 *duplex = DUPLEX_HALF;
2692 break;
2693
2694 case MII_TG3_AUX_STAT_1000FULL:
2695 *speed = SPEED_1000;
2696 *duplex = DUPLEX_FULL;
2697 break;
2698
2699 default:
7f97a4bd 2700 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2701 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2702 SPEED_10;
2703 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2704 DUPLEX_HALF;
2705 break;
2706 }
1da177e4
LT		 2707 *speed = SPEED_INVALID;
2708 *duplex = DUPLEX_INVALID;
2709 break;
855e1111 2710 }
1da177e4
LT		 2711}
2712
2713static void tg3_phy_copper_begin(struct tg3 *tp)
2714{
2715 u32 new_adv;
2716 int i;
2717
2718 if (tp->link_config.phy_is_low_power) {
2719 /* Entering low power mode. Disable gigabit and
2720 * 100baseT advertisements.
2721 */
2722 tg3_writephy(tp, MII_TG3_CTRL, 0);
2723
2724 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2725 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2726 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2727 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2728
2729 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2730 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2731 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2732 tp->link_config.advertising &=
2733 ~(ADVERTISED_1000baseT_Half |
2734 ADVERTISED_1000baseT_Full);
2735
ba4d07a8 2736 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2737 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2738 new_adv |= ADVERTISE_10HALF;
2739 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2740 new_adv |= ADVERTISE_10FULL;
2741 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2742 new_adv |= ADVERTISE_100HALF;
2743 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2744 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2745
2746 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2747
1da177e4
LT		 2748 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2749
2750 if (tp->link_config.advertising &
2751 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2752 new_adv = 0;
2753 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2754 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2755 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2756 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2757 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2758 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2759 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2760 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2761 MII_TG3_CTRL_ENABLE_AS_MASTER);
2762 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2763 } else {
2764 tg3_writephy(tp, MII_TG3_CTRL, 0);
2765 }
2766 } else {
ba4d07a8
MC		 2767 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2768 new_adv |= ADVERTISE_CSMA;
2769
1da177e4
LT		 2770 /* Asking for a specific link mode. */
2771 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2772 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2773
2774 if (tp->link_config.duplex == DUPLEX_FULL)
2775 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2776 else
2777 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2778 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2779 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2780 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2781 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2782 } else {
1da177e4
LT		 2783 if (tp->link_config.speed == SPEED_100) {
2784 if (tp->link_config.duplex == DUPLEX_FULL)
2785 new_adv |= ADVERTISE_100FULL;
2786 else
2787 new_adv |= ADVERTISE_100HALF;
2788 } else {
2789 if (tp->link_config.duplex == DUPLEX_FULL)
2790 new_adv |= ADVERTISE_10FULL;
2791 else
2792 new_adv |= ADVERTISE_10HALF;
2793 }
2794 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2795
2796 new_adv = 0;
1da177e4 2797 }
ba4d07a8
MC		 2798
2799 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2800 }
2801
2802 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2803 tp->link_config.speed != SPEED_INVALID) {
2804 u32 bmcr, orig_bmcr;
2805
2806 tp->link_config.active_speed = tp->link_config.speed;
2807 tp->link_config.active_duplex = tp->link_config.duplex;
2808
2809 bmcr = 0;
2810 switch (tp->link_config.speed) {
2811 default:
2812 case SPEED_10:
2813 break;
2814
2815 case SPEED_100:
2816 bmcr |= BMCR_SPEED100;
2817 break;
2818
2819 case SPEED_1000:
2820 bmcr |= TG3_BMCR_SPEED1000;
2821 break;
855e1111 2822 }
1da177e4
LT		 2823
2824 if (tp->link_config.duplex == DUPLEX_FULL)
2825 bmcr |= BMCR_FULLDPLX;
2826
2827 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2828 (bmcr != orig_bmcr)) {
2829 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2830 for (i = 0; i < 1500; i++) {
2831 u32 tmp;
2832
2833 udelay(10);
2834 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2835 tg3_readphy(tp, MII_BMSR, &tmp))
2836 continue;
2837 if (!(tmp & BMSR_LSTATUS)) {
2838 udelay(40);
2839 break;
2840 }
2841 }
2842 tg3_writephy(tp, MII_BMCR, bmcr);
2843 udelay(40);
2844 }
2845 } else {
2846 tg3_writephy(tp, MII_BMCR,
2847 BMCR_ANENABLE | BMCR_ANRESTART);
2848 }
2849}
2850
2851static int tg3_init_5401phy_dsp(struct tg3 *tp)
2852{
2853 int err;
2854
2855 /* Turn off tap power management. */
2856 /* Set Extended packet length bit */
2857 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2858
2859 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2860 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2861
2862 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2863 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2864
2865 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2866 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2867
2868 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2869 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2870
2871 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2872 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2873
2874 udelay(40);
2875
2876 return err;
2877}
2878
3600d918 2879static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2880{
3600d918
MC		 2881 u32 adv_reg, all_mask = 0;
2882
2883 if (mask & ADVERTISED_10baseT_Half)
2884 all_mask |= ADVERTISE_10HALF;
2885 if (mask & ADVERTISED_10baseT_Full)
2886 all_mask |= ADVERTISE_10FULL;
2887 if (mask & ADVERTISED_100baseT_Half)
2888 all_mask |= ADVERTISE_100HALF;
2889 if (mask & ADVERTISED_100baseT_Full)
2890 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2891
2892 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2893 return 0;
2894
1da177e4
LT		 2895 if ((adv_reg & all_mask) != all_mask)
2896 return 0;
2897 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2898 u32 tg3_ctrl;
2899
3600d918
MC		 2900 all_mask = 0;
2901 if (mask & ADVERTISED_1000baseT_Half)
2902 all_mask |= ADVERTISE_1000HALF;
2903 if (mask & ADVERTISED_1000baseT_Full)
2904 all_mask |= ADVERTISE_1000FULL;
2905
1da177e4
LT		 2906 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2907 return 0;
2908
1da177e4
LT		 2909 if ((tg3_ctrl & all_mask) != all_mask)
2910 return 0;
2911 }
2912 return 1;
2913}
2914
ef167e27
MC		 2915static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2916{
2917 u32 curadv, reqadv;
2918
2919 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2920 return 1;
2921
2922 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2923 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2924
2925 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2926 if (curadv != reqadv)
2927 return 0;
2928
2929 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2930 tg3_readphy(tp, MII_LPA, rmtadv);
2931 } else {
2932 /* Reprogram the advertisement register, even if it
2933 * does not affect the current link. If the link
2934 * gets renegotiated in the future, we can save an
2935 * additional renegotiation cycle by advertising
2936 * it correctly in the first place.
2937 */
2938 if (curadv != reqadv) {
2939 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2940 ADVERTISE_PAUSE_ASYM);
2941 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2942 }
2943 }
2944
2945 return 1;
2946}
2947
1da177e4
LT		 2948static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2949{
2950 int current_link_up;
2951 u32 bmsr, dummy;
ef167e27 2952 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2953 u16 current_speed;
2954 u8 current_duplex;
2955 int i, err;
2956
2957 tw32(MAC_EVENT, 0);
2958
2959 tw32_f(MAC_STATUS,
2960 (MAC_STATUS_SYNC_CHANGED |
2961 MAC_STATUS_CFG_CHANGED |
2962 MAC_STATUS_MI_COMPLETION |
2963 MAC_STATUS_LNKSTATE_CHANGED));
2964 udelay(40);
2965
8ef21428
MC		 2966 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2967 tw32_f(MAC_MI_MODE,
2968 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2969 udelay(80);
2970 }
1da177e4
LT		 2971
2972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2973
2974 /* Some third-party PHYs need to be reset on link going
2975 * down.
2976 */
2977 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2980 netif_carrier_ok(tp->dev)) {
2981 tg3_readphy(tp, MII_BMSR, &bmsr);
2982 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2983 !(bmsr & BMSR_LSTATUS))
2984 force_reset = 1;
2985 }
2986 if (force_reset)
2987 tg3_phy_reset(tp);
2988
2989 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2990 tg3_readphy(tp, MII_BMSR, &bmsr);
2991 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2992 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2993 bmsr = 0;
2994
2995 if (!(bmsr & BMSR_LSTATUS)) {
2996 err = tg3_init_5401phy_dsp(tp);
2997 if (err)
2998 return err;
2999
3000 tg3_readphy(tp, MII_BMSR, &bmsr);
3001 for (i = 0; i < 1000; i++) {
3002 udelay(10);
3003 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3004 (bmsr & BMSR_LSTATUS)) {
3005 udelay(40);
3006 break;
3007 }
3008 }
3009
3010 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3011 !(bmsr & BMSR_LSTATUS) &&
3012 tp->link_config.active_speed == SPEED_1000) {
3013 err = tg3_phy_reset(tp);
3014 if (!err)
3015 err = tg3_init_5401phy_dsp(tp);
3016 if (err)
3017 return err;
3018 }
3019 }
3020 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3021 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3022 /* 5701 {A0,B0} CRC bug workaround */
3023 tg3_writephy(tp, 0x15, 0x0a75);
3024 tg3_writephy(tp, 0x1c, 0x8c68);
3025 tg3_writephy(tp, 0x1c, 0x8d68);
3026 tg3_writephy(tp, 0x1c, 0x8c68);
3027 }
3028
3029 /* Clear pending interrupts... */
3030 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3031 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3032
3033 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3034 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3035 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3036 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3037
3038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3040 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3041 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3042 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3043 else
3044 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3045 }
3046
3047 current_link_up = 0;
3048 current_speed = SPEED_INVALID;
3049 current_duplex = DUPLEX_INVALID;
3050
3051 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3052 u32 val;
3053
3054 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3055 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3056 if (!(val & (1 << 10))) {
3057 val |= (1 << 10);
3058 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3059 goto relink;
3060 }
3061 }
3062
3063 bmsr = 0;
3064 for (i = 0; i < 100; i++) {
3065 tg3_readphy(tp, MII_BMSR, &bmsr);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 (bmsr & BMSR_LSTATUS))
3068 break;
3069 udelay(40);
3070 }
3071
3072 if (bmsr & BMSR_LSTATUS) {
3073 u32 aux_stat, bmcr;
3074
3075 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3076 for (i = 0; i < 2000; i++) {
3077 udelay(10);
3078 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3079 aux_stat)
3080 break;
3081 }
3082
3083 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3084 &current_speed,
3085 &current_duplex);
3086
3087 bmcr = 0;
3088 for (i = 0; i < 200; i++) {
3089 tg3_readphy(tp, MII_BMCR, &bmcr);
3090 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3091 continue;
3092 if (bmcr && bmcr != 0x7fff)
3093 break;
3094 udelay(10);
3095 }
3096
ef167e27
MC		 3097 lcl_adv = 0;
3098 rmt_adv = 0;
1da177e4 3099
ef167e27
MC		 3100 tp->link_config.active_speed = current_speed;
3101 tp->link_config.active_duplex = current_duplex;
3102
3103 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3104 if ((bmcr & BMCR_ANENABLE) &&
3105 tg3_copper_is_advertising_all(tp,
3106 tp->link_config.advertising)) {
3107 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3108 &rmt_adv))
3109 current_link_up = 1;
1da177e4
LT		 3110 }
3111 } else {
3112 if (!(bmcr & BMCR_ANENABLE) &&
3113 tp->link_config.speed == current_speed &&
ef167e27
MC		 3114 tp->link_config.duplex == current_duplex &&
3115 tp->link_config.flowctrl ==
3116 tp->link_config.active_flowctrl) {
1da177e4 3117 current_link_up = 1;
1da177e4
LT		 3118 }
3119 }
3120
ef167e27
MC		 3121 if (current_link_up == 1 &&
3122 tp->link_config.active_duplex == DUPLEX_FULL)
3123 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3124 }
3125
1da177e4 3126relink:
6921d201 3127 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3128 u32 tmp;
3129
3130 tg3_phy_copper_begin(tp);
3131
3132 tg3_readphy(tp, MII_BMSR, &tmp);
3133 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3134 (tmp & BMSR_LSTATUS))
3135 current_link_up = 1;
3136 }
3137
3138 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3139 if (current_link_up == 1) {
3140 if (tp->link_config.active_speed == SPEED_100 ||
3141 tp->link_config.active_speed == SPEED_10)
3142 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3143 else
3144 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3145 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3146 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3147 else
1da177e4
LT		 3148 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3149
3150 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3151 if (tp->link_config.active_duplex == DUPLEX_HALF)
3152 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3153
1da177e4 3154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3155 if (current_link_up == 1 &&
3156 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3157 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3158 else
3159 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3160 }
3161
3162 /* ??? Without this setting Netgear GA302T PHY does not
3163 * ??? send/receive packets...
3164 */
3165 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3166 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3167 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3168 tw32_f(MAC_MI_MODE, tp->mi_mode);
3169 udelay(80);
3170 }
3171
3172 tw32_f(MAC_MODE, tp->mac_mode);
3173 udelay(40);
3174
3175 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3176 /* Polled via timer. */
3177 tw32_f(MAC_EVENT, 0);
3178 } else {
3179 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3180 }
3181 udelay(40);
3182
3183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3184 current_link_up == 1 &&
3185 tp->link_config.active_speed == SPEED_1000 &&
3186 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3187 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3188 udelay(120);
3189 tw32_f(MAC_STATUS,
3190 (MAC_STATUS_SYNC_CHANGED |
3191 MAC_STATUS_CFG_CHANGED));
3192 udelay(40);
3193 tg3_write_mem(tp,
3194 NIC_SRAM_FIRMWARE_MBOX,
3195 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3196 }
3197
5e7dfd0f
MC		 3198 /* Prevent send BD corruption. */
3199 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3200 u16 oldlnkctl, newlnkctl;
3201
3202 pci_read_config_word(tp->pdev,
3203 tp->pcie_cap + PCI_EXP_LNKCTL,
3204 &oldlnkctl);
3205 if (tp->link_config.active_speed == SPEED_100 ||
3206 tp->link_config.active_speed == SPEED_10)
3207 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3208 else
3209 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3210 if (newlnkctl != oldlnkctl)
3211 pci_write_config_word(tp->pdev,
3212 tp->pcie_cap + PCI_EXP_LNKCTL,
3213 newlnkctl);
255ca311
MC		 3214 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3215 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3216 if (tp->link_config.active_speed == SPEED_100 ||
3217 tp->link_config.active_speed == SPEED_10)
3218 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3219 else
3220 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3221 if (newreg != oldreg)
3222 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC		 3223 }
3224
1da177e4
LT		 3225 if (current_link_up != netif_carrier_ok(tp->dev)) {
3226 if (current_link_up)
3227 netif_carrier_on(tp->dev);
3228 else
3229 netif_carrier_off(tp->dev);
3230 tg3_link_report(tp);
3231 }
3232
3233 return 0;
3234}
3235
3236struct tg3_fiber_aneginfo {
3237 int state;
3238#define ANEG_STATE_UNKNOWN 0
3239#define ANEG_STATE_AN_ENABLE 1
3240#define ANEG_STATE_RESTART_INIT 2
3241#define ANEG_STATE_RESTART 3
3242#define ANEG_STATE_DISABLE_LINK_OK 4
3243#define ANEG_STATE_ABILITY_DETECT_INIT 5
3244#define ANEG_STATE_ABILITY_DETECT 6
3245#define ANEG_STATE_ACK_DETECT_INIT 7
3246#define ANEG_STATE_ACK_DETECT 8
3247#define ANEG_STATE_COMPLETE_ACK_INIT 9
3248#define ANEG_STATE_COMPLETE_ACK 10
3249#define ANEG_STATE_IDLE_DETECT_INIT 11
3250#define ANEG_STATE_IDLE_DETECT 12
3251#define ANEG_STATE_LINK_OK 13
3252#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3253#define ANEG_STATE_NEXT_PAGE_WAIT 15
3254
3255 u32 flags;
3256#define MR_AN_ENABLE 0x00000001
3257#define MR_RESTART_AN 0x00000002
3258#define MR_AN_COMPLETE 0x00000004
3259#define MR_PAGE_RX 0x00000008
3260#define MR_NP_LOADED 0x00000010
3261#define MR_TOGGLE_TX 0x00000020
3262#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3263#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3264#define MR_LP_ADV_SYM_PAUSE 0x00000100
3265#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3266#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3267#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3268#define MR_LP_ADV_NEXT_PAGE 0x00001000
3269#define MR_TOGGLE_RX 0x00002000
3270#define MR_NP_RX 0x00004000
3271
3272#define MR_LINK_OK 0x80000000
3273
3274 unsigned long link_time, cur_time;
3275
3276 u32 ability_match_cfg;
3277 int ability_match_count;
3278
3279 char ability_match, idle_match, ack_match;
3280
3281 u32 txconfig, rxconfig;
3282#define ANEG_CFG_NP 0x00000080
3283#define ANEG_CFG_ACK 0x00000040
3284#define ANEG_CFG_RF2 0x00000020
3285#define ANEG_CFG_RF1 0x00000010
3286#define ANEG_CFG_PS2 0x00000001
3287#define ANEG_CFG_PS1 0x00008000
3288#define ANEG_CFG_HD 0x00004000
3289#define ANEG_CFG_FD 0x00002000
3290#define ANEG_CFG_INVAL 0x00001f06
3291
3292};
3293#define ANEG_OK 0
3294#define ANEG_DONE 1
3295#define ANEG_TIMER_ENAB 2
3296#define ANEG_FAILED -1
3297
3298#define ANEG_STATE_SETTLE_TIME 10000
3299
3300static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3301 struct tg3_fiber_aneginfo *ap)
3302{
5be73b47 3303 u16 flowctrl;
1da177e4
LT		 3304 unsigned long delta;
3305 u32 rx_cfg_reg;
3306 int ret;
3307
3308 if (ap->state == ANEG_STATE_UNKNOWN) {
3309 ap->rxconfig = 0;
3310 ap->link_time = 0;
3311 ap->cur_time = 0;
3312 ap->ability_match_cfg = 0;
3313 ap->ability_match_count = 0;
3314 ap->ability_match = 0;
3315 ap->idle_match = 0;
3316 ap->ack_match = 0;
3317 }
3318 ap->cur_time++;
3319
3320 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3321 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3322
3323 if (rx_cfg_reg != ap->ability_match_cfg) {
3324 ap->ability_match_cfg = rx_cfg_reg;
3325 ap->ability_match = 0;
3326 ap->ability_match_count = 0;
3327 } else {
3328 if (++ap->ability_match_count > 1) {
3329 ap->ability_match = 1;
3330 ap->ability_match_cfg = rx_cfg_reg;
3331 }
3332 }
3333 if (rx_cfg_reg & ANEG_CFG_ACK)
3334 ap->ack_match = 1;
3335 else
3336 ap->ack_match = 0;
3337
3338 ap->idle_match = 0;
3339 } else {
3340 ap->idle_match = 1;
3341 ap->ability_match_cfg = 0;
3342 ap->ability_match_count = 0;
3343 ap->ability_match = 0;
3344 ap->ack_match = 0;
3345
3346 rx_cfg_reg = 0;
3347 }
3348
3349 ap->rxconfig = rx_cfg_reg;
3350 ret = ANEG_OK;
3351
3352 switch(ap->state) {
3353 case ANEG_STATE_UNKNOWN:
3354 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3355 ap->state = ANEG_STATE_AN_ENABLE;
3356
3357 /* fallthru */
3358 case ANEG_STATE_AN_ENABLE:
3359 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3360 if (ap->flags & MR_AN_ENABLE) {
3361 ap->link_time = 0;
3362 ap->cur_time = 0;
3363 ap->ability_match_cfg = 0;
3364 ap->ability_match_count = 0;
3365 ap->ability_match = 0;
3366 ap->idle_match = 0;
3367 ap->ack_match = 0;
3368
3369 ap->state = ANEG_STATE_RESTART_INIT;
3370 } else {
3371 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3372 }
3373 break;
3374
3375 case ANEG_STATE_RESTART_INIT:
3376 ap->link_time = ap->cur_time;
3377 ap->flags &= ~(MR_NP_LOADED);
3378 ap->txconfig = 0;
3379 tw32(MAC_TX_AUTO_NEG, 0);
3380 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3381 tw32_f(MAC_MODE, tp->mac_mode);
3382 udelay(40);
3383
3384 ret = ANEG_TIMER_ENAB;
3385 ap->state = ANEG_STATE_RESTART;
3386
3387 /* fallthru */
3388 case ANEG_STATE_RESTART:
3389 delta = ap->cur_time - ap->link_time;
3390 if (delta > ANEG_STATE_SETTLE_TIME) {
3391 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3392 } else {
3393 ret = ANEG_TIMER_ENAB;
3394 }
3395 break;
3396
3397 case ANEG_STATE_DISABLE_LINK_OK:
3398 ret = ANEG_DONE;
3399 break;
3400
3401 case ANEG_STATE_ABILITY_DETECT_INIT:
3402 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3403 ap->txconfig = ANEG_CFG_FD;
3404 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3405 if (flowctrl & ADVERTISE_1000XPAUSE)
3406 ap->txconfig |= ANEG_CFG_PS1;
3407 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3408 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3409 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3410 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3411 tw32_f(MAC_MODE, tp->mac_mode);
3412 udelay(40);
3413
3414 ap->state = ANEG_STATE_ABILITY_DETECT;
3415 break;
3416
3417 case ANEG_STATE_ABILITY_DETECT:
3418 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3419 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3420 }
3421 break;
3422
3423 case ANEG_STATE_ACK_DETECT_INIT:
3424 ap->txconfig |= ANEG_CFG_ACK;
3425 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3426 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3427 tw32_f(MAC_MODE, tp->mac_mode);
3428 udelay(40);
3429
3430 ap->state = ANEG_STATE_ACK_DETECT;
3431
3432 /* fallthru */
3433 case ANEG_STATE_ACK_DETECT:
3434 if (ap->ack_match != 0) {
3435 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3436 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3437 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3438 } else {
3439 ap->state = ANEG_STATE_AN_ENABLE;
3440 }
3441 } else if (ap->ability_match != 0 &&
3442 ap->rxconfig == 0) {
3443 ap->state = ANEG_STATE_AN_ENABLE;
3444 }
3445 break;
3446
3447 case ANEG_STATE_COMPLETE_ACK_INIT:
3448 if (ap->rxconfig & ANEG_CFG_INVAL) {
3449 ret = ANEG_FAILED;
3450 break;
3451 }
3452 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3453 MR_LP_ADV_HALF_DUPLEX |
3454 MR_LP_ADV_SYM_PAUSE |
3455 MR_LP_ADV_ASYM_PAUSE |
3456 MR_LP_ADV_REMOTE_FAULT1 |
3457 MR_LP_ADV_REMOTE_FAULT2 |
3458 MR_LP_ADV_NEXT_PAGE |
3459 MR_TOGGLE_RX |
3460 MR_NP_RX);
3461 if (ap->rxconfig & ANEG_CFG_FD)
3462 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3463 if (ap->rxconfig & ANEG_CFG_HD)
3464 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3465 if (ap->rxconfig & ANEG_CFG_PS1)
3466 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3467 if (ap->rxconfig & ANEG_CFG_PS2)
3468 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3469 if (ap->rxconfig & ANEG_CFG_RF1)
3470 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3471 if (ap->rxconfig & ANEG_CFG_RF2)
3472 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3473 if (ap->rxconfig & ANEG_CFG_NP)
3474 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3475
3476 ap->link_time = ap->cur_time;
3477
3478 ap->flags ^= (MR_TOGGLE_TX);
3479 if (ap->rxconfig & 0x0008)
3480 ap->flags |= MR_TOGGLE_RX;
3481 if (ap->rxconfig & ANEG_CFG_NP)
3482 ap->flags |= MR_NP_RX;
3483 ap->flags |= MR_PAGE_RX;
3484
3485 ap->state = ANEG_STATE_COMPLETE_ACK;
3486 ret = ANEG_TIMER_ENAB;
3487 break;
3488
3489 case ANEG_STATE_COMPLETE_ACK:
3490 if (ap->ability_match != 0 &&
3491 ap->rxconfig == 0) {
3492 ap->state = ANEG_STATE_AN_ENABLE;
3493 break;
3494 }
3495 delta = ap->cur_time - ap->link_time;
3496 if (delta > ANEG_STATE_SETTLE_TIME) {
3497 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3498 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3499 } else {
3500 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3501 !(ap->flags & MR_NP_RX)) {
3502 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3503 } else {
3504 ret = ANEG_FAILED;
3505 }
3506 }
3507 }
3508 break;
3509
3510 case ANEG_STATE_IDLE_DETECT_INIT:
3511 ap->link_time = ap->cur_time;
3512 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3513 tw32_f(MAC_MODE, tp->mac_mode);
3514 udelay(40);
3515
3516 ap->state = ANEG_STATE_IDLE_DETECT;
3517 ret = ANEG_TIMER_ENAB;
3518 break;
3519
3520 case ANEG_STATE_IDLE_DETECT:
3521 if (ap->ability_match != 0 &&
3522 ap->rxconfig == 0) {
3523 ap->state = ANEG_STATE_AN_ENABLE;
3524 break;
3525 }
3526 delta = ap->cur_time - ap->link_time;
3527 if (delta > ANEG_STATE_SETTLE_TIME) {
3528 /* XXX another gem from the Broadcom driver :( */
3529 ap->state = ANEG_STATE_LINK_OK;
3530 }
3531 break;
3532
3533 case ANEG_STATE_LINK_OK:
3534 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3535 ret = ANEG_DONE;
3536 break;
3537
3538 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3539 /* ??? unimplemented */
3540 break;
3541
3542 case ANEG_STATE_NEXT_PAGE_WAIT:
3543 /* ??? unimplemented */
3544 break;
3545
3546 default:
3547 ret = ANEG_FAILED;
3548 break;
855e1111 3549 }
1da177e4
LT		 3550
3551 return ret;
3552}
3553
5be73b47 3554static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3555{
3556 int res = 0;
3557 struct tg3_fiber_aneginfo aninfo;
3558 int status = ANEG_FAILED;
3559 unsigned int tick;
3560 u32 tmp;
3561
3562 tw32_f(MAC_TX_AUTO_NEG, 0);
3563
3564 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3565 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3566 udelay(40);
3567
3568 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3569 udelay(40);
3570
3571 memset(&aninfo, 0, sizeof(aninfo));
3572 aninfo.flags |= MR_AN_ENABLE;
3573 aninfo.state = ANEG_STATE_UNKNOWN;
3574 aninfo.cur_time = 0;
3575 tick = 0;
3576 while (++tick < 195000) {
3577 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3578 if (status == ANEG_DONE || status == ANEG_FAILED)
3579 break;
3580
3581 udelay(1);
3582 }
3583
3584 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3585 tw32_f(MAC_MODE, tp->mac_mode);
3586 udelay(40);
3587
5be73b47
MC		 3588 *txflags = aninfo.txconfig;
3589 *rxflags = aninfo.flags;
1da177e4
LT		 3590
3591 if (status == ANEG_DONE &&
3592 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3593 MR_LP_ADV_FULL_DUPLEX)))
3594 res = 1;
3595
3596 return res;
3597}
3598
3599static void tg3_init_bcm8002(struct tg3 *tp)
3600{
3601 u32 mac_status = tr32(MAC_STATUS);
3602 int i;
3603
3604 /* Reset when initting first time or we have a link. */
3605 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3606 !(mac_status & MAC_STATUS_PCS_SYNCED))
3607 return;
3608
3609 /* Set PLL lock range. */
3610 tg3_writephy(tp, 0x16, 0x8007);
3611
3612 /* SW reset */
3613 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3614
3615 /* Wait for reset to complete. */
3616 /* XXX schedule_timeout() ... */
3617 for (i = 0; i < 500; i++)
3618 udelay(10);
3619
3620 /* Config mode; select PMA/Ch 1 regs. */
3621 tg3_writephy(tp, 0x10, 0x8411);
3622
3623 /* Enable auto-lock and comdet, select txclk for tx. */
3624 tg3_writephy(tp, 0x11, 0x0a10);
3625
3626 tg3_writephy(tp, 0x18, 0x00a0);
3627 tg3_writephy(tp, 0x16, 0x41ff);
3628
3629 /* Assert and deassert POR. */
3630 tg3_writephy(tp, 0x13, 0x0400);
3631 udelay(40);
3632 tg3_writephy(tp, 0x13, 0x0000);
3633
3634 tg3_writephy(tp, 0x11, 0x0a50);
3635 udelay(40);
3636 tg3_writephy(tp, 0x11, 0x0a10);
3637
3638 /* Wait for signal to stabilize */
3639 /* XXX schedule_timeout() ... */
3640 for (i = 0; i < 15000; i++)
3641 udelay(10);
3642
3643 /* Deselect the channel register so we can read the PHYID
3644 * later.
3645 */
3646 tg3_writephy(tp, 0x10, 0x8011);
3647}
3648
3649static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3650{
82cd3d11 3651 u16 flowctrl;
1da177e4
LT		 3652 u32 sg_dig_ctrl, sg_dig_status;
3653 u32 serdes_cfg, expected_sg_dig_ctrl;
3654 int workaround, port_a;
3655 int current_link_up;
3656
3657 serdes_cfg = 0;
3658 expected_sg_dig_ctrl = 0;
3659 workaround = 0;
3660 port_a = 1;
3661 current_link_up = 0;
3662
3663 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3664 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3665 workaround = 1;
3666 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3667 port_a = 0;
3668
3669 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3670 /* preserve bits 20-23 for voltage regulator */
3671 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3672 }
3673
3674 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3675
3676 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3677 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3678 if (workaround) {
3679 u32 val = serdes_cfg;
3680
3681 if (port_a)
3682 val |= 0xc010000;
3683 else
3684 val |= 0x4010000;
3685 tw32_f(MAC_SERDES_CFG, val);
3686 }
c98f6e3b
MC		 3687
3688 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3689 }
3690 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3691 tg3_setup_flow_control(tp, 0, 0);
3692 current_link_up = 1;
3693 }
3694 goto out;
3695 }
3696
3697 /* Want auto-negotiation. */
c98f6e3b 3698 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3699
82cd3d11
MC		 3700 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3701 if (flowctrl & ADVERTISE_1000XPAUSE)
3702 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3703 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3704 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3705
3706 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3707 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3708 tp->serdes_counter &&
3709 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3710 MAC_STATUS_RCVD_CFG)) ==
3711 MAC_STATUS_PCS_SYNCED)) {
3712 tp->serdes_counter--;
3713 current_link_up = 1;
3714 goto out;
3715 }
3716restart_autoneg:
1da177e4
LT		 3717 if (workaround)
3718 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3719 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3720 udelay(5);
3721 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3722
3d3ebe74
MC		 3723 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3724 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3725 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3726 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3727 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3728 mac_status = tr32(MAC_STATUS);
3729
c98f6e3b 3730 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3731 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3732 u32 local_adv = 0, remote_adv = 0;
3733
3734 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3735 local_adv |= ADVERTISE_1000XPAUSE;
3736 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3737 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3738
c98f6e3b 3739 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3740 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3741 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3742 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3743
3744 tg3_setup_flow_control(tp, local_adv, remote_adv);
3745 current_link_up = 1;
3d3ebe74
MC		 3746 tp->serdes_counter = 0;
3747 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3748 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3749 if (tp->serdes_counter)
3750 tp->serdes_counter--;
1da177e4
LT		 3751 else {
3752 if (workaround) {
3753 u32 val = serdes_cfg;
3754
3755 if (port_a)
3756 val |= 0xc010000;
3757 else
3758 val |= 0x4010000;
3759
3760 tw32_f(MAC_SERDES_CFG, val);
3761 }
3762
c98f6e3b 3763 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3764 udelay(40);
3765
3766 /* Link parallel detection - link is up */
3767 /* only if we have PCS_SYNC and not */
3768 /* receiving config code words */
3769 mac_status = tr32(MAC_STATUS);
3770 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3771 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3772 tg3_setup_flow_control(tp, 0, 0);
3773 current_link_up = 1;
3d3ebe74
MC		 3774 tp->tg3_flags2 |=
3775 TG3_FLG2_PARALLEL_DETECT;
3776 tp->serdes_counter =
3777 SERDES_PARALLEL_DET_TIMEOUT;
3778 } else
3779 goto restart_autoneg;
1da177e4
LT		 3780 }
3781 }
3d3ebe74
MC		 3782 } else {
3783 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3784 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3785 }
3786
3787out:
3788 return current_link_up;
3789}
3790
3791static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3792{
3793 int current_link_up = 0;
3794
5cf64b8a 3795 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3796 goto out;
1da177e4
LT		 3797
3798 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3799 u32 txflags, rxflags;
1da177e4 3800 int i;
6aa20a22 3801
5be73b47
MC		 3802 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3803 u32 local_adv = 0, remote_adv = 0;
1da177e4 3804
5be73b47
MC		 3805 if (txflags & ANEG_CFG_PS1)
3806 local_adv |= ADVERTISE_1000XPAUSE;
3807 if (txflags & ANEG_CFG_PS2)
3808 local_adv |= ADVERTISE_1000XPSE_ASYM;
3809
3810 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE;
3812 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3813 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3814
3815 tg3_setup_flow_control(tp, local_adv, remote_adv);
3816
1da177e4
LT		 3817 current_link_up = 1;
3818 }
3819 for (i = 0; i < 30; i++) {
3820 udelay(20);
3821 tw32_f(MAC_STATUS,
3822 (MAC_STATUS_SYNC_CHANGED |
3823 MAC_STATUS_CFG_CHANGED));
3824 udelay(40);
3825 if ((tr32(MAC_STATUS) &
3826 (MAC_STATUS_SYNC_CHANGED |
3827 MAC_STATUS_CFG_CHANGED)) == 0)
3828 break;
3829 }
3830
3831 mac_status = tr32(MAC_STATUS);
3832 if (current_link_up == 0 &&
3833 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG))
3835 current_link_up = 1;
3836 } else {
5be73b47
MC		 3837 tg3_setup_flow_control(tp, 0, 0);
3838
1da177e4
LT		 3839 /* Forcing 1000FD link up. */
3840 current_link_up = 1;
1da177e4
LT		 3841
3842 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3843 udelay(40);
e8f3f6ca
MC		 3844
3845 tw32_f(MAC_MODE, tp->mac_mode);
3846 udelay(40);
1da177e4
LT		 3847 }
3848
3849out:
3850 return current_link_up;
3851}
3852
3853static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3854{
3855 u32 orig_pause_cfg;
3856 u16 orig_active_speed;
3857 u8 orig_active_duplex;
3858 u32 mac_status;
3859 int current_link_up;
3860 int i;
3861
8d018621 3862 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3863 orig_active_speed = tp->link_config.active_speed;
3864 orig_active_duplex = tp->link_config.active_duplex;
3865
3866 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3867 netif_carrier_ok(tp->dev) &&
3868 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3869 mac_status = tr32(MAC_STATUS);
3870 mac_status &= (MAC_STATUS_PCS_SYNCED |
3871 MAC_STATUS_SIGNAL_DET |
3872 MAC_STATUS_CFG_CHANGED |
3873 MAC_STATUS_RCVD_CFG);
3874 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3875 MAC_STATUS_SIGNAL_DET)) {
3876 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED));
3878 return 0;
3879 }
3880 }
3881
3882 tw32_f(MAC_TX_AUTO_NEG, 0);
3883
3884 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3885 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3886 tw32_f(MAC_MODE, tp->mac_mode);
3887 udelay(40);
3888
3889 if (tp->phy_id == PHY_ID_BCM8002)
3890 tg3_init_bcm8002(tp);
3891
3892 /* Enable link change event even when serdes polling. */
3893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3894 udelay(40);
3895
3896 current_link_up = 0;
3897 mac_status = tr32(MAC_STATUS);
3898
3899 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3900 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3901 else
3902 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3903
898a56f8 3904 tp->napi[0].hw_status->status =
1da177e4 3905 (SD_STATUS_UPDATED |
898a56f8 3906 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3907
3908 for (i = 0; i < 100; i++) {
3909 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3910 MAC_STATUS_CFG_CHANGED));
3911 udelay(5);
3912 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3913 MAC_STATUS_CFG_CHANGED |
3914 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3915 break;
3916 }
3917
3918 mac_status = tr32(MAC_STATUS);
3919 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3920 current_link_up = 0;
3d3ebe74
MC		 3921 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3922 tp->serdes_counter == 0) {
1da177e4
LT		 3923 tw32_f(MAC_MODE, (tp->mac_mode |
3924 MAC_MODE_SEND_CONFIGS));
3925 udelay(1);
3926 tw32_f(MAC_MODE, tp->mac_mode);
3927 }
3928 }
3929
3930 if (current_link_up == 1) {
3931 tp->link_config.active_speed = SPEED_1000;
3932 tp->link_config.active_duplex = DUPLEX_FULL;
3933 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3934 LED_CTRL_LNKLED_OVERRIDE |
3935 LED_CTRL_1000MBPS_ON));
3936 } else {
3937 tp->link_config.active_speed = SPEED_INVALID;
3938 tp->link_config.active_duplex = DUPLEX_INVALID;
3939 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3940 LED_CTRL_LNKLED_OVERRIDE |
3941 LED_CTRL_TRAFFIC_OVERRIDE));
3942 }
3943
3944 if (current_link_up != netif_carrier_ok(tp->dev)) {
3945 if (current_link_up)
3946 netif_carrier_on(tp->dev);
3947 else
3948 netif_carrier_off(tp->dev);
3949 tg3_link_report(tp);
3950 } else {
8d018621 3951 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3952 if (orig_pause_cfg != now_pause_cfg ||
3953 orig_active_speed != tp->link_config.active_speed ||
3954 orig_active_duplex != tp->link_config.active_duplex)
3955 tg3_link_report(tp);
3956 }
3957
3958 return 0;
3959}
3960
747e8f8b
MC		 3961static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3962{
3963 int current_link_up, err = 0;
3964 u32 bmsr, bmcr;
3965 u16 current_speed;
3966 u8 current_duplex;
ef167e27 3967 u32 local_adv, remote_adv;
747e8f8b
MC		 3968
3969 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3970 tw32_f(MAC_MODE, tp->mac_mode);
3971 udelay(40);
3972
3973 tw32(MAC_EVENT, 0);
3974
3975 tw32_f(MAC_STATUS,
3976 (MAC_STATUS_SYNC_CHANGED |
3977 MAC_STATUS_CFG_CHANGED |
3978 MAC_STATUS_MI_COMPLETION |
3979 MAC_STATUS_LNKSTATE_CHANGED));
3980 udelay(40);
3981
3982 if (force_reset)
3983 tg3_phy_reset(tp);
3984
3985 current_link_up = 0;
3986 current_speed = SPEED_INVALID;
3987 current_duplex = DUPLEX_INVALID;
3988
3989 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3990 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3992 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3993 bmsr |= BMSR_LSTATUS;
3994 else
3995 bmsr &= ~BMSR_LSTATUS;
3996 }
747e8f8b
MC		 3997
3998 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3999
4000 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4001 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4002 /* do nothing, just check for link up at the end */
4003 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4004 u32 adv, new_adv;
4005
4006 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4007 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4008 ADVERTISE_1000XPAUSE |
4009 ADVERTISE_1000XPSE_ASYM |
4010 ADVERTISE_SLCT);
4011
ba4d07a8 4012 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4013
4014 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4015 new_adv |= ADVERTISE_1000XHALF;
4016 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4017 new_adv |= ADVERTISE_1000XFULL;
4018
4019 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4020 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4021 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4022 tg3_writephy(tp, MII_BMCR, bmcr);
4023
4024 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4025 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4027
4028 return err;
4029 }
4030 } else {
4031 u32 new_bmcr;
4032
4033 bmcr &= ~BMCR_SPEED1000;
4034 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4035
4036 if (tp->link_config.duplex == DUPLEX_FULL)
4037 new_bmcr |= BMCR_FULLDPLX;
4038
4039 if (new_bmcr != bmcr) {
4040 /* BMCR_SPEED1000 is a reserved bit that needs
4041 * to be set on write.
4042 */
4043 new_bmcr |= BMCR_SPEED1000;
4044
4045 /* Force a linkdown */
4046 if (netif_carrier_ok(tp->dev)) {
4047 u32 adv;
4048
4049 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4050 adv &= ~(ADVERTISE_1000XFULL |
4051 ADVERTISE_1000XHALF |
4052 ADVERTISE_SLCT);
4053 tg3_writephy(tp, MII_ADVERTISE, adv);
4054 tg3_writephy(tp, MII_BMCR, bmcr |
4055 BMCR_ANRESTART |
4056 BMCR_ANENABLE);
4057 udelay(10);
4058 netif_carrier_off(tp->dev);
4059 }
4060 tg3_writephy(tp, MII_BMCR, new_bmcr);
4061 bmcr = new_bmcr;
4062 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4063 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4064 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4065 ASIC_REV_5714) {
4066 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4067 bmsr |= BMSR_LSTATUS;
4068 else
4069 bmsr &= ~BMSR_LSTATUS;
4070 }
747e8f8b
MC		 4071 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4072 }
4073 }
4074
4075 if (bmsr & BMSR_LSTATUS) {
4076 current_speed = SPEED_1000;
4077 current_link_up = 1;
4078 if (bmcr & BMCR_FULLDPLX)
4079 current_duplex = DUPLEX_FULL;
4080 else
4081 current_duplex = DUPLEX_HALF;
4082
ef167e27
MC		 4083 local_adv = 0;
4084 remote_adv = 0;
4085
747e8f8b 4086 if (bmcr & BMCR_ANENABLE) {
ef167e27 4087 u32 common;
747e8f8b
MC		 4088
4089 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4090 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4091 common = local_adv & remote_adv;
4092 if (common & (ADVERTISE_1000XHALF |
4093 ADVERTISE_1000XFULL)) {
4094 if (common & ADVERTISE_1000XFULL)
4095 current_duplex = DUPLEX_FULL;
4096 else
4097 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4098 }
4099 else
4100 current_link_up = 0;
4101 }
4102 }
4103
ef167e27
MC		 4104 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4105 tg3_setup_flow_control(tp, local_adv, remote_adv);
4106
747e8f8b
MC		 4107 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4108 if (tp->link_config.active_duplex == DUPLEX_HALF)
4109 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4110
4111 tw32_f(MAC_MODE, tp->mac_mode);
4112 udelay(40);
4113
4114 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4115
4116 tp->link_config.active_speed = current_speed;
4117 tp->link_config.active_duplex = current_duplex;
4118
4119 if (current_link_up != netif_carrier_ok(tp->dev)) {
4120 if (current_link_up)
4121 netif_carrier_on(tp->dev);
4122 else {
4123 netif_carrier_off(tp->dev);
4124 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4125 }
4126 tg3_link_report(tp);
4127 }
4128 return err;
4129}
4130
4131static void tg3_serdes_parallel_detect(struct tg3 *tp)
4132{
3d3ebe74 4133 if (tp->serdes_counter) {
747e8f8b 4134 /* Give autoneg time to complete. */
3d3ebe74 4135 tp->serdes_counter--;
747e8f8b
MC		 4136 return;
4137 }
4138 if (!netif_carrier_ok(tp->dev) &&
4139 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4140 u32 bmcr;
4141
4142 tg3_readphy(tp, MII_BMCR, &bmcr);
4143 if (bmcr & BMCR_ANENABLE) {
4144 u32 phy1, phy2;
4145
4146 /* Select shadow register 0x1f */
4147 tg3_writephy(tp, 0x1c, 0x7c00);
4148 tg3_readphy(tp, 0x1c, &phy1);
4149
4150 /* Select expansion interrupt status register */
4151 tg3_writephy(tp, 0x17, 0x0f01);
4152 tg3_readphy(tp, 0x15, &phy2);
4153 tg3_readphy(tp, 0x15, &phy2);
4154
4155 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4156 /* We have signal detect and not receiving
4157 * config code words, link is up by parallel
4158 * detection.
4159 */
4160
4161 bmcr &= ~BMCR_ANENABLE;
4162 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4163 tg3_writephy(tp, MII_BMCR, bmcr);
4164 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4165 }
4166 }
4167 }
4168 else if (netif_carrier_ok(tp->dev) &&
4169 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4170 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4171 u32 phy2;
4172
4173 /* Select expansion interrupt status register */
4174 tg3_writephy(tp, 0x17, 0x0f01);
4175 tg3_readphy(tp, 0x15, &phy2);
4176 if (phy2 & 0x20) {
4177 u32 bmcr;
4178
4179 /* Config code words received, turn on autoneg. */
4180 tg3_readphy(tp, MII_BMCR, &bmcr);
4181 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4182
4183 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4184
4185 }
4186 }
4187}
4188
1da177e4
LT		 4189static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4190{
4191 int err;
4192
4193 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4194 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4195 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4196 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4197 } else {
4198 err = tg3_setup_copper_phy(tp, force_reset);
4199 }
4200
bcb37f6c 4201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4202 u32 val, scale;
4203
4204 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4205 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4206 scale = 65;
4207 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4208 scale = 6;
4209 else
4210 scale = 12;
4211
4212 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4213 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4214 tw32(GRC_MISC_CFG, val);
4215 }
4216
1da177e4
LT		 4217 if (tp->link_config.active_speed == SPEED_1000 &&
4218 tp->link_config.active_duplex == DUPLEX_HALF)
4219 tw32(MAC_TX_LENGTHS,
4220 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4221 (6 << TX_LENGTHS_IPG_SHIFT) |
4222 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4223 else
4224 tw32(MAC_TX_LENGTHS,
4225 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4226 (6 << TX_LENGTHS_IPG_SHIFT) |
4227 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4228
4229 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4230 if (netif_carrier_ok(tp->dev)) {
4231 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4232 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4233 } else {
4234 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4235 }
4236 }
4237
8ed5d97e
MC		 4238 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4239 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4240 if (!netif_carrier_ok(tp->dev))
4241 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4242 tp->pwrmgmt_thresh;
4243 else
4244 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4245 tw32(PCIE_PWR_MGMT_THRESH, val);
4246 }
4247
1da177e4
LT		 4248 return err;
4249}
4250
df3e6548
MC		 4251/* This is called whenever we suspect that the system chipset is re-
4252 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4253 * is bogus tx completions. We try to recover by setting the
4254 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4255 * in the workqueue.
4256 */
4257static void tg3_tx_recover(struct tg3 *tp)
4258{
4259 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4260 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4261
4262 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4263 "mapped I/O cycles to the network device, attempting to "
4264 "recover. Please report the problem to the driver maintainer "
4265 "and include system chipset information.\n", tp->dev->name);
4266
4267 spin_lock(&tp->lock);
df3e6548 4268 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4269 spin_unlock(&tp->lock);
4270}
4271
f3f3f27e 4272static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4273{
4274 smp_mb();
f3f3f27e
MC		 4275 return tnapi->tx_pending -
4276 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4277}
4278
1da177e4
LT		 4279/* Tigon3 never reports partial packet sends. So we do not
4280 * need special logic to handle SKBs that have not had all
4281 * of their frags sent yet, like SunGEM does.
4282 */
17375d25 4283static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4284{
17375d25 4285 struct tg3 *tp = tnapi->tp;
898a56f8 4286 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4287 u32 sw_idx = tnapi->tx_cons;
1da177e4
LT		 4288
4289 while (sw_idx != hw_idx) {
f3f3f27e 4290 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4291 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4292 int i, tx_bug = 0;
4293
4294 if (unlikely(skb == NULL)) {
4295 tg3_tx_recover(tp);
4296 return;
4297 }
1da177e4 4298
90079ce8 4299 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4300
4301 ri->skb = NULL;
4302
4303 sw_idx = NEXT_TX(sw_idx);
4304
4305 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4306 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4307 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4308 tx_bug = 1;
1da177e4
LT		 4309 sw_idx = NEXT_TX(sw_idx);
4310 }
4311
f47c11ee 4312 dev_kfree_skb(skb);
df3e6548
MC		 4313
4314 if (unlikely(tx_bug)) {
4315 tg3_tx_recover(tp);
4316 return;
4317 }
1da177e4
LT		 4318 }
4319
f3f3f27e 4320 tnapi->tx_cons = sw_idx;
1da177e4 4321
1b2a7205
MC		 4322 /* Need to make the tx_cons update visible to tg3_start_xmit()
4323 * before checking for netif_queue_stopped(). Without the
4324 * memory barrier, there is a small possibility that tg3_start_xmit()
4325 * will miss it and cause the queue to be stopped forever.
4326 */
4327 smp_mb();
4328
4329 if (unlikely(netif_queue_stopped(tp->dev) &&
f3f3f27e 4330 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
1b2a7205 4331 netif_tx_lock(tp->dev);
51b91468 4332 if (netif_queue_stopped(tp->dev) &&
f3f3f27e 4333 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
51b91468 4334 netif_wake_queue(tp->dev);
1b2a7205 4335 netif_tx_unlock(tp->dev);
51b91468 4336 }
1da177e4
LT		 4337}
4338
4339/* Returns size of skb allocated or < 0 on error.
4340 *
4341 * We only need to fill in the address because the other members
4342 * of the RX descriptor are invariant, see tg3_init_rings.
4343 *
4344 * Note the purposeful assymetry of cpu vs. chip accesses. For
4345 * posting buffers we only dirty the first cache line of the RX
4346 * descriptor (containing the address). Whereas for the RX status
4347 * buffers the cpu only reads the last cacheline of the RX descriptor
4348 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4349 */
17375d25 4350static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4351 int src_idx, u32 dest_idx_unmasked)
4352{
17375d25 4353 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4354 struct tg3_rx_buffer_desc *desc;
4355 struct ring_info *map, *src_map;
4356 struct sk_buff *skb;
4357 dma_addr_t mapping;
4358 int skb_size, dest_idx;
21f581a5 4359 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4360
4361 src_map = NULL;
4362 switch (opaque_key) {
4363 case RXD_OPAQUE_RING_STD:
4364 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4365 desc = &tpr->rx_std[dest_idx];
4366 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4367 if (src_idx >= 0)
21f581a5 4368 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4369 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4370 break;
4371
4372 case RXD_OPAQUE_RING_JUMBO:
4373 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4374 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4375 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4376 if (src_idx >= 0)
21f581a5 4377 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4378 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4379 break;
4380
4381 default:
4382 return -EINVAL;
855e1111 4383 }
1da177e4
LT		 4384
4385 /* Do not overwrite any of the map or rp information
4386 * until we are sure we can commit to a new buffer.
4387 *
4388 * Callers depend upon this behavior and assume that
4389 * we leave everything unchanged if we fail.
4390 */
287be12e 4391 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4392 if (skb == NULL)
4393 return -ENOMEM;
4394
1da177e4
LT		 4395 skb_reserve(skb, tp->rx_offset);
4396
287be12e 4397 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4
LT		 4398 PCI_DMA_FROMDEVICE);
4399
4400 map->skb = skb;
4401 pci_unmap_addr_set(map, mapping, mapping);
4402
4403 if (src_map != NULL)
4404 src_map->skb = NULL;
4405
4406 desc->addr_hi = ((u64)mapping >> 32);
4407 desc->addr_lo = ((u64)mapping & 0xffffffff);
4408
4409 return skb_size;
4410}
4411
4412/* We only need to move over in the address because the other
4413 * members of the RX descriptor are invariant. See notes above
4414 * tg3_alloc_rx_skb for full details.
4415 */
17375d25 4416static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4417 int src_idx, u32 dest_idx_unmasked)
4418{
17375d25 4419 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4420 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4421 struct ring_info *src_map, *dest_map;
4422 int dest_idx;
21f581a5 4423 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4424
4425 switch (opaque_key) {
4426 case RXD_OPAQUE_RING_STD:
4427 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4428 dest_desc = &tpr->rx_std[dest_idx];
4429 dest_map = &tpr->rx_std_buffers[dest_idx];
4430 src_desc = &tpr->rx_std[src_idx];
4431 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4432 break;
4433
4434 case RXD_OPAQUE_RING_JUMBO:
4435 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4436 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4437 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4438 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4439 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4440 break;
4441
4442 default:
4443 return;
855e1111 4444 }
1da177e4
LT		 4445
4446 dest_map->skb = src_map->skb;
4447 pci_unmap_addr_set(dest_map, mapping,
4448 pci_unmap_addr(src_map, mapping));
4449 dest_desc->addr_hi = src_desc->addr_hi;
4450 dest_desc->addr_lo = src_desc->addr_lo;
4451
4452 src_map->skb = NULL;
4453}
4454
1da177e4
LT		 4455/* The RX ring scheme is composed of multiple rings which post fresh
4456 * buffers to the chip, and one special ring the chip uses to report
4457 * status back to the host.
4458 *
4459 * The special ring reports the status of received packets to the
4460 * host. The chip does not write into the original descriptor the
4461 * RX buffer was obtained from. The chip simply takes the original
4462 * descriptor as provided by the host, updates the status and length
4463 * field, then writes this into the next status ring entry.
4464 *
4465 * Each ring the host uses to post buffers to the chip is described
4466 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4467 * it is first placed into the on-chip ram. When the packet's length
4468 * is known, it walks down the TG3_BDINFO entries to select the ring.
4469 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4470 * which is within the range of the new packet's length is chosen.
4471 *
4472 * The "separate ring for rx status" scheme may sound queer, but it makes
4473 * sense from a cache coherency perspective. If only the host writes
4474 * to the buffer post rings, and only the chip writes to the rx status
4475 * rings, then cache lines never move beyond shared-modified state.
4476 * If both the host and chip were to write into the same ring, cache line
4477 * eviction could occur since both entities want it in an exclusive state.
4478 */
17375d25 4479static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4480{
17375d25 4481 struct tg3 *tp = tnapi->tp;
f92905de 4482 u32 work_mask, rx_std_posted = 0;
72334482 4483 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4484 u16 hw_idx;
1da177e4 4485 int received;
21f581a5 4486 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4487
898a56f8 4488 hw_idx = tnapi->hw_status->idx[0].rx_producer;
1da177e4
LT		 4489 /*
4490 * We need to order the read of hw_idx and the read of
4491 * the opaque cookie.
4492 */
4493 rmb();
1da177e4
LT		 4494 work_mask = 0;
4495 received = 0;
4496 while (sw_idx != hw_idx && budget > 0) {
72334482 4497 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4498 unsigned int len;
4499 struct sk_buff *skb;
4500 dma_addr_t dma_addr;
4501 u32 opaque_key, desc_idx, *post_ptr;
4502
4503 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4504 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4505 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4506 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4507 dma_addr = pci_unmap_addr(ri, mapping);
4508 skb = ri->skb;
4509 post_ptr = &tpr->rx_std_ptr;
f92905de 4510 rx_std_posted++;
1da177e4 4511 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4512 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4513 dma_addr = pci_unmap_addr(ri, mapping);
4514 skb = ri->skb;
4515 post_ptr = &tpr->rx_jmb_ptr;
4516 } else
1da177e4 4517 goto next_pkt_nopost;
1da177e4
LT		 4518
4519 work_mask |= opaque_key;
4520
4521 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4522 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4523 drop_it:
17375d25 4524 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4525 desc_idx, *post_ptr);
4526 drop_it_no_recycle:
4527 /* Other statistics kept track of by card. */
4528 tp->net_stats.rx_dropped++;
4529 goto next_pkt;
4530 }
4531
ad829268
MC		 4532 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4533 ETH_FCS_LEN;
1da177e4 4534
6aa20a22 4535 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4536 && tp->rx_offset == NET_IP_ALIGN
4537 /* rx_offset will likely not equal NET_IP_ALIGN
4538 * if this is a 5701 card running in PCI-X mode
4539 * [see tg3_get_invariants()]
4540 */
1da177e4
LT		 4541 ) {
4542 int skb_size;
4543
17375d25 4544 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4545 desc_idx, *post_ptr);
4546 if (skb_size < 0)
4547 goto drop_it;
4548
287be12e 4549 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4550 PCI_DMA_FROMDEVICE);
4551
4552 skb_put(skb, len);
4553 } else {
4554 struct sk_buff *copy_skb;
4555
17375d25 4556 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4557 desc_idx, *post_ptr);
4558
ad829268
MC		 4559 copy_skb = netdev_alloc_skb(tp->dev,
4560 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4561 if (copy_skb == NULL)
4562 goto drop_it_no_recycle;
4563
ad829268 4564 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4565 skb_put(copy_skb, len);
4566 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4567 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4568 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4569
4570 /* We'll reuse the original ring buffer. */
4571 skb = copy_skb;
4572 }
4573
4574 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4575 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4576 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4577 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4578 skb->ip_summed = CHECKSUM_UNNECESSARY;
4579 else
4580 skb->ip_summed = CHECKSUM_NONE;
4581
4582 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4583
4584 if (len > (tp->dev->mtu + ETH_HLEN) &&
4585 skb->protocol != htons(ETH_P_8021Q)) {
4586 dev_kfree_skb(skb);
4587 goto next_pkt;
4588 }
4589
1da177e4
LT		 4590#if TG3_VLAN_TAG_USED
4591 if (tp->vlgrp != NULL &&
4592 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4593 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4594 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4595 } else
4596#endif
17375d25 4597 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4598
1da177e4
LT		 4599 received++;
4600 budget--;
4601
4602next_pkt:
4603 (*post_ptr)++;
f92905de
MC		 4604
4605 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4606 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4607
4608 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4609 TG3_64BIT_REG_LOW, idx);
4610 work_mask &= ~RXD_OPAQUE_RING_STD;
4611 rx_std_posted = 0;
4612 }
1da177e4 4613next_pkt_nopost:
483ba50b 4614 sw_idx++;
6b31a515 4615 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4616
4617 /* Refresh hw_idx to see if there is new work */
4618 if (sw_idx == hw_idx) {
898a56f8 4619 hw_idx = tnapi->hw_status->idx[0].rx_producer;
52f6d697
MC		 4620 rmb();
4621 }
1da177e4
LT		 4622 }
4623
4624 /* ACK the status ring. */
72334482
MC		 4625 tnapi->rx_rcb_ptr = sw_idx;
4626 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4627
4628 /* Refill RX ring(s). */
4629 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4630 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4631 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4632 sw_idx);
4633 }
4634 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4635 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4636 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4637 sw_idx);
4638 }
4639 mmiowb();
4640
4641 return received;
4642}
4643
17375d25 4644static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4645{
17375d25 4646 struct tg3 *tp = tnapi->tp;
898a56f8 4647 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4648
1da177e4
LT		 4649 /* handle link change and other phy events */
4650 if (!(tp->tg3_flags &
4651 (TG3_FLAG_USE_LINKCHG_REG |
4652 TG3_FLAG_POLL_SERDES))) {
4653 if (sblk->status & SD_STATUS_LINK_CHG) {
4654 sblk->status = SD_STATUS_UPDATED |
4655 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4656 spin_lock(&tp->lock);
dd477003
MC		 4657 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4658 tw32_f(MAC_STATUS,
4659 (MAC_STATUS_SYNC_CHANGED |
4660 MAC_STATUS_CFG_CHANGED |
4661 MAC_STATUS_MI_COMPLETION |
4662 MAC_STATUS_LNKSTATE_CHANGED));
4663 udelay(40);
4664 } else
4665 tg3_setup_phy(tp, 0);
f47c11ee 4666 spin_unlock(&tp->lock);
1da177e4
LT		 4667 }
4668 }
4669
4670 /* run TX completion thread */
f3f3f27e 4671 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4672 tg3_tx(tnapi);
6f535763 4673 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4674 return work_done;
1da177e4
LT		 4675 }
4676
1da177e4
LT		 4677 /* run RX thread, within the bounds set by NAPI.
4678 * All RX "locking" is done by ensuring outside
bea3348e 4679 * code synchronizes with tg3->napi.poll()
1da177e4 4680 */
72334482 4681 if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
17375d25 4682 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4683
6f535763
DM		 4684 return work_done;
4685}
4686
4687static int tg3_poll(struct napi_struct *napi, int budget)
4688{
8ef0442f
MC		 4689 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4690 struct tg3 *tp = tnapi->tp;
6f535763 4691 int work_done = 0;
898a56f8 4692 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4693
4694 while (1) {
17375d25 4695 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4696
4697 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4698 goto tx_recovery;
4699
4700 if (unlikely(work_done >= budget))
4701 break;
4702
4fd7ab59 4703 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4704 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4705 * to tell the hw how much work has been processed,
4706 * so we must read it before checking for more work.
4707 */
898a56f8
MC		 4708 tnapi->last_tag = sblk->status_tag;
4709 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4710 rmb();
4711 } else
4712 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4713
17375d25 4714 if (likely(!tg3_has_work(tnapi))) {
288379f0 4715 napi_complete(napi);
17375d25 4716 tg3_int_reenable(tnapi);
6f535763
DM		 4717 break;
4718 }
1da177e4
LT		 4719 }
4720
bea3348e 4721 return work_done;
6f535763
DM		 4722
4723tx_recovery:
4fd7ab59 4724 /* work_done is guaranteed to be less than budget. */
288379f0 4725 napi_complete(napi);
6f535763 4726 schedule_work(&tp->reset_task);
4fd7ab59 4727 return work_done;
1da177e4
LT		 4728}
4729
f47c11ee
DM		 4730static void tg3_irq_quiesce(struct tg3 *tp)
4731{
4732 BUG_ON(tp->irq_sync);
4733
4734 tp->irq_sync = 1;
4735 smp_mb();
4736
4737 synchronize_irq(tp->pdev->irq);
4738}
4739
4740static inline int tg3_irq_sync(struct tg3 *tp)
4741{
4742 return tp->irq_sync;
4743}
4744
4745/* Fully shutdown all tg3 driver activity elsewhere in the system.
4746 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4747 * with as well. Most of the time, this is not necessary except when
4748 * shutting down the device.
4749 */
4750static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4751{
46966545 4752 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4753 if (irq_sync)
4754 tg3_irq_quiesce(tp);
f47c11ee
DM		 4755}
4756
4757static inline void tg3_full_unlock(struct tg3 *tp)
4758{
f47c11ee
DM		 4759 spin_unlock_bh(&tp->lock);
4760}
4761
fcfa0a32
MC		 4762/* One-shot MSI handler - Chip automatically disables interrupt
4763 * after sending MSI so driver doesn't have to do it.
4764 */
7d12e780 4765static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4766{
09943a18
MC		 4767 struct tg3_napi *tnapi = dev_id;
4768 struct tg3 *tp = tnapi->tp;
fcfa0a32 4769
898a56f8 4770 prefetch(tnapi->hw_status);
72334482 4771 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4772
4773 if (likely(!tg3_irq_sync(tp)))
09943a18 4774 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4775
4776 return IRQ_HANDLED;
4777}
4778
88b06bc2
MC		 4779/* MSI ISR - No need to check for interrupt sharing and no need to
4780 * flush status block and interrupt mailbox. PCI ordering rules
4781 * guarantee that MSI will arrive after the status block.
4782 */
7d12e780 4783static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4784{
09943a18
MC		 4785 struct tg3_napi *tnapi = dev_id;
4786 struct tg3 *tp = tnapi->tp;
88b06bc2 4787
898a56f8 4788 prefetch(tnapi->hw_status);
72334482 4789 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4790 /*
fac9b83e 4791 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4792 * chip-internal interrupt pending events.
fac9b83e 4793 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4794 * NIC to stop sending us irqs, engaging "in-intr-handler"
4795 * event coalescing.
4796 */
4797 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4798 if (likely(!tg3_irq_sync(tp)))
09943a18 4799 napi_schedule(&tnapi->napi);
61487480 4800
88b06bc2
MC		 4801 return IRQ_RETVAL(1);
4802}
4803
7d12e780 4804static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4805{
09943a18
MC		 4806 struct tg3_napi *tnapi = dev_id;
4807 struct tg3 *tp = tnapi->tp;
898a56f8 4808 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4809 unsigned int handled = 1;
4810
1da177e4
LT		 4811 /* In INTx mode, it is possible for the interrupt to arrive at
4812 * the CPU before the status block posted prior to the interrupt.
4813 * Reading the PCI State register will confirm whether the
4814 * interrupt is ours and will flush the status block.
4815 */
d18edcb2
MC		 4816 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4817 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4818 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4819 handled = 0;
f47c11ee 4820 goto out;
fac9b83e 4821 }
d18edcb2
MC		 4822 }
4823
4824 /*
4825 * Writing any value to intr-mbox-0 clears PCI INTA# and
4826 * chip-internal interrupt pending events.
4827 * Writing non-zero to intr-mbox-0 additional tells the
4828 * NIC to stop sending us irqs, engaging "in-intr-handler"
4829 * event coalescing.
c04cb347
MC		 4830 *
4831 * Flush the mailbox to de-assert the IRQ immediately to prevent
4832 * spurious interrupts. The flush impacts performance but
4833 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4834 */
c04cb347 4835 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4836 if (tg3_irq_sync(tp))
4837 goto out;
4838 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4839 if (likely(tg3_has_work(tnapi))) {
72334482 4840 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4841 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4842 } else {
4843 /* No work, shared interrupt perhaps? re-enable
4844 * interrupts, and flush that PCI write
4845 */
4846 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4847 0x00000000);
fac9b83e 4848 }
f47c11ee 4849out:
fac9b83e
DM		 4850 return IRQ_RETVAL(handled);
4851}
4852
7d12e780 4853static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4854{
09943a18
MC		 4855 struct tg3_napi *tnapi = dev_id;
4856 struct tg3 *tp = tnapi->tp;
898a56f8 4857 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4858 unsigned int handled = 1;
4859
fac9b83e
DM		 4860 /* In INTx mode, it is possible for the interrupt to arrive at
4861 * the CPU before the status block posted prior to the interrupt.
4862 * Reading the PCI State register will confirm whether the
4863 * interrupt is ours and will flush the status block.
4864 */
898a56f8 4865 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4866 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4867 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4868 handled = 0;
f47c11ee 4869 goto out;
1da177e4 4870 }
d18edcb2
MC		 4871 }
4872
4873 /*
4874 * writing any value to intr-mbox-0 clears PCI INTA# and
4875 * chip-internal interrupt pending events.
4876 * writing non-zero to intr-mbox-0 additional tells the
4877 * NIC to stop sending us irqs, engaging "in-intr-handler"
4878 * event coalescing.
c04cb347
MC		 4879 *
4880 * Flush the mailbox to de-assert the IRQ immediately to prevent
4881 * spurious interrupts. The flush impacts performance but
4882 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4883 */
c04cb347 4884 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4885
4886 /*
4887 * In a shared interrupt configuration, sometimes other devices'
4888 * interrupts will scream. We record the current status tag here
4889 * so that the above check can report that the screaming interrupts
4890 * are unhandled. Eventually they will be silenced.
4891 */
898a56f8 4892 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4893
d18edcb2
MC		 4894 if (tg3_irq_sync(tp))
4895 goto out;
624f8e50 4896
72334482 4897 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4898
09943a18 4899 napi_schedule(&tnapi->napi);
624f8e50 4900
f47c11ee 4901out:
1da177e4
LT		 4902 return IRQ_RETVAL(handled);
4903}
4904
7938109f 4905/* ISR for interrupt test */
7d12e780 4906static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4907{
09943a18
MC		 4908 struct tg3_napi *tnapi = dev_id;
4909 struct tg3 *tp = tnapi->tp;
898a56f8 4910 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4911
f9804ddb
MC		 4912 if ((sblk->status & SD_STATUS_UPDATED) ||
4913 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4914 tg3_disable_ints(tp);
7938109f
MC		 4915 return IRQ_RETVAL(1);
4916 }
4917 return IRQ_RETVAL(0);
4918}
4919
8e7a22e3 4920static int tg3_init_hw(struct tg3 *, int);
944d980e 4921static int tg3_halt(struct tg3 *, int, int);
1da177e4 4922
b9ec6c1b
MC		 4923/* Restart hardware after configuration changes, self-test, etc.
4924 * Invoked with tp->lock held.
4925 */
4926static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4927 __releases(tp->lock)
4928 __acquires(tp->lock)
b9ec6c1b
MC		 4929{
4930 int err;
4931
4932 err = tg3_init_hw(tp, reset_phy);
4933 if (err) {
4934 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4935 "aborting.\n", tp->dev->name);
4936 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4937 tg3_full_unlock(tp);
4938 del_timer_sync(&tp->timer);
4939 tp->irq_sync = 0;
8ef0442f 4940 napi_enable(&tp->napi[0].napi);
b9ec6c1b
MC		 4941 dev_close(tp->dev);
4942 tg3_full_lock(tp, 0);
4943 }
4944 return err;
4945}
4946
1da177e4
LT		 4947#ifdef CONFIG_NET_POLL_CONTROLLER
4948static void tg3_poll_controller(struct net_device *dev)
4949{
88b06bc2
MC		 4950 struct tg3 *tp = netdev_priv(dev);
4951
7d12e780 4952 tg3_interrupt(tp->pdev->irq, dev);
1da177e4
LT		 4953}
4954#endif
4955
c4028958 4956static void tg3_reset_task(struct work_struct *work)
1da177e4 4957{
c4028958 4958 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4959 int err;
1da177e4
LT		 4960 unsigned int restart_timer;
4961
7faa006f 4962 tg3_full_lock(tp, 0);
7faa006f
MC		 4963
4964 if (!netif_running(tp->dev)) {
7faa006f
MC		 4965 tg3_full_unlock(tp);
4966 return;
4967 }
4968
4969 tg3_full_unlock(tp);
4970
b02fd9e3
MC		 4971 tg3_phy_stop(tp);
4972
1da177e4
LT		 4973 tg3_netif_stop(tp);
4974
f47c11ee 4975 tg3_full_lock(tp, 1);
1da177e4
LT		 4976
4977 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4978 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4979
df3e6548
MC		 4980 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4981 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4982 tp->write32_rx_mbox = tg3_write_flush_reg32;
4983 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4984 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4985 }
4986
944d980e 4987 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4988 err = tg3_init_hw(tp, 1);
4989 if (err)
b9ec6c1b 4990 goto out;
1da177e4
LT		 4991
4992 tg3_netif_start(tp);
4993
1da177e4
LT		 4994 if (restart_timer)
4995 mod_timer(&tp->timer, jiffies + 1);
7faa006f 4996
b9ec6c1b 4997out:
7faa006f 4998 tg3_full_unlock(tp);
b02fd9e3
MC		 4999
5000 if (!err)
5001 tg3_phy_start(tp);
1da177e4
LT		 5002}
5003
b0408751
MC		 5004static void tg3_dump_short_state(struct tg3 *tp)
5005{
5006 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5007 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5008 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5009 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5010}
5011
1da177e4
LT		 5012static void tg3_tx_timeout(struct net_device *dev)
5013{
5014 struct tg3 *tp = netdev_priv(dev);
5015
b0408751 5016 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5017 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5018 dev->name);
b0408751
MC		 5019 tg3_dump_short_state(tp);
5020 }
1da177e4
LT		 5021
5022 schedule_work(&tp->reset_task);
5023}
5024
c58ec932
MC		 5025/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5026static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5027{
5028 u32 base = (u32) mapping & 0xffffffff;
5029
5030 return ((base > 0xffffdcc0) &&
5031 (base + len + 8 < base));
5032}
5033
72f2afb8
MC		 5034/* Test for DMA addresses > 40-bit */
5035static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5036 int len)
5037{
5038#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5039 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5040 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5041 return 0;
5042#else
5043 return 0;
5044#endif
5045}
5046
f3f3f27e 5047static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5048
72f2afb8
MC		 5049/* Workaround 4GB and 40-bit hardware DMA bugs. */
5050static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5051 u32 last_plus_one, u32 *start,
5052 u32 base_flags, u32 mss)
1da177e4 5053{
f3f3f27e 5054 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5055 struct sk_buff *new_skb;
c58ec932 5056 dma_addr_t new_addr = 0;
1da177e4 5057 u32 entry = *start;
c58ec932 5058 int i, ret = 0;
1da177e4 5059
41588ba1
MC		 5060 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5061 new_skb = skb_copy(skb, GFP_ATOMIC);
5062 else {
5063 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5064
5065 new_skb = skb_copy_expand(skb,
5066 skb_headroom(skb) + more_headroom,
5067 skb_tailroom(skb), GFP_ATOMIC);
5068 }
5069
1da177e4 5070 if (!new_skb) {
c58ec932
MC		 5071 ret = -1;
5072 } else {
5073 /* New SKB is guaranteed to be linear. */
5074 entry = *start;
90079ce8 5075 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5076 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5077
c58ec932
MC		 5078 /* Make sure new skb does not cross any 4G boundaries.
5079 * Drop the packet if it does.
5080 */
90079ce8 5081 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5082 if (!ret)
5083 skb_dma_unmap(&tp->pdev->dev, new_skb,
5084 DMA_TO_DEVICE);
c58ec932
MC		 5085 ret = -1;
5086 dev_kfree_skb(new_skb);
5087 new_skb = NULL;
5088 } else {
f3f3f27e 5089 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5090 base_flags, 1 | (mss << 1));
5091 *start = NEXT_TX(entry);
5092 }
1da177e4
LT		 5093 }
5094
1da177e4
LT		 5095 /* Now clean up the sw ring entries. */
5096 i = 0;
5097 while (entry != last_plus_one) {
f3f3f27e
MC		 5098 if (i == 0)
5099 tnapi->tx_buffers[entry].skb = new_skb;
5100 else
5101 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5102 entry = NEXT_TX(entry);
5103 i++;
5104 }
5105
90079ce8 5106 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5107 dev_kfree_skb(skb);
5108
c58ec932 5109 return ret;
1da177e4
LT		 5110}
5111
f3f3f27e 5112static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5113 dma_addr_t mapping, int len, u32 flags,
5114 u32 mss_and_is_end)
5115{
f3f3f27e 5116 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5117 int is_end = (mss_and_is_end & 0x1);
5118 u32 mss = (mss_and_is_end >> 1);
5119 u32 vlan_tag = 0;
5120
5121 if (is_end)
5122 flags |= TXD_FLAG_END;
5123 if (flags & TXD_FLAG_VLAN) {
5124 vlan_tag = flags >> 16;
5125 flags &= 0xffff;
5126 }
5127 vlan_tag |= (mss << TXD_MSS_SHIFT);
5128
5129 txd->addr_hi = ((u64) mapping >> 32);
5130 txd->addr_lo = ((u64) mapping & 0xffffffff);
5131 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5132 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5133}
5134
5a6f3074
MC		 5135/* hard_start_xmit for devices that don't have any bugs and
5136 * support TG3_FLG2_HW_TSO_2 only.
5137 */
61357325
SH		 5138static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5139 struct net_device *dev)
5a6f3074
MC		 5140{
5141 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5142 u32 len, entry, base_flags, mss;
90079ce8
DM		 5143 struct skb_shared_info *sp;
5144 dma_addr_t mapping;
f3f3f27e 5145 struct tg3_napi *tnapi = &tp->napi[0];
5a6f3074
MC		 5146
5147 len = skb_headlen(skb);
5148
00b70504 5149 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5150 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5151 * interrupt. Furthermore, IRQ processing runs lockless so we have
5152 * no IRQ context deadlocks to worry about either. Rejoice!
5153 */
f3f3f27e 5154 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5155 if (!netif_queue_stopped(dev)) {
5156 netif_stop_queue(dev);
5157
5158 /* This is a hard error, log it. */
5159 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5160 "queue awake!\n", dev->name);
5161 }
5a6f3074
MC		 5162 return NETDEV_TX_BUSY;
5163 }
5164
f3f3f27e 5165 entry = tnapi->tx_prod;
5a6f3074 5166 base_flags = 0;
5a6f3074 5167 mss = 0;
c13e3713 5168 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5169 int tcp_opt_len, ip_tcp_len;
5170
5171 if (skb_header_cloned(skb) &&
5172 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5173 dev_kfree_skb(skb);
5174 goto out_unlock;
5175 }
5176
b0026624
MC		 5177 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5178 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5179 else {
eddc9ec5
ACM		 5180 struct iphdr *iph = ip_hdr(skb);
5181
ab6a5bb6 5182 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5183 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5184
eddc9ec5
ACM		 5185 iph->check = 0;
5186 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5187 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5188 }
5a6f3074
MC		 5189
5190 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5191 TXD_FLAG_CPU_POST_DMA);
5192
aa8223c7 5193 tcp_hdr(skb)->check = 0;
5a6f3074 5194
5a6f3074 5195 }
84fa7933 5196 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5197 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5198#if TG3_VLAN_TAG_USED
5199 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5200 base_flags |= (TXD_FLAG_VLAN |
5201 (vlan_tx_tag_get(skb) << 16));
5202#endif
5203
90079ce8
DM		 5204 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5205 dev_kfree_skb(skb);
5206 goto out_unlock;
5207 }
5208
5209 sp = skb_shinfo(skb);
5210
042a53a9 5211 mapping = sp->dma_head;
5a6f3074 5212
f3f3f27e 5213 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5214
f3f3f27e 5215 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5216 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5217
5218 entry = NEXT_TX(entry);
5219
5220 /* Now loop through additional data fragments, and queue them. */
5221 if (skb_shinfo(skb)->nr_frags > 0) {
5222 unsigned int i, last;
5223
5224 last = skb_shinfo(skb)->nr_frags - 1;
5225 for (i = 0; i <= last; i++) {
5226 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5227
5228 len = frag->size;
042a53a9 5229 mapping = sp->dma_maps[i];
f3f3f27e 5230 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5231
f3f3f27e 5232 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5233 base_flags, (i == last) | (mss << 1));
5234
5235 entry = NEXT_TX(entry);
5236 }
5237 }
5238
5239 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5240 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5241
f3f3f27e
MC		 5242 tnapi->tx_prod = entry;
5243 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5244 netif_stop_queue(dev);
f3f3f27e 5245 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5a6f3074
MC		 5246 netif_wake_queue(tp->dev);
5247 }
5248
5249out_unlock:
cdd0db05 5250 mmiowb();
5a6f3074
MC		 5251
5252 return NETDEV_TX_OK;
5253}
5254
61357325
SH		 5255static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5256 struct net_device *);
52c0fd83
MC		 5257
5258/* Use GSO to workaround a rare TSO bug that may be triggered when the
5259 * TSO header is greater than 80 bytes.
5260 */
5261static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5262{
5263 struct sk_buff *segs, *nskb;
f3f3f27e 5264 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5265
5266 /* Estimate the number of fragments in the worst case */
f3f3f27e 5267 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5268 netif_stop_queue(tp->dev);
f3f3f27e 5269 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5270 return NETDEV_TX_BUSY;
5271
5272 netif_wake_queue(tp->dev);
52c0fd83
MC		 5273 }
5274
5275 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5276 if (IS_ERR(segs))
52c0fd83
MC		 5277 goto tg3_tso_bug_end;
5278
5279 do {
5280 nskb = segs;
5281 segs = segs->next;
5282 nskb->next = NULL;
5283 tg3_start_xmit_dma_bug(nskb, tp->dev);
5284 } while (segs);
5285
5286tg3_tso_bug_end:
5287 dev_kfree_skb(skb);
5288
5289 return NETDEV_TX_OK;
5290}
52c0fd83 5291
5a6f3074
MC		 5292/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5293 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5294 */
61357325
SH		 5295static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5296 struct net_device *dev)
1da177e4
LT		 5297{
5298 struct tg3 *tp = netdev_priv(dev);
1da177e4 5299 u32 len, entry, base_flags, mss;
90079ce8 5300 struct skb_shared_info *sp;
1da177e4 5301 int would_hit_hwbug;
90079ce8 5302 dma_addr_t mapping;
f3f3f27e 5303 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5304
5305 len = skb_headlen(skb);
5306
00b70504 5307 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5308 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5309 * interrupt. Furthermore, IRQ processing runs lockless so we have
5310 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5311 */
f3f3f27e 5312 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5313 if (!netif_queue_stopped(dev)) {
5314 netif_stop_queue(dev);
5315
5316 /* This is a hard error, log it. */
5317 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5318 "queue awake!\n", dev->name);
5319 }
1da177e4
LT		 5320 return NETDEV_TX_BUSY;
5321 }
5322
f3f3f27e 5323 entry = tnapi->tx_prod;
1da177e4 5324 base_flags = 0;
84fa7933 5325 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5326 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5327 mss = 0;
c13e3713 5328 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5329 struct iphdr *iph;
52c0fd83 5330 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5331
5332 if (skb_header_cloned(skb) &&
5333 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5334 dev_kfree_skb(skb);
5335 goto out_unlock;
5336 }
5337
ab6a5bb6 5338 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5339 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5340
52c0fd83
MC		 5341 hdr_len = ip_tcp_len + tcp_opt_len;
5342 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5343 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5344 return (tg3_tso_bug(tp, skb));
5345
1da177e4
LT		 5346 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5347 TXD_FLAG_CPU_POST_DMA);
5348
eddc9ec5
ACM		 5349 iph = ip_hdr(skb);
5350 iph->check = 0;
5351 iph->tot_len = htons(mss + hdr_len);
1da177e4 5352 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5353 tcp_hdr(skb)->check = 0;
1da177e4 5354 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5355 } else
5356 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5357 iph->daddr, 0,
5358 IPPROTO_TCP,
5359 0);
1da177e4
LT		 5360
5361 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5362 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5363 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5364 int tsflags;
5365
eddc9ec5 5366 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5367 mss |= (tsflags << 11);
5368 }
5369 } else {
eddc9ec5 5370 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5371 int tsflags;
5372
eddc9ec5 5373 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5374 base_flags |= tsflags << 12;
5375 }
5376 }
5377 }
1da177e4
LT		 5378#if TG3_VLAN_TAG_USED
5379 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5380 base_flags |= (TXD_FLAG_VLAN |
5381 (vlan_tx_tag_get(skb) << 16));
5382#endif
5383
90079ce8
DM		 5384 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5385 dev_kfree_skb(skb);
5386 goto out_unlock;
5387 }
5388
5389 sp = skb_shinfo(skb);
5390
042a53a9 5391 mapping = sp->dma_head;
1da177e4 5392
f3f3f27e 5393 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5394
5395 would_hit_hwbug = 0;
5396
41588ba1
MC		 5397 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5398 would_hit_hwbug = 1;
5399 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5400 would_hit_hwbug = 1;
1da177e4 5401
f3f3f27e 5402 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5403 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5404
5405 entry = NEXT_TX(entry);
5406
5407 /* Now loop through additional data fragments, and queue them. */
5408 if (skb_shinfo(skb)->nr_frags > 0) {
5409 unsigned int i, last;
5410
5411 last = skb_shinfo(skb)->nr_frags - 1;
5412 for (i = 0; i <= last; i++) {
5413 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5414
5415 len = frag->size;
042a53a9 5416 mapping = sp->dma_maps[i];
1da177e4 5417
f3f3f27e 5418 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5419
c58ec932
MC		 5420 if (tg3_4g_overflow_test(mapping, len))
5421 would_hit_hwbug = 1;
1da177e4 5422
72f2afb8
MC		 5423 if (tg3_40bit_overflow_test(tp, mapping, len))
5424 would_hit_hwbug = 1;
5425
1da177e4 5426 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5427 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5428 base_flags, (i == last)|(mss << 1));
5429 else
f3f3f27e 5430 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5431 base_flags, (i == last));
5432
5433 entry = NEXT_TX(entry);
5434 }
5435 }
5436
5437 if (would_hit_hwbug) {
5438 u32 last_plus_one = entry;
5439 u32 start;
1da177e4 5440
c58ec932
MC		 5441 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5442 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5443
5444 /* If the workaround fails due to memory/mapping
5445 * failure, silently drop this packet.
5446 */
72f2afb8 5447 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5448 &start, base_flags, mss))
1da177e4
LT		 5449 goto out_unlock;
5450
5451 entry = start;
5452 }
5453
5454 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5455 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5456
f3f3f27e
MC		 5457 tnapi->tx_prod = entry;
5458 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5459 netif_stop_queue(dev);
f3f3f27e 5460 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5461 netif_wake_queue(tp->dev);
5462 }
1da177e4
LT		 5463
5464out_unlock:
cdd0db05 5465 mmiowb();
1da177e4
LT		 5466
5467 return NETDEV_TX_OK;
5468}
5469
5470static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5471 int new_mtu)
5472{
5473 dev->mtu = new_mtu;
5474
ef7f5ec0 5475 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5476 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5477 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5478 ethtool_op_set_tso(dev, 0);
5479 }
5480 else
5481 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5482 } else {
a4e2b347 5483 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5484 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5485 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5486 }
1da177e4
LT		 5487}
5488
5489static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5490{
5491 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5492 int err;
1da177e4
LT		 5493
5494 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5495 return -EINVAL;
5496
5497 if (!netif_running(dev)) {
5498 /* We'll just catch it later when the
5499 * device is up'd.
5500 */
5501 tg3_set_mtu(dev, tp, new_mtu);
5502 return 0;
5503 }
5504
b02fd9e3
MC		 5505 tg3_phy_stop(tp);
5506
1da177e4 5507 tg3_netif_stop(tp);
f47c11ee
DM		 5508
5509 tg3_full_lock(tp, 1);
1da177e4 5510
944d980e 5511 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5512
5513 tg3_set_mtu(dev, tp, new_mtu);
5514
b9ec6c1b 5515 err = tg3_restart_hw(tp, 0);
1da177e4 5516
b9ec6c1b
MC		 5517 if (!err)
5518 tg3_netif_start(tp);
1da177e4 5519
f47c11ee 5520 tg3_full_unlock(tp);
1da177e4 5521
b02fd9e3
MC		 5522 if (!err)
5523 tg3_phy_start(tp);
5524
b9ec6c1b 5525 return err;
1da177e4
LT		 5526}
5527
21f581a5
MC		 5528static void tg3_rx_prodring_free(struct tg3 *tp,
5529 struct tg3_rx_prodring_set *tpr)
1da177e4 5530{
1da177e4 5531 int i;
f3f3f27e 5532 struct ring_info *rxp;
1da177e4
LT		 5533
5534 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5535 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5536
5537 if (rxp->skb == NULL)
5538 continue;
1da177e4 5539
1da177e4
LT		 5540 pci_unmap_single(tp->pdev,
5541 pci_unmap_addr(rxp, mapping),
cf7a7298 5542 tp->rx_pkt_map_sz,
1da177e4
LT		 5543 PCI_DMA_FROMDEVICE);
5544 dev_kfree_skb_any(rxp->skb);
5545 rxp->skb = NULL;
5546 }
5547
cf7a7298
MC		 5548 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5549 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5550 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5551
cf7a7298
MC		 5552 if (rxp->skb == NULL)
5553 continue;
1da177e4 5554
cf7a7298
MC		 5555 pci_unmap_single(tp->pdev,
5556 pci_unmap_addr(rxp, mapping),
5557 TG3_RX_JMB_MAP_SZ,
5558 PCI_DMA_FROMDEVICE);
5559 dev_kfree_skb_any(rxp->skb);
5560 rxp->skb = NULL;
1da177e4 5561 }
1da177e4
LT		 5562 }
5563}
5564
5565/* Initialize tx/rx rings for packet processing.
5566 *
5567 * The chip has been shut down and the driver detached from
5568 * the networking, so no interrupts or new tx packets will
5569 * end up in the driver. tp->{tx,}lock are held and thus
5570 * we may not sleep.
5571 */
21f581a5
MC		 5572static int tg3_rx_prodring_alloc(struct tg3 *tp,
5573 struct tg3_rx_prodring_set *tpr)
1da177e4 5574{
287be12e 5575 u32 i, rx_pkt_dma_sz;
17375d25 5576 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5577
1da177e4 5578 /* Zero out all descriptors. */
21f581a5 5579 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5580
287be12e 5581 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5582 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5583 tp->dev->mtu > ETH_DATA_LEN)
5584 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5585 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5586
1da177e4
LT		 5587 /* Initialize invariants of the rings, we only set this
5588 * stuff once. This works because the card does not
5589 * write into the rx buffer posting rings.
5590 */
5591 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5592 struct tg3_rx_buffer_desc *rxd;
5593
21f581a5 5594 rxd = &tpr->rx_std[i];
287be12e 5595 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5596 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5597 rxd->opaque = (RXD_OPAQUE_RING_STD |
5598 (i << RXD_OPAQUE_INDEX_SHIFT));
5599 }
5600
1da177e4
LT		 5601 /* Now allocate fresh SKBs for each rx ring. */
5602 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5603 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5604 printk(KERN_WARNING PFX
5605 "%s: Using a smaller RX standard ring, "
5606 "only %d out of %d buffers were allocated "
5607 "successfully.\n",
5608 tp->dev->name, i, tp->rx_pending);
5609 if (i == 0)
cf7a7298 5610 goto initfail;
32d8c572 5611 tp->rx_pending = i;
1da177e4 5612 break;
32d8c572 5613 }
1da177e4
LT		 5614 }
5615
cf7a7298
MC		 5616 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5617 goto done;
5618
21f581a5 5619 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5620
0f893dc6 5621 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5622 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5623 struct tg3_rx_buffer_desc *rxd;
5624
79ed5ac7 5625 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5626 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5627 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5628 RXD_FLAG_JUMBO;
5629 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5630 (i << RXD_OPAQUE_INDEX_SHIFT));
5631 }
5632
1da177e4 5633 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5634 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5635 -1, i) < 0) {
5636 printk(KERN_WARNING PFX
5637 "%s: Using a smaller RX jumbo ring, "
5638 "only %d out of %d buffers were "
5639 "allocated successfully.\n",
5640 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5641 if (i == 0)
5642 goto initfail;
32d8c572 5643 tp->rx_jumbo_pending = i;
1da177e4 5644 break;
32d8c572 5645 }
1da177e4
LT		 5646 }
5647 }
cf7a7298
MC		 5648
5649done:
32d8c572 5650 return 0;
cf7a7298
MC		 5651
5652initfail:
21f581a5 5653 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5654 return -ENOMEM;
1da177e4
LT		 5655}
5656
21f581a5
MC		 5657static void tg3_rx_prodring_fini(struct tg3 *tp,
5658 struct tg3_rx_prodring_set *tpr)
1da177e4 5659{
21f581a5
MC		 5660 kfree(tpr->rx_std_buffers);
5661 tpr->rx_std_buffers = NULL;
5662 kfree(tpr->rx_jmb_buffers);
5663 tpr->rx_jmb_buffers = NULL;
5664 if (tpr->rx_std) {
1da177e4 5665 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5666 tpr->rx_std, tpr->rx_std_mapping);
5667 tpr->rx_std = NULL;
1da177e4 5668 }
21f581a5 5669 if (tpr->rx_jmb) {
1da177e4 5670 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5671 tpr->rx_jmb, tpr->rx_jmb_mapping);
5672 tpr->rx_jmb = NULL;
1da177e4 5673 }
cf7a7298
MC		 5674}
5675
21f581a5
MC		 5676static int tg3_rx_prodring_init(struct tg3 *tp,
5677 struct tg3_rx_prodring_set *tpr)
cf7a7298 5678{
21f581a5
MC		 5679 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5680 TG3_RX_RING_SIZE, GFP_KERNEL);
5681 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5682 return -ENOMEM;
5683
21f581a5
MC		 5684 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5685 &tpr->rx_std_mapping);
5686 if (!tpr->rx_std)
cf7a7298
MC		 5687 goto err_out;
5688
5689 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5690 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5691 TG3_RX_JUMBO_RING_SIZE,
5692 GFP_KERNEL);
5693 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5694 goto err_out;
5695
21f581a5
MC		 5696 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5697 TG3_RX_JUMBO_RING_BYTES,
5698 &tpr->rx_jmb_mapping);
5699 if (!tpr->rx_jmb)
cf7a7298
MC		 5700 goto err_out;
5701 }
5702
5703 return 0;
5704
5705err_out:
21f581a5 5706 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5707 return -ENOMEM;
5708}
5709
5710/* Free up pending packets in all rx/tx rings.
5711 *
5712 * The chip has been shut down and the driver detached from
5713 * the networking, so no interrupts or new tx packets will
5714 * end up in the driver. tp->{tx,}lock is not held and we are not
5715 * in an interrupt context and thus may sleep.
5716 */
5717static void tg3_free_rings(struct tg3 *tp)
5718{
f3f3f27e 5719 struct tg3_napi *tnapi = &tp->napi[0];
cf7a7298
MC		 5720 int i;
5721
5722 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5723 struct tx_ring_info *txp;
5724 struct sk_buff *skb;
5725
f3f3f27e 5726 txp = &tnapi->tx_buffers[i];
cf7a7298
MC		 5727 skb = txp->skb;
5728
5729 if (skb == NULL) {
5730 i++;
5731 continue;
5732 }
5733
5734 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5735
5736 txp->skb = NULL;
5737
5738 i += skb_shinfo(skb)->nr_frags + 1;
5739
5740 dev_kfree_skb_any(skb);
5741 }
5742
21f581a5 5743 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5744}
5745
5746/* Initialize tx/rx rings for packet processing.
5747 *
5748 * The chip has been shut down and the driver detached from
5749 * the networking, so no interrupts or new tx packets will
5750 * end up in the driver. tp->{tx,}lock are held and thus
5751 * we may not sleep.
5752 */
5753static int tg3_init_rings(struct tg3 *tp)
5754{
72334482
MC		 5755 struct tg3_napi *tnapi = &tp->napi[0];
5756
cf7a7298
MC		 5757 /* Free up all the SKBs. */
5758 tg3_free_rings(tp);
5759
5760 /* Zero out all descriptors. */
f3f3f27e 5761 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
cf7a7298 5762
72334482
MC		 5763 tnapi->rx_rcb_ptr = 0;
5764 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5765
21f581a5 5766 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5767}
5768
5769/*
5770 * Must not be invoked with interrupt sources disabled and
5771 * the hardware shutdown down.
5772 */
5773static void tg3_free_consistent(struct tg3 *tp)
5774{
898a56f8
MC		 5775 struct tg3_napi *tnapi = &tp->napi[0];
5776
f3f3f27e
MC		 5777 kfree(tnapi->tx_buffers);
5778 tnapi->tx_buffers = NULL;
5779 if (tnapi->tx_ring) {
1da177e4 5780 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
f3f3f27e
MC		 5781 tnapi->tx_ring, tnapi->tx_desc_mapping);
5782 tnapi->tx_ring = NULL;
1da177e4 5783 }
72334482
MC		 5784 if (tnapi->rx_rcb) {
5785 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5786 tnapi->rx_rcb, tnapi->rx_rcb_mapping);
5787 tnapi->rx_rcb = NULL;
5788 }
898a56f8 5789 if (tnapi->hw_status) {
1da177e4 5790 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
898a56f8
MC		 5791 tnapi->hw_status,
5792 tnapi->status_mapping);
5793 tnapi->hw_status = NULL;
1da177e4
LT		 5794 }
5795 if (tp->hw_stats) {
5796 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5797 tp->hw_stats, tp->stats_mapping);
5798 tp->hw_stats = NULL;
5799 }
21f581a5 5800 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5801}
5802
5803/*
5804 * Must not be invoked with interrupt sources disabled and
5805 * the hardware shutdown down. Can sleep.
5806 */
5807static int tg3_alloc_consistent(struct tg3 *tp)
5808{
898a56f8
MC		 5809 struct tg3_napi *tnapi = &tp->napi[0];
5810
21f581a5 5811 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5812 return -ENOMEM;
5813
f3f3f27e
MC		 5814 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5815 TG3_TX_RING_SIZE, GFP_KERNEL);
5816 if (!tnapi->tx_buffers)
1da177e4
LT		 5817 goto err_out;
5818
f3f3f27e
MC		 5819 tnapi->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5820 &tnapi->tx_desc_mapping);
5821 if (!tnapi->tx_ring)
1da177e4
LT		 5822 goto err_out;
5823
898a56f8
MC		 5824 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5825 TG3_HW_STATUS_SIZE,
5826 &tnapi->status_mapping);
5827 if (!tnapi->hw_status)
1da177e4
LT		 5828 goto err_out;
5829
898a56f8
MC		 5830 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5831
72334482
MC		 5832 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5833 TG3_RX_RCB_RING_BYTES(tp),
5834 &tnapi->rx_rcb_mapping);
5835 if (!tnapi->rx_rcb)
5836 goto err_out;
5837
5838 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5839
1da177e4
LT		 5840 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5841 sizeof(struct tg3_hw_stats),
5842 &tp->stats_mapping);
5843 if (!tp->hw_stats)
5844 goto err_out;
5845
1da177e4
LT		 5846 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5847
5848 return 0;
5849
5850err_out:
5851 tg3_free_consistent(tp);
5852 return -ENOMEM;
5853}
5854
5855#define MAX_WAIT_CNT 1000
5856
5857/* To stop a block, clear the enable bit and poll till it
5858 * clears. tp->lock is held.
5859 */
b3b7d6be 5860static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5861{
5862 unsigned int i;
5863 u32 val;
5864
5865 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5866 switch (ofs) {
5867 case RCVLSC_MODE:
5868 case DMAC_MODE:
5869 case MBFREE_MODE:
5870 case BUFMGR_MODE:
5871 case MEMARB_MODE:
5872 /* We can't enable/disable these bits of the
5873 * 5705/5750, just say success.
5874 */
5875 return 0;
5876
5877 default:
5878 break;
855e1111 5879 }
1da177e4
LT		 5880 }
5881
5882 val = tr32(ofs);
5883 val &= ~enable_bit;
5884 tw32_f(ofs, val);
5885
5886 for (i = 0; i < MAX_WAIT_CNT; i++) {
5887 udelay(100);
5888 val = tr32(ofs);
5889 if ((val & enable_bit) == 0)
5890 break;
5891 }
5892
b3b7d6be 5893 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5894 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5895 "ofs=%lx enable_bit=%x\n",
5896 ofs, enable_bit);
5897 return -ENODEV;
5898 }
5899
5900 return 0;
5901}
5902
5903/* tp->lock is held. */
b3b7d6be 5904static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5905{
5906 int i, err;
898a56f8 5907 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5908
5909 tg3_disable_ints(tp);
5910
5911 tp->rx_mode &= ~RX_MODE_ENABLE;
5912 tw32_f(MAC_RX_MODE, tp->rx_mode);
5913 udelay(10);
5914
b3b7d6be
DM		 5915 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5916 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5917 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5918 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5919 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5920 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5921
5922 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5923 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5924 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5925 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5926 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5927 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5928 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5929
5930 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5931 tw32_f(MAC_MODE, tp->mac_mode);
5932 udelay(40);
5933
5934 tp->tx_mode &= ~TX_MODE_ENABLE;
5935 tw32_f(MAC_TX_MODE, tp->tx_mode);
5936
5937 for (i = 0; i < MAX_WAIT_CNT; i++) {
5938 udelay(100);
5939 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5940 break;
5941 }
5942 if (i >= MAX_WAIT_CNT) {
5943 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5944 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5945 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5946 err |= -ENODEV;
1da177e4
LT		 5947 }
5948
e6de8ad1 5949 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5950 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5951 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5952
5953 tw32(FTQ_RESET, 0xffffffff);
5954 tw32(FTQ_RESET, 0x00000000);
5955
b3b7d6be
DM		 5956 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5957 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 5958
898a56f8
MC		 5959 if (tnapi->hw_status)
5960 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
1da177e4
LT		 5961 if (tp->hw_stats)
5962 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5963
1da177e4
LT		 5964 return err;
5965}
5966
0d3031d9
MC		 5967static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5968{
5969 int i;
5970 u32 apedata;
5971
5972 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5973 if (apedata != APE_SEG_SIG_MAGIC)
5974 return;
5975
5976 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5977 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5978 return;
5979
5980 /* Wait for up to 1 millisecond for APE to service previous event. */
5981 for (i = 0; i < 10; i++) {
5982 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5983 return;
5984
5985 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5986
5987 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5988 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5989 event | APE_EVENT_STATUS_EVENT_PENDING);
5990
5991 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5992
5993 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5994 break;
5995
5996 udelay(100);
5997 }
5998
5999 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6000 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6001}
6002
6003static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6004{
6005 u32 event;
6006 u32 apedata;
6007
6008 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6009 return;
6010
6011 switch (kind) {
6012 case RESET_KIND_INIT:
6013 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6014 APE_HOST_SEG_SIG_MAGIC);
6015 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6016 APE_HOST_SEG_LEN_MAGIC);
6017 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6018 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6019 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6020 APE_HOST_DRIVER_ID_MAGIC);
6021 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6022 APE_HOST_BEHAV_NO_PHYLOCK);
6023
6024 event = APE_EVENT_STATUS_STATE_START;
6025 break;
6026 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6027 /* With the interface we are currently using,
6028 * APE does not track driver state. Wiping
6029 * out the HOST SEGMENT SIGNATURE forces
6030 * the APE to assume OS absent status.
6031 */
6032 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6033
0d3031d9
MC		 6034 event = APE_EVENT_STATUS_STATE_UNLOAD;
6035 break;
6036 case RESET_KIND_SUSPEND:
6037 event = APE_EVENT_STATUS_STATE_SUSPEND;
6038 break;
6039 default:
6040 return;
6041 }
6042
6043 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6044
6045 tg3_ape_send_event(tp, event);
6046}
6047
1da177e4
LT		 6048/* tp->lock is held. */
6049static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6050{
f49639e6
DM		 6051 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6052 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6053
6054 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6055 switch (kind) {
6056 case RESET_KIND_INIT:
6057 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6058 DRV_STATE_START);
6059 break;
6060
6061 case RESET_KIND_SHUTDOWN:
6062 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6063 DRV_STATE_UNLOAD);
6064 break;
6065
6066 case RESET_KIND_SUSPEND:
6067 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6068 DRV_STATE_SUSPEND);
6069 break;
6070
6071 default:
6072 break;
855e1111 6073 }
1da177e4 6074 }
0d3031d9
MC		 6075
6076 if (kind == RESET_KIND_INIT ||
6077 kind == RESET_KIND_SUSPEND)
6078 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6079}
6080
6081/* tp->lock is held. */
6082static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6083{
6084 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6085 switch (kind) {
6086 case RESET_KIND_INIT:
6087 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6088 DRV_STATE_START_DONE);
6089 break;
6090
6091 case RESET_KIND_SHUTDOWN:
6092 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6093 DRV_STATE_UNLOAD_DONE);
6094 break;
6095
6096 default:
6097 break;
855e1111 6098 }
1da177e4 6099 }
0d3031d9
MC		 6100
6101 if (kind == RESET_KIND_SHUTDOWN)
6102 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6103}
6104
6105/* tp->lock is held. */
6106static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6107{
6108 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6109 switch (kind) {
6110 case RESET_KIND_INIT:
6111 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6112 DRV_STATE_START);
6113 break;
6114
6115 case RESET_KIND_SHUTDOWN:
6116 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6117 DRV_STATE_UNLOAD);
6118 break;
6119
6120 case RESET_KIND_SUSPEND:
6121 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6122 DRV_STATE_SUSPEND);
6123 break;
6124
6125 default:
6126 break;
855e1111 6127 }
1da177e4
LT		 6128 }
6129}
6130
7a6f4369
MC		 6131static int tg3_poll_fw(struct tg3 *tp)
6132{
6133 int i;
6134 u32 val;
6135
b5d3772c 6136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6137 /* Wait up to 20ms for init done. */
6138 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6139 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6140 return 0;
0ccead18 6141 udelay(100);
b5d3772c
MC		 6142 }
6143 return -ENODEV;
6144 }
6145
7a6f4369
MC		 6146 /* Wait for firmware initialization to complete. */
6147 for (i = 0; i < 100000; i++) {
6148 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6149 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6150 break;
6151 udelay(10);
6152 }
6153
6154 /* Chip might not be fitted with firmware. Some Sun onboard
6155 * parts are configured like that. So don't signal the timeout
6156 * of the above loop as an error, but do report the lack of
6157 * running firmware once.
6158 */
6159 if (i >= 100000 &&
6160 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6161 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6162
6163 printk(KERN_INFO PFX "%s: No firmware running.\n",
6164 tp->dev->name);
6165 }
6166
6167 return 0;
6168}
6169
ee6a99b5
MC		 6170/* Save PCI command register before chip reset */
6171static void tg3_save_pci_state(struct tg3 *tp)
6172{
8a6eac90 6173 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6174}
6175
6176/* Restore PCI state after chip reset */
6177static void tg3_restore_pci_state(struct tg3 *tp)
6178{
6179 u32 val;
6180
6181 /* Re-enable indirect register accesses. */
6182 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6183 tp->misc_host_ctrl);
6184
6185 /* Set MAX PCI retry to zero. */
6186 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6187 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6188 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6189 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6190 /* Allow reads and writes to the APE register and memory space. */
6191 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6192 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6193 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6194 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6195
8a6eac90 6196 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6197
fcb389df
MC		 6198 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6199 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6200 pcie_set_readrq(tp->pdev, 4096);
6201 else {
6202 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6203 tp->pci_cacheline_sz);
6204 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6205 tp->pci_lat_timer);
6206 }
114342f2 6207 }
5f5c51e3 6208
ee6a99b5 6209 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6210 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6211 u16 pcix_cmd;
6212
6213 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6214 &pcix_cmd);
6215 pcix_cmd &= ~PCI_X_CMD_ERO;
6216 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6217 pcix_cmd);
6218 }
ee6a99b5
MC		 6219
6220 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6221
6222 /* Chip reset on 5780 will reset MSI enable bit,
6223 * so need to restore it.
6224 */
6225 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6226 u16 ctrl;
6227
6228 pci_read_config_word(tp->pdev,
6229 tp->msi_cap + PCI_MSI_FLAGS,
6230 &ctrl);
6231 pci_write_config_word(tp->pdev,
6232 tp->msi_cap + PCI_MSI_FLAGS,
6233 ctrl | PCI_MSI_FLAGS_ENABLE);
6234 val = tr32(MSGINT_MODE);
6235 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6236 }
6237 }
6238}
6239
1da177e4
LT		 6240static void tg3_stop_fw(struct tg3 *);
6241
6242/* tp->lock is held. */
6243static int tg3_chip_reset(struct tg3 *tp)
6244{
6245 u32 val;
1ee582d8 6246 void (*write_op)(struct tg3 *, u32, u32);
7a6f4369 6247 int err;
1da177e4 6248
f49639e6
DM		 6249 tg3_nvram_lock(tp);
6250
158d7abd
MC		 6251 tg3_mdio_stop(tp);
6252
77b483f1
MC		 6253 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6254
f49639e6
DM		 6255 /* No matching tg3_nvram_unlock() after this because
6256 * chip reset below will undo the nvram lock.
6257 */
6258 tp->nvram_lock_cnt = 0;
1da177e4 6259
ee6a99b5
MC		 6260 /* GRC_MISC_CFG core clock reset will clear the memory
6261 * enable bit in PCI register 4 and the MSI enable bit
6262 * on some chips, so we save relevant registers here.
6263 */
6264 tg3_save_pci_state(tp);
6265
d9ab5ad1 6266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6267 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6268 tw32(GRC_FASTBOOT_PC, 0);
6269
1da177e4
LT		 6270 /*
6271 * We must avoid the readl() that normally takes place.
6272 * It locks machines, causes machine checks, and other
6273 * fun things. So, temporarily disable the 5701
6274 * hardware workaround, while we do the reset.
6275 */
1ee582d8
MC		 6276 write_op = tp->write32;
6277 if (write_op == tg3_write_flush_reg32)
6278 tp->write32 = tg3_write32;
1da177e4 6279
d18edcb2
MC		 6280 /* Prevent the irq handler from reading or writing PCI registers
6281 * during chip reset when the memory enable bit in the PCI command
6282 * register may be cleared. The chip does not generate interrupt
6283 * at this time, but the irq handler may still be called due to irq
6284 * sharing or irqpoll.
6285 */
6286 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
898a56f8
MC		 6287 if (tp->napi[0].hw_status) {
6288 tp->napi[0].hw_status->status = 0;
6289 tp->napi[0].hw_status->status_tag = 0;
b8fa2f3a 6290 }
898a56f8
MC		 6291 tp->napi[0].last_tag = 0;
6292 tp->napi[0].last_irq_tag = 0;
d18edcb2
MC		 6293 smp_mb();
6294 synchronize_irq(tp->pdev->irq);
6295
255ca311
MC		 6296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6297 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6298 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6299 }
6300
1da177e4
LT		 6301 /* do the reset */
6302 val = GRC_MISC_CFG_CORECLK_RESET;
6303
6304 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6305 if (tr32(0x7e2c) == 0x60) {
6306 tw32(0x7e2c, 0x20);
6307 }
6308 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6309 tw32(GRC_MISC_CFG, (1 << 29));
6310 val |= (1 << 29);
6311 }
6312 }
6313
b5d3772c
MC		 6314 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6315 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6316 tw32(GRC_VCPU_EXT_CTRL,
6317 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6318 }
6319
1da177e4
LT		 6320 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6321 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6322 tw32(GRC_MISC_CFG, val);
6323
1ee582d8
MC		 6324 /* restore 5701 hardware bug workaround write method */
6325 tp->write32 = write_op;
1da177e4
LT		 6326
6327 /* Unfortunately, we have to delay before the PCI read back.
6328 * Some 575X chips even will not respond to a PCI cfg access
6329 * when the reset command is given to the chip.
6330 *
6331 * How do these hardware designers expect things to work
6332 * properly if the PCI write is posted for a long period
6333 * of time? It is always necessary to have some method by
6334 * which a register read back can occur to push the write
6335 * out which does the reset.
6336 *
6337 * For most tg3 variants the trick below was working.
6338 * Ho hum...
6339 */
6340 udelay(120);
6341
6342 /* Flush PCI posted writes. The normal MMIO registers
6343 * are inaccessible at this time so this is the only
6344 * way to make this reliably (actually, this is no longer
6345 * the case, see above). I tried to use indirect
6346 * register read/write but this upset some 5701 variants.
6347 */
6348 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6349
6350 udelay(120);
6351
5e7dfd0f 6352 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6353 u16 val16;
6354
1da177e4
LT		 6355 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6356 int i;
6357 u32 cfg_val;
6358
6359 /* Wait for link training to complete. */
6360 for (i = 0; i < 5000; i++)
6361 udelay(100);
6362
6363 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6364 pci_write_config_dword(tp->pdev, 0xc4,
6365 cfg_val | (1 << 15));
6366 }
5e7dfd0f 6367
e7126997
MC		 6368 /* Clear the "no snoop" and "relaxed ordering" bits. */
6369 pci_read_config_word(tp->pdev,
6370 tp->pcie_cap + PCI_EXP_DEVCTL,
6371 &val16);
6372 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6373 PCI_EXP_DEVCTL_NOSNOOP_EN);
6374 /*
6375 * Older PCIe devices only support the 128 byte
6376 * MPS setting. Enforce the restriction.
5e7dfd0f 6377 */
e7126997
MC		 6378 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6379 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6380 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6381 pci_write_config_word(tp->pdev,
6382 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6383 val16);
5e7dfd0f
MC		 6384
6385 pcie_set_readrq(tp->pdev, 4096);
6386
6387 /* Clear error status */
6388 pci_write_config_word(tp->pdev,
6389 tp->pcie_cap + PCI_EXP_DEVSTA,
6390 PCI_EXP_DEVSTA_CED |
6391 PCI_EXP_DEVSTA_NFED |
6392 PCI_EXP_DEVSTA_FED |
6393 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6394 }
6395
ee6a99b5 6396 tg3_restore_pci_state(tp);
1da177e4 6397
d18edcb2
MC		 6398 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6399
ee6a99b5
MC		 6400 val = 0;
6401 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6402 val = tr32(MEMARB_MODE);
ee6a99b5 6403 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6404
6405 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6406 tg3_stop_fw(tp);
6407 tw32(0x5000, 0x400);
6408 }
6409
6410 tw32(GRC_MODE, tp->grc_mode);
6411
6412 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6413 val = tr32(0xc4);
1da177e4
LT		 6414
6415 tw32(0xc4, val | (1 << 15));
6416 }
6417
6418 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6420 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6421 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6422 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6423 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6424 }
6425
6426 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6427 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6428 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6429 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6430 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6431 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6432 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6433 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6434 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6435 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6436 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6437 } else
6438 tw32_f(MAC_MODE, 0);
6439 udelay(40);
6440
77b483f1
MC		 6441 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6442
7a6f4369
MC		 6443 err = tg3_poll_fw(tp);
6444 if (err)
6445 return err;
1da177e4 6446
0a9140cf
MC		 6447 tg3_mdio_start(tp);
6448
1da177e4
LT		 6449 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6450 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6451 val = tr32(0x7c00);
1da177e4
LT		 6452
6453 tw32(0x7c00, val | (1 << 25));
6454 }
6455
6456 /* Reprobe ASF enable state. */
6457 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6458 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6459 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6460 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6461 u32 nic_cfg;
6462
6463 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6464 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6465 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6466 tp->last_event_jiffies = jiffies;
cbf46853 6467 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6468 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6469 }
6470 }
6471
6472 return 0;
6473}
6474
6475/* tp->lock is held. */
6476static void tg3_stop_fw(struct tg3 *tp)
6477{
0d3031d9
MC		 6478 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6479 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6480 /* Wait for RX cpu to ACK the previous event. */
6481 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6482
6483 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6484
6485 tg3_generate_fw_event(tp);
1da177e4 6486
7c5026aa
MC		 6487 /* Wait for RX cpu to ACK this event. */
6488 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6489 }
6490}
6491
6492/* tp->lock is held. */
944d980e 6493static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6494{
6495 int err;
6496
6497 tg3_stop_fw(tp);
6498
944d980e 6499 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6500
b3b7d6be 6501 tg3_abort_hw(tp, silent);
1da177e4
LT		 6502 err = tg3_chip_reset(tp);
6503
daba2a63
MC		 6504 __tg3_set_mac_addr(tp, 0);
6505
944d980e
MC		 6506 tg3_write_sig_legacy(tp, kind);
6507 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6508
6509 if (err)
6510 return err;
6511
6512 return 0;
6513}
6514
1da177e4
LT		 6515#define RX_CPU_SCRATCH_BASE 0x30000
6516#define RX_CPU_SCRATCH_SIZE 0x04000
6517#define TX_CPU_SCRATCH_BASE 0x34000
6518#define TX_CPU_SCRATCH_SIZE 0x04000
6519
6520/* tp->lock is held. */
6521static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6522{
6523 int i;
6524
5d9428de
ES		 6525 BUG_ON(offset == TX_CPU_BASE &&
6526 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6527
b5d3772c
MC		 6528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6529 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6530
6531 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6532 return 0;
6533 }
1da177e4
LT		 6534 if (offset == RX_CPU_BASE) {
6535 for (i = 0; i < 10000; i++) {
6536 tw32(offset + CPU_STATE, 0xffffffff);
6537 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6538 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6539 break;
6540 }
6541
6542 tw32(offset + CPU_STATE, 0xffffffff);
6543 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6544 udelay(10);
6545 } else {
6546 for (i = 0; i < 10000; i++) {
6547 tw32(offset + CPU_STATE, 0xffffffff);
6548 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6549 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6550 break;
6551 }
6552 }
6553
6554 if (i >= 10000) {
6555 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6556 "and %s CPU\n",
6557 tp->dev->name,
6558 (offset == RX_CPU_BASE ? "RX" : "TX"));
6559 return -ENODEV;
6560 }
ec41c7df
MC		 6561
6562 /* Clear firmware's nvram arbitration. */
6563 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6564 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6565 return 0;
6566}
6567
6568struct fw_info {
077f849d
JSR		 6569 unsigned int fw_base;
6570 unsigned int fw_len;
6571 const __be32 *fw_data;
1da177e4
LT		 6572};
6573
6574/* tp->lock is held. */
6575static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6576 int cpu_scratch_size, struct fw_info *info)
6577{
ec41c7df 6578 int err, lock_err, i;
1da177e4
LT		 6579 void (*write_op)(struct tg3 *, u32, u32);
6580
6581 if (cpu_base == TX_CPU_BASE &&
6582 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6583 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6584 "TX cpu firmware on %s which is 5705.\n",
6585 tp->dev->name);
6586 return -EINVAL;
6587 }
6588
6589 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6590 write_op = tg3_write_mem;
6591 else
6592 write_op = tg3_write_indirect_reg32;
6593
1b628151
MC		 6594 /* It is possible that bootcode is still loading at this point.
6595 * Get the nvram lock first before halting the cpu.
6596 */
ec41c7df 6597 lock_err = tg3_nvram_lock(tp);
1da177e4 6598 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6599 if (!lock_err)
6600 tg3_nvram_unlock(tp);
1da177e4
LT		 6601 if (err)
6602 goto out;
6603
6604 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6605 write_op(tp, cpu_scratch_base + i, 0);
6606 tw32(cpu_base + CPU_STATE, 0xffffffff);
6607 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6608 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6609 write_op(tp, (cpu_scratch_base +
077f849d 6610 (info->fw_base & 0xffff) +
1da177e4 6611 (i * sizeof(u32))),
077f849d 6612 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6613
6614 err = 0;
6615
6616out:
1da177e4
LT		 6617 return err;
6618}
6619
6620/* tp->lock is held. */
6621static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6622{
6623 struct fw_info info;
077f849d 6624 const __be32 *fw_data;
1da177e4
LT		 6625 int err, i;
6626
077f849d
JSR		 6627 fw_data = (void *)tp->fw->data;
6628
6629 /* Firmware blob starts with version numbers, followed by
6630 start address and length. We are setting complete length.
6631 length = end_address_of_bss - start_address_of_text.
6632 Remainder is the blob to be loaded contiguously
6633 from start address. */
6634
6635 info.fw_base = be32_to_cpu(fw_data[1]);
6636 info.fw_len = tp->fw->size - 12;
6637 info.fw_data = &fw_data[3];
1da177e4
LT		 6638
6639 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6640 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6641 &info);
6642 if (err)
6643 return err;
6644
6645 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6646 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6647 &info);
6648 if (err)
6649 return err;
6650
6651 /* Now startup only the RX cpu. */
6652 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6653 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6654
6655 for (i = 0; i < 5; i++) {
077f849d 6656 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6657 break;
6658 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6659 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6660 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6661 udelay(1000);
6662 }
6663 if (i >= 5) {
6664 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6665 "to set RX CPU PC, is %08x should be %08x\n",
6666 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6667 info.fw_base);
1da177e4
LT		 6668 return -ENODEV;
6669 }
6670 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6671 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6672
6673 return 0;
6674}
6675
1da177e4 6676/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6677
6678/* tp->lock is held. */
6679static int tg3_load_tso_firmware(struct tg3 *tp)
6680{
6681 struct fw_info info;
077f849d 6682 const __be32 *fw_data;
1da177e4
LT		 6683 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6684 int err, i;
6685
6686 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6687 return 0;
6688
077f849d
JSR		 6689 fw_data = (void *)tp->fw->data;
6690
6691 /* Firmware blob starts with version numbers, followed by
6692 start address and length. We are setting complete length.
6693 length = end_address_of_bss - start_address_of_text.
6694 Remainder is the blob to be loaded contiguously
6695 from start address. */
6696
6697 info.fw_base = be32_to_cpu(fw_data[1]);
6698 cpu_scratch_size = tp->fw_len;
6699 info.fw_len = tp->fw->size - 12;
6700 info.fw_data = &fw_data[3];
6701
1da177e4 6702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6703 cpu_base = RX_CPU_BASE;
6704 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6705 } else {
1da177e4
LT		 6706 cpu_base = TX_CPU_BASE;
6707 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6708 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6709 }
6710
6711 err = tg3_load_firmware_cpu(tp, cpu_base,
6712 cpu_scratch_base, cpu_scratch_size,
6713 &info);
6714 if (err)
6715 return err;
6716
6717 /* Now startup the cpu. */
6718 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6719 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6720
6721 for (i = 0; i < 5; i++) {
077f849d 6722 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6723 break;
6724 tw32(cpu_base + CPU_STATE, 0xffffffff);
6725 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6726 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6727 udelay(1000);
6728 }
6729 if (i >= 5) {
6730 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6731 "to set CPU PC, is %08x should be %08x\n",
6732 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6733 info.fw_base);
1da177e4
LT		 6734 return -ENODEV;
6735 }
6736 tw32(cpu_base + CPU_STATE, 0xffffffff);
6737 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6738 return 0;
6739}
6740
1da177e4 6741
1da177e4
LT		 6742static int tg3_set_mac_addr(struct net_device *dev, void *p)
6743{
6744 struct tg3 *tp = netdev_priv(dev);
6745 struct sockaddr *addr = p;
986e0aeb 6746 int err = 0, skip_mac_1 = 0;
1da177e4 6747
f9804ddb
MC		 6748 if (!is_valid_ether_addr(addr->sa_data))
6749 return -EINVAL;
6750
1da177e4
LT		 6751 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6752
e75f7c90
MC		 6753 if (!netif_running(dev))
6754 return 0;
6755
58712ef9 6756 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6757 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6758
986e0aeb
MC		 6759 addr0_high = tr32(MAC_ADDR_0_HIGH);
6760 addr0_low = tr32(MAC_ADDR_0_LOW);
6761 addr1_high = tr32(MAC_ADDR_1_HIGH);
6762 addr1_low = tr32(MAC_ADDR_1_LOW);
6763
6764 /* Skip MAC addr 1 if ASF is using it. */
6765 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6766 !(addr1_high == 0 && addr1_low == 0))
6767 skip_mac_1 = 1;
58712ef9 6768 }
986e0aeb
MC		 6769 spin_lock_bh(&tp->lock);
6770 __tg3_set_mac_addr(tp, skip_mac_1);
6771 spin_unlock_bh(&tp->lock);
1da177e4 6772
b9ec6c1b 6773 return err;
1da177e4
LT		 6774}
6775
6776/* tp->lock is held. */
6777static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6778 dma_addr_t mapping, u32 maxlen_flags,
6779 u32 nic_addr)
6780{
6781 tg3_write_mem(tp,
6782 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6783 ((u64) mapping >> 32));
6784 tg3_write_mem(tp,
6785 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6786 ((u64) mapping & 0xffffffff));
6787 tg3_write_mem(tp,
6788 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6789 maxlen_flags);
6790
6791 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6792 tg3_write_mem(tp,
6793 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6794 nic_addr);
6795}
6796
6797static void __tg3_set_rx_mode(struct net_device *);
d244c892 6798static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6799{
6800 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6801 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6802 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6803 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6804 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6805 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6806 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6807 }
6808 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6809 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6810 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6811 u32 val = ec->stats_block_coalesce_usecs;
6812
6813 if (!netif_carrier_ok(tp->dev))
6814 val = 0;
6815
6816 tw32(HOSTCC_STAT_COAL_TICKS, val);
6817 }
6818}
1da177e4 6819
2d31ecaf
MC		 6820/* tp->lock is held. */
6821static void tg3_rings_reset(struct tg3 *tp)
6822{
6823 int i;
6824 u32 txrcb, rxrcb, limit;
6825 struct tg3_napi *tnapi = &tp->napi[0];
6826
6827 /* Disable all transmit rings but the first. */
6828 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6829 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
6830 else
6831 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6832
6833 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6834 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
6835 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
6836 BDINFO_FLAGS_DISABLED);
6837
6838
6839 /* Disable all receive return rings but the first. */
6840 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6841 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
6842 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6843 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
6844 else
6845 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6846
6847 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6848 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
6849 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
6850 BDINFO_FLAGS_DISABLED);
6851
6852 /* Disable interrupts */
6853 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
6854
6855 /* Zero mailbox registers. */
6856 tp->napi[0].tx_prod = 0;
6857 tp->napi[0].tx_cons = 0;
6858 tw32_mailbox(tp->napi[0].prodmbox, 0);
6859 tw32_rx_mbox(tp->napi[0].consmbox, 0);
6860
6861 /* Make sure the NIC-based send BD rings are disabled. */
6862 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6863 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6864 for (i = 0; i < 16; i++)
6865 tw32_tx_mbox(mbox + i * 8, 0);
6866 }
6867
6868 txrcb = NIC_SRAM_SEND_RCB;
6869 rxrcb = NIC_SRAM_RCV_RET_RCB;
6870
6871 /* Clear status block in ram. */
6872 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6873
6874 /* Set status block DMA address */
6875 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6876 ((u64) tnapi->status_mapping >> 32));
6877 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6878 ((u64) tnapi->status_mapping & 0xffffffff));
6879
6880 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
6881 (TG3_TX_RING_SIZE <<
6882 BDINFO_FLAGS_MAXLEN_SHIFT),
6883 NIC_SRAM_TX_BUFFER_DESC);
6884
6885 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
6886 (TG3_RX_RCB_RING_SIZE(tp) <<
6887 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
6888}
6889
1da177e4 6890/* tp->lock is held. */
8e7a22e3 6891static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6892{
6893 u32 val, rdmac_mode;
6894 int i, err, limit;
21f581a5 6895 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 6896
6897 tg3_disable_ints(tp);
6898
6899 tg3_stop_fw(tp);
6900
6901 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6902
6903 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6904 tg3_abort_hw(tp, 1);
1da177e4
LT		 6905 }
6906
dd477003
MC		 6907 if (reset_phy &&
6908 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6909 tg3_phy_reset(tp);
6910
1da177e4
LT		 6911 err = tg3_chip_reset(tp);
6912 if (err)
6913 return err;
6914
6915 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6916
bcb37f6c 6917 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6918 val = tr32(TG3_CPMU_CTRL);
6919 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6920 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6921
6922 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6923 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6924 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6925 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6926
6927 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6928 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6929 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6930 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6931
6932 val = tr32(TG3_CPMU_HST_ACC);
6933 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6934 val |= CPMU_HST_ACC_MACCLK_6_25;
6935 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6936 }
6937
33466d93
MC		 6938 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6939 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6940 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6941 PCIE_PWR_MGMT_L1_THRESH_4MS;
6942 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 6943
6944 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6945 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6946
6947 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC		 6948 }
6949
255ca311
MC		 6950 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6951 val = tr32(TG3_PCIE_LNKCTL);
6952 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6953 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6954 else
6955 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6956 tw32(TG3_PCIE_LNKCTL, val);
6957 }
6958
1da177e4
LT		 6959 /* This works around an issue with Athlon chipsets on
6960 * B3 tigon3 silicon. This bit has no effect on any
6961 * other revision. But do not set this on PCI Express
795d01c5 6962 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6963 */
795d01c5
MC		 6964 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6965 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6966 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6967 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6968 }
1da177e4
LT		 6969
6970 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6971 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6972 val = tr32(TG3PCI_PCISTATE);
6973 val |= PCISTATE_RETRY_SAME_DMA;
6974 tw32(TG3PCI_PCISTATE, val);
6975 }
6976
0d3031d9
MC		 6977 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6978 /* Allow reads and writes to the
6979 * APE register and memory space.
6980 */
6981 val = tr32(TG3PCI_PCISTATE);
6982 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6983 PCISTATE_ALLOW_APE_SHMEM_WR;
6984 tw32(TG3PCI_PCISTATE, val);
6985 }
6986
1da177e4
LT		 6987 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6988 /* Enable some hw fixes. */
6989 val = tr32(TG3PCI_MSI_DATA);
6990 val |= (1 << 26) | (1 << 28) | (1 << 29);
6991 tw32(TG3PCI_MSI_DATA, val);
6992 }
6993
6994 /* Descriptor ring init may make accesses to the
6995 * NIC SRAM area to setup the TX descriptors, so we
6996 * can only do this after the hardware has been
6997 * successfully reset.
6998 */
32d8c572
MC		 6999 err = tg3_init_rings(tp);
7000 if (err)
7001 return err;
1da177e4 7002
9936bcf6 7003 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 7004 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7005 /* This value is determined during the probe time DMA
7006 * engine test, tg3_test_dma.
7007 */
7008 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7009 }
1da177e4
LT		 7010
7011 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7012 GRC_MODE_4X_NIC_SEND_RINGS |
7013 GRC_MODE_NO_TX_PHDR_CSUM |
7014 GRC_MODE_NO_RX_PHDR_CSUM);
7015 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7016
7017 /* Pseudo-header checksum is done by hardware logic and not
7018 * the offload processers, so make the chip do the pseudo-
7019 * header checksums on receive. For transmit it is more
7020 * convenient to do the pseudo-header checksum in software
7021 * as Linux does that on transmit for us in all cases.
7022 */
7023 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7024
7025 tw32(GRC_MODE,
7026 tp->grc_mode |
7027 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7028
7029 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7030 val = tr32(GRC_MISC_CFG);
7031 val &= ~0xff;
7032 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7033 tw32(GRC_MISC_CFG, val);
7034
7035 /* Initialize MBUF/DESC pool. */
cbf46853 7036 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7037 /* Do nothing. */
7038 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7039 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7041 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7042 else
7043 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7044 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7045 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7046 }
1da177e4
LT		 7047 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7048 int fw_len;
7049
077f849d 7050 fw_len = tp->fw_len;
1da177e4
LT		 7051 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7052 tw32(BUFMGR_MB_POOL_ADDR,
7053 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7054 tw32(BUFMGR_MB_POOL_SIZE,
7055 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7056 }
1da177e4 7057
0f893dc6 7058 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7059 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7060 tp->bufmgr_config.mbuf_read_dma_low_water);
7061 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7062 tp->bufmgr_config.mbuf_mac_rx_low_water);
7063 tw32(BUFMGR_MB_HIGH_WATER,
7064 tp->bufmgr_config.mbuf_high_water);
7065 } else {
7066 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7067 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7068 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7069 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7070 tw32(BUFMGR_MB_HIGH_WATER,
7071 tp->bufmgr_config.mbuf_high_water_jumbo);
7072 }
7073 tw32(BUFMGR_DMA_LOW_WATER,
7074 tp->bufmgr_config.dma_low_water);
7075 tw32(BUFMGR_DMA_HIGH_WATER,
7076 tp->bufmgr_config.dma_high_water);
7077
7078 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7079 for (i = 0; i < 2000; i++) {
7080 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7081 break;
7082 udelay(10);
7083 }
7084 if (i >= 2000) {
7085 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7086 tp->dev->name);
7087 return -ENODEV;
7088 }
7089
7090 /* Setup replenish threshold. */
f92905de
MC		 7091 val = tp->rx_pending / 8;
7092 if (val == 0)
7093 val = 1;
7094 else if (val > tp->rx_std_max_post)
7095 val = tp->rx_std_max_post;
b5d3772c
MC		 7096 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7097 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7098 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7099
7100 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7101 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7102 }
f92905de
MC		 7103
7104 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7105
7106 /* Initialize TG3_BDINFO's at:
7107 * RCVDBDI_STD_BD: standard eth size rx ring
7108 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7109 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7110 *
7111 * like so:
7112 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7113 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7114 * ring attribute flags
7115 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7116 *
7117 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7118 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7119 *
7120 * The size of each ring is fixed in the firmware, but the location is
7121 * configurable.
7122 */
7123 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7124 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7125 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7126 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7127 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7128 NIC_SRAM_RX_BUFFER_DESC);
7129
fdb72b38
MC		 7130 /* Disable the mini ring */
7131 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7132 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7133 BDINFO_FLAGS_DISABLED);
7134
fdb72b38
MC		 7135 /* Program the jumbo buffer descriptor ring control
7136 * blocks on those devices that have them.
7137 */
8f666b07 7138 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7139 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7140 /* Setup replenish threshold. */
7141 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7142
0f893dc6 7143 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7144 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7145 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7146 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7147 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7148 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7149 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7150 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7151 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7152 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7153 } else {
7154 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7155 BDINFO_FLAGS_DISABLED);
7156 }
7157
fdb72b38
MC		 7158 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7159 } else
7160 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7161
7162 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7163
21f581a5 7164 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7165 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7166 tpr->rx_std_ptr);
1da177e4 7167
21f581a5
MC		 7168 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7169 tp->rx_jumbo_pending : 0;
1da177e4 7170 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7171 tpr->rx_jmb_ptr);
1da177e4 7172
2d31ecaf
MC		 7173 tg3_rings_reset(tp);
7174
1da177e4 7175 /* Initialize MAC address and backoff seed. */
986e0aeb 7176 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7177
7178 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7179 tw32(MAC_RX_MTU_SIZE,
7180 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7181
7182 /* The slot time is changed by tg3_setup_phy if we
7183 * run at gigabit with half duplex.
7184 */
7185 tw32(MAC_TX_LENGTHS,
7186 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7187 (6 << TX_LENGTHS_IPG_SHIFT) |
7188 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7189
7190 /* Receive rules. */
7191 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7192 tw32(RCVLPC_CONFIG, 0x0181);
7193
7194 /* Calculate RDMAC_MODE setting early, we need it to determine
7195 * the RCVLPC_STATE_ENABLE mask.
7196 */
7197 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7198 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7199 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7200 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7201 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7202
57e6983c 7203 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7204 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7205 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7206 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7207 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7208 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7209
85e94ced
MC		 7210 /* If statement applies to 5705 and 5750 PCI devices only */
7211 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7212 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7213 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7214 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7215 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7216 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7217 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7218 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7219 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7220 }
7221 }
7222
85e94ced
MC		 7223 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7224 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7225
1da177e4 7226 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7227 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7228
7229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7230 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7231 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7232
7233 /* Receive/send statistics. */
1661394e
MC		 7234 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7235 val = tr32(RCVLPC_STATS_ENABLE);
7236 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7237 tw32(RCVLPC_STATS_ENABLE, val);
7238 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7239 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7240 val = tr32(RCVLPC_STATS_ENABLE);
7241 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7242 tw32(RCVLPC_STATS_ENABLE, val);
7243 } else {
7244 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7245 }
7246 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7247 tw32(SNDDATAI_STATSENAB, 0xffffff);
7248 tw32(SNDDATAI_STATSCTRL,
7249 (SNDDATAI_SCTRL_ENABLE |
7250 SNDDATAI_SCTRL_FASTUPD));
7251
7252 /* Setup host coalescing engine. */
7253 tw32(HOSTCC_MODE, 0);
7254 for (i = 0; i < 2000; i++) {
7255 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7256 break;
7257 udelay(10);
7258 }
7259
d244c892 7260 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7261
1da177e4
LT		 7262 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7263 /* Status/statistics block address. See tg3_timer,
7264 * the tg3_periodic_fetch_stats call there, and
7265 * tg3_get_stats to see how this works for 5705/5750 chips.
7266 */
1da177e4
LT		 7267 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7268 ((u64) tp->stats_mapping >> 32));
7269 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7270 ((u64) tp->stats_mapping & 0xffffffff));
7271 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7272
1da177e4 7273 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7274
7275 /* Clear statistics and status block memory areas */
7276 for (i = NIC_SRAM_STATS_BLK;
7277 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7278 i += sizeof(u32)) {
7279 tg3_write_mem(tp, i, 0);
7280 udelay(40);
7281 }
1da177e4
LT		 7282 }
7283
7284 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7285
7286 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7287 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7288 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7289 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7290
c94e3941
MC		 7291 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7292 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7293 /* reset to prevent losing 1st rx packet intermittently */
7294 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7295 udelay(10);
7296 }
7297
3bda1258
MC		 7298 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7299 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7300 else
7301 tp->mac_mode = 0;
7302 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7303 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7304 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7305 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7306 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7307 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7308 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7309 udelay(40);
7310
314fba34 7311 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7312 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7313 * register to preserve the GPIO settings for LOMs. The GPIOs,
7314 * whether used as inputs or outputs, are set by boot code after
7315 * reset.
7316 */
9d26e213 7317 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7318 u32 gpio_mask;
7319
9d26e213
MC		 7320 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7321 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7322 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7323
7324 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7325 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7326 GRC_LCLCTRL_GPIO_OUTPUT3;
7327
af36e6b6
MC		 7328 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7329 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7330
aaf84465 7331 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7332 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7333
7334 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7335 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7336 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7337 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7338 }
1da177e4
LT		 7339 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7340 udelay(100);
7341
1da177e4
LT		 7342 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7343 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7344 udelay(40);
7345 }
7346
7347 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7348 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7349 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7350 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7351 WDMAC_MODE_LNGREAD_ENAB);
7352
85e94ced
MC		 7353 /* If statement applies to 5705 and 5750 PCI devices only */
7354 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7355 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7357 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7358 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7359 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7360 /* nothing */
7361 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7362 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7363 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7364 val |= WDMAC_MODE_RX_ACCEL;
7365 }
7366 }
7367
d9ab5ad1 7368 /* Enable host coalescing bug fix */
321d32a0 7369 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7370 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7371
1da177e4
LT		 7372 tw32_f(WDMAC_MODE, val);
7373 udelay(40);
7374
9974a356
MC		 7375 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7376 u16 pcix_cmd;
7377
7378 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7379 &pcix_cmd);
1da177e4 7380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7381 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7382 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7383 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7384 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7385 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7386 }
9974a356
MC		 7387 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7388 pcix_cmd);
1da177e4
LT		 7389 }
7390
7391 tw32_f(RDMAC_MODE, rdmac_mode);
7392 udelay(40);
7393
7394 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7395 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7396 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7397
7398 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7399 tw32(SNDDATAC_MODE,
7400 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7401 else
7402 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7403
1da177e4
LT		 7404 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7405 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7406 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7407 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7408 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7409 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7410 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7411 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7412
7413 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7414 err = tg3_load_5701_a0_firmware_fix(tp);
7415 if (err)
7416 return err;
7417 }
7418
1da177e4
LT		 7419 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7420 err = tg3_load_tso_firmware(tp);
7421 if (err)
7422 return err;
7423 }
1da177e4
LT		 7424
7425 tp->tx_mode = TX_MODE_ENABLE;
7426 tw32_f(MAC_TX_MODE, tp->tx_mode);
7427 udelay(100);
7428
7429 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7430 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7431 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7432
1da177e4
LT		 7433 tw32_f(MAC_RX_MODE, tp->rx_mode);
7434 udelay(10);
7435
1da177e4
LT		 7436 tw32(MAC_LED_CTRL, tp->led_ctrl);
7437
7438 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7439 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7440 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7441 udelay(10);
7442 }
7443 tw32_f(MAC_RX_MODE, tp->rx_mode);
7444 udelay(10);
7445
7446 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7447 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7448 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7449 /* Set drive transmission level to 1.2V */
7450 /* only if the signal pre-emphasis bit is not set */
7451 val = tr32(MAC_SERDES_CFG);
7452 val &= 0xfffff000;
7453 val |= 0x880;
7454 tw32(MAC_SERDES_CFG, val);
7455 }
7456 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7457 tw32(MAC_SERDES_CFG, 0x616000);
7458 }
7459
7460 /* Prevent chip from dropping frames when flow control
7461 * is enabled.
7462 */
7463 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7464
7465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7466 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7467 /* Use hardware link auto-negotiation */
7468 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7469 }
7470
d4d2c558
MC		 7471 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7472 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7473 u32 tmp;
7474
7475 tmp = tr32(SERDES_RX_CTRL);
7476 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7477 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7478 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7479 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7480 }
7481
dd477003
MC		 7482 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7483 if (tp->link_config.phy_is_low_power) {
7484 tp->link_config.phy_is_low_power = 0;
7485 tp->link_config.speed = tp->link_config.orig_speed;
7486 tp->link_config.duplex = tp->link_config.orig_duplex;
7487 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7488 }
1da177e4 7489
dd477003
MC		 7490 err = tg3_setup_phy(tp, 0);
7491 if (err)
7492 return err;
1da177e4 7493
dd477003 7494 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7495 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7496 u32 tmp;
7497
7498 /* Clear CRC stats. */
7499 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7500 tg3_writephy(tp, MII_TG3_TEST1,
7501 tmp | MII_TG3_TEST1_CRC_EN);
7502 tg3_readphy(tp, 0x14, &tmp);
7503 }
1da177e4
LT		 7504 }
7505 }
7506
7507 __tg3_set_rx_mode(tp->dev);
7508
7509 /* Initialize receive rules. */
7510 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7511 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7512 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7513 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7514
4cf78e4f 7515 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7516 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7517 limit = 8;
7518 else
7519 limit = 16;
7520 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7521 limit -= 4;
7522 switch (limit) {
7523 case 16:
7524 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7525 case 15:
7526 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7527 case 14:
7528 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7529 case 13:
7530 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7531 case 12:
7532 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7533 case 11:
7534 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7535 case 10:
7536 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7537 case 9:
7538 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7539 case 8:
7540 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7541 case 7:
7542 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7543 case 6:
7544 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7545 case 5:
7546 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7547 case 4:
7548 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7549 case 3:
7550 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7551 case 2:
7552 case 1:
7553
7554 default:
7555 break;
855e1111 7556 }
1da177e4 7557
9ce768ea
MC		 7558 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7559 /* Write our heartbeat update interval to APE. */
7560 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7561 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7562
1da177e4
LT		 7563 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7564
1da177e4
LT		 7565 return 0;
7566}
7567
7568/* Called at device open time to get the chip ready for
7569 * packet processing. Invoked with tp->lock held.
7570 */
8e7a22e3 7571static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7572{
1da177e4
LT		 7573 tg3_switch_clocks(tp);
7574
7575 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7576
2f751b67 7577 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7578}
7579
7580#define TG3_STAT_ADD32(PSTAT, REG) \
7581do { u32 __val = tr32(REG); \
7582 (PSTAT)->low += __val; \
7583 if ((PSTAT)->low < __val) \
7584 (PSTAT)->high += 1; \
7585} while (0)
7586
7587static void tg3_periodic_fetch_stats(struct tg3 *tp)
7588{
7589 struct tg3_hw_stats *sp = tp->hw_stats;
7590
7591 if (!netif_carrier_ok(tp->dev))
7592 return;
7593
7594 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7595 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7596 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7597 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7598 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7599 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7600 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7601 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7602 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7603 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7604 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7605 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7606 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7607
7608 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7609 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7610 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7611 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7612 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7613 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7614 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7615 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7616 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7617 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7618 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7619 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7620 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7621 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7622
7623 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7624 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7625 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7626}
7627
7628static void tg3_timer(unsigned long __opaque)
7629{
7630 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7631
f475f163
MC		 7632 if (tp->irq_sync)
7633 goto restart_timer;
7634
f47c11ee 7635 spin_lock(&tp->lock);
1da177e4 7636
fac9b83e
DM		 7637 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7638 /* All of this garbage is because when using non-tagged
7639 * IRQ status the mailbox/status_block protocol the chip
7640 * uses with the cpu is race prone.
7641 */
898a56f8 7642 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7643 tw32(GRC_LOCAL_CTRL,
7644 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7645 } else {
7646 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7647 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7648 }
1da177e4 7649
fac9b83e
DM		 7650 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7651 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7652 spin_unlock(&tp->lock);
fac9b83e
DM		 7653 schedule_work(&tp->reset_task);
7654 return;
7655 }
1da177e4
LT		 7656 }
7657
1da177e4
LT		 7658 /* This part only runs once per second. */
7659 if (!--tp->timer_counter) {
fac9b83e
DM		 7660 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7661 tg3_periodic_fetch_stats(tp);
7662
1da177e4
LT		 7663 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7664 u32 mac_stat;
7665 int phy_event;
7666
7667 mac_stat = tr32(MAC_STATUS);
7668
7669 phy_event = 0;
7670 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7671 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7672 phy_event = 1;
7673 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7674 phy_event = 1;
7675
7676 if (phy_event)
7677 tg3_setup_phy(tp, 0);
7678 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7679 u32 mac_stat = tr32(MAC_STATUS);
7680 int need_setup = 0;
7681
7682 if (netif_carrier_ok(tp->dev) &&
7683 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7684 need_setup = 1;
7685 }
7686 if (! netif_carrier_ok(tp->dev) &&
7687 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7688 MAC_STATUS_SIGNAL_DET))) {
7689 need_setup = 1;
7690 }
7691 if (need_setup) {
3d3ebe74
MC		 7692 if (!tp->serdes_counter) {
7693 tw32_f(MAC_MODE,
7694 (tp->mac_mode &
7695 ~MAC_MODE_PORT_MODE_MASK));
7696 udelay(40);
7697 tw32_f(MAC_MODE, tp->mac_mode);
7698 udelay(40);
7699 }
1da177e4
LT		 7700 tg3_setup_phy(tp, 0);
7701 }
747e8f8b
MC		 7702 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7703 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7704
7705 tp->timer_counter = tp->timer_multiplier;
7706 }
7707
130b8e4d
MC		 7708 /* Heartbeat is only sent once every 2 seconds.
7709 *
7710 * The heartbeat is to tell the ASF firmware that the host
7711 * driver is still alive. In the event that the OS crashes,
7712 * ASF needs to reset the hardware to free up the FIFO space
7713 * that may be filled with rx packets destined for the host.
7714 * If the FIFO is full, ASF will no longer function properly.
7715 *
7716 * Unintended resets have been reported on real time kernels
7717 * where the timer doesn't run on time. Netpoll will also have
7718 * same problem.
7719 *
7720 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7721 * to check the ring condition when the heartbeat is expiring
7722 * before doing the reset. This will prevent most unintended
7723 * resets.
7724 */
1da177e4 7725 if (!--tp->asf_counter) {
bc7959b2
MC		 7726 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7727 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7728 tg3_wait_for_event_ack(tp);
7729
bbadf503 7730 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7731 FWCMD_NICDRV_ALIVE3);
bbadf503 7732 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7733 /* 5 seconds timeout */
bbadf503 7734 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7735
7736 tg3_generate_fw_event(tp);
1da177e4
LT		 7737 }
7738 tp->asf_counter = tp->asf_multiplier;
7739 }
7740
f47c11ee 7741 spin_unlock(&tp->lock);
1da177e4 7742
f475f163 7743restart_timer:
1da177e4
LT		 7744 tp->timer.expires = jiffies + tp->timer_offset;
7745 add_timer(&tp->timer);
7746}
7747
81789ef5 7748static int tg3_request_irq(struct tg3 *tp)
fcfa0a32 7749{
7d12e780 7750 irq_handler_t fn;
fcfa0a32 7751 unsigned long flags;
09943a18 7752 char *name = tp->dev->name;
fcfa0a32
MC		 7753
7754 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7755 fn = tg3_msi;
7756 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7757 fn = tg3_msi_1shot;
1fb9df5d 7758 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7759 } else {
7760 fn = tg3_interrupt;
7761 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7762 fn = tg3_interrupt_tagged;
1fb9df5d 7763 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 7764 }
09943a18 7765 return request_irq(tp->pdev->irq, fn, flags, name, &tp->napi[0]);
fcfa0a32
MC		 7766}
7767
7938109f
MC		 7768static int tg3_test_interrupt(struct tg3 *tp)
7769{
09943a18 7770 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 7771 struct net_device *dev = tp->dev;
b16250e3 7772 int err, i, intr_ok = 0;
7938109f 7773
d4bc3927
MC		 7774 if (!netif_running(dev))
7775 return -ENODEV;
7776
7938109f
MC		 7777 tg3_disable_ints(tp);
7778
09943a18 7779 free_irq(tp->pdev->irq, tnapi);
7938109f
MC		 7780
7781 err = request_irq(tp->pdev->irq, tg3_test_isr,
09943a18 7782 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 7783 if (err)
7784 return err;
7785
898a56f8 7786 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7787 tg3_enable_ints(tp);
7788
7789 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 7790 tnapi->coal_now);
7938109f
MC		 7791
7792 for (i = 0; i < 5; i++) {
b16250e3
MC		 7793 u32 int_mbox, misc_host_ctrl;
7794
898a56f8 7795 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 7796 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7797
7798 if ((int_mbox != 0) ||
7799 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7800 intr_ok = 1;
7938109f 7801 break;
b16250e3
MC		 7802 }
7803
7938109f
MC		 7804 msleep(10);
7805 }
7806
7807 tg3_disable_ints(tp);
7808
09943a18 7809 free_irq(tp->pdev->irq, tnapi);
6aa20a22 7810
fcfa0a32 7811 err = tg3_request_irq(tp);
7938109f
MC		 7812
7813 if (err)
7814 return err;
7815
b16250e3 7816 if (intr_ok)
7938109f
MC		 7817 return 0;
7818
7819 return -EIO;
7820}
7821
7822/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7823 * successfully restored
7824 */
7825static int tg3_test_msi(struct tg3 *tp)
7826{
7938109f
MC		 7827 int err;
7828 u16 pci_cmd;
7829
7830 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7831 return 0;
7832
7833 /* Turn off SERR reporting in case MSI terminates with Master
7834 * Abort.
7835 */
7836 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7837 pci_write_config_word(tp->pdev, PCI_COMMAND,
7838 pci_cmd & ~PCI_COMMAND_SERR);
7839
7840 err = tg3_test_interrupt(tp);
7841
7842 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7843
7844 if (!err)
7845 return 0;
7846
7847 /* other failures */
7848 if (err != -EIO)
7849 return err;
7850
7851 /* MSI test failed, go back to INTx mode */
7852 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7853 "switching to INTx mode. Please report this failure to "
7854 "the PCI maintainer and include system chipset information.\n",
7855 tp->dev->name);
7856
09943a18
MC		 7857 free_irq(tp->pdev->irq, &tp->napi[0]);
7858
7938109f
MC		 7859 pci_disable_msi(tp->pdev);
7860
7861 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7862
fcfa0a32 7863 err = tg3_request_irq(tp);
7938109f
MC		 7864 if (err)
7865 return err;
7866
7867 /* Need to reset the chip because the MSI cycle may have terminated
7868 * with Master Abort.
7869 */
f47c11ee 7870 tg3_full_lock(tp, 1);
7938109f 7871
944d980e 7872 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7873 err = tg3_init_hw(tp, 1);
7938109f 7874
f47c11ee 7875 tg3_full_unlock(tp);
7938109f
MC		 7876
7877 if (err)
09943a18 7878 free_irq(tp->pdev->irq, &tp->napi[0]);
7938109f
MC		 7879
7880 return err;
7881}
7882
9e9fd12d
MC		 7883static int tg3_request_firmware(struct tg3 *tp)
7884{
7885 const __be32 *fw_data;
7886
7887 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7888 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7889 tp->dev->name, tp->fw_needed);
7890 return -ENOENT;
7891 }
7892
7893 fw_data = (void *)tp->fw->data;
7894
7895 /* Firmware blob starts with version numbers, followed by
7896 * start address and _full_ length including BSS sections
7897 * (which must be longer than the actual data, of course
7898 */
7899
7900 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7901 if (tp->fw_len < (tp->fw->size - 12)) {
7902 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7903 tp->dev->name, tp->fw_len, tp->fw_needed);
7904 release_firmware(tp->fw);
7905 tp->fw = NULL;
7906 return -EINVAL;
7907 }
7908
7909 /* We no longer need firmware; we have it. */
7910 tp->fw_needed = NULL;
7911 return 0;
7912}
7913
07b0173c
MC		 7914static void tg3_ints_init(struct tg3 *tp)
7915{
7916 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7917 /* All MSI supporting chips should support tagged
7918 * status. Assert that this is the case.
7919 */
7920 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7921 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7922 "Not using MSI.\n", tp->dev->name);
7923 } else if (pci_enable_msi(tp->pdev) == 0) {
7924 u32 msi_mode;
7925
7926 msi_mode = tr32(MSGINT_MODE);
7927 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7928 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7929 }
7930 }
7931}
7932
7933static void tg3_ints_fini(struct tg3 *tp)
7934{
7935 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7936 pci_disable_msi(tp->pdev);
7937 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7938 }
7939}
7940
1da177e4
LT		 7941static int tg3_open(struct net_device *dev)
7942{
7943 struct tg3 *tp = netdev_priv(dev);
7944 int err;
7945
9e9fd12d
MC		 7946 if (tp->fw_needed) {
7947 err = tg3_request_firmware(tp);
7948 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7949 if (err)
7950 return err;
7951 } else if (err) {
7952 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7953 tp->dev->name);
7954 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7955 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7956 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7957 tp->dev->name);
7958 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7959 }
7960 }
7961
c49a1561
MC		 7962 netif_carrier_off(tp->dev);
7963
bc1c7567 7964 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7965 if (err)
bc1c7567 7966 return err;
2f751b67
MC		 7967
7968 tg3_full_lock(tp, 0);
bc1c7567 7969
1da177e4
LT		 7970 tg3_disable_ints(tp);
7971 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7972
f47c11ee 7973 tg3_full_unlock(tp);
1da177e4
LT		 7974
7975 /* The placement of this call is tied
7976 * to the setup and use of Host TX descriptors.
7977 */
7978 err = tg3_alloc_consistent(tp);
7979 if (err)
7980 return err;
7981
07b0173c 7982 tg3_ints_init(tp);
88b06bc2 7983
8ef0442f 7984 napi_enable(&tp->napi[0].napi);
1da177e4 7985
07b0173c 7986 err = tg3_request_irq(tp);
1da177e4 7987
07b0173c
MC		 7988 if (err)
7989 goto err_out1;
bea3348e 7990
f47c11ee 7991 tg3_full_lock(tp, 0);
1da177e4 7992
8e7a22e3 7993 err = tg3_init_hw(tp, 1);
1da177e4 7994 if (err) {
944d980e 7995 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7996 tg3_free_rings(tp);
7997 } else {
fac9b83e
DM		 7998 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7999 tp->timer_offset = HZ;
8000 else
8001 tp->timer_offset = HZ / 10;
8002
8003 BUG_ON(tp->timer_offset > HZ);
8004 tp->timer_counter = tp->timer_multiplier =
8005 (HZ / tp->timer_offset);
8006 tp->asf_counter = tp->asf_multiplier =
28fbef78 8007 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8008
8009 init_timer(&tp->timer);
8010 tp->timer.expires = jiffies + tp->timer_offset;
8011 tp->timer.data = (unsigned long) tp;
8012 tp->timer.function = tg3_timer;
1da177e4
LT		 8013 }
8014
f47c11ee 8015 tg3_full_unlock(tp);
1da177e4 8016
07b0173c
MC		 8017 if (err)
8018 goto err_out2;
1da177e4 8019
7938109f
MC		 8020 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8021 err = tg3_test_msi(tp);
fac9b83e 8022
7938109f 8023 if (err) {
f47c11ee 8024 tg3_full_lock(tp, 0);
944d980e 8025 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8026 tg3_free_rings(tp);
f47c11ee 8027 tg3_full_unlock(tp);
7938109f 8028
07b0173c 8029 goto err_out1;
7938109f 8030 }
fcfa0a32
MC		 8031
8032 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8033 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 8034 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8035
b5d3772c
MC		 8036 tw32(PCIE_TRANSACTION_CFG,
8037 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 8038 }
8039 }
7938109f
MC		 8040 }
8041
b02fd9e3
MC		 8042 tg3_phy_start(tp);
8043
f47c11ee 8044 tg3_full_lock(tp, 0);
1da177e4 8045
7938109f
MC		 8046 add_timer(&tp->timer);
8047 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8048 tg3_enable_ints(tp);
8049
f47c11ee 8050 tg3_full_unlock(tp);
1da177e4
LT		 8051
8052 netif_start_queue(dev);
8053
8054 return 0;
07b0173c
MC		 8055
8056err_out2:
09943a18 8057 free_irq(tp->pdev->irq, &tp->napi[0]);
07b0173c
MC		 8058
8059err_out1:
8ef0442f 8060 napi_disable(&tp->napi[0].napi);
07b0173c
MC		 8061 tg3_ints_fini(tp);
8062 tg3_free_consistent(tp);
8063 return err;
1da177e4
LT		 8064}
8065
8066#if 0
8067/*static*/ void tg3_dump_state(struct tg3 *tp)
8068{
8069 u32 val32, val32_2, val32_3, val32_4, val32_5;
8070 u16 val16;
8071 int i;
898a56f8 8072 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8073
8074 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8075 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8076 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8077 val16, val32);
8078
8079 /* MAC block */
8080 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8081 tr32(MAC_MODE), tr32(MAC_STATUS));
8082 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8083 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8084 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8085 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8086 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8087 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8088
8089 /* Send data initiator control block */
8090 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8091 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8092 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8093 tr32(SNDDATAI_STATSCTRL));
8094
8095 /* Send data completion control block */
8096 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8097
8098 /* Send BD ring selector block */
8099 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8100 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8101
8102 /* Send BD initiator control block */
8103 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8104 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8105
8106 /* Send BD completion control block */
8107 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8108
8109 /* Receive list placement control block */
8110 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8111 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8112 printk(" RCVLPC_STATSCTRL[%08x]\n",
8113 tr32(RCVLPC_STATSCTRL));
8114
8115 /* Receive data and receive BD initiator control block */
8116 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8117 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8118
8119 /* Receive data completion control block */
8120 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8121 tr32(RCVDCC_MODE));
8122
8123 /* Receive BD initiator control block */
8124 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8125 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8126
8127 /* Receive BD completion control block */
8128 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8129 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8130
8131 /* Receive list selector control block */
8132 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8133 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8134
8135 /* Mbuf cluster free block */
8136 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8137 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8138
8139 /* Host coalescing control block */
8140 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8141 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8142 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8143 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8144 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8145 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8146 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8147 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8148 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8149 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8150 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8151 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8152
8153 /* Memory arbiter control block */
8154 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8155 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8156
8157 /* Buffer manager control block */
8158 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8159 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8160 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8161 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8162 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8163 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8164 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8165 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8166
8167 /* Read DMA control block */
8168 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8169 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8170
8171 /* Write DMA control block */
8172 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8173 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8174
8175 /* DMA completion block */
8176 printk("DEBUG: DMAC_MODE[%08x]\n",
8177 tr32(DMAC_MODE));
8178
8179 /* GRC block */
8180 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8181 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8182 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8183 tr32(GRC_LOCAL_CTRL));
8184
8185 /* TG3_BDINFOs */
8186 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8187 tr32(RCVDBDI_JUMBO_BD + 0x0),
8188 tr32(RCVDBDI_JUMBO_BD + 0x4),
8189 tr32(RCVDBDI_JUMBO_BD + 0x8),
8190 tr32(RCVDBDI_JUMBO_BD + 0xc));
8191 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8192 tr32(RCVDBDI_STD_BD + 0x0),
8193 tr32(RCVDBDI_STD_BD + 0x4),
8194 tr32(RCVDBDI_STD_BD + 0x8),
8195 tr32(RCVDBDI_STD_BD + 0xc));
8196 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8197 tr32(RCVDBDI_MINI_BD + 0x0),
8198 tr32(RCVDBDI_MINI_BD + 0x4),
8199 tr32(RCVDBDI_MINI_BD + 0x8),
8200 tr32(RCVDBDI_MINI_BD + 0xc));
8201
8202 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8203 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8204 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8205 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8206 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8207 val32, val32_2, val32_3, val32_4);
8208
8209 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8210 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8211 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8212 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8213 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8214 val32, val32_2, val32_3, val32_4);
8215
8216 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8217 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8218 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8219 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8220 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8221 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8222 val32, val32_2, val32_3, val32_4, val32_5);
8223
8224 /* SW status block */
898a56f8
MC		 8225 printk(KERN_DEBUG
8226 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8227 sblk->status,
8228 sblk->status_tag,
8229 sblk->rx_jumbo_consumer,
8230 sblk->rx_consumer,
8231 sblk->rx_mini_consumer,
8232 sblk->idx[0].rx_producer,
8233 sblk->idx[0].tx_consumer);
1da177e4
LT		 8234
8235 /* SW statistics block */
8236 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8237 ((u32 *)tp->hw_stats)[0],
8238 ((u32 *)tp->hw_stats)[1],
8239 ((u32 *)tp->hw_stats)[2],
8240 ((u32 *)tp->hw_stats)[3]);
8241
8242 /* Mailboxes */
8243 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8244 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8245 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8246 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8247 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8248
8249 /* NIC side send descriptors. */
8250 for (i = 0; i < 6; i++) {
8251 unsigned long txd;
8252
8253 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8254 + (i * sizeof(struct tg3_tx_buffer_desc));
8255 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8256 i,
8257 readl(txd + 0x0), readl(txd + 0x4),
8258 readl(txd + 0x8), readl(txd + 0xc));
8259 }
8260
8261 /* NIC side RX descriptors. */
8262 for (i = 0; i < 6; i++) {
8263 unsigned long rxd;
8264
8265 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8266 + (i * sizeof(struct tg3_rx_buffer_desc));
8267 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8268 i,
8269 readl(rxd + 0x0), readl(rxd + 0x4),
8270 readl(rxd + 0x8), readl(rxd + 0xc));
8271 rxd += (4 * sizeof(u32));
8272 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8273 i,
8274 readl(rxd + 0x0), readl(rxd + 0x4),
8275 readl(rxd + 0x8), readl(rxd + 0xc));
8276 }
8277
8278 for (i = 0; i < 6; i++) {
8279 unsigned long rxd;
8280
8281 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8282 + (i * sizeof(struct tg3_rx_buffer_desc));
8283 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8284 i,
8285 readl(rxd + 0x0), readl(rxd + 0x4),
8286 readl(rxd + 0x8), readl(rxd + 0xc));
8287 rxd += (4 * sizeof(u32));
8288 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8289 i,
8290 readl(rxd + 0x0), readl(rxd + 0x4),
8291 readl(rxd + 0x8), readl(rxd + 0xc));
8292 }
8293}
8294#endif
8295
8296static struct net_device_stats *tg3_get_stats(struct net_device *);
8297static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8298
8299static int tg3_close(struct net_device *dev)
8300{
8301 struct tg3 *tp = netdev_priv(dev);
8302
8ef0442f 8303 napi_disable(&tp->napi[0].napi);
28e53bdd 8304 cancel_work_sync(&tp->reset_task);
7faa006f 8305
1da177e4
LT		 8306 netif_stop_queue(dev);
8307
8308 del_timer_sync(&tp->timer);
8309
f47c11ee 8310 tg3_full_lock(tp, 1);
1da177e4
LT		 8311#if 0
8312 tg3_dump_state(tp);
8313#endif
8314
8315 tg3_disable_ints(tp);
8316
944d980e 8317 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8318 tg3_free_rings(tp);
5cf64b8a 8319 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8320
f47c11ee 8321 tg3_full_unlock(tp);
1da177e4 8322
09943a18 8323 free_irq(tp->pdev->irq, &tp->napi[0]);
07b0173c
MC		 8324
8325 tg3_ints_fini(tp);
1da177e4
LT		 8326
8327 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8328 sizeof(tp->net_stats_prev));
8329 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8330 sizeof(tp->estats_prev));
8331
8332 tg3_free_consistent(tp);
8333
bc1c7567
MC		 8334 tg3_set_power_state(tp, PCI_D3hot);
8335
8336 netif_carrier_off(tp->dev);
8337
1da177e4
LT		 8338 return 0;
8339}
8340
8341static inline unsigned long get_stat64(tg3_stat64_t *val)
8342{
8343 unsigned long ret;
8344
8345#if (BITS_PER_LONG == 32)
8346 ret = val->low;
8347#else
8348 ret = ((u64)val->high << 32) | ((u64)val->low);
8349#endif
8350 return ret;
8351}
8352
816f8b86
SB		 8353static inline u64 get_estat64(tg3_stat64_t *val)
8354{
8355 return ((u64)val->high << 32) | ((u64)val->low);
8356}
8357
1da177e4
LT		 8358static unsigned long calc_crc_errors(struct tg3 *tp)
8359{
8360 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8361
8362 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8363 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8365 u32 val;
8366
f47c11ee 8367 spin_lock_bh(&tp->lock);
569a5df8
MC		 8368 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8369 tg3_writephy(tp, MII_TG3_TEST1,
8370 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8371 tg3_readphy(tp, 0x14, &val);
8372 } else
8373 val = 0;
f47c11ee 8374 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8375
8376 tp->phy_crc_errors += val;
8377
8378 return tp->phy_crc_errors;
8379 }
8380
8381 return get_stat64(&hw_stats->rx_fcs_errors);
8382}
8383
8384#define ESTAT_ADD(member) \
8385 estats->member = old_estats->member + \
816f8b86 8386 get_estat64(&hw_stats->member)
1da177e4
LT		 8387
8388static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8389{
8390 struct tg3_ethtool_stats *estats = &tp->estats;
8391 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8392 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8393
8394 if (!hw_stats)
8395 return old_estats;
8396
8397 ESTAT_ADD(rx_octets);
8398 ESTAT_ADD(rx_fragments);
8399 ESTAT_ADD(rx_ucast_packets);
8400 ESTAT_ADD(rx_mcast_packets);
8401 ESTAT_ADD(rx_bcast_packets);
8402 ESTAT_ADD(rx_fcs_errors);
8403 ESTAT_ADD(rx_align_errors);
8404 ESTAT_ADD(rx_xon_pause_rcvd);
8405 ESTAT_ADD(rx_xoff_pause_rcvd);
8406 ESTAT_ADD(rx_mac_ctrl_rcvd);
8407 ESTAT_ADD(rx_xoff_entered);
8408 ESTAT_ADD(rx_frame_too_long_errors);
8409 ESTAT_ADD(rx_jabbers);
8410 ESTAT_ADD(rx_undersize_packets);
8411 ESTAT_ADD(rx_in_length_errors);
8412 ESTAT_ADD(rx_out_length_errors);
8413 ESTAT_ADD(rx_64_or_less_octet_packets);
8414 ESTAT_ADD(rx_65_to_127_octet_packets);
8415 ESTAT_ADD(rx_128_to_255_octet_packets);
8416 ESTAT_ADD(rx_256_to_511_octet_packets);
8417 ESTAT_ADD(rx_512_to_1023_octet_packets);
8418 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8419 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8420 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8421 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8422 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8423
8424 ESTAT_ADD(tx_octets);
8425 ESTAT_ADD(tx_collisions);
8426 ESTAT_ADD(tx_xon_sent);
8427 ESTAT_ADD(tx_xoff_sent);
8428 ESTAT_ADD(tx_flow_control);
8429 ESTAT_ADD(tx_mac_errors);
8430 ESTAT_ADD(tx_single_collisions);
8431 ESTAT_ADD(tx_mult_collisions);
8432 ESTAT_ADD(tx_deferred);
8433 ESTAT_ADD(tx_excessive_collisions);
8434 ESTAT_ADD(tx_late_collisions);
8435 ESTAT_ADD(tx_collide_2times);
8436 ESTAT_ADD(tx_collide_3times);
8437 ESTAT_ADD(tx_collide_4times);
8438 ESTAT_ADD(tx_collide_5times);
8439 ESTAT_ADD(tx_collide_6times);
8440 ESTAT_ADD(tx_collide_7times);
8441 ESTAT_ADD(tx_collide_8times);
8442 ESTAT_ADD(tx_collide_9times);
8443 ESTAT_ADD(tx_collide_10times);
8444 ESTAT_ADD(tx_collide_11times);
8445 ESTAT_ADD(tx_collide_12times);
8446 ESTAT_ADD(tx_collide_13times);
8447 ESTAT_ADD(tx_collide_14times);
8448 ESTAT_ADD(tx_collide_15times);
8449 ESTAT_ADD(tx_ucast_packets);
8450 ESTAT_ADD(tx_mcast_packets);
8451 ESTAT_ADD(tx_bcast_packets);
8452 ESTAT_ADD(tx_carrier_sense_errors);
8453 ESTAT_ADD(tx_discards);
8454 ESTAT_ADD(tx_errors);
8455
8456 ESTAT_ADD(dma_writeq_full);
8457 ESTAT_ADD(dma_write_prioq_full);
8458 ESTAT_ADD(rxbds_empty);
8459 ESTAT_ADD(rx_discards);
8460 ESTAT_ADD(rx_errors);
8461 ESTAT_ADD(rx_threshold_hit);
8462
8463 ESTAT_ADD(dma_readq_full);
8464 ESTAT_ADD(dma_read_prioq_full);
8465 ESTAT_ADD(tx_comp_queue_full);
8466
8467 ESTAT_ADD(ring_set_send_prod_index);
8468 ESTAT_ADD(ring_status_update);
8469 ESTAT_ADD(nic_irqs);
8470 ESTAT_ADD(nic_avoided_irqs);
8471 ESTAT_ADD(nic_tx_threshold_hit);
8472
8473 return estats;
8474}
8475
8476static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8477{
8478 struct tg3 *tp = netdev_priv(dev);
8479 struct net_device_stats *stats = &tp->net_stats;
8480 struct net_device_stats *old_stats = &tp->net_stats_prev;
8481 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8482
8483 if (!hw_stats)
8484 return old_stats;
8485
8486 stats->rx_packets = old_stats->rx_packets +
8487 get_stat64(&hw_stats->rx_ucast_packets) +
8488 get_stat64(&hw_stats->rx_mcast_packets) +
8489 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8490
1da177e4
LT		 8491 stats->tx_packets = old_stats->tx_packets +
8492 get_stat64(&hw_stats->tx_ucast_packets) +
8493 get_stat64(&hw_stats->tx_mcast_packets) +
8494 get_stat64(&hw_stats->tx_bcast_packets);
8495
8496 stats->rx_bytes = old_stats->rx_bytes +
8497 get_stat64(&hw_stats->rx_octets);
8498 stats->tx_bytes = old_stats->tx_bytes +
8499 get_stat64(&hw_stats->tx_octets);
8500
8501 stats->rx_errors = old_stats->rx_errors +
4f63b877 8502 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8503 stats->tx_errors = old_stats->tx_errors +
8504 get_stat64(&hw_stats->tx_errors) +
8505 get_stat64(&hw_stats->tx_mac_errors) +
8506 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8507 get_stat64(&hw_stats->tx_discards);
8508
8509 stats->multicast = old_stats->multicast +
8510 get_stat64(&hw_stats->rx_mcast_packets);
8511 stats->collisions = old_stats->collisions +
8512 get_stat64(&hw_stats->tx_collisions);
8513
8514 stats->rx_length_errors = old_stats->rx_length_errors +
8515 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8516 get_stat64(&hw_stats->rx_undersize_packets);
8517
8518 stats->rx_over_errors = old_stats->rx_over_errors +
8519 get_stat64(&hw_stats->rxbds_empty);
8520 stats->rx_frame_errors = old_stats->rx_frame_errors +
8521 get_stat64(&hw_stats->rx_align_errors);
8522 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8523 get_stat64(&hw_stats->tx_discards);
8524 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8525 get_stat64(&hw_stats->tx_carrier_sense_errors);
8526
8527 stats->rx_crc_errors = old_stats->rx_crc_errors +
8528 calc_crc_errors(tp);
8529
4f63b877
JL		 8530 stats->rx_missed_errors = old_stats->rx_missed_errors +
8531 get_stat64(&hw_stats->rx_discards);
8532
1da177e4
LT		 8533 return stats;
8534}
8535
8536static inline u32 calc_crc(unsigned char *buf, int len)
8537{
8538 u32 reg;
8539 u32 tmp;
8540 int j, k;
8541
8542 reg = 0xffffffff;
8543
8544 for (j = 0; j < len; j++) {
8545 reg ^= buf[j];
8546
8547 for (k = 0; k < 8; k++) {
8548 tmp = reg & 0x01;
8549
8550 reg >>= 1;
8551
8552 if (tmp) {
8553 reg ^= 0xedb88320;
8554 }
8555 }
8556 }
8557
8558 return ~reg;
8559}
8560
8561static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8562{
8563 /* accept or reject all multicast frames */
8564 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8565 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8566 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8567 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8568}
8569
8570static void __tg3_set_rx_mode(struct net_device *dev)
8571{
8572 struct tg3 *tp = netdev_priv(dev);
8573 u32 rx_mode;
8574
8575 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8576 RX_MODE_KEEP_VLAN_TAG);
8577
8578 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8579 * flag clear.
8580 */
8581#if TG3_VLAN_TAG_USED
8582 if (!tp->vlgrp &&
8583 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8584 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8585#else
8586 /* By definition, VLAN is disabled always in this
8587 * case.
8588 */
8589 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8590 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8591#endif
8592
8593 if (dev->flags & IFF_PROMISC) {
8594 /* Promiscuous mode. */
8595 rx_mode |= RX_MODE_PROMISC;
8596 } else if (dev->flags & IFF_ALLMULTI) {
8597 /* Accept all multicast. */
8598 tg3_set_multi (tp, 1);
8599 } else if (dev->mc_count < 1) {
8600 /* Reject all multicast. */
8601 tg3_set_multi (tp, 0);
8602 } else {
8603 /* Accept one or more multicast(s). */
8604 struct dev_mc_list *mclist;
8605 unsigned int i;
8606 u32 mc_filter[4] = { 0, };
8607 u32 regidx;
8608 u32 bit;
8609 u32 crc;
8610
8611 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8612 i++, mclist = mclist->next) {
8613
8614 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8615 bit = ~crc & 0x7f;
8616 regidx = (bit & 0x60) >> 5;
8617 bit &= 0x1f;
8618 mc_filter[regidx] |= (1 << bit);
8619 }
8620
8621 tw32(MAC_HASH_REG_0, mc_filter[0]);
8622 tw32(MAC_HASH_REG_1, mc_filter[1]);
8623 tw32(MAC_HASH_REG_2, mc_filter[2]);
8624 tw32(MAC_HASH_REG_3, mc_filter[3]);
8625 }
8626
8627 if (rx_mode != tp->rx_mode) {
8628 tp->rx_mode = rx_mode;
8629 tw32_f(MAC_RX_MODE, rx_mode);
8630 udelay(10);
8631 }
8632}
8633
8634static void tg3_set_rx_mode(struct net_device *dev)
8635{
8636 struct tg3 *tp = netdev_priv(dev);
8637
e75f7c90
MC		 8638 if (!netif_running(dev))
8639 return;
8640
f47c11ee 8641 tg3_full_lock(tp, 0);
1da177e4 8642 __tg3_set_rx_mode(dev);
f47c11ee 8643 tg3_full_unlock(tp);
1da177e4
LT		 8644}
8645
8646#define TG3_REGDUMP_LEN (32 * 1024)
8647
8648static int tg3_get_regs_len(struct net_device *dev)
8649{
8650 return TG3_REGDUMP_LEN;
8651}
8652
8653static void tg3_get_regs(struct net_device *dev,
8654 struct ethtool_regs *regs, void *_p)
8655{
8656 u32 *p = _p;
8657 struct tg3 *tp = netdev_priv(dev);
8658 u8 *orig_p = _p;
8659 int i;
8660
8661 regs->version = 0;
8662
8663 memset(p, 0, TG3_REGDUMP_LEN);
8664
bc1c7567
MC		 8665 if (tp->link_config.phy_is_low_power)
8666 return;
8667
f47c11ee 8668 tg3_full_lock(tp, 0);
1da177e4
LT		 8669
8670#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8671#define GET_REG32_LOOP(base,len) \
8672do { p = (u32 *)(orig_p + (base)); \
8673 for (i = 0; i < len; i += 4) \
8674 __GET_REG32((base) + i); \
8675} while (0)
8676#define GET_REG32_1(reg) \
8677do { p = (u32 *)(orig_p + (reg)); \
8678 __GET_REG32((reg)); \
8679} while (0)
8680
8681 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8682 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8683 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8684 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8685 GET_REG32_1(SNDDATAC_MODE);
8686 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8687 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8688 GET_REG32_1(SNDBDC_MODE);
8689 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8690 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8691 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8692 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8693 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8694 GET_REG32_1(RCVDCC_MODE);
8695 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8696 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8697 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8698 GET_REG32_1(MBFREE_MODE);
8699 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8700 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8701 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8702 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8703 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8704 GET_REG32_1(RX_CPU_MODE);
8705 GET_REG32_1(RX_CPU_STATE);
8706 GET_REG32_1(RX_CPU_PGMCTR);
8707 GET_REG32_1(RX_CPU_HWBKPT);
8708 GET_REG32_1(TX_CPU_MODE);
8709 GET_REG32_1(TX_CPU_STATE);
8710 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8711 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8712 GET_REG32_LOOP(FTQ_RESET, 0x120);
8713 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8714 GET_REG32_1(DMAC_MODE);
8715 GET_REG32_LOOP(GRC_MODE, 0x4c);
8716 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8717 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8718
8719#undef __GET_REG32
8720#undef GET_REG32_LOOP
8721#undef GET_REG32_1
8722
f47c11ee 8723 tg3_full_unlock(tp);
1da177e4
LT		 8724}
8725
8726static int tg3_get_eeprom_len(struct net_device *dev)
8727{
8728 struct tg3 *tp = netdev_priv(dev);
8729
8730 return tp->nvram_size;
8731}
8732
1da177e4
LT		 8733static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8734{
8735 struct tg3 *tp = netdev_priv(dev);
8736 int ret;
8737 u8 *pd;
b9fc7dc5 8738 u32 i, offset, len, b_offset, b_count;
a9dc529d 8739 __be32 val;
1da177e4 8740
df259d8c
MC		 8741 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8742 return -EINVAL;
8743
bc1c7567
MC		 8744 if (tp->link_config.phy_is_low_power)
8745 return -EAGAIN;
8746
1da177e4
LT		 8747 offset = eeprom->offset;
8748 len = eeprom->len;
8749 eeprom->len = 0;
8750
8751 eeprom->magic = TG3_EEPROM_MAGIC;
8752
8753 if (offset & 3) {
8754 /* adjustments to start on required 4 byte boundary */
8755 b_offset = offset & 3;
8756 b_count = 4 - b_offset;
8757 if (b_count > len) {
8758 /* i.e. offset=1 len=2 */
8759 b_count = len;
8760 }
a9dc529d 8761 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8762 if (ret)
8763 return ret;
1da177e4
LT		 8764 memcpy(data, ((char*)&val) + b_offset, b_count);
8765 len -= b_count;
8766 offset += b_count;
8767 eeprom->len += b_count;
8768 }
8769
8770 /* read bytes upto the last 4 byte boundary */
8771 pd = &data[eeprom->len];
8772 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8773 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8774 if (ret) {
8775 eeprom->len += i;
8776 return ret;
8777 }
1da177e4
LT		 8778 memcpy(pd + i, &val, 4);
8779 }
8780 eeprom->len += i;
8781
8782 if (len & 3) {
8783 /* read last bytes not ending on 4 byte boundary */
8784 pd = &data[eeprom->len];
8785 b_count = len & 3;
8786 b_offset = offset + len - b_count;
a9dc529d 8787 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8788 if (ret)
8789 return ret;
b9fc7dc5 8790 memcpy(pd, &val, b_count);
1da177e4
LT		 8791 eeprom->len += b_count;
8792 }
8793 return 0;
8794}
8795
6aa20a22 8796static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8797
8798static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8799{
8800 struct tg3 *tp = netdev_priv(dev);
8801 int ret;
b9fc7dc5 8802 u32 offset, len, b_offset, odd_len;
1da177e4 8803 u8 *buf;
a9dc529d 8804 __be32 start, end;
1da177e4 8805
bc1c7567
MC		 8806 if (tp->link_config.phy_is_low_power)
8807 return -EAGAIN;
8808
df259d8c
MC		 8809 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8810 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 8811 return -EINVAL;
8812
8813 offset = eeprom->offset;
8814 len = eeprom->len;
8815
8816 if ((b_offset = (offset & 3))) {
8817 /* adjustments to start on required 4 byte boundary */
a9dc529d 8818 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8819 if (ret)
8820 return ret;
1da177e4
LT		 8821 len += b_offset;
8822 offset &= ~3;
1c8594b4
MC		 8823 if (len < 4)
8824 len = 4;
1da177e4
LT		 8825 }
8826
8827 odd_len = 0;
1c8594b4 8828 if (len & 3) {
1da177e4
LT		 8829 /* adjustments to end on required 4 byte boundary */
8830 odd_len = 1;
8831 len = (len + 3) & ~3;
a9dc529d 8832 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8833 if (ret)
8834 return ret;
1da177e4
LT		 8835 }
8836
8837 buf = data;
8838 if (b_offset || odd_len) {
8839 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8840 if (!buf)
1da177e4
LT		 8841 return -ENOMEM;
8842 if (b_offset)
8843 memcpy(buf, &start, 4);
8844 if (odd_len)
8845 memcpy(buf+len-4, &end, 4);
8846 memcpy(buf + b_offset, data, eeprom->len);
8847 }
8848
8849 ret = tg3_nvram_write_block(tp, offset, len, buf);
8850
8851 if (buf != data)
8852 kfree(buf);
8853
8854 return ret;
8855}
8856
8857static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8858{
b02fd9e3
MC		 8859 struct tg3 *tp = netdev_priv(dev);
8860
8861 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8862 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8863 return -EAGAIN;
298cf9be 8864 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8865 }
6aa20a22 8866
1da177e4
LT		 8867 cmd->supported = (SUPPORTED_Autoneg);
8868
8869 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8870 cmd->supported |= (SUPPORTED_1000baseT_Half |
8871 SUPPORTED_1000baseT_Full);
8872
ef348144 8873 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8874 cmd->supported |= (SUPPORTED_100baseT_Half |
8875 SUPPORTED_100baseT_Full |
8876 SUPPORTED_10baseT_Half |
8877 SUPPORTED_10baseT_Full |
3bebab59 8878 SUPPORTED_TP);
ef348144
KK		 8879 cmd->port = PORT_TP;
8880 } else {
1da177e4 8881 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8882 cmd->port = PORT_FIBRE;
8883 }
6aa20a22 8884
1da177e4
LT		 8885 cmd->advertising = tp->link_config.advertising;
8886 if (netif_running(dev)) {
8887 cmd->speed = tp->link_config.active_speed;
8888 cmd->duplex = tp->link_config.active_duplex;
8889 }
1da177e4 8890 cmd->phy_address = PHY_ADDR;
7e5856bd 8891 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8892 cmd->autoneg = tp->link_config.autoneg;
8893 cmd->maxtxpkt = 0;
8894 cmd->maxrxpkt = 0;
8895 return 0;
8896}
6aa20a22 8897
1da177e4
LT		 8898static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8899{
8900 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8901
b02fd9e3
MC		 8902 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8903 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8904 return -EAGAIN;
298cf9be 8905 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8906 }
8907
7e5856bd
MC		 8908 if (cmd->autoneg != AUTONEG_ENABLE &&
8909 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8910 return -EINVAL;
7e5856bd
MC		 8911
8912 if (cmd->autoneg == AUTONEG_DISABLE &&
8913 cmd->duplex != DUPLEX_FULL &&
8914 cmd->duplex != DUPLEX_HALF)
37ff238d 8915 return -EINVAL;
1da177e4 8916
7e5856bd
MC		 8917 if (cmd->autoneg == AUTONEG_ENABLE) {
8918 u32 mask = ADVERTISED_Autoneg |
8919 ADVERTISED_Pause |
8920 ADVERTISED_Asym_Pause;
8921
8922 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8923 mask |= ADVERTISED_1000baseT_Half |
8924 ADVERTISED_1000baseT_Full;
8925
8926 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8927 mask |= ADVERTISED_100baseT_Half |
8928 ADVERTISED_100baseT_Full |
8929 ADVERTISED_10baseT_Half |
8930 ADVERTISED_10baseT_Full |
8931 ADVERTISED_TP;
8932 else
8933 mask |= ADVERTISED_FIBRE;
8934
8935 if (cmd->advertising & ~mask)
8936 return -EINVAL;
8937
8938 mask &= (ADVERTISED_1000baseT_Half |
8939 ADVERTISED_1000baseT_Full |
8940 ADVERTISED_100baseT_Half |
8941 ADVERTISED_100baseT_Full |
8942 ADVERTISED_10baseT_Half |
8943 ADVERTISED_10baseT_Full);
8944
8945 cmd->advertising &= mask;
8946 } else {
8947 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8948 if (cmd->speed != SPEED_1000)
8949 return -EINVAL;
8950
8951 if (cmd->duplex != DUPLEX_FULL)
8952 return -EINVAL;
8953 } else {
8954 if (cmd->speed != SPEED_100 &&
8955 cmd->speed != SPEED_10)
8956 return -EINVAL;
8957 }
8958 }
8959
f47c11ee 8960 tg3_full_lock(tp, 0);
1da177e4
LT		 8961
8962 tp->link_config.autoneg = cmd->autoneg;
8963 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8964 tp->link_config.advertising = (cmd->advertising |
8965 ADVERTISED_Autoneg);
1da177e4
LT		 8966 tp->link_config.speed = SPEED_INVALID;
8967 tp->link_config.duplex = DUPLEX_INVALID;
8968 } else {
8969 tp->link_config.advertising = 0;
8970 tp->link_config.speed = cmd->speed;
8971 tp->link_config.duplex = cmd->duplex;
b02fd9e3 8972 }
6aa20a22 8973
24fcad6b
MC		 8974 tp->link_config.orig_speed = tp->link_config.speed;
8975 tp->link_config.orig_duplex = tp->link_config.duplex;
8976 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8977
1da177e4
LT		 8978 if (netif_running(dev))
8979 tg3_setup_phy(tp, 1);
8980
f47c11ee 8981 tg3_full_unlock(tp);
6aa20a22 8982
1da177e4
LT		 8983 return 0;
8984}
6aa20a22 8985
1da177e4
LT		 8986static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8987{
8988 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8989
1da177e4
LT		 8990 strcpy(info->driver, DRV_MODULE_NAME);
8991 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 8992 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 8993 strcpy(info->bus_info, pci_name(tp->pdev));
8994}
6aa20a22 8995
1da177e4
LT		 8996static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8997{
8998 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8999
12dac075
RW		 9000 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9001 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9002 wol->supported = WAKE_MAGIC;
9003 else
9004 wol->supported = 0;
1da177e4 9005 wol->wolopts = 0;
05ac4cb7
MC		 9006 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9007 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9008 wol->wolopts = WAKE_MAGIC;
9009 memset(&wol->sopass, 0, sizeof(wol->sopass));
9010}
6aa20a22 9011
1da177e4
LT		 9012static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9013{
9014 struct tg3 *tp = netdev_priv(dev);
12dac075 9015 struct device *dp = &tp->pdev->dev;
6aa20a22 9016
1da177e4
LT		 9017 if (wol->wolopts & ~WAKE_MAGIC)
9018 return -EINVAL;
9019 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9020 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9021 return -EINVAL;
6aa20a22 9022
f47c11ee 9023 spin_lock_bh(&tp->lock);
12dac075 9024 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9025 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9026 device_set_wakeup_enable(dp, true);
9027 } else {
1da177e4 9028 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9029 device_set_wakeup_enable(dp, false);
9030 }
f47c11ee 9031 spin_unlock_bh(&tp->lock);
6aa20a22 9032
1da177e4
LT		 9033 return 0;
9034}
6aa20a22 9035
1da177e4
LT		 9036static u32 tg3_get_msglevel(struct net_device *dev)
9037{
9038 struct tg3 *tp = netdev_priv(dev);
9039 return tp->msg_enable;
9040}
6aa20a22 9041
1da177e4
LT		 9042static void tg3_set_msglevel(struct net_device *dev, u32 value)
9043{
9044 struct tg3 *tp = netdev_priv(dev);
9045 tp->msg_enable = value;
9046}
6aa20a22 9047
1da177e4
LT		 9048static int tg3_set_tso(struct net_device *dev, u32 value)
9049{
9050 struct tg3 *tp = netdev_priv(dev);
9051
9052 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9053 if (value)
9054 return -EINVAL;
9055 return 0;
9056 }
027455ad
MC		 9057 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9058 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9059 if (value) {
b0026624 9060 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9061 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9062 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9063 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 9064 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9065 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9066 dev->features |= NETIF_F_TSO_ECN;
9067 } else
9068 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9069 }
1da177e4
LT		 9070 return ethtool_op_set_tso(dev, value);
9071}
6aa20a22 9072
1da177e4
LT		 9073static int tg3_nway_reset(struct net_device *dev)
9074{
9075 struct tg3 *tp = netdev_priv(dev);
1da177e4 9076 int r;
6aa20a22 9077
1da177e4
LT		 9078 if (!netif_running(dev))
9079 return -EAGAIN;
9080
c94e3941
MC		 9081 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9082 return -EINVAL;
9083
b02fd9e3
MC		 9084 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9085 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9086 return -EAGAIN;
298cf9be 9087 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 9088 } else {
9089 u32 bmcr;
9090
9091 spin_lock_bh(&tp->lock);
9092 r = -EINVAL;
9093 tg3_readphy(tp, MII_BMCR, &bmcr);
9094 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9095 ((bmcr & BMCR_ANENABLE) ||
9096 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9097 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9098 BMCR_ANENABLE);
9099 r = 0;
9100 }
9101 spin_unlock_bh(&tp->lock);
1da177e4 9102 }
6aa20a22 9103
1da177e4
LT		 9104 return r;
9105}
6aa20a22 9106
1da177e4
LT		 9107static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9108{
9109 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9110
1da177e4
LT		 9111 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9112 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9113 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9114 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9115 else
9116 ering->rx_jumbo_max_pending = 0;
9117
9118 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9119
9120 ering->rx_pending = tp->rx_pending;
9121 ering->rx_mini_pending = 0;
4f81c32b
MC		 9122 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9123 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9124 else
9125 ering->rx_jumbo_pending = 0;
9126
f3f3f27e 9127 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9128}
6aa20a22 9129
1da177e4
LT		 9130static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9131{
9132 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 9133 int irq_sync = 0, err = 0;
6aa20a22 9134
1da177e4
LT		 9135 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9136 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9137 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9138 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9139 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9140 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9141 return -EINVAL;
6aa20a22 9142
bbe832c0 9143 if (netif_running(dev)) {
b02fd9e3 9144 tg3_phy_stop(tp);
1da177e4 9145 tg3_netif_stop(tp);
bbe832c0
MC		 9146 irq_sync = 1;
9147 }
1da177e4 9148
bbe832c0 9149 tg3_full_lock(tp, irq_sync);
6aa20a22 9150
1da177e4
LT		 9151 tp->rx_pending = ering->rx_pending;
9152
9153 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9154 tp->rx_pending > 63)
9155 tp->rx_pending = 63;
9156 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
f3f3f27e 9157 tp->napi[0].tx_pending = ering->tx_pending;
1da177e4
LT		 9158
9159 if (netif_running(dev)) {
944d980e 9160 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9161 err = tg3_restart_hw(tp, 1);
9162 if (!err)
9163 tg3_netif_start(tp);
1da177e4
LT		 9164 }
9165
f47c11ee 9166 tg3_full_unlock(tp);
6aa20a22 9167
b02fd9e3
MC		 9168 if (irq_sync && !err)
9169 tg3_phy_start(tp);
9170
b9ec6c1b 9171 return err;
1da177e4 9172}
6aa20a22 9173
1da177e4
LT		 9174static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9175{
9176 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9177
1da177e4 9178 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9179
e18ce346 9180 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9181 epause->rx_pause = 1;
9182 else
9183 epause->rx_pause = 0;
9184
e18ce346 9185 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9186 epause->tx_pause = 1;
9187 else
9188 epause->tx_pause = 0;
1da177e4 9189}
6aa20a22 9190
1da177e4
LT		 9191static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9192{
9193 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9194 int err = 0;
6aa20a22 9195
b02fd9e3
MC		 9196 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9197 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9198 return -EAGAIN;
1da177e4 9199
b02fd9e3
MC		 9200 if (epause->autoneg) {
9201 u32 newadv;
9202 struct phy_device *phydev;
f47c11ee 9203
298cf9be 9204 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9205
b02fd9e3
MC		 9206 if (epause->rx_pause) {
9207 if (epause->tx_pause)
9208 newadv = ADVERTISED_Pause;
9209 else
9210 newadv = ADVERTISED_Pause |
9211 ADVERTISED_Asym_Pause;
9212 } else if (epause->tx_pause) {
9213 newadv = ADVERTISED_Asym_Pause;
9214 } else
9215 newadv = 0;
9216
9217 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9218 u32 oldadv = phydev->advertising &
9219 (ADVERTISED_Pause |
9220 ADVERTISED_Asym_Pause);
9221 if (oldadv != newadv) {
9222 phydev->advertising &=
9223 ~(ADVERTISED_Pause |
9224 ADVERTISED_Asym_Pause);
9225 phydev->advertising |= newadv;
9226 err = phy_start_aneg(phydev);
9227 }
9228 } else {
9229 tp->link_config.advertising &=
9230 ~(ADVERTISED_Pause |
9231 ADVERTISED_Asym_Pause);
9232 tp->link_config.advertising |= newadv;
9233 }
9234 } else {
9235 if (epause->rx_pause)
e18ce346 9236 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9237 else
e18ce346 9238 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9239
b02fd9e3 9240 if (epause->tx_pause)
e18ce346 9241 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9242 else
e18ce346 9243 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9244
9245 if (netif_running(dev))
9246 tg3_setup_flow_control(tp, 0, 0);
9247 }
9248 } else {
9249 int irq_sync = 0;
9250
9251 if (netif_running(dev)) {
9252 tg3_netif_stop(tp);
9253 irq_sync = 1;
9254 }
9255
9256 tg3_full_lock(tp, irq_sync);
9257
9258 if (epause->autoneg)
9259 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9260 else
9261 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9262 if (epause->rx_pause)
e18ce346 9263 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9264 else
e18ce346 9265 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9266 if (epause->tx_pause)
e18ce346 9267 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9268 else
e18ce346 9269 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9270
9271 if (netif_running(dev)) {
9272 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9273 err = tg3_restart_hw(tp, 1);
9274 if (!err)
9275 tg3_netif_start(tp);
9276 }
9277
9278 tg3_full_unlock(tp);
9279 }
6aa20a22 9280
b9ec6c1b 9281 return err;
1da177e4 9282}
6aa20a22 9283
1da177e4
LT		 9284static u32 tg3_get_rx_csum(struct net_device *dev)
9285{
9286 struct tg3 *tp = netdev_priv(dev);
9287 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9288}
6aa20a22 9289
1da177e4
LT		 9290static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9291{
9292 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9293
1da177e4
LT		 9294 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9295 if (data != 0)
9296 return -EINVAL;
9297 return 0;
9298 }
6aa20a22 9299
f47c11ee 9300 spin_lock_bh(&tp->lock);
1da177e4
LT		 9301 if (data)
9302 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9303 else
9304 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9305 spin_unlock_bh(&tp->lock);
6aa20a22 9306
1da177e4
LT		 9307 return 0;
9308}
6aa20a22 9309
1da177e4
LT		 9310static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9311{
9312 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9313
1da177e4
LT		 9314 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9315 if (data != 0)
9316 return -EINVAL;
9317 return 0;
9318 }
6aa20a22 9319
321d32a0 9320 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9321 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9322 else
9c27dbdf 9323 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9324
9325 return 0;
9326}
9327
b9f2c044 9328static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9329{
b9f2c044
JG		 9330 switch (sset) {
9331 case ETH_SS_TEST:
9332 return TG3_NUM_TEST;
9333 case ETH_SS_STATS:
9334 return TG3_NUM_STATS;
9335 default:
9336 return -EOPNOTSUPP;
9337 }
4cafd3f5
MC		 9338}
9339
1da177e4
LT		 9340static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9341{
9342 switch (stringset) {
9343 case ETH_SS_STATS:
9344 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9345 break;
4cafd3f5
MC		 9346 case ETH_SS_TEST:
9347 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9348 break;
1da177e4
LT		 9349 default:
9350 WARN_ON(1); /* we need a WARN() */
9351 break;
9352 }
9353}
9354
4009a93d
MC		 9355static int tg3_phys_id(struct net_device *dev, u32 data)
9356{
9357 struct tg3 *tp = netdev_priv(dev);
9358 int i;
9359
9360 if (!netif_running(tp->dev))
9361 return -EAGAIN;
9362
9363 if (data == 0)
759afc31 9364 data = UINT_MAX / 2;
4009a93d
MC		 9365
9366 for (i = 0; i < (data * 2); i++) {
9367 if ((i % 2) == 0)
9368 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9369 LED_CTRL_1000MBPS_ON |
9370 LED_CTRL_100MBPS_ON |
9371 LED_CTRL_10MBPS_ON |
9372 LED_CTRL_TRAFFIC_OVERRIDE |
9373 LED_CTRL_TRAFFIC_BLINK |
9374 LED_CTRL_TRAFFIC_LED);
6aa20a22 9375
4009a93d
MC		 9376 else
9377 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9378 LED_CTRL_TRAFFIC_OVERRIDE);
9379
9380 if (msleep_interruptible(500))
9381 break;
9382 }
9383 tw32(MAC_LED_CTRL, tp->led_ctrl);
9384 return 0;
9385}
9386
1da177e4
LT		 9387static void tg3_get_ethtool_stats (struct net_device *dev,
9388 struct ethtool_stats *estats, u64 *tmp_stats)
9389{
9390 struct tg3 *tp = netdev_priv(dev);
9391 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9392}
9393
566f86ad 9394#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9395#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9396#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9397#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9398#define NVRAM_SELFBOOT_HW_SIZE 0x20
9399#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9400
9401static int tg3_test_nvram(struct tg3 *tp)
9402{
b9fc7dc5 9403 u32 csum, magic;
a9dc529d 9404 __be32 *buf;
ab0049b4 9405 int i, j, k, err = 0, size;
566f86ad 9406
df259d8c
MC		 9407 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9408 return 0;
9409
e4f34110 9410 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9411 return -EIO;
9412
1b27777a
MC		 9413 if (magic == TG3_EEPROM_MAGIC)
9414 size = NVRAM_TEST_SIZE;
b16250e3 9415 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9416 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9417 TG3_EEPROM_SB_FORMAT_1) {
9418 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9419 case TG3_EEPROM_SB_REVISION_0:
9420 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9421 break;
9422 case TG3_EEPROM_SB_REVISION_2:
9423 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9424 break;
9425 case TG3_EEPROM_SB_REVISION_3:
9426 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9427 break;
9428 default:
9429 return 0;
9430 }
9431 } else
1b27777a 9432 return 0;
b16250e3
MC		 9433 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9434 size = NVRAM_SELFBOOT_HW_SIZE;
9435 else
1b27777a
MC		 9436 return -EIO;
9437
9438 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9439 if (buf == NULL)
9440 return -ENOMEM;
9441
1b27777a
MC		 9442 err = -EIO;
9443 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9444 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9445 if (err)
566f86ad 9446 break;
566f86ad 9447 }
1b27777a 9448 if (i < size)
566f86ad
MC		 9449 goto out;
9450
1b27777a 9451 /* Selfboot format */
a9dc529d 9452 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9453 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9454 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9455 u8 *buf8 = (u8 *) buf, csum8 = 0;
9456
b9fc7dc5 9457 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9458 TG3_EEPROM_SB_REVISION_2) {
9459 /* For rev 2, the csum doesn't include the MBA. */
9460 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9461 csum8 += buf8[i];
9462 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9463 csum8 += buf8[i];
9464 } else {
9465 for (i = 0; i < size; i++)
9466 csum8 += buf8[i];
9467 }
1b27777a 9468
ad96b485
AB		 9469 if (csum8 == 0) {
9470 err = 0;
9471 goto out;
9472 }
9473
9474 err = -EIO;
9475 goto out;
1b27777a 9476 }
566f86ad 9477
b9fc7dc5 9478 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9479 TG3_EEPROM_MAGIC_HW) {
9480 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9481 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9482 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9483
9484 /* Separate the parity bits and the data bytes. */
9485 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9486 if ((i == 0) || (i == 8)) {
9487 int l;
9488 u8 msk;
9489
9490 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9491 parity[k++] = buf8[i] & msk;
9492 i++;
9493 }
9494 else if (i == 16) {
9495 int l;
9496 u8 msk;
9497
9498 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9499 parity[k++] = buf8[i] & msk;
9500 i++;
9501
9502 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9503 parity[k++] = buf8[i] & msk;
9504 i++;
9505 }
9506 data[j++] = buf8[i];
9507 }
9508
9509 err = -EIO;
9510 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9511 u8 hw8 = hweight8(data[i]);
9512
9513 if ((hw8 & 0x1) && parity[i])
9514 goto out;
9515 else if (!(hw8 & 0x1) && !parity[i])
9516 goto out;
9517 }
9518 err = 0;
9519 goto out;
9520 }
9521
566f86ad
MC		 9522 /* Bootstrap checksum at offset 0x10 */
9523 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9524 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9525 goto out;
9526
9527 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9528 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9529 if (csum != be32_to_cpu(buf[0xfc/4]))
9530 goto out;
566f86ad
MC		 9531
9532 err = 0;
9533
9534out:
9535 kfree(buf);
9536 return err;
9537}
9538
ca43007a
MC		 9539#define TG3_SERDES_TIMEOUT_SEC 2
9540#define TG3_COPPER_TIMEOUT_SEC 6
9541
9542static int tg3_test_link(struct tg3 *tp)
9543{
9544 int i, max;
9545
9546 if (!netif_running(tp->dev))
9547 return -ENODEV;
9548
4c987487 9549 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9550 max = TG3_SERDES_TIMEOUT_SEC;
9551 else
9552 max = TG3_COPPER_TIMEOUT_SEC;
9553
9554 for (i = 0; i < max; i++) {
9555 if (netif_carrier_ok(tp->dev))
9556 return 0;
9557
9558 if (msleep_interruptible(1000))
9559 break;
9560 }
9561
9562 return -EIO;
9563}
9564
a71116d1 9565/* Only test the commonly used registers */
30ca3e37 9566static int tg3_test_registers(struct tg3 *tp)
a71116d1 9567{
b16250e3 9568 int i, is_5705, is_5750;
a71116d1
MC		 9569 u32 offset, read_mask, write_mask, val, save_val, read_val;
9570 static struct {
9571 u16 offset;
9572 u16 flags;
9573#define TG3_FL_5705 0x1
9574#define TG3_FL_NOT_5705 0x2
9575#define TG3_FL_NOT_5788 0x4
b16250e3 9576#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9577 u32 read_mask;
9578 u32 write_mask;
9579 } reg_tbl[] = {
9580 /* MAC Control Registers */
9581 { MAC_MODE, TG3_FL_NOT_5705,
9582 0x00000000, 0x00ef6f8c },
9583 { MAC_MODE, TG3_FL_5705,
9584 0x00000000, 0x01ef6b8c },
9585 { MAC_STATUS, TG3_FL_NOT_5705,
9586 0x03800107, 0x00000000 },
9587 { MAC_STATUS, TG3_FL_5705,
9588 0x03800100, 0x00000000 },
9589 { MAC_ADDR_0_HIGH, 0x0000,
9590 0x00000000, 0x0000ffff },
9591 { MAC_ADDR_0_LOW, 0x0000,
9592 0x00000000, 0xffffffff },
9593 { MAC_RX_MTU_SIZE, 0x0000,
9594 0x00000000, 0x0000ffff },
9595 { MAC_TX_MODE, 0x0000,
9596 0x00000000, 0x00000070 },
9597 { MAC_TX_LENGTHS, 0x0000,
9598 0x00000000, 0x00003fff },
9599 { MAC_RX_MODE, TG3_FL_NOT_5705,
9600 0x00000000, 0x000007fc },
9601 { MAC_RX_MODE, TG3_FL_5705,
9602 0x00000000, 0x000007dc },
9603 { MAC_HASH_REG_0, 0x0000,
9604 0x00000000, 0xffffffff },
9605 { MAC_HASH_REG_1, 0x0000,
9606 0x00000000, 0xffffffff },
9607 { MAC_HASH_REG_2, 0x0000,
9608 0x00000000, 0xffffffff },
9609 { MAC_HASH_REG_3, 0x0000,
9610 0x00000000, 0xffffffff },
9611
9612 /* Receive Data and Receive BD Initiator Control Registers. */
9613 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9614 0x00000000, 0xffffffff },
9615 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9616 0x00000000, 0xffffffff },
9617 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9618 0x00000000, 0x00000003 },
9619 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9620 0x00000000, 0xffffffff },
9621 { RCVDBDI_STD_BD+0, 0x0000,
9622 0x00000000, 0xffffffff },
9623 { RCVDBDI_STD_BD+4, 0x0000,
9624 0x00000000, 0xffffffff },
9625 { RCVDBDI_STD_BD+8, 0x0000,
9626 0x00000000, 0xffff0002 },
9627 { RCVDBDI_STD_BD+0xc, 0x0000,
9628 0x00000000, 0xffffffff },
6aa20a22 9629
a71116d1
MC		 9630 /* Receive BD Initiator Control Registers. */
9631 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9632 0x00000000, 0xffffffff },
9633 { RCVBDI_STD_THRESH, TG3_FL_5705,
9634 0x00000000, 0x000003ff },
9635 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9636 0x00000000, 0xffffffff },
6aa20a22 9637
a71116d1
MC		 9638 /* Host Coalescing Control Registers. */
9639 { HOSTCC_MODE, TG3_FL_NOT_5705,
9640 0x00000000, 0x00000004 },
9641 { HOSTCC_MODE, TG3_FL_5705,
9642 0x00000000, 0x000000f6 },
9643 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9644 0x00000000, 0xffffffff },
9645 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9646 0x00000000, 0x000003ff },
9647 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9648 0x00000000, 0xffffffff },
9649 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9650 0x00000000, 0x000003ff },
9651 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9652 0x00000000, 0xffffffff },
9653 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9654 0x00000000, 0x000000ff },
9655 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9656 0x00000000, 0xffffffff },
9657 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9658 0x00000000, 0x000000ff },
9659 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9660 0x00000000, 0xffffffff },
9661 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9662 0x00000000, 0xffffffff },
9663 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9664 0x00000000, 0xffffffff },
9665 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9666 0x00000000, 0x000000ff },
9667 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9668 0x00000000, 0xffffffff },
9669 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9670 0x00000000, 0x000000ff },
9671 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9672 0x00000000, 0xffffffff },
9673 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9674 0x00000000, 0xffffffff },
9675 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9676 0x00000000, 0xffffffff },
9677 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9678 0x00000000, 0xffffffff },
9679 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9680 0x00000000, 0xffffffff },
9681 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9682 0xffffffff, 0x00000000 },
9683 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9684 0xffffffff, 0x00000000 },
9685
9686 /* Buffer Manager Control Registers. */
b16250e3 9687 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9688 0x00000000, 0x007fff80 },
b16250e3 9689 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9690 0x00000000, 0x007fffff },
9691 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9692 0x00000000, 0x0000003f },
9693 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9694 0x00000000, 0x000001ff },
9695 { BUFMGR_MB_HIGH_WATER, 0x0000,
9696 0x00000000, 0x000001ff },
9697 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9698 0xffffffff, 0x00000000 },
9699 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9700 0xffffffff, 0x00000000 },
6aa20a22 9701
a71116d1
MC		 9702 /* Mailbox Registers */
9703 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9704 0x00000000, 0x000001ff },
9705 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9706 0x00000000, 0x000001ff },
9707 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9708 0x00000000, 0x000007ff },
9709 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9710 0x00000000, 0x000001ff },
9711
9712 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9713 };
9714
b16250e3
MC		 9715 is_5705 = is_5750 = 0;
9716 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9717 is_5705 = 1;
b16250e3
MC		 9718 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9719 is_5750 = 1;
9720 }
a71116d1
MC		 9721
9722 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9723 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9724 continue;
9725
9726 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9727 continue;
9728
9729 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9730 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9731 continue;
9732
b16250e3
MC		 9733 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9734 continue;
9735
a71116d1
MC		 9736 offset = (u32) reg_tbl[i].offset;
9737 read_mask = reg_tbl[i].read_mask;
9738 write_mask = reg_tbl[i].write_mask;
9739
9740 /* Save the original register content */
9741 save_val = tr32(offset);
9742
9743 /* Determine the read-only value. */
9744 read_val = save_val & read_mask;
9745
9746 /* Write zero to the register, then make sure the read-only bits
9747 * are not changed and the read/write bits are all zeros.
9748 */
9749 tw32(offset, 0);
9750
9751 val = tr32(offset);
9752
9753 /* Test the read-only and read/write bits. */
9754 if (((val & read_mask) != read_val) || (val & write_mask))
9755 goto out;
9756
9757 /* Write ones to all the bits defined by RdMask and WrMask, then
9758 * make sure the read-only bits are not changed and the
9759 * read/write bits are all ones.
9760 */
9761 tw32(offset, read_mask | write_mask);
9762
9763 val = tr32(offset);
9764
9765 /* Test the read-only bits. */
9766 if ((val & read_mask) != read_val)
9767 goto out;
9768
9769 /* Test the read/write bits. */
9770 if ((val & write_mask) != write_mask)
9771 goto out;
9772
9773 tw32(offset, save_val);
9774 }
9775
9776 return 0;
9777
9778out:
9f88f29f
MC		 9779 if (netif_msg_hw(tp))
9780 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9781 offset);
a71116d1
MC		 9782 tw32(offset, save_val);
9783 return -EIO;
9784}
9785
7942e1db
MC		 9786static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9787{
f71e1309 9788 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9789 int i;
9790 u32 j;
9791
e9edda69 9792 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9793 for (j = 0; j < len; j += 4) {
9794 u32 val;
9795
9796 tg3_write_mem(tp, offset + j, test_pattern[i]);
9797 tg3_read_mem(tp, offset + j, &val);
9798 if (val != test_pattern[i])
9799 return -EIO;
9800 }
9801 }
9802 return 0;
9803}
9804
9805static int tg3_test_memory(struct tg3 *tp)
9806{
9807 static struct mem_entry {
9808 u32 offset;
9809 u32 len;
9810 } mem_tbl_570x[] = {
38690194 9811 { 0x00000000, 0x00b50},
7942e1db
MC		 9812 { 0x00002000, 0x1c000},
9813 { 0xffffffff, 0x00000}
9814 }, mem_tbl_5705[] = {
9815 { 0x00000100, 0x0000c},
9816 { 0x00000200, 0x00008},
7942e1db
MC		 9817 { 0x00004000, 0x00800},
9818 { 0x00006000, 0x01000},
9819 { 0x00008000, 0x02000},
9820 { 0x00010000, 0x0e000},
9821 { 0xffffffff, 0x00000}
79f4d13a
MC		 9822 }, mem_tbl_5755[] = {
9823 { 0x00000200, 0x00008},
9824 { 0x00004000, 0x00800},
9825 { 0x00006000, 0x00800},
9826 { 0x00008000, 0x02000},
9827 { 0x00010000, 0x0c000},
9828 { 0xffffffff, 0x00000}
b16250e3
MC		 9829 }, mem_tbl_5906[] = {
9830 { 0x00000200, 0x00008},
9831 { 0x00004000, 0x00400},
9832 { 0x00006000, 0x00400},
9833 { 0x00008000, 0x01000},
9834 { 0x00010000, 0x01000},
9835 { 0xffffffff, 0x00000}
7942e1db
MC		 9836 };
9837 struct mem_entry *mem_tbl;
9838 int err = 0;
9839 int i;
9840
321d32a0
MC		 9841 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9842 mem_tbl = mem_tbl_5755;
9843 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9844 mem_tbl = mem_tbl_5906;
9845 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9846 mem_tbl = mem_tbl_5705;
9847 else
7942e1db
MC		 9848 mem_tbl = mem_tbl_570x;
9849
9850 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9851 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9852 mem_tbl[i].len)) != 0)
9853 break;
9854 }
6aa20a22 9855
7942e1db
MC		 9856 return err;
9857}
9858
9f40dead
MC		 9859#define TG3_MAC_LOOPBACK 0
9860#define TG3_PHY_LOOPBACK 1
9861
9862static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9863{
9f40dead 9864 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 9865 u32 desc_idx, coal_now;
c76949a6
MC		 9866 struct sk_buff *skb, *rx_skb;
9867 u8 *tx_data;
9868 dma_addr_t map;
9869 int num_pkts, tx_len, rx_len, i, err;
9870 struct tg3_rx_buffer_desc *desc;
898a56f8 9871 struct tg3_napi *tnapi, *rnapi;
21f581a5 9872 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 9873
898a56f8
MC		 9874 tnapi = &tp->napi[0];
9875 rnapi = &tp->napi[0];
fd2ce37f 9876 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 9877
9f40dead 9878 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9879 /* HW errata - mac loopback fails in some cases on 5780.
9880 * Normal traffic and PHY loopback are not affected by
9881 * errata.
9882 */
9883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9884 return 0;
9885
9f40dead 9886 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9887 MAC_MODE_PORT_INT_LPBACK;
9888 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9889 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9890 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9891 mac_mode |= MAC_MODE_PORT_MODE_MII;
9892 else
9893 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9894 tw32(MAC_MODE, mac_mode);
9895 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9896 u32 val;
9897
7f97a4bd
MC		 9898 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9899 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 9900 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9901 } else
9902 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9903
9ef8ca99
MC		 9904 tg3_phy_toggle_automdix(tp, 0);
9905
3f7045c1 9906 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9907 udelay(40);
5d64ad34 9908
e8f3f6ca 9909 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 9910 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9912 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 9913 mac_mode |= MAC_MODE_PORT_MODE_MII;
9914 } else
9915 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9916
c94e3941
MC		 9917 /* reset to prevent losing 1st rx packet intermittently */
9918 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9919 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9920 udelay(10);
9921 tw32_f(MAC_RX_MODE, tp->rx_mode);
9922 }
e8f3f6ca
MC		 9923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9924 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9925 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9926 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9927 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9928 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9929 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9930 }
9f40dead 9931 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9932 }
9933 else
9934 return -EINVAL;
c76949a6
MC		 9935
9936 err = -EIO;
9937
c76949a6 9938 tx_len = 1514;
a20e9c62 9939 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9940 if (!skb)
9941 return -ENOMEM;
9942
c76949a6
MC		 9943 tx_data = skb_put(skb, tx_len);
9944 memcpy(tx_data, tp->dev->dev_addr, 6);
9945 memset(tx_data + 6, 0x0, 8);
9946
9947 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9948
9949 for (i = 14; i < tx_len; i++)
9950 tx_data[i] = (u8) (i & 0xff);
9951
9952 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9953
9954 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 9955 rnapi->coal_now);
c76949a6
MC		 9956
9957 udelay(10);
9958
898a56f8 9959 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 9960
c76949a6
MC		 9961 num_pkts = 0;
9962
f3f3f27e 9963 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 9964
f3f3f27e 9965 tnapi->tx_prod++;
c76949a6
MC		 9966 num_pkts++;
9967
f3f3f27e
MC		 9968 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
9969 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 9970
9971 udelay(10);
9972
3f7045c1
MC		 9973 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9974 for (i = 0; i < 25; i++) {
c76949a6 9975 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 9976 coal_now);
c76949a6
MC		 9977
9978 udelay(10);
9979
898a56f8
MC		 9980 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
9981 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 9982 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 9983 (rx_idx == (rx_start_idx + num_pkts)))
9984 break;
9985 }
9986
9987 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9988 dev_kfree_skb(skb);
9989
f3f3f27e 9990 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 9991 goto out;
9992
9993 if (rx_idx != rx_start_idx + num_pkts)
9994 goto out;
9995
72334482 9996 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 9997 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9998 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9999 if (opaque_key != RXD_OPAQUE_RING_STD)
10000 goto out;
10001
10002 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10003 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10004 goto out;
10005
10006 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10007 if (rx_len != tx_len)
10008 goto out;
10009
21f581a5 10010 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10011
21f581a5 10012 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10013 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10014
10015 for (i = 14; i < tx_len; i++) {
10016 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10017 goto out;
10018 }
10019 err = 0;
6aa20a22 10020
c76949a6
MC		 10021 /* tg3_free_rings will unmap and free the rx_skb */
10022out:
10023 return err;
10024}
10025
9f40dead
MC		 10026#define TG3_MAC_LOOPBACK_FAILED 1
10027#define TG3_PHY_LOOPBACK_FAILED 2
10028#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10029 TG3_PHY_LOOPBACK_FAILED)
10030
10031static int tg3_test_loopback(struct tg3 *tp)
10032{
10033 int err = 0;
9936bcf6 10034 u32 cpmuctrl = 0;
9f40dead
MC		 10035
10036 if (!netif_running(tp->dev))
10037 return TG3_LOOPBACK_FAILED;
10038
b9ec6c1b
MC		 10039 err = tg3_reset_hw(tp, 1);
10040 if (err)
10041 return TG3_LOOPBACK_FAILED;
9f40dead 10042
6833c043
MC		 10043 /* Turn off gphy autopowerdown. */
10044 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10045 tg3_phy_toggle_apd(tp, false);
10046
321d32a0 10047 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10048 int i;
10049 u32 status;
10050
10051 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10052
10053 /* Wait for up to 40 microseconds to acquire lock. */
10054 for (i = 0; i < 4; i++) {
10055 status = tr32(TG3_CPMU_MUTEX_GNT);
10056 if (status == CPMU_MUTEX_GNT_DRIVER)
10057 break;
10058 udelay(10);
10059 }
10060
10061 if (status != CPMU_MUTEX_GNT_DRIVER)
10062 return TG3_LOOPBACK_FAILED;
10063
b2a5c19c 10064 /* Turn off link-based power management. */
e875093c 10065 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10066 tw32(TG3_CPMU_CTRL,
10067 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10068 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10069 }
10070
9f40dead
MC		 10071 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10072 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10073
321d32a0 10074 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10075 tw32(TG3_CPMU_CTRL, cpmuctrl);
10076
10077 /* Release the mutex */
10078 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10079 }
10080
dd477003
MC		 10081 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10082 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10083 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10084 err |= TG3_PHY_LOOPBACK_FAILED;
10085 }
10086
6833c043
MC		 10087 /* Re-enable gphy autopowerdown. */
10088 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10089 tg3_phy_toggle_apd(tp, true);
10090
9f40dead
MC		 10091 return err;
10092}
10093
4cafd3f5
MC		 10094static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10095 u64 *data)
10096{
566f86ad
MC		 10097 struct tg3 *tp = netdev_priv(dev);
10098
bc1c7567
MC		 10099 if (tp->link_config.phy_is_low_power)
10100 tg3_set_power_state(tp, PCI_D0);
10101
566f86ad
MC		 10102 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10103
10104 if (tg3_test_nvram(tp) != 0) {
10105 etest->flags |= ETH_TEST_FL_FAILED;
10106 data[0] = 1;
10107 }
ca43007a
MC		 10108 if (tg3_test_link(tp) != 0) {
10109 etest->flags |= ETH_TEST_FL_FAILED;
10110 data[1] = 1;
10111 }
a71116d1 10112 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10113 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10114
10115 if (netif_running(dev)) {
b02fd9e3 10116 tg3_phy_stop(tp);
a71116d1 10117 tg3_netif_stop(tp);
bbe832c0
MC		 10118 irq_sync = 1;
10119 }
a71116d1 10120
bbe832c0 10121 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10122
10123 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10124 err = tg3_nvram_lock(tp);
a71116d1
MC		 10125 tg3_halt_cpu(tp, RX_CPU_BASE);
10126 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10127 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10128 if (!err)
10129 tg3_nvram_unlock(tp);
a71116d1 10130
d9ab5ad1
MC		 10131 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10132 tg3_phy_reset(tp);
10133
a71116d1
MC		 10134 if (tg3_test_registers(tp) != 0) {
10135 etest->flags |= ETH_TEST_FL_FAILED;
10136 data[2] = 1;
10137 }
7942e1db
MC		 10138 if (tg3_test_memory(tp) != 0) {
10139 etest->flags |= ETH_TEST_FL_FAILED;
10140 data[3] = 1;
10141 }
9f40dead 10142 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10143 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10144
f47c11ee
DM		 10145 tg3_full_unlock(tp);
10146
d4bc3927
MC		 10147 if (tg3_test_interrupt(tp) != 0) {
10148 etest->flags |= ETH_TEST_FL_FAILED;
10149 data[5] = 1;
10150 }
f47c11ee
DM		 10151
10152 tg3_full_lock(tp, 0);
d4bc3927 10153
a71116d1
MC		 10154 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10155 if (netif_running(dev)) {
10156 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10157 err2 = tg3_restart_hw(tp, 1);
10158 if (!err2)
b9ec6c1b 10159 tg3_netif_start(tp);
a71116d1 10160 }
f47c11ee
DM		 10161
10162 tg3_full_unlock(tp);
b02fd9e3
MC		 10163
10164 if (irq_sync && !err2)
10165 tg3_phy_start(tp);
a71116d1 10166 }
bc1c7567
MC		 10167 if (tp->link_config.phy_is_low_power)
10168 tg3_set_power_state(tp, PCI_D3hot);
10169
4cafd3f5
MC		 10170}
10171
1da177e4
LT		 10172static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10173{
10174 struct mii_ioctl_data *data = if_mii(ifr);
10175 struct tg3 *tp = netdev_priv(dev);
10176 int err;
10177
b02fd9e3
MC		 10178 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10179 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10180 return -EAGAIN;
298cf9be 10181 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10182 }
10183
1da177e4
LT		 10184 switch(cmd) {
10185 case SIOCGMIIPHY:
10186 data->phy_id = PHY_ADDR;
10187
10188 /* fallthru */
10189 case SIOCGMIIREG: {
10190 u32 mii_regval;
10191
10192 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10193 break; /* We have no PHY */
10194
bc1c7567
MC		 10195 if (tp->link_config.phy_is_low_power)
10196 return -EAGAIN;
10197
f47c11ee 10198 spin_lock_bh(&tp->lock);
1da177e4 10199 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10200 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10201
10202 data->val_out = mii_regval;
10203
10204 return err;
10205 }
10206
10207 case SIOCSMIIREG:
10208 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10209 break; /* We have no PHY */
10210
10211 if (!capable(CAP_NET_ADMIN))
10212 return -EPERM;
10213
bc1c7567
MC		 10214 if (tp->link_config.phy_is_low_power)
10215 return -EAGAIN;
10216
f47c11ee 10217 spin_lock_bh(&tp->lock);
1da177e4 10218 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10219 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10220
10221 return err;
10222
10223 default:
10224 /* do nothing */
10225 break;
10226 }
10227 return -EOPNOTSUPP;
10228}
10229
10230#if TG3_VLAN_TAG_USED
10231static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10232{
10233 struct tg3 *tp = netdev_priv(dev);
10234
844b3eed
MC		 10235 if (!netif_running(dev)) {
10236 tp->vlgrp = grp;
10237 return;
10238 }
10239
10240 tg3_netif_stop(tp);
29315e87 10241
f47c11ee 10242 tg3_full_lock(tp, 0);
1da177e4
LT		 10243
10244 tp->vlgrp = grp;
10245
10246 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10247 __tg3_set_rx_mode(dev);
10248
844b3eed 10249 tg3_netif_start(tp);
46966545
MC		 10250
10251 tg3_full_unlock(tp);
1da177e4 10252}
1da177e4
LT		 10253#endif
10254
15f9850d
DM		 10255static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10256{
10257 struct tg3 *tp = netdev_priv(dev);
10258
10259 memcpy(ec, &tp->coal, sizeof(*ec));
10260 return 0;
10261}
10262
d244c892
MC		 10263static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10264{
10265 struct tg3 *tp = netdev_priv(dev);
10266 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10267 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10268
10269 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10270 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10271 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10272 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10273 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10274 }
10275
10276 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10277 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10278 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10279 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10280 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10281 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10282 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10283 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10284 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10285 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10286 return -EINVAL;
10287
10288 /* No rx interrupts will be generated if both are zero */
10289 if ((ec->rx_coalesce_usecs == 0) &&
10290 (ec->rx_max_coalesced_frames == 0))
10291 return -EINVAL;
10292
10293 /* No tx interrupts will be generated if both are zero */
10294 if ((ec->tx_coalesce_usecs == 0) &&
10295 (ec->tx_max_coalesced_frames == 0))
10296 return -EINVAL;
10297
10298 /* Only copy relevant parameters, ignore all others. */
10299 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10300 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10301 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10302 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10303 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10304 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10305 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10306 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10307 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10308
10309 if (netif_running(dev)) {
10310 tg3_full_lock(tp, 0);
10311 __tg3_set_coalesce(tp, &tp->coal);
10312 tg3_full_unlock(tp);
10313 }
10314 return 0;
10315}
10316
7282d491 10317static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10318 .get_settings = tg3_get_settings,
10319 .set_settings = tg3_set_settings,
10320 .get_drvinfo = tg3_get_drvinfo,
10321 .get_regs_len = tg3_get_regs_len,
10322 .get_regs = tg3_get_regs,
10323 .get_wol = tg3_get_wol,
10324 .set_wol = tg3_set_wol,
10325 .get_msglevel = tg3_get_msglevel,
10326 .set_msglevel = tg3_set_msglevel,
10327 .nway_reset = tg3_nway_reset,
10328 .get_link = ethtool_op_get_link,
10329 .get_eeprom_len = tg3_get_eeprom_len,
10330 .get_eeprom = tg3_get_eeprom,
10331 .set_eeprom = tg3_set_eeprom,
10332 .get_ringparam = tg3_get_ringparam,
10333 .set_ringparam = tg3_set_ringparam,
10334 .get_pauseparam = tg3_get_pauseparam,
10335 .set_pauseparam = tg3_set_pauseparam,
10336 .get_rx_csum = tg3_get_rx_csum,
10337 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10338 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10339 .set_sg = ethtool_op_set_sg,
1da177e4 10340 .set_tso = tg3_set_tso,
4cafd3f5 10341 .self_test = tg3_self_test,
1da177e4 10342 .get_strings = tg3_get_strings,
4009a93d 10343 .phys_id = tg3_phys_id,
1da177e4 10344 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10345 .get_coalesce = tg3_get_coalesce,
d244c892 10346 .set_coalesce = tg3_set_coalesce,
b9f2c044 10347 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10348};
10349
10350static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10351{
1b27777a 10352 u32 cursize, val, magic;
1da177e4
LT		 10353
10354 tp->nvram_size = EEPROM_CHIP_SIZE;
10355
e4f34110 10356 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10357 return;
10358
b16250e3
MC		 10359 if ((magic != TG3_EEPROM_MAGIC) &&
10360 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10361 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10362 return;
10363
10364 /*
10365 * Size the chip by reading offsets at increasing powers of two.
10366 * When we encounter our validation signature, we know the addressing
10367 * has wrapped around, and thus have our chip size.
10368 */
1b27777a 10369 cursize = 0x10;
1da177e4
LT		 10370
10371 while (cursize < tp->nvram_size) {
e4f34110 10372 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10373 return;
10374
1820180b 10375 if (val == magic)
1da177e4
LT		 10376 break;
10377
10378 cursize <<= 1;
10379 }
10380
10381 tp->nvram_size = cursize;
10382}
6aa20a22 10383
1da177e4
LT		 10384static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10385{
10386 u32 val;
10387
df259d8c
MC		 10388 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10389 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10390 return;
10391
10392 /* Selfboot format */
1820180b 10393 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10394 tg3_get_eeprom_size(tp);
10395 return;
10396 }
10397
6d348f2c 10398 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10399 if (val != 0) {
6d348f2c
MC		 10400 /* This is confusing. We want to operate on the
10401 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10402 * call will read from NVRAM and byteswap the data
10403 * according to the byteswapping settings for all
10404 * other register accesses. This ensures the data we
10405 * want will always reside in the lower 16-bits.
10406 * However, the data in NVRAM is in LE format, which
10407 * means the data from the NVRAM read will always be
10408 * opposite the endianness of the CPU. The 16-bit
10409 * byteswap then brings the data to CPU endianness.
10410 */
10411 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10412 return;
10413 }
10414 }
fd1122a2 10415 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10416}
10417
10418static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10419{
10420 u32 nvcfg1;
10421
10422 nvcfg1 = tr32(NVRAM_CFG1);
10423 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10424 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10425 } else {
1da177e4
LT		 10426 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10427 tw32(NVRAM_CFG1, nvcfg1);
10428 }
10429
4c987487 10430 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10431 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10432 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10433 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10434 tp->nvram_jedecnum = JEDEC_ATMEL;
10435 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10436 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10437 break;
10438 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10439 tp->nvram_jedecnum = JEDEC_ATMEL;
10440 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10441 break;
10442 case FLASH_VENDOR_ATMEL_EEPROM:
10443 tp->nvram_jedecnum = JEDEC_ATMEL;
10444 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10445 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10446 break;
10447 case FLASH_VENDOR_ST:
10448 tp->nvram_jedecnum = JEDEC_ST;
10449 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10450 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10451 break;
10452 case FLASH_VENDOR_SAIFUN:
10453 tp->nvram_jedecnum = JEDEC_SAIFUN;
10454 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10455 break;
10456 case FLASH_VENDOR_SST_SMALL:
10457 case FLASH_VENDOR_SST_LARGE:
10458 tp->nvram_jedecnum = JEDEC_SST;
10459 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10460 break;
1da177e4 10461 }
8590a603 10462 } else {
1da177e4
LT		 10463 tp->nvram_jedecnum = JEDEC_ATMEL;
10464 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10465 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10466 }
10467}
10468
361b4ac2
MC		 10469static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10470{
10471 u32 nvcfg1;
10472
10473 nvcfg1 = tr32(NVRAM_CFG1);
10474
e6af301b
MC		 10475 /* NVRAM protection for TPM */
10476 if (nvcfg1 & (1 << 27))
10477 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10478
361b4ac2 10479 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10480 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10481 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10482 tp->nvram_jedecnum = JEDEC_ATMEL;
10483 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10484 break;
10485 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10486 tp->nvram_jedecnum = JEDEC_ATMEL;
10487 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10488 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10489 break;
10490 case FLASH_5752VENDOR_ST_M45PE10:
10491 case FLASH_5752VENDOR_ST_M45PE20:
10492 case FLASH_5752VENDOR_ST_M45PE40:
10493 tp->nvram_jedecnum = JEDEC_ST;
10494 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10495 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10496 break;
361b4ac2
MC		 10497 }
10498
10499 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10500 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8590a603
MC		 10501 case FLASH_5752PAGE_SIZE_256:
10502 tp->nvram_pagesize = 256;
10503 break;
10504 case FLASH_5752PAGE_SIZE_512:
10505 tp->nvram_pagesize = 512;
10506 break;
10507 case FLASH_5752PAGE_SIZE_1K:
10508 tp->nvram_pagesize = 1024;
10509 break;
10510 case FLASH_5752PAGE_SIZE_2K:
10511 tp->nvram_pagesize = 2048;
10512 break;
10513 case FLASH_5752PAGE_SIZE_4K:
10514 tp->nvram_pagesize = 4096;
10515 break;
10516 case FLASH_5752PAGE_SIZE_264:
10517 tp->nvram_pagesize = 264;
10518 break;
361b4ac2 10519 }
8590a603 10520 } else {
361b4ac2
MC		 10521 /* For eeprom, set pagesize to maximum eeprom size */
10522 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10523
10524 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10525 tw32(NVRAM_CFG1, nvcfg1);
10526 }
10527}
10528
d3c7b886
MC		 10529static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10530{
989a9d23 10531 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10532
10533 nvcfg1 = tr32(NVRAM_CFG1);
10534
10535 /* NVRAM protection for TPM */
989a9d23 10536 if (nvcfg1 & (1 << 27)) {
d3c7b886 10537 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10538 protect = 1;
10539 }
d3c7b886 10540
989a9d23
MC		 10541 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10542 switch (nvcfg1) {
8590a603
MC		 10543 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10544 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10545 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10546 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10547 tp->nvram_jedecnum = JEDEC_ATMEL;
10548 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10549 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10550 tp->nvram_pagesize = 264;
10551 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10552 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10553 tp->nvram_size = (protect ? 0x3e200 :
10554 TG3_NVRAM_SIZE_512KB);
10555 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10556 tp->nvram_size = (protect ? 0x1f200 :
10557 TG3_NVRAM_SIZE_256KB);
10558 else
10559 tp->nvram_size = (protect ? 0x1f200 :
10560 TG3_NVRAM_SIZE_128KB);
10561 break;
10562 case FLASH_5752VENDOR_ST_M45PE10:
10563 case FLASH_5752VENDOR_ST_M45PE20:
10564 case FLASH_5752VENDOR_ST_M45PE40:
10565 tp->nvram_jedecnum = JEDEC_ST;
10566 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10567 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10568 tp->nvram_pagesize = 256;
10569 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10570 tp->nvram_size = (protect ?
10571 TG3_NVRAM_SIZE_64KB :
10572 TG3_NVRAM_SIZE_128KB);
10573 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10574 tp->nvram_size = (protect ?
10575 TG3_NVRAM_SIZE_64KB :
10576 TG3_NVRAM_SIZE_256KB);
10577 else
10578 tp->nvram_size = (protect ?
10579 TG3_NVRAM_SIZE_128KB :
10580 TG3_NVRAM_SIZE_512KB);
10581 break;
d3c7b886
MC		 10582 }
10583}
10584
1b27777a
MC		 10585static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10586{
10587 u32 nvcfg1;
10588
10589 nvcfg1 = tr32(NVRAM_CFG1);
10590
10591 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10592 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10593 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10594 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10595 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10596 tp->nvram_jedecnum = JEDEC_ATMEL;
10597 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10598 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 10599
8590a603
MC		 10600 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10601 tw32(NVRAM_CFG1, nvcfg1);
10602 break;
10603 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10604 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10605 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10606 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10607 tp->nvram_jedecnum = JEDEC_ATMEL;
10608 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10609 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10610 tp->nvram_pagesize = 264;
10611 break;
10612 case FLASH_5752VENDOR_ST_M45PE10:
10613 case FLASH_5752VENDOR_ST_M45PE20:
10614 case FLASH_5752VENDOR_ST_M45PE40:
10615 tp->nvram_jedecnum = JEDEC_ST;
10616 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10617 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10618 tp->nvram_pagesize = 256;
10619 break;
1b27777a
MC		 10620 }
10621}
10622
6b91fa02
MC		 10623static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10624{
10625 u32 nvcfg1, protect = 0;
10626
10627 nvcfg1 = tr32(NVRAM_CFG1);
10628
10629 /* NVRAM protection for TPM */
10630 if (nvcfg1 & (1 << 27)) {
10631 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10632 protect = 1;
10633 }
10634
10635 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10636 switch (nvcfg1) {
8590a603
MC		 10637 case FLASH_5761VENDOR_ATMEL_ADB021D:
10638 case FLASH_5761VENDOR_ATMEL_ADB041D:
10639 case FLASH_5761VENDOR_ATMEL_ADB081D:
10640 case FLASH_5761VENDOR_ATMEL_ADB161D:
10641 case FLASH_5761VENDOR_ATMEL_MDB021D:
10642 case FLASH_5761VENDOR_ATMEL_MDB041D:
10643 case FLASH_5761VENDOR_ATMEL_MDB081D:
10644 case FLASH_5761VENDOR_ATMEL_MDB161D:
10645 tp->nvram_jedecnum = JEDEC_ATMEL;
10646 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10647 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10648 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10649 tp->nvram_pagesize = 256;
10650 break;
10651 case FLASH_5761VENDOR_ST_A_M45PE20:
10652 case FLASH_5761VENDOR_ST_A_M45PE40:
10653 case FLASH_5761VENDOR_ST_A_M45PE80:
10654 case FLASH_5761VENDOR_ST_A_M45PE16:
10655 case FLASH_5761VENDOR_ST_M_M45PE20:
10656 case FLASH_5761VENDOR_ST_M_M45PE40:
10657 case FLASH_5761VENDOR_ST_M_M45PE80:
10658 case FLASH_5761VENDOR_ST_M_M45PE16:
10659 tp->nvram_jedecnum = JEDEC_ST;
10660 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10661 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10662 tp->nvram_pagesize = 256;
10663 break;
6b91fa02
MC		 10664 }
10665
10666 if (protect) {
10667 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10668 } else {
10669 switch (nvcfg1) {
8590a603
MC		 10670 case FLASH_5761VENDOR_ATMEL_ADB161D:
10671 case FLASH_5761VENDOR_ATMEL_MDB161D:
10672 case FLASH_5761VENDOR_ST_A_M45PE16:
10673 case FLASH_5761VENDOR_ST_M_M45PE16:
10674 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10675 break;
10676 case FLASH_5761VENDOR_ATMEL_ADB081D:
10677 case FLASH_5761VENDOR_ATMEL_MDB081D:
10678 case FLASH_5761VENDOR_ST_A_M45PE80:
10679 case FLASH_5761VENDOR_ST_M_M45PE80:
10680 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10681 break;
10682 case FLASH_5761VENDOR_ATMEL_ADB041D:
10683 case FLASH_5761VENDOR_ATMEL_MDB041D:
10684 case FLASH_5761VENDOR_ST_A_M45PE40:
10685 case FLASH_5761VENDOR_ST_M_M45PE40:
10686 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10687 break;
10688 case FLASH_5761VENDOR_ATMEL_ADB021D:
10689 case FLASH_5761VENDOR_ATMEL_MDB021D:
10690 case FLASH_5761VENDOR_ST_A_M45PE20:
10691 case FLASH_5761VENDOR_ST_M_M45PE20:
10692 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10693 break;
6b91fa02
MC		 10694 }
10695 }
10696}
10697
b5d3772c
MC		 10698static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10699{
10700 tp->nvram_jedecnum = JEDEC_ATMEL;
10701 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10702 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10703}
10704
321d32a0
MC		 10705static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10706{
10707 u32 nvcfg1;
10708
10709 nvcfg1 = tr32(NVRAM_CFG1);
10710
10711 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10712 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10713 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10714 tp->nvram_jedecnum = JEDEC_ATMEL;
10715 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10716 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10717
10718 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10719 tw32(NVRAM_CFG1, nvcfg1);
10720 return;
10721 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10722 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10723 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10724 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10725 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10726 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10727 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10728 tp->nvram_jedecnum = JEDEC_ATMEL;
10729 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10730 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10731
10732 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10733 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10734 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10735 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10736 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10737 break;
10738 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10739 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10740 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10741 break;
10742 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10743 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10744 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10745 break;
10746 }
10747 break;
10748 case FLASH_5752VENDOR_ST_M45PE10:
10749 case FLASH_5752VENDOR_ST_M45PE20:
10750 case FLASH_5752VENDOR_ST_M45PE40:
10751 tp->nvram_jedecnum = JEDEC_ST;
10752 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10753 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10754
10755 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10756 case FLASH_5752VENDOR_ST_M45PE10:
10757 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10758 break;
10759 case FLASH_5752VENDOR_ST_M45PE20:
10760 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10761 break;
10762 case FLASH_5752VENDOR_ST_M45PE40:
10763 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10764 break;
10765 }
10766 break;
10767 default:
df259d8c 10768 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 10769 return;
10770 }
10771
10772 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10773 case FLASH_5752PAGE_SIZE_256:
10774 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10775 tp->nvram_pagesize = 256;
10776 break;
10777 case FLASH_5752PAGE_SIZE_512:
10778 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10779 tp->nvram_pagesize = 512;
10780 break;
10781 case FLASH_5752PAGE_SIZE_1K:
10782 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10783 tp->nvram_pagesize = 1024;
10784 break;
10785 case FLASH_5752PAGE_SIZE_2K:
10786 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10787 tp->nvram_pagesize = 2048;
10788 break;
10789 case FLASH_5752PAGE_SIZE_4K:
10790 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10791 tp->nvram_pagesize = 4096;
10792 break;
10793 case FLASH_5752PAGE_SIZE_264:
10794 tp->nvram_pagesize = 264;
10795 break;
10796 case FLASH_5752PAGE_SIZE_528:
10797 tp->nvram_pagesize = 528;
10798 break;
10799 }
10800}
10801
1da177e4
LT		 10802/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10803static void __devinit tg3_nvram_init(struct tg3 *tp)
10804{
1da177e4
LT		 10805 tw32_f(GRC_EEPROM_ADDR,
10806 (EEPROM_ADDR_FSM_RESET |
10807 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10808 EEPROM_ADDR_CLKPERD_SHIFT)));
10809
9d57f01c 10810 msleep(1);
1da177e4
LT		 10811
10812 /* Enable seeprom accesses. */
10813 tw32_f(GRC_LOCAL_CTRL,
10814 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10815 udelay(100);
10816
10817 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10818 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10819 tp->tg3_flags |= TG3_FLAG_NVRAM;
10820
ec41c7df
MC		 10821 if (tg3_nvram_lock(tp)) {
10822 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10823 "tg3_nvram_init failed.\n", tp->dev->name);
10824 return;
10825 }
e6af301b 10826 tg3_enable_nvram_access(tp);
1da177e4 10827
989a9d23
MC		 10828 tp->nvram_size = 0;
10829
361b4ac2
MC		 10830 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10831 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10832 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10833 tg3_get_5755_nvram_info(tp);
d30cdd28 10834 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10837 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10838 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10839 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10840 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10841 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10842 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10843 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10844 else
10845 tg3_get_nvram_info(tp);
10846
989a9d23
MC		 10847 if (tp->nvram_size == 0)
10848 tg3_get_nvram_size(tp);
1da177e4 10849
e6af301b 10850 tg3_disable_nvram_access(tp);
381291b7 10851 tg3_nvram_unlock(tp);
1da177e4
LT		 10852
10853 } else {
10854 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10855
10856 tg3_get_eeprom_size(tp);
10857 }
10858}
10859
1da177e4
LT		 10860static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10861 u32 offset, u32 len, u8 *buf)
10862{
10863 int i, j, rc = 0;
10864 u32 val;
10865
10866 for (i = 0; i < len; i += 4) {
b9fc7dc5 10867 u32 addr;
a9dc529d 10868 __be32 data;
1da177e4
LT		 10869
10870 addr = offset + i;
10871
10872 memcpy(&data, buf + i, 4);
10873
62cedd11
MC		 10874 /*
10875 * The SEEPROM interface expects the data to always be opposite
10876 * the native endian format. We accomplish this by reversing
10877 * all the operations that would have been performed on the
10878 * data from a call to tg3_nvram_read_be32().
10879 */
10880 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10881
10882 val = tr32(GRC_EEPROM_ADDR);
10883 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10884
10885 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10886 EEPROM_ADDR_READ);
10887 tw32(GRC_EEPROM_ADDR, val |
10888 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10889 (addr & EEPROM_ADDR_ADDR_MASK) |
10890 EEPROM_ADDR_START |
10891 EEPROM_ADDR_WRITE);
6aa20a22 10892
9d57f01c 10893 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10894 val = tr32(GRC_EEPROM_ADDR);
10895
10896 if (val & EEPROM_ADDR_COMPLETE)
10897 break;
9d57f01c 10898 msleep(1);
1da177e4
LT		 10899 }
10900 if (!(val & EEPROM_ADDR_COMPLETE)) {
10901 rc = -EBUSY;
10902 break;
10903 }
10904 }
10905
10906 return rc;
10907}
10908
10909/* offset and length are dword aligned */
10910static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10911 u8 *buf)
10912{
10913 int ret = 0;
10914 u32 pagesize = tp->nvram_pagesize;
10915 u32 pagemask = pagesize - 1;
10916 u32 nvram_cmd;
10917 u8 *tmp;
10918
10919 tmp = kmalloc(pagesize, GFP_KERNEL);
10920 if (tmp == NULL)
10921 return -ENOMEM;
10922
10923 while (len) {
10924 int j;
e6af301b 10925 u32 phy_addr, page_off, size;
1da177e4
LT		 10926
10927 phy_addr = offset & ~pagemask;
6aa20a22 10928
1da177e4 10929 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10930 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10931 (__be32 *) (tmp + j));
10932 if (ret)
1da177e4
LT		 10933 break;
10934 }
10935 if (ret)
10936 break;
10937
10938 page_off = offset & pagemask;
10939 size = pagesize;
10940 if (len < size)
10941 size = len;
10942
10943 len -= size;
10944
10945 memcpy(tmp + page_off, buf, size);
10946
10947 offset = offset + (pagesize - page_off);
10948
e6af301b 10949 tg3_enable_nvram_access(tp);
1da177e4
LT		 10950
10951 /*
10952 * Before we can erase the flash page, we need
10953 * to issue a special "write enable" command.
10954 */
10955 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10956
10957 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10958 break;
10959
10960 /* Erase the target page */
10961 tw32(NVRAM_ADDR, phy_addr);
10962
10963 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10964 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10965
10966 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10967 break;
10968
10969 /* Issue another write enable to start the write. */
10970 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10971
10972 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10973 break;
10974
10975 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 10976 __be32 data;
1da177e4 10977
b9fc7dc5 10978 data = *((__be32 *) (tmp + j));
a9dc529d 10979
b9fc7dc5 10980 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 10981
10982 tw32(NVRAM_ADDR, phy_addr + j);
10983
10984 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10985 NVRAM_CMD_WR;
10986
10987 if (j == 0)
10988 nvram_cmd |= NVRAM_CMD_FIRST;
10989 else if (j == (pagesize - 4))
10990 nvram_cmd |= NVRAM_CMD_LAST;
10991
10992 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10993 break;
10994 }
10995 if (ret)
10996 break;
10997 }
10998
10999 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11000 tg3_nvram_exec_cmd(tp, nvram_cmd);
11001
11002 kfree(tmp);
11003
11004 return ret;
11005}
11006
11007/* offset and length are dword aligned */
11008static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11009 u8 *buf)
11010{
11011 int i, ret = 0;
11012
11013 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11014 u32 page_off, phy_addr, nvram_cmd;
11015 __be32 data;
1da177e4
LT		 11016
11017 memcpy(&data, buf + i, 4);
b9fc7dc5 11018 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11019
11020 page_off = offset % tp->nvram_pagesize;
11021
1820180b 11022 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11023
11024 tw32(NVRAM_ADDR, phy_addr);
11025
11026 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11027
11028 if ((page_off == 0) || (i == 0))
11029 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11030 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11031 nvram_cmd |= NVRAM_CMD_LAST;
11032
11033 if (i == (len - 4))
11034 nvram_cmd |= NVRAM_CMD_LAST;
11035
321d32a0
MC		 11036 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11037 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11038 (tp->nvram_jedecnum == JEDEC_ST) &&
11039 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11040
11041 if ((ret = tg3_nvram_exec_cmd(tp,
11042 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11043 NVRAM_CMD_DONE)))
11044
11045 break;
11046 }
11047 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11048 /* We always do complete word writes to eeprom. */
11049 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11050 }
11051
11052 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11053 break;
11054 }
11055 return ret;
11056}
11057
11058/* offset and length are dword aligned */
11059static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11060{
11061 int ret;
11062
1da177e4 11063 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11064 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11065 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11066 udelay(40);
11067 }
11068
11069 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11070 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11071 }
11072 else {
11073 u32 grc_mode;
11074
ec41c7df
MC		 11075 ret = tg3_nvram_lock(tp);
11076 if (ret)
11077 return ret;
1da177e4 11078
e6af301b
MC		 11079 tg3_enable_nvram_access(tp);
11080 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11081 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11082 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11083
11084 grc_mode = tr32(GRC_MODE);
11085 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11086
11087 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11088 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11089
11090 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11091 buf);
11092 }
11093 else {
11094 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11095 buf);
11096 }
11097
11098 grc_mode = tr32(GRC_MODE);
11099 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11100
e6af301b 11101 tg3_disable_nvram_access(tp);
1da177e4
LT		 11102 tg3_nvram_unlock(tp);
11103 }
11104
11105 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11106 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11107 udelay(40);
11108 }
11109
11110 return ret;
11111}
11112
11113struct subsys_tbl_ent {
11114 u16 subsys_vendor, subsys_devid;
11115 u32 phy_id;
11116};
11117
11118static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11119 /* Broadcom boards. */
11120 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11121 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11122 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11123 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11124 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11125 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11126 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11127 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11128 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11129 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11130 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11131
11132 /* 3com boards. */
11133 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11134 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11135 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11136 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11137 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11138
11139 /* DELL boards. */
11140 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11141 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11142 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11143 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11144
11145 /* Compaq boards. */
11146 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11147 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11148 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11149 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11150 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11151
11152 /* IBM boards. */
11153 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11154};
11155
11156static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11157{
11158 int i;
11159
11160 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11161 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11162 tp->pdev->subsystem_vendor) &&
11163 (subsys_id_to_phy_id[i].subsys_devid ==
11164 tp->pdev->subsystem_device))
11165 return &subsys_id_to_phy_id[i];
11166 }
11167 return NULL;
11168}
11169
7d0c41ef 11170static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11171{
1da177e4 11172 u32 val;
caf636c7
MC		 11173 u16 pmcsr;
11174
11175 /* On some early chips the SRAM cannot be accessed in D3hot state,
11176 * so need make sure we're in D0.
11177 */
11178 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11179 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11180 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11181 msleep(1);
7d0c41ef
MC		 11182
11183 /* Make sure register accesses (indirect or otherwise)
11184 * will function correctly.
11185 */
11186 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11187 tp->misc_host_ctrl);
1da177e4 11188
f49639e6
DM		 11189 /* The memory arbiter has to be enabled in order for SRAM accesses
11190 * to succeed. Normally on powerup the tg3 chip firmware will make
11191 * sure it is enabled, but other entities such as system netboot
11192 * code might disable it.
11193 */
11194 val = tr32(MEMARB_MODE);
11195 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11196
1da177e4 11197 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11198 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11199
a85feb8c
GZ		 11200 /* Assume an onboard device and WOL capable by default. */
11201 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11202
b5d3772c 11203 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11204 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11205 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11206 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11207 }
0527ba35
MC		 11208 val = tr32(VCPU_CFGSHDW);
11209 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11210 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11211 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11212 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11213 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11214 goto done;
b5d3772c
MC		 11215 }
11216
1da177e4
LT		 11217 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11218 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11219 u32 nic_cfg, led_cfg;
a9daf367 11220 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11221 int eeprom_phy_serdes = 0;
1da177e4
LT		 11222
11223 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11224 tp->nic_sram_data_cfg = nic_cfg;
11225
11226 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11227 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11228 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11229 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11230 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11231 (ver > 0) && (ver < 0x100))
11232 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11233
a9daf367
MC		 11234 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11235 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11236
1da177e4
LT		 11237 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11238 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11239 eeprom_phy_serdes = 1;
11240
11241 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11242 if (nic_phy_id != 0) {
11243 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11244 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11245
11246 eeprom_phy_id = (id1 >> 16) << 10;
11247 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11248 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11249 } else
11250 eeprom_phy_id = 0;
11251
7d0c41ef 11252 tp->phy_id = eeprom_phy_id;
747e8f8b 11253 if (eeprom_phy_serdes) {
a4e2b347 11254 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11255 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11256 else
11257 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11258 }
7d0c41ef 11259
cbf46853 11260 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11261 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11262 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11263 else
1da177e4
LT		 11264 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11265
11266 switch (led_cfg) {
11267 default:
11268 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11269 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11270 break;
11271
11272 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11273 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11274 break;
11275
11276 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11277 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11278
11279 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11280 * read on some older 5700/5701 bootcode.
11281 */
11282 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11283 ASIC_REV_5700 ||
11284 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11285 ASIC_REV_5701)
11286 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11287
1da177e4
LT		 11288 break;
11289
11290 case SHASTA_EXT_LED_SHARED:
11291 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11292 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11293 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11294 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11295 LED_CTRL_MODE_PHY_2);
11296 break;
11297
11298 case SHASTA_EXT_LED_MAC:
11299 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11300 break;
11301
11302 case SHASTA_EXT_LED_COMBO:
11303 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11304 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11305 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11306 LED_CTRL_MODE_PHY_2);
11307 break;
11308
855e1111 11309 }
1da177e4
LT		 11310
11311 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11313 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11314 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11315
b2a5c19c
MC		 11316 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11317 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11318
9d26e213 11319 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11320 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11321 if ((tp->pdev->subsystem_vendor ==
11322 PCI_VENDOR_ID_ARIMA) &&
11323 (tp->pdev->subsystem_device == 0x205a ||
11324 tp->pdev->subsystem_device == 0x2063))
11325 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11326 } else {
f49639e6 11327 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11328 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11329 }
1da177e4
LT		 11330
11331 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11332 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11333 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11334 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11335 }
b2b98d4a
MC		 11336
11337 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11338 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11339 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11340
a85feb8c
GZ		 11341 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11342 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11343 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11344
12dac075 11345 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11346 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11347 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11348
1da177e4
LT		 11349 if (cfg2 & (1 << 17))
11350 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11351
11352 /* serdes signal pre-emphasis in register 0x590 set by */
11353 /* bootcode if bit 18 is set */
11354 if (cfg2 & (1 << 18))
11355 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11356
321d32a0
MC		 11357 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11358 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11359 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11360 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11361
8ed5d97e
MC		 11362 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11363 u32 cfg3;
11364
11365 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11366 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11367 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11368 }
a9daf367
MC		 11369
11370 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11371 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11372 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11373 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11374 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11375 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11376 }
05ac4cb7
MC		 11377done:
11378 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11379 device_set_wakeup_enable(&tp->pdev->dev,
11380 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11381}
11382
b2a5c19c
MC		 11383static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11384{
11385 int i;
11386 u32 val;
11387
11388 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11389 tw32(OTP_CTRL, cmd);
11390
11391 /* Wait for up to 1 ms for command to execute. */
11392 for (i = 0; i < 100; i++) {
11393 val = tr32(OTP_STATUS);
11394 if (val & OTP_STATUS_CMD_DONE)
11395 break;
11396 udelay(10);
11397 }
11398
11399 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11400}
11401
11402/* Read the gphy configuration from the OTP region of the chip. The gphy
11403 * configuration is a 32-bit value that straddles the alignment boundary.
11404 * We do two 32-bit reads and then shift and merge the results.
11405 */
11406static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11407{
11408 u32 bhalf_otp, thalf_otp;
11409
11410 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11411
11412 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11413 return 0;
11414
11415 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11416
11417 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11418 return 0;
11419
11420 thalf_otp = tr32(OTP_READ_DATA);
11421
11422 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11423
11424 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11425 return 0;
11426
11427 bhalf_otp = tr32(OTP_READ_DATA);
11428
11429 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11430}
11431
7d0c41ef
MC		 11432static int __devinit tg3_phy_probe(struct tg3 *tp)
11433{
11434 u32 hw_phy_id_1, hw_phy_id_2;
11435 u32 hw_phy_id, hw_phy_id_masked;
11436 int err;
1da177e4 11437
b02fd9e3
MC		 11438 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11439 return tg3_phy_init(tp);
11440
1da177e4 11441 /* Reading the PHY ID register can conflict with ASF
877d0310 11442 * firmware access to the PHY hardware.
1da177e4
LT		 11443 */
11444 err = 0;
0d3031d9
MC		 11445 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11446 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11447 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11448 } else {
11449 /* Now read the physical PHY_ID from the chip and verify
11450 * that it is sane. If it doesn't look good, we fall back
11451 * to either the hard-coded table based PHY_ID and failing
11452 * that the value found in the eeprom area.
11453 */
11454 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11455 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11456
11457 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11458 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11459 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11460
11461 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11462 }
11463
11464 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11465 tp->phy_id = hw_phy_id;
11466 if (hw_phy_id_masked == PHY_ID_BCM8002)
11467 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11468 else
11469 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11470 } else {
7d0c41ef
MC		 11471 if (tp->phy_id != PHY_ID_INVALID) {
11472 /* Do nothing, phy ID already set up in
11473 * tg3_get_eeprom_hw_cfg().
11474 */
1da177e4
LT		 11475 } else {
11476 struct subsys_tbl_ent *p;
11477
11478 /* No eeprom signature? Try the hardcoded
11479 * subsys device table.
11480 */
11481 p = lookup_by_subsys(tp);
11482 if (!p)
11483 return -ENODEV;
11484
11485 tp->phy_id = p->phy_id;
11486 if (!tp->phy_id ||
11487 tp->phy_id == PHY_ID_BCM8002)
11488 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11489 }
11490 }
11491
747e8f8b 11492 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11493 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11494 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11495 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11496
11497 tg3_readphy(tp, MII_BMSR, &bmsr);
11498 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11499 (bmsr & BMSR_LSTATUS))
11500 goto skip_phy_reset;
6aa20a22 11501
1da177e4
LT		 11502 err = tg3_phy_reset(tp);
11503 if (err)
11504 return err;
11505
11506 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11507 ADVERTISE_100HALF | ADVERTISE_100FULL |
11508 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11509 tg3_ctrl = 0;
11510 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11511 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11512 MII_TG3_CTRL_ADV_1000_FULL);
11513 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11514 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11515 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11516 MII_TG3_CTRL_ENABLE_AS_MASTER);
11517 }
11518
3600d918
MC		 11519 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11520 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11521 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11522 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11523 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11524
11525 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11526 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11527
11528 tg3_writephy(tp, MII_BMCR,
11529 BMCR_ANENABLE | BMCR_ANRESTART);
11530 }
11531 tg3_phy_set_wirespeed(tp);
11532
11533 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11534 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11535 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11536 }
11537
11538skip_phy_reset:
11539 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11540 err = tg3_init_5401phy_dsp(tp);
11541 if (err)
11542 return err;
11543 }
11544
11545 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11546 err = tg3_init_5401phy_dsp(tp);
11547 }
11548
747e8f8b 11549 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11550 tp->link_config.advertising =
11551 (ADVERTISED_1000baseT_Half |
11552 ADVERTISED_1000baseT_Full |
11553 ADVERTISED_Autoneg |
11554 ADVERTISED_FIBRE);
11555 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11556 tp->link_config.advertising &=
11557 ~(ADVERTISED_1000baseT_Half |
11558 ADVERTISED_1000baseT_Full);
11559
11560 return err;
11561}
11562
11563static void __devinit tg3_read_partno(struct tg3 *tp)
11564{
6d348f2c 11565 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11566 unsigned int i;
1b27777a 11567 u32 magic;
1da177e4 11568
df259d8c
MC		 11569 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11570 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11571 goto out_not_found;
1da177e4 11572
1820180b 11573 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11574 for (i = 0; i < 256; i += 4) {
11575 u32 tmp;
1da177e4 11576
6d348f2c
MC		 11577 /* The data is in little-endian format in NVRAM.
11578 * Use the big-endian read routines to preserve
11579 * the byte order as it exists in NVRAM.
11580 */
11581 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11582 goto out_not_found;
11583
6d348f2c 11584 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11585 }
11586 } else {
11587 int vpd_cap;
11588
11589 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11590 for (i = 0; i < 256; i += 4) {
11591 u32 tmp, j = 0;
b9fc7dc5 11592 __le32 v;
1b27777a
MC		 11593 u16 tmp16;
11594
11595 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11596 i);
11597 while (j++ < 100) {
11598 pci_read_config_word(tp->pdev, vpd_cap +
11599 PCI_VPD_ADDR, &tmp16);
11600 if (tmp16 & 0x8000)
11601 break;
11602 msleep(1);
11603 }
f49639e6
DM		 11604 if (!(tmp16 & 0x8000))
11605 goto out_not_found;
11606
1b27777a
MC		 11607 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11608 &tmp);
b9fc7dc5 11609 v = cpu_to_le32(tmp);
6d348f2c 11610 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11611 }
1da177e4
LT		 11612 }
11613
11614 /* Now parse and find the part number. */
af2c6a4a 11615 for (i = 0; i < 254; ) {
1da177e4 11616 unsigned char val = vpd_data[i];
af2c6a4a 11617 unsigned int block_end;
1da177e4
LT		 11618
11619 if (val == 0x82 || val == 0x91) {
11620 i = (i + 3 +
11621 (vpd_data[i + 1] +
11622 (vpd_data[i + 2] << 8)));
11623 continue;
11624 }
11625
11626 if (val != 0x90)
11627 goto out_not_found;
11628
11629 block_end = (i + 3 +
11630 (vpd_data[i + 1] +
11631 (vpd_data[i + 2] << 8)));
11632 i += 3;
af2c6a4a
MC		 11633
11634 if (block_end > 256)
11635 goto out_not_found;
11636
11637 while (i < (block_end - 2)) {
1da177e4
LT		 11638 if (vpd_data[i + 0] == 'P' &&
11639 vpd_data[i + 1] == 'N') {
11640 int partno_len = vpd_data[i + 2];
11641
af2c6a4a
MC		 11642 i += 3;
11643 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11644 goto out_not_found;
11645
11646 memcpy(tp->board_part_number,
af2c6a4a 11647 &vpd_data[i], partno_len);
1da177e4
LT		 11648
11649 /* Success. */
11650 return;
11651 }
af2c6a4a 11652 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11653 }
11654
11655 /* Part number not found. */
11656 goto out_not_found;
11657 }
11658
11659out_not_found:
b5d3772c
MC		 11660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11661 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 11662 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11663 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11664 strcpy(tp->board_part_number, "BCM57780");
11665 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11666 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11667 strcpy(tp->board_part_number, "BCM57760");
11668 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11669 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11670 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 11671 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11672 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11673 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 11674 else
11675 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11676}
11677
9c8a620e
MC		 11678static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11679{
11680 u32 val;
11681
e4f34110 11682 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11683 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11684 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11685 val != 0)
11686 return 0;
11687
11688 return 1;
11689}
11690
acd9c119
MC		 11691static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11692{
ff3a7cb2 11693 u32 val, offset, start, ver_offset;
acd9c119 11694 int i;
ff3a7cb2 11695 bool newver = false;
acd9c119
MC		 11696
11697 if (tg3_nvram_read(tp, 0xc, &offset) ||
11698 tg3_nvram_read(tp, 0x4, &start))
11699 return;
11700
11701 offset = tg3_nvram_logical_addr(tp, offset);
11702
ff3a7cb2 11703 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11704 return;
11705
ff3a7cb2
MC		 11706 if ((val & 0xfc000000) == 0x0c000000) {
11707 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11708 return;
11709
ff3a7cb2
MC		 11710 if (val == 0)
11711 newver = true;
11712 }
11713
11714 if (newver) {
11715 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11716 return;
11717
11718 offset = offset + ver_offset - start;
11719 for (i = 0; i < 16; i += 4) {
11720 __be32 v;
11721 if (tg3_nvram_read_be32(tp, offset + i, &v))
11722 return;
11723
11724 memcpy(tp->fw_ver + i, &v, sizeof(v));
11725 }
11726 } else {
11727 u32 major, minor;
11728
11729 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11730 return;
11731
11732 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11733 TG3_NVM_BCVER_MAJSFT;
11734 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11735 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11736 }
11737}
11738
a6f6cb1c
MC		 11739static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11740{
11741 u32 val, major, minor;
11742
11743 /* Use native endian representation */
11744 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11745 return;
11746
11747 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11748 TG3_NVM_HWSB_CFG1_MAJSFT;
11749 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11750 TG3_NVM_HWSB_CFG1_MINSFT;
11751
11752 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11753}
11754
dfe00d7d
MC		 11755static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11756{
11757 u32 offset, major, minor, build;
11758
11759 tp->fw_ver[0] = 's';
11760 tp->fw_ver[1] = 'b';
11761 tp->fw_ver[2] = '\0';
11762
11763 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11764 return;
11765
11766 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11767 case TG3_EEPROM_SB_REVISION_0:
11768 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11769 break;
11770 case TG3_EEPROM_SB_REVISION_2:
11771 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11772 break;
11773 case TG3_EEPROM_SB_REVISION_3:
11774 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11775 break;
11776 default:
11777 return;
11778 }
11779
e4f34110 11780 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11781 return;
11782
11783 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11784 TG3_EEPROM_SB_EDH_BLD_SHFT;
11785 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11786 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11787 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11788
11789 if (minor > 99 || build > 26)
11790 return;
11791
11792 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11793
11794 if (build > 0) {
11795 tp->fw_ver[8] = 'a' + build - 1;
11796 tp->fw_ver[9] = '\0';
11797 }
11798}
11799
acd9c119 11800static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11801{
11802 u32 val, offset, start;
acd9c119 11803 int i, vlen;
9c8a620e
MC		 11804
11805 for (offset = TG3_NVM_DIR_START;
11806 offset < TG3_NVM_DIR_END;
11807 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11808 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11809 return;
11810
9c8a620e
MC		 11811 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11812 break;
11813 }
11814
11815 if (offset == TG3_NVM_DIR_END)
11816 return;
11817
11818 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11819 start = 0x08000000;
e4f34110 11820 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11821 return;
11822
e4f34110 11823 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11824 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11825 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11826 return;
11827
11828 offset += val - start;
11829
acd9c119 11830 vlen = strlen(tp->fw_ver);
9c8a620e 11831
acd9c119
MC		 11832 tp->fw_ver[vlen++] = ',';
11833 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11834
11835 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11836 __be32 v;
11837 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11838 return;
11839
b9fc7dc5 11840 offset += sizeof(v);
c4e6575c 11841
acd9c119
MC		 11842 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11843 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11844 break;
c4e6575c 11845 }
9c8a620e 11846
acd9c119
MC		 11847 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11848 vlen += sizeof(v);
c4e6575c 11849 }
acd9c119
MC		 11850}
11851
7fd76445
MC		 11852static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11853{
11854 int vlen;
11855 u32 apedata;
11856
11857 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11858 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11859 return;
11860
11861 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11862 if (apedata != APE_SEG_SIG_MAGIC)
11863 return;
11864
11865 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11866 if (!(apedata & APE_FW_STATUS_READY))
11867 return;
11868
11869 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11870
11871 vlen = strlen(tp->fw_ver);
11872
11873 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11874 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11875 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11876 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11877 (apedata & APE_FW_VERSION_BLDMSK));
11878}
11879
acd9c119
MC		 11880static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11881{
11882 u32 val;
11883
df259d8c
MC		 11884 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11885 tp->fw_ver[0] = 's';
11886 tp->fw_ver[1] = 'b';
11887 tp->fw_ver[2] = '\0';
11888
11889 return;
11890 }
11891
acd9c119
MC		 11892 if (tg3_nvram_read(tp, 0, &val))
11893 return;
11894
11895 if (val == TG3_EEPROM_MAGIC)
11896 tg3_read_bc_ver(tp);
11897 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11898 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11899 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11900 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11901 else
11902 return;
11903
11904 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11905 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11906 return;
11907
11908 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11909
11910 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11911}
11912
7544b097
MC		 11913static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11914
1da177e4
LT		 11915static int __devinit tg3_get_invariants(struct tg3 *tp)
11916{
11917 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11918 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11919 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11920 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11921 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11922 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11923 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11924 { },
11925 };
11926 u32 misc_ctrl_reg;
1da177e4
LT		 11927 u32 pci_state_reg, grc_misc_cfg;
11928 u32 val;
11929 u16 pci_cmd;
5e7dfd0f 11930 int err;
1da177e4 11931
1da177e4
LT		 11932 /* Force memory write invalidate off. If we leave it on,
11933 * then on 5700_BX chips we have to enable a workaround.
11934 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11935 * to match the cacheline size. The Broadcom driver have this
11936 * workaround but turns MWI off all the times so never uses
11937 * it. This seems to suggest that the workaround is insufficient.
11938 */
11939 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11940 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11941 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11942
11943 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11944 * has the register indirect write enable bit set before
11945 * we try to access any of the MMIO registers. It is also
11946 * critical that the PCI-X hw workaround situation is decided
11947 * before that as well.
11948 */
11949 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11950 &misc_ctrl_reg);
11951
11952 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11953 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11955 u32 prod_id_asic_rev;
11956
11957 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11958 &prod_id_asic_rev);
321d32a0 11959 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11960 }
1da177e4 11961
ff645bec
MC		 11962 /* Wrong chip ID in 5752 A0. This code can be removed later
11963 * as A0 is not in production.
11964 */
11965 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11966 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11967
6892914f
MC		 11968 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11969 * we need to disable memory and use config. cycles
11970 * only to access all registers. The 5702/03 chips
11971 * can mistakenly decode the special cycles from the
11972 * ICH chipsets as memory write cycles, causing corruption
11973 * of register and memory space. Only certain ICH bridges
11974 * will drive special cycles with non-zero data during the
11975 * address phase which can fall within the 5703's address
11976 * range. This is not an ICH bug as the PCI spec allows
11977 * non-zero address during special cycles. However, only
11978 * these ICH bridges are known to drive non-zero addresses
11979 * during special cycles.
11980 *
11981 * Since special cycles do not cross PCI bridges, we only
11982 * enable this workaround if the 5703 is on the secondary
11983 * bus of these ICH bridges.
11984 */
11985 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11986 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11987 static struct tg3_dev_id {
11988 u32 vendor;
11989 u32 device;
11990 u32 rev;
11991 } ich_chipsets[] = {
11992 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11993 PCI_ANY_ID },
11994 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11995 PCI_ANY_ID },
11996 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11997 0xa },
11998 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11999 PCI_ANY_ID },
12000 { },
12001 };
12002 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12003 struct pci_dev *bridge = NULL;
12004
12005 while (pci_id->vendor != 0) {
12006 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12007 bridge);
12008 if (!bridge) {
12009 pci_id++;
12010 continue;
12011 }
12012 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12013 if (bridge->revision > pci_id->rev)
6892914f
MC		 12014 continue;
12015 }
12016 if (bridge->subordinate &&
12017 (bridge->subordinate->number ==
12018 tp->pdev->bus->number)) {
12019
12020 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12021 pci_dev_put(bridge);
12022 break;
12023 }
12024 }
12025 }
12026
41588ba1
MC		 12027 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12028 static struct tg3_dev_id {
12029 u32 vendor;
12030 u32 device;
12031 } bridge_chipsets[] = {
12032 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12033 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12034 { },
12035 };
12036 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12037 struct pci_dev *bridge = NULL;
12038
12039 while (pci_id->vendor != 0) {
12040 bridge = pci_get_device(pci_id->vendor,
12041 pci_id->device,
12042 bridge);
12043 if (!bridge) {
12044 pci_id++;
12045 continue;
12046 }
12047 if (bridge->subordinate &&
12048 (bridge->subordinate->number <=
12049 tp->pdev->bus->number) &&
12050 (bridge->subordinate->subordinate >=
12051 tp->pdev->bus->number)) {
12052 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12053 pci_dev_put(bridge);
12054 break;
12055 }
12056 }
12057 }
12058
4a29cc2e
MC		 12059 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12060 * DMA addresses > 40-bit. This bridge may have other additional
12061 * 57xx devices behind it in some 4-port NIC designs for example.
12062 * Any tg3 device found behind the bridge will also need the 40-bit
12063 * DMA workaround.
12064 */
a4e2b347
MC		 12065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12067 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12068 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12069 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12070 }
4a29cc2e
MC		 12071 else {
12072 struct pci_dev *bridge = NULL;
12073
12074 do {
12075 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12076 PCI_DEVICE_ID_SERVERWORKS_EPB,
12077 bridge);
12078 if (bridge && bridge->subordinate &&
12079 (bridge->subordinate->number <=
12080 tp->pdev->bus->number) &&
12081 (bridge->subordinate->subordinate >=
12082 tp->pdev->bus->number)) {
12083 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12084 pci_dev_put(bridge);
12085 break;
12086 }
12087 } while (bridge);
12088 }
4cf78e4f 12089
1da177e4
LT		 12090 /* Initialize misc host control in PCI block. */
12091 tp->misc_host_ctrl |= (misc_ctrl_reg &
12092 MISC_HOST_CTRL_CHIPREV);
12093 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12094 tp->misc_host_ctrl);
12095
7544b097
MC		 12096 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12097 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12098 tp->pdev_peer = tg3_find_peer(tp);
12099
321d32a0
MC		 12100 /* Intentionally exclude ASIC_REV_5906 */
12101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 12106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12107 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12108
12109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12112 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12113 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12114 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12115
1b440c56
JL		 12116 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12117 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12118 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12119
027455ad
MC		 12120 /* 5700 B0 chips do not support checksumming correctly due
12121 * to hardware bugs.
12122 */
12123 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12124 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12125 else {
12126 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12127 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12128 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12129 tp->dev->features |= NETIF_F_IPV6_CSUM;
12130 }
12131
5a6f3074 12132 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12133 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12134 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12135 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12137 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12138 tp->pdev_peer == tp->pdev))
12139 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12140
321d32a0 12141 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12142 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12143 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12144 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12145 } else {
7f62ad5d 12146 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12147 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12148 ASIC_REV_5750 &&
12149 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12150 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12151 }
5a6f3074 12152 }
1da177e4 12153
f51f3562
MC		 12154 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12155 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8f666b07 12156 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12157
52f4490c
MC		 12158 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12159 &pci_state_reg);
12160
5e7dfd0f
MC		 12161 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12162 if (tp->pcie_cap != 0) {
12163 u16 lnkctl;
12164
1da177e4 12165 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12166
12167 pcie_set_readrq(tp->pdev, 4096);
12168
5e7dfd0f
MC		 12169 pci_read_config_word(tp->pdev,
12170 tp->pcie_cap + PCI_EXP_LNKCTL,
12171 &lnkctl);
12172 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12174 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12176 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12177 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12178 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12179 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12180 }
52f4490c 12181 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12182 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12183 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12184 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12185 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12186 if (!tp->pcix_cap) {
12187 printk(KERN_ERR PFX "Cannot find PCI-X "
12188 "capability, aborting.\n");
12189 return -EIO;
12190 }
12191
12192 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12193 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12194 }
1da177e4 12195
399de50b
MC		 12196 /* If we have an AMD 762 or VIA K8T800 chipset, write
12197 * reordering to the mailbox registers done by the host
12198 * controller can cause major troubles. We read back from
12199 * every mailbox register write to force the writes to be
12200 * posted to the chip in order.
12201 */
12202 if (pci_dev_present(write_reorder_chipsets) &&
12203 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12204 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12205
69fc4053
MC		 12206 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12207 &tp->pci_cacheline_sz);
12208 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12209 &tp->pci_lat_timer);
1da177e4
LT		 12210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12211 tp->pci_lat_timer < 64) {
12212 tp->pci_lat_timer = 64;
69fc4053
MC		 12213 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12214 tp->pci_lat_timer);
1da177e4
LT		 12215 }
12216
52f4490c
MC		 12217 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12218 /* 5700 BX chips need to have their TX producer index
12219 * mailboxes written twice to workaround a bug.
12220 */
12221 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12222
52f4490c 12223 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12224 *
12225 * The workaround is to use indirect register accesses
12226 * for all chip writes not to mailbox registers.
12227 */
52f4490c 12228 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12229 u32 pm_reg;
1da177e4
LT		 12230
12231 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12232
12233 /* The chip can have it's power management PCI config
12234 * space registers clobbered due to this bug.
12235 * So explicitly force the chip into D0 here.
12236 */
9974a356
MC		 12237 pci_read_config_dword(tp->pdev,
12238 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12239 &pm_reg);
12240 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12241 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12242 pci_write_config_dword(tp->pdev,
12243 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12244 pm_reg);
12245
12246 /* Also, force SERR#/PERR# in PCI command. */
12247 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12248 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12249 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12250 }
12251 }
12252
1da177e4
LT		 12253 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12254 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12255 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12256 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12257
12258 /* Chip-specific fixup from Broadcom driver */
12259 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12260 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12261 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12262 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12263 }
12264
1ee582d8 12265 /* Default fast path register access methods */
20094930 12266 tp->read32 = tg3_read32;
1ee582d8 12267 tp->write32 = tg3_write32;
09ee929c 12268 tp->read32_mbox = tg3_read32;
20094930 12269 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12270 tp->write32_tx_mbox = tg3_write32;
12271 tp->write32_rx_mbox = tg3_write32;
12272
12273 /* Various workaround register access methods */
12274 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12275 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12276 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12277 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12278 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12279 /*
12280 * Back to back register writes can cause problems on these
12281 * chips, the workaround is to read back all reg writes
12282 * except those to mailbox regs.
12283 *
12284 * See tg3_write_indirect_reg32().
12285 */
1ee582d8 12286 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12287 }
12288
1ee582d8
MC		 12289
12290 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12291 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12292 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12293 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12294 tp->write32_rx_mbox = tg3_write_flush_reg32;
12295 }
20094930 12296
6892914f
MC		 12297 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12298 tp->read32 = tg3_read_indirect_reg32;
12299 tp->write32 = tg3_write_indirect_reg32;
12300 tp->read32_mbox = tg3_read_indirect_mbox;
12301 tp->write32_mbox = tg3_write_indirect_mbox;
12302 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12303 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12304
12305 iounmap(tp->regs);
22abe310 12306 tp->regs = NULL;
6892914f
MC		 12307
12308 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12309 pci_cmd &= ~PCI_COMMAND_MEMORY;
12310 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12311 }
b5d3772c
MC		 12312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12313 tp->read32_mbox = tg3_read32_mbox_5906;
12314 tp->write32_mbox = tg3_write32_mbox_5906;
12315 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12316 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12317 }
6892914f 12318
bbadf503
MC		 12319 if (tp->write32 == tg3_write_indirect_reg32 ||
12320 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12321 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12322 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12323 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12324
7d0c41ef 12325 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12326 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12327 * determined before calling tg3_set_power_state() so that
12328 * we know whether or not to switch out of Vaux power.
12329 * When the flag is set, it means that GPIO1 is used for eeprom
12330 * write protect and also implies that it is a LOM where GPIOs
12331 * are not used to switch power.
6aa20a22 12332 */
7d0c41ef
MC		 12333 tg3_get_eeprom_hw_cfg(tp);
12334
0d3031d9
MC		 12335 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12336 /* Allow reads and writes to the
12337 * APE register and memory space.
12338 */
12339 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12340 PCISTATE_ALLOW_APE_SHMEM_WR;
12341 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12342 pci_state_reg);
12343 }
12344
9936bcf6 12345 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12349 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12350
314fba34
MC		 12351 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12352 * GPIO1 driven high will bring 5700's external PHY out of reset.
12353 * It is also used as eeprom write protect on LOMs.
12354 */
12355 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12356 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12357 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12358 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12359 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12360 /* Unused GPIO3 must be driven as output on 5752 because there
12361 * are no pull-up resistors on unused GPIO pins.
12362 */
12363 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12364 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12365
321d32a0
MC		 12366 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12367 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12368 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12369
8d519ab2
MC		 12370 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12371 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12372 /* Turn off the debug UART. */
12373 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12374 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12375 /* Keep VMain power. */
12376 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12377 GRC_LCLCTRL_GPIO_OUTPUT0;
12378 }
12379
1da177e4 12380 /* Force the chip into D0. */
bc1c7567 12381 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12382 if (err) {
12383 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12384 pci_name(tp->pdev));
12385 return err;
12386 }
12387
1da177e4
LT		 12388 /* Derive initial jumbo mode from MTU assigned in
12389 * ether_setup() via the alloc_etherdev() call
12390 */
0f893dc6 12391 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12392 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12393 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12394
12395 /* Determine WakeOnLan speed to use. */
12396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12397 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12398 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12399 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12400 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12401 } else {
12402 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12403 }
12404
7f97a4bd
MC		 12405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12406 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12407
1da177e4
LT		 12408 /* A few boards don't want Ethernet@WireSpeed phy feature */
12409 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12410 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12411 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12412 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12413 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12414 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12415 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12416
12417 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12418 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12419 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12420 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12421 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12422
321d32a0 12423 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12424 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0
MC		 12425 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12426 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12427 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12430 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12431 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12432 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12433 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12434 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12435 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12436 } else
c424cb24
MC		 12437 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12438 }
1da177e4 12439
b2a5c19c
MC		 12440 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12441 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12442 tp->phy_otp = tg3_read_otp_phycfg(tp);
12443 if (tp->phy_otp == 0)
12444 tp->phy_otp = TG3_OTP_DEFAULT;
12445 }
12446
f51f3562 12447 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12448 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12449 else
12450 tp->mi_mode = MAC_MI_MODE_BASE;
12451
1da177e4 12452 tp->coalesce_mode = 0;
1da177e4
LT		 12453 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12454 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12455 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12456
321d32a0
MC		 12457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12458 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12459 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12460
255ca311
MC		 12461 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12462 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12463 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12464 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12465
158d7abd
MC		 12466 err = tg3_mdio_init(tp);
12467 if (err)
12468 return err;
1da177e4
LT		 12469
12470 /* Initialize data/descriptor byte/word swapping. */
12471 val = tr32(GRC_MODE);
12472 val &= GRC_MODE_HOST_STACKUP;
12473 tw32(GRC_MODE, val | tp->grc_mode);
12474
12475 tg3_switch_clocks(tp);
12476
12477 /* Clear this out for sanity. */
12478 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12479
12480 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12481 &pci_state_reg);
12482 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12483 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12484 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12485
12486 if (chiprevid == CHIPREV_ID_5701_A0 ||
12487 chiprevid == CHIPREV_ID_5701_B0 ||
12488 chiprevid == CHIPREV_ID_5701_B2 ||
12489 chiprevid == CHIPREV_ID_5701_B5) {
12490 void __iomem *sram_base;
12491
12492 /* Write some dummy words into the SRAM status block
12493 * area, see if it reads back correctly. If the return
12494 * value is bad, force enable the PCIX workaround.
12495 */
12496 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12497
12498 writel(0x00000000, sram_base);
12499 writel(0x00000000, sram_base + 4);
12500 writel(0xffffffff, sram_base + 4);
12501 if (readl(sram_base) != 0x00000000)
12502 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12503 }
12504 }
12505
12506 udelay(50);
12507 tg3_nvram_init(tp);
12508
12509 grc_misc_cfg = tr32(GRC_MISC_CFG);
12510 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12511
1da177e4
LT		 12512 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12513 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12514 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12515 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12516
fac9b83e
DM		 12517 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12518 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12519 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12520 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12521 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12522 HOSTCC_MODE_CLRTICK_TXBD);
12523
12524 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12525 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12526 tp->misc_host_ctrl);
12527 }
12528
3bda1258
MC		 12529 /* Preserve the APE MAC_MODE bits */
12530 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12531 tp->mac_mode = tr32(MAC_MODE) |
12532 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12533 else
12534 tp->mac_mode = TG3_DEF_MAC_MODE;
12535
1da177e4
LT		 12536 /* these are limited to 10/100 only */
12537 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12538 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12539 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12540 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12541 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12542 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12543 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12544 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12545 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12546 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12547 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12548 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 12549 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 12550 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12551
12552 err = tg3_phy_probe(tp);
12553 if (err) {
12554 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12555 pci_name(tp->pdev), err);
12556 /* ... but do not return immediately ... */
b02fd9e3 12557 tg3_mdio_fini(tp);
1da177e4
LT		 12558 }
12559
12560 tg3_read_partno(tp);
c4e6575c 12561 tg3_read_fw_ver(tp);
1da177e4
LT		 12562
12563 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12564 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12565 } else {
12566 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12567 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12568 else
12569 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12570 }
12571
12572 /* 5700 {AX,BX} chips have a broken status block link
12573 * change bit implementation, so we must use the
12574 * status register in those cases.
12575 */
12576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12577 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12578 else
12579 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12580
12581 /* The led_ctrl is set during tg3_phy_probe, here we might
12582 * have to force the link status polling mechanism based
12583 * upon subsystem IDs.
12584 */
12585 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12587 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12588 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12589 TG3_FLAG_USE_LINKCHG_REG);
12590 }
12591
12592 /* For all SERDES we poll the MAC status register. */
12593 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12594 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12595 else
12596 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12597
ad829268 12598 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12599 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12600 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12601 tp->rx_offset = 0;
12602
f92905de
MC		 12603 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12604
12605 /* Increment the rx prod index on the rx std ring by at most
12606 * 8 for these chips to workaround hw errata.
12607 */
12608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12609 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12611 tp->rx_std_max_post = 8;
12612
8ed5d97e
MC		 12613 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12614 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12615 PCIE_PWR_MGMT_L1_THRESH_MSK;
12616
1da177e4
LT		 12617 return err;
12618}
12619
49b6e95f 12620#ifdef CONFIG_SPARC
1da177e4
LT		 12621static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12622{
12623 struct net_device *dev = tp->dev;
12624 struct pci_dev *pdev = tp->pdev;
49b6e95f 12625 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12626 const unsigned char *addr;
49b6e95f
DM		 12627 int len;
12628
12629 addr = of_get_property(dp, "local-mac-address", &len);
12630 if (addr && len == 6) {
12631 memcpy(dev->dev_addr, addr, 6);
12632 memcpy(dev->perm_addr, dev->dev_addr, 6);
12633 return 0;
1da177e4
LT		 12634 }
12635 return -ENODEV;
12636}
12637
12638static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12639{
12640 struct net_device *dev = tp->dev;
12641
12642 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12643 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12644 return 0;
12645}
12646#endif
12647
12648static int __devinit tg3_get_device_address(struct tg3 *tp)
12649{
12650 struct net_device *dev = tp->dev;
12651 u32 hi, lo, mac_offset;
008652b3 12652 int addr_ok = 0;
1da177e4 12653
49b6e95f 12654#ifdef CONFIG_SPARC
1da177e4
LT		 12655 if (!tg3_get_macaddr_sparc(tp))
12656 return 0;
12657#endif
12658
12659 mac_offset = 0x7c;
f49639e6 12660 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12661 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12662 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12663 mac_offset = 0xcc;
12664 if (tg3_nvram_lock(tp))
12665 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12666 else
12667 tg3_nvram_unlock(tp);
12668 }
b5d3772c
MC		 12669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12670 mac_offset = 0x10;
1da177e4
LT		 12671
12672 /* First try to get it from MAC address mailbox. */
12673 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12674 if ((hi >> 16) == 0x484b) {
12675 dev->dev_addr[0] = (hi >> 8) & 0xff;
12676 dev->dev_addr[1] = (hi >> 0) & 0xff;
12677
12678 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12679 dev->dev_addr[2] = (lo >> 24) & 0xff;
12680 dev->dev_addr[3] = (lo >> 16) & 0xff;
12681 dev->dev_addr[4] = (lo >> 8) & 0xff;
12682 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12683
008652b3
MC		 12684 /* Some old bootcode may report a 0 MAC address in SRAM */
12685 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12686 }
12687 if (!addr_ok) {
12688 /* Next, try NVRAM. */
df259d8c
MC		 12689 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12690 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12691 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12692 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12693 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12694 }
12695 /* Finally just fetch it out of the MAC control regs. */
12696 else {
12697 hi = tr32(MAC_ADDR_0_HIGH);
12698 lo = tr32(MAC_ADDR_0_LOW);
12699
12700 dev->dev_addr[5] = lo & 0xff;
12701 dev->dev_addr[4] = (lo >> 8) & 0xff;
12702 dev->dev_addr[3] = (lo >> 16) & 0xff;
12703 dev->dev_addr[2] = (lo >> 24) & 0xff;
12704 dev->dev_addr[1] = hi & 0xff;
12705 dev->dev_addr[0] = (hi >> 8) & 0xff;
12706 }
1da177e4
LT		 12707 }
12708
12709 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12710#ifdef CONFIG_SPARC
1da177e4
LT		 12711 if (!tg3_get_default_macaddr_sparc(tp))
12712 return 0;
12713#endif
12714 return -EINVAL;
12715 }
2ff43697 12716 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12717 return 0;
12718}
12719
59e6b434
DM		 12720#define BOUNDARY_SINGLE_CACHELINE 1
12721#define BOUNDARY_MULTI_CACHELINE 2
12722
12723static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12724{
12725 int cacheline_size;
12726 u8 byte;
12727 int goal;
12728
12729 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12730 if (byte == 0)
12731 cacheline_size = 1024;
12732 else
12733 cacheline_size = (int) byte * 4;
12734
12735 /* On 5703 and later chips, the boundary bits have no
12736 * effect.
12737 */
12738 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12739 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12740 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12741 goto out;
12742
12743#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12744 goal = BOUNDARY_MULTI_CACHELINE;
12745#else
12746#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12747 goal = BOUNDARY_SINGLE_CACHELINE;
12748#else
12749 goal = 0;
12750#endif
12751#endif
12752
12753 if (!goal)
12754 goto out;
12755
12756 /* PCI controllers on most RISC systems tend to disconnect
12757 * when a device tries to burst across a cache-line boundary.
12758 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12759 *
12760 * Unfortunately, for PCI-E there are only limited
12761 * write-side controls for this, and thus for reads
12762 * we will still get the disconnects. We'll also waste
12763 * these PCI cycles for both read and write for chips
12764 * other than 5700 and 5701 which do not implement the
12765 * boundary bits.
12766 */
12767 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12768 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12769 switch (cacheline_size) {
12770 case 16:
12771 case 32:
12772 case 64:
12773 case 128:
12774 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12775 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12776 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12777 } else {
12778 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12779 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12780 }
12781 break;
12782
12783 case 256:
12784 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12785 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12786 break;
12787
12788 default:
12789 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12790 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12791 break;
855e1111 12792 }
59e6b434
DM		 12793 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12794 switch (cacheline_size) {
12795 case 16:
12796 case 32:
12797 case 64:
12798 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12799 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12800 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12801 break;
12802 }
12803 /* fallthrough */
12804 case 128:
12805 default:
12806 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12807 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12808 break;
855e1111 12809 }
59e6b434
DM		 12810 } else {
12811 switch (cacheline_size) {
12812 case 16:
12813 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12814 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12815 DMA_RWCTRL_WRITE_BNDRY_16);
12816 break;
12817 }
12818 /* fallthrough */
12819 case 32:
12820 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12821 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12822 DMA_RWCTRL_WRITE_BNDRY_32);
12823 break;
12824 }
12825 /* fallthrough */
12826 case 64:
12827 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12828 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12829 DMA_RWCTRL_WRITE_BNDRY_64);
12830 break;
12831 }
12832 /* fallthrough */
12833 case 128:
12834 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12835 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12836 DMA_RWCTRL_WRITE_BNDRY_128);
12837 break;
12838 }
12839 /* fallthrough */
12840 case 256:
12841 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12842 DMA_RWCTRL_WRITE_BNDRY_256);
12843 break;
12844 case 512:
12845 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12846 DMA_RWCTRL_WRITE_BNDRY_512);
12847 break;
12848 case 1024:
12849 default:
12850 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12851 DMA_RWCTRL_WRITE_BNDRY_1024);
12852 break;
855e1111 12853 }
59e6b434
DM		 12854 }
12855
12856out:
12857 return val;
12858}
12859
1da177e4
LT		 12860static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12861{
12862 struct tg3_internal_buffer_desc test_desc;
12863 u32 sram_dma_descs;
12864 int i, ret;
12865
12866 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12867
12868 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12869 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12870 tw32(RDMAC_STATUS, 0);
12871 tw32(WDMAC_STATUS, 0);
12872
12873 tw32(BUFMGR_MODE, 0);
12874 tw32(FTQ_RESET, 0);
12875
12876 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12877 test_desc.addr_lo = buf_dma & 0xffffffff;
12878 test_desc.nic_mbuf = 0x00002100;
12879 test_desc.len = size;
12880
12881 /*
12882 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12883 * the *second* time the tg3 driver was getting loaded after an
12884 * initial scan.
12885 *
12886 * Broadcom tells me:
12887 * ...the DMA engine is connected to the GRC block and a DMA
12888 * reset may affect the GRC block in some unpredictable way...
12889 * The behavior of resets to individual blocks has not been tested.
12890 *
12891 * Broadcom noted the GRC reset will also reset all sub-components.
12892 */
12893 if (to_device) {
12894 test_desc.cqid_sqid = (13 << 8) | 2;
12895
12896 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12897 udelay(40);
12898 } else {
12899 test_desc.cqid_sqid = (16 << 8) | 7;
12900
12901 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12902 udelay(40);
12903 }
12904 test_desc.flags = 0x00000005;
12905
12906 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12907 u32 val;
12908
12909 val = *(((u32 *)&test_desc) + i);
12910 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12911 sram_dma_descs + (i * sizeof(u32)));
12912 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12913 }
12914 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12915
12916 if (to_device) {
12917 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12918 } else {
12919 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12920 }
12921
12922 ret = -ENODEV;
12923 for (i = 0; i < 40; i++) {
12924 u32 val;
12925
12926 if (to_device)
12927 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12928 else
12929 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12930 if ((val & 0xffff) == sram_dma_descs) {
12931 ret = 0;
12932 break;
12933 }
12934
12935 udelay(100);
12936 }
12937
12938 return ret;
12939}
12940
ded7340d 12941#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12942
12943static int __devinit tg3_test_dma(struct tg3 *tp)
12944{
12945 dma_addr_t buf_dma;
59e6b434 12946 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12947 int ret;
12948
12949 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12950 if (!buf) {
12951 ret = -ENOMEM;
12952 goto out_nofree;
12953 }
12954
12955 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12956 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12957
59e6b434 12958 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12959
12960 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12961 /* DMA read watermark not used on PCIE */
12962 tp->dma_rwctrl |= 0x00180000;
12963 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 12964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 12966 tp->dma_rwctrl |= 0x003f0000;
12967 else
12968 tp->dma_rwctrl |= 0x003f000f;
12969 } else {
12970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12972 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 12973 u32 read_water = 0x7;
1da177e4 12974
4a29cc2e
MC		 12975 /* If the 5704 is behind the EPB bridge, we can
12976 * do the less restrictive ONE_DMA workaround for
12977 * better performance.
12978 */
12979 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12981 tp->dma_rwctrl |= 0x8000;
12982 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 12983 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12984
49afdeb6
MC		 12985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12986 read_water = 4;
59e6b434 12987 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 12988 tp->dma_rwctrl |=
12989 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12990 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12991 (1 << 23);
4cf78e4f
MC		 12992 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12993 /* 5780 always in PCIX mode */
12994 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 12995 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12996 /* 5714 always in PCIX mode */
12997 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 12998 } else {
12999 tp->dma_rwctrl |= 0x001b000f;
13000 }
13001 }
13002
13003 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13004 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13005 tp->dma_rwctrl &= 0xfffffff0;
13006
13007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13009 /* Remove this if it causes problems for some boards. */
13010 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13011
13012 /* On 5700/5701 chips, we need to set this bit.
13013 * Otherwise the chip will issue cacheline transactions
13014 * to streamable DMA memory with not all the byte
13015 * enables turned on. This is an error on several
13016 * RISC PCI controllers, in particular sparc64.
13017 *
13018 * On 5703/5704 chips, this bit has been reassigned
13019 * a different meaning. In particular, it is used
13020 * on those chips to enable a PCI-X workaround.
13021 */
13022 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13023 }
13024
13025 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13026
13027#if 0
13028 /* Unneeded, already done by tg3_get_invariants. */
13029 tg3_switch_clocks(tp);
13030#endif
13031
13032 ret = 0;
13033 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13034 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13035 goto out;
13036
59e6b434
DM		 13037 /* It is best to perform DMA test with maximum write burst size
13038 * to expose the 5700/5701 write DMA bug.
13039 */
13040 saved_dma_rwctrl = tp->dma_rwctrl;
13041 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13042 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13043
1da177e4
LT		 13044 while (1) {
13045 u32 *p = buf, i;
13046
13047 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13048 p[i] = i;
13049
13050 /* Send the buffer to the chip. */
13051 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13052 if (ret) {
13053 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13054 break;
13055 }
13056
13057#if 0
13058 /* validate data reached card RAM correctly. */
13059 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13060 u32 val;
13061 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13062 if (le32_to_cpu(val) != p[i]) {
13063 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13064 /* ret = -ENODEV here? */
13065 }
13066 p[i] = 0;
13067 }
13068#endif
13069 /* Now read it back. */
13070 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13071 if (ret) {
13072 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13073
13074 break;
13075 }
13076
13077 /* Verify it. */
13078 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13079 if (p[i] == i)
13080 continue;
13081
59e6b434
DM		 13082 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13083 DMA_RWCTRL_WRITE_BNDRY_16) {
13084 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13085 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13086 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13087 break;
13088 } else {
13089 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13090 ret = -ENODEV;
13091 goto out;
13092 }
13093 }
13094
13095 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13096 /* Success. */
13097 ret = 0;
13098 break;
13099 }
13100 }
59e6b434
DM		 13101 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13102 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13103 static struct pci_device_id dma_wait_state_chipsets[] = {
13104 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13105 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13106 { },
13107 };
13108
59e6b434 13109 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13110 * now look for chipsets that are known to expose the
13111 * DMA bug without failing the test.
59e6b434 13112 */
6d1cfbab
MC		 13113 if (pci_dev_present(dma_wait_state_chipsets)) {
13114 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13115 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13116 }
13117 else
13118 /* Safe to use the calculated DMA boundary. */
13119 tp->dma_rwctrl = saved_dma_rwctrl;
13120
59e6b434
DM		 13121 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13122 }
1da177e4
LT		 13123
13124out:
13125 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13126out_nofree:
13127 return ret;
13128}
13129
13130static void __devinit tg3_init_link_config(struct tg3 *tp)
13131{
13132 tp->link_config.advertising =
13133 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13134 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13135 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13136 ADVERTISED_Autoneg | ADVERTISED_MII);
13137 tp->link_config.speed = SPEED_INVALID;
13138 tp->link_config.duplex = DUPLEX_INVALID;
13139 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13140 tp->link_config.active_speed = SPEED_INVALID;
13141 tp->link_config.active_duplex = DUPLEX_INVALID;
13142 tp->link_config.phy_is_low_power = 0;
13143 tp->link_config.orig_speed = SPEED_INVALID;
13144 tp->link_config.orig_duplex = DUPLEX_INVALID;
13145 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13146}
13147
13148static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13149{
fdfec172
MC		 13150 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13151 tp->bufmgr_config.mbuf_read_dma_low_water =
13152 DEFAULT_MB_RDMA_LOW_WATER_5705;
13153 tp->bufmgr_config.mbuf_mac_rx_low_water =
13154 DEFAULT_MB_MACRX_LOW_WATER_5705;
13155 tp->bufmgr_config.mbuf_high_water =
13156 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13158 tp->bufmgr_config.mbuf_mac_rx_low_water =
13159 DEFAULT_MB_MACRX_LOW_WATER_5906;
13160 tp->bufmgr_config.mbuf_high_water =
13161 DEFAULT_MB_HIGH_WATER_5906;
13162 }
fdfec172
MC		 13163
13164 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13165 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13166 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13167 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13168 tp->bufmgr_config.mbuf_high_water_jumbo =
13169 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13170 } else {
13171 tp->bufmgr_config.mbuf_read_dma_low_water =
13172 DEFAULT_MB_RDMA_LOW_WATER;
13173 tp->bufmgr_config.mbuf_mac_rx_low_water =
13174 DEFAULT_MB_MACRX_LOW_WATER;
13175 tp->bufmgr_config.mbuf_high_water =
13176 DEFAULT_MB_HIGH_WATER;
13177
13178 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13179 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13180 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13181 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13182 tp->bufmgr_config.mbuf_high_water_jumbo =
13183 DEFAULT_MB_HIGH_WATER_JUMBO;
13184 }
1da177e4
LT		 13185
13186 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13187 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13188}
13189
13190static char * __devinit tg3_phy_string(struct tg3 *tp)
13191{
13192 switch (tp->phy_id & PHY_ID_MASK) {
13193 case PHY_ID_BCM5400: return "5400";
13194 case PHY_ID_BCM5401: return "5401";
13195 case PHY_ID_BCM5411: return "5411";
13196 case PHY_ID_BCM5701: return "5701";
13197 case PHY_ID_BCM5703: return "5703";
13198 case PHY_ID_BCM5704: return "5704";
13199 case PHY_ID_BCM5705: return "5705";
13200 case PHY_ID_BCM5750: return "5750";
85e94ced 13201 case PHY_ID_BCM5752: return "5752";
a4e2b347 13202 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13203 case PHY_ID_BCM5780: return "5780";
af36e6b6 13204 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13205 case PHY_ID_BCM5787: return "5787";
d30cdd28 13206 case PHY_ID_BCM5784: return "5784";
126a3368 13207 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13208 case PHY_ID_BCM5906: return "5906";
9936bcf6 13209 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13210 case PHY_ID_BCM8002: return "8002/serdes";
13211 case 0: return "serdes";
13212 default: return "unknown";
855e1111 13213 }
1da177e4
LT		 13214}
13215
f9804ddb
MC		 13216static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13217{
13218 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13219 strcpy(str, "PCI Express");
13220 return str;
13221 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13222 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13223
13224 strcpy(str, "PCIX:");
13225
13226 if ((clock_ctrl == 7) ||
13227 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13228 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13229 strcat(str, "133MHz");
13230 else if (clock_ctrl == 0)
13231 strcat(str, "33MHz");
13232 else if (clock_ctrl == 2)
13233 strcat(str, "50MHz");
13234 else if (clock_ctrl == 4)
13235 strcat(str, "66MHz");
13236 else if (clock_ctrl == 6)
13237 strcat(str, "100MHz");
f9804ddb
MC		 13238 } else {
13239 strcpy(str, "PCI:");
13240 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13241 strcat(str, "66MHz");
13242 else
13243 strcat(str, "33MHz");
13244 }
13245 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13246 strcat(str, ":32-bit");
13247 else
13248 strcat(str, ":64-bit");
13249 return str;
13250}
13251
8c2dc7e1 13252static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13253{
13254 struct pci_dev *peer;
13255 unsigned int func, devnr = tp->pdev->devfn & ~7;
13256
13257 for (func = 0; func < 8; func++) {
13258 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13259 if (peer && peer != tp->pdev)
13260 break;
13261 pci_dev_put(peer);
13262 }
16fe9d74
MC		 13263 /* 5704 can be configured in single-port mode, set peer to
13264 * tp->pdev in that case.
13265 */
13266 if (!peer) {
13267 peer = tp->pdev;
13268 return peer;
13269 }
1da177e4
LT		 13270
13271 /*
13272 * We don't need to keep the refcount elevated; there's no way
13273 * to remove one half of this device without removing the other
13274 */
13275 pci_dev_put(peer);
13276
13277 return peer;
13278}
13279
15f9850d
DM		 13280static void __devinit tg3_init_coal(struct tg3 *tp)
13281{
13282 struct ethtool_coalesce *ec = &tp->coal;
13283
13284 memset(ec, 0, sizeof(*ec));
13285 ec->cmd = ETHTOOL_GCOALESCE;
13286 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13287 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13288 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13289 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13290 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13291 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13292 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13293 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13294 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13295
13296 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13297 HOSTCC_MODE_CLRTICK_TXBD)) {
13298 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13299 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13300 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13301 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13302 }
d244c892
MC		 13303
13304 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13305 ec->rx_coalesce_usecs_irq = 0;
13306 ec->tx_coalesce_usecs_irq = 0;
13307 ec->stats_block_coalesce_usecs = 0;
13308 }
15f9850d
DM		 13309}
13310
7c7d64b8
SH		 13311static const struct net_device_ops tg3_netdev_ops = {
13312 .ndo_open = tg3_open,
13313 .ndo_stop = tg3_close,
00829823
SH		 13314 .ndo_start_xmit = tg3_start_xmit,
13315 .ndo_get_stats = tg3_get_stats,
13316 .ndo_validate_addr = eth_validate_addr,
13317 .ndo_set_multicast_list = tg3_set_rx_mode,
13318 .ndo_set_mac_address = tg3_set_mac_addr,
13319 .ndo_do_ioctl = tg3_ioctl,
13320 .ndo_tx_timeout = tg3_tx_timeout,
13321 .ndo_change_mtu = tg3_change_mtu,
13322#if TG3_VLAN_TAG_USED
13323 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13324#endif
13325#ifdef CONFIG_NET_POLL_CONTROLLER
13326 .ndo_poll_controller = tg3_poll_controller,
13327#endif
13328};
13329
13330static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13331 .ndo_open = tg3_open,
13332 .ndo_stop = tg3_close,
13333 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13334 .ndo_get_stats = tg3_get_stats,
13335 .ndo_validate_addr = eth_validate_addr,
13336 .ndo_set_multicast_list = tg3_set_rx_mode,
13337 .ndo_set_mac_address = tg3_set_mac_addr,
13338 .ndo_do_ioctl = tg3_ioctl,
13339 .ndo_tx_timeout = tg3_tx_timeout,
13340 .ndo_change_mtu = tg3_change_mtu,
13341#if TG3_VLAN_TAG_USED
13342 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13343#endif
13344#ifdef CONFIG_NET_POLL_CONTROLLER
13345 .ndo_poll_controller = tg3_poll_controller,
13346#endif
13347};
13348
1da177e4
LT		 13349static int __devinit tg3_init_one(struct pci_dev *pdev,
13350 const struct pci_device_id *ent)
13351{
13352 static int tg3_version_printed = 0;
1da177e4
LT		 13353 struct net_device *dev;
13354 struct tg3 *tp;
d6645372 13355 int err, pm_cap;
f9804ddb 13356 char str[40];
72f2afb8 13357 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13358
13359 if (tg3_version_printed++ == 0)
13360 printk(KERN_INFO "%s", version);
13361
13362 err = pci_enable_device(pdev);
13363 if (err) {
13364 printk(KERN_ERR PFX "Cannot enable PCI device, "
13365 "aborting.\n");
13366 return err;
13367 }
13368
1da177e4
LT		 13369 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13370 if (err) {
13371 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13372 "aborting.\n");
13373 goto err_out_disable_pdev;
13374 }
13375
13376 pci_set_master(pdev);
13377
13378 /* Find power-management capability. */
13379 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13380 if (pm_cap == 0) {
13381 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13382 "aborting.\n");
13383 err = -EIO;
13384 goto err_out_free_res;
13385 }
13386
1da177e4
LT		 13387 dev = alloc_etherdev(sizeof(*tp));
13388 if (!dev) {
13389 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13390 err = -ENOMEM;
13391 goto err_out_free_res;
13392 }
13393
1da177e4
LT		 13394 SET_NETDEV_DEV(dev, &pdev->dev);
13395
1da177e4
LT		 13396#if TG3_VLAN_TAG_USED
13397 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13398#endif
13399
13400 tp = netdev_priv(dev);
13401 tp->pdev = pdev;
13402 tp->dev = dev;
13403 tp->pm_cap = pm_cap;
1da177e4
LT		 13404 tp->rx_mode = TG3_DEF_RX_MODE;
13405 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13406
1da177e4
LT		 13407 if (tg3_debug > 0)
13408 tp->msg_enable = tg3_debug;
13409 else
13410 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13411
13412 /* The word/byte swap controls here control register access byte
13413 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13414 * setting below.
13415 */
13416 tp->misc_host_ctrl =
13417 MISC_HOST_CTRL_MASK_PCI_INT |
13418 MISC_HOST_CTRL_WORD_SWAP |
13419 MISC_HOST_CTRL_INDIR_ACCESS |
13420 MISC_HOST_CTRL_PCISTATE_RW;
13421
13422 /* The NONFRM (non-frame) byte/word swap controls take effect
13423 * on descriptor entries, anything which isn't packet data.
13424 *
13425 * The StrongARM chips on the board (one for tx, one for rx)
13426 * are running in big-endian mode.
13427 */
13428 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13429 GRC_MODE_WSWAP_NONFRM_DATA);
13430#ifdef __BIG_ENDIAN
13431 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13432#endif
13433 spin_lock_init(&tp->lock);
1da177e4 13434 spin_lock_init(&tp->indirect_lock);
c4028958 13435 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13436
d5fe488a 13437 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13438 if (!tp->regs) {
1da177e4
LT		 13439 printk(KERN_ERR PFX "Cannot map device registers, "
13440 "aborting.\n");
13441 err = -ENOMEM;
13442 goto err_out_free_dev;
13443 }
13444
13445 tg3_init_link_config(tp);
13446
1da177e4
LT		 13447 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13448 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 13449
8ef0442f 13450 tp->napi[0].tp = tp;
898a56f8 13451 tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
72334482 13452 tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
f3f3f27e 13453 tp->napi[0].prodmbox = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
fd2ce37f 13454 tp->napi[0].coal_now = HOSTCC_MODE_NOW;
f3f3f27e 13455 tp->napi[0].tx_pending = TG3_DEF_TX_RING_PENDING;
8ef0442f 13456 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 13457 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13458 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13459 dev->irq = pdev->irq;
1da177e4
LT		 13460
13461 err = tg3_get_invariants(tp);
13462 if (err) {
13463 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13464 "aborting.\n");
13465 goto err_out_iounmap;
13466 }
13467
321d32a0 13468 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13469 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13470 dev->netdev_ops = &tg3_netdev_ops;
13471 else
13472 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13473
13474
4a29cc2e
MC		 13475 /* The EPB bridge inside 5714, 5715, and 5780 and any
13476 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13477 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13478 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13479 * do DMA address check in tg3_start_xmit().
13480 */
4a29cc2e 13481 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13482 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13483 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13484 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13485#ifdef CONFIG_HIGHMEM
6a35528a 13486 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13487#endif
4a29cc2e 13488 } else
6a35528a 13489 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13490
13491 /* Configure DMA attributes. */
284901a9 13492 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13493 err = pci_set_dma_mask(pdev, dma_mask);
13494 if (!err) {
13495 dev->features |= NETIF_F_HIGHDMA;
13496 err = pci_set_consistent_dma_mask(pdev,
13497 persist_dma_mask);
13498 if (err < 0) {
13499 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13500 "DMA for consistent allocations\n");
13501 goto err_out_iounmap;
13502 }
13503 }
13504 }
284901a9
YH		 13505 if (err || dma_mask == DMA_BIT_MASK(32)) {
13506 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13507 if (err) {
13508 printk(KERN_ERR PFX "No usable DMA configuration, "
13509 "aborting.\n");
13510 goto err_out_iounmap;
13511 }
13512 }
13513
fdfec172 13514 tg3_init_bufmgr_config(tp);
1da177e4 13515
077f849d 13516 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13517 tp->fw_needed = FIRMWARE_TG3;
077f849d 13518
1da177e4
LT		 13519 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13520 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13521 }
13522 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13523 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13524 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13525 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13526 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13527 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13528 } else {
7f62ad5d 13529 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13531 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13532 else
9e9fd12d 13533 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13534 }
1da177e4 13535
4e3a7aaa
MC		 13536 /* TSO is on by default on chips that support hardware TSO.
13537 * Firmware TSO on older chips gives lower performance, so it
13538 * is off by default, but can be enabled using ethtool.
13539 */
b0026624 13540 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13541 if (dev->features & NETIF_F_IP_CSUM)
13542 dev->features |= NETIF_F_TSO;
13543 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13544 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13545 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13546 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13547 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13548 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13550 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13551 dev->features |= NETIF_F_TSO_ECN;
b0026624 13552 }
1da177e4 13553
1da177e4
LT		 13554
13555 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13556 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13557 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13558 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13559 tp->rx_pending = 63;
13560 }
13561
1da177e4
LT		 13562 err = tg3_get_device_address(tp);
13563 if (err) {
13564 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13565 "aborting.\n");
077f849d 13566 goto err_out_fw;
1da177e4
LT		 13567 }
13568
c88864df 13569 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13570 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13571 if (!tp->aperegs) {
c88864df
MC		 13572 printk(KERN_ERR PFX "Cannot map APE registers, "
13573 "aborting.\n");
13574 err = -ENOMEM;
077f849d 13575 goto err_out_fw;
c88864df
MC		 13576 }
13577
13578 tg3_ape_lock_init(tp);
7fd76445
MC		 13579
13580 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13581 tg3_read_dash_ver(tp);
c88864df
MC		 13582 }
13583
1da177e4
LT		 13584 /*
13585 * Reset chip in case UNDI or EFI driver did not shutdown
13586 * DMA self test will enable WDMAC and we'll see (spurious)
13587 * pending DMA on the PCI bus at that point.
13588 */
13589 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13590 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13591 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13592 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13593 }
13594
13595 err = tg3_test_dma(tp);
13596 if (err) {
13597 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13598 goto err_out_apeunmap;
1da177e4
LT		 13599 }
13600
1da177e4
LT		 13601 /* flow control autonegotiation is default behavior */
13602 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13603 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13604
15f9850d
DM		 13605 tg3_init_coal(tp);
13606
c49a1561
MC		 13607 pci_set_drvdata(pdev, dev);
13608
1da177e4
LT		 13609 err = register_netdev(dev);
13610 if (err) {
13611 printk(KERN_ERR PFX "Cannot register net device, "
13612 "aborting.\n");
0d3031d9 13613 goto err_out_apeunmap;
1da177e4
LT		 13614 }
13615
df59c940 13616 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13617 dev->name,
13618 tp->board_part_number,
13619 tp->pci_chip_rev_id,
f9804ddb 13620 tg3_bus_string(tp, str),
e174961c 13621 dev->dev_addr);
1da177e4 13622
df59c940
MC		 13623 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13624 printk(KERN_INFO
13625 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13626 tp->dev->name,
13627 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13628 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13629 else
13630 printk(KERN_INFO
13631 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13632 tp->dev->name, tg3_phy_string(tp),
13633 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13634 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13635 "10/100/1000Base-T")),
13636 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13637
13638 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13639 dev->name,
13640 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13641 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13642 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13643 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13644 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13645 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13646 dev->name, tp->dma_rwctrl,
284901a9 13647 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13648 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13649
13650 return 0;
13651
0d3031d9
MC		 13652err_out_apeunmap:
13653 if (tp->aperegs) {
13654 iounmap(tp->aperegs);
13655 tp->aperegs = NULL;
13656 }
13657
077f849d
JSR		 13658err_out_fw:
13659 if (tp->fw)
13660 release_firmware(tp->fw);
13661
1da177e4 13662err_out_iounmap:
6892914f
MC		 13663 if (tp->regs) {
13664 iounmap(tp->regs);
22abe310 13665 tp->regs = NULL;
6892914f 13666 }
1da177e4
LT		 13667
13668err_out_free_dev:
13669 free_netdev(dev);
13670
13671err_out_free_res:
13672 pci_release_regions(pdev);
13673
13674err_out_disable_pdev:
13675 pci_disable_device(pdev);
13676 pci_set_drvdata(pdev, NULL);
13677 return err;
13678}
13679
13680static void __devexit tg3_remove_one(struct pci_dev *pdev)
13681{
13682 struct net_device *dev = pci_get_drvdata(pdev);
13683
13684 if (dev) {
13685 struct tg3 *tp = netdev_priv(dev);
13686
077f849d
JSR		 13687 if (tp->fw)
13688 release_firmware(tp->fw);
13689
7faa006f 13690 flush_scheduled_work();
158d7abd 13691
b02fd9e3
MC		 13692 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13693 tg3_phy_fini(tp);
158d7abd 13694 tg3_mdio_fini(tp);
b02fd9e3 13695 }
158d7abd 13696
1da177e4 13697 unregister_netdev(dev);
0d3031d9
MC		 13698 if (tp->aperegs) {
13699 iounmap(tp->aperegs);
13700 tp->aperegs = NULL;
13701 }
6892914f
MC		 13702 if (tp->regs) {
13703 iounmap(tp->regs);
22abe310 13704 tp->regs = NULL;
6892914f 13705 }
1da177e4
LT		 13706 free_netdev(dev);
13707 pci_release_regions(pdev);
13708 pci_disable_device(pdev);
13709 pci_set_drvdata(pdev, NULL);
13710 }
13711}
13712
13713static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13714{
13715 struct net_device *dev = pci_get_drvdata(pdev);
13716 struct tg3 *tp = netdev_priv(dev);
12dac075 13717 pci_power_t target_state;
1da177e4
LT		 13718 int err;
13719
3e0c95fd
MC		 13720 /* PCI register 4 needs to be saved whether netif_running() or not.
13721 * MSI address and data need to be saved if using MSI and
13722 * netif_running().
13723 */
13724 pci_save_state(pdev);
13725
1da177e4
LT		 13726 if (!netif_running(dev))
13727 return 0;
13728
7faa006f 13729 flush_scheduled_work();
b02fd9e3 13730 tg3_phy_stop(tp);
1da177e4
LT		 13731 tg3_netif_stop(tp);
13732
13733 del_timer_sync(&tp->timer);
13734
f47c11ee 13735 tg3_full_lock(tp, 1);
1da177e4 13736 tg3_disable_ints(tp);
f47c11ee 13737 tg3_full_unlock(tp);
1da177e4
LT		 13738
13739 netif_device_detach(dev);
13740
f47c11ee 13741 tg3_full_lock(tp, 0);
944d980e 13742 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13743 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13744 tg3_full_unlock(tp);
1da177e4 13745
12dac075
RW		 13746 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13747
13748 err = tg3_set_power_state(tp, target_state);
1da177e4 13749 if (err) {
b02fd9e3
MC		 13750 int err2;
13751
f47c11ee 13752 tg3_full_lock(tp, 0);
1da177e4 13753
6a9eba15 13754 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13755 err2 = tg3_restart_hw(tp, 1);
13756 if (err2)
b9ec6c1b 13757 goto out;
1da177e4
LT		 13758
13759 tp->timer.expires = jiffies + tp->timer_offset;
13760 add_timer(&tp->timer);
13761
13762 netif_device_attach(dev);
13763 tg3_netif_start(tp);
13764
b9ec6c1b 13765out:
f47c11ee 13766 tg3_full_unlock(tp);
b02fd9e3
MC		 13767
13768 if (!err2)
13769 tg3_phy_start(tp);
1da177e4
LT		 13770 }
13771
13772 return err;
13773}
13774
13775static int tg3_resume(struct pci_dev *pdev)
13776{
13777 struct net_device *dev = pci_get_drvdata(pdev);
13778 struct tg3 *tp = netdev_priv(dev);
13779 int err;
13780
3e0c95fd
MC		 13781 pci_restore_state(tp->pdev);
13782
1da177e4
LT		 13783 if (!netif_running(dev))
13784 return 0;
13785
bc1c7567 13786 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13787 if (err)
13788 return err;
13789
13790 netif_device_attach(dev);
13791
f47c11ee 13792 tg3_full_lock(tp, 0);
1da177e4 13793
6a9eba15 13794 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13795 err = tg3_restart_hw(tp, 1);
13796 if (err)
13797 goto out;
1da177e4
LT		 13798
13799 tp->timer.expires = jiffies + tp->timer_offset;
13800 add_timer(&tp->timer);
13801
1da177e4
LT		 13802 tg3_netif_start(tp);
13803
b9ec6c1b 13804out:
f47c11ee 13805 tg3_full_unlock(tp);
1da177e4 13806
b02fd9e3
MC		 13807 if (!err)
13808 tg3_phy_start(tp);
13809
b9ec6c1b 13810 return err;
1da177e4
LT		 13811}
13812
13813static struct pci_driver tg3_driver = {
13814 .name = DRV_MODULE_NAME,
13815 .id_table = tg3_pci_tbl,
13816 .probe = tg3_init_one,
13817 .remove = __devexit_p(tg3_remove_one),
13818 .suspend = tg3_suspend,
13819 .resume = tg3_resume
13820};
13821
13822static int __init tg3_init(void)
13823{
29917620 13824 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13825}
13826
13827static void __exit tg3_cleanup(void)
13828{
13829 pci_unregister_driver(&tg3_driver);
13830}
13831
13832module_init(tg3_init);
13833module_exit(tg3_cleanup);
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