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tg3: Add support code around kernel interrupt API
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
fc57e515
MC		 71#define DRV_MODULE_VERSION "3.101"
72#define DRV_MODULE_RELDATE "August 28, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
79ed5ac7
MC		 120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
1da177e4 122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 123 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
287be12e
MC		 128#define TG3_DMA_BYTE_ENAB 64
129
130#define TG3_RX_STD_DMA_SZ 1536
131#define TG3_RX_JMB_DMA_SZ 9046
132
133#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
134
135#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 137
138/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 139#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 140
ad829268
MC		 141#define TG3_RAW_IP_ALIGN 2
142
1da177e4
LT		 143/* number of ETHTOOL_GSTATS u64's */
144#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
145
4cafd3f5
MC		 146#define TG3_NUM_TEST 6
147
077f849d
JSR		 148#define FIRMWARE_TG3 "tigon/tg3.bin"
149#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
151
1da177e4
LT		 152static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
154
155MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157MODULE_LICENSE("GPL");
158MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 159MODULE_FIRMWARE(FIRMWARE_TG3);
160MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
162
1da177e4
LT		 163
164static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165module_param(tg3_debug, int, 0);
166MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
167
168static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
242 {}
1da177e4
LT		 243};
244
245MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
50da859d 247static const struct {
1da177e4
LT		 248 const char string[ETH_GSTRING_LEN];
249} ethtool_stats_keys[TG3_NUM_STATS] = {
250 { "rx_octets" },
251 { "rx_fragments" },
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
255 { "rx_fcs_errors" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
262 { "rx_jabbers" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
276
277 { "tx_octets" },
278 { "tx_collisions" },
279
280 { "tx_xon_sent" },
281 { "tx_xoff_sent" },
282 { "tx_flow_control" },
283 { "tx_mac_errors" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
286 { "tx_deferred" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
307 { "tx_discards" },
308 { "tx_errors" },
309
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
312 { "rxbds_empty" },
313 { "rx_discards" },
314 { "rx_errors" },
315 { "rx_threshold_hit" },
316
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
320
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
323 { "nic_irqs" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
326};
327
50da859d 328static const struct {
4cafd3f5
MC		 329 const char string[ETH_GSTRING_LEN];
330} ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
337};
338
b401e9e2
MC		 339static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
340{
341 writel(val, tp->regs + off);
342}
343
344static u32 tg3_read32(struct tg3 *tp, u32 off)
345{
6aa20a22 346 return (readl(tp->regs + off));
b401e9e2
MC		 347}
348
0d3031d9
MC		 349static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
350{
351 writel(val, tp->aperegs + off);
352}
353
354static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
355{
356 return (readl(tp->aperegs + off));
357}
358
1da177e4
LT		 359static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
360{
6892914f
MC		 361 unsigned long flags;
362
363 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 364 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
365 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 366 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 367}
368
369static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
370{
371 writel(val, tp->regs + off);
372 readl(tp->regs + off);
1da177e4
LT		 373}
374
6892914f 375static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 376{
6892914f
MC		 377 unsigned long flags;
378 u32 val;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
384 return val;
385}
386
387static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
388{
389 unsigned long flags;
390
391 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
393 TG3_64BIT_REG_LOW, val);
394 return;
395 }
396 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
398 TG3_64BIT_REG_LOW, val);
399 return;
1da177e4 400 }
6892914f
MC		 401
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
409 */
410 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
411 (val == 0x1)) {
412 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
413 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
414 }
415}
416
417static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
418{
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427}
428
b401e9e2
MC		 429/* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
433 */
434static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 435{
b401e9e2
MC		 436 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
437 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
438 /* Non-posted methods */
439 tp->write32(tp, off, val);
440 else {
441 /* Posted method */
442 tg3_write32(tp, off, val);
443 if (usec_wait)
444 udelay(usec_wait);
445 tp->read32(tp, off);
446 }
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
449 */
450 if (usec_wait)
451 udelay(usec_wait);
1da177e4
LT		 452}
453
09ee929c
MC		 454static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
455{
456 tp->write32_mbox(tp, off, val);
6892914f
MC		 457 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
458 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
459 tp->read32_mbox(tp, off);
09ee929c
MC		 460}
461
20094930 462static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 463{
464 void __iomem *mbox = tp->regs + off;
465 writel(val, mbox);
466 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
467 writel(val, mbox);
468 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
469 readl(mbox);
470}
471
b5d3772c
MC		 472static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
473{
474 return (readl(tp->regs + off + GRCMBOX_BASE));
475}
476
477static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
478{
479 writel(val, tp->regs + off + GRCMBOX_BASE);
480}
481
20094930 482#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 483#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 484#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 486#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 487
488#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 489#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 491#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 492
493static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
494{
6892914f
MC		 495 unsigned long flags;
496
b5d3772c
MC		 497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
498 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
499 return;
500
6892914f 501 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 505
bbadf503
MC		 506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
508 } else {
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 511
bbadf503
MC		 512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
514 }
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 516}
517
1da177e4
LT		 518static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
519{
6892914f
MC		 520 unsigned long flags;
521
b5d3772c
MC		 522 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
523 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
524 *val = 0;
525 return;
526 }
527
6892914f 528 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 529 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
530 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
531 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 532
bbadf503
MC		 533 /* Always leave this as zero. */
534 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
535 } else {
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
537 *val = tr32(TG3PCI_MEM_WIN_DATA);
538
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
541 }
6892914f 542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 543}
544
0d3031d9
MC		 545static void tg3_ape_lock_init(struct tg3 *tp)
546{
547 int i;
548
549 /* Make sure the driver hasn't any stale locks. */
550 for (i = 0; i < 8; i++)
551 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
552 APE_LOCK_GRANT_DRIVER);
553}
554
555static int tg3_ape_lock(struct tg3 *tp, int locknum)
556{
557 int i, off;
558 int ret = 0;
559 u32 status;
560
561 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
562 return 0;
563
564 switch (locknum) {
77b483f1 565 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 566 case TG3_APE_LOCK_MEM:
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 off = 4 * locknum;
573
574 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
575
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i = 0; i < 100; i++) {
578 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
579 if (status == APE_LOCK_GRANT_DRIVER)
580 break;
581 udelay(10);
582 }
583
584 if (status != APE_LOCK_GRANT_DRIVER) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
587 APE_LOCK_GRANT_DRIVER);
588
589 ret = -EBUSY;
590 }
591
592 return ret;
593}
594
595static void tg3_ape_unlock(struct tg3 *tp, int locknum)
596{
597 int off;
598
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
600 return;
601
602 switch (locknum) {
77b483f1 603 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 604 case TG3_APE_LOCK_MEM:
605 break;
606 default:
607 return;
608 }
609
610 off = 4 * locknum;
611 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
612}
613
1da177e4
LT		 614static void tg3_disable_ints(struct tg3 *tp)
615{
616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
898a56f8 618 tw32_mailbox_f(tp->napi[0].int_mbox, 0x00000001);
1da177e4
LT		 619}
620
1da177e4
LT		 621static void tg3_enable_ints(struct tg3 *tp)
622{
f19af9c2 623 u32 coal_now;
898a56f8 624 struct tg3_napi *tnapi = &tp->napi[0];
bbe832c0
MC		 625 tp->irq_sync = 0;
626 wmb();
627
1da177e4
LT		 628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
898a56f8 630 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
fcfa0a32 631 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
898a56f8 632 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 633
fd2ce37f 634 coal_now = tnapi->coal_now;
f19af9c2
MC		 635
636 /* Force an initial interrupt */
637 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
638 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
639 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
640 else
641 tw32(HOSTCC_MODE, tp->coalesce_mode |
642 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 643}
644
17375d25 645static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 646{
17375d25 647 struct tg3 *tp = tnapi->tp;
898a56f8 648 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 649 unsigned int work_exists = 0;
650
651 /* check for phy events */
652 if (!(tp->tg3_flags &
653 (TG3_FLAG_USE_LINKCHG_REG |
654 TG3_FLAG_POLL_SERDES))) {
655 if (sblk->status & SD_STATUS_LINK_CHG)
656 work_exists = 1;
657 }
658 /* check for RX/TX work to do */
f3f3f27e 659 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
72334482 660 sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
04237ddd
MC		 661 work_exists = 1;
662
663 return work_exists;
664}
665
17375d25 666/* tg3_int_reenable
04237ddd
MC		 667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
6aa20a22 669 * which reenables interrupts
1da177e4 670 */
17375d25 671static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 672{
17375d25
MC		 673 struct tg3 *tp = tnapi->tp;
674
898a56f8 675 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 676 mmiowb();
677
fac9b83e
DM		 678 /* When doing tagged status, this work check is unnecessary.
679 * The last_tag we write above tells the chip which piece of
680 * work we've completed.
681 */
682 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 683 tg3_has_work(tnapi))
04237ddd 684 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 685 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 686}
687
688static inline void tg3_netif_stop(struct tg3 *tp)
689{
bbe832c0 690 tp->dev->trans_start = jiffies; /* prevent tx timeout */
8ef0442f 691 napi_disable(&tp->napi[0].napi);
1da177e4
LT		 692 netif_tx_disable(tp->dev);
693}
694
695static inline void tg3_netif_start(struct tg3 *tp)
696{
898a56f8 697 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 698 netif_wake_queue(tp->dev);
699 /* NOTE: unconditional netif_wake_queue is only appropriate
700 * so long as all callers are assured to have free tx slots
701 * (such as after tg3_init_hw)
702 */
898a56f8
MC		 703 napi_enable(&tnapi->napi);
704 tnapi->hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 705 tg3_enable_ints(tp);
1da177e4
LT		 706}
707
708static void tg3_switch_clocks(struct tg3 *tp)
709{
710 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
711 u32 orig_clock_ctrl;
712
795d01c5
MC		 713 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
714 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 715 return;
716
1da177e4
LT		 717 orig_clock_ctrl = clock_ctrl;
718 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
719 CLOCK_CTRL_CLKRUN_OENABLE |
720 0x1f);
721 tp->pci_clock_ctrl = clock_ctrl;
722
723 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
724 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 725 tw32_wait_f(TG3PCI_CLOCK_CTRL,
726 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 727 }
728 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 729 tw32_wait_f(TG3PCI_CLOCK_CTRL,
730 clock_ctrl |
731 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
732 40);
733 tw32_wait_f(TG3PCI_CLOCK_CTRL,
734 clock_ctrl | (CLOCK_CTRL_ALTCLK),
735 40);
1da177e4 736 }
b401e9e2 737 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 738}
739
740#define PHY_BUSY_LOOPS 5000
741
742static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
743{
744 u32 frame_val;
745 unsigned int loops;
746 int ret;
747
748 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
749 tw32_f(MAC_MI_MODE,
750 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
751 udelay(80);
752 }
753
754 *val = 0x0;
755
756 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
757 MI_COM_PHY_ADDR_MASK);
758 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
759 MI_COM_REG_ADDR_MASK);
760 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 761
1da177e4
LT		 762 tw32_f(MAC_MI_COM, frame_val);
763
764 loops = PHY_BUSY_LOOPS;
765 while (loops != 0) {
766 udelay(10);
767 frame_val = tr32(MAC_MI_COM);
768
769 if ((frame_val & MI_COM_BUSY) == 0) {
770 udelay(5);
771 frame_val = tr32(MAC_MI_COM);
772 break;
773 }
774 loops -= 1;
775 }
776
777 ret = -EBUSY;
778 if (loops != 0) {
779 *val = frame_val & MI_COM_DATA_MASK;
780 ret = 0;
781 }
782
783 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
784 tw32_f(MAC_MI_MODE, tp->mi_mode);
785 udelay(80);
786 }
787
788 return ret;
789}
790
791static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
792{
793 u32 frame_val;
794 unsigned int loops;
795 int ret;
796
7f97a4bd 797 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 798 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
799 return 0;
800
1da177e4
LT		 801 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
802 tw32_f(MAC_MI_MODE,
803 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
804 udelay(80);
805 }
806
807 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
808 MI_COM_PHY_ADDR_MASK);
809 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810 MI_COM_REG_ADDR_MASK);
811 frame_val |= (val & MI_COM_DATA_MASK);
812 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 813
1da177e4
LT		 814 tw32_f(MAC_MI_COM, frame_val);
815
816 loops = PHY_BUSY_LOOPS;
817 while (loops != 0) {
818 udelay(10);
819 frame_val = tr32(MAC_MI_COM);
820 if ((frame_val & MI_COM_BUSY) == 0) {
821 udelay(5);
822 frame_val = tr32(MAC_MI_COM);
823 break;
824 }
825 loops -= 1;
826 }
827
828 ret = -EBUSY;
829 if (loops != 0)
830 ret = 0;
831
832 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
833 tw32_f(MAC_MI_MODE, tp->mi_mode);
834 udelay(80);
835 }
836
837 return ret;
838}
839
95e2869a
MC		 840static int tg3_bmcr_reset(struct tg3 *tp)
841{
842 u32 phy_control;
843 int limit, err;
844
845 /* OK, reset it, and poll the BMCR_RESET bit until it
846 * clears or we time out.
847 */
848 phy_control = BMCR_RESET;
849 err = tg3_writephy(tp, MII_BMCR, phy_control);
850 if (err != 0)
851 return -EBUSY;
852
853 limit = 5000;
854 while (limit--) {
855 err = tg3_readphy(tp, MII_BMCR, &phy_control);
856 if (err != 0)
857 return -EBUSY;
858
859 if ((phy_control & BMCR_RESET) == 0) {
860 udelay(40);
861 break;
862 }
863 udelay(10);
864 }
d4675b52 865 if (limit < 0)
95e2869a
MC		 866 return -EBUSY;
867
868 return 0;
869}
870
158d7abd
MC		 871static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
872{
3d16543d 873 struct tg3 *tp = bp->priv;
158d7abd
MC		 874 u32 val;
875
876 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
877 return -EAGAIN;
878
879 if (tg3_readphy(tp, reg, &val))
880 return -EIO;
881
882 return val;
883}
884
885static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
886{
3d16543d 887 struct tg3 *tp = bp->priv;
158d7abd
MC		 888
889 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
890 return -EAGAIN;
891
892 if (tg3_writephy(tp, reg, val))
893 return -EIO;
894
895 return 0;
896}
897
898static int tg3_mdio_reset(struct mii_bus *bp)
899{
900 return 0;
901}
902
9c61d6bc 903static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 904{
905 u32 val;
fcb389df 906 struct phy_device *phydev;
a9daf367 907
fcb389df
MC		 908 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
909 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
910 case TG3_PHY_ID_BCM50610:
911 val = MAC_PHYCFG2_50610_LED_MODES;
912 break;
913 case TG3_PHY_ID_BCMAC131:
914 val = MAC_PHYCFG2_AC131_LED_MODES;
915 break;
916 case TG3_PHY_ID_RTL8211C:
917 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
918 break;
919 case TG3_PHY_ID_RTL8201E:
920 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
921 break;
922 default:
a9daf367 923 return;
fcb389df
MC		 924 }
925
926 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
927 tw32(MAC_PHYCFG2, val);
928
929 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 930 val &= ~(MAC_PHYCFG1_RGMII_INT |
931 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
932 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 933 tw32(MAC_PHYCFG1, val);
934
935 return;
936 }
937
938 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
939 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
940 MAC_PHYCFG2_FMODE_MASK_MASK |
941 MAC_PHYCFG2_GMODE_MASK_MASK |
942 MAC_PHYCFG2_ACT_MASK_MASK |
943 MAC_PHYCFG2_QUAL_MASK_MASK |
944 MAC_PHYCFG2_INBAND_ENABLE;
945
946 tw32(MAC_PHYCFG2, val);
a9daf367 947
bb85fbb6
MC		 948 val = tr32(MAC_PHYCFG1);
949 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
950 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
951 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 952 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
953 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
954 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
955 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
956 }
bb85fbb6
MC		 957 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
958 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
959 tw32(MAC_PHYCFG1, val);
a9daf367 960
a9daf367
MC		 961 val = tr32(MAC_EXT_RGMII_MODE);
962 val &= ~(MAC_RGMII_MODE_RX_INT_B |
963 MAC_RGMII_MODE_RX_QUALITY |
964 MAC_RGMII_MODE_RX_ACTIVITY |
965 MAC_RGMII_MODE_RX_ENG_DET |
966 MAC_RGMII_MODE_TX_ENABLE |
967 MAC_RGMII_MODE_TX_LOWPWR |
968 MAC_RGMII_MODE_TX_RESET);
fcb389df 969 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 970 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
971 val |= MAC_RGMII_MODE_RX_INT_B |
972 MAC_RGMII_MODE_RX_QUALITY |
973 MAC_RGMII_MODE_RX_ACTIVITY |
974 MAC_RGMII_MODE_RX_ENG_DET;
975 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
976 val |= MAC_RGMII_MODE_TX_ENABLE |
977 MAC_RGMII_MODE_TX_LOWPWR |
978 MAC_RGMII_MODE_TX_RESET;
979 }
980 tw32(MAC_EXT_RGMII_MODE, val);
981}
982
158d7abd
MC		 983static void tg3_mdio_start(struct tg3 *tp)
984{
985 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 986 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 987 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 988 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 989 }
990
991 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
992 tw32_f(MAC_MI_MODE, tp->mi_mode);
993 udelay(80);
a9daf367 994
9c61d6bc
MC		 995 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
997 tg3_mdio_config_5785(tp);
158d7abd
MC		 998}
999
1000static void tg3_mdio_stop(struct tg3 *tp)
1001{
1002 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 1003 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 1004 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 1005 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 1006 }
1007}
1008
1009static int tg3_mdio_init(struct tg3 *tp)
1010{
1011 int i;
1012 u32 reg;
a9daf367 1013 struct phy_device *phydev;
158d7abd
MC		 1014
1015 tg3_mdio_start(tp);
1016
1017 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1018 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1019 return 0;
1020
298cf9be
LB		 1021 tp->mdio_bus = mdiobus_alloc();
1022 if (tp->mdio_bus == NULL)
1023 return -ENOMEM;
158d7abd 1024
298cf9be
LB		 1025 tp->mdio_bus->name = "tg3 mdio bus";
1026 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1027 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1028 tp->mdio_bus->priv = tp;
1029 tp->mdio_bus->parent = &tp->pdev->dev;
1030 tp->mdio_bus->read = &tg3_mdio_read;
1031 tp->mdio_bus->write = &tg3_mdio_write;
1032 tp->mdio_bus->reset = &tg3_mdio_reset;
1033 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1034 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1035
1036 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1037 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1038
1039 /* The bus registration will look for all the PHYs on the mdio bus.
1040 * Unfortunately, it does not ensure the PHY is powered up before
1041 * accessing the PHY ID registers. A chip reset is the
1042 * quickest way to bring the device back to an operational state..
1043 */
1044 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1045 tg3_bmcr_reset(tp);
1046
298cf9be 1047 i = mdiobus_register(tp->mdio_bus);
a9daf367 1048 if (i) {
158d7abd
MC		 1049 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1050 tp->dev->name, i);
9c61d6bc 1051 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1052 return i;
1053 }
158d7abd 1054
298cf9be 1055 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1056
9c61d6bc
MC		 1057 if (!phydev || !phydev->drv) {
1058 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1059 mdiobus_unregister(tp->mdio_bus);
1060 mdiobus_free(tp->mdio_bus);
1061 return -ENODEV;
1062 }
1063
1064 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1065 case TG3_PHY_ID_BCM57780:
1066 phydev->interface = PHY_INTERFACE_MODE_GMII;
1067 break;
a9daf367 1068 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1069 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1070 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1071 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1072 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1073 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1074 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1075 /* fallthru */
1076 case TG3_PHY_ID_RTL8211C:
1077 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1078 break;
fcb389df 1079 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1080 case TG3_PHY_ID_BCMAC131:
1081 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1082 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1083 break;
1084 }
1085
9c61d6bc
MC		 1086 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1087
1088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1089 tg3_mdio_config_5785(tp);
a9daf367
MC		 1090
1091 return 0;
158d7abd
MC		 1092}
1093
1094static void tg3_mdio_fini(struct tg3 *tp)
1095{
1096 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1097 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1098 mdiobus_unregister(tp->mdio_bus);
1099 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1100 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1101 }
1102}
1103
4ba526ce
MC		 1104/* tp->lock is held. */
1105static inline void tg3_generate_fw_event(struct tg3 *tp)
1106{
1107 u32 val;
1108
1109 val = tr32(GRC_RX_CPU_EVENT);
1110 val |= GRC_RX_CPU_DRIVER_EVENT;
1111 tw32_f(GRC_RX_CPU_EVENT, val);
1112
1113 tp->last_event_jiffies = jiffies;
1114}
1115
1116#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1117
95e2869a
MC		 1118/* tp->lock is held. */
1119static void tg3_wait_for_event_ack(struct tg3 *tp)
1120{
1121 int i;
4ba526ce
MC		 1122 unsigned int delay_cnt;
1123 long time_remain;
1124
1125 /* If enough time has passed, no wait is necessary. */
1126 time_remain = (long)(tp->last_event_jiffies + 1 +
1127 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1128 (long)jiffies;
1129 if (time_remain < 0)
1130 return;
1131
1132 /* Check if we can shorten the wait time. */
1133 delay_cnt = jiffies_to_usecs(time_remain);
1134 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1135 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1136 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1137
4ba526ce 1138 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1139 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1140 break;
4ba526ce 1141 udelay(8);
95e2869a
MC		 1142 }
1143}
1144
1145/* tp->lock is held. */
1146static void tg3_ump_link_report(struct tg3 *tp)
1147{
1148 u32 reg;
1149 u32 val;
1150
1151 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1152 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1153 return;
1154
1155 tg3_wait_for_event_ack(tp);
1156
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1158
1159 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1160
1161 val = 0;
1162 if (!tg3_readphy(tp, MII_BMCR, &reg))
1163 val = reg << 16;
1164 if (!tg3_readphy(tp, MII_BMSR, &reg))
1165 val |= (reg & 0xffff);
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1167
1168 val = 0;
1169 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1170 val = reg << 16;
1171 if (!tg3_readphy(tp, MII_LPA, &reg))
1172 val |= (reg & 0xffff);
1173 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1174
1175 val = 0;
1176 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1177 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1178 val = reg << 16;
1179 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1180 val |= (reg & 0xffff);
1181 }
1182 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1183
1184 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1185 val = reg << 16;
1186 else
1187 val = 0;
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1189
4ba526ce 1190 tg3_generate_fw_event(tp);
95e2869a
MC		 1191}
1192
1193static void tg3_link_report(struct tg3 *tp)
1194{
1195 if (!netif_carrier_ok(tp->dev)) {
1196 if (netif_msg_link(tp))
1197 printk(KERN_INFO PFX "%s: Link is down.\n",
1198 tp->dev->name);
1199 tg3_ump_link_report(tp);
1200 } else if (netif_msg_link(tp)) {
1201 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1202 tp->dev->name,
1203 (tp->link_config.active_speed == SPEED_1000 ?
1204 1000 :
1205 (tp->link_config.active_speed == SPEED_100 ?
1206 100 : 10)),
1207 (tp->link_config.active_duplex == DUPLEX_FULL ?
1208 "full" : "half"));
1209
1210 printk(KERN_INFO PFX
1211 "%s: Flow control is %s for TX and %s for RX.\n",
1212 tp->dev->name,
e18ce346 1213 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1214 "on" : "off",
e18ce346 1215 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1216 "on" : "off");
1217 tg3_ump_link_report(tp);
1218 }
1219}
1220
1221static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1222{
1223 u16 miireg;
1224
e18ce346 1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1226 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1227 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1228 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1229 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1230 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235}
1236
1237static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1238{
1239 u16 miireg;
1240
e18ce346 1241 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1242 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1243 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1244 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1245 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1246 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1247 else
1248 miireg = 0;
1249
1250 return miireg;
1251}
1252
95e2869a
MC		 1253static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1254{
1255 u8 cap = 0;
1256
1257 if (lcladv & ADVERTISE_1000XPAUSE) {
1258 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1259 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1260 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1261 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1262 cap = FLOW_CTRL_RX;
95e2869a
MC		 1263 } else {
1264 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1265 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1266 }
1267 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1268 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1269 cap = FLOW_CTRL_TX;
95e2869a
MC		 1270 }
1271
1272 return cap;
1273}
1274
f51f3562 1275static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1276{
b02fd9e3 1277 u8 autoneg;
f51f3562 1278 u8 flowctrl = 0;
95e2869a
MC		 1279 u32 old_rx_mode = tp->rx_mode;
1280 u32 old_tx_mode = tp->tx_mode;
1281
b02fd9e3 1282 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1283 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1284 else
1285 autoneg = tp->link_config.autoneg;
1286
1287 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1288 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1289 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1290 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1291 else
bc02ff95 1292 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1293 } else
1294 flowctrl = tp->link_config.flowctrl;
95e2869a 1295
f51f3562 1296 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1297
e18ce346 1298 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1299 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1300 else
1301 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1302
f51f3562 1303 if (old_rx_mode != tp->rx_mode)
95e2869a 1304 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1305
e18ce346 1306 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1307 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1308 else
1309 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1310
f51f3562 1311 if (old_tx_mode != tp->tx_mode)
95e2869a 1312 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1313}
1314
b02fd9e3
MC		 1315static void tg3_adjust_link(struct net_device *dev)
1316{
1317 u8 oldflowctrl, linkmesg = 0;
1318 u32 mac_mode, lcl_adv, rmt_adv;
1319 struct tg3 *tp = netdev_priv(dev);
298cf9be 1320 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1321
1322 spin_lock(&tp->lock);
1323
1324 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1325 MAC_MODE_HALF_DUPLEX);
1326
1327 oldflowctrl = tp->link_config.active_flowctrl;
1328
1329 if (phydev->link) {
1330 lcl_adv = 0;
1331 rmt_adv = 0;
1332
1333 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1334 mac_mode |= MAC_MODE_PORT_MODE_MII;
1335 else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (phydev->duplex == DUPLEX_HALF)
1339 mac_mode |= MAC_MODE_HALF_DUPLEX;
1340 else {
1341 lcl_adv = tg3_advert_flowctrl_1000T(
1342 tp->link_config.flowctrl);
1343
1344 if (phydev->pause)
1345 rmt_adv = LPA_PAUSE_CAP;
1346 if (phydev->asym_pause)
1347 rmt_adv |= LPA_PAUSE_ASYM;
1348 }
1349
1350 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1351 } else
1352 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1353
1354 if (mac_mode != tp->mac_mode) {
1355 tp->mac_mode = mac_mode;
1356 tw32_f(MAC_MODE, tp->mac_mode);
1357 udelay(40);
1358 }
1359
fcb389df
MC		 1360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1361 if (phydev->speed == SPEED_10)
1362 tw32(MAC_MI_STAT,
1363 MAC_MI_STAT_10MBPS_MODE |
1364 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1365 else
1366 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1367 }
1368
b02fd9e3
MC		 1369 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1370 tw32(MAC_TX_LENGTHS,
1371 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1372 (6 << TX_LENGTHS_IPG_SHIFT) |
1373 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1374 else
1375 tw32(MAC_TX_LENGTHS,
1376 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1377 (6 << TX_LENGTHS_IPG_SHIFT) |
1378 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1379
1380 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1381 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1382 phydev->speed != tp->link_config.active_speed ||
1383 phydev->duplex != tp->link_config.active_duplex ||
1384 oldflowctrl != tp->link_config.active_flowctrl)
1385 linkmesg = 1;
1386
1387 tp->link_config.active_speed = phydev->speed;
1388 tp->link_config.active_duplex = phydev->duplex;
1389
1390 spin_unlock(&tp->lock);
1391
1392 if (linkmesg)
1393 tg3_link_report(tp);
1394}
1395
1396static int tg3_phy_init(struct tg3 *tp)
1397{
1398 struct phy_device *phydev;
1399
1400 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1401 return 0;
1402
1403 /* Bring the PHY back to a known state. */
1404 tg3_bmcr_reset(tp);
1405
298cf9be 1406 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1407
1408 /* Attach the MAC to the PHY. */
fb28ad35 1409 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1410 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1411 if (IS_ERR(phydev)) {
1412 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1413 return PTR_ERR(phydev);
1414 }
1415
b02fd9e3 1416 /* Mask with MAC supported features. */
9c61d6bc
MC		 1417 switch (phydev->interface) {
1418 case PHY_INTERFACE_MODE_GMII:
1419 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1420 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1421 phydev->supported &= (PHY_GBIT_FEATURES |
1422 SUPPORTED_Pause |
1423 SUPPORTED_Asym_Pause);
1424 break;
1425 }
1426 /* fallthru */
9c61d6bc
MC		 1427 case PHY_INTERFACE_MODE_MII:
1428 phydev->supported &= (PHY_BASIC_FEATURES |
1429 SUPPORTED_Pause |
1430 SUPPORTED_Asym_Pause);
1431 break;
1432 default:
1433 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1434 return -EINVAL;
1435 }
1436
1437 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1438
1439 phydev->advertising = phydev->supported;
1440
b02fd9e3
MC		 1441 return 0;
1442}
1443
1444static void tg3_phy_start(struct tg3 *tp)
1445{
1446 struct phy_device *phydev;
1447
1448 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1449 return;
1450
298cf9be 1451 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1452
1453 if (tp->link_config.phy_is_low_power) {
1454 tp->link_config.phy_is_low_power = 0;
1455 phydev->speed = tp->link_config.orig_speed;
1456 phydev->duplex = tp->link_config.orig_duplex;
1457 phydev->autoneg = tp->link_config.orig_autoneg;
1458 phydev->advertising = tp->link_config.orig_advertising;
1459 }
1460
1461 phy_start(phydev);
1462
1463 phy_start_aneg(phydev);
1464}
1465
1466static void tg3_phy_stop(struct tg3 *tp)
1467{
1468 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1469 return;
1470
298cf9be 1471 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1472}
1473
1474static void tg3_phy_fini(struct tg3 *tp)
1475{
1476 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1477 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1478 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1479 }
1480}
1481
b2a5c19c
MC		 1482static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1483{
1484 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1485 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1486}
1487
7f97a4bd
MC		 1488static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1489{
1490 u32 phytest;
1491
1492 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1493 u32 phy;
1494
1495 tg3_writephy(tp, MII_TG3_FET_TEST,
1496 phytest | MII_TG3_FET_SHADOW_EN);
1497 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1498 if (enable)
1499 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1500 else
1501 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1502 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1503 }
1504 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1505 }
1506}
1507
6833c043
MC		 1508static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1509{
1510 u32 reg;
1511
7f97a4bd 1512 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1513 return;
1514
7f97a4bd
MC		 1515 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1516 tg3_phy_fet_toggle_apd(tp, enable);
1517 return;
1518 }
1519
6833c043
MC		 1520 reg = MII_TG3_MISC_SHDW_WREN |
1521 MII_TG3_MISC_SHDW_SCR5_SEL |
1522 MII_TG3_MISC_SHDW_SCR5_LPED |
1523 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1524 MII_TG3_MISC_SHDW_SCR5_SDTL |
1525 MII_TG3_MISC_SHDW_SCR5_C125OE;
1526 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1527 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1528
1529 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1530
1531
1532 reg = MII_TG3_MISC_SHDW_WREN |
1533 MII_TG3_MISC_SHDW_APD_SEL |
1534 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1535 if (enable)
1536 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1537
1538 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1539}
1540
9ef8ca99
MC		 1541static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1542{
1543 u32 phy;
1544
1545 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1546 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1547 return;
1548
7f97a4bd 1549 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1550 u32 ephy;
1551
535ef6e1
MC		 1552 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1553 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1554
1555 tg3_writephy(tp, MII_TG3_FET_TEST,
1556 ephy | MII_TG3_FET_SHADOW_EN);
1557 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1558 if (enable)
535ef6e1 1559 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1560 else
535ef6e1
MC		 1561 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1562 tg3_writephy(tp, reg, phy);
9ef8ca99 1563 }
535ef6e1 1564 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1565 }
1566 } else {
1567 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1568 MII_TG3_AUXCTL_SHDWSEL_MISC;
1569 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1570 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1571 if (enable)
1572 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1573 else
1574 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1575 phy |= MII_TG3_AUXCTL_MISC_WREN;
1576 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1577 }
1578 }
1579}
1580
1da177e4
LT		 1581static void tg3_phy_set_wirespeed(struct tg3 *tp)
1582{
1583 u32 val;
1584
1585 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1586 return;
1587
1588 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1589 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1590 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1591 (val | (1 << 15) | (1 << 4)));
1592}
1593
b2a5c19c
MC		 1594static void tg3_phy_apply_otp(struct tg3 *tp)
1595{
1596 u32 otp, phy;
1597
1598 if (!tp->phy_otp)
1599 return;
1600
1601 otp = tp->phy_otp;
1602
1603 /* Enable SM_DSP clock and tx 6dB coding. */
1604 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1605 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1606 MII_TG3_AUXCTL_ACTL_TX_6DB;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608
1609 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1610 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1611 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1612
1613 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1614 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1615 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1616
1617 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1618 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1619 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1620
1621 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1622 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1623
1624 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1625 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1626
1627 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1628 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1629 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1630
1631 /* Turn off SM_DSP clock. */
1632 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1633 MII_TG3_AUXCTL_ACTL_TX_6DB;
1634 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1635}
1636
1da177e4
LT		 1637static int tg3_wait_macro_done(struct tg3 *tp)
1638{
1639 int limit = 100;
1640
1641 while (limit--) {
1642 u32 tmp32;
1643
1644 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1645 if ((tmp32 & 0x1000) == 0)
1646 break;
1647 }
1648 }
d4675b52 1649 if (limit < 0)
1da177e4
LT		 1650 return -EBUSY;
1651
1652 return 0;
1653}
1654
1655static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1656{
1657 static const u32 test_pat[4][6] = {
1658 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1659 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1660 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1661 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1662 };
1663 int chan;
1664
1665 for (chan = 0; chan < 4; chan++) {
1666 int i;
1667
1668 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1669 (chan * 0x2000) | 0x0200);
1670 tg3_writephy(tp, 0x16, 0x0002);
1671
1672 for (i = 0; i < 6; i++)
1673 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1674 test_pat[chan][i]);
1675
1676 tg3_writephy(tp, 0x16, 0x0202);
1677 if (tg3_wait_macro_done(tp)) {
1678 *resetp = 1;
1679 return -EBUSY;
1680 }
1681
1682 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1683 (chan * 0x2000) | 0x0200);
1684 tg3_writephy(tp, 0x16, 0x0082);
1685 if (tg3_wait_macro_done(tp)) {
1686 *resetp = 1;
1687 return -EBUSY;
1688 }
1689
1690 tg3_writephy(tp, 0x16, 0x0802);
1691 if (tg3_wait_macro_done(tp)) {
1692 *resetp = 1;
1693 return -EBUSY;
1694 }
1695
1696 for (i = 0; i < 6; i += 2) {
1697 u32 low, high;
1698
1699 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1700 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1701 tg3_wait_macro_done(tp)) {
1702 *resetp = 1;
1703 return -EBUSY;
1704 }
1705 low &= 0x7fff;
1706 high &= 0x000f;
1707 if (low != test_pat[chan][i] ||
1708 high != test_pat[chan][i+1]) {
1709 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1710 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1711 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1712
1713 return -EBUSY;
1714 }
1715 }
1716 }
1717
1718 return 0;
1719}
1720
1721static int tg3_phy_reset_chanpat(struct tg3 *tp)
1722{
1723 int chan;
1724
1725 for (chan = 0; chan < 4; chan++) {
1726 int i;
1727
1728 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1729 (chan * 0x2000) | 0x0200);
1730 tg3_writephy(tp, 0x16, 0x0002);
1731 for (i = 0; i < 6; i++)
1732 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1733 tg3_writephy(tp, 0x16, 0x0202);
1734 if (tg3_wait_macro_done(tp))
1735 return -EBUSY;
1736 }
1737
1738 return 0;
1739}
1740
1741static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1742{
1743 u32 reg32, phy9_orig;
1744 int retries, do_phy_reset, err;
1745
1746 retries = 10;
1747 do_phy_reset = 1;
1748 do {
1749 if (do_phy_reset) {
1750 err = tg3_bmcr_reset(tp);
1751 if (err)
1752 return err;
1753 do_phy_reset = 0;
1754 }
1755
1756 /* Disable transmitter and interrupt. */
1757 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1758 continue;
1759
1760 reg32 |= 0x3000;
1761 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1762
1763 /* Set full-duplex, 1000 mbps. */
1764 tg3_writephy(tp, MII_BMCR,
1765 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1766
1767 /* Set to master mode. */
1768 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1769 continue;
1770
1771 tg3_writephy(tp, MII_TG3_CTRL,
1772 (MII_TG3_CTRL_AS_MASTER |
1773 MII_TG3_CTRL_ENABLE_AS_MASTER));
1774
1775 /* Enable SM_DSP_CLOCK and 6dB. */
1776 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1777
1778 /* Block the PHY control access. */
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1780 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1781
1782 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1783 if (!err)
1784 break;
1785 } while (--retries);
1786
1787 err = tg3_phy_reset_chanpat(tp);
1788 if (err)
1789 return err;
1790
1791 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1792 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1793
1794 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1795 tg3_writephy(tp, 0x16, 0x0000);
1796
1797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1799 /* Set Extended packet length bit for jumbo frames */
1800 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1801 }
1802 else {
1803 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1804 }
1805
1806 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1807
1808 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1809 reg32 &= ~0x3000;
1810 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1811 } else if (!err)
1812 err = -EBUSY;
1813
1814 return err;
1815}
1816
1817/* This will reset the tigon3 PHY if there is no valid
1818 * link unless the FORCE argument is non-zero.
1819 */
1820static int tg3_phy_reset(struct tg3 *tp)
1821{
b2a5c19c 1822 u32 cpmuctrl;
1da177e4
LT		 1823 u32 phy_status;
1824 int err;
1825
60189ddf
MC		 1826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1827 u32 val;
1828
1829 val = tr32(GRC_MISC_CFG);
1830 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1831 udelay(40);
1832 }
1da177e4
LT		 1833 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1834 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1835 if (err != 0)
1836 return -EBUSY;
1837
c8e1e82b
MC		 1838 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1839 netif_carrier_off(tp->dev);
1840 tg3_link_report(tp);
1841 }
1842
1da177e4
LT		 1843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1846 err = tg3_phy_reset_5703_4_5(tp);
1847 if (err)
1848 return err;
1849 goto out;
1850 }
1851
b2a5c19c
MC		 1852 cpmuctrl = 0;
1853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1854 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1855 cpmuctrl = tr32(TG3_CPMU_CTRL);
1856 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1857 tw32(TG3_CPMU_CTRL,
1858 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1859 }
1860
1da177e4
LT		 1861 err = tg3_bmcr_reset(tp);
1862 if (err)
1863 return err;
1864
b2a5c19c
MC		 1865 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1866 u32 phy;
1867
1868 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1869 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1870
1871 tw32(TG3_CPMU_CTRL, cpmuctrl);
1872 }
1873
bcb37f6c
MC		 1874 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1875 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1876 u32 val;
1877
1878 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1879 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1880 CPMU_LSPD_1000MB_MACCLK_12_5) {
1881 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1882 udelay(40);
1883 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1884 }
1885 }
1886
b2a5c19c
MC		 1887 tg3_phy_apply_otp(tp);
1888
6833c043
MC		 1889 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1890 tg3_phy_toggle_apd(tp, true);
1891 else
1892 tg3_phy_toggle_apd(tp, false);
1893
1da177e4
LT		 1894out:
1895 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1896 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1898 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1899 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1900 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1901 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902 }
1903 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1904 tg3_writephy(tp, 0x1c, 0x8d68);
1905 tg3_writephy(tp, 0x1c, 0x8d68);
1906 }
1907 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1908 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1910 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1911 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1913 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1914 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1915 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1916 }
c424cb24
MC		 1917 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1918 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1919 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1920 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1921 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1922 tg3_writephy(tp, MII_TG3_TEST1,
1923 MII_TG3_TEST1_TRIM_EN | 0x4);
1924 } else
1925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1926 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1927 }
1da177e4
LT		 1928 /* Set Extended packet length bit (bit 14) on all chips that */
1929 /* support jumbo frames */
1930 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1931 /* Cannot do read-modify-write on 5401 */
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1933 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1934 u32 phy_reg;
1935
1936 /* Set bit 14 with read-modify-write to preserve other bits */
1937 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1938 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1940 }
1941
1942 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1943 * jumbo frames transmission.
1944 */
8f666b07 1945 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1946 u32 phy_reg;
1947
1948 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1949 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1950 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1951 }
1952
715116a1 1953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1954 /* adjust output voltage */
535ef6e1 1955 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1956 }
1957
9ef8ca99 1958 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1959 tg3_phy_set_wirespeed(tp);
1960 return 0;
1961}
1962
1963static void tg3_frob_aux_power(struct tg3 *tp)
1964{
1965 struct tg3 *tp_peer = tp;
1966
9d26e213 1967 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1968 return;
1969
8c2dc7e1
MC		 1970 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1971 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1972 struct net_device *dev_peer;
1973
1974 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1975 /* remove_one() may have been run on the peer. */
8c2dc7e1 1976 if (!dev_peer)
bc1c7567
MC		 1977 tp_peer = tp;
1978 else
1979 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1980 }
1981
1da177e4 1982 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1983 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1984 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1985 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1988 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1989 (GRC_LCLCTRL_GPIO_OE0 |
1990 GRC_LCLCTRL_GPIO_OE1 |
1991 GRC_LCLCTRL_GPIO_OE2 |
1992 GRC_LCLCTRL_GPIO_OUTPUT0 |
1993 GRC_LCLCTRL_GPIO_OUTPUT1),
1994 100);
8d519ab2
MC		 1995 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1996 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 1997 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1998 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1999 GRC_LCLCTRL_GPIO_OE1 |
2000 GRC_LCLCTRL_GPIO_OE2 |
2001 GRC_LCLCTRL_GPIO_OUTPUT0 |
2002 GRC_LCLCTRL_GPIO_OUTPUT1 |
2003 tp->grc_local_ctrl;
2004 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2005
2006 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2007 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2008
2009 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2010 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2011 } else {
2012 u32 no_gpio2;
dc56b7d4 2013 u32 grc_local_ctrl = 0;
1da177e4
LT		 2014
2015 if (tp_peer != tp &&
2016 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017 return;
2018
dc56b7d4
MC		 2019 /* Workaround to prevent overdrawing Amps. */
2020 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2021 ASIC_REV_5714) {
2022 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2023 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024 grc_local_ctrl, 100);
dc56b7d4
MC		 2025 }
2026
1da177e4
LT		 2027 /* On 5753 and variants, GPIO2 cannot be used. */
2028 no_gpio2 = tp->nic_sram_data_cfg &
2029 NIC_SRAM_DATA_CFG_NO_GPIO2;
2030
dc56b7d4 2031 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2032 GRC_LCLCTRL_GPIO_OE1 |
2033 GRC_LCLCTRL_GPIO_OE2 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 GRC_LCLCTRL_GPIO_OUTPUT2;
2036 if (no_gpio2) {
2037 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2038 GRC_LCLCTRL_GPIO_OUTPUT2);
2039 }
b401e9e2
MC		 2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 grc_local_ctrl, 100);
1da177e4
LT		 2042
2043 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2044
b401e9e2
MC		 2045 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2046 grc_local_ctrl, 100);
1da177e4
LT		 2047
2048 if (!no_gpio2) {
2049 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2050 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2051 grc_local_ctrl, 100);
1da177e4
LT		 2052 }
2053 }
2054 } else {
2055 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2056 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2057 if (tp_peer != tp &&
2058 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2059 return;
2060
b401e9e2
MC		 2061 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2062 (GRC_LCLCTRL_GPIO_OE1 |
2063 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2064
b401e9e2
MC		 2065 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2066 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2067
b401e9e2
MC		 2068 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2069 (GRC_LCLCTRL_GPIO_OE1 |
2070 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2071 }
2072 }
2073}
2074
e8f3f6ca
MC		 2075static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2076{
2077 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2078 return 1;
2079 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2080 if (speed != SPEED_10)
2081 return 1;
2082 } else if (speed == SPEED_10)
2083 return 1;
2084
2085 return 0;
2086}
2087
1da177e4
LT		 2088static int tg3_setup_phy(struct tg3 *, int);
2089
2090#define RESET_KIND_SHUTDOWN 0
2091#define RESET_KIND_INIT 1
2092#define RESET_KIND_SUSPEND 2
2093
2094static void tg3_write_sig_post_reset(struct tg3 *, int);
2095static int tg3_halt_cpu(struct tg3 *, u32);
2096
0a459aac 2097static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2098{
ce057f01
MC		 2099 u32 val;
2100
5129724a
MC		 2101 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2103 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2104 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2105
2106 sg_dig_ctrl |=
2107 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2108 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2109 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2110 }
3f7045c1 2111 return;
5129724a 2112 }
3f7045c1 2113
60189ddf 2114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2115 tg3_bmcr_reset(tp);
2116 val = tr32(GRC_MISC_CFG);
2117 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2118 udelay(40);
2119 return;
0a459aac 2120 } else if (do_low_power) {
715116a1
MC		 2121 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2122 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2123
2124 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2125 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2126 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2127 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2128 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2129 }
3f7045c1 2130
15c3b696
MC		 2131 /* The PHY should not be powered down on some chips because
2132 * of bugs.
2133 */
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2137 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2138 return;
ce057f01 2139
bcb37f6c
MC		 2140 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2141 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2142 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2143 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2144 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2145 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2146 }
2147
15c3b696
MC		 2148 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2149}
2150
ffbcfed4
MC		 2151/* tp->lock is held. */
2152static int tg3_nvram_lock(struct tg3 *tp)
2153{
2154 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2155 int i;
2156
2157 if (tp->nvram_lock_cnt == 0) {
2158 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2159 for (i = 0; i < 8000; i++) {
2160 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2161 break;
2162 udelay(20);
2163 }
2164 if (i == 8000) {
2165 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2166 return -ENODEV;
2167 }
2168 }
2169 tp->nvram_lock_cnt++;
2170 }
2171 return 0;
2172}
2173
2174/* tp->lock is held. */
2175static void tg3_nvram_unlock(struct tg3 *tp)
2176{
2177 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2178 if (tp->nvram_lock_cnt > 0)
2179 tp->nvram_lock_cnt--;
2180 if (tp->nvram_lock_cnt == 0)
2181 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2182 }
2183}
2184
2185/* tp->lock is held. */
2186static void tg3_enable_nvram_access(struct tg3 *tp)
2187{
2188 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2189 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2190 u32 nvaccess = tr32(NVRAM_ACCESS);
2191
2192 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2193 }
2194}
2195
2196/* tp->lock is held. */
2197static void tg3_disable_nvram_access(struct tg3 *tp)
2198{
2199 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2200 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2201 u32 nvaccess = tr32(NVRAM_ACCESS);
2202
2203 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2204 }
2205}
2206
2207static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2208 u32 offset, u32 *val)
2209{
2210 u32 tmp;
2211 int i;
2212
2213 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2214 return -EINVAL;
2215
2216 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2217 EEPROM_ADDR_DEVID_MASK |
2218 EEPROM_ADDR_READ);
2219 tw32(GRC_EEPROM_ADDR,
2220 tmp |
2221 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2222 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2223 EEPROM_ADDR_ADDR_MASK) |
2224 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2225
2226 for (i = 0; i < 1000; i++) {
2227 tmp = tr32(GRC_EEPROM_ADDR);
2228
2229 if (tmp & EEPROM_ADDR_COMPLETE)
2230 break;
2231 msleep(1);
2232 }
2233 if (!(tmp & EEPROM_ADDR_COMPLETE))
2234 return -EBUSY;
2235
62cedd11
MC		 2236 tmp = tr32(GRC_EEPROM_DATA);
2237
2238 /*
2239 * The data will always be opposite the native endian
2240 * format. Perform a blind byteswap to compensate.
2241 */
2242 *val = swab32(tmp);
2243
ffbcfed4
MC		 2244 return 0;
2245}
2246
2247#define NVRAM_CMD_TIMEOUT 10000
2248
2249static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2250{
2251 int i;
2252
2253 tw32(NVRAM_CMD, nvram_cmd);
2254 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2255 udelay(10);
2256 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2257 udelay(10);
2258 break;
2259 }
2260 }
2261
2262 if (i == NVRAM_CMD_TIMEOUT)
2263 return -EBUSY;
2264
2265 return 0;
2266}
2267
2268static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2269{
2270 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2271 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2272 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2273 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2274 (tp->nvram_jedecnum == JEDEC_ATMEL))
2275
2276 addr = ((addr / tp->nvram_pagesize) <<
2277 ATMEL_AT45DB0X1B_PAGE_POS) +
2278 (addr % tp->nvram_pagesize);
2279
2280 return addr;
2281}
2282
2283static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2284{
2285 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2286 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2287 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2288 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2289 (tp->nvram_jedecnum == JEDEC_ATMEL))
2290
2291 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2292 tp->nvram_pagesize) +
2293 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2294
2295 return addr;
2296}
2297
e4f34110
MC		 2298/* NOTE: Data read in from NVRAM is byteswapped according to
2299 * the byteswapping settings for all other register accesses.
2300 * tg3 devices are BE devices, so on a BE machine, the data
2301 * returned will be exactly as it is seen in NVRAM. On a LE
2302 * machine, the 32-bit value will be byteswapped.
2303 */
ffbcfed4
MC		 2304static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2305{
2306 int ret;
2307
2308 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2309 return tg3_nvram_read_using_eeprom(tp, offset, val);
2310
2311 offset = tg3_nvram_phys_addr(tp, offset);
2312
2313 if (offset > NVRAM_ADDR_MSK)
2314 return -EINVAL;
2315
2316 ret = tg3_nvram_lock(tp);
2317 if (ret)
2318 return ret;
2319
2320 tg3_enable_nvram_access(tp);
2321
2322 tw32(NVRAM_ADDR, offset);
2323 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2324 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2325
2326 if (ret == 0)
e4f34110 2327 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2328
2329 tg3_disable_nvram_access(tp);
2330
2331 tg3_nvram_unlock(tp);
2332
2333 return ret;
2334}
2335
a9dc529d
MC		 2336/* Ensures NVRAM data is in bytestream format. */
2337static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2338{
2339 u32 v;
a9dc529d 2340 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2341 if (!res)
a9dc529d 2342 *val = cpu_to_be32(v);
ffbcfed4
MC		 2343 return res;
2344}
2345
3f007891
MC		 2346/* tp->lock is held. */
2347static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2348{
2349 u32 addr_high, addr_low;
2350 int i;
2351
2352 addr_high = ((tp->dev->dev_addr[0] << 8) |
2353 tp->dev->dev_addr[1]);
2354 addr_low = ((tp->dev->dev_addr[2] << 24) |
2355 (tp->dev->dev_addr[3] << 16) |
2356 (tp->dev->dev_addr[4] << 8) |
2357 (tp->dev->dev_addr[5] << 0));
2358 for (i = 0; i < 4; i++) {
2359 if (i == 1 && skip_mac_1)
2360 continue;
2361 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2362 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2363 }
2364
2365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2367 for (i = 0; i < 12; i++) {
2368 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2369 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2370 }
2371 }
2372
2373 addr_high = (tp->dev->dev_addr[0] +
2374 tp->dev->dev_addr[1] +
2375 tp->dev->dev_addr[2] +
2376 tp->dev->dev_addr[3] +
2377 tp->dev->dev_addr[4] +
2378 tp->dev->dev_addr[5]) &
2379 TX_BACKOFF_SEED_MASK;
2380 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2381}
2382
bc1c7567 2383static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2384{
2385 u32 misc_host_ctrl;
0a459aac 2386 bool device_should_wake, do_low_power;
1da177e4
LT		 2387
2388 /* Make sure register accesses (indirect or otherwise)
2389 * will function correctly.
2390 */
2391 pci_write_config_dword(tp->pdev,
2392 TG3PCI_MISC_HOST_CTRL,
2393 tp->misc_host_ctrl);
2394
1da177e4 2395 switch (state) {
bc1c7567 2396 case PCI_D0:
12dac075
RW		 2397 pci_enable_wake(tp->pdev, state, false);
2398 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2399
9d26e213
MC		 2400 /* Switch out of Vaux if it is a NIC */
2401 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2402 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2403
2404 return 0;
2405
bc1c7567 2406 case PCI_D1:
bc1c7567 2407 case PCI_D2:
bc1c7567 2408 case PCI_D3hot:
1da177e4
LT		 2409 break;
2410
2411 default:
12dac075
RW		 2412 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2413 tp->dev->name, state);
1da177e4 2414 return -EINVAL;
855e1111 2415 }
5e7dfd0f
MC		 2416
2417 /* Restore the CLKREQ setting. */
2418 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2419 u16 lnkctl;
2420
2421 pci_read_config_word(tp->pdev,
2422 tp->pcie_cap + PCI_EXP_LNKCTL,
2423 &lnkctl);
2424 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2425 pci_write_config_word(tp->pdev,
2426 tp->pcie_cap + PCI_EXP_LNKCTL,
2427 lnkctl);
2428 }
2429
1da177e4
LT		 2430 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2431 tw32(TG3PCI_MISC_HOST_CTRL,
2432 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2433
05ac4cb7
MC		 2434 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2435 device_may_wakeup(&tp->pdev->dev) &&
2436 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2437
dd477003 2438 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2439 do_low_power = false;
b02fd9e3
MC		 2440 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2441 !tp->link_config.phy_is_low_power) {
2442 struct phy_device *phydev;
0a459aac 2443 u32 phyid, advertising;
b02fd9e3 2444
298cf9be 2445 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2446
2447 tp->link_config.phy_is_low_power = 1;
2448
2449 tp->link_config.orig_speed = phydev->speed;
2450 tp->link_config.orig_duplex = phydev->duplex;
2451 tp->link_config.orig_autoneg = phydev->autoneg;
2452 tp->link_config.orig_advertising = phydev->advertising;
2453
2454 advertising = ADVERTISED_TP |
2455 ADVERTISED_Pause |
2456 ADVERTISED_Autoneg |
2457 ADVERTISED_10baseT_Half;
2458
2459 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2460 device_should_wake) {
b02fd9e3
MC		 2461 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2462 advertising |=
2463 ADVERTISED_100baseT_Half |
2464 ADVERTISED_100baseT_Full |
2465 ADVERTISED_10baseT_Full;
2466 else
2467 advertising |= ADVERTISED_10baseT_Full;
2468 }
2469
2470 phydev->advertising = advertising;
2471
2472 phy_start_aneg(phydev);
0a459aac
MC		 2473
2474 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2475 if (phyid != TG3_PHY_ID_BCMAC131) {
2476 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2477 if (phyid == TG3_PHY_OUI_1 ||
2478 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2479 phyid == TG3_PHY_OUI_3)
2480 do_low_power = true;
2481 }
b02fd9e3 2482 }
dd477003 2483 } else {
2023276e 2484 do_low_power = true;
0a459aac 2485
dd477003
MC		 2486 if (tp->link_config.phy_is_low_power == 0) {
2487 tp->link_config.phy_is_low_power = 1;
2488 tp->link_config.orig_speed = tp->link_config.speed;
2489 tp->link_config.orig_duplex = tp->link_config.duplex;
2490 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2491 }
1da177e4 2492
dd477003
MC		 2493 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2494 tp->link_config.speed = SPEED_10;
2495 tp->link_config.duplex = DUPLEX_HALF;
2496 tp->link_config.autoneg = AUTONEG_ENABLE;
2497 tg3_setup_phy(tp, 0);
2498 }
1da177e4
LT		 2499 }
2500
b5d3772c
MC		 2501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2502 u32 val;
2503
2504 val = tr32(GRC_VCPU_EXT_CTRL);
2505 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2506 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2507 int i;
2508 u32 val;
2509
2510 for (i = 0; i < 200; i++) {
2511 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2512 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2513 break;
2514 msleep(1);
2515 }
2516 }
a85feb8c
GZ		 2517 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2518 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2519 WOL_DRV_STATE_SHUTDOWN |
2520 WOL_DRV_WOL |
2521 WOL_SET_MAGIC_PKT);
6921d201 2522
05ac4cb7 2523 if (device_should_wake) {
1da177e4
LT		 2524 u32 mac_mode;
2525
2526 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2527 if (do_low_power) {
dd477003
MC		 2528 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2529 udelay(40);
2530 }
1da177e4 2531
3f7045c1
MC		 2532 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2533 mac_mode = MAC_MODE_PORT_MODE_GMII;
2534 else
2535 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2536
e8f3f6ca
MC		 2537 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2538 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2539 ASIC_REV_5700) {
2540 u32 speed = (tp->tg3_flags &
2541 TG3_FLAG_WOL_SPEED_100MB) ?
2542 SPEED_100 : SPEED_10;
2543 if (tg3_5700_link_polarity(tp, speed))
2544 mac_mode |= MAC_MODE_LINK_POLARITY;
2545 else
2546 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2547 }
1da177e4
LT		 2548 } else {
2549 mac_mode = MAC_MODE_PORT_MODE_TBI;
2550 }
2551
cbf46853 2552 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2553 tw32(MAC_LED_CTRL, tp->led_ctrl);
2554
05ac4cb7
MC		 2555 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2556 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2557 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2558 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2559 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2560 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2561
3bda1258
MC		 2562 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2563 mac_mode |= tp->mac_mode &
2564 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2565 if (mac_mode & MAC_MODE_APE_TX_EN)
2566 mac_mode |= MAC_MODE_TDE_ENABLE;
2567 }
2568
1da177e4
LT		 2569 tw32_f(MAC_MODE, mac_mode);
2570 udelay(100);
2571
2572 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2573 udelay(10);
2574 }
2575
2576 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2577 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2579 u32 base_val;
2580
2581 base_val = tp->pci_clock_ctrl;
2582 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2583 CLOCK_CTRL_TXCLK_DISABLE);
2584
b401e9e2
MC		 2585 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2586 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2587 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2588 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2590 /* do nothing */
85e94ced 2591 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2592 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2593 u32 newbits1, newbits2;
2594
2595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2597 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2598 CLOCK_CTRL_TXCLK_DISABLE |
2599 CLOCK_CTRL_ALTCLK);
2600 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2601 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2602 newbits1 = CLOCK_CTRL_625_CORE;
2603 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2604 } else {
2605 newbits1 = CLOCK_CTRL_ALTCLK;
2606 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2607 }
2608
b401e9e2
MC		 2609 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2610 40);
1da177e4 2611
b401e9e2
MC		 2612 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2613 40);
1da177e4
LT		 2614
2615 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2616 u32 newbits3;
2617
2618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2620 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2621 CLOCK_CTRL_TXCLK_DISABLE |
2622 CLOCK_CTRL_44MHZ_CORE);
2623 } else {
2624 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2625 }
2626
b401e9e2
MC		 2627 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2628 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2629 }
2630 }
2631
05ac4cb7 2632 if (!(device_should_wake) &&
22435849 2633 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2634 tg3_power_down_phy(tp, do_low_power);
6921d201 2635
1da177e4
LT		 2636 tg3_frob_aux_power(tp);
2637
2638 /* Workaround for unstable PLL clock */
2639 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2640 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2641 u32 val = tr32(0x7d00);
2642
2643 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2644 tw32(0x7d00, val);
6921d201 2645 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2646 int err;
2647
2648 err = tg3_nvram_lock(tp);
1da177e4 2649 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2650 if (!err)
2651 tg3_nvram_unlock(tp);
6921d201 2652 }
1da177e4
LT		 2653 }
2654
bbadf503
MC		 2655 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2656
05ac4cb7 2657 if (device_should_wake)
12dac075
RW		 2658 pci_enable_wake(tp->pdev, state, true);
2659
1da177e4 2660 /* Finally, set the new power state. */
12dac075 2661 pci_set_power_state(tp->pdev, state);
1da177e4 2662
1da177e4
LT		 2663 return 0;
2664}
2665
1da177e4
LT		 2666static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2667{
2668 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2669 case MII_TG3_AUX_STAT_10HALF:
2670 *speed = SPEED_10;
2671 *duplex = DUPLEX_HALF;
2672 break;
2673
2674 case MII_TG3_AUX_STAT_10FULL:
2675 *speed = SPEED_10;
2676 *duplex = DUPLEX_FULL;
2677 break;
2678
2679 case MII_TG3_AUX_STAT_100HALF:
2680 *speed = SPEED_100;
2681 *duplex = DUPLEX_HALF;
2682 break;
2683
2684 case MII_TG3_AUX_STAT_100FULL:
2685 *speed = SPEED_100;
2686 *duplex = DUPLEX_FULL;
2687 break;
2688
2689 case MII_TG3_AUX_STAT_1000HALF:
2690 *speed = SPEED_1000;
2691 *duplex = DUPLEX_HALF;
2692 break;
2693
2694 case MII_TG3_AUX_STAT_1000FULL:
2695 *speed = SPEED_1000;
2696 *duplex = DUPLEX_FULL;
2697 break;
2698
2699 default:
7f97a4bd 2700 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2701 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2702 SPEED_10;
2703 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2704 DUPLEX_HALF;
2705 break;
2706 }
1da177e4
LT		 2707 *speed = SPEED_INVALID;
2708 *duplex = DUPLEX_INVALID;
2709 break;
855e1111 2710 }
1da177e4
LT		 2711}
2712
2713static void tg3_phy_copper_begin(struct tg3 *tp)
2714{
2715 u32 new_adv;
2716 int i;
2717
2718 if (tp->link_config.phy_is_low_power) {
2719 /* Entering low power mode. Disable gigabit and
2720 * 100baseT advertisements.
2721 */
2722 tg3_writephy(tp, MII_TG3_CTRL, 0);
2723
2724 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2725 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2726 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2727 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2728
2729 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2730 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2731 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2732 tp->link_config.advertising &=
2733 ~(ADVERTISED_1000baseT_Half |
2734 ADVERTISED_1000baseT_Full);
2735
ba4d07a8 2736 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2737 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2738 new_adv |= ADVERTISE_10HALF;
2739 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2740 new_adv |= ADVERTISE_10FULL;
2741 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2742 new_adv |= ADVERTISE_100HALF;
2743 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2744 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2745
2746 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2747
1da177e4
LT		 2748 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2749
2750 if (tp->link_config.advertising &
2751 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2752 new_adv = 0;
2753 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2754 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2755 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2756 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2757 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2758 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2759 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2760 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2761 MII_TG3_CTRL_ENABLE_AS_MASTER);
2762 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2763 } else {
2764 tg3_writephy(tp, MII_TG3_CTRL, 0);
2765 }
2766 } else {
ba4d07a8
MC		 2767 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2768 new_adv |= ADVERTISE_CSMA;
2769
1da177e4
LT		 2770 /* Asking for a specific link mode. */
2771 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2772 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2773
2774 if (tp->link_config.duplex == DUPLEX_FULL)
2775 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2776 else
2777 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2778 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2779 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2780 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2781 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2782 } else {
1da177e4
LT		 2783 if (tp->link_config.speed == SPEED_100) {
2784 if (tp->link_config.duplex == DUPLEX_FULL)
2785 new_adv |= ADVERTISE_100FULL;
2786 else
2787 new_adv |= ADVERTISE_100HALF;
2788 } else {
2789 if (tp->link_config.duplex == DUPLEX_FULL)
2790 new_adv |= ADVERTISE_10FULL;
2791 else
2792 new_adv |= ADVERTISE_10HALF;
2793 }
2794 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2795
2796 new_adv = 0;
1da177e4 2797 }
ba4d07a8
MC		 2798
2799 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2800 }
2801
2802 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2803 tp->link_config.speed != SPEED_INVALID) {
2804 u32 bmcr, orig_bmcr;
2805
2806 tp->link_config.active_speed = tp->link_config.speed;
2807 tp->link_config.active_duplex = tp->link_config.duplex;
2808
2809 bmcr = 0;
2810 switch (tp->link_config.speed) {
2811 default:
2812 case SPEED_10:
2813 break;
2814
2815 case SPEED_100:
2816 bmcr |= BMCR_SPEED100;
2817 break;
2818
2819 case SPEED_1000:
2820 bmcr |= TG3_BMCR_SPEED1000;
2821 break;
855e1111 2822 }
1da177e4
LT		 2823
2824 if (tp->link_config.duplex == DUPLEX_FULL)
2825 bmcr |= BMCR_FULLDPLX;
2826
2827 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2828 (bmcr != orig_bmcr)) {
2829 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2830 for (i = 0; i < 1500; i++) {
2831 u32 tmp;
2832
2833 udelay(10);
2834 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2835 tg3_readphy(tp, MII_BMSR, &tmp))
2836 continue;
2837 if (!(tmp & BMSR_LSTATUS)) {
2838 udelay(40);
2839 break;
2840 }
2841 }
2842 tg3_writephy(tp, MII_BMCR, bmcr);
2843 udelay(40);
2844 }
2845 } else {
2846 tg3_writephy(tp, MII_BMCR,
2847 BMCR_ANENABLE | BMCR_ANRESTART);
2848 }
2849}
2850
2851static int tg3_init_5401phy_dsp(struct tg3 *tp)
2852{
2853 int err;
2854
2855 /* Turn off tap power management. */
2856 /* Set Extended packet length bit */
2857 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2858
2859 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2860 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2861
2862 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2863 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2864
2865 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2866 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2867
2868 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2869 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2870
2871 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2872 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2873
2874 udelay(40);
2875
2876 return err;
2877}
2878
3600d918 2879static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2880{
3600d918
MC		 2881 u32 adv_reg, all_mask = 0;
2882
2883 if (mask & ADVERTISED_10baseT_Half)
2884 all_mask |= ADVERTISE_10HALF;
2885 if (mask & ADVERTISED_10baseT_Full)
2886 all_mask |= ADVERTISE_10FULL;
2887 if (mask & ADVERTISED_100baseT_Half)
2888 all_mask |= ADVERTISE_100HALF;
2889 if (mask & ADVERTISED_100baseT_Full)
2890 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2891
2892 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2893 return 0;
2894
1da177e4
LT		 2895 if ((adv_reg & all_mask) != all_mask)
2896 return 0;
2897 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2898 u32 tg3_ctrl;
2899
3600d918
MC		 2900 all_mask = 0;
2901 if (mask & ADVERTISED_1000baseT_Half)
2902 all_mask |= ADVERTISE_1000HALF;
2903 if (mask & ADVERTISED_1000baseT_Full)
2904 all_mask |= ADVERTISE_1000FULL;
2905
1da177e4
LT		 2906 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2907 return 0;
2908
1da177e4
LT		 2909 if ((tg3_ctrl & all_mask) != all_mask)
2910 return 0;
2911 }
2912 return 1;
2913}
2914
ef167e27
MC		 2915static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2916{
2917 u32 curadv, reqadv;
2918
2919 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2920 return 1;
2921
2922 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2923 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2924
2925 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2926 if (curadv != reqadv)
2927 return 0;
2928
2929 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2930 tg3_readphy(tp, MII_LPA, rmtadv);
2931 } else {
2932 /* Reprogram the advertisement register, even if it
2933 * does not affect the current link. If the link
2934 * gets renegotiated in the future, we can save an
2935 * additional renegotiation cycle by advertising
2936 * it correctly in the first place.
2937 */
2938 if (curadv != reqadv) {
2939 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2940 ADVERTISE_PAUSE_ASYM);
2941 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2942 }
2943 }
2944
2945 return 1;
2946}
2947
1da177e4
LT		 2948static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2949{
2950 int current_link_up;
2951 u32 bmsr, dummy;
ef167e27 2952 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2953 u16 current_speed;
2954 u8 current_duplex;
2955 int i, err;
2956
2957 tw32(MAC_EVENT, 0);
2958
2959 tw32_f(MAC_STATUS,
2960 (MAC_STATUS_SYNC_CHANGED |
2961 MAC_STATUS_CFG_CHANGED |
2962 MAC_STATUS_MI_COMPLETION |
2963 MAC_STATUS_LNKSTATE_CHANGED));
2964 udelay(40);
2965
8ef21428
MC		 2966 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2967 tw32_f(MAC_MI_MODE,
2968 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2969 udelay(80);
2970 }
1da177e4
LT		 2971
2972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2973
2974 /* Some third-party PHYs need to be reset on link going
2975 * down.
2976 */
2977 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2980 netif_carrier_ok(tp->dev)) {
2981 tg3_readphy(tp, MII_BMSR, &bmsr);
2982 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2983 !(bmsr & BMSR_LSTATUS))
2984 force_reset = 1;
2985 }
2986 if (force_reset)
2987 tg3_phy_reset(tp);
2988
2989 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2990 tg3_readphy(tp, MII_BMSR, &bmsr);
2991 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2992 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2993 bmsr = 0;
2994
2995 if (!(bmsr & BMSR_LSTATUS)) {
2996 err = tg3_init_5401phy_dsp(tp);
2997 if (err)
2998 return err;
2999
3000 tg3_readphy(tp, MII_BMSR, &bmsr);
3001 for (i = 0; i < 1000; i++) {
3002 udelay(10);
3003 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3004 (bmsr & BMSR_LSTATUS)) {
3005 udelay(40);
3006 break;
3007 }
3008 }
3009
3010 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3011 !(bmsr & BMSR_LSTATUS) &&
3012 tp->link_config.active_speed == SPEED_1000) {
3013 err = tg3_phy_reset(tp);
3014 if (!err)
3015 err = tg3_init_5401phy_dsp(tp);
3016 if (err)
3017 return err;
3018 }
3019 }
3020 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3021 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3022 /* 5701 {A0,B0} CRC bug workaround */
3023 tg3_writephy(tp, 0x15, 0x0a75);
3024 tg3_writephy(tp, 0x1c, 0x8c68);
3025 tg3_writephy(tp, 0x1c, 0x8d68);
3026 tg3_writephy(tp, 0x1c, 0x8c68);
3027 }
3028
3029 /* Clear pending interrupts... */
3030 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3031 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3032
3033 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3034 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3035 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3036 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3037
3038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3040 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3041 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3042 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3043 else
3044 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3045 }
3046
3047 current_link_up = 0;
3048 current_speed = SPEED_INVALID;
3049 current_duplex = DUPLEX_INVALID;
3050
3051 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3052 u32 val;
3053
3054 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3055 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3056 if (!(val & (1 << 10))) {
3057 val |= (1 << 10);
3058 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3059 goto relink;
3060 }
3061 }
3062
3063 bmsr = 0;
3064 for (i = 0; i < 100; i++) {
3065 tg3_readphy(tp, MII_BMSR, &bmsr);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 (bmsr & BMSR_LSTATUS))
3068 break;
3069 udelay(40);
3070 }
3071
3072 if (bmsr & BMSR_LSTATUS) {
3073 u32 aux_stat, bmcr;
3074
3075 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3076 for (i = 0; i < 2000; i++) {
3077 udelay(10);
3078 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3079 aux_stat)
3080 break;
3081 }
3082
3083 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3084 &current_speed,
3085 &current_duplex);
3086
3087 bmcr = 0;
3088 for (i = 0; i < 200; i++) {
3089 tg3_readphy(tp, MII_BMCR, &bmcr);
3090 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3091 continue;
3092 if (bmcr && bmcr != 0x7fff)
3093 break;
3094 udelay(10);
3095 }
3096
ef167e27
MC		 3097 lcl_adv = 0;
3098 rmt_adv = 0;
1da177e4 3099
ef167e27
MC		 3100 tp->link_config.active_speed = current_speed;
3101 tp->link_config.active_duplex = current_duplex;
3102
3103 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3104 if ((bmcr & BMCR_ANENABLE) &&
3105 tg3_copper_is_advertising_all(tp,
3106 tp->link_config.advertising)) {
3107 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3108 &rmt_adv))
3109 current_link_up = 1;
1da177e4
LT		 3110 }
3111 } else {
3112 if (!(bmcr & BMCR_ANENABLE) &&
3113 tp->link_config.speed == current_speed &&
ef167e27
MC		 3114 tp->link_config.duplex == current_duplex &&
3115 tp->link_config.flowctrl ==
3116 tp->link_config.active_flowctrl) {
1da177e4 3117 current_link_up = 1;
1da177e4
LT		 3118 }
3119 }
3120
ef167e27
MC		 3121 if (current_link_up == 1 &&
3122 tp->link_config.active_duplex == DUPLEX_FULL)
3123 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3124 }
3125
1da177e4 3126relink:
6921d201 3127 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3128 u32 tmp;
3129
3130 tg3_phy_copper_begin(tp);
3131
3132 tg3_readphy(tp, MII_BMSR, &tmp);
3133 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3134 (tmp & BMSR_LSTATUS))
3135 current_link_up = 1;
3136 }
3137
3138 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3139 if (current_link_up == 1) {
3140 if (tp->link_config.active_speed == SPEED_100 ||
3141 tp->link_config.active_speed == SPEED_10)
3142 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3143 else
3144 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3145 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3146 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3147 else
1da177e4
LT		 3148 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3149
3150 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3151 if (tp->link_config.active_duplex == DUPLEX_HALF)
3152 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3153
1da177e4 3154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3155 if (current_link_up == 1 &&
3156 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3157 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3158 else
3159 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3160 }
3161
3162 /* ??? Without this setting Netgear GA302T PHY does not
3163 * ??? send/receive packets...
3164 */
3165 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3166 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3167 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3168 tw32_f(MAC_MI_MODE, tp->mi_mode);
3169 udelay(80);
3170 }
3171
3172 tw32_f(MAC_MODE, tp->mac_mode);
3173 udelay(40);
3174
3175 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3176 /* Polled via timer. */
3177 tw32_f(MAC_EVENT, 0);
3178 } else {
3179 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3180 }
3181 udelay(40);
3182
3183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3184 current_link_up == 1 &&
3185 tp->link_config.active_speed == SPEED_1000 &&
3186 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3187 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3188 udelay(120);
3189 tw32_f(MAC_STATUS,
3190 (MAC_STATUS_SYNC_CHANGED |
3191 MAC_STATUS_CFG_CHANGED));
3192 udelay(40);
3193 tg3_write_mem(tp,
3194 NIC_SRAM_FIRMWARE_MBOX,
3195 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3196 }
3197
5e7dfd0f
MC		 3198 /* Prevent send BD corruption. */
3199 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3200 u16 oldlnkctl, newlnkctl;
3201
3202 pci_read_config_word(tp->pdev,
3203 tp->pcie_cap + PCI_EXP_LNKCTL,
3204 &oldlnkctl);
3205 if (tp->link_config.active_speed == SPEED_100 ||
3206 tp->link_config.active_speed == SPEED_10)
3207 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3208 else
3209 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3210 if (newlnkctl != oldlnkctl)
3211 pci_write_config_word(tp->pdev,
3212 tp->pcie_cap + PCI_EXP_LNKCTL,
3213 newlnkctl);
255ca311
MC		 3214 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3215 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3216 if (tp->link_config.active_speed == SPEED_100 ||
3217 tp->link_config.active_speed == SPEED_10)
3218 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3219 else
3220 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3221 if (newreg != oldreg)
3222 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC		 3223 }
3224
1da177e4
LT		 3225 if (current_link_up != netif_carrier_ok(tp->dev)) {
3226 if (current_link_up)
3227 netif_carrier_on(tp->dev);
3228 else
3229 netif_carrier_off(tp->dev);
3230 tg3_link_report(tp);
3231 }
3232
3233 return 0;
3234}
3235
3236struct tg3_fiber_aneginfo {
3237 int state;
3238#define ANEG_STATE_UNKNOWN 0
3239#define ANEG_STATE_AN_ENABLE 1
3240#define ANEG_STATE_RESTART_INIT 2
3241#define ANEG_STATE_RESTART 3
3242#define ANEG_STATE_DISABLE_LINK_OK 4
3243#define ANEG_STATE_ABILITY_DETECT_INIT 5
3244#define ANEG_STATE_ABILITY_DETECT 6
3245#define ANEG_STATE_ACK_DETECT_INIT 7
3246#define ANEG_STATE_ACK_DETECT 8
3247#define ANEG_STATE_COMPLETE_ACK_INIT 9
3248#define ANEG_STATE_COMPLETE_ACK 10
3249#define ANEG_STATE_IDLE_DETECT_INIT 11
3250#define ANEG_STATE_IDLE_DETECT 12
3251#define ANEG_STATE_LINK_OK 13
3252#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3253#define ANEG_STATE_NEXT_PAGE_WAIT 15
3254
3255 u32 flags;
3256#define MR_AN_ENABLE 0x00000001
3257#define MR_RESTART_AN 0x00000002
3258#define MR_AN_COMPLETE 0x00000004
3259#define MR_PAGE_RX 0x00000008
3260#define MR_NP_LOADED 0x00000010
3261#define MR_TOGGLE_TX 0x00000020
3262#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3263#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3264#define MR_LP_ADV_SYM_PAUSE 0x00000100
3265#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3266#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3267#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3268#define MR_LP_ADV_NEXT_PAGE 0x00001000
3269#define MR_TOGGLE_RX 0x00002000
3270#define MR_NP_RX 0x00004000
3271
3272#define MR_LINK_OK 0x80000000
3273
3274 unsigned long link_time, cur_time;
3275
3276 u32 ability_match_cfg;
3277 int ability_match_count;
3278
3279 char ability_match, idle_match, ack_match;
3280
3281 u32 txconfig, rxconfig;
3282#define ANEG_CFG_NP 0x00000080
3283#define ANEG_CFG_ACK 0x00000040
3284#define ANEG_CFG_RF2 0x00000020
3285#define ANEG_CFG_RF1 0x00000010
3286#define ANEG_CFG_PS2 0x00000001
3287#define ANEG_CFG_PS1 0x00008000
3288#define ANEG_CFG_HD 0x00004000
3289#define ANEG_CFG_FD 0x00002000
3290#define ANEG_CFG_INVAL 0x00001f06
3291
3292};
3293#define ANEG_OK 0
3294#define ANEG_DONE 1
3295#define ANEG_TIMER_ENAB 2
3296#define ANEG_FAILED -1
3297
3298#define ANEG_STATE_SETTLE_TIME 10000
3299
3300static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3301 struct tg3_fiber_aneginfo *ap)
3302{
5be73b47 3303 u16 flowctrl;
1da177e4
LT		 3304 unsigned long delta;
3305 u32 rx_cfg_reg;
3306 int ret;
3307
3308 if (ap->state == ANEG_STATE_UNKNOWN) {
3309 ap->rxconfig = 0;
3310 ap->link_time = 0;
3311 ap->cur_time = 0;
3312 ap->ability_match_cfg = 0;
3313 ap->ability_match_count = 0;
3314 ap->ability_match = 0;
3315 ap->idle_match = 0;
3316 ap->ack_match = 0;
3317 }
3318 ap->cur_time++;
3319
3320 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3321 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3322
3323 if (rx_cfg_reg != ap->ability_match_cfg) {
3324 ap->ability_match_cfg = rx_cfg_reg;
3325 ap->ability_match = 0;
3326 ap->ability_match_count = 0;
3327 } else {
3328 if (++ap->ability_match_count > 1) {
3329 ap->ability_match = 1;
3330 ap->ability_match_cfg = rx_cfg_reg;
3331 }
3332 }
3333 if (rx_cfg_reg & ANEG_CFG_ACK)
3334 ap->ack_match = 1;
3335 else
3336 ap->ack_match = 0;
3337
3338 ap->idle_match = 0;
3339 } else {
3340 ap->idle_match = 1;
3341 ap->ability_match_cfg = 0;
3342 ap->ability_match_count = 0;
3343 ap->ability_match = 0;
3344 ap->ack_match = 0;
3345
3346 rx_cfg_reg = 0;
3347 }
3348
3349 ap->rxconfig = rx_cfg_reg;
3350 ret = ANEG_OK;
3351
3352 switch(ap->state) {
3353 case ANEG_STATE_UNKNOWN:
3354 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3355 ap->state = ANEG_STATE_AN_ENABLE;
3356
3357 /* fallthru */
3358 case ANEG_STATE_AN_ENABLE:
3359 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3360 if (ap->flags & MR_AN_ENABLE) {
3361 ap->link_time = 0;
3362 ap->cur_time = 0;
3363 ap->ability_match_cfg = 0;
3364 ap->ability_match_count = 0;
3365 ap->ability_match = 0;
3366 ap->idle_match = 0;
3367 ap->ack_match = 0;
3368
3369 ap->state = ANEG_STATE_RESTART_INIT;
3370 } else {
3371 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3372 }
3373 break;
3374
3375 case ANEG_STATE_RESTART_INIT:
3376 ap->link_time = ap->cur_time;
3377 ap->flags &= ~(MR_NP_LOADED);
3378 ap->txconfig = 0;
3379 tw32(MAC_TX_AUTO_NEG, 0);
3380 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3381 tw32_f(MAC_MODE, tp->mac_mode);
3382 udelay(40);
3383
3384 ret = ANEG_TIMER_ENAB;
3385 ap->state = ANEG_STATE_RESTART;
3386
3387 /* fallthru */
3388 case ANEG_STATE_RESTART:
3389 delta = ap->cur_time - ap->link_time;
3390 if (delta > ANEG_STATE_SETTLE_TIME) {
3391 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3392 } else {
3393 ret = ANEG_TIMER_ENAB;
3394 }
3395 break;
3396
3397 case ANEG_STATE_DISABLE_LINK_OK:
3398 ret = ANEG_DONE;
3399 break;
3400
3401 case ANEG_STATE_ABILITY_DETECT_INIT:
3402 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3403 ap->txconfig = ANEG_CFG_FD;
3404 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3405 if (flowctrl & ADVERTISE_1000XPAUSE)
3406 ap->txconfig |= ANEG_CFG_PS1;
3407 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3408 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3409 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3410 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3411 tw32_f(MAC_MODE, tp->mac_mode);
3412 udelay(40);
3413
3414 ap->state = ANEG_STATE_ABILITY_DETECT;
3415 break;
3416
3417 case ANEG_STATE_ABILITY_DETECT:
3418 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3419 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3420 }
3421 break;
3422
3423 case ANEG_STATE_ACK_DETECT_INIT:
3424 ap->txconfig |= ANEG_CFG_ACK;
3425 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3426 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3427 tw32_f(MAC_MODE, tp->mac_mode);
3428 udelay(40);
3429
3430 ap->state = ANEG_STATE_ACK_DETECT;
3431
3432 /* fallthru */
3433 case ANEG_STATE_ACK_DETECT:
3434 if (ap->ack_match != 0) {
3435 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3436 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3437 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3438 } else {
3439 ap->state = ANEG_STATE_AN_ENABLE;
3440 }
3441 } else if (ap->ability_match != 0 &&
3442 ap->rxconfig == 0) {
3443 ap->state = ANEG_STATE_AN_ENABLE;
3444 }
3445 break;
3446
3447 case ANEG_STATE_COMPLETE_ACK_INIT:
3448 if (ap->rxconfig & ANEG_CFG_INVAL) {
3449 ret = ANEG_FAILED;
3450 break;
3451 }
3452 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3453 MR_LP_ADV_HALF_DUPLEX |
3454 MR_LP_ADV_SYM_PAUSE |
3455 MR_LP_ADV_ASYM_PAUSE |
3456 MR_LP_ADV_REMOTE_FAULT1 |
3457 MR_LP_ADV_REMOTE_FAULT2 |
3458 MR_LP_ADV_NEXT_PAGE |
3459 MR_TOGGLE_RX |
3460 MR_NP_RX);
3461 if (ap->rxconfig & ANEG_CFG_FD)
3462 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3463 if (ap->rxconfig & ANEG_CFG_HD)
3464 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3465 if (ap->rxconfig & ANEG_CFG_PS1)
3466 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3467 if (ap->rxconfig & ANEG_CFG_PS2)
3468 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3469 if (ap->rxconfig & ANEG_CFG_RF1)
3470 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3471 if (ap->rxconfig & ANEG_CFG_RF2)
3472 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3473 if (ap->rxconfig & ANEG_CFG_NP)
3474 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3475
3476 ap->link_time = ap->cur_time;
3477
3478 ap->flags ^= (MR_TOGGLE_TX);
3479 if (ap->rxconfig & 0x0008)
3480 ap->flags |= MR_TOGGLE_RX;
3481 if (ap->rxconfig & ANEG_CFG_NP)
3482 ap->flags |= MR_NP_RX;
3483 ap->flags |= MR_PAGE_RX;
3484
3485 ap->state = ANEG_STATE_COMPLETE_ACK;
3486 ret = ANEG_TIMER_ENAB;
3487 break;
3488
3489 case ANEG_STATE_COMPLETE_ACK:
3490 if (ap->ability_match != 0 &&
3491 ap->rxconfig == 0) {
3492 ap->state = ANEG_STATE_AN_ENABLE;
3493 break;
3494 }
3495 delta = ap->cur_time - ap->link_time;
3496 if (delta > ANEG_STATE_SETTLE_TIME) {
3497 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3498 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3499 } else {
3500 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3501 !(ap->flags & MR_NP_RX)) {
3502 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3503 } else {
3504 ret = ANEG_FAILED;
3505 }
3506 }
3507 }
3508 break;
3509
3510 case ANEG_STATE_IDLE_DETECT_INIT:
3511 ap->link_time = ap->cur_time;
3512 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3513 tw32_f(MAC_MODE, tp->mac_mode);
3514 udelay(40);
3515
3516 ap->state = ANEG_STATE_IDLE_DETECT;
3517 ret = ANEG_TIMER_ENAB;
3518 break;
3519
3520 case ANEG_STATE_IDLE_DETECT:
3521 if (ap->ability_match != 0 &&
3522 ap->rxconfig == 0) {
3523 ap->state = ANEG_STATE_AN_ENABLE;
3524 break;
3525 }
3526 delta = ap->cur_time - ap->link_time;
3527 if (delta > ANEG_STATE_SETTLE_TIME) {
3528 /* XXX another gem from the Broadcom driver :( */
3529 ap->state = ANEG_STATE_LINK_OK;
3530 }
3531 break;
3532
3533 case ANEG_STATE_LINK_OK:
3534 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3535 ret = ANEG_DONE;
3536 break;
3537
3538 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3539 /* ??? unimplemented */
3540 break;
3541
3542 case ANEG_STATE_NEXT_PAGE_WAIT:
3543 /* ??? unimplemented */
3544 break;
3545
3546 default:
3547 ret = ANEG_FAILED;
3548 break;
855e1111 3549 }
1da177e4
LT		 3550
3551 return ret;
3552}
3553
5be73b47 3554static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3555{
3556 int res = 0;
3557 struct tg3_fiber_aneginfo aninfo;
3558 int status = ANEG_FAILED;
3559 unsigned int tick;
3560 u32 tmp;
3561
3562 tw32_f(MAC_TX_AUTO_NEG, 0);
3563
3564 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3565 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3566 udelay(40);
3567
3568 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3569 udelay(40);
3570
3571 memset(&aninfo, 0, sizeof(aninfo));
3572 aninfo.flags |= MR_AN_ENABLE;
3573 aninfo.state = ANEG_STATE_UNKNOWN;
3574 aninfo.cur_time = 0;
3575 tick = 0;
3576 while (++tick < 195000) {
3577 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3578 if (status == ANEG_DONE || status == ANEG_FAILED)
3579 break;
3580
3581 udelay(1);
3582 }
3583
3584 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3585 tw32_f(MAC_MODE, tp->mac_mode);
3586 udelay(40);
3587
5be73b47
MC		 3588 *txflags = aninfo.txconfig;
3589 *rxflags = aninfo.flags;
1da177e4
LT		 3590
3591 if (status == ANEG_DONE &&
3592 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3593 MR_LP_ADV_FULL_DUPLEX)))
3594 res = 1;
3595
3596 return res;
3597}
3598
3599static void tg3_init_bcm8002(struct tg3 *tp)
3600{
3601 u32 mac_status = tr32(MAC_STATUS);
3602 int i;
3603
3604 /* Reset when initting first time or we have a link. */
3605 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3606 !(mac_status & MAC_STATUS_PCS_SYNCED))
3607 return;
3608
3609 /* Set PLL lock range. */
3610 tg3_writephy(tp, 0x16, 0x8007);
3611
3612 /* SW reset */
3613 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3614
3615 /* Wait for reset to complete. */
3616 /* XXX schedule_timeout() ... */
3617 for (i = 0; i < 500; i++)
3618 udelay(10);
3619
3620 /* Config mode; select PMA/Ch 1 regs. */
3621 tg3_writephy(tp, 0x10, 0x8411);
3622
3623 /* Enable auto-lock and comdet, select txclk for tx. */
3624 tg3_writephy(tp, 0x11, 0x0a10);
3625
3626 tg3_writephy(tp, 0x18, 0x00a0);
3627 tg3_writephy(tp, 0x16, 0x41ff);
3628
3629 /* Assert and deassert POR. */
3630 tg3_writephy(tp, 0x13, 0x0400);
3631 udelay(40);
3632 tg3_writephy(tp, 0x13, 0x0000);
3633
3634 tg3_writephy(tp, 0x11, 0x0a50);
3635 udelay(40);
3636 tg3_writephy(tp, 0x11, 0x0a10);
3637
3638 /* Wait for signal to stabilize */
3639 /* XXX schedule_timeout() ... */
3640 for (i = 0; i < 15000; i++)
3641 udelay(10);
3642
3643 /* Deselect the channel register so we can read the PHYID
3644 * later.
3645 */
3646 tg3_writephy(tp, 0x10, 0x8011);
3647}
3648
3649static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3650{
82cd3d11 3651 u16 flowctrl;
1da177e4
LT		 3652 u32 sg_dig_ctrl, sg_dig_status;
3653 u32 serdes_cfg, expected_sg_dig_ctrl;
3654 int workaround, port_a;
3655 int current_link_up;
3656
3657 serdes_cfg = 0;
3658 expected_sg_dig_ctrl = 0;
3659 workaround = 0;
3660 port_a = 1;
3661 current_link_up = 0;
3662
3663 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3664 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3665 workaround = 1;
3666 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3667 port_a = 0;
3668
3669 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3670 /* preserve bits 20-23 for voltage regulator */
3671 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3672 }
3673
3674 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3675
3676 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3677 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3678 if (workaround) {
3679 u32 val = serdes_cfg;
3680
3681 if (port_a)
3682 val |= 0xc010000;
3683 else
3684 val |= 0x4010000;
3685 tw32_f(MAC_SERDES_CFG, val);
3686 }
c98f6e3b
MC		 3687
3688 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3689 }
3690 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3691 tg3_setup_flow_control(tp, 0, 0);
3692 current_link_up = 1;
3693 }
3694 goto out;
3695 }
3696
3697 /* Want auto-negotiation. */
c98f6e3b 3698 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3699
82cd3d11
MC		 3700 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3701 if (flowctrl & ADVERTISE_1000XPAUSE)
3702 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3703 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3704 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3705
3706 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3707 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3708 tp->serdes_counter &&
3709 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3710 MAC_STATUS_RCVD_CFG)) ==
3711 MAC_STATUS_PCS_SYNCED)) {
3712 tp->serdes_counter--;
3713 current_link_up = 1;
3714 goto out;
3715 }
3716restart_autoneg:
1da177e4
LT		 3717 if (workaround)
3718 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3719 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3720 udelay(5);
3721 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3722
3d3ebe74
MC		 3723 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3724 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3725 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3726 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3727 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3728 mac_status = tr32(MAC_STATUS);
3729
c98f6e3b 3730 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3731 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3732 u32 local_adv = 0, remote_adv = 0;
3733
3734 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3735 local_adv |= ADVERTISE_1000XPAUSE;
3736 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3737 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3738
c98f6e3b 3739 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3740 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3741 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3742 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3743
3744 tg3_setup_flow_control(tp, local_adv, remote_adv);
3745 current_link_up = 1;
3d3ebe74
MC		 3746 tp->serdes_counter = 0;
3747 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3748 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3749 if (tp->serdes_counter)
3750 tp->serdes_counter--;
1da177e4
LT		 3751 else {
3752 if (workaround) {
3753 u32 val = serdes_cfg;
3754
3755 if (port_a)
3756 val |= 0xc010000;
3757 else
3758 val |= 0x4010000;
3759
3760 tw32_f(MAC_SERDES_CFG, val);
3761 }
3762
c98f6e3b 3763 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3764 udelay(40);
3765
3766 /* Link parallel detection - link is up */
3767 /* only if we have PCS_SYNC and not */
3768 /* receiving config code words */
3769 mac_status = tr32(MAC_STATUS);
3770 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3771 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3772 tg3_setup_flow_control(tp, 0, 0);
3773 current_link_up = 1;
3d3ebe74
MC		 3774 tp->tg3_flags2 |=
3775 TG3_FLG2_PARALLEL_DETECT;
3776 tp->serdes_counter =
3777 SERDES_PARALLEL_DET_TIMEOUT;
3778 } else
3779 goto restart_autoneg;
1da177e4
LT		 3780 }
3781 }
3d3ebe74
MC		 3782 } else {
3783 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3784 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3785 }
3786
3787out:
3788 return current_link_up;
3789}
3790
3791static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3792{
3793 int current_link_up = 0;
3794
5cf64b8a 3795 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3796 goto out;
1da177e4
LT		 3797
3798 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3799 u32 txflags, rxflags;
1da177e4 3800 int i;
6aa20a22 3801
5be73b47
MC		 3802 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3803 u32 local_adv = 0, remote_adv = 0;
1da177e4 3804
5be73b47
MC		 3805 if (txflags & ANEG_CFG_PS1)
3806 local_adv |= ADVERTISE_1000XPAUSE;
3807 if (txflags & ANEG_CFG_PS2)
3808 local_adv |= ADVERTISE_1000XPSE_ASYM;
3809
3810 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE;
3812 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3813 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3814
3815 tg3_setup_flow_control(tp, local_adv, remote_adv);
3816
1da177e4
LT		 3817 current_link_up = 1;
3818 }
3819 for (i = 0; i < 30; i++) {
3820 udelay(20);
3821 tw32_f(MAC_STATUS,
3822 (MAC_STATUS_SYNC_CHANGED |
3823 MAC_STATUS_CFG_CHANGED));
3824 udelay(40);
3825 if ((tr32(MAC_STATUS) &
3826 (MAC_STATUS_SYNC_CHANGED |
3827 MAC_STATUS_CFG_CHANGED)) == 0)
3828 break;
3829 }
3830
3831 mac_status = tr32(MAC_STATUS);
3832 if (current_link_up == 0 &&
3833 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG))
3835 current_link_up = 1;
3836 } else {
5be73b47
MC		 3837 tg3_setup_flow_control(tp, 0, 0);
3838
1da177e4
LT		 3839 /* Forcing 1000FD link up. */
3840 current_link_up = 1;
1da177e4
LT		 3841
3842 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3843 udelay(40);
e8f3f6ca
MC		 3844
3845 tw32_f(MAC_MODE, tp->mac_mode);
3846 udelay(40);
1da177e4
LT		 3847 }
3848
3849out:
3850 return current_link_up;
3851}
3852
3853static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3854{
3855 u32 orig_pause_cfg;
3856 u16 orig_active_speed;
3857 u8 orig_active_duplex;
3858 u32 mac_status;
3859 int current_link_up;
3860 int i;
3861
8d018621 3862 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3863 orig_active_speed = tp->link_config.active_speed;
3864 orig_active_duplex = tp->link_config.active_duplex;
3865
3866 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3867 netif_carrier_ok(tp->dev) &&
3868 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3869 mac_status = tr32(MAC_STATUS);
3870 mac_status &= (MAC_STATUS_PCS_SYNCED |
3871 MAC_STATUS_SIGNAL_DET |
3872 MAC_STATUS_CFG_CHANGED |
3873 MAC_STATUS_RCVD_CFG);
3874 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3875 MAC_STATUS_SIGNAL_DET)) {
3876 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED));
3878 return 0;
3879 }
3880 }
3881
3882 tw32_f(MAC_TX_AUTO_NEG, 0);
3883
3884 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3885 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3886 tw32_f(MAC_MODE, tp->mac_mode);
3887 udelay(40);
3888
3889 if (tp->phy_id == PHY_ID_BCM8002)
3890 tg3_init_bcm8002(tp);
3891
3892 /* Enable link change event even when serdes polling. */
3893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3894 udelay(40);
3895
3896 current_link_up = 0;
3897 mac_status = tr32(MAC_STATUS);
3898
3899 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3900 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3901 else
3902 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3903
898a56f8 3904 tp->napi[0].hw_status->status =
1da177e4 3905 (SD_STATUS_UPDATED |
898a56f8 3906 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3907
3908 for (i = 0; i < 100; i++) {
3909 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3910 MAC_STATUS_CFG_CHANGED));
3911 udelay(5);
3912 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3913 MAC_STATUS_CFG_CHANGED |
3914 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3915 break;
3916 }
3917
3918 mac_status = tr32(MAC_STATUS);
3919 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3920 current_link_up = 0;
3d3ebe74
MC		 3921 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3922 tp->serdes_counter == 0) {
1da177e4
LT		 3923 tw32_f(MAC_MODE, (tp->mac_mode |
3924 MAC_MODE_SEND_CONFIGS));
3925 udelay(1);
3926 tw32_f(MAC_MODE, tp->mac_mode);
3927 }
3928 }
3929
3930 if (current_link_up == 1) {
3931 tp->link_config.active_speed = SPEED_1000;
3932 tp->link_config.active_duplex = DUPLEX_FULL;
3933 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3934 LED_CTRL_LNKLED_OVERRIDE |
3935 LED_CTRL_1000MBPS_ON));
3936 } else {
3937 tp->link_config.active_speed = SPEED_INVALID;
3938 tp->link_config.active_duplex = DUPLEX_INVALID;
3939 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3940 LED_CTRL_LNKLED_OVERRIDE |
3941 LED_CTRL_TRAFFIC_OVERRIDE));
3942 }
3943
3944 if (current_link_up != netif_carrier_ok(tp->dev)) {
3945 if (current_link_up)
3946 netif_carrier_on(tp->dev);
3947 else
3948 netif_carrier_off(tp->dev);
3949 tg3_link_report(tp);
3950 } else {
8d018621 3951 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3952 if (orig_pause_cfg != now_pause_cfg ||
3953 orig_active_speed != tp->link_config.active_speed ||
3954 orig_active_duplex != tp->link_config.active_duplex)
3955 tg3_link_report(tp);
3956 }
3957
3958 return 0;
3959}
3960
747e8f8b
MC		 3961static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3962{
3963 int current_link_up, err = 0;
3964 u32 bmsr, bmcr;
3965 u16 current_speed;
3966 u8 current_duplex;
ef167e27 3967 u32 local_adv, remote_adv;
747e8f8b
MC		 3968
3969 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3970 tw32_f(MAC_MODE, tp->mac_mode);
3971 udelay(40);
3972
3973 tw32(MAC_EVENT, 0);
3974
3975 tw32_f(MAC_STATUS,
3976 (MAC_STATUS_SYNC_CHANGED |
3977 MAC_STATUS_CFG_CHANGED |
3978 MAC_STATUS_MI_COMPLETION |
3979 MAC_STATUS_LNKSTATE_CHANGED));
3980 udelay(40);
3981
3982 if (force_reset)
3983 tg3_phy_reset(tp);
3984
3985 current_link_up = 0;
3986 current_speed = SPEED_INVALID;
3987 current_duplex = DUPLEX_INVALID;
3988
3989 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3990 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3992 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3993 bmsr |= BMSR_LSTATUS;
3994 else
3995 bmsr &= ~BMSR_LSTATUS;
3996 }
747e8f8b
MC		 3997
3998 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3999
4000 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4001 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4002 /* do nothing, just check for link up at the end */
4003 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4004 u32 adv, new_adv;
4005
4006 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4007 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4008 ADVERTISE_1000XPAUSE |
4009 ADVERTISE_1000XPSE_ASYM |
4010 ADVERTISE_SLCT);
4011
ba4d07a8 4012 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4013
4014 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4015 new_adv |= ADVERTISE_1000XHALF;
4016 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4017 new_adv |= ADVERTISE_1000XFULL;
4018
4019 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4020 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4021 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4022 tg3_writephy(tp, MII_BMCR, bmcr);
4023
4024 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4025 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4027
4028 return err;
4029 }
4030 } else {
4031 u32 new_bmcr;
4032
4033 bmcr &= ~BMCR_SPEED1000;
4034 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4035
4036 if (tp->link_config.duplex == DUPLEX_FULL)
4037 new_bmcr |= BMCR_FULLDPLX;
4038
4039 if (new_bmcr != bmcr) {
4040 /* BMCR_SPEED1000 is a reserved bit that needs
4041 * to be set on write.
4042 */
4043 new_bmcr |= BMCR_SPEED1000;
4044
4045 /* Force a linkdown */
4046 if (netif_carrier_ok(tp->dev)) {
4047 u32 adv;
4048
4049 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4050 adv &= ~(ADVERTISE_1000XFULL |
4051 ADVERTISE_1000XHALF |
4052 ADVERTISE_SLCT);
4053 tg3_writephy(tp, MII_ADVERTISE, adv);
4054 tg3_writephy(tp, MII_BMCR, bmcr |
4055 BMCR_ANRESTART |
4056 BMCR_ANENABLE);
4057 udelay(10);
4058 netif_carrier_off(tp->dev);
4059 }
4060 tg3_writephy(tp, MII_BMCR, new_bmcr);
4061 bmcr = new_bmcr;
4062 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4063 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4064 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4065 ASIC_REV_5714) {
4066 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4067 bmsr |= BMSR_LSTATUS;
4068 else
4069 bmsr &= ~BMSR_LSTATUS;
4070 }
747e8f8b
MC		 4071 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4072 }
4073 }
4074
4075 if (bmsr & BMSR_LSTATUS) {
4076 current_speed = SPEED_1000;
4077 current_link_up = 1;
4078 if (bmcr & BMCR_FULLDPLX)
4079 current_duplex = DUPLEX_FULL;
4080 else
4081 current_duplex = DUPLEX_HALF;
4082
ef167e27
MC		 4083 local_adv = 0;
4084 remote_adv = 0;
4085
747e8f8b 4086 if (bmcr & BMCR_ANENABLE) {
ef167e27 4087 u32 common;
747e8f8b
MC		 4088
4089 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4090 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4091 common = local_adv & remote_adv;
4092 if (common & (ADVERTISE_1000XHALF |
4093 ADVERTISE_1000XFULL)) {
4094 if (common & ADVERTISE_1000XFULL)
4095 current_duplex = DUPLEX_FULL;
4096 else
4097 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4098 }
4099 else
4100 current_link_up = 0;
4101 }
4102 }
4103
ef167e27
MC		 4104 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4105 tg3_setup_flow_control(tp, local_adv, remote_adv);
4106
747e8f8b
MC		 4107 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4108 if (tp->link_config.active_duplex == DUPLEX_HALF)
4109 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4110
4111 tw32_f(MAC_MODE, tp->mac_mode);
4112 udelay(40);
4113
4114 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4115
4116 tp->link_config.active_speed = current_speed;
4117 tp->link_config.active_duplex = current_duplex;
4118
4119 if (current_link_up != netif_carrier_ok(tp->dev)) {
4120 if (current_link_up)
4121 netif_carrier_on(tp->dev);
4122 else {
4123 netif_carrier_off(tp->dev);
4124 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4125 }
4126 tg3_link_report(tp);
4127 }
4128 return err;
4129}
4130
4131static void tg3_serdes_parallel_detect(struct tg3 *tp)
4132{
3d3ebe74 4133 if (tp->serdes_counter) {
747e8f8b 4134 /* Give autoneg time to complete. */
3d3ebe74 4135 tp->serdes_counter--;
747e8f8b
MC		 4136 return;
4137 }
4138 if (!netif_carrier_ok(tp->dev) &&
4139 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4140 u32 bmcr;
4141
4142 tg3_readphy(tp, MII_BMCR, &bmcr);
4143 if (bmcr & BMCR_ANENABLE) {
4144 u32 phy1, phy2;
4145
4146 /* Select shadow register 0x1f */
4147 tg3_writephy(tp, 0x1c, 0x7c00);
4148 tg3_readphy(tp, 0x1c, &phy1);
4149
4150 /* Select expansion interrupt status register */
4151 tg3_writephy(tp, 0x17, 0x0f01);
4152 tg3_readphy(tp, 0x15, &phy2);
4153 tg3_readphy(tp, 0x15, &phy2);
4154
4155 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4156 /* We have signal detect and not receiving
4157 * config code words, link is up by parallel
4158 * detection.
4159 */
4160
4161 bmcr &= ~BMCR_ANENABLE;
4162 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4163 tg3_writephy(tp, MII_BMCR, bmcr);
4164 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4165 }
4166 }
4167 }
4168 else if (netif_carrier_ok(tp->dev) &&
4169 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4170 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4171 u32 phy2;
4172
4173 /* Select expansion interrupt status register */
4174 tg3_writephy(tp, 0x17, 0x0f01);
4175 tg3_readphy(tp, 0x15, &phy2);
4176 if (phy2 & 0x20) {
4177 u32 bmcr;
4178
4179 /* Config code words received, turn on autoneg. */
4180 tg3_readphy(tp, MII_BMCR, &bmcr);
4181 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4182
4183 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4184
4185 }
4186 }
4187}
4188
1da177e4
LT		 4189static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4190{
4191 int err;
4192
4193 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4194 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4195 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4196 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4197 } else {
4198 err = tg3_setup_copper_phy(tp, force_reset);
4199 }
4200
bcb37f6c 4201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4202 u32 val, scale;
4203
4204 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4205 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4206 scale = 65;
4207 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4208 scale = 6;
4209 else
4210 scale = 12;
4211
4212 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4213 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4214 tw32(GRC_MISC_CFG, val);
4215 }
4216
1da177e4
LT		 4217 if (tp->link_config.active_speed == SPEED_1000 &&
4218 tp->link_config.active_duplex == DUPLEX_HALF)
4219 tw32(MAC_TX_LENGTHS,
4220 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4221 (6 << TX_LENGTHS_IPG_SHIFT) |
4222 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4223 else
4224 tw32(MAC_TX_LENGTHS,
4225 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4226 (6 << TX_LENGTHS_IPG_SHIFT) |
4227 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4228
4229 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4230 if (netif_carrier_ok(tp->dev)) {
4231 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4232 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4233 } else {
4234 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4235 }
4236 }
4237
8ed5d97e
MC		 4238 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4239 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4240 if (!netif_carrier_ok(tp->dev))
4241 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4242 tp->pwrmgmt_thresh;
4243 else
4244 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4245 tw32(PCIE_PWR_MGMT_THRESH, val);
4246 }
4247
1da177e4
LT		 4248 return err;
4249}
4250
df3e6548
MC		 4251/* This is called whenever we suspect that the system chipset is re-
4252 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4253 * is bogus tx completions. We try to recover by setting the
4254 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4255 * in the workqueue.
4256 */
4257static void tg3_tx_recover(struct tg3 *tp)
4258{
4259 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4260 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4261
4262 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4263 "mapped I/O cycles to the network device, attempting to "
4264 "recover. Please report the problem to the driver maintainer "
4265 "and include system chipset information.\n", tp->dev->name);
4266
4267 spin_lock(&tp->lock);
df3e6548 4268 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4269 spin_unlock(&tp->lock);
4270}
4271
f3f3f27e 4272static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4273{
4274 smp_mb();
f3f3f27e
MC		 4275 return tnapi->tx_pending -
4276 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4277}
4278
1da177e4
LT		 4279/* Tigon3 never reports partial packet sends. So we do not
4280 * need special logic to handle SKBs that have not had all
4281 * of their frags sent yet, like SunGEM does.
4282 */
17375d25 4283static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4284{
17375d25 4285 struct tg3 *tp = tnapi->tp;
898a56f8 4286 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4287 u32 sw_idx = tnapi->tx_cons;
1da177e4
LT		 4288
4289 while (sw_idx != hw_idx) {
f3f3f27e 4290 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4291 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4292 int i, tx_bug = 0;
4293
4294 if (unlikely(skb == NULL)) {
4295 tg3_tx_recover(tp);
4296 return;
4297 }
1da177e4 4298
90079ce8 4299 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4300
4301 ri->skb = NULL;
4302
4303 sw_idx = NEXT_TX(sw_idx);
4304
4305 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4306 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4307 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4308 tx_bug = 1;
1da177e4
LT		 4309 sw_idx = NEXT_TX(sw_idx);
4310 }
4311
f47c11ee 4312 dev_kfree_skb(skb);
df3e6548
MC		 4313
4314 if (unlikely(tx_bug)) {
4315 tg3_tx_recover(tp);
4316 return;
4317 }
1da177e4
LT		 4318 }
4319
f3f3f27e 4320 tnapi->tx_cons = sw_idx;
1da177e4 4321
1b2a7205
MC		 4322 /* Need to make the tx_cons update visible to tg3_start_xmit()
4323 * before checking for netif_queue_stopped(). Without the
4324 * memory barrier, there is a small possibility that tg3_start_xmit()
4325 * will miss it and cause the queue to be stopped forever.
4326 */
4327 smp_mb();
4328
4329 if (unlikely(netif_queue_stopped(tp->dev) &&
f3f3f27e 4330 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
1b2a7205 4331 netif_tx_lock(tp->dev);
51b91468 4332 if (netif_queue_stopped(tp->dev) &&
f3f3f27e 4333 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
51b91468 4334 netif_wake_queue(tp->dev);
1b2a7205 4335 netif_tx_unlock(tp->dev);
51b91468 4336 }
1da177e4
LT		 4337}
4338
4339/* Returns size of skb allocated or < 0 on error.
4340 *
4341 * We only need to fill in the address because the other members
4342 * of the RX descriptor are invariant, see tg3_init_rings.
4343 *
4344 * Note the purposeful assymetry of cpu vs. chip accesses. For
4345 * posting buffers we only dirty the first cache line of the RX
4346 * descriptor (containing the address). Whereas for the RX status
4347 * buffers the cpu only reads the last cacheline of the RX descriptor
4348 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4349 */
17375d25 4350static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4351 int src_idx, u32 dest_idx_unmasked)
4352{
17375d25 4353 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4354 struct tg3_rx_buffer_desc *desc;
4355 struct ring_info *map, *src_map;
4356 struct sk_buff *skb;
4357 dma_addr_t mapping;
4358 int skb_size, dest_idx;
21f581a5 4359 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4360
4361 src_map = NULL;
4362 switch (opaque_key) {
4363 case RXD_OPAQUE_RING_STD:
4364 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4365 desc = &tpr->rx_std[dest_idx];
4366 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4367 if (src_idx >= 0)
21f581a5 4368 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4369 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4370 break;
4371
4372 case RXD_OPAQUE_RING_JUMBO:
4373 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4374 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4375 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4376 if (src_idx >= 0)
21f581a5 4377 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4378 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4379 break;
4380
4381 default:
4382 return -EINVAL;
855e1111 4383 }
1da177e4
LT		 4384
4385 /* Do not overwrite any of the map or rp information
4386 * until we are sure we can commit to a new buffer.
4387 *
4388 * Callers depend upon this behavior and assume that
4389 * we leave everything unchanged if we fail.
4390 */
287be12e 4391 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4392 if (skb == NULL)
4393 return -ENOMEM;
4394
1da177e4
LT		 4395 skb_reserve(skb, tp->rx_offset);
4396
287be12e 4397 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4
LT		 4398 PCI_DMA_FROMDEVICE);
4399
4400 map->skb = skb;
4401 pci_unmap_addr_set(map, mapping, mapping);
4402
4403 if (src_map != NULL)
4404 src_map->skb = NULL;
4405
4406 desc->addr_hi = ((u64)mapping >> 32);
4407 desc->addr_lo = ((u64)mapping & 0xffffffff);
4408
4409 return skb_size;
4410}
4411
4412/* We only need to move over in the address because the other
4413 * members of the RX descriptor are invariant. See notes above
4414 * tg3_alloc_rx_skb for full details.
4415 */
17375d25 4416static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4417 int src_idx, u32 dest_idx_unmasked)
4418{
17375d25 4419 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4420 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4421 struct ring_info *src_map, *dest_map;
4422 int dest_idx;
21f581a5 4423 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4424
4425 switch (opaque_key) {
4426 case RXD_OPAQUE_RING_STD:
4427 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4428 dest_desc = &tpr->rx_std[dest_idx];
4429 dest_map = &tpr->rx_std_buffers[dest_idx];
4430 src_desc = &tpr->rx_std[src_idx];
4431 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4432 break;
4433
4434 case RXD_OPAQUE_RING_JUMBO:
4435 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4436 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4437 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4438 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4439 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4440 break;
4441
4442 default:
4443 return;
855e1111 4444 }
1da177e4
LT		 4445
4446 dest_map->skb = src_map->skb;
4447 pci_unmap_addr_set(dest_map, mapping,
4448 pci_unmap_addr(src_map, mapping));
4449 dest_desc->addr_hi = src_desc->addr_hi;
4450 dest_desc->addr_lo = src_desc->addr_lo;
4451
4452 src_map->skb = NULL;
4453}
4454
1da177e4
LT		 4455/* The RX ring scheme is composed of multiple rings which post fresh
4456 * buffers to the chip, and one special ring the chip uses to report
4457 * status back to the host.
4458 *
4459 * The special ring reports the status of received packets to the
4460 * host. The chip does not write into the original descriptor the
4461 * RX buffer was obtained from. The chip simply takes the original
4462 * descriptor as provided by the host, updates the status and length
4463 * field, then writes this into the next status ring entry.
4464 *
4465 * Each ring the host uses to post buffers to the chip is described
4466 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4467 * it is first placed into the on-chip ram. When the packet's length
4468 * is known, it walks down the TG3_BDINFO entries to select the ring.
4469 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4470 * which is within the range of the new packet's length is chosen.
4471 *
4472 * The "separate ring for rx status" scheme may sound queer, but it makes
4473 * sense from a cache coherency perspective. If only the host writes
4474 * to the buffer post rings, and only the chip writes to the rx status
4475 * rings, then cache lines never move beyond shared-modified state.
4476 * If both the host and chip were to write into the same ring, cache line
4477 * eviction could occur since both entities want it in an exclusive state.
4478 */
17375d25 4479static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4480{
17375d25 4481 struct tg3 *tp = tnapi->tp;
f92905de 4482 u32 work_mask, rx_std_posted = 0;
72334482 4483 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4484 u16 hw_idx;
1da177e4 4485 int received;
21f581a5 4486 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4487
898a56f8 4488 hw_idx = tnapi->hw_status->idx[0].rx_producer;
1da177e4
LT		 4489 /*
4490 * We need to order the read of hw_idx and the read of
4491 * the opaque cookie.
4492 */
4493 rmb();
1da177e4
LT		 4494 work_mask = 0;
4495 received = 0;
4496 while (sw_idx != hw_idx && budget > 0) {
72334482 4497 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4498 unsigned int len;
4499 struct sk_buff *skb;
4500 dma_addr_t dma_addr;
4501 u32 opaque_key, desc_idx, *post_ptr;
4502
4503 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4504 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4505 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4506 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4507 dma_addr = pci_unmap_addr(ri, mapping);
4508 skb = ri->skb;
4509 post_ptr = &tpr->rx_std_ptr;
f92905de 4510 rx_std_posted++;
1da177e4 4511 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4512 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4513 dma_addr = pci_unmap_addr(ri, mapping);
4514 skb = ri->skb;
4515 post_ptr = &tpr->rx_jmb_ptr;
4516 } else
1da177e4 4517 goto next_pkt_nopost;
1da177e4
LT		 4518
4519 work_mask |= opaque_key;
4520
4521 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4522 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4523 drop_it:
17375d25 4524 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4525 desc_idx, *post_ptr);
4526 drop_it_no_recycle:
4527 /* Other statistics kept track of by card. */
4528 tp->net_stats.rx_dropped++;
4529 goto next_pkt;
4530 }
4531
ad829268
MC		 4532 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4533 ETH_FCS_LEN;
1da177e4 4534
6aa20a22 4535 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4536 && tp->rx_offset == NET_IP_ALIGN
4537 /* rx_offset will likely not equal NET_IP_ALIGN
4538 * if this is a 5701 card running in PCI-X mode
4539 * [see tg3_get_invariants()]
4540 */
1da177e4
LT		 4541 ) {
4542 int skb_size;
4543
17375d25 4544 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4545 desc_idx, *post_ptr);
4546 if (skb_size < 0)
4547 goto drop_it;
4548
287be12e 4549 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4550 PCI_DMA_FROMDEVICE);
4551
4552 skb_put(skb, len);
4553 } else {
4554 struct sk_buff *copy_skb;
4555
17375d25 4556 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4557 desc_idx, *post_ptr);
4558
ad829268
MC		 4559 copy_skb = netdev_alloc_skb(tp->dev,
4560 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4561 if (copy_skb == NULL)
4562 goto drop_it_no_recycle;
4563
ad829268 4564 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4565 skb_put(copy_skb, len);
4566 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4567 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4568 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4569
4570 /* We'll reuse the original ring buffer. */
4571 skb = copy_skb;
4572 }
4573
4574 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4575 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4576 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4577 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4578 skb->ip_summed = CHECKSUM_UNNECESSARY;
4579 else
4580 skb->ip_summed = CHECKSUM_NONE;
4581
4582 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4583
4584 if (len > (tp->dev->mtu + ETH_HLEN) &&
4585 skb->protocol != htons(ETH_P_8021Q)) {
4586 dev_kfree_skb(skb);
4587 goto next_pkt;
4588 }
4589
1da177e4
LT		 4590#if TG3_VLAN_TAG_USED
4591 if (tp->vlgrp != NULL &&
4592 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4593 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4594 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4595 } else
4596#endif
17375d25 4597 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4598
1da177e4
LT		 4599 received++;
4600 budget--;
4601
4602next_pkt:
4603 (*post_ptr)++;
f92905de
MC		 4604
4605 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4606 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4607
4608 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4609 TG3_64BIT_REG_LOW, idx);
4610 work_mask &= ~RXD_OPAQUE_RING_STD;
4611 rx_std_posted = 0;
4612 }
1da177e4 4613next_pkt_nopost:
483ba50b 4614 sw_idx++;
6b31a515 4615 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4616
4617 /* Refresh hw_idx to see if there is new work */
4618 if (sw_idx == hw_idx) {
898a56f8 4619 hw_idx = tnapi->hw_status->idx[0].rx_producer;
52f6d697
MC		 4620 rmb();
4621 }
1da177e4
LT		 4622 }
4623
4624 /* ACK the status ring. */
72334482
MC		 4625 tnapi->rx_rcb_ptr = sw_idx;
4626 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4627
4628 /* Refill RX ring(s). */
4629 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4630 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4631 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4632 sw_idx);
4633 }
4634 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4635 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4636 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4637 sw_idx);
4638 }
4639 mmiowb();
4640
4641 return received;
4642}
4643
17375d25 4644static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4645{
17375d25 4646 struct tg3 *tp = tnapi->tp;
898a56f8 4647 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4648
1da177e4
LT		 4649 /* handle link change and other phy events */
4650 if (!(tp->tg3_flags &
4651 (TG3_FLAG_USE_LINKCHG_REG |
4652 TG3_FLAG_POLL_SERDES))) {
4653 if (sblk->status & SD_STATUS_LINK_CHG) {
4654 sblk->status = SD_STATUS_UPDATED |
4655 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4656 spin_lock(&tp->lock);
dd477003
MC		 4657 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4658 tw32_f(MAC_STATUS,
4659 (MAC_STATUS_SYNC_CHANGED |
4660 MAC_STATUS_CFG_CHANGED |
4661 MAC_STATUS_MI_COMPLETION |
4662 MAC_STATUS_LNKSTATE_CHANGED));
4663 udelay(40);
4664 } else
4665 tg3_setup_phy(tp, 0);
f47c11ee 4666 spin_unlock(&tp->lock);
1da177e4
LT		 4667 }
4668 }
4669
4670 /* run TX completion thread */
f3f3f27e 4671 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4672 tg3_tx(tnapi);
6f535763 4673 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4674 return work_done;
1da177e4
LT		 4675 }
4676
1da177e4
LT		 4677 /* run RX thread, within the bounds set by NAPI.
4678 * All RX "locking" is done by ensuring outside
bea3348e 4679 * code synchronizes with tg3->napi.poll()
1da177e4 4680 */
72334482 4681 if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
17375d25 4682 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4683
6f535763
DM		 4684 return work_done;
4685}
4686
4687static int tg3_poll(struct napi_struct *napi, int budget)
4688{
8ef0442f
MC		 4689 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4690 struct tg3 *tp = tnapi->tp;
6f535763 4691 int work_done = 0;
898a56f8 4692 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4693
4694 while (1) {
17375d25 4695 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4696
4697 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4698 goto tx_recovery;
4699
4700 if (unlikely(work_done >= budget))
4701 break;
4702
4fd7ab59 4703 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4704 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4705 * to tell the hw how much work has been processed,
4706 * so we must read it before checking for more work.
4707 */
898a56f8
MC		 4708 tnapi->last_tag = sblk->status_tag;
4709 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4710 rmb();
4711 } else
4712 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4713
17375d25 4714 if (likely(!tg3_has_work(tnapi))) {
288379f0 4715 napi_complete(napi);
17375d25 4716 tg3_int_reenable(tnapi);
6f535763
DM		 4717 break;
4718 }
1da177e4
LT		 4719 }
4720
bea3348e 4721 return work_done;
6f535763
DM		 4722
4723tx_recovery:
4fd7ab59 4724 /* work_done is guaranteed to be less than budget. */
288379f0 4725 napi_complete(napi);
6f535763 4726 schedule_work(&tp->reset_task);
4fd7ab59 4727 return work_done;
1da177e4
LT		 4728}
4729
f47c11ee
DM		 4730static void tg3_irq_quiesce(struct tg3 *tp)
4731{
4f125f42
MC		 4732 int i;
4733
f47c11ee
DM		 4734 BUG_ON(tp->irq_sync);
4735
4736 tp->irq_sync = 1;
4737 smp_mb();
4738
4f125f42
MC		 4739 for (i = 0; i < tp->irq_cnt; i++)
4740 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4741}
4742
4743static inline int tg3_irq_sync(struct tg3 *tp)
4744{
4745 return tp->irq_sync;
4746}
4747
4748/* Fully shutdown all tg3 driver activity elsewhere in the system.
4749 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4750 * with as well. Most of the time, this is not necessary except when
4751 * shutting down the device.
4752 */
4753static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4754{
46966545 4755 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4756 if (irq_sync)
4757 tg3_irq_quiesce(tp);
f47c11ee
DM		 4758}
4759
4760static inline void tg3_full_unlock(struct tg3 *tp)
4761{
f47c11ee
DM		 4762 spin_unlock_bh(&tp->lock);
4763}
4764
fcfa0a32
MC		 4765/* One-shot MSI handler - Chip automatically disables interrupt
4766 * after sending MSI so driver doesn't have to do it.
4767 */
7d12e780 4768static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4769{
09943a18
MC		 4770 struct tg3_napi *tnapi = dev_id;
4771 struct tg3 *tp = tnapi->tp;
fcfa0a32 4772
898a56f8 4773 prefetch(tnapi->hw_status);
72334482 4774 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4775
4776 if (likely(!tg3_irq_sync(tp)))
09943a18 4777 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4778
4779 return IRQ_HANDLED;
4780}
4781
88b06bc2
MC		 4782/* MSI ISR - No need to check for interrupt sharing and no need to
4783 * flush status block and interrupt mailbox. PCI ordering rules
4784 * guarantee that MSI will arrive after the status block.
4785 */
7d12e780 4786static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4787{
09943a18
MC		 4788 struct tg3_napi *tnapi = dev_id;
4789 struct tg3 *tp = tnapi->tp;
88b06bc2 4790
898a56f8 4791 prefetch(tnapi->hw_status);
72334482 4792 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4793 /*
fac9b83e 4794 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4795 * chip-internal interrupt pending events.
fac9b83e 4796 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4797 * NIC to stop sending us irqs, engaging "in-intr-handler"
4798 * event coalescing.
4799 */
4800 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4801 if (likely(!tg3_irq_sync(tp)))
09943a18 4802 napi_schedule(&tnapi->napi);
61487480 4803
88b06bc2
MC		 4804 return IRQ_RETVAL(1);
4805}
4806
7d12e780 4807static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4808{
09943a18
MC		 4809 struct tg3_napi *tnapi = dev_id;
4810 struct tg3 *tp = tnapi->tp;
898a56f8 4811 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4812 unsigned int handled = 1;
4813
1da177e4
LT		 4814 /* In INTx mode, it is possible for the interrupt to arrive at
4815 * the CPU before the status block posted prior to the interrupt.
4816 * Reading the PCI State register will confirm whether the
4817 * interrupt is ours and will flush the status block.
4818 */
d18edcb2
MC		 4819 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4820 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4821 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4822 handled = 0;
f47c11ee 4823 goto out;
fac9b83e 4824 }
d18edcb2
MC		 4825 }
4826
4827 /*
4828 * Writing any value to intr-mbox-0 clears PCI INTA# and
4829 * chip-internal interrupt pending events.
4830 * Writing non-zero to intr-mbox-0 additional tells the
4831 * NIC to stop sending us irqs, engaging "in-intr-handler"
4832 * event coalescing.
c04cb347
MC		 4833 *
4834 * Flush the mailbox to de-assert the IRQ immediately to prevent
4835 * spurious interrupts. The flush impacts performance but
4836 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4837 */
c04cb347 4838 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4839 if (tg3_irq_sync(tp))
4840 goto out;
4841 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4842 if (likely(tg3_has_work(tnapi))) {
72334482 4843 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4844 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4845 } else {
4846 /* No work, shared interrupt perhaps? re-enable
4847 * interrupts, and flush that PCI write
4848 */
4849 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4850 0x00000000);
fac9b83e 4851 }
f47c11ee 4852out:
fac9b83e
DM		 4853 return IRQ_RETVAL(handled);
4854}
4855
7d12e780 4856static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4857{
09943a18
MC		 4858 struct tg3_napi *tnapi = dev_id;
4859 struct tg3 *tp = tnapi->tp;
898a56f8 4860 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4861 unsigned int handled = 1;
4862
fac9b83e
DM		 4863 /* In INTx mode, it is possible for the interrupt to arrive at
4864 * the CPU before the status block posted prior to the interrupt.
4865 * Reading the PCI State register will confirm whether the
4866 * interrupt is ours and will flush the status block.
4867 */
898a56f8 4868 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4869 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4870 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4871 handled = 0;
f47c11ee 4872 goto out;
1da177e4 4873 }
d18edcb2
MC		 4874 }
4875
4876 /*
4877 * writing any value to intr-mbox-0 clears PCI INTA# and
4878 * chip-internal interrupt pending events.
4879 * writing non-zero to intr-mbox-0 additional tells the
4880 * NIC to stop sending us irqs, engaging "in-intr-handler"
4881 * event coalescing.
c04cb347
MC		 4882 *
4883 * Flush the mailbox to de-assert the IRQ immediately to prevent
4884 * spurious interrupts. The flush impacts performance but
4885 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4886 */
c04cb347 4887 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4888
4889 /*
4890 * In a shared interrupt configuration, sometimes other devices'
4891 * interrupts will scream. We record the current status tag here
4892 * so that the above check can report that the screaming interrupts
4893 * are unhandled. Eventually they will be silenced.
4894 */
898a56f8 4895 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4896
d18edcb2
MC		 4897 if (tg3_irq_sync(tp))
4898 goto out;
624f8e50 4899
72334482 4900 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4901
09943a18 4902 napi_schedule(&tnapi->napi);
624f8e50 4903
f47c11ee 4904out:
1da177e4
LT		 4905 return IRQ_RETVAL(handled);
4906}
4907
7938109f 4908/* ISR for interrupt test */
7d12e780 4909static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4910{
09943a18
MC		 4911 struct tg3_napi *tnapi = dev_id;
4912 struct tg3 *tp = tnapi->tp;
898a56f8 4913 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4914
f9804ddb
MC		 4915 if ((sblk->status & SD_STATUS_UPDATED) ||
4916 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4917 tg3_disable_ints(tp);
7938109f
MC		 4918 return IRQ_RETVAL(1);
4919 }
4920 return IRQ_RETVAL(0);
4921}
4922
8e7a22e3 4923static int tg3_init_hw(struct tg3 *, int);
944d980e 4924static int tg3_halt(struct tg3 *, int, int);
1da177e4 4925
b9ec6c1b
MC		 4926/* Restart hardware after configuration changes, self-test, etc.
4927 * Invoked with tp->lock held.
4928 */
4929static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4930 __releases(tp->lock)
4931 __acquires(tp->lock)
b9ec6c1b
MC		 4932{
4933 int err;
4934
4935 err = tg3_init_hw(tp, reset_phy);
4936 if (err) {
4937 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4938 "aborting.\n", tp->dev->name);
4939 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4940 tg3_full_unlock(tp);
4941 del_timer_sync(&tp->timer);
4942 tp->irq_sync = 0;
8ef0442f 4943 napi_enable(&tp->napi[0].napi);
b9ec6c1b
MC		 4944 dev_close(tp->dev);
4945 tg3_full_lock(tp, 0);
4946 }
4947 return err;
4948}
4949
1da177e4
LT		 4950#ifdef CONFIG_NET_POLL_CONTROLLER
4951static void tg3_poll_controller(struct net_device *dev)
4952{
4f125f42 4953 int i;
88b06bc2
MC		 4954 struct tg3 *tp = netdev_priv(dev);
4955
4f125f42
MC		 4956 for (i = 0; i < tp->irq_cnt; i++)
4957 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 4958}
4959#endif
4960
c4028958 4961static void tg3_reset_task(struct work_struct *work)
1da177e4 4962{
c4028958 4963 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4964 int err;
1da177e4
LT		 4965 unsigned int restart_timer;
4966
7faa006f 4967 tg3_full_lock(tp, 0);
7faa006f
MC		 4968
4969 if (!netif_running(tp->dev)) {
7faa006f
MC		 4970 tg3_full_unlock(tp);
4971 return;
4972 }
4973
4974 tg3_full_unlock(tp);
4975
b02fd9e3
MC		 4976 tg3_phy_stop(tp);
4977
1da177e4
LT		 4978 tg3_netif_stop(tp);
4979
f47c11ee 4980 tg3_full_lock(tp, 1);
1da177e4
LT		 4981
4982 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4983 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4984
df3e6548
MC		 4985 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4986 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4987 tp->write32_rx_mbox = tg3_write_flush_reg32;
4988 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4989 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4990 }
4991
944d980e 4992 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4993 err = tg3_init_hw(tp, 1);
4994 if (err)
b9ec6c1b 4995 goto out;
1da177e4
LT		 4996
4997 tg3_netif_start(tp);
4998
1da177e4
LT		 4999 if (restart_timer)
5000 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5001
b9ec6c1b 5002out:
7faa006f 5003 tg3_full_unlock(tp);
b02fd9e3
MC		 5004
5005 if (!err)
5006 tg3_phy_start(tp);
1da177e4
LT		 5007}
5008
b0408751
MC		 5009static void tg3_dump_short_state(struct tg3 *tp)
5010{
5011 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5012 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5013 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5014 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5015}
5016
1da177e4
LT		 5017static void tg3_tx_timeout(struct net_device *dev)
5018{
5019 struct tg3 *tp = netdev_priv(dev);
5020
b0408751 5021 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5022 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5023 dev->name);
b0408751
MC		 5024 tg3_dump_short_state(tp);
5025 }
1da177e4
LT		 5026
5027 schedule_work(&tp->reset_task);
5028}
5029
c58ec932
MC		 5030/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5031static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5032{
5033 u32 base = (u32) mapping & 0xffffffff;
5034
5035 return ((base > 0xffffdcc0) &&
5036 (base + len + 8 < base));
5037}
5038
72f2afb8
MC		 5039/* Test for DMA addresses > 40-bit */
5040static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5041 int len)
5042{
5043#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5044 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5045 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5046 return 0;
5047#else
5048 return 0;
5049#endif
5050}
5051
f3f3f27e 5052static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5053
72f2afb8
MC		 5054/* Workaround 4GB and 40-bit hardware DMA bugs. */
5055static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5056 u32 last_plus_one, u32 *start,
5057 u32 base_flags, u32 mss)
1da177e4 5058{
f3f3f27e 5059 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5060 struct sk_buff *new_skb;
c58ec932 5061 dma_addr_t new_addr = 0;
1da177e4 5062 u32 entry = *start;
c58ec932 5063 int i, ret = 0;
1da177e4 5064
41588ba1
MC		 5065 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5066 new_skb = skb_copy(skb, GFP_ATOMIC);
5067 else {
5068 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5069
5070 new_skb = skb_copy_expand(skb,
5071 skb_headroom(skb) + more_headroom,
5072 skb_tailroom(skb), GFP_ATOMIC);
5073 }
5074
1da177e4 5075 if (!new_skb) {
c58ec932
MC		 5076 ret = -1;
5077 } else {
5078 /* New SKB is guaranteed to be linear. */
5079 entry = *start;
90079ce8 5080 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5081 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5082
c58ec932
MC		 5083 /* Make sure new skb does not cross any 4G boundaries.
5084 * Drop the packet if it does.
5085 */
90079ce8 5086 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5087 if (!ret)
5088 skb_dma_unmap(&tp->pdev->dev, new_skb,
5089 DMA_TO_DEVICE);
c58ec932
MC		 5090 ret = -1;
5091 dev_kfree_skb(new_skb);
5092 new_skb = NULL;
5093 } else {
f3f3f27e 5094 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5095 base_flags, 1 | (mss << 1));
5096 *start = NEXT_TX(entry);
5097 }
1da177e4
LT		 5098 }
5099
1da177e4
LT		 5100 /* Now clean up the sw ring entries. */
5101 i = 0;
5102 while (entry != last_plus_one) {
f3f3f27e
MC		 5103 if (i == 0)
5104 tnapi->tx_buffers[entry].skb = new_skb;
5105 else
5106 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5107 entry = NEXT_TX(entry);
5108 i++;
5109 }
5110
90079ce8 5111 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5112 dev_kfree_skb(skb);
5113
c58ec932 5114 return ret;
1da177e4
LT		 5115}
5116
f3f3f27e 5117static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5118 dma_addr_t mapping, int len, u32 flags,
5119 u32 mss_and_is_end)
5120{
f3f3f27e 5121 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5122 int is_end = (mss_and_is_end & 0x1);
5123 u32 mss = (mss_and_is_end >> 1);
5124 u32 vlan_tag = 0;
5125
5126 if (is_end)
5127 flags |= TXD_FLAG_END;
5128 if (flags & TXD_FLAG_VLAN) {
5129 vlan_tag = flags >> 16;
5130 flags &= 0xffff;
5131 }
5132 vlan_tag |= (mss << TXD_MSS_SHIFT);
5133
5134 txd->addr_hi = ((u64) mapping >> 32);
5135 txd->addr_lo = ((u64) mapping & 0xffffffff);
5136 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5137 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5138}
5139
5a6f3074
MC		 5140/* hard_start_xmit for devices that don't have any bugs and
5141 * support TG3_FLG2_HW_TSO_2 only.
5142 */
61357325
SH		 5143static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5144 struct net_device *dev)
5a6f3074
MC		 5145{
5146 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5147 u32 len, entry, base_flags, mss;
90079ce8
DM		 5148 struct skb_shared_info *sp;
5149 dma_addr_t mapping;
f3f3f27e 5150 struct tg3_napi *tnapi = &tp->napi[0];
5a6f3074
MC		 5151
5152 len = skb_headlen(skb);
5153
00b70504 5154 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5155 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5156 * interrupt. Furthermore, IRQ processing runs lockless so we have
5157 * no IRQ context deadlocks to worry about either. Rejoice!
5158 */
f3f3f27e 5159 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5160 if (!netif_queue_stopped(dev)) {
5161 netif_stop_queue(dev);
5162
5163 /* This is a hard error, log it. */
5164 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5165 "queue awake!\n", dev->name);
5166 }
5a6f3074
MC		 5167 return NETDEV_TX_BUSY;
5168 }
5169
f3f3f27e 5170 entry = tnapi->tx_prod;
5a6f3074 5171 base_flags = 0;
5a6f3074 5172 mss = 0;
c13e3713 5173 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5174 int tcp_opt_len, ip_tcp_len;
5175
5176 if (skb_header_cloned(skb) &&
5177 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5178 dev_kfree_skb(skb);
5179 goto out_unlock;
5180 }
5181
b0026624
MC		 5182 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5183 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5184 else {
eddc9ec5
ACM		 5185 struct iphdr *iph = ip_hdr(skb);
5186
ab6a5bb6 5187 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5188 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5189
eddc9ec5
ACM		 5190 iph->check = 0;
5191 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5192 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5193 }
5a6f3074
MC		 5194
5195 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5196 TXD_FLAG_CPU_POST_DMA);
5197
aa8223c7 5198 tcp_hdr(skb)->check = 0;
5a6f3074 5199
5a6f3074 5200 }
84fa7933 5201 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5202 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5203#if TG3_VLAN_TAG_USED
5204 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5205 base_flags |= (TXD_FLAG_VLAN |
5206 (vlan_tx_tag_get(skb) << 16));
5207#endif
5208
90079ce8
DM		 5209 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5210 dev_kfree_skb(skb);
5211 goto out_unlock;
5212 }
5213
5214 sp = skb_shinfo(skb);
5215
042a53a9 5216 mapping = sp->dma_head;
5a6f3074 5217
f3f3f27e 5218 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5219
f3f3f27e 5220 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5221 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5222
5223 entry = NEXT_TX(entry);
5224
5225 /* Now loop through additional data fragments, and queue them. */
5226 if (skb_shinfo(skb)->nr_frags > 0) {
5227 unsigned int i, last;
5228
5229 last = skb_shinfo(skb)->nr_frags - 1;
5230 for (i = 0; i <= last; i++) {
5231 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5232
5233 len = frag->size;
042a53a9 5234 mapping = sp->dma_maps[i];
f3f3f27e 5235 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5236
f3f3f27e 5237 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5238 base_flags, (i == last) | (mss << 1));
5239
5240 entry = NEXT_TX(entry);
5241 }
5242 }
5243
5244 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5245 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5246
f3f3f27e
MC		 5247 tnapi->tx_prod = entry;
5248 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5249 netif_stop_queue(dev);
f3f3f27e 5250 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5a6f3074
MC		 5251 netif_wake_queue(tp->dev);
5252 }
5253
5254out_unlock:
cdd0db05 5255 mmiowb();
5a6f3074
MC		 5256
5257 return NETDEV_TX_OK;
5258}
5259
61357325
SH		 5260static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5261 struct net_device *);
52c0fd83
MC		 5262
5263/* Use GSO to workaround a rare TSO bug that may be triggered when the
5264 * TSO header is greater than 80 bytes.
5265 */
5266static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5267{
5268 struct sk_buff *segs, *nskb;
f3f3f27e 5269 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5270
5271 /* Estimate the number of fragments in the worst case */
f3f3f27e 5272 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5273 netif_stop_queue(tp->dev);
f3f3f27e 5274 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5275 return NETDEV_TX_BUSY;
5276
5277 netif_wake_queue(tp->dev);
52c0fd83
MC		 5278 }
5279
5280 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5281 if (IS_ERR(segs))
52c0fd83
MC		 5282 goto tg3_tso_bug_end;
5283
5284 do {
5285 nskb = segs;
5286 segs = segs->next;
5287 nskb->next = NULL;
5288 tg3_start_xmit_dma_bug(nskb, tp->dev);
5289 } while (segs);
5290
5291tg3_tso_bug_end:
5292 dev_kfree_skb(skb);
5293
5294 return NETDEV_TX_OK;
5295}
52c0fd83 5296
5a6f3074
MC		 5297/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5298 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5299 */
61357325
SH		 5300static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5301 struct net_device *dev)
1da177e4
LT		 5302{
5303 struct tg3 *tp = netdev_priv(dev);
1da177e4 5304 u32 len, entry, base_flags, mss;
90079ce8 5305 struct skb_shared_info *sp;
1da177e4 5306 int would_hit_hwbug;
90079ce8 5307 dma_addr_t mapping;
f3f3f27e 5308 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5309
5310 len = skb_headlen(skb);
5311
00b70504 5312 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5313 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5314 * interrupt. Furthermore, IRQ processing runs lockless so we have
5315 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5316 */
f3f3f27e 5317 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5318 if (!netif_queue_stopped(dev)) {
5319 netif_stop_queue(dev);
5320
5321 /* This is a hard error, log it. */
5322 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5323 "queue awake!\n", dev->name);
5324 }
1da177e4
LT		 5325 return NETDEV_TX_BUSY;
5326 }
5327
f3f3f27e 5328 entry = tnapi->tx_prod;
1da177e4 5329 base_flags = 0;
84fa7933 5330 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5331 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5332 mss = 0;
c13e3713 5333 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5334 struct iphdr *iph;
52c0fd83 5335 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5336
5337 if (skb_header_cloned(skb) &&
5338 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5339 dev_kfree_skb(skb);
5340 goto out_unlock;
5341 }
5342
ab6a5bb6 5343 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5344 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5345
52c0fd83
MC		 5346 hdr_len = ip_tcp_len + tcp_opt_len;
5347 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5348 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5349 return (tg3_tso_bug(tp, skb));
5350
1da177e4
LT		 5351 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5352 TXD_FLAG_CPU_POST_DMA);
5353
eddc9ec5
ACM		 5354 iph = ip_hdr(skb);
5355 iph->check = 0;
5356 iph->tot_len = htons(mss + hdr_len);
1da177e4 5357 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5358 tcp_hdr(skb)->check = 0;
1da177e4 5359 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5360 } else
5361 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5362 iph->daddr, 0,
5363 IPPROTO_TCP,
5364 0);
1da177e4
LT		 5365
5366 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5367 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5368 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5369 int tsflags;
5370
eddc9ec5 5371 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5372 mss |= (tsflags << 11);
5373 }
5374 } else {
eddc9ec5 5375 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5376 int tsflags;
5377
eddc9ec5 5378 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5379 base_flags |= tsflags << 12;
5380 }
5381 }
5382 }
1da177e4
LT		 5383#if TG3_VLAN_TAG_USED
5384 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5385 base_flags |= (TXD_FLAG_VLAN |
5386 (vlan_tx_tag_get(skb) << 16));
5387#endif
5388
90079ce8
DM		 5389 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5390 dev_kfree_skb(skb);
5391 goto out_unlock;
5392 }
5393
5394 sp = skb_shinfo(skb);
5395
042a53a9 5396 mapping = sp->dma_head;
1da177e4 5397
f3f3f27e 5398 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5399
5400 would_hit_hwbug = 0;
5401
41588ba1
MC		 5402 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5403 would_hit_hwbug = 1;
5404 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5405 would_hit_hwbug = 1;
1da177e4 5406
f3f3f27e 5407 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5408 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5409
5410 entry = NEXT_TX(entry);
5411
5412 /* Now loop through additional data fragments, and queue them. */
5413 if (skb_shinfo(skb)->nr_frags > 0) {
5414 unsigned int i, last;
5415
5416 last = skb_shinfo(skb)->nr_frags - 1;
5417 for (i = 0; i <= last; i++) {
5418 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5419
5420 len = frag->size;
042a53a9 5421 mapping = sp->dma_maps[i];
1da177e4 5422
f3f3f27e 5423 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5424
c58ec932
MC		 5425 if (tg3_4g_overflow_test(mapping, len))
5426 would_hit_hwbug = 1;
1da177e4 5427
72f2afb8
MC		 5428 if (tg3_40bit_overflow_test(tp, mapping, len))
5429 would_hit_hwbug = 1;
5430
1da177e4 5431 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5432 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5433 base_flags, (i == last)|(mss << 1));
5434 else
f3f3f27e 5435 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5436 base_flags, (i == last));
5437
5438 entry = NEXT_TX(entry);
5439 }
5440 }
5441
5442 if (would_hit_hwbug) {
5443 u32 last_plus_one = entry;
5444 u32 start;
1da177e4 5445
c58ec932
MC		 5446 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5447 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5448
5449 /* If the workaround fails due to memory/mapping
5450 * failure, silently drop this packet.
5451 */
72f2afb8 5452 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5453 &start, base_flags, mss))
1da177e4
LT		 5454 goto out_unlock;
5455
5456 entry = start;
5457 }
5458
5459 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5460 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5461
f3f3f27e
MC		 5462 tnapi->tx_prod = entry;
5463 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5464 netif_stop_queue(dev);
f3f3f27e 5465 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5466 netif_wake_queue(tp->dev);
5467 }
1da177e4
LT		 5468
5469out_unlock:
cdd0db05 5470 mmiowb();
1da177e4
LT		 5471
5472 return NETDEV_TX_OK;
5473}
5474
5475static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5476 int new_mtu)
5477{
5478 dev->mtu = new_mtu;
5479
ef7f5ec0 5480 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5481 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5482 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5483 ethtool_op_set_tso(dev, 0);
5484 }
5485 else
5486 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5487 } else {
a4e2b347 5488 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5489 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5490 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5491 }
1da177e4
LT		 5492}
5493
5494static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5495{
5496 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5497 int err;
1da177e4
LT		 5498
5499 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5500 return -EINVAL;
5501
5502 if (!netif_running(dev)) {
5503 /* We'll just catch it later when the
5504 * device is up'd.
5505 */
5506 tg3_set_mtu(dev, tp, new_mtu);
5507 return 0;
5508 }
5509
b02fd9e3
MC		 5510 tg3_phy_stop(tp);
5511
1da177e4 5512 tg3_netif_stop(tp);
f47c11ee
DM		 5513
5514 tg3_full_lock(tp, 1);
1da177e4 5515
944d980e 5516 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5517
5518 tg3_set_mtu(dev, tp, new_mtu);
5519
b9ec6c1b 5520 err = tg3_restart_hw(tp, 0);
1da177e4 5521
b9ec6c1b
MC		 5522 if (!err)
5523 tg3_netif_start(tp);
1da177e4 5524
f47c11ee 5525 tg3_full_unlock(tp);
1da177e4 5526
b02fd9e3
MC		 5527 if (!err)
5528 tg3_phy_start(tp);
5529
b9ec6c1b 5530 return err;
1da177e4
LT		 5531}
5532
21f581a5
MC		 5533static void tg3_rx_prodring_free(struct tg3 *tp,
5534 struct tg3_rx_prodring_set *tpr)
1da177e4 5535{
1da177e4 5536 int i;
f3f3f27e 5537 struct ring_info *rxp;
1da177e4
LT		 5538
5539 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5540 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5541
5542 if (rxp->skb == NULL)
5543 continue;
1da177e4 5544
1da177e4
LT		 5545 pci_unmap_single(tp->pdev,
5546 pci_unmap_addr(rxp, mapping),
cf7a7298 5547 tp->rx_pkt_map_sz,
1da177e4
LT		 5548 PCI_DMA_FROMDEVICE);
5549 dev_kfree_skb_any(rxp->skb);
5550 rxp->skb = NULL;
5551 }
5552
cf7a7298
MC		 5553 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5554 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5555 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5556
cf7a7298
MC		 5557 if (rxp->skb == NULL)
5558 continue;
1da177e4 5559
cf7a7298
MC		 5560 pci_unmap_single(tp->pdev,
5561 pci_unmap_addr(rxp, mapping),
5562 TG3_RX_JMB_MAP_SZ,
5563 PCI_DMA_FROMDEVICE);
5564 dev_kfree_skb_any(rxp->skb);
5565 rxp->skb = NULL;
1da177e4 5566 }
1da177e4
LT		 5567 }
5568}
5569
5570/* Initialize tx/rx rings for packet processing.
5571 *
5572 * The chip has been shut down and the driver detached from
5573 * the networking, so no interrupts or new tx packets will
5574 * end up in the driver. tp->{tx,}lock are held and thus
5575 * we may not sleep.
5576 */
21f581a5
MC		 5577static int tg3_rx_prodring_alloc(struct tg3 *tp,
5578 struct tg3_rx_prodring_set *tpr)
1da177e4 5579{
287be12e 5580 u32 i, rx_pkt_dma_sz;
17375d25 5581 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5582
1da177e4 5583 /* Zero out all descriptors. */
21f581a5 5584 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5585
287be12e 5586 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5587 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5588 tp->dev->mtu > ETH_DATA_LEN)
5589 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5590 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5591
1da177e4
LT		 5592 /* Initialize invariants of the rings, we only set this
5593 * stuff once. This works because the card does not
5594 * write into the rx buffer posting rings.
5595 */
5596 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5597 struct tg3_rx_buffer_desc *rxd;
5598
21f581a5 5599 rxd = &tpr->rx_std[i];
287be12e 5600 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5601 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5602 rxd->opaque = (RXD_OPAQUE_RING_STD |
5603 (i << RXD_OPAQUE_INDEX_SHIFT));
5604 }
5605
1da177e4
LT		 5606 /* Now allocate fresh SKBs for each rx ring. */
5607 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5608 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5609 printk(KERN_WARNING PFX
5610 "%s: Using a smaller RX standard ring, "
5611 "only %d out of %d buffers were allocated "
5612 "successfully.\n",
5613 tp->dev->name, i, tp->rx_pending);
5614 if (i == 0)
cf7a7298 5615 goto initfail;
32d8c572 5616 tp->rx_pending = i;
1da177e4 5617 break;
32d8c572 5618 }
1da177e4
LT		 5619 }
5620
cf7a7298
MC		 5621 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5622 goto done;
5623
21f581a5 5624 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5625
0f893dc6 5626 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5627 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5628 struct tg3_rx_buffer_desc *rxd;
5629
79ed5ac7 5630 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5631 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5632 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5633 RXD_FLAG_JUMBO;
5634 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5635 (i << RXD_OPAQUE_INDEX_SHIFT));
5636 }
5637
1da177e4 5638 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5639 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5640 -1, i) < 0) {
5641 printk(KERN_WARNING PFX
5642 "%s: Using a smaller RX jumbo ring, "
5643 "only %d out of %d buffers were "
5644 "allocated successfully.\n",
5645 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5646 if (i == 0)
5647 goto initfail;
32d8c572 5648 tp->rx_jumbo_pending = i;
1da177e4 5649 break;
32d8c572 5650 }
1da177e4
LT		 5651 }
5652 }
cf7a7298
MC		 5653
5654done:
32d8c572 5655 return 0;
cf7a7298
MC		 5656
5657initfail:
21f581a5 5658 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5659 return -ENOMEM;
1da177e4
LT		 5660}
5661
21f581a5
MC		 5662static void tg3_rx_prodring_fini(struct tg3 *tp,
5663 struct tg3_rx_prodring_set *tpr)
1da177e4 5664{
21f581a5
MC		 5665 kfree(tpr->rx_std_buffers);
5666 tpr->rx_std_buffers = NULL;
5667 kfree(tpr->rx_jmb_buffers);
5668 tpr->rx_jmb_buffers = NULL;
5669 if (tpr->rx_std) {
1da177e4 5670 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5671 tpr->rx_std, tpr->rx_std_mapping);
5672 tpr->rx_std = NULL;
1da177e4 5673 }
21f581a5 5674 if (tpr->rx_jmb) {
1da177e4 5675 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5676 tpr->rx_jmb, tpr->rx_jmb_mapping);
5677 tpr->rx_jmb = NULL;
1da177e4 5678 }
cf7a7298
MC		 5679}
5680
21f581a5
MC		 5681static int tg3_rx_prodring_init(struct tg3 *tp,
5682 struct tg3_rx_prodring_set *tpr)
cf7a7298 5683{
21f581a5
MC		 5684 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5685 TG3_RX_RING_SIZE, GFP_KERNEL);
5686 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5687 return -ENOMEM;
5688
21f581a5
MC		 5689 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5690 &tpr->rx_std_mapping);
5691 if (!tpr->rx_std)
cf7a7298
MC		 5692 goto err_out;
5693
5694 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5695 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5696 TG3_RX_JUMBO_RING_SIZE,
5697 GFP_KERNEL);
5698 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5699 goto err_out;
5700
21f581a5
MC		 5701 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5702 TG3_RX_JUMBO_RING_BYTES,
5703 &tpr->rx_jmb_mapping);
5704 if (!tpr->rx_jmb)
cf7a7298
MC		 5705 goto err_out;
5706 }
5707
5708 return 0;
5709
5710err_out:
21f581a5 5711 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5712 return -ENOMEM;
5713}
5714
5715/* Free up pending packets in all rx/tx rings.
5716 *
5717 * The chip has been shut down and the driver detached from
5718 * the networking, so no interrupts or new tx packets will
5719 * end up in the driver. tp->{tx,}lock is not held and we are not
5720 * in an interrupt context and thus may sleep.
5721 */
5722static void tg3_free_rings(struct tg3 *tp)
5723{
f3f3f27e 5724 struct tg3_napi *tnapi = &tp->napi[0];
cf7a7298
MC		 5725 int i;
5726
5727 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5728 struct tx_ring_info *txp;
5729 struct sk_buff *skb;
5730
f3f3f27e 5731 txp = &tnapi->tx_buffers[i];
cf7a7298
MC		 5732 skb = txp->skb;
5733
5734 if (skb == NULL) {
5735 i++;
5736 continue;
5737 }
5738
5739 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5740
5741 txp->skb = NULL;
5742
5743 i += skb_shinfo(skb)->nr_frags + 1;
5744
5745 dev_kfree_skb_any(skb);
5746 }
5747
21f581a5 5748 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5749}
5750
5751/* Initialize tx/rx rings for packet processing.
5752 *
5753 * The chip has been shut down and the driver detached from
5754 * the networking, so no interrupts or new tx packets will
5755 * end up in the driver. tp->{tx,}lock are held and thus
5756 * we may not sleep.
5757 */
5758static int tg3_init_rings(struct tg3 *tp)
5759{
72334482
MC		 5760 struct tg3_napi *tnapi = &tp->napi[0];
5761
cf7a7298
MC		 5762 /* Free up all the SKBs. */
5763 tg3_free_rings(tp);
5764
5765 /* Zero out all descriptors. */
f3f3f27e 5766 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
cf7a7298 5767
72334482
MC		 5768 tnapi->rx_rcb_ptr = 0;
5769 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5770
21f581a5 5771 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5772}
5773
5774/*
5775 * Must not be invoked with interrupt sources disabled and
5776 * the hardware shutdown down.
5777 */
5778static void tg3_free_consistent(struct tg3 *tp)
5779{
898a56f8
MC		 5780 struct tg3_napi *tnapi = &tp->napi[0];
5781
f3f3f27e
MC		 5782 kfree(tnapi->tx_buffers);
5783 tnapi->tx_buffers = NULL;
5784 if (tnapi->tx_ring) {
1da177e4 5785 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
f3f3f27e
MC		 5786 tnapi->tx_ring, tnapi->tx_desc_mapping);
5787 tnapi->tx_ring = NULL;
1da177e4 5788 }
72334482
MC		 5789 if (tnapi->rx_rcb) {
5790 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5791 tnapi->rx_rcb, tnapi->rx_rcb_mapping);
5792 tnapi->rx_rcb = NULL;
5793 }
898a56f8 5794 if (tnapi->hw_status) {
1da177e4 5795 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
898a56f8
MC		 5796 tnapi->hw_status,
5797 tnapi->status_mapping);
5798 tnapi->hw_status = NULL;
1da177e4
LT		 5799 }
5800 if (tp->hw_stats) {
5801 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5802 tp->hw_stats, tp->stats_mapping);
5803 tp->hw_stats = NULL;
5804 }
21f581a5 5805 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5806}
5807
5808/*
5809 * Must not be invoked with interrupt sources disabled and
5810 * the hardware shutdown down. Can sleep.
5811 */
5812static int tg3_alloc_consistent(struct tg3 *tp)
5813{
898a56f8
MC		 5814 struct tg3_napi *tnapi = &tp->napi[0];
5815
21f581a5 5816 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5817 return -ENOMEM;
5818
f3f3f27e
MC		 5819 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5820 TG3_TX_RING_SIZE, GFP_KERNEL);
5821 if (!tnapi->tx_buffers)
1da177e4
LT		 5822 goto err_out;
5823
f3f3f27e
MC		 5824 tnapi->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5825 &tnapi->tx_desc_mapping);
5826 if (!tnapi->tx_ring)
1da177e4
LT		 5827 goto err_out;
5828
898a56f8
MC		 5829 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5830 TG3_HW_STATUS_SIZE,
5831 &tnapi->status_mapping);
5832 if (!tnapi->hw_status)
1da177e4
LT		 5833 goto err_out;
5834
898a56f8
MC		 5835 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5836
72334482
MC		 5837 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5838 TG3_RX_RCB_RING_BYTES(tp),
5839 &tnapi->rx_rcb_mapping);
5840 if (!tnapi->rx_rcb)
5841 goto err_out;
5842
5843 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5844
1da177e4
LT		 5845 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5846 sizeof(struct tg3_hw_stats),
5847 &tp->stats_mapping);
5848 if (!tp->hw_stats)
5849 goto err_out;
5850
1da177e4
LT		 5851 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5852
5853 return 0;
5854
5855err_out:
5856 tg3_free_consistent(tp);
5857 return -ENOMEM;
5858}
5859
5860#define MAX_WAIT_CNT 1000
5861
5862/* To stop a block, clear the enable bit and poll till it
5863 * clears. tp->lock is held.
5864 */
b3b7d6be 5865static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5866{
5867 unsigned int i;
5868 u32 val;
5869
5870 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5871 switch (ofs) {
5872 case RCVLSC_MODE:
5873 case DMAC_MODE:
5874 case MBFREE_MODE:
5875 case BUFMGR_MODE:
5876 case MEMARB_MODE:
5877 /* We can't enable/disable these bits of the
5878 * 5705/5750, just say success.
5879 */
5880 return 0;
5881
5882 default:
5883 break;
855e1111 5884 }
1da177e4
LT		 5885 }
5886
5887 val = tr32(ofs);
5888 val &= ~enable_bit;
5889 tw32_f(ofs, val);
5890
5891 for (i = 0; i < MAX_WAIT_CNT; i++) {
5892 udelay(100);
5893 val = tr32(ofs);
5894 if ((val & enable_bit) == 0)
5895 break;
5896 }
5897
b3b7d6be 5898 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5899 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5900 "ofs=%lx enable_bit=%x\n",
5901 ofs, enable_bit);
5902 return -ENODEV;
5903 }
5904
5905 return 0;
5906}
5907
5908/* tp->lock is held. */
b3b7d6be 5909static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5910{
5911 int i, err;
898a56f8 5912 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5913
5914 tg3_disable_ints(tp);
5915
5916 tp->rx_mode &= ~RX_MODE_ENABLE;
5917 tw32_f(MAC_RX_MODE, tp->rx_mode);
5918 udelay(10);
5919
b3b7d6be
DM		 5920 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5921 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5922 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5923 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5924 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5925 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5926
5927 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5928 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5929 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5930 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5931 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5932 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5933 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5934
5935 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5936 tw32_f(MAC_MODE, tp->mac_mode);
5937 udelay(40);
5938
5939 tp->tx_mode &= ~TX_MODE_ENABLE;
5940 tw32_f(MAC_TX_MODE, tp->tx_mode);
5941
5942 for (i = 0; i < MAX_WAIT_CNT; i++) {
5943 udelay(100);
5944 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5945 break;
5946 }
5947 if (i >= MAX_WAIT_CNT) {
5948 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5949 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5950 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5951 err |= -ENODEV;
1da177e4
LT		 5952 }
5953
e6de8ad1 5954 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5955 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5956 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5957
5958 tw32(FTQ_RESET, 0xffffffff);
5959 tw32(FTQ_RESET, 0x00000000);
5960
b3b7d6be
DM		 5961 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5962 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 5963
898a56f8
MC		 5964 if (tnapi->hw_status)
5965 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
1da177e4
LT		 5966 if (tp->hw_stats)
5967 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5968
1da177e4
LT		 5969 return err;
5970}
5971
0d3031d9
MC		 5972static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5973{
5974 int i;
5975 u32 apedata;
5976
5977 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5978 if (apedata != APE_SEG_SIG_MAGIC)
5979 return;
5980
5981 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5982 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5983 return;
5984
5985 /* Wait for up to 1 millisecond for APE to service previous event. */
5986 for (i = 0; i < 10; i++) {
5987 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5988 return;
5989
5990 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5991
5992 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5993 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5994 event | APE_EVENT_STATUS_EVENT_PENDING);
5995
5996 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5997
5998 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5999 break;
6000
6001 udelay(100);
6002 }
6003
6004 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6005 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6006}
6007
6008static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6009{
6010 u32 event;
6011 u32 apedata;
6012
6013 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6014 return;
6015
6016 switch (kind) {
6017 case RESET_KIND_INIT:
6018 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6019 APE_HOST_SEG_SIG_MAGIC);
6020 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6021 APE_HOST_SEG_LEN_MAGIC);
6022 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6023 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6024 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6025 APE_HOST_DRIVER_ID_MAGIC);
6026 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6027 APE_HOST_BEHAV_NO_PHYLOCK);
6028
6029 event = APE_EVENT_STATUS_STATE_START;
6030 break;
6031 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6032 /* With the interface we are currently using,
6033 * APE does not track driver state. Wiping
6034 * out the HOST SEGMENT SIGNATURE forces
6035 * the APE to assume OS absent status.
6036 */
6037 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6038
0d3031d9
MC		 6039 event = APE_EVENT_STATUS_STATE_UNLOAD;
6040 break;
6041 case RESET_KIND_SUSPEND:
6042 event = APE_EVENT_STATUS_STATE_SUSPEND;
6043 break;
6044 default:
6045 return;
6046 }
6047
6048 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6049
6050 tg3_ape_send_event(tp, event);
6051}
6052
1da177e4
LT		 6053/* tp->lock is held. */
6054static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6055{
f49639e6
DM		 6056 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6057 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6058
6059 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6060 switch (kind) {
6061 case RESET_KIND_INIT:
6062 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6063 DRV_STATE_START);
6064 break;
6065
6066 case RESET_KIND_SHUTDOWN:
6067 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6068 DRV_STATE_UNLOAD);
6069 break;
6070
6071 case RESET_KIND_SUSPEND:
6072 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6073 DRV_STATE_SUSPEND);
6074 break;
6075
6076 default:
6077 break;
855e1111 6078 }
1da177e4 6079 }
0d3031d9
MC		 6080
6081 if (kind == RESET_KIND_INIT ||
6082 kind == RESET_KIND_SUSPEND)
6083 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6084}
6085
6086/* tp->lock is held. */
6087static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6088{
6089 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6090 switch (kind) {
6091 case RESET_KIND_INIT:
6092 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6093 DRV_STATE_START_DONE);
6094 break;
6095
6096 case RESET_KIND_SHUTDOWN:
6097 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6098 DRV_STATE_UNLOAD_DONE);
6099 break;
6100
6101 default:
6102 break;
855e1111 6103 }
1da177e4 6104 }
0d3031d9
MC		 6105
6106 if (kind == RESET_KIND_SHUTDOWN)
6107 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6108}
6109
6110/* tp->lock is held. */
6111static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6112{
6113 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6114 switch (kind) {
6115 case RESET_KIND_INIT:
6116 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6117 DRV_STATE_START);
6118 break;
6119
6120 case RESET_KIND_SHUTDOWN:
6121 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6122 DRV_STATE_UNLOAD);
6123 break;
6124
6125 case RESET_KIND_SUSPEND:
6126 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6127 DRV_STATE_SUSPEND);
6128 break;
6129
6130 default:
6131 break;
855e1111 6132 }
1da177e4
LT		 6133 }
6134}
6135
7a6f4369
MC		 6136static int tg3_poll_fw(struct tg3 *tp)
6137{
6138 int i;
6139 u32 val;
6140
b5d3772c 6141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6142 /* Wait up to 20ms for init done. */
6143 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6144 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6145 return 0;
0ccead18 6146 udelay(100);
b5d3772c
MC		 6147 }
6148 return -ENODEV;
6149 }
6150
7a6f4369
MC		 6151 /* Wait for firmware initialization to complete. */
6152 for (i = 0; i < 100000; i++) {
6153 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6154 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6155 break;
6156 udelay(10);
6157 }
6158
6159 /* Chip might not be fitted with firmware. Some Sun onboard
6160 * parts are configured like that. So don't signal the timeout
6161 * of the above loop as an error, but do report the lack of
6162 * running firmware once.
6163 */
6164 if (i >= 100000 &&
6165 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6166 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6167
6168 printk(KERN_INFO PFX "%s: No firmware running.\n",
6169 tp->dev->name);
6170 }
6171
6172 return 0;
6173}
6174
ee6a99b5
MC		 6175/* Save PCI command register before chip reset */
6176static void tg3_save_pci_state(struct tg3 *tp)
6177{
8a6eac90 6178 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6179}
6180
6181/* Restore PCI state after chip reset */
6182static void tg3_restore_pci_state(struct tg3 *tp)
6183{
6184 u32 val;
6185
6186 /* Re-enable indirect register accesses. */
6187 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6188 tp->misc_host_ctrl);
6189
6190 /* Set MAX PCI retry to zero. */
6191 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6192 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6193 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6194 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6195 /* Allow reads and writes to the APE register and memory space. */
6196 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6197 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6198 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6199 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6200
8a6eac90 6201 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6202
fcb389df
MC		 6203 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6204 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6205 pcie_set_readrq(tp->pdev, 4096);
6206 else {
6207 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6208 tp->pci_cacheline_sz);
6209 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6210 tp->pci_lat_timer);
6211 }
114342f2 6212 }
5f5c51e3 6213
ee6a99b5 6214 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6215 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6216 u16 pcix_cmd;
6217
6218 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6219 &pcix_cmd);
6220 pcix_cmd &= ~PCI_X_CMD_ERO;
6221 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6222 pcix_cmd);
6223 }
ee6a99b5
MC		 6224
6225 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6226
6227 /* Chip reset on 5780 will reset MSI enable bit,
6228 * so need to restore it.
6229 */
6230 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6231 u16 ctrl;
6232
6233 pci_read_config_word(tp->pdev,
6234 tp->msi_cap + PCI_MSI_FLAGS,
6235 &ctrl);
6236 pci_write_config_word(tp->pdev,
6237 tp->msi_cap + PCI_MSI_FLAGS,
6238 ctrl | PCI_MSI_FLAGS_ENABLE);
6239 val = tr32(MSGINT_MODE);
6240 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6241 }
6242 }
6243}
6244
1da177e4
LT		 6245static void tg3_stop_fw(struct tg3 *);
6246
6247/* tp->lock is held. */
6248static int tg3_chip_reset(struct tg3 *tp)
6249{
6250 u32 val;
1ee582d8 6251 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6252 int i, err;
1da177e4 6253
f49639e6
DM		 6254 tg3_nvram_lock(tp);
6255
158d7abd
MC		 6256 tg3_mdio_stop(tp);
6257
77b483f1
MC		 6258 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6259
f49639e6
DM		 6260 /* No matching tg3_nvram_unlock() after this because
6261 * chip reset below will undo the nvram lock.
6262 */
6263 tp->nvram_lock_cnt = 0;
1da177e4 6264
ee6a99b5
MC		 6265 /* GRC_MISC_CFG core clock reset will clear the memory
6266 * enable bit in PCI register 4 and the MSI enable bit
6267 * on some chips, so we save relevant registers here.
6268 */
6269 tg3_save_pci_state(tp);
6270
d9ab5ad1 6271 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6272 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6273 tw32(GRC_FASTBOOT_PC, 0);
6274
1da177e4
LT		 6275 /*
6276 * We must avoid the readl() that normally takes place.
6277 * It locks machines, causes machine checks, and other
6278 * fun things. So, temporarily disable the 5701
6279 * hardware workaround, while we do the reset.
6280 */
1ee582d8
MC		 6281 write_op = tp->write32;
6282 if (write_op == tg3_write_flush_reg32)
6283 tp->write32 = tg3_write32;
1da177e4 6284
d18edcb2
MC		 6285 /* Prevent the irq handler from reading or writing PCI registers
6286 * during chip reset when the memory enable bit in the PCI command
6287 * register may be cleared. The chip does not generate interrupt
6288 * at this time, but the irq handler may still be called due to irq
6289 * sharing or irqpoll.
6290 */
6291 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
898a56f8
MC		 6292 if (tp->napi[0].hw_status) {
6293 tp->napi[0].hw_status->status = 0;
6294 tp->napi[0].hw_status->status_tag = 0;
b8fa2f3a 6295 }
898a56f8
MC		 6296 tp->napi[0].last_tag = 0;
6297 tp->napi[0].last_irq_tag = 0;
d18edcb2 6298 smp_mb();
4f125f42
MC		 6299
6300 for (i = 0; i < tp->irq_cnt; i++)
6301 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6302
255ca311
MC		 6303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6304 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6305 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6306 }
6307
1da177e4
LT		 6308 /* do the reset */
6309 val = GRC_MISC_CFG_CORECLK_RESET;
6310
6311 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6312 if (tr32(0x7e2c) == 0x60) {
6313 tw32(0x7e2c, 0x20);
6314 }
6315 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6316 tw32(GRC_MISC_CFG, (1 << 29));
6317 val |= (1 << 29);
6318 }
6319 }
6320
b5d3772c
MC		 6321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6322 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6323 tw32(GRC_VCPU_EXT_CTRL,
6324 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6325 }
6326
1da177e4
LT		 6327 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6328 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6329 tw32(GRC_MISC_CFG, val);
6330
1ee582d8
MC		 6331 /* restore 5701 hardware bug workaround write method */
6332 tp->write32 = write_op;
1da177e4
LT		 6333
6334 /* Unfortunately, we have to delay before the PCI read back.
6335 * Some 575X chips even will not respond to a PCI cfg access
6336 * when the reset command is given to the chip.
6337 *
6338 * How do these hardware designers expect things to work
6339 * properly if the PCI write is posted for a long period
6340 * of time? It is always necessary to have some method by
6341 * which a register read back can occur to push the write
6342 * out which does the reset.
6343 *
6344 * For most tg3 variants the trick below was working.
6345 * Ho hum...
6346 */
6347 udelay(120);
6348
6349 /* Flush PCI posted writes. The normal MMIO registers
6350 * are inaccessible at this time so this is the only
6351 * way to make this reliably (actually, this is no longer
6352 * the case, see above). I tried to use indirect
6353 * register read/write but this upset some 5701 variants.
6354 */
6355 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6356
6357 udelay(120);
6358
5e7dfd0f 6359 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6360 u16 val16;
6361
1da177e4
LT		 6362 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6363 int i;
6364 u32 cfg_val;
6365
6366 /* Wait for link training to complete. */
6367 for (i = 0; i < 5000; i++)
6368 udelay(100);
6369
6370 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6371 pci_write_config_dword(tp->pdev, 0xc4,
6372 cfg_val | (1 << 15));
6373 }
5e7dfd0f 6374
e7126997
MC		 6375 /* Clear the "no snoop" and "relaxed ordering" bits. */
6376 pci_read_config_word(tp->pdev,
6377 tp->pcie_cap + PCI_EXP_DEVCTL,
6378 &val16);
6379 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6380 PCI_EXP_DEVCTL_NOSNOOP_EN);
6381 /*
6382 * Older PCIe devices only support the 128 byte
6383 * MPS setting. Enforce the restriction.
5e7dfd0f 6384 */
e7126997
MC		 6385 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6386 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6387 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6388 pci_write_config_word(tp->pdev,
6389 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6390 val16);
5e7dfd0f
MC		 6391
6392 pcie_set_readrq(tp->pdev, 4096);
6393
6394 /* Clear error status */
6395 pci_write_config_word(tp->pdev,
6396 tp->pcie_cap + PCI_EXP_DEVSTA,
6397 PCI_EXP_DEVSTA_CED |
6398 PCI_EXP_DEVSTA_NFED |
6399 PCI_EXP_DEVSTA_FED |
6400 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6401 }
6402
ee6a99b5 6403 tg3_restore_pci_state(tp);
1da177e4 6404
d18edcb2
MC		 6405 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6406
ee6a99b5
MC		 6407 val = 0;
6408 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6409 val = tr32(MEMARB_MODE);
ee6a99b5 6410 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6411
6412 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6413 tg3_stop_fw(tp);
6414 tw32(0x5000, 0x400);
6415 }
6416
6417 tw32(GRC_MODE, tp->grc_mode);
6418
6419 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6420 val = tr32(0xc4);
1da177e4
LT		 6421
6422 tw32(0xc4, val | (1 << 15));
6423 }
6424
6425 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6427 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6428 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6429 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6430 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6431 }
6432
6433 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6434 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6435 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6436 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6437 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6438 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6439 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6440 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6441 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6442 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6443 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6444 } else
6445 tw32_f(MAC_MODE, 0);
6446 udelay(40);
6447
77b483f1
MC		 6448 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6449
7a6f4369
MC		 6450 err = tg3_poll_fw(tp);
6451 if (err)
6452 return err;
1da177e4 6453
0a9140cf
MC		 6454 tg3_mdio_start(tp);
6455
1da177e4
LT		 6456 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6457 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6458 val = tr32(0x7c00);
1da177e4
LT		 6459
6460 tw32(0x7c00, val | (1 << 25));
6461 }
6462
6463 /* Reprobe ASF enable state. */
6464 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6465 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6466 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6467 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6468 u32 nic_cfg;
6469
6470 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6471 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6472 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6473 tp->last_event_jiffies = jiffies;
cbf46853 6474 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6475 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6476 }
6477 }
6478
6479 return 0;
6480}
6481
6482/* tp->lock is held. */
6483static void tg3_stop_fw(struct tg3 *tp)
6484{
0d3031d9
MC		 6485 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6486 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6487 /* Wait for RX cpu to ACK the previous event. */
6488 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6489
6490 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6491
6492 tg3_generate_fw_event(tp);
1da177e4 6493
7c5026aa
MC		 6494 /* Wait for RX cpu to ACK this event. */
6495 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6496 }
6497}
6498
6499/* tp->lock is held. */
944d980e 6500static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6501{
6502 int err;
6503
6504 tg3_stop_fw(tp);
6505
944d980e 6506 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6507
b3b7d6be 6508 tg3_abort_hw(tp, silent);
1da177e4
LT		 6509 err = tg3_chip_reset(tp);
6510
daba2a63
MC		 6511 __tg3_set_mac_addr(tp, 0);
6512
944d980e
MC		 6513 tg3_write_sig_legacy(tp, kind);
6514 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6515
6516 if (err)
6517 return err;
6518
6519 return 0;
6520}
6521
1da177e4
LT		 6522#define RX_CPU_SCRATCH_BASE 0x30000
6523#define RX_CPU_SCRATCH_SIZE 0x04000
6524#define TX_CPU_SCRATCH_BASE 0x34000
6525#define TX_CPU_SCRATCH_SIZE 0x04000
6526
6527/* tp->lock is held. */
6528static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6529{
6530 int i;
6531
5d9428de
ES		 6532 BUG_ON(offset == TX_CPU_BASE &&
6533 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6534
b5d3772c
MC		 6535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6536 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6537
6538 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6539 return 0;
6540 }
1da177e4
LT		 6541 if (offset == RX_CPU_BASE) {
6542 for (i = 0; i < 10000; i++) {
6543 tw32(offset + CPU_STATE, 0xffffffff);
6544 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6545 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6546 break;
6547 }
6548
6549 tw32(offset + CPU_STATE, 0xffffffff);
6550 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6551 udelay(10);
6552 } else {
6553 for (i = 0; i < 10000; i++) {
6554 tw32(offset + CPU_STATE, 0xffffffff);
6555 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6556 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6557 break;
6558 }
6559 }
6560
6561 if (i >= 10000) {
6562 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6563 "and %s CPU\n",
6564 tp->dev->name,
6565 (offset == RX_CPU_BASE ? "RX" : "TX"));
6566 return -ENODEV;
6567 }
ec41c7df
MC		 6568
6569 /* Clear firmware's nvram arbitration. */
6570 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6571 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6572 return 0;
6573}
6574
6575struct fw_info {
077f849d
JSR		 6576 unsigned int fw_base;
6577 unsigned int fw_len;
6578 const __be32 *fw_data;
1da177e4
LT		 6579};
6580
6581/* tp->lock is held. */
6582static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6583 int cpu_scratch_size, struct fw_info *info)
6584{
ec41c7df 6585 int err, lock_err, i;
1da177e4
LT		 6586 void (*write_op)(struct tg3 *, u32, u32);
6587
6588 if (cpu_base == TX_CPU_BASE &&
6589 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6590 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6591 "TX cpu firmware on %s which is 5705.\n",
6592 tp->dev->name);
6593 return -EINVAL;
6594 }
6595
6596 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6597 write_op = tg3_write_mem;
6598 else
6599 write_op = tg3_write_indirect_reg32;
6600
1b628151
MC		 6601 /* It is possible that bootcode is still loading at this point.
6602 * Get the nvram lock first before halting the cpu.
6603 */
ec41c7df 6604 lock_err = tg3_nvram_lock(tp);
1da177e4 6605 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6606 if (!lock_err)
6607 tg3_nvram_unlock(tp);
1da177e4
LT		 6608 if (err)
6609 goto out;
6610
6611 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6612 write_op(tp, cpu_scratch_base + i, 0);
6613 tw32(cpu_base + CPU_STATE, 0xffffffff);
6614 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6615 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6616 write_op(tp, (cpu_scratch_base +
077f849d 6617 (info->fw_base & 0xffff) +
1da177e4 6618 (i * sizeof(u32))),
077f849d 6619 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6620
6621 err = 0;
6622
6623out:
1da177e4
LT		 6624 return err;
6625}
6626
6627/* tp->lock is held. */
6628static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6629{
6630 struct fw_info info;
077f849d 6631 const __be32 *fw_data;
1da177e4
LT		 6632 int err, i;
6633
077f849d
JSR		 6634 fw_data = (void *)tp->fw->data;
6635
6636 /* Firmware blob starts with version numbers, followed by
6637 start address and length. We are setting complete length.
6638 length = end_address_of_bss - start_address_of_text.
6639 Remainder is the blob to be loaded contiguously
6640 from start address. */
6641
6642 info.fw_base = be32_to_cpu(fw_data[1]);
6643 info.fw_len = tp->fw->size - 12;
6644 info.fw_data = &fw_data[3];
1da177e4
LT		 6645
6646 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6647 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6648 &info);
6649 if (err)
6650 return err;
6651
6652 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6653 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6654 &info);
6655 if (err)
6656 return err;
6657
6658 /* Now startup only the RX cpu. */
6659 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6660 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6661
6662 for (i = 0; i < 5; i++) {
077f849d 6663 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6664 break;
6665 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6666 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6667 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6668 udelay(1000);
6669 }
6670 if (i >= 5) {
6671 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6672 "to set RX CPU PC, is %08x should be %08x\n",
6673 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6674 info.fw_base);
1da177e4
LT		 6675 return -ENODEV;
6676 }
6677 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6678 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6679
6680 return 0;
6681}
6682
1da177e4 6683/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6684
6685/* tp->lock is held. */
6686static int tg3_load_tso_firmware(struct tg3 *tp)
6687{
6688 struct fw_info info;
077f849d 6689 const __be32 *fw_data;
1da177e4
LT		 6690 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6691 int err, i;
6692
6693 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6694 return 0;
6695
077f849d
JSR		 6696 fw_data = (void *)tp->fw->data;
6697
6698 /* Firmware blob starts with version numbers, followed by
6699 start address and length. We are setting complete length.
6700 length = end_address_of_bss - start_address_of_text.
6701 Remainder is the blob to be loaded contiguously
6702 from start address. */
6703
6704 info.fw_base = be32_to_cpu(fw_data[1]);
6705 cpu_scratch_size = tp->fw_len;
6706 info.fw_len = tp->fw->size - 12;
6707 info.fw_data = &fw_data[3];
6708
1da177e4 6709 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6710 cpu_base = RX_CPU_BASE;
6711 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6712 } else {
1da177e4
LT		 6713 cpu_base = TX_CPU_BASE;
6714 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6715 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6716 }
6717
6718 err = tg3_load_firmware_cpu(tp, cpu_base,
6719 cpu_scratch_base, cpu_scratch_size,
6720 &info);
6721 if (err)
6722 return err;
6723
6724 /* Now startup the cpu. */
6725 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6726 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6727
6728 for (i = 0; i < 5; i++) {
077f849d 6729 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6730 break;
6731 tw32(cpu_base + CPU_STATE, 0xffffffff);
6732 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6733 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6734 udelay(1000);
6735 }
6736 if (i >= 5) {
6737 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6738 "to set CPU PC, is %08x should be %08x\n",
6739 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6740 info.fw_base);
1da177e4
LT		 6741 return -ENODEV;
6742 }
6743 tw32(cpu_base + CPU_STATE, 0xffffffff);
6744 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6745 return 0;
6746}
6747
1da177e4 6748
1da177e4
LT		 6749static int tg3_set_mac_addr(struct net_device *dev, void *p)
6750{
6751 struct tg3 *tp = netdev_priv(dev);
6752 struct sockaddr *addr = p;
986e0aeb 6753 int err = 0, skip_mac_1 = 0;
1da177e4 6754
f9804ddb
MC		 6755 if (!is_valid_ether_addr(addr->sa_data))
6756 return -EINVAL;
6757
1da177e4
LT		 6758 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6759
e75f7c90
MC		 6760 if (!netif_running(dev))
6761 return 0;
6762
58712ef9 6763 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6764 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6765
986e0aeb
MC		 6766 addr0_high = tr32(MAC_ADDR_0_HIGH);
6767 addr0_low = tr32(MAC_ADDR_0_LOW);
6768 addr1_high = tr32(MAC_ADDR_1_HIGH);
6769 addr1_low = tr32(MAC_ADDR_1_LOW);
6770
6771 /* Skip MAC addr 1 if ASF is using it. */
6772 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6773 !(addr1_high == 0 && addr1_low == 0))
6774 skip_mac_1 = 1;
58712ef9 6775 }
986e0aeb
MC		 6776 spin_lock_bh(&tp->lock);
6777 __tg3_set_mac_addr(tp, skip_mac_1);
6778 spin_unlock_bh(&tp->lock);
1da177e4 6779
b9ec6c1b 6780 return err;
1da177e4
LT		 6781}
6782
6783/* tp->lock is held. */
6784static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6785 dma_addr_t mapping, u32 maxlen_flags,
6786 u32 nic_addr)
6787{
6788 tg3_write_mem(tp,
6789 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6790 ((u64) mapping >> 32));
6791 tg3_write_mem(tp,
6792 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6793 ((u64) mapping & 0xffffffff));
6794 tg3_write_mem(tp,
6795 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6796 maxlen_flags);
6797
6798 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6799 tg3_write_mem(tp,
6800 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6801 nic_addr);
6802}
6803
6804static void __tg3_set_rx_mode(struct net_device *);
d244c892 6805static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6806{
6807 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6808 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6809 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6810 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6811 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6812 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6813 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6814 }
6815 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6816 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6817 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6818 u32 val = ec->stats_block_coalesce_usecs;
6819
6820 if (!netif_carrier_ok(tp->dev))
6821 val = 0;
6822
6823 tw32(HOSTCC_STAT_COAL_TICKS, val);
6824 }
6825}
1da177e4 6826
2d31ecaf
MC		 6827/* tp->lock is held. */
6828static void tg3_rings_reset(struct tg3 *tp)
6829{
6830 int i;
6831 u32 txrcb, rxrcb, limit;
6832 struct tg3_napi *tnapi = &tp->napi[0];
6833
6834 /* Disable all transmit rings but the first. */
6835 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6836 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
6837 else
6838 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6839
6840 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6841 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
6842 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
6843 BDINFO_FLAGS_DISABLED);
6844
6845
6846 /* Disable all receive return rings but the first. */
6847 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6848 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
6849 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6850 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
6851 else
6852 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6853
6854 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6855 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
6856 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
6857 BDINFO_FLAGS_DISABLED);
6858
6859 /* Disable interrupts */
6860 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
6861
6862 /* Zero mailbox registers. */
6863 tp->napi[0].tx_prod = 0;
6864 tp->napi[0].tx_cons = 0;
6865 tw32_mailbox(tp->napi[0].prodmbox, 0);
6866 tw32_rx_mbox(tp->napi[0].consmbox, 0);
6867
6868 /* Make sure the NIC-based send BD rings are disabled. */
6869 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6870 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6871 for (i = 0; i < 16; i++)
6872 tw32_tx_mbox(mbox + i * 8, 0);
6873 }
6874
6875 txrcb = NIC_SRAM_SEND_RCB;
6876 rxrcb = NIC_SRAM_RCV_RET_RCB;
6877
6878 /* Clear status block in ram. */
6879 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6880
6881 /* Set status block DMA address */
6882 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6883 ((u64) tnapi->status_mapping >> 32));
6884 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6885 ((u64) tnapi->status_mapping & 0xffffffff));
6886
6887 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
6888 (TG3_TX_RING_SIZE <<
6889 BDINFO_FLAGS_MAXLEN_SHIFT),
6890 NIC_SRAM_TX_BUFFER_DESC);
6891
6892 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
6893 (TG3_RX_RCB_RING_SIZE(tp) <<
6894 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
6895}
6896
1da177e4 6897/* tp->lock is held. */
8e7a22e3 6898static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6899{
6900 u32 val, rdmac_mode;
6901 int i, err, limit;
21f581a5 6902 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 6903
6904 tg3_disable_ints(tp);
6905
6906 tg3_stop_fw(tp);
6907
6908 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6909
6910 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6911 tg3_abort_hw(tp, 1);
1da177e4
LT		 6912 }
6913
dd477003
MC		 6914 if (reset_phy &&
6915 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6916 tg3_phy_reset(tp);
6917
1da177e4
LT		 6918 err = tg3_chip_reset(tp);
6919 if (err)
6920 return err;
6921
6922 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6923
bcb37f6c 6924 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6925 val = tr32(TG3_CPMU_CTRL);
6926 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6927 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6928
6929 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6930 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6931 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6932 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6933
6934 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6935 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6936 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6937 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6938
6939 val = tr32(TG3_CPMU_HST_ACC);
6940 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6941 val |= CPMU_HST_ACC_MACCLK_6_25;
6942 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6943 }
6944
33466d93
MC		 6945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6946 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6947 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6948 PCIE_PWR_MGMT_L1_THRESH_4MS;
6949 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 6950
6951 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6952 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6953
6954 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC		 6955 }
6956
255ca311
MC		 6957 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6958 val = tr32(TG3_PCIE_LNKCTL);
6959 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6960 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6961 else
6962 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6963 tw32(TG3_PCIE_LNKCTL, val);
6964 }
6965
1da177e4
LT		 6966 /* This works around an issue with Athlon chipsets on
6967 * B3 tigon3 silicon. This bit has no effect on any
6968 * other revision. But do not set this on PCI Express
795d01c5 6969 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6970 */
795d01c5
MC		 6971 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6972 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6973 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6974 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6975 }
1da177e4
LT		 6976
6977 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6978 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6979 val = tr32(TG3PCI_PCISTATE);
6980 val |= PCISTATE_RETRY_SAME_DMA;
6981 tw32(TG3PCI_PCISTATE, val);
6982 }
6983
0d3031d9
MC		 6984 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6985 /* Allow reads and writes to the
6986 * APE register and memory space.
6987 */
6988 val = tr32(TG3PCI_PCISTATE);
6989 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6990 PCISTATE_ALLOW_APE_SHMEM_WR;
6991 tw32(TG3PCI_PCISTATE, val);
6992 }
6993
1da177e4
LT		 6994 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6995 /* Enable some hw fixes. */
6996 val = tr32(TG3PCI_MSI_DATA);
6997 val |= (1 << 26) | (1 << 28) | (1 << 29);
6998 tw32(TG3PCI_MSI_DATA, val);
6999 }
7000
7001 /* Descriptor ring init may make accesses to the
7002 * NIC SRAM area to setup the TX descriptors, so we
7003 * can only do this after the hardware has been
7004 * successfully reset.
7005 */
32d8c572
MC		 7006 err = tg3_init_rings(tp);
7007 if (err)
7008 return err;
1da177e4 7009
9936bcf6 7010 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 7011 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7012 /* This value is determined during the probe time DMA
7013 * engine test, tg3_test_dma.
7014 */
7015 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7016 }
1da177e4
LT		 7017
7018 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7019 GRC_MODE_4X_NIC_SEND_RINGS |
7020 GRC_MODE_NO_TX_PHDR_CSUM |
7021 GRC_MODE_NO_RX_PHDR_CSUM);
7022 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7023
7024 /* Pseudo-header checksum is done by hardware logic and not
7025 * the offload processers, so make the chip do the pseudo-
7026 * header checksums on receive. For transmit it is more
7027 * convenient to do the pseudo-header checksum in software
7028 * as Linux does that on transmit for us in all cases.
7029 */
7030 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7031
7032 tw32(GRC_MODE,
7033 tp->grc_mode |
7034 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7035
7036 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7037 val = tr32(GRC_MISC_CFG);
7038 val &= ~0xff;
7039 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7040 tw32(GRC_MISC_CFG, val);
7041
7042 /* Initialize MBUF/DESC pool. */
cbf46853 7043 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7044 /* Do nothing. */
7045 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7046 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7048 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7049 else
7050 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7051 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7052 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7053 }
1da177e4
LT		 7054 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7055 int fw_len;
7056
077f849d 7057 fw_len = tp->fw_len;
1da177e4
LT		 7058 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7059 tw32(BUFMGR_MB_POOL_ADDR,
7060 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7061 tw32(BUFMGR_MB_POOL_SIZE,
7062 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7063 }
1da177e4 7064
0f893dc6 7065 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7066 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7067 tp->bufmgr_config.mbuf_read_dma_low_water);
7068 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7069 tp->bufmgr_config.mbuf_mac_rx_low_water);
7070 tw32(BUFMGR_MB_HIGH_WATER,
7071 tp->bufmgr_config.mbuf_high_water);
7072 } else {
7073 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7074 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7075 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7076 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7077 tw32(BUFMGR_MB_HIGH_WATER,
7078 tp->bufmgr_config.mbuf_high_water_jumbo);
7079 }
7080 tw32(BUFMGR_DMA_LOW_WATER,
7081 tp->bufmgr_config.dma_low_water);
7082 tw32(BUFMGR_DMA_HIGH_WATER,
7083 tp->bufmgr_config.dma_high_water);
7084
7085 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7086 for (i = 0; i < 2000; i++) {
7087 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7088 break;
7089 udelay(10);
7090 }
7091 if (i >= 2000) {
7092 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7093 tp->dev->name);
7094 return -ENODEV;
7095 }
7096
7097 /* Setup replenish threshold. */
f92905de
MC		 7098 val = tp->rx_pending / 8;
7099 if (val == 0)
7100 val = 1;
7101 else if (val > tp->rx_std_max_post)
7102 val = tp->rx_std_max_post;
b5d3772c
MC		 7103 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7104 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7105 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7106
7107 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7108 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7109 }
f92905de
MC		 7110
7111 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7112
7113 /* Initialize TG3_BDINFO's at:
7114 * RCVDBDI_STD_BD: standard eth size rx ring
7115 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7116 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7117 *
7118 * like so:
7119 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7120 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7121 * ring attribute flags
7122 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7123 *
7124 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7125 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7126 *
7127 * The size of each ring is fixed in the firmware, but the location is
7128 * configurable.
7129 */
7130 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7131 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7132 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7133 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7134 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7135 NIC_SRAM_RX_BUFFER_DESC);
7136
fdb72b38
MC		 7137 /* Disable the mini ring */
7138 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7139 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7140 BDINFO_FLAGS_DISABLED);
7141
fdb72b38
MC		 7142 /* Program the jumbo buffer descriptor ring control
7143 * blocks on those devices that have them.
7144 */
8f666b07 7145 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7146 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7147 /* Setup replenish threshold. */
7148 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7149
0f893dc6 7150 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7151 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7152 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7153 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7154 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7155 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7156 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7157 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7158 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7159 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7160 } else {
7161 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7162 BDINFO_FLAGS_DISABLED);
7163 }
7164
fdb72b38
MC		 7165 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7166 } else
7167 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7168
7169 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7170
21f581a5 7171 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7172 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7173 tpr->rx_std_ptr);
1da177e4 7174
21f581a5
MC		 7175 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7176 tp->rx_jumbo_pending : 0;
1da177e4 7177 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7178 tpr->rx_jmb_ptr);
1da177e4 7179
2d31ecaf
MC		 7180 tg3_rings_reset(tp);
7181
1da177e4 7182 /* Initialize MAC address and backoff seed. */
986e0aeb 7183 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7184
7185 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7186 tw32(MAC_RX_MTU_SIZE,
7187 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7188
7189 /* The slot time is changed by tg3_setup_phy if we
7190 * run at gigabit with half duplex.
7191 */
7192 tw32(MAC_TX_LENGTHS,
7193 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7194 (6 << TX_LENGTHS_IPG_SHIFT) |
7195 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7196
7197 /* Receive rules. */
7198 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7199 tw32(RCVLPC_CONFIG, 0x0181);
7200
7201 /* Calculate RDMAC_MODE setting early, we need it to determine
7202 * the RCVLPC_STATE_ENABLE mask.
7203 */
7204 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7205 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7206 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7207 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7208 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7209
57e6983c 7210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7211 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7213 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7214 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7215 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7216
85e94ced
MC		 7217 /* If statement applies to 5705 and 5750 PCI devices only */
7218 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7219 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7220 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7221 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7223 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7224 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7225 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7226 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7227 }
7228 }
7229
85e94ced
MC		 7230 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7231 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7232
1da177e4 7233 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7234 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7235
7236 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7237 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7238 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7239
7240 /* Receive/send statistics. */
1661394e
MC		 7241 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7242 val = tr32(RCVLPC_STATS_ENABLE);
7243 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7244 tw32(RCVLPC_STATS_ENABLE, val);
7245 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7246 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7247 val = tr32(RCVLPC_STATS_ENABLE);
7248 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7249 tw32(RCVLPC_STATS_ENABLE, val);
7250 } else {
7251 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7252 }
7253 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7254 tw32(SNDDATAI_STATSENAB, 0xffffff);
7255 tw32(SNDDATAI_STATSCTRL,
7256 (SNDDATAI_SCTRL_ENABLE |
7257 SNDDATAI_SCTRL_FASTUPD));
7258
7259 /* Setup host coalescing engine. */
7260 tw32(HOSTCC_MODE, 0);
7261 for (i = 0; i < 2000; i++) {
7262 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7263 break;
7264 udelay(10);
7265 }
7266
d244c892 7267 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7268
1da177e4
LT		 7269 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7270 /* Status/statistics block address. See tg3_timer,
7271 * the tg3_periodic_fetch_stats call there, and
7272 * tg3_get_stats to see how this works for 5705/5750 chips.
7273 */
1da177e4
LT		 7274 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7275 ((u64) tp->stats_mapping >> 32));
7276 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7277 ((u64) tp->stats_mapping & 0xffffffff));
7278 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7279
1da177e4 7280 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7281
7282 /* Clear statistics and status block memory areas */
7283 for (i = NIC_SRAM_STATS_BLK;
7284 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7285 i += sizeof(u32)) {
7286 tg3_write_mem(tp, i, 0);
7287 udelay(40);
7288 }
1da177e4
LT		 7289 }
7290
7291 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7292
7293 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7294 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7295 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7296 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7297
c94e3941
MC		 7298 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7299 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7300 /* reset to prevent losing 1st rx packet intermittently */
7301 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7302 udelay(10);
7303 }
7304
3bda1258
MC		 7305 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7306 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7307 else
7308 tp->mac_mode = 0;
7309 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7310 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7311 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7312 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7313 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7314 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7315 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7316 udelay(40);
7317
314fba34 7318 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7319 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7320 * register to preserve the GPIO settings for LOMs. The GPIOs,
7321 * whether used as inputs or outputs, are set by boot code after
7322 * reset.
7323 */
9d26e213 7324 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7325 u32 gpio_mask;
7326
9d26e213
MC		 7327 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7328 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7329 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7330
7331 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7332 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7333 GRC_LCLCTRL_GPIO_OUTPUT3;
7334
af36e6b6
MC		 7335 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7336 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7337
aaf84465 7338 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7339 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7340
7341 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7342 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7343 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7344 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7345 }
1da177e4
LT		 7346 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7347 udelay(100);
7348
1da177e4
LT		 7349 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7350 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7351 udelay(40);
7352 }
7353
7354 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7355 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7356 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7357 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7358 WDMAC_MODE_LNGREAD_ENAB);
7359
85e94ced
MC		 7360 /* If statement applies to 5705 and 5750 PCI devices only */
7361 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7362 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7364 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7365 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7366 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7367 /* nothing */
7368 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7369 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7370 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7371 val |= WDMAC_MODE_RX_ACCEL;
7372 }
7373 }
7374
d9ab5ad1 7375 /* Enable host coalescing bug fix */
321d32a0 7376 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7377 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7378
1da177e4
LT		 7379 tw32_f(WDMAC_MODE, val);
7380 udelay(40);
7381
9974a356
MC		 7382 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7383 u16 pcix_cmd;
7384
7385 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7386 &pcix_cmd);
1da177e4 7387 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7388 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7389 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7390 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7391 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7392 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7393 }
9974a356
MC		 7394 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7395 pcix_cmd);
1da177e4
LT		 7396 }
7397
7398 tw32_f(RDMAC_MODE, rdmac_mode);
7399 udelay(40);
7400
7401 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7402 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7403 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7404
7405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7406 tw32(SNDDATAC_MODE,
7407 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7408 else
7409 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7410
1da177e4
LT		 7411 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7412 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7413 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7414 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7415 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7416 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7417 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7418 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7419
7420 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7421 err = tg3_load_5701_a0_firmware_fix(tp);
7422 if (err)
7423 return err;
7424 }
7425
1da177e4
LT		 7426 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7427 err = tg3_load_tso_firmware(tp);
7428 if (err)
7429 return err;
7430 }
1da177e4
LT		 7431
7432 tp->tx_mode = TX_MODE_ENABLE;
7433 tw32_f(MAC_TX_MODE, tp->tx_mode);
7434 udelay(100);
7435
7436 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7437 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7438 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7439
1da177e4
LT		 7440 tw32_f(MAC_RX_MODE, tp->rx_mode);
7441 udelay(10);
7442
1da177e4
LT		 7443 tw32(MAC_LED_CTRL, tp->led_ctrl);
7444
7445 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7446 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7447 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7448 udelay(10);
7449 }
7450 tw32_f(MAC_RX_MODE, tp->rx_mode);
7451 udelay(10);
7452
7453 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7454 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7455 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7456 /* Set drive transmission level to 1.2V */
7457 /* only if the signal pre-emphasis bit is not set */
7458 val = tr32(MAC_SERDES_CFG);
7459 val &= 0xfffff000;
7460 val |= 0x880;
7461 tw32(MAC_SERDES_CFG, val);
7462 }
7463 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7464 tw32(MAC_SERDES_CFG, 0x616000);
7465 }
7466
7467 /* Prevent chip from dropping frames when flow control
7468 * is enabled.
7469 */
7470 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7471
7472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7473 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7474 /* Use hardware link auto-negotiation */
7475 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7476 }
7477
d4d2c558
MC		 7478 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7479 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7480 u32 tmp;
7481
7482 tmp = tr32(SERDES_RX_CTRL);
7483 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7484 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7485 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7486 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7487 }
7488
dd477003
MC		 7489 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7490 if (tp->link_config.phy_is_low_power) {
7491 tp->link_config.phy_is_low_power = 0;
7492 tp->link_config.speed = tp->link_config.orig_speed;
7493 tp->link_config.duplex = tp->link_config.orig_duplex;
7494 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7495 }
1da177e4 7496
dd477003
MC		 7497 err = tg3_setup_phy(tp, 0);
7498 if (err)
7499 return err;
1da177e4 7500
dd477003 7501 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7502 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7503 u32 tmp;
7504
7505 /* Clear CRC stats. */
7506 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7507 tg3_writephy(tp, MII_TG3_TEST1,
7508 tmp | MII_TG3_TEST1_CRC_EN);
7509 tg3_readphy(tp, 0x14, &tmp);
7510 }
1da177e4
LT		 7511 }
7512 }
7513
7514 __tg3_set_rx_mode(tp->dev);
7515
7516 /* Initialize receive rules. */
7517 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7518 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7519 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7520 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7521
4cf78e4f 7522 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7523 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7524 limit = 8;
7525 else
7526 limit = 16;
7527 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7528 limit -= 4;
7529 switch (limit) {
7530 case 16:
7531 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7532 case 15:
7533 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7534 case 14:
7535 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7536 case 13:
7537 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7538 case 12:
7539 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7540 case 11:
7541 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7542 case 10:
7543 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7544 case 9:
7545 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7546 case 8:
7547 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7548 case 7:
7549 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7550 case 6:
7551 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7552 case 5:
7553 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7554 case 4:
7555 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7556 case 3:
7557 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7558 case 2:
7559 case 1:
7560
7561 default:
7562 break;
855e1111 7563 }
1da177e4 7564
9ce768ea
MC		 7565 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7566 /* Write our heartbeat update interval to APE. */
7567 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7568 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7569
1da177e4
LT		 7570 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7571
1da177e4
LT		 7572 return 0;
7573}
7574
7575/* Called at device open time to get the chip ready for
7576 * packet processing. Invoked with tp->lock held.
7577 */
8e7a22e3 7578static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7579{
1da177e4
LT		 7580 tg3_switch_clocks(tp);
7581
7582 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7583
2f751b67 7584 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7585}
7586
7587#define TG3_STAT_ADD32(PSTAT, REG) \
7588do { u32 __val = tr32(REG); \
7589 (PSTAT)->low += __val; \
7590 if ((PSTAT)->low < __val) \
7591 (PSTAT)->high += 1; \
7592} while (0)
7593
7594static void tg3_periodic_fetch_stats(struct tg3 *tp)
7595{
7596 struct tg3_hw_stats *sp = tp->hw_stats;
7597
7598 if (!netif_carrier_ok(tp->dev))
7599 return;
7600
7601 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7602 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7603 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7604 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7605 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7606 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7607 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7608 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7609 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7610 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7611 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7612 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7613 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7614
7615 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7616 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7617 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7618 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7619 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7620 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7621 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7622 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7623 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7624 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7625 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7626 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7627 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7628 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7629
7630 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7631 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7632 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7633}
7634
7635static void tg3_timer(unsigned long __opaque)
7636{
7637 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7638
f475f163
MC		 7639 if (tp->irq_sync)
7640 goto restart_timer;
7641
f47c11ee 7642 spin_lock(&tp->lock);
1da177e4 7643
fac9b83e
DM		 7644 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7645 /* All of this garbage is because when using non-tagged
7646 * IRQ status the mailbox/status_block protocol the chip
7647 * uses with the cpu is race prone.
7648 */
898a56f8 7649 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7650 tw32(GRC_LOCAL_CTRL,
7651 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7652 } else {
7653 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7654 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7655 }
1da177e4 7656
fac9b83e
DM		 7657 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7658 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7659 spin_unlock(&tp->lock);
fac9b83e
DM		 7660 schedule_work(&tp->reset_task);
7661 return;
7662 }
1da177e4
LT		 7663 }
7664
1da177e4
LT		 7665 /* This part only runs once per second. */
7666 if (!--tp->timer_counter) {
fac9b83e
DM		 7667 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7668 tg3_periodic_fetch_stats(tp);
7669
1da177e4
LT		 7670 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7671 u32 mac_stat;
7672 int phy_event;
7673
7674 mac_stat = tr32(MAC_STATUS);
7675
7676 phy_event = 0;
7677 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7678 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7679 phy_event = 1;
7680 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7681 phy_event = 1;
7682
7683 if (phy_event)
7684 tg3_setup_phy(tp, 0);
7685 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7686 u32 mac_stat = tr32(MAC_STATUS);
7687 int need_setup = 0;
7688
7689 if (netif_carrier_ok(tp->dev) &&
7690 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7691 need_setup = 1;
7692 }
7693 if (! netif_carrier_ok(tp->dev) &&
7694 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7695 MAC_STATUS_SIGNAL_DET))) {
7696 need_setup = 1;
7697 }
7698 if (need_setup) {
3d3ebe74
MC		 7699 if (!tp->serdes_counter) {
7700 tw32_f(MAC_MODE,
7701 (tp->mac_mode &
7702 ~MAC_MODE_PORT_MODE_MASK));
7703 udelay(40);
7704 tw32_f(MAC_MODE, tp->mac_mode);
7705 udelay(40);
7706 }
1da177e4
LT		 7707 tg3_setup_phy(tp, 0);
7708 }
747e8f8b
MC		 7709 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7710 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7711
7712 tp->timer_counter = tp->timer_multiplier;
7713 }
7714
130b8e4d
MC		 7715 /* Heartbeat is only sent once every 2 seconds.
7716 *
7717 * The heartbeat is to tell the ASF firmware that the host
7718 * driver is still alive. In the event that the OS crashes,
7719 * ASF needs to reset the hardware to free up the FIFO space
7720 * that may be filled with rx packets destined for the host.
7721 * If the FIFO is full, ASF will no longer function properly.
7722 *
7723 * Unintended resets have been reported on real time kernels
7724 * where the timer doesn't run on time. Netpoll will also have
7725 * same problem.
7726 *
7727 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7728 * to check the ring condition when the heartbeat is expiring
7729 * before doing the reset. This will prevent most unintended
7730 * resets.
7731 */
1da177e4 7732 if (!--tp->asf_counter) {
bc7959b2
MC		 7733 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7734 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7735 tg3_wait_for_event_ack(tp);
7736
bbadf503 7737 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7738 FWCMD_NICDRV_ALIVE3);
bbadf503 7739 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7740 /* 5 seconds timeout */
bbadf503 7741 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7742
7743 tg3_generate_fw_event(tp);
1da177e4
LT		 7744 }
7745 tp->asf_counter = tp->asf_multiplier;
7746 }
7747
f47c11ee 7748 spin_unlock(&tp->lock);
1da177e4 7749
f475f163 7750restart_timer:
1da177e4
LT		 7751 tp->timer.expires = jiffies + tp->timer_offset;
7752 add_timer(&tp->timer);
7753}
7754
4f125f42 7755static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 7756{
7d12e780 7757 irq_handler_t fn;
fcfa0a32 7758 unsigned long flags;
4f125f42
MC		 7759 char *name;
7760 struct tg3_napi *tnapi = &tp->napi[irq_num];
7761
7762 if (tp->irq_cnt == 1)
7763 name = tp->dev->name;
7764 else {
7765 name = &tnapi->irq_lbl[0];
7766 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
7767 name[IFNAMSIZ-1] = 0;
7768 }
fcfa0a32
MC		 7769
7770 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7771 fn = tg3_msi;
7772 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7773 fn = tg3_msi_1shot;
1fb9df5d 7774 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7775 } else {
7776 fn = tg3_interrupt;
7777 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7778 fn = tg3_interrupt_tagged;
1fb9df5d 7779 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 7780 }
4f125f42
MC		 7781
7782 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 7783}
7784
7938109f
MC		 7785static int tg3_test_interrupt(struct tg3 *tp)
7786{
09943a18 7787 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 7788 struct net_device *dev = tp->dev;
b16250e3 7789 int err, i, intr_ok = 0;
7938109f 7790
d4bc3927
MC		 7791 if (!netif_running(dev))
7792 return -ENODEV;
7793
7938109f
MC		 7794 tg3_disable_ints(tp);
7795
4f125f42 7796 free_irq(tnapi->irq_vec, tnapi);
7938109f 7797
4f125f42 7798 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 7799 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 7800 if (err)
7801 return err;
7802
898a56f8 7803 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7804 tg3_enable_ints(tp);
7805
7806 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 7807 tnapi->coal_now);
7938109f
MC		 7808
7809 for (i = 0; i < 5; i++) {
b16250e3
MC		 7810 u32 int_mbox, misc_host_ctrl;
7811
898a56f8 7812 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 7813 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7814
7815 if ((int_mbox != 0) ||
7816 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7817 intr_ok = 1;
7938109f 7818 break;
b16250e3
MC		 7819 }
7820
7938109f
MC		 7821 msleep(10);
7822 }
7823
7824 tg3_disable_ints(tp);
7825
4f125f42 7826 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 7827
4f125f42 7828 err = tg3_request_irq(tp, 0);
7938109f
MC		 7829
7830 if (err)
7831 return err;
7832
b16250e3 7833 if (intr_ok)
7938109f
MC		 7834 return 0;
7835
7836 return -EIO;
7837}
7838
7839/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7840 * successfully restored
7841 */
7842static int tg3_test_msi(struct tg3 *tp)
7843{
7938109f
MC		 7844 int err;
7845 u16 pci_cmd;
7846
7847 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7848 return 0;
7849
7850 /* Turn off SERR reporting in case MSI terminates with Master
7851 * Abort.
7852 */
7853 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7854 pci_write_config_word(tp->pdev, PCI_COMMAND,
7855 pci_cmd & ~PCI_COMMAND_SERR);
7856
7857 err = tg3_test_interrupt(tp);
7858
7859 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7860
7861 if (!err)
7862 return 0;
7863
7864 /* other failures */
7865 if (err != -EIO)
7866 return err;
7867
7868 /* MSI test failed, go back to INTx mode */
7869 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7870 "switching to INTx mode. Please report this failure to "
7871 "the PCI maintainer and include system chipset information.\n",
7872 tp->dev->name);
7873
4f125f42 7874 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 7875
7938109f
MC		 7876 pci_disable_msi(tp->pdev);
7877
7878 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7879
4f125f42 7880 err = tg3_request_irq(tp, 0);
7938109f
MC		 7881 if (err)
7882 return err;
7883
7884 /* Need to reset the chip because the MSI cycle may have terminated
7885 * with Master Abort.
7886 */
f47c11ee 7887 tg3_full_lock(tp, 1);
7938109f 7888
944d980e 7889 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7890 err = tg3_init_hw(tp, 1);
7938109f 7891
f47c11ee 7892 tg3_full_unlock(tp);
7938109f
MC		 7893
7894 if (err)
4f125f42 7895 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 7896
7897 return err;
7898}
7899
9e9fd12d
MC		 7900static int tg3_request_firmware(struct tg3 *tp)
7901{
7902 const __be32 *fw_data;
7903
7904 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7905 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7906 tp->dev->name, tp->fw_needed);
7907 return -ENOENT;
7908 }
7909
7910 fw_data = (void *)tp->fw->data;
7911
7912 /* Firmware blob starts with version numbers, followed by
7913 * start address and _full_ length including BSS sections
7914 * (which must be longer than the actual data, of course
7915 */
7916
7917 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7918 if (tp->fw_len < (tp->fw->size - 12)) {
7919 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7920 tp->dev->name, tp->fw_len, tp->fw_needed);
7921 release_firmware(tp->fw);
7922 tp->fw = NULL;
7923 return -EINVAL;
7924 }
7925
7926 /* We no longer need firmware; we have it. */
7927 tp->fw_needed = NULL;
7928 return 0;
7929}
7930
07b0173c
MC		 7931static void tg3_ints_init(struct tg3 *tp)
7932{
7933 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7934 /* All MSI supporting chips should support tagged
7935 * status. Assert that this is the case.
7936 */
7937 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7938 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7939 "Not using MSI.\n", tp->dev->name);
7940 } else if (pci_enable_msi(tp->pdev) == 0) {
7941 u32 msi_mode;
7942
7943 msi_mode = tr32(MSGINT_MODE);
7944 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7945 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7946 }
7947 }
4f125f42
MC		 7948
7949 tp->irq_cnt = 1;
7950 tp->napi[0].irq_vec = tp->pdev->irq;
07b0173c
MC		 7951}
7952
7953static void tg3_ints_fini(struct tg3 *tp)
7954{
7955 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7956 pci_disable_msi(tp->pdev);
7957 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7958 }
7959}
7960
1da177e4
LT		 7961static int tg3_open(struct net_device *dev)
7962{
7963 struct tg3 *tp = netdev_priv(dev);
4f125f42 7964 int i, err;
1da177e4 7965
9e9fd12d
MC		 7966 if (tp->fw_needed) {
7967 err = tg3_request_firmware(tp);
7968 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7969 if (err)
7970 return err;
7971 } else if (err) {
7972 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7973 tp->dev->name);
7974 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7975 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7976 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7977 tp->dev->name);
7978 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7979 }
7980 }
7981
c49a1561
MC		 7982 netif_carrier_off(tp->dev);
7983
bc1c7567 7984 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 7985 if (err)
bc1c7567 7986 return err;
2f751b67
MC		 7987
7988 tg3_full_lock(tp, 0);
bc1c7567 7989
1da177e4
LT		 7990 tg3_disable_ints(tp);
7991 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7992
f47c11ee 7993 tg3_full_unlock(tp);
1da177e4
LT		 7994
7995 /* The placement of this call is tied
7996 * to the setup and use of Host TX descriptors.
7997 */
7998 err = tg3_alloc_consistent(tp);
7999 if (err)
8000 return err;
8001
07b0173c 8002 tg3_ints_init(tp);
88b06bc2 8003
8ef0442f 8004 napi_enable(&tp->napi[0].napi);
1da177e4 8005
4f125f42
MC		 8006 for (i = 0; i < tp->irq_cnt; i++) {
8007 struct tg3_napi *tnapi = &tp->napi[i];
8008 err = tg3_request_irq(tp, i);
8009 if (err) {
8010 for (i--; i >= 0; i--)
8011 free_irq(tnapi->irq_vec, tnapi);
8012 break;
8013 }
8014 }
1da177e4 8015
07b0173c
MC		 8016 if (err)
8017 goto err_out1;
bea3348e 8018
f47c11ee 8019 tg3_full_lock(tp, 0);
1da177e4 8020
8e7a22e3 8021 err = tg3_init_hw(tp, 1);
1da177e4 8022 if (err) {
944d980e 8023 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8024 tg3_free_rings(tp);
8025 } else {
fac9b83e
DM		 8026 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8027 tp->timer_offset = HZ;
8028 else
8029 tp->timer_offset = HZ / 10;
8030
8031 BUG_ON(tp->timer_offset > HZ);
8032 tp->timer_counter = tp->timer_multiplier =
8033 (HZ / tp->timer_offset);
8034 tp->asf_counter = tp->asf_multiplier =
28fbef78 8035 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8036
8037 init_timer(&tp->timer);
8038 tp->timer.expires = jiffies + tp->timer_offset;
8039 tp->timer.data = (unsigned long) tp;
8040 tp->timer.function = tg3_timer;
1da177e4
LT		 8041 }
8042
f47c11ee 8043 tg3_full_unlock(tp);
1da177e4 8044
07b0173c
MC		 8045 if (err)
8046 goto err_out2;
1da177e4 8047
7938109f
MC		 8048 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8049 err = tg3_test_msi(tp);
fac9b83e 8050
7938109f 8051 if (err) {
f47c11ee 8052 tg3_full_lock(tp, 0);
944d980e 8053 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8054 tg3_free_rings(tp);
f47c11ee 8055 tg3_full_unlock(tp);
7938109f 8056
07b0173c 8057 goto err_out1;
7938109f 8058 }
fcfa0a32
MC		 8059
8060 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8061 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 8062 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8063
b5d3772c
MC		 8064 tw32(PCIE_TRANSACTION_CFG,
8065 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 8066 }
8067 }
7938109f
MC		 8068 }
8069
b02fd9e3
MC		 8070 tg3_phy_start(tp);
8071
f47c11ee 8072 tg3_full_lock(tp, 0);
1da177e4 8073
7938109f
MC		 8074 add_timer(&tp->timer);
8075 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8076 tg3_enable_ints(tp);
8077
f47c11ee 8078 tg3_full_unlock(tp);
1da177e4
LT		 8079
8080 netif_start_queue(dev);
8081
8082 return 0;
07b0173c
MC		 8083
8084err_out2:
4f125f42
MC		 8085 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8086 struct tg3_napi *tnapi = &tp->napi[i];
8087 free_irq(tnapi->irq_vec, tnapi);
8088 }
07b0173c
MC		 8089
8090err_out1:
8ef0442f 8091 napi_disable(&tp->napi[0].napi);
07b0173c
MC		 8092 tg3_ints_fini(tp);
8093 tg3_free_consistent(tp);
8094 return err;
1da177e4
LT		 8095}
8096
8097#if 0
8098/*static*/ void tg3_dump_state(struct tg3 *tp)
8099{
8100 u32 val32, val32_2, val32_3, val32_4, val32_5;
8101 u16 val16;
8102 int i;
898a56f8 8103 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8104
8105 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8106 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8107 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8108 val16, val32);
8109
8110 /* MAC block */
8111 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8112 tr32(MAC_MODE), tr32(MAC_STATUS));
8113 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8114 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8115 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8116 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8117 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8118 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8119
8120 /* Send data initiator control block */
8121 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8122 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8123 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8124 tr32(SNDDATAI_STATSCTRL));
8125
8126 /* Send data completion control block */
8127 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8128
8129 /* Send BD ring selector block */
8130 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8131 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8132
8133 /* Send BD initiator control block */
8134 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8135 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8136
8137 /* Send BD completion control block */
8138 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8139
8140 /* Receive list placement control block */
8141 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8142 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8143 printk(" RCVLPC_STATSCTRL[%08x]\n",
8144 tr32(RCVLPC_STATSCTRL));
8145
8146 /* Receive data and receive BD initiator control block */
8147 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8148 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8149
8150 /* Receive data completion control block */
8151 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8152 tr32(RCVDCC_MODE));
8153
8154 /* Receive BD initiator control block */
8155 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8156 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8157
8158 /* Receive BD completion control block */
8159 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8160 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8161
8162 /* Receive list selector control block */
8163 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8164 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8165
8166 /* Mbuf cluster free block */
8167 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8168 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8169
8170 /* Host coalescing control block */
8171 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8172 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8173 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8174 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8175 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8176 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8177 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8178 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8179 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8180 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8181 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8182 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8183
8184 /* Memory arbiter control block */
8185 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8186 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8187
8188 /* Buffer manager control block */
8189 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8190 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8191 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8192 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8193 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8194 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8195 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8196 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8197
8198 /* Read DMA control block */
8199 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8200 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8201
8202 /* Write DMA control block */
8203 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8204 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8205
8206 /* DMA completion block */
8207 printk("DEBUG: DMAC_MODE[%08x]\n",
8208 tr32(DMAC_MODE));
8209
8210 /* GRC block */
8211 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8212 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8213 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8214 tr32(GRC_LOCAL_CTRL));
8215
8216 /* TG3_BDINFOs */
8217 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8218 tr32(RCVDBDI_JUMBO_BD + 0x0),
8219 tr32(RCVDBDI_JUMBO_BD + 0x4),
8220 tr32(RCVDBDI_JUMBO_BD + 0x8),
8221 tr32(RCVDBDI_JUMBO_BD + 0xc));
8222 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8223 tr32(RCVDBDI_STD_BD + 0x0),
8224 tr32(RCVDBDI_STD_BD + 0x4),
8225 tr32(RCVDBDI_STD_BD + 0x8),
8226 tr32(RCVDBDI_STD_BD + 0xc));
8227 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8228 tr32(RCVDBDI_MINI_BD + 0x0),
8229 tr32(RCVDBDI_MINI_BD + 0x4),
8230 tr32(RCVDBDI_MINI_BD + 0x8),
8231 tr32(RCVDBDI_MINI_BD + 0xc));
8232
8233 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8234 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8235 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8236 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8237 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8238 val32, val32_2, val32_3, val32_4);
8239
8240 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8241 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8242 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8243 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8244 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8245 val32, val32_2, val32_3, val32_4);
8246
8247 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8248 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8249 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8250 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8251 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8252 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8253 val32, val32_2, val32_3, val32_4, val32_5);
8254
8255 /* SW status block */
898a56f8
MC		 8256 printk(KERN_DEBUG
8257 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8258 sblk->status,
8259 sblk->status_tag,
8260 sblk->rx_jumbo_consumer,
8261 sblk->rx_consumer,
8262 sblk->rx_mini_consumer,
8263 sblk->idx[0].rx_producer,
8264 sblk->idx[0].tx_consumer);
1da177e4
LT		 8265
8266 /* SW statistics block */
8267 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8268 ((u32 *)tp->hw_stats)[0],
8269 ((u32 *)tp->hw_stats)[1],
8270 ((u32 *)tp->hw_stats)[2],
8271 ((u32 *)tp->hw_stats)[3]);
8272
8273 /* Mailboxes */
8274 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8275 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8276 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8277 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8278 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8279
8280 /* NIC side send descriptors. */
8281 for (i = 0; i < 6; i++) {
8282 unsigned long txd;
8283
8284 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8285 + (i * sizeof(struct tg3_tx_buffer_desc));
8286 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8287 i,
8288 readl(txd + 0x0), readl(txd + 0x4),
8289 readl(txd + 0x8), readl(txd + 0xc));
8290 }
8291
8292 /* NIC side RX descriptors. */
8293 for (i = 0; i < 6; i++) {
8294 unsigned long rxd;
8295
8296 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8297 + (i * sizeof(struct tg3_rx_buffer_desc));
8298 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8299 i,
8300 readl(rxd + 0x0), readl(rxd + 0x4),
8301 readl(rxd + 0x8), readl(rxd + 0xc));
8302 rxd += (4 * sizeof(u32));
8303 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8304 i,
8305 readl(rxd + 0x0), readl(rxd + 0x4),
8306 readl(rxd + 0x8), readl(rxd + 0xc));
8307 }
8308
8309 for (i = 0; i < 6; i++) {
8310 unsigned long rxd;
8311
8312 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8313 + (i * sizeof(struct tg3_rx_buffer_desc));
8314 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8315 i,
8316 readl(rxd + 0x0), readl(rxd + 0x4),
8317 readl(rxd + 0x8), readl(rxd + 0xc));
8318 rxd += (4 * sizeof(u32));
8319 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8320 i,
8321 readl(rxd + 0x0), readl(rxd + 0x4),
8322 readl(rxd + 0x8), readl(rxd + 0xc));
8323 }
8324}
8325#endif
8326
8327static struct net_device_stats *tg3_get_stats(struct net_device *);
8328static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8329
8330static int tg3_close(struct net_device *dev)
8331{
4f125f42 8332 int i;
1da177e4
LT		 8333 struct tg3 *tp = netdev_priv(dev);
8334
8ef0442f 8335 napi_disable(&tp->napi[0].napi);
28e53bdd 8336 cancel_work_sync(&tp->reset_task);
7faa006f 8337
1da177e4
LT		 8338 netif_stop_queue(dev);
8339
8340 del_timer_sync(&tp->timer);
8341
f47c11ee 8342 tg3_full_lock(tp, 1);
1da177e4
LT		 8343#if 0
8344 tg3_dump_state(tp);
8345#endif
8346
8347 tg3_disable_ints(tp);
8348
944d980e 8349 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8350 tg3_free_rings(tp);
5cf64b8a 8351 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8352
f47c11ee 8353 tg3_full_unlock(tp);
1da177e4 8354
4f125f42
MC		 8355 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8356 struct tg3_napi *tnapi = &tp->napi[i];
8357 free_irq(tnapi->irq_vec, tnapi);
8358 }
07b0173c
MC		 8359
8360 tg3_ints_fini(tp);
1da177e4
LT		 8361
8362 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8363 sizeof(tp->net_stats_prev));
8364 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8365 sizeof(tp->estats_prev));
8366
8367 tg3_free_consistent(tp);
8368
bc1c7567
MC		 8369 tg3_set_power_state(tp, PCI_D3hot);
8370
8371 netif_carrier_off(tp->dev);
8372
1da177e4
LT		 8373 return 0;
8374}
8375
8376static inline unsigned long get_stat64(tg3_stat64_t *val)
8377{
8378 unsigned long ret;
8379
8380#if (BITS_PER_LONG == 32)
8381 ret = val->low;
8382#else
8383 ret = ((u64)val->high << 32) | ((u64)val->low);
8384#endif
8385 return ret;
8386}
8387
816f8b86
SB		 8388static inline u64 get_estat64(tg3_stat64_t *val)
8389{
8390 return ((u64)val->high << 32) | ((u64)val->low);
8391}
8392
1da177e4
LT		 8393static unsigned long calc_crc_errors(struct tg3 *tp)
8394{
8395 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8396
8397 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8398 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8400 u32 val;
8401
f47c11ee 8402 spin_lock_bh(&tp->lock);
569a5df8
MC		 8403 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8404 tg3_writephy(tp, MII_TG3_TEST1,
8405 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8406 tg3_readphy(tp, 0x14, &val);
8407 } else
8408 val = 0;
f47c11ee 8409 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8410
8411 tp->phy_crc_errors += val;
8412
8413 return tp->phy_crc_errors;
8414 }
8415
8416 return get_stat64(&hw_stats->rx_fcs_errors);
8417}
8418
8419#define ESTAT_ADD(member) \
8420 estats->member = old_estats->member + \
816f8b86 8421 get_estat64(&hw_stats->member)
1da177e4
LT		 8422
8423static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8424{
8425 struct tg3_ethtool_stats *estats = &tp->estats;
8426 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8427 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8428
8429 if (!hw_stats)
8430 return old_estats;
8431
8432 ESTAT_ADD(rx_octets);
8433 ESTAT_ADD(rx_fragments);
8434 ESTAT_ADD(rx_ucast_packets);
8435 ESTAT_ADD(rx_mcast_packets);
8436 ESTAT_ADD(rx_bcast_packets);
8437 ESTAT_ADD(rx_fcs_errors);
8438 ESTAT_ADD(rx_align_errors);
8439 ESTAT_ADD(rx_xon_pause_rcvd);
8440 ESTAT_ADD(rx_xoff_pause_rcvd);
8441 ESTAT_ADD(rx_mac_ctrl_rcvd);
8442 ESTAT_ADD(rx_xoff_entered);
8443 ESTAT_ADD(rx_frame_too_long_errors);
8444 ESTAT_ADD(rx_jabbers);
8445 ESTAT_ADD(rx_undersize_packets);
8446 ESTAT_ADD(rx_in_length_errors);
8447 ESTAT_ADD(rx_out_length_errors);
8448 ESTAT_ADD(rx_64_or_less_octet_packets);
8449 ESTAT_ADD(rx_65_to_127_octet_packets);
8450 ESTAT_ADD(rx_128_to_255_octet_packets);
8451 ESTAT_ADD(rx_256_to_511_octet_packets);
8452 ESTAT_ADD(rx_512_to_1023_octet_packets);
8453 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8454 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8455 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8456 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8457 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8458
8459 ESTAT_ADD(tx_octets);
8460 ESTAT_ADD(tx_collisions);
8461 ESTAT_ADD(tx_xon_sent);
8462 ESTAT_ADD(tx_xoff_sent);
8463 ESTAT_ADD(tx_flow_control);
8464 ESTAT_ADD(tx_mac_errors);
8465 ESTAT_ADD(tx_single_collisions);
8466 ESTAT_ADD(tx_mult_collisions);
8467 ESTAT_ADD(tx_deferred);
8468 ESTAT_ADD(tx_excessive_collisions);
8469 ESTAT_ADD(tx_late_collisions);
8470 ESTAT_ADD(tx_collide_2times);
8471 ESTAT_ADD(tx_collide_3times);
8472 ESTAT_ADD(tx_collide_4times);
8473 ESTAT_ADD(tx_collide_5times);
8474 ESTAT_ADD(tx_collide_6times);
8475 ESTAT_ADD(tx_collide_7times);
8476 ESTAT_ADD(tx_collide_8times);
8477 ESTAT_ADD(tx_collide_9times);
8478 ESTAT_ADD(tx_collide_10times);
8479 ESTAT_ADD(tx_collide_11times);
8480 ESTAT_ADD(tx_collide_12times);
8481 ESTAT_ADD(tx_collide_13times);
8482 ESTAT_ADD(tx_collide_14times);
8483 ESTAT_ADD(tx_collide_15times);
8484 ESTAT_ADD(tx_ucast_packets);
8485 ESTAT_ADD(tx_mcast_packets);
8486 ESTAT_ADD(tx_bcast_packets);
8487 ESTAT_ADD(tx_carrier_sense_errors);
8488 ESTAT_ADD(tx_discards);
8489 ESTAT_ADD(tx_errors);
8490
8491 ESTAT_ADD(dma_writeq_full);
8492 ESTAT_ADD(dma_write_prioq_full);
8493 ESTAT_ADD(rxbds_empty);
8494 ESTAT_ADD(rx_discards);
8495 ESTAT_ADD(rx_errors);
8496 ESTAT_ADD(rx_threshold_hit);
8497
8498 ESTAT_ADD(dma_readq_full);
8499 ESTAT_ADD(dma_read_prioq_full);
8500 ESTAT_ADD(tx_comp_queue_full);
8501
8502 ESTAT_ADD(ring_set_send_prod_index);
8503 ESTAT_ADD(ring_status_update);
8504 ESTAT_ADD(nic_irqs);
8505 ESTAT_ADD(nic_avoided_irqs);
8506 ESTAT_ADD(nic_tx_threshold_hit);
8507
8508 return estats;
8509}
8510
8511static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8512{
8513 struct tg3 *tp = netdev_priv(dev);
8514 struct net_device_stats *stats = &tp->net_stats;
8515 struct net_device_stats *old_stats = &tp->net_stats_prev;
8516 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8517
8518 if (!hw_stats)
8519 return old_stats;
8520
8521 stats->rx_packets = old_stats->rx_packets +
8522 get_stat64(&hw_stats->rx_ucast_packets) +
8523 get_stat64(&hw_stats->rx_mcast_packets) +
8524 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8525
1da177e4
LT		 8526 stats->tx_packets = old_stats->tx_packets +
8527 get_stat64(&hw_stats->tx_ucast_packets) +
8528 get_stat64(&hw_stats->tx_mcast_packets) +
8529 get_stat64(&hw_stats->tx_bcast_packets);
8530
8531 stats->rx_bytes = old_stats->rx_bytes +
8532 get_stat64(&hw_stats->rx_octets);
8533 stats->tx_bytes = old_stats->tx_bytes +
8534 get_stat64(&hw_stats->tx_octets);
8535
8536 stats->rx_errors = old_stats->rx_errors +
4f63b877 8537 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8538 stats->tx_errors = old_stats->tx_errors +
8539 get_stat64(&hw_stats->tx_errors) +
8540 get_stat64(&hw_stats->tx_mac_errors) +
8541 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8542 get_stat64(&hw_stats->tx_discards);
8543
8544 stats->multicast = old_stats->multicast +
8545 get_stat64(&hw_stats->rx_mcast_packets);
8546 stats->collisions = old_stats->collisions +
8547 get_stat64(&hw_stats->tx_collisions);
8548
8549 stats->rx_length_errors = old_stats->rx_length_errors +
8550 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8551 get_stat64(&hw_stats->rx_undersize_packets);
8552
8553 stats->rx_over_errors = old_stats->rx_over_errors +
8554 get_stat64(&hw_stats->rxbds_empty);
8555 stats->rx_frame_errors = old_stats->rx_frame_errors +
8556 get_stat64(&hw_stats->rx_align_errors);
8557 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8558 get_stat64(&hw_stats->tx_discards);
8559 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8560 get_stat64(&hw_stats->tx_carrier_sense_errors);
8561
8562 stats->rx_crc_errors = old_stats->rx_crc_errors +
8563 calc_crc_errors(tp);
8564
4f63b877
JL		 8565 stats->rx_missed_errors = old_stats->rx_missed_errors +
8566 get_stat64(&hw_stats->rx_discards);
8567
1da177e4
LT		 8568 return stats;
8569}
8570
8571static inline u32 calc_crc(unsigned char *buf, int len)
8572{
8573 u32 reg;
8574 u32 tmp;
8575 int j, k;
8576
8577 reg = 0xffffffff;
8578
8579 for (j = 0; j < len; j++) {
8580 reg ^= buf[j];
8581
8582 for (k = 0; k < 8; k++) {
8583 tmp = reg & 0x01;
8584
8585 reg >>= 1;
8586
8587 if (tmp) {
8588 reg ^= 0xedb88320;
8589 }
8590 }
8591 }
8592
8593 return ~reg;
8594}
8595
8596static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8597{
8598 /* accept or reject all multicast frames */
8599 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8600 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8601 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8602 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8603}
8604
8605static void __tg3_set_rx_mode(struct net_device *dev)
8606{
8607 struct tg3 *tp = netdev_priv(dev);
8608 u32 rx_mode;
8609
8610 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8611 RX_MODE_KEEP_VLAN_TAG);
8612
8613 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8614 * flag clear.
8615 */
8616#if TG3_VLAN_TAG_USED
8617 if (!tp->vlgrp &&
8618 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8619 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8620#else
8621 /* By definition, VLAN is disabled always in this
8622 * case.
8623 */
8624 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8625 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8626#endif
8627
8628 if (dev->flags & IFF_PROMISC) {
8629 /* Promiscuous mode. */
8630 rx_mode |= RX_MODE_PROMISC;
8631 } else if (dev->flags & IFF_ALLMULTI) {
8632 /* Accept all multicast. */
8633 tg3_set_multi (tp, 1);
8634 } else if (dev->mc_count < 1) {
8635 /* Reject all multicast. */
8636 tg3_set_multi (tp, 0);
8637 } else {
8638 /* Accept one or more multicast(s). */
8639 struct dev_mc_list *mclist;
8640 unsigned int i;
8641 u32 mc_filter[4] = { 0, };
8642 u32 regidx;
8643 u32 bit;
8644 u32 crc;
8645
8646 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8647 i++, mclist = mclist->next) {
8648
8649 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8650 bit = ~crc & 0x7f;
8651 regidx = (bit & 0x60) >> 5;
8652 bit &= 0x1f;
8653 mc_filter[regidx] |= (1 << bit);
8654 }
8655
8656 tw32(MAC_HASH_REG_0, mc_filter[0]);
8657 tw32(MAC_HASH_REG_1, mc_filter[1]);
8658 tw32(MAC_HASH_REG_2, mc_filter[2]);
8659 tw32(MAC_HASH_REG_3, mc_filter[3]);
8660 }
8661
8662 if (rx_mode != tp->rx_mode) {
8663 tp->rx_mode = rx_mode;
8664 tw32_f(MAC_RX_MODE, rx_mode);
8665 udelay(10);
8666 }
8667}
8668
8669static void tg3_set_rx_mode(struct net_device *dev)
8670{
8671 struct tg3 *tp = netdev_priv(dev);
8672
e75f7c90
MC		 8673 if (!netif_running(dev))
8674 return;
8675
f47c11ee 8676 tg3_full_lock(tp, 0);
1da177e4 8677 __tg3_set_rx_mode(dev);
f47c11ee 8678 tg3_full_unlock(tp);
1da177e4
LT		 8679}
8680
8681#define TG3_REGDUMP_LEN (32 * 1024)
8682
8683static int tg3_get_regs_len(struct net_device *dev)
8684{
8685 return TG3_REGDUMP_LEN;
8686}
8687
8688static void tg3_get_regs(struct net_device *dev,
8689 struct ethtool_regs *regs, void *_p)
8690{
8691 u32 *p = _p;
8692 struct tg3 *tp = netdev_priv(dev);
8693 u8 *orig_p = _p;
8694 int i;
8695
8696 regs->version = 0;
8697
8698 memset(p, 0, TG3_REGDUMP_LEN);
8699
bc1c7567
MC		 8700 if (tp->link_config.phy_is_low_power)
8701 return;
8702
f47c11ee 8703 tg3_full_lock(tp, 0);
1da177e4
LT		 8704
8705#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8706#define GET_REG32_LOOP(base,len) \
8707do { p = (u32 *)(orig_p + (base)); \
8708 for (i = 0; i < len; i += 4) \
8709 __GET_REG32((base) + i); \
8710} while (0)
8711#define GET_REG32_1(reg) \
8712do { p = (u32 *)(orig_p + (reg)); \
8713 __GET_REG32((reg)); \
8714} while (0)
8715
8716 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8717 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8718 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8719 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8720 GET_REG32_1(SNDDATAC_MODE);
8721 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8722 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8723 GET_REG32_1(SNDBDC_MODE);
8724 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8725 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8726 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8727 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8728 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8729 GET_REG32_1(RCVDCC_MODE);
8730 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8731 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8732 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8733 GET_REG32_1(MBFREE_MODE);
8734 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8735 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8736 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8737 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8738 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8739 GET_REG32_1(RX_CPU_MODE);
8740 GET_REG32_1(RX_CPU_STATE);
8741 GET_REG32_1(RX_CPU_PGMCTR);
8742 GET_REG32_1(RX_CPU_HWBKPT);
8743 GET_REG32_1(TX_CPU_MODE);
8744 GET_REG32_1(TX_CPU_STATE);
8745 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8746 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8747 GET_REG32_LOOP(FTQ_RESET, 0x120);
8748 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8749 GET_REG32_1(DMAC_MODE);
8750 GET_REG32_LOOP(GRC_MODE, 0x4c);
8751 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8752 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8753
8754#undef __GET_REG32
8755#undef GET_REG32_LOOP
8756#undef GET_REG32_1
8757
f47c11ee 8758 tg3_full_unlock(tp);
1da177e4
LT		 8759}
8760
8761static int tg3_get_eeprom_len(struct net_device *dev)
8762{
8763 struct tg3 *tp = netdev_priv(dev);
8764
8765 return tp->nvram_size;
8766}
8767
1da177e4
LT		 8768static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8769{
8770 struct tg3 *tp = netdev_priv(dev);
8771 int ret;
8772 u8 *pd;
b9fc7dc5 8773 u32 i, offset, len, b_offset, b_count;
a9dc529d 8774 __be32 val;
1da177e4 8775
df259d8c
MC		 8776 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8777 return -EINVAL;
8778
bc1c7567
MC		 8779 if (tp->link_config.phy_is_low_power)
8780 return -EAGAIN;
8781
1da177e4
LT		 8782 offset = eeprom->offset;
8783 len = eeprom->len;
8784 eeprom->len = 0;
8785
8786 eeprom->magic = TG3_EEPROM_MAGIC;
8787
8788 if (offset & 3) {
8789 /* adjustments to start on required 4 byte boundary */
8790 b_offset = offset & 3;
8791 b_count = 4 - b_offset;
8792 if (b_count > len) {
8793 /* i.e. offset=1 len=2 */
8794 b_count = len;
8795 }
a9dc529d 8796 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8797 if (ret)
8798 return ret;
1da177e4
LT		 8799 memcpy(data, ((char*)&val) + b_offset, b_count);
8800 len -= b_count;
8801 offset += b_count;
8802 eeprom->len += b_count;
8803 }
8804
8805 /* read bytes upto the last 4 byte boundary */
8806 pd = &data[eeprom->len];
8807 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8808 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8809 if (ret) {
8810 eeprom->len += i;
8811 return ret;
8812 }
1da177e4
LT		 8813 memcpy(pd + i, &val, 4);
8814 }
8815 eeprom->len += i;
8816
8817 if (len & 3) {
8818 /* read last bytes not ending on 4 byte boundary */
8819 pd = &data[eeprom->len];
8820 b_count = len & 3;
8821 b_offset = offset + len - b_count;
a9dc529d 8822 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8823 if (ret)
8824 return ret;
b9fc7dc5 8825 memcpy(pd, &val, b_count);
1da177e4
LT		 8826 eeprom->len += b_count;
8827 }
8828 return 0;
8829}
8830
6aa20a22 8831static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8832
8833static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8834{
8835 struct tg3 *tp = netdev_priv(dev);
8836 int ret;
b9fc7dc5 8837 u32 offset, len, b_offset, odd_len;
1da177e4 8838 u8 *buf;
a9dc529d 8839 __be32 start, end;
1da177e4 8840
bc1c7567
MC		 8841 if (tp->link_config.phy_is_low_power)
8842 return -EAGAIN;
8843
df259d8c
MC		 8844 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8845 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 8846 return -EINVAL;
8847
8848 offset = eeprom->offset;
8849 len = eeprom->len;
8850
8851 if ((b_offset = (offset & 3))) {
8852 /* adjustments to start on required 4 byte boundary */
a9dc529d 8853 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8854 if (ret)
8855 return ret;
1da177e4
LT		 8856 len += b_offset;
8857 offset &= ~3;
1c8594b4
MC		 8858 if (len < 4)
8859 len = 4;
1da177e4
LT		 8860 }
8861
8862 odd_len = 0;
1c8594b4 8863 if (len & 3) {
1da177e4
LT		 8864 /* adjustments to end on required 4 byte boundary */
8865 odd_len = 1;
8866 len = (len + 3) & ~3;
a9dc529d 8867 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8868 if (ret)
8869 return ret;
1da177e4
LT		 8870 }
8871
8872 buf = data;
8873 if (b_offset || odd_len) {
8874 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8875 if (!buf)
1da177e4
LT		 8876 return -ENOMEM;
8877 if (b_offset)
8878 memcpy(buf, &start, 4);
8879 if (odd_len)
8880 memcpy(buf+len-4, &end, 4);
8881 memcpy(buf + b_offset, data, eeprom->len);
8882 }
8883
8884 ret = tg3_nvram_write_block(tp, offset, len, buf);
8885
8886 if (buf != data)
8887 kfree(buf);
8888
8889 return ret;
8890}
8891
8892static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8893{
b02fd9e3
MC		 8894 struct tg3 *tp = netdev_priv(dev);
8895
8896 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8897 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8898 return -EAGAIN;
298cf9be 8899 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8900 }
6aa20a22 8901
1da177e4
LT		 8902 cmd->supported = (SUPPORTED_Autoneg);
8903
8904 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8905 cmd->supported |= (SUPPORTED_1000baseT_Half |
8906 SUPPORTED_1000baseT_Full);
8907
ef348144 8908 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8909 cmd->supported |= (SUPPORTED_100baseT_Half |
8910 SUPPORTED_100baseT_Full |
8911 SUPPORTED_10baseT_Half |
8912 SUPPORTED_10baseT_Full |
3bebab59 8913 SUPPORTED_TP);
ef348144
KK		 8914 cmd->port = PORT_TP;
8915 } else {
1da177e4 8916 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8917 cmd->port = PORT_FIBRE;
8918 }
6aa20a22 8919
1da177e4
LT		 8920 cmd->advertising = tp->link_config.advertising;
8921 if (netif_running(dev)) {
8922 cmd->speed = tp->link_config.active_speed;
8923 cmd->duplex = tp->link_config.active_duplex;
8924 }
1da177e4 8925 cmd->phy_address = PHY_ADDR;
7e5856bd 8926 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8927 cmd->autoneg = tp->link_config.autoneg;
8928 cmd->maxtxpkt = 0;
8929 cmd->maxrxpkt = 0;
8930 return 0;
8931}
6aa20a22 8932
1da177e4
LT		 8933static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8934{
8935 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8936
b02fd9e3
MC		 8937 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8938 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8939 return -EAGAIN;
298cf9be 8940 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8941 }
8942
7e5856bd
MC		 8943 if (cmd->autoneg != AUTONEG_ENABLE &&
8944 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8945 return -EINVAL;
7e5856bd
MC		 8946
8947 if (cmd->autoneg == AUTONEG_DISABLE &&
8948 cmd->duplex != DUPLEX_FULL &&
8949 cmd->duplex != DUPLEX_HALF)
37ff238d 8950 return -EINVAL;
1da177e4 8951
7e5856bd
MC		 8952 if (cmd->autoneg == AUTONEG_ENABLE) {
8953 u32 mask = ADVERTISED_Autoneg |
8954 ADVERTISED_Pause |
8955 ADVERTISED_Asym_Pause;
8956
8957 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8958 mask |= ADVERTISED_1000baseT_Half |
8959 ADVERTISED_1000baseT_Full;
8960
8961 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8962 mask |= ADVERTISED_100baseT_Half |
8963 ADVERTISED_100baseT_Full |
8964 ADVERTISED_10baseT_Half |
8965 ADVERTISED_10baseT_Full |
8966 ADVERTISED_TP;
8967 else
8968 mask |= ADVERTISED_FIBRE;
8969
8970 if (cmd->advertising & ~mask)
8971 return -EINVAL;
8972
8973 mask &= (ADVERTISED_1000baseT_Half |
8974 ADVERTISED_1000baseT_Full |
8975 ADVERTISED_100baseT_Half |
8976 ADVERTISED_100baseT_Full |
8977 ADVERTISED_10baseT_Half |
8978 ADVERTISED_10baseT_Full);
8979
8980 cmd->advertising &= mask;
8981 } else {
8982 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8983 if (cmd->speed != SPEED_1000)
8984 return -EINVAL;
8985
8986 if (cmd->duplex != DUPLEX_FULL)
8987 return -EINVAL;
8988 } else {
8989 if (cmd->speed != SPEED_100 &&
8990 cmd->speed != SPEED_10)
8991 return -EINVAL;
8992 }
8993 }
8994
f47c11ee 8995 tg3_full_lock(tp, 0);
1da177e4
LT		 8996
8997 tp->link_config.autoneg = cmd->autoneg;
8998 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 8999 tp->link_config.advertising = (cmd->advertising |
9000 ADVERTISED_Autoneg);
1da177e4
LT		 9001 tp->link_config.speed = SPEED_INVALID;
9002 tp->link_config.duplex = DUPLEX_INVALID;
9003 } else {
9004 tp->link_config.advertising = 0;
9005 tp->link_config.speed = cmd->speed;
9006 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9007 }
6aa20a22 9008
24fcad6b
MC		 9009 tp->link_config.orig_speed = tp->link_config.speed;
9010 tp->link_config.orig_duplex = tp->link_config.duplex;
9011 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9012
1da177e4
LT		 9013 if (netif_running(dev))
9014 tg3_setup_phy(tp, 1);
9015
f47c11ee 9016 tg3_full_unlock(tp);
6aa20a22 9017
1da177e4
LT		 9018 return 0;
9019}
6aa20a22 9020
1da177e4
LT		 9021static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9022{
9023 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9024
1da177e4
LT		 9025 strcpy(info->driver, DRV_MODULE_NAME);
9026 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9027 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9028 strcpy(info->bus_info, pci_name(tp->pdev));
9029}
6aa20a22 9030
1da177e4
LT		 9031static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9032{
9033 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9034
12dac075
RW		 9035 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9036 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9037 wol->supported = WAKE_MAGIC;
9038 else
9039 wol->supported = 0;
1da177e4 9040 wol->wolopts = 0;
05ac4cb7
MC		 9041 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9042 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9043 wol->wolopts = WAKE_MAGIC;
9044 memset(&wol->sopass, 0, sizeof(wol->sopass));
9045}
6aa20a22 9046
1da177e4
LT		 9047static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9048{
9049 struct tg3 *tp = netdev_priv(dev);
12dac075 9050 struct device *dp = &tp->pdev->dev;
6aa20a22 9051
1da177e4
LT		 9052 if (wol->wolopts & ~WAKE_MAGIC)
9053 return -EINVAL;
9054 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9055 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9056 return -EINVAL;
6aa20a22 9057
f47c11ee 9058 spin_lock_bh(&tp->lock);
12dac075 9059 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9060 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9061 device_set_wakeup_enable(dp, true);
9062 } else {
1da177e4 9063 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9064 device_set_wakeup_enable(dp, false);
9065 }
f47c11ee 9066 spin_unlock_bh(&tp->lock);
6aa20a22 9067
1da177e4
LT		 9068 return 0;
9069}
6aa20a22 9070
1da177e4
LT		 9071static u32 tg3_get_msglevel(struct net_device *dev)
9072{
9073 struct tg3 *tp = netdev_priv(dev);
9074 return tp->msg_enable;
9075}
6aa20a22 9076
1da177e4
LT		 9077static void tg3_set_msglevel(struct net_device *dev, u32 value)
9078{
9079 struct tg3 *tp = netdev_priv(dev);
9080 tp->msg_enable = value;
9081}
6aa20a22 9082
1da177e4
LT		 9083static int tg3_set_tso(struct net_device *dev, u32 value)
9084{
9085 struct tg3 *tp = netdev_priv(dev);
9086
9087 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9088 if (value)
9089 return -EINVAL;
9090 return 0;
9091 }
027455ad
MC		 9092 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9093 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9094 if (value) {
b0026624 9095 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9097 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9098 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 9099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9101 dev->features |= NETIF_F_TSO_ECN;
9102 } else
9103 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9104 }
1da177e4
LT		 9105 return ethtool_op_set_tso(dev, value);
9106}
6aa20a22 9107
1da177e4
LT		 9108static int tg3_nway_reset(struct net_device *dev)
9109{
9110 struct tg3 *tp = netdev_priv(dev);
1da177e4 9111 int r;
6aa20a22 9112
1da177e4
LT		 9113 if (!netif_running(dev))
9114 return -EAGAIN;
9115
c94e3941
MC		 9116 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9117 return -EINVAL;
9118
b02fd9e3
MC		 9119 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9120 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9121 return -EAGAIN;
298cf9be 9122 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 9123 } else {
9124 u32 bmcr;
9125
9126 spin_lock_bh(&tp->lock);
9127 r = -EINVAL;
9128 tg3_readphy(tp, MII_BMCR, &bmcr);
9129 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9130 ((bmcr & BMCR_ANENABLE) ||
9131 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9132 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9133 BMCR_ANENABLE);
9134 r = 0;
9135 }
9136 spin_unlock_bh(&tp->lock);
1da177e4 9137 }
6aa20a22 9138
1da177e4
LT		 9139 return r;
9140}
6aa20a22 9141
1da177e4
LT		 9142static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9143{
9144 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9145
1da177e4
LT		 9146 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9147 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9148 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9149 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9150 else
9151 ering->rx_jumbo_max_pending = 0;
9152
9153 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9154
9155 ering->rx_pending = tp->rx_pending;
9156 ering->rx_mini_pending = 0;
4f81c32b
MC		 9157 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9158 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9159 else
9160 ering->rx_jumbo_pending = 0;
9161
f3f3f27e 9162 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9163}
6aa20a22 9164
1da177e4
LT		 9165static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9166{
9167 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 9168 int irq_sync = 0, err = 0;
6aa20a22 9169
1da177e4
LT		 9170 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9171 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9172 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9173 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9174 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9175 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9176 return -EINVAL;
6aa20a22 9177
bbe832c0 9178 if (netif_running(dev)) {
b02fd9e3 9179 tg3_phy_stop(tp);
1da177e4 9180 tg3_netif_stop(tp);
bbe832c0
MC		 9181 irq_sync = 1;
9182 }
1da177e4 9183
bbe832c0 9184 tg3_full_lock(tp, irq_sync);
6aa20a22 9185
1da177e4
LT		 9186 tp->rx_pending = ering->rx_pending;
9187
9188 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9189 tp->rx_pending > 63)
9190 tp->rx_pending = 63;
9191 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
f3f3f27e 9192 tp->napi[0].tx_pending = ering->tx_pending;
1da177e4
LT		 9193
9194 if (netif_running(dev)) {
944d980e 9195 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9196 err = tg3_restart_hw(tp, 1);
9197 if (!err)
9198 tg3_netif_start(tp);
1da177e4
LT		 9199 }
9200
f47c11ee 9201 tg3_full_unlock(tp);
6aa20a22 9202
b02fd9e3
MC		 9203 if (irq_sync && !err)
9204 tg3_phy_start(tp);
9205
b9ec6c1b 9206 return err;
1da177e4 9207}
6aa20a22 9208
1da177e4
LT		 9209static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9210{
9211 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9212
1da177e4 9213 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9214
e18ce346 9215 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9216 epause->rx_pause = 1;
9217 else
9218 epause->rx_pause = 0;
9219
e18ce346 9220 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9221 epause->tx_pause = 1;
9222 else
9223 epause->tx_pause = 0;
1da177e4 9224}
6aa20a22 9225
1da177e4
LT		 9226static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9227{
9228 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9229 int err = 0;
6aa20a22 9230
b02fd9e3
MC		 9231 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9232 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9233 return -EAGAIN;
1da177e4 9234
b02fd9e3
MC		 9235 if (epause->autoneg) {
9236 u32 newadv;
9237 struct phy_device *phydev;
f47c11ee 9238
298cf9be 9239 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9240
b02fd9e3
MC		 9241 if (epause->rx_pause) {
9242 if (epause->tx_pause)
9243 newadv = ADVERTISED_Pause;
9244 else
9245 newadv = ADVERTISED_Pause |
9246 ADVERTISED_Asym_Pause;
9247 } else if (epause->tx_pause) {
9248 newadv = ADVERTISED_Asym_Pause;
9249 } else
9250 newadv = 0;
9251
9252 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9253 u32 oldadv = phydev->advertising &
9254 (ADVERTISED_Pause |
9255 ADVERTISED_Asym_Pause);
9256 if (oldadv != newadv) {
9257 phydev->advertising &=
9258 ~(ADVERTISED_Pause |
9259 ADVERTISED_Asym_Pause);
9260 phydev->advertising |= newadv;
9261 err = phy_start_aneg(phydev);
9262 }
9263 } else {
9264 tp->link_config.advertising &=
9265 ~(ADVERTISED_Pause |
9266 ADVERTISED_Asym_Pause);
9267 tp->link_config.advertising |= newadv;
9268 }
9269 } else {
9270 if (epause->rx_pause)
e18ce346 9271 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9272 else
e18ce346 9273 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9274
b02fd9e3 9275 if (epause->tx_pause)
e18ce346 9276 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9277 else
e18ce346 9278 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9279
9280 if (netif_running(dev))
9281 tg3_setup_flow_control(tp, 0, 0);
9282 }
9283 } else {
9284 int irq_sync = 0;
9285
9286 if (netif_running(dev)) {
9287 tg3_netif_stop(tp);
9288 irq_sync = 1;
9289 }
9290
9291 tg3_full_lock(tp, irq_sync);
9292
9293 if (epause->autoneg)
9294 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9295 else
9296 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9297 if (epause->rx_pause)
e18ce346 9298 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9299 else
e18ce346 9300 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9301 if (epause->tx_pause)
e18ce346 9302 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9303 else
e18ce346 9304 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9305
9306 if (netif_running(dev)) {
9307 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9308 err = tg3_restart_hw(tp, 1);
9309 if (!err)
9310 tg3_netif_start(tp);
9311 }
9312
9313 tg3_full_unlock(tp);
9314 }
6aa20a22 9315
b9ec6c1b 9316 return err;
1da177e4 9317}
6aa20a22 9318
1da177e4
LT		 9319static u32 tg3_get_rx_csum(struct net_device *dev)
9320{
9321 struct tg3 *tp = netdev_priv(dev);
9322 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9323}
6aa20a22 9324
1da177e4
LT		 9325static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9326{
9327 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9328
1da177e4
LT		 9329 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9330 if (data != 0)
9331 return -EINVAL;
9332 return 0;
9333 }
6aa20a22 9334
f47c11ee 9335 spin_lock_bh(&tp->lock);
1da177e4
LT		 9336 if (data)
9337 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9338 else
9339 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9340 spin_unlock_bh(&tp->lock);
6aa20a22 9341
1da177e4
LT		 9342 return 0;
9343}
6aa20a22 9344
1da177e4
LT		 9345static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9346{
9347 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9348
1da177e4
LT		 9349 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9350 if (data != 0)
9351 return -EINVAL;
9352 return 0;
9353 }
6aa20a22 9354
321d32a0 9355 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9356 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9357 else
9c27dbdf 9358 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9359
9360 return 0;
9361}
9362
b9f2c044 9363static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9364{
b9f2c044
JG		 9365 switch (sset) {
9366 case ETH_SS_TEST:
9367 return TG3_NUM_TEST;
9368 case ETH_SS_STATS:
9369 return TG3_NUM_STATS;
9370 default:
9371 return -EOPNOTSUPP;
9372 }
4cafd3f5
MC		 9373}
9374
1da177e4
LT		 9375static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9376{
9377 switch (stringset) {
9378 case ETH_SS_STATS:
9379 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9380 break;
4cafd3f5
MC		 9381 case ETH_SS_TEST:
9382 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9383 break;
1da177e4
LT		 9384 default:
9385 WARN_ON(1); /* we need a WARN() */
9386 break;
9387 }
9388}
9389
4009a93d
MC		 9390static int tg3_phys_id(struct net_device *dev, u32 data)
9391{
9392 struct tg3 *tp = netdev_priv(dev);
9393 int i;
9394
9395 if (!netif_running(tp->dev))
9396 return -EAGAIN;
9397
9398 if (data == 0)
759afc31 9399 data = UINT_MAX / 2;
4009a93d
MC		 9400
9401 for (i = 0; i < (data * 2); i++) {
9402 if ((i % 2) == 0)
9403 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9404 LED_CTRL_1000MBPS_ON |
9405 LED_CTRL_100MBPS_ON |
9406 LED_CTRL_10MBPS_ON |
9407 LED_CTRL_TRAFFIC_OVERRIDE |
9408 LED_CTRL_TRAFFIC_BLINK |
9409 LED_CTRL_TRAFFIC_LED);
6aa20a22 9410
4009a93d
MC		 9411 else
9412 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9413 LED_CTRL_TRAFFIC_OVERRIDE);
9414
9415 if (msleep_interruptible(500))
9416 break;
9417 }
9418 tw32(MAC_LED_CTRL, tp->led_ctrl);
9419 return 0;
9420}
9421
1da177e4
LT		 9422static void tg3_get_ethtool_stats (struct net_device *dev,
9423 struct ethtool_stats *estats, u64 *tmp_stats)
9424{
9425 struct tg3 *tp = netdev_priv(dev);
9426 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9427}
9428
566f86ad 9429#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9430#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9431#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9432#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9433#define NVRAM_SELFBOOT_HW_SIZE 0x20
9434#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9435
9436static int tg3_test_nvram(struct tg3 *tp)
9437{
b9fc7dc5 9438 u32 csum, magic;
a9dc529d 9439 __be32 *buf;
ab0049b4 9440 int i, j, k, err = 0, size;
566f86ad 9441
df259d8c
MC		 9442 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9443 return 0;
9444
e4f34110 9445 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9446 return -EIO;
9447
1b27777a
MC		 9448 if (magic == TG3_EEPROM_MAGIC)
9449 size = NVRAM_TEST_SIZE;
b16250e3 9450 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9451 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9452 TG3_EEPROM_SB_FORMAT_1) {
9453 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9454 case TG3_EEPROM_SB_REVISION_0:
9455 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9456 break;
9457 case TG3_EEPROM_SB_REVISION_2:
9458 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9459 break;
9460 case TG3_EEPROM_SB_REVISION_3:
9461 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9462 break;
9463 default:
9464 return 0;
9465 }
9466 } else
1b27777a 9467 return 0;
b16250e3
MC		 9468 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9469 size = NVRAM_SELFBOOT_HW_SIZE;
9470 else
1b27777a
MC		 9471 return -EIO;
9472
9473 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9474 if (buf == NULL)
9475 return -ENOMEM;
9476
1b27777a
MC		 9477 err = -EIO;
9478 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9479 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9480 if (err)
566f86ad 9481 break;
566f86ad 9482 }
1b27777a 9483 if (i < size)
566f86ad
MC		 9484 goto out;
9485
1b27777a 9486 /* Selfboot format */
a9dc529d 9487 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9488 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9489 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9490 u8 *buf8 = (u8 *) buf, csum8 = 0;
9491
b9fc7dc5 9492 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9493 TG3_EEPROM_SB_REVISION_2) {
9494 /* For rev 2, the csum doesn't include the MBA. */
9495 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9496 csum8 += buf8[i];
9497 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9498 csum8 += buf8[i];
9499 } else {
9500 for (i = 0; i < size; i++)
9501 csum8 += buf8[i];
9502 }
1b27777a 9503
ad96b485
AB		 9504 if (csum8 == 0) {
9505 err = 0;
9506 goto out;
9507 }
9508
9509 err = -EIO;
9510 goto out;
1b27777a 9511 }
566f86ad 9512
b9fc7dc5 9513 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9514 TG3_EEPROM_MAGIC_HW) {
9515 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9516 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9517 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9518
9519 /* Separate the parity bits and the data bytes. */
9520 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9521 if ((i == 0) || (i == 8)) {
9522 int l;
9523 u8 msk;
9524
9525 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9526 parity[k++] = buf8[i] & msk;
9527 i++;
9528 }
9529 else if (i == 16) {
9530 int l;
9531 u8 msk;
9532
9533 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9534 parity[k++] = buf8[i] & msk;
9535 i++;
9536
9537 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9538 parity[k++] = buf8[i] & msk;
9539 i++;
9540 }
9541 data[j++] = buf8[i];
9542 }
9543
9544 err = -EIO;
9545 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9546 u8 hw8 = hweight8(data[i]);
9547
9548 if ((hw8 & 0x1) && parity[i])
9549 goto out;
9550 else if (!(hw8 & 0x1) && !parity[i])
9551 goto out;
9552 }
9553 err = 0;
9554 goto out;
9555 }
9556
566f86ad
MC		 9557 /* Bootstrap checksum at offset 0x10 */
9558 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9559 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9560 goto out;
9561
9562 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9563 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9564 if (csum != be32_to_cpu(buf[0xfc/4]))
9565 goto out;
566f86ad
MC		 9566
9567 err = 0;
9568
9569out:
9570 kfree(buf);
9571 return err;
9572}
9573
ca43007a
MC		 9574#define TG3_SERDES_TIMEOUT_SEC 2
9575#define TG3_COPPER_TIMEOUT_SEC 6
9576
9577static int tg3_test_link(struct tg3 *tp)
9578{
9579 int i, max;
9580
9581 if (!netif_running(tp->dev))
9582 return -ENODEV;
9583
4c987487 9584 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9585 max = TG3_SERDES_TIMEOUT_SEC;
9586 else
9587 max = TG3_COPPER_TIMEOUT_SEC;
9588
9589 for (i = 0; i < max; i++) {
9590 if (netif_carrier_ok(tp->dev))
9591 return 0;
9592
9593 if (msleep_interruptible(1000))
9594 break;
9595 }
9596
9597 return -EIO;
9598}
9599
a71116d1 9600/* Only test the commonly used registers */
30ca3e37 9601static int tg3_test_registers(struct tg3 *tp)
a71116d1 9602{
b16250e3 9603 int i, is_5705, is_5750;
a71116d1
MC		 9604 u32 offset, read_mask, write_mask, val, save_val, read_val;
9605 static struct {
9606 u16 offset;
9607 u16 flags;
9608#define TG3_FL_5705 0x1
9609#define TG3_FL_NOT_5705 0x2
9610#define TG3_FL_NOT_5788 0x4
b16250e3 9611#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9612 u32 read_mask;
9613 u32 write_mask;
9614 } reg_tbl[] = {
9615 /* MAC Control Registers */
9616 { MAC_MODE, TG3_FL_NOT_5705,
9617 0x00000000, 0x00ef6f8c },
9618 { MAC_MODE, TG3_FL_5705,
9619 0x00000000, 0x01ef6b8c },
9620 { MAC_STATUS, TG3_FL_NOT_5705,
9621 0x03800107, 0x00000000 },
9622 { MAC_STATUS, TG3_FL_5705,
9623 0x03800100, 0x00000000 },
9624 { MAC_ADDR_0_HIGH, 0x0000,
9625 0x00000000, 0x0000ffff },
9626 { MAC_ADDR_0_LOW, 0x0000,
9627 0x00000000, 0xffffffff },
9628 { MAC_RX_MTU_SIZE, 0x0000,
9629 0x00000000, 0x0000ffff },
9630 { MAC_TX_MODE, 0x0000,
9631 0x00000000, 0x00000070 },
9632 { MAC_TX_LENGTHS, 0x0000,
9633 0x00000000, 0x00003fff },
9634 { MAC_RX_MODE, TG3_FL_NOT_5705,
9635 0x00000000, 0x000007fc },
9636 { MAC_RX_MODE, TG3_FL_5705,
9637 0x00000000, 0x000007dc },
9638 { MAC_HASH_REG_0, 0x0000,
9639 0x00000000, 0xffffffff },
9640 { MAC_HASH_REG_1, 0x0000,
9641 0x00000000, 0xffffffff },
9642 { MAC_HASH_REG_2, 0x0000,
9643 0x00000000, 0xffffffff },
9644 { MAC_HASH_REG_3, 0x0000,
9645 0x00000000, 0xffffffff },
9646
9647 /* Receive Data and Receive BD Initiator Control Registers. */
9648 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9649 0x00000000, 0xffffffff },
9650 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9651 0x00000000, 0xffffffff },
9652 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9653 0x00000000, 0x00000003 },
9654 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9655 0x00000000, 0xffffffff },
9656 { RCVDBDI_STD_BD+0, 0x0000,
9657 0x00000000, 0xffffffff },
9658 { RCVDBDI_STD_BD+4, 0x0000,
9659 0x00000000, 0xffffffff },
9660 { RCVDBDI_STD_BD+8, 0x0000,
9661 0x00000000, 0xffff0002 },
9662 { RCVDBDI_STD_BD+0xc, 0x0000,
9663 0x00000000, 0xffffffff },
6aa20a22 9664
a71116d1
MC		 9665 /* Receive BD Initiator Control Registers. */
9666 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9667 0x00000000, 0xffffffff },
9668 { RCVBDI_STD_THRESH, TG3_FL_5705,
9669 0x00000000, 0x000003ff },
9670 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9671 0x00000000, 0xffffffff },
6aa20a22 9672
a71116d1
MC		 9673 /* Host Coalescing Control Registers. */
9674 { HOSTCC_MODE, TG3_FL_NOT_5705,
9675 0x00000000, 0x00000004 },
9676 { HOSTCC_MODE, TG3_FL_5705,
9677 0x00000000, 0x000000f6 },
9678 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9679 0x00000000, 0xffffffff },
9680 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9681 0x00000000, 0x000003ff },
9682 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9683 0x00000000, 0xffffffff },
9684 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9685 0x00000000, 0x000003ff },
9686 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9687 0x00000000, 0xffffffff },
9688 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9689 0x00000000, 0x000000ff },
9690 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9691 0x00000000, 0xffffffff },
9692 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9693 0x00000000, 0x000000ff },
9694 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9695 0x00000000, 0xffffffff },
9696 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9697 0x00000000, 0xffffffff },
9698 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9699 0x00000000, 0xffffffff },
9700 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9701 0x00000000, 0x000000ff },
9702 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9703 0x00000000, 0xffffffff },
9704 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9705 0x00000000, 0x000000ff },
9706 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9707 0x00000000, 0xffffffff },
9708 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9709 0x00000000, 0xffffffff },
9710 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9711 0x00000000, 0xffffffff },
9712 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9713 0x00000000, 0xffffffff },
9714 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9715 0x00000000, 0xffffffff },
9716 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9717 0xffffffff, 0x00000000 },
9718 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9719 0xffffffff, 0x00000000 },
9720
9721 /* Buffer Manager Control Registers. */
b16250e3 9722 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9723 0x00000000, 0x007fff80 },
b16250e3 9724 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9725 0x00000000, 0x007fffff },
9726 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9727 0x00000000, 0x0000003f },
9728 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9729 0x00000000, 0x000001ff },
9730 { BUFMGR_MB_HIGH_WATER, 0x0000,
9731 0x00000000, 0x000001ff },
9732 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9733 0xffffffff, 0x00000000 },
9734 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9735 0xffffffff, 0x00000000 },
6aa20a22 9736
a71116d1
MC		 9737 /* Mailbox Registers */
9738 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9739 0x00000000, 0x000001ff },
9740 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9741 0x00000000, 0x000001ff },
9742 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9743 0x00000000, 0x000007ff },
9744 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9745 0x00000000, 0x000001ff },
9746
9747 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9748 };
9749
b16250e3
MC		 9750 is_5705 = is_5750 = 0;
9751 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9752 is_5705 = 1;
b16250e3
MC		 9753 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9754 is_5750 = 1;
9755 }
a71116d1
MC		 9756
9757 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9758 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9759 continue;
9760
9761 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9762 continue;
9763
9764 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9765 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9766 continue;
9767
b16250e3
MC		 9768 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9769 continue;
9770
a71116d1
MC		 9771 offset = (u32) reg_tbl[i].offset;
9772 read_mask = reg_tbl[i].read_mask;
9773 write_mask = reg_tbl[i].write_mask;
9774
9775 /* Save the original register content */
9776 save_val = tr32(offset);
9777
9778 /* Determine the read-only value. */
9779 read_val = save_val & read_mask;
9780
9781 /* Write zero to the register, then make sure the read-only bits
9782 * are not changed and the read/write bits are all zeros.
9783 */
9784 tw32(offset, 0);
9785
9786 val = tr32(offset);
9787
9788 /* Test the read-only and read/write bits. */
9789 if (((val & read_mask) != read_val) || (val & write_mask))
9790 goto out;
9791
9792 /* Write ones to all the bits defined by RdMask and WrMask, then
9793 * make sure the read-only bits are not changed and the
9794 * read/write bits are all ones.
9795 */
9796 tw32(offset, read_mask | write_mask);
9797
9798 val = tr32(offset);
9799
9800 /* Test the read-only bits. */
9801 if ((val & read_mask) != read_val)
9802 goto out;
9803
9804 /* Test the read/write bits. */
9805 if ((val & write_mask) != write_mask)
9806 goto out;
9807
9808 tw32(offset, save_val);
9809 }
9810
9811 return 0;
9812
9813out:
9f88f29f
MC		 9814 if (netif_msg_hw(tp))
9815 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9816 offset);
a71116d1
MC		 9817 tw32(offset, save_val);
9818 return -EIO;
9819}
9820
7942e1db
MC		 9821static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9822{
f71e1309 9823 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9824 int i;
9825 u32 j;
9826
e9edda69 9827 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9828 for (j = 0; j < len; j += 4) {
9829 u32 val;
9830
9831 tg3_write_mem(tp, offset + j, test_pattern[i]);
9832 tg3_read_mem(tp, offset + j, &val);
9833 if (val != test_pattern[i])
9834 return -EIO;
9835 }
9836 }
9837 return 0;
9838}
9839
9840static int tg3_test_memory(struct tg3 *tp)
9841{
9842 static struct mem_entry {
9843 u32 offset;
9844 u32 len;
9845 } mem_tbl_570x[] = {
38690194 9846 { 0x00000000, 0x00b50},
7942e1db
MC		 9847 { 0x00002000, 0x1c000},
9848 { 0xffffffff, 0x00000}
9849 }, mem_tbl_5705[] = {
9850 { 0x00000100, 0x0000c},
9851 { 0x00000200, 0x00008},
7942e1db
MC		 9852 { 0x00004000, 0x00800},
9853 { 0x00006000, 0x01000},
9854 { 0x00008000, 0x02000},
9855 { 0x00010000, 0x0e000},
9856 { 0xffffffff, 0x00000}
79f4d13a
MC		 9857 }, mem_tbl_5755[] = {
9858 { 0x00000200, 0x00008},
9859 { 0x00004000, 0x00800},
9860 { 0x00006000, 0x00800},
9861 { 0x00008000, 0x02000},
9862 { 0x00010000, 0x0c000},
9863 { 0xffffffff, 0x00000}
b16250e3
MC		 9864 }, mem_tbl_5906[] = {
9865 { 0x00000200, 0x00008},
9866 { 0x00004000, 0x00400},
9867 { 0x00006000, 0x00400},
9868 { 0x00008000, 0x01000},
9869 { 0x00010000, 0x01000},
9870 { 0xffffffff, 0x00000}
7942e1db
MC		 9871 };
9872 struct mem_entry *mem_tbl;
9873 int err = 0;
9874 int i;
9875
321d32a0
MC		 9876 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9877 mem_tbl = mem_tbl_5755;
9878 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9879 mem_tbl = mem_tbl_5906;
9880 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9881 mem_tbl = mem_tbl_5705;
9882 else
7942e1db
MC		 9883 mem_tbl = mem_tbl_570x;
9884
9885 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9886 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9887 mem_tbl[i].len)) != 0)
9888 break;
9889 }
6aa20a22 9890
7942e1db
MC		 9891 return err;
9892}
9893
9f40dead
MC		 9894#define TG3_MAC_LOOPBACK 0
9895#define TG3_PHY_LOOPBACK 1
9896
9897static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9898{
9f40dead 9899 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 9900 u32 desc_idx, coal_now;
c76949a6
MC		 9901 struct sk_buff *skb, *rx_skb;
9902 u8 *tx_data;
9903 dma_addr_t map;
9904 int num_pkts, tx_len, rx_len, i, err;
9905 struct tg3_rx_buffer_desc *desc;
898a56f8 9906 struct tg3_napi *tnapi, *rnapi;
21f581a5 9907 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 9908
898a56f8
MC		 9909 tnapi = &tp->napi[0];
9910 rnapi = &tp->napi[0];
fd2ce37f 9911 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 9912
9f40dead 9913 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9914 /* HW errata - mac loopback fails in some cases on 5780.
9915 * Normal traffic and PHY loopback are not affected by
9916 * errata.
9917 */
9918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9919 return 0;
9920
9f40dead 9921 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9922 MAC_MODE_PORT_INT_LPBACK;
9923 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9924 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9925 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9926 mac_mode |= MAC_MODE_PORT_MODE_MII;
9927 else
9928 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9929 tw32(MAC_MODE, mac_mode);
9930 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9931 u32 val;
9932
7f97a4bd
MC		 9933 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9934 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 9935 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9936 } else
9937 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9938
9ef8ca99
MC		 9939 tg3_phy_toggle_automdix(tp, 0);
9940
3f7045c1 9941 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9942 udelay(40);
5d64ad34 9943
e8f3f6ca 9944 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 9945 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9947 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 9948 mac_mode |= MAC_MODE_PORT_MODE_MII;
9949 } else
9950 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 9951
c94e3941
MC		 9952 /* reset to prevent losing 1st rx packet intermittently */
9953 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9954 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9955 udelay(10);
9956 tw32_f(MAC_RX_MODE, tp->rx_mode);
9957 }
e8f3f6ca
MC		 9958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9959 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9960 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9961 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9962 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 9963 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9964 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9965 }
9f40dead 9966 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 9967 }
9968 else
9969 return -EINVAL;
c76949a6
MC		 9970
9971 err = -EIO;
9972
c76949a6 9973 tx_len = 1514;
a20e9c62 9974 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 9975 if (!skb)
9976 return -ENOMEM;
9977
c76949a6
MC		 9978 tx_data = skb_put(skb, tx_len);
9979 memcpy(tx_data, tp->dev->dev_addr, 6);
9980 memset(tx_data + 6, 0x0, 8);
9981
9982 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9983
9984 for (i = 14; i < tx_len; i++)
9985 tx_data[i] = (u8) (i & 0xff);
9986
9987 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9988
9989 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 9990 rnapi->coal_now);
c76949a6
MC		 9991
9992 udelay(10);
9993
898a56f8 9994 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 9995
c76949a6
MC		 9996 num_pkts = 0;
9997
f3f3f27e 9998 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 9999
f3f3f27e 10000 tnapi->tx_prod++;
c76949a6
MC		 10001 num_pkts++;
10002
f3f3f27e
MC		 10003 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10004 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10005
10006 udelay(10);
10007
3f7045c1
MC		 10008 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10009 for (i = 0; i < 25; i++) {
c76949a6 10010 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10011 coal_now);
c76949a6
MC		 10012
10013 udelay(10);
10014
898a56f8
MC		 10015 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10016 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10017 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10018 (rx_idx == (rx_start_idx + num_pkts)))
10019 break;
10020 }
10021
10022 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10023 dev_kfree_skb(skb);
10024
f3f3f27e 10025 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10026 goto out;
10027
10028 if (rx_idx != rx_start_idx + num_pkts)
10029 goto out;
10030
72334482 10031 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10032 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10033 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10034 if (opaque_key != RXD_OPAQUE_RING_STD)
10035 goto out;
10036
10037 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10038 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10039 goto out;
10040
10041 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10042 if (rx_len != tx_len)
10043 goto out;
10044
21f581a5 10045 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10046
21f581a5 10047 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10048 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10049
10050 for (i = 14; i < tx_len; i++) {
10051 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10052 goto out;
10053 }
10054 err = 0;
6aa20a22 10055
c76949a6
MC		 10056 /* tg3_free_rings will unmap and free the rx_skb */
10057out:
10058 return err;
10059}
10060
9f40dead
MC		 10061#define TG3_MAC_LOOPBACK_FAILED 1
10062#define TG3_PHY_LOOPBACK_FAILED 2
10063#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10064 TG3_PHY_LOOPBACK_FAILED)
10065
10066static int tg3_test_loopback(struct tg3 *tp)
10067{
10068 int err = 0;
9936bcf6 10069 u32 cpmuctrl = 0;
9f40dead
MC		 10070
10071 if (!netif_running(tp->dev))
10072 return TG3_LOOPBACK_FAILED;
10073
b9ec6c1b
MC		 10074 err = tg3_reset_hw(tp, 1);
10075 if (err)
10076 return TG3_LOOPBACK_FAILED;
9f40dead 10077
6833c043
MC		 10078 /* Turn off gphy autopowerdown. */
10079 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10080 tg3_phy_toggle_apd(tp, false);
10081
321d32a0 10082 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10083 int i;
10084 u32 status;
10085
10086 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10087
10088 /* Wait for up to 40 microseconds to acquire lock. */
10089 for (i = 0; i < 4; i++) {
10090 status = tr32(TG3_CPMU_MUTEX_GNT);
10091 if (status == CPMU_MUTEX_GNT_DRIVER)
10092 break;
10093 udelay(10);
10094 }
10095
10096 if (status != CPMU_MUTEX_GNT_DRIVER)
10097 return TG3_LOOPBACK_FAILED;
10098
b2a5c19c 10099 /* Turn off link-based power management. */
e875093c 10100 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10101 tw32(TG3_CPMU_CTRL,
10102 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10103 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10104 }
10105
9f40dead
MC		 10106 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10107 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10108
321d32a0 10109 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10110 tw32(TG3_CPMU_CTRL, cpmuctrl);
10111
10112 /* Release the mutex */
10113 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10114 }
10115
dd477003
MC		 10116 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10117 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10118 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10119 err |= TG3_PHY_LOOPBACK_FAILED;
10120 }
10121
6833c043
MC		 10122 /* Re-enable gphy autopowerdown. */
10123 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10124 tg3_phy_toggle_apd(tp, true);
10125
9f40dead
MC		 10126 return err;
10127}
10128
4cafd3f5
MC		 10129static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10130 u64 *data)
10131{
566f86ad
MC		 10132 struct tg3 *tp = netdev_priv(dev);
10133
bc1c7567
MC		 10134 if (tp->link_config.phy_is_low_power)
10135 tg3_set_power_state(tp, PCI_D0);
10136
566f86ad
MC		 10137 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10138
10139 if (tg3_test_nvram(tp) != 0) {
10140 etest->flags |= ETH_TEST_FL_FAILED;
10141 data[0] = 1;
10142 }
ca43007a
MC		 10143 if (tg3_test_link(tp) != 0) {
10144 etest->flags |= ETH_TEST_FL_FAILED;
10145 data[1] = 1;
10146 }
a71116d1 10147 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10148 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10149
10150 if (netif_running(dev)) {
b02fd9e3 10151 tg3_phy_stop(tp);
a71116d1 10152 tg3_netif_stop(tp);
bbe832c0
MC		 10153 irq_sync = 1;
10154 }
a71116d1 10155
bbe832c0 10156 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10157
10158 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10159 err = tg3_nvram_lock(tp);
a71116d1
MC		 10160 tg3_halt_cpu(tp, RX_CPU_BASE);
10161 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10162 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10163 if (!err)
10164 tg3_nvram_unlock(tp);
a71116d1 10165
d9ab5ad1
MC		 10166 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10167 tg3_phy_reset(tp);
10168
a71116d1
MC		 10169 if (tg3_test_registers(tp) != 0) {
10170 etest->flags |= ETH_TEST_FL_FAILED;
10171 data[2] = 1;
10172 }
7942e1db
MC		 10173 if (tg3_test_memory(tp) != 0) {
10174 etest->flags |= ETH_TEST_FL_FAILED;
10175 data[3] = 1;
10176 }
9f40dead 10177 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10178 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10179
f47c11ee
DM		 10180 tg3_full_unlock(tp);
10181
d4bc3927
MC		 10182 if (tg3_test_interrupt(tp) != 0) {
10183 etest->flags |= ETH_TEST_FL_FAILED;
10184 data[5] = 1;
10185 }
f47c11ee
DM		 10186
10187 tg3_full_lock(tp, 0);
d4bc3927 10188
a71116d1
MC		 10189 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10190 if (netif_running(dev)) {
10191 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10192 err2 = tg3_restart_hw(tp, 1);
10193 if (!err2)
b9ec6c1b 10194 tg3_netif_start(tp);
a71116d1 10195 }
f47c11ee
DM		 10196
10197 tg3_full_unlock(tp);
b02fd9e3
MC		 10198
10199 if (irq_sync && !err2)
10200 tg3_phy_start(tp);
a71116d1 10201 }
bc1c7567
MC		 10202 if (tp->link_config.phy_is_low_power)
10203 tg3_set_power_state(tp, PCI_D3hot);
10204
4cafd3f5
MC		 10205}
10206
1da177e4
LT		 10207static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10208{
10209 struct mii_ioctl_data *data = if_mii(ifr);
10210 struct tg3 *tp = netdev_priv(dev);
10211 int err;
10212
b02fd9e3
MC		 10213 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10214 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10215 return -EAGAIN;
298cf9be 10216 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10217 }
10218
1da177e4
LT		 10219 switch(cmd) {
10220 case SIOCGMIIPHY:
10221 data->phy_id = PHY_ADDR;
10222
10223 /* fallthru */
10224 case SIOCGMIIREG: {
10225 u32 mii_regval;
10226
10227 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10228 break; /* We have no PHY */
10229
bc1c7567
MC		 10230 if (tp->link_config.phy_is_low_power)
10231 return -EAGAIN;
10232
f47c11ee 10233 spin_lock_bh(&tp->lock);
1da177e4 10234 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10235 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10236
10237 data->val_out = mii_regval;
10238
10239 return err;
10240 }
10241
10242 case SIOCSMIIREG:
10243 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10244 break; /* We have no PHY */
10245
10246 if (!capable(CAP_NET_ADMIN))
10247 return -EPERM;
10248
bc1c7567
MC		 10249 if (tp->link_config.phy_is_low_power)
10250 return -EAGAIN;
10251
f47c11ee 10252 spin_lock_bh(&tp->lock);
1da177e4 10253 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10254 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10255
10256 return err;
10257
10258 default:
10259 /* do nothing */
10260 break;
10261 }
10262 return -EOPNOTSUPP;
10263}
10264
10265#if TG3_VLAN_TAG_USED
10266static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10267{
10268 struct tg3 *tp = netdev_priv(dev);
10269
844b3eed
MC		 10270 if (!netif_running(dev)) {
10271 tp->vlgrp = grp;
10272 return;
10273 }
10274
10275 tg3_netif_stop(tp);
29315e87 10276
f47c11ee 10277 tg3_full_lock(tp, 0);
1da177e4
LT		 10278
10279 tp->vlgrp = grp;
10280
10281 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10282 __tg3_set_rx_mode(dev);
10283
844b3eed 10284 tg3_netif_start(tp);
46966545
MC		 10285
10286 tg3_full_unlock(tp);
1da177e4 10287}
1da177e4
LT		 10288#endif
10289
15f9850d
DM		 10290static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10291{
10292 struct tg3 *tp = netdev_priv(dev);
10293
10294 memcpy(ec, &tp->coal, sizeof(*ec));
10295 return 0;
10296}
10297
d244c892
MC		 10298static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10299{
10300 struct tg3 *tp = netdev_priv(dev);
10301 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10302 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10303
10304 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10305 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10306 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10307 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10308 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10309 }
10310
10311 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10312 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10313 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10314 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10315 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10316 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10317 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10318 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10319 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10320 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10321 return -EINVAL;
10322
10323 /* No rx interrupts will be generated if both are zero */
10324 if ((ec->rx_coalesce_usecs == 0) &&
10325 (ec->rx_max_coalesced_frames == 0))
10326 return -EINVAL;
10327
10328 /* No tx interrupts will be generated if both are zero */
10329 if ((ec->tx_coalesce_usecs == 0) &&
10330 (ec->tx_max_coalesced_frames == 0))
10331 return -EINVAL;
10332
10333 /* Only copy relevant parameters, ignore all others. */
10334 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10335 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10336 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10337 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10338 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10339 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10340 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10341 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10342 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10343
10344 if (netif_running(dev)) {
10345 tg3_full_lock(tp, 0);
10346 __tg3_set_coalesce(tp, &tp->coal);
10347 tg3_full_unlock(tp);
10348 }
10349 return 0;
10350}
10351
7282d491 10352static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10353 .get_settings = tg3_get_settings,
10354 .set_settings = tg3_set_settings,
10355 .get_drvinfo = tg3_get_drvinfo,
10356 .get_regs_len = tg3_get_regs_len,
10357 .get_regs = tg3_get_regs,
10358 .get_wol = tg3_get_wol,
10359 .set_wol = tg3_set_wol,
10360 .get_msglevel = tg3_get_msglevel,
10361 .set_msglevel = tg3_set_msglevel,
10362 .nway_reset = tg3_nway_reset,
10363 .get_link = ethtool_op_get_link,
10364 .get_eeprom_len = tg3_get_eeprom_len,
10365 .get_eeprom = tg3_get_eeprom,
10366 .set_eeprom = tg3_set_eeprom,
10367 .get_ringparam = tg3_get_ringparam,
10368 .set_ringparam = tg3_set_ringparam,
10369 .get_pauseparam = tg3_get_pauseparam,
10370 .set_pauseparam = tg3_set_pauseparam,
10371 .get_rx_csum = tg3_get_rx_csum,
10372 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10373 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10374 .set_sg = ethtool_op_set_sg,
1da177e4 10375 .set_tso = tg3_set_tso,
4cafd3f5 10376 .self_test = tg3_self_test,
1da177e4 10377 .get_strings = tg3_get_strings,
4009a93d 10378 .phys_id = tg3_phys_id,
1da177e4 10379 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10380 .get_coalesce = tg3_get_coalesce,
d244c892 10381 .set_coalesce = tg3_set_coalesce,
b9f2c044 10382 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10383};
10384
10385static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10386{
1b27777a 10387 u32 cursize, val, magic;
1da177e4
LT		 10388
10389 tp->nvram_size = EEPROM_CHIP_SIZE;
10390
e4f34110 10391 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10392 return;
10393
b16250e3
MC		 10394 if ((magic != TG3_EEPROM_MAGIC) &&
10395 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10396 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10397 return;
10398
10399 /*
10400 * Size the chip by reading offsets at increasing powers of two.
10401 * When we encounter our validation signature, we know the addressing
10402 * has wrapped around, and thus have our chip size.
10403 */
1b27777a 10404 cursize = 0x10;
1da177e4
LT		 10405
10406 while (cursize < tp->nvram_size) {
e4f34110 10407 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10408 return;
10409
1820180b 10410 if (val == magic)
1da177e4
LT		 10411 break;
10412
10413 cursize <<= 1;
10414 }
10415
10416 tp->nvram_size = cursize;
10417}
6aa20a22 10418
1da177e4
LT		 10419static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10420{
10421 u32 val;
10422
df259d8c
MC		 10423 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10424 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10425 return;
10426
10427 /* Selfboot format */
1820180b 10428 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10429 tg3_get_eeprom_size(tp);
10430 return;
10431 }
10432
6d348f2c 10433 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10434 if (val != 0) {
6d348f2c
MC		 10435 /* This is confusing. We want to operate on the
10436 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10437 * call will read from NVRAM and byteswap the data
10438 * according to the byteswapping settings for all
10439 * other register accesses. This ensures the data we
10440 * want will always reside in the lower 16-bits.
10441 * However, the data in NVRAM is in LE format, which
10442 * means the data from the NVRAM read will always be
10443 * opposite the endianness of the CPU. The 16-bit
10444 * byteswap then brings the data to CPU endianness.
10445 */
10446 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10447 return;
10448 }
10449 }
fd1122a2 10450 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10451}
10452
10453static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10454{
10455 u32 nvcfg1;
10456
10457 nvcfg1 = tr32(NVRAM_CFG1);
10458 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10459 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10460 } else {
1da177e4
LT		 10461 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10462 tw32(NVRAM_CFG1, nvcfg1);
10463 }
10464
4c987487 10465 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10466 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10467 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10468 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10469 tp->nvram_jedecnum = JEDEC_ATMEL;
10470 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10471 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10472 break;
10473 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10474 tp->nvram_jedecnum = JEDEC_ATMEL;
10475 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10476 break;
10477 case FLASH_VENDOR_ATMEL_EEPROM:
10478 tp->nvram_jedecnum = JEDEC_ATMEL;
10479 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10480 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10481 break;
10482 case FLASH_VENDOR_ST:
10483 tp->nvram_jedecnum = JEDEC_ST;
10484 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10485 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10486 break;
10487 case FLASH_VENDOR_SAIFUN:
10488 tp->nvram_jedecnum = JEDEC_SAIFUN;
10489 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10490 break;
10491 case FLASH_VENDOR_SST_SMALL:
10492 case FLASH_VENDOR_SST_LARGE:
10493 tp->nvram_jedecnum = JEDEC_SST;
10494 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10495 break;
1da177e4 10496 }
8590a603 10497 } else {
1da177e4
LT		 10498 tp->nvram_jedecnum = JEDEC_ATMEL;
10499 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10500 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10501 }
10502}
10503
361b4ac2
MC		 10504static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10505{
10506 u32 nvcfg1;
10507
10508 nvcfg1 = tr32(NVRAM_CFG1);
10509
e6af301b
MC		 10510 /* NVRAM protection for TPM */
10511 if (nvcfg1 & (1 << 27))
10512 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10513
361b4ac2 10514 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10515 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10516 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10517 tp->nvram_jedecnum = JEDEC_ATMEL;
10518 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10519 break;
10520 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10521 tp->nvram_jedecnum = JEDEC_ATMEL;
10522 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10523 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10524 break;
10525 case FLASH_5752VENDOR_ST_M45PE10:
10526 case FLASH_5752VENDOR_ST_M45PE20:
10527 case FLASH_5752VENDOR_ST_M45PE40:
10528 tp->nvram_jedecnum = JEDEC_ST;
10529 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10530 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10531 break;
361b4ac2
MC		 10532 }
10533
10534 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10535 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8590a603
MC		 10536 case FLASH_5752PAGE_SIZE_256:
10537 tp->nvram_pagesize = 256;
10538 break;
10539 case FLASH_5752PAGE_SIZE_512:
10540 tp->nvram_pagesize = 512;
10541 break;
10542 case FLASH_5752PAGE_SIZE_1K:
10543 tp->nvram_pagesize = 1024;
10544 break;
10545 case FLASH_5752PAGE_SIZE_2K:
10546 tp->nvram_pagesize = 2048;
10547 break;
10548 case FLASH_5752PAGE_SIZE_4K:
10549 tp->nvram_pagesize = 4096;
10550 break;
10551 case FLASH_5752PAGE_SIZE_264:
10552 tp->nvram_pagesize = 264;
10553 break;
361b4ac2 10554 }
8590a603 10555 } else {
361b4ac2
MC		 10556 /* For eeprom, set pagesize to maximum eeprom size */
10557 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10558
10559 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10560 tw32(NVRAM_CFG1, nvcfg1);
10561 }
10562}
10563
d3c7b886
MC		 10564static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10565{
989a9d23 10566 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10567
10568 nvcfg1 = tr32(NVRAM_CFG1);
10569
10570 /* NVRAM protection for TPM */
989a9d23 10571 if (nvcfg1 & (1 << 27)) {
d3c7b886 10572 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10573 protect = 1;
10574 }
d3c7b886 10575
989a9d23
MC		 10576 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10577 switch (nvcfg1) {
8590a603
MC		 10578 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10579 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10580 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10581 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10582 tp->nvram_jedecnum = JEDEC_ATMEL;
10583 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10584 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10585 tp->nvram_pagesize = 264;
10586 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10587 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10588 tp->nvram_size = (protect ? 0x3e200 :
10589 TG3_NVRAM_SIZE_512KB);
10590 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10591 tp->nvram_size = (protect ? 0x1f200 :
10592 TG3_NVRAM_SIZE_256KB);
10593 else
10594 tp->nvram_size = (protect ? 0x1f200 :
10595 TG3_NVRAM_SIZE_128KB);
10596 break;
10597 case FLASH_5752VENDOR_ST_M45PE10:
10598 case FLASH_5752VENDOR_ST_M45PE20:
10599 case FLASH_5752VENDOR_ST_M45PE40:
10600 tp->nvram_jedecnum = JEDEC_ST;
10601 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10602 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10603 tp->nvram_pagesize = 256;
10604 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10605 tp->nvram_size = (protect ?
10606 TG3_NVRAM_SIZE_64KB :
10607 TG3_NVRAM_SIZE_128KB);
10608 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10609 tp->nvram_size = (protect ?
10610 TG3_NVRAM_SIZE_64KB :
10611 TG3_NVRAM_SIZE_256KB);
10612 else
10613 tp->nvram_size = (protect ?
10614 TG3_NVRAM_SIZE_128KB :
10615 TG3_NVRAM_SIZE_512KB);
10616 break;
d3c7b886
MC		 10617 }
10618}
10619
1b27777a
MC		 10620static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10621{
10622 u32 nvcfg1;
10623
10624 nvcfg1 = tr32(NVRAM_CFG1);
10625
10626 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10627 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10628 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10629 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10630 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10631 tp->nvram_jedecnum = JEDEC_ATMEL;
10632 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10633 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 10634
8590a603
MC		 10635 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10636 tw32(NVRAM_CFG1, nvcfg1);
10637 break;
10638 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10639 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10640 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10641 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10642 tp->nvram_jedecnum = JEDEC_ATMEL;
10643 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10644 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10645 tp->nvram_pagesize = 264;
10646 break;
10647 case FLASH_5752VENDOR_ST_M45PE10:
10648 case FLASH_5752VENDOR_ST_M45PE20:
10649 case FLASH_5752VENDOR_ST_M45PE40:
10650 tp->nvram_jedecnum = JEDEC_ST;
10651 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10652 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10653 tp->nvram_pagesize = 256;
10654 break;
1b27777a
MC		 10655 }
10656}
10657
6b91fa02
MC		 10658static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10659{
10660 u32 nvcfg1, protect = 0;
10661
10662 nvcfg1 = tr32(NVRAM_CFG1);
10663
10664 /* NVRAM protection for TPM */
10665 if (nvcfg1 & (1 << 27)) {
10666 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10667 protect = 1;
10668 }
10669
10670 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10671 switch (nvcfg1) {
8590a603
MC		 10672 case FLASH_5761VENDOR_ATMEL_ADB021D:
10673 case FLASH_5761VENDOR_ATMEL_ADB041D:
10674 case FLASH_5761VENDOR_ATMEL_ADB081D:
10675 case FLASH_5761VENDOR_ATMEL_ADB161D:
10676 case FLASH_5761VENDOR_ATMEL_MDB021D:
10677 case FLASH_5761VENDOR_ATMEL_MDB041D:
10678 case FLASH_5761VENDOR_ATMEL_MDB081D:
10679 case FLASH_5761VENDOR_ATMEL_MDB161D:
10680 tp->nvram_jedecnum = JEDEC_ATMEL;
10681 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10682 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10683 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10684 tp->nvram_pagesize = 256;
10685 break;
10686 case FLASH_5761VENDOR_ST_A_M45PE20:
10687 case FLASH_5761VENDOR_ST_A_M45PE40:
10688 case FLASH_5761VENDOR_ST_A_M45PE80:
10689 case FLASH_5761VENDOR_ST_A_M45PE16:
10690 case FLASH_5761VENDOR_ST_M_M45PE20:
10691 case FLASH_5761VENDOR_ST_M_M45PE40:
10692 case FLASH_5761VENDOR_ST_M_M45PE80:
10693 case FLASH_5761VENDOR_ST_M_M45PE16:
10694 tp->nvram_jedecnum = JEDEC_ST;
10695 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10696 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10697 tp->nvram_pagesize = 256;
10698 break;
6b91fa02
MC		 10699 }
10700
10701 if (protect) {
10702 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10703 } else {
10704 switch (nvcfg1) {
8590a603
MC		 10705 case FLASH_5761VENDOR_ATMEL_ADB161D:
10706 case FLASH_5761VENDOR_ATMEL_MDB161D:
10707 case FLASH_5761VENDOR_ST_A_M45PE16:
10708 case FLASH_5761VENDOR_ST_M_M45PE16:
10709 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10710 break;
10711 case FLASH_5761VENDOR_ATMEL_ADB081D:
10712 case FLASH_5761VENDOR_ATMEL_MDB081D:
10713 case FLASH_5761VENDOR_ST_A_M45PE80:
10714 case FLASH_5761VENDOR_ST_M_M45PE80:
10715 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10716 break;
10717 case FLASH_5761VENDOR_ATMEL_ADB041D:
10718 case FLASH_5761VENDOR_ATMEL_MDB041D:
10719 case FLASH_5761VENDOR_ST_A_M45PE40:
10720 case FLASH_5761VENDOR_ST_M_M45PE40:
10721 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10722 break;
10723 case FLASH_5761VENDOR_ATMEL_ADB021D:
10724 case FLASH_5761VENDOR_ATMEL_MDB021D:
10725 case FLASH_5761VENDOR_ST_A_M45PE20:
10726 case FLASH_5761VENDOR_ST_M_M45PE20:
10727 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10728 break;
6b91fa02
MC		 10729 }
10730 }
10731}
10732
b5d3772c
MC		 10733static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10734{
10735 tp->nvram_jedecnum = JEDEC_ATMEL;
10736 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10737 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10738}
10739
321d32a0
MC		 10740static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10741{
10742 u32 nvcfg1;
10743
10744 nvcfg1 = tr32(NVRAM_CFG1);
10745
10746 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10747 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10748 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10749 tp->nvram_jedecnum = JEDEC_ATMEL;
10750 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10751 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10752
10753 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10754 tw32(NVRAM_CFG1, nvcfg1);
10755 return;
10756 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10757 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10758 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10759 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10760 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10761 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10762 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10763 tp->nvram_jedecnum = JEDEC_ATMEL;
10764 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10765 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10766
10767 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10768 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10769 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10770 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10771 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10772 break;
10773 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10774 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10775 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10776 break;
10777 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10778 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10779 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10780 break;
10781 }
10782 break;
10783 case FLASH_5752VENDOR_ST_M45PE10:
10784 case FLASH_5752VENDOR_ST_M45PE20:
10785 case FLASH_5752VENDOR_ST_M45PE40:
10786 tp->nvram_jedecnum = JEDEC_ST;
10787 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10788 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10789
10790 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10791 case FLASH_5752VENDOR_ST_M45PE10:
10792 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10793 break;
10794 case FLASH_5752VENDOR_ST_M45PE20:
10795 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10796 break;
10797 case FLASH_5752VENDOR_ST_M45PE40:
10798 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10799 break;
10800 }
10801 break;
10802 default:
df259d8c 10803 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 10804 return;
10805 }
10806
10807 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10808 case FLASH_5752PAGE_SIZE_256:
10809 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10810 tp->nvram_pagesize = 256;
10811 break;
10812 case FLASH_5752PAGE_SIZE_512:
10813 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10814 tp->nvram_pagesize = 512;
10815 break;
10816 case FLASH_5752PAGE_SIZE_1K:
10817 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10818 tp->nvram_pagesize = 1024;
10819 break;
10820 case FLASH_5752PAGE_SIZE_2K:
10821 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10822 tp->nvram_pagesize = 2048;
10823 break;
10824 case FLASH_5752PAGE_SIZE_4K:
10825 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10826 tp->nvram_pagesize = 4096;
10827 break;
10828 case FLASH_5752PAGE_SIZE_264:
10829 tp->nvram_pagesize = 264;
10830 break;
10831 case FLASH_5752PAGE_SIZE_528:
10832 tp->nvram_pagesize = 528;
10833 break;
10834 }
10835}
10836
1da177e4
LT		 10837/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10838static void __devinit tg3_nvram_init(struct tg3 *tp)
10839{
1da177e4
LT		 10840 tw32_f(GRC_EEPROM_ADDR,
10841 (EEPROM_ADDR_FSM_RESET |
10842 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10843 EEPROM_ADDR_CLKPERD_SHIFT)));
10844
9d57f01c 10845 msleep(1);
1da177e4
LT		 10846
10847 /* Enable seeprom accesses. */
10848 tw32_f(GRC_LOCAL_CTRL,
10849 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10850 udelay(100);
10851
10852 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10853 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10854 tp->tg3_flags |= TG3_FLAG_NVRAM;
10855
ec41c7df
MC		 10856 if (tg3_nvram_lock(tp)) {
10857 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10858 "tg3_nvram_init failed.\n", tp->dev->name);
10859 return;
10860 }
e6af301b 10861 tg3_enable_nvram_access(tp);
1da177e4 10862
989a9d23
MC		 10863 tp->nvram_size = 0;
10864
361b4ac2
MC		 10865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10866 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10867 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10868 tg3_get_5755_nvram_info(tp);
d30cdd28 10869 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10870 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10871 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10872 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10873 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10874 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10875 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10876 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10877 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10878 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10879 else
10880 tg3_get_nvram_info(tp);
10881
989a9d23
MC		 10882 if (tp->nvram_size == 0)
10883 tg3_get_nvram_size(tp);
1da177e4 10884
e6af301b 10885 tg3_disable_nvram_access(tp);
381291b7 10886 tg3_nvram_unlock(tp);
1da177e4
LT		 10887
10888 } else {
10889 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10890
10891 tg3_get_eeprom_size(tp);
10892 }
10893}
10894
1da177e4
LT		 10895static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10896 u32 offset, u32 len, u8 *buf)
10897{
10898 int i, j, rc = 0;
10899 u32 val;
10900
10901 for (i = 0; i < len; i += 4) {
b9fc7dc5 10902 u32 addr;
a9dc529d 10903 __be32 data;
1da177e4
LT		 10904
10905 addr = offset + i;
10906
10907 memcpy(&data, buf + i, 4);
10908
62cedd11
MC		 10909 /*
10910 * The SEEPROM interface expects the data to always be opposite
10911 * the native endian format. We accomplish this by reversing
10912 * all the operations that would have been performed on the
10913 * data from a call to tg3_nvram_read_be32().
10914 */
10915 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10916
10917 val = tr32(GRC_EEPROM_ADDR);
10918 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10919
10920 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10921 EEPROM_ADDR_READ);
10922 tw32(GRC_EEPROM_ADDR, val |
10923 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10924 (addr & EEPROM_ADDR_ADDR_MASK) |
10925 EEPROM_ADDR_START |
10926 EEPROM_ADDR_WRITE);
6aa20a22 10927
9d57f01c 10928 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10929 val = tr32(GRC_EEPROM_ADDR);
10930
10931 if (val & EEPROM_ADDR_COMPLETE)
10932 break;
9d57f01c 10933 msleep(1);
1da177e4
LT		 10934 }
10935 if (!(val & EEPROM_ADDR_COMPLETE)) {
10936 rc = -EBUSY;
10937 break;
10938 }
10939 }
10940
10941 return rc;
10942}
10943
10944/* offset and length are dword aligned */
10945static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10946 u8 *buf)
10947{
10948 int ret = 0;
10949 u32 pagesize = tp->nvram_pagesize;
10950 u32 pagemask = pagesize - 1;
10951 u32 nvram_cmd;
10952 u8 *tmp;
10953
10954 tmp = kmalloc(pagesize, GFP_KERNEL);
10955 if (tmp == NULL)
10956 return -ENOMEM;
10957
10958 while (len) {
10959 int j;
e6af301b 10960 u32 phy_addr, page_off, size;
1da177e4
LT		 10961
10962 phy_addr = offset & ~pagemask;
6aa20a22 10963
1da177e4 10964 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 10965 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10966 (__be32 *) (tmp + j));
10967 if (ret)
1da177e4
LT		 10968 break;
10969 }
10970 if (ret)
10971 break;
10972
10973 page_off = offset & pagemask;
10974 size = pagesize;
10975 if (len < size)
10976 size = len;
10977
10978 len -= size;
10979
10980 memcpy(tmp + page_off, buf, size);
10981
10982 offset = offset + (pagesize - page_off);
10983
e6af301b 10984 tg3_enable_nvram_access(tp);
1da177e4
LT		 10985
10986 /*
10987 * Before we can erase the flash page, we need
10988 * to issue a special "write enable" command.
10989 */
10990 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10991
10992 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10993 break;
10994
10995 /* Erase the target page */
10996 tw32(NVRAM_ADDR, phy_addr);
10997
10998 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10999 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11000
11001 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11002 break;
11003
11004 /* Issue another write enable to start the write. */
11005 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11006
11007 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11008 break;
11009
11010 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11011 __be32 data;
1da177e4 11012
b9fc7dc5 11013 data = *((__be32 *) (tmp + j));
a9dc529d 11014
b9fc7dc5 11015 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11016
11017 tw32(NVRAM_ADDR, phy_addr + j);
11018
11019 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11020 NVRAM_CMD_WR;
11021
11022 if (j == 0)
11023 nvram_cmd |= NVRAM_CMD_FIRST;
11024 else if (j == (pagesize - 4))
11025 nvram_cmd |= NVRAM_CMD_LAST;
11026
11027 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11028 break;
11029 }
11030 if (ret)
11031 break;
11032 }
11033
11034 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11035 tg3_nvram_exec_cmd(tp, nvram_cmd);
11036
11037 kfree(tmp);
11038
11039 return ret;
11040}
11041
11042/* offset and length are dword aligned */
11043static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11044 u8 *buf)
11045{
11046 int i, ret = 0;
11047
11048 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11049 u32 page_off, phy_addr, nvram_cmd;
11050 __be32 data;
1da177e4
LT		 11051
11052 memcpy(&data, buf + i, 4);
b9fc7dc5 11053 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11054
11055 page_off = offset % tp->nvram_pagesize;
11056
1820180b 11057 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11058
11059 tw32(NVRAM_ADDR, phy_addr);
11060
11061 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11062
11063 if ((page_off == 0) || (i == 0))
11064 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11065 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11066 nvram_cmd |= NVRAM_CMD_LAST;
11067
11068 if (i == (len - 4))
11069 nvram_cmd |= NVRAM_CMD_LAST;
11070
321d32a0
MC		 11071 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11072 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11073 (tp->nvram_jedecnum == JEDEC_ST) &&
11074 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11075
11076 if ((ret = tg3_nvram_exec_cmd(tp,
11077 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11078 NVRAM_CMD_DONE)))
11079
11080 break;
11081 }
11082 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11083 /* We always do complete word writes to eeprom. */
11084 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11085 }
11086
11087 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11088 break;
11089 }
11090 return ret;
11091}
11092
11093/* offset and length are dword aligned */
11094static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11095{
11096 int ret;
11097
1da177e4 11098 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11099 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11100 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11101 udelay(40);
11102 }
11103
11104 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11105 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11106 }
11107 else {
11108 u32 grc_mode;
11109
ec41c7df
MC		 11110 ret = tg3_nvram_lock(tp);
11111 if (ret)
11112 return ret;
1da177e4 11113
e6af301b
MC		 11114 tg3_enable_nvram_access(tp);
11115 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11116 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11117 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11118
11119 grc_mode = tr32(GRC_MODE);
11120 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11121
11122 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11123 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11124
11125 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11126 buf);
11127 }
11128 else {
11129 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11130 buf);
11131 }
11132
11133 grc_mode = tr32(GRC_MODE);
11134 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11135
e6af301b 11136 tg3_disable_nvram_access(tp);
1da177e4
LT		 11137 tg3_nvram_unlock(tp);
11138 }
11139
11140 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11141 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11142 udelay(40);
11143 }
11144
11145 return ret;
11146}
11147
11148struct subsys_tbl_ent {
11149 u16 subsys_vendor, subsys_devid;
11150 u32 phy_id;
11151};
11152
11153static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11154 /* Broadcom boards. */
11155 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11156 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11157 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11158 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11159 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11160 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11161 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11162 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11163 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11164 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11165 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11166
11167 /* 3com boards. */
11168 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11169 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11170 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11171 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11172 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11173
11174 /* DELL boards. */
11175 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11176 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11177 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11178 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11179
11180 /* Compaq boards. */
11181 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11182 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11183 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11184 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11185 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11186
11187 /* IBM boards. */
11188 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11189};
11190
11191static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11192{
11193 int i;
11194
11195 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11196 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11197 tp->pdev->subsystem_vendor) &&
11198 (subsys_id_to_phy_id[i].subsys_devid ==
11199 tp->pdev->subsystem_device))
11200 return &subsys_id_to_phy_id[i];
11201 }
11202 return NULL;
11203}
11204
7d0c41ef 11205static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11206{
1da177e4 11207 u32 val;
caf636c7
MC		 11208 u16 pmcsr;
11209
11210 /* On some early chips the SRAM cannot be accessed in D3hot state,
11211 * so need make sure we're in D0.
11212 */
11213 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11214 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11215 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11216 msleep(1);
7d0c41ef
MC		 11217
11218 /* Make sure register accesses (indirect or otherwise)
11219 * will function correctly.
11220 */
11221 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11222 tp->misc_host_ctrl);
1da177e4 11223
f49639e6
DM		 11224 /* The memory arbiter has to be enabled in order for SRAM accesses
11225 * to succeed. Normally on powerup the tg3 chip firmware will make
11226 * sure it is enabled, but other entities such as system netboot
11227 * code might disable it.
11228 */
11229 val = tr32(MEMARB_MODE);
11230 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11231
1da177e4 11232 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11233 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11234
a85feb8c
GZ		 11235 /* Assume an onboard device and WOL capable by default. */
11236 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11237
b5d3772c 11238 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11239 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11240 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11241 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11242 }
0527ba35
MC		 11243 val = tr32(VCPU_CFGSHDW);
11244 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11245 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11246 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11247 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11248 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11249 goto done;
b5d3772c
MC		 11250 }
11251
1da177e4
LT		 11252 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11253 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11254 u32 nic_cfg, led_cfg;
a9daf367 11255 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11256 int eeprom_phy_serdes = 0;
1da177e4
LT		 11257
11258 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11259 tp->nic_sram_data_cfg = nic_cfg;
11260
11261 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11262 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11263 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11264 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11265 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11266 (ver > 0) && (ver < 0x100))
11267 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11268
a9daf367
MC		 11269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11270 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11271
1da177e4
LT		 11272 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11273 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11274 eeprom_phy_serdes = 1;
11275
11276 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11277 if (nic_phy_id != 0) {
11278 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11279 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11280
11281 eeprom_phy_id = (id1 >> 16) << 10;
11282 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11283 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11284 } else
11285 eeprom_phy_id = 0;
11286
7d0c41ef 11287 tp->phy_id = eeprom_phy_id;
747e8f8b 11288 if (eeprom_phy_serdes) {
a4e2b347 11289 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11290 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11291 else
11292 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11293 }
7d0c41ef 11294
cbf46853 11295 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11296 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11297 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11298 else
1da177e4
LT		 11299 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11300
11301 switch (led_cfg) {
11302 default:
11303 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11304 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11305 break;
11306
11307 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11308 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11309 break;
11310
11311 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11312 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11313
11314 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11315 * read on some older 5700/5701 bootcode.
11316 */
11317 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11318 ASIC_REV_5700 ||
11319 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11320 ASIC_REV_5701)
11321 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11322
1da177e4
LT		 11323 break;
11324
11325 case SHASTA_EXT_LED_SHARED:
11326 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11327 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11328 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11329 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11330 LED_CTRL_MODE_PHY_2);
11331 break;
11332
11333 case SHASTA_EXT_LED_MAC:
11334 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11335 break;
11336
11337 case SHASTA_EXT_LED_COMBO:
11338 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11339 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11340 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11341 LED_CTRL_MODE_PHY_2);
11342 break;
11343
855e1111 11344 }
1da177e4
LT		 11345
11346 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11348 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11349 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11350
b2a5c19c
MC		 11351 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11352 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11353
9d26e213 11354 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11355 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11356 if ((tp->pdev->subsystem_vendor ==
11357 PCI_VENDOR_ID_ARIMA) &&
11358 (tp->pdev->subsystem_device == 0x205a ||
11359 tp->pdev->subsystem_device == 0x2063))
11360 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11361 } else {
f49639e6 11362 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11363 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11364 }
1da177e4
LT		 11365
11366 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11367 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11368 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11369 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11370 }
b2b98d4a
MC		 11371
11372 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11373 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11374 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11375
a85feb8c
GZ		 11376 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11377 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11378 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11379
12dac075 11380 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11381 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11382 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11383
1da177e4
LT		 11384 if (cfg2 & (1 << 17))
11385 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11386
11387 /* serdes signal pre-emphasis in register 0x590 set by */
11388 /* bootcode if bit 18 is set */
11389 if (cfg2 & (1 << 18))
11390 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11391
321d32a0
MC		 11392 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11393 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11394 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11395 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11396
8ed5d97e
MC		 11397 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11398 u32 cfg3;
11399
11400 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11401 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11402 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11403 }
a9daf367
MC		 11404
11405 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11406 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11407 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11408 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11409 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11410 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11411 }
05ac4cb7
MC		 11412done:
11413 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11414 device_set_wakeup_enable(&tp->pdev->dev,
11415 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11416}
11417
b2a5c19c
MC		 11418static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11419{
11420 int i;
11421 u32 val;
11422
11423 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11424 tw32(OTP_CTRL, cmd);
11425
11426 /* Wait for up to 1 ms for command to execute. */
11427 for (i = 0; i < 100; i++) {
11428 val = tr32(OTP_STATUS);
11429 if (val & OTP_STATUS_CMD_DONE)
11430 break;
11431 udelay(10);
11432 }
11433
11434 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11435}
11436
11437/* Read the gphy configuration from the OTP region of the chip. The gphy
11438 * configuration is a 32-bit value that straddles the alignment boundary.
11439 * We do two 32-bit reads and then shift and merge the results.
11440 */
11441static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11442{
11443 u32 bhalf_otp, thalf_otp;
11444
11445 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11446
11447 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11448 return 0;
11449
11450 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11451
11452 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11453 return 0;
11454
11455 thalf_otp = tr32(OTP_READ_DATA);
11456
11457 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11458
11459 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11460 return 0;
11461
11462 bhalf_otp = tr32(OTP_READ_DATA);
11463
11464 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11465}
11466
7d0c41ef
MC		 11467static int __devinit tg3_phy_probe(struct tg3 *tp)
11468{
11469 u32 hw_phy_id_1, hw_phy_id_2;
11470 u32 hw_phy_id, hw_phy_id_masked;
11471 int err;
1da177e4 11472
b02fd9e3
MC		 11473 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11474 return tg3_phy_init(tp);
11475
1da177e4 11476 /* Reading the PHY ID register can conflict with ASF
877d0310 11477 * firmware access to the PHY hardware.
1da177e4
LT		 11478 */
11479 err = 0;
0d3031d9
MC		 11480 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11481 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11482 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11483 } else {
11484 /* Now read the physical PHY_ID from the chip and verify
11485 * that it is sane. If it doesn't look good, we fall back
11486 * to either the hard-coded table based PHY_ID and failing
11487 * that the value found in the eeprom area.
11488 */
11489 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11490 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11491
11492 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11493 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11494 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11495
11496 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11497 }
11498
11499 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11500 tp->phy_id = hw_phy_id;
11501 if (hw_phy_id_masked == PHY_ID_BCM8002)
11502 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11503 else
11504 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11505 } else {
7d0c41ef
MC		 11506 if (tp->phy_id != PHY_ID_INVALID) {
11507 /* Do nothing, phy ID already set up in
11508 * tg3_get_eeprom_hw_cfg().
11509 */
1da177e4
LT		 11510 } else {
11511 struct subsys_tbl_ent *p;
11512
11513 /* No eeprom signature? Try the hardcoded
11514 * subsys device table.
11515 */
11516 p = lookup_by_subsys(tp);
11517 if (!p)
11518 return -ENODEV;
11519
11520 tp->phy_id = p->phy_id;
11521 if (!tp->phy_id ||
11522 tp->phy_id == PHY_ID_BCM8002)
11523 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11524 }
11525 }
11526
747e8f8b 11527 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11528 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11529 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11530 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11531
11532 tg3_readphy(tp, MII_BMSR, &bmsr);
11533 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11534 (bmsr & BMSR_LSTATUS))
11535 goto skip_phy_reset;
6aa20a22 11536
1da177e4
LT		 11537 err = tg3_phy_reset(tp);
11538 if (err)
11539 return err;
11540
11541 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11542 ADVERTISE_100HALF | ADVERTISE_100FULL |
11543 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11544 tg3_ctrl = 0;
11545 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11546 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11547 MII_TG3_CTRL_ADV_1000_FULL);
11548 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11549 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11550 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11551 MII_TG3_CTRL_ENABLE_AS_MASTER);
11552 }
11553
3600d918
MC		 11554 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11555 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11556 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11557 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11558 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11559
11560 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11561 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11562
11563 tg3_writephy(tp, MII_BMCR,
11564 BMCR_ANENABLE | BMCR_ANRESTART);
11565 }
11566 tg3_phy_set_wirespeed(tp);
11567
11568 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11569 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11570 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11571 }
11572
11573skip_phy_reset:
11574 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11575 err = tg3_init_5401phy_dsp(tp);
11576 if (err)
11577 return err;
11578 }
11579
11580 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11581 err = tg3_init_5401phy_dsp(tp);
11582 }
11583
747e8f8b 11584 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11585 tp->link_config.advertising =
11586 (ADVERTISED_1000baseT_Half |
11587 ADVERTISED_1000baseT_Full |
11588 ADVERTISED_Autoneg |
11589 ADVERTISED_FIBRE);
11590 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11591 tp->link_config.advertising &=
11592 ~(ADVERTISED_1000baseT_Half |
11593 ADVERTISED_1000baseT_Full);
11594
11595 return err;
11596}
11597
11598static void __devinit tg3_read_partno(struct tg3 *tp)
11599{
6d348f2c 11600 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11601 unsigned int i;
1b27777a 11602 u32 magic;
1da177e4 11603
df259d8c
MC		 11604 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11605 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11606 goto out_not_found;
1da177e4 11607
1820180b 11608 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11609 for (i = 0; i < 256; i += 4) {
11610 u32 tmp;
1da177e4 11611
6d348f2c
MC		 11612 /* The data is in little-endian format in NVRAM.
11613 * Use the big-endian read routines to preserve
11614 * the byte order as it exists in NVRAM.
11615 */
11616 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11617 goto out_not_found;
11618
6d348f2c 11619 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11620 }
11621 } else {
11622 int vpd_cap;
11623
11624 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11625 for (i = 0; i < 256; i += 4) {
11626 u32 tmp, j = 0;
b9fc7dc5 11627 __le32 v;
1b27777a
MC		 11628 u16 tmp16;
11629
11630 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11631 i);
11632 while (j++ < 100) {
11633 pci_read_config_word(tp->pdev, vpd_cap +
11634 PCI_VPD_ADDR, &tmp16);
11635 if (tmp16 & 0x8000)
11636 break;
11637 msleep(1);
11638 }
f49639e6
DM		 11639 if (!(tmp16 & 0x8000))
11640 goto out_not_found;
11641
1b27777a
MC		 11642 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11643 &tmp);
b9fc7dc5 11644 v = cpu_to_le32(tmp);
6d348f2c 11645 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11646 }
1da177e4
LT		 11647 }
11648
11649 /* Now parse and find the part number. */
af2c6a4a 11650 for (i = 0; i < 254; ) {
1da177e4 11651 unsigned char val = vpd_data[i];
af2c6a4a 11652 unsigned int block_end;
1da177e4
LT		 11653
11654 if (val == 0x82 || val == 0x91) {
11655 i = (i + 3 +
11656 (vpd_data[i + 1] +
11657 (vpd_data[i + 2] << 8)));
11658 continue;
11659 }
11660
11661 if (val != 0x90)
11662 goto out_not_found;
11663
11664 block_end = (i + 3 +
11665 (vpd_data[i + 1] +
11666 (vpd_data[i + 2] << 8)));
11667 i += 3;
af2c6a4a
MC		 11668
11669 if (block_end > 256)
11670 goto out_not_found;
11671
11672 while (i < (block_end - 2)) {
1da177e4
LT		 11673 if (vpd_data[i + 0] == 'P' &&
11674 vpd_data[i + 1] == 'N') {
11675 int partno_len = vpd_data[i + 2];
11676
af2c6a4a
MC		 11677 i += 3;
11678 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11679 goto out_not_found;
11680
11681 memcpy(tp->board_part_number,
af2c6a4a 11682 &vpd_data[i], partno_len);
1da177e4
LT		 11683
11684 /* Success. */
11685 return;
11686 }
af2c6a4a 11687 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11688 }
11689
11690 /* Part number not found. */
11691 goto out_not_found;
11692 }
11693
11694out_not_found:
b5d3772c
MC		 11695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11696 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 11697 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11698 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11699 strcpy(tp->board_part_number, "BCM57780");
11700 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11701 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11702 strcpy(tp->board_part_number, "BCM57760");
11703 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11704 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11705 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 11706 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11707 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11708 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 11709 else
11710 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11711}
11712
9c8a620e
MC		 11713static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11714{
11715 u32 val;
11716
e4f34110 11717 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11718 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11719 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11720 val != 0)
11721 return 0;
11722
11723 return 1;
11724}
11725
acd9c119
MC		 11726static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11727{
ff3a7cb2 11728 u32 val, offset, start, ver_offset;
acd9c119 11729 int i;
ff3a7cb2 11730 bool newver = false;
acd9c119
MC		 11731
11732 if (tg3_nvram_read(tp, 0xc, &offset) ||
11733 tg3_nvram_read(tp, 0x4, &start))
11734 return;
11735
11736 offset = tg3_nvram_logical_addr(tp, offset);
11737
ff3a7cb2 11738 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11739 return;
11740
ff3a7cb2
MC		 11741 if ((val & 0xfc000000) == 0x0c000000) {
11742 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11743 return;
11744
ff3a7cb2
MC		 11745 if (val == 0)
11746 newver = true;
11747 }
11748
11749 if (newver) {
11750 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11751 return;
11752
11753 offset = offset + ver_offset - start;
11754 for (i = 0; i < 16; i += 4) {
11755 __be32 v;
11756 if (tg3_nvram_read_be32(tp, offset + i, &v))
11757 return;
11758
11759 memcpy(tp->fw_ver + i, &v, sizeof(v));
11760 }
11761 } else {
11762 u32 major, minor;
11763
11764 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11765 return;
11766
11767 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11768 TG3_NVM_BCVER_MAJSFT;
11769 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11770 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11771 }
11772}
11773
a6f6cb1c
MC		 11774static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11775{
11776 u32 val, major, minor;
11777
11778 /* Use native endian representation */
11779 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11780 return;
11781
11782 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11783 TG3_NVM_HWSB_CFG1_MAJSFT;
11784 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11785 TG3_NVM_HWSB_CFG1_MINSFT;
11786
11787 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11788}
11789
dfe00d7d
MC		 11790static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11791{
11792 u32 offset, major, minor, build;
11793
11794 tp->fw_ver[0] = 's';
11795 tp->fw_ver[1] = 'b';
11796 tp->fw_ver[2] = '\0';
11797
11798 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11799 return;
11800
11801 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11802 case TG3_EEPROM_SB_REVISION_0:
11803 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11804 break;
11805 case TG3_EEPROM_SB_REVISION_2:
11806 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11807 break;
11808 case TG3_EEPROM_SB_REVISION_3:
11809 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11810 break;
11811 default:
11812 return;
11813 }
11814
e4f34110 11815 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11816 return;
11817
11818 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11819 TG3_EEPROM_SB_EDH_BLD_SHFT;
11820 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11821 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11822 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11823
11824 if (minor > 99 || build > 26)
11825 return;
11826
11827 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11828
11829 if (build > 0) {
11830 tp->fw_ver[8] = 'a' + build - 1;
11831 tp->fw_ver[9] = '\0';
11832 }
11833}
11834
acd9c119 11835static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11836{
11837 u32 val, offset, start;
acd9c119 11838 int i, vlen;
9c8a620e
MC		 11839
11840 for (offset = TG3_NVM_DIR_START;
11841 offset < TG3_NVM_DIR_END;
11842 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11843 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11844 return;
11845
9c8a620e
MC		 11846 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11847 break;
11848 }
11849
11850 if (offset == TG3_NVM_DIR_END)
11851 return;
11852
11853 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11854 start = 0x08000000;
e4f34110 11855 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11856 return;
11857
e4f34110 11858 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11859 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11860 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11861 return;
11862
11863 offset += val - start;
11864
acd9c119 11865 vlen = strlen(tp->fw_ver);
9c8a620e 11866
acd9c119
MC		 11867 tp->fw_ver[vlen++] = ',';
11868 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11869
11870 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11871 __be32 v;
11872 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11873 return;
11874
b9fc7dc5 11875 offset += sizeof(v);
c4e6575c 11876
acd9c119
MC		 11877 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11878 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11879 break;
c4e6575c 11880 }
9c8a620e 11881
acd9c119
MC		 11882 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11883 vlen += sizeof(v);
c4e6575c 11884 }
acd9c119
MC		 11885}
11886
7fd76445
MC		 11887static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11888{
11889 int vlen;
11890 u32 apedata;
11891
11892 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11893 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11894 return;
11895
11896 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11897 if (apedata != APE_SEG_SIG_MAGIC)
11898 return;
11899
11900 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11901 if (!(apedata & APE_FW_STATUS_READY))
11902 return;
11903
11904 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11905
11906 vlen = strlen(tp->fw_ver);
11907
11908 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11909 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11910 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11911 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11912 (apedata & APE_FW_VERSION_BLDMSK));
11913}
11914
acd9c119
MC		 11915static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11916{
11917 u32 val;
11918
df259d8c
MC		 11919 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11920 tp->fw_ver[0] = 's';
11921 tp->fw_ver[1] = 'b';
11922 tp->fw_ver[2] = '\0';
11923
11924 return;
11925 }
11926
acd9c119
MC		 11927 if (tg3_nvram_read(tp, 0, &val))
11928 return;
11929
11930 if (val == TG3_EEPROM_MAGIC)
11931 tg3_read_bc_ver(tp);
11932 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11933 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11934 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11935 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11936 else
11937 return;
11938
11939 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11940 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11941 return;
11942
11943 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 11944
11945 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 11946}
11947
7544b097
MC		 11948static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11949
1da177e4
LT		 11950static int __devinit tg3_get_invariants(struct tg3 *tp)
11951{
11952 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 11953 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11954 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 11955 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11956 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 11957 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11958 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 11959 { },
11960 };
11961 u32 misc_ctrl_reg;
1da177e4
LT		 11962 u32 pci_state_reg, grc_misc_cfg;
11963 u32 val;
11964 u16 pci_cmd;
5e7dfd0f 11965 int err;
1da177e4 11966
1da177e4
LT		 11967 /* Force memory write invalidate off. If we leave it on,
11968 * then on 5700_BX chips we have to enable a workaround.
11969 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11970 * to match the cacheline size. The Broadcom driver have this
11971 * workaround but turns MWI off all the times so never uses
11972 * it. This seems to suggest that the workaround is insufficient.
11973 */
11974 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11975 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11976 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11977
11978 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11979 * has the register indirect write enable bit set before
11980 * we try to access any of the MMIO registers. It is also
11981 * critical that the PCI-X hw workaround situation is decided
11982 * before that as well.
11983 */
11984 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11985 &misc_ctrl_reg);
11986
11987 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11988 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 11989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11990 u32 prod_id_asic_rev;
11991
11992 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11993 &prod_id_asic_rev);
321d32a0 11994 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 11995 }
1da177e4 11996
ff645bec
MC		 11997 /* Wrong chip ID in 5752 A0. This code can be removed later
11998 * as A0 is not in production.
11999 */
12000 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12001 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12002
6892914f
MC		 12003 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12004 * we need to disable memory and use config. cycles
12005 * only to access all registers. The 5702/03 chips
12006 * can mistakenly decode the special cycles from the
12007 * ICH chipsets as memory write cycles, causing corruption
12008 * of register and memory space. Only certain ICH bridges
12009 * will drive special cycles with non-zero data during the
12010 * address phase which can fall within the 5703's address
12011 * range. This is not an ICH bug as the PCI spec allows
12012 * non-zero address during special cycles. However, only
12013 * these ICH bridges are known to drive non-zero addresses
12014 * during special cycles.
12015 *
12016 * Since special cycles do not cross PCI bridges, we only
12017 * enable this workaround if the 5703 is on the secondary
12018 * bus of these ICH bridges.
12019 */
12020 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12021 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12022 static struct tg3_dev_id {
12023 u32 vendor;
12024 u32 device;
12025 u32 rev;
12026 } ich_chipsets[] = {
12027 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12028 PCI_ANY_ID },
12029 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12030 PCI_ANY_ID },
12031 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12032 0xa },
12033 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12034 PCI_ANY_ID },
12035 { },
12036 };
12037 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12038 struct pci_dev *bridge = NULL;
12039
12040 while (pci_id->vendor != 0) {
12041 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12042 bridge);
12043 if (!bridge) {
12044 pci_id++;
12045 continue;
12046 }
12047 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12048 if (bridge->revision > pci_id->rev)
6892914f
MC		 12049 continue;
12050 }
12051 if (bridge->subordinate &&
12052 (bridge->subordinate->number ==
12053 tp->pdev->bus->number)) {
12054
12055 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12056 pci_dev_put(bridge);
12057 break;
12058 }
12059 }
12060 }
12061
41588ba1
MC		 12062 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12063 static struct tg3_dev_id {
12064 u32 vendor;
12065 u32 device;
12066 } bridge_chipsets[] = {
12067 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12068 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12069 { },
12070 };
12071 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12072 struct pci_dev *bridge = NULL;
12073
12074 while (pci_id->vendor != 0) {
12075 bridge = pci_get_device(pci_id->vendor,
12076 pci_id->device,
12077 bridge);
12078 if (!bridge) {
12079 pci_id++;
12080 continue;
12081 }
12082 if (bridge->subordinate &&
12083 (bridge->subordinate->number <=
12084 tp->pdev->bus->number) &&
12085 (bridge->subordinate->subordinate >=
12086 tp->pdev->bus->number)) {
12087 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12088 pci_dev_put(bridge);
12089 break;
12090 }
12091 }
12092 }
12093
4a29cc2e
MC		 12094 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12095 * DMA addresses > 40-bit. This bridge may have other additional
12096 * 57xx devices behind it in some 4-port NIC designs for example.
12097 * Any tg3 device found behind the bridge will also need the 40-bit
12098 * DMA workaround.
12099 */
a4e2b347
MC		 12100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12102 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12103 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12104 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12105 }
4a29cc2e
MC		 12106 else {
12107 struct pci_dev *bridge = NULL;
12108
12109 do {
12110 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12111 PCI_DEVICE_ID_SERVERWORKS_EPB,
12112 bridge);
12113 if (bridge && bridge->subordinate &&
12114 (bridge->subordinate->number <=
12115 tp->pdev->bus->number) &&
12116 (bridge->subordinate->subordinate >=
12117 tp->pdev->bus->number)) {
12118 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12119 pci_dev_put(bridge);
12120 break;
12121 }
12122 } while (bridge);
12123 }
4cf78e4f 12124
1da177e4
LT		 12125 /* Initialize misc host control in PCI block. */
12126 tp->misc_host_ctrl |= (misc_ctrl_reg &
12127 MISC_HOST_CTRL_CHIPREV);
12128 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12129 tp->misc_host_ctrl);
12130
7544b097
MC		 12131 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12132 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12133 tp->pdev_peer = tg3_find_peer(tp);
12134
321d32a0
MC		 12135 /* Intentionally exclude ASIC_REV_5906 */
12136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12137 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12139 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 12141 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12142 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12143
12144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12146 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12147 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12148 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12149 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12150
1b440c56
JL		 12151 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12152 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12153 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12154
027455ad
MC		 12155 /* 5700 B0 chips do not support checksumming correctly due
12156 * to hardware bugs.
12157 */
12158 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12159 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12160 else {
12161 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12162 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12163 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12164 tp->dev->features |= NETIF_F_IPV6_CSUM;
12165 }
12166
5a6f3074 12167 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12168 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12169 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12170 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12171 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12172 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12173 tp->pdev_peer == tp->pdev))
12174 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12175
321d32a0 12176 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12178 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12179 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12180 } else {
7f62ad5d 12181 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12182 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12183 ASIC_REV_5750 &&
12184 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12185 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12186 }
5a6f3074 12187 }
1da177e4 12188
4f125f42
MC		 12189 tp->irq_max = 1;
12190
f51f3562
MC		 12191 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12192 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8f666b07 12193 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12194
52f4490c
MC		 12195 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12196 &pci_state_reg);
12197
5e7dfd0f
MC		 12198 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12199 if (tp->pcie_cap != 0) {
12200 u16 lnkctl;
12201
1da177e4 12202 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12203
12204 pcie_set_readrq(tp->pdev, 4096);
12205
5e7dfd0f
MC		 12206 pci_read_config_word(tp->pdev,
12207 tp->pcie_cap + PCI_EXP_LNKCTL,
12208 &lnkctl);
12209 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12211 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12213 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12214 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12215 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12216 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12217 }
52f4490c 12218 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12219 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12220 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12221 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12222 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12223 if (!tp->pcix_cap) {
12224 printk(KERN_ERR PFX "Cannot find PCI-X "
12225 "capability, aborting.\n");
12226 return -EIO;
12227 }
12228
12229 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12230 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12231 }
1da177e4 12232
399de50b
MC		 12233 /* If we have an AMD 762 or VIA K8T800 chipset, write
12234 * reordering to the mailbox registers done by the host
12235 * controller can cause major troubles. We read back from
12236 * every mailbox register write to force the writes to be
12237 * posted to the chip in order.
12238 */
12239 if (pci_dev_present(write_reorder_chipsets) &&
12240 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12241 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12242
69fc4053
MC		 12243 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12244 &tp->pci_cacheline_sz);
12245 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12246 &tp->pci_lat_timer);
1da177e4
LT		 12247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12248 tp->pci_lat_timer < 64) {
12249 tp->pci_lat_timer = 64;
69fc4053
MC		 12250 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12251 tp->pci_lat_timer);
1da177e4
LT		 12252 }
12253
52f4490c
MC		 12254 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12255 /* 5700 BX chips need to have their TX producer index
12256 * mailboxes written twice to workaround a bug.
12257 */
12258 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12259
52f4490c 12260 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12261 *
12262 * The workaround is to use indirect register accesses
12263 * for all chip writes not to mailbox registers.
12264 */
52f4490c 12265 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12266 u32 pm_reg;
1da177e4
LT		 12267
12268 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12269
12270 /* The chip can have it's power management PCI config
12271 * space registers clobbered due to this bug.
12272 * So explicitly force the chip into D0 here.
12273 */
9974a356
MC		 12274 pci_read_config_dword(tp->pdev,
12275 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12276 &pm_reg);
12277 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12278 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12279 pci_write_config_dword(tp->pdev,
12280 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12281 pm_reg);
12282
12283 /* Also, force SERR#/PERR# in PCI command. */
12284 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12285 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12286 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12287 }
12288 }
12289
1da177e4
LT		 12290 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12291 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12292 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12293 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12294
12295 /* Chip-specific fixup from Broadcom driver */
12296 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12297 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12298 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12299 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12300 }
12301
1ee582d8 12302 /* Default fast path register access methods */
20094930 12303 tp->read32 = tg3_read32;
1ee582d8 12304 tp->write32 = tg3_write32;
09ee929c 12305 tp->read32_mbox = tg3_read32;
20094930 12306 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12307 tp->write32_tx_mbox = tg3_write32;
12308 tp->write32_rx_mbox = tg3_write32;
12309
12310 /* Various workaround register access methods */
12311 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12312 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12313 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12314 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12315 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12316 /*
12317 * Back to back register writes can cause problems on these
12318 * chips, the workaround is to read back all reg writes
12319 * except those to mailbox regs.
12320 *
12321 * See tg3_write_indirect_reg32().
12322 */
1ee582d8 12323 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12324 }
12325
1ee582d8
MC		 12326
12327 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12328 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12329 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12330 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12331 tp->write32_rx_mbox = tg3_write_flush_reg32;
12332 }
20094930 12333
6892914f
MC		 12334 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12335 tp->read32 = tg3_read_indirect_reg32;
12336 tp->write32 = tg3_write_indirect_reg32;
12337 tp->read32_mbox = tg3_read_indirect_mbox;
12338 tp->write32_mbox = tg3_write_indirect_mbox;
12339 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12340 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12341
12342 iounmap(tp->regs);
22abe310 12343 tp->regs = NULL;
6892914f
MC		 12344
12345 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12346 pci_cmd &= ~PCI_COMMAND_MEMORY;
12347 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12348 }
b5d3772c
MC		 12349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12350 tp->read32_mbox = tg3_read32_mbox_5906;
12351 tp->write32_mbox = tg3_write32_mbox_5906;
12352 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12353 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12354 }
6892914f 12355
bbadf503
MC		 12356 if (tp->write32 == tg3_write_indirect_reg32 ||
12357 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12358 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12359 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12360 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12361
7d0c41ef 12362 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12363 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12364 * determined before calling tg3_set_power_state() so that
12365 * we know whether or not to switch out of Vaux power.
12366 * When the flag is set, it means that GPIO1 is used for eeprom
12367 * write protect and also implies that it is a LOM where GPIOs
12368 * are not used to switch power.
6aa20a22 12369 */
7d0c41ef
MC		 12370 tg3_get_eeprom_hw_cfg(tp);
12371
0d3031d9
MC		 12372 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12373 /* Allow reads and writes to the
12374 * APE register and memory space.
12375 */
12376 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12377 PCISTATE_ALLOW_APE_SHMEM_WR;
12378 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12379 pci_state_reg);
12380 }
12381
9936bcf6 12382 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12383 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12384 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12385 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12386 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12387
314fba34
MC		 12388 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12389 * GPIO1 driven high will bring 5700's external PHY out of reset.
12390 * It is also used as eeprom write protect on LOMs.
12391 */
12392 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12393 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12394 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12395 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12396 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12397 /* Unused GPIO3 must be driven as output on 5752 because there
12398 * are no pull-up resistors on unused GPIO pins.
12399 */
12400 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12401 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12402
321d32a0
MC		 12403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12404 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12405 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12406
8d519ab2
MC		 12407 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12408 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12409 /* Turn off the debug UART. */
12410 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12411 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12412 /* Keep VMain power. */
12413 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12414 GRC_LCLCTRL_GPIO_OUTPUT0;
12415 }
12416
1da177e4 12417 /* Force the chip into D0. */
bc1c7567 12418 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12419 if (err) {
12420 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12421 pci_name(tp->pdev));
12422 return err;
12423 }
12424
1da177e4
LT		 12425 /* Derive initial jumbo mode from MTU assigned in
12426 * ether_setup() via the alloc_etherdev() call
12427 */
0f893dc6 12428 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12429 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12430 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12431
12432 /* Determine WakeOnLan speed to use. */
12433 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12434 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12435 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12436 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12437 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12438 } else {
12439 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12440 }
12441
7f97a4bd
MC		 12442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12443 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12444
1da177e4
LT		 12445 /* A few boards don't want Ethernet@WireSpeed phy feature */
12446 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12447 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12448 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12449 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12450 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12451 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12452 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12453
12454 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12455 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12456 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12457 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12458 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12459
321d32a0 12460 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12461 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0
MC		 12462 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12463 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12468 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12469 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12470 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12471 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12472 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12473 } else
c424cb24
MC		 12474 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12475 }
1da177e4 12476
b2a5c19c
MC		 12477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12478 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12479 tp->phy_otp = tg3_read_otp_phycfg(tp);
12480 if (tp->phy_otp == 0)
12481 tp->phy_otp = TG3_OTP_DEFAULT;
12482 }
12483
f51f3562 12484 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12485 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12486 else
12487 tp->mi_mode = MAC_MI_MODE_BASE;
12488
1da177e4 12489 tp->coalesce_mode = 0;
1da177e4
LT		 12490 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12491 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12492 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12493
321d32a0
MC		 12494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12495 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12496 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12497
255ca311
MC		 12498 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12499 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12500 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12501 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12502
158d7abd
MC		 12503 err = tg3_mdio_init(tp);
12504 if (err)
12505 return err;
1da177e4
LT		 12506
12507 /* Initialize data/descriptor byte/word swapping. */
12508 val = tr32(GRC_MODE);
12509 val &= GRC_MODE_HOST_STACKUP;
12510 tw32(GRC_MODE, val | tp->grc_mode);
12511
12512 tg3_switch_clocks(tp);
12513
12514 /* Clear this out for sanity. */
12515 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12516
12517 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12518 &pci_state_reg);
12519 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12520 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12521 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12522
12523 if (chiprevid == CHIPREV_ID_5701_A0 ||
12524 chiprevid == CHIPREV_ID_5701_B0 ||
12525 chiprevid == CHIPREV_ID_5701_B2 ||
12526 chiprevid == CHIPREV_ID_5701_B5) {
12527 void __iomem *sram_base;
12528
12529 /* Write some dummy words into the SRAM status block
12530 * area, see if it reads back correctly. If the return
12531 * value is bad, force enable the PCIX workaround.
12532 */
12533 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12534
12535 writel(0x00000000, sram_base);
12536 writel(0x00000000, sram_base + 4);
12537 writel(0xffffffff, sram_base + 4);
12538 if (readl(sram_base) != 0x00000000)
12539 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12540 }
12541 }
12542
12543 udelay(50);
12544 tg3_nvram_init(tp);
12545
12546 grc_misc_cfg = tr32(GRC_MISC_CFG);
12547 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12548
1da177e4
LT		 12549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12550 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12551 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12552 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12553
fac9b83e
DM		 12554 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12555 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12556 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12557 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12558 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12559 HOSTCC_MODE_CLRTICK_TXBD);
12560
12561 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12562 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12563 tp->misc_host_ctrl);
12564 }
12565
3bda1258
MC		 12566 /* Preserve the APE MAC_MODE bits */
12567 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12568 tp->mac_mode = tr32(MAC_MODE) |
12569 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12570 else
12571 tp->mac_mode = TG3_DEF_MAC_MODE;
12572
1da177e4
LT		 12573 /* these are limited to 10/100 only */
12574 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12575 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12576 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12577 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12578 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12579 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12580 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12581 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12582 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12583 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12584 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12585 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 12586 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 12587 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12588
12589 err = tg3_phy_probe(tp);
12590 if (err) {
12591 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12592 pci_name(tp->pdev), err);
12593 /* ... but do not return immediately ... */
b02fd9e3 12594 tg3_mdio_fini(tp);
1da177e4
LT		 12595 }
12596
12597 tg3_read_partno(tp);
c4e6575c 12598 tg3_read_fw_ver(tp);
1da177e4
LT		 12599
12600 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12601 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12602 } else {
12603 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12604 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12605 else
12606 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12607 }
12608
12609 /* 5700 {AX,BX} chips have a broken status block link
12610 * change bit implementation, so we must use the
12611 * status register in those cases.
12612 */
12613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12614 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12615 else
12616 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12617
12618 /* The led_ctrl is set during tg3_phy_probe, here we might
12619 * have to force the link status polling mechanism based
12620 * upon subsystem IDs.
12621 */
12622 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12624 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12625 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12626 TG3_FLAG_USE_LINKCHG_REG);
12627 }
12628
12629 /* For all SERDES we poll the MAC status register. */
12630 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12631 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12632 else
12633 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12634
ad829268 12635 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12637 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12638 tp->rx_offset = 0;
12639
f92905de
MC		 12640 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12641
12642 /* Increment the rx prod index on the rx std ring by at most
12643 * 8 for these chips to workaround hw errata.
12644 */
12645 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12646 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12648 tp->rx_std_max_post = 8;
12649
8ed5d97e
MC		 12650 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12651 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12652 PCIE_PWR_MGMT_L1_THRESH_MSK;
12653
1da177e4
LT		 12654 return err;
12655}
12656
49b6e95f 12657#ifdef CONFIG_SPARC
1da177e4
LT		 12658static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12659{
12660 struct net_device *dev = tp->dev;
12661 struct pci_dev *pdev = tp->pdev;
49b6e95f 12662 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12663 const unsigned char *addr;
49b6e95f
DM		 12664 int len;
12665
12666 addr = of_get_property(dp, "local-mac-address", &len);
12667 if (addr && len == 6) {
12668 memcpy(dev->dev_addr, addr, 6);
12669 memcpy(dev->perm_addr, dev->dev_addr, 6);
12670 return 0;
1da177e4
LT		 12671 }
12672 return -ENODEV;
12673}
12674
12675static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12676{
12677 struct net_device *dev = tp->dev;
12678
12679 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12680 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12681 return 0;
12682}
12683#endif
12684
12685static int __devinit tg3_get_device_address(struct tg3 *tp)
12686{
12687 struct net_device *dev = tp->dev;
12688 u32 hi, lo, mac_offset;
008652b3 12689 int addr_ok = 0;
1da177e4 12690
49b6e95f 12691#ifdef CONFIG_SPARC
1da177e4
LT		 12692 if (!tg3_get_macaddr_sparc(tp))
12693 return 0;
12694#endif
12695
12696 mac_offset = 0x7c;
f49639e6 12697 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12698 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12699 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12700 mac_offset = 0xcc;
12701 if (tg3_nvram_lock(tp))
12702 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12703 else
12704 tg3_nvram_unlock(tp);
12705 }
b5d3772c
MC		 12706 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12707 mac_offset = 0x10;
1da177e4
LT		 12708
12709 /* First try to get it from MAC address mailbox. */
12710 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12711 if ((hi >> 16) == 0x484b) {
12712 dev->dev_addr[0] = (hi >> 8) & 0xff;
12713 dev->dev_addr[1] = (hi >> 0) & 0xff;
12714
12715 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12716 dev->dev_addr[2] = (lo >> 24) & 0xff;
12717 dev->dev_addr[3] = (lo >> 16) & 0xff;
12718 dev->dev_addr[4] = (lo >> 8) & 0xff;
12719 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12720
008652b3
MC		 12721 /* Some old bootcode may report a 0 MAC address in SRAM */
12722 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12723 }
12724 if (!addr_ok) {
12725 /* Next, try NVRAM. */
df259d8c
MC		 12726 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12727 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12728 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12729 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12730 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12731 }
12732 /* Finally just fetch it out of the MAC control regs. */
12733 else {
12734 hi = tr32(MAC_ADDR_0_HIGH);
12735 lo = tr32(MAC_ADDR_0_LOW);
12736
12737 dev->dev_addr[5] = lo & 0xff;
12738 dev->dev_addr[4] = (lo >> 8) & 0xff;
12739 dev->dev_addr[3] = (lo >> 16) & 0xff;
12740 dev->dev_addr[2] = (lo >> 24) & 0xff;
12741 dev->dev_addr[1] = hi & 0xff;
12742 dev->dev_addr[0] = (hi >> 8) & 0xff;
12743 }
1da177e4
LT		 12744 }
12745
12746 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12747#ifdef CONFIG_SPARC
1da177e4
LT		 12748 if (!tg3_get_default_macaddr_sparc(tp))
12749 return 0;
12750#endif
12751 return -EINVAL;
12752 }
2ff43697 12753 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12754 return 0;
12755}
12756
59e6b434
DM		 12757#define BOUNDARY_SINGLE_CACHELINE 1
12758#define BOUNDARY_MULTI_CACHELINE 2
12759
12760static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12761{
12762 int cacheline_size;
12763 u8 byte;
12764 int goal;
12765
12766 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12767 if (byte == 0)
12768 cacheline_size = 1024;
12769 else
12770 cacheline_size = (int) byte * 4;
12771
12772 /* On 5703 and later chips, the boundary bits have no
12773 * effect.
12774 */
12775 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12776 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12777 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12778 goto out;
12779
12780#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12781 goal = BOUNDARY_MULTI_CACHELINE;
12782#else
12783#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12784 goal = BOUNDARY_SINGLE_CACHELINE;
12785#else
12786 goal = 0;
12787#endif
12788#endif
12789
12790 if (!goal)
12791 goto out;
12792
12793 /* PCI controllers on most RISC systems tend to disconnect
12794 * when a device tries to burst across a cache-line boundary.
12795 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12796 *
12797 * Unfortunately, for PCI-E there are only limited
12798 * write-side controls for this, and thus for reads
12799 * we will still get the disconnects. We'll also waste
12800 * these PCI cycles for both read and write for chips
12801 * other than 5700 and 5701 which do not implement the
12802 * boundary bits.
12803 */
12804 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12805 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12806 switch (cacheline_size) {
12807 case 16:
12808 case 32:
12809 case 64:
12810 case 128:
12811 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12812 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12813 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12814 } else {
12815 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12816 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12817 }
12818 break;
12819
12820 case 256:
12821 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12822 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12823 break;
12824
12825 default:
12826 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12827 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12828 break;
855e1111 12829 }
59e6b434
DM		 12830 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12831 switch (cacheline_size) {
12832 case 16:
12833 case 32:
12834 case 64:
12835 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12836 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12837 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12838 break;
12839 }
12840 /* fallthrough */
12841 case 128:
12842 default:
12843 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12844 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12845 break;
855e1111 12846 }
59e6b434
DM		 12847 } else {
12848 switch (cacheline_size) {
12849 case 16:
12850 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12851 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12852 DMA_RWCTRL_WRITE_BNDRY_16);
12853 break;
12854 }
12855 /* fallthrough */
12856 case 32:
12857 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12858 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12859 DMA_RWCTRL_WRITE_BNDRY_32);
12860 break;
12861 }
12862 /* fallthrough */
12863 case 64:
12864 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12865 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12866 DMA_RWCTRL_WRITE_BNDRY_64);
12867 break;
12868 }
12869 /* fallthrough */
12870 case 128:
12871 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12872 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12873 DMA_RWCTRL_WRITE_BNDRY_128);
12874 break;
12875 }
12876 /* fallthrough */
12877 case 256:
12878 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12879 DMA_RWCTRL_WRITE_BNDRY_256);
12880 break;
12881 case 512:
12882 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12883 DMA_RWCTRL_WRITE_BNDRY_512);
12884 break;
12885 case 1024:
12886 default:
12887 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12888 DMA_RWCTRL_WRITE_BNDRY_1024);
12889 break;
855e1111 12890 }
59e6b434
DM		 12891 }
12892
12893out:
12894 return val;
12895}
12896
1da177e4
LT		 12897static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12898{
12899 struct tg3_internal_buffer_desc test_desc;
12900 u32 sram_dma_descs;
12901 int i, ret;
12902
12903 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12904
12905 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12906 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12907 tw32(RDMAC_STATUS, 0);
12908 tw32(WDMAC_STATUS, 0);
12909
12910 tw32(BUFMGR_MODE, 0);
12911 tw32(FTQ_RESET, 0);
12912
12913 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12914 test_desc.addr_lo = buf_dma & 0xffffffff;
12915 test_desc.nic_mbuf = 0x00002100;
12916 test_desc.len = size;
12917
12918 /*
12919 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12920 * the *second* time the tg3 driver was getting loaded after an
12921 * initial scan.
12922 *
12923 * Broadcom tells me:
12924 * ...the DMA engine is connected to the GRC block and a DMA
12925 * reset may affect the GRC block in some unpredictable way...
12926 * The behavior of resets to individual blocks has not been tested.
12927 *
12928 * Broadcom noted the GRC reset will also reset all sub-components.
12929 */
12930 if (to_device) {
12931 test_desc.cqid_sqid = (13 << 8) | 2;
12932
12933 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12934 udelay(40);
12935 } else {
12936 test_desc.cqid_sqid = (16 << 8) | 7;
12937
12938 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12939 udelay(40);
12940 }
12941 test_desc.flags = 0x00000005;
12942
12943 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12944 u32 val;
12945
12946 val = *(((u32 *)&test_desc) + i);
12947 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12948 sram_dma_descs + (i * sizeof(u32)));
12949 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12950 }
12951 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12952
12953 if (to_device) {
12954 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12955 } else {
12956 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12957 }
12958
12959 ret = -ENODEV;
12960 for (i = 0; i < 40; i++) {
12961 u32 val;
12962
12963 if (to_device)
12964 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12965 else
12966 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12967 if ((val & 0xffff) == sram_dma_descs) {
12968 ret = 0;
12969 break;
12970 }
12971
12972 udelay(100);
12973 }
12974
12975 return ret;
12976}
12977
ded7340d 12978#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 12979
12980static int __devinit tg3_test_dma(struct tg3 *tp)
12981{
12982 dma_addr_t buf_dma;
59e6b434 12983 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 12984 int ret;
12985
12986 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12987 if (!buf) {
12988 ret = -ENOMEM;
12989 goto out_nofree;
12990 }
12991
12992 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12993 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12994
59e6b434 12995 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 12996
12997 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12998 /* DMA read watermark not used on PCIE */
12999 tp->dma_rwctrl |= 0x00180000;
13000 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13003 tp->dma_rwctrl |= 0x003f0000;
13004 else
13005 tp->dma_rwctrl |= 0x003f000f;
13006 } else {
13007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13009 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13010 u32 read_water = 0x7;
1da177e4 13011
4a29cc2e
MC		 13012 /* If the 5704 is behind the EPB bridge, we can
13013 * do the less restrictive ONE_DMA workaround for
13014 * better performance.
13015 */
13016 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13017 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13018 tp->dma_rwctrl |= 0x8000;
13019 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13020 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13021
49afdeb6
MC		 13022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13023 read_water = 4;
59e6b434 13024 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13025 tp->dma_rwctrl |=
13026 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13027 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13028 (1 << 23);
4cf78e4f
MC		 13029 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13030 /* 5780 always in PCIX mode */
13031 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13032 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13033 /* 5714 always in PCIX mode */
13034 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13035 } else {
13036 tp->dma_rwctrl |= 0x001b000f;
13037 }
13038 }
13039
13040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13042 tp->dma_rwctrl &= 0xfffffff0;
13043
13044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13046 /* Remove this if it causes problems for some boards. */
13047 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13048
13049 /* On 5700/5701 chips, we need to set this bit.
13050 * Otherwise the chip will issue cacheline transactions
13051 * to streamable DMA memory with not all the byte
13052 * enables turned on. This is an error on several
13053 * RISC PCI controllers, in particular sparc64.
13054 *
13055 * On 5703/5704 chips, this bit has been reassigned
13056 * a different meaning. In particular, it is used
13057 * on those chips to enable a PCI-X workaround.
13058 */
13059 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13060 }
13061
13062 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13063
13064#if 0
13065 /* Unneeded, already done by tg3_get_invariants. */
13066 tg3_switch_clocks(tp);
13067#endif
13068
13069 ret = 0;
13070 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13071 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13072 goto out;
13073
59e6b434
DM		 13074 /* It is best to perform DMA test with maximum write burst size
13075 * to expose the 5700/5701 write DMA bug.
13076 */
13077 saved_dma_rwctrl = tp->dma_rwctrl;
13078 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13079 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13080
1da177e4
LT		 13081 while (1) {
13082 u32 *p = buf, i;
13083
13084 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13085 p[i] = i;
13086
13087 /* Send the buffer to the chip. */
13088 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13089 if (ret) {
13090 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13091 break;
13092 }
13093
13094#if 0
13095 /* validate data reached card RAM correctly. */
13096 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13097 u32 val;
13098 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13099 if (le32_to_cpu(val) != p[i]) {
13100 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13101 /* ret = -ENODEV here? */
13102 }
13103 p[i] = 0;
13104 }
13105#endif
13106 /* Now read it back. */
13107 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13108 if (ret) {
13109 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13110
13111 break;
13112 }
13113
13114 /* Verify it. */
13115 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13116 if (p[i] == i)
13117 continue;
13118
59e6b434
DM		 13119 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13120 DMA_RWCTRL_WRITE_BNDRY_16) {
13121 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13122 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13123 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13124 break;
13125 } else {
13126 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13127 ret = -ENODEV;
13128 goto out;
13129 }
13130 }
13131
13132 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13133 /* Success. */
13134 ret = 0;
13135 break;
13136 }
13137 }
59e6b434
DM		 13138 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13139 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13140 static struct pci_device_id dma_wait_state_chipsets[] = {
13141 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13142 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13143 { },
13144 };
13145
59e6b434 13146 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13147 * now look for chipsets that are known to expose the
13148 * DMA bug without failing the test.
59e6b434 13149 */
6d1cfbab
MC		 13150 if (pci_dev_present(dma_wait_state_chipsets)) {
13151 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13152 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13153 }
13154 else
13155 /* Safe to use the calculated DMA boundary. */
13156 tp->dma_rwctrl = saved_dma_rwctrl;
13157
59e6b434
DM		 13158 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13159 }
1da177e4
LT		 13160
13161out:
13162 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13163out_nofree:
13164 return ret;
13165}
13166
13167static void __devinit tg3_init_link_config(struct tg3 *tp)
13168{
13169 tp->link_config.advertising =
13170 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13171 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13172 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13173 ADVERTISED_Autoneg | ADVERTISED_MII);
13174 tp->link_config.speed = SPEED_INVALID;
13175 tp->link_config.duplex = DUPLEX_INVALID;
13176 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13177 tp->link_config.active_speed = SPEED_INVALID;
13178 tp->link_config.active_duplex = DUPLEX_INVALID;
13179 tp->link_config.phy_is_low_power = 0;
13180 tp->link_config.orig_speed = SPEED_INVALID;
13181 tp->link_config.orig_duplex = DUPLEX_INVALID;
13182 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13183}
13184
13185static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13186{
fdfec172
MC		 13187 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13188 tp->bufmgr_config.mbuf_read_dma_low_water =
13189 DEFAULT_MB_RDMA_LOW_WATER_5705;
13190 tp->bufmgr_config.mbuf_mac_rx_low_water =
13191 DEFAULT_MB_MACRX_LOW_WATER_5705;
13192 tp->bufmgr_config.mbuf_high_water =
13193 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13195 tp->bufmgr_config.mbuf_mac_rx_low_water =
13196 DEFAULT_MB_MACRX_LOW_WATER_5906;
13197 tp->bufmgr_config.mbuf_high_water =
13198 DEFAULT_MB_HIGH_WATER_5906;
13199 }
fdfec172
MC		 13200
13201 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13202 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13203 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13204 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13205 tp->bufmgr_config.mbuf_high_water_jumbo =
13206 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13207 } else {
13208 tp->bufmgr_config.mbuf_read_dma_low_water =
13209 DEFAULT_MB_RDMA_LOW_WATER;
13210 tp->bufmgr_config.mbuf_mac_rx_low_water =
13211 DEFAULT_MB_MACRX_LOW_WATER;
13212 tp->bufmgr_config.mbuf_high_water =
13213 DEFAULT_MB_HIGH_WATER;
13214
13215 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13216 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13217 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13218 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13219 tp->bufmgr_config.mbuf_high_water_jumbo =
13220 DEFAULT_MB_HIGH_WATER_JUMBO;
13221 }
1da177e4
LT		 13222
13223 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13224 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13225}
13226
13227static char * __devinit tg3_phy_string(struct tg3 *tp)
13228{
13229 switch (tp->phy_id & PHY_ID_MASK) {
13230 case PHY_ID_BCM5400: return "5400";
13231 case PHY_ID_BCM5401: return "5401";
13232 case PHY_ID_BCM5411: return "5411";
13233 case PHY_ID_BCM5701: return "5701";
13234 case PHY_ID_BCM5703: return "5703";
13235 case PHY_ID_BCM5704: return "5704";
13236 case PHY_ID_BCM5705: return "5705";
13237 case PHY_ID_BCM5750: return "5750";
85e94ced 13238 case PHY_ID_BCM5752: return "5752";
a4e2b347 13239 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13240 case PHY_ID_BCM5780: return "5780";
af36e6b6 13241 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13242 case PHY_ID_BCM5787: return "5787";
d30cdd28 13243 case PHY_ID_BCM5784: return "5784";
126a3368 13244 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13245 case PHY_ID_BCM5906: return "5906";
9936bcf6 13246 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13247 case PHY_ID_BCM8002: return "8002/serdes";
13248 case 0: return "serdes";
13249 default: return "unknown";
855e1111 13250 }
1da177e4
LT		 13251}
13252
f9804ddb
MC		 13253static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13254{
13255 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13256 strcpy(str, "PCI Express");
13257 return str;
13258 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13259 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13260
13261 strcpy(str, "PCIX:");
13262
13263 if ((clock_ctrl == 7) ||
13264 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13265 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13266 strcat(str, "133MHz");
13267 else if (clock_ctrl == 0)
13268 strcat(str, "33MHz");
13269 else if (clock_ctrl == 2)
13270 strcat(str, "50MHz");
13271 else if (clock_ctrl == 4)
13272 strcat(str, "66MHz");
13273 else if (clock_ctrl == 6)
13274 strcat(str, "100MHz");
f9804ddb
MC		 13275 } else {
13276 strcpy(str, "PCI:");
13277 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13278 strcat(str, "66MHz");
13279 else
13280 strcat(str, "33MHz");
13281 }
13282 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13283 strcat(str, ":32-bit");
13284 else
13285 strcat(str, ":64-bit");
13286 return str;
13287}
13288
8c2dc7e1 13289static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13290{
13291 struct pci_dev *peer;
13292 unsigned int func, devnr = tp->pdev->devfn & ~7;
13293
13294 for (func = 0; func < 8; func++) {
13295 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13296 if (peer && peer != tp->pdev)
13297 break;
13298 pci_dev_put(peer);
13299 }
16fe9d74
MC		 13300 /* 5704 can be configured in single-port mode, set peer to
13301 * tp->pdev in that case.
13302 */
13303 if (!peer) {
13304 peer = tp->pdev;
13305 return peer;
13306 }
1da177e4
LT		 13307
13308 /*
13309 * We don't need to keep the refcount elevated; there's no way
13310 * to remove one half of this device without removing the other
13311 */
13312 pci_dev_put(peer);
13313
13314 return peer;
13315}
13316
15f9850d
DM		 13317static void __devinit tg3_init_coal(struct tg3 *tp)
13318{
13319 struct ethtool_coalesce *ec = &tp->coal;
13320
13321 memset(ec, 0, sizeof(*ec));
13322 ec->cmd = ETHTOOL_GCOALESCE;
13323 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13324 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13325 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13326 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13327 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13328 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13329 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13330 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13331 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13332
13333 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13334 HOSTCC_MODE_CLRTICK_TXBD)) {
13335 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13336 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13337 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13338 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13339 }
d244c892
MC		 13340
13341 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13342 ec->rx_coalesce_usecs_irq = 0;
13343 ec->tx_coalesce_usecs_irq = 0;
13344 ec->stats_block_coalesce_usecs = 0;
13345 }
15f9850d
DM		 13346}
13347
7c7d64b8
SH		 13348static const struct net_device_ops tg3_netdev_ops = {
13349 .ndo_open = tg3_open,
13350 .ndo_stop = tg3_close,
00829823
SH		 13351 .ndo_start_xmit = tg3_start_xmit,
13352 .ndo_get_stats = tg3_get_stats,
13353 .ndo_validate_addr = eth_validate_addr,
13354 .ndo_set_multicast_list = tg3_set_rx_mode,
13355 .ndo_set_mac_address = tg3_set_mac_addr,
13356 .ndo_do_ioctl = tg3_ioctl,
13357 .ndo_tx_timeout = tg3_tx_timeout,
13358 .ndo_change_mtu = tg3_change_mtu,
13359#if TG3_VLAN_TAG_USED
13360 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13361#endif
13362#ifdef CONFIG_NET_POLL_CONTROLLER
13363 .ndo_poll_controller = tg3_poll_controller,
13364#endif
13365};
13366
13367static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13368 .ndo_open = tg3_open,
13369 .ndo_stop = tg3_close,
13370 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13371 .ndo_get_stats = tg3_get_stats,
13372 .ndo_validate_addr = eth_validate_addr,
13373 .ndo_set_multicast_list = tg3_set_rx_mode,
13374 .ndo_set_mac_address = tg3_set_mac_addr,
13375 .ndo_do_ioctl = tg3_ioctl,
13376 .ndo_tx_timeout = tg3_tx_timeout,
13377 .ndo_change_mtu = tg3_change_mtu,
13378#if TG3_VLAN_TAG_USED
13379 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13380#endif
13381#ifdef CONFIG_NET_POLL_CONTROLLER
13382 .ndo_poll_controller = tg3_poll_controller,
13383#endif
13384};
13385
1da177e4
LT		 13386static int __devinit tg3_init_one(struct pci_dev *pdev,
13387 const struct pci_device_id *ent)
13388{
13389 static int tg3_version_printed = 0;
1da177e4
LT		 13390 struct net_device *dev;
13391 struct tg3 *tp;
d6645372 13392 int err, pm_cap;
f9804ddb 13393 char str[40];
72f2afb8 13394 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13395
13396 if (tg3_version_printed++ == 0)
13397 printk(KERN_INFO "%s", version);
13398
13399 err = pci_enable_device(pdev);
13400 if (err) {
13401 printk(KERN_ERR PFX "Cannot enable PCI device, "
13402 "aborting.\n");
13403 return err;
13404 }
13405
1da177e4
LT		 13406 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13407 if (err) {
13408 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13409 "aborting.\n");
13410 goto err_out_disable_pdev;
13411 }
13412
13413 pci_set_master(pdev);
13414
13415 /* Find power-management capability. */
13416 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13417 if (pm_cap == 0) {
13418 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13419 "aborting.\n");
13420 err = -EIO;
13421 goto err_out_free_res;
13422 }
13423
1da177e4
LT		 13424 dev = alloc_etherdev(sizeof(*tp));
13425 if (!dev) {
13426 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13427 err = -ENOMEM;
13428 goto err_out_free_res;
13429 }
13430
1da177e4
LT		 13431 SET_NETDEV_DEV(dev, &pdev->dev);
13432
1da177e4
LT		 13433#if TG3_VLAN_TAG_USED
13434 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13435#endif
13436
13437 tp = netdev_priv(dev);
13438 tp->pdev = pdev;
13439 tp->dev = dev;
13440 tp->pm_cap = pm_cap;
1da177e4
LT		 13441 tp->rx_mode = TG3_DEF_RX_MODE;
13442 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13443
1da177e4
LT		 13444 if (tg3_debug > 0)
13445 tp->msg_enable = tg3_debug;
13446 else
13447 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13448
13449 /* The word/byte swap controls here control register access byte
13450 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13451 * setting below.
13452 */
13453 tp->misc_host_ctrl =
13454 MISC_HOST_CTRL_MASK_PCI_INT |
13455 MISC_HOST_CTRL_WORD_SWAP |
13456 MISC_HOST_CTRL_INDIR_ACCESS |
13457 MISC_HOST_CTRL_PCISTATE_RW;
13458
13459 /* The NONFRM (non-frame) byte/word swap controls take effect
13460 * on descriptor entries, anything which isn't packet data.
13461 *
13462 * The StrongARM chips on the board (one for tx, one for rx)
13463 * are running in big-endian mode.
13464 */
13465 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13466 GRC_MODE_WSWAP_NONFRM_DATA);
13467#ifdef __BIG_ENDIAN
13468 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13469#endif
13470 spin_lock_init(&tp->lock);
1da177e4 13471 spin_lock_init(&tp->indirect_lock);
c4028958 13472 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13473
d5fe488a 13474 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13475 if (!tp->regs) {
1da177e4
LT		 13476 printk(KERN_ERR PFX "Cannot map device registers, "
13477 "aborting.\n");
13478 err = -ENOMEM;
13479 goto err_out_free_dev;
13480 }
13481
13482 tg3_init_link_config(tp);
13483
1da177e4
LT		 13484 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13485 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 13486
8ef0442f 13487 tp->napi[0].tp = tp;
898a56f8 13488 tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
72334482 13489 tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
f3f3f27e 13490 tp->napi[0].prodmbox = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
fd2ce37f 13491 tp->napi[0].coal_now = HOSTCC_MODE_NOW;
f3f3f27e 13492 tp->napi[0].tx_pending = TG3_DEF_TX_RING_PENDING;
8ef0442f 13493 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 13494 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13495 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13496 dev->irq = pdev->irq;
1da177e4
LT		 13497
13498 err = tg3_get_invariants(tp);
13499 if (err) {
13500 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13501 "aborting.\n");
13502 goto err_out_iounmap;
13503 }
13504
321d32a0 13505 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13507 dev->netdev_ops = &tg3_netdev_ops;
13508 else
13509 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13510
13511
4a29cc2e
MC		 13512 /* The EPB bridge inside 5714, 5715, and 5780 and any
13513 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13514 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13515 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13516 * do DMA address check in tg3_start_xmit().
13517 */
4a29cc2e 13518 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13519 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13520 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13521 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13522#ifdef CONFIG_HIGHMEM
6a35528a 13523 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13524#endif
4a29cc2e 13525 } else
6a35528a 13526 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13527
13528 /* Configure DMA attributes. */
284901a9 13529 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13530 err = pci_set_dma_mask(pdev, dma_mask);
13531 if (!err) {
13532 dev->features |= NETIF_F_HIGHDMA;
13533 err = pci_set_consistent_dma_mask(pdev,
13534 persist_dma_mask);
13535 if (err < 0) {
13536 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13537 "DMA for consistent allocations\n");
13538 goto err_out_iounmap;
13539 }
13540 }
13541 }
284901a9
YH		 13542 if (err || dma_mask == DMA_BIT_MASK(32)) {
13543 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13544 if (err) {
13545 printk(KERN_ERR PFX "No usable DMA configuration, "
13546 "aborting.\n");
13547 goto err_out_iounmap;
13548 }
13549 }
13550
fdfec172 13551 tg3_init_bufmgr_config(tp);
1da177e4 13552
077f849d 13553 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13554 tp->fw_needed = FIRMWARE_TG3;
077f849d 13555
1da177e4
LT		 13556 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13557 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13558 }
13559 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13560 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13561 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13562 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13563 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13564 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13565 } else {
7f62ad5d 13566 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13567 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13568 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13569 else
9e9fd12d 13570 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13571 }
1da177e4 13572
4e3a7aaa
MC		 13573 /* TSO is on by default on chips that support hardware TSO.
13574 * Firmware TSO on older chips gives lower performance, so it
13575 * is off by default, but can be enabled using ethtool.
13576 */
b0026624 13577 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13578 if (dev->features & NETIF_F_IP_CSUM)
13579 dev->features |= NETIF_F_TSO;
13580 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13581 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13582 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13583 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13584 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13585 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13588 dev->features |= NETIF_F_TSO_ECN;
b0026624 13589 }
1da177e4 13590
1da177e4
LT		 13591
13592 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13593 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13594 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13595 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13596 tp->rx_pending = 63;
13597 }
13598
1da177e4
LT		 13599 err = tg3_get_device_address(tp);
13600 if (err) {
13601 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13602 "aborting.\n");
077f849d 13603 goto err_out_fw;
1da177e4
LT		 13604 }
13605
c88864df 13606 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13607 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13608 if (!tp->aperegs) {
c88864df
MC		 13609 printk(KERN_ERR PFX "Cannot map APE registers, "
13610 "aborting.\n");
13611 err = -ENOMEM;
077f849d 13612 goto err_out_fw;
c88864df
MC		 13613 }
13614
13615 tg3_ape_lock_init(tp);
7fd76445
MC		 13616
13617 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13618 tg3_read_dash_ver(tp);
c88864df
MC		 13619 }
13620
1da177e4
LT		 13621 /*
13622 * Reset chip in case UNDI or EFI driver did not shutdown
13623 * DMA self test will enable WDMAC and we'll see (spurious)
13624 * pending DMA on the PCI bus at that point.
13625 */
13626 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13627 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13628 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13629 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13630 }
13631
13632 err = tg3_test_dma(tp);
13633 if (err) {
13634 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13635 goto err_out_apeunmap;
1da177e4
LT		 13636 }
13637
1da177e4
LT		 13638 /* flow control autonegotiation is default behavior */
13639 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13640 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13641
15f9850d
DM		 13642 tg3_init_coal(tp);
13643
c49a1561
MC		 13644 pci_set_drvdata(pdev, dev);
13645
1da177e4
LT		 13646 err = register_netdev(dev);
13647 if (err) {
13648 printk(KERN_ERR PFX "Cannot register net device, "
13649 "aborting.\n");
0d3031d9 13650 goto err_out_apeunmap;
1da177e4
LT		 13651 }
13652
df59c940 13653 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13654 dev->name,
13655 tp->board_part_number,
13656 tp->pci_chip_rev_id,
f9804ddb 13657 tg3_bus_string(tp, str),
e174961c 13658 dev->dev_addr);
1da177e4 13659
df59c940
MC		 13660 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13661 printk(KERN_INFO
13662 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13663 tp->dev->name,
13664 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13665 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13666 else
13667 printk(KERN_INFO
13668 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13669 tp->dev->name, tg3_phy_string(tp),
13670 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13671 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13672 "10/100/1000Base-T")),
13673 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13674
13675 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13676 dev->name,
13677 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13678 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13679 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13680 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13681 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13682 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13683 dev->name, tp->dma_rwctrl,
284901a9 13684 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13685 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13686
13687 return 0;
13688
0d3031d9
MC		 13689err_out_apeunmap:
13690 if (tp->aperegs) {
13691 iounmap(tp->aperegs);
13692 tp->aperegs = NULL;
13693 }
13694
077f849d
JSR		 13695err_out_fw:
13696 if (tp->fw)
13697 release_firmware(tp->fw);
13698
1da177e4 13699err_out_iounmap:
6892914f
MC		 13700 if (tp->regs) {
13701 iounmap(tp->regs);
22abe310 13702 tp->regs = NULL;
6892914f 13703 }
1da177e4
LT		 13704
13705err_out_free_dev:
13706 free_netdev(dev);
13707
13708err_out_free_res:
13709 pci_release_regions(pdev);
13710
13711err_out_disable_pdev:
13712 pci_disable_device(pdev);
13713 pci_set_drvdata(pdev, NULL);
13714 return err;
13715}
13716
13717static void __devexit tg3_remove_one(struct pci_dev *pdev)
13718{
13719 struct net_device *dev = pci_get_drvdata(pdev);
13720
13721 if (dev) {
13722 struct tg3 *tp = netdev_priv(dev);
13723
077f849d
JSR		 13724 if (tp->fw)
13725 release_firmware(tp->fw);
13726
7faa006f 13727 flush_scheduled_work();
158d7abd 13728
b02fd9e3
MC		 13729 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13730 tg3_phy_fini(tp);
158d7abd 13731 tg3_mdio_fini(tp);
b02fd9e3 13732 }
158d7abd 13733
1da177e4 13734 unregister_netdev(dev);
0d3031d9
MC		 13735 if (tp->aperegs) {
13736 iounmap(tp->aperegs);
13737 tp->aperegs = NULL;
13738 }
6892914f
MC		 13739 if (tp->regs) {
13740 iounmap(tp->regs);
22abe310 13741 tp->regs = NULL;
6892914f 13742 }
1da177e4
LT		 13743 free_netdev(dev);
13744 pci_release_regions(pdev);
13745 pci_disable_device(pdev);
13746 pci_set_drvdata(pdev, NULL);
13747 }
13748}
13749
13750static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13751{
13752 struct net_device *dev = pci_get_drvdata(pdev);
13753 struct tg3 *tp = netdev_priv(dev);
12dac075 13754 pci_power_t target_state;
1da177e4
LT		 13755 int err;
13756
3e0c95fd
MC		 13757 /* PCI register 4 needs to be saved whether netif_running() or not.
13758 * MSI address and data need to be saved if using MSI and
13759 * netif_running().
13760 */
13761 pci_save_state(pdev);
13762
1da177e4
LT		 13763 if (!netif_running(dev))
13764 return 0;
13765
7faa006f 13766 flush_scheduled_work();
b02fd9e3 13767 tg3_phy_stop(tp);
1da177e4
LT		 13768 tg3_netif_stop(tp);
13769
13770 del_timer_sync(&tp->timer);
13771
f47c11ee 13772 tg3_full_lock(tp, 1);
1da177e4 13773 tg3_disable_ints(tp);
f47c11ee 13774 tg3_full_unlock(tp);
1da177e4
LT		 13775
13776 netif_device_detach(dev);
13777
f47c11ee 13778 tg3_full_lock(tp, 0);
944d980e 13779 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13780 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13781 tg3_full_unlock(tp);
1da177e4 13782
12dac075
RW		 13783 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13784
13785 err = tg3_set_power_state(tp, target_state);
1da177e4 13786 if (err) {
b02fd9e3
MC		 13787 int err2;
13788
f47c11ee 13789 tg3_full_lock(tp, 0);
1da177e4 13790
6a9eba15 13791 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13792 err2 = tg3_restart_hw(tp, 1);
13793 if (err2)
b9ec6c1b 13794 goto out;
1da177e4
LT		 13795
13796 tp->timer.expires = jiffies + tp->timer_offset;
13797 add_timer(&tp->timer);
13798
13799 netif_device_attach(dev);
13800 tg3_netif_start(tp);
13801
b9ec6c1b 13802out:
f47c11ee 13803 tg3_full_unlock(tp);
b02fd9e3
MC		 13804
13805 if (!err2)
13806 tg3_phy_start(tp);
1da177e4
LT		 13807 }
13808
13809 return err;
13810}
13811
13812static int tg3_resume(struct pci_dev *pdev)
13813{
13814 struct net_device *dev = pci_get_drvdata(pdev);
13815 struct tg3 *tp = netdev_priv(dev);
13816 int err;
13817
3e0c95fd
MC		 13818 pci_restore_state(tp->pdev);
13819
1da177e4
LT		 13820 if (!netif_running(dev))
13821 return 0;
13822
bc1c7567 13823 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13824 if (err)
13825 return err;
13826
13827 netif_device_attach(dev);
13828
f47c11ee 13829 tg3_full_lock(tp, 0);
1da177e4 13830
6a9eba15 13831 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13832 err = tg3_restart_hw(tp, 1);
13833 if (err)
13834 goto out;
1da177e4
LT		 13835
13836 tp->timer.expires = jiffies + tp->timer_offset;
13837 add_timer(&tp->timer);
13838
1da177e4
LT		 13839 tg3_netif_start(tp);
13840
b9ec6c1b 13841out:
f47c11ee 13842 tg3_full_unlock(tp);
1da177e4 13843
b02fd9e3
MC		 13844 if (!err)
13845 tg3_phy_start(tp);
13846
b9ec6c1b 13847 return err;
1da177e4
LT		 13848}
13849
13850static struct pci_driver tg3_driver = {
13851 .name = DRV_MODULE_NAME,
13852 .id_table = tg3_pci_tbl,
13853 .probe = tg3_init_one,
13854 .remove = __devexit_p(tg3_remove_one),
13855 .suspend = tg3_suspend,
13856 .resume = tg3_resume
13857};
13858
13859static int __init tg3_init(void)
13860{
29917620 13861 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13862}
13863
13864static void __exit tg3_cleanup(void)
13865{
13866 pci_unregister_driver(&tg3_driver);
13867}
13868
13869module_init(tg3_init);
13870module_exit(tg3_cleanup);
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