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[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
fc57e515
MC		 71#define DRV_MODULE_VERSION "3.101"
72#define DRV_MODULE_RELDATE "August 28, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106/* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112#define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115#define TG3_TX_RING_SIZE 512
116#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
79ed5ac7
MC		 120#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
1da177e4 122#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 123 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 124#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
1da177e4
LT		 126#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
287be12e
MC		 128#define TG3_DMA_BYTE_ENAB 64
129
130#define TG3_RX_STD_DMA_SZ 1536
131#define TG3_RX_JMB_DMA_SZ 9046
132
133#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
134
135#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 137
138/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 139#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 140
ad829268
MC		 141#define TG3_RAW_IP_ALIGN 2
142
1da177e4
LT		 143/* number of ETHTOOL_GSTATS u64's */
144#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
145
4cafd3f5
MC		 146#define TG3_NUM_TEST 6
147
077f849d
JSR		 148#define FIRMWARE_TG3 "tigon/tg3.bin"
149#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
151
1da177e4
LT		 152static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
154
155MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157MODULE_LICENSE("GPL");
158MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 159MODULE_FIRMWARE(FIRMWARE_TG3);
160MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
162
679563f4 163#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 164
165static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
166module_param(tg3_debug, int, 0);
167MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
168
169static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
242 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
243 {}
1da177e4
LT		 244};
245
246MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
247
50da859d 248static const struct {
1da177e4
LT		 249 const char string[ETH_GSTRING_LEN];
250} ethtool_stats_keys[TG3_NUM_STATS] = {
251 { "rx_octets" },
252 { "rx_fragments" },
253 { "rx_ucast_packets" },
254 { "rx_mcast_packets" },
255 { "rx_bcast_packets" },
256 { "rx_fcs_errors" },
257 { "rx_align_errors" },
258 { "rx_xon_pause_rcvd" },
259 { "rx_xoff_pause_rcvd" },
260 { "rx_mac_ctrl_rcvd" },
261 { "rx_xoff_entered" },
262 { "rx_frame_too_long_errors" },
263 { "rx_jabbers" },
264 { "rx_undersize_packets" },
265 { "rx_in_length_errors" },
266 { "rx_out_length_errors" },
267 { "rx_64_or_less_octet_packets" },
268 { "rx_65_to_127_octet_packets" },
269 { "rx_128_to_255_octet_packets" },
270 { "rx_256_to_511_octet_packets" },
271 { "rx_512_to_1023_octet_packets" },
272 { "rx_1024_to_1522_octet_packets" },
273 { "rx_1523_to_2047_octet_packets" },
274 { "rx_2048_to_4095_octet_packets" },
275 { "rx_4096_to_8191_octet_packets" },
276 { "rx_8192_to_9022_octet_packets" },
277
278 { "tx_octets" },
279 { "tx_collisions" },
280
281 { "tx_xon_sent" },
282 { "tx_xoff_sent" },
283 { "tx_flow_control" },
284 { "tx_mac_errors" },
285 { "tx_single_collisions" },
286 { "tx_mult_collisions" },
287 { "tx_deferred" },
288 { "tx_excessive_collisions" },
289 { "tx_late_collisions" },
290 { "tx_collide_2times" },
291 { "tx_collide_3times" },
292 { "tx_collide_4times" },
293 { "tx_collide_5times" },
294 { "tx_collide_6times" },
295 { "tx_collide_7times" },
296 { "tx_collide_8times" },
297 { "tx_collide_9times" },
298 { "tx_collide_10times" },
299 { "tx_collide_11times" },
300 { "tx_collide_12times" },
301 { "tx_collide_13times" },
302 { "tx_collide_14times" },
303 { "tx_collide_15times" },
304 { "tx_ucast_packets" },
305 { "tx_mcast_packets" },
306 { "tx_bcast_packets" },
307 { "tx_carrier_sense_errors" },
308 { "tx_discards" },
309 { "tx_errors" },
310
311 { "dma_writeq_full" },
312 { "dma_write_prioq_full" },
313 { "rxbds_empty" },
314 { "rx_discards" },
315 { "rx_errors" },
316 { "rx_threshold_hit" },
317
318 { "dma_readq_full" },
319 { "dma_read_prioq_full" },
320 { "tx_comp_queue_full" },
321
322 { "ring_set_send_prod_index" },
323 { "ring_status_update" },
324 { "nic_irqs" },
325 { "nic_avoided_irqs" },
326 { "nic_tx_threshold_hit" }
327};
328
50da859d 329static const struct {
4cafd3f5
MC		 330 const char string[ETH_GSTRING_LEN];
331} ethtool_test_keys[TG3_NUM_TEST] = {
332 { "nvram test (online) " },
333 { "link test (online) " },
334 { "register test (offline)" },
335 { "memory test (offline)" },
336 { "loopback test (offline)" },
337 { "interrupt test (offline)" },
338};
339
b401e9e2
MC		 340static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
341{
342 writel(val, tp->regs + off);
343}
344
345static u32 tg3_read32(struct tg3 *tp, u32 off)
346{
6aa20a22 347 return (readl(tp->regs + off));
b401e9e2
MC		 348}
349
0d3031d9
MC		 350static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
351{
352 writel(val, tp->aperegs + off);
353}
354
355static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
356{
357 return (readl(tp->aperegs + off));
358}
359
1da177e4
LT		 360static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
361{
6892914f
MC		 362 unsigned long flags;
363
364 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 365 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
366 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 367 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 368}
369
370static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
371{
372 writel(val, tp->regs + off);
373 readl(tp->regs + off);
1da177e4
LT		 374}
375
6892914f 376static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 377{
6892914f
MC		 378 unsigned long flags;
379 u32 val;
380
381 spin_lock_irqsave(&tp->indirect_lock, flags);
382 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
383 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
384 spin_unlock_irqrestore(&tp->indirect_lock, flags);
385 return val;
386}
387
388static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
389{
390 unsigned long flags;
391
392 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
393 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
394 TG3_64BIT_REG_LOW, val);
395 return;
396 }
397 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
398 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
399 TG3_64BIT_REG_LOW, val);
400 return;
1da177e4 401 }
6892914f
MC		 402
403 spin_lock_irqsave(&tp->indirect_lock, flags);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
405 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
406 spin_unlock_irqrestore(&tp->indirect_lock, flags);
407
408 /* In indirect mode when disabling interrupts, we also need
409 * to clear the interrupt bit in the GRC local ctrl register.
410 */
411 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
412 (val == 0x1)) {
413 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
414 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
415 }
416}
417
418static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
419{
420 unsigned long flags;
421 u32 val;
422
423 spin_lock_irqsave(&tp->indirect_lock, flags);
424 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
425 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
426 spin_unlock_irqrestore(&tp->indirect_lock, flags);
427 return val;
428}
429
b401e9e2
MC		 430/* usec_wait specifies the wait time in usec when writing to certain registers
431 * where it is unsafe to read back the register without some delay.
432 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
433 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
434 */
435static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 436{
b401e9e2
MC		 437 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
438 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
439 /* Non-posted methods */
440 tp->write32(tp, off, val);
441 else {
442 /* Posted method */
443 tg3_write32(tp, off, val);
444 if (usec_wait)
445 udelay(usec_wait);
446 tp->read32(tp, off);
447 }
448 /* Wait again after the read for the posted method to guarantee that
449 * the wait time is met.
450 */
451 if (usec_wait)
452 udelay(usec_wait);
1da177e4
LT		 453}
454
09ee929c
MC		 455static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
456{
457 tp->write32_mbox(tp, off, val);
6892914f
MC		 458 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
459 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
460 tp->read32_mbox(tp, off);
09ee929c
MC		 461}
462
20094930 463static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 464{
465 void __iomem *mbox = tp->regs + off;
466 writel(val, mbox);
467 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
470 readl(mbox);
471}
472
b5d3772c
MC		 473static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
474{
475 return (readl(tp->regs + off + GRCMBOX_BASE));
476}
477
478static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
479{
480 writel(val, tp->regs + off + GRCMBOX_BASE);
481}
482
20094930 483#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 484#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 485#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
486#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 487#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 488
489#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 490#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
491#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 492#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 493
494static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
495{
6892914f
MC		 496 unsigned long flags;
497
b5d3772c
MC		 498 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
499 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
500 return;
501
6892914f 502 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 503 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 506
bbadf503
MC		 507 /* Always leave this as zero. */
508 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
509 } else {
510 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
511 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 512
bbadf503
MC		 513 /* Always leave this as zero. */
514 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
515 }
516 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 517}
518
1da177e4
LT		 519static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
520{
6892914f
MC		 521 unsigned long flags;
522
b5d3772c
MC		 523 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
524 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
525 *val = 0;
526 return;
527 }
528
6892914f 529 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 530 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
531 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
532 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 533
bbadf503
MC		 534 /* Always leave this as zero. */
535 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
536 } else {
537 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
538 *val = tr32(TG3PCI_MEM_WIN_DATA);
539
540 /* Always leave this as zero. */
541 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
542 }
6892914f 543 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 544}
545
0d3031d9
MC		 546static void tg3_ape_lock_init(struct tg3 *tp)
547{
548 int i;
549
550 /* Make sure the driver hasn't any stale locks. */
551 for (i = 0; i < 8; i++)
552 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
553 APE_LOCK_GRANT_DRIVER);
554}
555
556static int tg3_ape_lock(struct tg3 *tp, int locknum)
557{
558 int i, off;
559 int ret = 0;
560 u32 status;
561
562 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
563 return 0;
564
565 switch (locknum) {
77b483f1 566 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 567 case TG3_APE_LOCK_MEM:
568 break;
569 default:
570 return -EINVAL;
571 }
572
573 off = 4 * locknum;
574
575 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
576
577 /* Wait for up to 1 millisecond to acquire lock. */
578 for (i = 0; i < 100; i++) {
579 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
580 if (status == APE_LOCK_GRANT_DRIVER)
581 break;
582 udelay(10);
583 }
584
585 if (status != APE_LOCK_GRANT_DRIVER) {
586 /* Revoke the lock request. */
587 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
588 APE_LOCK_GRANT_DRIVER);
589
590 ret = -EBUSY;
591 }
592
593 return ret;
594}
595
596static void tg3_ape_unlock(struct tg3 *tp, int locknum)
597{
598 int off;
599
600 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
601 return;
602
603 switch (locknum) {
77b483f1 604 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 605 case TG3_APE_LOCK_MEM:
606 break;
607 default:
608 return;
609 }
610
611 off = 4 * locknum;
612 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
613}
614
1da177e4
LT		 615static void tg3_disable_ints(struct tg3 *tp)
616{
617 tw32(TG3PCI_MISC_HOST_CTRL,
618 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
898a56f8 619 tw32_mailbox_f(tp->napi[0].int_mbox, 0x00000001);
1da177e4
LT		 620}
621
1da177e4
LT		 622static void tg3_enable_ints(struct tg3 *tp)
623{
f19af9c2 624 u32 coal_now;
898a56f8 625 struct tg3_napi *tnapi = &tp->napi[0];
bbe832c0
MC		 626 tp->irq_sync = 0;
627 wmb();
628
1da177e4
LT		 629 tw32(TG3PCI_MISC_HOST_CTRL,
630 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
898a56f8 631 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
fcfa0a32 632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
898a56f8 633 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 634
fd2ce37f 635 coal_now = tnapi->coal_now;
f19af9c2
MC		 636
637 /* Force an initial interrupt */
638 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
639 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
640 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
641 else
642 tw32(HOSTCC_MODE, tp->coalesce_mode |
643 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 644}
645
17375d25 646static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 647{
17375d25 648 struct tg3 *tp = tnapi->tp;
898a56f8 649 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 650 unsigned int work_exists = 0;
651
652 /* check for phy events */
653 if (!(tp->tg3_flags &
654 (TG3_FLAG_USE_LINKCHG_REG |
655 TG3_FLAG_POLL_SERDES))) {
656 if (sblk->status & SD_STATUS_LINK_CHG)
657 work_exists = 1;
658 }
659 /* check for RX/TX work to do */
f3f3f27e 660 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
72334482 661 sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
04237ddd
MC		 662 work_exists = 1;
663
664 return work_exists;
665}
666
17375d25 667/* tg3_int_reenable
04237ddd
MC		 668 * similar to tg3_enable_ints, but it accurately determines whether there
669 * is new work pending and can return without flushing the PIO write
6aa20a22 670 * which reenables interrupts
1da177e4 671 */
17375d25 672static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 673{
17375d25
MC		 674 struct tg3 *tp = tnapi->tp;
675
898a56f8 676 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 677 mmiowb();
678
fac9b83e
DM		 679 /* When doing tagged status, this work check is unnecessary.
680 * The last_tag we write above tells the chip which piece of
681 * work we've completed.
682 */
683 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 684 tg3_has_work(tnapi))
04237ddd 685 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 686 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 687}
688
689static inline void tg3_netif_stop(struct tg3 *tp)
690{
bbe832c0 691 tp->dev->trans_start = jiffies; /* prevent tx timeout */
8ef0442f 692 napi_disable(&tp->napi[0].napi);
1da177e4
LT		 693 netif_tx_disable(tp->dev);
694}
695
696static inline void tg3_netif_start(struct tg3 *tp)
697{
898a56f8 698 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 699 netif_wake_queue(tp->dev);
700 /* NOTE: unconditional netif_wake_queue is only appropriate
701 * so long as all callers are assured to have free tx slots
702 * (such as after tg3_init_hw)
703 */
898a56f8
MC		 704 napi_enable(&tnapi->napi);
705 tnapi->hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 706 tg3_enable_ints(tp);
1da177e4
LT		 707}
708
709static void tg3_switch_clocks(struct tg3 *tp)
710{
711 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
712 u32 orig_clock_ctrl;
713
795d01c5
MC		 714 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
715 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 716 return;
717
1da177e4
LT		 718 orig_clock_ctrl = clock_ctrl;
719 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
720 CLOCK_CTRL_CLKRUN_OENABLE |
721 0x1f);
722 tp->pci_clock_ctrl = clock_ctrl;
723
724 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
725 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 726 tw32_wait_f(TG3PCI_CLOCK_CTRL,
727 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 728 }
729 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 730 tw32_wait_f(TG3PCI_CLOCK_CTRL,
731 clock_ctrl |
732 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
733 40);
734 tw32_wait_f(TG3PCI_CLOCK_CTRL,
735 clock_ctrl | (CLOCK_CTRL_ALTCLK),
736 40);
1da177e4 737 }
b401e9e2 738 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 739}
740
741#define PHY_BUSY_LOOPS 5000
742
743static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
744{
745 u32 frame_val;
746 unsigned int loops;
747 int ret;
748
749 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
750 tw32_f(MAC_MI_MODE,
751 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
752 udelay(80);
753 }
754
755 *val = 0x0;
756
757 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
758 MI_COM_PHY_ADDR_MASK);
759 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
760 MI_COM_REG_ADDR_MASK);
761 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 762
1da177e4
LT		 763 tw32_f(MAC_MI_COM, frame_val);
764
765 loops = PHY_BUSY_LOOPS;
766 while (loops != 0) {
767 udelay(10);
768 frame_val = tr32(MAC_MI_COM);
769
770 if ((frame_val & MI_COM_BUSY) == 0) {
771 udelay(5);
772 frame_val = tr32(MAC_MI_COM);
773 break;
774 }
775 loops -= 1;
776 }
777
778 ret = -EBUSY;
779 if (loops != 0) {
780 *val = frame_val & MI_COM_DATA_MASK;
781 ret = 0;
782 }
783
784 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
785 tw32_f(MAC_MI_MODE, tp->mi_mode);
786 udelay(80);
787 }
788
789 return ret;
790}
791
792static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
793{
794 u32 frame_val;
795 unsigned int loops;
796 int ret;
797
7f97a4bd 798 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 799 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
800 return 0;
801
1da177e4
LT		 802 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
803 tw32_f(MAC_MI_MODE,
804 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
805 udelay(80);
806 }
807
808 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
809 MI_COM_PHY_ADDR_MASK);
810 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
811 MI_COM_REG_ADDR_MASK);
812 frame_val |= (val & MI_COM_DATA_MASK);
813 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 814
1da177e4
LT		 815 tw32_f(MAC_MI_COM, frame_val);
816
817 loops = PHY_BUSY_LOOPS;
818 while (loops != 0) {
819 udelay(10);
820 frame_val = tr32(MAC_MI_COM);
821 if ((frame_val & MI_COM_BUSY) == 0) {
822 udelay(5);
823 frame_val = tr32(MAC_MI_COM);
824 break;
825 }
826 loops -= 1;
827 }
828
829 ret = -EBUSY;
830 if (loops != 0)
831 ret = 0;
832
833 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
834 tw32_f(MAC_MI_MODE, tp->mi_mode);
835 udelay(80);
836 }
837
838 return ret;
839}
840
95e2869a
MC		 841static int tg3_bmcr_reset(struct tg3 *tp)
842{
843 u32 phy_control;
844 int limit, err;
845
846 /* OK, reset it, and poll the BMCR_RESET bit until it
847 * clears or we time out.
848 */
849 phy_control = BMCR_RESET;
850 err = tg3_writephy(tp, MII_BMCR, phy_control);
851 if (err != 0)
852 return -EBUSY;
853
854 limit = 5000;
855 while (limit--) {
856 err = tg3_readphy(tp, MII_BMCR, &phy_control);
857 if (err != 0)
858 return -EBUSY;
859
860 if ((phy_control & BMCR_RESET) == 0) {
861 udelay(40);
862 break;
863 }
864 udelay(10);
865 }
d4675b52 866 if (limit < 0)
95e2869a
MC		 867 return -EBUSY;
868
869 return 0;
870}
871
158d7abd
MC		 872static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
873{
3d16543d 874 struct tg3 *tp = bp->priv;
158d7abd
MC		 875 u32 val;
876
877 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
878 return -EAGAIN;
879
880 if (tg3_readphy(tp, reg, &val))
881 return -EIO;
882
883 return val;
884}
885
886static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
887{
3d16543d 888 struct tg3 *tp = bp->priv;
158d7abd
MC		 889
890 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
891 return -EAGAIN;
892
893 if (tg3_writephy(tp, reg, val))
894 return -EIO;
895
896 return 0;
897}
898
899static int tg3_mdio_reset(struct mii_bus *bp)
900{
901 return 0;
902}
903
9c61d6bc 904static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 905{
906 u32 val;
fcb389df 907 struct phy_device *phydev;
a9daf367 908
fcb389df
MC		 909 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
910 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
911 case TG3_PHY_ID_BCM50610:
912 val = MAC_PHYCFG2_50610_LED_MODES;
913 break;
914 case TG3_PHY_ID_BCMAC131:
915 val = MAC_PHYCFG2_AC131_LED_MODES;
916 break;
917 case TG3_PHY_ID_RTL8211C:
918 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
919 break;
920 case TG3_PHY_ID_RTL8201E:
921 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
922 break;
923 default:
a9daf367 924 return;
fcb389df
MC		 925 }
926
927 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
928 tw32(MAC_PHYCFG2, val);
929
930 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 931 val &= ~(MAC_PHYCFG1_RGMII_INT |
932 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
933 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 934 tw32(MAC_PHYCFG1, val);
935
936 return;
937 }
938
939 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
940 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
941 MAC_PHYCFG2_FMODE_MASK_MASK |
942 MAC_PHYCFG2_GMODE_MASK_MASK |
943 MAC_PHYCFG2_ACT_MASK_MASK |
944 MAC_PHYCFG2_QUAL_MASK_MASK |
945 MAC_PHYCFG2_INBAND_ENABLE;
946
947 tw32(MAC_PHYCFG2, val);
a9daf367 948
bb85fbb6
MC		 949 val = tr32(MAC_PHYCFG1);
950 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
951 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
952 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 953 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
954 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
956 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
957 }
bb85fbb6
MC		 958 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
959 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
960 tw32(MAC_PHYCFG1, val);
a9daf367 961
a9daf367
MC		 962 val = tr32(MAC_EXT_RGMII_MODE);
963 val &= ~(MAC_RGMII_MODE_RX_INT_B |
964 MAC_RGMII_MODE_RX_QUALITY |
965 MAC_RGMII_MODE_RX_ACTIVITY |
966 MAC_RGMII_MODE_RX_ENG_DET |
967 MAC_RGMII_MODE_TX_ENABLE |
968 MAC_RGMII_MODE_TX_LOWPWR |
969 MAC_RGMII_MODE_TX_RESET);
fcb389df 970 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 971 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
972 val |= MAC_RGMII_MODE_RX_INT_B |
973 MAC_RGMII_MODE_RX_QUALITY |
974 MAC_RGMII_MODE_RX_ACTIVITY |
975 MAC_RGMII_MODE_RX_ENG_DET;
976 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
977 val |= MAC_RGMII_MODE_TX_ENABLE |
978 MAC_RGMII_MODE_TX_LOWPWR |
979 MAC_RGMII_MODE_TX_RESET;
980 }
981 tw32(MAC_EXT_RGMII_MODE, val);
982}
983
158d7abd
MC		 984static void tg3_mdio_start(struct tg3 *tp)
985{
986 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 987 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 988 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 989 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 990 }
991
992 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
993 tw32_f(MAC_MI_MODE, tp->mi_mode);
994 udelay(80);
a9daf367 995
9c61d6bc
MC		 996 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
998 tg3_mdio_config_5785(tp);
158d7abd
MC		 999}
1000
1001static void tg3_mdio_stop(struct tg3 *tp)
1002{
1003 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
298cf9be 1004 mutex_lock(&tp->mdio_bus->mdio_lock);
158d7abd 1005 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
298cf9be 1006 mutex_unlock(&tp->mdio_bus->mdio_lock);
158d7abd
MC		 1007 }
1008}
1009
1010static int tg3_mdio_init(struct tg3 *tp)
1011{
1012 int i;
1013 u32 reg;
a9daf367 1014 struct phy_device *phydev;
158d7abd
MC		 1015
1016 tg3_mdio_start(tp);
1017
1018 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1019 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1020 return 0;
1021
298cf9be
LB		 1022 tp->mdio_bus = mdiobus_alloc();
1023 if (tp->mdio_bus == NULL)
1024 return -ENOMEM;
158d7abd 1025
298cf9be
LB		 1026 tp->mdio_bus->name = "tg3 mdio bus";
1027 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1028 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1029 tp->mdio_bus->priv = tp;
1030 tp->mdio_bus->parent = &tp->pdev->dev;
1031 tp->mdio_bus->read = &tg3_mdio_read;
1032 tp->mdio_bus->write = &tg3_mdio_write;
1033 tp->mdio_bus->reset = &tg3_mdio_reset;
1034 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1035 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1036
1037 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1038 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1039
1040 /* The bus registration will look for all the PHYs on the mdio bus.
1041 * Unfortunately, it does not ensure the PHY is powered up before
1042 * accessing the PHY ID registers. A chip reset is the
1043 * quickest way to bring the device back to an operational state..
1044 */
1045 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1046 tg3_bmcr_reset(tp);
1047
298cf9be 1048 i = mdiobus_register(tp->mdio_bus);
a9daf367 1049 if (i) {
158d7abd
MC		 1050 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1051 tp->dev->name, i);
9c61d6bc 1052 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1053 return i;
1054 }
158d7abd 1055
298cf9be 1056 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
a9daf367 1057
9c61d6bc
MC		 1058 if (!phydev || !phydev->drv) {
1059 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1060 mdiobus_unregister(tp->mdio_bus);
1061 mdiobus_free(tp->mdio_bus);
1062 return -ENODEV;
1063 }
1064
1065 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1066 case TG3_PHY_ID_BCM57780:
1067 phydev->interface = PHY_INTERFACE_MODE_GMII;
1068 break;
a9daf367 1069 case TG3_PHY_ID_BCM50610:
a9daf367
MC		 1070 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1071 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1072 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1073 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1074 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1075 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1076 /* fallthru */
1077 case TG3_PHY_ID_RTL8211C:
1078 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1079 break;
fcb389df 1080 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1081 case TG3_PHY_ID_BCMAC131:
1082 phydev->interface = PHY_INTERFACE_MODE_MII;
7f97a4bd 1083 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1084 break;
1085 }
1086
9c61d6bc
MC		 1087 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1088
1089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1090 tg3_mdio_config_5785(tp);
a9daf367
MC		 1091
1092 return 0;
158d7abd
MC		 1093}
1094
1095static void tg3_mdio_fini(struct tg3 *tp)
1096{
1097 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1098 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1099 mdiobus_unregister(tp->mdio_bus);
1100 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1101 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1102 }
1103}
1104
4ba526ce
MC		 1105/* tp->lock is held. */
1106static inline void tg3_generate_fw_event(struct tg3 *tp)
1107{
1108 u32 val;
1109
1110 val = tr32(GRC_RX_CPU_EVENT);
1111 val |= GRC_RX_CPU_DRIVER_EVENT;
1112 tw32_f(GRC_RX_CPU_EVENT, val);
1113
1114 tp->last_event_jiffies = jiffies;
1115}
1116
1117#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1118
95e2869a
MC		 1119/* tp->lock is held. */
1120static void tg3_wait_for_event_ack(struct tg3 *tp)
1121{
1122 int i;
4ba526ce
MC		 1123 unsigned int delay_cnt;
1124 long time_remain;
1125
1126 /* If enough time has passed, no wait is necessary. */
1127 time_remain = (long)(tp->last_event_jiffies + 1 +
1128 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1129 (long)jiffies;
1130 if (time_remain < 0)
1131 return;
1132
1133 /* Check if we can shorten the wait time. */
1134 delay_cnt = jiffies_to_usecs(time_remain);
1135 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1136 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1137 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1138
4ba526ce 1139 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1140 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1141 break;
4ba526ce 1142 udelay(8);
95e2869a
MC		 1143 }
1144}
1145
1146/* tp->lock is held. */
1147static void tg3_ump_link_report(struct tg3 *tp)
1148{
1149 u32 reg;
1150 u32 val;
1151
1152 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1153 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1154 return;
1155
1156 tg3_wait_for_event_ack(tp);
1157
1158 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1159
1160 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1161
1162 val = 0;
1163 if (!tg3_readphy(tp, MII_BMCR, &reg))
1164 val = reg << 16;
1165 if (!tg3_readphy(tp, MII_BMSR, &reg))
1166 val |= (reg & 0xffff);
1167 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1168
1169 val = 0;
1170 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1171 val = reg << 16;
1172 if (!tg3_readphy(tp, MII_LPA, &reg))
1173 val |= (reg & 0xffff);
1174 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1175
1176 val = 0;
1177 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1178 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1179 val = reg << 16;
1180 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1181 val |= (reg & 0xffff);
1182 }
1183 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1184
1185 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1186 val = reg << 16;
1187 else
1188 val = 0;
1189 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1190
4ba526ce 1191 tg3_generate_fw_event(tp);
95e2869a
MC		 1192}
1193
1194static void tg3_link_report(struct tg3 *tp)
1195{
1196 if (!netif_carrier_ok(tp->dev)) {
1197 if (netif_msg_link(tp))
1198 printk(KERN_INFO PFX "%s: Link is down.\n",
1199 tp->dev->name);
1200 tg3_ump_link_report(tp);
1201 } else if (netif_msg_link(tp)) {
1202 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1203 tp->dev->name,
1204 (tp->link_config.active_speed == SPEED_1000 ?
1205 1000 :
1206 (tp->link_config.active_speed == SPEED_100 ?
1207 100 : 10)),
1208 (tp->link_config.active_duplex == DUPLEX_FULL ?
1209 "full" : "half"));
1210
1211 printk(KERN_INFO PFX
1212 "%s: Flow control is %s for TX and %s for RX.\n",
1213 tp->dev->name,
e18ce346 1214 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1215 "on" : "off",
e18ce346 1216 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1217 "on" : "off");
1218 tg3_ump_link_report(tp);
1219 }
1220}
1221
1222static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1223{
1224 u16 miireg;
1225
e18ce346 1226 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1227 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1228 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1229 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1230 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1231 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1232 else
1233 miireg = 0;
1234
1235 return miireg;
1236}
1237
1238static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1239{
1240 u16 miireg;
1241
e18ce346 1242 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1243 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1244 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1245 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1246 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1247 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1248 else
1249 miireg = 0;
1250
1251 return miireg;
1252}
1253
95e2869a
MC		 1254static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1255{
1256 u8 cap = 0;
1257
1258 if (lcladv & ADVERTISE_1000XPAUSE) {
1259 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1260 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1261 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1262 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1263 cap = FLOW_CTRL_RX;
95e2869a
MC		 1264 } else {
1265 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1266 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1267 }
1268 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1269 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1270 cap = FLOW_CTRL_TX;
95e2869a
MC		 1271 }
1272
1273 return cap;
1274}
1275
f51f3562 1276static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1277{
b02fd9e3 1278 u8 autoneg;
f51f3562 1279 u8 flowctrl = 0;
95e2869a
MC		 1280 u32 old_rx_mode = tp->rx_mode;
1281 u32 old_tx_mode = tp->tx_mode;
1282
b02fd9e3 1283 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
298cf9be 1284 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
b02fd9e3
MC		 1285 else
1286 autoneg = tp->link_config.autoneg;
1287
1288 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1289 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1290 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1291 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1292 else
bc02ff95 1293 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1294 } else
1295 flowctrl = tp->link_config.flowctrl;
95e2869a 1296
f51f3562 1297 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1298
e18ce346 1299 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1300 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1301 else
1302 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1303
f51f3562 1304 if (old_rx_mode != tp->rx_mode)
95e2869a 1305 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1306
e18ce346 1307 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1308 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1309 else
1310 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1311
f51f3562 1312 if (old_tx_mode != tp->tx_mode)
95e2869a 1313 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1314}
1315
b02fd9e3
MC		 1316static void tg3_adjust_link(struct net_device *dev)
1317{
1318 u8 oldflowctrl, linkmesg = 0;
1319 u32 mac_mode, lcl_adv, rmt_adv;
1320 struct tg3 *tp = netdev_priv(dev);
298cf9be 1321 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1322
1323 spin_lock(&tp->lock);
1324
1325 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1326 MAC_MODE_HALF_DUPLEX);
1327
1328 oldflowctrl = tp->link_config.active_flowctrl;
1329
1330 if (phydev->link) {
1331 lcl_adv = 0;
1332 rmt_adv = 0;
1333
1334 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1335 mac_mode |= MAC_MODE_PORT_MODE_MII;
1336 else
1337 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1338
1339 if (phydev->duplex == DUPLEX_HALF)
1340 mac_mode |= MAC_MODE_HALF_DUPLEX;
1341 else {
1342 lcl_adv = tg3_advert_flowctrl_1000T(
1343 tp->link_config.flowctrl);
1344
1345 if (phydev->pause)
1346 rmt_adv = LPA_PAUSE_CAP;
1347 if (phydev->asym_pause)
1348 rmt_adv |= LPA_PAUSE_ASYM;
1349 }
1350
1351 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1352 } else
1353 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1354
1355 if (mac_mode != tp->mac_mode) {
1356 tp->mac_mode = mac_mode;
1357 tw32_f(MAC_MODE, tp->mac_mode);
1358 udelay(40);
1359 }
1360
fcb389df
MC		 1361 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1362 if (phydev->speed == SPEED_10)
1363 tw32(MAC_MI_STAT,
1364 MAC_MI_STAT_10MBPS_MODE |
1365 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1366 else
1367 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1368 }
1369
b02fd9e3
MC		 1370 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1371 tw32(MAC_TX_LENGTHS,
1372 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1373 (6 << TX_LENGTHS_IPG_SHIFT) |
1374 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1375 else
1376 tw32(MAC_TX_LENGTHS,
1377 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1378 (6 << TX_LENGTHS_IPG_SHIFT) |
1379 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1380
1381 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1382 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1383 phydev->speed != tp->link_config.active_speed ||
1384 phydev->duplex != tp->link_config.active_duplex ||
1385 oldflowctrl != tp->link_config.active_flowctrl)
1386 linkmesg = 1;
1387
1388 tp->link_config.active_speed = phydev->speed;
1389 tp->link_config.active_duplex = phydev->duplex;
1390
1391 spin_unlock(&tp->lock);
1392
1393 if (linkmesg)
1394 tg3_link_report(tp);
1395}
1396
1397static int tg3_phy_init(struct tg3 *tp)
1398{
1399 struct phy_device *phydev;
1400
1401 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1402 return 0;
1403
1404 /* Bring the PHY back to a known state. */
1405 tg3_bmcr_reset(tp);
1406
298cf9be 1407 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1408
1409 /* Attach the MAC to the PHY. */
fb28ad35 1410 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1411 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1412 if (IS_ERR(phydev)) {
1413 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1414 return PTR_ERR(phydev);
1415 }
1416
b02fd9e3 1417 /* Mask with MAC supported features. */
9c61d6bc
MC		 1418 switch (phydev->interface) {
1419 case PHY_INTERFACE_MODE_GMII:
1420 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1421 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1422 phydev->supported &= (PHY_GBIT_FEATURES |
1423 SUPPORTED_Pause |
1424 SUPPORTED_Asym_Pause);
1425 break;
1426 }
1427 /* fallthru */
9c61d6bc
MC		 1428 case PHY_INTERFACE_MODE_MII:
1429 phydev->supported &= (PHY_BASIC_FEATURES |
1430 SUPPORTED_Pause |
1431 SUPPORTED_Asym_Pause);
1432 break;
1433 default:
1434 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1435 return -EINVAL;
1436 }
1437
1438 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1439
1440 phydev->advertising = phydev->supported;
1441
b02fd9e3
MC		 1442 return 0;
1443}
1444
1445static void tg3_phy_start(struct tg3 *tp)
1446{
1447 struct phy_device *phydev;
1448
1449 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1450 return;
1451
298cf9be 1452 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 1453
1454 if (tp->link_config.phy_is_low_power) {
1455 tp->link_config.phy_is_low_power = 0;
1456 phydev->speed = tp->link_config.orig_speed;
1457 phydev->duplex = tp->link_config.orig_duplex;
1458 phydev->autoneg = tp->link_config.orig_autoneg;
1459 phydev->advertising = tp->link_config.orig_advertising;
1460 }
1461
1462 phy_start(phydev);
1463
1464 phy_start_aneg(phydev);
1465}
1466
1467static void tg3_phy_stop(struct tg3 *tp)
1468{
1469 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1470 return;
1471
298cf9be 1472 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1473}
1474
1475static void tg3_phy_fini(struct tg3 *tp)
1476{
1477 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
298cf9be 1478 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 1479 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1480 }
1481}
1482
b2a5c19c
MC		 1483static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1484{
1485 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1486 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1487}
1488
7f97a4bd
MC		 1489static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1490{
1491 u32 phytest;
1492
1493 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1494 u32 phy;
1495
1496 tg3_writephy(tp, MII_TG3_FET_TEST,
1497 phytest | MII_TG3_FET_SHADOW_EN);
1498 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1499 if (enable)
1500 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1501 else
1502 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1503 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1504 }
1505 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1506 }
1507}
1508
6833c043
MC		 1509static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1510{
1511 u32 reg;
1512
7f97a4bd 1513 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1514 return;
1515
7f97a4bd
MC		 1516 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1517 tg3_phy_fet_toggle_apd(tp, enable);
1518 return;
1519 }
1520
6833c043
MC		 1521 reg = MII_TG3_MISC_SHDW_WREN |
1522 MII_TG3_MISC_SHDW_SCR5_SEL |
1523 MII_TG3_MISC_SHDW_SCR5_LPED |
1524 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1525 MII_TG3_MISC_SHDW_SCR5_SDTL |
1526 MII_TG3_MISC_SHDW_SCR5_C125OE;
1527 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1528 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1529
1530 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1531
1532
1533 reg = MII_TG3_MISC_SHDW_WREN |
1534 MII_TG3_MISC_SHDW_APD_SEL |
1535 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1536 if (enable)
1537 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1538
1539 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1540}
1541
9ef8ca99
MC		 1542static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1543{
1544 u32 phy;
1545
1546 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1547 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1548 return;
1549
7f97a4bd 1550 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1551 u32 ephy;
1552
535ef6e1
MC		 1553 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1554 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1555
1556 tg3_writephy(tp, MII_TG3_FET_TEST,
1557 ephy | MII_TG3_FET_SHADOW_EN);
1558 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1559 if (enable)
535ef6e1 1560 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1561 else
535ef6e1
MC		 1562 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1563 tg3_writephy(tp, reg, phy);
9ef8ca99 1564 }
535ef6e1 1565 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1566 }
1567 } else {
1568 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1569 MII_TG3_AUXCTL_SHDWSEL_MISC;
1570 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1571 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1572 if (enable)
1573 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1574 else
1575 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1576 phy |= MII_TG3_AUXCTL_MISC_WREN;
1577 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1578 }
1579 }
1580}
1581
1da177e4
LT		 1582static void tg3_phy_set_wirespeed(struct tg3 *tp)
1583{
1584 u32 val;
1585
1586 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1587 return;
1588
1589 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1590 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1591 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1592 (val | (1 << 15) | (1 << 4)));
1593}
1594
b2a5c19c
MC		 1595static void tg3_phy_apply_otp(struct tg3 *tp)
1596{
1597 u32 otp, phy;
1598
1599 if (!tp->phy_otp)
1600 return;
1601
1602 otp = tp->phy_otp;
1603
1604 /* Enable SM_DSP clock and tx 6dB coding. */
1605 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1606 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1607 MII_TG3_AUXCTL_ACTL_TX_6DB;
1608 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1609
1610 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1611 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1612 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1613
1614 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1615 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1616 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1617
1618 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1619 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1620 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1621
1622 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1623 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1624
1625 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1626 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1627
1628 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1629 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1630 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1631
1632 /* Turn off SM_DSP clock. */
1633 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1634 MII_TG3_AUXCTL_ACTL_TX_6DB;
1635 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1636}
1637
1da177e4
LT		 1638static int tg3_wait_macro_done(struct tg3 *tp)
1639{
1640 int limit = 100;
1641
1642 while (limit--) {
1643 u32 tmp32;
1644
1645 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1646 if ((tmp32 & 0x1000) == 0)
1647 break;
1648 }
1649 }
d4675b52 1650 if (limit < 0)
1da177e4
LT		 1651 return -EBUSY;
1652
1653 return 0;
1654}
1655
1656static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1657{
1658 static const u32 test_pat[4][6] = {
1659 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1660 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1661 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1662 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1663 };
1664 int chan;
1665
1666 for (chan = 0; chan < 4; chan++) {
1667 int i;
1668
1669 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1670 (chan * 0x2000) | 0x0200);
1671 tg3_writephy(tp, 0x16, 0x0002);
1672
1673 for (i = 0; i < 6; i++)
1674 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1675 test_pat[chan][i]);
1676
1677 tg3_writephy(tp, 0x16, 0x0202);
1678 if (tg3_wait_macro_done(tp)) {
1679 *resetp = 1;
1680 return -EBUSY;
1681 }
1682
1683 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1684 (chan * 0x2000) | 0x0200);
1685 tg3_writephy(tp, 0x16, 0x0082);
1686 if (tg3_wait_macro_done(tp)) {
1687 *resetp = 1;
1688 return -EBUSY;
1689 }
1690
1691 tg3_writephy(tp, 0x16, 0x0802);
1692 if (tg3_wait_macro_done(tp)) {
1693 *resetp = 1;
1694 return -EBUSY;
1695 }
1696
1697 for (i = 0; i < 6; i += 2) {
1698 u32 low, high;
1699
1700 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1701 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1702 tg3_wait_macro_done(tp)) {
1703 *resetp = 1;
1704 return -EBUSY;
1705 }
1706 low &= 0x7fff;
1707 high &= 0x000f;
1708 if (low != test_pat[chan][i] ||
1709 high != test_pat[chan][i+1]) {
1710 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1711 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1712 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1713
1714 return -EBUSY;
1715 }
1716 }
1717 }
1718
1719 return 0;
1720}
1721
1722static int tg3_phy_reset_chanpat(struct tg3 *tp)
1723{
1724 int chan;
1725
1726 for (chan = 0; chan < 4; chan++) {
1727 int i;
1728
1729 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1730 (chan * 0x2000) | 0x0200);
1731 tg3_writephy(tp, 0x16, 0x0002);
1732 for (i = 0; i < 6; i++)
1733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1734 tg3_writephy(tp, 0x16, 0x0202);
1735 if (tg3_wait_macro_done(tp))
1736 return -EBUSY;
1737 }
1738
1739 return 0;
1740}
1741
1742static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1743{
1744 u32 reg32, phy9_orig;
1745 int retries, do_phy_reset, err;
1746
1747 retries = 10;
1748 do_phy_reset = 1;
1749 do {
1750 if (do_phy_reset) {
1751 err = tg3_bmcr_reset(tp);
1752 if (err)
1753 return err;
1754 do_phy_reset = 0;
1755 }
1756
1757 /* Disable transmitter and interrupt. */
1758 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1759 continue;
1760
1761 reg32 |= 0x3000;
1762 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1763
1764 /* Set full-duplex, 1000 mbps. */
1765 tg3_writephy(tp, MII_BMCR,
1766 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1767
1768 /* Set to master mode. */
1769 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1770 continue;
1771
1772 tg3_writephy(tp, MII_TG3_CTRL,
1773 (MII_TG3_CTRL_AS_MASTER |
1774 MII_TG3_CTRL_ENABLE_AS_MASTER));
1775
1776 /* Enable SM_DSP_CLOCK and 6dB. */
1777 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1778
1779 /* Block the PHY control access. */
1780 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1781 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1782
1783 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1784 if (!err)
1785 break;
1786 } while (--retries);
1787
1788 err = tg3_phy_reset_chanpat(tp);
1789 if (err)
1790 return err;
1791
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1793 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1794
1795 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1796 tg3_writephy(tp, 0x16, 0x0000);
1797
1798 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1800 /* Set Extended packet length bit for jumbo frames */
1801 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1802 }
1803 else {
1804 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1805 }
1806
1807 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1808
1809 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1810 reg32 &= ~0x3000;
1811 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1812 } else if (!err)
1813 err = -EBUSY;
1814
1815 return err;
1816}
1817
1818/* This will reset the tigon3 PHY if there is no valid
1819 * link unless the FORCE argument is non-zero.
1820 */
1821static int tg3_phy_reset(struct tg3 *tp)
1822{
b2a5c19c 1823 u32 cpmuctrl;
1da177e4
LT		 1824 u32 phy_status;
1825 int err;
1826
60189ddf
MC		 1827 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1828 u32 val;
1829
1830 val = tr32(GRC_MISC_CFG);
1831 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1832 udelay(40);
1833 }
1da177e4
LT		 1834 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1835 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1836 if (err != 0)
1837 return -EBUSY;
1838
c8e1e82b
MC		 1839 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1840 netif_carrier_off(tp->dev);
1841 tg3_link_report(tp);
1842 }
1843
1da177e4
LT		 1844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1847 err = tg3_phy_reset_5703_4_5(tp);
1848 if (err)
1849 return err;
1850 goto out;
1851 }
1852
b2a5c19c
MC		 1853 cpmuctrl = 0;
1854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1855 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1856 cpmuctrl = tr32(TG3_CPMU_CTRL);
1857 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1858 tw32(TG3_CPMU_CTRL,
1859 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1860 }
1861
1da177e4
LT		 1862 err = tg3_bmcr_reset(tp);
1863 if (err)
1864 return err;
1865
b2a5c19c
MC		 1866 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1867 u32 phy;
1868
1869 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1870 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1871
1872 tw32(TG3_CPMU_CTRL, cpmuctrl);
1873 }
1874
bcb37f6c
MC		 1875 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1876 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1877 u32 val;
1878
1879 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1880 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1881 CPMU_LSPD_1000MB_MACCLK_12_5) {
1882 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1883 udelay(40);
1884 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1885 }
1886 }
1887
b2a5c19c
MC		 1888 tg3_phy_apply_otp(tp);
1889
6833c043
MC		 1890 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1891 tg3_phy_toggle_apd(tp, true);
1892 else
1893 tg3_phy_toggle_apd(tp, false);
1894
1da177e4
LT		 1895out:
1896 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1898 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1899 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1900 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1901 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1902 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1903 }
1904 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1905 tg3_writephy(tp, 0x1c, 0x8d68);
1906 tg3_writephy(tp, 0x1c, 0x8d68);
1907 }
1908 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1909 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1912 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1913 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1914 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1915 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1916 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1917 }
c424cb24
MC		 1918 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1919 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1920 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1921 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1922 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1923 tg3_writephy(tp, MII_TG3_TEST1,
1924 MII_TG3_TEST1_TRIM_EN | 0x4);
1925 } else
1926 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1927 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1928 }
1da177e4
LT		 1929 /* Set Extended packet length bit (bit 14) on all chips that */
1930 /* support jumbo frames */
1931 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1932 /* Cannot do read-modify-write on 5401 */
1933 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1934 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1935 u32 phy_reg;
1936
1937 /* Set bit 14 with read-modify-write to preserve other bits */
1938 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1939 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1940 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1941 }
1942
1943 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1944 * jumbo frames transmission.
1945 */
8f666b07 1946 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1947 u32 phy_reg;
1948
1949 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1950 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1951 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1952 }
1953
715116a1 1954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1955 /* adjust output voltage */
535ef6e1 1956 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1957 }
1958
9ef8ca99 1959 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 1960 tg3_phy_set_wirespeed(tp);
1961 return 0;
1962}
1963
1964static void tg3_frob_aux_power(struct tg3 *tp)
1965{
1966 struct tg3 *tp_peer = tp;
1967
9d26e213 1968 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 1969 return;
1970
8c2dc7e1
MC		 1971 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1972 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1973 struct net_device *dev_peer;
1974
1975 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 1976 /* remove_one() may have been run on the peer. */
8c2dc7e1 1977 if (!dev_peer)
bc1c7567
MC		 1978 tp_peer = tp;
1979 else
1980 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 1981 }
1982
1da177e4 1983 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 1984 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1985 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1986 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 1987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 1989 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1990 (GRC_LCLCTRL_GPIO_OE0 |
1991 GRC_LCLCTRL_GPIO_OE1 |
1992 GRC_LCLCTRL_GPIO_OE2 |
1993 GRC_LCLCTRL_GPIO_OUTPUT0 |
1994 GRC_LCLCTRL_GPIO_OUTPUT1),
1995 100);
8d519ab2
MC		 1996 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1997 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 1998 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1999 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2000 GRC_LCLCTRL_GPIO_OE1 |
2001 GRC_LCLCTRL_GPIO_OE2 |
2002 GRC_LCLCTRL_GPIO_OUTPUT0 |
2003 GRC_LCLCTRL_GPIO_OUTPUT1 |
2004 tp->grc_local_ctrl;
2005 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2006
2007 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2008 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2009
2010 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2011 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2012 } else {
2013 u32 no_gpio2;
dc56b7d4 2014 u32 grc_local_ctrl = 0;
1da177e4
LT		 2015
2016 if (tp_peer != tp &&
2017 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2018 return;
2019
dc56b7d4
MC		 2020 /* Workaround to prevent overdrawing Amps. */
2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2022 ASIC_REV_5714) {
2023 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2024 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2025 grc_local_ctrl, 100);
dc56b7d4
MC		 2026 }
2027
1da177e4
LT		 2028 /* On 5753 and variants, GPIO2 cannot be used. */
2029 no_gpio2 = tp->nic_sram_data_cfg &
2030 NIC_SRAM_DATA_CFG_NO_GPIO2;
2031
dc56b7d4 2032 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2033 GRC_LCLCTRL_GPIO_OE1 |
2034 GRC_LCLCTRL_GPIO_OE2 |
2035 GRC_LCLCTRL_GPIO_OUTPUT1 |
2036 GRC_LCLCTRL_GPIO_OUTPUT2;
2037 if (no_gpio2) {
2038 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2039 GRC_LCLCTRL_GPIO_OUTPUT2);
2040 }
b401e9e2
MC		 2041 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2042 grc_local_ctrl, 100);
1da177e4
LT		 2043
2044 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2045
b401e9e2
MC		 2046 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2047 grc_local_ctrl, 100);
1da177e4
LT		 2048
2049 if (!no_gpio2) {
2050 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2051 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2052 grc_local_ctrl, 100);
1da177e4
LT		 2053 }
2054 }
2055 } else {
2056 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2057 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2058 if (tp_peer != tp &&
2059 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060 return;
2061
b401e9e2
MC		 2062 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2063 (GRC_LCLCTRL_GPIO_OE1 |
2064 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2065
b401e9e2
MC		 2066 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2068
b401e9e2
MC		 2069 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2070 (GRC_LCLCTRL_GPIO_OE1 |
2071 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2072 }
2073 }
2074}
2075
e8f3f6ca
MC		 2076static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2077{
2078 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2079 return 1;
2080 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2081 if (speed != SPEED_10)
2082 return 1;
2083 } else if (speed == SPEED_10)
2084 return 1;
2085
2086 return 0;
2087}
2088
1da177e4
LT		 2089static int tg3_setup_phy(struct tg3 *, int);
2090
2091#define RESET_KIND_SHUTDOWN 0
2092#define RESET_KIND_INIT 1
2093#define RESET_KIND_SUSPEND 2
2094
2095static void tg3_write_sig_post_reset(struct tg3 *, int);
2096static int tg3_halt_cpu(struct tg3 *, u32);
2097
0a459aac 2098static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2099{
ce057f01
MC		 2100 u32 val;
2101
5129724a
MC		 2102 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2104 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2105 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2106
2107 sg_dig_ctrl |=
2108 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2109 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2110 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2111 }
3f7045c1 2112 return;
5129724a 2113 }
3f7045c1 2114
60189ddf 2115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2116 tg3_bmcr_reset(tp);
2117 val = tr32(GRC_MISC_CFG);
2118 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2119 udelay(40);
2120 return;
0a459aac 2121 } else if (do_low_power) {
715116a1
MC		 2122 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2123 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2124
2125 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2126 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2127 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2128 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2129 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2130 }
3f7045c1 2131
15c3b696
MC		 2132 /* The PHY should not be powered down on some chips because
2133 * of bugs.
2134 */
2135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2137 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2138 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2139 return;
ce057f01 2140
bcb37f6c
MC		 2141 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2142 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2143 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2144 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2145 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2146 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2147 }
2148
15c3b696
MC		 2149 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2150}
2151
ffbcfed4
MC		 2152/* tp->lock is held. */
2153static int tg3_nvram_lock(struct tg3 *tp)
2154{
2155 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2156 int i;
2157
2158 if (tp->nvram_lock_cnt == 0) {
2159 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2160 for (i = 0; i < 8000; i++) {
2161 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2162 break;
2163 udelay(20);
2164 }
2165 if (i == 8000) {
2166 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2167 return -ENODEV;
2168 }
2169 }
2170 tp->nvram_lock_cnt++;
2171 }
2172 return 0;
2173}
2174
2175/* tp->lock is held. */
2176static void tg3_nvram_unlock(struct tg3 *tp)
2177{
2178 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2179 if (tp->nvram_lock_cnt > 0)
2180 tp->nvram_lock_cnt--;
2181 if (tp->nvram_lock_cnt == 0)
2182 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2183 }
2184}
2185
2186/* tp->lock is held. */
2187static void tg3_enable_nvram_access(struct tg3 *tp)
2188{
2189 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2190 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2191 u32 nvaccess = tr32(NVRAM_ACCESS);
2192
2193 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2194 }
2195}
2196
2197/* tp->lock is held. */
2198static void tg3_disable_nvram_access(struct tg3 *tp)
2199{
2200 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2201 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2202 u32 nvaccess = tr32(NVRAM_ACCESS);
2203
2204 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2205 }
2206}
2207
2208static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2209 u32 offset, u32 *val)
2210{
2211 u32 tmp;
2212 int i;
2213
2214 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2215 return -EINVAL;
2216
2217 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2218 EEPROM_ADDR_DEVID_MASK |
2219 EEPROM_ADDR_READ);
2220 tw32(GRC_EEPROM_ADDR,
2221 tmp |
2222 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2223 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2224 EEPROM_ADDR_ADDR_MASK) |
2225 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2226
2227 for (i = 0; i < 1000; i++) {
2228 tmp = tr32(GRC_EEPROM_ADDR);
2229
2230 if (tmp & EEPROM_ADDR_COMPLETE)
2231 break;
2232 msleep(1);
2233 }
2234 if (!(tmp & EEPROM_ADDR_COMPLETE))
2235 return -EBUSY;
2236
62cedd11
MC		 2237 tmp = tr32(GRC_EEPROM_DATA);
2238
2239 /*
2240 * The data will always be opposite the native endian
2241 * format. Perform a blind byteswap to compensate.
2242 */
2243 *val = swab32(tmp);
2244
ffbcfed4
MC		 2245 return 0;
2246}
2247
2248#define NVRAM_CMD_TIMEOUT 10000
2249
2250static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2251{
2252 int i;
2253
2254 tw32(NVRAM_CMD, nvram_cmd);
2255 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2256 udelay(10);
2257 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2258 udelay(10);
2259 break;
2260 }
2261 }
2262
2263 if (i == NVRAM_CMD_TIMEOUT)
2264 return -EBUSY;
2265
2266 return 0;
2267}
2268
2269static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2270{
2271 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2272 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2273 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2274 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2275 (tp->nvram_jedecnum == JEDEC_ATMEL))
2276
2277 addr = ((addr / tp->nvram_pagesize) <<
2278 ATMEL_AT45DB0X1B_PAGE_POS) +
2279 (addr % tp->nvram_pagesize);
2280
2281 return addr;
2282}
2283
2284static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2285{
2286 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2287 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2288 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2289 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2290 (tp->nvram_jedecnum == JEDEC_ATMEL))
2291
2292 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2293 tp->nvram_pagesize) +
2294 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2295
2296 return addr;
2297}
2298
e4f34110
MC		 2299/* NOTE: Data read in from NVRAM is byteswapped according to
2300 * the byteswapping settings for all other register accesses.
2301 * tg3 devices are BE devices, so on a BE machine, the data
2302 * returned will be exactly as it is seen in NVRAM. On a LE
2303 * machine, the 32-bit value will be byteswapped.
2304 */
ffbcfed4
MC		 2305static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2306{
2307 int ret;
2308
2309 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2310 return tg3_nvram_read_using_eeprom(tp, offset, val);
2311
2312 offset = tg3_nvram_phys_addr(tp, offset);
2313
2314 if (offset > NVRAM_ADDR_MSK)
2315 return -EINVAL;
2316
2317 ret = tg3_nvram_lock(tp);
2318 if (ret)
2319 return ret;
2320
2321 tg3_enable_nvram_access(tp);
2322
2323 tw32(NVRAM_ADDR, offset);
2324 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2325 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2326
2327 if (ret == 0)
e4f34110 2328 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2329
2330 tg3_disable_nvram_access(tp);
2331
2332 tg3_nvram_unlock(tp);
2333
2334 return ret;
2335}
2336
a9dc529d
MC		 2337/* Ensures NVRAM data is in bytestream format. */
2338static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2339{
2340 u32 v;
a9dc529d 2341 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2342 if (!res)
a9dc529d 2343 *val = cpu_to_be32(v);
ffbcfed4
MC		 2344 return res;
2345}
2346
3f007891
MC		 2347/* tp->lock is held. */
2348static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2349{
2350 u32 addr_high, addr_low;
2351 int i;
2352
2353 addr_high = ((tp->dev->dev_addr[0] << 8) |
2354 tp->dev->dev_addr[1]);
2355 addr_low = ((tp->dev->dev_addr[2] << 24) |
2356 (tp->dev->dev_addr[3] << 16) |
2357 (tp->dev->dev_addr[4] << 8) |
2358 (tp->dev->dev_addr[5] << 0));
2359 for (i = 0; i < 4; i++) {
2360 if (i == 1 && skip_mac_1)
2361 continue;
2362 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2363 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2364 }
2365
2366 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2367 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2368 for (i = 0; i < 12; i++) {
2369 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2370 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2371 }
2372 }
2373
2374 addr_high = (tp->dev->dev_addr[0] +
2375 tp->dev->dev_addr[1] +
2376 tp->dev->dev_addr[2] +
2377 tp->dev->dev_addr[3] +
2378 tp->dev->dev_addr[4] +
2379 tp->dev->dev_addr[5]) &
2380 TX_BACKOFF_SEED_MASK;
2381 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2382}
2383
bc1c7567 2384static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2385{
2386 u32 misc_host_ctrl;
0a459aac 2387 bool device_should_wake, do_low_power;
1da177e4
LT		 2388
2389 /* Make sure register accesses (indirect or otherwise)
2390 * will function correctly.
2391 */
2392 pci_write_config_dword(tp->pdev,
2393 TG3PCI_MISC_HOST_CTRL,
2394 tp->misc_host_ctrl);
2395
1da177e4 2396 switch (state) {
bc1c7567 2397 case PCI_D0:
12dac075
RW		 2398 pci_enable_wake(tp->pdev, state, false);
2399 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2400
9d26e213
MC		 2401 /* Switch out of Vaux if it is a NIC */
2402 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2403 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2404
2405 return 0;
2406
bc1c7567 2407 case PCI_D1:
bc1c7567 2408 case PCI_D2:
bc1c7567 2409 case PCI_D3hot:
1da177e4
LT		 2410 break;
2411
2412 default:
12dac075
RW		 2413 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2414 tp->dev->name, state);
1da177e4 2415 return -EINVAL;
855e1111 2416 }
5e7dfd0f
MC		 2417
2418 /* Restore the CLKREQ setting. */
2419 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2420 u16 lnkctl;
2421
2422 pci_read_config_word(tp->pdev,
2423 tp->pcie_cap + PCI_EXP_LNKCTL,
2424 &lnkctl);
2425 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2426 pci_write_config_word(tp->pdev,
2427 tp->pcie_cap + PCI_EXP_LNKCTL,
2428 lnkctl);
2429 }
2430
1da177e4
LT		 2431 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2432 tw32(TG3PCI_MISC_HOST_CTRL,
2433 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2434
05ac4cb7
MC		 2435 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2436 device_may_wakeup(&tp->pdev->dev) &&
2437 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2438
dd477003 2439 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2440 do_low_power = false;
b02fd9e3
MC		 2441 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2442 !tp->link_config.phy_is_low_power) {
2443 struct phy_device *phydev;
0a459aac 2444 u32 phyid, advertising;
b02fd9e3 2445
298cf9be 2446 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
b02fd9e3
MC		 2447
2448 tp->link_config.phy_is_low_power = 1;
2449
2450 tp->link_config.orig_speed = phydev->speed;
2451 tp->link_config.orig_duplex = phydev->duplex;
2452 tp->link_config.orig_autoneg = phydev->autoneg;
2453 tp->link_config.orig_advertising = phydev->advertising;
2454
2455 advertising = ADVERTISED_TP |
2456 ADVERTISED_Pause |
2457 ADVERTISED_Autoneg |
2458 ADVERTISED_10baseT_Half;
2459
2460 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2461 device_should_wake) {
b02fd9e3
MC		 2462 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2463 advertising |=
2464 ADVERTISED_100baseT_Half |
2465 ADVERTISED_100baseT_Full |
2466 ADVERTISED_10baseT_Full;
2467 else
2468 advertising |= ADVERTISED_10baseT_Full;
2469 }
2470
2471 phydev->advertising = advertising;
2472
2473 phy_start_aneg(phydev);
0a459aac
MC		 2474
2475 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2476 if (phyid != TG3_PHY_ID_BCMAC131) {
2477 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2478 if (phyid == TG3_PHY_OUI_1 ||
2479 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2480 phyid == TG3_PHY_OUI_3)
2481 do_low_power = true;
2482 }
b02fd9e3 2483 }
dd477003 2484 } else {
2023276e 2485 do_low_power = true;
0a459aac 2486
dd477003
MC		 2487 if (tp->link_config.phy_is_low_power == 0) {
2488 tp->link_config.phy_is_low_power = 1;
2489 tp->link_config.orig_speed = tp->link_config.speed;
2490 tp->link_config.orig_duplex = tp->link_config.duplex;
2491 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2492 }
1da177e4 2493
dd477003
MC		 2494 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2495 tp->link_config.speed = SPEED_10;
2496 tp->link_config.duplex = DUPLEX_HALF;
2497 tp->link_config.autoneg = AUTONEG_ENABLE;
2498 tg3_setup_phy(tp, 0);
2499 }
1da177e4
LT		 2500 }
2501
b5d3772c
MC		 2502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2503 u32 val;
2504
2505 val = tr32(GRC_VCPU_EXT_CTRL);
2506 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2507 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2508 int i;
2509 u32 val;
2510
2511 for (i = 0; i < 200; i++) {
2512 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2513 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2514 break;
2515 msleep(1);
2516 }
2517 }
a85feb8c
GZ		 2518 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2519 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2520 WOL_DRV_STATE_SHUTDOWN |
2521 WOL_DRV_WOL |
2522 WOL_SET_MAGIC_PKT);
6921d201 2523
05ac4cb7 2524 if (device_should_wake) {
1da177e4
LT		 2525 u32 mac_mode;
2526
2527 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2528 if (do_low_power) {
dd477003
MC		 2529 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2530 udelay(40);
2531 }
1da177e4 2532
3f7045c1
MC		 2533 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2534 mac_mode = MAC_MODE_PORT_MODE_GMII;
2535 else
2536 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2537
e8f3f6ca
MC		 2538 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2539 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2540 ASIC_REV_5700) {
2541 u32 speed = (tp->tg3_flags &
2542 TG3_FLAG_WOL_SPEED_100MB) ?
2543 SPEED_100 : SPEED_10;
2544 if (tg3_5700_link_polarity(tp, speed))
2545 mac_mode |= MAC_MODE_LINK_POLARITY;
2546 else
2547 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2548 }
1da177e4
LT		 2549 } else {
2550 mac_mode = MAC_MODE_PORT_MODE_TBI;
2551 }
2552
cbf46853 2553 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2554 tw32(MAC_LED_CTRL, tp->led_ctrl);
2555
05ac4cb7
MC		 2556 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2557 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2558 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2559 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2560 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2561 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2562
3bda1258
MC		 2563 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2564 mac_mode |= tp->mac_mode &
2565 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2566 if (mac_mode & MAC_MODE_APE_TX_EN)
2567 mac_mode |= MAC_MODE_TDE_ENABLE;
2568 }
2569
1da177e4
LT		 2570 tw32_f(MAC_MODE, mac_mode);
2571 udelay(100);
2572
2573 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2574 udelay(10);
2575 }
2576
2577 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2578 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2580 u32 base_val;
2581
2582 base_val = tp->pci_clock_ctrl;
2583 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2584 CLOCK_CTRL_TXCLK_DISABLE);
2585
b401e9e2
MC		 2586 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2587 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2588 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2589 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2590 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2591 /* do nothing */
85e94ced 2592 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2593 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2594 u32 newbits1, newbits2;
2595
2596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2597 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2598 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2599 CLOCK_CTRL_TXCLK_DISABLE |
2600 CLOCK_CTRL_ALTCLK);
2601 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2602 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2603 newbits1 = CLOCK_CTRL_625_CORE;
2604 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2605 } else {
2606 newbits1 = CLOCK_CTRL_ALTCLK;
2607 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2608 }
2609
b401e9e2
MC		 2610 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2611 40);
1da177e4 2612
b401e9e2
MC		 2613 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2614 40);
1da177e4
LT		 2615
2616 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2617 u32 newbits3;
2618
2619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2621 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2622 CLOCK_CTRL_TXCLK_DISABLE |
2623 CLOCK_CTRL_44MHZ_CORE);
2624 } else {
2625 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2626 }
2627
b401e9e2
MC		 2628 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2629 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2630 }
2631 }
2632
05ac4cb7 2633 if (!(device_should_wake) &&
22435849 2634 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2635 tg3_power_down_phy(tp, do_low_power);
6921d201 2636
1da177e4
LT		 2637 tg3_frob_aux_power(tp);
2638
2639 /* Workaround for unstable PLL clock */
2640 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2641 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2642 u32 val = tr32(0x7d00);
2643
2644 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2645 tw32(0x7d00, val);
6921d201 2646 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2647 int err;
2648
2649 err = tg3_nvram_lock(tp);
1da177e4 2650 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2651 if (!err)
2652 tg3_nvram_unlock(tp);
6921d201 2653 }
1da177e4
LT		 2654 }
2655
bbadf503
MC		 2656 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2657
05ac4cb7 2658 if (device_should_wake)
12dac075
RW		 2659 pci_enable_wake(tp->pdev, state, true);
2660
1da177e4 2661 /* Finally, set the new power state. */
12dac075 2662 pci_set_power_state(tp->pdev, state);
1da177e4 2663
1da177e4
LT		 2664 return 0;
2665}
2666
1da177e4
LT		 2667static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2668{
2669 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2670 case MII_TG3_AUX_STAT_10HALF:
2671 *speed = SPEED_10;
2672 *duplex = DUPLEX_HALF;
2673 break;
2674
2675 case MII_TG3_AUX_STAT_10FULL:
2676 *speed = SPEED_10;
2677 *duplex = DUPLEX_FULL;
2678 break;
2679
2680 case MII_TG3_AUX_STAT_100HALF:
2681 *speed = SPEED_100;
2682 *duplex = DUPLEX_HALF;
2683 break;
2684
2685 case MII_TG3_AUX_STAT_100FULL:
2686 *speed = SPEED_100;
2687 *duplex = DUPLEX_FULL;
2688 break;
2689
2690 case MII_TG3_AUX_STAT_1000HALF:
2691 *speed = SPEED_1000;
2692 *duplex = DUPLEX_HALF;
2693 break;
2694
2695 case MII_TG3_AUX_STAT_1000FULL:
2696 *speed = SPEED_1000;
2697 *duplex = DUPLEX_FULL;
2698 break;
2699
2700 default:
7f97a4bd 2701 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2702 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2703 SPEED_10;
2704 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2705 DUPLEX_HALF;
2706 break;
2707 }
1da177e4
LT		 2708 *speed = SPEED_INVALID;
2709 *duplex = DUPLEX_INVALID;
2710 break;
855e1111 2711 }
1da177e4
LT		 2712}
2713
2714static void tg3_phy_copper_begin(struct tg3 *tp)
2715{
2716 u32 new_adv;
2717 int i;
2718
2719 if (tp->link_config.phy_is_low_power) {
2720 /* Entering low power mode. Disable gigabit and
2721 * 100baseT advertisements.
2722 */
2723 tg3_writephy(tp, MII_TG3_CTRL, 0);
2724
2725 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2726 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2727 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2728 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2729
2730 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2731 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2732 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2733 tp->link_config.advertising &=
2734 ~(ADVERTISED_1000baseT_Half |
2735 ADVERTISED_1000baseT_Full);
2736
ba4d07a8 2737 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2738 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2739 new_adv |= ADVERTISE_10HALF;
2740 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2741 new_adv |= ADVERTISE_10FULL;
2742 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2743 new_adv |= ADVERTISE_100HALF;
2744 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2745 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2746
2747 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2748
1da177e4
LT		 2749 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2750
2751 if (tp->link_config.advertising &
2752 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2753 new_adv = 0;
2754 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2755 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2756 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2757 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2758 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2759 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2760 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2761 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2762 MII_TG3_CTRL_ENABLE_AS_MASTER);
2763 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2764 } else {
2765 tg3_writephy(tp, MII_TG3_CTRL, 0);
2766 }
2767 } else {
ba4d07a8
MC		 2768 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2769 new_adv |= ADVERTISE_CSMA;
2770
1da177e4
LT		 2771 /* Asking for a specific link mode. */
2772 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2773 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2774
2775 if (tp->link_config.duplex == DUPLEX_FULL)
2776 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2777 else
2778 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2779 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2780 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2781 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2782 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2783 } else {
1da177e4
LT		 2784 if (tp->link_config.speed == SPEED_100) {
2785 if (tp->link_config.duplex == DUPLEX_FULL)
2786 new_adv |= ADVERTISE_100FULL;
2787 else
2788 new_adv |= ADVERTISE_100HALF;
2789 } else {
2790 if (tp->link_config.duplex == DUPLEX_FULL)
2791 new_adv |= ADVERTISE_10FULL;
2792 else
2793 new_adv |= ADVERTISE_10HALF;
2794 }
2795 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2796
2797 new_adv = 0;
1da177e4 2798 }
ba4d07a8
MC		 2799
2800 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2801 }
2802
2803 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2804 tp->link_config.speed != SPEED_INVALID) {
2805 u32 bmcr, orig_bmcr;
2806
2807 tp->link_config.active_speed = tp->link_config.speed;
2808 tp->link_config.active_duplex = tp->link_config.duplex;
2809
2810 bmcr = 0;
2811 switch (tp->link_config.speed) {
2812 default:
2813 case SPEED_10:
2814 break;
2815
2816 case SPEED_100:
2817 bmcr |= BMCR_SPEED100;
2818 break;
2819
2820 case SPEED_1000:
2821 bmcr |= TG3_BMCR_SPEED1000;
2822 break;
855e1111 2823 }
1da177e4
LT		 2824
2825 if (tp->link_config.duplex == DUPLEX_FULL)
2826 bmcr |= BMCR_FULLDPLX;
2827
2828 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2829 (bmcr != orig_bmcr)) {
2830 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2831 for (i = 0; i < 1500; i++) {
2832 u32 tmp;
2833
2834 udelay(10);
2835 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2836 tg3_readphy(tp, MII_BMSR, &tmp))
2837 continue;
2838 if (!(tmp & BMSR_LSTATUS)) {
2839 udelay(40);
2840 break;
2841 }
2842 }
2843 tg3_writephy(tp, MII_BMCR, bmcr);
2844 udelay(40);
2845 }
2846 } else {
2847 tg3_writephy(tp, MII_BMCR,
2848 BMCR_ANENABLE | BMCR_ANRESTART);
2849 }
2850}
2851
2852static int tg3_init_5401phy_dsp(struct tg3 *tp)
2853{
2854 int err;
2855
2856 /* Turn off tap power management. */
2857 /* Set Extended packet length bit */
2858 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2859
2860 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2861 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2862
2863 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2864 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2865
2866 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2867 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2868
2869 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2870 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2871
2872 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2873 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2874
2875 udelay(40);
2876
2877 return err;
2878}
2879
3600d918 2880static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2881{
3600d918
MC		 2882 u32 adv_reg, all_mask = 0;
2883
2884 if (mask & ADVERTISED_10baseT_Half)
2885 all_mask |= ADVERTISE_10HALF;
2886 if (mask & ADVERTISED_10baseT_Full)
2887 all_mask |= ADVERTISE_10FULL;
2888 if (mask & ADVERTISED_100baseT_Half)
2889 all_mask |= ADVERTISE_100HALF;
2890 if (mask & ADVERTISED_100baseT_Full)
2891 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2892
2893 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2894 return 0;
2895
1da177e4
LT		 2896 if ((adv_reg & all_mask) != all_mask)
2897 return 0;
2898 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2899 u32 tg3_ctrl;
2900
3600d918
MC		 2901 all_mask = 0;
2902 if (mask & ADVERTISED_1000baseT_Half)
2903 all_mask |= ADVERTISE_1000HALF;
2904 if (mask & ADVERTISED_1000baseT_Full)
2905 all_mask |= ADVERTISE_1000FULL;
2906
1da177e4
LT		 2907 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2908 return 0;
2909
1da177e4
LT		 2910 if ((tg3_ctrl & all_mask) != all_mask)
2911 return 0;
2912 }
2913 return 1;
2914}
2915
ef167e27
MC		 2916static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2917{
2918 u32 curadv, reqadv;
2919
2920 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2921 return 1;
2922
2923 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2924 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2925
2926 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2927 if (curadv != reqadv)
2928 return 0;
2929
2930 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2931 tg3_readphy(tp, MII_LPA, rmtadv);
2932 } else {
2933 /* Reprogram the advertisement register, even if it
2934 * does not affect the current link. If the link
2935 * gets renegotiated in the future, we can save an
2936 * additional renegotiation cycle by advertising
2937 * it correctly in the first place.
2938 */
2939 if (curadv != reqadv) {
2940 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2941 ADVERTISE_PAUSE_ASYM);
2942 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2943 }
2944 }
2945
2946 return 1;
2947}
2948
1da177e4
LT		 2949static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2950{
2951 int current_link_up;
2952 u32 bmsr, dummy;
ef167e27 2953 u32 lcl_adv, rmt_adv;
1da177e4
LT		 2954 u16 current_speed;
2955 u8 current_duplex;
2956 int i, err;
2957
2958 tw32(MAC_EVENT, 0);
2959
2960 tw32_f(MAC_STATUS,
2961 (MAC_STATUS_SYNC_CHANGED |
2962 MAC_STATUS_CFG_CHANGED |
2963 MAC_STATUS_MI_COMPLETION |
2964 MAC_STATUS_LNKSTATE_CHANGED));
2965 udelay(40);
2966
8ef21428
MC		 2967 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2968 tw32_f(MAC_MI_MODE,
2969 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2970 udelay(80);
2971 }
1da177e4
LT		 2972
2973 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2974
2975 /* Some third-party PHYs need to be reset on link going
2976 * down.
2977 */
2978 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2981 netif_carrier_ok(tp->dev)) {
2982 tg3_readphy(tp, MII_BMSR, &bmsr);
2983 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2984 !(bmsr & BMSR_LSTATUS))
2985 force_reset = 1;
2986 }
2987 if (force_reset)
2988 tg3_phy_reset(tp);
2989
2990 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2991 tg3_readphy(tp, MII_BMSR, &bmsr);
2992 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2993 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2994 bmsr = 0;
2995
2996 if (!(bmsr & BMSR_LSTATUS)) {
2997 err = tg3_init_5401phy_dsp(tp);
2998 if (err)
2999 return err;
3000
3001 tg3_readphy(tp, MII_BMSR, &bmsr);
3002 for (i = 0; i < 1000; i++) {
3003 udelay(10);
3004 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3005 (bmsr & BMSR_LSTATUS)) {
3006 udelay(40);
3007 break;
3008 }
3009 }
3010
3011 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3012 !(bmsr & BMSR_LSTATUS) &&
3013 tp->link_config.active_speed == SPEED_1000) {
3014 err = tg3_phy_reset(tp);
3015 if (!err)
3016 err = tg3_init_5401phy_dsp(tp);
3017 if (err)
3018 return err;
3019 }
3020 }
3021 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3022 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3023 /* 5701 {A0,B0} CRC bug workaround */
3024 tg3_writephy(tp, 0x15, 0x0a75);
3025 tg3_writephy(tp, 0x1c, 0x8c68);
3026 tg3_writephy(tp, 0x1c, 0x8d68);
3027 tg3_writephy(tp, 0x1c, 0x8c68);
3028 }
3029
3030 /* Clear pending interrupts... */
3031 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3032 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3033
3034 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3035 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3036 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3037 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3038
3039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3040 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3041 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3042 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3043 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3044 else
3045 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3046 }
3047
3048 current_link_up = 0;
3049 current_speed = SPEED_INVALID;
3050 current_duplex = DUPLEX_INVALID;
3051
3052 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3053 u32 val;
3054
3055 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3056 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3057 if (!(val & (1 << 10))) {
3058 val |= (1 << 10);
3059 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3060 goto relink;
3061 }
3062 }
3063
3064 bmsr = 0;
3065 for (i = 0; i < 100; i++) {
3066 tg3_readphy(tp, MII_BMSR, &bmsr);
3067 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3068 (bmsr & BMSR_LSTATUS))
3069 break;
3070 udelay(40);
3071 }
3072
3073 if (bmsr & BMSR_LSTATUS) {
3074 u32 aux_stat, bmcr;
3075
3076 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3077 for (i = 0; i < 2000; i++) {
3078 udelay(10);
3079 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3080 aux_stat)
3081 break;
3082 }
3083
3084 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3085 &current_speed,
3086 &current_duplex);
3087
3088 bmcr = 0;
3089 for (i = 0; i < 200; i++) {
3090 tg3_readphy(tp, MII_BMCR, &bmcr);
3091 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3092 continue;
3093 if (bmcr && bmcr != 0x7fff)
3094 break;
3095 udelay(10);
3096 }
3097
ef167e27
MC		 3098 lcl_adv = 0;
3099 rmt_adv = 0;
1da177e4 3100
ef167e27
MC		 3101 tp->link_config.active_speed = current_speed;
3102 tp->link_config.active_duplex = current_duplex;
3103
3104 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3105 if ((bmcr & BMCR_ANENABLE) &&
3106 tg3_copper_is_advertising_all(tp,
3107 tp->link_config.advertising)) {
3108 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3109 &rmt_adv))
3110 current_link_up = 1;
1da177e4
LT		 3111 }
3112 } else {
3113 if (!(bmcr & BMCR_ANENABLE) &&
3114 tp->link_config.speed == current_speed &&
ef167e27
MC		 3115 tp->link_config.duplex == current_duplex &&
3116 tp->link_config.flowctrl ==
3117 tp->link_config.active_flowctrl) {
1da177e4 3118 current_link_up = 1;
1da177e4
LT		 3119 }
3120 }
3121
ef167e27
MC		 3122 if (current_link_up == 1 &&
3123 tp->link_config.active_duplex == DUPLEX_FULL)
3124 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3125 }
3126
1da177e4 3127relink:
6921d201 3128 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3129 u32 tmp;
3130
3131 tg3_phy_copper_begin(tp);
3132
3133 tg3_readphy(tp, MII_BMSR, &tmp);
3134 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3135 (tmp & BMSR_LSTATUS))
3136 current_link_up = 1;
3137 }
3138
3139 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3140 if (current_link_up == 1) {
3141 if (tp->link_config.active_speed == SPEED_100 ||
3142 tp->link_config.active_speed == SPEED_10)
3143 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3144 else
3145 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3146 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3147 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3148 else
1da177e4
LT		 3149 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3150
3151 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3152 if (tp->link_config.active_duplex == DUPLEX_HALF)
3153 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3154
1da177e4 3155 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3156 if (current_link_up == 1 &&
3157 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3158 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3159 else
3160 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3161 }
3162
3163 /* ??? Without this setting Netgear GA302T PHY does not
3164 * ??? send/receive packets...
3165 */
3166 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3167 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3168 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3169 tw32_f(MAC_MI_MODE, tp->mi_mode);
3170 udelay(80);
3171 }
3172
3173 tw32_f(MAC_MODE, tp->mac_mode);
3174 udelay(40);
3175
3176 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3177 /* Polled via timer. */
3178 tw32_f(MAC_EVENT, 0);
3179 } else {
3180 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3181 }
3182 udelay(40);
3183
3184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3185 current_link_up == 1 &&
3186 tp->link_config.active_speed == SPEED_1000 &&
3187 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3188 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3189 udelay(120);
3190 tw32_f(MAC_STATUS,
3191 (MAC_STATUS_SYNC_CHANGED |
3192 MAC_STATUS_CFG_CHANGED));
3193 udelay(40);
3194 tg3_write_mem(tp,
3195 NIC_SRAM_FIRMWARE_MBOX,
3196 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3197 }
3198
5e7dfd0f
MC		 3199 /* Prevent send BD corruption. */
3200 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3201 u16 oldlnkctl, newlnkctl;
3202
3203 pci_read_config_word(tp->pdev,
3204 tp->pcie_cap + PCI_EXP_LNKCTL,
3205 &oldlnkctl);
3206 if (tp->link_config.active_speed == SPEED_100 ||
3207 tp->link_config.active_speed == SPEED_10)
3208 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3209 else
3210 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3211 if (newlnkctl != oldlnkctl)
3212 pci_write_config_word(tp->pdev,
3213 tp->pcie_cap + PCI_EXP_LNKCTL,
3214 newlnkctl);
255ca311
MC		 3215 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3216 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3217 if (tp->link_config.active_speed == SPEED_100 ||
3218 tp->link_config.active_speed == SPEED_10)
3219 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3220 else
3221 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3222 if (newreg != oldreg)
3223 tw32(TG3_PCIE_LNKCTL, newreg);
5e7dfd0f
MC		 3224 }
3225
1da177e4
LT		 3226 if (current_link_up != netif_carrier_ok(tp->dev)) {
3227 if (current_link_up)
3228 netif_carrier_on(tp->dev);
3229 else
3230 netif_carrier_off(tp->dev);
3231 tg3_link_report(tp);
3232 }
3233
3234 return 0;
3235}
3236
3237struct tg3_fiber_aneginfo {
3238 int state;
3239#define ANEG_STATE_UNKNOWN 0
3240#define ANEG_STATE_AN_ENABLE 1
3241#define ANEG_STATE_RESTART_INIT 2
3242#define ANEG_STATE_RESTART 3
3243#define ANEG_STATE_DISABLE_LINK_OK 4
3244#define ANEG_STATE_ABILITY_DETECT_INIT 5
3245#define ANEG_STATE_ABILITY_DETECT 6
3246#define ANEG_STATE_ACK_DETECT_INIT 7
3247#define ANEG_STATE_ACK_DETECT 8
3248#define ANEG_STATE_COMPLETE_ACK_INIT 9
3249#define ANEG_STATE_COMPLETE_ACK 10
3250#define ANEG_STATE_IDLE_DETECT_INIT 11
3251#define ANEG_STATE_IDLE_DETECT 12
3252#define ANEG_STATE_LINK_OK 13
3253#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3254#define ANEG_STATE_NEXT_PAGE_WAIT 15
3255
3256 u32 flags;
3257#define MR_AN_ENABLE 0x00000001
3258#define MR_RESTART_AN 0x00000002
3259#define MR_AN_COMPLETE 0x00000004
3260#define MR_PAGE_RX 0x00000008
3261#define MR_NP_LOADED 0x00000010
3262#define MR_TOGGLE_TX 0x00000020
3263#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3264#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3265#define MR_LP_ADV_SYM_PAUSE 0x00000100
3266#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3267#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3268#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3269#define MR_LP_ADV_NEXT_PAGE 0x00001000
3270#define MR_TOGGLE_RX 0x00002000
3271#define MR_NP_RX 0x00004000
3272
3273#define MR_LINK_OK 0x80000000
3274
3275 unsigned long link_time, cur_time;
3276
3277 u32 ability_match_cfg;
3278 int ability_match_count;
3279
3280 char ability_match, idle_match, ack_match;
3281
3282 u32 txconfig, rxconfig;
3283#define ANEG_CFG_NP 0x00000080
3284#define ANEG_CFG_ACK 0x00000040
3285#define ANEG_CFG_RF2 0x00000020
3286#define ANEG_CFG_RF1 0x00000010
3287#define ANEG_CFG_PS2 0x00000001
3288#define ANEG_CFG_PS1 0x00008000
3289#define ANEG_CFG_HD 0x00004000
3290#define ANEG_CFG_FD 0x00002000
3291#define ANEG_CFG_INVAL 0x00001f06
3292
3293};
3294#define ANEG_OK 0
3295#define ANEG_DONE 1
3296#define ANEG_TIMER_ENAB 2
3297#define ANEG_FAILED -1
3298
3299#define ANEG_STATE_SETTLE_TIME 10000
3300
3301static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3302 struct tg3_fiber_aneginfo *ap)
3303{
5be73b47 3304 u16 flowctrl;
1da177e4
LT		 3305 unsigned long delta;
3306 u32 rx_cfg_reg;
3307 int ret;
3308
3309 if (ap->state == ANEG_STATE_UNKNOWN) {
3310 ap->rxconfig = 0;
3311 ap->link_time = 0;
3312 ap->cur_time = 0;
3313 ap->ability_match_cfg = 0;
3314 ap->ability_match_count = 0;
3315 ap->ability_match = 0;
3316 ap->idle_match = 0;
3317 ap->ack_match = 0;
3318 }
3319 ap->cur_time++;
3320
3321 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3322 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3323
3324 if (rx_cfg_reg != ap->ability_match_cfg) {
3325 ap->ability_match_cfg = rx_cfg_reg;
3326 ap->ability_match = 0;
3327 ap->ability_match_count = 0;
3328 } else {
3329 if (++ap->ability_match_count > 1) {
3330 ap->ability_match = 1;
3331 ap->ability_match_cfg = rx_cfg_reg;
3332 }
3333 }
3334 if (rx_cfg_reg & ANEG_CFG_ACK)
3335 ap->ack_match = 1;
3336 else
3337 ap->ack_match = 0;
3338
3339 ap->idle_match = 0;
3340 } else {
3341 ap->idle_match = 1;
3342 ap->ability_match_cfg = 0;
3343 ap->ability_match_count = 0;
3344 ap->ability_match = 0;
3345 ap->ack_match = 0;
3346
3347 rx_cfg_reg = 0;
3348 }
3349
3350 ap->rxconfig = rx_cfg_reg;
3351 ret = ANEG_OK;
3352
3353 switch(ap->state) {
3354 case ANEG_STATE_UNKNOWN:
3355 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3356 ap->state = ANEG_STATE_AN_ENABLE;
3357
3358 /* fallthru */
3359 case ANEG_STATE_AN_ENABLE:
3360 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3361 if (ap->flags & MR_AN_ENABLE) {
3362 ap->link_time = 0;
3363 ap->cur_time = 0;
3364 ap->ability_match_cfg = 0;
3365 ap->ability_match_count = 0;
3366 ap->ability_match = 0;
3367 ap->idle_match = 0;
3368 ap->ack_match = 0;
3369
3370 ap->state = ANEG_STATE_RESTART_INIT;
3371 } else {
3372 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3373 }
3374 break;
3375
3376 case ANEG_STATE_RESTART_INIT:
3377 ap->link_time = ap->cur_time;
3378 ap->flags &= ~(MR_NP_LOADED);
3379 ap->txconfig = 0;
3380 tw32(MAC_TX_AUTO_NEG, 0);
3381 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3382 tw32_f(MAC_MODE, tp->mac_mode);
3383 udelay(40);
3384
3385 ret = ANEG_TIMER_ENAB;
3386 ap->state = ANEG_STATE_RESTART;
3387
3388 /* fallthru */
3389 case ANEG_STATE_RESTART:
3390 delta = ap->cur_time - ap->link_time;
3391 if (delta > ANEG_STATE_SETTLE_TIME) {
3392 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3393 } else {
3394 ret = ANEG_TIMER_ENAB;
3395 }
3396 break;
3397
3398 case ANEG_STATE_DISABLE_LINK_OK:
3399 ret = ANEG_DONE;
3400 break;
3401
3402 case ANEG_STATE_ABILITY_DETECT_INIT:
3403 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3404 ap->txconfig = ANEG_CFG_FD;
3405 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3406 if (flowctrl & ADVERTISE_1000XPAUSE)
3407 ap->txconfig |= ANEG_CFG_PS1;
3408 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3409 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3410 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3411 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3412 tw32_f(MAC_MODE, tp->mac_mode);
3413 udelay(40);
3414
3415 ap->state = ANEG_STATE_ABILITY_DETECT;
3416 break;
3417
3418 case ANEG_STATE_ABILITY_DETECT:
3419 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3420 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3421 }
3422 break;
3423
3424 case ANEG_STATE_ACK_DETECT_INIT:
3425 ap->txconfig |= ANEG_CFG_ACK;
3426 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3427 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3428 tw32_f(MAC_MODE, tp->mac_mode);
3429 udelay(40);
3430
3431 ap->state = ANEG_STATE_ACK_DETECT;
3432
3433 /* fallthru */
3434 case ANEG_STATE_ACK_DETECT:
3435 if (ap->ack_match != 0) {
3436 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3437 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3438 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3439 } else {
3440 ap->state = ANEG_STATE_AN_ENABLE;
3441 }
3442 } else if (ap->ability_match != 0 &&
3443 ap->rxconfig == 0) {
3444 ap->state = ANEG_STATE_AN_ENABLE;
3445 }
3446 break;
3447
3448 case ANEG_STATE_COMPLETE_ACK_INIT:
3449 if (ap->rxconfig & ANEG_CFG_INVAL) {
3450 ret = ANEG_FAILED;
3451 break;
3452 }
3453 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3454 MR_LP_ADV_HALF_DUPLEX |
3455 MR_LP_ADV_SYM_PAUSE |
3456 MR_LP_ADV_ASYM_PAUSE |
3457 MR_LP_ADV_REMOTE_FAULT1 |
3458 MR_LP_ADV_REMOTE_FAULT2 |
3459 MR_LP_ADV_NEXT_PAGE |
3460 MR_TOGGLE_RX |
3461 MR_NP_RX);
3462 if (ap->rxconfig & ANEG_CFG_FD)
3463 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3464 if (ap->rxconfig & ANEG_CFG_HD)
3465 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3466 if (ap->rxconfig & ANEG_CFG_PS1)
3467 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3468 if (ap->rxconfig & ANEG_CFG_PS2)
3469 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3470 if (ap->rxconfig & ANEG_CFG_RF1)
3471 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3472 if (ap->rxconfig & ANEG_CFG_RF2)
3473 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3474 if (ap->rxconfig & ANEG_CFG_NP)
3475 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3476
3477 ap->link_time = ap->cur_time;
3478
3479 ap->flags ^= (MR_TOGGLE_TX);
3480 if (ap->rxconfig & 0x0008)
3481 ap->flags |= MR_TOGGLE_RX;
3482 if (ap->rxconfig & ANEG_CFG_NP)
3483 ap->flags |= MR_NP_RX;
3484 ap->flags |= MR_PAGE_RX;
3485
3486 ap->state = ANEG_STATE_COMPLETE_ACK;
3487 ret = ANEG_TIMER_ENAB;
3488 break;
3489
3490 case ANEG_STATE_COMPLETE_ACK:
3491 if (ap->ability_match != 0 &&
3492 ap->rxconfig == 0) {
3493 ap->state = ANEG_STATE_AN_ENABLE;
3494 break;
3495 }
3496 delta = ap->cur_time - ap->link_time;
3497 if (delta > ANEG_STATE_SETTLE_TIME) {
3498 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3499 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3500 } else {
3501 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3502 !(ap->flags & MR_NP_RX)) {
3503 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3504 } else {
3505 ret = ANEG_FAILED;
3506 }
3507 }
3508 }
3509 break;
3510
3511 case ANEG_STATE_IDLE_DETECT_INIT:
3512 ap->link_time = ap->cur_time;
3513 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3514 tw32_f(MAC_MODE, tp->mac_mode);
3515 udelay(40);
3516
3517 ap->state = ANEG_STATE_IDLE_DETECT;
3518 ret = ANEG_TIMER_ENAB;
3519 break;
3520
3521 case ANEG_STATE_IDLE_DETECT:
3522 if (ap->ability_match != 0 &&
3523 ap->rxconfig == 0) {
3524 ap->state = ANEG_STATE_AN_ENABLE;
3525 break;
3526 }
3527 delta = ap->cur_time - ap->link_time;
3528 if (delta > ANEG_STATE_SETTLE_TIME) {
3529 /* XXX another gem from the Broadcom driver :( */
3530 ap->state = ANEG_STATE_LINK_OK;
3531 }
3532 break;
3533
3534 case ANEG_STATE_LINK_OK:
3535 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3536 ret = ANEG_DONE;
3537 break;
3538
3539 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3540 /* ??? unimplemented */
3541 break;
3542
3543 case ANEG_STATE_NEXT_PAGE_WAIT:
3544 /* ??? unimplemented */
3545 break;
3546
3547 default:
3548 ret = ANEG_FAILED;
3549 break;
855e1111 3550 }
1da177e4
LT		 3551
3552 return ret;
3553}
3554
5be73b47 3555static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3556{
3557 int res = 0;
3558 struct tg3_fiber_aneginfo aninfo;
3559 int status = ANEG_FAILED;
3560 unsigned int tick;
3561 u32 tmp;
3562
3563 tw32_f(MAC_TX_AUTO_NEG, 0);
3564
3565 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3566 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3567 udelay(40);
3568
3569 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3570 udelay(40);
3571
3572 memset(&aninfo, 0, sizeof(aninfo));
3573 aninfo.flags |= MR_AN_ENABLE;
3574 aninfo.state = ANEG_STATE_UNKNOWN;
3575 aninfo.cur_time = 0;
3576 tick = 0;
3577 while (++tick < 195000) {
3578 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3579 if (status == ANEG_DONE || status == ANEG_FAILED)
3580 break;
3581
3582 udelay(1);
3583 }
3584
3585 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3586 tw32_f(MAC_MODE, tp->mac_mode);
3587 udelay(40);
3588
5be73b47
MC		 3589 *txflags = aninfo.txconfig;
3590 *rxflags = aninfo.flags;
1da177e4
LT		 3591
3592 if (status == ANEG_DONE &&
3593 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3594 MR_LP_ADV_FULL_DUPLEX)))
3595 res = 1;
3596
3597 return res;
3598}
3599
3600static void tg3_init_bcm8002(struct tg3 *tp)
3601{
3602 u32 mac_status = tr32(MAC_STATUS);
3603 int i;
3604
3605 /* Reset when initting first time or we have a link. */
3606 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3607 !(mac_status & MAC_STATUS_PCS_SYNCED))
3608 return;
3609
3610 /* Set PLL lock range. */
3611 tg3_writephy(tp, 0x16, 0x8007);
3612
3613 /* SW reset */
3614 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3615
3616 /* Wait for reset to complete. */
3617 /* XXX schedule_timeout() ... */
3618 for (i = 0; i < 500; i++)
3619 udelay(10);
3620
3621 /* Config mode; select PMA/Ch 1 regs. */
3622 tg3_writephy(tp, 0x10, 0x8411);
3623
3624 /* Enable auto-lock and comdet, select txclk for tx. */
3625 tg3_writephy(tp, 0x11, 0x0a10);
3626
3627 tg3_writephy(tp, 0x18, 0x00a0);
3628 tg3_writephy(tp, 0x16, 0x41ff);
3629
3630 /* Assert and deassert POR. */
3631 tg3_writephy(tp, 0x13, 0x0400);
3632 udelay(40);
3633 tg3_writephy(tp, 0x13, 0x0000);
3634
3635 tg3_writephy(tp, 0x11, 0x0a50);
3636 udelay(40);
3637 tg3_writephy(tp, 0x11, 0x0a10);
3638
3639 /* Wait for signal to stabilize */
3640 /* XXX schedule_timeout() ... */
3641 for (i = 0; i < 15000; i++)
3642 udelay(10);
3643
3644 /* Deselect the channel register so we can read the PHYID
3645 * later.
3646 */
3647 tg3_writephy(tp, 0x10, 0x8011);
3648}
3649
3650static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3651{
82cd3d11 3652 u16 flowctrl;
1da177e4
LT		 3653 u32 sg_dig_ctrl, sg_dig_status;
3654 u32 serdes_cfg, expected_sg_dig_ctrl;
3655 int workaround, port_a;
3656 int current_link_up;
3657
3658 serdes_cfg = 0;
3659 expected_sg_dig_ctrl = 0;
3660 workaround = 0;
3661 port_a = 1;
3662 current_link_up = 0;
3663
3664 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3665 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3666 workaround = 1;
3667 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3668 port_a = 0;
3669
3670 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3671 /* preserve bits 20-23 for voltage regulator */
3672 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3673 }
3674
3675 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3676
3677 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3678 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3679 if (workaround) {
3680 u32 val = serdes_cfg;
3681
3682 if (port_a)
3683 val |= 0xc010000;
3684 else
3685 val |= 0x4010000;
3686 tw32_f(MAC_SERDES_CFG, val);
3687 }
c98f6e3b
MC		 3688
3689 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3690 }
3691 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3692 tg3_setup_flow_control(tp, 0, 0);
3693 current_link_up = 1;
3694 }
3695 goto out;
3696 }
3697
3698 /* Want auto-negotiation. */
c98f6e3b 3699 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3700
82cd3d11
MC		 3701 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3702 if (flowctrl & ADVERTISE_1000XPAUSE)
3703 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3704 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3705 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3706
3707 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3708 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3709 tp->serdes_counter &&
3710 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3711 MAC_STATUS_RCVD_CFG)) ==
3712 MAC_STATUS_PCS_SYNCED)) {
3713 tp->serdes_counter--;
3714 current_link_up = 1;
3715 goto out;
3716 }
3717restart_autoneg:
1da177e4
LT		 3718 if (workaround)
3719 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3720 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3721 udelay(5);
3722 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3723
3d3ebe74
MC		 3724 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3725 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3726 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3727 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3728 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3729 mac_status = tr32(MAC_STATUS);
3730
c98f6e3b 3731 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3732 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3733 u32 local_adv = 0, remote_adv = 0;
3734
3735 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3736 local_adv |= ADVERTISE_1000XPAUSE;
3737 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3738 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3739
c98f6e3b 3740 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3741 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3742 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3743 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3744
3745 tg3_setup_flow_control(tp, local_adv, remote_adv);
3746 current_link_up = 1;
3d3ebe74
MC		 3747 tp->serdes_counter = 0;
3748 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3749 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3750 if (tp->serdes_counter)
3751 tp->serdes_counter--;
1da177e4
LT		 3752 else {
3753 if (workaround) {
3754 u32 val = serdes_cfg;
3755
3756 if (port_a)
3757 val |= 0xc010000;
3758 else
3759 val |= 0x4010000;
3760
3761 tw32_f(MAC_SERDES_CFG, val);
3762 }
3763
c98f6e3b 3764 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3765 udelay(40);
3766
3767 /* Link parallel detection - link is up */
3768 /* only if we have PCS_SYNC and not */
3769 /* receiving config code words */
3770 mac_status = tr32(MAC_STATUS);
3771 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3772 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3773 tg3_setup_flow_control(tp, 0, 0);
3774 current_link_up = 1;
3d3ebe74
MC		 3775 tp->tg3_flags2 |=
3776 TG3_FLG2_PARALLEL_DETECT;
3777 tp->serdes_counter =
3778 SERDES_PARALLEL_DET_TIMEOUT;
3779 } else
3780 goto restart_autoneg;
1da177e4
LT		 3781 }
3782 }
3d3ebe74
MC		 3783 } else {
3784 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3785 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3786 }
3787
3788out:
3789 return current_link_up;
3790}
3791
3792static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3793{
3794 int current_link_up = 0;
3795
5cf64b8a 3796 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3797 goto out;
1da177e4
LT		 3798
3799 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3800 u32 txflags, rxflags;
1da177e4 3801 int i;
6aa20a22 3802
5be73b47
MC		 3803 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3804 u32 local_adv = 0, remote_adv = 0;
1da177e4 3805
5be73b47
MC		 3806 if (txflags & ANEG_CFG_PS1)
3807 local_adv |= ADVERTISE_1000XPAUSE;
3808 if (txflags & ANEG_CFG_PS2)
3809 local_adv |= ADVERTISE_1000XPSE_ASYM;
3810
3811 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3812 remote_adv |= LPA_1000XPAUSE;
3813 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3814 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3815
3816 tg3_setup_flow_control(tp, local_adv, remote_adv);
3817
1da177e4
LT		 3818 current_link_up = 1;
3819 }
3820 for (i = 0; i < 30; i++) {
3821 udelay(20);
3822 tw32_f(MAC_STATUS,
3823 (MAC_STATUS_SYNC_CHANGED |
3824 MAC_STATUS_CFG_CHANGED));
3825 udelay(40);
3826 if ((tr32(MAC_STATUS) &
3827 (MAC_STATUS_SYNC_CHANGED |
3828 MAC_STATUS_CFG_CHANGED)) == 0)
3829 break;
3830 }
3831
3832 mac_status = tr32(MAC_STATUS);
3833 if (current_link_up == 0 &&
3834 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3835 !(mac_status & MAC_STATUS_RCVD_CFG))
3836 current_link_up = 1;
3837 } else {
5be73b47
MC		 3838 tg3_setup_flow_control(tp, 0, 0);
3839
1da177e4
LT		 3840 /* Forcing 1000FD link up. */
3841 current_link_up = 1;
1da177e4
LT		 3842
3843 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3844 udelay(40);
e8f3f6ca
MC		 3845
3846 tw32_f(MAC_MODE, tp->mac_mode);
3847 udelay(40);
1da177e4
LT		 3848 }
3849
3850out:
3851 return current_link_up;
3852}
3853
3854static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3855{
3856 u32 orig_pause_cfg;
3857 u16 orig_active_speed;
3858 u8 orig_active_duplex;
3859 u32 mac_status;
3860 int current_link_up;
3861 int i;
3862
8d018621 3863 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3864 orig_active_speed = tp->link_config.active_speed;
3865 orig_active_duplex = tp->link_config.active_duplex;
3866
3867 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3868 netif_carrier_ok(tp->dev) &&
3869 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3870 mac_status = tr32(MAC_STATUS);
3871 mac_status &= (MAC_STATUS_PCS_SYNCED |
3872 MAC_STATUS_SIGNAL_DET |
3873 MAC_STATUS_CFG_CHANGED |
3874 MAC_STATUS_RCVD_CFG);
3875 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3876 MAC_STATUS_SIGNAL_DET)) {
3877 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3878 MAC_STATUS_CFG_CHANGED));
3879 return 0;
3880 }
3881 }
3882
3883 tw32_f(MAC_TX_AUTO_NEG, 0);
3884
3885 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3886 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3887 tw32_f(MAC_MODE, tp->mac_mode);
3888 udelay(40);
3889
3890 if (tp->phy_id == PHY_ID_BCM8002)
3891 tg3_init_bcm8002(tp);
3892
3893 /* Enable link change event even when serdes polling. */
3894 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3895 udelay(40);
3896
3897 current_link_up = 0;
3898 mac_status = tr32(MAC_STATUS);
3899
3900 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3901 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3902 else
3903 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3904
898a56f8 3905 tp->napi[0].hw_status->status =
1da177e4 3906 (SD_STATUS_UPDATED |
898a56f8 3907 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3908
3909 for (i = 0; i < 100; i++) {
3910 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3911 MAC_STATUS_CFG_CHANGED));
3912 udelay(5);
3913 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3914 MAC_STATUS_CFG_CHANGED |
3915 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3916 break;
3917 }
3918
3919 mac_status = tr32(MAC_STATUS);
3920 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3921 current_link_up = 0;
3d3ebe74
MC		 3922 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3923 tp->serdes_counter == 0) {
1da177e4
LT		 3924 tw32_f(MAC_MODE, (tp->mac_mode |
3925 MAC_MODE_SEND_CONFIGS));
3926 udelay(1);
3927 tw32_f(MAC_MODE, tp->mac_mode);
3928 }
3929 }
3930
3931 if (current_link_up == 1) {
3932 tp->link_config.active_speed = SPEED_1000;
3933 tp->link_config.active_duplex = DUPLEX_FULL;
3934 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3935 LED_CTRL_LNKLED_OVERRIDE |
3936 LED_CTRL_1000MBPS_ON));
3937 } else {
3938 tp->link_config.active_speed = SPEED_INVALID;
3939 tp->link_config.active_duplex = DUPLEX_INVALID;
3940 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3941 LED_CTRL_LNKLED_OVERRIDE |
3942 LED_CTRL_TRAFFIC_OVERRIDE));
3943 }
3944
3945 if (current_link_up != netif_carrier_ok(tp->dev)) {
3946 if (current_link_up)
3947 netif_carrier_on(tp->dev);
3948 else
3949 netif_carrier_off(tp->dev);
3950 tg3_link_report(tp);
3951 } else {
8d018621 3952 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3953 if (orig_pause_cfg != now_pause_cfg ||
3954 orig_active_speed != tp->link_config.active_speed ||
3955 orig_active_duplex != tp->link_config.active_duplex)
3956 tg3_link_report(tp);
3957 }
3958
3959 return 0;
3960}
3961
747e8f8b
MC		 3962static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3963{
3964 int current_link_up, err = 0;
3965 u32 bmsr, bmcr;
3966 u16 current_speed;
3967 u8 current_duplex;
ef167e27 3968 u32 local_adv, remote_adv;
747e8f8b
MC		 3969
3970 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3971 tw32_f(MAC_MODE, tp->mac_mode);
3972 udelay(40);
3973
3974 tw32(MAC_EVENT, 0);
3975
3976 tw32_f(MAC_STATUS,
3977 (MAC_STATUS_SYNC_CHANGED |
3978 MAC_STATUS_CFG_CHANGED |
3979 MAC_STATUS_MI_COMPLETION |
3980 MAC_STATUS_LNKSTATE_CHANGED));
3981 udelay(40);
3982
3983 if (force_reset)
3984 tg3_phy_reset(tp);
3985
3986 current_link_up = 0;
3987 current_speed = SPEED_INVALID;
3988 current_duplex = DUPLEX_INVALID;
3989
3990 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3991 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 3992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3993 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3994 bmsr |= BMSR_LSTATUS;
3995 else
3996 bmsr &= ~BMSR_LSTATUS;
3997 }
747e8f8b
MC		 3998
3999 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4000
4001 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4002 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4003 /* do nothing, just check for link up at the end */
4004 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4005 u32 adv, new_adv;
4006
4007 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4008 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4009 ADVERTISE_1000XPAUSE |
4010 ADVERTISE_1000XPSE_ASYM |
4011 ADVERTISE_SLCT);
4012
ba4d07a8 4013 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4014
4015 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4016 new_adv |= ADVERTISE_1000XHALF;
4017 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4018 new_adv |= ADVERTISE_1000XFULL;
4019
4020 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4021 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4022 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4023 tg3_writephy(tp, MII_BMCR, bmcr);
4024
4025 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4026 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4027 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4028
4029 return err;
4030 }
4031 } else {
4032 u32 new_bmcr;
4033
4034 bmcr &= ~BMCR_SPEED1000;
4035 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4036
4037 if (tp->link_config.duplex == DUPLEX_FULL)
4038 new_bmcr |= BMCR_FULLDPLX;
4039
4040 if (new_bmcr != bmcr) {
4041 /* BMCR_SPEED1000 is a reserved bit that needs
4042 * to be set on write.
4043 */
4044 new_bmcr |= BMCR_SPEED1000;
4045
4046 /* Force a linkdown */
4047 if (netif_carrier_ok(tp->dev)) {
4048 u32 adv;
4049
4050 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4051 adv &= ~(ADVERTISE_1000XFULL |
4052 ADVERTISE_1000XHALF |
4053 ADVERTISE_SLCT);
4054 tg3_writephy(tp, MII_ADVERTISE, adv);
4055 tg3_writephy(tp, MII_BMCR, bmcr |
4056 BMCR_ANRESTART |
4057 BMCR_ANENABLE);
4058 udelay(10);
4059 netif_carrier_off(tp->dev);
4060 }
4061 tg3_writephy(tp, MII_BMCR, new_bmcr);
4062 bmcr = new_bmcr;
4063 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4064 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4065 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4066 ASIC_REV_5714) {
4067 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4068 bmsr |= BMSR_LSTATUS;
4069 else
4070 bmsr &= ~BMSR_LSTATUS;
4071 }
747e8f8b
MC		 4072 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4073 }
4074 }
4075
4076 if (bmsr & BMSR_LSTATUS) {
4077 current_speed = SPEED_1000;
4078 current_link_up = 1;
4079 if (bmcr & BMCR_FULLDPLX)
4080 current_duplex = DUPLEX_FULL;
4081 else
4082 current_duplex = DUPLEX_HALF;
4083
ef167e27
MC		 4084 local_adv = 0;
4085 remote_adv = 0;
4086
747e8f8b 4087 if (bmcr & BMCR_ANENABLE) {
ef167e27 4088 u32 common;
747e8f8b
MC		 4089
4090 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4091 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4092 common = local_adv & remote_adv;
4093 if (common & (ADVERTISE_1000XHALF |
4094 ADVERTISE_1000XFULL)) {
4095 if (common & ADVERTISE_1000XFULL)
4096 current_duplex = DUPLEX_FULL;
4097 else
4098 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4099 }
4100 else
4101 current_link_up = 0;
4102 }
4103 }
4104
ef167e27
MC		 4105 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4106 tg3_setup_flow_control(tp, local_adv, remote_adv);
4107
747e8f8b
MC		 4108 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4109 if (tp->link_config.active_duplex == DUPLEX_HALF)
4110 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4111
4112 tw32_f(MAC_MODE, tp->mac_mode);
4113 udelay(40);
4114
4115 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4116
4117 tp->link_config.active_speed = current_speed;
4118 tp->link_config.active_duplex = current_duplex;
4119
4120 if (current_link_up != netif_carrier_ok(tp->dev)) {
4121 if (current_link_up)
4122 netif_carrier_on(tp->dev);
4123 else {
4124 netif_carrier_off(tp->dev);
4125 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126 }
4127 tg3_link_report(tp);
4128 }
4129 return err;
4130}
4131
4132static void tg3_serdes_parallel_detect(struct tg3 *tp)
4133{
3d3ebe74 4134 if (tp->serdes_counter) {
747e8f8b 4135 /* Give autoneg time to complete. */
3d3ebe74 4136 tp->serdes_counter--;
747e8f8b
MC		 4137 return;
4138 }
4139 if (!netif_carrier_ok(tp->dev) &&
4140 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4141 u32 bmcr;
4142
4143 tg3_readphy(tp, MII_BMCR, &bmcr);
4144 if (bmcr & BMCR_ANENABLE) {
4145 u32 phy1, phy2;
4146
4147 /* Select shadow register 0x1f */
4148 tg3_writephy(tp, 0x1c, 0x7c00);
4149 tg3_readphy(tp, 0x1c, &phy1);
4150
4151 /* Select expansion interrupt status register */
4152 tg3_writephy(tp, 0x17, 0x0f01);
4153 tg3_readphy(tp, 0x15, &phy2);
4154 tg3_readphy(tp, 0x15, &phy2);
4155
4156 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4157 /* We have signal detect and not receiving
4158 * config code words, link is up by parallel
4159 * detection.
4160 */
4161
4162 bmcr &= ~BMCR_ANENABLE;
4163 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4164 tg3_writephy(tp, MII_BMCR, bmcr);
4165 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4166 }
4167 }
4168 }
4169 else if (netif_carrier_ok(tp->dev) &&
4170 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4171 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4172 u32 phy2;
4173
4174 /* Select expansion interrupt status register */
4175 tg3_writephy(tp, 0x17, 0x0f01);
4176 tg3_readphy(tp, 0x15, &phy2);
4177 if (phy2 & 0x20) {
4178 u32 bmcr;
4179
4180 /* Config code words received, turn on autoneg. */
4181 tg3_readphy(tp, MII_BMCR, &bmcr);
4182 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4183
4184 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4185
4186 }
4187 }
4188}
4189
1da177e4
LT		 4190static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4191{
4192 int err;
4193
4194 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4195 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4196 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4197 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4198 } else {
4199 err = tg3_setup_copper_phy(tp, force_reset);
4200 }
4201
bcb37f6c 4202 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4203 u32 val, scale;
4204
4205 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4206 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4207 scale = 65;
4208 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4209 scale = 6;
4210 else
4211 scale = 12;
4212
4213 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4214 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4215 tw32(GRC_MISC_CFG, val);
4216 }
4217
1da177e4
LT		 4218 if (tp->link_config.active_speed == SPEED_1000 &&
4219 tp->link_config.active_duplex == DUPLEX_HALF)
4220 tw32(MAC_TX_LENGTHS,
4221 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4222 (6 << TX_LENGTHS_IPG_SHIFT) |
4223 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4224 else
4225 tw32(MAC_TX_LENGTHS,
4226 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4227 (6 << TX_LENGTHS_IPG_SHIFT) |
4228 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4229
4230 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4231 if (netif_carrier_ok(tp->dev)) {
4232 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4233 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4234 } else {
4235 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4236 }
4237 }
4238
8ed5d97e
MC		 4239 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4240 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4241 if (!netif_carrier_ok(tp->dev))
4242 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4243 tp->pwrmgmt_thresh;
4244 else
4245 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4246 tw32(PCIE_PWR_MGMT_THRESH, val);
4247 }
4248
1da177e4
LT		 4249 return err;
4250}
4251
df3e6548
MC		 4252/* This is called whenever we suspect that the system chipset is re-
4253 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4254 * is bogus tx completions. We try to recover by setting the
4255 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4256 * in the workqueue.
4257 */
4258static void tg3_tx_recover(struct tg3 *tp)
4259{
4260 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4261 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4262
4263 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4264 "mapped I/O cycles to the network device, attempting to "
4265 "recover. Please report the problem to the driver maintainer "
4266 "and include system chipset information.\n", tp->dev->name);
4267
4268 spin_lock(&tp->lock);
df3e6548 4269 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4270 spin_unlock(&tp->lock);
4271}
4272
f3f3f27e 4273static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4274{
4275 smp_mb();
f3f3f27e
MC		 4276 return tnapi->tx_pending -
4277 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4278}
4279
1da177e4
LT		 4280/* Tigon3 never reports partial packet sends. So we do not
4281 * need special logic to handle SKBs that have not had all
4282 * of their frags sent yet, like SunGEM does.
4283 */
17375d25 4284static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4285{
17375d25 4286 struct tg3 *tp = tnapi->tp;
898a56f8 4287 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4288 u32 sw_idx = tnapi->tx_cons;
1da177e4
LT		 4289
4290 while (sw_idx != hw_idx) {
f3f3f27e 4291 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4292 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4293 int i, tx_bug = 0;
4294
4295 if (unlikely(skb == NULL)) {
4296 tg3_tx_recover(tp);
4297 return;
4298 }
1da177e4 4299
90079ce8 4300 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4301
4302 ri->skb = NULL;
4303
4304 sw_idx = NEXT_TX(sw_idx);
4305
4306 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4307 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4308 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4309 tx_bug = 1;
1da177e4
LT		 4310 sw_idx = NEXT_TX(sw_idx);
4311 }
4312
f47c11ee 4313 dev_kfree_skb(skb);
df3e6548
MC		 4314
4315 if (unlikely(tx_bug)) {
4316 tg3_tx_recover(tp);
4317 return;
4318 }
1da177e4
LT		 4319 }
4320
f3f3f27e 4321 tnapi->tx_cons = sw_idx;
1da177e4 4322
1b2a7205
MC		 4323 /* Need to make the tx_cons update visible to tg3_start_xmit()
4324 * before checking for netif_queue_stopped(). Without the
4325 * memory barrier, there is a small possibility that tg3_start_xmit()
4326 * will miss it and cause the queue to be stopped forever.
4327 */
4328 smp_mb();
4329
4330 if (unlikely(netif_queue_stopped(tp->dev) &&
f3f3f27e 4331 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
1b2a7205 4332 netif_tx_lock(tp->dev);
51b91468 4333 if (netif_queue_stopped(tp->dev) &&
f3f3f27e 4334 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
51b91468 4335 netif_wake_queue(tp->dev);
1b2a7205 4336 netif_tx_unlock(tp->dev);
51b91468 4337 }
1da177e4
LT		 4338}
4339
4340/* Returns size of skb allocated or < 0 on error.
4341 *
4342 * We only need to fill in the address because the other members
4343 * of the RX descriptor are invariant, see tg3_init_rings.
4344 *
4345 * Note the purposeful assymetry of cpu vs. chip accesses. For
4346 * posting buffers we only dirty the first cache line of the RX
4347 * descriptor (containing the address). Whereas for the RX status
4348 * buffers the cpu only reads the last cacheline of the RX descriptor
4349 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4350 */
17375d25 4351static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4352 int src_idx, u32 dest_idx_unmasked)
4353{
17375d25 4354 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4355 struct tg3_rx_buffer_desc *desc;
4356 struct ring_info *map, *src_map;
4357 struct sk_buff *skb;
4358 dma_addr_t mapping;
4359 int skb_size, dest_idx;
21f581a5 4360 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4361
4362 src_map = NULL;
4363 switch (opaque_key) {
4364 case RXD_OPAQUE_RING_STD:
4365 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4366 desc = &tpr->rx_std[dest_idx];
4367 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4368 if (src_idx >= 0)
21f581a5 4369 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4370 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4371 break;
4372
4373 case RXD_OPAQUE_RING_JUMBO:
4374 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4375 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4376 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4377 if (src_idx >= 0)
21f581a5 4378 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4379 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4380 break;
4381
4382 default:
4383 return -EINVAL;
855e1111 4384 }
1da177e4
LT		 4385
4386 /* Do not overwrite any of the map or rp information
4387 * until we are sure we can commit to a new buffer.
4388 *
4389 * Callers depend upon this behavior and assume that
4390 * we leave everything unchanged if we fail.
4391 */
287be12e 4392 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4393 if (skb == NULL)
4394 return -ENOMEM;
4395
1da177e4
LT		 4396 skb_reserve(skb, tp->rx_offset);
4397
287be12e 4398 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4
LT		 4399 PCI_DMA_FROMDEVICE);
4400
4401 map->skb = skb;
4402 pci_unmap_addr_set(map, mapping, mapping);
4403
4404 if (src_map != NULL)
4405 src_map->skb = NULL;
4406
4407 desc->addr_hi = ((u64)mapping >> 32);
4408 desc->addr_lo = ((u64)mapping & 0xffffffff);
4409
4410 return skb_size;
4411}
4412
4413/* We only need to move over in the address because the other
4414 * members of the RX descriptor are invariant. See notes above
4415 * tg3_alloc_rx_skb for full details.
4416 */
17375d25 4417static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4418 int src_idx, u32 dest_idx_unmasked)
4419{
17375d25 4420 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4421 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4422 struct ring_info *src_map, *dest_map;
4423 int dest_idx;
21f581a5 4424 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4425
4426 switch (opaque_key) {
4427 case RXD_OPAQUE_RING_STD:
4428 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4429 dest_desc = &tpr->rx_std[dest_idx];
4430 dest_map = &tpr->rx_std_buffers[dest_idx];
4431 src_desc = &tpr->rx_std[src_idx];
4432 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4433 break;
4434
4435 case RXD_OPAQUE_RING_JUMBO:
4436 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4437 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4438 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4439 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4440 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4441 break;
4442
4443 default:
4444 return;
855e1111 4445 }
1da177e4
LT		 4446
4447 dest_map->skb = src_map->skb;
4448 pci_unmap_addr_set(dest_map, mapping,
4449 pci_unmap_addr(src_map, mapping));
4450 dest_desc->addr_hi = src_desc->addr_hi;
4451 dest_desc->addr_lo = src_desc->addr_lo;
4452
4453 src_map->skb = NULL;
4454}
4455
1da177e4
LT		 4456/* The RX ring scheme is composed of multiple rings which post fresh
4457 * buffers to the chip, and one special ring the chip uses to report
4458 * status back to the host.
4459 *
4460 * The special ring reports the status of received packets to the
4461 * host. The chip does not write into the original descriptor the
4462 * RX buffer was obtained from. The chip simply takes the original
4463 * descriptor as provided by the host, updates the status and length
4464 * field, then writes this into the next status ring entry.
4465 *
4466 * Each ring the host uses to post buffers to the chip is described
4467 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4468 * it is first placed into the on-chip ram. When the packet's length
4469 * is known, it walks down the TG3_BDINFO entries to select the ring.
4470 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4471 * which is within the range of the new packet's length is chosen.
4472 *
4473 * The "separate ring for rx status" scheme may sound queer, but it makes
4474 * sense from a cache coherency perspective. If only the host writes
4475 * to the buffer post rings, and only the chip writes to the rx status
4476 * rings, then cache lines never move beyond shared-modified state.
4477 * If both the host and chip were to write into the same ring, cache line
4478 * eviction could occur since both entities want it in an exclusive state.
4479 */
17375d25 4480static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4481{
17375d25 4482 struct tg3 *tp = tnapi->tp;
f92905de 4483 u32 work_mask, rx_std_posted = 0;
72334482 4484 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4485 u16 hw_idx;
1da177e4 4486 int received;
21f581a5 4487 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4488
898a56f8 4489 hw_idx = tnapi->hw_status->idx[0].rx_producer;
1da177e4
LT		 4490 /*
4491 * We need to order the read of hw_idx and the read of
4492 * the opaque cookie.
4493 */
4494 rmb();
1da177e4
LT		 4495 work_mask = 0;
4496 received = 0;
4497 while (sw_idx != hw_idx && budget > 0) {
72334482 4498 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4499 unsigned int len;
4500 struct sk_buff *skb;
4501 dma_addr_t dma_addr;
4502 u32 opaque_key, desc_idx, *post_ptr;
4503
4504 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4505 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4506 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4507 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4508 dma_addr = pci_unmap_addr(ri, mapping);
4509 skb = ri->skb;
4510 post_ptr = &tpr->rx_std_ptr;
f92905de 4511 rx_std_posted++;
1da177e4 4512 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4513 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4514 dma_addr = pci_unmap_addr(ri, mapping);
4515 skb = ri->skb;
4516 post_ptr = &tpr->rx_jmb_ptr;
4517 } else
1da177e4 4518 goto next_pkt_nopost;
1da177e4
LT		 4519
4520 work_mask |= opaque_key;
4521
4522 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4523 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4524 drop_it:
17375d25 4525 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4526 desc_idx, *post_ptr);
4527 drop_it_no_recycle:
4528 /* Other statistics kept track of by card. */
4529 tp->net_stats.rx_dropped++;
4530 goto next_pkt;
4531 }
4532
ad829268
MC		 4533 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4534 ETH_FCS_LEN;
1da177e4 4535
6aa20a22 4536 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4537 && tp->rx_offset == NET_IP_ALIGN
4538 /* rx_offset will likely not equal NET_IP_ALIGN
4539 * if this is a 5701 card running in PCI-X mode
4540 * [see tg3_get_invariants()]
4541 */
1da177e4
LT		 4542 ) {
4543 int skb_size;
4544
17375d25 4545 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4546 desc_idx, *post_ptr);
4547 if (skb_size < 0)
4548 goto drop_it;
4549
287be12e 4550 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4551 PCI_DMA_FROMDEVICE);
4552
4553 skb_put(skb, len);
4554 } else {
4555 struct sk_buff *copy_skb;
4556
17375d25 4557 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4558 desc_idx, *post_ptr);
4559
ad829268
MC		 4560 copy_skb = netdev_alloc_skb(tp->dev,
4561 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4562 if (copy_skb == NULL)
4563 goto drop_it_no_recycle;
4564
ad829268 4565 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4566 skb_put(copy_skb, len);
4567 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4568 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4569 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4570
4571 /* We'll reuse the original ring buffer. */
4572 skb = copy_skb;
4573 }
4574
4575 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4576 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4577 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4578 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4579 skb->ip_summed = CHECKSUM_UNNECESSARY;
4580 else
4581 skb->ip_summed = CHECKSUM_NONE;
4582
4583 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4584
4585 if (len > (tp->dev->mtu + ETH_HLEN) &&
4586 skb->protocol != htons(ETH_P_8021Q)) {
4587 dev_kfree_skb(skb);
4588 goto next_pkt;
4589 }
4590
1da177e4
LT		 4591#if TG3_VLAN_TAG_USED
4592 if (tp->vlgrp != NULL &&
4593 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4594 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4595 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4596 } else
4597#endif
17375d25 4598 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4599
1da177e4
LT		 4600 received++;
4601 budget--;
4602
4603next_pkt:
4604 (*post_ptr)++;
f92905de
MC		 4605
4606 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4607 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4608
4609 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4610 TG3_64BIT_REG_LOW, idx);
4611 work_mask &= ~RXD_OPAQUE_RING_STD;
4612 rx_std_posted = 0;
4613 }
1da177e4 4614next_pkt_nopost:
483ba50b 4615 sw_idx++;
6b31a515 4616 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4617
4618 /* Refresh hw_idx to see if there is new work */
4619 if (sw_idx == hw_idx) {
898a56f8 4620 hw_idx = tnapi->hw_status->idx[0].rx_producer;
52f6d697
MC		 4621 rmb();
4622 }
1da177e4
LT		 4623 }
4624
4625 /* ACK the status ring. */
72334482
MC		 4626 tnapi->rx_rcb_ptr = sw_idx;
4627 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4628
4629 /* Refill RX ring(s). */
4630 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4631 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4632 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4633 sw_idx);
4634 }
4635 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4636 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4637 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4638 sw_idx);
4639 }
4640 mmiowb();
4641
4642 return received;
4643}
4644
17375d25 4645static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4646{
17375d25 4647 struct tg3 *tp = tnapi->tp;
898a56f8 4648 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4649
1da177e4
LT		 4650 /* handle link change and other phy events */
4651 if (!(tp->tg3_flags &
4652 (TG3_FLAG_USE_LINKCHG_REG |
4653 TG3_FLAG_POLL_SERDES))) {
4654 if (sblk->status & SD_STATUS_LINK_CHG) {
4655 sblk->status = SD_STATUS_UPDATED |
4656 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4657 spin_lock(&tp->lock);
dd477003
MC		 4658 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4659 tw32_f(MAC_STATUS,
4660 (MAC_STATUS_SYNC_CHANGED |
4661 MAC_STATUS_CFG_CHANGED |
4662 MAC_STATUS_MI_COMPLETION |
4663 MAC_STATUS_LNKSTATE_CHANGED));
4664 udelay(40);
4665 } else
4666 tg3_setup_phy(tp, 0);
f47c11ee 4667 spin_unlock(&tp->lock);
1da177e4
LT		 4668 }
4669 }
4670
4671 /* run TX completion thread */
f3f3f27e 4672 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4673 tg3_tx(tnapi);
6f535763 4674 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4675 return work_done;
1da177e4
LT		 4676 }
4677
1da177e4
LT		 4678 /* run RX thread, within the bounds set by NAPI.
4679 * All RX "locking" is done by ensuring outside
bea3348e 4680 * code synchronizes with tg3->napi.poll()
1da177e4 4681 */
72334482 4682 if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
17375d25 4683 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4684
6f535763
DM		 4685 return work_done;
4686}
4687
4688static int tg3_poll(struct napi_struct *napi, int budget)
4689{
8ef0442f
MC		 4690 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4691 struct tg3 *tp = tnapi->tp;
6f535763 4692 int work_done = 0;
898a56f8 4693 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4694
4695 while (1) {
17375d25 4696 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4697
4698 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4699 goto tx_recovery;
4700
4701 if (unlikely(work_done >= budget))
4702 break;
4703
4fd7ab59 4704 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4705 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4706 * to tell the hw how much work has been processed,
4707 * so we must read it before checking for more work.
4708 */
898a56f8
MC		 4709 tnapi->last_tag = sblk->status_tag;
4710 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4711 rmb();
4712 } else
4713 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4714
17375d25 4715 if (likely(!tg3_has_work(tnapi))) {
288379f0 4716 napi_complete(napi);
17375d25 4717 tg3_int_reenable(tnapi);
6f535763
DM		 4718 break;
4719 }
1da177e4
LT		 4720 }
4721
bea3348e 4722 return work_done;
6f535763
DM		 4723
4724tx_recovery:
4fd7ab59 4725 /* work_done is guaranteed to be less than budget. */
288379f0 4726 napi_complete(napi);
6f535763 4727 schedule_work(&tp->reset_task);
4fd7ab59 4728 return work_done;
1da177e4
LT		 4729}
4730
f47c11ee
DM		 4731static void tg3_irq_quiesce(struct tg3 *tp)
4732{
4f125f42
MC		 4733 int i;
4734
f47c11ee
DM		 4735 BUG_ON(tp->irq_sync);
4736
4737 tp->irq_sync = 1;
4738 smp_mb();
4739
4f125f42
MC		 4740 for (i = 0; i < tp->irq_cnt; i++)
4741 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4742}
4743
4744static inline int tg3_irq_sync(struct tg3 *tp)
4745{
4746 return tp->irq_sync;
4747}
4748
4749/* Fully shutdown all tg3 driver activity elsewhere in the system.
4750 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4751 * with as well. Most of the time, this is not necessary except when
4752 * shutting down the device.
4753 */
4754static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4755{
46966545 4756 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4757 if (irq_sync)
4758 tg3_irq_quiesce(tp);
f47c11ee
DM		 4759}
4760
4761static inline void tg3_full_unlock(struct tg3 *tp)
4762{
f47c11ee
DM		 4763 spin_unlock_bh(&tp->lock);
4764}
4765
fcfa0a32
MC		 4766/* One-shot MSI handler - Chip automatically disables interrupt
4767 * after sending MSI so driver doesn't have to do it.
4768 */
7d12e780 4769static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4770{
09943a18
MC		 4771 struct tg3_napi *tnapi = dev_id;
4772 struct tg3 *tp = tnapi->tp;
fcfa0a32 4773
898a56f8 4774 prefetch(tnapi->hw_status);
72334482 4775 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4776
4777 if (likely(!tg3_irq_sync(tp)))
09943a18 4778 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4779
4780 return IRQ_HANDLED;
4781}
4782
88b06bc2
MC		 4783/* MSI ISR - No need to check for interrupt sharing and no need to
4784 * flush status block and interrupt mailbox. PCI ordering rules
4785 * guarantee that MSI will arrive after the status block.
4786 */
7d12e780 4787static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4788{
09943a18
MC		 4789 struct tg3_napi *tnapi = dev_id;
4790 struct tg3 *tp = tnapi->tp;
88b06bc2 4791
898a56f8 4792 prefetch(tnapi->hw_status);
72334482 4793 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4794 /*
fac9b83e 4795 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4796 * chip-internal interrupt pending events.
fac9b83e 4797 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4798 * NIC to stop sending us irqs, engaging "in-intr-handler"
4799 * event coalescing.
4800 */
4801 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4802 if (likely(!tg3_irq_sync(tp)))
09943a18 4803 napi_schedule(&tnapi->napi);
61487480 4804
88b06bc2
MC		 4805 return IRQ_RETVAL(1);
4806}
4807
7d12e780 4808static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4809{
09943a18
MC		 4810 struct tg3_napi *tnapi = dev_id;
4811 struct tg3 *tp = tnapi->tp;
898a56f8 4812 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4813 unsigned int handled = 1;
4814
1da177e4
LT		 4815 /* In INTx mode, it is possible for the interrupt to arrive at
4816 * the CPU before the status block posted prior to the interrupt.
4817 * Reading the PCI State register will confirm whether the
4818 * interrupt is ours and will flush the status block.
4819 */
d18edcb2
MC		 4820 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4821 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4822 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4823 handled = 0;
f47c11ee 4824 goto out;
fac9b83e 4825 }
d18edcb2
MC		 4826 }
4827
4828 /*
4829 * Writing any value to intr-mbox-0 clears PCI INTA# and
4830 * chip-internal interrupt pending events.
4831 * Writing non-zero to intr-mbox-0 additional tells the
4832 * NIC to stop sending us irqs, engaging "in-intr-handler"
4833 * event coalescing.
c04cb347
MC		 4834 *
4835 * Flush the mailbox to de-assert the IRQ immediately to prevent
4836 * spurious interrupts. The flush impacts performance but
4837 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4838 */
c04cb347 4839 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4840 if (tg3_irq_sync(tp))
4841 goto out;
4842 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4843 if (likely(tg3_has_work(tnapi))) {
72334482 4844 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4845 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4846 } else {
4847 /* No work, shared interrupt perhaps? re-enable
4848 * interrupts, and flush that PCI write
4849 */
4850 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4851 0x00000000);
fac9b83e 4852 }
f47c11ee 4853out:
fac9b83e
DM		 4854 return IRQ_RETVAL(handled);
4855}
4856
7d12e780 4857static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4858{
09943a18
MC		 4859 struct tg3_napi *tnapi = dev_id;
4860 struct tg3 *tp = tnapi->tp;
898a56f8 4861 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4862 unsigned int handled = 1;
4863
fac9b83e
DM		 4864 /* In INTx mode, it is possible for the interrupt to arrive at
4865 * the CPU before the status block posted prior to the interrupt.
4866 * Reading the PCI State register will confirm whether the
4867 * interrupt is ours and will flush the status block.
4868 */
898a56f8 4869 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4870 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4871 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4872 handled = 0;
f47c11ee 4873 goto out;
1da177e4 4874 }
d18edcb2
MC		 4875 }
4876
4877 /*
4878 * writing any value to intr-mbox-0 clears PCI INTA# and
4879 * chip-internal interrupt pending events.
4880 * writing non-zero to intr-mbox-0 additional tells the
4881 * NIC to stop sending us irqs, engaging "in-intr-handler"
4882 * event coalescing.
c04cb347
MC		 4883 *
4884 * Flush the mailbox to de-assert the IRQ immediately to prevent
4885 * spurious interrupts. The flush impacts performance but
4886 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4887 */
c04cb347 4888 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4889
4890 /*
4891 * In a shared interrupt configuration, sometimes other devices'
4892 * interrupts will scream. We record the current status tag here
4893 * so that the above check can report that the screaming interrupts
4894 * are unhandled. Eventually they will be silenced.
4895 */
898a56f8 4896 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4897
d18edcb2
MC		 4898 if (tg3_irq_sync(tp))
4899 goto out;
624f8e50 4900
72334482 4901 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4902
09943a18 4903 napi_schedule(&tnapi->napi);
624f8e50 4904
f47c11ee 4905out:
1da177e4
LT		 4906 return IRQ_RETVAL(handled);
4907}
4908
7938109f 4909/* ISR for interrupt test */
7d12e780 4910static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4911{
09943a18
MC		 4912 struct tg3_napi *tnapi = dev_id;
4913 struct tg3 *tp = tnapi->tp;
898a56f8 4914 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4915
f9804ddb
MC		 4916 if ((sblk->status & SD_STATUS_UPDATED) ||
4917 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4918 tg3_disable_ints(tp);
7938109f
MC		 4919 return IRQ_RETVAL(1);
4920 }
4921 return IRQ_RETVAL(0);
4922}
4923
8e7a22e3 4924static int tg3_init_hw(struct tg3 *, int);
944d980e 4925static int tg3_halt(struct tg3 *, int, int);
1da177e4 4926
b9ec6c1b
MC		 4927/* Restart hardware after configuration changes, self-test, etc.
4928 * Invoked with tp->lock held.
4929 */
4930static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4931 __releases(tp->lock)
4932 __acquires(tp->lock)
b9ec6c1b
MC		 4933{
4934 int err;
4935
4936 err = tg3_init_hw(tp, reset_phy);
4937 if (err) {
4938 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4939 "aborting.\n", tp->dev->name);
4940 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4941 tg3_full_unlock(tp);
4942 del_timer_sync(&tp->timer);
4943 tp->irq_sync = 0;
8ef0442f 4944 napi_enable(&tp->napi[0].napi);
b9ec6c1b
MC		 4945 dev_close(tp->dev);
4946 tg3_full_lock(tp, 0);
4947 }
4948 return err;
4949}
4950
1da177e4
LT		 4951#ifdef CONFIG_NET_POLL_CONTROLLER
4952static void tg3_poll_controller(struct net_device *dev)
4953{
4f125f42 4954 int i;
88b06bc2
MC		 4955 struct tg3 *tp = netdev_priv(dev);
4956
4f125f42
MC		 4957 for (i = 0; i < tp->irq_cnt; i++)
4958 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 4959}
4960#endif
4961
c4028958 4962static void tg3_reset_task(struct work_struct *work)
1da177e4 4963{
c4028958 4964 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 4965 int err;
1da177e4
LT		 4966 unsigned int restart_timer;
4967
7faa006f 4968 tg3_full_lock(tp, 0);
7faa006f
MC		 4969
4970 if (!netif_running(tp->dev)) {
7faa006f
MC		 4971 tg3_full_unlock(tp);
4972 return;
4973 }
4974
4975 tg3_full_unlock(tp);
4976
b02fd9e3
MC		 4977 tg3_phy_stop(tp);
4978
1da177e4
LT		 4979 tg3_netif_stop(tp);
4980
f47c11ee 4981 tg3_full_lock(tp, 1);
1da177e4
LT		 4982
4983 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4984 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4985
df3e6548
MC		 4986 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4987 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4988 tp->write32_rx_mbox = tg3_write_flush_reg32;
4989 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4990 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4991 }
4992
944d980e 4993 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 4994 err = tg3_init_hw(tp, 1);
4995 if (err)
b9ec6c1b 4996 goto out;
1da177e4
LT		 4997
4998 tg3_netif_start(tp);
4999
1da177e4
LT		 5000 if (restart_timer)
5001 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5002
b9ec6c1b 5003out:
7faa006f 5004 tg3_full_unlock(tp);
b02fd9e3
MC		 5005
5006 if (!err)
5007 tg3_phy_start(tp);
1da177e4
LT		 5008}
5009
b0408751
MC		 5010static void tg3_dump_short_state(struct tg3 *tp)
5011{
5012 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5013 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5014 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5015 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5016}
5017
1da177e4
LT		 5018static void tg3_tx_timeout(struct net_device *dev)
5019{
5020 struct tg3 *tp = netdev_priv(dev);
5021
b0408751 5022 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5023 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5024 dev->name);
b0408751
MC		 5025 tg3_dump_short_state(tp);
5026 }
1da177e4
LT		 5027
5028 schedule_work(&tp->reset_task);
5029}
5030
c58ec932
MC		 5031/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5032static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5033{
5034 u32 base = (u32) mapping & 0xffffffff;
5035
5036 return ((base > 0xffffdcc0) &&
5037 (base + len + 8 < base));
5038}
5039
72f2afb8
MC		 5040/* Test for DMA addresses > 40-bit */
5041static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5042 int len)
5043{
5044#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5045 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5046 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5047 return 0;
5048#else
5049 return 0;
5050#endif
5051}
5052
f3f3f27e 5053static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5054
72f2afb8
MC		 5055/* Workaround 4GB and 40-bit hardware DMA bugs. */
5056static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5057 u32 last_plus_one, u32 *start,
5058 u32 base_flags, u32 mss)
1da177e4 5059{
f3f3f27e 5060 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5061 struct sk_buff *new_skb;
c58ec932 5062 dma_addr_t new_addr = 0;
1da177e4 5063 u32 entry = *start;
c58ec932 5064 int i, ret = 0;
1da177e4 5065
41588ba1
MC		 5066 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5067 new_skb = skb_copy(skb, GFP_ATOMIC);
5068 else {
5069 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5070
5071 new_skb = skb_copy_expand(skb,
5072 skb_headroom(skb) + more_headroom,
5073 skb_tailroom(skb), GFP_ATOMIC);
5074 }
5075
1da177e4 5076 if (!new_skb) {
c58ec932
MC		 5077 ret = -1;
5078 } else {
5079 /* New SKB is guaranteed to be linear. */
5080 entry = *start;
90079ce8 5081 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5082 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5083
c58ec932
MC		 5084 /* Make sure new skb does not cross any 4G boundaries.
5085 * Drop the packet if it does.
5086 */
90079ce8 5087 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
638266f7
DM		 5088 if (!ret)
5089 skb_dma_unmap(&tp->pdev->dev, new_skb,
5090 DMA_TO_DEVICE);
c58ec932
MC		 5091 ret = -1;
5092 dev_kfree_skb(new_skb);
5093 new_skb = NULL;
5094 } else {
f3f3f27e 5095 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5096 base_flags, 1 | (mss << 1));
5097 *start = NEXT_TX(entry);
5098 }
1da177e4
LT		 5099 }
5100
1da177e4
LT		 5101 /* Now clean up the sw ring entries. */
5102 i = 0;
5103 while (entry != last_plus_one) {
f3f3f27e
MC		 5104 if (i == 0)
5105 tnapi->tx_buffers[entry].skb = new_skb;
5106 else
5107 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5108 entry = NEXT_TX(entry);
5109 i++;
5110 }
5111
90079ce8 5112 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5113 dev_kfree_skb(skb);
5114
c58ec932 5115 return ret;
1da177e4
LT		 5116}
5117
f3f3f27e 5118static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5119 dma_addr_t mapping, int len, u32 flags,
5120 u32 mss_and_is_end)
5121{
f3f3f27e 5122 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5123 int is_end = (mss_and_is_end & 0x1);
5124 u32 mss = (mss_and_is_end >> 1);
5125 u32 vlan_tag = 0;
5126
5127 if (is_end)
5128 flags |= TXD_FLAG_END;
5129 if (flags & TXD_FLAG_VLAN) {
5130 vlan_tag = flags >> 16;
5131 flags &= 0xffff;
5132 }
5133 vlan_tag |= (mss << TXD_MSS_SHIFT);
5134
5135 txd->addr_hi = ((u64) mapping >> 32);
5136 txd->addr_lo = ((u64) mapping & 0xffffffff);
5137 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5138 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5139}
5140
5a6f3074
MC		 5141/* hard_start_xmit for devices that don't have any bugs and
5142 * support TG3_FLG2_HW_TSO_2 only.
5143 */
61357325
SH		 5144static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5145 struct net_device *dev)
5a6f3074
MC		 5146{
5147 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5148 u32 len, entry, base_flags, mss;
90079ce8
DM		 5149 struct skb_shared_info *sp;
5150 dma_addr_t mapping;
f3f3f27e 5151 struct tg3_napi *tnapi = &tp->napi[0];
5a6f3074
MC		 5152
5153 len = skb_headlen(skb);
5154
00b70504 5155 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5156 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5157 * interrupt. Furthermore, IRQ processing runs lockless so we have
5158 * no IRQ context deadlocks to worry about either. Rejoice!
5159 */
f3f3f27e 5160 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5a6f3074
MC		 5161 if (!netif_queue_stopped(dev)) {
5162 netif_stop_queue(dev);
5163
5164 /* This is a hard error, log it. */
5165 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5166 "queue awake!\n", dev->name);
5167 }
5a6f3074
MC		 5168 return NETDEV_TX_BUSY;
5169 }
5170
f3f3f27e 5171 entry = tnapi->tx_prod;
5a6f3074 5172 base_flags = 0;
5a6f3074 5173 mss = 0;
c13e3713 5174 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074
MC		 5175 int tcp_opt_len, ip_tcp_len;
5176
5177 if (skb_header_cloned(skb) &&
5178 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5179 dev_kfree_skb(skb);
5180 goto out_unlock;
5181 }
5182
b0026624
MC		 5183 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5184 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5185 else {
eddc9ec5
ACM		 5186 struct iphdr *iph = ip_hdr(skb);
5187
ab6a5bb6 5188 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5189 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5190
eddc9ec5
ACM		 5191 iph->check = 0;
5192 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
b0026624
MC		 5193 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5194 }
5a6f3074
MC		 5195
5196 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5197 TXD_FLAG_CPU_POST_DMA);
5198
aa8223c7 5199 tcp_hdr(skb)->check = 0;
5a6f3074 5200
5a6f3074 5201 }
84fa7933 5202 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5203 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5204#if TG3_VLAN_TAG_USED
5205 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5206 base_flags |= (TXD_FLAG_VLAN |
5207 (vlan_tx_tag_get(skb) << 16));
5208#endif
5209
90079ce8
DM		 5210 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5211 dev_kfree_skb(skb);
5212 goto out_unlock;
5213 }
5214
5215 sp = skb_shinfo(skb);
5216
042a53a9 5217 mapping = sp->dma_head;
5a6f3074 5218
f3f3f27e 5219 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5220
f3f3f27e 5221 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5222 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5223
5224 entry = NEXT_TX(entry);
5225
5226 /* Now loop through additional data fragments, and queue them. */
5227 if (skb_shinfo(skb)->nr_frags > 0) {
5228 unsigned int i, last;
5229
5230 last = skb_shinfo(skb)->nr_frags - 1;
5231 for (i = 0; i <= last; i++) {
5232 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5233
5234 len = frag->size;
042a53a9 5235 mapping = sp->dma_maps[i];
f3f3f27e 5236 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5237
f3f3f27e 5238 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5239 base_flags, (i == last) | (mss << 1));
5240
5241 entry = NEXT_TX(entry);
5242 }
5243 }
5244
5245 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5246 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5247
f3f3f27e
MC		 5248 tnapi->tx_prod = entry;
5249 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5a6f3074 5250 netif_stop_queue(dev);
f3f3f27e 5251 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5a6f3074
MC		 5252 netif_wake_queue(tp->dev);
5253 }
5254
5255out_unlock:
cdd0db05 5256 mmiowb();
5a6f3074
MC		 5257
5258 return NETDEV_TX_OK;
5259}
5260
61357325
SH		 5261static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5262 struct net_device *);
52c0fd83
MC		 5263
5264/* Use GSO to workaround a rare TSO bug that may be triggered when the
5265 * TSO header is greater than 80 bytes.
5266 */
5267static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5268{
5269 struct sk_buff *segs, *nskb;
f3f3f27e 5270 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5271
5272 /* Estimate the number of fragments in the worst case */
f3f3f27e 5273 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5274 netif_stop_queue(tp->dev);
f3f3f27e 5275 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5276 return NETDEV_TX_BUSY;
5277
5278 netif_wake_queue(tp->dev);
52c0fd83
MC		 5279 }
5280
5281 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5282 if (IS_ERR(segs))
52c0fd83
MC		 5283 goto tg3_tso_bug_end;
5284
5285 do {
5286 nskb = segs;
5287 segs = segs->next;
5288 nskb->next = NULL;
5289 tg3_start_xmit_dma_bug(nskb, tp->dev);
5290 } while (segs);
5291
5292tg3_tso_bug_end:
5293 dev_kfree_skb(skb);
5294
5295 return NETDEV_TX_OK;
5296}
52c0fd83 5297
5a6f3074
MC		 5298/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5299 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5300 */
61357325
SH		 5301static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5302 struct net_device *dev)
1da177e4
LT		 5303{
5304 struct tg3 *tp = netdev_priv(dev);
1da177e4 5305 u32 len, entry, base_flags, mss;
90079ce8 5306 struct skb_shared_info *sp;
1da177e4 5307 int would_hit_hwbug;
90079ce8 5308 dma_addr_t mapping;
f3f3f27e 5309 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5310
5311 len = skb_headlen(skb);
5312
00b70504 5313 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5314 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5315 * interrupt. Furthermore, IRQ processing runs lockless so we have
5316 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5317 */
f3f3f27e 5318 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5319 if (!netif_queue_stopped(dev)) {
5320 netif_stop_queue(dev);
5321
5322 /* This is a hard error, log it. */
5323 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5324 "queue awake!\n", dev->name);
5325 }
1da177e4
LT		 5326 return NETDEV_TX_BUSY;
5327 }
5328
f3f3f27e 5329 entry = tnapi->tx_prod;
1da177e4 5330 base_flags = 0;
84fa7933 5331 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5332 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5333 mss = 0;
c13e3713 5334 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5335 struct iphdr *iph;
52c0fd83 5336 int tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5337
5338 if (skb_header_cloned(skb) &&
5339 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5340 dev_kfree_skb(skb);
5341 goto out_unlock;
5342 }
5343
ab6a5bb6 5344 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5345 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5346
52c0fd83
MC		 5347 hdr_len = ip_tcp_len + tcp_opt_len;
5348 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5349 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5350 return (tg3_tso_bug(tp, skb));
5351
1da177e4
LT		 5352 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5353 TXD_FLAG_CPU_POST_DMA);
5354
eddc9ec5
ACM		 5355 iph = ip_hdr(skb);
5356 iph->check = 0;
5357 iph->tot_len = htons(mss + hdr_len);
1da177e4 5358 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5359 tcp_hdr(skb)->check = 0;
1da177e4 5360 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5361 } else
5362 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5363 iph->daddr, 0,
5364 IPPROTO_TCP,
5365 0);
1da177e4
LT		 5366
5367 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5368 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
eddc9ec5 5369 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5370 int tsflags;
5371
eddc9ec5 5372 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5373 mss |= (tsflags << 11);
5374 }
5375 } else {
eddc9ec5 5376 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5377 int tsflags;
5378
eddc9ec5 5379 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5380 base_flags |= tsflags << 12;
5381 }
5382 }
5383 }
1da177e4
LT		 5384#if TG3_VLAN_TAG_USED
5385 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5386 base_flags |= (TXD_FLAG_VLAN |
5387 (vlan_tx_tag_get(skb) << 16));
5388#endif
5389
90079ce8
DM		 5390 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5391 dev_kfree_skb(skb);
5392 goto out_unlock;
5393 }
5394
5395 sp = skb_shinfo(skb);
5396
042a53a9 5397 mapping = sp->dma_head;
1da177e4 5398
f3f3f27e 5399 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5400
5401 would_hit_hwbug = 0;
5402
41588ba1
MC		 5403 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5404 would_hit_hwbug = 1;
5405 else if (tg3_4g_overflow_test(mapping, len))
c58ec932 5406 would_hit_hwbug = 1;
1da177e4 5407
f3f3f27e 5408 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5409 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5410
5411 entry = NEXT_TX(entry);
5412
5413 /* Now loop through additional data fragments, and queue them. */
5414 if (skb_shinfo(skb)->nr_frags > 0) {
5415 unsigned int i, last;
5416
5417 last = skb_shinfo(skb)->nr_frags - 1;
5418 for (i = 0; i <= last; i++) {
5419 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5420
5421 len = frag->size;
042a53a9 5422 mapping = sp->dma_maps[i];
1da177e4 5423
f3f3f27e 5424 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5425
c58ec932
MC		 5426 if (tg3_4g_overflow_test(mapping, len))
5427 would_hit_hwbug = 1;
1da177e4 5428
72f2afb8
MC		 5429 if (tg3_40bit_overflow_test(tp, mapping, len))
5430 would_hit_hwbug = 1;
5431
1da177e4 5432 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5433 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5434 base_flags, (i == last)|(mss << 1));
5435 else
f3f3f27e 5436 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5437 base_flags, (i == last));
5438
5439 entry = NEXT_TX(entry);
5440 }
5441 }
5442
5443 if (would_hit_hwbug) {
5444 u32 last_plus_one = entry;
5445 u32 start;
1da177e4 5446
c58ec932
MC		 5447 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5448 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5449
5450 /* If the workaround fails due to memory/mapping
5451 * failure, silently drop this packet.
5452 */
72f2afb8 5453 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5454 &start, base_flags, mss))
1da177e4
LT		 5455 goto out_unlock;
5456
5457 entry = start;
5458 }
5459
5460 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5461 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5462
f3f3f27e
MC		 5463 tnapi->tx_prod = entry;
5464 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5465 netif_stop_queue(dev);
f3f3f27e 5466 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5467 netif_wake_queue(tp->dev);
5468 }
1da177e4
LT		 5469
5470out_unlock:
cdd0db05 5471 mmiowb();
1da177e4
LT		 5472
5473 return NETDEV_TX_OK;
5474}
5475
5476static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5477 int new_mtu)
5478{
5479 dev->mtu = new_mtu;
5480
ef7f5ec0 5481 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5482 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5483 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5484 ethtool_op_set_tso(dev, 0);
5485 }
5486 else
5487 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5488 } else {
a4e2b347 5489 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5490 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5491 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5492 }
1da177e4
LT		 5493}
5494
5495static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5496{
5497 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5498 int err;
1da177e4
LT		 5499
5500 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5501 return -EINVAL;
5502
5503 if (!netif_running(dev)) {
5504 /* We'll just catch it later when the
5505 * device is up'd.
5506 */
5507 tg3_set_mtu(dev, tp, new_mtu);
5508 return 0;
5509 }
5510
b02fd9e3
MC		 5511 tg3_phy_stop(tp);
5512
1da177e4 5513 tg3_netif_stop(tp);
f47c11ee
DM		 5514
5515 tg3_full_lock(tp, 1);
1da177e4 5516
944d980e 5517 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5518
5519 tg3_set_mtu(dev, tp, new_mtu);
5520
b9ec6c1b 5521 err = tg3_restart_hw(tp, 0);
1da177e4 5522
b9ec6c1b
MC		 5523 if (!err)
5524 tg3_netif_start(tp);
1da177e4 5525
f47c11ee 5526 tg3_full_unlock(tp);
1da177e4 5527
b02fd9e3
MC		 5528 if (!err)
5529 tg3_phy_start(tp);
5530
b9ec6c1b 5531 return err;
1da177e4
LT		 5532}
5533
21f581a5
MC		 5534static void tg3_rx_prodring_free(struct tg3 *tp,
5535 struct tg3_rx_prodring_set *tpr)
1da177e4 5536{
1da177e4 5537 int i;
f3f3f27e 5538 struct ring_info *rxp;
1da177e4
LT		 5539
5540 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5541 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5542
5543 if (rxp->skb == NULL)
5544 continue;
1da177e4 5545
1da177e4
LT		 5546 pci_unmap_single(tp->pdev,
5547 pci_unmap_addr(rxp, mapping),
cf7a7298 5548 tp->rx_pkt_map_sz,
1da177e4
LT		 5549 PCI_DMA_FROMDEVICE);
5550 dev_kfree_skb_any(rxp->skb);
5551 rxp->skb = NULL;
5552 }
5553
cf7a7298
MC		 5554 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5555 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5556 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5557
cf7a7298
MC		 5558 if (rxp->skb == NULL)
5559 continue;
1da177e4 5560
cf7a7298
MC		 5561 pci_unmap_single(tp->pdev,
5562 pci_unmap_addr(rxp, mapping),
5563 TG3_RX_JMB_MAP_SZ,
5564 PCI_DMA_FROMDEVICE);
5565 dev_kfree_skb_any(rxp->skb);
5566 rxp->skb = NULL;
1da177e4 5567 }
1da177e4
LT		 5568 }
5569}
5570
5571/* Initialize tx/rx rings for packet processing.
5572 *
5573 * The chip has been shut down and the driver detached from
5574 * the networking, so no interrupts or new tx packets will
5575 * end up in the driver. tp->{tx,}lock are held and thus
5576 * we may not sleep.
5577 */
21f581a5
MC		 5578static int tg3_rx_prodring_alloc(struct tg3 *tp,
5579 struct tg3_rx_prodring_set *tpr)
1da177e4 5580{
287be12e 5581 u32 i, rx_pkt_dma_sz;
17375d25 5582 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5583
1da177e4 5584 /* Zero out all descriptors. */
21f581a5 5585 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5586
287be12e 5587 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5588 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5589 tp->dev->mtu > ETH_DATA_LEN)
5590 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5591 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5592
1da177e4
LT		 5593 /* Initialize invariants of the rings, we only set this
5594 * stuff once. This works because the card does not
5595 * write into the rx buffer posting rings.
5596 */
5597 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5598 struct tg3_rx_buffer_desc *rxd;
5599
21f581a5 5600 rxd = &tpr->rx_std[i];
287be12e 5601 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5602 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5603 rxd->opaque = (RXD_OPAQUE_RING_STD |
5604 (i << RXD_OPAQUE_INDEX_SHIFT));
5605 }
5606
1da177e4
LT		 5607 /* Now allocate fresh SKBs for each rx ring. */
5608 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5609 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5610 printk(KERN_WARNING PFX
5611 "%s: Using a smaller RX standard ring, "
5612 "only %d out of %d buffers were allocated "
5613 "successfully.\n",
5614 tp->dev->name, i, tp->rx_pending);
5615 if (i == 0)
cf7a7298 5616 goto initfail;
32d8c572 5617 tp->rx_pending = i;
1da177e4 5618 break;
32d8c572 5619 }
1da177e4
LT		 5620 }
5621
cf7a7298
MC		 5622 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5623 goto done;
5624
21f581a5 5625 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5626
0f893dc6 5627 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5628 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5629 struct tg3_rx_buffer_desc *rxd;
5630
79ed5ac7 5631 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5632 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5633 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5634 RXD_FLAG_JUMBO;
5635 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5636 (i << RXD_OPAQUE_INDEX_SHIFT));
5637 }
5638
1da177e4 5639 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5640 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5641 -1, i) < 0) {
5642 printk(KERN_WARNING PFX
5643 "%s: Using a smaller RX jumbo ring, "
5644 "only %d out of %d buffers were "
5645 "allocated successfully.\n",
5646 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5647 if (i == 0)
5648 goto initfail;
32d8c572 5649 tp->rx_jumbo_pending = i;
1da177e4 5650 break;
32d8c572 5651 }
1da177e4
LT		 5652 }
5653 }
cf7a7298
MC		 5654
5655done:
32d8c572 5656 return 0;
cf7a7298
MC		 5657
5658initfail:
21f581a5 5659 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5660 return -ENOMEM;
1da177e4
LT		 5661}
5662
21f581a5
MC		 5663static void tg3_rx_prodring_fini(struct tg3 *tp,
5664 struct tg3_rx_prodring_set *tpr)
1da177e4 5665{
21f581a5
MC		 5666 kfree(tpr->rx_std_buffers);
5667 tpr->rx_std_buffers = NULL;
5668 kfree(tpr->rx_jmb_buffers);
5669 tpr->rx_jmb_buffers = NULL;
5670 if (tpr->rx_std) {
1da177e4 5671 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5672 tpr->rx_std, tpr->rx_std_mapping);
5673 tpr->rx_std = NULL;
1da177e4 5674 }
21f581a5 5675 if (tpr->rx_jmb) {
1da177e4 5676 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5677 tpr->rx_jmb, tpr->rx_jmb_mapping);
5678 tpr->rx_jmb = NULL;
1da177e4 5679 }
cf7a7298
MC		 5680}
5681
21f581a5
MC		 5682static int tg3_rx_prodring_init(struct tg3 *tp,
5683 struct tg3_rx_prodring_set *tpr)
cf7a7298 5684{
21f581a5
MC		 5685 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5686 TG3_RX_RING_SIZE, GFP_KERNEL);
5687 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5688 return -ENOMEM;
5689
21f581a5
MC		 5690 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5691 &tpr->rx_std_mapping);
5692 if (!tpr->rx_std)
cf7a7298
MC		 5693 goto err_out;
5694
5695 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5696 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5697 TG3_RX_JUMBO_RING_SIZE,
5698 GFP_KERNEL);
5699 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5700 goto err_out;
5701
21f581a5
MC		 5702 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5703 TG3_RX_JUMBO_RING_BYTES,
5704 &tpr->rx_jmb_mapping);
5705 if (!tpr->rx_jmb)
cf7a7298
MC		 5706 goto err_out;
5707 }
5708
5709 return 0;
5710
5711err_out:
21f581a5 5712 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5713 return -ENOMEM;
5714}
5715
5716/* Free up pending packets in all rx/tx rings.
5717 *
5718 * The chip has been shut down and the driver detached from
5719 * the networking, so no interrupts or new tx packets will
5720 * end up in the driver. tp->{tx,}lock is not held and we are not
5721 * in an interrupt context and thus may sleep.
5722 */
5723static void tg3_free_rings(struct tg3 *tp)
5724{
f3f3f27e 5725 struct tg3_napi *tnapi = &tp->napi[0];
cf7a7298
MC		 5726 int i;
5727
5728 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5729 struct tx_ring_info *txp;
5730 struct sk_buff *skb;
5731
f3f3f27e 5732 txp = &tnapi->tx_buffers[i];
cf7a7298
MC		 5733 skb = txp->skb;
5734
5735 if (skb == NULL) {
5736 i++;
5737 continue;
5738 }
5739
5740 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5741
5742 txp->skb = NULL;
5743
5744 i += skb_shinfo(skb)->nr_frags + 1;
5745
5746 dev_kfree_skb_any(skb);
5747 }
5748
21f581a5 5749 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5750}
5751
5752/* Initialize tx/rx rings for packet processing.
5753 *
5754 * The chip has been shut down and the driver detached from
5755 * the networking, so no interrupts or new tx packets will
5756 * end up in the driver. tp->{tx,}lock are held and thus
5757 * we may not sleep.
5758 */
5759static int tg3_init_rings(struct tg3 *tp)
5760{
72334482
MC		 5761 struct tg3_napi *tnapi = &tp->napi[0];
5762
cf7a7298
MC		 5763 /* Free up all the SKBs. */
5764 tg3_free_rings(tp);
5765
5766 /* Zero out all descriptors. */
f3f3f27e 5767 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
cf7a7298 5768
72334482
MC		 5769 tnapi->rx_rcb_ptr = 0;
5770 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5771
21f581a5 5772 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5773}
5774
5775/*
5776 * Must not be invoked with interrupt sources disabled and
5777 * the hardware shutdown down.
5778 */
5779static void tg3_free_consistent(struct tg3 *tp)
5780{
898a56f8
MC		 5781 struct tg3_napi *tnapi = &tp->napi[0];
5782
f3f3f27e
MC		 5783 kfree(tnapi->tx_buffers);
5784 tnapi->tx_buffers = NULL;
5785 if (tnapi->tx_ring) {
1da177e4 5786 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
f3f3f27e
MC		 5787 tnapi->tx_ring, tnapi->tx_desc_mapping);
5788 tnapi->tx_ring = NULL;
1da177e4 5789 }
72334482
MC		 5790 if (tnapi->rx_rcb) {
5791 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5792 tnapi->rx_rcb, tnapi->rx_rcb_mapping);
5793 tnapi->rx_rcb = NULL;
5794 }
898a56f8 5795 if (tnapi->hw_status) {
1da177e4 5796 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
898a56f8
MC		 5797 tnapi->hw_status,
5798 tnapi->status_mapping);
5799 tnapi->hw_status = NULL;
1da177e4
LT		 5800 }
5801 if (tp->hw_stats) {
5802 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5803 tp->hw_stats, tp->stats_mapping);
5804 tp->hw_stats = NULL;
5805 }
21f581a5 5806 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5807}
5808
5809/*
5810 * Must not be invoked with interrupt sources disabled and
5811 * the hardware shutdown down. Can sleep.
5812 */
5813static int tg3_alloc_consistent(struct tg3 *tp)
5814{
898a56f8
MC		 5815 struct tg3_napi *tnapi = &tp->napi[0];
5816
21f581a5 5817 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5818 return -ENOMEM;
5819
f3f3f27e
MC		 5820 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5821 TG3_TX_RING_SIZE, GFP_KERNEL);
5822 if (!tnapi->tx_buffers)
1da177e4
LT		 5823 goto err_out;
5824
f3f3f27e
MC		 5825 tnapi->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5826 &tnapi->tx_desc_mapping);
5827 if (!tnapi->tx_ring)
1da177e4
LT		 5828 goto err_out;
5829
898a56f8
MC		 5830 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5831 TG3_HW_STATUS_SIZE,
5832 &tnapi->status_mapping);
5833 if (!tnapi->hw_status)
1da177e4
LT		 5834 goto err_out;
5835
898a56f8
MC		 5836 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5837
72334482
MC		 5838 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5839 TG3_RX_RCB_RING_BYTES(tp),
5840 &tnapi->rx_rcb_mapping);
5841 if (!tnapi->rx_rcb)
5842 goto err_out;
5843
5844 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5845
1da177e4
LT		 5846 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5847 sizeof(struct tg3_hw_stats),
5848 &tp->stats_mapping);
5849 if (!tp->hw_stats)
5850 goto err_out;
5851
1da177e4
LT		 5852 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5853
5854 return 0;
5855
5856err_out:
5857 tg3_free_consistent(tp);
5858 return -ENOMEM;
5859}
5860
5861#define MAX_WAIT_CNT 1000
5862
5863/* To stop a block, clear the enable bit and poll till it
5864 * clears. tp->lock is held.
5865 */
b3b7d6be 5866static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 5867{
5868 unsigned int i;
5869 u32 val;
5870
5871 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5872 switch (ofs) {
5873 case RCVLSC_MODE:
5874 case DMAC_MODE:
5875 case MBFREE_MODE:
5876 case BUFMGR_MODE:
5877 case MEMARB_MODE:
5878 /* We can't enable/disable these bits of the
5879 * 5705/5750, just say success.
5880 */
5881 return 0;
5882
5883 default:
5884 break;
855e1111 5885 }
1da177e4
LT		 5886 }
5887
5888 val = tr32(ofs);
5889 val &= ~enable_bit;
5890 tw32_f(ofs, val);
5891
5892 for (i = 0; i < MAX_WAIT_CNT; i++) {
5893 udelay(100);
5894 val = tr32(ofs);
5895 if ((val & enable_bit) == 0)
5896 break;
5897 }
5898
b3b7d6be 5899 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 5900 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5901 "ofs=%lx enable_bit=%x\n",
5902 ofs, enable_bit);
5903 return -ENODEV;
5904 }
5905
5906 return 0;
5907}
5908
5909/* tp->lock is held. */
b3b7d6be 5910static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 5911{
5912 int i, err;
898a56f8 5913 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5914
5915 tg3_disable_ints(tp);
5916
5917 tp->rx_mode &= ~RX_MODE_ENABLE;
5918 tw32_f(MAC_RX_MODE, tp->rx_mode);
5919 udelay(10);
5920
b3b7d6be
DM		 5921 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5922 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5923 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5924 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5925 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5926 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5927
5928 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5929 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5930 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5931 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5932 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5933 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5934 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 5935
5936 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5937 tw32_f(MAC_MODE, tp->mac_mode);
5938 udelay(40);
5939
5940 tp->tx_mode &= ~TX_MODE_ENABLE;
5941 tw32_f(MAC_TX_MODE, tp->tx_mode);
5942
5943 for (i = 0; i < MAX_WAIT_CNT; i++) {
5944 udelay(100);
5945 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5946 break;
5947 }
5948 if (i >= MAX_WAIT_CNT) {
5949 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5950 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5951 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 5952 err |= -ENODEV;
1da177e4
LT		 5953 }
5954
e6de8ad1 5955 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 5956 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5957 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 5958
5959 tw32(FTQ_RESET, 0xffffffff);
5960 tw32(FTQ_RESET, 0x00000000);
5961
b3b7d6be
DM		 5962 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5963 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 5964
898a56f8
MC		 5965 if (tnapi->hw_status)
5966 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
1da177e4
LT		 5967 if (tp->hw_stats)
5968 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5969
1da177e4
LT		 5970 return err;
5971}
5972
0d3031d9
MC		 5973static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5974{
5975 int i;
5976 u32 apedata;
5977
5978 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5979 if (apedata != APE_SEG_SIG_MAGIC)
5980 return;
5981
5982 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 5983 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 5984 return;
5985
5986 /* Wait for up to 1 millisecond for APE to service previous event. */
5987 for (i = 0; i < 10; i++) {
5988 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5989 return;
5990
5991 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5992
5993 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5994 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5995 event | APE_EVENT_STATUS_EVENT_PENDING);
5996
5997 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5998
5999 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6000 break;
6001
6002 udelay(100);
6003 }
6004
6005 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6006 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6007}
6008
6009static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6010{
6011 u32 event;
6012 u32 apedata;
6013
6014 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6015 return;
6016
6017 switch (kind) {
6018 case RESET_KIND_INIT:
6019 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6020 APE_HOST_SEG_SIG_MAGIC);
6021 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6022 APE_HOST_SEG_LEN_MAGIC);
6023 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6024 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6025 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6026 APE_HOST_DRIVER_ID_MAGIC);
6027 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6028 APE_HOST_BEHAV_NO_PHYLOCK);
6029
6030 event = APE_EVENT_STATUS_STATE_START;
6031 break;
6032 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6033 /* With the interface we are currently using,
6034 * APE does not track driver state. Wiping
6035 * out the HOST SEGMENT SIGNATURE forces
6036 * the APE to assume OS absent status.
6037 */
6038 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6039
0d3031d9
MC		 6040 event = APE_EVENT_STATUS_STATE_UNLOAD;
6041 break;
6042 case RESET_KIND_SUSPEND:
6043 event = APE_EVENT_STATUS_STATE_SUSPEND;
6044 break;
6045 default:
6046 return;
6047 }
6048
6049 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6050
6051 tg3_ape_send_event(tp, event);
6052}
6053
1da177e4
LT		 6054/* tp->lock is held. */
6055static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6056{
f49639e6
DM		 6057 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6058 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6059
6060 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6061 switch (kind) {
6062 case RESET_KIND_INIT:
6063 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6064 DRV_STATE_START);
6065 break;
6066
6067 case RESET_KIND_SHUTDOWN:
6068 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6069 DRV_STATE_UNLOAD);
6070 break;
6071
6072 case RESET_KIND_SUSPEND:
6073 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6074 DRV_STATE_SUSPEND);
6075 break;
6076
6077 default:
6078 break;
855e1111 6079 }
1da177e4 6080 }
0d3031d9
MC		 6081
6082 if (kind == RESET_KIND_INIT ||
6083 kind == RESET_KIND_SUSPEND)
6084 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6085}
6086
6087/* tp->lock is held. */
6088static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6089{
6090 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6091 switch (kind) {
6092 case RESET_KIND_INIT:
6093 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6094 DRV_STATE_START_DONE);
6095 break;
6096
6097 case RESET_KIND_SHUTDOWN:
6098 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6099 DRV_STATE_UNLOAD_DONE);
6100 break;
6101
6102 default:
6103 break;
855e1111 6104 }
1da177e4 6105 }
0d3031d9
MC		 6106
6107 if (kind == RESET_KIND_SHUTDOWN)
6108 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6109}
6110
6111/* tp->lock is held. */
6112static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6113{
6114 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6115 switch (kind) {
6116 case RESET_KIND_INIT:
6117 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6118 DRV_STATE_START);
6119 break;
6120
6121 case RESET_KIND_SHUTDOWN:
6122 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6123 DRV_STATE_UNLOAD);
6124 break;
6125
6126 case RESET_KIND_SUSPEND:
6127 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6128 DRV_STATE_SUSPEND);
6129 break;
6130
6131 default:
6132 break;
855e1111 6133 }
1da177e4
LT		 6134 }
6135}
6136
7a6f4369
MC		 6137static int tg3_poll_fw(struct tg3 *tp)
6138{
6139 int i;
6140 u32 val;
6141
b5d3772c 6142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6143 /* Wait up to 20ms for init done. */
6144 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6145 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6146 return 0;
0ccead18 6147 udelay(100);
b5d3772c
MC		 6148 }
6149 return -ENODEV;
6150 }
6151
7a6f4369
MC		 6152 /* Wait for firmware initialization to complete. */
6153 for (i = 0; i < 100000; i++) {
6154 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6155 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6156 break;
6157 udelay(10);
6158 }
6159
6160 /* Chip might not be fitted with firmware. Some Sun onboard
6161 * parts are configured like that. So don't signal the timeout
6162 * of the above loop as an error, but do report the lack of
6163 * running firmware once.
6164 */
6165 if (i >= 100000 &&
6166 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6167 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6168
6169 printk(KERN_INFO PFX "%s: No firmware running.\n",
6170 tp->dev->name);
6171 }
6172
6173 return 0;
6174}
6175
ee6a99b5
MC		 6176/* Save PCI command register before chip reset */
6177static void tg3_save_pci_state(struct tg3 *tp)
6178{
8a6eac90 6179 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6180}
6181
6182/* Restore PCI state after chip reset */
6183static void tg3_restore_pci_state(struct tg3 *tp)
6184{
6185 u32 val;
6186
6187 /* Re-enable indirect register accesses. */
6188 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6189 tp->misc_host_ctrl);
6190
6191 /* Set MAX PCI retry to zero. */
6192 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6193 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6194 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6195 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6196 /* Allow reads and writes to the APE register and memory space. */
6197 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6198 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6199 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6200 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6201
8a6eac90 6202 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6203
fcb389df
MC		 6204 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6205 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6206 pcie_set_readrq(tp->pdev, 4096);
6207 else {
6208 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6209 tp->pci_cacheline_sz);
6210 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6211 tp->pci_lat_timer);
6212 }
114342f2 6213 }
5f5c51e3 6214
ee6a99b5 6215 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6216 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6217 u16 pcix_cmd;
6218
6219 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6220 &pcix_cmd);
6221 pcix_cmd &= ~PCI_X_CMD_ERO;
6222 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6223 pcix_cmd);
6224 }
ee6a99b5
MC		 6225
6226 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6227
6228 /* Chip reset on 5780 will reset MSI enable bit,
6229 * so need to restore it.
6230 */
6231 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6232 u16 ctrl;
6233
6234 pci_read_config_word(tp->pdev,
6235 tp->msi_cap + PCI_MSI_FLAGS,
6236 &ctrl);
6237 pci_write_config_word(tp->pdev,
6238 tp->msi_cap + PCI_MSI_FLAGS,
6239 ctrl | PCI_MSI_FLAGS_ENABLE);
6240 val = tr32(MSGINT_MODE);
6241 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6242 }
6243 }
6244}
6245
1da177e4
LT		 6246static void tg3_stop_fw(struct tg3 *);
6247
6248/* tp->lock is held. */
6249static int tg3_chip_reset(struct tg3 *tp)
6250{
6251 u32 val;
1ee582d8 6252 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6253 int i, err;
1da177e4 6254
f49639e6
DM		 6255 tg3_nvram_lock(tp);
6256
158d7abd
MC		 6257 tg3_mdio_stop(tp);
6258
77b483f1
MC		 6259 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6260
f49639e6
DM		 6261 /* No matching tg3_nvram_unlock() after this because
6262 * chip reset below will undo the nvram lock.
6263 */
6264 tp->nvram_lock_cnt = 0;
1da177e4 6265
ee6a99b5
MC		 6266 /* GRC_MISC_CFG core clock reset will clear the memory
6267 * enable bit in PCI register 4 and the MSI enable bit
6268 * on some chips, so we save relevant registers here.
6269 */
6270 tg3_save_pci_state(tp);
6271
d9ab5ad1 6272 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6273 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6274 tw32(GRC_FASTBOOT_PC, 0);
6275
1da177e4
LT		 6276 /*
6277 * We must avoid the readl() that normally takes place.
6278 * It locks machines, causes machine checks, and other
6279 * fun things. So, temporarily disable the 5701
6280 * hardware workaround, while we do the reset.
6281 */
1ee582d8
MC		 6282 write_op = tp->write32;
6283 if (write_op == tg3_write_flush_reg32)
6284 tp->write32 = tg3_write32;
1da177e4 6285
d18edcb2
MC		 6286 /* Prevent the irq handler from reading or writing PCI registers
6287 * during chip reset when the memory enable bit in the PCI command
6288 * register may be cleared. The chip does not generate interrupt
6289 * at this time, but the irq handler may still be called due to irq
6290 * sharing or irqpoll.
6291 */
6292 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
898a56f8
MC		 6293 if (tp->napi[0].hw_status) {
6294 tp->napi[0].hw_status->status = 0;
6295 tp->napi[0].hw_status->status_tag = 0;
b8fa2f3a 6296 }
898a56f8
MC		 6297 tp->napi[0].last_tag = 0;
6298 tp->napi[0].last_irq_tag = 0;
d18edcb2 6299 smp_mb();
4f125f42
MC		 6300
6301 for (i = 0; i < tp->irq_cnt; i++)
6302 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6303
255ca311
MC		 6304 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6305 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6306 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6307 }
6308
1da177e4
LT		 6309 /* do the reset */
6310 val = GRC_MISC_CFG_CORECLK_RESET;
6311
6312 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6313 if (tr32(0x7e2c) == 0x60) {
6314 tw32(0x7e2c, 0x20);
6315 }
6316 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6317 tw32(GRC_MISC_CFG, (1 << 29));
6318 val |= (1 << 29);
6319 }
6320 }
6321
b5d3772c
MC		 6322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6323 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6324 tw32(GRC_VCPU_EXT_CTRL,
6325 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6326 }
6327
1da177e4
LT		 6328 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6329 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6330 tw32(GRC_MISC_CFG, val);
6331
1ee582d8
MC		 6332 /* restore 5701 hardware bug workaround write method */
6333 tp->write32 = write_op;
1da177e4
LT		 6334
6335 /* Unfortunately, we have to delay before the PCI read back.
6336 * Some 575X chips even will not respond to a PCI cfg access
6337 * when the reset command is given to the chip.
6338 *
6339 * How do these hardware designers expect things to work
6340 * properly if the PCI write is posted for a long period
6341 * of time? It is always necessary to have some method by
6342 * which a register read back can occur to push the write
6343 * out which does the reset.
6344 *
6345 * For most tg3 variants the trick below was working.
6346 * Ho hum...
6347 */
6348 udelay(120);
6349
6350 /* Flush PCI posted writes. The normal MMIO registers
6351 * are inaccessible at this time so this is the only
6352 * way to make this reliably (actually, this is no longer
6353 * the case, see above). I tried to use indirect
6354 * register read/write but this upset some 5701 variants.
6355 */
6356 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6357
6358 udelay(120);
6359
5e7dfd0f 6360 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6361 u16 val16;
6362
1da177e4
LT		 6363 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6364 int i;
6365 u32 cfg_val;
6366
6367 /* Wait for link training to complete. */
6368 for (i = 0; i < 5000; i++)
6369 udelay(100);
6370
6371 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6372 pci_write_config_dword(tp->pdev, 0xc4,
6373 cfg_val | (1 << 15));
6374 }
5e7dfd0f 6375
e7126997
MC		 6376 /* Clear the "no snoop" and "relaxed ordering" bits. */
6377 pci_read_config_word(tp->pdev,
6378 tp->pcie_cap + PCI_EXP_DEVCTL,
6379 &val16);
6380 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6381 PCI_EXP_DEVCTL_NOSNOOP_EN);
6382 /*
6383 * Older PCIe devices only support the 128 byte
6384 * MPS setting. Enforce the restriction.
5e7dfd0f 6385 */
e7126997
MC		 6386 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6387 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6388 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6389 pci_write_config_word(tp->pdev,
6390 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6391 val16);
5e7dfd0f
MC		 6392
6393 pcie_set_readrq(tp->pdev, 4096);
6394
6395 /* Clear error status */
6396 pci_write_config_word(tp->pdev,
6397 tp->pcie_cap + PCI_EXP_DEVSTA,
6398 PCI_EXP_DEVSTA_CED |
6399 PCI_EXP_DEVSTA_NFED |
6400 PCI_EXP_DEVSTA_FED |
6401 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6402 }
6403
ee6a99b5 6404 tg3_restore_pci_state(tp);
1da177e4 6405
d18edcb2
MC		 6406 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6407
ee6a99b5
MC		 6408 val = 0;
6409 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6410 val = tr32(MEMARB_MODE);
ee6a99b5 6411 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6412
6413 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6414 tg3_stop_fw(tp);
6415 tw32(0x5000, 0x400);
6416 }
6417
6418 tw32(GRC_MODE, tp->grc_mode);
6419
6420 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6421 val = tr32(0xc4);
1da177e4
LT		 6422
6423 tw32(0xc4, val | (1 << 15));
6424 }
6425
6426 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6428 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6429 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6430 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6431 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6432 }
6433
6434 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6435 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6436 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6437 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6438 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6439 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6440 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6441 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6442 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6443 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6444 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6445 } else
6446 tw32_f(MAC_MODE, 0);
6447 udelay(40);
6448
77b483f1
MC		 6449 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6450
7a6f4369
MC		 6451 err = tg3_poll_fw(tp);
6452 if (err)
6453 return err;
1da177e4 6454
0a9140cf
MC		 6455 tg3_mdio_start(tp);
6456
1da177e4
LT		 6457 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6458 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
ab0049b4 6459 val = tr32(0x7c00);
1da177e4
LT		 6460
6461 tw32(0x7c00, val | (1 << 25));
6462 }
6463
6464 /* Reprobe ASF enable state. */
6465 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6466 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6467 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6468 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6469 u32 nic_cfg;
6470
6471 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6472 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6473 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6474 tp->last_event_jiffies = jiffies;
cbf46853 6475 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6476 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6477 }
6478 }
6479
6480 return 0;
6481}
6482
6483/* tp->lock is held. */
6484static void tg3_stop_fw(struct tg3 *tp)
6485{
0d3031d9
MC		 6486 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6487 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6488 /* Wait for RX cpu to ACK the previous event. */
6489 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6490
6491 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6492
6493 tg3_generate_fw_event(tp);
1da177e4 6494
7c5026aa
MC		 6495 /* Wait for RX cpu to ACK this event. */
6496 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6497 }
6498}
6499
6500/* tp->lock is held. */
944d980e 6501static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6502{
6503 int err;
6504
6505 tg3_stop_fw(tp);
6506
944d980e 6507 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6508
b3b7d6be 6509 tg3_abort_hw(tp, silent);
1da177e4
LT		 6510 err = tg3_chip_reset(tp);
6511
daba2a63
MC		 6512 __tg3_set_mac_addr(tp, 0);
6513
944d980e
MC		 6514 tg3_write_sig_legacy(tp, kind);
6515 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6516
6517 if (err)
6518 return err;
6519
6520 return 0;
6521}
6522
1da177e4
LT		 6523#define RX_CPU_SCRATCH_BASE 0x30000
6524#define RX_CPU_SCRATCH_SIZE 0x04000
6525#define TX_CPU_SCRATCH_BASE 0x34000
6526#define TX_CPU_SCRATCH_SIZE 0x04000
6527
6528/* tp->lock is held. */
6529static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6530{
6531 int i;
6532
5d9428de
ES		 6533 BUG_ON(offset == TX_CPU_BASE &&
6534 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6535
b5d3772c
MC		 6536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6537 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6538
6539 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6540 return 0;
6541 }
1da177e4
LT		 6542 if (offset == RX_CPU_BASE) {
6543 for (i = 0; i < 10000; i++) {
6544 tw32(offset + CPU_STATE, 0xffffffff);
6545 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6546 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6547 break;
6548 }
6549
6550 tw32(offset + CPU_STATE, 0xffffffff);
6551 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6552 udelay(10);
6553 } else {
6554 for (i = 0; i < 10000; i++) {
6555 tw32(offset + CPU_STATE, 0xffffffff);
6556 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6557 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6558 break;
6559 }
6560 }
6561
6562 if (i >= 10000) {
6563 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6564 "and %s CPU\n",
6565 tp->dev->name,
6566 (offset == RX_CPU_BASE ? "RX" : "TX"));
6567 return -ENODEV;
6568 }
ec41c7df
MC		 6569
6570 /* Clear firmware's nvram arbitration. */
6571 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6572 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6573 return 0;
6574}
6575
6576struct fw_info {
077f849d
JSR		 6577 unsigned int fw_base;
6578 unsigned int fw_len;
6579 const __be32 *fw_data;
1da177e4
LT		 6580};
6581
6582/* tp->lock is held. */
6583static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6584 int cpu_scratch_size, struct fw_info *info)
6585{
ec41c7df 6586 int err, lock_err, i;
1da177e4
LT		 6587 void (*write_op)(struct tg3 *, u32, u32);
6588
6589 if (cpu_base == TX_CPU_BASE &&
6590 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6591 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6592 "TX cpu firmware on %s which is 5705.\n",
6593 tp->dev->name);
6594 return -EINVAL;
6595 }
6596
6597 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6598 write_op = tg3_write_mem;
6599 else
6600 write_op = tg3_write_indirect_reg32;
6601
1b628151
MC		 6602 /* It is possible that bootcode is still loading at this point.
6603 * Get the nvram lock first before halting the cpu.
6604 */
ec41c7df 6605 lock_err = tg3_nvram_lock(tp);
1da177e4 6606 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6607 if (!lock_err)
6608 tg3_nvram_unlock(tp);
1da177e4
LT		 6609 if (err)
6610 goto out;
6611
6612 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6613 write_op(tp, cpu_scratch_base + i, 0);
6614 tw32(cpu_base + CPU_STATE, 0xffffffff);
6615 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6616 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6617 write_op(tp, (cpu_scratch_base +
077f849d 6618 (info->fw_base & 0xffff) +
1da177e4 6619 (i * sizeof(u32))),
077f849d 6620 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6621
6622 err = 0;
6623
6624out:
1da177e4
LT		 6625 return err;
6626}
6627
6628/* tp->lock is held. */
6629static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6630{
6631 struct fw_info info;
077f849d 6632 const __be32 *fw_data;
1da177e4
LT		 6633 int err, i;
6634
077f849d
JSR		 6635 fw_data = (void *)tp->fw->data;
6636
6637 /* Firmware blob starts with version numbers, followed by
6638 start address and length. We are setting complete length.
6639 length = end_address_of_bss - start_address_of_text.
6640 Remainder is the blob to be loaded contiguously
6641 from start address. */
6642
6643 info.fw_base = be32_to_cpu(fw_data[1]);
6644 info.fw_len = tp->fw->size - 12;
6645 info.fw_data = &fw_data[3];
1da177e4
LT		 6646
6647 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6648 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6649 &info);
6650 if (err)
6651 return err;
6652
6653 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6654 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6655 &info);
6656 if (err)
6657 return err;
6658
6659 /* Now startup only the RX cpu. */
6660 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6661 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6662
6663 for (i = 0; i < 5; i++) {
077f849d 6664 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6665 break;
6666 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6667 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6668 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6669 udelay(1000);
6670 }
6671 if (i >= 5) {
6672 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6673 "to set RX CPU PC, is %08x should be %08x\n",
6674 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6675 info.fw_base);
1da177e4
LT		 6676 return -ENODEV;
6677 }
6678 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6679 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6680
6681 return 0;
6682}
6683
1da177e4 6684/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6685
6686/* tp->lock is held. */
6687static int tg3_load_tso_firmware(struct tg3 *tp)
6688{
6689 struct fw_info info;
077f849d 6690 const __be32 *fw_data;
1da177e4
LT		 6691 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6692 int err, i;
6693
6694 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6695 return 0;
6696
077f849d
JSR		 6697 fw_data = (void *)tp->fw->data;
6698
6699 /* Firmware blob starts with version numbers, followed by
6700 start address and length. We are setting complete length.
6701 length = end_address_of_bss - start_address_of_text.
6702 Remainder is the blob to be loaded contiguously
6703 from start address. */
6704
6705 info.fw_base = be32_to_cpu(fw_data[1]);
6706 cpu_scratch_size = tp->fw_len;
6707 info.fw_len = tp->fw->size - 12;
6708 info.fw_data = &fw_data[3];
6709
1da177e4 6710 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6711 cpu_base = RX_CPU_BASE;
6712 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6713 } else {
1da177e4
LT		 6714 cpu_base = TX_CPU_BASE;
6715 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6716 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6717 }
6718
6719 err = tg3_load_firmware_cpu(tp, cpu_base,
6720 cpu_scratch_base, cpu_scratch_size,
6721 &info);
6722 if (err)
6723 return err;
6724
6725 /* Now startup the cpu. */
6726 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6727 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6728
6729 for (i = 0; i < 5; i++) {
077f849d 6730 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6731 break;
6732 tw32(cpu_base + CPU_STATE, 0xffffffff);
6733 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6734 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6735 udelay(1000);
6736 }
6737 if (i >= 5) {
6738 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6739 "to set CPU PC, is %08x should be %08x\n",
6740 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6741 info.fw_base);
1da177e4
LT		 6742 return -ENODEV;
6743 }
6744 tw32(cpu_base + CPU_STATE, 0xffffffff);
6745 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6746 return 0;
6747}
6748
1da177e4 6749
1da177e4
LT		 6750static int tg3_set_mac_addr(struct net_device *dev, void *p)
6751{
6752 struct tg3 *tp = netdev_priv(dev);
6753 struct sockaddr *addr = p;
986e0aeb 6754 int err = 0, skip_mac_1 = 0;
1da177e4 6755
f9804ddb
MC		 6756 if (!is_valid_ether_addr(addr->sa_data))
6757 return -EINVAL;
6758
1da177e4
LT		 6759 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6760
e75f7c90
MC		 6761 if (!netif_running(dev))
6762 return 0;
6763
58712ef9 6764 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6765 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6766
986e0aeb
MC		 6767 addr0_high = tr32(MAC_ADDR_0_HIGH);
6768 addr0_low = tr32(MAC_ADDR_0_LOW);
6769 addr1_high = tr32(MAC_ADDR_1_HIGH);
6770 addr1_low = tr32(MAC_ADDR_1_LOW);
6771
6772 /* Skip MAC addr 1 if ASF is using it. */
6773 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6774 !(addr1_high == 0 && addr1_low == 0))
6775 skip_mac_1 = 1;
58712ef9 6776 }
986e0aeb
MC		 6777 spin_lock_bh(&tp->lock);
6778 __tg3_set_mac_addr(tp, skip_mac_1);
6779 spin_unlock_bh(&tp->lock);
1da177e4 6780
b9ec6c1b 6781 return err;
1da177e4
LT		 6782}
6783
6784/* tp->lock is held. */
6785static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6786 dma_addr_t mapping, u32 maxlen_flags,
6787 u32 nic_addr)
6788{
6789 tg3_write_mem(tp,
6790 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6791 ((u64) mapping >> 32));
6792 tg3_write_mem(tp,
6793 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6794 ((u64) mapping & 0xffffffff));
6795 tg3_write_mem(tp,
6796 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6797 maxlen_flags);
6798
6799 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6800 tg3_write_mem(tp,
6801 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6802 nic_addr);
6803}
6804
6805static void __tg3_set_rx_mode(struct net_device *);
d244c892 6806static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 6807{
6808 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6809 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6810 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6811 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6812 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6813 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6814 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6815 }
6816 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6817 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6818 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6819 u32 val = ec->stats_block_coalesce_usecs;
6820
6821 if (!netif_carrier_ok(tp->dev))
6822 val = 0;
6823
6824 tw32(HOSTCC_STAT_COAL_TICKS, val);
6825 }
6826}
1da177e4 6827
2d31ecaf
MC		 6828/* tp->lock is held. */
6829static void tg3_rings_reset(struct tg3 *tp)
6830{
6831 int i;
6832 u32 txrcb, rxrcb, limit;
6833 struct tg3_napi *tnapi = &tp->napi[0];
6834
6835 /* Disable all transmit rings but the first. */
6836 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6837 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
6838 else
6839 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6840
6841 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
6842 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
6843 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
6844 BDINFO_FLAGS_DISABLED);
6845
6846
6847 /* Disable all receive return rings but the first. */
6848 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6849 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
6850 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6851 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
6852 else
6853 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6854
6855 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
6856 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
6857 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
6858 BDINFO_FLAGS_DISABLED);
6859
6860 /* Disable interrupts */
6861 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
6862
6863 /* Zero mailbox registers. */
6864 tp->napi[0].tx_prod = 0;
6865 tp->napi[0].tx_cons = 0;
6866 tw32_mailbox(tp->napi[0].prodmbox, 0);
6867 tw32_rx_mbox(tp->napi[0].consmbox, 0);
6868
6869 /* Make sure the NIC-based send BD rings are disabled. */
6870 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6871 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6872 for (i = 0; i < 16; i++)
6873 tw32_tx_mbox(mbox + i * 8, 0);
6874 }
6875
6876 txrcb = NIC_SRAM_SEND_RCB;
6877 rxrcb = NIC_SRAM_RCV_RET_RCB;
6878
6879 /* Clear status block in ram. */
6880 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6881
6882 /* Set status block DMA address */
6883 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6884 ((u64) tnapi->status_mapping >> 32));
6885 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6886 ((u64) tnapi->status_mapping & 0xffffffff));
6887
6888 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
6889 (TG3_TX_RING_SIZE <<
6890 BDINFO_FLAGS_MAXLEN_SHIFT),
6891 NIC_SRAM_TX_BUFFER_DESC);
6892
6893 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
6894 (TG3_RX_RCB_RING_SIZE(tp) <<
6895 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
6896}
6897
1da177e4 6898/* tp->lock is held. */
8e7a22e3 6899static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 6900{
6901 u32 val, rdmac_mode;
6902 int i, err, limit;
21f581a5 6903 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 6904
6905 tg3_disable_ints(tp);
6906
6907 tg3_stop_fw(tp);
6908
6909 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6910
6911 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 6912 tg3_abort_hw(tp, 1);
1da177e4
LT		 6913 }
6914
dd477003
MC		 6915 if (reset_phy &&
6916 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 6917 tg3_phy_reset(tp);
6918
1da177e4
LT		 6919 err = tg3_chip_reset(tp);
6920 if (err)
6921 return err;
6922
6923 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6924
bcb37f6c 6925 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 6926 val = tr32(TG3_CPMU_CTRL);
6927 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6928 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 6929
6930 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6931 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6932 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6933 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6934
6935 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6936 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6937 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6938 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6939
6940 val = tr32(TG3_CPMU_HST_ACC);
6941 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6942 val |= CPMU_HST_ACC_MACCLK_6_25;
6943 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 6944 }
6945
33466d93
MC		 6946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6947 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6948 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6949 PCIE_PWR_MGMT_L1_THRESH_4MS;
6950 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 6951
6952 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6953 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6954
6955 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93
MC		 6956 }
6957
255ca311
MC		 6958 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6959 val = tr32(TG3_PCIE_LNKCTL);
6960 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6961 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6962 else
6963 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6964 tw32(TG3_PCIE_LNKCTL, val);
6965 }
6966
1da177e4
LT		 6967 /* This works around an issue with Athlon chipsets on
6968 * B3 tigon3 silicon. This bit has no effect on any
6969 * other revision. But do not set this on PCI Express
795d01c5 6970 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 6971 */
795d01c5
MC		 6972 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6973 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6974 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6975 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6976 }
1da177e4
LT		 6977
6978 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6979 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6980 val = tr32(TG3PCI_PCISTATE);
6981 val |= PCISTATE_RETRY_SAME_DMA;
6982 tw32(TG3PCI_PCISTATE, val);
6983 }
6984
0d3031d9
MC		 6985 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6986 /* Allow reads and writes to the
6987 * APE register and memory space.
6988 */
6989 val = tr32(TG3PCI_PCISTATE);
6990 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6991 PCISTATE_ALLOW_APE_SHMEM_WR;
6992 tw32(TG3PCI_PCISTATE, val);
6993 }
6994
1da177e4
LT		 6995 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6996 /* Enable some hw fixes. */
6997 val = tr32(TG3PCI_MSI_DATA);
6998 val |= (1 << 26) | (1 << 28) | (1 << 29);
6999 tw32(TG3PCI_MSI_DATA, val);
7000 }
7001
7002 /* Descriptor ring init may make accesses to the
7003 * NIC SRAM area to setup the TX descriptors, so we
7004 * can only do this after the hardware has been
7005 * successfully reset.
7006 */
32d8c572
MC		 7007 err = tg3_init_rings(tp);
7008 if (err)
7009 return err;
1da177e4 7010
9936bcf6 7011 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
fcb389df 7012 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7013 /* This value is determined during the probe time DMA
7014 * engine test, tg3_test_dma.
7015 */
7016 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7017 }
1da177e4
LT		 7018
7019 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7020 GRC_MODE_4X_NIC_SEND_RINGS |
7021 GRC_MODE_NO_TX_PHDR_CSUM |
7022 GRC_MODE_NO_RX_PHDR_CSUM);
7023 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7024
7025 /* Pseudo-header checksum is done by hardware logic and not
7026 * the offload processers, so make the chip do the pseudo-
7027 * header checksums on receive. For transmit it is more
7028 * convenient to do the pseudo-header checksum in software
7029 * as Linux does that on transmit for us in all cases.
7030 */
7031 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7032
7033 tw32(GRC_MODE,
7034 tp->grc_mode |
7035 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7036
7037 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7038 val = tr32(GRC_MISC_CFG);
7039 val &= ~0xff;
7040 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7041 tw32(GRC_MISC_CFG, val);
7042
7043 /* Initialize MBUF/DESC pool. */
cbf46853 7044 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7045 /* Do nothing. */
7046 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7047 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7049 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7050 else
7051 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7052 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7053 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7054 }
1da177e4
LT		 7055 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7056 int fw_len;
7057
077f849d 7058 fw_len = tp->fw_len;
1da177e4
LT		 7059 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7060 tw32(BUFMGR_MB_POOL_ADDR,
7061 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7062 tw32(BUFMGR_MB_POOL_SIZE,
7063 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7064 }
1da177e4 7065
0f893dc6 7066 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7067 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7068 tp->bufmgr_config.mbuf_read_dma_low_water);
7069 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7070 tp->bufmgr_config.mbuf_mac_rx_low_water);
7071 tw32(BUFMGR_MB_HIGH_WATER,
7072 tp->bufmgr_config.mbuf_high_water);
7073 } else {
7074 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7075 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7076 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7077 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7078 tw32(BUFMGR_MB_HIGH_WATER,
7079 tp->bufmgr_config.mbuf_high_water_jumbo);
7080 }
7081 tw32(BUFMGR_DMA_LOW_WATER,
7082 tp->bufmgr_config.dma_low_water);
7083 tw32(BUFMGR_DMA_HIGH_WATER,
7084 tp->bufmgr_config.dma_high_water);
7085
7086 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7087 for (i = 0; i < 2000; i++) {
7088 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7089 break;
7090 udelay(10);
7091 }
7092 if (i >= 2000) {
7093 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7094 tp->dev->name);
7095 return -ENODEV;
7096 }
7097
7098 /* Setup replenish threshold. */
f92905de
MC		 7099 val = tp->rx_pending / 8;
7100 if (val == 0)
7101 val = 1;
7102 else if (val > tp->rx_std_max_post)
7103 val = tp->rx_std_max_post;
b5d3772c
MC		 7104 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7105 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7106 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7107
7108 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7109 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7110 }
f92905de
MC		 7111
7112 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7113
7114 /* Initialize TG3_BDINFO's at:
7115 * RCVDBDI_STD_BD: standard eth size rx ring
7116 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7117 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7118 *
7119 * like so:
7120 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7121 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7122 * ring attribute flags
7123 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7124 *
7125 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7126 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7127 *
7128 * The size of each ring is fixed in the firmware, but the location is
7129 * configurable.
7130 */
7131 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7132 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7133 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7134 ((u64) tpr->rx_std_mapping & 0xffffffff));
1da177e4
LT		 7135 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7136 NIC_SRAM_RX_BUFFER_DESC);
7137
fdb72b38
MC		 7138 /* Disable the mini ring */
7139 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7140 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7141 BDINFO_FLAGS_DISABLED);
7142
fdb72b38
MC		 7143 /* Program the jumbo buffer descriptor ring control
7144 * blocks on those devices that have them.
7145 */
8f666b07 7146 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7147 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7148 /* Setup replenish threshold. */
7149 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7150
0f893dc6 7151 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7152 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7153 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7154 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7155 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7156 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7157 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7158 BDINFO_FLAGS_USE_EXT_RECV);
1da177e4
LT		 7159 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7160 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7161 } else {
7162 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7163 BDINFO_FLAGS_DISABLED);
7164 }
7165
fdb72b38
MC		 7166 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7167 } else
7168 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7169
7170 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7171
21f581a5 7172 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7173 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7174 tpr->rx_std_ptr);
1da177e4 7175
21f581a5
MC		 7176 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7177 tp->rx_jumbo_pending : 0;
1da177e4 7178 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7179 tpr->rx_jmb_ptr);
1da177e4 7180
2d31ecaf
MC		 7181 tg3_rings_reset(tp);
7182
1da177e4 7183 /* Initialize MAC address and backoff seed. */
986e0aeb 7184 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7185
7186 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7187 tw32(MAC_RX_MTU_SIZE,
7188 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7189
7190 /* The slot time is changed by tg3_setup_phy if we
7191 * run at gigabit with half duplex.
7192 */
7193 tw32(MAC_TX_LENGTHS,
7194 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7195 (6 << TX_LENGTHS_IPG_SHIFT) |
7196 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7197
7198 /* Receive rules. */
7199 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7200 tw32(RCVLPC_CONFIG, 0x0181);
7201
7202 /* Calculate RDMAC_MODE setting early, we need it to determine
7203 * the RCVLPC_STATE_ENABLE mask.
7204 */
7205 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7206 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7207 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7208 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7209 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7210
57e6983c 7211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7213 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7214 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7215 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7216 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7217
85e94ced
MC		 7218 /* If statement applies to 5705 and 5750 PCI devices only */
7219 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7220 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7221 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7222 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7223 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7224 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7225 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7226 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7227 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7228 }
7229 }
7230
85e94ced
MC		 7231 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7232 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7233
1da177e4 7234 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7235 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7236
7237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7239 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7240
7241 /* Receive/send statistics. */
1661394e
MC		 7242 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7243 val = tr32(RCVLPC_STATS_ENABLE);
7244 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7245 tw32(RCVLPC_STATS_ENABLE, val);
7246 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7247 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7248 val = tr32(RCVLPC_STATS_ENABLE);
7249 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7250 tw32(RCVLPC_STATS_ENABLE, val);
7251 } else {
7252 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7253 }
7254 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7255 tw32(SNDDATAI_STATSENAB, 0xffffff);
7256 tw32(SNDDATAI_STATSCTRL,
7257 (SNDDATAI_SCTRL_ENABLE |
7258 SNDDATAI_SCTRL_FASTUPD));
7259
7260 /* Setup host coalescing engine. */
7261 tw32(HOSTCC_MODE, 0);
7262 for (i = 0; i < 2000; i++) {
7263 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7264 break;
7265 udelay(10);
7266 }
7267
d244c892 7268 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7269
1da177e4
LT		 7270 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7271 /* Status/statistics block address. See tg3_timer,
7272 * the tg3_periodic_fetch_stats call there, and
7273 * tg3_get_stats to see how this works for 5705/5750 chips.
7274 */
1da177e4
LT		 7275 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7276 ((u64) tp->stats_mapping >> 32));
7277 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7278 ((u64) tp->stats_mapping & 0xffffffff));
7279 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7280
1da177e4 7281 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7282
7283 /* Clear statistics and status block memory areas */
7284 for (i = NIC_SRAM_STATS_BLK;
7285 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7286 i += sizeof(u32)) {
7287 tg3_write_mem(tp, i, 0);
7288 udelay(40);
7289 }
1da177e4
LT		 7290 }
7291
7292 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7293
7294 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7295 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7296 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7297 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7298
c94e3941
MC		 7299 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7300 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7301 /* reset to prevent losing 1st rx packet intermittently */
7302 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7303 udelay(10);
7304 }
7305
3bda1258
MC		 7306 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7307 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7308 else
7309 tp->mac_mode = 0;
7310 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7311 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7312 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7313 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7314 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7315 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7316 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7317 udelay(40);
7318
314fba34 7319 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7320 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7321 * register to preserve the GPIO settings for LOMs. The GPIOs,
7322 * whether used as inputs or outputs, are set by boot code after
7323 * reset.
7324 */
9d26e213 7325 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7326 u32 gpio_mask;
7327
9d26e213
MC		 7328 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7329 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7330 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7331
7332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7333 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7334 GRC_LCLCTRL_GPIO_OUTPUT3;
7335
af36e6b6
MC		 7336 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7337 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7338
aaf84465 7339 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7340 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7341
7342 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7343 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7344 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7345 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7346 }
1da177e4
LT		 7347 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7348 udelay(100);
7349
1da177e4
LT		 7350 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7351 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7352 udelay(40);
7353 }
7354
7355 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7356 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7357 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7358 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7359 WDMAC_MODE_LNGREAD_ENAB);
7360
85e94ced
MC		 7361 /* If statement applies to 5705 and 5750 PCI devices only */
7362 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7363 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7365 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7366 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7367 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7368 /* nothing */
7369 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7370 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7371 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7372 val |= WDMAC_MODE_RX_ACCEL;
7373 }
7374 }
7375
d9ab5ad1 7376 /* Enable host coalescing bug fix */
321d32a0 7377 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7378 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7379
1da177e4
LT		 7380 tw32_f(WDMAC_MODE, val);
7381 udelay(40);
7382
9974a356
MC		 7383 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7384 u16 pcix_cmd;
7385
7386 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7387 &pcix_cmd);
1da177e4 7388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7389 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7390 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7391 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7392 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7393 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7394 }
9974a356
MC		 7395 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7396 pcix_cmd);
1da177e4
LT		 7397 }
7398
7399 tw32_f(RDMAC_MODE, rdmac_mode);
7400 udelay(40);
7401
7402 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7403 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7404 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7405
7406 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7407 tw32(SNDDATAC_MODE,
7408 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7409 else
7410 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7411
1da177e4
LT		 7412 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7413 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7414 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7415 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7416 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7417 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
1da177e4
LT		 7418 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7419 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7420
7421 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7422 err = tg3_load_5701_a0_firmware_fix(tp);
7423 if (err)
7424 return err;
7425 }
7426
1da177e4
LT		 7427 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7428 err = tg3_load_tso_firmware(tp);
7429 if (err)
7430 return err;
7431 }
1da177e4
LT		 7432
7433 tp->tx_mode = TX_MODE_ENABLE;
7434 tw32_f(MAC_TX_MODE, tp->tx_mode);
7435 udelay(100);
7436
7437 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7438 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7439 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7440
1da177e4
LT		 7441 tw32_f(MAC_RX_MODE, tp->rx_mode);
7442 udelay(10);
7443
1da177e4
LT		 7444 tw32(MAC_LED_CTRL, tp->led_ctrl);
7445
7446 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7447 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7448 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7449 udelay(10);
7450 }
7451 tw32_f(MAC_RX_MODE, tp->rx_mode);
7452 udelay(10);
7453
7454 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7455 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7456 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7457 /* Set drive transmission level to 1.2V */
7458 /* only if the signal pre-emphasis bit is not set */
7459 val = tr32(MAC_SERDES_CFG);
7460 val &= 0xfffff000;
7461 val |= 0x880;
7462 tw32(MAC_SERDES_CFG, val);
7463 }
7464 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7465 tw32(MAC_SERDES_CFG, 0x616000);
7466 }
7467
7468 /* Prevent chip from dropping frames when flow control
7469 * is enabled.
7470 */
7471 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7472
7473 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7474 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7475 /* Use hardware link auto-negotiation */
7476 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7477 }
7478
d4d2c558
MC		 7479 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7480 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7481 u32 tmp;
7482
7483 tmp = tr32(SERDES_RX_CTRL);
7484 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7485 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7486 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7487 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7488 }
7489
dd477003
MC		 7490 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7491 if (tp->link_config.phy_is_low_power) {
7492 tp->link_config.phy_is_low_power = 0;
7493 tp->link_config.speed = tp->link_config.orig_speed;
7494 tp->link_config.duplex = tp->link_config.orig_duplex;
7495 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7496 }
1da177e4 7497
dd477003
MC		 7498 err = tg3_setup_phy(tp, 0);
7499 if (err)
7500 return err;
1da177e4 7501
dd477003 7502 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7503 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7504 u32 tmp;
7505
7506 /* Clear CRC stats. */
7507 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7508 tg3_writephy(tp, MII_TG3_TEST1,
7509 tmp | MII_TG3_TEST1_CRC_EN);
7510 tg3_readphy(tp, 0x14, &tmp);
7511 }
1da177e4
LT		 7512 }
7513 }
7514
7515 __tg3_set_rx_mode(tp->dev);
7516
7517 /* Initialize receive rules. */
7518 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7519 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7520 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7521 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7522
4cf78e4f 7523 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7524 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7525 limit = 8;
7526 else
7527 limit = 16;
7528 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7529 limit -= 4;
7530 switch (limit) {
7531 case 16:
7532 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7533 case 15:
7534 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7535 case 14:
7536 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7537 case 13:
7538 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7539 case 12:
7540 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7541 case 11:
7542 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7543 case 10:
7544 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7545 case 9:
7546 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7547 case 8:
7548 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7549 case 7:
7550 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7551 case 6:
7552 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7553 case 5:
7554 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7555 case 4:
7556 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7557 case 3:
7558 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7559 case 2:
7560 case 1:
7561
7562 default:
7563 break;
855e1111 7564 }
1da177e4 7565
9ce768ea
MC		 7566 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7567 /* Write our heartbeat update interval to APE. */
7568 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7569 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7570
1da177e4
LT		 7571 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7572
1da177e4
LT		 7573 return 0;
7574}
7575
7576/* Called at device open time to get the chip ready for
7577 * packet processing. Invoked with tp->lock held.
7578 */
8e7a22e3 7579static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7580{
1da177e4
LT		 7581 tg3_switch_clocks(tp);
7582
7583 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7584
2f751b67 7585 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7586}
7587
7588#define TG3_STAT_ADD32(PSTAT, REG) \
7589do { u32 __val = tr32(REG); \
7590 (PSTAT)->low += __val; \
7591 if ((PSTAT)->low < __val) \
7592 (PSTAT)->high += 1; \
7593} while (0)
7594
7595static void tg3_periodic_fetch_stats(struct tg3 *tp)
7596{
7597 struct tg3_hw_stats *sp = tp->hw_stats;
7598
7599 if (!netif_carrier_ok(tp->dev))
7600 return;
7601
7602 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7603 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7604 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7605 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7606 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7607 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7608 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7609 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7610 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7611 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7612 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7613 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7614 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7615
7616 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7617 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7618 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7619 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7620 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7621 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7622 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7623 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7624 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7625 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7626 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7627 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7628 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7629 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7630
7631 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7632 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7633 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7634}
7635
7636static void tg3_timer(unsigned long __opaque)
7637{
7638 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7639
f475f163
MC		 7640 if (tp->irq_sync)
7641 goto restart_timer;
7642
f47c11ee 7643 spin_lock(&tp->lock);
1da177e4 7644
fac9b83e
DM		 7645 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7646 /* All of this garbage is because when using non-tagged
7647 * IRQ status the mailbox/status_block protocol the chip
7648 * uses with the cpu is race prone.
7649 */
898a56f8 7650 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7651 tw32(GRC_LOCAL_CTRL,
7652 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7653 } else {
7654 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7655 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7656 }
1da177e4 7657
fac9b83e
DM		 7658 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7659 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7660 spin_unlock(&tp->lock);
fac9b83e
DM		 7661 schedule_work(&tp->reset_task);
7662 return;
7663 }
1da177e4
LT		 7664 }
7665
1da177e4
LT		 7666 /* This part only runs once per second. */
7667 if (!--tp->timer_counter) {
fac9b83e
DM		 7668 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7669 tg3_periodic_fetch_stats(tp);
7670
1da177e4
LT		 7671 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7672 u32 mac_stat;
7673 int phy_event;
7674
7675 mac_stat = tr32(MAC_STATUS);
7676
7677 phy_event = 0;
7678 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7679 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7680 phy_event = 1;
7681 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7682 phy_event = 1;
7683
7684 if (phy_event)
7685 tg3_setup_phy(tp, 0);
7686 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7687 u32 mac_stat = tr32(MAC_STATUS);
7688 int need_setup = 0;
7689
7690 if (netif_carrier_ok(tp->dev) &&
7691 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7692 need_setup = 1;
7693 }
7694 if (! netif_carrier_ok(tp->dev) &&
7695 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7696 MAC_STATUS_SIGNAL_DET))) {
7697 need_setup = 1;
7698 }
7699 if (need_setup) {
3d3ebe74
MC		 7700 if (!tp->serdes_counter) {
7701 tw32_f(MAC_MODE,
7702 (tp->mac_mode &
7703 ~MAC_MODE_PORT_MODE_MASK));
7704 udelay(40);
7705 tw32_f(MAC_MODE, tp->mac_mode);
7706 udelay(40);
7707 }
1da177e4
LT		 7708 tg3_setup_phy(tp, 0);
7709 }
747e8f8b
MC		 7710 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7711 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 7712
7713 tp->timer_counter = tp->timer_multiplier;
7714 }
7715
130b8e4d
MC		 7716 /* Heartbeat is only sent once every 2 seconds.
7717 *
7718 * The heartbeat is to tell the ASF firmware that the host
7719 * driver is still alive. In the event that the OS crashes,
7720 * ASF needs to reset the hardware to free up the FIFO space
7721 * that may be filled with rx packets destined for the host.
7722 * If the FIFO is full, ASF will no longer function properly.
7723 *
7724 * Unintended resets have been reported on real time kernels
7725 * where the timer doesn't run on time. Netpoll will also have
7726 * same problem.
7727 *
7728 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7729 * to check the ring condition when the heartbeat is expiring
7730 * before doing the reset. This will prevent most unintended
7731 * resets.
7732 */
1da177e4 7733 if (!--tp->asf_counter) {
bc7959b2
MC		 7734 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7735 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7736 tg3_wait_for_event_ack(tp);
7737
bbadf503 7738 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 7739 FWCMD_NICDRV_ALIVE3);
bbadf503 7740 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 7741 /* 5 seconds timeout */
bbadf503 7742 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 7743
7744 tg3_generate_fw_event(tp);
1da177e4
LT		 7745 }
7746 tp->asf_counter = tp->asf_multiplier;
7747 }
7748
f47c11ee 7749 spin_unlock(&tp->lock);
1da177e4 7750
f475f163 7751restart_timer:
1da177e4
LT		 7752 tp->timer.expires = jiffies + tp->timer_offset;
7753 add_timer(&tp->timer);
7754}
7755
4f125f42 7756static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 7757{
7d12e780 7758 irq_handler_t fn;
fcfa0a32 7759 unsigned long flags;
4f125f42
MC		 7760 char *name;
7761 struct tg3_napi *tnapi = &tp->napi[irq_num];
7762
7763 if (tp->irq_cnt == 1)
7764 name = tp->dev->name;
7765 else {
7766 name = &tnapi->irq_lbl[0];
7767 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
7768 name[IFNAMSIZ-1] = 0;
7769 }
fcfa0a32 7770
679563f4 7771 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 7772 fn = tg3_msi;
7773 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7774 fn = tg3_msi_1shot;
1fb9df5d 7775 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 7776 } else {
7777 fn = tg3_interrupt;
7778 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7779 fn = tg3_interrupt_tagged;
1fb9df5d 7780 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 7781 }
4f125f42
MC		 7782
7783 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 7784}
7785
7938109f
MC		 7786static int tg3_test_interrupt(struct tg3 *tp)
7787{
09943a18 7788 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 7789 struct net_device *dev = tp->dev;
b16250e3 7790 int err, i, intr_ok = 0;
7938109f 7791
d4bc3927
MC		 7792 if (!netif_running(dev))
7793 return -ENODEV;
7794
7938109f
MC		 7795 tg3_disable_ints(tp);
7796
4f125f42 7797 free_irq(tnapi->irq_vec, tnapi);
7938109f 7798
4f125f42 7799 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 7800 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 7801 if (err)
7802 return err;
7803
898a56f8 7804 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 7805 tg3_enable_ints(tp);
7806
7807 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 7808 tnapi->coal_now);
7938109f
MC		 7809
7810 for (i = 0; i < 5; i++) {
b16250e3
MC		 7811 u32 int_mbox, misc_host_ctrl;
7812
898a56f8 7813 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 7814 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7815
7816 if ((int_mbox != 0) ||
7817 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7818 intr_ok = 1;
7938109f 7819 break;
b16250e3
MC		 7820 }
7821
7938109f
MC		 7822 msleep(10);
7823 }
7824
7825 tg3_disable_ints(tp);
7826
4f125f42 7827 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 7828
4f125f42 7829 err = tg3_request_irq(tp, 0);
7938109f
MC		 7830
7831 if (err)
7832 return err;
7833
b16250e3 7834 if (intr_ok)
7938109f
MC		 7835 return 0;
7836
7837 return -EIO;
7838}
7839
7840/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7841 * successfully restored
7842 */
7843static int tg3_test_msi(struct tg3 *tp)
7844{
7938109f
MC		 7845 int err;
7846 u16 pci_cmd;
7847
7848 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7849 return 0;
7850
7851 /* Turn off SERR reporting in case MSI terminates with Master
7852 * Abort.
7853 */
7854 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7855 pci_write_config_word(tp->pdev, PCI_COMMAND,
7856 pci_cmd & ~PCI_COMMAND_SERR);
7857
7858 err = tg3_test_interrupt(tp);
7859
7860 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7861
7862 if (!err)
7863 return 0;
7864
7865 /* other failures */
7866 if (err != -EIO)
7867 return err;
7868
7869 /* MSI test failed, go back to INTx mode */
7870 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7871 "switching to INTx mode. Please report this failure to "
7872 "the PCI maintainer and include system chipset information.\n",
7873 tp->dev->name);
7874
4f125f42 7875 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 7876
7938109f
MC		 7877 pci_disable_msi(tp->pdev);
7878
7879 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7880
4f125f42 7881 err = tg3_request_irq(tp, 0);
7938109f
MC		 7882 if (err)
7883 return err;
7884
7885 /* Need to reset the chip because the MSI cycle may have terminated
7886 * with Master Abort.
7887 */
f47c11ee 7888 tg3_full_lock(tp, 1);
7938109f 7889
944d980e 7890 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 7891 err = tg3_init_hw(tp, 1);
7938109f 7892
f47c11ee 7893 tg3_full_unlock(tp);
7938109f
MC		 7894
7895 if (err)
4f125f42 7896 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 7897
7898 return err;
7899}
7900
9e9fd12d
MC		 7901static int tg3_request_firmware(struct tg3 *tp)
7902{
7903 const __be32 *fw_data;
7904
7905 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7906 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7907 tp->dev->name, tp->fw_needed);
7908 return -ENOENT;
7909 }
7910
7911 fw_data = (void *)tp->fw->data;
7912
7913 /* Firmware blob starts with version numbers, followed by
7914 * start address and _full_ length including BSS sections
7915 * (which must be longer than the actual data, of course
7916 */
7917
7918 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7919 if (tp->fw_len < (tp->fw->size - 12)) {
7920 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7921 tp->dev->name, tp->fw_len, tp->fw_needed);
7922 release_firmware(tp->fw);
7923 tp->fw = NULL;
7924 return -EINVAL;
7925 }
7926
7927 /* We no longer need firmware; we have it. */
7928 tp->fw_needed = NULL;
7929 return 0;
7930}
7931
679563f4
MC		 7932static bool tg3_enable_msix(struct tg3 *tp)
7933{
7934 int i, rc, cpus = num_online_cpus();
7935 struct msix_entry msix_ent[tp->irq_max];
7936
7937 if (cpus == 1)
7938 /* Just fallback to the simpler MSI mode. */
7939 return false;
7940
7941 /*
7942 * We want as many rx rings enabled as there are cpus.
7943 * The first MSIX vector only deals with link interrupts, etc,
7944 * so we add one to the number of vectors we are requesting.
7945 */
7946 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
7947
7948 for (i = 0; i < tp->irq_max; i++) {
7949 msix_ent[i].entry = i;
7950 msix_ent[i].vector = 0;
7951 }
7952
7953 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
7954 if (rc != 0) {
7955 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
7956 return false;
7957 if (pci_enable_msix(tp->pdev, msix_ent, rc))
7958 return false;
7959 printk(KERN_NOTICE
7960 "%s: Requested %d MSI-X vectors, received %d\n",
7961 tp->dev->name, tp->irq_cnt, rc);
7962 tp->irq_cnt = rc;
7963 }
7964
7965 for (i = 0; i < tp->irq_max; i++)
7966 tp->napi[i].irq_vec = msix_ent[i].vector;
7967
7968 return true;
7969}
7970
07b0173c
MC		 7971static void tg3_ints_init(struct tg3 *tp)
7972{
679563f4
MC		 7973 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
7974 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 7975 /* All MSI supporting chips should support tagged
7976 * status. Assert that this is the case.
7977 */
679563f4
MC		 7978 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7979 "Not using MSI.\n", tp->dev->name);
7980 goto defcfg;
07b0173c 7981 }
4f125f42 7982
679563f4
MC		 7983 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
7984 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
7985 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
7986 pci_enable_msi(tp->pdev) == 0)
7987 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7988
7989 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
7990 u32 msi_mode = tr32(MSGINT_MODE);
7991 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7992 }
7993defcfg:
7994 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7995 tp->irq_cnt = 1;
7996 tp->napi[0].irq_vec = tp->pdev->irq;
7997 }
07b0173c
MC		 7998}
7999
8000static void tg3_ints_fini(struct tg3 *tp)
8001{
679563f4
MC		 8002 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8003 pci_disable_msix(tp->pdev);
8004 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8005 pci_disable_msi(tp->pdev);
8006 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
07b0173c
MC		 8007}
8008
1da177e4
LT		 8009static int tg3_open(struct net_device *dev)
8010{
8011 struct tg3 *tp = netdev_priv(dev);
4f125f42 8012 int i, err;
1da177e4 8013
9e9fd12d
MC		 8014 if (tp->fw_needed) {
8015 err = tg3_request_firmware(tp);
8016 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8017 if (err)
8018 return err;
8019 } else if (err) {
8020 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8021 tp->dev->name);
8022 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8023 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8024 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8025 tp->dev->name);
8026 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8027 }
8028 }
8029
c49a1561
MC		 8030 netif_carrier_off(tp->dev);
8031
bc1c7567 8032 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8033 if (err)
bc1c7567 8034 return err;
2f751b67
MC		 8035
8036 tg3_full_lock(tp, 0);
bc1c7567 8037
1da177e4
LT		 8038 tg3_disable_ints(tp);
8039 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8040
f47c11ee 8041 tg3_full_unlock(tp);
1da177e4 8042
679563f4
MC		 8043 /*
8044 * Setup interrupts first so we know how
8045 * many NAPI resources to allocate
8046 */
8047 tg3_ints_init(tp);
8048
1da177e4
LT		 8049 /* The placement of this call is tied
8050 * to the setup and use of Host TX descriptors.
8051 */
8052 err = tg3_alloc_consistent(tp);
8053 if (err)
679563f4 8054 goto err_out1;
88b06bc2 8055
8ef0442f 8056 napi_enable(&tp->napi[0].napi);
1da177e4 8057
4f125f42
MC		 8058 for (i = 0; i < tp->irq_cnt; i++) {
8059 struct tg3_napi *tnapi = &tp->napi[i];
8060 err = tg3_request_irq(tp, i);
8061 if (err) {
8062 for (i--; i >= 0; i--)
8063 free_irq(tnapi->irq_vec, tnapi);
8064 break;
8065 }
8066 }
1da177e4 8067
07b0173c 8068 if (err)
679563f4 8069 goto err_out2;
bea3348e 8070
f47c11ee 8071 tg3_full_lock(tp, 0);
1da177e4 8072
8e7a22e3 8073 err = tg3_init_hw(tp, 1);
1da177e4 8074 if (err) {
944d980e 8075 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8076 tg3_free_rings(tp);
8077 } else {
fac9b83e
DM		 8078 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8079 tp->timer_offset = HZ;
8080 else
8081 tp->timer_offset = HZ / 10;
8082
8083 BUG_ON(tp->timer_offset > HZ);
8084 tp->timer_counter = tp->timer_multiplier =
8085 (HZ / tp->timer_offset);
8086 tp->asf_counter = tp->asf_multiplier =
28fbef78 8087 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8088
8089 init_timer(&tp->timer);
8090 tp->timer.expires = jiffies + tp->timer_offset;
8091 tp->timer.data = (unsigned long) tp;
8092 tp->timer.function = tg3_timer;
1da177e4
LT		 8093 }
8094
f47c11ee 8095 tg3_full_unlock(tp);
1da177e4 8096
07b0173c 8097 if (err)
679563f4 8098 goto err_out3;
1da177e4 8099
7938109f
MC		 8100 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8101 err = tg3_test_msi(tp);
fac9b83e 8102
7938109f 8103 if (err) {
f47c11ee 8104 tg3_full_lock(tp, 0);
944d980e 8105 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8106 tg3_free_rings(tp);
f47c11ee 8107 tg3_full_unlock(tp);
7938109f 8108
679563f4 8109 goto err_out2;
7938109f 8110 }
fcfa0a32
MC		 8111
8112 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8113 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
b5d3772c 8114 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8115
b5d3772c
MC		 8116 tw32(PCIE_TRANSACTION_CFG,
8117 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32
MC		 8118 }
8119 }
7938109f
MC		 8120 }
8121
b02fd9e3
MC		 8122 tg3_phy_start(tp);
8123
f47c11ee 8124 tg3_full_lock(tp, 0);
1da177e4 8125
7938109f
MC		 8126 add_timer(&tp->timer);
8127 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8128 tg3_enable_ints(tp);
8129
f47c11ee 8130 tg3_full_unlock(tp);
1da177e4
LT		 8131
8132 netif_start_queue(dev);
8133
8134 return 0;
07b0173c 8135
679563f4 8136err_out3:
4f125f42
MC		 8137 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8138 struct tg3_napi *tnapi = &tp->napi[i];
8139 free_irq(tnapi->irq_vec, tnapi);
8140 }
07b0173c 8141
679563f4 8142err_out2:
8ef0442f 8143 napi_disable(&tp->napi[0].napi);
07b0173c 8144 tg3_free_consistent(tp);
679563f4
MC		 8145
8146err_out1:
8147 tg3_ints_fini(tp);
07b0173c 8148 return err;
1da177e4
LT		 8149}
8150
8151#if 0
8152/*static*/ void tg3_dump_state(struct tg3 *tp)
8153{
8154 u32 val32, val32_2, val32_3, val32_4, val32_5;
8155 u16 val16;
8156 int i;
898a56f8 8157 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8158
8159 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8160 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8161 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8162 val16, val32);
8163
8164 /* MAC block */
8165 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8166 tr32(MAC_MODE), tr32(MAC_STATUS));
8167 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8168 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8169 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8170 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8171 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8172 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8173
8174 /* Send data initiator control block */
8175 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8176 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8177 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8178 tr32(SNDDATAI_STATSCTRL));
8179
8180 /* Send data completion control block */
8181 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8182
8183 /* Send BD ring selector block */
8184 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8185 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8186
8187 /* Send BD initiator control block */
8188 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8189 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8190
8191 /* Send BD completion control block */
8192 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8193
8194 /* Receive list placement control block */
8195 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8196 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8197 printk(" RCVLPC_STATSCTRL[%08x]\n",
8198 tr32(RCVLPC_STATSCTRL));
8199
8200 /* Receive data and receive BD initiator control block */
8201 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8202 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8203
8204 /* Receive data completion control block */
8205 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8206 tr32(RCVDCC_MODE));
8207
8208 /* Receive BD initiator control block */
8209 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8210 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8211
8212 /* Receive BD completion control block */
8213 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8214 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8215
8216 /* Receive list selector control block */
8217 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8218 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8219
8220 /* Mbuf cluster free block */
8221 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8222 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8223
8224 /* Host coalescing control block */
8225 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8226 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8227 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8228 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8229 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8230 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8231 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8232 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8233 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8234 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8235 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8236 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8237
8238 /* Memory arbiter control block */
8239 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8240 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8241
8242 /* Buffer manager control block */
8243 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8244 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8245 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8246 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8247 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8248 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8249 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8250 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8251
8252 /* Read DMA control block */
8253 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8254 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8255
8256 /* Write DMA control block */
8257 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8258 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8259
8260 /* DMA completion block */
8261 printk("DEBUG: DMAC_MODE[%08x]\n",
8262 tr32(DMAC_MODE));
8263
8264 /* GRC block */
8265 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8266 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8267 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8268 tr32(GRC_LOCAL_CTRL));
8269
8270 /* TG3_BDINFOs */
8271 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8272 tr32(RCVDBDI_JUMBO_BD + 0x0),
8273 tr32(RCVDBDI_JUMBO_BD + 0x4),
8274 tr32(RCVDBDI_JUMBO_BD + 0x8),
8275 tr32(RCVDBDI_JUMBO_BD + 0xc));
8276 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8277 tr32(RCVDBDI_STD_BD + 0x0),
8278 tr32(RCVDBDI_STD_BD + 0x4),
8279 tr32(RCVDBDI_STD_BD + 0x8),
8280 tr32(RCVDBDI_STD_BD + 0xc));
8281 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8282 tr32(RCVDBDI_MINI_BD + 0x0),
8283 tr32(RCVDBDI_MINI_BD + 0x4),
8284 tr32(RCVDBDI_MINI_BD + 0x8),
8285 tr32(RCVDBDI_MINI_BD + 0xc));
8286
8287 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8288 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8289 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8290 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8291 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8292 val32, val32_2, val32_3, val32_4);
8293
8294 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8295 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8296 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8297 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8298 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8299 val32, val32_2, val32_3, val32_4);
8300
8301 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8302 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8303 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8304 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8305 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8306 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8307 val32, val32_2, val32_3, val32_4, val32_5);
8308
8309 /* SW status block */
898a56f8
MC		 8310 printk(KERN_DEBUG
8311 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8312 sblk->status,
8313 sblk->status_tag,
8314 sblk->rx_jumbo_consumer,
8315 sblk->rx_consumer,
8316 sblk->rx_mini_consumer,
8317 sblk->idx[0].rx_producer,
8318 sblk->idx[0].tx_consumer);
1da177e4
LT		 8319
8320 /* SW statistics block */
8321 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8322 ((u32 *)tp->hw_stats)[0],
8323 ((u32 *)tp->hw_stats)[1],
8324 ((u32 *)tp->hw_stats)[2],
8325 ((u32 *)tp->hw_stats)[3]);
8326
8327 /* Mailboxes */
8328 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8329 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8330 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8331 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8332 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8333
8334 /* NIC side send descriptors. */
8335 for (i = 0; i < 6; i++) {
8336 unsigned long txd;
8337
8338 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8339 + (i * sizeof(struct tg3_tx_buffer_desc));
8340 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8341 i,
8342 readl(txd + 0x0), readl(txd + 0x4),
8343 readl(txd + 0x8), readl(txd + 0xc));
8344 }
8345
8346 /* NIC side RX descriptors. */
8347 for (i = 0; i < 6; i++) {
8348 unsigned long rxd;
8349
8350 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8351 + (i * sizeof(struct tg3_rx_buffer_desc));
8352 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8353 i,
8354 readl(rxd + 0x0), readl(rxd + 0x4),
8355 readl(rxd + 0x8), readl(rxd + 0xc));
8356 rxd += (4 * sizeof(u32));
8357 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8358 i,
8359 readl(rxd + 0x0), readl(rxd + 0x4),
8360 readl(rxd + 0x8), readl(rxd + 0xc));
8361 }
8362
8363 for (i = 0; i < 6; i++) {
8364 unsigned long rxd;
8365
8366 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8367 + (i * sizeof(struct tg3_rx_buffer_desc));
8368 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8369 i,
8370 readl(rxd + 0x0), readl(rxd + 0x4),
8371 readl(rxd + 0x8), readl(rxd + 0xc));
8372 rxd += (4 * sizeof(u32));
8373 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8374 i,
8375 readl(rxd + 0x0), readl(rxd + 0x4),
8376 readl(rxd + 0x8), readl(rxd + 0xc));
8377 }
8378}
8379#endif
8380
8381static struct net_device_stats *tg3_get_stats(struct net_device *);
8382static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8383
8384static int tg3_close(struct net_device *dev)
8385{
4f125f42 8386 int i;
1da177e4
LT		 8387 struct tg3 *tp = netdev_priv(dev);
8388
8ef0442f 8389 napi_disable(&tp->napi[0].napi);
28e53bdd 8390 cancel_work_sync(&tp->reset_task);
7faa006f 8391
1da177e4
LT		 8392 netif_stop_queue(dev);
8393
8394 del_timer_sync(&tp->timer);
8395
f47c11ee 8396 tg3_full_lock(tp, 1);
1da177e4
LT		 8397#if 0
8398 tg3_dump_state(tp);
8399#endif
8400
8401 tg3_disable_ints(tp);
8402
944d980e 8403 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8404 tg3_free_rings(tp);
5cf64b8a 8405 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8406
f47c11ee 8407 tg3_full_unlock(tp);
1da177e4 8408
4f125f42
MC		 8409 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8410 struct tg3_napi *tnapi = &tp->napi[i];
8411 free_irq(tnapi->irq_vec, tnapi);
8412 }
07b0173c
MC		 8413
8414 tg3_ints_fini(tp);
1da177e4
LT		 8415
8416 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8417 sizeof(tp->net_stats_prev));
8418 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8419 sizeof(tp->estats_prev));
8420
8421 tg3_free_consistent(tp);
8422
bc1c7567
MC		 8423 tg3_set_power_state(tp, PCI_D3hot);
8424
8425 netif_carrier_off(tp->dev);
8426
1da177e4
LT		 8427 return 0;
8428}
8429
8430static inline unsigned long get_stat64(tg3_stat64_t *val)
8431{
8432 unsigned long ret;
8433
8434#if (BITS_PER_LONG == 32)
8435 ret = val->low;
8436#else
8437 ret = ((u64)val->high << 32) | ((u64)val->low);
8438#endif
8439 return ret;
8440}
8441
816f8b86
SB		 8442static inline u64 get_estat64(tg3_stat64_t *val)
8443{
8444 return ((u64)val->high << 32) | ((u64)val->low);
8445}
8446
1da177e4
LT		 8447static unsigned long calc_crc_errors(struct tg3 *tp)
8448{
8449 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8450
8451 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8452 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8453 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8454 u32 val;
8455
f47c11ee 8456 spin_lock_bh(&tp->lock);
569a5df8
MC		 8457 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8458 tg3_writephy(tp, MII_TG3_TEST1,
8459 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8460 tg3_readphy(tp, 0x14, &val);
8461 } else
8462 val = 0;
f47c11ee 8463 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8464
8465 tp->phy_crc_errors += val;
8466
8467 return tp->phy_crc_errors;
8468 }
8469
8470 return get_stat64(&hw_stats->rx_fcs_errors);
8471}
8472
8473#define ESTAT_ADD(member) \
8474 estats->member = old_estats->member + \
816f8b86 8475 get_estat64(&hw_stats->member)
1da177e4
LT		 8476
8477static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8478{
8479 struct tg3_ethtool_stats *estats = &tp->estats;
8480 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8481 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8482
8483 if (!hw_stats)
8484 return old_estats;
8485
8486 ESTAT_ADD(rx_octets);
8487 ESTAT_ADD(rx_fragments);
8488 ESTAT_ADD(rx_ucast_packets);
8489 ESTAT_ADD(rx_mcast_packets);
8490 ESTAT_ADD(rx_bcast_packets);
8491 ESTAT_ADD(rx_fcs_errors);
8492 ESTAT_ADD(rx_align_errors);
8493 ESTAT_ADD(rx_xon_pause_rcvd);
8494 ESTAT_ADD(rx_xoff_pause_rcvd);
8495 ESTAT_ADD(rx_mac_ctrl_rcvd);
8496 ESTAT_ADD(rx_xoff_entered);
8497 ESTAT_ADD(rx_frame_too_long_errors);
8498 ESTAT_ADD(rx_jabbers);
8499 ESTAT_ADD(rx_undersize_packets);
8500 ESTAT_ADD(rx_in_length_errors);
8501 ESTAT_ADD(rx_out_length_errors);
8502 ESTAT_ADD(rx_64_or_less_octet_packets);
8503 ESTAT_ADD(rx_65_to_127_octet_packets);
8504 ESTAT_ADD(rx_128_to_255_octet_packets);
8505 ESTAT_ADD(rx_256_to_511_octet_packets);
8506 ESTAT_ADD(rx_512_to_1023_octet_packets);
8507 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8508 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8509 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8510 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8511 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8512
8513 ESTAT_ADD(tx_octets);
8514 ESTAT_ADD(tx_collisions);
8515 ESTAT_ADD(tx_xon_sent);
8516 ESTAT_ADD(tx_xoff_sent);
8517 ESTAT_ADD(tx_flow_control);
8518 ESTAT_ADD(tx_mac_errors);
8519 ESTAT_ADD(tx_single_collisions);
8520 ESTAT_ADD(tx_mult_collisions);
8521 ESTAT_ADD(tx_deferred);
8522 ESTAT_ADD(tx_excessive_collisions);
8523 ESTAT_ADD(tx_late_collisions);
8524 ESTAT_ADD(tx_collide_2times);
8525 ESTAT_ADD(tx_collide_3times);
8526 ESTAT_ADD(tx_collide_4times);
8527 ESTAT_ADD(tx_collide_5times);
8528 ESTAT_ADD(tx_collide_6times);
8529 ESTAT_ADD(tx_collide_7times);
8530 ESTAT_ADD(tx_collide_8times);
8531 ESTAT_ADD(tx_collide_9times);
8532 ESTAT_ADD(tx_collide_10times);
8533 ESTAT_ADD(tx_collide_11times);
8534 ESTAT_ADD(tx_collide_12times);
8535 ESTAT_ADD(tx_collide_13times);
8536 ESTAT_ADD(tx_collide_14times);
8537 ESTAT_ADD(tx_collide_15times);
8538 ESTAT_ADD(tx_ucast_packets);
8539 ESTAT_ADD(tx_mcast_packets);
8540 ESTAT_ADD(tx_bcast_packets);
8541 ESTAT_ADD(tx_carrier_sense_errors);
8542 ESTAT_ADD(tx_discards);
8543 ESTAT_ADD(tx_errors);
8544
8545 ESTAT_ADD(dma_writeq_full);
8546 ESTAT_ADD(dma_write_prioq_full);
8547 ESTAT_ADD(rxbds_empty);
8548 ESTAT_ADD(rx_discards);
8549 ESTAT_ADD(rx_errors);
8550 ESTAT_ADD(rx_threshold_hit);
8551
8552 ESTAT_ADD(dma_readq_full);
8553 ESTAT_ADD(dma_read_prioq_full);
8554 ESTAT_ADD(tx_comp_queue_full);
8555
8556 ESTAT_ADD(ring_set_send_prod_index);
8557 ESTAT_ADD(ring_status_update);
8558 ESTAT_ADD(nic_irqs);
8559 ESTAT_ADD(nic_avoided_irqs);
8560 ESTAT_ADD(nic_tx_threshold_hit);
8561
8562 return estats;
8563}
8564
8565static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8566{
8567 struct tg3 *tp = netdev_priv(dev);
8568 struct net_device_stats *stats = &tp->net_stats;
8569 struct net_device_stats *old_stats = &tp->net_stats_prev;
8570 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8571
8572 if (!hw_stats)
8573 return old_stats;
8574
8575 stats->rx_packets = old_stats->rx_packets +
8576 get_stat64(&hw_stats->rx_ucast_packets) +
8577 get_stat64(&hw_stats->rx_mcast_packets) +
8578 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8579
1da177e4
LT		 8580 stats->tx_packets = old_stats->tx_packets +
8581 get_stat64(&hw_stats->tx_ucast_packets) +
8582 get_stat64(&hw_stats->tx_mcast_packets) +
8583 get_stat64(&hw_stats->tx_bcast_packets);
8584
8585 stats->rx_bytes = old_stats->rx_bytes +
8586 get_stat64(&hw_stats->rx_octets);
8587 stats->tx_bytes = old_stats->tx_bytes +
8588 get_stat64(&hw_stats->tx_octets);
8589
8590 stats->rx_errors = old_stats->rx_errors +
4f63b877 8591 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8592 stats->tx_errors = old_stats->tx_errors +
8593 get_stat64(&hw_stats->tx_errors) +
8594 get_stat64(&hw_stats->tx_mac_errors) +
8595 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8596 get_stat64(&hw_stats->tx_discards);
8597
8598 stats->multicast = old_stats->multicast +
8599 get_stat64(&hw_stats->rx_mcast_packets);
8600 stats->collisions = old_stats->collisions +
8601 get_stat64(&hw_stats->tx_collisions);
8602
8603 stats->rx_length_errors = old_stats->rx_length_errors +
8604 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8605 get_stat64(&hw_stats->rx_undersize_packets);
8606
8607 stats->rx_over_errors = old_stats->rx_over_errors +
8608 get_stat64(&hw_stats->rxbds_empty);
8609 stats->rx_frame_errors = old_stats->rx_frame_errors +
8610 get_stat64(&hw_stats->rx_align_errors);
8611 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8612 get_stat64(&hw_stats->tx_discards);
8613 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8614 get_stat64(&hw_stats->tx_carrier_sense_errors);
8615
8616 stats->rx_crc_errors = old_stats->rx_crc_errors +
8617 calc_crc_errors(tp);
8618
4f63b877
JL		 8619 stats->rx_missed_errors = old_stats->rx_missed_errors +
8620 get_stat64(&hw_stats->rx_discards);
8621
1da177e4
LT		 8622 return stats;
8623}
8624
8625static inline u32 calc_crc(unsigned char *buf, int len)
8626{
8627 u32 reg;
8628 u32 tmp;
8629 int j, k;
8630
8631 reg = 0xffffffff;
8632
8633 for (j = 0; j < len; j++) {
8634 reg ^= buf[j];
8635
8636 for (k = 0; k < 8; k++) {
8637 tmp = reg & 0x01;
8638
8639 reg >>= 1;
8640
8641 if (tmp) {
8642 reg ^= 0xedb88320;
8643 }
8644 }
8645 }
8646
8647 return ~reg;
8648}
8649
8650static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8651{
8652 /* accept or reject all multicast frames */
8653 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8654 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8655 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8656 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8657}
8658
8659static void __tg3_set_rx_mode(struct net_device *dev)
8660{
8661 struct tg3 *tp = netdev_priv(dev);
8662 u32 rx_mode;
8663
8664 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8665 RX_MODE_KEEP_VLAN_TAG);
8666
8667 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8668 * flag clear.
8669 */
8670#if TG3_VLAN_TAG_USED
8671 if (!tp->vlgrp &&
8672 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8673 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8674#else
8675 /* By definition, VLAN is disabled always in this
8676 * case.
8677 */
8678 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8679 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8680#endif
8681
8682 if (dev->flags & IFF_PROMISC) {
8683 /* Promiscuous mode. */
8684 rx_mode |= RX_MODE_PROMISC;
8685 } else if (dev->flags & IFF_ALLMULTI) {
8686 /* Accept all multicast. */
8687 tg3_set_multi (tp, 1);
8688 } else if (dev->mc_count < 1) {
8689 /* Reject all multicast. */
8690 tg3_set_multi (tp, 0);
8691 } else {
8692 /* Accept one or more multicast(s). */
8693 struct dev_mc_list *mclist;
8694 unsigned int i;
8695 u32 mc_filter[4] = { 0, };
8696 u32 regidx;
8697 u32 bit;
8698 u32 crc;
8699
8700 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8701 i++, mclist = mclist->next) {
8702
8703 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8704 bit = ~crc & 0x7f;
8705 regidx = (bit & 0x60) >> 5;
8706 bit &= 0x1f;
8707 mc_filter[regidx] |= (1 << bit);
8708 }
8709
8710 tw32(MAC_HASH_REG_0, mc_filter[0]);
8711 tw32(MAC_HASH_REG_1, mc_filter[1]);
8712 tw32(MAC_HASH_REG_2, mc_filter[2]);
8713 tw32(MAC_HASH_REG_3, mc_filter[3]);
8714 }
8715
8716 if (rx_mode != tp->rx_mode) {
8717 tp->rx_mode = rx_mode;
8718 tw32_f(MAC_RX_MODE, rx_mode);
8719 udelay(10);
8720 }
8721}
8722
8723static void tg3_set_rx_mode(struct net_device *dev)
8724{
8725 struct tg3 *tp = netdev_priv(dev);
8726
e75f7c90
MC		 8727 if (!netif_running(dev))
8728 return;
8729
f47c11ee 8730 tg3_full_lock(tp, 0);
1da177e4 8731 __tg3_set_rx_mode(dev);
f47c11ee 8732 tg3_full_unlock(tp);
1da177e4
LT		 8733}
8734
8735#define TG3_REGDUMP_LEN (32 * 1024)
8736
8737static int tg3_get_regs_len(struct net_device *dev)
8738{
8739 return TG3_REGDUMP_LEN;
8740}
8741
8742static void tg3_get_regs(struct net_device *dev,
8743 struct ethtool_regs *regs, void *_p)
8744{
8745 u32 *p = _p;
8746 struct tg3 *tp = netdev_priv(dev);
8747 u8 *orig_p = _p;
8748 int i;
8749
8750 regs->version = 0;
8751
8752 memset(p, 0, TG3_REGDUMP_LEN);
8753
bc1c7567
MC		 8754 if (tp->link_config.phy_is_low_power)
8755 return;
8756
f47c11ee 8757 tg3_full_lock(tp, 0);
1da177e4
LT		 8758
8759#define __GET_REG32(reg) (*(p)++ = tr32(reg))
8760#define GET_REG32_LOOP(base,len) \
8761do { p = (u32 *)(orig_p + (base)); \
8762 for (i = 0; i < len; i += 4) \
8763 __GET_REG32((base) + i); \
8764} while (0)
8765#define GET_REG32_1(reg) \
8766do { p = (u32 *)(orig_p + (reg)); \
8767 __GET_REG32((reg)); \
8768} while (0)
8769
8770 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8771 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8772 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8773 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8774 GET_REG32_1(SNDDATAC_MODE);
8775 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8776 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8777 GET_REG32_1(SNDBDC_MODE);
8778 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8779 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8780 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8781 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8782 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8783 GET_REG32_1(RCVDCC_MODE);
8784 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8785 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8786 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8787 GET_REG32_1(MBFREE_MODE);
8788 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8789 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8790 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8791 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8792 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 8793 GET_REG32_1(RX_CPU_MODE);
8794 GET_REG32_1(RX_CPU_STATE);
8795 GET_REG32_1(RX_CPU_PGMCTR);
8796 GET_REG32_1(RX_CPU_HWBKPT);
8797 GET_REG32_1(TX_CPU_MODE);
8798 GET_REG32_1(TX_CPU_STATE);
8799 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 8800 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8801 GET_REG32_LOOP(FTQ_RESET, 0x120);
8802 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8803 GET_REG32_1(DMAC_MODE);
8804 GET_REG32_LOOP(GRC_MODE, 0x4c);
8805 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8806 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8807
8808#undef __GET_REG32
8809#undef GET_REG32_LOOP
8810#undef GET_REG32_1
8811
f47c11ee 8812 tg3_full_unlock(tp);
1da177e4
LT		 8813}
8814
8815static int tg3_get_eeprom_len(struct net_device *dev)
8816{
8817 struct tg3 *tp = netdev_priv(dev);
8818
8819 return tp->nvram_size;
8820}
8821
1da177e4
LT		 8822static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8823{
8824 struct tg3 *tp = netdev_priv(dev);
8825 int ret;
8826 u8 *pd;
b9fc7dc5 8827 u32 i, offset, len, b_offset, b_count;
a9dc529d 8828 __be32 val;
1da177e4 8829
df259d8c
MC		 8830 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8831 return -EINVAL;
8832
bc1c7567
MC		 8833 if (tp->link_config.phy_is_low_power)
8834 return -EAGAIN;
8835
1da177e4
LT		 8836 offset = eeprom->offset;
8837 len = eeprom->len;
8838 eeprom->len = 0;
8839
8840 eeprom->magic = TG3_EEPROM_MAGIC;
8841
8842 if (offset & 3) {
8843 /* adjustments to start on required 4 byte boundary */
8844 b_offset = offset & 3;
8845 b_count = 4 - b_offset;
8846 if (b_count > len) {
8847 /* i.e. offset=1 len=2 */
8848 b_count = len;
8849 }
a9dc529d 8850 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 8851 if (ret)
8852 return ret;
1da177e4
LT		 8853 memcpy(data, ((char*)&val) + b_offset, b_count);
8854 len -= b_count;
8855 offset += b_count;
8856 eeprom->len += b_count;
8857 }
8858
8859 /* read bytes upto the last 4 byte boundary */
8860 pd = &data[eeprom->len];
8861 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 8862 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 8863 if (ret) {
8864 eeprom->len += i;
8865 return ret;
8866 }
1da177e4
LT		 8867 memcpy(pd + i, &val, 4);
8868 }
8869 eeprom->len += i;
8870
8871 if (len & 3) {
8872 /* read last bytes not ending on 4 byte boundary */
8873 pd = &data[eeprom->len];
8874 b_count = len & 3;
8875 b_offset = offset + len - b_count;
a9dc529d 8876 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 8877 if (ret)
8878 return ret;
b9fc7dc5 8879 memcpy(pd, &val, b_count);
1da177e4
LT		 8880 eeprom->len += b_count;
8881 }
8882 return 0;
8883}
8884
6aa20a22 8885static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 8886
8887static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8888{
8889 struct tg3 *tp = netdev_priv(dev);
8890 int ret;
b9fc7dc5 8891 u32 offset, len, b_offset, odd_len;
1da177e4 8892 u8 *buf;
a9dc529d 8893 __be32 start, end;
1da177e4 8894
bc1c7567
MC		 8895 if (tp->link_config.phy_is_low_power)
8896 return -EAGAIN;
8897
df259d8c
MC		 8898 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8899 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 8900 return -EINVAL;
8901
8902 offset = eeprom->offset;
8903 len = eeprom->len;
8904
8905 if ((b_offset = (offset & 3))) {
8906 /* adjustments to start on required 4 byte boundary */
a9dc529d 8907 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 8908 if (ret)
8909 return ret;
1da177e4
LT		 8910 len += b_offset;
8911 offset &= ~3;
1c8594b4
MC		 8912 if (len < 4)
8913 len = 4;
1da177e4
LT		 8914 }
8915
8916 odd_len = 0;
1c8594b4 8917 if (len & 3) {
1da177e4
LT		 8918 /* adjustments to end on required 4 byte boundary */
8919 odd_len = 1;
8920 len = (len + 3) & ~3;
a9dc529d 8921 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 8922 if (ret)
8923 return ret;
1da177e4
LT		 8924 }
8925
8926 buf = data;
8927 if (b_offset || odd_len) {
8928 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 8929 if (!buf)
1da177e4
LT		 8930 return -ENOMEM;
8931 if (b_offset)
8932 memcpy(buf, &start, 4);
8933 if (odd_len)
8934 memcpy(buf+len-4, &end, 4);
8935 memcpy(buf + b_offset, data, eeprom->len);
8936 }
8937
8938 ret = tg3_nvram_write_block(tp, offset, len, buf);
8939
8940 if (buf != data)
8941 kfree(buf);
8942
8943 return ret;
8944}
8945
8946static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8947{
b02fd9e3
MC		 8948 struct tg3 *tp = netdev_priv(dev);
8949
8950 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8951 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8952 return -EAGAIN;
298cf9be 8953 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3 8954 }
6aa20a22 8955
1da177e4
LT		 8956 cmd->supported = (SUPPORTED_Autoneg);
8957
8958 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8959 cmd->supported |= (SUPPORTED_1000baseT_Half |
8960 SUPPORTED_1000baseT_Full);
8961
ef348144 8962 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 8963 cmd->supported |= (SUPPORTED_100baseT_Half |
8964 SUPPORTED_100baseT_Full |
8965 SUPPORTED_10baseT_Half |
8966 SUPPORTED_10baseT_Full |
3bebab59 8967 SUPPORTED_TP);
ef348144
KK		 8968 cmd->port = PORT_TP;
8969 } else {
1da177e4 8970 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 8971 cmd->port = PORT_FIBRE;
8972 }
6aa20a22 8973
1da177e4
LT		 8974 cmd->advertising = tp->link_config.advertising;
8975 if (netif_running(dev)) {
8976 cmd->speed = tp->link_config.active_speed;
8977 cmd->duplex = tp->link_config.active_duplex;
8978 }
1da177e4 8979 cmd->phy_address = PHY_ADDR;
7e5856bd 8980 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 8981 cmd->autoneg = tp->link_config.autoneg;
8982 cmd->maxtxpkt = 0;
8983 cmd->maxrxpkt = 0;
8984 return 0;
8985}
6aa20a22 8986
1da177e4
LT		 8987static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8988{
8989 struct tg3 *tp = netdev_priv(dev);
6aa20a22 8990
b02fd9e3
MC		 8991 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8992 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8993 return -EAGAIN;
298cf9be 8994 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
b02fd9e3
MC		 8995 }
8996
7e5856bd
MC		 8997 if (cmd->autoneg != AUTONEG_ENABLE &&
8998 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 8999 return -EINVAL;
7e5856bd
MC		 9000
9001 if (cmd->autoneg == AUTONEG_DISABLE &&
9002 cmd->duplex != DUPLEX_FULL &&
9003 cmd->duplex != DUPLEX_HALF)
37ff238d 9004 return -EINVAL;
1da177e4 9005
7e5856bd
MC		 9006 if (cmd->autoneg == AUTONEG_ENABLE) {
9007 u32 mask = ADVERTISED_Autoneg |
9008 ADVERTISED_Pause |
9009 ADVERTISED_Asym_Pause;
9010
9011 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9012 mask |= ADVERTISED_1000baseT_Half |
9013 ADVERTISED_1000baseT_Full;
9014
9015 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9016 mask |= ADVERTISED_100baseT_Half |
9017 ADVERTISED_100baseT_Full |
9018 ADVERTISED_10baseT_Half |
9019 ADVERTISED_10baseT_Full |
9020 ADVERTISED_TP;
9021 else
9022 mask |= ADVERTISED_FIBRE;
9023
9024 if (cmd->advertising & ~mask)
9025 return -EINVAL;
9026
9027 mask &= (ADVERTISED_1000baseT_Half |
9028 ADVERTISED_1000baseT_Full |
9029 ADVERTISED_100baseT_Half |
9030 ADVERTISED_100baseT_Full |
9031 ADVERTISED_10baseT_Half |
9032 ADVERTISED_10baseT_Full);
9033
9034 cmd->advertising &= mask;
9035 } else {
9036 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9037 if (cmd->speed != SPEED_1000)
9038 return -EINVAL;
9039
9040 if (cmd->duplex != DUPLEX_FULL)
9041 return -EINVAL;
9042 } else {
9043 if (cmd->speed != SPEED_100 &&
9044 cmd->speed != SPEED_10)
9045 return -EINVAL;
9046 }
9047 }
9048
f47c11ee 9049 tg3_full_lock(tp, 0);
1da177e4
LT		 9050
9051 tp->link_config.autoneg = cmd->autoneg;
9052 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9053 tp->link_config.advertising = (cmd->advertising |
9054 ADVERTISED_Autoneg);
1da177e4
LT		 9055 tp->link_config.speed = SPEED_INVALID;
9056 tp->link_config.duplex = DUPLEX_INVALID;
9057 } else {
9058 tp->link_config.advertising = 0;
9059 tp->link_config.speed = cmd->speed;
9060 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9061 }
6aa20a22 9062
24fcad6b
MC		 9063 tp->link_config.orig_speed = tp->link_config.speed;
9064 tp->link_config.orig_duplex = tp->link_config.duplex;
9065 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9066
1da177e4
LT		 9067 if (netif_running(dev))
9068 tg3_setup_phy(tp, 1);
9069
f47c11ee 9070 tg3_full_unlock(tp);
6aa20a22 9071
1da177e4
LT		 9072 return 0;
9073}
6aa20a22 9074
1da177e4
LT		 9075static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9076{
9077 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9078
1da177e4
LT		 9079 strcpy(info->driver, DRV_MODULE_NAME);
9080 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9081 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9082 strcpy(info->bus_info, pci_name(tp->pdev));
9083}
6aa20a22 9084
1da177e4
LT		 9085static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9086{
9087 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9088
12dac075
RW		 9089 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9090 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9091 wol->supported = WAKE_MAGIC;
9092 else
9093 wol->supported = 0;
1da177e4 9094 wol->wolopts = 0;
05ac4cb7
MC		 9095 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9096 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9097 wol->wolopts = WAKE_MAGIC;
9098 memset(&wol->sopass, 0, sizeof(wol->sopass));
9099}
6aa20a22 9100
1da177e4
LT		 9101static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9102{
9103 struct tg3 *tp = netdev_priv(dev);
12dac075 9104 struct device *dp = &tp->pdev->dev;
6aa20a22 9105
1da177e4
LT		 9106 if (wol->wolopts & ~WAKE_MAGIC)
9107 return -EINVAL;
9108 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9109 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9110 return -EINVAL;
6aa20a22 9111
f47c11ee 9112 spin_lock_bh(&tp->lock);
12dac075 9113 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9114 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9115 device_set_wakeup_enable(dp, true);
9116 } else {
1da177e4 9117 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9118 device_set_wakeup_enable(dp, false);
9119 }
f47c11ee 9120 spin_unlock_bh(&tp->lock);
6aa20a22 9121
1da177e4
LT		 9122 return 0;
9123}
6aa20a22 9124
1da177e4
LT		 9125static u32 tg3_get_msglevel(struct net_device *dev)
9126{
9127 struct tg3 *tp = netdev_priv(dev);
9128 return tp->msg_enable;
9129}
6aa20a22 9130
1da177e4
LT		 9131static void tg3_set_msglevel(struct net_device *dev, u32 value)
9132{
9133 struct tg3 *tp = netdev_priv(dev);
9134 tp->msg_enable = value;
9135}
6aa20a22 9136
1da177e4
LT		 9137static int tg3_set_tso(struct net_device *dev, u32 value)
9138{
9139 struct tg3 *tp = netdev_priv(dev);
9140
9141 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9142 if (value)
9143 return -EINVAL;
9144 return 0;
9145 }
027455ad
MC		 9146 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9147 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9148 if (value) {
b0026624 9149 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9151 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9152 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 9153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9154 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9155 dev->features |= NETIF_F_TSO_ECN;
9156 } else
9157 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9158 }
1da177e4
LT		 9159 return ethtool_op_set_tso(dev, value);
9160}
6aa20a22 9161
1da177e4
LT		 9162static int tg3_nway_reset(struct net_device *dev)
9163{
9164 struct tg3 *tp = netdev_priv(dev);
1da177e4 9165 int r;
6aa20a22 9166
1da177e4
LT		 9167 if (!netif_running(dev))
9168 return -EAGAIN;
9169
c94e3941
MC		 9170 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9171 return -EINVAL;
9172
b02fd9e3
MC		 9173 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9174 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9175 return -EAGAIN;
298cf9be 9176 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
b02fd9e3
MC		 9177 } else {
9178 u32 bmcr;
9179
9180 spin_lock_bh(&tp->lock);
9181 r = -EINVAL;
9182 tg3_readphy(tp, MII_BMCR, &bmcr);
9183 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9184 ((bmcr & BMCR_ANENABLE) ||
9185 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9186 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9187 BMCR_ANENABLE);
9188 r = 0;
9189 }
9190 spin_unlock_bh(&tp->lock);
1da177e4 9191 }
6aa20a22 9192
1da177e4
LT		 9193 return r;
9194}
6aa20a22 9195
1da177e4
LT		 9196static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9197{
9198 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9199
1da177e4
LT		 9200 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9201 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9202 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9203 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9204 else
9205 ering->rx_jumbo_max_pending = 0;
9206
9207 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9208
9209 ering->rx_pending = tp->rx_pending;
9210 ering->rx_mini_pending = 0;
4f81c32b
MC		 9211 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9212 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9213 else
9214 ering->rx_jumbo_pending = 0;
9215
f3f3f27e 9216 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9217}
6aa20a22 9218
1da177e4
LT		 9219static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9220{
9221 struct tg3 *tp = netdev_priv(dev);
646c9edd 9222 int i, irq_sync = 0, err = 0;
6aa20a22 9223
1da177e4
LT		 9224 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9225 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9226 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9227 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9228 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9229 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9230 return -EINVAL;
6aa20a22 9231
bbe832c0 9232 if (netif_running(dev)) {
b02fd9e3 9233 tg3_phy_stop(tp);
1da177e4 9234 tg3_netif_stop(tp);
bbe832c0
MC		 9235 irq_sync = 1;
9236 }
1da177e4 9237
bbe832c0 9238 tg3_full_lock(tp, irq_sync);
6aa20a22 9239
1da177e4
LT		 9240 tp->rx_pending = ering->rx_pending;
9241
9242 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9243 tp->rx_pending > 63)
9244 tp->rx_pending = 63;
9245 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9246
9247 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9248 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9249
9250 if (netif_running(dev)) {
944d980e 9251 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9252 err = tg3_restart_hw(tp, 1);
9253 if (!err)
9254 tg3_netif_start(tp);
1da177e4
LT		 9255 }
9256
f47c11ee 9257 tg3_full_unlock(tp);
6aa20a22 9258
b02fd9e3
MC		 9259 if (irq_sync && !err)
9260 tg3_phy_start(tp);
9261
b9ec6c1b 9262 return err;
1da177e4 9263}
6aa20a22 9264
1da177e4
LT		 9265static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9266{
9267 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9268
1da177e4 9269 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9270
e18ce346 9271 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9272 epause->rx_pause = 1;
9273 else
9274 epause->rx_pause = 0;
9275
e18ce346 9276 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9277 epause->tx_pause = 1;
9278 else
9279 epause->tx_pause = 0;
1da177e4 9280}
6aa20a22 9281
1da177e4
LT		 9282static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9283{
9284 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9285 int err = 0;
6aa20a22 9286
b02fd9e3
MC		 9287 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9288 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9289 return -EAGAIN;
1da177e4 9290
b02fd9e3
MC		 9291 if (epause->autoneg) {
9292 u32 newadv;
9293 struct phy_device *phydev;
f47c11ee 9294
298cf9be 9295 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1da177e4 9296
b02fd9e3
MC		 9297 if (epause->rx_pause) {
9298 if (epause->tx_pause)
9299 newadv = ADVERTISED_Pause;
9300 else
9301 newadv = ADVERTISED_Pause |
9302 ADVERTISED_Asym_Pause;
9303 } else if (epause->tx_pause) {
9304 newadv = ADVERTISED_Asym_Pause;
9305 } else
9306 newadv = 0;
9307
9308 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9309 u32 oldadv = phydev->advertising &
9310 (ADVERTISED_Pause |
9311 ADVERTISED_Asym_Pause);
9312 if (oldadv != newadv) {
9313 phydev->advertising &=
9314 ~(ADVERTISED_Pause |
9315 ADVERTISED_Asym_Pause);
9316 phydev->advertising |= newadv;
9317 err = phy_start_aneg(phydev);
9318 }
9319 } else {
9320 tp->link_config.advertising &=
9321 ~(ADVERTISED_Pause |
9322 ADVERTISED_Asym_Pause);
9323 tp->link_config.advertising |= newadv;
9324 }
9325 } else {
9326 if (epause->rx_pause)
e18ce346 9327 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9328 else
e18ce346 9329 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9330
b02fd9e3 9331 if (epause->tx_pause)
e18ce346 9332 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9333 else
e18ce346 9334 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9335
9336 if (netif_running(dev))
9337 tg3_setup_flow_control(tp, 0, 0);
9338 }
9339 } else {
9340 int irq_sync = 0;
9341
9342 if (netif_running(dev)) {
9343 tg3_netif_stop(tp);
9344 irq_sync = 1;
9345 }
9346
9347 tg3_full_lock(tp, irq_sync);
9348
9349 if (epause->autoneg)
9350 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9351 else
9352 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9353 if (epause->rx_pause)
e18ce346 9354 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9355 else
e18ce346 9356 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9357 if (epause->tx_pause)
e18ce346 9358 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9359 else
e18ce346 9360 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9361
9362 if (netif_running(dev)) {
9363 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9364 err = tg3_restart_hw(tp, 1);
9365 if (!err)
9366 tg3_netif_start(tp);
9367 }
9368
9369 tg3_full_unlock(tp);
9370 }
6aa20a22 9371
b9ec6c1b 9372 return err;
1da177e4 9373}
6aa20a22 9374
1da177e4
LT		 9375static u32 tg3_get_rx_csum(struct net_device *dev)
9376{
9377 struct tg3 *tp = netdev_priv(dev);
9378 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9379}
6aa20a22 9380
1da177e4
LT		 9381static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9382{
9383 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9384
1da177e4
LT		 9385 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9386 if (data != 0)
9387 return -EINVAL;
9388 return 0;
9389 }
6aa20a22 9390
f47c11ee 9391 spin_lock_bh(&tp->lock);
1da177e4
LT		 9392 if (data)
9393 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9394 else
9395 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9396 spin_unlock_bh(&tp->lock);
6aa20a22 9397
1da177e4
LT		 9398 return 0;
9399}
6aa20a22 9400
1da177e4
LT		 9401static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9402{
9403 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9404
1da177e4
LT		 9405 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9406 if (data != 0)
9407 return -EINVAL;
9408 return 0;
9409 }
6aa20a22 9410
321d32a0 9411 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9412 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9413 else
9c27dbdf 9414 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9415
9416 return 0;
9417}
9418
b9f2c044 9419static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9420{
b9f2c044
JG		 9421 switch (sset) {
9422 case ETH_SS_TEST:
9423 return TG3_NUM_TEST;
9424 case ETH_SS_STATS:
9425 return TG3_NUM_STATS;
9426 default:
9427 return -EOPNOTSUPP;
9428 }
4cafd3f5
MC		 9429}
9430
1da177e4
LT		 9431static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9432{
9433 switch (stringset) {
9434 case ETH_SS_STATS:
9435 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9436 break;
4cafd3f5
MC		 9437 case ETH_SS_TEST:
9438 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9439 break;
1da177e4
LT		 9440 default:
9441 WARN_ON(1); /* we need a WARN() */
9442 break;
9443 }
9444}
9445
4009a93d
MC		 9446static int tg3_phys_id(struct net_device *dev, u32 data)
9447{
9448 struct tg3 *tp = netdev_priv(dev);
9449 int i;
9450
9451 if (!netif_running(tp->dev))
9452 return -EAGAIN;
9453
9454 if (data == 0)
759afc31 9455 data = UINT_MAX / 2;
4009a93d
MC		 9456
9457 for (i = 0; i < (data * 2); i++) {
9458 if ((i % 2) == 0)
9459 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9460 LED_CTRL_1000MBPS_ON |
9461 LED_CTRL_100MBPS_ON |
9462 LED_CTRL_10MBPS_ON |
9463 LED_CTRL_TRAFFIC_OVERRIDE |
9464 LED_CTRL_TRAFFIC_BLINK |
9465 LED_CTRL_TRAFFIC_LED);
6aa20a22 9466
4009a93d
MC		 9467 else
9468 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9469 LED_CTRL_TRAFFIC_OVERRIDE);
9470
9471 if (msleep_interruptible(500))
9472 break;
9473 }
9474 tw32(MAC_LED_CTRL, tp->led_ctrl);
9475 return 0;
9476}
9477
1da177e4
LT		 9478static void tg3_get_ethtool_stats (struct net_device *dev,
9479 struct ethtool_stats *estats, u64 *tmp_stats)
9480{
9481 struct tg3 *tp = netdev_priv(dev);
9482 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9483}
9484
566f86ad 9485#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9486#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9487#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9488#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9489#define NVRAM_SELFBOOT_HW_SIZE 0x20
9490#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9491
9492static int tg3_test_nvram(struct tg3 *tp)
9493{
b9fc7dc5 9494 u32 csum, magic;
a9dc529d 9495 __be32 *buf;
ab0049b4 9496 int i, j, k, err = 0, size;
566f86ad 9497
df259d8c
MC		 9498 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9499 return 0;
9500
e4f34110 9501 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9502 return -EIO;
9503
1b27777a
MC		 9504 if (magic == TG3_EEPROM_MAGIC)
9505 size = NVRAM_TEST_SIZE;
b16250e3 9506 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9507 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9508 TG3_EEPROM_SB_FORMAT_1) {
9509 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9510 case TG3_EEPROM_SB_REVISION_0:
9511 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9512 break;
9513 case TG3_EEPROM_SB_REVISION_2:
9514 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9515 break;
9516 case TG3_EEPROM_SB_REVISION_3:
9517 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9518 break;
9519 default:
9520 return 0;
9521 }
9522 } else
1b27777a 9523 return 0;
b16250e3
MC		 9524 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9525 size = NVRAM_SELFBOOT_HW_SIZE;
9526 else
1b27777a
MC		 9527 return -EIO;
9528
9529 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9530 if (buf == NULL)
9531 return -ENOMEM;
9532
1b27777a
MC		 9533 err = -EIO;
9534 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9535 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9536 if (err)
566f86ad 9537 break;
566f86ad 9538 }
1b27777a 9539 if (i < size)
566f86ad
MC		 9540 goto out;
9541
1b27777a 9542 /* Selfboot format */
a9dc529d 9543 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9544 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9545 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9546 u8 *buf8 = (u8 *) buf, csum8 = 0;
9547
b9fc7dc5 9548 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9549 TG3_EEPROM_SB_REVISION_2) {
9550 /* For rev 2, the csum doesn't include the MBA. */
9551 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9552 csum8 += buf8[i];
9553 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9554 csum8 += buf8[i];
9555 } else {
9556 for (i = 0; i < size; i++)
9557 csum8 += buf8[i];
9558 }
1b27777a 9559
ad96b485
AB		 9560 if (csum8 == 0) {
9561 err = 0;
9562 goto out;
9563 }
9564
9565 err = -EIO;
9566 goto out;
1b27777a 9567 }
566f86ad 9568
b9fc7dc5 9569 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9570 TG3_EEPROM_MAGIC_HW) {
9571 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9572 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9573 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9574
9575 /* Separate the parity bits and the data bytes. */
9576 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9577 if ((i == 0) || (i == 8)) {
9578 int l;
9579 u8 msk;
9580
9581 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9582 parity[k++] = buf8[i] & msk;
9583 i++;
9584 }
9585 else if (i == 16) {
9586 int l;
9587 u8 msk;
9588
9589 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9590 parity[k++] = buf8[i] & msk;
9591 i++;
9592
9593 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9594 parity[k++] = buf8[i] & msk;
9595 i++;
9596 }
9597 data[j++] = buf8[i];
9598 }
9599
9600 err = -EIO;
9601 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9602 u8 hw8 = hweight8(data[i]);
9603
9604 if ((hw8 & 0x1) && parity[i])
9605 goto out;
9606 else if (!(hw8 & 0x1) && !parity[i])
9607 goto out;
9608 }
9609 err = 0;
9610 goto out;
9611 }
9612
566f86ad
MC		 9613 /* Bootstrap checksum at offset 0x10 */
9614 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9615 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9616 goto out;
9617
9618 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9619 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9620 if (csum != be32_to_cpu(buf[0xfc/4]))
9621 goto out;
566f86ad
MC		 9622
9623 err = 0;
9624
9625out:
9626 kfree(buf);
9627 return err;
9628}
9629
ca43007a
MC		 9630#define TG3_SERDES_TIMEOUT_SEC 2
9631#define TG3_COPPER_TIMEOUT_SEC 6
9632
9633static int tg3_test_link(struct tg3 *tp)
9634{
9635 int i, max;
9636
9637 if (!netif_running(tp->dev))
9638 return -ENODEV;
9639
4c987487 9640 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 9641 max = TG3_SERDES_TIMEOUT_SEC;
9642 else
9643 max = TG3_COPPER_TIMEOUT_SEC;
9644
9645 for (i = 0; i < max; i++) {
9646 if (netif_carrier_ok(tp->dev))
9647 return 0;
9648
9649 if (msleep_interruptible(1000))
9650 break;
9651 }
9652
9653 return -EIO;
9654}
9655
a71116d1 9656/* Only test the commonly used registers */
30ca3e37 9657static int tg3_test_registers(struct tg3 *tp)
a71116d1 9658{
b16250e3 9659 int i, is_5705, is_5750;
a71116d1
MC		 9660 u32 offset, read_mask, write_mask, val, save_val, read_val;
9661 static struct {
9662 u16 offset;
9663 u16 flags;
9664#define TG3_FL_5705 0x1
9665#define TG3_FL_NOT_5705 0x2
9666#define TG3_FL_NOT_5788 0x4
b16250e3 9667#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 9668 u32 read_mask;
9669 u32 write_mask;
9670 } reg_tbl[] = {
9671 /* MAC Control Registers */
9672 { MAC_MODE, TG3_FL_NOT_5705,
9673 0x00000000, 0x00ef6f8c },
9674 { MAC_MODE, TG3_FL_5705,
9675 0x00000000, 0x01ef6b8c },
9676 { MAC_STATUS, TG3_FL_NOT_5705,
9677 0x03800107, 0x00000000 },
9678 { MAC_STATUS, TG3_FL_5705,
9679 0x03800100, 0x00000000 },
9680 { MAC_ADDR_0_HIGH, 0x0000,
9681 0x00000000, 0x0000ffff },
9682 { MAC_ADDR_0_LOW, 0x0000,
9683 0x00000000, 0xffffffff },
9684 { MAC_RX_MTU_SIZE, 0x0000,
9685 0x00000000, 0x0000ffff },
9686 { MAC_TX_MODE, 0x0000,
9687 0x00000000, 0x00000070 },
9688 { MAC_TX_LENGTHS, 0x0000,
9689 0x00000000, 0x00003fff },
9690 { MAC_RX_MODE, TG3_FL_NOT_5705,
9691 0x00000000, 0x000007fc },
9692 { MAC_RX_MODE, TG3_FL_5705,
9693 0x00000000, 0x000007dc },
9694 { MAC_HASH_REG_0, 0x0000,
9695 0x00000000, 0xffffffff },
9696 { MAC_HASH_REG_1, 0x0000,
9697 0x00000000, 0xffffffff },
9698 { MAC_HASH_REG_2, 0x0000,
9699 0x00000000, 0xffffffff },
9700 { MAC_HASH_REG_3, 0x0000,
9701 0x00000000, 0xffffffff },
9702
9703 /* Receive Data and Receive BD Initiator Control Registers. */
9704 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9705 0x00000000, 0xffffffff },
9706 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9707 0x00000000, 0xffffffff },
9708 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9709 0x00000000, 0x00000003 },
9710 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9711 0x00000000, 0xffffffff },
9712 { RCVDBDI_STD_BD+0, 0x0000,
9713 0x00000000, 0xffffffff },
9714 { RCVDBDI_STD_BD+4, 0x0000,
9715 0x00000000, 0xffffffff },
9716 { RCVDBDI_STD_BD+8, 0x0000,
9717 0x00000000, 0xffff0002 },
9718 { RCVDBDI_STD_BD+0xc, 0x0000,
9719 0x00000000, 0xffffffff },
6aa20a22 9720
a71116d1
MC		 9721 /* Receive BD Initiator Control Registers. */
9722 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9723 0x00000000, 0xffffffff },
9724 { RCVBDI_STD_THRESH, TG3_FL_5705,
9725 0x00000000, 0x000003ff },
9726 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9727 0x00000000, 0xffffffff },
6aa20a22 9728
a71116d1
MC		 9729 /* Host Coalescing Control Registers. */
9730 { HOSTCC_MODE, TG3_FL_NOT_5705,
9731 0x00000000, 0x00000004 },
9732 { HOSTCC_MODE, TG3_FL_5705,
9733 0x00000000, 0x000000f6 },
9734 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9735 0x00000000, 0xffffffff },
9736 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9737 0x00000000, 0x000003ff },
9738 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9739 0x00000000, 0xffffffff },
9740 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9741 0x00000000, 0x000003ff },
9742 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9743 0x00000000, 0xffffffff },
9744 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9745 0x00000000, 0x000000ff },
9746 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9747 0x00000000, 0xffffffff },
9748 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9749 0x00000000, 0x000000ff },
9750 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9751 0x00000000, 0xffffffff },
9752 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9753 0x00000000, 0xffffffff },
9754 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9755 0x00000000, 0xffffffff },
9756 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9757 0x00000000, 0x000000ff },
9758 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9759 0x00000000, 0xffffffff },
9760 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9761 0x00000000, 0x000000ff },
9762 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9763 0x00000000, 0xffffffff },
9764 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9765 0x00000000, 0xffffffff },
9766 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9767 0x00000000, 0xffffffff },
9768 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9769 0x00000000, 0xffffffff },
9770 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9771 0x00000000, 0xffffffff },
9772 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9773 0xffffffff, 0x00000000 },
9774 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9775 0xffffffff, 0x00000000 },
9776
9777 /* Buffer Manager Control Registers. */
b16250e3 9778 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 9779 0x00000000, 0x007fff80 },
b16250e3 9780 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 9781 0x00000000, 0x007fffff },
9782 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9783 0x00000000, 0x0000003f },
9784 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9785 0x00000000, 0x000001ff },
9786 { BUFMGR_MB_HIGH_WATER, 0x0000,
9787 0x00000000, 0x000001ff },
9788 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9789 0xffffffff, 0x00000000 },
9790 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9791 0xffffffff, 0x00000000 },
6aa20a22 9792
a71116d1
MC		 9793 /* Mailbox Registers */
9794 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9795 0x00000000, 0x000001ff },
9796 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9797 0x00000000, 0x000001ff },
9798 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9799 0x00000000, 0x000007ff },
9800 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9801 0x00000000, 0x000001ff },
9802
9803 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9804 };
9805
b16250e3
MC		 9806 is_5705 = is_5750 = 0;
9807 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 9808 is_5705 = 1;
b16250e3
MC		 9809 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9810 is_5750 = 1;
9811 }
a71116d1
MC		 9812
9813 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9814 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9815 continue;
9816
9817 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9818 continue;
9819
9820 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9821 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9822 continue;
9823
b16250e3
MC		 9824 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9825 continue;
9826
a71116d1
MC		 9827 offset = (u32) reg_tbl[i].offset;
9828 read_mask = reg_tbl[i].read_mask;
9829 write_mask = reg_tbl[i].write_mask;
9830
9831 /* Save the original register content */
9832 save_val = tr32(offset);
9833
9834 /* Determine the read-only value. */
9835 read_val = save_val & read_mask;
9836
9837 /* Write zero to the register, then make sure the read-only bits
9838 * are not changed and the read/write bits are all zeros.
9839 */
9840 tw32(offset, 0);
9841
9842 val = tr32(offset);
9843
9844 /* Test the read-only and read/write bits. */
9845 if (((val & read_mask) != read_val) || (val & write_mask))
9846 goto out;
9847
9848 /* Write ones to all the bits defined by RdMask and WrMask, then
9849 * make sure the read-only bits are not changed and the
9850 * read/write bits are all ones.
9851 */
9852 tw32(offset, read_mask | write_mask);
9853
9854 val = tr32(offset);
9855
9856 /* Test the read-only bits. */
9857 if ((val & read_mask) != read_val)
9858 goto out;
9859
9860 /* Test the read/write bits. */
9861 if ((val & write_mask) != write_mask)
9862 goto out;
9863
9864 tw32(offset, save_val);
9865 }
9866
9867 return 0;
9868
9869out:
9f88f29f
MC		 9870 if (netif_msg_hw(tp))
9871 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9872 offset);
a71116d1
MC		 9873 tw32(offset, save_val);
9874 return -EIO;
9875}
9876
7942e1db
MC		 9877static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9878{
f71e1309 9879 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 9880 int i;
9881 u32 j;
9882
e9edda69 9883 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 9884 for (j = 0; j < len; j += 4) {
9885 u32 val;
9886
9887 tg3_write_mem(tp, offset + j, test_pattern[i]);
9888 tg3_read_mem(tp, offset + j, &val);
9889 if (val != test_pattern[i])
9890 return -EIO;
9891 }
9892 }
9893 return 0;
9894}
9895
9896static int tg3_test_memory(struct tg3 *tp)
9897{
9898 static struct mem_entry {
9899 u32 offset;
9900 u32 len;
9901 } mem_tbl_570x[] = {
38690194 9902 { 0x00000000, 0x00b50},
7942e1db
MC		 9903 { 0x00002000, 0x1c000},
9904 { 0xffffffff, 0x00000}
9905 }, mem_tbl_5705[] = {
9906 { 0x00000100, 0x0000c},
9907 { 0x00000200, 0x00008},
7942e1db
MC		 9908 { 0x00004000, 0x00800},
9909 { 0x00006000, 0x01000},
9910 { 0x00008000, 0x02000},
9911 { 0x00010000, 0x0e000},
9912 { 0xffffffff, 0x00000}
79f4d13a
MC		 9913 }, mem_tbl_5755[] = {
9914 { 0x00000200, 0x00008},
9915 { 0x00004000, 0x00800},
9916 { 0x00006000, 0x00800},
9917 { 0x00008000, 0x02000},
9918 { 0x00010000, 0x0c000},
9919 { 0xffffffff, 0x00000}
b16250e3
MC		 9920 }, mem_tbl_5906[] = {
9921 { 0x00000200, 0x00008},
9922 { 0x00004000, 0x00400},
9923 { 0x00006000, 0x00400},
9924 { 0x00008000, 0x01000},
9925 { 0x00010000, 0x01000},
9926 { 0xffffffff, 0x00000}
7942e1db
MC		 9927 };
9928 struct mem_entry *mem_tbl;
9929 int err = 0;
9930 int i;
9931
321d32a0
MC		 9932 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9933 mem_tbl = mem_tbl_5755;
9934 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9935 mem_tbl = mem_tbl_5906;
9936 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9937 mem_tbl = mem_tbl_5705;
9938 else
7942e1db
MC		 9939 mem_tbl = mem_tbl_570x;
9940
9941 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9942 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9943 mem_tbl[i].len)) != 0)
9944 break;
9945 }
6aa20a22 9946
7942e1db
MC		 9947 return err;
9948}
9949
9f40dead
MC		 9950#define TG3_MAC_LOOPBACK 0
9951#define TG3_PHY_LOOPBACK 1
9952
9953static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 9954{
9f40dead 9955 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 9956 u32 desc_idx, coal_now;
c76949a6
MC		 9957 struct sk_buff *skb, *rx_skb;
9958 u8 *tx_data;
9959 dma_addr_t map;
9960 int num_pkts, tx_len, rx_len, i, err;
9961 struct tg3_rx_buffer_desc *desc;
898a56f8 9962 struct tg3_napi *tnapi, *rnapi;
21f581a5 9963 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 9964
898a56f8
MC		 9965 tnapi = &tp->napi[0];
9966 rnapi = &tp->napi[0];
fd2ce37f 9967 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 9968
9f40dead 9969 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 9970 /* HW errata - mac loopback fails in some cases on 5780.
9971 * Normal traffic and PHY loopback are not affected by
9972 * errata.
9973 */
9974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9975 return 0;
9976
9f40dead 9977 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 9978 MAC_MODE_PORT_INT_LPBACK;
9979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9980 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 9981 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9982 mac_mode |= MAC_MODE_PORT_MODE_MII;
9983 else
9984 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 9985 tw32(MAC_MODE, mac_mode);
9986 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 9987 u32 val;
9988
7f97a4bd
MC		 9989 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9990 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 9991 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9992 } else
9993 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 9994
9ef8ca99
MC		 9995 tg3_phy_toggle_automdix(tp, 0);
9996
3f7045c1 9997 tg3_writephy(tp, MII_BMCR, val);
c94e3941 9998 udelay(40);
5d64ad34 9999
e8f3f6ca 10000 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10001 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10002 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10003 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10004 mac_mode |= MAC_MODE_PORT_MODE_MII;
10005 } else
10006 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10007
c94e3941
MC		 10008 /* reset to prevent losing 1st rx packet intermittently */
10009 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10010 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10011 udelay(10);
10012 tw32_f(MAC_RX_MODE, tp->rx_mode);
10013 }
e8f3f6ca
MC		 10014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10015 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10016 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10017 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10018 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10019 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10020 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10021 }
9f40dead 10022 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10023 }
10024 else
10025 return -EINVAL;
c76949a6
MC		 10026
10027 err = -EIO;
10028
c76949a6 10029 tx_len = 1514;
a20e9c62 10030 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10031 if (!skb)
10032 return -ENOMEM;
10033
c76949a6
MC		 10034 tx_data = skb_put(skb, tx_len);
10035 memcpy(tx_data, tp->dev->dev_addr, 6);
10036 memset(tx_data + 6, 0x0, 8);
10037
10038 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10039
10040 for (i = 14; i < tx_len; i++)
10041 tx_data[i] = (u8) (i & 0xff);
10042
10043 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10044
10045 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10046 rnapi->coal_now);
c76949a6
MC		 10047
10048 udelay(10);
10049
898a56f8 10050 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10051
c76949a6
MC		 10052 num_pkts = 0;
10053
f3f3f27e 10054 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10055
f3f3f27e 10056 tnapi->tx_prod++;
c76949a6
MC		 10057 num_pkts++;
10058
f3f3f27e
MC		 10059 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10060 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10061
10062 udelay(10);
10063
3f7045c1
MC		 10064 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10065 for (i = 0; i < 25; i++) {
c76949a6 10066 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10067 coal_now);
c76949a6
MC		 10068
10069 udelay(10);
10070
898a56f8
MC		 10071 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10072 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10073 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10074 (rx_idx == (rx_start_idx + num_pkts)))
10075 break;
10076 }
10077
10078 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10079 dev_kfree_skb(skb);
10080
f3f3f27e 10081 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10082 goto out;
10083
10084 if (rx_idx != rx_start_idx + num_pkts)
10085 goto out;
10086
72334482 10087 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10088 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10089 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10090 if (opaque_key != RXD_OPAQUE_RING_STD)
10091 goto out;
10092
10093 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10094 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10095 goto out;
10096
10097 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10098 if (rx_len != tx_len)
10099 goto out;
10100
21f581a5 10101 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10102
21f581a5 10103 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10104 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10105
10106 for (i = 14; i < tx_len; i++) {
10107 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10108 goto out;
10109 }
10110 err = 0;
6aa20a22 10111
c76949a6
MC		 10112 /* tg3_free_rings will unmap and free the rx_skb */
10113out:
10114 return err;
10115}
10116
9f40dead
MC		 10117#define TG3_MAC_LOOPBACK_FAILED 1
10118#define TG3_PHY_LOOPBACK_FAILED 2
10119#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10120 TG3_PHY_LOOPBACK_FAILED)
10121
10122static int tg3_test_loopback(struct tg3 *tp)
10123{
10124 int err = 0;
9936bcf6 10125 u32 cpmuctrl = 0;
9f40dead
MC		 10126
10127 if (!netif_running(tp->dev))
10128 return TG3_LOOPBACK_FAILED;
10129
b9ec6c1b
MC		 10130 err = tg3_reset_hw(tp, 1);
10131 if (err)
10132 return TG3_LOOPBACK_FAILED;
9f40dead 10133
6833c043
MC		 10134 /* Turn off gphy autopowerdown. */
10135 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10136 tg3_phy_toggle_apd(tp, false);
10137
321d32a0 10138 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10139 int i;
10140 u32 status;
10141
10142 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10143
10144 /* Wait for up to 40 microseconds to acquire lock. */
10145 for (i = 0; i < 4; i++) {
10146 status = tr32(TG3_CPMU_MUTEX_GNT);
10147 if (status == CPMU_MUTEX_GNT_DRIVER)
10148 break;
10149 udelay(10);
10150 }
10151
10152 if (status != CPMU_MUTEX_GNT_DRIVER)
10153 return TG3_LOOPBACK_FAILED;
10154
b2a5c19c 10155 /* Turn off link-based power management. */
e875093c 10156 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10157 tw32(TG3_CPMU_CTRL,
10158 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10159 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10160 }
10161
9f40dead
MC		 10162 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10163 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10164
321d32a0 10165 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10166 tw32(TG3_CPMU_CTRL, cpmuctrl);
10167
10168 /* Release the mutex */
10169 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10170 }
10171
dd477003
MC		 10172 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10173 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10174 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10175 err |= TG3_PHY_LOOPBACK_FAILED;
10176 }
10177
6833c043
MC		 10178 /* Re-enable gphy autopowerdown. */
10179 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10180 tg3_phy_toggle_apd(tp, true);
10181
9f40dead
MC		 10182 return err;
10183}
10184
4cafd3f5
MC		 10185static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10186 u64 *data)
10187{
566f86ad
MC		 10188 struct tg3 *tp = netdev_priv(dev);
10189
bc1c7567
MC		 10190 if (tp->link_config.phy_is_low_power)
10191 tg3_set_power_state(tp, PCI_D0);
10192
566f86ad
MC		 10193 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10194
10195 if (tg3_test_nvram(tp) != 0) {
10196 etest->flags |= ETH_TEST_FL_FAILED;
10197 data[0] = 1;
10198 }
ca43007a
MC		 10199 if (tg3_test_link(tp) != 0) {
10200 etest->flags |= ETH_TEST_FL_FAILED;
10201 data[1] = 1;
10202 }
a71116d1 10203 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10204 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10205
10206 if (netif_running(dev)) {
b02fd9e3 10207 tg3_phy_stop(tp);
a71116d1 10208 tg3_netif_stop(tp);
bbe832c0
MC		 10209 irq_sync = 1;
10210 }
a71116d1 10211
bbe832c0 10212 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10213
10214 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10215 err = tg3_nvram_lock(tp);
a71116d1
MC		 10216 tg3_halt_cpu(tp, RX_CPU_BASE);
10217 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10218 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10219 if (!err)
10220 tg3_nvram_unlock(tp);
a71116d1 10221
d9ab5ad1
MC		 10222 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10223 tg3_phy_reset(tp);
10224
a71116d1
MC		 10225 if (tg3_test_registers(tp) != 0) {
10226 etest->flags |= ETH_TEST_FL_FAILED;
10227 data[2] = 1;
10228 }
7942e1db
MC		 10229 if (tg3_test_memory(tp) != 0) {
10230 etest->flags |= ETH_TEST_FL_FAILED;
10231 data[3] = 1;
10232 }
9f40dead 10233 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10234 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10235
f47c11ee
DM		 10236 tg3_full_unlock(tp);
10237
d4bc3927
MC		 10238 if (tg3_test_interrupt(tp) != 0) {
10239 etest->flags |= ETH_TEST_FL_FAILED;
10240 data[5] = 1;
10241 }
f47c11ee
DM		 10242
10243 tg3_full_lock(tp, 0);
d4bc3927 10244
a71116d1
MC		 10245 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10246 if (netif_running(dev)) {
10247 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10248 err2 = tg3_restart_hw(tp, 1);
10249 if (!err2)
b9ec6c1b 10250 tg3_netif_start(tp);
a71116d1 10251 }
f47c11ee
DM		 10252
10253 tg3_full_unlock(tp);
b02fd9e3
MC		 10254
10255 if (irq_sync && !err2)
10256 tg3_phy_start(tp);
a71116d1 10257 }
bc1c7567
MC		 10258 if (tp->link_config.phy_is_low_power)
10259 tg3_set_power_state(tp, PCI_D3hot);
10260
4cafd3f5
MC		 10261}
10262
1da177e4
LT		 10263static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10264{
10265 struct mii_ioctl_data *data = if_mii(ifr);
10266 struct tg3 *tp = netdev_priv(dev);
10267 int err;
10268
b02fd9e3
MC		 10269 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10270 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10271 return -EAGAIN;
298cf9be 10272 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
b02fd9e3
MC		 10273 }
10274
1da177e4
LT		 10275 switch(cmd) {
10276 case SIOCGMIIPHY:
10277 data->phy_id = PHY_ADDR;
10278
10279 /* fallthru */
10280 case SIOCGMIIREG: {
10281 u32 mii_regval;
10282
10283 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10284 break; /* We have no PHY */
10285
bc1c7567
MC		 10286 if (tp->link_config.phy_is_low_power)
10287 return -EAGAIN;
10288
f47c11ee 10289 spin_lock_bh(&tp->lock);
1da177e4 10290 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10291 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10292
10293 data->val_out = mii_regval;
10294
10295 return err;
10296 }
10297
10298 case SIOCSMIIREG:
10299 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10300 break; /* We have no PHY */
10301
10302 if (!capable(CAP_NET_ADMIN))
10303 return -EPERM;
10304
bc1c7567
MC		 10305 if (tp->link_config.phy_is_low_power)
10306 return -EAGAIN;
10307
f47c11ee 10308 spin_lock_bh(&tp->lock);
1da177e4 10309 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10310 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10311
10312 return err;
10313
10314 default:
10315 /* do nothing */
10316 break;
10317 }
10318 return -EOPNOTSUPP;
10319}
10320
10321#if TG3_VLAN_TAG_USED
10322static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10323{
10324 struct tg3 *tp = netdev_priv(dev);
10325
844b3eed
MC		 10326 if (!netif_running(dev)) {
10327 tp->vlgrp = grp;
10328 return;
10329 }
10330
10331 tg3_netif_stop(tp);
29315e87 10332
f47c11ee 10333 tg3_full_lock(tp, 0);
1da177e4
LT		 10334
10335 tp->vlgrp = grp;
10336
10337 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10338 __tg3_set_rx_mode(dev);
10339
844b3eed 10340 tg3_netif_start(tp);
46966545
MC		 10341
10342 tg3_full_unlock(tp);
1da177e4 10343}
1da177e4
LT		 10344#endif
10345
15f9850d
DM		 10346static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10347{
10348 struct tg3 *tp = netdev_priv(dev);
10349
10350 memcpy(ec, &tp->coal, sizeof(*ec));
10351 return 0;
10352}
10353
d244c892
MC		 10354static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10355{
10356 struct tg3 *tp = netdev_priv(dev);
10357 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10358 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10359
10360 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10361 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10362 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10363 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10364 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10365 }
10366
10367 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10368 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10369 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10370 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10371 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10372 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10373 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10374 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10375 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10376 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10377 return -EINVAL;
10378
10379 /* No rx interrupts will be generated if both are zero */
10380 if ((ec->rx_coalesce_usecs == 0) &&
10381 (ec->rx_max_coalesced_frames == 0))
10382 return -EINVAL;
10383
10384 /* No tx interrupts will be generated if both are zero */
10385 if ((ec->tx_coalesce_usecs == 0) &&
10386 (ec->tx_max_coalesced_frames == 0))
10387 return -EINVAL;
10388
10389 /* Only copy relevant parameters, ignore all others. */
10390 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10391 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10392 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10393 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10394 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10395 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10396 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10397 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10398 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10399
10400 if (netif_running(dev)) {
10401 tg3_full_lock(tp, 0);
10402 __tg3_set_coalesce(tp, &tp->coal);
10403 tg3_full_unlock(tp);
10404 }
10405 return 0;
10406}
10407
7282d491 10408static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10409 .get_settings = tg3_get_settings,
10410 .set_settings = tg3_set_settings,
10411 .get_drvinfo = tg3_get_drvinfo,
10412 .get_regs_len = tg3_get_regs_len,
10413 .get_regs = tg3_get_regs,
10414 .get_wol = tg3_get_wol,
10415 .set_wol = tg3_set_wol,
10416 .get_msglevel = tg3_get_msglevel,
10417 .set_msglevel = tg3_set_msglevel,
10418 .nway_reset = tg3_nway_reset,
10419 .get_link = ethtool_op_get_link,
10420 .get_eeprom_len = tg3_get_eeprom_len,
10421 .get_eeprom = tg3_get_eeprom,
10422 .set_eeprom = tg3_set_eeprom,
10423 .get_ringparam = tg3_get_ringparam,
10424 .set_ringparam = tg3_set_ringparam,
10425 .get_pauseparam = tg3_get_pauseparam,
10426 .set_pauseparam = tg3_set_pauseparam,
10427 .get_rx_csum = tg3_get_rx_csum,
10428 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10429 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10430 .set_sg = ethtool_op_set_sg,
1da177e4 10431 .set_tso = tg3_set_tso,
4cafd3f5 10432 .self_test = tg3_self_test,
1da177e4 10433 .get_strings = tg3_get_strings,
4009a93d 10434 .phys_id = tg3_phys_id,
1da177e4 10435 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10436 .get_coalesce = tg3_get_coalesce,
d244c892 10437 .set_coalesce = tg3_set_coalesce,
b9f2c044 10438 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10439};
10440
10441static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10442{
1b27777a 10443 u32 cursize, val, magic;
1da177e4
LT		 10444
10445 tp->nvram_size = EEPROM_CHIP_SIZE;
10446
e4f34110 10447 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10448 return;
10449
b16250e3
MC		 10450 if ((magic != TG3_EEPROM_MAGIC) &&
10451 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10452 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10453 return;
10454
10455 /*
10456 * Size the chip by reading offsets at increasing powers of two.
10457 * When we encounter our validation signature, we know the addressing
10458 * has wrapped around, and thus have our chip size.
10459 */
1b27777a 10460 cursize = 0x10;
1da177e4
LT		 10461
10462 while (cursize < tp->nvram_size) {
e4f34110 10463 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10464 return;
10465
1820180b 10466 if (val == magic)
1da177e4
LT		 10467 break;
10468
10469 cursize <<= 1;
10470 }
10471
10472 tp->nvram_size = cursize;
10473}
6aa20a22 10474
1da177e4
LT		 10475static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10476{
10477 u32 val;
10478
df259d8c
MC		 10479 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10480 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10481 return;
10482
10483 /* Selfboot format */
1820180b 10484 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10485 tg3_get_eeprom_size(tp);
10486 return;
10487 }
10488
6d348f2c 10489 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10490 if (val != 0) {
6d348f2c
MC		 10491 /* This is confusing. We want to operate on the
10492 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10493 * call will read from NVRAM and byteswap the data
10494 * according to the byteswapping settings for all
10495 * other register accesses. This ensures the data we
10496 * want will always reside in the lower 16-bits.
10497 * However, the data in NVRAM is in LE format, which
10498 * means the data from the NVRAM read will always be
10499 * opposite the endianness of the CPU. The 16-bit
10500 * byteswap then brings the data to CPU endianness.
10501 */
10502 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10503 return;
10504 }
10505 }
fd1122a2 10506 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10507}
10508
10509static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10510{
10511 u32 nvcfg1;
10512
10513 nvcfg1 = tr32(NVRAM_CFG1);
10514 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10515 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10516 } else {
1da177e4
LT		 10517 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10518 tw32(NVRAM_CFG1, nvcfg1);
10519 }
10520
4c987487 10521 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10522 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10523 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10524 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10525 tp->nvram_jedecnum = JEDEC_ATMEL;
10526 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10527 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10528 break;
10529 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10530 tp->nvram_jedecnum = JEDEC_ATMEL;
10531 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10532 break;
10533 case FLASH_VENDOR_ATMEL_EEPROM:
10534 tp->nvram_jedecnum = JEDEC_ATMEL;
10535 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10536 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10537 break;
10538 case FLASH_VENDOR_ST:
10539 tp->nvram_jedecnum = JEDEC_ST;
10540 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10541 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10542 break;
10543 case FLASH_VENDOR_SAIFUN:
10544 tp->nvram_jedecnum = JEDEC_SAIFUN;
10545 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10546 break;
10547 case FLASH_VENDOR_SST_SMALL:
10548 case FLASH_VENDOR_SST_LARGE:
10549 tp->nvram_jedecnum = JEDEC_SST;
10550 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10551 break;
1da177e4 10552 }
8590a603 10553 } else {
1da177e4
LT		 10554 tp->nvram_jedecnum = JEDEC_ATMEL;
10555 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10556 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10557 }
10558}
10559
361b4ac2
MC		 10560static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10561{
10562 u32 nvcfg1;
10563
10564 nvcfg1 = tr32(NVRAM_CFG1);
10565
e6af301b
MC		 10566 /* NVRAM protection for TPM */
10567 if (nvcfg1 & (1 << 27))
10568 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10569
361b4ac2 10570 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10571 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10572 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10573 tp->nvram_jedecnum = JEDEC_ATMEL;
10574 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10575 break;
10576 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10577 tp->nvram_jedecnum = JEDEC_ATMEL;
10578 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10579 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10580 break;
10581 case FLASH_5752VENDOR_ST_M45PE10:
10582 case FLASH_5752VENDOR_ST_M45PE20:
10583 case FLASH_5752VENDOR_ST_M45PE40:
10584 tp->nvram_jedecnum = JEDEC_ST;
10585 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10586 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10587 break;
361b4ac2
MC		 10588 }
10589
10590 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10591 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8590a603
MC		 10592 case FLASH_5752PAGE_SIZE_256:
10593 tp->nvram_pagesize = 256;
10594 break;
10595 case FLASH_5752PAGE_SIZE_512:
10596 tp->nvram_pagesize = 512;
10597 break;
10598 case FLASH_5752PAGE_SIZE_1K:
10599 tp->nvram_pagesize = 1024;
10600 break;
10601 case FLASH_5752PAGE_SIZE_2K:
10602 tp->nvram_pagesize = 2048;
10603 break;
10604 case FLASH_5752PAGE_SIZE_4K:
10605 tp->nvram_pagesize = 4096;
10606 break;
10607 case FLASH_5752PAGE_SIZE_264:
10608 tp->nvram_pagesize = 264;
10609 break;
361b4ac2 10610 }
8590a603 10611 } else {
361b4ac2
MC		 10612 /* For eeprom, set pagesize to maximum eeprom size */
10613 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10614
10615 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10616 tw32(NVRAM_CFG1, nvcfg1);
10617 }
10618}
10619
d3c7b886
MC		 10620static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10621{
989a9d23 10622 u32 nvcfg1, protect = 0;
d3c7b886
MC		 10623
10624 nvcfg1 = tr32(NVRAM_CFG1);
10625
10626 /* NVRAM protection for TPM */
989a9d23 10627 if (nvcfg1 & (1 << 27)) {
d3c7b886 10628 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 10629 protect = 1;
10630 }
d3c7b886 10631
989a9d23
MC		 10632 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10633 switch (nvcfg1) {
8590a603
MC		 10634 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10635 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10636 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10637 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10638 tp->nvram_jedecnum = JEDEC_ATMEL;
10639 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10640 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10641 tp->nvram_pagesize = 264;
10642 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10643 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10644 tp->nvram_size = (protect ? 0x3e200 :
10645 TG3_NVRAM_SIZE_512KB);
10646 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10647 tp->nvram_size = (protect ? 0x1f200 :
10648 TG3_NVRAM_SIZE_256KB);
10649 else
10650 tp->nvram_size = (protect ? 0x1f200 :
10651 TG3_NVRAM_SIZE_128KB);
10652 break;
10653 case FLASH_5752VENDOR_ST_M45PE10:
10654 case FLASH_5752VENDOR_ST_M45PE20:
10655 case FLASH_5752VENDOR_ST_M45PE40:
10656 tp->nvram_jedecnum = JEDEC_ST;
10657 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10658 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10659 tp->nvram_pagesize = 256;
10660 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10661 tp->nvram_size = (protect ?
10662 TG3_NVRAM_SIZE_64KB :
10663 TG3_NVRAM_SIZE_128KB);
10664 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10665 tp->nvram_size = (protect ?
10666 TG3_NVRAM_SIZE_64KB :
10667 TG3_NVRAM_SIZE_256KB);
10668 else
10669 tp->nvram_size = (protect ?
10670 TG3_NVRAM_SIZE_128KB :
10671 TG3_NVRAM_SIZE_512KB);
10672 break;
d3c7b886
MC		 10673 }
10674}
10675
1b27777a
MC		 10676static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10677{
10678 u32 nvcfg1;
10679
10680 nvcfg1 = tr32(NVRAM_CFG1);
10681
10682 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10683 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10684 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10685 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10686 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10687 tp->nvram_jedecnum = JEDEC_ATMEL;
10688 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10689 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 10690
8590a603
MC		 10691 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10692 tw32(NVRAM_CFG1, nvcfg1);
10693 break;
10694 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10695 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10696 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10697 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10698 tp->nvram_jedecnum = JEDEC_ATMEL;
10699 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10700 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10701 tp->nvram_pagesize = 264;
10702 break;
10703 case FLASH_5752VENDOR_ST_M45PE10:
10704 case FLASH_5752VENDOR_ST_M45PE20:
10705 case FLASH_5752VENDOR_ST_M45PE40:
10706 tp->nvram_jedecnum = JEDEC_ST;
10707 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10708 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10709 tp->nvram_pagesize = 256;
10710 break;
1b27777a
MC		 10711 }
10712}
10713
6b91fa02
MC		 10714static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10715{
10716 u32 nvcfg1, protect = 0;
10717
10718 nvcfg1 = tr32(NVRAM_CFG1);
10719
10720 /* NVRAM protection for TPM */
10721 if (nvcfg1 & (1 << 27)) {
10722 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10723 protect = 1;
10724 }
10725
10726 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10727 switch (nvcfg1) {
8590a603
MC		 10728 case FLASH_5761VENDOR_ATMEL_ADB021D:
10729 case FLASH_5761VENDOR_ATMEL_ADB041D:
10730 case FLASH_5761VENDOR_ATMEL_ADB081D:
10731 case FLASH_5761VENDOR_ATMEL_ADB161D:
10732 case FLASH_5761VENDOR_ATMEL_MDB021D:
10733 case FLASH_5761VENDOR_ATMEL_MDB041D:
10734 case FLASH_5761VENDOR_ATMEL_MDB081D:
10735 case FLASH_5761VENDOR_ATMEL_MDB161D:
10736 tp->nvram_jedecnum = JEDEC_ATMEL;
10737 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10738 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10739 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10740 tp->nvram_pagesize = 256;
10741 break;
10742 case FLASH_5761VENDOR_ST_A_M45PE20:
10743 case FLASH_5761VENDOR_ST_A_M45PE40:
10744 case FLASH_5761VENDOR_ST_A_M45PE80:
10745 case FLASH_5761VENDOR_ST_A_M45PE16:
10746 case FLASH_5761VENDOR_ST_M_M45PE20:
10747 case FLASH_5761VENDOR_ST_M_M45PE40:
10748 case FLASH_5761VENDOR_ST_M_M45PE80:
10749 case FLASH_5761VENDOR_ST_M_M45PE16:
10750 tp->nvram_jedecnum = JEDEC_ST;
10751 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10752 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10753 tp->nvram_pagesize = 256;
10754 break;
6b91fa02
MC		 10755 }
10756
10757 if (protect) {
10758 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10759 } else {
10760 switch (nvcfg1) {
8590a603
MC		 10761 case FLASH_5761VENDOR_ATMEL_ADB161D:
10762 case FLASH_5761VENDOR_ATMEL_MDB161D:
10763 case FLASH_5761VENDOR_ST_A_M45PE16:
10764 case FLASH_5761VENDOR_ST_M_M45PE16:
10765 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10766 break;
10767 case FLASH_5761VENDOR_ATMEL_ADB081D:
10768 case FLASH_5761VENDOR_ATMEL_MDB081D:
10769 case FLASH_5761VENDOR_ST_A_M45PE80:
10770 case FLASH_5761VENDOR_ST_M_M45PE80:
10771 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10772 break;
10773 case FLASH_5761VENDOR_ATMEL_ADB041D:
10774 case FLASH_5761VENDOR_ATMEL_MDB041D:
10775 case FLASH_5761VENDOR_ST_A_M45PE40:
10776 case FLASH_5761VENDOR_ST_M_M45PE40:
10777 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10778 break;
10779 case FLASH_5761VENDOR_ATMEL_ADB021D:
10780 case FLASH_5761VENDOR_ATMEL_MDB021D:
10781 case FLASH_5761VENDOR_ST_A_M45PE20:
10782 case FLASH_5761VENDOR_ST_M_M45PE20:
10783 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10784 break;
6b91fa02
MC		 10785 }
10786 }
10787}
10788
b5d3772c
MC		 10789static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10790{
10791 tp->nvram_jedecnum = JEDEC_ATMEL;
10792 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10793 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10794}
10795
321d32a0
MC		 10796static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10797{
10798 u32 nvcfg1;
10799
10800 nvcfg1 = tr32(NVRAM_CFG1);
10801
10802 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10803 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10804 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10805 tp->nvram_jedecnum = JEDEC_ATMEL;
10806 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10807 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10808
10809 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10810 tw32(NVRAM_CFG1, nvcfg1);
10811 return;
10812 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10813 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10814 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10815 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10816 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10817 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10818 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10819 tp->nvram_jedecnum = JEDEC_ATMEL;
10820 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10821 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10822
10823 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10824 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10825 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10826 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10827 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10828 break;
10829 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10830 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10831 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10832 break;
10833 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10834 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10835 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10836 break;
10837 }
10838 break;
10839 case FLASH_5752VENDOR_ST_M45PE10:
10840 case FLASH_5752VENDOR_ST_M45PE20:
10841 case FLASH_5752VENDOR_ST_M45PE40:
10842 tp->nvram_jedecnum = JEDEC_ST;
10843 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10844 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10845
10846 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10847 case FLASH_5752VENDOR_ST_M45PE10:
10848 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10849 break;
10850 case FLASH_5752VENDOR_ST_M45PE20:
10851 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10852 break;
10853 case FLASH_5752VENDOR_ST_M45PE40:
10854 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10855 break;
10856 }
10857 break;
10858 default:
df259d8c 10859 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 10860 return;
10861 }
10862
10863 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10864 case FLASH_5752PAGE_SIZE_256:
10865 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10866 tp->nvram_pagesize = 256;
10867 break;
10868 case FLASH_5752PAGE_SIZE_512:
10869 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10870 tp->nvram_pagesize = 512;
10871 break;
10872 case FLASH_5752PAGE_SIZE_1K:
10873 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10874 tp->nvram_pagesize = 1024;
10875 break;
10876 case FLASH_5752PAGE_SIZE_2K:
10877 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10878 tp->nvram_pagesize = 2048;
10879 break;
10880 case FLASH_5752PAGE_SIZE_4K:
10881 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10882 tp->nvram_pagesize = 4096;
10883 break;
10884 case FLASH_5752PAGE_SIZE_264:
10885 tp->nvram_pagesize = 264;
10886 break;
10887 case FLASH_5752PAGE_SIZE_528:
10888 tp->nvram_pagesize = 528;
10889 break;
10890 }
10891}
10892
1da177e4
LT		 10893/* Chips other than 5700/5701 use the NVRAM for fetching info. */
10894static void __devinit tg3_nvram_init(struct tg3 *tp)
10895{
1da177e4
LT		 10896 tw32_f(GRC_EEPROM_ADDR,
10897 (EEPROM_ADDR_FSM_RESET |
10898 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10899 EEPROM_ADDR_CLKPERD_SHIFT)));
10900
9d57f01c 10901 msleep(1);
1da177e4
LT		 10902
10903 /* Enable seeprom accesses. */
10904 tw32_f(GRC_LOCAL_CTRL,
10905 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10906 udelay(100);
10907
10908 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10909 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10910 tp->tg3_flags |= TG3_FLAG_NVRAM;
10911
ec41c7df
MC		 10912 if (tg3_nvram_lock(tp)) {
10913 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10914 "tg3_nvram_init failed.\n", tp->dev->name);
10915 return;
10916 }
e6af301b 10917 tg3_enable_nvram_access(tp);
1da177e4 10918
989a9d23
MC		 10919 tp->nvram_size = 0;
10920
361b4ac2
MC		 10921 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10922 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 10923 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10924 tg3_get_5755_nvram_info(tp);
d30cdd28 10925 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 10926 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 10928 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 10929 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10930 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 10931 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10932 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 10933 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10934 tg3_get_57780_nvram_info(tp);
361b4ac2
MC		 10935 else
10936 tg3_get_nvram_info(tp);
10937
989a9d23
MC		 10938 if (tp->nvram_size == 0)
10939 tg3_get_nvram_size(tp);
1da177e4 10940
e6af301b 10941 tg3_disable_nvram_access(tp);
381291b7 10942 tg3_nvram_unlock(tp);
1da177e4
LT		 10943
10944 } else {
10945 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10946
10947 tg3_get_eeprom_size(tp);
10948 }
10949}
10950
1da177e4
LT		 10951static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10952 u32 offset, u32 len, u8 *buf)
10953{
10954 int i, j, rc = 0;
10955 u32 val;
10956
10957 for (i = 0; i < len; i += 4) {
b9fc7dc5 10958 u32 addr;
a9dc529d 10959 __be32 data;
1da177e4
LT		 10960
10961 addr = offset + i;
10962
10963 memcpy(&data, buf + i, 4);
10964
62cedd11
MC		 10965 /*
10966 * The SEEPROM interface expects the data to always be opposite
10967 * the native endian format. We accomplish this by reversing
10968 * all the operations that would have been performed on the
10969 * data from a call to tg3_nvram_read_be32().
10970 */
10971 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 10972
10973 val = tr32(GRC_EEPROM_ADDR);
10974 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10975
10976 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10977 EEPROM_ADDR_READ);
10978 tw32(GRC_EEPROM_ADDR, val |
10979 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10980 (addr & EEPROM_ADDR_ADDR_MASK) |
10981 EEPROM_ADDR_START |
10982 EEPROM_ADDR_WRITE);
6aa20a22 10983
9d57f01c 10984 for (j = 0; j < 1000; j++) {
1da177e4
LT		 10985 val = tr32(GRC_EEPROM_ADDR);
10986
10987 if (val & EEPROM_ADDR_COMPLETE)
10988 break;
9d57f01c 10989 msleep(1);
1da177e4
LT		 10990 }
10991 if (!(val & EEPROM_ADDR_COMPLETE)) {
10992 rc = -EBUSY;
10993 break;
10994 }
10995 }
10996
10997 return rc;
10998}
10999
11000/* offset and length are dword aligned */
11001static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11002 u8 *buf)
11003{
11004 int ret = 0;
11005 u32 pagesize = tp->nvram_pagesize;
11006 u32 pagemask = pagesize - 1;
11007 u32 nvram_cmd;
11008 u8 *tmp;
11009
11010 tmp = kmalloc(pagesize, GFP_KERNEL);
11011 if (tmp == NULL)
11012 return -ENOMEM;
11013
11014 while (len) {
11015 int j;
e6af301b 11016 u32 phy_addr, page_off, size;
1da177e4
LT		 11017
11018 phy_addr = offset & ~pagemask;
6aa20a22 11019
1da177e4 11020 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11021 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11022 (__be32 *) (tmp + j));
11023 if (ret)
1da177e4
LT		 11024 break;
11025 }
11026 if (ret)
11027 break;
11028
11029 page_off = offset & pagemask;
11030 size = pagesize;
11031 if (len < size)
11032 size = len;
11033
11034 len -= size;
11035
11036 memcpy(tmp + page_off, buf, size);
11037
11038 offset = offset + (pagesize - page_off);
11039
e6af301b 11040 tg3_enable_nvram_access(tp);
1da177e4
LT		 11041
11042 /*
11043 * Before we can erase the flash page, we need
11044 * to issue a special "write enable" command.
11045 */
11046 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11047
11048 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11049 break;
11050
11051 /* Erase the target page */
11052 tw32(NVRAM_ADDR, phy_addr);
11053
11054 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11055 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11056
11057 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11058 break;
11059
11060 /* Issue another write enable to start the write. */
11061 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11062
11063 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11064 break;
11065
11066 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11067 __be32 data;
1da177e4 11068
b9fc7dc5 11069 data = *((__be32 *) (tmp + j));
a9dc529d 11070
b9fc7dc5 11071 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11072
11073 tw32(NVRAM_ADDR, phy_addr + j);
11074
11075 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11076 NVRAM_CMD_WR;
11077
11078 if (j == 0)
11079 nvram_cmd |= NVRAM_CMD_FIRST;
11080 else if (j == (pagesize - 4))
11081 nvram_cmd |= NVRAM_CMD_LAST;
11082
11083 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11084 break;
11085 }
11086 if (ret)
11087 break;
11088 }
11089
11090 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11091 tg3_nvram_exec_cmd(tp, nvram_cmd);
11092
11093 kfree(tmp);
11094
11095 return ret;
11096}
11097
11098/* offset and length are dword aligned */
11099static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11100 u8 *buf)
11101{
11102 int i, ret = 0;
11103
11104 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11105 u32 page_off, phy_addr, nvram_cmd;
11106 __be32 data;
1da177e4
LT		 11107
11108 memcpy(&data, buf + i, 4);
b9fc7dc5 11109 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11110
11111 page_off = offset % tp->nvram_pagesize;
11112
1820180b 11113 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11114
11115 tw32(NVRAM_ADDR, phy_addr);
11116
11117 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11118
11119 if ((page_off == 0) || (i == 0))
11120 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11121 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11122 nvram_cmd |= NVRAM_CMD_LAST;
11123
11124 if (i == (len - 4))
11125 nvram_cmd |= NVRAM_CMD_LAST;
11126
321d32a0
MC		 11127 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11128 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11129 (tp->nvram_jedecnum == JEDEC_ST) &&
11130 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11131
11132 if ((ret = tg3_nvram_exec_cmd(tp,
11133 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11134 NVRAM_CMD_DONE)))
11135
11136 break;
11137 }
11138 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11139 /* We always do complete word writes to eeprom. */
11140 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11141 }
11142
11143 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11144 break;
11145 }
11146 return ret;
11147}
11148
11149/* offset and length are dword aligned */
11150static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11151{
11152 int ret;
11153
1da177e4 11154 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11155 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11156 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11157 udelay(40);
11158 }
11159
11160 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11161 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11162 }
11163 else {
11164 u32 grc_mode;
11165
ec41c7df
MC		 11166 ret = tg3_nvram_lock(tp);
11167 if (ret)
11168 return ret;
1da177e4 11169
e6af301b
MC		 11170 tg3_enable_nvram_access(tp);
11171 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11172 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11173 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11174
11175 grc_mode = tr32(GRC_MODE);
11176 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11177
11178 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11179 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11180
11181 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11182 buf);
11183 }
11184 else {
11185 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11186 buf);
11187 }
11188
11189 grc_mode = tr32(GRC_MODE);
11190 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11191
e6af301b 11192 tg3_disable_nvram_access(tp);
1da177e4
LT		 11193 tg3_nvram_unlock(tp);
11194 }
11195
11196 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11197 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11198 udelay(40);
11199 }
11200
11201 return ret;
11202}
11203
11204struct subsys_tbl_ent {
11205 u16 subsys_vendor, subsys_devid;
11206 u32 phy_id;
11207};
11208
11209static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11210 /* Broadcom boards. */
11211 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11212 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11213 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11214 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11215 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11216 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11217 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11218 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11219 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11220 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11221 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11222
11223 /* 3com boards. */
11224 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11225 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11226 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11227 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11228 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11229
11230 /* DELL boards. */
11231 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11232 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11233 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11234 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11235
11236 /* Compaq boards. */
11237 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11238 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11239 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11240 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11241 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11242
11243 /* IBM boards. */
11244 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11245};
11246
11247static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11248{
11249 int i;
11250
11251 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11252 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11253 tp->pdev->subsystem_vendor) &&
11254 (subsys_id_to_phy_id[i].subsys_devid ==
11255 tp->pdev->subsystem_device))
11256 return &subsys_id_to_phy_id[i];
11257 }
11258 return NULL;
11259}
11260
7d0c41ef 11261static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11262{
1da177e4 11263 u32 val;
caf636c7
MC		 11264 u16 pmcsr;
11265
11266 /* On some early chips the SRAM cannot be accessed in D3hot state,
11267 * so need make sure we're in D0.
11268 */
11269 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11270 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11271 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11272 msleep(1);
7d0c41ef
MC		 11273
11274 /* Make sure register accesses (indirect or otherwise)
11275 * will function correctly.
11276 */
11277 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11278 tp->misc_host_ctrl);
1da177e4 11279
f49639e6
DM		 11280 /* The memory arbiter has to be enabled in order for SRAM accesses
11281 * to succeed. Normally on powerup the tg3 chip firmware will make
11282 * sure it is enabled, but other entities such as system netboot
11283 * code might disable it.
11284 */
11285 val = tr32(MEMARB_MODE);
11286 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11287
1da177e4 11288 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11289 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11290
a85feb8c
GZ		 11291 /* Assume an onboard device and WOL capable by default. */
11292 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11293
b5d3772c 11294 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11295 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11296 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11297 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11298 }
0527ba35
MC		 11299 val = tr32(VCPU_CFGSHDW);
11300 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11301 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11302 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11303 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11304 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11305 goto done;
b5d3772c
MC		 11306 }
11307
1da177e4
LT		 11308 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11309 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11310 u32 nic_cfg, led_cfg;
a9daf367 11311 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11312 int eeprom_phy_serdes = 0;
1da177e4
LT		 11313
11314 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11315 tp->nic_sram_data_cfg = nic_cfg;
11316
11317 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11318 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11319 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11320 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11321 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11322 (ver > 0) && (ver < 0x100))
11323 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11324
a9daf367
MC		 11325 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11326 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11327
1da177e4
LT		 11328 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11329 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11330 eeprom_phy_serdes = 1;
11331
11332 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11333 if (nic_phy_id != 0) {
11334 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11335 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11336
11337 eeprom_phy_id = (id1 >> 16) << 10;
11338 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11339 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11340 } else
11341 eeprom_phy_id = 0;
11342
7d0c41ef 11343 tp->phy_id = eeprom_phy_id;
747e8f8b 11344 if (eeprom_phy_serdes) {
a4e2b347 11345 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11346 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11347 else
11348 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11349 }
7d0c41ef 11350
cbf46853 11351 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11352 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11353 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11354 else
1da177e4
LT		 11355 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11356
11357 switch (led_cfg) {
11358 default:
11359 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11360 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11361 break;
11362
11363 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11364 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11365 break;
11366
11367 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11368 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11369
11370 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11371 * read on some older 5700/5701 bootcode.
11372 */
11373 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11374 ASIC_REV_5700 ||
11375 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11376 ASIC_REV_5701)
11377 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11378
1da177e4
LT		 11379 break;
11380
11381 case SHASTA_EXT_LED_SHARED:
11382 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11383 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11384 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11385 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11386 LED_CTRL_MODE_PHY_2);
11387 break;
11388
11389 case SHASTA_EXT_LED_MAC:
11390 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11391 break;
11392
11393 case SHASTA_EXT_LED_COMBO:
11394 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11395 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11396 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11397 LED_CTRL_MODE_PHY_2);
11398 break;
11399
855e1111 11400 }
1da177e4
LT		 11401
11402 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11403 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11404 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11405 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11406
b2a5c19c
MC		 11407 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11408 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11409
9d26e213 11410 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11411 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11412 if ((tp->pdev->subsystem_vendor ==
11413 PCI_VENDOR_ID_ARIMA) &&
11414 (tp->pdev->subsystem_device == 0x205a ||
11415 tp->pdev->subsystem_device == 0x2063))
11416 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11417 } else {
f49639e6 11418 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11419 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11420 }
1da177e4
LT		 11421
11422 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11423 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11424 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11425 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11426 }
b2b98d4a
MC		 11427
11428 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11429 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11430 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11431
a85feb8c
GZ		 11432 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11433 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11434 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11435
12dac075 11436 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11437 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11438 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11439
1da177e4
LT		 11440 if (cfg2 & (1 << 17))
11441 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11442
11443 /* serdes signal pre-emphasis in register 0x590 set by */
11444 /* bootcode if bit 18 is set */
11445 if (cfg2 & (1 << 18))
11446 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11447
321d32a0
MC		 11448 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11449 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11450 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11451 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11452
8ed5d97e
MC		 11453 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11454 u32 cfg3;
11455
11456 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11457 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11458 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11459 }
a9daf367
MC		 11460
11461 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11462 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11463 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11464 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11465 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11466 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11467 }
05ac4cb7
MC		 11468done:
11469 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11470 device_set_wakeup_enable(&tp->pdev->dev,
11471 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11472}
11473
b2a5c19c
MC		 11474static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11475{
11476 int i;
11477 u32 val;
11478
11479 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11480 tw32(OTP_CTRL, cmd);
11481
11482 /* Wait for up to 1 ms for command to execute. */
11483 for (i = 0; i < 100; i++) {
11484 val = tr32(OTP_STATUS);
11485 if (val & OTP_STATUS_CMD_DONE)
11486 break;
11487 udelay(10);
11488 }
11489
11490 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11491}
11492
11493/* Read the gphy configuration from the OTP region of the chip. The gphy
11494 * configuration is a 32-bit value that straddles the alignment boundary.
11495 * We do two 32-bit reads and then shift and merge the results.
11496 */
11497static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11498{
11499 u32 bhalf_otp, thalf_otp;
11500
11501 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11502
11503 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11504 return 0;
11505
11506 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11507
11508 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11509 return 0;
11510
11511 thalf_otp = tr32(OTP_READ_DATA);
11512
11513 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11514
11515 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11516 return 0;
11517
11518 bhalf_otp = tr32(OTP_READ_DATA);
11519
11520 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11521}
11522
7d0c41ef
MC		 11523static int __devinit tg3_phy_probe(struct tg3 *tp)
11524{
11525 u32 hw_phy_id_1, hw_phy_id_2;
11526 u32 hw_phy_id, hw_phy_id_masked;
11527 int err;
1da177e4 11528
b02fd9e3
MC		 11529 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11530 return tg3_phy_init(tp);
11531
1da177e4 11532 /* Reading the PHY ID register can conflict with ASF
877d0310 11533 * firmware access to the PHY hardware.
1da177e4
LT		 11534 */
11535 err = 0;
0d3031d9
MC		 11536 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11537 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11538 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11539 } else {
11540 /* Now read the physical PHY_ID from the chip and verify
11541 * that it is sane. If it doesn't look good, we fall back
11542 * to either the hard-coded table based PHY_ID and failing
11543 * that the value found in the eeprom area.
11544 */
11545 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11546 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11547
11548 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11549 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11550 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11551
11552 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11553 }
11554
11555 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11556 tp->phy_id = hw_phy_id;
11557 if (hw_phy_id_masked == PHY_ID_BCM8002)
11558 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11559 else
11560 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11561 } else {
7d0c41ef
MC		 11562 if (tp->phy_id != PHY_ID_INVALID) {
11563 /* Do nothing, phy ID already set up in
11564 * tg3_get_eeprom_hw_cfg().
11565 */
1da177e4
LT		 11566 } else {
11567 struct subsys_tbl_ent *p;
11568
11569 /* No eeprom signature? Try the hardcoded
11570 * subsys device table.
11571 */
11572 p = lookup_by_subsys(tp);
11573 if (!p)
11574 return -ENODEV;
11575
11576 tp->phy_id = p->phy_id;
11577 if (!tp->phy_id ||
11578 tp->phy_id == PHY_ID_BCM8002)
11579 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11580 }
11581 }
11582
747e8f8b 11583 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 11584 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 11585 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 11586 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 11587
11588 tg3_readphy(tp, MII_BMSR, &bmsr);
11589 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11590 (bmsr & BMSR_LSTATUS))
11591 goto skip_phy_reset;
6aa20a22 11592
1da177e4
LT		 11593 err = tg3_phy_reset(tp);
11594 if (err)
11595 return err;
11596
11597 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11598 ADVERTISE_100HALF | ADVERTISE_100FULL |
11599 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11600 tg3_ctrl = 0;
11601 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11602 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11603 MII_TG3_CTRL_ADV_1000_FULL);
11604 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11605 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11606 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11607 MII_TG3_CTRL_ENABLE_AS_MASTER);
11608 }
11609
3600d918
MC		 11610 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11611 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11612 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11613 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 11614 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11615
11616 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11617 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11618
11619 tg3_writephy(tp, MII_BMCR,
11620 BMCR_ANENABLE | BMCR_ANRESTART);
11621 }
11622 tg3_phy_set_wirespeed(tp);
11623
11624 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11625 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11626 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11627 }
11628
11629skip_phy_reset:
11630 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11631 err = tg3_init_5401phy_dsp(tp);
11632 if (err)
11633 return err;
11634 }
11635
11636 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11637 err = tg3_init_5401phy_dsp(tp);
11638 }
11639
747e8f8b 11640 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 11641 tp->link_config.advertising =
11642 (ADVERTISED_1000baseT_Half |
11643 ADVERTISED_1000baseT_Full |
11644 ADVERTISED_Autoneg |
11645 ADVERTISED_FIBRE);
11646 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11647 tp->link_config.advertising &=
11648 ~(ADVERTISED_1000baseT_Half |
11649 ADVERTISED_1000baseT_Full);
11650
11651 return err;
11652}
11653
11654static void __devinit tg3_read_partno(struct tg3 *tp)
11655{
6d348f2c 11656 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 11657 unsigned int i;
1b27777a 11658 u32 magic;
1da177e4 11659
df259d8c
MC		 11660 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11661 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 11662 goto out_not_found;
1da177e4 11663
1820180b 11664 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 11665 for (i = 0; i < 256; i += 4) {
11666 u32 tmp;
1da177e4 11667
6d348f2c
MC		 11668 /* The data is in little-endian format in NVRAM.
11669 * Use the big-endian read routines to preserve
11670 * the byte order as it exists in NVRAM.
11671 */
11672 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 11673 goto out_not_found;
11674
6d348f2c 11675 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 11676 }
11677 } else {
11678 int vpd_cap;
11679
11680 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11681 for (i = 0; i < 256; i += 4) {
11682 u32 tmp, j = 0;
b9fc7dc5 11683 __le32 v;
1b27777a
MC		 11684 u16 tmp16;
11685
11686 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11687 i);
11688 while (j++ < 100) {
11689 pci_read_config_word(tp->pdev, vpd_cap +
11690 PCI_VPD_ADDR, &tmp16);
11691 if (tmp16 & 0x8000)
11692 break;
11693 msleep(1);
11694 }
f49639e6
DM		 11695 if (!(tmp16 & 0x8000))
11696 goto out_not_found;
11697
1b27777a
MC		 11698 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11699 &tmp);
b9fc7dc5 11700 v = cpu_to_le32(tmp);
6d348f2c 11701 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 11702 }
1da177e4
LT		 11703 }
11704
11705 /* Now parse and find the part number. */
af2c6a4a 11706 for (i = 0; i < 254; ) {
1da177e4 11707 unsigned char val = vpd_data[i];
af2c6a4a 11708 unsigned int block_end;
1da177e4
LT		 11709
11710 if (val == 0x82 || val == 0x91) {
11711 i = (i + 3 +
11712 (vpd_data[i + 1] +
11713 (vpd_data[i + 2] << 8)));
11714 continue;
11715 }
11716
11717 if (val != 0x90)
11718 goto out_not_found;
11719
11720 block_end = (i + 3 +
11721 (vpd_data[i + 1] +
11722 (vpd_data[i + 2] << 8)));
11723 i += 3;
af2c6a4a
MC		 11724
11725 if (block_end > 256)
11726 goto out_not_found;
11727
11728 while (i < (block_end - 2)) {
1da177e4
LT		 11729 if (vpd_data[i + 0] == 'P' &&
11730 vpd_data[i + 1] == 'N') {
11731 int partno_len = vpd_data[i + 2];
11732
af2c6a4a
MC		 11733 i += 3;
11734 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 11735 goto out_not_found;
11736
11737 memcpy(tp->board_part_number,
af2c6a4a 11738 &vpd_data[i], partno_len);
1da177e4
LT		 11739
11740 /* Success. */
11741 return;
11742 }
af2c6a4a 11743 i += 3 + vpd_data[i + 2];
1da177e4
LT		 11744 }
11745
11746 /* Part number not found. */
11747 goto out_not_found;
11748 }
11749
11750out_not_found:
b5d3772c
MC		 11751 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11752 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 11753 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11754 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11755 strcpy(tp->board_part_number, "BCM57780");
11756 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11757 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11758 strcpy(tp->board_part_number, "BCM57760");
11759 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11760 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11761 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 11762 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11763 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11764 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 11765 else
11766 strcpy(tp->board_part_number, "none");
1da177e4
LT		 11767}
11768
9c8a620e
MC		 11769static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11770{
11771 u32 val;
11772
e4f34110 11773 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 11774 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 11775 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 11776 val != 0)
11777 return 0;
11778
11779 return 1;
11780}
11781
acd9c119
MC		 11782static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11783{
ff3a7cb2 11784 u32 val, offset, start, ver_offset;
acd9c119 11785 int i;
ff3a7cb2 11786 bool newver = false;
acd9c119
MC		 11787
11788 if (tg3_nvram_read(tp, 0xc, &offset) ||
11789 tg3_nvram_read(tp, 0x4, &start))
11790 return;
11791
11792 offset = tg3_nvram_logical_addr(tp, offset);
11793
ff3a7cb2 11794 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 11795 return;
11796
ff3a7cb2
MC		 11797 if ((val & 0xfc000000) == 0x0c000000) {
11798 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 11799 return;
11800
ff3a7cb2
MC		 11801 if (val == 0)
11802 newver = true;
11803 }
11804
11805 if (newver) {
11806 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11807 return;
11808
11809 offset = offset + ver_offset - start;
11810 for (i = 0; i < 16; i += 4) {
11811 __be32 v;
11812 if (tg3_nvram_read_be32(tp, offset + i, &v))
11813 return;
11814
11815 memcpy(tp->fw_ver + i, &v, sizeof(v));
11816 }
11817 } else {
11818 u32 major, minor;
11819
11820 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11821 return;
11822
11823 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11824 TG3_NVM_BCVER_MAJSFT;
11825 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11826 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 11827 }
11828}
11829
a6f6cb1c
MC		 11830static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11831{
11832 u32 val, major, minor;
11833
11834 /* Use native endian representation */
11835 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11836 return;
11837
11838 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11839 TG3_NVM_HWSB_CFG1_MAJSFT;
11840 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11841 TG3_NVM_HWSB_CFG1_MINSFT;
11842
11843 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11844}
11845
dfe00d7d
MC		 11846static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11847{
11848 u32 offset, major, minor, build;
11849
11850 tp->fw_ver[0] = 's';
11851 tp->fw_ver[1] = 'b';
11852 tp->fw_ver[2] = '\0';
11853
11854 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11855 return;
11856
11857 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11858 case TG3_EEPROM_SB_REVISION_0:
11859 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11860 break;
11861 case TG3_EEPROM_SB_REVISION_2:
11862 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11863 break;
11864 case TG3_EEPROM_SB_REVISION_3:
11865 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11866 break;
11867 default:
11868 return;
11869 }
11870
e4f34110 11871 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 11872 return;
11873
11874 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11875 TG3_EEPROM_SB_EDH_BLD_SHFT;
11876 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11877 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11878 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11879
11880 if (minor > 99 || build > 26)
11881 return;
11882
11883 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11884
11885 if (build > 0) {
11886 tp->fw_ver[8] = 'a' + build - 1;
11887 tp->fw_ver[9] = '\0';
11888 }
11889}
11890
acd9c119 11891static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 11892{
11893 u32 val, offset, start;
acd9c119 11894 int i, vlen;
9c8a620e
MC		 11895
11896 for (offset = TG3_NVM_DIR_START;
11897 offset < TG3_NVM_DIR_END;
11898 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 11899 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 11900 return;
11901
9c8a620e
MC		 11902 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11903 break;
11904 }
11905
11906 if (offset == TG3_NVM_DIR_END)
11907 return;
11908
11909 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11910 start = 0x08000000;
e4f34110 11911 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 11912 return;
11913
e4f34110 11914 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 11915 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 11916 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 11917 return;
11918
11919 offset += val - start;
11920
acd9c119 11921 vlen = strlen(tp->fw_ver);
9c8a620e 11922
acd9c119
MC		 11923 tp->fw_ver[vlen++] = ',';
11924 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 11925
11926 for (i = 0; i < 4; i++) {
a9dc529d
MC		 11927 __be32 v;
11928 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 11929 return;
11930
b9fc7dc5 11931 offset += sizeof(v);
c4e6575c 11932
acd9c119
MC		 11933 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11934 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 11935 break;
c4e6575c 11936 }
9c8a620e 11937
acd9c119
MC		 11938 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11939 vlen += sizeof(v);
c4e6575c 11940 }
acd9c119
MC		 11941}
11942
7fd76445
MC		 11943static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11944{
11945 int vlen;
11946 u32 apedata;
11947
11948 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11949 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11950 return;
11951
11952 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11953 if (apedata != APE_SEG_SIG_MAGIC)
11954 return;
11955
11956 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11957 if (!(apedata & APE_FW_STATUS_READY))
11958 return;
11959
11960 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11961
11962 vlen = strlen(tp->fw_ver);
11963
11964 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11965 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11966 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11967 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11968 (apedata & APE_FW_VERSION_BLDMSK));
11969}
11970
acd9c119
MC		 11971static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11972{
11973 u32 val;
11974
df259d8c
MC		 11975 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11976 tp->fw_ver[0] = 's';
11977 tp->fw_ver[1] = 'b';
11978 tp->fw_ver[2] = '\0';
11979
11980 return;
11981 }
11982
acd9c119
MC		 11983 if (tg3_nvram_read(tp, 0, &val))
11984 return;
11985
11986 if (val == TG3_EEPROM_MAGIC)
11987 tg3_read_bc_ver(tp);
11988 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11989 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 11990 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11991 tg3_read_hwsb_ver(tp);
acd9c119
MC		 11992 else
11993 return;
11994
11995 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11996 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11997 return;
11998
11999 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12000
12001 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12002}
12003
7544b097
MC		 12004static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12005
1da177e4
LT		 12006static int __devinit tg3_get_invariants(struct tg3 *tp)
12007{
12008 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12009 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12010 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12011 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12012 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12013 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12014 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12015 { },
12016 };
12017 u32 misc_ctrl_reg;
1da177e4
LT		 12018 u32 pci_state_reg, grc_misc_cfg;
12019 u32 val;
12020 u16 pci_cmd;
5e7dfd0f 12021 int err;
1da177e4 12022
1da177e4
LT		 12023 /* Force memory write invalidate off. If we leave it on,
12024 * then on 5700_BX chips we have to enable a workaround.
12025 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12026 * to match the cacheline size. The Broadcom driver have this
12027 * workaround but turns MWI off all the times so never uses
12028 * it. This seems to suggest that the workaround is insufficient.
12029 */
12030 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12031 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12032 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12033
12034 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12035 * has the register indirect write enable bit set before
12036 * we try to access any of the MMIO registers. It is also
12037 * critical that the PCI-X hw workaround situation is decided
12038 * before that as well.
12039 */
12040 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12041 &misc_ctrl_reg);
12042
12043 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12044 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12046 u32 prod_id_asic_rev;
12047
12048 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12049 &prod_id_asic_rev);
321d32a0 12050 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12051 }
1da177e4 12052
ff645bec
MC		 12053 /* Wrong chip ID in 5752 A0. This code can be removed later
12054 * as A0 is not in production.
12055 */
12056 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12057 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12058
6892914f
MC		 12059 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12060 * we need to disable memory and use config. cycles
12061 * only to access all registers. The 5702/03 chips
12062 * can mistakenly decode the special cycles from the
12063 * ICH chipsets as memory write cycles, causing corruption
12064 * of register and memory space. Only certain ICH bridges
12065 * will drive special cycles with non-zero data during the
12066 * address phase which can fall within the 5703's address
12067 * range. This is not an ICH bug as the PCI spec allows
12068 * non-zero address during special cycles. However, only
12069 * these ICH bridges are known to drive non-zero addresses
12070 * during special cycles.
12071 *
12072 * Since special cycles do not cross PCI bridges, we only
12073 * enable this workaround if the 5703 is on the secondary
12074 * bus of these ICH bridges.
12075 */
12076 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12077 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12078 static struct tg3_dev_id {
12079 u32 vendor;
12080 u32 device;
12081 u32 rev;
12082 } ich_chipsets[] = {
12083 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12084 PCI_ANY_ID },
12085 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12086 PCI_ANY_ID },
12087 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12088 0xa },
12089 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12090 PCI_ANY_ID },
12091 { },
12092 };
12093 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12094 struct pci_dev *bridge = NULL;
12095
12096 while (pci_id->vendor != 0) {
12097 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12098 bridge);
12099 if (!bridge) {
12100 pci_id++;
12101 continue;
12102 }
12103 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12104 if (bridge->revision > pci_id->rev)
6892914f
MC		 12105 continue;
12106 }
12107 if (bridge->subordinate &&
12108 (bridge->subordinate->number ==
12109 tp->pdev->bus->number)) {
12110
12111 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12112 pci_dev_put(bridge);
12113 break;
12114 }
12115 }
12116 }
12117
41588ba1
MC		 12118 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12119 static struct tg3_dev_id {
12120 u32 vendor;
12121 u32 device;
12122 } bridge_chipsets[] = {
12123 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12124 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12125 { },
12126 };
12127 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12128 struct pci_dev *bridge = NULL;
12129
12130 while (pci_id->vendor != 0) {
12131 bridge = pci_get_device(pci_id->vendor,
12132 pci_id->device,
12133 bridge);
12134 if (!bridge) {
12135 pci_id++;
12136 continue;
12137 }
12138 if (bridge->subordinate &&
12139 (bridge->subordinate->number <=
12140 tp->pdev->bus->number) &&
12141 (bridge->subordinate->subordinate >=
12142 tp->pdev->bus->number)) {
12143 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12144 pci_dev_put(bridge);
12145 break;
12146 }
12147 }
12148 }
12149
4a29cc2e
MC		 12150 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12151 * DMA addresses > 40-bit. This bridge may have other additional
12152 * 57xx devices behind it in some 4-port NIC designs for example.
12153 * Any tg3 device found behind the bridge will also need the 40-bit
12154 * DMA workaround.
12155 */
a4e2b347
MC		 12156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12158 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12159 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12160 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12161 }
4a29cc2e
MC		 12162 else {
12163 struct pci_dev *bridge = NULL;
12164
12165 do {
12166 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12167 PCI_DEVICE_ID_SERVERWORKS_EPB,
12168 bridge);
12169 if (bridge && bridge->subordinate &&
12170 (bridge->subordinate->number <=
12171 tp->pdev->bus->number) &&
12172 (bridge->subordinate->subordinate >=
12173 tp->pdev->bus->number)) {
12174 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12175 pci_dev_put(bridge);
12176 break;
12177 }
12178 } while (bridge);
12179 }
4cf78e4f 12180
1da177e4
LT		 12181 /* Initialize misc host control in PCI block. */
12182 tp->misc_host_ctrl |= (misc_ctrl_reg &
12183 MISC_HOST_CTRL_CHIPREV);
12184 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12185 tp->misc_host_ctrl);
12186
7544b097
MC		 12187 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12188 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12189 tp->pdev_peer = tg3_find_peer(tp);
12190
321d32a0
MC		 12191 /* Intentionally exclude ASIC_REV_5906 */
12192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12193 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12194 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12195 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12196 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
321d32a0
MC		 12197 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12198 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12199
12200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12203 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12204 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12205 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12206
1b440c56
JL		 12207 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12208 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12209 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12210
027455ad
MC		 12211 /* 5700 B0 chips do not support checksumming correctly due
12212 * to hardware bugs.
12213 */
12214 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12215 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12216 else {
12217 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12218 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12219 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12220 tp->dev->features |= NETIF_F_IPV6_CSUM;
12221 }
12222
5a6f3074 12223 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12224 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12225 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12226 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12227 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12228 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12229 tp->pdev_peer == tp->pdev))
12230 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12231
321d32a0 12232 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12233 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12234 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12235 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12236 } else {
7f62ad5d 12237 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12238 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12239 ASIC_REV_5750 &&
12240 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12241 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12242 }
5a6f3074 12243 }
1da177e4 12244
4f125f42
MC		 12245 tp->irq_max = 1;
12246
f51f3562
MC		 12247 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12248 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8f666b07 12249 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12250
52f4490c
MC		 12251 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12252 &pci_state_reg);
12253
5e7dfd0f
MC		 12254 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12255 if (tp->pcie_cap != 0) {
12256 u16 lnkctl;
12257
1da177e4 12258 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12259
12260 pcie_set_readrq(tp->pdev, 4096);
12261
5e7dfd0f
MC		 12262 pci_read_config_word(tp->pdev,
12263 tp->pcie_cap + PCI_EXP_LNKCTL,
12264 &lnkctl);
12265 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12267 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12270 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12271 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12272 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12273 }
52f4490c 12274 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12275 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12276 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12277 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12278 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12279 if (!tp->pcix_cap) {
12280 printk(KERN_ERR PFX "Cannot find PCI-X "
12281 "capability, aborting.\n");
12282 return -EIO;
12283 }
12284
12285 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12286 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12287 }
1da177e4 12288
399de50b
MC		 12289 /* If we have an AMD 762 or VIA K8T800 chipset, write
12290 * reordering to the mailbox registers done by the host
12291 * controller can cause major troubles. We read back from
12292 * every mailbox register write to force the writes to be
12293 * posted to the chip in order.
12294 */
12295 if (pci_dev_present(write_reorder_chipsets) &&
12296 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12297 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12298
69fc4053
MC		 12299 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12300 &tp->pci_cacheline_sz);
12301 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12302 &tp->pci_lat_timer);
1da177e4
LT		 12303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12304 tp->pci_lat_timer < 64) {
12305 tp->pci_lat_timer = 64;
69fc4053
MC		 12306 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12307 tp->pci_lat_timer);
1da177e4
LT		 12308 }
12309
52f4490c
MC		 12310 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12311 /* 5700 BX chips need to have their TX producer index
12312 * mailboxes written twice to workaround a bug.
12313 */
12314 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12315
52f4490c 12316 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12317 *
12318 * The workaround is to use indirect register accesses
12319 * for all chip writes not to mailbox registers.
12320 */
52f4490c 12321 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12322 u32 pm_reg;
1da177e4
LT		 12323
12324 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12325
12326 /* The chip can have it's power management PCI config
12327 * space registers clobbered due to this bug.
12328 * So explicitly force the chip into D0 here.
12329 */
9974a356
MC		 12330 pci_read_config_dword(tp->pdev,
12331 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12332 &pm_reg);
12333 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12334 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12335 pci_write_config_dword(tp->pdev,
12336 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12337 pm_reg);
12338
12339 /* Also, force SERR#/PERR# in PCI command. */
12340 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12341 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12342 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12343 }
12344 }
12345
1da177e4
LT		 12346 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12347 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12348 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12349 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12350
12351 /* Chip-specific fixup from Broadcom driver */
12352 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12353 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12354 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12355 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12356 }
12357
1ee582d8 12358 /* Default fast path register access methods */
20094930 12359 tp->read32 = tg3_read32;
1ee582d8 12360 tp->write32 = tg3_write32;
09ee929c 12361 tp->read32_mbox = tg3_read32;
20094930 12362 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12363 tp->write32_tx_mbox = tg3_write32;
12364 tp->write32_rx_mbox = tg3_write32;
12365
12366 /* Various workaround register access methods */
12367 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12368 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12369 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12370 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12371 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12372 /*
12373 * Back to back register writes can cause problems on these
12374 * chips, the workaround is to read back all reg writes
12375 * except those to mailbox regs.
12376 *
12377 * See tg3_write_indirect_reg32().
12378 */
1ee582d8 12379 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12380 }
12381
1ee582d8
MC		 12382
12383 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12384 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12385 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12386 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12387 tp->write32_rx_mbox = tg3_write_flush_reg32;
12388 }
20094930 12389
6892914f
MC		 12390 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12391 tp->read32 = tg3_read_indirect_reg32;
12392 tp->write32 = tg3_write_indirect_reg32;
12393 tp->read32_mbox = tg3_read_indirect_mbox;
12394 tp->write32_mbox = tg3_write_indirect_mbox;
12395 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12396 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12397
12398 iounmap(tp->regs);
22abe310 12399 tp->regs = NULL;
6892914f
MC		 12400
12401 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12402 pci_cmd &= ~PCI_COMMAND_MEMORY;
12403 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12404 }
b5d3772c
MC		 12405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12406 tp->read32_mbox = tg3_read32_mbox_5906;
12407 tp->write32_mbox = tg3_write32_mbox_5906;
12408 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12409 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12410 }
6892914f 12411
bbadf503
MC		 12412 if (tp->write32 == tg3_write_indirect_reg32 ||
12413 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12414 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12415 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12416 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12417
7d0c41ef 12418 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12419 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12420 * determined before calling tg3_set_power_state() so that
12421 * we know whether or not to switch out of Vaux power.
12422 * When the flag is set, it means that GPIO1 is used for eeprom
12423 * write protect and also implies that it is a LOM where GPIOs
12424 * are not used to switch power.
6aa20a22 12425 */
7d0c41ef
MC		 12426 tg3_get_eeprom_hw_cfg(tp);
12427
0d3031d9
MC		 12428 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12429 /* Allow reads and writes to the
12430 * APE register and memory space.
12431 */
12432 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12433 PCISTATE_ALLOW_APE_SHMEM_WR;
12434 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12435 pci_state_reg);
12436 }
12437
9936bcf6 12438 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12439 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0
MC		 12440 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12441 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 12442 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12443
314fba34
MC		 12444 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12445 * GPIO1 driven high will bring 5700's external PHY out of reset.
12446 * It is also used as eeprom write protect on LOMs.
12447 */
12448 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12449 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12450 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12451 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12452 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12453 /* Unused GPIO3 must be driven as output on 5752 because there
12454 * are no pull-up resistors on unused GPIO pins.
12455 */
12456 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12457 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12458
321d32a0
MC		 12459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12460 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12461 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12462
8d519ab2
MC		 12463 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12464 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12465 /* Turn off the debug UART. */
12466 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12467 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12468 /* Keep VMain power. */
12469 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12470 GRC_LCLCTRL_GPIO_OUTPUT0;
12471 }
12472
1da177e4 12473 /* Force the chip into D0. */
bc1c7567 12474 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12475 if (err) {
12476 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12477 pci_name(tp->pdev));
12478 return err;
12479 }
12480
1da177e4
LT		 12481 /* Derive initial jumbo mode from MTU assigned in
12482 * ether_setup() via the alloc_etherdev() call
12483 */
0f893dc6 12484 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12485 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12486 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12487
12488 /* Determine WakeOnLan speed to use. */
12489 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12490 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12491 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12492 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12493 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12494 } else {
12495 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12496 }
12497
7f97a4bd
MC		 12498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12499 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12500
1da177e4
LT		 12501 /* A few boards don't want Ethernet@WireSpeed phy feature */
12502 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12503 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12504 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12505 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12506 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12507 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12508 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12509
12510 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12511 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12512 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12513 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12514 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12515
321d32a0 12516 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12517 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0
MC		 12518 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12519 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
c424cb24 12520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12522 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12523 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12524 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12525 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12526 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12527 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12528 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12529 } else
c424cb24
MC		 12530 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12531 }
1da177e4 12532
b2a5c19c
MC		 12533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12534 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12535 tp->phy_otp = tg3_read_otp_phycfg(tp);
12536 if (tp->phy_otp == 0)
12537 tp->phy_otp = TG3_OTP_DEFAULT;
12538 }
12539
f51f3562 12540 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 12541 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12542 else
12543 tp->mi_mode = MAC_MI_MODE_BASE;
12544
1da177e4 12545 tp->coalesce_mode = 0;
1da177e4
LT		 12546 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12547 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12548 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12549
321d32a0
MC		 12550 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12551 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 12552 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12553
255ca311
MC		 12554 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12555 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12556 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12557 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12558
158d7abd
MC		 12559 err = tg3_mdio_init(tp);
12560 if (err)
12561 return err;
1da177e4
LT		 12562
12563 /* Initialize data/descriptor byte/word swapping. */
12564 val = tr32(GRC_MODE);
12565 val &= GRC_MODE_HOST_STACKUP;
12566 tw32(GRC_MODE, val | tp->grc_mode);
12567
12568 tg3_switch_clocks(tp);
12569
12570 /* Clear this out for sanity. */
12571 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12572
12573 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12574 &pci_state_reg);
12575 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12576 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12577 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12578
12579 if (chiprevid == CHIPREV_ID_5701_A0 ||
12580 chiprevid == CHIPREV_ID_5701_B0 ||
12581 chiprevid == CHIPREV_ID_5701_B2 ||
12582 chiprevid == CHIPREV_ID_5701_B5) {
12583 void __iomem *sram_base;
12584
12585 /* Write some dummy words into the SRAM status block
12586 * area, see if it reads back correctly. If the return
12587 * value is bad, force enable the PCIX workaround.
12588 */
12589 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12590
12591 writel(0x00000000, sram_base);
12592 writel(0x00000000, sram_base + 4);
12593 writel(0xffffffff, sram_base + 4);
12594 if (readl(sram_base) != 0x00000000)
12595 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12596 }
12597 }
12598
12599 udelay(50);
12600 tg3_nvram_init(tp);
12601
12602 grc_misc_cfg = tr32(GRC_MISC_CFG);
12603 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12604
1da177e4
LT		 12605 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12606 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12607 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12608 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12609
fac9b83e
DM		 12610 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12611 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12612 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12613 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12614 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12615 HOSTCC_MODE_CLRTICK_TXBD);
12616
12617 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12618 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12619 tp->misc_host_ctrl);
12620 }
12621
3bda1258
MC		 12622 /* Preserve the APE MAC_MODE bits */
12623 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12624 tp->mac_mode = tr32(MAC_MODE) |
12625 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12626 else
12627 tp->mac_mode = TG3_DEF_MAC_MODE;
12628
1da177e4
LT		 12629 /* these are limited to 10/100 only */
12630 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12631 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12632 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12633 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12634 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12635 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12636 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12637 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12638 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 12639 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12640 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 12641 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 12642 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 12643 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12644
12645 err = tg3_phy_probe(tp);
12646 if (err) {
12647 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12648 pci_name(tp->pdev), err);
12649 /* ... but do not return immediately ... */
b02fd9e3 12650 tg3_mdio_fini(tp);
1da177e4
LT		 12651 }
12652
12653 tg3_read_partno(tp);
c4e6575c 12654 tg3_read_fw_ver(tp);
1da177e4
LT		 12655
12656 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12657 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12658 } else {
12659 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12660 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12661 else
12662 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12663 }
12664
12665 /* 5700 {AX,BX} chips have a broken status block link
12666 * change bit implementation, so we must use the
12667 * status register in those cases.
12668 */
12669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12670 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12671 else
12672 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12673
12674 /* The led_ctrl is set during tg3_phy_probe, here we might
12675 * have to force the link status polling mechanism based
12676 * upon subsystem IDs.
12677 */
12678 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 12679 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 12680 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12681 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12682 TG3_FLAG_USE_LINKCHG_REG);
12683 }
12684
12685 /* For all SERDES we poll the MAC status register. */
12686 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12687 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12688 else
12689 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12690
ad829268 12691 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 12692 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12693 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12694 tp->rx_offset = 0;
12695
f92905de
MC		 12696 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12697
12698 /* Increment the rx prod index on the rx std ring by at most
12699 * 8 for these chips to workaround hw errata.
12700 */
12701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12704 tp->rx_std_max_post = 8;
12705
8ed5d97e
MC		 12706 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12707 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12708 PCIE_PWR_MGMT_L1_THRESH_MSK;
12709
1da177e4
LT		 12710 return err;
12711}
12712
49b6e95f 12713#ifdef CONFIG_SPARC
1da177e4
LT		 12714static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12715{
12716 struct net_device *dev = tp->dev;
12717 struct pci_dev *pdev = tp->pdev;
49b6e95f 12718 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 12719 const unsigned char *addr;
49b6e95f
DM		 12720 int len;
12721
12722 addr = of_get_property(dp, "local-mac-address", &len);
12723 if (addr && len == 6) {
12724 memcpy(dev->dev_addr, addr, 6);
12725 memcpy(dev->perm_addr, dev->dev_addr, 6);
12726 return 0;
1da177e4
LT		 12727 }
12728 return -ENODEV;
12729}
12730
12731static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12732{
12733 struct net_device *dev = tp->dev;
12734
12735 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 12736 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 12737 return 0;
12738}
12739#endif
12740
12741static int __devinit tg3_get_device_address(struct tg3 *tp)
12742{
12743 struct net_device *dev = tp->dev;
12744 u32 hi, lo, mac_offset;
008652b3 12745 int addr_ok = 0;
1da177e4 12746
49b6e95f 12747#ifdef CONFIG_SPARC
1da177e4
LT		 12748 if (!tg3_get_macaddr_sparc(tp))
12749 return 0;
12750#endif
12751
12752 mac_offset = 0x7c;
f49639e6 12753 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 12754 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 12755 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12756 mac_offset = 0xcc;
12757 if (tg3_nvram_lock(tp))
12758 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12759 else
12760 tg3_nvram_unlock(tp);
12761 }
b5d3772c
MC		 12762 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12763 mac_offset = 0x10;
1da177e4
LT		 12764
12765 /* First try to get it from MAC address mailbox. */
12766 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12767 if ((hi >> 16) == 0x484b) {
12768 dev->dev_addr[0] = (hi >> 8) & 0xff;
12769 dev->dev_addr[1] = (hi >> 0) & 0xff;
12770
12771 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12772 dev->dev_addr[2] = (lo >> 24) & 0xff;
12773 dev->dev_addr[3] = (lo >> 16) & 0xff;
12774 dev->dev_addr[4] = (lo >> 8) & 0xff;
12775 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 12776
008652b3
MC		 12777 /* Some old bootcode may report a 0 MAC address in SRAM */
12778 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12779 }
12780 if (!addr_ok) {
12781 /* Next, try NVRAM. */
df259d8c
MC		 12782 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12783 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 12784 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 12785 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12786 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 12787 }
12788 /* Finally just fetch it out of the MAC control regs. */
12789 else {
12790 hi = tr32(MAC_ADDR_0_HIGH);
12791 lo = tr32(MAC_ADDR_0_LOW);
12792
12793 dev->dev_addr[5] = lo & 0xff;
12794 dev->dev_addr[4] = (lo >> 8) & 0xff;
12795 dev->dev_addr[3] = (lo >> 16) & 0xff;
12796 dev->dev_addr[2] = (lo >> 24) & 0xff;
12797 dev->dev_addr[1] = hi & 0xff;
12798 dev->dev_addr[0] = (hi >> 8) & 0xff;
12799 }
1da177e4
LT		 12800 }
12801
12802 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 12803#ifdef CONFIG_SPARC
1da177e4
LT		 12804 if (!tg3_get_default_macaddr_sparc(tp))
12805 return 0;
12806#endif
12807 return -EINVAL;
12808 }
2ff43697 12809 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 12810 return 0;
12811}
12812
59e6b434
DM		 12813#define BOUNDARY_SINGLE_CACHELINE 1
12814#define BOUNDARY_MULTI_CACHELINE 2
12815
12816static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12817{
12818 int cacheline_size;
12819 u8 byte;
12820 int goal;
12821
12822 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12823 if (byte == 0)
12824 cacheline_size = 1024;
12825 else
12826 cacheline_size = (int) byte * 4;
12827
12828 /* On 5703 and later chips, the boundary bits have no
12829 * effect.
12830 */
12831 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12832 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12833 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12834 goto out;
12835
12836#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12837 goal = BOUNDARY_MULTI_CACHELINE;
12838#else
12839#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12840 goal = BOUNDARY_SINGLE_CACHELINE;
12841#else
12842 goal = 0;
12843#endif
12844#endif
12845
12846 if (!goal)
12847 goto out;
12848
12849 /* PCI controllers on most RISC systems tend to disconnect
12850 * when a device tries to burst across a cache-line boundary.
12851 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12852 *
12853 * Unfortunately, for PCI-E there are only limited
12854 * write-side controls for this, and thus for reads
12855 * we will still get the disconnects. We'll also waste
12856 * these PCI cycles for both read and write for chips
12857 * other than 5700 and 5701 which do not implement the
12858 * boundary bits.
12859 */
12860 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12861 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12862 switch (cacheline_size) {
12863 case 16:
12864 case 32:
12865 case 64:
12866 case 128:
12867 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12868 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12869 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12870 } else {
12871 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12872 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12873 }
12874 break;
12875
12876 case 256:
12877 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12878 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12879 break;
12880
12881 default:
12882 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12883 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12884 break;
855e1111 12885 }
59e6b434
DM		 12886 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12887 switch (cacheline_size) {
12888 case 16:
12889 case 32:
12890 case 64:
12891 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12892 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12893 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12894 break;
12895 }
12896 /* fallthrough */
12897 case 128:
12898 default:
12899 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12900 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12901 break;
855e1111 12902 }
59e6b434
DM		 12903 } else {
12904 switch (cacheline_size) {
12905 case 16:
12906 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12907 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12908 DMA_RWCTRL_WRITE_BNDRY_16);
12909 break;
12910 }
12911 /* fallthrough */
12912 case 32:
12913 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12914 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12915 DMA_RWCTRL_WRITE_BNDRY_32);
12916 break;
12917 }
12918 /* fallthrough */
12919 case 64:
12920 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12921 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12922 DMA_RWCTRL_WRITE_BNDRY_64);
12923 break;
12924 }
12925 /* fallthrough */
12926 case 128:
12927 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12928 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12929 DMA_RWCTRL_WRITE_BNDRY_128);
12930 break;
12931 }
12932 /* fallthrough */
12933 case 256:
12934 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12935 DMA_RWCTRL_WRITE_BNDRY_256);
12936 break;
12937 case 512:
12938 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12939 DMA_RWCTRL_WRITE_BNDRY_512);
12940 break;
12941 case 1024:
12942 default:
12943 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12944 DMA_RWCTRL_WRITE_BNDRY_1024);
12945 break;
855e1111 12946 }
59e6b434
DM		 12947 }
12948
12949out:
12950 return val;
12951}
12952
1da177e4
LT		 12953static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12954{
12955 struct tg3_internal_buffer_desc test_desc;
12956 u32 sram_dma_descs;
12957 int i, ret;
12958
12959 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12960
12961 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12962 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12963 tw32(RDMAC_STATUS, 0);
12964 tw32(WDMAC_STATUS, 0);
12965
12966 tw32(BUFMGR_MODE, 0);
12967 tw32(FTQ_RESET, 0);
12968
12969 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12970 test_desc.addr_lo = buf_dma & 0xffffffff;
12971 test_desc.nic_mbuf = 0x00002100;
12972 test_desc.len = size;
12973
12974 /*
12975 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12976 * the *second* time the tg3 driver was getting loaded after an
12977 * initial scan.
12978 *
12979 * Broadcom tells me:
12980 * ...the DMA engine is connected to the GRC block and a DMA
12981 * reset may affect the GRC block in some unpredictable way...
12982 * The behavior of resets to individual blocks has not been tested.
12983 *
12984 * Broadcom noted the GRC reset will also reset all sub-components.
12985 */
12986 if (to_device) {
12987 test_desc.cqid_sqid = (13 << 8) | 2;
12988
12989 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12990 udelay(40);
12991 } else {
12992 test_desc.cqid_sqid = (16 << 8) | 7;
12993
12994 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12995 udelay(40);
12996 }
12997 test_desc.flags = 0x00000005;
12998
12999 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13000 u32 val;
13001
13002 val = *(((u32 *)&test_desc) + i);
13003 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13004 sram_dma_descs + (i * sizeof(u32)));
13005 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13006 }
13007 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13008
13009 if (to_device) {
13010 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13011 } else {
13012 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13013 }
13014
13015 ret = -ENODEV;
13016 for (i = 0; i < 40; i++) {
13017 u32 val;
13018
13019 if (to_device)
13020 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13021 else
13022 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13023 if ((val & 0xffff) == sram_dma_descs) {
13024 ret = 0;
13025 break;
13026 }
13027
13028 udelay(100);
13029 }
13030
13031 return ret;
13032}
13033
ded7340d 13034#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13035
13036static int __devinit tg3_test_dma(struct tg3 *tp)
13037{
13038 dma_addr_t buf_dma;
59e6b434 13039 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 13040 int ret;
13041
13042 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13043 if (!buf) {
13044 ret = -ENOMEM;
13045 goto out_nofree;
13046 }
13047
13048 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13049 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13050
59e6b434 13051 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 13052
13053 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13054 /* DMA read watermark not used on PCIE */
13055 tp->dma_rwctrl |= 0x00180000;
13056 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13059 tp->dma_rwctrl |= 0x003f0000;
13060 else
13061 tp->dma_rwctrl |= 0x003f000f;
13062 } else {
13063 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13064 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13065 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13066 u32 read_water = 0x7;
1da177e4 13067
4a29cc2e
MC		 13068 /* If the 5704 is behind the EPB bridge, we can
13069 * do the less restrictive ONE_DMA workaround for
13070 * better performance.
13071 */
13072 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13074 tp->dma_rwctrl |= 0x8000;
13075 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13076 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13077
49afdeb6
MC		 13078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13079 read_water = 4;
59e6b434 13080 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13081 tp->dma_rwctrl |=
13082 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13083 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13084 (1 << 23);
4cf78e4f
MC		 13085 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13086 /* 5780 always in PCIX mode */
13087 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13088 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13089 /* 5714 always in PCIX mode */
13090 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13091 } else {
13092 tp->dma_rwctrl |= 0x001b000f;
13093 }
13094 }
13095
13096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13098 tp->dma_rwctrl &= 0xfffffff0;
13099
13100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13102 /* Remove this if it causes problems for some boards. */
13103 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13104
13105 /* On 5700/5701 chips, we need to set this bit.
13106 * Otherwise the chip will issue cacheline transactions
13107 * to streamable DMA memory with not all the byte
13108 * enables turned on. This is an error on several
13109 * RISC PCI controllers, in particular sparc64.
13110 *
13111 * On 5703/5704 chips, this bit has been reassigned
13112 * a different meaning. In particular, it is used
13113 * on those chips to enable a PCI-X workaround.
13114 */
13115 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13116 }
13117
13118 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13119
13120#if 0
13121 /* Unneeded, already done by tg3_get_invariants. */
13122 tg3_switch_clocks(tp);
13123#endif
13124
13125 ret = 0;
13126 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13127 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13128 goto out;
13129
59e6b434
DM		 13130 /* It is best to perform DMA test with maximum write burst size
13131 * to expose the 5700/5701 write DMA bug.
13132 */
13133 saved_dma_rwctrl = tp->dma_rwctrl;
13134 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13135 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13136
1da177e4
LT		 13137 while (1) {
13138 u32 *p = buf, i;
13139
13140 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13141 p[i] = i;
13142
13143 /* Send the buffer to the chip. */
13144 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13145 if (ret) {
13146 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13147 break;
13148 }
13149
13150#if 0
13151 /* validate data reached card RAM correctly. */
13152 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13153 u32 val;
13154 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13155 if (le32_to_cpu(val) != p[i]) {
13156 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13157 /* ret = -ENODEV here? */
13158 }
13159 p[i] = 0;
13160 }
13161#endif
13162 /* Now read it back. */
13163 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13164 if (ret) {
13165 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13166
13167 break;
13168 }
13169
13170 /* Verify it. */
13171 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13172 if (p[i] == i)
13173 continue;
13174
59e6b434
DM		 13175 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13176 DMA_RWCTRL_WRITE_BNDRY_16) {
13177 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13178 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13179 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13180 break;
13181 } else {
13182 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13183 ret = -ENODEV;
13184 goto out;
13185 }
13186 }
13187
13188 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13189 /* Success. */
13190 ret = 0;
13191 break;
13192 }
13193 }
59e6b434
DM		 13194 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13195 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13196 static struct pci_device_id dma_wait_state_chipsets[] = {
13197 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13198 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13199 { },
13200 };
13201
59e6b434 13202 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13203 * now look for chipsets that are known to expose the
13204 * DMA bug without failing the test.
59e6b434 13205 */
6d1cfbab
MC		 13206 if (pci_dev_present(dma_wait_state_chipsets)) {
13207 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13208 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13209 }
13210 else
13211 /* Safe to use the calculated DMA boundary. */
13212 tp->dma_rwctrl = saved_dma_rwctrl;
13213
59e6b434
DM		 13214 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13215 }
1da177e4
LT		 13216
13217out:
13218 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13219out_nofree:
13220 return ret;
13221}
13222
13223static void __devinit tg3_init_link_config(struct tg3 *tp)
13224{
13225 tp->link_config.advertising =
13226 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13227 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13228 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13229 ADVERTISED_Autoneg | ADVERTISED_MII);
13230 tp->link_config.speed = SPEED_INVALID;
13231 tp->link_config.duplex = DUPLEX_INVALID;
13232 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13233 tp->link_config.active_speed = SPEED_INVALID;
13234 tp->link_config.active_duplex = DUPLEX_INVALID;
13235 tp->link_config.phy_is_low_power = 0;
13236 tp->link_config.orig_speed = SPEED_INVALID;
13237 tp->link_config.orig_duplex = DUPLEX_INVALID;
13238 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13239}
13240
13241static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13242{
fdfec172
MC		 13243 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13244 tp->bufmgr_config.mbuf_read_dma_low_water =
13245 DEFAULT_MB_RDMA_LOW_WATER_5705;
13246 tp->bufmgr_config.mbuf_mac_rx_low_water =
13247 DEFAULT_MB_MACRX_LOW_WATER_5705;
13248 tp->bufmgr_config.mbuf_high_water =
13249 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13250 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13251 tp->bufmgr_config.mbuf_mac_rx_low_water =
13252 DEFAULT_MB_MACRX_LOW_WATER_5906;
13253 tp->bufmgr_config.mbuf_high_water =
13254 DEFAULT_MB_HIGH_WATER_5906;
13255 }
fdfec172
MC		 13256
13257 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13258 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13259 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13260 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13261 tp->bufmgr_config.mbuf_high_water_jumbo =
13262 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13263 } else {
13264 tp->bufmgr_config.mbuf_read_dma_low_water =
13265 DEFAULT_MB_RDMA_LOW_WATER;
13266 tp->bufmgr_config.mbuf_mac_rx_low_water =
13267 DEFAULT_MB_MACRX_LOW_WATER;
13268 tp->bufmgr_config.mbuf_high_water =
13269 DEFAULT_MB_HIGH_WATER;
13270
13271 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13272 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13273 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13274 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13275 tp->bufmgr_config.mbuf_high_water_jumbo =
13276 DEFAULT_MB_HIGH_WATER_JUMBO;
13277 }
1da177e4
LT		 13278
13279 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13280 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13281}
13282
13283static char * __devinit tg3_phy_string(struct tg3 *tp)
13284{
13285 switch (tp->phy_id & PHY_ID_MASK) {
13286 case PHY_ID_BCM5400: return "5400";
13287 case PHY_ID_BCM5401: return "5401";
13288 case PHY_ID_BCM5411: return "5411";
13289 case PHY_ID_BCM5701: return "5701";
13290 case PHY_ID_BCM5703: return "5703";
13291 case PHY_ID_BCM5704: return "5704";
13292 case PHY_ID_BCM5705: return "5705";
13293 case PHY_ID_BCM5750: return "5750";
85e94ced 13294 case PHY_ID_BCM5752: return "5752";
a4e2b347 13295 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13296 case PHY_ID_BCM5780: return "5780";
af36e6b6 13297 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13298 case PHY_ID_BCM5787: return "5787";
d30cdd28 13299 case PHY_ID_BCM5784: return "5784";
126a3368 13300 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13301 case PHY_ID_BCM5906: return "5906";
9936bcf6 13302 case PHY_ID_BCM5761: return "5761";
1da177e4
LT		 13303 case PHY_ID_BCM8002: return "8002/serdes";
13304 case 0: return "serdes";
13305 default: return "unknown";
855e1111 13306 }
1da177e4
LT		 13307}
13308
f9804ddb
MC		 13309static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13310{
13311 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13312 strcpy(str, "PCI Express");
13313 return str;
13314 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13315 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13316
13317 strcpy(str, "PCIX:");
13318
13319 if ((clock_ctrl == 7) ||
13320 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13321 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13322 strcat(str, "133MHz");
13323 else if (clock_ctrl == 0)
13324 strcat(str, "33MHz");
13325 else if (clock_ctrl == 2)
13326 strcat(str, "50MHz");
13327 else if (clock_ctrl == 4)
13328 strcat(str, "66MHz");
13329 else if (clock_ctrl == 6)
13330 strcat(str, "100MHz");
f9804ddb
MC		 13331 } else {
13332 strcpy(str, "PCI:");
13333 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13334 strcat(str, "66MHz");
13335 else
13336 strcat(str, "33MHz");
13337 }
13338 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13339 strcat(str, ":32-bit");
13340 else
13341 strcat(str, ":64-bit");
13342 return str;
13343}
13344
8c2dc7e1 13345static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13346{
13347 struct pci_dev *peer;
13348 unsigned int func, devnr = tp->pdev->devfn & ~7;
13349
13350 for (func = 0; func < 8; func++) {
13351 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13352 if (peer && peer != tp->pdev)
13353 break;
13354 pci_dev_put(peer);
13355 }
16fe9d74
MC		 13356 /* 5704 can be configured in single-port mode, set peer to
13357 * tp->pdev in that case.
13358 */
13359 if (!peer) {
13360 peer = tp->pdev;
13361 return peer;
13362 }
1da177e4
LT		 13363
13364 /*
13365 * We don't need to keep the refcount elevated; there's no way
13366 * to remove one half of this device without removing the other
13367 */
13368 pci_dev_put(peer);
13369
13370 return peer;
13371}
13372
15f9850d
DM		 13373static void __devinit tg3_init_coal(struct tg3 *tp)
13374{
13375 struct ethtool_coalesce *ec = &tp->coal;
13376
13377 memset(ec, 0, sizeof(*ec));
13378 ec->cmd = ETHTOOL_GCOALESCE;
13379 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13380 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13381 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13382 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13383 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13384 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13385 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13386 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13387 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13388
13389 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13390 HOSTCC_MODE_CLRTICK_TXBD)) {
13391 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13392 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13393 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13394 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13395 }
d244c892
MC		 13396
13397 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13398 ec->rx_coalesce_usecs_irq = 0;
13399 ec->tx_coalesce_usecs_irq = 0;
13400 ec->stats_block_coalesce_usecs = 0;
13401 }
15f9850d
DM		 13402}
13403
7c7d64b8
SH		 13404static const struct net_device_ops tg3_netdev_ops = {
13405 .ndo_open = tg3_open,
13406 .ndo_stop = tg3_close,
00829823
SH		 13407 .ndo_start_xmit = tg3_start_xmit,
13408 .ndo_get_stats = tg3_get_stats,
13409 .ndo_validate_addr = eth_validate_addr,
13410 .ndo_set_multicast_list = tg3_set_rx_mode,
13411 .ndo_set_mac_address = tg3_set_mac_addr,
13412 .ndo_do_ioctl = tg3_ioctl,
13413 .ndo_tx_timeout = tg3_tx_timeout,
13414 .ndo_change_mtu = tg3_change_mtu,
13415#if TG3_VLAN_TAG_USED
13416 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13417#endif
13418#ifdef CONFIG_NET_POLL_CONTROLLER
13419 .ndo_poll_controller = tg3_poll_controller,
13420#endif
13421};
13422
13423static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13424 .ndo_open = tg3_open,
13425 .ndo_stop = tg3_close,
13426 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13427 .ndo_get_stats = tg3_get_stats,
13428 .ndo_validate_addr = eth_validate_addr,
13429 .ndo_set_multicast_list = tg3_set_rx_mode,
13430 .ndo_set_mac_address = tg3_set_mac_addr,
13431 .ndo_do_ioctl = tg3_ioctl,
13432 .ndo_tx_timeout = tg3_tx_timeout,
13433 .ndo_change_mtu = tg3_change_mtu,
13434#if TG3_VLAN_TAG_USED
13435 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13436#endif
13437#ifdef CONFIG_NET_POLL_CONTROLLER
13438 .ndo_poll_controller = tg3_poll_controller,
13439#endif
13440};
13441
1da177e4
LT		 13442static int __devinit tg3_init_one(struct pci_dev *pdev,
13443 const struct pci_device_id *ent)
13444{
13445 static int tg3_version_printed = 0;
1da177e4
LT		 13446 struct net_device *dev;
13447 struct tg3 *tp;
646c9edd
MC		 13448 int i, err, pm_cap;
13449 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13450 char str[40];
72f2afb8 13451 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13452
13453 if (tg3_version_printed++ == 0)
13454 printk(KERN_INFO "%s", version);
13455
13456 err = pci_enable_device(pdev);
13457 if (err) {
13458 printk(KERN_ERR PFX "Cannot enable PCI device, "
13459 "aborting.\n");
13460 return err;
13461 }
13462
1da177e4
LT		 13463 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13464 if (err) {
13465 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13466 "aborting.\n");
13467 goto err_out_disable_pdev;
13468 }
13469
13470 pci_set_master(pdev);
13471
13472 /* Find power-management capability. */
13473 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13474 if (pm_cap == 0) {
13475 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13476 "aborting.\n");
13477 err = -EIO;
13478 goto err_out_free_res;
13479 }
13480
1da177e4
LT		 13481 dev = alloc_etherdev(sizeof(*tp));
13482 if (!dev) {
13483 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13484 err = -ENOMEM;
13485 goto err_out_free_res;
13486 }
13487
1da177e4
LT		 13488 SET_NETDEV_DEV(dev, &pdev->dev);
13489
1da177e4
LT		 13490#if TG3_VLAN_TAG_USED
13491 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13492#endif
13493
13494 tp = netdev_priv(dev);
13495 tp->pdev = pdev;
13496 tp->dev = dev;
13497 tp->pm_cap = pm_cap;
1da177e4
LT		 13498 tp->rx_mode = TG3_DEF_RX_MODE;
13499 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13500
1da177e4
LT		 13501 if (tg3_debug > 0)
13502 tp->msg_enable = tg3_debug;
13503 else
13504 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13505
13506 /* The word/byte swap controls here control register access byte
13507 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13508 * setting below.
13509 */
13510 tp->misc_host_ctrl =
13511 MISC_HOST_CTRL_MASK_PCI_INT |
13512 MISC_HOST_CTRL_WORD_SWAP |
13513 MISC_HOST_CTRL_INDIR_ACCESS |
13514 MISC_HOST_CTRL_PCISTATE_RW;
13515
13516 /* The NONFRM (non-frame) byte/word swap controls take effect
13517 * on descriptor entries, anything which isn't packet data.
13518 *
13519 * The StrongARM chips on the board (one for tx, one for rx)
13520 * are running in big-endian mode.
13521 */
13522 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13523 GRC_MODE_WSWAP_NONFRM_DATA);
13524#ifdef __BIG_ENDIAN
13525 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13526#endif
13527 spin_lock_init(&tp->lock);
1da177e4 13528 spin_lock_init(&tp->indirect_lock);
c4028958 13529 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13530
d5fe488a 13531 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13532 if (!tp->regs) {
1da177e4
LT		 13533 printk(KERN_ERR PFX "Cannot map device registers, "
13534 "aborting.\n");
13535 err = -ENOMEM;
13536 goto err_out_free_dev;
13537 }
13538
13539 tg3_init_link_config(tp);
13540
1da177e4
LT		 13541 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13542 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 13543
646c9edd
MC		 13544 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13545 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13546 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13547 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13548 struct tg3_napi *tnapi = &tp->napi[i];
13549
13550 tnapi->tp = tp;
13551 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13552
13553 tnapi->int_mbox = intmbx;
13554 if (i < 4)
13555 intmbx += 0x8;
13556 else
13557 intmbx += 0x4;
13558
13559 tnapi->consmbox = rcvmbx;
13560 tnapi->prodmbox = sndmbx;
13561
13562 if (i)
13563 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13564 else
13565 tnapi->coal_now = HOSTCC_MODE_NOW;
13566
13567 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13568 break;
13569
13570 /*
13571 * If we support MSIX, we'll be using RSS. If we're using
13572 * RSS, the first vector only handles link interrupts and the
13573 * remaining vectors handle rx and tx interrupts. Reuse the
13574 * mailbox values for the next iteration. The values we setup
13575 * above are still useful for the single vectored mode.
13576 */
13577 if (!i)
13578 continue;
13579
13580 rcvmbx += 0x8;
13581
13582 if (sndmbx & 0x4)
13583 sndmbx -= 0x4;
13584 else
13585 sndmbx += 0xc;
13586 }
13587
8ef0442f 13588 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 13589 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 13590 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 13591 dev->irq = pdev->irq;
1da177e4
LT		 13592
13593 err = tg3_get_invariants(tp);
13594 if (err) {
13595 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13596 "aborting.\n");
13597 goto err_out_iounmap;
13598 }
13599
321d32a0 13600 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
00829823
SH		 13601 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13602 dev->netdev_ops = &tg3_netdev_ops;
13603 else
13604 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13605
13606
4a29cc2e
MC		 13607 /* The EPB bridge inside 5714, 5715, and 5780 and any
13608 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 13609 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13610 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13611 * do DMA address check in tg3_start_xmit().
13612 */
4a29cc2e 13613 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 13614 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 13615 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 13616 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 13617#ifdef CONFIG_HIGHMEM
6a35528a 13618 dma_mask = DMA_BIT_MASK(64);
72f2afb8 13619#endif
4a29cc2e 13620 } else
6a35528a 13621 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 13622
13623 /* Configure DMA attributes. */
284901a9 13624 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 13625 err = pci_set_dma_mask(pdev, dma_mask);
13626 if (!err) {
13627 dev->features |= NETIF_F_HIGHDMA;
13628 err = pci_set_consistent_dma_mask(pdev,
13629 persist_dma_mask);
13630 if (err < 0) {
13631 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13632 "DMA for consistent allocations\n");
13633 goto err_out_iounmap;
13634 }
13635 }
13636 }
284901a9
YH		 13637 if (err || dma_mask == DMA_BIT_MASK(32)) {
13638 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 13639 if (err) {
13640 printk(KERN_ERR PFX "No usable DMA configuration, "
13641 "aborting.\n");
13642 goto err_out_iounmap;
13643 }
13644 }
13645
fdfec172 13646 tg3_init_bufmgr_config(tp);
1da177e4 13647
077f849d 13648 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 13649 tp->fw_needed = FIRMWARE_TG3;
077f849d 13650
1da177e4
LT		 13651 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13652 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13653 }
13654 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13655 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13656 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 13657 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 13658 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13659 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13660 } else {
7f62ad5d 13661 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 13662 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 13663 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 13664 else
9e9fd12d 13665 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 13666 }
1da177e4 13667
4e3a7aaa
MC		 13668 /* TSO is on by default on chips that support hardware TSO.
13669 * Firmware TSO on older chips gives lower performance, so it
13670 * is off by default, but can be enabled using ethtool.
13671 */
b0026624 13672 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 13673 if (dev->features & NETIF_F_IP_CSUM)
13674 dev->features |= NETIF_F_TSO;
13675 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13676 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 13677 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 13678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13679 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13680 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0
MC		 13681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13682 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 13683 dev->features |= NETIF_F_TSO_ECN;
b0026624 13684 }
1da177e4 13685
1da177e4
LT		 13686
13687 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13688 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13689 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13690 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13691 tp->rx_pending = 63;
13692 }
13693
1da177e4
LT		 13694 err = tg3_get_device_address(tp);
13695 if (err) {
13696 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13697 "aborting.\n");
077f849d 13698 goto err_out_fw;
1da177e4
LT		 13699 }
13700
c88864df 13701 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 13702 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 13703 if (!tp->aperegs) {
c88864df
MC		 13704 printk(KERN_ERR PFX "Cannot map APE registers, "
13705 "aborting.\n");
13706 err = -ENOMEM;
077f849d 13707 goto err_out_fw;
c88864df
MC		 13708 }
13709
13710 tg3_ape_lock_init(tp);
7fd76445
MC		 13711
13712 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13713 tg3_read_dash_ver(tp);
c88864df
MC		 13714 }
13715
1da177e4
LT		 13716 /*
13717 * Reset chip in case UNDI or EFI driver did not shutdown
13718 * DMA self test will enable WDMAC and we'll see (spurious)
13719 * pending DMA on the PCI bus at that point.
13720 */
13721 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13722 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 13723 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 13724 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 13725 }
13726
13727 err = tg3_test_dma(tp);
13728 if (err) {
13729 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 13730 goto err_out_apeunmap;
1da177e4
LT		 13731 }
13732
1da177e4
LT		 13733 /* flow control autonegotiation is default behavior */
13734 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 13735 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 13736
15f9850d
DM		 13737 tg3_init_coal(tp);
13738
c49a1561
MC		 13739 pci_set_drvdata(pdev, dev);
13740
1da177e4
LT		 13741 err = register_netdev(dev);
13742 if (err) {
13743 printk(KERN_ERR PFX "Cannot register net device, "
13744 "aborting.\n");
0d3031d9 13745 goto err_out_apeunmap;
1da177e4
LT		 13746 }
13747
df59c940 13748 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 13749 dev->name,
13750 tp->board_part_number,
13751 tp->pci_chip_rev_id,
f9804ddb 13752 tg3_bus_string(tp, str),
e174961c 13753 dev->dev_addr);
1da177e4 13754
df59c940
MC		 13755 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13756 printk(KERN_INFO
13757 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13758 tp->dev->name,
13759 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
fb28ad35 13760 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
df59c940
MC		 13761 else
13762 printk(KERN_INFO
13763 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13764 tp->dev->name, tg3_phy_string(tp),
13765 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13766 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13767 "10/100/1000Base-T")),
13768 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13769
13770 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 13771 dev->name,
13772 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13773 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13774 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13775 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 13776 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 13777 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13778 dev->name, tp->dma_rwctrl,
284901a9 13779 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 13780 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 13781
13782 return 0;
13783
0d3031d9
MC		 13784err_out_apeunmap:
13785 if (tp->aperegs) {
13786 iounmap(tp->aperegs);
13787 tp->aperegs = NULL;
13788 }
13789
077f849d
JSR		 13790err_out_fw:
13791 if (tp->fw)
13792 release_firmware(tp->fw);
13793
1da177e4 13794err_out_iounmap:
6892914f
MC		 13795 if (tp->regs) {
13796 iounmap(tp->regs);
22abe310 13797 tp->regs = NULL;
6892914f 13798 }
1da177e4
LT		 13799
13800err_out_free_dev:
13801 free_netdev(dev);
13802
13803err_out_free_res:
13804 pci_release_regions(pdev);
13805
13806err_out_disable_pdev:
13807 pci_disable_device(pdev);
13808 pci_set_drvdata(pdev, NULL);
13809 return err;
13810}
13811
13812static void __devexit tg3_remove_one(struct pci_dev *pdev)
13813{
13814 struct net_device *dev = pci_get_drvdata(pdev);
13815
13816 if (dev) {
13817 struct tg3 *tp = netdev_priv(dev);
13818
077f849d
JSR		 13819 if (tp->fw)
13820 release_firmware(tp->fw);
13821
7faa006f 13822 flush_scheduled_work();
158d7abd 13823
b02fd9e3
MC		 13824 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13825 tg3_phy_fini(tp);
158d7abd 13826 tg3_mdio_fini(tp);
b02fd9e3 13827 }
158d7abd 13828
1da177e4 13829 unregister_netdev(dev);
0d3031d9
MC		 13830 if (tp->aperegs) {
13831 iounmap(tp->aperegs);
13832 tp->aperegs = NULL;
13833 }
6892914f
MC		 13834 if (tp->regs) {
13835 iounmap(tp->regs);
22abe310 13836 tp->regs = NULL;
6892914f 13837 }
1da177e4
LT		 13838 free_netdev(dev);
13839 pci_release_regions(pdev);
13840 pci_disable_device(pdev);
13841 pci_set_drvdata(pdev, NULL);
13842 }
13843}
13844
13845static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13846{
13847 struct net_device *dev = pci_get_drvdata(pdev);
13848 struct tg3 *tp = netdev_priv(dev);
12dac075 13849 pci_power_t target_state;
1da177e4
LT		 13850 int err;
13851
3e0c95fd
MC		 13852 /* PCI register 4 needs to be saved whether netif_running() or not.
13853 * MSI address and data need to be saved if using MSI and
13854 * netif_running().
13855 */
13856 pci_save_state(pdev);
13857
1da177e4
LT		 13858 if (!netif_running(dev))
13859 return 0;
13860
7faa006f 13861 flush_scheduled_work();
b02fd9e3 13862 tg3_phy_stop(tp);
1da177e4
LT		 13863 tg3_netif_stop(tp);
13864
13865 del_timer_sync(&tp->timer);
13866
f47c11ee 13867 tg3_full_lock(tp, 1);
1da177e4 13868 tg3_disable_ints(tp);
f47c11ee 13869 tg3_full_unlock(tp);
1da177e4
LT		 13870
13871 netif_device_detach(dev);
13872
f47c11ee 13873 tg3_full_lock(tp, 0);
944d980e 13874 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 13875 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 13876 tg3_full_unlock(tp);
1da177e4 13877
12dac075
RW		 13878 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13879
13880 err = tg3_set_power_state(tp, target_state);
1da177e4 13881 if (err) {
b02fd9e3
MC		 13882 int err2;
13883
f47c11ee 13884 tg3_full_lock(tp, 0);
1da177e4 13885
6a9eba15 13886 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 13887 err2 = tg3_restart_hw(tp, 1);
13888 if (err2)
b9ec6c1b 13889 goto out;
1da177e4
LT		 13890
13891 tp->timer.expires = jiffies + tp->timer_offset;
13892 add_timer(&tp->timer);
13893
13894 netif_device_attach(dev);
13895 tg3_netif_start(tp);
13896
b9ec6c1b 13897out:
f47c11ee 13898 tg3_full_unlock(tp);
b02fd9e3
MC		 13899
13900 if (!err2)
13901 tg3_phy_start(tp);
1da177e4
LT		 13902 }
13903
13904 return err;
13905}
13906
13907static int tg3_resume(struct pci_dev *pdev)
13908{
13909 struct net_device *dev = pci_get_drvdata(pdev);
13910 struct tg3 *tp = netdev_priv(dev);
13911 int err;
13912
3e0c95fd
MC		 13913 pci_restore_state(tp->pdev);
13914
1da177e4
LT		 13915 if (!netif_running(dev))
13916 return 0;
13917
bc1c7567 13918 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13919 if (err)
13920 return err;
13921
13922 netif_device_attach(dev);
13923
f47c11ee 13924 tg3_full_lock(tp, 0);
1da177e4 13925
6a9eba15 13926 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 13927 err = tg3_restart_hw(tp, 1);
13928 if (err)
13929 goto out;
1da177e4
LT		 13930
13931 tp->timer.expires = jiffies + tp->timer_offset;
13932 add_timer(&tp->timer);
13933
1da177e4
LT		 13934 tg3_netif_start(tp);
13935
b9ec6c1b 13936out:
f47c11ee 13937 tg3_full_unlock(tp);
1da177e4 13938
b02fd9e3
MC		 13939 if (!err)
13940 tg3_phy_start(tp);
13941
b9ec6c1b 13942 return err;
1da177e4
LT		 13943}
13944
13945static struct pci_driver tg3_driver = {
13946 .name = DRV_MODULE_NAME,
13947 .id_table = tg3_pci_tbl,
13948 .probe = tg3_init_one,
13949 .remove = __devexit_p(tg3_remove_one),
13950 .suspend = tg3_suspend,
13951 .resume = tg3_resume
13952};
13953
13954static int __init tg3_init(void)
13955{
29917620 13956 return pci_register_driver(&tg3_driver);
1da177e4
LT		 13957}
13958
13959static void __exit tg3_cleanup(void)
13960{
13961 pci_unregister_driver(&tg3_driver);
13962}
13963
13964module_init(tg3_init);
13965module_exit(tg3_cleanup);
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