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tg3: Bypass power source switching for 57765
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
cceea982
MC		 71#define DRV_MODULE_VERSION "3.105"
72#define DRV_MODULE_RELDATE "December 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
13185217
HK		 247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
254 {}
1da177e4
LT		 255};
256
257MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
258
50da859d 259static const struct {
1da177e4
LT		 260 const char string[ETH_GSTRING_LEN];
261} ethtool_stats_keys[TG3_NUM_STATS] = {
262 { "rx_octets" },
263 { "rx_fragments" },
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
267 { "rx_fcs_errors" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
274 { "rx_jabbers" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
288
289 { "tx_octets" },
290 { "tx_collisions" },
291
292 { "tx_xon_sent" },
293 { "tx_xoff_sent" },
294 { "tx_flow_control" },
295 { "tx_mac_errors" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
298 { "tx_deferred" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
319 { "tx_discards" },
320 { "tx_errors" },
321
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
324 { "rxbds_empty" },
325 { "rx_discards" },
326 { "rx_errors" },
327 { "rx_threshold_hit" },
328
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
332
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
335 { "nic_irqs" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
338};
339
50da859d 340static const struct {
4cafd3f5
MC		 341 const char string[ETH_GSTRING_LEN];
342} ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
349};
350
b401e9e2
MC		 351static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
352{
353 writel(val, tp->regs + off);
354}
355
356static u32 tg3_read32(struct tg3 *tp, u32 off)
357{
6aa20a22 358 return (readl(tp->regs + off));
b401e9e2
MC		 359}
360
0d3031d9
MC		 361static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->aperegs + off);
364}
365
366static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
367{
368 return (readl(tp->aperegs + off));
369}
370
1da177e4
LT		 371static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372{
6892914f
MC		 373 unsigned long flags;
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 379}
380
381static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382{
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
1da177e4
LT		 385}
386
6892914f 387static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 388{
6892914f
MC		 389 unsigned long flags;
390 u32 val;
391
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
396 return val;
397}
398
399static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400{
401 unsigned long flags;
402
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
406 return;
407 }
66711e66 408 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
1da177e4 412 }
6892914f
MC		 413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
421 */
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423 (val == 0x1)) {
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426 }
427}
428
429static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430{
431 unsigned long flags;
432 u32 val;
433
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
438 return val;
439}
440
b401e9e2
MC		 441/* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445 */
446static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 447{
b401e9e2
MC		 448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
452 else {
453 /* Posted method */
454 tg3_write32(tp, off, val);
455 if (usec_wait)
456 udelay(usec_wait);
457 tp->read32(tp, off);
458 }
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
461 */
462 if (usec_wait)
463 udelay(usec_wait);
1da177e4
LT		 464}
465
09ee929c
MC		 466static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467{
468 tp->write32_mbox(tp, off, val);
6892914f
MC		 469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
09ee929c
MC		 472}
473
20094930 474static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 475{
476 void __iomem *mbox = tp->regs + off;
477 writel(val, mbox);
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479 writel(val, mbox);
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481 readl(mbox);
482}
483
b5d3772c
MC		 484static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
485{
486 return (readl(tp->regs + off + GRCMBOX_BASE));
487}
488
489static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
490{
491 writel(val, tp->regs + off + GRCMBOX_BASE);
492}
493
20094930 494#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 495#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 496#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 498#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 499
500#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 501#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 503#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 504
505static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
506{
6892914f
MC		 507 unsigned long flags;
508
b5d3772c
MC		 509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
511 return;
512
6892914f 513 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 517
bbadf503
MC		 518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520 } else {
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 523
bbadf503
MC		 524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 }
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 528}
529
1da177e4
LT		 530static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
531{
6892914f
MC		 532 unsigned long flags;
533
b5d3772c
MC		 534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
536 *val = 0;
537 return;
538 }
539
6892914f 540 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 544
bbadf503
MC		 545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547 } else {
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
550
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 }
6892914f 554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 555}
556
0d3031d9
MC		 557static void tg3_ape_lock_init(struct tg3 *tp)
558{
559 int i;
560
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
565}
566
567static int tg3_ape_lock(struct tg3 *tp, int locknum)
568{
569 int i, off;
570 int ret = 0;
571 u32 status;
572
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
574 return 0;
575
576 switch (locknum) {
77b483f1 577 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 578 case TG3_APE_LOCK_MEM:
579 break;
580 default:
581 return -EINVAL;
582 }
583
584 off = 4 * locknum;
585
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
587
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
592 break;
593 udelay(10);
594 }
595
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
600
601 ret = -EBUSY;
602 }
603
604 return ret;
605}
606
607static void tg3_ape_unlock(struct tg3 *tp, int locknum)
608{
609 int off;
610
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
612 return;
613
614 switch (locknum) {
77b483f1 615 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 616 case TG3_APE_LOCK_MEM:
617 break;
618 default:
619 return;
620 }
621
622 off = 4 * locknum;
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
624}
625
1da177e4
LT		 626static void tg3_disable_ints(struct tg3 *tp)
627{
89aeb3bc
MC		 628 int i;
629
1da177e4
LT		 630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 634}
635
1da177e4
LT		 636static void tg3_enable_ints(struct tg3 *tp)
637{
89aeb3bc
MC		 638 int i;
639 u32 coal_now = 0;
640
bbe832c0
MC		 641 tp->irq_sync = 0;
642 wmb();
643
1da177e4
LT		 644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 646
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 652
89aeb3bc
MC		 653 coal_now |= tnapi->coal_now;
654 }
f19af9c2
MC		 655
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
660 else
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 663}
664
17375d25 665static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 666{
17375d25 667 struct tg3 *tp = tnapi->tp;
898a56f8 668 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 669 unsigned int work_exists = 0;
670
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
676 work_exists = 1;
677 }
678 /* check for RX/TX work to do */
f3f3f27e 679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 681 work_exists = 1;
682
683 return work_exists;
684}
685
17375d25 686/* tg3_int_reenable
04237ddd
MC		 687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
6aa20a22 689 * which reenables interrupts
1da177e4 690 */
17375d25 691static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 692{
17375d25
MC		 693 struct tg3 *tp = tnapi->tp;
694
898a56f8 695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 696 mmiowb();
697
fac9b83e
DM		 698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
701 */
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 703 tg3_has_work(tnapi))
04237ddd 704 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 706}
707
fed97810
MC		 708static void tg3_napi_disable(struct tg3 *tp)
709{
710 int i;
711
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
714}
715
716static void tg3_napi_enable(struct tg3 *tp)
717{
718 int i;
719
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
722}
723
1da177e4
LT		 724static inline void tg3_netif_stop(struct tg3 *tp)
725{
bbe832c0 726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 727 tg3_napi_disable(tp);
1da177e4
LT		 728 netif_tx_disable(tp->dev);
729}
730
731static inline void tg3_netif_start(struct tg3 *tp)
732{
fe5f5787
MC		 733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
1da177e4 736 */
fe5f5787
MC		 737 netif_tx_wake_all_queues(tp->dev);
738
fed97810
MC		 739 tg3_napi_enable(tp);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 741 tg3_enable_ints(tp);
1da177e4
LT		 742}
743
744static void tg3_switch_clocks(struct tg3 *tp)
745{
f6eb9b1f 746 u32 clock_ctrl;
1da177e4
LT		 747 u32 orig_clock_ctrl;
748
795d01c5
MC		 749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 751 return;
752
f6eb9b1f
MC		 753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
754
1da177e4
LT		 755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
758 0x1f);
759 tp->pci_clock_ctrl = clock_ctrl;
760
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 765 }
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
768 clock_ctrl |
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
770 40);
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
773 40);
1da177e4 774 }
b401e9e2 775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 776}
777
778#define PHY_BUSY_LOOPS 5000
779
780static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
781{
782 u32 frame_val;
783 unsigned int loops;
784 int ret;
785
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
787 tw32_f(MAC_MI_MODE,
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
789 udelay(80);
790 }
791
792 *val = 0x0;
793
882e9793 794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 799
1da177e4
LT		 800 tw32_f(MAC_MI_COM, frame_val);
801
802 loops = PHY_BUSY_LOOPS;
803 while (loops != 0) {
804 udelay(10);
805 frame_val = tr32(MAC_MI_COM);
806
807 if ((frame_val & MI_COM_BUSY) == 0) {
808 udelay(5);
809 frame_val = tr32(MAC_MI_COM);
810 break;
811 }
812 loops -= 1;
813 }
814
815 ret = -EBUSY;
816 if (loops != 0) {
817 *val = frame_val & MI_COM_DATA_MASK;
818 ret = 0;
819 }
820
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
823 udelay(80);
824 }
825
826 return ret;
827}
828
829static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
830{
831 u32 frame_val;
832 unsigned int loops;
833 int ret;
834
7f97a4bd 835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
837 return 0;
838
1da177e4
LT		 839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
840 tw32_f(MAC_MI_MODE,
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
842 udelay(80);
843 }
844
882e9793 845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 851
1da177e4
LT		 852 tw32_f(MAC_MI_COM, frame_val);
853
854 loops = PHY_BUSY_LOOPS;
855 while (loops != 0) {
856 udelay(10);
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
859 udelay(5);
860 frame_val = tr32(MAC_MI_COM);
861 break;
862 }
863 loops -= 1;
864 }
865
866 ret = -EBUSY;
867 if (loops != 0)
868 ret = 0;
869
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
872 udelay(80);
873 }
874
875 return ret;
876}
877
95e2869a
MC		 878static int tg3_bmcr_reset(struct tg3 *tp)
879{
880 u32 phy_control;
881 int limit, err;
882
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
885 */
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
888 if (err != 0)
889 return -EBUSY;
890
891 limit = 5000;
892 while (limit--) {
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 if ((phy_control & BMCR_RESET) == 0) {
898 udelay(40);
899 break;
900 }
901 udelay(10);
902 }
d4675b52 903 if (limit < 0)
95e2869a
MC		 904 return -EBUSY;
905
906 return 0;
907}
908
158d7abd
MC		 909static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
910{
3d16543d 911 struct tg3 *tp = bp->priv;
158d7abd
MC		 912 u32 val;
913
24bb4fb6 914 spin_lock_bh(&tp->lock);
158d7abd
MC		 915
916 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 917 val = -EIO;
918
919 spin_unlock_bh(&tp->lock);
158d7abd
MC		 920
921 return val;
922}
923
924static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
925{
3d16543d 926 struct tg3 *tp = bp->priv;
24bb4fb6 927 u32 ret = 0;
158d7abd 928
24bb4fb6 929 spin_lock_bh(&tp->lock);
158d7abd
MC		 930
931 if (tg3_writephy(tp, reg, val))
24bb4fb6 932 ret = -EIO;
158d7abd 933
24bb4fb6
MC		 934 spin_unlock_bh(&tp->lock);
935
936 return ret;
158d7abd
MC		 937}
938
939static int tg3_mdio_reset(struct mii_bus *bp)
940{
941 return 0;
942}
943
9c61d6bc 944static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 945{
946 u32 val;
fcb389df 947 struct phy_device *phydev;
a9daf367 948
3f0e3ad7 949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
c73430d0 952 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 953 val = MAC_PHYCFG2_50610_LED_MODES;
954 break;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
957 break;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
960 break;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
963 break;
964 default:
a9daf367 965 return;
fcb389df
MC		 966 }
967
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
970
971 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 975 tw32(MAC_PHYCFG1, val);
976
977 return;
978 }
979
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
987
988 tw32(MAC_PHYCFG2, val);
a9daf367 989
bb85fbb6
MC		 990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
998 }
bb85fbb6
MC		 999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
a9daf367 1002
a9daf367
MC		 1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
fcb389df 1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1021 }
1022 tw32(MAC_EXT_RGMII_MODE, val);
1023}
1024
158d7abd
MC		 1025static void tg3_mdio_start(struct tg3 *tp)
1026{
158d7abd
MC		 1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1029 udelay(80);
a9daf367 1030
882e9793
MC		 1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1033
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035 if (funcnum)
1036 tp->phy_addr = 2;
1037 else
1038 tp->phy_addr = 1;
1039
1040 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041 if (is_serdes)
1042 tp->phy_addr += 7;
1043 } else
3f0e3ad7 1044 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1045
9c61d6bc
MC		 1046 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048 tg3_mdio_config_5785(tp);
158d7abd
MC		 1049}
1050
158d7abd
MC		 1051static int tg3_mdio_init(struct tg3 *tp)
1052{
1053 int i;
1054 u32 reg;
a9daf367 1055 struct phy_device *phydev;
158d7abd
MC		 1056
1057 tg3_mdio_start(tp);
1058
1059 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061 return 0;
1062
298cf9be
LB		 1063 tp->mdio_bus = mdiobus_alloc();
1064 if (tp->mdio_bus == NULL)
1065 return -ENOMEM;
158d7abd 1066
298cf9be
LB		 1067 tp->mdio_bus->name = "tg3 mdio bus";
1068 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1069 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1070 tp->mdio_bus->priv = tp;
1071 tp->mdio_bus->parent = &tp->pdev->dev;
1072 tp->mdio_bus->read = &tg3_mdio_read;
1073 tp->mdio_bus->write = &tg3_mdio_write;
1074 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1075 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1076 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1077
1078 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1079 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1080
1081 /* The bus registration will look for all the PHYs on the mdio bus.
1082 * Unfortunately, it does not ensure the PHY is powered up before
1083 * accessing the PHY ID registers. A chip reset is the
1084 * quickest way to bring the device back to an operational state..
1085 */
1086 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087 tg3_bmcr_reset(tp);
1088
298cf9be 1089 i = mdiobus_register(tp->mdio_bus);
a9daf367 1090 if (i) {
158d7abd
MC		 1091 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092 tp->dev->name, i);
9c61d6bc 1093 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1094 return i;
1095 }
158d7abd 1096
3f0e3ad7 1097 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1098
9c61d6bc
MC		 1099 if (!phydev || !phydev->drv) {
1100 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101 mdiobus_unregister(tp->mdio_bus);
1102 mdiobus_free(tp->mdio_bus);
1103 return -ENODEV;
1104 }
1105
1106 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1107 case TG3_PHY_ID_BCM57780:
1108 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1109 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1110 break;
a9daf367 1111 case TG3_PHY_ID_BCM50610:
c73430d0 1112 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1113 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1114 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1115 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1116 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1117 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1123 /* fallthru */
1124 case TG3_PHY_ID_RTL8211C:
1125 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1126 break;
fcb389df 1127 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1128 case TG3_PHY_ID_BCMAC131:
1129 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1130 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1131 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1132 break;
1133 }
1134
9c61d6bc
MC		 1135 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138 tg3_mdio_config_5785(tp);
a9daf367
MC		 1139
1140 return 0;
158d7abd
MC		 1141}
1142
1143static void tg3_mdio_fini(struct tg3 *tp)
1144{
1145 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1147 mdiobus_unregister(tp->mdio_bus);
1148 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1149 }
1150}
1151
4ba526ce
MC		 1152/* tp->lock is held. */
1153static inline void tg3_generate_fw_event(struct tg3 *tp)
1154{
1155 u32 val;
1156
1157 val = tr32(GRC_RX_CPU_EVENT);
1158 val |= GRC_RX_CPU_DRIVER_EVENT;
1159 tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161 tp->last_event_jiffies = jiffies;
1162}
1163
1164#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
95e2869a
MC		 1166/* tp->lock is held. */
1167static void tg3_wait_for_event_ack(struct tg3 *tp)
1168{
1169 int i;
4ba526ce
MC		 1170 unsigned int delay_cnt;
1171 long time_remain;
1172
1173 /* If enough time has passed, no wait is necessary. */
1174 time_remain = (long)(tp->last_event_jiffies + 1 +
1175 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176 (long)jiffies;
1177 if (time_remain < 0)
1178 return;
1179
1180 /* Check if we can shorten the wait time. */
1181 delay_cnt = jiffies_to_usecs(time_remain);
1182 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1185
4ba526ce 1186 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1187 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188 break;
4ba526ce 1189 udelay(8);
95e2869a
MC		 1190 }
1191}
1192
1193/* tp->lock is held. */
1194static void tg3_ump_link_report(struct tg3 *tp)
1195{
1196 u32 reg;
1197 u32 val;
1198
1199 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1201 return;
1202
1203 tg3_wait_for_event_ack(tp);
1204
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209 val = 0;
1210 if (!tg3_readphy(tp, MII_BMCR, &reg))
1211 val = reg << 16;
1212 if (!tg3_readphy(tp, MII_BMSR, &reg))
1213 val |= (reg & 0xffff);
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216 val = 0;
1217 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218 val = reg << 16;
1219 if (!tg3_readphy(tp, MII_LPA, &reg))
1220 val |= (reg & 0xffff);
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223 val = 0;
1224 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226 val = reg << 16;
1227 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228 val |= (reg & 0xffff);
1229 }
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233 val = reg << 16;
1234 else
1235 val = 0;
1236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
4ba526ce 1238 tg3_generate_fw_event(tp);
95e2869a
MC		 1239}
1240
1241static void tg3_link_report(struct tg3 *tp)
1242{
1243 if (!netif_carrier_ok(tp->dev)) {
1244 if (netif_msg_link(tp))
1245 printk(KERN_INFO PFX "%s: Link is down.\n",
1246 tp->dev->name);
1247 tg3_ump_link_report(tp);
1248 } else if (netif_msg_link(tp)) {
1249 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250 tp->dev->name,
1251 (tp->link_config.active_speed == SPEED_1000 ?
1252 1000 :
1253 (tp->link_config.active_speed == SPEED_100 ?
1254 100 : 10)),
1255 (tp->link_config.active_duplex == DUPLEX_FULL ?
1256 "full" : "half"));
1257
1258 printk(KERN_INFO PFX
1259 "%s: Flow control is %s for TX and %s for RX.\n",
1260 tp->dev->name,
e18ce346 1261 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1262 "on" : "off",
e18ce346 1263 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1264 "on" : "off");
1265 tg3_ump_link_report(tp);
1266 }
1267}
1268
1269static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270{
1271 u16 miireg;
1272
e18ce346 1273 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1274 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1275 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1276 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1277 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1278 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279 else
1280 miireg = 0;
1281
1282 return miireg;
1283}
1284
1285static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286{
1287 u16 miireg;
1288
e18ce346 1289 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1290 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1291 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1292 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1293 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1294 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295 else
1296 miireg = 0;
1297
1298 return miireg;
1299}
1300
95e2869a
MC		 1301static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302{
1303 u8 cap = 0;
1304
1305 if (lcladv & ADVERTISE_1000XPAUSE) {
1306 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1308 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1309 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1310 cap = FLOW_CTRL_RX;
95e2869a
MC		 1311 } else {
1312 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1314 }
1315 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1317 cap = FLOW_CTRL_TX;
95e2869a
MC		 1318 }
1319
1320 return cap;
1321}
1322
f51f3562 1323static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1324{
b02fd9e3 1325 u8 autoneg;
f51f3562 1326 u8 flowctrl = 0;
95e2869a
MC		 1327 u32 old_rx_mode = tp->rx_mode;
1328 u32 old_tx_mode = tp->tx_mode;
1329
b02fd9e3 1330 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1331 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1332 else
1333 autoneg = tp->link_config.autoneg;
1334
1335 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1336 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1338 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1339 else
bc02ff95 1340 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1341 } else
1342 flowctrl = tp->link_config.flowctrl;
95e2869a 1343
f51f3562 1344 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1345
e18ce346 1346 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1347 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348 else
1349 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
f51f3562 1351 if (old_rx_mode != tp->rx_mode)
95e2869a 1352 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1353
e18ce346 1354 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1355 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356 else
1357 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
f51f3562 1359 if (old_tx_mode != tp->tx_mode)
95e2869a 1360 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1361}
1362
b02fd9e3
MC		 1363static void tg3_adjust_link(struct net_device *dev)
1364{
1365 u8 oldflowctrl, linkmesg = 0;
1366 u32 mac_mode, lcl_adv, rmt_adv;
1367 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1368 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1369
24bb4fb6 1370 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1371
1372 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373 MAC_MODE_HALF_DUPLEX);
1374
1375 oldflowctrl = tp->link_config.active_flowctrl;
1376
1377 if (phydev->link) {
1378 lcl_adv = 0;
1379 rmt_adv = 0;
1380
1381 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1383 else if (phydev->speed == SPEED_1000 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1385 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1386 else
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1388
1389 if (phydev->duplex == DUPLEX_HALF)
1390 mac_mode |= MAC_MODE_HALF_DUPLEX;
1391 else {
1392 lcl_adv = tg3_advert_flowctrl_1000T(
1393 tp->link_config.flowctrl);
1394
1395 if (phydev->pause)
1396 rmt_adv = LPA_PAUSE_CAP;
1397 if (phydev->asym_pause)
1398 rmt_adv |= LPA_PAUSE_ASYM;
1399 }
1400
1401 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402 } else
1403 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405 if (mac_mode != tp->mac_mode) {
1406 tp->mac_mode = mac_mode;
1407 tw32_f(MAC_MODE, tp->mac_mode);
1408 udelay(40);
1409 }
1410
fcb389df
MC		 1411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412 if (phydev->speed == SPEED_10)
1413 tw32(MAC_MI_STAT,
1414 MAC_MI_STAT_10MBPS_MODE |
1415 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416 else
1417 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418 }
1419
b02fd9e3
MC		 1420 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421 tw32(MAC_TX_LENGTHS,
1422 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423 (6 << TX_LENGTHS_IPG_SHIFT) |
1424 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425 else
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433 phydev->speed != tp->link_config.active_speed ||
1434 phydev->duplex != tp->link_config.active_duplex ||
1435 oldflowctrl != tp->link_config.active_flowctrl)
1436 linkmesg = 1;
1437
1438 tp->link_config.active_speed = phydev->speed;
1439 tp->link_config.active_duplex = phydev->duplex;
1440
24bb4fb6 1441 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1442
1443 if (linkmesg)
1444 tg3_link_report(tp);
1445}
1446
1447static int tg3_phy_init(struct tg3 *tp)
1448{
1449 struct phy_device *phydev;
1450
1451 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452 return 0;
1453
1454 /* Bring the PHY back to a known state. */
1455 tg3_bmcr_reset(tp);
1456
3f0e3ad7 1457 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1458
1459 /* Attach the MAC to the PHY. */
fb28ad35 1460 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1461 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1462 if (IS_ERR(phydev)) {
1463 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464 return PTR_ERR(phydev);
1465 }
1466
b02fd9e3 1467 /* Mask with MAC supported features. */
9c61d6bc
MC		 1468 switch (phydev->interface) {
1469 case PHY_INTERFACE_MODE_GMII:
1470 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472 phydev->supported &= (PHY_GBIT_FEATURES |
1473 SUPPORTED_Pause |
1474 SUPPORTED_Asym_Pause);
1475 break;
1476 }
1477 /* fallthru */
9c61d6bc
MC		 1478 case PHY_INTERFACE_MODE_MII:
1479 phydev->supported &= (PHY_BASIC_FEATURES |
1480 SUPPORTED_Pause |
1481 SUPPORTED_Asym_Pause);
1482 break;
1483 default:
3f0e3ad7 1484 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1485 return -EINVAL;
1486 }
1487
1488 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1489
1490 phydev->advertising = phydev->supported;
1491
b02fd9e3
MC		 1492 return 0;
1493}
1494
1495static void tg3_phy_start(struct tg3 *tp)
1496{
1497 struct phy_device *phydev;
1498
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
3f0e3ad7 1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1503
1504 if (tp->link_config.phy_is_low_power) {
1505 tp->link_config.phy_is_low_power = 0;
1506 phydev->speed = tp->link_config.orig_speed;
1507 phydev->duplex = tp->link_config.orig_duplex;
1508 phydev->autoneg = tp->link_config.orig_autoneg;
1509 phydev->advertising = tp->link_config.orig_advertising;
1510 }
1511
1512 phy_start(phydev);
1513
1514 phy_start_aneg(phydev);
1515}
1516
1517static void tg3_phy_stop(struct tg3 *tp)
1518{
1519 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520 return;
1521
3f0e3ad7 1522 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1523}
1524
1525static void tg3_phy_fini(struct tg3 *tp)
1526{
1527 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1529 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530 }
1531}
1532
b2a5c19c
MC		 1533static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534{
1535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537}
1538
7f97a4bd
MC		 1539static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540{
1541 u32 phytest;
1542
1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544 u32 phy;
1545
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 phytest | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549 if (enable)
1550 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551 else
1552 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554 }
1555 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556 }
1557}
1558
6833c043
MC		 1559static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560{
1561 u32 reg;
1562
ecf1410b
MC		 1563 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1564 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1565 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
6833c043
MC		 1566 return;
1567
7f97a4bd
MC		 1568 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1569 tg3_phy_fet_toggle_apd(tp, enable);
1570 return;
1571 }
1572
6833c043
MC		 1573 reg = MII_TG3_MISC_SHDW_WREN |
1574 MII_TG3_MISC_SHDW_SCR5_SEL |
1575 MII_TG3_MISC_SHDW_SCR5_LPED |
1576 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1577 MII_TG3_MISC_SHDW_SCR5_SDTL |
1578 MII_TG3_MISC_SHDW_SCR5_C125OE;
1579 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1580 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1581
1582 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1583
1584
1585 reg = MII_TG3_MISC_SHDW_WREN |
1586 MII_TG3_MISC_SHDW_APD_SEL |
1587 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1588 if (enable)
1589 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1590
1591 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1592}
1593
9ef8ca99
MC		 1594static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1595{
1596 u32 phy;
1597
1598 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1599 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1600 return;
1601
7f97a4bd 1602 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1603 u32 ephy;
1604
535ef6e1
MC		 1605 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1606 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1607
1608 tg3_writephy(tp, MII_TG3_FET_TEST,
1609 ephy | MII_TG3_FET_SHADOW_EN);
1610 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1611 if (enable)
535ef6e1 1612 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1613 else
535ef6e1
MC		 1614 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1615 tg3_writephy(tp, reg, phy);
9ef8ca99 1616 }
535ef6e1 1617 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1618 }
1619 } else {
1620 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1621 MII_TG3_AUXCTL_SHDWSEL_MISC;
1622 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1623 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1624 if (enable)
1625 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626 else
1627 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1628 phy |= MII_TG3_AUXCTL_MISC_WREN;
1629 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1630 }
1631 }
1632}
1633
1da177e4
LT		 1634static void tg3_phy_set_wirespeed(struct tg3 *tp)
1635{
1636 u32 val;
1637
1638 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1639 return;
1640
1641 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1642 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1643 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1644 (val | (1 << 15) | (1 << 4)));
1645}
1646
b2a5c19c
MC		 1647static void tg3_phy_apply_otp(struct tg3 *tp)
1648{
1649 u32 otp, phy;
1650
1651 if (!tp->phy_otp)
1652 return;
1653
1654 otp = tp->phy_otp;
1655
1656 /* Enable SM_DSP clock and tx 6dB coding. */
1657 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1658 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1659 MII_TG3_AUXCTL_ACTL_TX_6DB;
1660 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1661
1662 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1663 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1664 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1665
1666 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1667 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1668 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1669
1670 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1671 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1672 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1673
1674 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1675 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1676
1677 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1678 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1679
1680 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1681 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1683
1684 /* Turn off SM_DSP clock. */
1685 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1686 MII_TG3_AUXCTL_ACTL_TX_6DB;
1687 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1688}
1689
1da177e4
LT		 1690static int tg3_wait_macro_done(struct tg3 *tp)
1691{
1692 int limit = 100;
1693
1694 while (limit--) {
1695 u32 tmp32;
1696
1697 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1698 if ((tmp32 & 0x1000) == 0)
1699 break;
1700 }
1701 }
d4675b52 1702 if (limit < 0)
1da177e4
LT		 1703 return -EBUSY;
1704
1705 return 0;
1706}
1707
1708static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1709{
1710 static const u32 test_pat[4][6] = {
1711 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1712 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1713 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1714 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1715 };
1716 int chan;
1717
1718 for (chan = 0; chan < 4; chan++) {
1719 int i;
1720
1721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1722 (chan * 0x2000) | 0x0200);
1723 tg3_writephy(tp, 0x16, 0x0002);
1724
1725 for (i = 0; i < 6; i++)
1726 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1727 test_pat[chan][i]);
1728
1729 tg3_writephy(tp, 0x16, 0x0202);
1730 if (tg3_wait_macro_done(tp)) {
1731 *resetp = 1;
1732 return -EBUSY;
1733 }
1734
1735 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1736 (chan * 0x2000) | 0x0200);
1737 tg3_writephy(tp, 0x16, 0x0082);
1738 if (tg3_wait_macro_done(tp)) {
1739 *resetp = 1;
1740 return -EBUSY;
1741 }
1742
1743 tg3_writephy(tp, 0x16, 0x0802);
1744 if (tg3_wait_macro_done(tp)) {
1745 *resetp = 1;
1746 return -EBUSY;
1747 }
1748
1749 for (i = 0; i < 6; i += 2) {
1750 u32 low, high;
1751
1752 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1753 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1754 tg3_wait_macro_done(tp)) {
1755 *resetp = 1;
1756 return -EBUSY;
1757 }
1758 low &= 0x7fff;
1759 high &= 0x000f;
1760 if (low != test_pat[chan][i] ||
1761 high != test_pat[chan][i+1]) {
1762 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1763 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1764 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1765
1766 return -EBUSY;
1767 }
1768 }
1769 }
1770
1771 return 0;
1772}
1773
1774static int tg3_phy_reset_chanpat(struct tg3 *tp)
1775{
1776 int chan;
1777
1778 for (chan = 0; chan < 4; chan++) {
1779 int i;
1780
1781 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782 (chan * 0x2000) | 0x0200);
1783 tg3_writephy(tp, 0x16, 0x0002);
1784 for (i = 0; i < 6; i++)
1785 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1786 tg3_writephy(tp, 0x16, 0x0202);
1787 if (tg3_wait_macro_done(tp))
1788 return -EBUSY;
1789 }
1790
1791 return 0;
1792}
1793
1794static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1795{
1796 u32 reg32, phy9_orig;
1797 int retries, do_phy_reset, err;
1798
1799 retries = 10;
1800 do_phy_reset = 1;
1801 do {
1802 if (do_phy_reset) {
1803 err = tg3_bmcr_reset(tp);
1804 if (err)
1805 return err;
1806 do_phy_reset = 0;
1807 }
1808
1809 /* Disable transmitter and interrupt. */
1810 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1811 continue;
1812
1813 reg32 |= 0x3000;
1814 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1815
1816 /* Set full-duplex, 1000 mbps. */
1817 tg3_writephy(tp, MII_BMCR,
1818 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1819
1820 /* Set to master mode. */
1821 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1822 continue;
1823
1824 tg3_writephy(tp, MII_TG3_CTRL,
1825 (MII_TG3_CTRL_AS_MASTER |
1826 MII_TG3_CTRL_ENABLE_AS_MASTER));
1827
1828 /* Enable SM_DSP_CLOCK and 6dB. */
1829 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1830
1831 /* Block the PHY control access. */
1832 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1834
1835 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1836 if (!err)
1837 break;
1838 } while (--retries);
1839
1840 err = tg3_phy_reset_chanpat(tp);
1841 if (err)
1842 return err;
1843
1844 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1845 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1846
1847 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1848 tg3_writephy(tp, 0x16, 0x0000);
1849
1850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1852 /* Set Extended packet length bit for jumbo frames */
1853 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1854 }
1855 else {
1856 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1857 }
1858
1859 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1860
1861 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1862 reg32 &= ~0x3000;
1863 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1864 } else if (!err)
1865 err = -EBUSY;
1866
1867 return err;
1868}
1869
1870/* This will reset the tigon3 PHY if there is no valid
1871 * link unless the FORCE argument is non-zero.
1872 */
1873static int tg3_phy_reset(struct tg3 *tp)
1874{
b2a5c19c 1875 u32 cpmuctrl;
1da177e4
LT		 1876 u32 phy_status;
1877 int err;
1878
60189ddf
MC		 1879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1880 u32 val;
1881
1882 val = tr32(GRC_MISC_CFG);
1883 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1884 udelay(40);
1885 }
1da177e4
LT		 1886 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1887 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1888 if (err != 0)
1889 return -EBUSY;
1890
c8e1e82b
MC		 1891 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1892 netif_carrier_off(tp->dev);
1893 tg3_link_report(tp);
1894 }
1895
1da177e4
LT		 1896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1899 err = tg3_phy_reset_5703_4_5(tp);
1900 if (err)
1901 return err;
1902 goto out;
1903 }
1904
b2a5c19c
MC		 1905 cpmuctrl = 0;
1906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1907 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1908 cpmuctrl = tr32(TG3_CPMU_CTRL);
1909 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1910 tw32(TG3_CPMU_CTRL,
1911 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1912 }
1913
1da177e4
LT		 1914 err = tg3_bmcr_reset(tp);
1915 if (err)
1916 return err;
1917
b2a5c19c
MC		 1918 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1919 u32 phy;
1920
1921 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1922 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1923
1924 tw32(TG3_CPMU_CTRL, cpmuctrl);
1925 }
1926
bcb37f6c
MC		 1927 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1928 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1929 u32 val;
1930
1931 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1932 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1933 CPMU_LSPD_1000MB_MACCLK_12_5) {
1934 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1935 udelay(40);
1936 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1937 }
1938 }
1939
ecf1410b
MC		 1940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1941 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1942 return 0;
1943
b2a5c19c
MC		 1944 tg3_phy_apply_otp(tp);
1945
6833c043
MC		 1946 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1947 tg3_phy_toggle_apd(tp, true);
1948 else
1949 tg3_phy_toggle_apd(tp, false);
1950
1da177e4
LT		 1951out:
1952 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1953 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1955 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1956 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1957 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1958 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1959 }
1960 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1961 tg3_writephy(tp, 0x1c, 0x8d68);
1962 tg3_writephy(tp, 0x1c, 0x8d68);
1963 }
1964 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1965 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1968 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1969 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1971 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1973 }
c424cb24
MC		 1974 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1975 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1976 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1977 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1979 tg3_writephy(tp, MII_TG3_TEST1,
1980 MII_TG3_TEST1_TRIM_EN | 0x4);
1981 } else
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984 }
1da177e4
LT		 1985 /* Set Extended packet length bit (bit 14) on all chips that */
1986 /* support jumbo frames */
1987 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1988 /* Cannot do read-modify-write on 5401 */
1989 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1990 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1991 u32 phy_reg;
1992
1993 /* Set bit 14 with read-modify-write to preserve other bits */
1994 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1995 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1996 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1997 }
1998
1999 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2000 * jumbo frames transmission.
2001 */
8f666b07 2002 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 2003 u32 phy_reg;
2004
2005 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2006 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2007 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2008 }
2009
715116a1 2010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2011 /* adjust output voltage */
535ef6e1 2012 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2013 }
2014
9ef8ca99 2015 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2016 tg3_phy_set_wirespeed(tp);
2017 return 0;
2018}
2019
2020static void tg3_frob_aux_power(struct tg3 *tp)
2021{
2022 struct tg3 *tp_peer = tp;
2023
334355aa
MC		 2024 /* The GPIOs do something completely different on 57765. */
2025 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
1da177e4
LT		 2027 return;
2028
f6eb9b1f
MC		 2029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2032 struct net_device *dev_peer;
2033
2034 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2035 /* remove_one() may have been run on the peer. */
8c2dc7e1 2036 if (!dev_peer)
bc1c7567
MC		 2037 tp_peer = tp;
2038 else
2039 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2040 }
2041
1da177e4 2042 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2043 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2044 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2045 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2048 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2049 (GRC_LCLCTRL_GPIO_OE0 |
2050 GRC_LCLCTRL_GPIO_OE1 |
2051 GRC_LCLCTRL_GPIO_OE2 |
2052 GRC_LCLCTRL_GPIO_OUTPUT0 |
2053 GRC_LCLCTRL_GPIO_OUTPUT1),
2054 100);
8d519ab2
MC		 2055 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2056 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2057 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2058 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2059 GRC_LCLCTRL_GPIO_OE1 |
2060 GRC_LCLCTRL_GPIO_OE2 |
2061 GRC_LCLCTRL_GPIO_OUTPUT0 |
2062 GRC_LCLCTRL_GPIO_OUTPUT1 |
2063 tp->grc_local_ctrl;
2064 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2065
2066 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2067 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2068
2069 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2070 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2071 } else {
2072 u32 no_gpio2;
dc56b7d4 2073 u32 grc_local_ctrl = 0;
1da177e4
LT		 2074
2075 if (tp_peer != tp &&
2076 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2077 return;
2078
dc56b7d4
MC		 2079 /* Workaround to prevent overdrawing Amps. */
2080 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2081 ASIC_REV_5714) {
2082 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2083 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084 grc_local_ctrl, 100);
dc56b7d4
MC		 2085 }
2086
1da177e4
LT		 2087 /* On 5753 and variants, GPIO2 cannot be used. */
2088 no_gpio2 = tp->nic_sram_data_cfg &
2089 NIC_SRAM_DATA_CFG_NO_GPIO2;
2090
dc56b7d4 2091 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2092 GRC_LCLCTRL_GPIO_OE1 |
2093 GRC_LCLCTRL_GPIO_OE2 |
2094 GRC_LCLCTRL_GPIO_OUTPUT1 |
2095 GRC_LCLCTRL_GPIO_OUTPUT2;
2096 if (no_gpio2) {
2097 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2098 GRC_LCLCTRL_GPIO_OUTPUT2);
2099 }
b401e9e2
MC		 2100 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2101 grc_local_ctrl, 100);
1da177e4
LT		 2102
2103 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2104
b401e9e2
MC		 2105 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2106 grc_local_ctrl, 100);
1da177e4
LT		 2107
2108 if (!no_gpio2) {
2109 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2110 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111 grc_local_ctrl, 100);
1da177e4
LT		 2112 }
2113 }
2114 } else {
2115 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2116 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2117 if (tp_peer != tp &&
2118 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2119 return;
2120
b401e9e2
MC		 2121 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122 (GRC_LCLCTRL_GPIO_OE1 |
2123 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2124
b401e9e2
MC		 2125 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2126 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2127
b401e9e2
MC		 2128 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2129 (GRC_LCLCTRL_GPIO_OE1 |
2130 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2131 }
2132 }
2133}
2134
e8f3f6ca
MC		 2135static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2136{
2137 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2138 return 1;
2139 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2140 if (speed != SPEED_10)
2141 return 1;
2142 } else if (speed == SPEED_10)
2143 return 1;
2144
2145 return 0;
2146}
2147
1da177e4
LT		 2148static int tg3_setup_phy(struct tg3 *, int);
2149
2150#define RESET_KIND_SHUTDOWN 0
2151#define RESET_KIND_INIT 1
2152#define RESET_KIND_SUSPEND 2
2153
2154static void tg3_write_sig_post_reset(struct tg3 *, int);
2155static int tg3_halt_cpu(struct tg3 *, u32);
2156
0a459aac 2157static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2158{
ce057f01
MC		 2159 u32 val;
2160
5129724a
MC		 2161 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2162 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2163 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2164 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2165
2166 sg_dig_ctrl |=
2167 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2168 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2169 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2170 }
3f7045c1 2171 return;
5129724a 2172 }
3f7045c1 2173
60189ddf 2174 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2175 tg3_bmcr_reset(tp);
2176 val = tr32(GRC_MISC_CFG);
2177 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2178 udelay(40);
2179 return;
0e5f784c
MC		 2180 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2181 u32 phytest;
2182 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2183 u32 phy;
2184
2185 tg3_writephy(tp, MII_ADVERTISE, 0);
2186 tg3_writephy(tp, MII_BMCR,
2187 BMCR_ANENABLE | BMCR_ANRESTART);
2188
2189 tg3_writephy(tp, MII_TG3_FET_TEST,
2190 phytest | MII_TG3_FET_SHADOW_EN);
2191 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2192 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2193 tg3_writephy(tp,
2194 MII_TG3_FET_SHDW_AUXMODE4,
2195 phy);
2196 }
2197 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2198 }
2199 return;
0a459aac 2200 } else if (do_low_power) {
715116a1
MC		 2201 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2202 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2203
2204 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2205 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2206 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2207 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2208 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2209 }
3f7045c1 2210
15c3b696
MC		 2211 /* The PHY should not be powered down on some chips because
2212 * of bugs.
2213 */
2214 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2215 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2216 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2217 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2218 return;
ce057f01 2219
bcb37f6c
MC		 2220 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2221 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2222 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2223 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2224 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2225 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2226 }
2227
15c3b696
MC		 2228 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2229}
2230
ffbcfed4
MC		 2231/* tp->lock is held. */
2232static int tg3_nvram_lock(struct tg3 *tp)
2233{
2234 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2235 int i;
2236
2237 if (tp->nvram_lock_cnt == 0) {
2238 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2239 for (i = 0; i < 8000; i++) {
2240 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2241 break;
2242 udelay(20);
2243 }
2244 if (i == 8000) {
2245 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2246 return -ENODEV;
2247 }
2248 }
2249 tp->nvram_lock_cnt++;
2250 }
2251 return 0;
2252}
2253
2254/* tp->lock is held. */
2255static void tg3_nvram_unlock(struct tg3 *tp)
2256{
2257 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2258 if (tp->nvram_lock_cnt > 0)
2259 tp->nvram_lock_cnt--;
2260 if (tp->nvram_lock_cnt == 0)
2261 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2262 }
2263}
2264
2265/* tp->lock is held. */
2266static void tg3_enable_nvram_access(struct tg3 *tp)
2267{
2268 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2269 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2270 u32 nvaccess = tr32(NVRAM_ACCESS);
2271
2272 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2273 }
2274}
2275
2276/* tp->lock is held. */
2277static void tg3_disable_nvram_access(struct tg3 *tp)
2278{
2279 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2280 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2281 u32 nvaccess = tr32(NVRAM_ACCESS);
2282
2283 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2284 }
2285}
2286
2287static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2288 u32 offset, u32 *val)
2289{
2290 u32 tmp;
2291 int i;
2292
2293 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2294 return -EINVAL;
2295
2296 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2297 EEPROM_ADDR_DEVID_MASK |
2298 EEPROM_ADDR_READ);
2299 tw32(GRC_EEPROM_ADDR,
2300 tmp |
2301 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2302 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2303 EEPROM_ADDR_ADDR_MASK) |
2304 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2305
2306 for (i = 0; i < 1000; i++) {
2307 tmp = tr32(GRC_EEPROM_ADDR);
2308
2309 if (tmp & EEPROM_ADDR_COMPLETE)
2310 break;
2311 msleep(1);
2312 }
2313 if (!(tmp & EEPROM_ADDR_COMPLETE))
2314 return -EBUSY;
2315
62cedd11
MC		 2316 tmp = tr32(GRC_EEPROM_DATA);
2317
2318 /*
2319 * The data will always be opposite the native endian
2320 * format. Perform a blind byteswap to compensate.
2321 */
2322 *val = swab32(tmp);
2323
ffbcfed4
MC		 2324 return 0;
2325}
2326
2327#define NVRAM_CMD_TIMEOUT 10000
2328
2329static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2330{
2331 int i;
2332
2333 tw32(NVRAM_CMD, nvram_cmd);
2334 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2335 udelay(10);
2336 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2337 udelay(10);
2338 break;
2339 }
2340 }
2341
2342 if (i == NVRAM_CMD_TIMEOUT)
2343 return -EBUSY;
2344
2345 return 0;
2346}
2347
2348static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2349{
2350 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2351 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2352 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2353 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2354 (tp->nvram_jedecnum == JEDEC_ATMEL))
2355
2356 addr = ((addr / tp->nvram_pagesize) <<
2357 ATMEL_AT45DB0X1B_PAGE_POS) +
2358 (addr % tp->nvram_pagesize);
2359
2360 return addr;
2361}
2362
2363static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2364{
2365 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2366 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2367 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2368 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2369 (tp->nvram_jedecnum == JEDEC_ATMEL))
2370
2371 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2372 tp->nvram_pagesize) +
2373 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2374
2375 return addr;
2376}
2377
e4f34110
MC		 2378/* NOTE: Data read in from NVRAM is byteswapped according to
2379 * the byteswapping settings for all other register accesses.
2380 * tg3 devices are BE devices, so on a BE machine, the data
2381 * returned will be exactly as it is seen in NVRAM. On a LE
2382 * machine, the 32-bit value will be byteswapped.
2383 */
ffbcfed4
MC		 2384static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2385{
2386 int ret;
2387
2388 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2389 return tg3_nvram_read_using_eeprom(tp, offset, val);
2390
2391 offset = tg3_nvram_phys_addr(tp, offset);
2392
2393 if (offset > NVRAM_ADDR_MSK)
2394 return -EINVAL;
2395
2396 ret = tg3_nvram_lock(tp);
2397 if (ret)
2398 return ret;
2399
2400 tg3_enable_nvram_access(tp);
2401
2402 tw32(NVRAM_ADDR, offset);
2403 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2404 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2405
2406 if (ret == 0)
e4f34110 2407 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2408
2409 tg3_disable_nvram_access(tp);
2410
2411 tg3_nvram_unlock(tp);
2412
2413 return ret;
2414}
2415
a9dc529d
MC		 2416/* Ensures NVRAM data is in bytestream format. */
2417static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2418{
2419 u32 v;
a9dc529d 2420 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2421 if (!res)
a9dc529d 2422 *val = cpu_to_be32(v);
ffbcfed4
MC		 2423 return res;
2424}
2425
3f007891
MC		 2426/* tp->lock is held. */
2427static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2428{
2429 u32 addr_high, addr_low;
2430 int i;
2431
2432 addr_high = ((tp->dev->dev_addr[0] << 8) |
2433 tp->dev->dev_addr[1]);
2434 addr_low = ((tp->dev->dev_addr[2] << 24) |
2435 (tp->dev->dev_addr[3] << 16) |
2436 (tp->dev->dev_addr[4] << 8) |
2437 (tp->dev->dev_addr[5] << 0));
2438 for (i = 0; i < 4; i++) {
2439 if (i == 1 && skip_mac_1)
2440 continue;
2441 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2442 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2443 }
2444
2445 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2446 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2447 for (i = 0; i < 12; i++) {
2448 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2449 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2450 }
2451 }
2452
2453 addr_high = (tp->dev->dev_addr[0] +
2454 tp->dev->dev_addr[1] +
2455 tp->dev->dev_addr[2] +
2456 tp->dev->dev_addr[3] +
2457 tp->dev->dev_addr[4] +
2458 tp->dev->dev_addr[5]) &
2459 TX_BACKOFF_SEED_MASK;
2460 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2461}
2462
bc1c7567 2463static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2464{
2465 u32 misc_host_ctrl;
0a459aac 2466 bool device_should_wake, do_low_power;
1da177e4
LT		 2467
2468 /* Make sure register accesses (indirect or otherwise)
2469 * will function correctly.
2470 */
2471 pci_write_config_dword(tp->pdev,
2472 TG3PCI_MISC_HOST_CTRL,
2473 tp->misc_host_ctrl);
2474
1da177e4 2475 switch (state) {
bc1c7567 2476 case PCI_D0:
12dac075
RW		 2477 pci_enable_wake(tp->pdev, state, false);
2478 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2479
9d26e213
MC		 2480 /* Switch out of Vaux if it is a NIC */
2481 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2482 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2483
2484 return 0;
2485
bc1c7567 2486 case PCI_D1:
bc1c7567 2487 case PCI_D2:
bc1c7567 2488 case PCI_D3hot:
1da177e4
LT		 2489 break;
2490
2491 default:
12dac075
RW		 2492 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2493 tp->dev->name, state);
1da177e4 2494 return -EINVAL;
855e1111 2495 }
5e7dfd0f
MC		 2496
2497 /* Restore the CLKREQ setting. */
2498 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2499 u16 lnkctl;
2500
2501 pci_read_config_word(tp->pdev,
2502 tp->pcie_cap + PCI_EXP_LNKCTL,
2503 &lnkctl);
2504 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2505 pci_write_config_word(tp->pdev,
2506 tp->pcie_cap + PCI_EXP_LNKCTL,
2507 lnkctl);
2508 }
2509
1da177e4
LT		 2510 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2511 tw32(TG3PCI_MISC_HOST_CTRL,
2512 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2513
05ac4cb7
MC		 2514 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2515 device_may_wakeup(&tp->pdev->dev) &&
2516 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2517
dd477003 2518 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2519 do_low_power = false;
b02fd9e3
MC		 2520 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2521 !tp->link_config.phy_is_low_power) {
2522 struct phy_device *phydev;
0a459aac 2523 u32 phyid, advertising;
b02fd9e3 2524
3f0e3ad7 2525 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2526
2527 tp->link_config.phy_is_low_power = 1;
2528
2529 tp->link_config.orig_speed = phydev->speed;
2530 tp->link_config.orig_duplex = phydev->duplex;
2531 tp->link_config.orig_autoneg = phydev->autoneg;
2532 tp->link_config.orig_advertising = phydev->advertising;
2533
2534 advertising = ADVERTISED_TP |
2535 ADVERTISED_Pause |
2536 ADVERTISED_Autoneg |
2537 ADVERTISED_10baseT_Half;
2538
2539 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2540 device_should_wake) {
b02fd9e3
MC		 2541 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2542 advertising |=
2543 ADVERTISED_100baseT_Half |
2544 ADVERTISED_100baseT_Full |
2545 ADVERTISED_10baseT_Full;
2546 else
2547 advertising |= ADVERTISED_10baseT_Full;
2548 }
2549
2550 phydev->advertising = advertising;
2551
2552 phy_start_aneg(phydev);
0a459aac
MC		 2553
2554 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2555 if (phyid != TG3_PHY_ID_BCMAC131) {
2556 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2557 if (phyid == TG3_PHY_OUI_1 ||
2558 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2559 phyid == TG3_PHY_OUI_3)
2560 do_low_power = true;
2561 }
b02fd9e3 2562 }
dd477003 2563 } else {
2023276e 2564 do_low_power = true;
0a459aac 2565
dd477003
MC		 2566 if (tp->link_config.phy_is_low_power == 0) {
2567 tp->link_config.phy_is_low_power = 1;
2568 tp->link_config.orig_speed = tp->link_config.speed;
2569 tp->link_config.orig_duplex = tp->link_config.duplex;
2570 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2571 }
1da177e4 2572
dd477003
MC		 2573 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2574 tp->link_config.speed = SPEED_10;
2575 tp->link_config.duplex = DUPLEX_HALF;
2576 tp->link_config.autoneg = AUTONEG_ENABLE;
2577 tg3_setup_phy(tp, 0);
2578 }
1da177e4
LT		 2579 }
2580
b5d3772c
MC		 2581 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2582 u32 val;
2583
2584 val = tr32(GRC_VCPU_EXT_CTRL);
2585 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2586 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2587 int i;
2588 u32 val;
2589
2590 for (i = 0; i < 200; i++) {
2591 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2592 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2593 break;
2594 msleep(1);
2595 }
2596 }
a85feb8c
GZ		 2597 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2598 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2599 WOL_DRV_STATE_SHUTDOWN |
2600 WOL_DRV_WOL |
2601 WOL_SET_MAGIC_PKT);
6921d201 2602
05ac4cb7 2603 if (device_should_wake) {
1da177e4
LT		 2604 u32 mac_mode;
2605
2606 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2607 if (do_low_power) {
dd477003
MC		 2608 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2609 udelay(40);
2610 }
1da177e4 2611
3f7045c1
MC		 2612 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2613 mac_mode = MAC_MODE_PORT_MODE_GMII;
2614 else
2615 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2616
e8f3f6ca
MC		 2617 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2618 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2619 ASIC_REV_5700) {
2620 u32 speed = (tp->tg3_flags &
2621 TG3_FLAG_WOL_SPEED_100MB) ?
2622 SPEED_100 : SPEED_10;
2623 if (tg3_5700_link_polarity(tp, speed))
2624 mac_mode |= MAC_MODE_LINK_POLARITY;
2625 else
2626 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2627 }
1da177e4
LT		 2628 } else {
2629 mac_mode = MAC_MODE_PORT_MODE_TBI;
2630 }
2631
cbf46853 2632 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2633 tw32(MAC_LED_CTRL, tp->led_ctrl);
2634
05ac4cb7
MC		 2635 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2636 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2637 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2638 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2639 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2640 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2641
3bda1258
MC		 2642 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2643 mac_mode |= tp->mac_mode &
2644 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2645 if (mac_mode & MAC_MODE_APE_TX_EN)
2646 mac_mode |= MAC_MODE_TDE_ENABLE;
2647 }
2648
1da177e4
LT		 2649 tw32_f(MAC_MODE, mac_mode);
2650 udelay(100);
2651
2652 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2653 udelay(10);
2654 }
2655
2656 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2657 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2658 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2659 u32 base_val;
2660
2661 base_val = tp->pci_clock_ctrl;
2662 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2663 CLOCK_CTRL_TXCLK_DISABLE);
2664
b401e9e2
MC		 2665 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2666 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2667 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2668 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2669 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2670 /* do nothing */
85e94ced 2671 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2672 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2673 u32 newbits1, newbits2;
2674
2675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2676 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2677 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2678 CLOCK_CTRL_TXCLK_DISABLE |
2679 CLOCK_CTRL_ALTCLK);
2680 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2681 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2682 newbits1 = CLOCK_CTRL_625_CORE;
2683 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2684 } else {
2685 newbits1 = CLOCK_CTRL_ALTCLK;
2686 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2687 }
2688
b401e9e2
MC		 2689 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2690 40);
1da177e4 2691
b401e9e2
MC		 2692 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2693 40);
1da177e4
LT		 2694
2695 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2696 u32 newbits3;
2697
2698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2700 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2701 CLOCK_CTRL_TXCLK_DISABLE |
2702 CLOCK_CTRL_44MHZ_CORE);
2703 } else {
2704 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2705 }
2706
b401e9e2
MC		 2707 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2708 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2709 }
2710 }
2711
05ac4cb7 2712 if (!(device_should_wake) &&
22435849 2713 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2714 tg3_power_down_phy(tp, do_low_power);
6921d201 2715
1da177e4
LT		 2716 tg3_frob_aux_power(tp);
2717
2718 /* Workaround for unstable PLL clock */
2719 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2720 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2721 u32 val = tr32(0x7d00);
2722
2723 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2724 tw32(0x7d00, val);
6921d201 2725 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2726 int err;
2727
2728 err = tg3_nvram_lock(tp);
1da177e4 2729 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2730 if (!err)
2731 tg3_nvram_unlock(tp);
6921d201 2732 }
1da177e4
LT		 2733 }
2734
bbadf503
MC		 2735 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2736
05ac4cb7 2737 if (device_should_wake)
12dac075
RW		 2738 pci_enable_wake(tp->pdev, state, true);
2739
1da177e4 2740 /* Finally, set the new power state. */
12dac075 2741 pci_set_power_state(tp->pdev, state);
1da177e4 2742
1da177e4
LT		 2743 return 0;
2744}
2745
1da177e4
LT		 2746static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2747{
2748 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2749 case MII_TG3_AUX_STAT_10HALF:
2750 *speed = SPEED_10;
2751 *duplex = DUPLEX_HALF;
2752 break;
2753
2754 case MII_TG3_AUX_STAT_10FULL:
2755 *speed = SPEED_10;
2756 *duplex = DUPLEX_FULL;
2757 break;
2758
2759 case MII_TG3_AUX_STAT_100HALF:
2760 *speed = SPEED_100;
2761 *duplex = DUPLEX_HALF;
2762 break;
2763
2764 case MII_TG3_AUX_STAT_100FULL:
2765 *speed = SPEED_100;
2766 *duplex = DUPLEX_FULL;
2767 break;
2768
2769 case MII_TG3_AUX_STAT_1000HALF:
2770 *speed = SPEED_1000;
2771 *duplex = DUPLEX_HALF;
2772 break;
2773
2774 case MII_TG3_AUX_STAT_1000FULL:
2775 *speed = SPEED_1000;
2776 *duplex = DUPLEX_FULL;
2777 break;
2778
2779 default:
7f97a4bd 2780 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2781 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2782 SPEED_10;
2783 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2784 DUPLEX_HALF;
2785 break;
2786 }
1da177e4
LT		 2787 *speed = SPEED_INVALID;
2788 *duplex = DUPLEX_INVALID;
2789 break;
855e1111 2790 }
1da177e4
LT		 2791}
2792
2793static void tg3_phy_copper_begin(struct tg3 *tp)
2794{
2795 u32 new_adv;
2796 int i;
2797
2798 if (tp->link_config.phy_is_low_power) {
2799 /* Entering low power mode. Disable gigabit and
2800 * 100baseT advertisements.
2801 */
2802 tg3_writephy(tp, MII_TG3_CTRL, 0);
2803
2804 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2805 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2806 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2807 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2808
2809 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2810 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2811 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2812 tp->link_config.advertising &=
2813 ~(ADVERTISED_1000baseT_Half |
2814 ADVERTISED_1000baseT_Full);
2815
ba4d07a8 2816 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2817 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2818 new_adv |= ADVERTISE_10HALF;
2819 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2820 new_adv |= ADVERTISE_10FULL;
2821 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2822 new_adv |= ADVERTISE_100HALF;
2823 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2824 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2825
2826 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2827
1da177e4
LT		 2828 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2829
2830 if (tp->link_config.advertising &
2831 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2832 new_adv = 0;
2833 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2834 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2835 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2836 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2837 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2838 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2839 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2840 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2841 MII_TG3_CTRL_ENABLE_AS_MASTER);
2842 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2843 } else {
2844 tg3_writephy(tp, MII_TG3_CTRL, 0);
2845 }
2846 } else {
ba4d07a8
MC		 2847 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2848 new_adv |= ADVERTISE_CSMA;
2849
1da177e4
LT		 2850 /* Asking for a specific link mode. */
2851 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2852 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2853
2854 if (tp->link_config.duplex == DUPLEX_FULL)
2855 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2856 else
2857 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2858 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2859 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2860 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2861 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2862 } else {
1da177e4
LT		 2863 if (tp->link_config.speed == SPEED_100) {
2864 if (tp->link_config.duplex == DUPLEX_FULL)
2865 new_adv |= ADVERTISE_100FULL;
2866 else
2867 new_adv |= ADVERTISE_100HALF;
2868 } else {
2869 if (tp->link_config.duplex == DUPLEX_FULL)
2870 new_adv |= ADVERTISE_10FULL;
2871 else
2872 new_adv |= ADVERTISE_10HALF;
2873 }
2874 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2875
2876 new_adv = 0;
1da177e4 2877 }
ba4d07a8
MC		 2878
2879 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2880 }
2881
2882 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2883 tp->link_config.speed != SPEED_INVALID) {
2884 u32 bmcr, orig_bmcr;
2885
2886 tp->link_config.active_speed = tp->link_config.speed;
2887 tp->link_config.active_duplex = tp->link_config.duplex;
2888
2889 bmcr = 0;
2890 switch (tp->link_config.speed) {
2891 default:
2892 case SPEED_10:
2893 break;
2894
2895 case SPEED_100:
2896 bmcr |= BMCR_SPEED100;
2897 break;
2898
2899 case SPEED_1000:
2900 bmcr |= TG3_BMCR_SPEED1000;
2901 break;
855e1111 2902 }
1da177e4
LT		 2903
2904 if (tp->link_config.duplex == DUPLEX_FULL)
2905 bmcr |= BMCR_FULLDPLX;
2906
2907 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2908 (bmcr != orig_bmcr)) {
2909 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2910 for (i = 0; i < 1500; i++) {
2911 u32 tmp;
2912
2913 udelay(10);
2914 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2915 tg3_readphy(tp, MII_BMSR, &tmp))
2916 continue;
2917 if (!(tmp & BMSR_LSTATUS)) {
2918 udelay(40);
2919 break;
2920 }
2921 }
2922 tg3_writephy(tp, MII_BMCR, bmcr);
2923 udelay(40);
2924 }
2925 } else {
2926 tg3_writephy(tp, MII_BMCR,
2927 BMCR_ANENABLE | BMCR_ANRESTART);
2928 }
2929}
2930
2931static int tg3_init_5401phy_dsp(struct tg3 *tp)
2932{
2933 int err;
2934
2935 /* Turn off tap power management. */
2936 /* Set Extended packet length bit */
2937 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2938
2939 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2940 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2941
2942 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2943 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2944
2945 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2946 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2947
2948 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2949 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2950
2951 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2952 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2953
2954 udelay(40);
2955
2956 return err;
2957}
2958
3600d918 2959static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2960{
3600d918
MC		 2961 u32 adv_reg, all_mask = 0;
2962
2963 if (mask & ADVERTISED_10baseT_Half)
2964 all_mask |= ADVERTISE_10HALF;
2965 if (mask & ADVERTISED_10baseT_Full)
2966 all_mask |= ADVERTISE_10FULL;
2967 if (mask & ADVERTISED_100baseT_Half)
2968 all_mask |= ADVERTISE_100HALF;
2969 if (mask & ADVERTISED_100baseT_Full)
2970 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2971
2972 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2973 return 0;
2974
1da177e4
LT		 2975 if ((adv_reg & all_mask) != all_mask)
2976 return 0;
2977 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2978 u32 tg3_ctrl;
2979
3600d918
MC		 2980 all_mask = 0;
2981 if (mask & ADVERTISED_1000baseT_Half)
2982 all_mask |= ADVERTISE_1000HALF;
2983 if (mask & ADVERTISED_1000baseT_Full)
2984 all_mask |= ADVERTISE_1000FULL;
2985
1da177e4
LT		 2986 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2987 return 0;
2988
1da177e4
LT		 2989 if ((tg3_ctrl & all_mask) != all_mask)
2990 return 0;
2991 }
2992 return 1;
2993}
2994
ef167e27
MC		 2995static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2996{
2997 u32 curadv, reqadv;
2998
2999 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3000 return 1;
3001
3002 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3003 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3004
3005 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3006 if (curadv != reqadv)
3007 return 0;
3008
3009 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3010 tg3_readphy(tp, MII_LPA, rmtadv);
3011 } else {
3012 /* Reprogram the advertisement register, even if it
3013 * does not affect the current link. If the link
3014 * gets renegotiated in the future, we can save an
3015 * additional renegotiation cycle by advertising
3016 * it correctly in the first place.
3017 */
3018 if (curadv != reqadv) {
3019 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3020 ADVERTISE_PAUSE_ASYM);
3021 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3022 }
3023 }
3024
3025 return 1;
3026}
3027
1da177e4
LT		 3028static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3029{
3030 int current_link_up;
3031 u32 bmsr, dummy;
ef167e27 3032 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3033 u16 current_speed;
3034 u8 current_duplex;
3035 int i, err;
3036
3037 tw32(MAC_EVENT, 0);
3038
3039 tw32_f(MAC_STATUS,
3040 (MAC_STATUS_SYNC_CHANGED |
3041 MAC_STATUS_CFG_CHANGED |
3042 MAC_STATUS_MI_COMPLETION |
3043 MAC_STATUS_LNKSTATE_CHANGED));
3044 udelay(40);
3045
8ef21428
MC		 3046 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3047 tw32_f(MAC_MI_MODE,
3048 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3049 udelay(80);
3050 }
1da177e4
LT		 3051
3052 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3053
3054 /* Some third-party PHYs need to be reset on link going
3055 * down.
3056 */
3057 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3060 netif_carrier_ok(tp->dev)) {
3061 tg3_readphy(tp, MII_BMSR, &bmsr);
3062 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3063 !(bmsr & BMSR_LSTATUS))
3064 force_reset = 1;
3065 }
3066 if (force_reset)
3067 tg3_phy_reset(tp);
3068
3069 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3070 tg3_readphy(tp, MII_BMSR, &bmsr);
3071 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3072 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3073 bmsr = 0;
3074
3075 if (!(bmsr & BMSR_LSTATUS)) {
3076 err = tg3_init_5401phy_dsp(tp);
3077 if (err)
3078 return err;
3079
3080 tg3_readphy(tp, MII_BMSR, &bmsr);
3081 for (i = 0; i < 1000; i++) {
3082 udelay(10);
3083 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3084 (bmsr & BMSR_LSTATUS)) {
3085 udelay(40);
3086 break;
3087 }
3088 }
3089
3090 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3091 !(bmsr & BMSR_LSTATUS) &&
3092 tp->link_config.active_speed == SPEED_1000) {
3093 err = tg3_phy_reset(tp);
3094 if (!err)
3095 err = tg3_init_5401phy_dsp(tp);
3096 if (err)
3097 return err;
3098 }
3099 }
3100 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3101 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3102 /* 5701 {A0,B0} CRC bug workaround */
3103 tg3_writephy(tp, 0x15, 0x0a75);
3104 tg3_writephy(tp, 0x1c, 0x8c68);
3105 tg3_writephy(tp, 0x1c, 0x8d68);
3106 tg3_writephy(tp, 0x1c, 0x8c68);
3107 }
3108
3109 /* Clear pending interrupts... */
3110 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3111 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3112
3113 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3114 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3115 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3116 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3117
3118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3120 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3121 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3122 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3123 else
3124 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3125 }
3126
3127 current_link_up = 0;
3128 current_speed = SPEED_INVALID;
3129 current_duplex = DUPLEX_INVALID;
3130
3131 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3132 u32 val;
3133
3134 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3135 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3136 if (!(val & (1 << 10))) {
3137 val |= (1 << 10);
3138 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3139 goto relink;
3140 }
3141 }
3142
3143 bmsr = 0;
3144 for (i = 0; i < 100; i++) {
3145 tg3_readphy(tp, MII_BMSR, &bmsr);
3146 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3147 (bmsr & BMSR_LSTATUS))
3148 break;
3149 udelay(40);
3150 }
3151
3152 if (bmsr & BMSR_LSTATUS) {
3153 u32 aux_stat, bmcr;
3154
3155 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3156 for (i = 0; i < 2000; i++) {
3157 udelay(10);
3158 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3159 aux_stat)
3160 break;
3161 }
3162
3163 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3164 &current_speed,
3165 &current_duplex);
3166
3167 bmcr = 0;
3168 for (i = 0; i < 200; i++) {
3169 tg3_readphy(tp, MII_BMCR, &bmcr);
3170 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3171 continue;
3172 if (bmcr && bmcr != 0x7fff)
3173 break;
3174 udelay(10);
3175 }
3176
ef167e27
MC		 3177 lcl_adv = 0;
3178 rmt_adv = 0;
1da177e4 3179
ef167e27
MC		 3180 tp->link_config.active_speed = current_speed;
3181 tp->link_config.active_duplex = current_duplex;
3182
3183 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3184 if ((bmcr & BMCR_ANENABLE) &&
3185 tg3_copper_is_advertising_all(tp,
3186 tp->link_config.advertising)) {
3187 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3188 &rmt_adv))
3189 current_link_up = 1;
1da177e4
LT		 3190 }
3191 } else {
3192 if (!(bmcr & BMCR_ANENABLE) &&
3193 tp->link_config.speed == current_speed &&
ef167e27
MC		 3194 tp->link_config.duplex == current_duplex &&
3195 tp->link_config.flowctrl ==
3196 tp->link_config.active_flowctrl) {
1da177e4 3197 current_link_up = 1;
1da177e4
LT		 3198 }
3199 }
3200
ef167e27
MC		 3201 if (current_link_up == 1 &&
3202 tp->link_config.active_duplex == DUPLEX_FULL)
3203 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3204 }
3205
1da177e4 3206relink:
6921d201 3207 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3208 u32 tmp;
3209
3210 tg3_phy_copper_begin(tp);
3211
3212 tg3_readphy(tp, MII_BMSR, &tmp);
3213 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3214 (tmp & BMSR_LSTATUS))
3215 current_link_up = 1;
3216 }
3217
3218 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3219 if (current_link_up == 1) {
3220 if (tp->link_config.active_speed == SPEED_100 ||
3221 tp->link_config.active_speed == SPEED_10)
3222 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3223 else
3224 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3225 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3226 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3227 else
1da177e4
LT		 3228 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3229
3230 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3231 if (tp->link_config.active_duplex == DUPLEX_HALF)
3232 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3233
1da177e4 3234 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3235 if (current_link_up == 1 &&
3236 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3237 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3238 else
3239 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3240 }
3241
3242 /* ??? Without this setting Netgear GA302T PHY does not
3243 * ??? send/receive packets...
3244 */
3245 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3246 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3247 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3248 tw32_f(MAC_MI_MODE, tp->mi_mode);
3249 udelay(80);
3250 }
3251
3252 tw32_f(MAC_MODE, tp->mac_mode);
3253 udelay(40);
3254
3255 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3256 /* Polled via timer. */
3257 tw32_f(MAC_EVENT, 0);
3258 } else {
3259 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3260 }
3261 udelay(40);
3262
3263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3264 current_link_up == 1 &&
3265 tp->link_config.active_speed == SPEED_1000 &&
3266 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3267 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3268 udelay(120);
3269 tw32_f(MAC_STATUS,
3270 (MAC_STATUS_SYNC_CHANGED |
3271 MAC_STATUS_CFG_CHANGED));
3272 udelay(40);
3273 tg3_write_mem(tp,
3274 NIC_SRAM_FIRMWARE_MBOX,
3275 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3276 }
3277
5e7dfd0f
MC		 3278 /* Prevent send BD corruption. */
3279 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3280 u16 oldlnkctl, newlnkctl;
3281
3282 pci_read_config_word(tp->pdev,
3283 tp->pcie_cap + PCI_EXP_LNKCTL,
3284 &oldlnkctl);
3285 if (tp->link_config.active_speed == SPEED_100 ||
3286 tp->link_config.active_speed == SPEED_10)
3287 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3288 else
3289 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3290 if (newlnkctl != oldlnkctl)
3291 pci_write_config_word(tp->pdev,
3292 tp->pcie_cap + PCI_EXP_LNKCTL,
3293 newlnkctl);
3294 }
3295
1da177e4
LT		 3296 if (current_link_up != netif_carrier_ok(tp->dev)) {
3297 if (current_link_up)
3298 netif_carrier_on(tp->dev);
3299 else
3300 netif_carrier_off(tp->dev);
3301 tg3_link_report(tp);
3302 }
3303
3304 return 0;
3305}
3306
3307struct tg3_fiber_aneginfo {
3308 int state;
3309#define ANEG_STATE_UNKNOWN 0
3310#define ANEG_STATE_AN_ENABLE 1
3311#define ANEG_STATE_RESTART_INIT 2
3312#define ANEG_STATE_RESTART 3
3313#define ANEG_STATE_DISABLE_LINK_OK 4
3314#define ANEG_STATE_ABILITY_DETECT_INIT 5
3315#define ANEG_STATE_ABILITY_DETECT 6
3316#define ANEG_STATE_ACK_DETECT_INIT 7
3317#define ANEG_STATE_ACK_DETECT 8
3318#define ANEG_STATE_COMPLETE_ACK_INIT 9
3319#define ANEG_STATE_COMPLETE_ACK 10
3320#define ANEG_STATE_IDLE_DETECT_INIT 11
3321#define ANEG_STATE_IDLE_DETECT 12
3322#define ANEG_STATE_LINK_OK 13
3323#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3324#define ANEG_STATE_NEXT_PAGE_WAIT 15
3325
3326 u32 flags;
3327#define MR_AN_ENABLE 0x00000001
3328#define MR_RESTART_AN 0x00000002
3329#define MR_AN_COMPLETE 0x00000004
3330#define MR_PAGE_RX 0x00000008
3331#define MR_NP_LOADED 0x00000010
3332#define MR_TOGGLE_TX 0x00000020
3333#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3334#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3335#define MR_LP_ADV_SYM_PAUSE 0x00000100
3336#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3337#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3338#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3339#define MR_LP_ADV_NEXT_PAGE 0x00001000
3340#define MR_TOGGLE_RX 0x00002000
3341#define MR_NP_RX 0x00004000
3342
3343#define MR_LINK_OK 0x80000000
3344
3345 unsigned long link_time, cur_time;
3346
3347 u32 ability_match_cfg;
3348 int ability_match_count;
3349
3350 char ability_match, idle_match, ack_match;
3351
3352 u32 txconfig, rxconfig;
3353#define ANEG_CFG_NP 0x00000080
3354#define ANEG_CFG_ACK 0x00000040
3355#define ANEG_CFG_RF2 0x00000020
3356#define ANEG_CFG_RF1 0x00000010
3357#define ANEG_CFG_PS2 0x00000001
3358#define ANEG_CFG_PS1 0x00008000
3359#define ANEG_CFG_HD 0x00004000
3360#define ANEG_CFG_FD 0x00002000
3361#define ANEG_CFG_INVAL 0x00001f06
3362
3363};
3364#define ANEG_OK 0
3365#define ANEG_DONE 1
3366#define ANEG_TIMER_ENAB 2
3367#define ANEG_FAILED -1
3368
3369#define ANEG_STATE_SETTLE_TIME 10000
3370
3371static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3372 struct tg3_fiber_aneginfo *ap)
3373{
5be73b47 3374 u16 flowctrl;
1da177e4
LT		 3375 unsigned long delta;
3376 u32 rx_cfg_reg;
3377 int ret;
3378
3379 if (ap->state == ANEG_STATE_UNKNOWN) {
3380 ap->rxconfig = 0;
3381 ap->link_time = 0;
3382 ap->cur_time = 0;
3383 ap->ability_match_cfg = 0;
3384 ap->ability_match_count = 0;
3385 ap->ability_match = 0;
3386 ap->idle_match = 0;
3387 ap->ack_match = 0;
3388 }
3389 ap->cur_time++;
3390
3391 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3392 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3393
3394 if (rx_cfg_reg != ap->ability_match_cfg) {
3395 ap->ability_match_cfg = rx_cfg_reg;
3396 ap->ability_match = 0;
3397 ap->ability_match_count = 0;
3398 } else {
3399 if (++ap->ability_match_count > 1) {
3400 ap->ability_match = 1;
3401 ap->ability_match_cfg = rx_cfg_reg;
3402 }
3403 }
3404 if (rx_cfg_reg & ANEG_CFG_ACK)
3405 ap->ack_match = 1;
3406 else
3407 ap->ack_match = 0;
3408
3409 ap->idle_match = 0;
3410 } else {
3411 ap->idle_match = 1;
3412 ap->ability_match_cfg = 0;
3413 ap->ability_match_count = 0;
3414 ap->ability_match = 0;
3415 ap->ack_match = 0;
3416
3417 rx_cfg_reg = 0;
3418 }
3419
3420 ap->rxconfig = rx_cfg_reg;
3421 ret = ANEG_OK;
3422
3423 switch(ap->state) {
3424 case ANEG_STATE_UNKNOWN:
3425 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3426 ap->state = ANEG_STATE_AN_ENABLE;
3427
3428 /* fallthru */
3429 case ANEG_STATE_AN_ENABLE:
3430 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3431 if (ap->flags & MR_AN_ENABLE) {
3432 ap->link_time = 0;
3433 ap->cur_time = 0;
3434 ap->ability_match_cfg = 0;
3435 ap->ability_match_count = 0;
3436 ap->ability_match = 0;
3437 ap->idle_match = 0;
3438 ap->ack_match = 0;
3439
3440 ap->state = ANEG_STATE_RESTART_INIT;
3441 } else {
3442 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3443 }
3444 break;
3445
3446 case ANEG_STATE_RESTART_INIT:
3447 ap->link_time = ap->cur_time;
3448 ap->flags &= ~(MR_NP_LOADED);
3449 ap->txconfig = 0;
3450 tw32(MAC_TX_AUTO_NEG, 0);
3451 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3452 tw32_f(MAC_MODE, tp->mac_mode);
3453 udelay(40);
3454
3455 ret = ANEG_TIMER_ENAB;
3456 ap->state = ANEG_STATE_RESTART;
3457
3458 /* fallthru */
3459 case ANEG_STATE_RESTART:
3460 delta = ap->cur_time - ap->link_time;
3461 if (delta > ANEG_STATE_SETTLE_TIME) {
3462 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3463 } else {
3464 ret = ANEG_TIMER_ENAB;
3465 }
3466 break;
3467
3468 case ANEG_STATE_DISABLE_LINK_OK:
3469 ret = ANEG_DONE;
3470 break;
3471
3472 case ANEG_STATE_ABILITY_DETECT_INIT:
3473 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3474 ap->txconfig = ANEG_CFG_FD;
3475 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3476 if (flowctrl & ADVERTISE_1000XPAUSE)
3477 ap->txconfig |= ANEG_CFG_PS1;
3478 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3479 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3480 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3481 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3482 tw32_f(MAC_MODE, tp->mac_mode);
3483 udelay(40);
3484
3485 ap->state = ANEG_STATE_ABILITY_DETECT;
3486 break;
3487
3488 case ANEG_STATE_ABILITY_DETECT:
3489 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3490 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3491 }
3492 break;
3493
3494 case ANEG_STATE_ACK_DETECT_INIT:
3495 ap->txconfig |= ANEG_CFG_ACK;
3496 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3497 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3498 tw32_f(MAC_MODE, tp->mac_mode);
3499 udelay(40);
3500
3501 ap->state = ANEG_STATE_ACK_DETECT;
3502
3503 /* fallthru */
3504 case ANEG_STATE_ACK_DETECT:
3505 if (ap->ack_match != 0) {
3506 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3507 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3508 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3509 } else {
3510 ap->state = ANEG_STATE_AN_ENABLE;
3511 }
3512 } else if (ap->ability_match != 0 &&
3513 ap->rxconfig == 0) {
3514 ap->state = ANEG_STATE_AN_ENABLE;
3515 }
3516 break;
3517
3518 case ANEG_STATE_COMPLETE_ACK_INIT:
3519 if (ap->rxconfig & ANEG_CFG_INVAL) {
3520 ret = ANEG_FAILED;
3521 break;
3522 }
3523 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3524 MR_LP_ADV_HALF_DUPLEX |
3525 MR_LP_ADV_SYM_PAUSE |
3526 MR_LP_ADV_ASYM_PAUSE |
3527 MR_LP_ADV_REMOTE_FAULT1 |
3528 MR_LP_ADV_REMOTE_FAULT2 |
3529 MR_LP_ADV_NEXT_PAGE |
3530 MR_TOGGLE_RX |
3531 MR_NP_RX);
3532 if (ap->rxconfig & ANEG_CFG_FD)
3533 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3534 if (ap->rxconfig & ANEG_CFG_HD)
3535 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3536 if (ap->rxconfig & ANEG_CFG_PS1)
3537 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3538 if (ap->rxconfig & ANEG_CFG_PS2)
3539 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3540 if (ap->rxconfig & ANEG_CFG_RF1)
3541 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3542 if (ap->rxconfig & ANEG_CFG_RF2)
3543 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3544 if (ap->rxconfig & ANEG_CFG_NP)
3545 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3546
3547 ap->link_time = ap->cur_time;
3548
3549 ap->flags ^= (MR_TOGGLE_TX);
3550 if (ap->rxconfig & 0x0008)
3551 ap->flags |= MR_TOGGLE_RX;
3552 if (ap->rxconfig & ANEG_CFG_NP)
3553 ap->flags |= MR_NP_RX;
3554 ap->flags |= MR_PAGE_RX;
3555
3556 ap->state = ANEG_STATE_COMPLETE_ACK;
3557 ret = ANEG_TIMER_ENAB;
3558 break;
3559
3560 case ANEG_STATE_COMPLETE_ACK:
3561 if (ap->ability_match != 0 &&
3562 ap->rxconfig == 0) {
3563 ap->state = ANEG_STATE_AN_ENABLE;
3564 break;
3565 }
3566 delta = ap->cur_time - ap->link_time;
3567 if (delta > ANEG_STATE_SETTLE_TIME) {
3568 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3569 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3570 } else {
3571 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3572 !(ap->flags & MR_NP_RX)) {
3573 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3574 } else {
3575 ret = ANEG_FAILED;
3576 }
3577 }
3578 }
3579 break;
3580
3581 case ANEG_STATE_IDLE_DETECT_INIT:
3582 ap->link_time = ap->cur_time;
3583 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3584 tw32_f(MAC_MODE, tp->mac_mode);
3585 udelay(40);
3586
3587 ap->state = ANEG_STATE_IDLE_DETECT;
3588 ret = ANEG_TIMER_ENAB;
3589 break;
3590
3591 case ANEG_STATE_IDLE_DETECT:
3592 if (ap->ability_match != 0 &&
3593 ap->rxconfig == 0) {
3594 ap->state = ANEG_STATE_AN_ENABLE;
3595 break;
3596 }
3597 delta = ap->cur_time - ap->link_time;
3598 if (delta > ANEG_STATE_SETTLE_TIME) {
3599 /* XXX another gem from the Broadcom driver :( */
3600 ap->state = ANEG_STATE_LINK_OK;
3601 }
3602 break;
3603
3604 case ANEG_STATE_LINK_OK:
3605 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3606 ret = ANEG_DONE;
3607 break;
3608
3609 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3610 /* ??? unimplemented */
3611 break;
3612
3613 case ANEG_STATE_NEXT_PAGE_WAIT:
3614 /* ??? unimplemented */
3615 break;
3616
3617 default:
3618 ret = ANEG_FAILED;
3619 break;
855e1111 3620 }
1da177e4
LT		 3621
3622 return ret;
3623}
3624
5be73b47 3625static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3626{
3627 int res = 0;
3628 struct tg3_fiber_aneginfo aninfo;
3629 int status = ANEG_FAILED;
3630 unsigned int tick;
3631 u32 tmp;
3632
3633 tw32_f(MAC_TX_AUTO_NEG, 0);
3634
3635 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3636 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3637 udelay(40);
3638
3639 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3640 udelay(40);
3641
3642 memset(&aninfo, 0, sizeof(aninfo));
3643 aninfo.flags |= MR_AN_ENABLE;
3644 aninfo.state = ANEG_STATE_UNKNOWN;
3645 aninfo.cur_time = 0;
3646 tick = 0;
3647 while (++tick < 195000) {
3648 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3649 if (status == ANEG_DONE || status == ANEG_FAILED)
3650 break;
3651
3652 udelay(1);
3653 }
3654
3655 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3656 tw32_f(MAC_MODE, tp->mac_mode);
3657 udelay(40);
3658
5be73b47
MC		 3659 *txflags = aninfo.txconfig;
3660 *rxflags = aninfo.flags;
1da177e4
LT		 3661
3662 if (status == ANEG_DONE &&
3663 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3664 MR_LP_ADV_FULL_DUPLEX)))
3665 res = 1;
3666
3667 return res;
3668}
3669
3670static void tg3_init_bcm8002(struct tg3 *tp)
3671{
3672 u32 mac_status = tr32(MAC_STATUS);
3673 int i;
3674
3675 /* Reset when initting first time or we have a link. */
3676 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3677 !(mac_status & MAC_STATUS_PCS_SYNCED))
3678 return;
3679
3680 /* Set PLL lock range. */
3681 tg3_writephy(tp, 0x16, 0x8007);
3682
3683 /* SW reset */
3684 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3685
3686 /* Wait for reset to complete. */
3687 /* XXX schedule_timeout() ... */
3688 for (i = 0; i < 500; i++)
3689 udelay(10);
3690
3691 /* Config mode; select PMA/Ch 1 regs. */
3692 tg3_writephy(tp, 0x10, 0x8411);
3693
3694 /* Enable auto-lock and comdet, select txclk for tx. */
3695 tg3_writephy(tp, 0x11, 0x0a10);
3696
3697 tg3_writephy(tp, 0x18, 0x00a0);
3698 tg3_writephy(tp, 0x16, 0x41ff);
3699
3700 /* Assert and deassert POR. */
3701 tg3_writephy(tp, 0x13, 0x0400);
3702 udelay(40);
3703 tg3_writephy(tp, 0x13, 0x0000);
3704
3705 tg3_writephy(tp, 0x11, 0x0a50);
3706 udelay(40);
3707 tg3_writephy(tp, 0x11, 0x0a10);
3708
3709 /* Wait for signal to stabilize */
3710 /* XXX schedule_timeout() ... */
3711 for (i = 0; i < 15000; i++)
3712 udelay(10);
3713
3714 /* Deselect the channel register so we can read the PHYID
3715 * later.
3716 */
3717 tg3_writephy(tp, 0x10, 0x8011);
3718}
3719
3720static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3721{
82cd3d11 3722 u16 flowctrl;
1da177e4
LT		 3723 u32 sg_dig_ctrl, sg_dig_status;
3724 u32 serdes_cfg, expected_sg_dig_ctrl;
3725 int workaround, port_a;
3726 int current_link_up;
3727
3728 serdes_cfg = 0;
3729 expected_sg_dig_ctrl = 0;
3730 workaround = 0;
3731 port_a = 1;
3732 current_link_up = 0;
3733
3734 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3735 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3736 workaround = 1;
3737 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3738 port_a = 0;
3739
3740 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3741 /* preserve bits 20-23 for voltage regulator */
3742 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3743 }
3744
3745 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3746
3747 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3748 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3749 if (workaround) {
3750 u32 val = serdes_cfg;
3751
3752 if (port_a)
3753 val |= 0xc010000;
3754 else
3755 val |= 0x4010000;
3756 tw32_f(MAC_SERDES_CFG, val);
3757 }
c98f6e3b
MC		 3758
3759 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3760 }
3761 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3762 tg3_setup_flow_control(tp, 0, 0);
3763 current_link_up = 1;
3764 }
3765 goto out;
3766 }
3767
3768 /* Want auto-negotiation. */
c98f6e3b 3769 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3770
82cd3d11
MC		 3771 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3772 if (flowctrl & ADVERTISE_1000XPAUSE)
3773 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3774 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3775 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3776
3777 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3778 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3779 tp->serdes_counter &&
3780 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3781 MAC_STATUS_RCVD_CFG)) ==
3782 MAC_STATUS_PCS_SYNCED)) {
3783 tp->serdes_counter--;
3784 current_link_up = 1;
3785 goto out;
3786 }
3787restart_autoneg:
1da177e4
LT		 3788 if (workaround)
3789 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3790 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3791 udelay(5);
3792 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3793
3d3ebe74
MC		 3794 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3795 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3796 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3797 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3798 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3799 mac_status = tr32(MAC_STATUS);
3800
c98f6e3b 3801 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3802 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3803 u32 local_adv = 0, remote_adv = 0;
3804
3805 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3806 local_adv |= ADVERTISE_1000XPAUSE;
3807 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3808 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3809
c98f6e3b 3810 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3811 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3812 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3813 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3814
3815 tg3_setup_flow_control(tp, local_adv, remote_adv);
3816 current_link_up = 1;
3d3ebe74
MC		 3817 tp->serdes_counter = 0;
3818 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3819 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3820 if (tp->serdes_counter)
3821 tp->serdes_counter--;
1da177e4
LT		 3822 else {
3823 if (workaround) {
3824 u32 val = serdes_cfg;
3825
3826 if (port_a)
3827 val |= 0xc010000;
3828 else
3829 val |= 0x4010000;
3830
3831 tw32_f(MAC_SERDES_CFG, val);
3832 }
3833
c98f6e3b 3834 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3835 udelay(40);
3836
3837 /* Link parallel detection - link is up */
3838 /* only if we have PCS_SYNC and not */
3839 /* receiving config code words */
3840 mac_status = tr32(MAC_STATUS);
3841 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3842 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3843 tg3_setup_flow_control(tp, 0, 0);
3844 current_link_up = 1;
3d3ebe74
MC		 3845 tp->tg3_flags2 |=
3846 TG3_FLG2_PARALLEL_DETECT;
3847 tp->serdes_counter =
3848 SERDES_PARALLEL_DET_TIMEOUT;
3849 } else
3850 goto restart_autoneg;
1da177e4
LT		 3851 }
3852 }
3d3ebe74
MC		 3853 } else {
3854 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3855 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3856 }
3857
3858out:
3859 return current_link_up;
3860}
3861
3862static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3863{
3864 int current_link_up = 0;
3865
5cf64b8a 3866 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3867 goto out;
1da177e4
LT		 3868
3869 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3870 u32 txflags, rxflags;
1da177e4 3871 int i;
6aa20a22 3872
5be73b47
MC		 3873 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3874 u32 local_adv = 0, remote_adv = 0;
1da177e4 3875
5be73b47
MC		 3876 if (txflags & ANEG_CFG_PS1)
3877 local_adv |= ADVERTISE_1000XPAUSE;
3878 if (txflags & ANEG_CFG_PS2)
3879 local_adv |= ADVERTISE_1000XPSE_ASYM;
3880
3881 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3882 remote_adv |= LPA_1000XPAUSE;
3883 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3884 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3885
3886 tg3_setup_flow_control(tp, local_adv, remote_adv);
3887
1da177e4
LT		 3888 current_link_up = 1;
3889 }
3890 for (i = 0; i < 30; i++) {
3891 udelay(20);
3892 tw32_f(MAC_STATUS,
3893 (MAC_STATUS_SYNC_CHANGED |
3894 MAC_STATUS_CFG_CHANGED));
3895 udelay(40);
3896 if ((tr32(MAC_STATUS) &
3897 (MAC_STATUS_SYNC_CHANGED |
3898 MAC_STATUS_CFG_CHANGED)) == 0)
3899 break;
3900 }
3901
3902 mac_status = tr32(MAC_STATUS);
3903 if (current_link_up == 0 &&
3904 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3905 !(mac_status & MAC_STATUS_RCVD_CFG))
3906 current_link_up = 1;
3907 } else {
5be73b47
MC		 3908 tg3_setup_flow_control(tp, 0, 0);
3909
1da177e4
LT		 3910 /* Forcing 1000FD link up. */
3911 current_link_up = 1;
1da177e4
LT		 3912
3913 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3914 udelay(40);
e8f3f6ca
MC		 3915
3916 tw32_f(MAC_MODE, tp->mac_mode);
3917 udelay(40);
1da177e4
LT		 3918 }
3919
3920out:
3921 return current_link_up;
3922}
3923
3924static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3925{
3926 u32 orig_pause_cfg;
3927 u16 orig_active_speed;
3928 u8 orig_active_duplex;
3929 u32 mac_status;
3930 int current_link_up;
3931 int i;
3932
8d018621 3933 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3934 orig_active_speed = tp->link_config.active_speed;
3935 orig_active_duplex = tp->link_config.active_duplex;
3936
3937 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3938 netif_carrier_ok(tp->dev) &&
3939 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3940 mac_status = tr32(MAC_STATUS);
3941 mac_status &= (MAC_STATUS_PCS_SYNCED |
3942 MAC_STATUS_SIGNAL_DET |
3943 MAC_STATUS_CFG_CHANGED |
3944 MAC_STATUS_RCVD_CFG);
3945 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3946 MAC_STATUS_SIGNAL_DET)) {
3947 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3948 MAC_STATUS_CFG_CHANGED));
3949 return 0;
3950 }
3951 }
3952
3953 tw32_f(MAC_TX_AUTO_NEG, 0);
3954
3955 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3956 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3957 tw32_f(MAC_MODE, tp->mac_mode);
3958 udelay(40);
3959
3960 if (tp->phy_id == PHY_ID_BCM8002)
3961 tg3_init_bcm8002(tp);
3962
3963 /* Enable link change event even when serdes polling. */
3964 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3965 udelay(40);
3966
3967 current_link_up = 0;
3968 mac_status = tr32(MAC_STATUS);
3969
3970 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3971 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3972 else
3973 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3974
898a56f8 3975 tp->napi[0].hw_status->status =
1da177e4 3976 (SD_STATUS_UPDATED |
898a56f8 3977 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3978
3979 for (i = 0; i < 100; i++) {
3980 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3981 MAC_STATUS_CFG_CHANGED));
3982 udelay(5);
3983 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3984 MAC_STATUS_CFG_CHANGED |
3985 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3986 break;
3987 }
3988
3989 mac_status = tr32(MAC_STATUS);
3990 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3991 current_link_up = 0;
3d3ebe74
MC		 3992 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3993 tp->serdes_counter == 0) {
1da177e4
LT		 3994 tw32_f(MAC_MODE, (tp->mac_mode |
3995 MAC_MODE_SEND_CONFIGS));
3996 udelay(1);
3997 tw32_f(MAC_MODE, tp->mac_mode);
3998 }
3999 }
4000
4001 if (current_link_up == 1) {
4002 tp->link_config.active_speed = SPEED_1000;
4003 tp->link_config.active_duplex = DUPLEX_FULL;
4004 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4005 LED_CTRL_LNKLED_OVERRIDE |
4006 LED_CTRL_1000MBPS_ON));
4007 } else {
4008 tp->link_config.active_speed = SPEED_INVALID;
4009 tp->link_config.active_duplex = DUPLEX_INVALID;
4010 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4011 LED_CTRL_LNKLED_OVERRIDE |
4012 LED_CTRL_TRAFFIC_OVERRIDE));
4013 }
4014
4015 if (current_link_up != netif_carrier_ok(tp->dev)) {
4016 if (current_link_up)
4017 netif_carrier_on(tp->dev);
4018 else
4019 netif_carrier_off(tp->dev);
4020 tg3_link_report(tp);
4021 } else {
8d018621 4022 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4023 if (orig_pause_cfg != now_pause_cfg ||
4024 orig_active_speed != tp->link_config.active_speed ||
4025 orig_active_duplex != tp->link_config.active_duplex)
4026 tg3_link_report(tp);
4027 }
4028
4029 return 0;
4030}
4031
747e8f8b
MC		 4032static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4033{
4034 int current_link_up, err = 0;
4035 u32 bmsr, bmcr;
4036 u16 current_speed;
4037 u8 current_duplex;
ef167e27 4038 u32 local_adv, remote_adv;
747e8f8b
MC		 4039
4040 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4041 tw32_f(MAC_MODE, tp->mac_mode);
4042 udelay(40);
4043
4044 tw32(MAC_EVENT, 0);
4045
4046 tw32_f(MAC_STATUS,
4047 (MAC_STATUS_SYNC_CHANGED |
4048 MAC_STATUS_CFG_CHANGED |
4049 MAC_STATUS_MI_COMPLETION |
4050 MAC_STATUS_LNKSTATE_CHANGED));
4051 udelay(40);
4052
4053 if (force_reset)
4054 tg3_phy_reset(tp);
4055
4056 current_link_up = 0;
4057 current_speed = SPEED_INVALID;
4058 current_duplex = DUPLEX_INVALID;
4059
4060 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4061 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4063 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4064 bmsr |= BMSR_LSTATUS;
4065 else
4066 bmsr &= ~BMSR_LSTATUS;
4067 }
747e8f8b
MC		 4068
4069 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4070
4071 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4072 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4073 /* do nothing, just check for link up at the end */
4074 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4075 u32 adv, new_adv;
4076
4077 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4078 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4079 ADVERTISE_1000XPAUSE |
4080 ADVERTISE_1000XPSE_ASYM |
4081 ADVERTISE_SLCT);
4082
ba4d07a8 4083 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4084
4085 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4086 new_adv |= ADVERTISE_1000XHALF;
4087 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4088 new_adv |= ADVERTISE_1000XFULL;
4089
4090 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4091 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4092 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4093 tg3_writephy(tp, MII_BMCR, bmcr);
4094
4095 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4096 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4097 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4098
4099 return err;
4100 }
4101 } else {
4102 u32 new_bmcr;
4103
4104 bmcr &= ~BMCR_SPEED1000;
4105 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4106
4107 if (tp->link_config.duplex == DUPLEX_FULL)
4108 new_bmcr |= BMCR_FULLDPLX;
4109
4110 if (new_bmcr != bmcr) {
4111 /* BMCR_SPEED1000 is a reserved bit that needs
4112 * to be set on write.
4113 */
4114 new_bmcr |= BMCR_SPEED1000;
4115
4116 /* Force a linkdown */
4117 if (netif_carrier_ok(tp->dev)) {
4118 u32 adv;
4119
4120 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4121 adv &= ~(ADVERTISE_1000XFULL |
4122 ADVERTISE_1000XHALF |
4123 ADVERTISE_SLCT);
4124 tg3_writephy(tp, MII_ADVERTISE, adv);
4125 tg3_writephy(tp, MII_BMCR, bmcr |
4126 BMCR_ANRESTART |
4127 BMCR_ANENABLE);
4128 udelay(10);
4129 netif_carrier_off(tp->dev);
4130 }
4131 tg3_writephy(tp, MII_BMCR, new_bmcr);
4132 bmcr = new_bmcr;
4133 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4134 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4135 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4136 ASIC_REV_5714) {
4137 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4138 bmsr |= BMSR_LSTATUS;
4139 else
4140 bmsr &= ~BMSR_LSTATUS;
4141 }
747e8f8b
MC		 4142 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4143 }
4144 }
4145
4146 if (bmsr & BMSR_LSTATUS) {
4147 current_speed = SPEED_1000;
4148 current_link_up = 1;
4149 if (bmcr & BMCR_FULLDPLX)
4150 current_duplex = DUPLEX_FULL;
4151 else
4152 current_duplex = DUPLEX_HALF;
4153
ef167e27
MC		 4154 local_adv = 0;
4155 remote_adv = 0;
4156
747e8f8b 4157 if (bmcr & BMCR_ANENABLE) {
ef167e27 4158 u32 common;
747e8f8b
MC		 4159
4160 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4161 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4162 common = local_adv & remote_adv;
4163 if (common & (ADVERTISE_1000XHALF |
4164 ADVERTISE_1000XFULL)) {
4165 if (common & ADVERTISE_1000XFULL)
4166 current_duplex = DUPLEX_FULL;
4167 else
4168 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4169 }
4170 else
4171 current_link_up = 0;
4172 }
4173 }
4174
ef167e27
MC		 4175 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4176 tg3_setup_flow_control(tp, local_adv, remote_adv);
4177
747e8f8b
MC		 4178 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4179 if (tp->link_config.active_duplex == DUPLEX_HALF)
4180 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4181
4182 tw32_f(MAC_MODE, tp->mac_mode);
4183 udelay(40);
4184
4185 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4186
4187 tp->link_config.active_speed = current_speed;
4188 tp->link_config.active_duplex = current_duplex;
4189
4190 if (current_link_up != netif_carrier_ok(tp->dev)) {
4191 if (current_link_up)
4192 netif_carrier_on(tp->dev);
4193 else {
4194 netif_carrier_off(tp->dev);
4195 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4196 }
4197 tg3_link_report(tp);
4198 }
4199 return err;
4200}
4201
4202static void tg3_serdes_parallel_detect(struct tg3 *tp)
4203{
3d3ebe74 4204 if (tp->serdes_counter) {
747e8f8b 4205 /* Give autoneg time to complete. */
3d3ebe74 4206 tp->serdes_counter--;
747e8f8b
MC		 4207 return;
4208 }
4209 if (!netif_carrier_ok(tp->dev) &&
4210 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4211 u32 bmcr;
4212
4213 tg3_readphy(tp, MII_BMCR, &bmcr);
4214 if (bmcr & BMCR_ANENABLE) {
4215 u32 phy1, phy2;
4216
4217 /* Select shadow register 0x1f */
4218 tg3_writephy(tp, 0x1c, 0x7c00);
4219 tg3_readphy(tp, 0x1c, &phy1);
4220
4221 /* Select expansion interrupt status register */
4222 tg3_writephy(tp, 0x17, 0x0f01);
4223 tg3_readphy(tp, 0x15, &phy2);
4224 tg3_readphy(tp, 0x15, &phy2);
4225
4226 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4227 /* We have signal detect and not receiving
4228 * config code words, link is up by parallel
4229 * detection.
4230 */
4231
4232 bmcr &= ~BMCR_ANENABLE;
4233 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4234 tg3_writephy(tp, MII_BMCR, bmcr);
4235 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4236 }
4237 }
4238 }
4239 else if (netif_carrier_ok(tp->dev) &&
4240 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4241 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4242 u32 phy2;
4243
4244 /* Select expansion interrupt status register */
4245 tg3_writephy(tp, 0x17, 0x0f01);
4246 tg3_readphy(tp, 0x15, &phy2);
4247 if (phy2 & 0x20) {
4248 u32 bmcr;
4249
4250 /* Config code words received, turn on autoneg. */
4251 tg3_readphy(tp, MII_BMCR, &bmcr);
4252 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4253
4254 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4255
4256 }
4257 }
4258}
4259
1da177e4
LT		 4260static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4261{
4262 int err;
4263
4264 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4265 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4266 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4267 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4268 } else {
4269 err = tg3_setup_copper_phy(tp, force_reset);
4270 }
4271
bcb37f6c 4272 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4273 u32 val, scale;
4274
4275 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4276 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4277 scale = 65;
4278 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4279 scale = 6;
4280 else
4281 scale = 12;
4282
4283 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4284 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4285 tw32(GRC_MISC_CFG, val);
4286 }
4287
1da177e4
LT		 4288 if (tp->link_config.active_speed == SPEED_1000 &&
4289 tp->link_config.active_duplex == DUPLEX_HALF)
4290 tw32(MAC_TX_LENGTHS,
4291 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4292 (6 << TX_LENGTHS_IPG_SHIFT) |
4293 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4294 else
4295 tw32(MAC_TX_LENGTHS,
4296 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4297 (6 << TX_LENGTHS_IPG_SHIFT) |
4298 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4299
4300 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4301 if (netif_carrier_ok(tp->dev)) {
4302 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4303 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4304 } else {
4305 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4306 }
4307 }
4308
8ed5d97e
MC		 4309 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4310 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4311 if (!netif_carrier_ok(tp->dev))
4312 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4313 tp->pwrmgmt_thresh;
4314 else
4315 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4316 tw32(PCIE_PWR_MGMT_THRESH, val);
4317 }
4318
1da177e4
LT		 4319 return err;
4320}
4321
df3e6548
MC		 4322/* This is called whenever we suspect that the system chipset is re-
4323 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4324 * is bogus tx completions. We try to recover by setting the
4325 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4326 * in the workqueue.
4327 */
4328static void tg3_tx_recover(struct tg3 *tp)
4329{
4330 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4331 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4332
4333 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4334 "mapped I/O cycles to the network device, attempting to "
4335 "recover. Please report the problem to the driver maintainer "
4336 "and include system chipset information.\n", tp->dev->name);
4337
4338 spin_lock(&tp->lock);
df3e6548 4339 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4340 spin_unlock(&tp->lock);
4341}
4342
f3f3f27e 4343static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4344{
4345 smp_mb();
f3f3f27e
MC		 4346 return tnapi->tx_pending -
4347 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4348}
4349
1da177e4
LT		 4350/* Tigon3 never reports partial packet sends. So we do not
4351 * need special logic to handle SKBs that have not had all
4352 * of their frags sent yet, like SunGEM does.
4353 */
17375d25 4354static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4355{
17375d25 4356 struct tg3 *tp = tnapi->tp;
898a56f8 4357 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4358 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4359 struct netdev_queue *txq;
4360 int index = tnapi - tp->napi;
4361
19cfaecc 4362 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787
MC		 4363 index--;
4364
4365 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4366
4367 while (sw_idx != hw_idx) {
f4188d8a 4368 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4369 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4370 int i, tx_bug = 0;
4371
4372 if (unlikely(skb == NULL)) {
4373 tg3_tx_recover(tp);
4374 return;
4375 }
1da177e4 4376
f4188d8a
AD		 4377 pci_unmap_single(tp->pdev,
4378 pci_unmap_addr(ri, mapping),
4379 skb_headlen(skb),
4380 PCI_DMA_TODEVICE);
1da177e4
LT		 4381
4382 ri->skb = NULL;
4383
4384 sw_idx = NEXT_TX(sw_idx);
4385
4386 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4387 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4388 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4389 tx_bug = 1;
f4188d8a
AD		 4390
4391 pci_unmap_page(tp->pdev,
4392 pci_unmap_addr(ri, mapping),
4393 skb_shinfo(skb)->frags[i].size,
4394 PCI_DMA_TODEVICE);
1da177e4
LT		 4395 sw_idx = NEXT_TX(sw_idx);
4396 }
4397
f47c11ee 4398 dev_kfree_skb(skb);
df3e6548
MC		 4399
4400 if (unlikely(tx_bug)) {
4401 tg3_tx_recover(tp);
4402 return;
4403 }
1da177e4
LT		 4404 }
4405
f3f3f27e 4406 tnapi->tx_cons = sw_idx;
1da177e4 4407
1b2a7205
MC		 4408 /* Need to make the tx_cons update visible to tg3_start_xmit()
4409 * before checking for netif_queue_stopped(). Without the
4410 * memory barrier, there is a small possibility that tg3_start_xmit()
4411 * will miss it and cause the queue to be stopped forever.
4412 */
4413 smp_mb();
4414
fe5f5787 4415 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4416 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4417 __netif_tx_lock(txq, smp_processor_id());
4418 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4419 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4420 netif_tx_wake_queue(txq);
4421 __netif_tx_unlock(txq);
51b91468 4422 }
1da177e4
LT		 4423}
4424
2b2cdb65
MC		 4425static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4426{
4427 if (!ri->skb)
4428 return;
4429
4430 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4431 map_sz, PCI_DMA_FROMDEVICE);
4432 dev_kfree_skb_any(ri->skb);
4433 ri->skb = NULL;
4434}
4435
1da177e4
LT		 4436/* Returns size of skb allocated or < 0 on error.
4437 *
4438 * We only need to fill in the address because the other members
4439 * of the RX descriptor are invariant, see tg3_init_rings.
4440 *
4441 * Note the purposeful assymetry of cpu vs. chip accesses. For
4442 * posting buffers we only dirty the first cache line of the RX
4443 * descriptor (containing the address). Whereas for the RX status
4444 * buffers the cpu only reads the last cacheline of the RX descriptor
4445 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4446 */
86b21e59 4447static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4448 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4449{
4450 struct tg3_rx_buffer_desc *desc;
4451 struct ring_info *map, *src_map;
4452 struct sk_buff *skb;
4453 dma_addr_t mapping;
4454 int skb_size, dest_idx;
4455
4456 src_map = NULL;
4457 switch (opaque_key) {
4458 case RXD_OPAQUE_RING_STD:
4459 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4460 desc = &tpr->rx_std[dest_idx];
4461 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4462 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4463 break;
4464
4465 case RXD_OPAQUE_RING_JUMBO:
4466 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4467 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4468 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4469 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4470 break;
4471
4472 default:
4473 return -EINVAL;
855e1111 4474 }
1da177e4
LT		 4475
4476 /* Do not overwrite any of the map or rp information
4477 * until we are sure we can commit to a new buffer.
4478 *
4479 * Callers depend upon this behavior and assume that
4480 * we leave everything unchanged if we fail.
4481 */
287be12e 4482 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4483 if (skb == NULL)
4484 return -ENOMEM;
4485
1da177e4
LT		 4486 skb_reserve(skb, tp->rx_offset);
4487
287be12e 4488 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4489 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4490 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4491 dev_kfree_skb(skb);
4492 return -EIO;
4493 }
1da177e4
LT		 4494
4495 map->skb = skb;
4496 pci_unmap_addr_set(map, mapping, mapping);
4497
1da177e4
LT		 4498 desc->addr_hi = ((u64)mapping >> 32);
4499 desc->addr_lo = ((u64)mapping & 0xffffffff);
4500
4501 return skb_size;
4502}
4503
4504/* We only need to move over in the address because the other
4505 * members of the RX descriptor are invariant. See notes above
4506 * tg3_alloc_rx_skb for full details.
4507 */
a3896167
MC		 4508static void tg3_recycle_rx(struct tg3_napi *tnapi,
4509 struct tg3_rx_prodring_set *dpr,
4510 u32 opaque_key, int src_idx,
4511 u32 dest_idx_unmasked)
1da177e4 4512{
17375d25 4513 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4514 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4515 struct ring_info *src_map, *dest_map;
4516 int dest_idx;
a3896167 4517 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4518
4519 switch (opaque_key) {
4520 case RXD_OPAQUE_RING_STD:
4521 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4522 dest_desc = &dpr->rx_std[dest_idx];
4523 dest_map = &dpr->rx_std_buffers[dest_idx];
4524 src_desc = &spr->rx_std[src_idx];
4525 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4526 break;
4527
4528 case RXD_OPAQUE_RING_JUMBO:
4529 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4530 dest_desc = &dpr->rx_jmb[dest_idx].std;
4531 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4532 src_desc = &spr->rx_jmb[src_idx].std;
4533 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4534 break;
4535
4536 default:
4537 return;
855e1111 4538 }
1da177e4
LT		 4539
4540 dest_map->skb = src_map->skb;
4541 pci_unmap_addr_set(dest_map, mapping,
4542 pci_unmap_addr(src_map, mapping));
4543 dest_desc->addr_hi = src_desc->addr_hi;
4544 dest_desc->addr_lo = src_desc->addr_lo;
1da177e4
LT		 4545 src_map->skb = NULL;
4546}
4547
1da177e4
LT		 4548/* The RX ring scheme is composed of multiple rings which post fresh
4549 * buffers to the chip, and one special ring the chip uses to report
4550 * status back to the host.
4551 *
4552 * The special ring reports the status of received packets to the
4553 * host. The chip does not write into the original descriptor the
4554 * RX buffer was obtained from. The chip simply takes the original
4555 * descriptor as provided by the host, updates the status and length
4556 * field, then writes this into the next status ring entry.
4557 *
4558 * Each ring the host uses to post buffers to the chip is described
4559 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4560 * it is first placed into the on-chip ram. When the packet's length
4561 * is known, it walks down the TG3_BDINFO entries to select the ring.
4562 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4563 * which is within the range of the new packet's length is chosen.
4564 *
4565 * The "separate ring for rx status" scheme may sound queer, but it makes
4566 * sense from a cache coherency perspective. If only the host writes
4567 * to the buffer post rings, and only the chip writes to the rx status
4568 * rings, then cache lines never move beyond shared-modified state.
4569 * If both the host and chip were to write into the same ring, cache line
4570 * eviction could occur since both entities want it in an exclusive state.
4571 */
17375d25 4572static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4573{
17375d25 4574 struct tg3 *tp = tnapi->tp;
f92905de 4575 u32 work_mask, rx_std_posted = 0;
4361935a 4576 u32 std_prod_idx, jmb_prod_idx;
72334482 4577 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4578 u16 hw_idx;
1da177e4 4579 int received;
b196c7e4 4580 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4581
8d9d7cfc 4582 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4583 /*
4584 * We need to order the read of hw_idx and the read of
4585 * the opaque cookie.
4586 */
4587 rmb();
1da177e4
LT		 4588 work_mask = 0;
4589 received = 0;
4361935a
MC		 4590 std_prod_idx = tpr->rx_std_prod_idx;
4591 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4592 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4593 struct ring_info *ri;
72334482 4594 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4595 unsigned int len;
4596 struct sk_buff *skb;
4597 dma_addr_t dma_addr;
4598 u32 opaque_key, desc_idx, *post_ptr;
4599
4600 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4601 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4602 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4603 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4604 dma_addr = pci_unmap_addr(ri, mapping);
4605 skb = ri->skb;
4361935a 4606 post_ptr = &std_prod_idx;
f92905de 4607 rx_std_posted++;
1da177e4 4608 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4609 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4610 dma_addr = pci_unmap_addr(ri, mapping);
4611 skb = ri->skb;
4361935a 4612 post_ptr = &jmb_prod_idx;
21f581a5 4613 } else
1da177e4 4614 goto next_pkt_nopost;
1da177e4
LT		 4615
4616 work_mask |= opaque_key;
4617
4618 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4619 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4620 drop_it:
a3896167 4621 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4622 desc_idx, *post_ptr);
4623 drop_it_no_recycle:
4624 /* Other statistics kept track of by card. */
4625 tp->net_stats.rx_dropped++;
4626 goto next_pkt;
4627 }
4628
ad829268
MC		 4629 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4630 ETH_FCS_LEN;
1da177e4 4631
8e95a202
JP		 4632 if (len > RX_COPY_THRESHOLD &&
4633 tp->rx_offset == NET_IP_ALIGN) {
4634 /* rx_offset will likely not equal NET_IP_ALIGN
4635 * if this is a 5701 card running in PCI-X mode
4636 * [see tg3_get_invariants()]
4637 */
1da177e4
LT		 4638 int skb_size;
4639
86b21e59 4640 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4641 *post_ptr);
1da177e4
LT		 4642 if (skb_size < 0)
4643 goto drop_it;
4644
afc081f8
MC		 4645 ri->skb = NULL;
4646
287be12e 4647 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4648 PCI_DMA_FROMDEVICE);
4649
4650 skb_put(skb, len);
4651 } else {
4652 struct sk_buff *copy_skb;
4653
a3896167 4654 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4655 desc_idx, *post_ptr);
4656
ad829268
MC		 4657 copy_skb = netdev_alloc_skb(tp->dev,
4658 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4659 if (copy_skb == NULL)
4660 goto drop_it_no_recycle;
4661
ad829268 4662 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4663 skb_put(copy_skb, len);
4664 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4665 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4666 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4667
4668 /* We'll reuse the original ring buffer. */
4669 skb = copy_skb;
4670 }
4671
4672 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4673 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4674 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4675 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4676 skb->ip_summed = CHECKSUM_UNNECESSARY;
4677 else
4678 skb->ip_summed = CHECKSUM_NONE;
4679
4680 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4681
4682 if (len > (tp->dev->mtu + ETH_HLEN) &&
4683 skb->protocol != htons(ETH_P_8021Q)) {
4684 dev_kfree_skb(skb);
4685 goto next_pkt;
4686 }
4687
1da177e4
LT		 4688#if TG3_VLAN_TAG_USED
4689 if (tp->vlgrp != NULL &&
4690 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4691 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4692 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4693 } else
4694#endif
17375d25 4695 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4696
1da177e4
LT		 4697 received++;
4698 budget--;
4699
4700next_pkt:
4701 (*post_ptr)++;
f92905de
MC		 4702
4703 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4704 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
66711e66 4705 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
f92905de
MC		 4706 work_mask &= ~RXD_OPAQUE_RING_STD;
4707 rx_std_posted = 0;
4708 }
1da177e4 4709next_pkt_nopost:
483ba50b 4710 sw_idx++;
6b31a515 4711 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4712
4713 /* Refresh hw_idx to see if there is new work */
4714 if (sw_idx == hw_idx) {
8d9d7cfc 4715 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4716 rmb();
4717 }
1da177e4
LT		 4718 }
4719
4720 /* ACK the status ring. */
72334482
MC		 4721 tnapi->rx_rcb_ptr = sw_idx;
4722 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4723
4724 /* Refill RX ring(s). */
b196c7e4
MC		 4725 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4726 if (work_mask & RXD_OPAQUE_RING_STD) {
4727 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4728 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4729 tpr->rx_std_prod_idx);
4730 }
4731 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4732 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4733 TG3_RX_JUMBO_RING_SIZE;
4734 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4735 tpr->rx_jmb_prod_idx);
4736 }
4737 mmiowb();
4738 } else if (work_mask) {
4739 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4740 * updated before the producer indices can be updated.
4741 */
4742 smp_wmb();
4743
4361935a 4744 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4745 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4
MC		 4746
4747 napi_schedule(&tp->napi[1].napi);
1da177e4 4748 }
1da177e4
LT		 4749
4750 return received;
4751}
4752
35f2d7d0 4753static void tg3_poll_link(struct tg3 *tp)
1da177e4 4754{
1da177e4
LT		 4755 /* handle link change and other phy events */
4756 if (!(tp->tg3_flags &
4757 (TG3_FLAG_USE_LINKCHG_REG |
4758 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4759 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4760
1da177e4
LT		 4761 if (sblk->status & SD_STATUS_LINK_CHG) {
4762 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4763 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4764 spin_lock(&tp->lock);
dd477003
MC		 4765 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4766 tw32_f(MAC_STATUS,
4767 (MAC_STATUS_SYNC_CHANGED |
4768 MAC_STATUS_CFG_CHANGED |
4769 MAC_STATUS_MI_COMPLETION |
4770 MAC_STATUS_LNKSTATE_CHANGED));
4771 udelay(40);
4772 } else
4773 tg3_setup_phy(tp, 0);
f47c11ee 4774 spin_unlock(&tp->lock);
1da177e4
LT		 4775 }
4776 }
35f2d7d0
MC		 4777}
4778
b196c7e4
MC		 4779static void tg3_rx_prodring_xfer(struct tg3 *tp,
4780 struct tg3_rx_prodring_set *dpr,
4781 struct tg3_rx_prodring_set *spr)
4782{
4783 u32 si, di, cpycnt, src_prod_idx;
4784 int i;
4785
4786 while (1) {
4787 src_prod_idx = spr->rx_std_prod_idx;
4788
4789 /* Make sure updates to the rx_std_buffers[] entries and the
4790 * standard producer index are seen in the correct order.
4791 */
4792 smp_rmb();
4793
4794 if (spr->rx_std_cons_idx == src_prod_idx)
4795 break;
4796
4797 if (spr->rx_std_cons_idx < src_prod_idx)
4798 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4799 else
4800 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4801
4802 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4803
4804 si = spr->rx_std_cons_idx;
4805 di = dpr->rx_std_prod_idx;
4806
4807 memcpy(&dpr->rx_std_buffers[di],
4808 &spr->rx_std_buffers[si],
4809 cpycnt * sizeof(struct ring_info));
4810
4811 for (i = 0; i < cpycnt; i++, di++, si++) {
4812 struct tg3_rx_buffer_desc *sbd, *dbd;
4813 sbd = &spr->rx_std[si];
4814 dbd = &dpr->rx_std[di];
4815 dbd->addr_hi = sbd->addr_hi;
4816 dbd->addr_lo = sbd->addr_lo;
4817 }
4818
4819 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4820 TG3_RX_RING_SIZE;
4821 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4822 TG3_RX_RING_SIZE;
4823 }
4824
4825 while (1) {
4826 src_prod_idx = spr->rx_jmb_prod_idx;
4827
4828 /* Make sure updates to the rx_jmb_buffers[] entries and
4829 * the jumbo producer index are seen in the correct order.
4830 */
4831 smp_rmb();
4832
4833 if (spr->rx_jmb_cons_idx == src_prod_idx)
4834 break;
4835
4836 if (spr->rx_jmb_cons_idx < src_prod_idx)
4837 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4838 else
4839 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4840
4841 cpycnt = min(cpycnt,
4842 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4843
4844 si = spr->rx_jmb_cons_idx;
4845 di = dpr->rx_jmb_prod_idx;
4846
4847 memcpy(&dpr->rx_jmb_buffers[di],
4848 &spr->rx_jmb_buffers[si],
4849 cpycnt * sizeof(struct ring_info));
4850
4851 for (i = 0; i < cpycnt; i++, di++, si++) {
4852 struct tg3_rx_buffer_desc *sbd, *dbd;
4853 sbd = &spr->rx_jmb[si].std;
4854 dbd = &dpr->rx_jmb[di].std;
4855 dbd->addr_hi = sbd->addr_hi;
4856 dbd->addr_lo = sbd->addr_lo;
4857 }
4858
4859 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4860 TG3_RX_JUMBO_RING_SIZE;
4861 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4862 TG3_RX_JUMBO_RING_SIZE;
4863 }
4864}
4865
35f2d7d0
MC		 4866static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4867{
4868 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4869
4870 /* run TX completion thread */
f3f3f27e 4871 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4872 tg3_tx(tnapi);
6f535763 4873 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4874 return work_done;
1da177e4
LT		 4875 }
4876
1da177e4
LT		 4877 /* run RX thread, within the bounds set by NAPI.
4878 * All RX "locking" is done by ensuring outside
bea3348e 4879 * code synchronizes with tg3->napi.poll()
1da177e4 4880 */
8d9d7cfc 4881 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4882 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4883
b196c7e4
MC		 4884 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4885 int i;
4886 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4887 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4888
4889 for (i = 2; i < tp->irq_cnt; i++)
4890 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4891 tp->napi[i].prodring);
4892
4893 wmb();
4894
4895 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4896 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4897 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4898 }
4899
4900 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4901 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4902 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4903 }
4904
4905 mmiowb();
4906 }
4907
6f535763
DM		 4908 return work_done;
4909}
4910
35f2d7d0
MC		 4911static int tg3_poll_msix(struct napi_struct *napi, int budget)
4912{
4913 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4914 struct tg3 *tp = tnapi->tp;
4915 int work_done = 0;
4916 struct tg3_hw_status *sblk = tnapi->hw_status;
4917
4918 while (1) {
4919 work_done = tg3_poll_work(tnapi, work_done, budget);
4920
4921 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4922 goto tx_recovery;
4923
4924 if (unlikely(work_done >= budget))
4925 break;
4926
4927 /* tp->last_tag is used in tg3_restart_ints() below
4928 * to tell the hw how much work has been processed,
4929 * so we must read it before checking for more work.
4930 */
4931 tnapi->last_tag = sblk->status_tag;
4932 tnapi->last_irq_tag = tnapi->last_tag;
4933 rmb();
4934
4935 /* check for RX/TX work to do */
4936 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4937 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4938 napi_complete(napi);
4939 /* Reenable interrupts. */
4940 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4941 mmiowb();
4942 break;
4943 }
4944 }
4945
4946 return work_done;
4947
4948tx_recovery:
4949 /* work_done is guaranteed to be less than budget. */
4950 napi_complete(napi);
4951 schedule_work(&tp->reset_task);
4952 return work_done;
4953}
4954
6f535763
DM		 4955static int tg3_poll(struct napi_struct *napi, int budget)
4956{
8ef0442f
MC		 4957 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4958 struct tg3 *tp = tnapi->tp;
6f535763 4959 int work_done = 0;
898a56f8 4960 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4961
4962 while (1) {
35f2d7d0
MC		 4963 tg3_poll_link(tp);
4964
17375d25 4965 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4966
4967 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4968 goto tx_recovery;
4969
4970 if (unlikely(work_done >= budget))
4971 break;
4972
4fd7ab59 4973 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4974 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4975 * to tell the hw how much work has been processed,
4976 * so we must read it before checking for more work.
4977 */
898a56f8
MC		 4978 tnapi->last_tag = sblk->status_tag;
4979 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4980 rmb();
4981 } else
4982 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4983
17375d25 4984 if (likely(!tg3_has_work(tnapi))) {
288379f0 4985 napi_complete(napi);
17375d25 4986 tg3_int_reenable(tnapi);
6f535763
DM		 4987 break;
4988 }
1da177e4
LT		 4989 }
4990
bea3348e 4991 return work_done;
6f535763
DM		 4992
4993tx_recovery:
4fd7ab59 4994 /* work_done is guaranteed to be less than budget. */
288379f0 4995 napi_complete(napi);
6f535763 4996 schedule_work(&tp->reset_task);
4fd7ab59 4997 return work_done;
1da177e4
LT		 4998}
4999
f47c11ee
DM		 5000static void tg3_irq_quiesce(struct tg3 *tp)
5001{
4f125f42
MC		 5002 int i;
5003
f47c11ee
DM		 5004 BUG_ON(tp->irq_sync);
5005
5006 tp->irq_sync = 1;
5007 smp_mb();
5008
4f125f42
MC		 5009 for (i = 0; i < tp->irq_cnt; i++)
5010 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5011}
5012
5013static inline int tg3_irq_sync(struct tg3 *tp)
5014{
5015 return tp->irq_sync;
5016}
5017
5018/* Fully shutdown all tg3 driver activity elsewhere in the system.
5019 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5020 * with as well. Most of the time, this is not necessary except when
5021 * shutting down the device.
5022 */
5023static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5024{
46966545 5025 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5026 if (irq_sync)
5027 tg3_irq_quiesce(tp);
f47c11ee
DM		 5028}
5029
5030static inline void tg3_full_unlock(struct tg3 *tp)
5031{
f47c11ee
DM		 5032 spin_unlock_bh(&tp->lock);
5033}
5034
fcfa0a32
MC		 5035/* One-shot MSI handler - Chip automatically disables interrupt
5036 * after sending MSI so driver doesn't have to do it.
5037 */
7d12e780 5038static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5039{
09943a18
MC		 5040 struct tg3_napi *tnapi = dev_id;
5041 struct tg3 *tp = tnapi->tp;
fcfa0a32 5042
898a56f8 5043 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5044 if (tnapi->rx_rcb)
5045 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5046
5047 if (likely(!tg3_irq_sync(tp)))
09943a18 5048 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5049
5050 return IRQ_HANDLED;
5051}
5052
88b06bc2
MC		 5053/* MSI ISR - No need to check for interrupt sharing and no need to
5054 * flush status block and interrupt mailbox. PCI ordering rules
5055 * guarantee that MSI will arrive after the status block.
5056 */
7d12e780 5057static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5058{
09943a18
MC		 5059 struct tg3_napi *tnapi = dev_id;
5060 struct tg3 *tp = tnapi->tp;
88b06bc2 5061
898a56f8 5062 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5063 if (tnapi->rx_rcb)
5064 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5065 /*
fac9b83e 5066 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5067 * chip-internal interrupt pending events.
fac9b83e 5068 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5069 * NIC to stop sending us irqs, engaging "in-intr-handler"
5070 * event coalescing.
5071 */
5072 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5073 if (likely(!tg3_irq_sync(tp)))
09943a18 5074 napi_schedule(&tnapi->napi);
61487480 5075
88b06bc2
MC		 5076 return IRQ_RETVAL(1);
5077}
5078
7d12e780 5079static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5080{
09943a18
MC		 5081 struct tg3_napi *tnapi = dev_id;
5082 struct tg3 *tp = tnapi->tp;
898a56f8 5083 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5084 unsigned int handled = 1;
5085
1da177e4
LT		 5086 /* In INTx mode, it is possible for the interrupt to arrive at
5087 * the CPU before the status block posted prior to the interrupt.
5088 * Reading the PCI State register will confirm whether the
5089 * interrupt is ours and will flush the status block.
5090 */
d18edcb2
MC		 5091 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5092 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5093 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5094 handled = 0;
f47c11ee 5095 goto out;
fac9b83e 5096 }
d18edcb2
MC		 5097 }
5098
5099 /*
5100 * Writing any value to intr-mbox-0 clears PCI INTA# and
5101 * chip-internal interrupt pending events.
5102 * Writing non-zero to intr-mbox-0 additional tells the
5103 * NIC to stop sending us irqs, engaging "in-intr-handler"
5104 * event coalescing.
c04cb347
MC		 5105 *
5106 * Flush the mailbox to de-assert the IRQ immediately to prevent
5107 * spurious interrupts. The flush impacts performance but
5108 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5109 */
c04cb347 5110 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5111 if (tg3_irq_sync(tp))
5112 goto out;
5113 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5114 if (likely(tg3_has_work(tnapi))) {
72334482 5115 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5116 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5117 } else {
5118 /* No work, shared interrupt perhaps? re-enable
5119 * interrupts, and flush that PCI write
5120 */
5121 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5122 0x00000000);
fac9b83e 5123 }
f47c11ee 5124out:
fac9b83e
DM		 5125 return IRQ_RETVAL(handled);
5126}
5127
7d12e780 5128static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5129{
09943a18
MC		 5130 struct tg3_napi *tnapi = dev_id;
5131 struct tg3 *tp = tnapi->tp;
898a56f8 5132 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5133 unsigned int handled = 1;
5134
fac9b83e
DM		 5135 /* In INTx mode, it is possible for the interrupt to arrive at
5136 * the CPU before the status block posted prior to the interrupt.
5137 * Reading the PCI State register will confirm whether the
5138 * interrupt is ours and will flush the status block.
5139 */
898a56f8 5140 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5141 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5142 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5143 handled = 0;
f47c11ee 5144 goto out;
1da177e4 5145 }
d18edcb2
MC		 5146 }
5147
5148 /*
5149 * writing any value to intr-mbox-0 clears PCI INTA# and
5150 * chip-internal interrupt pending events.
5151 * writing non-zero to intr-mbox-0 additional tells the
5152 * NIC to stop sending us irqs, engaging "in-intr-handler"
5153 * event coalescing.
c04cb347
MC		 5154 *
5155 * Flush the mailbox to de-assert the IRQ immediately to prevent
5156 * spurious interrupts. The flush impacts performance but
5157 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5158 */
c04cb347 5159 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5160
5161 /*
5162 * In a shared interrupt configuration, sometimes other devices'
5163 * interrupts will scream. We record the current status tag here
5164 * so that the above check can report that the screaming interrupts
5165 * are unhandled. Eventually they will be silenced.
5166 */
898a56f8 5167 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5168
d18edcb2
MC		 5169 if (tg3_irq_sync(tp))
5170 goto out;
624f8e50 5171
72334482 5172 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5173
09943a18 5174 napi_schedule(&tnapi->napi);
624f8e50 5175
f47c11ee 5176out:
1da177e4
LT		 5177 return IRQ_RETVAL(handled);
5178}
5179
7938109f 5180/* ISR for interrupt test */
7d12e780 5181static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5182{
09943a18
MC		 5183 struct tg3_napi *tnapi = dev_id;
5184 struct tg3 *tp = tnapi->tp;
898a56f8 5185 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5186
f9804ddb
MC		 5187 if ((sblk->status & SD_STATUS_UPDATED) ||
5188 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5189 tg3_disable_ints(tp);
7938109f
MC		 5190 return IRQ_RETVAL(1);
5191 }
5192 return IRQ_RETVAL(0);
5193}
5194
8e7a22e3 5195static int tg3_init_hw(struct tg3 *, int);
944d980e 5196static int tg3_halt(struct tg3 *, int, int);
1da177e4 5197
b9ec6c1b
MC		 5198/* Restart hardware after configuration changes, self-test, etc.
5199 * Invoked with tp->lock held.
5200 */
5201static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5202 __releases(tp->lock)
5203 __acquires(tp->lock)
b9ec6c1b
MC		 5204{
5205 int err;
5206
5207 err = tg3_init_hw(tp, reset_phy);
5208 if (err) {
5209 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5210 "aborting.\n", tp->dev->name);
5211 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5212 tg3_full_unlock(tp);
5213 del_timer_sync(&tp->timer);
5214 tp->irq_sync = 0;
fed97810 5215 tg3_napi_enable(tp);
b9ec6c1b
MC		 5216 dev_close(tp->dev);
5217 tg3_full_lock(tp, 0);
5218 }
5219 return err;
5220}
5221
1da177e4
LT		 5222#ifdef CONFIG_NET_POLL_CONTROLLER
5223static void tg3_poll_controller(struct net_device *dev)
5224{
4f125f42 5225 int i;
88b06bc2
MC		 5226 struct tg3 *tp = netdev_priv(dev);
5227
4f125f42
MC		 5228 for (i = 0; i < tp->irq_cnt; i++)
5229 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5230}
5231#endif
5232
c4028958 5233static void tg3_reset_task(struct work_struct *work)
1da177e4 5234{
c4028958 5235 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5236 int err;
1da177e4
LT		 5237 unsigned int restart_timer;
5238
7faa006f 5239 tg3_full_lock(tp, 0);
7faa006f
MC		 5240
5241 if (!netif_running(tp->dev)) {
7faa006f
MC		 5242 tg3_full_unlock(tp);
5243 return;
5244 }
5245
5246 tg3_full_unlock(tp);
5247
b02fd9e3
MC		 5248 tg3_phy_stop(tp);
5249
1da177e4
LT		 5250 tg3_netif_stop(tp);
5251
f47c11ee 5252 tg3_full_lock(tp, 1);
1da177e4
LT		 5253
5254 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5255 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5256
df3e6548
MC		 5257 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5258 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5259 tp->write32_rx_mbox = tg3_write_flush_reg32;
5260 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5261 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5262 }
5263
944d980e 5264 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5265 err = tg3_init_hw(tp, 1);
5266 if (err)
b9ec6c1b 5267 goto out;
1da177e4
LT		 5268
5269 tg3_netif_start(tp);
5270
1da177e4
LT		 5271 if (restart_timer)
5272 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5273
b9ec6c1b 5274out:
7faa006f 5275 tg3_full_unlock(tp);
b02fd9e3
MC		 5276
5277 if (!err)
5278 tg3_phy_start(tp);
1da177e4
LT		 5279}
5280
b0408751
MC		 5281static void tg3_dump_short_state(struct tg3 *tp)
5282{
5283 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5284 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5285 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5286 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5287}
5288
1da177e4
LT		 5289static void tg3_tx_timeout(struct net_device *dev)
5290{
5291 struct tg3 *tp = netdev_priv(dev);
5292
b0408751 5293 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5294 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5295 dev->name);
b0408751
MC		 5296 tg3_dump_short_state(tp);
5297 }
1da177e4
LT		 5298
5299 schedule_work(&tp->reset_task);
5300}
5301
c58ec932
MC		 5302/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5303static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5304{
5305 u32 base = (u32) mapping & 0xffffffff;
5306
5307 return ((base > 0xffffdcc0) &&
5308 (base + len + 8 < base));
5309}
5310
72f2afb8
MC		 5311/* Test for DMA addresses > 40-bit */
5312static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5313 int len)
5314{
5315#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5316 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5317 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5318 return 0;
5319#else
5320 return 0;
5321#endif
5322}
5323
f3f3f27e 5324static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5325
72f2afb8 5326/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5327static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5328 struct sk_buff *skb, u32 last_plus_one,
5329 u32 *start, u32 base_flags, u32 mss)
1da177e4 5330{
24f4efd4 5331 struct tg3 *tp = tnapi->tp;
41588ba1 5332 struct sk_buff *new_skb;
c58ec932 5333 dma_addr_t new_addr = 0;
1da177e4 5334 u32 entry = *start;
c58ec932 5335 int i, ret = 0;
1da177e4 5336
41588ba1
MC		 5337 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5338 new_skb = skb_copy(skb, GFP_ATOMIC);
5339 else {
5340 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5341
5342 new_skb = skb_copy_expand(skb,
5343 skb_headroom(skb) + more_headroom,
5344 skb_tailroom(skb), GFP_ATOMIC);
5345 }
5346
1da177e4 5347 if (!new_skb) {
c58ec932
MC		 5348 ret = -1;
5349 } else {
5350 /* New SKB is guaranteed to be linear. */
5351 entry = *start;
f4188d8a
AD		 5352 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5353 PCI_DMA_TODEVICE);
5354 /* Make sure the mapping succeeded */
5355 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5356 ret = -1;
5357 dev_kfree_skb(new_skb);
5358 new_skb = NULL;
90079ce8 5359
c58ec932
MC		 5360 /* Make sure new skb does not cross any 4G boundaries.
5361 * Drop the packet if it does.
5362 */
f4188d8a
AD		 5363 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5364 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5365 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5366 PCI_DMA_TODEVICE);
c58ec932
MC		 5367 ret = -1;
5368 dev_kfree_skb(new_skb);
5369 new_skb = NULL;
5370 } else {
f3f3f27e 5371 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5372 base_flags, 1 | (mss << 1));
5373 *start = NEXT_TX(entry);
5374 }
1da177e4
LT		 5375 }
5376
1da177e4
LT		 5377 /* Now clean up the sw ring entries. */
5378 i = 0;
5379 while (entry != last_plus_one) {
f4188d8a
AD		 5380 int len;
5381
f3f3f27e 5382 if (i == 0)
f4188d8a 5383 len = skb_headlen(skb);
f3f3f27e 5384 else
f4188d8a
AD		 5385 len = skb_shinfo(skb)->frags[i-1].size;
5386
5387 pci_unmap_single(tp->pdev,
5388 pci_unmap_addr(&tnapi->tx_buffers[entry],
5389 mapping),
5390 len, PCI_DMA_TODEVICE);
5391 if (i == 0) {
5392 tnapi->tx_buffers[entry].skb = new_skb;
5393 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5394 new_addr);
5395 } else {
f3f3f27e 5396 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5397 }
1da177e4
LT		 5398 entry = NEXT_TX(entry);
5399 i++;
5400 }
5401
5402 dev_kfree_skb(skb);
5403
c58ec932 5404 return ret;
1da177e4
LT		 5405}
5406
f3f3f27e 5407static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5408 dma_addr_t mapping, int len, u32 flags,
5409 u32 mss_and_is_end)
5410{
f3f3f27e 5411 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5412 int is_end = (mss_and_is_end & 0x1);
5413 u32 mss = (mss_and_is_end >> 1);
5414 u32 vlan_tag = 0;
5415
5416 if (is_end)
5417 flags |= TXD_FLAG_END;
5418 if (flags & TXD_FLAG_VLAN) {
5419 vlan_tag = flags >> 16;
5420 flags &= 0xffff;
5421 }
5422 vlan_tag |= (mss << TXD_MSS_SHIFT);
5423
5424 txd->addr_hi = ((u64) mapping >> 32);
5425 txd->addr_lo = ((u64) mapping & 0xffffffff);
5426 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5427 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5428}
5429
5a6f3074 5430/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5431 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5432 */
61357325
SH		 5433static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5434 struct net_device *dev)
5a6f3074
MC		 5435{
5436 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5437 u32 len, entry, base_flags, mss;
90079ce8 5438 dma_addr_t mapping;
fe5f5787
MC		 5439 struct tg3_napi *tnapi;
5440 struct netdev_queue *txq;
f4188d8a
AD		 5441 unsigned int i, last;
5442
5a6f3074 5443
fe5f5787
MC		 5444 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5445 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5446 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
fe5f5787 5447 tnapi++;
5a6f3074 5448
00b70504 5449 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5450 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5451 * interrupt. Furthermore, IRQ processing runs lockless so we have
5452 * no IRQ context deadlocks to worry about either. Rejoice!
5453 */
f3f3f27e 5454 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5455 if (!netif_tx_queue_stopped(txq)) {
5456 netif_tx_stop_queue(txq);
5a6f3074
MC		 5457
5458 /* This is a hard error, log it. */
5459 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5460 "queue awake!\n", dev->name);
5461 }
5a6f3074
MC		 5462 return NETDEV_TX_BUSY;
5463 }
5464
f3f3f27e 5465 entry = tnapi->tx_prod;
5a6f3074 5466 base_flags = 0;
5a6f3074 5467 mss = 0;
c13e3713 5468 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5469 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5470 u32 hdrlen;
5a6f3074
MC		 5471
5472 if (skb_header_cloned(skb) &&
5473 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5474 dev_kfree_skb(skb);
5475 goto out_unlock;
5476 }
5477
b0026624 5478 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5479 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5480 else {
eddc9ec5
ACM		 5481 struct iphdr *iph = ip_hdr(skb);
5482
ab6a5bb6 5483 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5484 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5485
eddc9ec5
ACM		 5486 iph->check = 0;
5487 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5488 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5489 }
5a6f3074 5490
e849cdc3 5491 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5492 mss |= (hdrlen & 0xc) << 12;
5493 if (hdrlen & 0x10)
5494 base_flags |= 0x00000010;
5495 base_flags |= (hdrlen & 0x3e0) << 5;
5496 } else
5497 mss |= hdrlen << 9;
5498
5a6f3074
MC		 5499 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5500 TXD_FLAG_CPU_POST_DMA);
5501
aa8223c7 5502 tcp_hdr(skb)->check = 0;
5a6f3074 5503
5a6f3074 5504 }
84fa7933 5505 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5506 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5507#if TG3_VLAN_TAG_USED
5508 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5509 base_flags |= (TXD_FLAG_VLAN |
5510 (vlan_tx_tag_get(skb) << 16));
5511#endif
5512
f4188d8a
AD		 5513 len = skb_headlen(skb);
5514
5515 /* Queue skb data, a.k.a. the main skb fragment. */
5516 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5517 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5518 dev_kfree_skb(skb);
5519 goto out_unlock;
5520 }
5521
f3f3f27e 5522 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5523 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5524
b703df6f 5525 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
f6eb9b1f
MC		 5526 !mss && skb->len > ETH_DATA_LEN)
5527 base_flags |= TXD_FLAG_JMB_PKT;
5528
f3f3f27e 5529 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5530 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5531
5532 entry = NEXT_TX(entry);
5533
5534 /* Now loop through additional data fragments, and queue them. */
5535 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5536 last = skb_shinfo(skb)->nr_frags - 1;
5537 for (i = 0; i <= last; i++) {
5538 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5539
5540 len = frag->size;
f4188d8a
AD		 5541 mapping = pci_map_page(tp->pdev,
5542 frag->page,
5543 frag->page_offset,
5544 len, PCI_DMA_TODEVICE);
5545 if (pci_dma_mapping_error(tp->pdev, mapping))
5546 goto dma_error;
5547
f3f3f27e 5548 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5549 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5550 mapping);
5a6f3074 5551
f3f3f27e 5552 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5553 base_flags, (i == last) | (mss << 1));
5554
5555 entry = NEXT_TX(entry);
5556 }
5557 }
5558
5559 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5560 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5561
f3f3f27e
MC		 5562 tnapi->tx_prod = entry;
5563 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5564 netif_tx_stop_queue(txq);
f3f3f27e 5565 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5566 netif_tx_wake_queue(txq);
5a6f3074
MC		 5567 }
5568
5569out_unlock:
cdd0db05 5570 mmiowb();
5a6f3074
MC		 5571
5572 return NETDEV_TX_OK;
f4188d8a
AD		 5573
5574dma_error:
5575 last = i;
5576 entry = tnapi->tx_prod;
5577 tnapi->tx_buffers[entry].skb = NULL;
5578 pci_unmap_single(tp->pdev,
5579 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5580 skb_headlen(skb),
5581 PCI_DMA_TODEVICE);
5582 for (i = 0; i <= last; i++) {
5583 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5584 entry = NEXT_TX(entry);
5585
5586 pci_unmap_page(tp->pdev,
5587 pci_unmap_addr(&tnapi->tx_buffers[entry],
5588 mapping),
5589 frag->size, PCI_DMA_TODEVICE);
5590 }
5591
5592 dev_kfree_skb(skb);
5593 return NETDEV_TX_OK;
5a6f3074
MC		 5594}
5595
61357325
SH		 5596static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5597 struct net_device *);
52c0fd83
MC		 5598
5599/* Use GSO to workaround a rare TSO bug that may be triggered when the
5600 * TSO header is greater than 80 bytes.
5601 */
5602static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5603{
5604 struct sk_buff *segs, *nskb;
f3f3f27e 5605 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5606
5607 /* Estimate the number of fragments in the worst case */
f3f3f27e 5608 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5609 netif_stop_queue(tp->dev);
f3f3f27e 5610 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5611 return NETDEV_TX_BUSY;
5612
5613 netif_wake_queue(tp->dev);
52c0fd83
MC		 5614 }
5615
5616 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5617 if (IS_ERR(segs))
52c0fd83
MC		 5618 goto tg3_tso_bug_end;
5619
5620 do {
5621 nskb = segs;
5622 segs = segs->next;
5623 nskb->next = NULL;
5624 tg3_start_xmit_dma_bug(nskb, tp->dev);
5625 } while (segs);
5626
5627tg3_tso_bug_end:
5628 dev_kfree_skb(skb);
5629
5630 return NETDEV_TX_OK;
5631}
52c0fd83 5632
5a6f3074
MC		 5633/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5634 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5635 */
61357325
SH		 5636static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5637 struct net_device *dev)
1da177e4
LT		 5638{
5639 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5640 u32 len, entry, base_flags, mss;
5641 int would_hit_hwbug;
90079ce8 5642 dma_addr_t mapping;
24f4efd4
MC		 5643 struct tg3_napi *tnapi;
5644 struct netdev_queue *txq;
f4188d8a
AD		 5645 unsigned int i, last;
5646
1da177e4 5647
24f4efd4
MC		 5648 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5649 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
19cfaecc 5650 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
24f4efd4 5651 tnapi++;
1da177e4 5652
00b70504 5653 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5654 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5655 * interrupt. Furthermore, IRQ processing runs lockless so we have
5656 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5657 */
f3f3f27e 5658 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5659 if (!netif_tx_queue_stopped(txq)) {
5660 netif_tx_stop_queue(txq);
1f064a87
SH		 5661
5662 /* This is a hard error, log it. */
5663 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5664 "queue awake!\n", dev->name);
5665 }
1da177e4
LT		 5666 return NETDEV_TX_BUSY;
5667 }
5668
f3f3f27e 5669 entry = tnapi->tx_prod;
1da177e4 5670 base_flags = 0;
84fa7933 5671 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5672 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5673
c13e3713 5674 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5675 struct iphdr *iph;
92c6b8d1 5676 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5677
5678 if (skb_header_cloned(skb) &&
5679 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5680 dev_kfree_skb(skb);
5681 goto out_unlock;
5682 }
5683
ab6a5bb6 5684 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5685 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5686
52c0fd83
MC		 5687 hdr_len = ip_tcp_len + tcp_opt_len;
5688 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5689 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5690 return (tg3_tso_bug(tp, skb));
5691
1da177e4
LT		 5692 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5693 TXD_FLAG_CPU_POST_DMA);
5694
eddc9ec5
ACM		 5695 iph = ip_hdr(skb);
5696 iph->check = 0;
5697 iph->tot_len = htons(mss + hdr_len);
1da177e4 5698 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5699 tcp_hdr(skb)->check = 0;
1da177e4 5700 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5701 } else
5702 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5703 iph->daddr, 0,
5704 IPPROTO_TCP,
5705 0);
1da177e4 5706
615774fe
MC		 5707 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5708 mss |= (hdr_len & 0xc) << 12;
5709 if (hdr_len & 0x10)
5710 base_flags |= 0x00000010;
5711 base_flags |= (hdr_len & 0x3e0) << 5;
5712 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5713 mss |= hdr_len << 9;
5714 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5716 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5717 int tsflags;
5718
eddc9ec5 5719 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5720 mss |= (tsflags << 11);
5721 }
5722 } else {
eddc9ec5 5723 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5724 int tsflags;
5725
eddc9ec5 5726 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5727 base_flags |= tsflags << 12;
5728 }
5729 }
5730 }
1da177e4
LT		 5731#if TG3_VLAN_TAG_USED
5732 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5733 base_flags |= (TXD_FLAG_VLAN |
5734 (vlan_tx_tag_get(skb) << 16));
5735#endif
5736
b703df6f 5737 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
615774fe
MC		 5738 !mss && skb->len > ETH_DATA_LEN)
5739 base_flags |= TXD_FLAG_JMB_PKT;
5740
f4188d8a
AD		 5741 len = skb_headlen(skb);
5742
5743 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5744 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5745 dev_kfree_skb(skb);
5746 goto out_unlock;
5747 }
5748
f3f3f27e 5749 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5750 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5751
5752 would_hit_hwbug = 0;
5753
92c6b8d1
MC		 5754 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5755 would_hit_hwbug = 1;
5756
0e1406dd
MC		 5757 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5758 tg3_4g_overflow_test(mapping, len))
5759 would_hit_hwbug = 1;
5760
5761 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5762 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5763 would_hit_hwbug = 1;
0e1406dd
MC		 5764
5765 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5766 would_hit_hwbug = 1;
1da177e4 5767
f3f3f27e 5768 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5769 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5770
5771 entry = NEXT_TX(entry);
5772
5773 /* Now loop through additional data fragments, and queue them. */
5774 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5775 last = skb_shinfo(skb)->nr_frags - 1;
5776 for (i = 0; i <= last; i++) {
5777 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5778
5779 len = frag->size;
f4188d8a
AD		 5780 mapping = pci_map_page(tp->pdev,
5781 frag->page,
5782 frag->page_offset,
5783 len, PCI_DMA_TODEVICE);
1da177e4 5784
f3f3f27e 5785 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5786 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5787 mapping);
5788 if (pci_dma_mapping_error(tp->pdev, mapping))
5789 goto dma_error;
1da177e4 5790
92c6b8d1
MC		 5791 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5792 len <= 8)
5793 would_hit_hwbug = 1;
5794
0e1406dd
MC		 5795 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5796 tg3_4g_overflow_test(mapping, len))
c58ec932 5797 would_hit_hwbug = 1;
1da177e4 5798
0e1406dd
MC		 5799 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5800 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5801 would_hit_hwbug = 1;
5802
1da177e4 5803 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5804 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5805 base_flags, (i == last)|(mss << 1));
5806 else
f3f3f27e 5807 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5808 base_flags, (i == last));
5809
5810 entry = NEXT_TX(entry);
5811 }
5812 }
5813
5814 if (would_hit_hwbug) {
5815 u32 last_plus_one = entry;
5816 u32 start;
1da177e4 5817
c58ec932
MC		 5818 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5819 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5820
5821 /* If the workaround fails due to memory/mapping
5822 * failure, silently drop this packet.
5823 */
24f4efd4 5824 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5825 &start, base_flags, mss))
1da177e4
LT		 5826 goto out_unlock;
5827
5828 entry = start;
5829 }
5830
5831 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5832 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5833
f3f3f27e
MC		 5834 tnapi->tx_prod = entry;
5835 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5836 netif_tx_stop_queue(txq);
f3f3f27e 5837 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5838 netif_tx_wake_queue(txq);
51b91468 5839 }
1da177e4
LT		 5840
5841out_unlock:
cdd0db05 5842 mmiowb();
1da177e4
LT		 5843
5844 return NETDEV_TX_OK;
f4188d8a
AD		 5845
5846dma_error:
5847 last = i;
5848 entry = tnapi->tx_prod;
5849 tnapi->tx_buffers[entry].skb = NULL;
5850 pci_unmap_single(tp->pdev,
5851 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5852 skb_headlen(skb),
5853 PCI_DMA_TODEVICE);
5854 for (i = 0; i <= last; i++) {
5855 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5856 entry = NEXT_TX(entry);
5857
5858 pci_unmap_page(tp->pdev,
5859 pci_unmap_addr(&tnapi->tx_buffers[entry],
5860 mapping),
5861 frag->size, PCI_DMA_TODEVICE);
5862 }
5863
5864 dev_kfree_skb(skb);
5865 return NETDEV_TX_OK;
1da177e4
LT		 5866}
5867
5868static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5869 int new_mtu)
5870{
5871 dev->mtu = new_mtu;
5872
ef7f5ec0 5873 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5874 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5875 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5876 ethtool_op_set_tso(dev, 0);
5877 }
5878 else
5879 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5880 } else {
a4e2b347 5881 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5882 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5883 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5884 }
1da177e4
LT		 5885}
5886
5887static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5888{
5889 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5890 int err;
1da177e4
LT		 5891
5892 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5893 return -EINVAL;
5894
5895 if (!netif_running(dev)) {
5896 /* We'll just catch it later when the
5897 * device is up'd.
5898 */
5899 tg3_set_mtu(dev, tp, new_mtu);
5900 return 0;
5901 }
5902
b02fd9e3
MC		 5903 tg3_phy_stop(tp);
5904
1da177e4 5905 tg3_netif_stop(tp);
f47c11ee
DM		 5906
5907 tg3_full_lock(tp, 1);
1da177e4 5908
944d980e 5909 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5910
5911 tg3_set_mtu(dev, tp, new_mtu);
5912
b9ec6c1b 5913 err = tg3_restart_hw(tp, 0);
1da177e4 5914
b9ec6c1b
MC		 5915 if (!err)
5916 tg3_netif_start(tp);
1da177e4 5917
f47c11ee 5918 tg3_full_unlock(tp);
1da177e4 5919
b02fd9e3
MC		 5920 if (!err)
5921 tg3_phy_start(tp);
5922
b9ec6c1b 5923 return err;
1da177e4
LT		 5924}
5925
21f581a5
MC		 5926static void tg3_rx_prodring_free(struct tg3 *tp,
5927 struct tg3_rx_prodring_set *tpr)
1da177e4 5928{
1da177e4
LT		 5929 int i;
5930
b196c7e4
MC		 5931 if (tpr != &tp->prodring[0]) {
5932 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5933 i = (i + 1) % TG3_RX_RING_SIZE)
5934 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5935 tp->rx_pkt_map_sz);
5936
5937 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5938 for (i = tpr->rx_jmb_cons_idx;
5939 i != tpr->rx_jmb_prod_idx;
5940 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5941 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5942 TG3_RX_JMB_MAP_SZ);
5943 }
5944 }
5945
2b2cdb65 5946 return;
b196c7e4 5947 }
1da177e4 5948
2b2cdb65
MC		 5949 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5950 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5951 tp->rx_pkt_map_sz);
1da177e4 5952
cf7a7298 5953 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 5954 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5955 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5956 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 5957 }
5958}
5959
5960/* Initialize tx/rx rings for packet processing.
5961 *
5962 * The chip has been shut down and the driver detached from
5963 * the networking, so no interrupts or new tx packets will
5964 * end up in the driver. tp->{tx,}lock are held and thus
5965 * we may not sleep.
5966 */
21f581a5
MC		 5967static int tg3_rx_prodring_alloc(struct tg3 *tp,
5968 struct tg3_rx_prodring_set *tpr)
1da177e4 5969{
287be12e 5970 u32 i, rx_pkt_dma_sz;
1da177e4 5971
b196c7e4
MC		 5972 tpr->rx_std_cons_idx = 0;
5973 tpr->rx_std_prod_idx = 0;
5974 tpr->rx_jmb_cons_idx = 0;
5975 tpr->rx_jmb_prod_idx = 0;
5976
2b2cdb65
MC		 5977 if (tpr != &tp->prodring[0]) {
5978 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5979 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5980 memset(&tpr->rx_jmb_buffers[0], 0,
5981 TG3_RX_JMB_BUFF_RING_SIZE);
5982 goto done;
5983 }
5984
1da177e4 5985 /* Zero out all descriptors. */
21f581a5 5986 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5987
287be12e 5988 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5989 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5990 tp->dev->mtu > ETH_DATA_LEN)
5991 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5992 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5993
1da177e4
LT		 5994 /* Initialize invariants of the rings, we only set this
5995 * stuff once. This works because the card does not
5996 * write into the rx buffer posting rings.
5997 */
5998 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5999 struct tg3_rx_buffer_desc *rxd;
6000
21f581a5 6001 rxd = &tpr->rx_std[i];
287be12e 6002 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 6003 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6004 rxd->opaque = (RXD_OPAQUE_RING_STD |
6005 (i << RXD_OPAQUE_INDEX_SHIFT));
6006 }
6007
1da177e4
LT		 6008 /* Now allocate fresh SKBs for each rx ring. */
6009 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6010 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 6011 printk(KERN_WARNING PFX
6012 "%s: Using a smaller RX standard ring, "
6013 "only %d out of %d buffers were allocated "
6014 "successfully.\n",
6015 tp->dev->name, i, tp->rx_pending);
6016 if (i == 0)
cf7a7298 6017 goto initfail;
32d8c572 6018 tp->rx_pending = i;
1da177e4 6019 break;
32d8c572 6020 }
1da177e4
LT		 6021 }
6022
cf7a7298
MC		 6023 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6024 goto done;
6025
21f581a5 6026 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6027
0f893dc6 6028 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 6029 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6030 struct tg3_rx_buffer_desc *rxd;
6031
79ed5ac7 6032 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 6033 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6034 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6035 RXD_FLAG_JUMBO;
6036 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6037 (i << RXD_OPAQUE_INDEX_SHIFT));
6038 }
6039
1da177e4 6040 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 6041 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 6042 i) < 0) {
32d8c572
MC		 6043 printk(KERN_WARNING PFX
6044 "%s: Using a smaller RX jumbo ring, "
6045 "only %d out of %d buffers were "
6046 "allocated successfully.\n",
6047 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 6048 if (i == 0)
6049 goto initfail;
32d8c572 6050 tp->rx_jumbo_pending = i;
1da177e4 6051 break;
32d8c572 6052 }
1da177e4
LT		 6053 }
6054 }
cf7a7298
MC		 6055
6056done:
32d8c572 6057 return 0;
cf7a7298
MC		 6058
6059initfail:
21f581a5 6060 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6061 return -ENOMEM;
1da177e4
LT		 6062}
6063
21f581a5
MC		 6064static void tg3_rx_prodring_fini(struct tg3 *tp,
6065 struct tg3_rx_prodring_set *tpr)
1da177e4 6066{
21f581a5
MC		 6067 kfree(tpr->rx_std_buffers);
6068 tpr->rx_std_buffers = NULL;
6069 kfree(tpr->rx_jmb_buffers);
6070 tpr->rx_jmb_buffers = NULL;
6071 if (tpr->rx_std) {
1da177e4 6072 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6073 tpr->rx_std, tpr->rx_std_mapping);
6074 tpr->rx_std = NULL;
1da177e4 6075 }
21f581a5 6076 if (tpr->rx_jmb) {
1da177e4 6077 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6078 tpr->rx_jmb, tpr->rx_jmb_mapping);
6079 tpr->rx_jmb = NULL;
1da177e4 6080 }
cf7a7298
MC		 6081}
6082
21f581a5
MC		 6083static int tg3_rx_prodring_init(struct tg3 *tp,
6084 struct tg3_rx_prodring_set *tpr)
cf7a7298 6085{
2b2cdb65 6086 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6087 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6088 return -ENOMEM;
6089
21f581a5
MC		 6090 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6091 &tpr->rx_std_mapping);
6092 if (!tpr->rx_std)
cf7a7298
MC		 6093 goto err_out;
6094
6095 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6096 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6097 GFP_KERNEL);
6098 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6099 goto err_out;
6100
21f581a5
MC		 6101 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6102 TG3_RX_JUMBO_RING_BYTES,
6103 &tpr->rx_jmb_mapping);
6104 if (!tpr->rx_jmb)
cf7a7298
MC		 6105 goto err_out;
6106 }
6107
6108 return 0;
6109
6110err_out:
21f581a5 6111 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6112 return -ENOMEM;
6113}
6114
6115/* Free up pending packets in all rx/tx rings.
6116 *
6117 * The chip has been shut down and the driver detached from
6118 * the networking, so no interrupts or new tx packets will
6119 * end up in the driver. tp->{tx,}lock is not held and we are not
6120 * in an interrupt context and thus may sleep.
6121 */
6122static void tg3_free_rings(struct tg3 *tp)
6123{
f77a6a8e 6124 int i, j;
cf7a7298 6125
f77a6a8e
MC		 6126 for (j = 0; j < tp->irq_cnt; j++) {
6127 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6128
0c1d0e2b
MC		 6129 if (!tnapi->tx_buffers)
6130 continue;
6131
f77a6a8e 6132 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6133 struct ring_info *txp;
f77a6a8e 6134 struct sk_buff *skb;
f4188d8a 6135 unsigned int k;
cf7a7298 6136
f77a6a8e
MC		 6137 txp = &tnapi->tx_buffers[i];
6138 skb = txp->skb;
cf7a7298 6139
f77a6a8e
MC		 6140 if (skb == NULL) {
6141 i++;
6142 continue;
6143 }
cf7a7298 6144
f4188d8a
AD		 6145 pci_unmap_single(tp->pdev,
6146 pci_unmap_addr(txp, mapping),
6147 skb_headlen(skb),
6148 PCI_DMA_TODEVICE);
f77a6a8e 6149 txp->skb = NULL;
cf7a7298 6150
f4188d8a
AD		 6151 i++;
6152
6153 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6154 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6155 pci_unmap_page(tp->pdev,
6156 pci_unmap_addr(txp, mapping),
6157 skb_shinfo(skb)->frags[k].size,
6158 PCI_DMA_TODEVICE);
6159 i++;
6160 }
f77a6a8e
MC		 6161
6162 dev_kfree_skb_any(skb);
6163 }
cf7a7298 6164
2b2cdb65
MC		 6165 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6166 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6167 }
cf7a7298
MC		 6168}
6169
6170/* Initialize tx/rx rings for packet processing.
6171 *
6172 * The chip has been shut down and the driver detached from
6173 * the networking, so no interrupts or new tx packets will
6174 * end up in the driver. tp->{tx,}lock are held and thus
6175 * we may not sleep.
6176 */
6177static int tg3_init_rings(struct tg3 *tp)
6178{
f77a6a8e 6179 int i;
72334482 6180
cf7a7298
MC		 6181 /* Free up all the SKBs. */
6182 tg3_free_rings(tp);
6183
f77a6a8e
MC		 6184 for (i = 0; i < tp->irq_cnt; i++) {
6185 struct tg3_napi *tnapi = &tp->napi[i];
6186
6187 tnapi->last_tag = 0;
6188 tnapi->last_irq_tag = 0;
6189 tnapi->hw_status->status = 0;
6190 tnapi->hw_status->status_tag = 0;
6191 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6192
f77a6a8e
MC		 6193 tnapi->tx_prod = 0;
6194 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6195 if (tnapi->tx_ring)
6196 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6197
6198 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6199 if (tnapi->rx_rcb)
6200 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65
MC		 6201
6202 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6203 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6204 return -ENOMEM;
f77a6a8e 6205 }
72334482 6206
2b2cdb65 6207 return 0;
cf7a7298
MC		 6208}
6209
6210/*
6211 * Must not be invoked with interrupt sources disabled and
6212 * the hardware shutdown down.
6213 */
6214static void tg3_free_consistent(struct tg3 *tp)
6215{
f77a6a8e 6216 int i;
898a56f8 6217
f77a6a8e
MC		 6218 for (i = 0; i < tp->irq_cnt; i++) {
6219 struct tg3_napi *tnapi = &tp->napi[i];
6220
6221 if (tnapi->tx_ring) {
6222 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6223 tnapi->tx_ring, tnapi->tx_desc_mapping);
6224 tnapi->tx_ring = NULL;
6225 }
6226
6227 kfree(tnapi->tx_buffers);
6228 tnapi->tx_buffers = NULL;
6229
6230 if (tnapi->rx_rcb) {
6231 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6232 tnapi->rx_rcb,
6233 tnapi->rx_rcb_mapping);
6234 tnapi->rx_rcb = NULL;
6235 }
6236
6237 if (tnapi->hw_status) {
6238 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6239 tnapi->hw_status,
6240 tnapi->status_mapping);
6241 tnapi->hw_status = NULL;
6242 }
1da177e4 6243 }
f77a6a8e 6244
1da177e4
LT		 6245 if (tp->hw_stats) {
6246 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6247 tp->hw_stats, tp->stats_mapping);
6248 tp->hw_stats = NULL;
6249 }
f77a6a8e 6250
2b2cdb65
MC		 6251 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6252 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6253}
6254
6255/*
6256 * Must not be invoked with interrupt sources disabled and
6257 * the hardware shutdown down. Can sleep.
6258 */
6259static int tg3_alloc_consistent(struct tg3 *tp)
6260{
f77a6a8e 6261 int i;
898a56f8 6262
2b2cdb65
MC		 6263 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6264 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6265 goto err_out;
6266 }
1da177e4 6267
f77a6a8e
MC		 6268 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6269 sizeof(struct tg3_hw_stats),
6270 &tp->stats_mapping);
6271 if (!tp->hw_stats)
1da177e4
LT		 6272 goto err_out;
6273
f77a6a8e 6274 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6275
f77a6a8e
MC		 6276 for (i = 0; i < tp->irq_cnt; i++) {
6277 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6278 struct tg3_hw_status *sblk;
1da177e4 6279
f77a6a8e
MC		 6280 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6281 TG3_HW_STATUS_SIZE,
6282 &tnapi->status_mapping);
6283 if (!tnapi->hw_status)
6284 goto err_out;
898a56f8 6285
f77a6a8e 6286 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6287 sblk = tnapi->hw_status;
6288
19cfaecc
MC		 6289 /* If multivector TSS is enabled, vector 0 does not handle
6290 * tx interrupts. Don't allocate any resources for it.
6291 */
6292 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6293 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6294 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6295 TG3_TX_RING_SIZE,
6296 GFP_KERNEL);
6297 if (!tnapi->tx_buffers)
6298 goto err_out;
6299
6300 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6301 TG3_TX_RING_BYTES,
6302 &tnapi->tx_desc_mapping);
6303 if (!tnapi->tx_ring)
6304 goto err_out;
6305 }
6306
8d9d7cfc
MC		 6307 /*
6308 * When RSS is enabled, the status block format changes
6309 * slightly. The "rx_jumbo_consumer", "reserved",
6310 * and "rx_mini_consumer" members get mapped to the
6311 * other three rx return ring producer indexes.
6312 */
6313 switch (i) {
6314 default:
6315 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6316 break;
6317 case 2:
6318 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6319 break;
6320 case 3:
6321 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6322 break;
6323 case 4:
6324 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6325 break;
6326 }
72334482 6327
b196c7e4
MC		 6328 if (tp->irq_cnt == 1)
6329 tnapi->prodring = &tp->prodring[0];
6330 else if (i)
6331 tnapi->prodring = &tp->prodring[i - 1];
6332
0c1d0e2b
MC		 6333 /*
6334 * If multivector RSS is enabled, vector 0 does not handle
6335 * rx or tx interrupts. Don't allocate any resources for it.
6336 */
6337 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6338 continue;
6339
f77a6a8e
MC		 6340 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6341 TG3_RX_RCB_RING_BYTES(tp),
6342 &tnapi->rx_rcb_mapping);
6343 if (!tnapi->rx_rcb)
6344 goto err_out;
72334482 6345
f77a6a8e 6346 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 6347 }
1da177e4
LT		 6348
6349 return 0;
6350
6351err_out:
6352 tg3_free_consistent(tp);
6353 return -ENOMEM;
6354}
6355
6356#define MAX_WAIT_CNT 1000
6357
6358/* To stop a block, clear the enable bit and poll till it
6359 * clears. tp->lock is held.
6360 */
b3b7d6be 6361static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6362{
6363 unsigned int i;
6364 u32 val;
6365
6366 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6367 switch (ofs) {
6368 case RCVLSC_MODE:
6369 case DMAC_MODE:
6370 case MBFREE_MODE:
6371 case BUFMGR_MODE:
6372 case MEMARB_MODE:
6373 /* We can't enable/disable these bits of the
6374 * 5705/5750, just say success.
6375 */
6376 return 0;
6377
6378 default:
6379 break;
855e1111 6380 }
1da177e4
LT		 6381 }
6382
6383 val = tr32(ofs);
6384 val &= ~enable_bit;
6385 tw32_f(ofs, val);
6386
6387 for (i = 0; i < MAX_WAIT_CNT; i++) {
6388 udelay(100);
6389 val = tr32(ofs);
6390 if ((val & enable_bit) == 0)
6391 break;
6392 }
6393
b3b7d6be 6394 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6395 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6396 "ofs=%lx enable_bit=%x\n",
6397 ofs, enable_bit);
6398 return -ENODEV;
6399 }
6400
6401 return 0;
6402}
6403
6404/* tp->lock is held. */
b3b7d6be 6405static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6406{
6407 int i, err;
6408
6409 tg3_disable_ints(tp);
6410
6411 tp->rx_mode &= ~RX_MODE_ENABLE;
6412 tw32_f(MAC_RX_MODE, tp->rx_mode);
6413 udelay(10);
6414
b3b7d6be
DM		 6415 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6416 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6417 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6418 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6419 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6420 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6421
6422 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6423 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6424 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6425 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6426 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6427 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6428 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6429
6430 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6431 tw32_f(MAC_MODE, tp->mac_mode);
6432 udelay(40);
6433
6434 tp->tx_mode &= ~TX_MODE_ENABLE;
6435 tw32_f(MAC_TX_MODE, tp->tx_mode);
6436
6437 for (i = 0; i < MAX_WAIT_CNT; i++) {
6438 udelay(100);
6439 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6440 break;
6441 }
6442 if (i >= MAX_WAIT_CNT) {
6443 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6444 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6445 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6446 err |= -ENODEV;
1da177e4
LT		 6447 }
6448
e6de8ad1 6449 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6450 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6451 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6452
6453 tw32(FTQ_RESET, 0xffffffff);
6454 tw32(FTQ_RESET, 0x00000000);
6455
b3b7d6be
DM		 6456 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6457 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6458
f77a6a8e
MC		 6459 for (i = 0; i < tp->irq_cnt; i++) {
6460 struct tg3_napi *tnapi = &tp->napi[i];
6461 if (tnapi->hw_status)
6462 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6463 }
1da177e4
LT		 6464 if (tp->hw_stats)
6465 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6466
1da177e4
LT		 6467 return err;
6468}
6469
0d3031d9
MC		 6470static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6471{
6472 int i;
6473 u32 apedata;
6474
6475 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6476 if (apedata != APE_SEG_SIG_MAGIC)
6477 return;
6478
6479 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6480 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6481 return;
6482
6483 /* Wait for up to 1 millisecond for APE to service previous event. */
6484 for (i = 0; i < 10; i++) {
6485 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6486 return;
6487
6488 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6489
6490 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6491 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6492 event | APE_EVENT_STATUS_EVENT_PENDING);
6493
6494 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6495
6496 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6497 break;
6498
6499 udelay(100);
6500 }
6501
6502 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6503 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6504}
6505
6506static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6507{
6508 u32 event;
6509 u32 apedata;
6510
6511 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6512 return;
6513
6514 switch (kind) {
6515 case RESET_KIND_INIT:
6516 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6517 APE_HOST_SEG_SIG_MAGIC);
6518 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6519 APE_HOST_SEG_LEN_MAGIC);
6520 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6521 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6522 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6523 APE_HOST_DRIVER_ID_MAGIC);
6524 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6525 APE_HOST_BEHAV_NO_PHYLOCK);
6526
6527 event = APE_EVENT_STATUS_STATE_START;
6528 break;
6529 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6530 /* With the interface we are currently using,
6531 * APE does not track driver state. Wiping
6532 * out the HOST SEGMENT SIGNATURE forces
6533 * the APE to assume OS absent status.
6534 */
6535 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6536
0d3031d9
MC		 6537 event = APE_EVENT_STATUS_STATE_UNLOAD;
6538 break;
6539 case RESET_KIND_SUSPEND:
6540 event = APE_EVENT_STATUS_STATE_SUSPEND;
6541 break;
6542 default:
6543 return;
6544 }
6545
6546 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6547
6548 tg3_ape_send_event(tp, event);
6549}
6550
1da177e4
LT		 6551/* tp->lock is held. */
6552static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6553{
f49639e6
DM		 6554 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6555 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6556
6557 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6558 switch (kind) {
6559 case RESET_KIND_INIT:
6560 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6561 DRV_STATE_START);
6562 break;
6563
6564 case RESET_KIND_SHUTDOWN:
6565 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6566 DRV_STATE_UNLOAD);
6567 break;
6568
6569 case RESET_KIND_SUSPEND:
6570 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6571 DRV_STATE_SUSPEND);
6572 break;
6573
6574 default:
6575 break;
855e1111 6576 }
1da177e4 6577 }
0d3031d9
MC		 6578
6579 if (kind == RESET_KIND_INIT ||
6580 kind == RESET_KIND_SUSPEND)
6581 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6582}
6583
6584/* tp->lock is held. */
6585static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6586{
6587 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6588 switch (kind) {
6589 case RESET_KIND_INIT:
6590 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6591 DRV_STATE_START_DONE);
6592 break;
6593
6594 case RESET_KIND_SHUTDOWN:
6595 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6596 DRV_STATE_UNLOAD_DONE);
6597 break;
6598
6599 default:
6600 break;
855e1111 6601 }
1da177e4 6602 }
0d3031d9
MC		 6603
6604 if (kind == RESET_KIND_SHUTDOWN)
6605 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6606}
6607
6608/* tp->lock is held. */
6609static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6610{
6611 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6612 switch (kind) {
6613 case RESET_KIND_INIT:
6614 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6615 DRV_STATE_START);
6616 break;
6617
6618 case RESET_KIND_SHUTDOWN:
6619 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6620 DRV_STATE_UNLOAD);
6621 break;
6622
6623 case RESET_KIND_SUSPEND:
6624 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6625 DRV_STATE_SUSPEND);
6626 break;
6627
6628 default:
6629 break;
855e1111 6630 }
1da177e4
LT		 6631 }
6632}
6633
7a6f4369
MC		 6634static int tg3_poll_fw(struct tg3 *tp)
6635{
6636 int i;
6637 u32 val;
6638
b5d3772c 6639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6640 /* Wait up to 20ms for init done. */
6641 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6642 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6643 return 0;
0ccead18 6644 udelay(100);
b5d3772c
MC		 6645 }
6646 return -ENODEV;
6647 }
6648
7a6f4369
MC		 6649 /* Wait for firmware initialization to complete. */
6650 for (i = 0; i < 100000; i++) {
6651 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6652 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6653 break;
6654 udelay(10);
6655 }
6656
6657 /* Chip might not be fitted with firmware. Some Sun onboard
6658 * parts are configured like that. So don't signal the timeout
6659 * of the above loop as an error, but do report the lack of
6660 * running firmware once.
6661 */
6662 if (i >= 100000 &&
6663 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6664 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6665
6666 printk(KERN_INFO PFX "%s: No firmware running.\n",
6667 tp->dev->name);
6668 }
6669
6670 return 0;
6671}
6672
ee6a99b5
MC		 6673/* Save PCI command register before chip reset */
6674static void tg3_save_pci_state(struct tg3 *tp)
6675{
8a6eac90 6676 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6677}
6678
6679/* Restore PCI state after chip reset */
6680static void tg3_restore_pci_state(struct tg3 *tp)
6681{
6682 u32 val;
6683
6684 /* Re-enable indirect register accesses. */
6685 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6686 tp->misc_host_ctrl);
6687
6688 /* Set MAX PCI retry to zero. */
6689 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6690 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6691 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6692 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6693 /* Allow reads and writes to the APE register and memory space. */
6694 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6695 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6696 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6697 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6698
8a6eac90 6699 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6700
fcb389df
MC		 6701 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6702 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6703 pcie_set_readrq(tp->pdev, 4096);
6704 else {
6705 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6706 tp->pci_cacheline_sz);
6707 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6708 tp->pci_lat_timer);
6709 }
114342f2 6710 }
5f5c51e3 6711
ee6a99b5 6712 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6713 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6714 u16 pcix_cmd;
6715
6716 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6717 &pcix_cmd);
6718 pcix_cmd &= ~PCI_X_CMD_ERO;
6719 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6720 pcix_cmd);
6721 }
ee6a99b5
MC		 6722
6723 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6724
6725 /* Chip reset on 5780 will reset MSI enable bit,
6726 * so need to restore it.
6727 */
6728 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6729 u16 ctrl;
6730
6731 pci_read_config_word(tp->pdev,
6732 tp->msi_cap + PCI_MSI_FLAGS,
6733 &ctrl);
6734 pci_write_config_word(tp->pdev,
6735 tp->msi_cap + PCI_MSI_FLAGS,
6736 ctrl | PCI_MSI_FLAGS_ENABLE);
6737 val = tr32(MSGINT_MODE);
6738 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6739 }
6740 }
6741}
6742
1da177e4
LT		 6743static void tg3_stop_fw(struct tg3 *);
6744
6745/* tp->lock is held. */
6746static int tg3_chip_reset(struct tg3 *tp)
6747{
6748 u32 val;
1ee582d8 6749 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6750 int i, err;
1da177e4 6751
f49639e6
DM		 6752 tg3_nvram_lock(tp);
6753
77b483f1
MC		 6754 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6755
f49639e6
DM		 6756 /* No matching tg3_nvram_unlock() after this because
6757 * chip reset below will undo the nvram lock.
6758 */
6759 tp->nvram_lock_cnt = 0;
1da177e4 6760
ee6a99b5
MC		 6761 /* GRC_MISC_CFG core clock reset will clear the memory
6762 * enable bit in PCI register 4 and the MSI enable bit
6763 * on some chips, so we save relevant registers here.
6764 */
6765 tg3_save_pci_state(tp);
6766
d9ab5ad1 6767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6768 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6769 tw32(GRC_FASTBOOT_PC, 0);
6770
1da177e4
LT		 6771 /*
6772 * We must avoid the readl() that normally takes place.
6773 * It locks machines, causes machine checks, and other
6774 * fun things. So, temporarily disable the 5701
6775 * hardware workaround, while we do the reset.
6776 */
1ee582d8
MC		 6777 write_op = tp->write32;
6778 if (write_op == tg3_write_flush_reg32)
6779 tp->write32 = tg3_write32;
1da177e4 6780
d18edcb2
MC		 6781 /* Prevent the irq handler from reading or writing PCI registers
6782 * during chip reset when the memory enable bit in the PCI command
6783 * register may be cleared. The chip does not generate interrupt
6784 * at this time, but the irq handler may still be called due to irq
6785 * sharing or irqpoll.
6786 */
6787 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6788 for (i = 0; i < tp->irq_cnt; i++) {
6789 struct tg3_napi *tnapi = &tp->napi[i];
6790 if (tnapi->hw_status) {
6791 tnapi->hw_status->status = 0;
6792 tnapi->hw_status->status_tag = 0;
6793 }
6794 tnapi->last_tag = 0;
6795 tnapi->last_irq_tag = 0;
b8fa2f3a 6796 }
d18edcb2 6797 smp_mb();
4f125f42
MC		 6798
6799 for (i = 0; i < tp->irq_cnt; i++)
6800 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6801
255ca311
MC		 6802 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6803 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6804 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6805 }
6806
1da177e4
LT		 6807 /* do the reset */
6808 val = GRC_MISC_CFG_CORECLK_RESET;
6809
6810 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6811 if (tr32(0x7e2c) == 0x60) {
6812 tw32(0x7e2c, 0x20);
6813 }
6814 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6815 tw32(GRC_MISC_CFG, (1 << 29));
6816 val |= (1 << 29);
6817 }
6818 }
6819
b5d3772c
MC		 6820 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6821 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6822 tw32(GRC_VCPU_EXT_CTRL,
6823 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6824 }
6825
1da177e4
LT		 6826 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6827 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6828 tw32(GRC_MISC_CFG, val);
6829
1ee582d8
MC		 6830 /* restore 5701 hardware bug workaround write method */
6831 tp->write32 = write_op;
1da177e4
LT		 6832
6833 /* Unfortunately, we have to delay before the PCI read back.
6834 * Some 575X chips even will not respond to a PCI cfg access
6835 * when the reset command is given to the chip.
6836 *
6837 * How do these hardware designers expect things to work
6838 * properly if the PCI write is posted for a long period
6839 * of time? It is always necessary to have some method by
6840 * which a register read back can occur to push the write
6841 * out which does the reset.
6842 *
6843 * For most tg3 variants the trick below was working.
6844 * Ho hum...
6845 */
6846 udelay(120);
6847
6848 /* Flush PCI posted writes. The normal MMIO registers
6849 * are inaccessible at this time so this is the only
6850 * way to make this reliably (actually, this is no longer
6851 * the case, see above). I tried to use indirect
6852 * register read/write but this upset some 5701 variants.
6853 */
6854 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6855
6856 udelay(120);
6857
5e7dfd0f 6858 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6859 u16 val16;
6860
1da177e4
LT		 6861 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6862 int i;
6863 u32 cfg_val;
6864
6865 /* Wait for link training to complete. */
6866 for (i = 0; i < 5000; i++)
6867 udelay(100);
6868
6869 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6870 pci_write_config_dword(tp->pdev, 0xc4,
6871 cfg_val | (1 << 15));
6872 }
5e7dfd0f 6873
e7126997
MC		 6874 /* Clear the "no snoop" and "relaxed ordering" bits. */
6875 pci_read_config_word(tp->pdev,
6876 tp->pcie_cap + PCI_EXP_DEVCTL,
6877 &val16);
6878 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6879 PCI_EXP_DEVCTL_NOSNOOP_EN);
6880 /*
6881 * Older PCIe devices only support the 128 byte
6882 * MPS setting. Enforce the restriction.
5e7dfd0f 6883 */
e7126997
MC		 6884 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6885 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6886 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6887 pci_write_config_word(tp->pdev,
6888 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6889 val16);
5e7dfd0f
MC		 6890
6891 pcie_set_readrq(tp->pdev, 4096);
6892
6893 /* Clear error status */
6894 pci_write_config_word(tp->pdev,
6895 tp->pcie_cap + PCI_EXP_DEVSTA,
6896 PCI_EXP_DEVSTA_CED |
6897 PCI_EXP_DEVSTA_NFED |
6898 PCI_EXP_DEVSTA_FED |
6899 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6900 }
6901
ee6a99b5 6902 tg3_restore_pci_state(tp);
1da177e4 6903
d18edcb2
MC		 6904 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6905
ee6a99b5
MC		 6906 val = 0;
6907 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6908 val = tr32(MEMARB_MODE);
ee6a99b5 6909 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6910
6911 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6912 tg3_stop_fw(tp);
6913 tw32(0x5000, 0x400);
6914 }
6915
6916 tw32(GRC_MODE, tp->grc_mode);
6917
6918 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6919 val = tr32(0xc4);
1da177e4
LT		 6920
6921 tw32(0xc4, val | (1 << 15));
6922 }
6923
6924 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6926 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6927 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6928 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6929 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6930 }
6931
6932 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6933 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6934 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6935 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6936 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6937 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6938 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6939 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6940 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6941 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6942 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6943 } else
6944 tw32_f(MAC_MODE, 0);
6945 udelay(40);
6946
77b483f1
MC		 6947 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6948
7a6f4369
MC		 6949 err = tg3_poll_fw(tp);
6950 if (err)
6951 return err;
1da177e4 6952
0a9140cf
MC		 6953 tg3_mdio_start(tp);
6954
52cdf852
MC		 6955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6956 u8 phy_addr;
6957
6958 phy_addr = tp->phy_addr;
6959 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6960
6961 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6962 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6963 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6964 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6965 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6966 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6967 udelay(10);
6968
6969 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6970 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6971 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6972 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6973 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6974 udelay(10);
6975
6976 tp->phy_addr = phy_addr;
6977 }
6978
1da177e4 6979 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6980 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6981 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
b703df6f
MC		 6982 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6983 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
ab0049b4 6984 val = tr32(0x7c00);
1da177e4
LT		 6985
6986 tw32(0x7c00, val | (1 << 25));
6987 }
6988
6989 /* Reprobe ASF enable state. */
6990 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6991 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6992 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6993 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6994 u32 nic_cfg;
6995
6996 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6997 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6998 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6999 tp->last_event_jiffies = jiffies;
cbf46853 7000 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 7001 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7002 }
7003 }
7004
7005 return 0;
7006}
7007
7008/* tp->lock is held. */
7009static void tg3_stop_fw(struct tg3 *tp)
7010{
0d3031d9
MC		 7011 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7012 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 7013 /* Wait for RX cpu to ACK the previous event. */
7014 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7015
7016 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7017
7018 tg3_generate_fw_event(tp);
1da177e4 7019
7c5026aa
MC		 7020 /* Wait for RX cpu to ACK this event. */
7021 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7022 }
7023}
7024
7025/* tp->lock is held. */
944d980e 7026static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7027{
7028 int err;
7029
7030 tg3_stop_fw(tp);
7031
944d980e 7032 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7033
b3b7d6be 7034 tg3_abort_hw(tp, silent);
1da177e4
LT		 7035 err = tg3_chip_reset(tp);
7036
daba2a63
MC		 7037 __tg3_set_mac_addr(tp, 0);
7038
944d980e
MC		 7039 tg3_write_sig_legacy(tp, kind);
7040 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7041
7042 if (err)
7043 return err;
7044
7045 return 0;
7046}
7047
1da177e4
LT		 7048#define RX_CPU_SCRATCH_BASE 0x30000
7049#define RX_CPU_SCRATCH_SIZE 0x04000
7050#define TX_CPU_SCRATCH_BASE 0x34000
7051#define TX_CPU_SCRATCH_SIZE 0x04000
7052
7053/* tp->lock is held. */
7054static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7055{
7056 int i;
7057
5d9428de
ES		 7058 BUG_ON(offset == TX_CPU_BASE &&
7059 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7060
b5d3772c
MC		 7061 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7062 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7063
7064 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7065 return 0;
7066 }
1da177e4
LT		 7067 if (offset == RX_CPU_BASE) {
7068 for (i = 0; i < 10000; i++) {
7069 tw32(offset + CPU_STATE, 0xffffffff);
7070 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7071 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7072 break;
7073 }
7074
7075 tw32(offset + CPU_STATE, 0xffffffff);
7076 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7077 udelay(10);
7078 } else {
7079 for (i = 0; i < 10000; i++) {
7080 tw32(offset + CPU_STATE, 0xffffffff);
7081 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7082 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7083 break;
7084 }
7085 }
7086
7087 if (i >= 10000) {
7088 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7089 "and %s CPU\n",
7090 tp->dev->name,
7091 (offset == RX_CPU_BASE ? "RX" : "TX"));
7092 return -ENODEV;
7093 }
ec41c7df
MC		 7094
7095 /* Clear firmware's nvram arbitration. */
7096 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7097 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7098 return 0;
7099}
7100
7101struct fw_info {
077f849d
JSR		 7102 unsigned int fw_base;
7103 unsigned int fw_len;
7104 const __be32 *fw_data;
1da177e4
LT		 7105};
7106
7107/* tp->lock is held. */
7108static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7109 int cpu_scratch_size, struct fw_info *info)
7110{
ec41c7df 7111 int err, lock_err, i;
1da177e4
LT		 7112 void (*write_op)(struct tg3 *, u32, u32);
7113
7114 if (cpu_base == TX_CPU_BASE &&
7115 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7116 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7117 "TX cpu firmware on %s which is 5705.\n",
7118 tp->dev->name);
7119 return -EINVAL;
7120 }
7121
7122 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7123 write_op = tg3_write_mem;
7124 else
7125 write_op = tg3_write_indirect_reg32;
7126
1b628151
MC		 7127 /* It is possible that bootcode is still loading at this point.
7128 * Get the nvram lock first before halting the cpu.
7129 */
ec41c7df 7130 lock_err = tg3_nvram_lock(tp);
1da177e4 7131 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7132 if (!lock_err)
7133 tg3_nvram_unlock(tp);
1da177e4
LT		 7134 if (err)
7135 goto out;
7136
7137 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7138 write_op(tp, cpu_scratch_base + i, 0);
7139 tw32(cpu_base + CPU_STATE, 0xffffffff);
7140 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7141 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7142 write_op(tp, (cpu_scratch_base +
077f849d 7143 (info->fw_base & 0xffff) +
1da177e4 7144 (i * sizeof(u32))),
077f849d 7145 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7146
7147 err = 0;
7148
7149out:
1da177e4
LT		 7150 return err;
7151}
7152
7153/* tp->lock is held. */
7154static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7155{
7156 struct fw_info info;
077f849d 7157 const __be32 *fw_data;
1da177e4
LT		 7158 int err, i;
7159
077f849d
JSR		 7160 fw_data = (void *)tp->fw->data;
7161
7162 /* Firmware blob starts with version numbers, followed by
7163 start address and length. We are setting complete length.
7164 length = end_address_of_bss - start_address_of_text.
7165 Remainder is the blob to be loaded contiguously
7166 from start address. */
7167
7168 info.fw_base = be32_to_cpu(fw_data[1]);
7169 info.fw_len = tp->fw->size - 12;
7170 info.fw_data = &fw_data[3];
1da177e4
LT		 7171
7172 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7173 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7174 &info);
7175 if (err)
7176 return err;
7177
7178 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7179 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7180 &info);
7181 if (err)
7182 return err;
7183
7184 /* Now startup only the RX cpu. */
7185 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7186 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7187
7188 for (i = 0; i < 5; i++) {
077f849d 7189 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7190 break;
7191 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7192 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7193 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7194 udelay(1000);
7195 }
7196 if (i >= 5) {
7197 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7198 "to set RX CPU PC, is %08x should be %08x\n",
7199 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 7200 info.fw_base);
1da177e4
LT		 7201 return -ENODEV;
7202 }
7203 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7204 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7205
7206 return 0;
7207}
7208
1da177e4 7209/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7210
7211/* tp->lock is held. */
7212static int tg3_load_tso_firmware(struct tg3 *tp)
7213{
7214 struct fw_info info;
077f849d 7215 const __be32 *fw_data;
1da177e4
LT		 7216 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7217 int err, i;
7218
7219 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7220 return 0;
7221
077f849d
JSR		 7222 fw_data = (void *)tp->fw->data;
7223
7224 /* Firmware blob starts with version numbers, followed by
7225 start address and length. We are setting complete length.
7226 length = end_address_of_bss - start_address_of_text.
7227 Remainder is the blob to be loaded contiguously
7228 from start address. */
7229
7230 info.fw_base = be32_to_cpu(fw_data[1]);
7231 cpu_scratch_size = tp->fw_len;
7232 info.fw_len = tp->fw->size - 12;
7233 info.fw_data = &fw_data[3];
7234
1da177e4 7235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7236 cpu_base = RX_CPU_BASE;
7237 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7238 } else {
1da177e4
LT		 7239 cpu_base = TX_CPU_BASE;
7240 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7241 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7242 }
7243
7244 err = tg3_load_firmware_cpu(tp, cpu_base,
7245 cpu_scratch_base, cpu_scratch_size,
7246 &info);
7247 if (err)
7248 return err;
7249
7250 /* Now startup the cpu. */
7251 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7252 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7253
7254 for (i = 0; i < 5; i++) {
077f849d 7255 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7256 break;
7257 tw32(cpu_base + CPU_STATE, 0xffffffff);
7258 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7259 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7260 udelay(1000);
7261 }
7262 if (i >= 5) {
7263 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7264 "to set CPU PC, is %08x should be %08x\n",
7265 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7266 info.fw_base);
1da177e4
LT		 7267 return -ENODEV;
7268 }
7269 tw32(cpu_base + CPU_STATE, 0xffffffff);
7270 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7271 return 0;
7272}
7273
1da177e4 7274
1da177e4
LT		 7275static int tg3_set_mac_addr(struct net_device *dev, void *p)
7276{
7277 struct tg3 *tp = netdev_priv(dev);
7278 struct sockaddr *addr = p;
986e0aeb 7279 int err = 0, skip_mac_1 = 0;
1da177e4 7280
f9804ddb
MC		 7281 if (!is_valid_ether_addr(addr->sa_data))
7282 return -EINVAL;
7283
1da177e4
LT		 7284 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7285
e75f7c90
MC		 7286 if (!netif_running(dev))
7287 return 0;
7288
58712ef9 7289 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7290 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7291
986e0aeb
MC		 7292 addr0_high = tr32(MAC_ADDR_0_HIGH);
7293 addr0_low = tr32(MAC_ADDR_0_LOW);
7294 addr1_high = tr32(MAC_ADDR_1_HIGH);
7295 addr1_low = tr32(MAC_ADDR_1_LOW);
7296
7297 /* Skip MAC addr 1 if ASF is using it. */
7298 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7299 !(addr1_high == 0 && addr1_low == 0))
7300 skip_mac_1 = 1;
58712ef9 7301 }
986e0aeb
MC		 7302 spin_lock_bh(&tp->lock);
7303 __tg3_set_mac_addr(tp, skip_mac_1);
7304 spin_unlock_bh(&tp->lock);
1da177e4 7305
b9ec6c1b 7306 return err;
1da177e4
LT		 7307}
7308
7309/* tp->lock is held. */
7310static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7311 dma_addr_t mapping, u32 maxlen_flags,
7312 u32 nic_addr)
7313{
7314 tg3_write_mem(tp,
7315 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7316 ((u64) mapping >> 32));
7317 tg3_write_mem(tp,
7318 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7319 ((u64) mapping & 0xffffffff));
7320 tg3_write_mem(tp,
7321 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7322 maxlen_flags);
7323
7324 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7325 tg3_write_mem(tp,
7326 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7327 nic_addr);
7328}
7329
7330static void __tg3_set_rx_mode(struct net_device *);
d244c892 7331static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7332{
b6080e12
MC		 7333 int i;
7334
19cfaecc 7335 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
b6080e12
MC		 7336 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7337 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7338 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 7339 } else {
7340 tw32(HOSTCC_TXCOL_TICKS, 0);
7341 tw32(HOSTCC_TXMAX_FRAMES, 0);
7342 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
19cfaecc 7343 }
b6080e12 7344
19cfaecc
MC		 7345 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7346 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7347 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7348 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7349 } else {
b6080e12
MC		 7350 tw32(HOSTCC_RXCOL_TICKS, 0);
7351 tw32(HOSTCC_RXMAX_FRAMES, 0);
7352 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7353 }
b6080e12 7354
15f9850d
DM		 7355 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7356 u32 val = ec->stats_block_coalesce_usecs;
7357
b6080e12
MC		 7358 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7359 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7360
15f9850d
DM		 7361 if (!netif_carrier_ok(tp->dev))
7362 val = 0;
7363
7364 tw32(HOSTCC_STAT_COAL_TICKS, val);
7365 }
b6080e12
MC		 7366
7367 for (i = 0; i < tp->irq_cnt - 1; i++) {
7368 u32 reg;
7369
7370 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7371 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 7372 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7373 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 7374 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7375 tw32(reg, ec->rx_max_coalesced_frames_irq);
19cfaecc
MC		 7376
7377 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7378 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7379 tw32(reg, ec->tx_coalesce_usecs);
7380 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7381 tw32(reg, ec->tx_max_coalesced_frames);
7382 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7383 tw32(reg, ec->tx_max_coalesced_frames_irq);
7384 }
b6080e12
MC		 7385 }
7386
7387 for (; i < tp->irq_max - 1; i++) {
7388 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 7389 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 7390 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
19cfaecc
MC		 7391
7392 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7393 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7394 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7395 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7396 }
b6080e12 7397 }
15f9850d 7398}
1da177e4 7399
2d31ecaf
MC		 7400/* tp->lock is held. */
7401static void tg3_rings_reset(struct tg3 *tp)
7402{
7403 int i;
f77a6a8e 7404 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7405 struct tg3_napi *tnapi = &tp->napi[0];
7406
7407 /* Disable all transmit rings but the first. */
7408 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7409 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7410 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7411 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
2d31ecaf
MC		 7412 else
7413 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7414
7415 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7416 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7417 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7418 BDINFO_FLAGS_DISABLED);
7419
7420
7421 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7423 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7424 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf 7425 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
b703df6f
MC		 7426 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2d31ecaf
MC		 7428 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7429 else
7430 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7431
7432 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7433 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7434 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7435 BDINFO_FLAGS_DISABLED);
7436
7437 /* Disable interrupts */
7438 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7439
7440 /* Zero mailbox registers. */
f77a6a8e
MC		 7441 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7442 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7443 tp->napi[i].tx_prod = 0;
7444 tp->napi[i].tx_cons = 0;
c2353a32
MC		 7445 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7446 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 7447 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7448 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7449 }
c2353a32
MC		 7450 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7451 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 7452 } else {
7453 tp->napi[0].tx_prod = 0;
7454 tp->napi[0].tx_cons = 0;
7455 tw32_mailbox(tp->napi[0].prodmbox, 0);
7456 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7457 }
2d31ecaf
MC		 7458
7459 /* Make sure the NIC-based send BD rings are disabled. */
7460 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7461 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7462 for (i = 0; i < 16; i++)
7463 tw32_tx_mbox(mbox + i * 8, 0);
7464 }
7465
7466 txrcb = NIC_SRAM_SEND_RCB;
7467 rxrcb = NIC_SRAM_RCV_RET_RCB;
7468
7469 /* Clear status block in ram. */
7470 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7471
7472 /* Set status block DMA address */
7473 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7474 ((u64) tnapi->status_mapping >> 32));
7475 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7476 ((u64) tnapi->status_mapping & 0xffffffff));
7477
f77a6a8e
MC		 7478 if (tnapi->tx_ring) {
7479 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7480 (TG3_TX_RING_SIZE <<
7481 BDINFO_FLAGS_MAXLEN_SHIFT),
7482 NIC_SRAM_TX_BUFFER_DESC);
7483 txrcb += TG3_BDINFO_SIZE;
7484 }
7485
7486 if (tnapi->rx_rcb) {
7487 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7488 (TG3_RX_RCB_RING_SIZE(tp) <<
7489 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7490 rxrcb += TG3_BDINFO_SIZE;
7491 }
7492
7493 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7494
f77a6a8e
MC		 7495 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7496 u64 mapping = (u64)tnapi->status_mapping;
7497 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7498 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7499
7500 /* Clear status block in ram. */
7501 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7502
19cfaecc
MC		 7503 if (tnapi->tx_ring) {
7504 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7505 (TG3_TX_RING_SIZE <<
7506 BDINFO_FLAGS_MAXLEN_SHIFT),
7507 NIC_SRAM_TX_BUFFER_DESC);
7508 txrcb += TG3_BDINFO_SIZE;
7509 }
f77a6a8e
MC		 7510
7511 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7512 (TG3_RX_RCB_RING_SIZE(tp) <<
7513 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7514
7515 stblk += 8;
f77a6a8e
MC		 7516 rxrcb += TG3_BDINFO_SIZE;
7517 }
2d31ecaf
MC		 7518}
7519
1da177e4 7520/* tp->lock is held. */
8e7a22e3 7521static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7522{
7523 u32 val, rdmac_mode;
7524 int i, err, limit;
21f581a5 7525 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7526
7527 tg3_disable_ints(tp);
7528
7529 tg3_stop_fw(tp);
7530
7531 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7532
7533 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7534 tg3_abort_hw(tp, 1);
1da177e4
LT		 7535 }
7536
dd477003
MC		 7537 if (reset_phy &&
7538 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7539 tg3_phy_reset(tp);
7540
1da177e4
LT		 7541 err = tg3_chip_reset(tp);
7542 if (err)
7543 return err;
7544
7545 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7546
bcb37f6c 7547 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7548 val = tr32(TG3_CPMU_CTRL);
7549 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7550 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7551
7552 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7553 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7554 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7555 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7556
7557 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7558 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7559 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7560 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7561
7562 val = tr32(TG3_CPMU_HST_ACC);
7563 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7564 val |= CPMU_HST_ACC_MACCLK_6_25;
7565 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7566 }
7567
33466d93
MC		 7568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7569 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7570 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7571 PCIE_PWR_MGMT_L1_THRESH_4MS;
7572 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7573
7574 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7575 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7576
7577 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7578
f40386c8
MC		 7579 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7580 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7581 }
7582
614b0590
MC		 7583 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7584 u32 grc_mode = tr32(GRC_MODE);
7585
7586 /* Access the lower 1K of PL PCIE block registers. */
7587 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7588 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7589
7590 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7591 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7592 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7593
7594 tw32(GRC_MODE, grc_mode);
7595 }
7596
1da177e4
LT		 7597 /* This works around an issue with Athlon chipsets on
7598 * B3 tigon3 silicon. This bit has no effect on any
7599 * other revision. But do not set this on PCI Express
795d01c5 7600 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7601 */
795d01c5
MC		 7602 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7603 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7604 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7605 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7606 }
1da177e4
LT		 7607
7608 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7609 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7610 val = tr32(TG3PCI_PCISTATE);
7611 val |= PCISTATE_RETRY_SAME_DMA;
7612 tw32(TG3PCI_PCISTATE, val);
7613 }
7614
0d3031d9
MC		 7615 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7616 /* Allow reads and writes to the
7617 * APE register and memory space.
7618 */
7619 val = tr32(TG3PCI_PCISTATE);
7620 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7621 PCISTATE_ALLOW_APE_SHMEM_WR;
7622 tw32(TG3PCI_PCISTATE, val);
7623 }
7624
1da177e4
LT		 7625 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7626 /* Enable some hw fixes. */
7627 val = tr32(TG3PCI_MSI_DATA);
7628 val |= (1 << 26) | (1 << 28) | (1 << 29);
7629 tw32(TG3PCI_MSI_DATA, val);
7630 }
7631
7632 /* Descriptor ring init may make accesses to the
7633 * NIC SRAM area to setup the TX descriptors, so we
7634 * can only do this after the hardware has been
7635 * successfully reset.
7636 */
32d8c572
MC		 7637 err = tg3_init_rings(tp);
7638 if (err)
7639 return err;
1da177e4 7640
b703df6f
MC		 7641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 7643 val = tr32(TG3PCI_DMA_RW_CTRL) &
7644 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7645 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7646 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7647 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7648 /* This value is determined during the probe time DMA
7649 * engine test, tg3_test_dma.
7650 */
7651 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7652 }
1da177e4
LT		 7653
7654 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7655 GRC_MODE_4X_NIC_SEND_RINGS |
7656 GRC_MODE_NO_TX_PHDR_CSUM |
7657 GRC_MODE_NO_RX_PHDR_CSUM);
7658 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7659
7660 /* Pseudo-header checksum is done by hardware logic and not
7661 * the offload processers, so make the chip do the pseudo-
7662 * header checksums on receive. For transmit it is more
7663 * convenient to do the pseudo-header checksum in software
7664 * as Linux does that on transmit for us in all cases.
7665 */
7666 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7667
7668 tw32(GRC_MODE,
7669 tp->grc_mode |
7670 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7671
7672 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7673 val = tr32(GRC_MISC_CFG);
7674 val &= ~0xff;
7675 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7676 tw32(GRC_MISC_CFG, val);
7677
7678 /* Initialize MBUF/DESC pool. */
cbf46853 7679 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7680 /* Do nothing. */
7681 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7682 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7684 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7685 else
7686 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7687 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7688 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7689 }
1da177e4
LT		 7690 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7691 int fw_len;
7692
077f849d 7693 fw_len = tp->fw_len;
1da177e4
LT		 7694 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7695 tw32(BUFMGR_MB_POOL_ADDR,
7696 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7697 tw32(BUFMGR_MB_POOL_SIZE,
7698 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7699 }
1da177e4 7700
0f893dc6 7701 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7702 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7703 tp->bufmgr_config.mbuf_read_dma_low_water);
7704 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7705 tp->bufmgr_config.mbuf_mac_rx_low_water);
7706 tw32(BUFMGR_MB_HIGH_WATER,
7707 tp->bufmgr_config.mbuf_high_water);
7708 } else {
7709 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7710 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7711 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7712 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7713 tw32(BUFMGR_MB_HIGH_WATER,
7714 tp->bufmgr_config.mbuf_high_water_jumbo);
7715 }
7716 tw32(BUFMGR_DMA_LOW_WATER,
7717 tp->bufmgr_config.dma_low_water);
7718 tw32(BUFMGR_DMA_HIGH_WATER,
7719 tp->bufmgr_config.dma_high_water);
7720
7721 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7722 for (i = 0; i < 2000; i++) {
7723 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7724 break;
7725 udelay(10);
7726 }
7727 if (i >= 2000) {
7728 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7729 tp->dev->name);
7730 return -ENODEV;
7731 }
7732
7733 /* Setup replenish threshold. */
f92905de
MC		 7734 val = tp->rx_pending / 8;
7735 if (val == 0)
7736 val = 1;
7737 else if (val > tp->rx_std_max_post)
7738 val = tp->rx_std_max_post;
b5d3772c
MC		 7739 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7740 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7741 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7742
7743 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7744 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7745 }
f92905de
MC		 7746
7747 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7748
7749 /* Initialize TG3_BDINFO's at:
7750 * RCVDBDI_STD_BD: standard eth size rx ring
7751 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7752 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7753 *
7754 * like so:
7755 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7756 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7757 * ring attribute flags
7758 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7759 *
7760 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7761 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7762 *
7763 * The size of each ring is fixed in the firmware, but the location is
7764 * configurable.
7765 */
7766 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7767 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7768 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7769 ((u64) tpr->rx_std_mapping & 0xffffffff));
87668d35
MC		 7770 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7771 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7772 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7773
fdb72b38
MC		 7774 /* Disable the mini ring */
7775 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7776 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7777 BDINFO_FLAGS_DISABLED);
7778
fdb72b38
MC		 7779 /* Program the jumbo buffer descriptor ring control
7780 * blocks on those devices that have them.
7781 */
8f666b07 7782 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7783 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7784 /* Setup replenish threshold. */
7785 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7786
0f893dc6 7787 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7788 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7789 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7790 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7791 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7792 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7793 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7794 BDINFO_FLAGS_USE_EXT_RECV);
5fd68fbd 7795 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
87668d35
MC		 7796 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7797 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7798 } else {
7799 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7800 BDINFO_FLAGS_DISABLED);
7801 }
7802
b703df6f
MC		 7803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
f6eb9b1f
MC		 7805 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7806 (RX_STD_MAX_SIZE << 2);
7807 else
7808 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7809 } else
7810 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7811
7812 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7813
411da640 7814 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7815 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7816
411da640 7817 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7818 tp->rx_jumbo_pending : 0;
66711e66 7819 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7820
b703df6f
MC		 7821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7822 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
f6eb9b1f
MC		 7823 tw32(STD_REPLENISH_LWM, 32);
7824 tw32(JMB_REPLENISH_LWM, 16);
7825 }
7826
2d31ecaf
MC		 7827 tg3_rings_reset(tp);
7828
1da177e4 7829 /* Initialize MAC address and backoff seed. */
986e0aeb 7830 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7831
7832 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7833 tw32(MAC_RX_MTU_SIZE,
7834 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7835
7836 /* The slot time is changed by tg3_setup_phy if we
7837 * run at gigabit with half duplex.
7838 */
7839 tw32(MAC_TX_LENGTHS,
7840 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7841 (6 << TX_LENGTHS_IPG_SHIFT) |
7842 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7843
7844 /* Receive rules. */
7845 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7846 tw32(RCVLPC_CONFIG, 0x0181);
7847
7848 /* Calculate RDMAC_MODE setting early, we need it to determine
7849 * the RCVLPC_STATE_ENABLE mask.
7850 */
7851 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7852 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7853 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7854 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7855 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7856
57e6983c 7857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7860 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7861 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7862 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7863
85e94ced
MC		 7864 /* If statement applies to 5705 and 5750 PCI devices only */
7865 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7866 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7867 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7868 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7869 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7870 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7871 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7872 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7873 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7874 }
7875 }
7876
85e94ced
MC		 7877 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7878 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7879
1da177e4 7880 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7881 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7882
e849cdc3
MC		 7883 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7885 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7886 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7887
7888 /* Receive/send statistics. */
1661394e
MC		 7889 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7890 val = tr32(RCVLPC_STATS_ENABLE);
7891 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7892 tw32(RCVLPC_STATS_ENABLE, val);
7893 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7894 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7895 val = tr32(RCVLPC_STATS_ENABLE);
7896 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7897 tw32(RCVLPC_STATS_ENABLE, val);
7898 } else {
7899 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7900 }
7901 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7902 tw32(SNDDATAI_STATSENAB, 0xffffff);
7903 tw32(SNDDATAI_STATSCTRL,
7904 (SNDDATAI_SCTRL_ENABLE |
7905 SNDDATAI_SCTRL_FASTUPD));
7906
7907 /* Setup host coalescing engine. */
7908 tw32(HOSTCC_MODE, 0);
7909 for (i = 0; i < 2000; i++) {
7910 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7911 break;
7912 udelay(10);
7913 }
7914
d244c892 7915 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7916
1da177e4
LT		 7917 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7918 /* Status/statistics block address. See tg3_timer,
7919 * the tg3_periodic_fetch_stats call there, and
7920 * tg3_get_stats to see how this works for 5705/5750 chips.
7921 */
1da177e4
LT		 7922 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7923 ((u64) tp->stats_mapping >> 32));
7924 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7925 ((u64) tp->stats_mapping & 0xffffffff));
7926 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7927
1da177e4 7928 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7929
7930 /* Clear statistics and status block memory areas */
7931 for (i = NIC_SRAM_STATS_BLK;
7932 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7933 i += sizeof(u32)) {
7934 tg3_write_mem(tp, i, 0);
7935 udelay(40);
7936 }
1da177e4
LT		 7937 }
7938
7939 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7940
7941 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7942 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7943 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7944 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7945
c94e3941
MC		 7946 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7947 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7948 /* reset to prevent losing 1st rx packet intermittently */
7949 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7950 udelay(10);
7951 }
7952
3bda1258
MC		 7953 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7954 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7955 else
7956 tp->mac_mode = 0;
7957 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7958 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7959 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7960 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7961 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7962 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7963 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7964 udelay(40);
7965
314fba34 7966 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7967 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7968 * register to preserve the GPIO settings for LOMs. The GPIOs,
7969 * whether used as inputs or outputs, are set by boot code after
7970 * reset.
7971 */
9d26e213 7972 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7973 u32 gpio_mask;
7974
9d26e213
MC		 7975 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7976 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7977 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7978
7979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7980 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7981 GRC_LCLCTRL_GPIO_OUTPUT3;
7982
af36e6b6
MC		 7983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7984 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7985
aaf84465 7986 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7987 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7988
7989 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7990 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7991 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7992 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7993 }
1da177e4
LT		 7994 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7995 udelay(100);
7996
baf8a94a
MC		 7997 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7998 val = tr32(MSGINT_MODE);
7999 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8000 tw32(MSGINT_MODE, val);
8001 }
8002
1da177e4
LT		 8003 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8004 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8005 udelay(40);
8006 }
8007
8008 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8009 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8010 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8011 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8012 WDMAC_MODE_LNGREAD_ENAB);
8013
85e94ced
MC		 8014 /* If statement applies to 5705 and 5750 PCI devices only */
8015 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8016 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8017 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 8018 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 8019 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8020 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8021 /* nothing */
8022 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8023 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8024 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8025 val |= WDMAC_MODE_RX_ACCEL;
8026 }
8027 }
8028
d9ab5ad1 8029 /* Enable host coalescing bug fix */
321d32a0 8030 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 8031 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 8032
788a035e
MC		 8033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8034 val |= WDMAC_MODE_BURST_ALL_DATA;
8035
1da177e4
LT		 8036 tw32_f(WDMAC_MODE, val);
8037 udelay(40);
8038
9974a356
MC		 8039 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8040 u16 pcix_cmd;
8041
8042 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8043 &pcix_cmd);
1da177e4 8044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 8045 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8046 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8047 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8048 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8049 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8050 }
9974a356
MC		 8051 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8052 pcix_cmd);
1da177e4
LT		 8053 }
8054
8055 tw32_f(RDMAC_MODE, rdmac_mode);
8056 udelay(40);
8057
8058 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8059 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8060 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8061
8062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8063 tw32(SNDDATAC_MODE,
8064 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8065 else
8066 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8067
1da177e4
LT		 8068 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8069 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8070 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8071 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8072 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8073 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 8074 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
19cfaecc 8075 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
baf8a94a
MC		 8076 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8077 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8078 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8079
8080 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8081 err = tg3_load_5701_a0_firmware_fix(tp);
8082 if (err)
8083 return err;
8084 }
8085
1da177e4
LT		 8086 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8087 err = tg3_load_tso_firmware(tp);
8088 if (err)
8089 return err;
8090 }
1da177e4
LT		 8091
8092 tp->tx_mode = TX_MODE_ENABLE;
8093 tw32_f(MAC_TX_MODE, tp->tx_mode);
8094 udelay(100);
8095
baf8a94a
MC		 8096 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8097 u32 reg = MAC_RSS_INDIR_TBL_0;
8098 u8 *ent = (u8 *)&val;
8099
8100 /* Setup the indirection table */
8101 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8102 int idx = i % sizeof(val);
8103
8104 ent[idx] = i % (tp->irq_cnt - 1);
8105 if (idx == sizeof(val) - 1) {
8106 tw32(reg, val);
8107 reg += 4;
8108 }
8109 }
8110
8111 /* Setup the "secret" hash key. */
8112 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8113 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8114 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8115 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8116 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8117 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8118 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8119 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8120 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8121 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8122 }
8123
1da177e4 8124 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8125 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8126 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8127
baf8a94a
MC		 8128 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8129 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8130 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8131 RX_MODE_RSS_IPV6_HASH_EN |
8132 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8133 RX_MODE_RSS_IPV4_HASH_EN |
8134 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8135
1da177e4
LT		 8136 tw32_f(MAC_RX_MODE, tp->rx_mode);
8137 udelay(10);
8138
1da177e4
LT		 8139 tw32(MAC_LED_CTRL, tp->led_ctrl);
8140
8141 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8142 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8143 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8144 udelay(10);
8145 }
8146 tw32_f(MAC_RX_MODE, tp->rx_mode);
8147 udelay(10);
8148
8149 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8150 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8151 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8152 /* Set drive transmission level to 1.2V */
8153 /* only if the signal pre-emphasis bit is not set */
8154 val = tr32(MAC_SERDES_CFG);
8155 val &= 0xfffff000;
8156 val |= 0x880;
8157 tw32(MAC_SERDES_CFG, val);
8158 }
8159 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8160 tw32(MAC_SERDES_CFG, 0x616000);
8161 }
8162
8163 /* Prevent chip from dropping frames when flow control
8164 * is enabled.
8165 */
666bc831
MC		 8166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8167 val = 1;
8168 else
8169 val = 2;
8170 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4
LT		 8171
8172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8173 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8174 /* Use hardware link auto-negotiation */
8175 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8176 }
8177
d4d2c558
MC		 8178 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8179 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8180 u32 tmp;
8181
8182 tmp = tr32(SERDES_RX_CTRL);
8183 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8184 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8185 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8186 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8187 }
8188
dd477003
MC		 8189 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8190 if (tp->link_config.phy_is_low_power) {
8191 tp->link_config.phy_is_low_power = 0;
8192 tp->link_config.speed = tp->link_config.orig_speed;
8193 tp->link_config.duplex = tp->link_config.orig_duplex;
8194 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8195 }
1da177e4 8196
dd477003
MC		 8197 err = tg3_setup_phy(tp, 0);
8198 if (err)
8199 return err;
1da177e4 8200
dd477003 8201 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8202 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8203 u32 tmp;
8204
8205 /* Clear CRC stats. */
8206 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8207 tg3_writephy(tp, MII_TG3_TEST1,
8208 tmp | MII_TG3_TEST1_CRC_EN);
8209 tg3_readphy(tp, 0x14, &tmp);
8210 }
1da177e4
LT		 8211 }
8212 }
8213
8214 __tg3_set_rx_mode(tp->dev);
8215
8216 /* Initialize receive rules. */
8217 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8218 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8219 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8220 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8221
4cf78e4f 8222 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8223 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8224 limit = 8;
8225 else
8226 limit = 16;
8227 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8228 limit -= 4;
8229 switch (limit) {
8230 case 16:
8231 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8232 case 15:
8233 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8234 case 14:
8235 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8236 case 13:
8237 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8238 case 12:
8239 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8240 case 11:
8241 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8242 case 10:
8243 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8244 case 9:
8245 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8246 case 8:
8247 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8248 case 7:
8249 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8250 case 6:
8251 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8252 case 5:
8253 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8254 case 4:
8255 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8256 case 3:
8257 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8258 case 2:
8259 case 1:
8260
8261 default:
8262 break;
855e1111 8263 }
1da177e4 8264
9ce768ea
MC		 8265 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8266 /* Write our heartbeat update interval to APE. */
8267 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8268 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8269
1da177e4
LT		 8270 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8271
1da177e4
LT		 8272 return 0;
8273}
8274
8275/* Called at device open time to get the chip ready for
8276 * packet processing. Invoked with tp->lock held.
8277 */
8e7a22e3 8278static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8279{
1da177e4
LT		 8280 tg3_switch_clocks(tp);
8281
8282 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8283
2f751b67 8284 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8285}
8286
8287#define TG3_STAT_ADD32(PSTAT, REG) \
8288do { u32 __val = tr32(REG); \
8289 (PSTAT)->low += __val; \
8290 if ((PSTAT)->low < __val) \
8291 (PSTAT)->high += 1; \
8292} while (0)
8293
8294static void tg3_periodic_fetch_stats(struct tg3 *tp)
8295{
8296 struct tg3_hw_stats *sp = tp->hw_stats;
8297
8298 if (!netif_carrier_ok(tp->dev))
8299 return;
8300
8301 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8302 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8303 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8304 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8305 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8306 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8307 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8308 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8309 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8310 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8311 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8312 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8313 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8314
8315 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8316 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8317 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8318 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8319 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8320 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8321 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8322 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8323 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8324 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8325 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8326 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8327 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8328 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8329
8330 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8331 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8332 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8333}
8334
8335static void tg3_timer(unsigned long __opaque)
8336{
8337 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8338
f475f163
MC		 8339 if (tp->irq_sync)
8340 goto restart_timer;
8341
f47c11ee 8342 spin_lock(&tp->lock);
1da177e4 8343
fac9b83e
DM		 8344 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8345 /* All of this garbage is because when using non-tagged
8346 * IRQ status the mailbox/status_block protocol the chip
8347 * uses with the cpu is race prone.
8348 */
898a56f8 8349 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8350 tw32(GRC_LOCAL_CTRL,
8351 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8352 } else {
8353 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8354 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8355 }
1da177e4 8356
fac9b83e
DM		 8357 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8358 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8359 spin_unlock(&tp->lock);
fac9b83e
DM		 8360 schedule_work(&tp->reset_task);
8361 return;
8362 }
1da177e4
LT		 8363 }
8364
1da177e4
LT		 8365 /* This part only runs once per second. */
8366 if (!--tp->timer_counter) {
fac9b83e
DM		 8367 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8368 tg3_periodic_fetch_stats(tp);
8369
1da177e4
LT		 8370 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8371 u32 mac_stat;
8372 int phy_event;
8373
8374 mac_stat = tr32(MAC_STATUS);
8375
8376 phy_event = 0;
8377 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8378 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8379 phy_event = 1;
8380 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8381 phy_event = 1;
8382
8383 if (phy_event)
8384 tg3_setup_phy(tp, 0);
8385 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8386 u32 mac_stat = tr32(MAC_STATUS);
8387 int need_setup = 0;
8388
8389 if (netif_carrier_ok(tp->dev) &&
8390 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8391 need_setup = 1;
8392 }
8393 if (! netif_carrier_ok(tp->dev) &&
8394 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8395 MAC_STATUS_SIGNAL_DET))) {
8396 need_setup = 1;
8397 }
8398 if (need_setup) {
3d3ebe74
MC		 8399 if (!tp->serdes_counter) {
8400 tw32_f(MAC_MODE,
8401 (tp->mac_mode &
8402 ~MAC_MODE_PORT_MODE_MASK));
8403 udelay(40);
8404 tw32_f(MAC_MODE, tp->mac_mode);
8405 udelay(40);
8406 }
1da177e4
LT		 8407 tg3_setup_phy(tp, 0);
8408 }
747e8f8b
MC		 8409 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8410 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8411
8412 tp->timer_counter = tp->timer_multiplier;
8413 }
8414
130b8e4d
MC		 8415 /* Heartbeat is only sent once every 2 seconds.
8416 *
8417 * The heartbeat is to tell the ASF firmware that the host
8418 * driver is still alive. In the event that the OS crashes,
8419 * ASF needs to reset the hardware to free up the FIFO space
8420 * that may be filled with rx packets destined for the host.
8421 * If the FIFO is full, ASF will no longer function properly.
8422 *
8423 * Unintended resets have been reported on real time kernels
8424 * where the timer doesn't run on time. Netpoll will also have
8425 * same problem.
8426 *
8427 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8428 * to check the ring condition when the heartbeat is expiring
8429 * before doing the reset. This will prevent most unintended
8430 * resets.
8431 */
1da177e4 8432 if (!--tp->asf_counter) {
bc7959b2
MC		 8433 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8434 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8435 tg3_wait_for_event_ack(tp);
8436
bbadf503 8437 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8438 FWCMD_NICDRV_ALIVE3);
bbadf503 8439 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8440 /* 5 seconds timeout */
bbadf503 8441 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8442
8443 tg3_generate_fw_event(tp);
1da177e4
LT		 8444 }
8445 tp->asf_counter = tp->asf_multiplier;
8446 }
8447
f47c11ee 8448 spin_unlock(&tp->lock);
1da177e4 8449
f475f163 8450restart_timer:
1da177e4
LT		 8451 tp->timer.expires = jiffies + tp->timer_offset;
8452 add_timer(&tp->timer);
8453}
8454
4f125f42 8455static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8456{
7d12e780 8457 irq_handler_t fn;
fcfa0a32 8458 unsigned long flags;
4f125f42
MC		 8459 char *name;
8460 struct tg3_napi *tnapi = &tp->napi[irq_num];
8461
8462 if (tp->irq_cnt == 1)
8463 name = tp->dev->name;
8464 else {
8465 name = &tnapi->irq_lbl[0];
8466 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8467 name[IFNAMSIZ-1] = 0;
8468 }
fcfa0a32 8469
679563f4 8470 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8471 fn = tg3_msi;
8472 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8473 fn = tg3_msi_1shot;
1fb9df5d 8474 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8475 } else {
8476 fn = tg3_interrupt;
8477 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8478 fn = tg3_interrupt_tagged;
1fb9df5d 8479 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8480 }
4f125f42
MC		 8481
8482 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8483}
8484
7938109f
MC		 8485static int tg3_test_interrupt(struct tg3 *tp)
8486{
09943a18 8487 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8488 struct net_device *dev = tp->dev;
b16250e3 8489 int err, i, intr_ok = 0;
f6eb9b1f 8490 u32 val;
7938109f 8491
d4bc3927
MC		 8492 if (!netif_running(dev))
8493 return -ENODEV;
8494
7938109f
MC		 8495 tg3_disable_ints(tp);
8496
4f125f42 8497 free_irq(tnapi->irq_vec, tnapi);
7938109f 8498
f6eb9b1f
MC		 8499 /*
8500 * Turn off MSI one shot mode. Otherwise this test has no
8501 * observable way to know whether the interrupt was delivered.
8502 */
b703df6f
MC		 8503 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8504 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8505 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8506 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8507 tw32(MSGINT_MODE, val);
8508 }
8509
4f125f42 8510 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8511 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8512 if (err)
8513 return err;
8514
898a56f8 8515 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8516 tg3_enable_ints(tp);
8517
8518 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8519 tnapi->coal_now);
7938109f
MC		 8520
8521 for (i = 0; i < 5; i++) {
b16250e3
MC		 8522 u32 int_mbox, misc_host_ctrl;
8523
898a56f8 8524 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8525 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8526
8527 if ((int_mbox != 0) ||
8528 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8529 intr_ok = 1;
7938109f 8530 break;
b16250e3
MC		 8531 }
8532
7938109f
MC		 8533 msleep(10);
8534 }
8535
8536 tg3_disable_ints(tp);
8537
4f125f42 8538 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8539
4f125f42 8540 err = tg3_request_irq(tp, 0);
7938109f
MC		 8541
8542 if (err)
8543 return err;
8544
f6eb9b1f
MC		 8545 if (intr_ok) {
8546 /* Reenable MSI one shot mode. */
b703df6f
MC		 8547 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8548 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
f6eb9b1f
MC		 8549 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8550 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8551 tw32(MSGINT_MODE, val);
8552 }
7938109f 8553 return 0;
f6eb9b1f 8554 }
7938109f
MC		 8555
8556 return -EIO;
8557}
8558
8559/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8560 * successfully restored
8561 */
8562static int tg3_test_msi(struct tg3 *tp)
8563{
7938109f
MC		 8564 int err;
8565 u16 pci_cmd;
8566
8567 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8568 return 0;
8569
8570 /* Turn off SERR reporting in case MSI terminates with Master
8571 * Abort.
8572 */
8573 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8574 pci_write_config_word(tp->pdev, PCI_COMMAND,
8575 pci_cmd & ~PCI_COMMAND_SERR);
8576
8577 err = tg3_test_interrupt(tp);
8578
8579 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8580
8581 if (!err)
8582 return 0;
8583
8584 /* other failures */
8585 if (err != -EIO)
8586 return err;
8587
8588 /* MSI test failed, go back to INTx mode */
8589 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8590 "switching to INTx mode. Please report this failure to "
8591 "the PCI maintainer and include system chipset information.\n",
8592 tp->dev->name);
8593
4f125f42 8594 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8595
7938109f
MC		 8596 pci_disable_msi(tp->pdev);
8597
8598 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8599
4f125f42 8600 err = tg3_request_irq(tp, 0);
7938109f
MC		 8601 if (err)
8602 return err;
8603
8604 /* Need to reset the chip because the MSI cycle may have terminated
8605 * with Master Abort.
8606 */
f47c11ee 8607 tg3_full_lock(tp, 1);
7938109f 8608
944d980e 8609 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8610 err = tg3_init_hw(tp, 1);
7938109f 8611
f47c11ee 8612 tg3_full_unlock(tp);
7938109f
MC		 8613
8614 if (err)
4f125f42 8615 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8616
8617 return err;
8618}
8619
9e9fd12d
MC		 8620static int tg3_request_firmware(struct tg3 *tp)
8621{
8622 const __be32 *fw_data;
8623
8624 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8625 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8626 tp->dev->name, tp->fw_needed);
8627 return -ENOENT;
8628 }
8629
8630 fw_data = (void *)tp->fw->data;
8631
8632 /* Firmware blob starts with version numbers, followed by
8633 * start address and _full_ length including BSS sections
8634 * (which must be longer than the actual data, of course
8635 */
8636
8637 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8638 if (tp->fw_len < (tp->fw->size - 12)) {
8639 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8640 tp->dev->name, tp->fw_len, tp->fw_needed);
8641 release_firmware(tp->fw);
8642 tp->fw = NULL;
8643 return -EINVAL;
8644 }
8645
8646 /* We no longer need firmware; we have it. */
8647 tp->fw_needed = NULL;
8648 return 0;
8649}
8650
679563f4
MC		 8651static bool tg3_enable_msix(struct tg3 *tp)
8652{
8653 int i, rc, cpus = num_online_cpus();
8654 struct msix_entry msix_ent[tp->irq_max];
8655
8656 if (cpus == 1)
8657 /* Just fallback to the simpler MSI mode. */
8658 return false;
8659
8660 /*
8661 * We want as many rx rings enabled as there are cpus.
8662 * The first MSIX vector only deals with link interrupts, etc,
8663 * so we add one to the number of vectors we are requesting.
8664 */
8665 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8666
8667 for (i = 0; i < tp->irq_max; i++) {
8668 msix_ent[i].entry = i;
8669 msix_ent[i].vector = 0;
8670 }
8671
8672 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8673 if (rc != 0) {
8674 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8675 return false;
8676 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8677 return false;
8678 printk(KERN_NOTICE
8679 "%s: Requested %d MSI-X vectors, received %d\n",
8680 tp->dev->name, tp->irq_cnt, rc);
8681 tp->irq_cnt = rc;
8682 }
8683
baf8a94a
MC		 8684 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8685
679563f4
MC		 8686 for (i = 0; i < tp->irq_max; i++)
8687 tp->napi[i].irq_vec = msix_ent[i].vector;
8688
19cfaecc
MC		 8689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8690 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8691 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8692 } else
8693 tp->dev->real_num_tx_queues = 1;
fe5f5787 8694
679563f4
MC		 8695 return true;
8696}
8697
07b0173c
MC		 8698static void tg3_ints_init(struct tg3 *tp)
8699{
679563f4
MC		 8700 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8701 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8702 /* All MSI supporting chips should support tagged
8703 * status. Assert that this is the case.
8704 */
679563f4
MC		 8705 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8706 "Not using MSI.\n", tp->dev->name);
8707 goto defcfg;
07b0173c 8708 }
4f125f42 8709
679563f4
MC		 8710 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8711 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8712 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8713 pci_enable_msi(tp->pdev) == 0)
8714 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8715
8716 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8717 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8718 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8719 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8720 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8721 }
8722defcfg:
8723 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8724 tp->irq_cnt = 1;
8725 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8726 tp->dev->real_num_tx_queues = 1;
679563f4 8727 }
07b0173c
MC		 8728}
8729
8730static void tg3_ints_fini(struct tg3 *tp)
8731{
679563f4
MC		 8732 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8733 pci_disable_msix(tp->pdev);
8734 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8735 pci_disable_msi(tp->pdev);
8736 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8737 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8738}
8739
1da177e4
LT		 8740static int tg3_open(struct net_device *dev)
8741{
8742 struct tg3 *tp = netdev_priv(dev);
4f125f42 8743 int i, err;
1da177e4 8744
9e9fd12d
MC		 8745 if (tp->fw_needed) {
8746 err = tg3_request_firmware(tp);
8747 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8748 if (err)
8749 return err;
8750 } else if (err) {
8751 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8752 tp->dev->name);
8753 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8754 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8755 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8756 tp->dev->name);
8757 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8758 }
8759 }
8760
c49a1561
MC		 8761 netif_carrier_off(tp->dev);
8762
bc1c7567 8763 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8764 if (err)
bc1c7567 8765 return err;
2f751b67
MC		 8766
8767 tg3_full_lock(tp, 0);
bc1c7567 8768
1da177e4
LT		 8769 tg3_disable_ints(tp);
8770 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8771
f47c11ee 8772 tg3_full_unlock(tp);
1da177e4 8773
679563f4
MC		 8774 /*
8775 * Setup interrupts first so we know how
8776 * many NAPI resources to allocate
8777 */
8778 tg3_ints_init(tp);
8779
1da177e4
LT		 8780 /* The placement of this call is tied
8781 * to the setup and use of Host TX descriptors.
8782 */
8783 err = tg3_alloc_consistent(tp);
8784 if (err)
679563f4 8785 goto err_out1;
88b06bc2 8786
fed97810 8787 tg3_napi_enable(tp);
1da177e4 8788
4f125f42
MC		 8789 for (i = 0; i < tp->irq_cnt; i++) {
8790 struct tg3_napi *tnapi = &tp->napi[i];
8791 err = tg3_request_irq(tp, i);
8792 if (err) {
8793 for (i--; i >= 0; i--)
8794 free_irq(tnapi->irq_vec, tnapi);
8795 break;
8796 }
8797 }
1da177e4 8798
07b0173c 8799 if (err)
679563f4 8800 goto err_out2;
bea3348e 8801
f47c11ee 8802 tg3_full_lock(tp, 0);
1da177e4 8803
8e7a22e3 8804 err = tg3_init_hw(tp, 1);
1da177e4 8805 if (err) {
944d980e 8806 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8807 tg3_free_rings(tp);
8808 } else {
fac9b83e
DM		 8809 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8810 tp->timer_offset = HZ;
8811 else
8812 tp->timer_offset = HZ / 10;
8813
8814 BUG_ON(tp->timer_offset > HZ);
8815 tp->timer_counter = tp->timer_multiplier =
8816 (HZ / tp->timer_offset);
8817 tp->asf_counter = tp->asf_multiplier =
28fbef78 8818 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8819
8820 init_timer(&tp->timer);
8821 tp->timer.expires = jiffies + tp->timer_offset;
8822 tp->timer.data = (unsigned long) tp;
8823 tp->timer.function = tg3_timer;
1da177e4
LT		 8824 }
8825
f47c11ee 8826 tg3_full_unlock(tp);
1da177e4 8827
07b0173c 8828 if (err)
679563f4 8829 goto err_out3;
1da177e4 8830
7938109f
MC		 8831 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8832 err = tg3_test_msi(tp);
fac9b83e 8833
7938109f 8834 if (err) {
f47c11ee 8835 tg3_full_lock(tp, 0);
944d980e 8836 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8837 tg3_free_rings(tp);
f47c11ee 8838 tg3_full_unlock(tp);
7938109f 8839
679563f4 8840 goto err_out2;
7938109f 8841 }
fcfa0a32 8842
f6eb9b1f 8843 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
b703df6f 8844 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
f6eb9b1f
MC		 8845 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8846 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8847 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8848
f6eb9b1f
MC		 8849 tw32(PCIE_TRANSACTION_CFG,
8850 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8851 }
7938109f
MC		 8852 }
8853
b02fd9e3
MC		 8854 tg3_phy_start(tp);
8855
f47c11ee 8856 tg3_full_lock(tp, 0);
1da177e4 8857
7938109f
MC		 8858 add_timer(&tp->timer);
8859 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8860 tg3_enable_ints(tp);
8861
f47c11ee 8862 tg3_full_unlock(tp);
1da177e4 8863
fe5f5787 8864 netif_tx_start_all_queues(dev);
1da177e4
LT		 8865
8866 return 0;
07b0173c 8867
679563f4 8868err_out3:
4f125f42
MC		 8869 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8870 struct tg3_napi *tnapi = &tp->napi[i];
8871 free_irq(tnapi->irq_vec, tnapi);
8872 }
07b0173c 8873
679563f4 8874err_out2:
fed97810 8875 tg3_napi_disable(tp);
07b0173c 8876 tg3_free_consistent(tp);
679563f4
MC		 8877
8878err_out1:
8879 tg3_ints_fini(tp);
07b0173c 8880 return err;
1da177e4
LT		 8881}
8882
8883#if 0
8884/*static*/ void tg3_dump_state(struct tg3 *tp)
8885{
8886 u32 val32, val32_2, val32_3, val32_4, val32_5;
8887 u16 val16;
8888 int i;
898a56f8 8889 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8890
8891 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8892 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8893 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8894 val16, val32);
8895
8896 /* MAC block */
8897 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8898 tr32(MAC_MODE), tr32(MAC_STATUS));
8899 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8900 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8901 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8902 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8903 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8904 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8905
8906 /* Send data initiator control block */
8907 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8908 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8909 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8910 tr32(SNDDATAI_STATSCTRL));
8911
8912 /* Send data completion control block */
8913 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8914
8915 /* Send BD ring selector block */
8916 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8917 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8918
8919 /* Send BD initiator control block */
8920 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8921 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8922
8923 /* Send BD completion control block */
8924 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8925
8926 /* Receive list placement control block */
8927 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8928 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8929 printk(" RCVLPC_STATSCTRL[%08x]\n",
8930 tr32(RCVLPC_STATSCTRL));
8931
8932 /* Receive data and receive BD initiator control block */
8933 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8934 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8935
8936 /* Receive data completion control block */
8937 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8938 tr32(RCVDCC_MODE));
8939
8940 /* Receive BD initiator control block */
8941 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8942 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8943
8944 /* Receive BD completion control block */
8945 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8946 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8947
8948 /* Receive list selector control block */
8949 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8950 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8951
8952 /* Mbuf cluster free block */
8953 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8954 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8955
8956 /* Host coalescing control block */
8957 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8958 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8959 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8960 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8961 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8962 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8963 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8964 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8965 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8966 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8967 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8968 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8969
8970 /* Memory arbiter control block */
8971 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8972 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8973
8974 /* Buffer manager control block */
8975 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8976 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8977 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8978 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8979 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8980 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8981 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8982 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8983
8984 /* Read DMA control block */
8985 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8986 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8987
8988 /* Write DMA control block */
8989 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8990 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8991
8992 /* DMA completion block */
8993 printk("DEBUG: DMAC_MODE[%08x]\n",
8994 tr32(DMAC_MODE));
8995
8996 /* GRC block */
8997 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8998 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8999 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9000 tr32(GRC_LOCAL_CTRL));
9001
9002 /* TG3_BDINFOs */
9003 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9004 tr32(RCVDBDI_JUMBO_BD + 0x0),
9005 tr32(RCVDBDI_JUMBO_BD + 0x4),
9006 tr32(RCVDBDI_JUMBO_BD + 0x8),
9007 tr32(RCVDBDI_JUMBO_BD + 0xc));
9008 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9009 tr32(RCVDBDI_STD_BD + 0x0),
9010 tr32(RCVDBDI_STD_BD + 0x4),
9011 tr32(RCVDBDI_STD_BD + 0x8),
9012 tr32(RCVDBDI_STD_BD + 0xc));
9013 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9014 tr32(RCVDBDI_MINI_BD + 0x0),
9015 tr32(RCVDBDI_MINI_BD + 0x4),
9016 tr32(RCVDBDI_MINI_BD + 0x8),
9017 tr32(RCVDBDI_MINI_BD + 0xc));
9018
9019 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9020 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9021 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9022 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9023 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9024 val32, val32_2, val32_3, val32_4);
9025
9026 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9027 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9028 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9029 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9030 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9031 val32, val32_2, val32_3, val32_4);
9032
9033 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9034 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9035 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9036 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9037 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9038 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9039 val32, val32_2, val32_3, val32_4, val32_5);
9040
9041 /* SW status block */
898a56f8
MC		 9042 printk(KERN_DEBUG
9043 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9044 sblk->status,
9045 sblk->status_tag,
9046 sblk->rx_jumbo_consumer,
9047 sblk->rx_consumer,
9048 sblk->rx_mini_consumer,
9049 sblk->idx[0].rx_producer,
9050 sblk->idx[0].tx_consumer);
1da177e4
LT		 9051
9052 /* SW statistics block */
9053 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9054 ((u32 *)tp->hw_stats)[0],
9055 ((u32 *)tp->hw_stats)[1],
9056 ((u32 *)tp->hw_stats)[2],
9057 ((u32 *)tp->hw_stats)[3]);
9058
9059 /* Mailboxes */
9060 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9061 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9062 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9063 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9064 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9065
9066 /* NIC side send descriptors. */
9067 for (i = 0; i < 6; i++) {
9068 unsigned long txd;
9069
9070 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9071 + (i * sizeof(struct tg3_tx_buffer_desc));
9072 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9073 i,
9074 readl(txd + 0x0), readl(txd + 0x4),
9075 readl(txd + 0x8), readl(txd + 0xc));
9076 }
9077
9078 /* NIC side RX descriptors. */
9079 for (i = 0; i < 6; i++) {
9080 unsigned long rxd;
9081
9082 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9083 + (i * sizeof(struct tg3_rx_buffer_desc));
9084 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9085 i,
9086 readl(rxd + 0x0), readl(rxd + 0x4),
9087 readl(rxd + 0x8), readl(rxd + 0xc));
9088 rxd += (4 * sizeof(u32));
9089 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9090 i,
9091 readl(rxd + 0x0), readl(rxd + 0x4),
9092 readl(rxd + 0x8), readl(rxd + 0xc));
9093 }
9094
9095 for (i = 0; i < 6; i++) {
9096 unsigned long rxd;
9097
9098 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9099 + (i * sizeof(struct tg3_rx_buffer_desc));
9100 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9101 i,
9102 readl(rxd + 0x0), readl(rxd + 0x4),
9103 readl(rxd + 0x8), readl(rxd + 0xc));
9104 rxd += (4 * sizeof(u32));
9105 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9106 i,
9107 readl(rxd + 0x0), readl(rxd + 0x4),
9108 readl(rxd + 0x8), readl(rxd + 0xc));
9109 }
9110}
9111#endif
9112
9113static struct net_device_stats *tg3_get_stats(struct net_device *);
9114static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9115
9116static int tg3_close(struct net_device *dev)
9117{
4f125f42 9118 int i;
1da177e4
LT		 9119 struct tg3 *tp = netdev_priv(dev);
9120
fed97810 9121 tg3_napi_disable(tp);
28e53bdd 9122 cancel_work_sync(&tp->reset_task);
7faa006f 9123
fe5f5787 9124 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9125
9126 del_timer_sync(&tp->timer);
9127
24bb4fb6
MC		 9128 tg3_phy_stop(tp);
9129
f47c11ee 9130 tg3_full_lock(tp, 1);
1da177e4
LT		 9131#if 0
9132 tg3_dump_state(tp);
9133#endif
9134
9135 tg3_disable_ints(tp);
9136
944d980e 9137 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9138 tg3_free_rings(tp);
5cf64b8a 9139 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9140
f47c11ee 9141 tg3_full_unlock(tp);
1da177e4 9142
4f125f42
MC		 9143 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9144 struct tg3_napi *tnapi = &tp->napi[i];
9145 free_irq(tnapi->irq_vec, tnapi);
9146 }
07b0173c
MC		 9147
9148 tg3_ints_fini(tp);
1da177e4
LT		 9149
9150 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9151 sizeof(tp->net_stats_prev));
9152 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9153 sizeof(tp->estats_prev));
9154
9155 tg3_free_consistent(tp);
9156
bc1c7567
MC		 9157 tg3_set_power_state(tp, PCI_D3hot);
9158
9159 netif_carrier_off(tp->dev);
9160
1da177e4
LT		 9161 return 0;
9162}
9163
9164static inline unsigned long get_stat64(tg3_stat64_t *val)
9165{
9166 unsigned long ret;
9167
9168#if (BITS_PER_LONG == 32)
9169 ret = val->low;
9170#else
9171 ret = ((u64)val->high << 32) | ((u64)val->low);
9172#endif
9173 return ret;
9174}
9175
816f8b86
SB		 9176static inline u64 get_estat64(tg3_stat64_t *val)
9177{
9178 return ((u64)val->high << 32) | ((u64)val->low);
9179}
9180
1da177e4
LT		 9181static unsigned long calc_crc_errors(struct tg3 *tp)
9182{
9183 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9184
9185 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9186 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9187 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9188 u32 val;
9189
f47c11ee 9190 spin_lock_bh(&tp->lock);
569a5df8
MC		 9191 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9192 tg3_writephy(tp, MII_TG3_TEST1,
9193 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9194 tg3_readphy(tp, 0x14, &val);
9195 } else
9196 val = 0;
f47c11ee 9197 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9198
9199 tp->phy_crc_errors += val;
9200
9201 return tp->phy_crc_errors;
9202 }
9203
9204 return get_stat64(&hw_stats->rx_fcs_errors);
9205}
9206
9207#define ESTAT_ADD(member) \
9208 estats->member = old_estats->member + \
816f8b86 9209 get_estat64(&hw_stats->member)
1da177e4
LT		 9210
9211static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9212{
9213 struct tg3_ethtool_stats *estats = &tp->estats;
9214 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9215 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9216
9217 if (!hw_stats)
9218 return old_estats;
9219
9220 ESTAT_ADD(rx_octets);
9221 ESTAT_ADD(rx_fragments);
9222 ESTAT_ADD(rx_ucast_packets);
9223 ESTAT_ADD(rx_mcast_packets);
9224 ESTAT_ADD(rx_bcast_packets);
9225 ESTAT_ADD(rx_fcs_errors);
9226 ESTAT_ADD(rx_align_errors);
9227 ESTAT_ADD(rx_xon_pause_rcvd);
9228 ESTAT_ADD(rx_xoff_pause_rcvd);
9229 ESTAT_ADD(rx_mac_ctrl_rcvd);
9230 ESTAT_ADD(rx_xoff_entered);
9231 ESTAT_ADD(rx_frame_too_long_errors);
9232 ESTAT_ADD(rx_jabbers);
9233 ESTAT_ADD(rx_undersize_packets);
9234 ESTAT_ADD(rx_in_length_errors);
9235 ESTAT_ADD(rx_out_length_errors);
9236 ESTAT_ADD(rx_64_or_less_octet_packets);
9237 ESTAT_ADD(rx_65_to_127_octet_packets);
9238 ESTAT_ADD(rx_128_to_255_octet_packets);
9239 ESTAT_ADD(rx_256_to_511_octet_packets);
9240 ESTAT_ADD(rx_512_to_1023_octet_packets);
9241 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9242 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9243 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9244 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9245 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9246
9247 ESTAT_ADD(tx_octets);
9248 ESTAT_ADD(tx_collisions);
9249 ESTAT_ADD(tx_xon_sent);
9250 ESTAT_ADD(tx_xoff_sent);
9251 ESTAT_ADD(tx_flow_control);
9252 ESTAT_ADD(tx_mac_errors);
9253 ESTAT_ADD(tx_single_collisions);
9254 ESTAT_ADD(tx_mult_collisions);
9255 ESTAT_ADD(tx_deferred);
9256 ESTAT_ADD(tx_excessive_collisions);
9257 ESTAT_ADD(tx_late_collisions);
9258 ESTAT_ADD(tx_collide_2times);
9259 ESTAT_ADD(tx_collide_3times);
9260 ESTAT_ADD(tx_collide_4times);
9261 ESTAT_ADD(tx_collide_5times);
9262 ESTAT_ADD(tx_collide_6times);
9263 ESTAT_ADD(tx_collide_7times);
9264 ESTAT_ADD(tx_collide_8times);
9265 ESTAT_ADD(tx_collide_9times);
9266 ESTAT_ADD(tx_collide_10times);
9267 ESTAT_ADD(tx_collide_11times);
9268 ESTAT_ADD(tx_collide_12times);
9269 ESTAT_ADD(tx_collide_13times);
9270 ESTAT_ADD(tx_collide_14times);
9271 ESTAT_ADD(tx_collide_15times);
9272 ESTAT_ADD(tx_ucast_packets);
9273 ESTAT_ADD(tx_mcast_packets);
9274 ESTAT_ADD(tx_bcast_packets);
9275 ESTAT_ADD(tx_carrier_sense_errors);
9276 ESTAT_ADD(tx_discards);
9277 ESTAT_ADD(tx_errors);
9278
9279 ESTAT_ADD(dma_writeq_full);
9280 ESTAT_ADD(dma_write_prioq_full);
9281 ESTAT_ADD(rxbds_empty);
9282 ESTAT_ADD(rx_discards);
9283 ESTAT_ADD(rx_errors);
9284 ESTAT_ADD(rx_threshold_hit);
9285
9286 ESTAT_ADD(dma_readq_full);
9287 ESTAT_ADD(dma_read_prioq_full);
9288 ESTAT_ADD(tx_comp_queue_full);
9289
9290 ESTAT_ADD(ring_set_send_prod_index);
9291 ESTAT_ADD(ring_status_update);
9292 ESTAT_ADD(nic_irqs);
9293 ESTAT_ADD(nic_avoided_irqs);
9294 ESTAT_ADD(nic_tx_threshold_hit);
9295
9296 return estats;
9297}
9298
9299static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9300{
9301 struct tg3 *tp = netdev_priv(dev);
9302 struct net_device_stats *stats = &tp->net_stats;
9303 struct net_device_stats *old_stats = &tp->net_stats_prev;
9304 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9305
9306 if (!hw_stats)
9307 return old_stats;
9308
9309 stats->rx_packets = old_stats->rx_packets +
9310 get_stat64(&hw_stats->rx_ucast_packets) +
9311 get_stat64(&hw_stats->rx_mcast_packets) +
9312 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9313
1da177e4
LT		 9314 stats->tx_packets = old_stats->tx_packets +
9315 get_stat64(&hw_stats->tx_ucast_packets) +
9316 get_stat64(&hw_stats->tx_mcast_packets) +
9317 get_stat64(&hw_stats->tx_bcast_packets);
9318
9319 stats->rx_bytes = old_stats->rx_bytes +
9320 get_stat64(&hw_stats->rx_octets);
9321 stats->tx_bytes = old_stats->tx_bytes +
9322 get_stat64(&hw_stats->tx_octets);
9323
9324 stats->rx_errors = old_stats->rx_errors +
4f63b877 9325 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9326 stats->tx_errors = old_stats->tx_errors +
9327 get_stat64(&hw_stats->tx_errors) +
9328 get_stat64(&hw_stats->tx_mac_errors) +
9329 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9330 get_stat64(&hw_stats->tx_discards);
9331
9332 stats->multicast = old_stats->multicast +
9333 get_stat64(&hw_stats->rx_mcast_packets);
9334 stats->collisions = old_stats->collisions +
9335 get_stat64(&hw_stats->tx_collisions);
9336
9337 stats->rx_length_errors = old_stats->rx_length_errors +
9338 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9339 get_stat64(&hw_stats->rx_undersize_packets);
9340
9341 stats->rx_over_errors = old_stats->rx_over_errors +
9342 get_stat64(&hw_stats->rxbds_empty);
9343 stats->rx_frame_errors = old_stats->rx_frame_errors +
9344 get_stat64(&hw_stats->rx_align_errors);
9345 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9346 get_stat64(&hw_stats->tx_discards);
9347 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9348 get_stat64(&hw_stats->tx_carrier_sense_errors);
9349
9350 stats->rx_crc_errors = old_stats->rx_crc_errors +
9351 calc_crc_errors(tp);
9352
4f63b877
JL		 9353 stats->rx_missed_errors = old_stats->rx_missed_errors +
9354 get_stat64(&hw_stats->rx_discards);
9355
1da177e4
LT		 9356 return stats;
9357}
9358
9359static inline u32 calc_crc(unsigned char *buf, int len)
9360{
9361 u32 reg;
9362 u32 tmp;
9363 int j, k;
9364
9365 reg = 0xffffffff;
9366
9367 for (j = 0; j < len; j++) {
9368 reg ^= buf[j];
9369
9370 for (k = 0; k < 8; k++) {
9371 tmp = reg & 0x01;
9372
9373 reg >>= 1;
9374
9375 if (tmp) {
9376 reg ^= 0xedb88320;
9377 }
9378 }
9379 }
9380
9381 return ~reg;
9382}
9383
9384static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9385{
9386 /* accept or reject all multicast frames */
9387 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9388 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9389 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9390 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9391}
9392
9393static void __tg3_set_rx_mode(struct net_device *dev)
9394{
9395 struct tg3 *tp = netdev_priv(dev);
9396 u32 rx_mode;
9397
9398 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9399 RX_MODE_KEEP_VLAN_TAG);
9400
9401 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9402 * flag clear.
9403 */
9404#if TG3_VLAN_TAG_USED
9405 if (!tp->vlgrp &&
9406 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9407 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9408#else
9409 /* By definition, VLAN is disabled always in this
9410 * case.
9411 */
9412 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9413 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9414#endif
9415
9416 if (dev->flags & IFF_PROMISC) {
9417 /* Promiscuous mode. */
9418 rx_mode |= RX_MODE_PROMISC;
9419 } else if (dev->flags & IFF_ALLMULTI) {
9420 /* Accept all multicast. */
9421 tg3_set_multi (tp, 1);
9422 } else if (dev->mc_count < 1) {
9423 /* Reject all multicast. */
9424 tg3_set_multi (tp, 0);
9425 } else {
9426 /* Accept one or more multicast(s). */
9427 struct dev_mc_list *mclist;
9428 unsigned int i;
9429 u32 mc_filter[4] = { 0, };
9430 u32 regidx;
9431 u32 bit;
9432 u32 crc;
9433
9434 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9435 i++, mclist = mclist->next) {
9436
9437 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9438 bit = ~crc & 0x7f;
9439 regidx = (bit & 0x60) >> 5;
9440 bit &= 0x1f;
9441 mc_filter[regidx] |= (1 << bit);
9442 }
9443
9444 tw32(MAC_HASH_REG_0, mc_filter[0]);
9445 tw32(MAC_HASH_REG_1, mc_filter[1]);
9446 tw32(MAC_HASH_REG_2, mc_filter[2]);
9447 tw32(MAC_HASH_REG_3, mc_filter[3]);
9448 }
9449
9450 if (rx_mode != tp->rx_mode) {
9451 tp->rx_mode = rx_mode;
9452 tw32_f(MAC_RX_MODE, rx_mode);
9453 udelay(10);
9454 }
9455}
9456
9457static void tg3_set_rx_mode(struct net_device *dev)
9458{
9459 struct tg3 *tp = netdev_priv(dev);
9460
e75f7c90
MC		 9461 if (!netif_running(dev))
9462 return;
9463
f47c11ee 9464 tg3_full_lock(tp, 0);
1da177e4 9465 __tg3_set_rx_mode(dev);
f47c11ee 9466 tg3_full_unlock(tp);
1da177e4
LT		 9467}
9468
9469#define TG3_REGDUMP_LEN (32 * 1024)
9470
9471static int tg3_get_regs_len(struct net_device *dev)
9472{
9473 return TG3_REGDUMP_LEN;
9474}
9475
9476static void tg3_get_regs(struct net_device *dev,
9477 struct ethtool_regs *regs, void *_p)
9478{
9479 u32 *p = _p;
9480 struct tg3 *tp = netdev_priv(dev);
9481 u8 *orig_p = _p;
9482 int i;
9483
9484 regs->version = 0;
9485
9486 memset(p, 0, TG3_REGDUMP_LEN);
9487
bc1c7567
MC		 9488 if (tp->link_config.phy_is_low_power)
9489 return;
9490
f47c11ee 9491 tg3_full_lock(tp, 0);
1da177e4
LT		 9492
9493#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9494#define GET_REG32_LOOP(base,len) \
9495do { p = (u32 *)(orig_p + (base)); \
9496 for (i = 0; i < len; i += 4) \
9497 __GET_REG32((base) + i); \
9498} while (0)
9499#define GET_REG32_1(reg) \
9500do { p = (u32 *)(orig_p + (reg)); \
9501 __GET_REG32((reg)); \
9502} while (0)
9503
9504 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9505 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9506 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9507 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9508 GET_REG32_1(SNDDATAC_MODE);
9509 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9510 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9511 GET_REG32_1(SNDBDC_MODE);
9512 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9513 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9514 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9515 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9516 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9517 GET_REG32_1(RCVDCC_MODE);
9518 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9519 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9520 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9521 GET_REG32_1(MBFREE_MODE);
9522 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9523 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9524 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9525 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9526 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9527 GET_REG32_1(RX_CPU_MODE);
9528 GET_REG32_1(RX_CPU_STATE);
9529 GET_REG32_1(RX_CPU_PGMCTR);
9530 GET_REG32_1(RX_CPU_HWBKPT);
9531 GET_REG32_1(TX_CPU_MODE);
9532 GET_REG32_1(TX_CPU_STATE);
9533 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9534 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9535 GET_REG32_LOOP(FTQ_RESET, 0x120);
9536 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9537 GET_REG32_1(DMAC_MODE);
9538 GET_REG32_LOOP(GRC_MODE, 0x4c);
9539 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9540 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9541
9542#undef __GET_REG32
9543#undef GET_REG32_LOOP
9544#undef GET_REG32_1
9545
f47c11ee 9546 tg3_full_unlock(tp);
1da177e4
LT		 9547}
9548
9549static int tg3_get_eeprom_len(struct net_device *dev)
9550{
9551 struct tg3 *tp = netdev_priv(dev);
9552
9553 return tp->nvram_size;
9554}
9555
1da177e4
LT		 9556static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9557{
9558 struct tg3 *tp = netdev_priv(dev);
9559 int ret;
9560 u8 *pd;
b9fc7dc5 9561 u32 i, offset, len, b_offset, b_count;
a9dc529d 9562 __be32 val;
1da177e4 9563
df259d8c
MC		 9564 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9565 return -EINVAL;
9566
bc1c7567
MC		 9567 if (tp->link_config.phy_is_low_power)
9568 return -EAGAIN;
9569
1da177e4
LT		 9570 offset = eeprom->offset;
9571 len = eeprom->len;
9572 eeprom->len = 0;
9573
9574 eeprom->magic = TG3_EEPROM_MAGIC;
9575
9576 if (offset & 3) {
9577 /* adjustments to start on required 4 byte boundary */
9578 b_offset = offset & 3;
9579 b_count = 4 - b_offset;
9580 if (b_count > len) {
9581 /* i.e. offset=1 len=2 */
9582 b_count = len;
9583 }
a9dc529d 9584 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9585 if (ret)
9586 return ret;
1da177e4
LT		 9587 memcpy(data, ((char*)&val) + b_offset, b_count);
9588 len -= b_count;
9589 offset += b_count;
9590 eeprom->len += b_count;
9591 }
9592
9593 /* read bytes upto the last 4 byte boundary */
9594 pd = &data[eeprom->len];
9595 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9596 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9597 if (ret) {
9598 eeprom->len += i;
9599 return ret;
9600 }
1da177e4
LT		 9601 memcpy(pd + i, &val, 4);
9602 }
9603 eeprom->len += i;
9604
9605 if (len & 3) {
9606 /* read last bytes not ending on 4 byte boundary */
9607 pd = &data[eeprom->len];
9608 b_count = len & 3;
9609 b_offset = offset + len - b_count;
a9dc529d 9610 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9611 if (ret)
9612 return ret;
b9fc7dc5 9613 memcpy(pd, &val, b_count);
1da177e4
LT		 9614 eeprom->len += b_count;
9615 }
9616 return 0;
9617}
9618
6aa20a22 9619static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9620
9621static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9622{
9623 struct tg3 *tp = netdev_priv(dev);
9624 int ret;
b9fc7dc5 9625 u32 offset, len, b_offset, odd_len;
1da177e4 9626 u8 *buf;
a9dc529d 9627 __be32 start, end;
1da177e4 9628
bc1c7567
MC		 9629 if (tp->link_config.phy_is_low_power)
9630 return -EAGAIN;
9631
df259d8c
MC		 9632 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9633 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9634 return -EINVAL;
9635
9636 offset = eeprom->offset;
9637 len = eeprom->len;
9638
9639 if ((b_offset = (offset & 3))) {
9640 /* adjustments to start on required 4 byte boundary */
a9dc529d 9641 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9642 if (ret)
9643 return ret;
1da177e4
LT		 9644 len += b_offset;
9645 offset &= ~3;
1c8594b4
MC		 9646 if (len < 4)
9647 len = 4;
1da177e4
LT		 9648 }
9649
9650 odd_len = 0;
1c8594b4 9651 if (len & 3) {
1da177e4
LT		 9652 /* adjustments to end on required 4 byte boundary */
9653 odd_len = 1;
9654 len = (len + 3) & ~3;
a9dc529d 9655 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9656 if (ret)
9657 return ret;
1da177e4
LT		 9658 }
9659
9660 buf = data;
9661 if (b_offset || odd_len) {
9662 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9663 if (!buf)
1da177e4
LT		 9664 return -ENOMEM;
9665 if (b_offset)
9666 memcpy(buf, &start, 4);
9667 if (odd_len)
9668 memcpy(buf+len-4, &end, 4);
9669 memcpy(buf + b_offset, data, eeprom->len);
9670 }
9671
9672 ret = tg3_nvram_write_block(tp, offset, len, buf);
9673
9674 if (buf != data)
9675 kfree(buf);
9676
9677 return ret;
9678}
9679
9680static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9681{
b02fd9e3
MC		 9682 struct tg3 *tp = netdev_priv(dev);
9683
9684 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9685 struct phy_device *phydev;
b02fd9e3
MC		 9686 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9687 return -EAGAIN;
3f0e3ad7
MC		 9688 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9689 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9690 }
6aa20a22 9691
1da177e4
LT		 9692 cmd->supported = (SUPPORTED_Autoneg);
9693
9694 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9695 cmd->supported |= (SUPPORTED_1000baseT_Half |
9696 SUPPORTED_1000baseT_Full);
9697
ef348144 9698 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9699 cmd->supported |= (SUPPORTED_100baseT_Half |
9700 SUPPORTED_100baseT_Full |
9701 SUPPORTED_10baseT_Half |
9702 SUPPORTED_10baseT_Full |
3bebab59 9703 SUPPORTED_TP);
ef348144
KK		 9704 cmd->port = PORT_TP;
9705 } else {
1da177e4 9706 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9707 cmd->port = PORT_FIBRE;
9708 }
6aa20a22 9709
1da177e4
LT		 9710 cmd->advertising = tp->link_config.advertising;
9711 if (netif_running(dev)) {
9712 cmd->speed = tp->link_config.active_speed;
9713 cmd->duplex = tp->link_config.active_duplex;
9714 }
882e9793 9715 cmd->phy_address = tp->phy_addr;
7e5856bd 9716 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9717 cmd->autoneg = tp->link_config.autoneg;
9718 cmd->maxtxpkt = 0;
9719 cmd->maxrxpkt = 0;
9720 return 0;
9721}
6aa20a22 9722
1da177e4
LT		 9723static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9724{
9725 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9726
b02fd9e3 9727 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9728 struct phy_device *phydev;
b02fd9e3
MC		 9729 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9730 return -EAGAIN;
3f0e3ad7
MC		 9731 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9732 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9733 }
9734
7e5856bd
MC		 9735 if (cmd->autoneg != AUTONEG_ENABLE &&
9736 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9737 return -EINVAL;
7e5856bd
MC		 9738
9739 if (cmd->autoneg == AUTONEG_DISABLE &&
9740 cmd->duplex != DUPLEX_FULL &&
9741 cmd->duplex != DUPLEX_HALF)
37ff238d 9742 return -EINVAL;
1da177e4 9743
7e5856bd
MC		 9744 if (cmd->autoneg == AUTONEG_ENABLE) {
9745 u32 mask = ADVERTISED_Autoneg |
9746 ADVERTISED_Pause |
9747 ADVERTISED_Asym_Pause;
9748
9749 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9750 mask |= ADVERTISED_1000baseT_Half |
9751 ADVERTISED_1000baseT_Full;
9752
9753 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9754 mask |= ADVERTISED_100baseT_Half |
9755 ADVERTISED_100baseT_Full |
9756 ADVERTISED_10baseT_Half |
9757 ADVERTISED_10baseT_Full |
9758 ADVERTISED_TP;
9759 else
9760 mask |= ADVERTISED_FIBRE;
9761
9762 if (cmd->advertising & ~mask)
9763 return -EINVAL;
9764
9765 mask &= (ADVERTISED_1000baseT_Half |
9766 ADVERTISED_1000baseT_Full |
9767 ADVERTISED_100baseT_Half |
9768 ADVERTISED_100baseT_Full |
9769 ADVERTISED_10baseT_Half |
9770 ADVERTISED_10baseT_Full);
9771
9772 cmd->advertising &= mask;
9773 } else {
9774 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9775 if (cmd->speed != SPEED_1000)
9776 return -EINVAL;
9777
9778 if (cmd->duplex != DUPLEX_FULL)
9779 return -EINVAL;
9780 } else {
9781 if (cmd->speed != SPEED_100 &&
9782 cmd->speed != SPEED_10)
9783 return -EINVAL;
9784 }
9785 }
9786
f47c11ee 9787 tg3_full_lock(tp, 0);
1da177e4
LT		 9788
9789 tp->link_config.autoneg = cmd->autoneg;
9790 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9791 tp->link_config.advertising = (cmd->advertising |
9792 ADVERTISED_Autoneg);
1da177e4
LT		 9793 tp->link_config.speed = SPEED_INVALID;
9794 tp->link_config.duplex = DUPLEX_INVALID;
9795 } else {
9796 tp->link_config.advertising = 0;
9797 tp->link_config.speed = cmd->speed;
9798 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9799 }
6aa20a22 9800
24fcad6b
MC		 9801 tp->link_config.orig_speed = tp->link_config.speed;
9802 tp->link_config.orig_duplex = tp->link_config.duplex;
9803 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9804
1da177e4
LT		 9805 if (netif_running(dev))
9806 tg3_setup_phy(tp, 1);
9807
f47c11ee 9808 tg3_full_unlock(tp);
6aa20a22 9809
1da177e4
LT		 9810 return 0;
9811}
6aa20a22 9812
1da177e4
LT		 9813static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9814{
9815 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9816
1da177e4
LT		 9817 strcpy(info->driver, DRV_MODULE_NAME);
9818 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9819 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9820 strcpy(info->bus_info, pci_name(tp->pdev));
9821}
6aa20a22 9822
1da177e4
LT		 9823static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9824{
9825 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9826
12dac075
RW		 9827 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9828 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9829 wol->supported = WAKE_MAGIC;
9830 else
9831 wol->supported = 0;
1da177e4 9832 wol->wolopts = 0;
05ac4cb7
MC		 9833 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9834 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9835 wol->wolopts = WAKE_MAGIC;
9836 memset(&wol->sopass, 0, sizeof(wol->sopass));
9837}
6aa20a22 9838
1da177e4
LT		 9839static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9840{
9841 struct tg3 *tp = netdev_priv(dev);
12dac075 9842 struct device *dp = &tp->pdev->dev;
6aa20a22 9843
1da177e4
LT		 9844 if (wol->wolopts & ~WAKE_MAGIC)
9845 return -EINVAL;
9846 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9847 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9848 return -EINVAL;
6aa20a22 9849
f47c11ee 9850 spin_lock_bh(&tp->lock);
12dac075 9851 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9852 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9853 device_set_wakeup_enable(dp, true);
9854 } else {
1da177e4 9855 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9856 device_set_wakeup_enable(dp, false);
9857 }
f47c11ee 9858 spin_unlock_bh(&tp->lock);
6aa20a22 9859
1da177e4
LT		 9860 return 0;
9861}
6aa20a22 9862
1da177e4
LT		 9863static u32 tg3_get_msglevel(struct net_device *dev)
9864{
9865 struct tg3 *tp = netdev_priv(dev);
9866 return tp->msg_enable;
9867}
6aa20a22 9868
1da177e4
LT		 9869static void tg3_set_msglevel(struct net_device *dev, u32 value)
9870{
9871 struct tg3 *tp = netdev_priv(dev);
9872 tp->msg_enable = value;
9873}
6aa20a22 9874
1da177e4
LT		 9875static int tg3_set_tso(struct net_device *dev, u32 value)
9876{
9877 struct tg3 *tp = netdev_priv(dev);
9878
9879 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9880 if (value)
9881 return -EINVAL;
9882 return 0;
9883 }
027455ad 9884 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9885 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9886 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9887 if (value) {
b0026624 9888 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9889 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9891 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9892 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9894 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9895 dev->features |= NETIF_F_TSO_ECN;
9896 } else
9897 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9898 }
1da177e4
LT		 9899 return ethtool_op_set_tso(dev, value);
9900}
6aa20a22 9901
1da177e4
LT		 9902static int tg3_nway_reset(struct net_device *dev)
9903{
9904 struct tg3 *tp = netdev_priv(dev);
1da177e4 9905 int r;
6aa20a22 9906
1da177e4
LT		 9907 if (!netif_running(dev))
9908 return -EAGAIN;
9909
c94e3941
MC		 9910 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9911 return -EINVAL;
9912
b02fd9e3
MC		 9913 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9914 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9915 return -EAGAIN;
3f0e3ad7 9916 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9917 } else {
9918 u32 bmcr;
9919
9920 spin_lock_bh(&tp->lock);
9921 r = -EINVAL;
9922 tg3_readphy(tp, MII_BMCR, &bmcr);
9923 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9924 ((bmcr & BMCR_ANENABLE) ||
9925 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9926 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9927 BMCR_ANENABLE);
9928 r = 0;
9929 }
9930 spin_unlock_bh(&tp->lock);
1da177e4 9931 }
6aa20a22 9932
1da177e4
LT		 9933 return r;
9934}
6aa20a22 9935
1da177e4
LT		 9936static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9937{
9938 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9939
1da177e4
LT		 9940 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9941 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9942 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9943 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9944 else
9945 ering->rx_jumbo_max_pending = 0;
9946
9947 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9948
9949 ering->rx_pending = tp->rx_pending;
9950 ering->rx_mini_pending = 0;
4f81c32b
MC		 9951 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9952 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9953 else
9954 ering->rx_jumbo_pending = 0;
9955
f3f3f27e 9956 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9957}
6aa20a22 9958
1da177e4
LT		 9959static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9960{
9961 struct tg3 *tp = netdev_priv(dev);
646c9edd 9962 int i, irq_sync = 0, err = 0;
6aa20a22 9963
1da177e4
LT		 9964 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9965 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9966 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9967 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9968 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9969 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9970 return -EINVAL;
6aa20a22 9971
bbe832c0 9972 if (netif_running(dev)) {
b02fd9e3 9973 tg3_phy_stop(tp);
1da177e4 9974 tg3_netif_stop(tp);
bbe832c0
MC		 9975 irq_sync = 1;
9976 }
1da177e4 9977
bbe832c0 9978 tg3_full_lock(tp, irq_sync);
6aa20a22 9979
1da177e4
LT		 9980 tp->rx_pending = ering->rx_pending;
9981
9982 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9983 tp->rx_pending > 63)
9984 tp->rx_pending = 63;
9985 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9986
9987 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9988 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9989
9990 if (netif_running(dev)) {
944d980e 9991 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9992 err = tg3_restart_hw(tp, 1);
9993 if (!err)
9994 tg3_netif_start(tp);
1da177e4
LT		 9995 }
9996
f47c11ee 9997 tg3_full_unlock(tp);
6aa20a22 9998
b02fd9e3
MC		 9999 if (irq_sync && !err)
10000 tg3_phy_start(tp);
10001
b9ec6c1b 10002 return err;
1da177e4 10003}
6aa20a22 10004
1da177e4
LT		 10005static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10006{
10007 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10008
1da177e4 10009 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 10010
e18ce346 10011 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 10012 epause->rx_pause = 1;
10013 else
10014 epause->rx_pause = 0;
10015
e18ce346 10016 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 10017 epause->tx_pause = 1;
10018 else
10019 epause->tx_pause = 0;
1da177e4 10020}
6aa20a22 10021
1da177e4
LT		 10022static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10023{
10024 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 10025 int err = 0;
6aa20a22 10026
b02fd9e3
MC		 10027 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10028 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10029 return -EAGAIN;
1da177e4 10030
b02fd9e3
MC		 10031 if (epause->autoneg) {
10032 u32 newadv;
10033 struct phy_device *phydev;
f47c11ee 10034
3f0e3ad7 10035 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 10036
b02fd9e3
MC		 10037 if (epause->rx_pause) {
10038 if (epause->tx_pause)
10039 newadv = ADVERTISED_Pause;
10040 else
10041 newadv = ADVERTISED_Pause |
10042 ADVERTISED_Asym_Pause;
10043 } else if (epause->tx_pause) {
10044 newadv = ADVERTISED_Asym_Pause;
10045 } else
10046 newadv = 0;
10047
10048 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10049 u32 oldadv = phydev->advertising &
10050 (ADVERTISED_Pause |
10051 ADVERTISED_Asym_Pause);
10052 if (oldadv != newadv) {
10053 phydev->advertising &=
10054 ~(ADVERTISED_Pause |
10055 ADVERTISED_Asym_Pause);
10056 phydev->advertising |= newadv;
10057 err = phy_start_aneg(phydev);
10058 }
10059 } else {
10060 tp->link_config.advertising &=
10061 ~(ADVERTISED_Pause |
10062 ADVERTISED_Asym_Pause);
10063 tp->link_config.advertising |= newadv;
10064 }
10065 } else {
10066 if (epause->rx_pause)
e18ce346 10067 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10068 else
e18ce346 10069 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 10070
b02fd9e3 10071 if (epause->tx_pause)
e18ce346 10072 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10073 else
e18ce346 10074 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10075
10076 if (netif_running(dev))
10077 tg3_setup_flow_control(tp, 0, 0);
10078 }
10079 } else {
10080 int irq_sync = 0;
10081
10082 if (netif_running(dev)) {
10083 tg3_netif_stop(tp);
10084 irq_sync = 1;
10085 }
10086
10087 tg3_full_lock(tp, irq_sync);
10088
10089 if (epause->autoneg)
10090 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10091 else
10092 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10093 if (epause->rx_pause)
e18ce346 10094 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10095 else
e18ce346 10096 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10097 if (epause->tx_pause)
e18ce346 10098 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10099 else
e18ce346 10100 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10101
10102 if (netif_running(dev)) {
10103 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10104 err = tg3_restart_hw(tp, 1);
10105 if (!err)
10106 tg3_netif_start(tp);
10107 }
10108
10109 tg3_full_unlock(tp);
10110 }
6aa20a22 10111
b9ec6c1b 10112 return err;
1da177e4 10113}
6aa20a22 10114
1da177e4
LT		 10115static u32 tg3_get_rx_csum(struct net_device *dev)
10116{
10117 struct tg3 *tp = netdev_priv(dev);
10118 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10119}
6aa20a22 10120
1da177e4
LT		 10121static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10122{
10123 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10124
1da177e4
LT		 10125 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10126 if (data != 0)
10127 return -EINVAL;
10128 return 0;
10129 }
6aa20a22 10130
f47c11ee 10131 spin_lock_bh(&tp->lock);
1da177e4
LT		 10132 if (data)
10133 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10134 else
10135 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10136 spin_unlock_bh(&tp->lock);
6aa20a22 10137
1da177e4
LT		 10138 return 0;
10139}
6aa20a22 10140
1da177e4
LT		 10141static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10142{
10143 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10144
1da177e4
LT		 10145 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10146 if (data != 0)
10147 return -EINVAL;
10148 return 0;
10149 }
6aa20a22 10150
321d32a0 10151 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10152 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10153 else
9c27dbdf 10154 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10155
10156 return 0;
10157}
10158
b9f2c044 10159static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10160{
b9f2c044
JG		 10161 switch (sset) {
10162 case ETH_SS_TEST:
10163 return TG3_NUM_TEST;
10164 case ETH_SS_STATS:
10165 return TG3_NUM_STATS;
10166 default:
10167 return -EOPNOTSUPP;
10168 }
4cafd3f5
MC		 10169}
10170
1da177e4
LT		 10171static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10172{
10173 switch (stringset) {
10174 case ETH_SS_STATS:
10175 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10176 break;
4cafd3f5
MC		 10177 case ETH_SS_TEST:
10178 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10179 break;
1da177e4
LT		 10180 default:
10181 WARN_ON(1); /* we need a WARN() */
10182 break;
10183 }
10184}
10185
4009a93d
MC		 10186static int tg3_phys_id(struct net_device *dev, u32 data)
10187{
10188 struct tg3 *tp = netdev_priv(dev);
10189 int i;
10190
10191 if (!netif_running(tp->dev))
10192 return -EAGAIN;
10193
10194 if (data == 0)
759afc31 10195 data = UINT_MAX / 2;
4009a93d
MC		 10196
10197 for (i = 0; i < (data * 2); i++) {
10198 if ((i % 2) == 0)
10199 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10200 LED_CTRL_1000MBPS_ON |
10201 LED_CTRL_100MBPS_ON |
10202 LED_CTRL_10MBPS_ON |
10203 LED_CTRL_TRAFFIC_OVERRIDE |
10204 LED_CTRL_TRAFFIC_BLINK |
10205 LED_CTRL_TRAFFIC_LED);
6aa20a22 10206
4009a93d
MC		 10207 else
10208 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10209 LED_CTRL_TRAFFIC_OVERRIDE);
10210
10211 if (msleep_interruptible(500))
10212 break;
10213 }
10214 tw32(MAC_LED_CTRL, tp->led_ctrl);
10215 return 0;
10216}
10217
1da177e4
LT		 10218static void tg3_get_ethtool_stats (struct net_device *dev,
10219 struct ethtool_stats *estats, u64 *tmp_stats)
10220{
10221 struct tg3 *tp = netdev_priv(dev);
10222 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10223}
10224
566f86ad 10225#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10226#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10227#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10228#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10229#define NVRAM_SELFBOOT_HW_SIZE 0x20
10230#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10231
10232static int tg3_test_nvram(struct tg3 *tp)
10233{
b9fc7dc5 10234 u32 csum, magic;
a9dc529d 10235 __be32 *buf;
ab0049b4 10236 int i, j, k, err = 0, size;
566f86ad 10237
df259d8c
MC		 10238 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10239 return 0;
10240
e4f34110 10241 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10242 return -EIO;
10243
1b27777a
MC		 10244 if (magic == TG3_EEPROM_MAGIC)
10245 size = NVRAM_TEST_SIZE;
b16250e3 10246 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10247 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10248 TG3_EEPROM_SB_FORMAT_1) {
10249 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10250 case TG3_EEPROM_SB_REVISION_0:
10251 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10252 break;
10253 case TG3_EEPROM_SB_REVISION_2:
10254 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10255 break;
10256 case TG3_EEPROM_SB_REVISION_3:
10257 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10258 break;
10259 default:
10260 return 0;
10261 }
10262 } else
1b27777a 10263 return 0;
b16250e3
MC		 10264 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10265 size = NVRAM_SELFBOOT_HW_SIZE;
10266 else
1b27777a
MC		 10267 return -EIO;
10268
10269 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10270 if (buf == NULL)
10271 return -ENOMEM;
10272
1b27777a
MC		 10273 err = -EIO;
10274 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10275 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10276 if (err)
566f86ad 10277 break;
566f86ad 10278 }
1b27777a 10279 if (i < size)
566f86ad
MC		 10280 goto out;
10281
1b27777a 10282 /* Selfboot format */
a9dc529d 10283 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10284 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10285 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10286 u8 *buf8 = (u8 *) buf, csum8 = 0;
10287
b9fc7dc5 10288 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10289 TG3_EEPROM_SB_REVISION_2) {
10290 /* For rev 2, the csum doesn't include the MBA. */
10291 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10292 csum8 += buf8[i];
10293 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10294 csum8 += buf8[i];
10295 } else {
10296 for (i = 0; i < size; i++)
10297 csum8 += buf8[i];
10298 }
1b27777a 10299
ad96b485
AB		 10300 if (csum8 == 0) {
10301 err = 0;
10302 goto out;
10303 }
10304
10305 err = -EIO;
10306 goto out;
1b27777a 10307 }
566f86ad 10308
b9fc7dc5 10309 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10310 TG3_EEPROM_MAGIC_HW) {
10311 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10312 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10313 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10314
10315 /* Separate the parity bits and the data bytes. */
10316 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10317 if ((i == 0) || (i == 8)) {
10318 int l;
10319 u8 msk;
10320
10321 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10322 parity[k++] = buf8[i] & msk;
10323 i++;
10324 }
10325 else if (i == 16) {
10326 int l;
10327 u8 msk;
10328
10329 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10330 parity[k++] = buf8[i] & msk;
10331 i++;
10332
10333 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10334 parity[k++] = buf8[i] & msk;
10335 i++;
10336 }
10337 data[j++] = buf8[i];
10338 }
10339
10340 err = -EIO;
10341 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10342 u8 hw8 = hweight8(data[i]);
10343
10344 if ((hw8 & 0x1) && parity[i])
10345 goto out;
10346 else if (!(hw8 & 0x1) && !parity[i])
10347 goto out;
10348 }
10349 err = 0;
10350 goto out;
10351 }
10352
566f86ad
MC		 10353 /* Bootstrap checksum at offset 0x10 */
10354 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10355 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10356 goto out;
10357
10358 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10359 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10360 if (csum != be32_to_cpu(buf[0xfc/4]))
10361 goto out;
566f86ad
MC		 10362
10363 err = 0;
10364
10365out:
10366 kfree(buf);
10367 return err;
10368}
10369
ca43007a
MC		 10370#define TG3_SERDES_TIMEOUT_SEC 2
10371#define TG3_COPPER_TIMEOUT_SEC 6
10372
10373static int tg3_test_link(struct tg3 *tp)
10374{
10375 int i, max;
10376
10377 if (!netif_running(tp->dev))
10378 return -ENODEV;
10379
4c987487 10380 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10381 max = TG3_SERDES_TIMEOUT_SEC;
10382 else
10383 max = TG3_COPPER_TIMEOUT_SEC;
10384
10385 for (i = 0; i < max; i++) {
10386 if (netif_carrier_ok(tp->dev))
10387 return 0;
10388
10389 if (msleep_interruptible(1000))
10390 break;
10391 }
10392
10393 return -EIO;
10394}
10395
a71116d1 10396/* Only test the commonly used registers */
30ca3e37 10397static int tg3_test_registers(struct tg3 *tp)
a71116d1 10398{
b16250e3 10399 int i, is_5705, is_5750;
a71116d1
MC		 10400 u32 offset, read_mask, write_mask, val, save_val, read_val;
10401 static struct {
10402 u16 offset;
10403 u16 flags;
10404#define TG3_FL_5705 0x1
10405#define TG3_FL_NOT_5705 0x2
10406#define TG3_FL_NOT_5788 0x4
b16250e3 10407#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10408 u32 read_mask;
10409 u32 write_mask;
10410 } reg_tbl[] = {
10411 /* MAC Control Registers */
10412 { MAC_MODE, TG3_FL_NOT_5705,
10413 0x00000000, 0x00ef6f8c },
10414 { MAC_MODE, TG3_FL_5705,
10415 0x00000000, 0x01ef6b8c },
10416 { MAC_STATUS, TG3_FL_NOT_5705,
10417 0x03800107, 0x00000000 },
10418 { MAC_STATUS, TG3_FL_5705,
10419 0x03800100, 0x00000000 },
10420 { MAC_ADDR_0_HIGH, 0x0000,
10421 0x00000000, 0x0000ffff },
10422 { MAC_ADDR_0_LOW, 0x0000,
10423 0x00000000, 0xffffffff },
10424 { MAC_RX_MTU_SIZE, 0x0000,
10425 0x00000000, 0x0000ffff },
10426 { MAC_TX_MODE, 0x0000,
10427 0x00000000, 0x00000070 },
10428 { MAC_TX_LENGTHS, 0x0000,
10429 0x00000000, 0x00003fff },
10430 { MAC_RX_MODE, TG3_FL_NOT_5705,
10431 0x00000000, 0x000007fc },
10432 { MAC_RX_MODE, TG3_FL_5705,
10433 0x00000000, 0x000007dc },
10434 { MAC_HASH_REG_0, 0x0000,
10435 0x00000000, 0xffffffff },
10436 { MAC_HASH_REG_1, 0x0000,
10437 0x00000000, 0xffffffff },
10438 { MAC_HASH_REG_2, 0x0000,
10439 0x00000000, 0xffffffff },
10440 { MAC_HASH_REG_3, 0x0000,
10441 0x00000000, 0xffffffff },
10442
10443 /* Receive Data and Receive BD Initiator Control Registers. */
10444 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10445 0x00000000, 0xffffffff },
10446 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10447 0x00000000, 0xffffffff },
10448 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10449 0x00000000, 0x00000003 },
10450 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10451 0x00000000, 0xffffffff },
10452 { RCVDBDI_STD_BD+0, 0x0000,
10453 0x00000000, 0xffffffff },
10454 { RCVDBDI_STD_BD+4, 0x0000,
10455 0x00000000, 0xffffffff },
10456 { RCVDBDI_STD_BD+8, 0x0000,
10457 0x00000000, 0xffff0002 },
10458 { RCVDBDI_STD_BD+0xc, 0x0000,
10459 0x00000000, 0xffffffff },
6aa20a22 10460
a71116d1
MC		 10461 /* Receive BD Initiator Control Registers. */
10462 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10463 0x00000000, 0xffffffff },
10464 { RCVBDI_STD_THRESH, TG3_FL_5705,
10465 0x00000000, 0x000003ff },
10466 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10467 0x00000000, 0xffffffff },
6aa20a22 10468
a71116d1
MC		 10469 /* Host Coalescing Control Registers. */
10470 { HOSTCC_MODE, TG3_FL_NOT_5705,
10471 0x00000000, 0x00000004 },
10472 { HOSTCC_MODE, TG3_FL_5705,
10473 0x00000000, 0x000000f6 },
10474 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10475 0x00000000, 0xffffffff },
10476 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10477 0x00000000, 0x000003ff },
10478 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10479 0x00000000, 0xffffffff },
10480 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10481 0x00000000, 0x000003ff },
10482 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10483 0x00000000, 0xffffffff },
10484 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10485 0x00000000, 0x000000ff },
10486 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10487 0x00000000, 0xffffffff },
10488 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10489 0x00000000, 0x000000ff },
10490 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10491 0x00000000, 0xffffffff },
10492 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10493 0x00000000, 0xffffffff },
10494 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10495 0x00000000, 0xffffffff },
10496 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10497 0x00000000, 0x000000ff },
10498 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10499 0x00000000, 0xffffffff },
10500 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10501 0x00000000, 0x000000ff },
10502 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10503 0x00000000, 0xffffffff },
10504 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10505 0x00000000, 0xffffffff },
10506 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10507 0x00000000, 0xffffffff },
10508 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10509 0x00000000, 0xffffffff },
10510 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10511 0x00000000, 0xffffffff },
10512 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10513 0xffffffff, 0x00000000 },
10514 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10515 0xffffffff, 0x00000000 },
10516
10517 /* Buffer Manager Control Registers. */
b16250e3 10518 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10519 0x00000000, 0x007fff80 },
b16250e3 10520 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10521 0x00000000, 0x007fffff },
10522 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10523 0x00000000, 0x0000003f },
10524 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10525 0x00000000, 0x000001ff },
10526 { BUFMGR_MB_HIGH_WATER, 0x0000,
10527 0x00000000, 0x000001ff },
10528 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10529 0xffffffff, 0x00000000 },
10530 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10531 0xffffffff, 0x00000000 },
6aa20a22 10532
a71116d1
MC		 10533 /* Mailbox Registers */
10534 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10535 0x00000000, 0x000001ff },
10536 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10537 0x00000000, 0x000001ff },
10538 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10539 0x00000000, 0x000007ff },
10540 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10541 0x00000000, 0x000001ff },
10542
10543 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10544 };
10545
b16250e3
MC		 10546 is_5705 = is_5750 = 0;
10547 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10548 is_5705 = 1;
b16250e3
MC		 10549 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10550 is_5750 = 1;
10551 }
a71116d1
MC		 10552
10553 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10554 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10555 continue;
10556
10557 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10558 continue;
10559
10560 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10561 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10562 continue;
10563
b16250e3
MC		 10564 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10565 continue;
10566
a71116d1
MC		 10567 offset = (u32) reg_tbl[i].offset;
10568 read_mask = reg_tbl[i].read_mask;
10569 write_mask = reg_tbl[i].write_mask;
10570
10571 /* Save the original register content */
10572 save_val = tr32(offset);
10573
10574 /* Determine the read-only value. */
10575 read_val = save_val & read_mask;
10576
10577 /* Write zero to the register, then make sure the read-only bits
10578 * are not changed and the read/write bits are all zeros.
10579 */
10580 tw32(offset, 0);
10581
10582 val = tr32(offset);
10583
10584 /* Test the read-only and read/write bits. */
10585 if (((val & read_mask) != read_val) || (val & write_mask))
10586 goto out;
10587
10588 /* Write ones to all the bits defined by RdMask and WrMask, then
10589 * make sure the read-only bits are not changed and the
10590 * read/write bits are all ones.
10591 */
10592 tw32(offset, read_mask | write_mask);
10593
10594 val = tr32(offset);
10595
10596 /* Test the read-only bits. */
10597 if ((val & read_mask) != read_val)
10598 goto out;
10599
10600 /* Test the read/write bits. */
10601 if ((val & write_mask) != write_mask)
10602 goto out;
10603
10604 tw32(offset, save_val);
10605 }
10606
10607 return 0;
10608
10609out:
9f88f29f
MC		 10610 if (netif_msg_hw(tp))
10611 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10612 offset);
a71116d1
MC		 10613 tw32(offset, save_val);
10614 return -EIO;
10615}
10616
7942e1db
MC		 10617static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10618{
f71e1309 10619 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10620 int i;
10621 u32 j;
10622
e9edda69 10623 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10624 for (j = 0; j < len; j += 4) {
10625 u32 val;
10626
10627 tg3_write_mem(tp, offset + j, test_pattern[i]);
10628 tg3_read_mem(tp, offset + j, &val);
10629 if (val != test_pattern[i])
10630 return -EIO;
10631 }
10632 }
10633 return 0;
10634}
10635
10636static int tg3_test_memory(struct tg3 *tp)
10637{
10638 static struct mem_entry {
10639 u32 offset;
10640 u32 len;
10641 } mem_tbl_570x[] = {
38690194 10642 { 0x00000000, 0x00b50},
7942e1db
MC		 10643 { 0x00002000, 0x1c000},
10644 { 0xffffffff, 0x00000}
10645 }, mem_tbl_5705[] = {
10646 { 0x00000100, 0x0000c},
10647 { 0x00000200, 0x00008},
7942e1db
MC		 10648 { 0x00004000, 0x00800},
10649 { 0x00006000, 0x01000},
10650 { 0x00008000, 0x02000},
10651 { 0x00010000, 0x0e000},
10652 { 0xffffffff, 0x00000}
79f4d13a
MC		 10653 }, mem_tbl_5755[] = {
10654 { 0x00000200, 0x00008},
10655 { 0x00004000, 0x00800},
10656 { 0x00006000, 0x00800},
10657 { 0x00008000, 0x02000},
10658 { 0x00010000, 0x0c000},
10659 { 0xffffffff, 0x00000}
b16250e3
MC		 10660 }, mem_tbl_5906[] = {
10661 { 0x00000200, 0x00008},
10662 { 0x00004000, 0x00400},
10663 { 0x00006000, 0x00400},
10664 { 0x00008000, 0x01000},
10665 { 0x00010000, 0x01000},
10666 { 0xffffffff, 0x00000}
8b5a6c42
MC		 10667 }, mem_tbl_5717[] = {
10668 { 0x00000200, 0x00008},
10669 { 0x00010000, 0x0a000},
10670 { 0x00020000, 0x13c00},
10671 { 0xffffffff, 0x00000}
10672 }, mem_tbl_57765[] = {
10673 { 0x00000200, 0x00008},
10674 { 0x00004000, 0x00800},
10675 { 0x00006000, 0x09800},
10676 { 0x00010000, 0x0a000},
10677 { 0xffffffff, 0x00000}
7942e1db
MC		 10678 };
10679 struct mem_entry *mem_tbl;
10680 int err = 0;
10681 int i;
10682
8b5a6c42
MC		 10683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10684 mem_tbl = mem_tbl_5717;
10685 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10686 mem_tbl = mem_tbl_57765;
10687 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
321d32a0
MC		 10688 mem_tbl = mem_tbl_5755;
10689 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10690 mem_tbl = mem_tbl_5906;
10691 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10692 mem_tbl = mem_tbl_5705;
10693 else
7942e1db
MC		 10694 mem_tbl = mem_tbl_570x;
10695
10696 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10697 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10698 mem_tbl[i].len)) != 0)
10699 break;
10700 }
6aa20a22 10701
7942e1db
MC		 10702 return err;
10703}
10704
9f40dead
MC		 10705#define TG3_MAC_LOOPBACK 0
10706#define TG3_PHY_LOOPBACK 1
10707
10708static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10709{
9f40dead 10710 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10711 u32 desc_idx, coal_now;
c76949a6
MC		 10712 struct sk_buff *skb, *rx_skb;
10713 u8 *tx_data;
10714 dma_addr_t map;
10715 int num_pkts, tx_len, rx_len, i, err;
10716 struct tg3_rx_buffer_desc *desc;
898a56f8 10717 struct tg3_napi *tnapi, *rnapi;
21f581a5 10718 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10719
0c1d0e2b
MC		 10720 if (tp->irq_cnt > 1) {
10721 tnapi = &tp->napi[1];
10722 rnapi = &tp->napi[1];
10723 } else {
10724 tnapi = &tp->napi[0];
10725 rnapi = &tp->napi[0];
10726 }
fd2ce37f 10727 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10728
9f40dead 10729 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10730 /* HW errata - mac loopback fails in some cases on 5780.
10731 * Normal traffic and PHY loopback are not affected by
10732 * errata.
10733 */
10734 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10735 return 0;
10736
9f40dead 10737 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10738 MAC_MODE_PORT_INT_LPBACK;
10739 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10740 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10741 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10742 mac_mode |= MAC_MODE_PORT_MODE_MII;
10743 else
10744 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10745 tw32(MAC_MODE, mac_mode);
10746 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10747 u32 val;
10748
7f97a4bd
MC		 10749 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10750 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10751 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10752 } else
10753 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10754
9ef8ca99
MC		 10755 tg3_phy_toggle_automdix(tp, 0);
10756
3f7045c1 10757 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10758 udelay(40);
5d64ad34 10759
e8f3f6ca 10760 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10761 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10762 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10763 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10764 mac_mode |= MAC_MODE_PORT_MODE_MII;
10765 } else
10766 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10767
c94e3941
MC		 10768 /* reset to prevent losing 1st rx packet intermittently */
10769 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10770 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10771 udelay(10);
10772 tw32_f(MAC_RX_MODE, tp->rx_mode);
10773 }
e8f3f6ca
MC		 10774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10775 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10776 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10777 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10778 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10779 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10780 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10781 }
9f40dead 10782 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10783 }
10784 else
10785 return -EINVAL;
c76949a6
MC		 10786
10787 err = -EIO;
10788
c76949a6 10789 tx_len = 1514;
a20e9c62 10790 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10791 if (!skb)
10792 return -ENOMEM;
10793
c76949a6
MC		 10794 tx_data = skb_put(skb, tx_len);
10795 memcpy(tx_data, tp->dev->dev_addr, 6);
10796 memset(tx_data + 6, 0x0, 8);
10797
10798 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10799
10800 for (i = 14; i < tx_len; i++)
10801 tx_data[i] = (u8) (i & 0xff);
10802
f4188d8a
AD		 10803 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10804 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10805 dev_kfree_skb(skb);
10806 return -EIO;
10807 }
c76949a6
MC		 10808
10809 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10810 rnapi->coal_now);
c76949a6
MC		 10811
10812 udelay(10);
10813
898a56f8 10814 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10815
c76949a6
MC		 10816 num_pkts = 0;
10817
f4188d8a 10818 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10819
f3f3f27e 10820 tnapi->tx_prod++;
c76949a6
MC		 10821 num_pkts++;
10822
f3f3f27e
MC		 10823 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10824 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10825
10826 udelay(10);
10827
303fc921
MC		 10828 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10829 for (i = 0; i < 35; i++) {
c76949a6 10830 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10831 coal_now);
c76949a6
MC		 10832
10833 udelay(10);
10834
898a56f8
MC		 10835 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10836 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10837 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10838 (rx_idx == (rx_start_idx + num_pkts)))
10839 break;
10840 }
10841
f4188d8a 10842 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10843 dev_kfree_skb(skb);
10844
f3f3f27e 10845 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10846 goto out;
10847
10848 if (rx_idx != rx_start_idx + num_pkts)
10849 goto out;
10850
72334482 10851 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10852 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10853 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10854 if (opaque_key != RXD_OPAQUE_RING_STD)
10855 goto out;
10856
10857 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10858 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10859 goto out;
10860
10861 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10862 if (rx_len != tx_len)
10863 goto out;
10864
21f581a5 10865 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10866
21f581a5 10867 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10868 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10869
10870 for (i = 14; i < tx_len; i++) {
10871 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10872 goto out;
10873 }
10874 err = 0;
6aa20a22 10875
c76949a6
MC		 10876 /* tg3_free_rings will unmap and free the rx_skb */
10877out:
10878 return err;
10879}
10880
9f40dead
MC		 10881#define TG3_MAC_LOOPBACK_FAILED 1
10882#define TG3_PHY_LOOPBACK_FAILED 2
10883#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10884 TG3_PHY_LOOPBACK_FAILED)
10885
10886static int tg3_test_loopback(struct tg3 *tp)
10887{
10888 int err = 0;
9936bcf6 10889 u32 cpmuctrl = 0;
9f40dead
MC		 10890
10891 if (!netif_running(tp->dev))
10892 return TG3_LOOPBACK_FAILED;
10893
b9ec6c1b
MC		 10894 err = tg3_reset_hw(tp, 1);
10895 if (err)
10896 return TG3_LOOPBACK_FAILED;
9f40dead 10897
6833c043
MC		 10898 /* Turn off gphy autopowerdown. */
10899 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10900 tg3_phy_toggle_apd(tp, false);
10901
321d32a0 10902 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10903 int i;
10904 u32 status;
10905
10906 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10907
10908 /* Wait for up to 40 microseconds to acquire lock. */
10909 for (i = 0; i < 4; i++) {
10910 status = tr32(TG3_CPMU_MUTEX_GNT);
10911 if (status == CPMU_MUTEX_GNT_DRIVER)
10912 break;
10913 udelay(10);
10914 }
10915
10916 if (status != CPMU_MUTEX_GNT_DRIVER)
10917 return TG3_LOOPBACK_FAILED;
10918
b2a5c19c 10919 /* Turn off link-based power management. */
e875093c 10920 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10921 tw32(TG3_CPMU_CTRL,
10922 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10923 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10924 }
10925
9f40dead
MC		 10926 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10927 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10928
321d32a0 10929 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10930 tw32(TG3_CPMU_CTRL, cpmuctrl);
10931
10932 /* Release the mutex */
10933 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10934 }
10935
dd477003
MC		 10936 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10937 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10938 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10939 err |= TG3_PHY_LOOPBACK_FAILED;
10940 }
10941
6833c043
MC		 10942 /* Re-enable gphy autopowerdown. */
10943 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10944 tg3_phy_toggle_apd(tp, true);
10945
9f40dead
MC		 10946 return err;
10947}
10948
4cafd3f5
MC		 10949static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10950 u64 *data)
10951{
566f86ad
MC		 10952 struct tg3 *tp = netdev_priv(dev);
10953
bc1c7567
MC		 10954 if (tp->link_config.phy_is_low_power)
10955 tg3_set_power_state(tp, PCI_D0);
10956
566f86ad
MC		 10957 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10958
10959 if (tg3_test_nvram(tp) != 0) {
10960 etest->flags |= ETH_TEST_FL_FAILED;
10961 data[0] = 1;
10962 }
ca43007a
MC		 10963 if (tg3_test_link(tp) != 0) {
10964 etest->flags |= ETH_TEST_FL_FAILED;
10965 data[1] = 1;
10966 }
a71116d1 10967 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10968 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10969
10970 if (netif_running(dev)) {
b02fd9e3 10971 tg3_phy_stop(tp);
a71116d1 10972 tg3_netif_stop(tp);
bbe832c0
MC		 10973 irq_sync = 1;
10974 }
a71116d1 10975
bbe832c0 10976 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10977
10978 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10979 err = tg3_nvram_lock(tp);
a71116d1
MC		 10980 tg3_halt_cpu(tp, RX_CPU_BASE);
10981 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10982 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10983 if (!err)
10984 tg3_nvram_unlock(tp);
a71116d1 10985
d9ab5ad1
MC		 10986 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10987 tg3_phy_reset(tp);
10988
a71116d1
MC		 10989 if (tg3_test_registers(tp) != 0) {
10990 etest->flags |= ETH_TEST_FL_FAILED;
10991 data[2] = 1;
10992 }
7942e1db
MC		 10993 if (tg3_test_memory(tp) != 0) {
10994 etest->flags |= ETH_TEST_FL_FAILED;
10995 data[3] = 1;
10996 }
9f40dead 10997 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10998 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10999
f47c11ee
DM		 11000 tg3_full_unlock(tp);
11001
d4bc3927
MC		 11002 if (tg3_test_interrupt(tp) != 0) {
11003 etest->flags |= ETH_TEST_FL_FAILED;
11004 data[5] = 1;
11005 }
f47c11ee
DM		 11006
11007 tg3_full_lock(tp, 0);
d4bc3927 11008
a71116d1
MC		 11009 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11010 if (netif_running(dev)) {
11011 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 11012 err2 = tg3_restart_hw(tp, 1);
11013 if (!err2)
b9ec6c1b 11014 tg3_netif_start(tp);
a71116d1 11015 }
f47c11ee
DM		 11016
11017 tg3_full_unlock(tp);
b02fd9e3
MC		 11018
11019 if (irq_sync && !err2)
11020 tg3_phy_start(tp);
a71116d1 11021 }
bc1c7567
MC		 11022 if (tp->link_config.phy_is_low_power)
11023 tg3_set_power_state(tp, PCI_D3hot);
11024
4cafd3f5
MC		 11025}
11026
1da177e4
LT		 11027static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11028{
11029 struct mii_ioctl_data *data = if_mii(ifr);
11030 struct tg3 *tp = netdev_priv(dev);
11031 int err;
11032
b02fd9e3 11033 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 11034 struct phy_device *phydev;
b02fd9e3
MC		 11035 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11036 return -EAGAIN;
3f0e3ad7
MC		 11037 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11038 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 11039 }
11040
1da177e4
LT		 11041 switch(cmd) {
11042 case SIOCGMIIPHY:
882e9793 11043 data->phy_id = tp->phy_addr;
1da177e4
LT		 11044
11045 /* fallthru */
11046 case SIOCGMIIREG: {
11047 u32 mii_regval;
11048
11049 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11050 break; /* We have no PHY */
11051
bc1c7567
MC		 11052 if (tp->link_config.phy_is_low_power)
11053 return -EAGAIN;
11054
f47c11ee 11055 spin_lock_bh(&tp->lock);
1da177e4 11056 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 11057 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11058
11059 data->val_out = mii_regval;
11060
11061 return err;
11062 }
11063
11064 case SIOCSMIIREG:
11065 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11066 break; /* We have no PHY */
11067
bc1c7567
MC		 11068 if (tp->link_config.phy_is_low_power)
11069 return -EAGAIN;
11070
f47c11ee 11071 spin_lock_bh(&tp->lock);
1da177e4 11072 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 11073 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11074
11075 return err;
11076
11077 default:
11078 /* do nothing */
11079 break;
11080 }
11081 return -EOPNOTSUPP;
11082}
11083
11084#if TG3_VLAN_TAG_USED
11085static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11086{
11087 struct tg3 *tp = netdev_priv(dev);
11088
844b3eed
MC		 11089 if (!netif_running(dev)) {
11090 tp->vlgrp = grp;
11091 return;
11092 }
11093
11094 tg3_netif_stop(tp);
29315e87 11095
f47c11ee 11096 tg3_full_lock(tp, 0);
1da177e4
LT		 11097
11098 tp->vlgrp = grp;
11099
11100 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11101 __tg3_set_rx_mode(dev);
11102
844b3eed 11103 tg3_netif_start(tp);
46966545
MC		 11104
11105 tg3_full_unlock(tp);
1da177e4 11106}
1da177e4
LT		 11107#endif
11108
15f9850d
DM		 11109static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11110{
11111 struct tg3 *tp = netdev_priv(dev);
11112
11113 memcpy(ec, &tp->coal, sizeof(*ec));
11114 return 0;
11115}
11116
d244c892
MC		 11117static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11118{
11119 struct tg3 *tp = netdev_priv(dev);
11120 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11121 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11122
11123 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11124 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11125 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11126 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11127 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11128 }
11129
11130 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11131 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11132 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11133 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11134 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11135 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11136 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11137 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11138 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11139 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11140 return -EINVAL;
11141
11142 /* No rx interrupts will be generated if both are zero */
11143 if ((ec->rx_coalesce_usecs == 0) &&
11144 (ec->rx_max_coalesced_frames == 0))
11145 return -EINVAL;
11146
11147 /* No tx interrupts will be generated if both are zero */
11148 if ((ec->tx_coalesce_usecs == 0) &&
11149 (ec->tx_max_coalesced_frames == 0))
11150 return -EINVAL;
11151
11152 /* Only copy relevant parameters, ignore all others. */
11153 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11154 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11155 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11156 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11157 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11158 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11159 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11160 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11161 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11162
11163 if (netif_running(dev)) {
11164 tg3_full_lock(tp, 0);
11165 __tg3_set_coalesce(tp, &tp->coal);
11166 tg3_full_unlock(tp);
11167 }
11168 return 0;
11169}
11170
7282d491 11171static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11172 .get_settings = tg3_get_settings,
11173 .set_settings = tg3_set_settings,
11174 .get_drvinfo = tg3_get_drvinfo,
11175 .get_regs_len = tg3_get_regs_len,
11176 .get_regs = tg3_get_regs,
11177 .get_wol = tg3_get_wol,
11178 .set_wol = tg3_set_wol,
11179 .get_msglevel = tg3_get_msglevel,
11180 .set_msglevel = tg3_set_msglevel,
11181 .nway_reset = tg3_nway_reset,
11182 .get_link = ethtool_op_get_link,
11183 .get_eeprom_len = tg3_get_eeprom_len,
11184 .get_eeprom = tg3_get_eeprom,
11185 .set_eeprom = tg3_set_eeprom,
11186 .get_ringparam = tg3_get_ringparam,
11187 .set_ringparam = tg3_set_ringparam,
11188 .get_pauseparam = tg3_get_pauseparam,
11189 .set_pauseparam = tg3_set_pauseparam,
11190 .get_rx_csum = tg3_get_rx_csum,
11191 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11192 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11193 .set_sg = ethtool_op_set_sg,
1da177e4 11194 .set_tso = tg3_set_tso,
4cafd3f5 11195 .self_test = tg3_self_test,
1da177e4 11196 .get_strings = tg3_get_strings,
4009a93d 11197 .phys_id = tg3_phys_id,
1da177e4 11198 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11199 .get_coalesce = tg3_get_coalesce,
d244c892 11200 .set_coalesce = tg3_set_coalesce,
b9f2c044 11201 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11202};
11203
11204static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11205{
1b27777a 11206 u32 cursize, val, magic;
1da177e4
LT		 11207
11208 tp->nvram_size = EEPROM_CHIP_SIZE;
11209
e4f34110 11210 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11211 return;
11212
b16250e3
MC		 11213 if ((magic != TG3_EEPROM_MAGIC) &&
11214 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11215 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11216 return;
11217
11218 /*
11219 * Size the chip by reading offsets at increasing powers of two.
11220 * When we encounter our validation signature, we know the addressing
11221 * has wrapped around, and thus have our chip size.
11222 */
1b27777a 11223 cursize = 0x10;
1da177e4
LT		 11224
11225 while (cursize < tp->nvram_size) {
e4f34110 11226 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11227 return;
11228
1820180b 11229 if (val == magic)
1da177e4
LT		 11230 break;
11231
11232 cursize <<= 1;
11233 }
11234
11235 tp->nvram_size = cursize;
11236}
6aa20a22 11237
1da177e4
LT		 11238static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11239{
11240 u32 val;
11241
df259d8c
MC		 11242 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11243 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11244 return;
11245
11246 /* Selfboot format */
1820180b 11247 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11248 tg3_get_eeprom_size(tp);
11249 return;
11250 }
11251
6d348f2c 11252 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11253 if (val != 0) {
6d348f2c
MC		 11254 /* This is confusing. We want to operate on the
11255 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11256 * call will read from NVRAM and byteswap the data
11257 * according to the byteswapping settings for all
11258 * other register accesses. This ensures the data we
11259 * want will always reside in the lower 16-bits.
11260 * However, the data in NVRAM is in LE format, which
11261 * means the data from the NVRAM read will always be
11262 * opposite the endianness of the CPU. The 16-bit
11263 * byteswap then brings the data to CPU endianness.
11264 */
11265 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11266 return;
11267 }
11268 }
fd1122a2 11269 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11270}
11271
11272static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11273{
11274 u32 nvcfg1;
11275
11276 nvcfg1 = tr32(NVRAM_CFG1);
11277 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11278 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11279 } else {
1da177e4
LT		 11280 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11281 tw32(NVRAM_CFG1, nvcfg1);
11282 }
11283
4c987487 11284 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11285 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11286 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11287 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11288 tp->nvram_jedecnum = JEDEC_ATMEL;
11289 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11290 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11291 break;
11292 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11293 tp->nvram_jedecnum = JEDEC_ATMEL;
11294 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11295 break;
11296 case FLASH_VENDOR_ATMEL_EEPROM:
11297 tp->nvram_jedecnum = JEDEC_ATMEL;
11298 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11299 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11300 break;
11301 case FLASH_VENDOR_ST:
11302 tp->nvram_jedecnum = JEDEC_ST;
11303 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11304 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11305 break;
11306 case FLASH_VENDOR_SAIFUN:
11307 tp->nvram_jedecnum = JEDEC_SAIFUN;
11308 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11309 break;
11310 case FLASH_VENDOR_SST_SMALL:
11311 case FLASH_VENDOR_SST_LARGE:
11312 tp->nvram_jedecnum = JEDEC_SST;
11313 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11314 break;
1da177e4 11315 }
8590a603 11316 } else {
1da177e4
LT		 11317 tp->nvram_jedecnum = JEDEC_ATMEL;
11318 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11319 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11320 }
11321}
11322
a1b950d5
MC		 11323static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11324{
11325 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11326 case FLASH_5752PAGE_SIZE_256:
11327 tp->nvram_pagesize = 256;
11328 break;
11329 case FLASH_5752PAGE_SIZE_512:
11330 tp->nvram_pagesize = 512;
11331 break;
11332 case FLASH_5752PAGE_SIZE_1K:
11333 tp->nvram_pagesize = 1024;
11334 break;
11335 case FLASH_5752PAGE_SIZE_2K:
11336 tp->nvram_pagesize = 2048;
11337 break;
11338 case FLASH_5752PAGE_SIZE_4K:
11339 tp->nvram_pagesize = 4096;
11340 break;
11341 case FLASH_5752PAGE_SIZE_264:
11342 tp->nvram_pagesize = 264;
11343 break;
11344 case FLASH_5752PAGE_SIZE_528:
11345 tp->nvram_pagesize = 528;
11346 break;
11347 }
11348}
11349
361b4ac2
MC		 11350static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11351{
11352 u32 nvcfg1;
11353
11354 nvcfg1 = tr32(NVRAM_CFG1);
11355
e6af301b
MC		 11356 /* NVRAM protection for TPM */
11357 if (nvcfg1 & (1 << 27))
f66a29b0 11358 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11359
361b4ac2 11360 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11361 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11362 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11363 tp->nvram_jedecnum = JEDEC_ATMEL;
11364 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11365 break;
11366 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11367 tp->nvram_jedecnum = JEDEC_ATMEL;
11368 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11369 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11370 break;
11371 case FLASH_5752VENDOR_ST_M45PE10:
11372 case FLASH_5752VENDOR_ST_M45PE20:
11373 case FLASH_5752VENDOR_ST_M45PE40:
11374 tp->nvram_jedecnum = JEDEC_ST;
11375 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11376 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11377 break;
361b4ac2
MC		 11378 }
11379
11380 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11381 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11382 } else {
361b4ac2
MC		 11383 /* For eeprom, set pagesize to maximum eeprom size */
11384 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11385
11386 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11387 tw32(NVRAM_CFG1, nvcfg1);
11388 }
11389}
11390
d3c7b886
MC		 11391static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11392{
989a9d23 11393 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11394
11395 nvcfg1 = tr32(NVRAM_CFG1);
11396
11397 /* NVRAM protection for TPM */
989a9d23 11398 if (nvcfg1 & (1 << 27)) {
f66a29b0 11399 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11400 protect = 1;
11401 }
d3c7b886 11402
989a9d23
MC		 11403 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11404 switch (nvcfg1) {
8590a603
MC		 11405 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11406 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11407 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11408 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11409 tp->nvram_jedecnum = JEDEC_ATMEL;
11410 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11411 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11412 tp->nvram_pagesize = 264;
11413 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11414 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11415 tp->nvram_size = (protect ? 0x3e200 :
11416 TG3_NVRAM_SIZE_512KB);
11417 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11418 tp->nvram_size = (protect ? 0x1f200 :
11419 TG3_NVRAM_SIZE_256KB);
11420 else
11421 tp->nvram_size = (protect ? 0x1f200 :
11422 TG3_NVRAM_SIZE_128KB);
11423 break;
11424 case FLASH_5752VENDOR_ST_M45PE10:
11425 case FLASH_5752VENDOR_ST_M45PE20:
11426 case FLASH_5752VENDOR_ST_M45PE40:
11427 tp->nvram_jedecnum = JEDEC_ST;
11428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11429 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11430 tp->nvram_pagesize = 256;
11431 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11432 tp->nvram_size = (protect ?
11433 TG3_NVRAM_SIZE_64KB :
11434 TG3_NVRAM_SIZE_128KB);
11435 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11436 tp->nvram_size = (protect ?
11437 TG3_NVRAM_SIZE_64KB :
11438 TG3_NVRAM_SIZE_256KB);
11439 else
11440 tp->nvram_size = (protect ?
11441 TG3_NVRAM_SIZE_128KB :
11442 TG3_NVRAM_SIZE_512KB);
11443 break;
d3c7b886
MC		 11444 }
11445}
11446
1b27777a
MC		 11447static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11448{
11449 u32 nvcfg1;
11450
11451 nvcfg1 = tr32(NVRAM_CFG1);
11452
11453 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11454 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11455 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11456 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11457 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11458 tp->nvram_jedecnum = JEDEC_ATMEL;
11459 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11460 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11461
8590a603
MC		 11462 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11463 tw32(NVRAM_CFG1, nvcfg1);
11464 break;
11465 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11466 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11467 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11468 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11469 tp->nvram_jedecnum = JEDEC_ATMEL;
11470 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11471 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11472 tp->nvram_pagesize = 264;
11473 break;
11474 case FLASH_5752VENDOR_ST_M45PE10:
11475 case FLASH_5752VENDOR_ST_M45PE20:
11476 case FLASH_5752VENDOR_ST_M45PE40:
11477 tp->nvram_jedecnum = JEDEC_ST;
11478 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11479 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11480 tp->nvram_pagesize = 256;
11481 break;
1b27777a
MC		 11482 }
11483}
11484
6b91fa02
MC		 11485static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11486{
11487 u32 nvcfg1, protect = 0;
11488
11489 nvcfg1 = tr32(NVRAM_CFG1);
11490
11491 /* NVRAM protection for TPM */
11492 if (nvcfg1 & (1 << 27)) {
f66a29b0 11493 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11494 protect = 1;
11495 }
11496
11497 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11498 switch (nvcfg1) {
8590a603
MC		 11499 case FLASH_5761VENDOR_ATMEL_ADB021D:
11500 case FLASH_5761VENDOR_ATMEL_ADB041D:
11501 case FLASH_5761VENDOR_ATMEL_ADB081D:
11502 case FLASH_5761VENDOR_ATMEL_ADB161D:
11503 case FLASH_5761VENDOR_ATMEL_MDB021D:
11504 case FLASH_5761VENDOR_ATMEL_MDB041D:
11505 case FLASH_5761VENDOR_ATMEL_MDB081D:
11506 case FLASH_5761VENDOR_ATMEL_MDB161D:
11507 tp->nvram_jedecnum = JEDEC_ATMEL;
11508 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11509 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11510 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11511 tp->nvram_pagesize = 256;
11512 break;
11513 case FLASH_5761VENDOR_ST_A_M45PE20:
11514 case FLASH_5761VENDOR_ST_A_M45PE40:
11515 case FLASH_5761VENDOR_ST_A_M45PE80:
11516 case FLASH_5761VENDOR_ST_A_M45PE16:
11517 case FLASH_5761VENDOR_ST_M_M45PE20:
11518 case FLASH_5761VENDOR_ST_M_M45PE40:
11519 case FLASH_5761VENDOR_ST_M_M45PE80:
11520 case FLASH_5761VENDOR_ST_M_M45PE16:
11521 tp->nvram_jedecnum = JEDEC_ST;
11522 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11523 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11524 tp->nvram_pagesize = 256;
11525 break;
6b91fa02
MC		 11526 }
11527
11528 if (protect) {
11529 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11530 } else {
11531 switch (nvcfg1) {
8590a603
MC		 11532 case FLASH_5761VENDOR_ATMEL_ADB161D:
11533 case FLASH_5761VENDOR_ATMEL_MDB161D:
11534 case FLASH_5761VENDOR_ST_A_M45PE16:
11535 case FLASH_5761VENDOR_ST_M_M45PE16:
11536 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11537 break;
11538 case FLASH_5761VENDOR_ATMEL_ADB081D:
11539 case FLASH_5761VENDOR_ATMEL_MDB081D:
11540 case FLASH_5761VENDOR_ST_A_M45PE80:
11541 case FLASH_5761VENDOR_ST_M_M45PE80:
11542 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11543 break;
11544 case FLASH_5761VENDOR_ATMEL_ADB041D:
11545 case FLASH_5761VENDOR_ATMEL_MDB041D:
11546 case FLASH_5761VENDOR_ST_A_M45PE40:
11547 case FLASH_5761VENDOR_ST_M_M45PE40:
11548 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11549 break;
11550 case FLASH_5761VENDOR_ATMEL_ADB021D:
11551 case FLASH_5761VENDOR_ATMEL_MDB021D:
11552 case FLASH_5761VENDOR_ST_A_M45PE20:
11553 case FLASH_5761VENDOR_ST_M_M45PE20:
11554 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11555 break;
6b91fa02
MC		 11556 }
11557 }
11558}
11559
b5d3772c
MC		 11560static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11561{
11562 tp->nvram_jedecnum = JEDEC_ATMEL;
11563 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11564 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11565}
11566
321d32a0
MC		 11567static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11568{
11569 u32 nvcfg1;
11570
11571 nvcfg1 = tr32(NVRAM_CFG1);
11572
11573 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11574 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11575 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11576 tp->nvram_jedecnum = JEDEC_ATMEL;
11577 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11578 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11579
11580 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11581 tw32(NVRAM_CFG1, nvcfg1);
11582 return;
11583 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11584 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11585 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11586 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11587 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11588 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11589 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11590 tp->nvram_jedecnum = JEDEC_ATMEL;
11591 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11592 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11593
11594 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11595 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11596 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11597 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11598 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11599 break;
11600 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11601 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11602 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11603 break;
11604 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11605 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11606 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11607 break;
11608 }
11609 break;
11610 case FLASH_5752VENDOR_ST_M45PE10:
11611 case FLASH_5752VENDOR_ST_M45PE20:
11612 case FLASH_5752VENDOR_ST_M45PE40:
11613 tp->nvram_jedecnum = JEDEC_ST;
11614 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11615 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11616
11617 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11618 case FLASH_5752VENDOR_ST_M45PE10:
11619 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11620 break;
11621 case FLASH_5752VENDOR_ST_M45PE20:
11622 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11623 break;
11624 case FLASH_5752VENDOR_ST_M45PE40:
11625 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11626 break;
11627 }
11628 break;
11629 default:
df259d8c 11630 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11631 return;
11632 }
11633
a1b950d5
MC		 11634 tg3_nvram_get_pagesize(tp, nvcfg1);
11635 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11636 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11637}
11638
11639
11640static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11641{
11642 u32 nvcfg1;
11643
11644 nvcfg1 = tr32(NVRAM_CFG1);
11645
11646 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11647 case FLASH_5717VENDOR_ATMEL_EEPROM:
11648 case FLASH_5717VENDOR_MICRO_EEPROM:
11649 tp->nvram_jedecnum = JEDEC_ATMEL;
11650 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11651 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11652
11653 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11654 tw32(NVRAM_CFG1, nvcfg1);
11655 return;
11656 case FLASH_5717VENDOR_ATMEL_MDB011D:
11657 case FLASH_5717VENDOR_ATMEL_ADB011B:
11658 case FLASH_5717VENDOR_ATMEL_ADB011D:
11659 case FLASH_5717VENDOR_ATMEL_MDB021D:
11660 case FLASH_5717VENDOR_ATMEL_ADB021B:
11661 case FLASH_5717VENDOR_ATMEL_ADB021D:
11662 case FLASH_5717VENDOR_ATMEL_45USPT:
11663 tp->nvram_jedecnum = JEDEC_ATMEL;
11664 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11665 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11666
11667 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11668 case FLASH_5717VENDOR_ATMEL_MDB021D:
11669 case FLASH_5717VENDOR_ATMEL_ADB021B:
11670 case FLASH_5717VENDOR_ATMEL_ADB021D:
11671 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11672 break;
11673 default:
11674 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11675 break;
11676 }
321d32a0 11677 break;
a1b950d5
MC		 11678 case FLASH_5717VENDOR_ST_M_M25PE10:
11679 case FLASH_5717VENDOR_ST_A_M25PE10:
11680 case FLASH_5717VENDOR_ST_M_M45PE10:
11681 case FLASH_5717VENDOR_ST_A_M45PE10:
11682 case FLASH_5717VENDOR_ST_M_M25PE20:
11683 case FLASH_5717VENDOR_ST_A_M25PE20:
11684 case FLASH_5717VENDOR_ST_M_M45PE20:
11685 case FLASH_5717VENDOR_ST_A_M45PE20:
11686 case FLASH_5717VENDOR_ST_25USPT:
11687 case FLASH_5717VENDOR_ST_45USPT:
11688 tp->nvram_jedecnum = JEDEC_ST;
11689 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11690 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11691
11692 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11693 case FLASH_5717VENDOR_ST_M_M25PE20:
11694 case FLASH_5717VENDOR_ST_A_M25PE20:
11695 case FLASH_5717VENDOR_ST_M_M45PE20:
11696 case FLASH_5717VENDOR_ST_A_M45PE20:
11697 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11698 break;
11699 default:
11700 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11701 break;
11702 }
321d32a0 11703 break;
a1b950d5
MC		 11704 default:
11705 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11706 return;
321d32a0 11707 }
a1b950d5
MC		 11708
11709 tg3_nvram_get_pagesize(tp, nvcfg1);
11710 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11711 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11712}
11713
1da177e4
LT		 11714/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11715static void __devinit tg3_nvram_init(struct tg3 *tp)
11716{
1da177e4
LT		 11717 tw32_f(GRC_EEPROM_ADDR,
11718 (EEPROM_ADDR_FSM_RESET |
11719 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11720 EEPROM_ADDR_CLKPERD_SHIFT)));
11721
9d57f01c 11722 msleep(1);
1da177e4
LT		 11723
11724 /* Enable seeprom accesses. */
11725 tw32_f(GRC_LOCAL_CTRL,
11726 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11727 udelay(100);
11728
11729 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11730 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11731 tp->tg3_flags |= TG3_FLAG_NVRAM;
11732
ec41c7df
MC		 11733 if (tg3_nvram_lock(tp)) {
11734 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11735 "tg3_nvram_init failed.\n", tp->dev->name);
11736 return;
11737 }
e6af301b 11738 tg3_enable_nvram_access(tp);
1da177e4 11739
989a9d23
MC		 11740 tp->nvram_size = 0;
11741
361b4ac2
MC		 11742 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11743 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11744 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11745 tg3_get_5755_nvram_info(tp);
d30cdd28 11746 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11747 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11748 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11749 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11750 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11751 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11752 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11753 tg3_get_5906_nvram_info(tp);
b703df6f
MC		 11754 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11755 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0 11756 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11757 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11758 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11759 else
11760 tg3_get_nvram_info(tp);
11761
989a9d23
MC		 11762 if (tp->nvram_size == 0)
11763 tg3_get_nvram_size(tp);
1da177e4 11764
e6af301b 11765 tg3_disable_nvram_access(tp);
381291b7 11766 tg3_nvram_unlock(tp);
1da177e4
LT		 11767
11768 } else {
11769 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11770
11771 tg3_get_eeprom_size(tp);
11772 }
11773}
11774
1da177e4
LT		 11775static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11776 u32 offset, u32 len, u8 *buf)
11777{
11778 int i, j, rc = 0;
11779 u32 val;
11780
11781 for (i = 0; i < len; i += 4) {
b9fc7dc5 11782 u32 addr;
a9dc529d 11783 __be32 data;
1da177e4
LT		 11784
11785 addr = offset + i;
11786
11787 memcpy(&data, buf + i, 4);
11788
62cedd11
MC		 11789 /*
11790 * The SEEPROM interface expects the data to always be opposite
11791 * the native endian format. We accomplish this by reversing
11792 * all the operations that would have been performed on the
11793 * data from a call to tg3_nvram_read_be32().
11794 */
11795 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11796
11797 val = tr32(GRC_EEPROM_ADDR);
11798 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11799
11800 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11801 EEPROM_ADDR_READ);
11802 tw32(GRC_EEPROM_ADDR, val |
11803 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11804 (addr & EEPROM_ADDR_ADDR_MASK) |
11805 EEPROM_ADDR_START |
11806 EEPROM_ADDR_WRITE);
6aa20a22 11807
9d57f01c 11808 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11809 val = tr32(GRC_EEPROM_ADDR);
11810
11811 if (val & EEPROM_ADDR_COMPLETE)
11812 break;
9d57f01c 11813 msleep(1);
1da177e4
LT		 11814 }
11815 if (!(val & EEPROM_ADDR_COMPLETE)) {
11816 rc = -EBUSY;
11817 break;
11818 }
11819 }
11820
11821 return rc;
11822}
11823
11824/* offset and length are dword aligned */
11825static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11826 u8 *buf)
11827{
11828 int ret = 0;
11829 u32 pagesize = tp->nvram_pagesize;
11830 u32 pagemask = pagesize - 1;
11831 u32 nvram_cmd;
11832 u8 *tmp;
11833
11834 tmp = kmalloc(pagesize, GFP_KERNEL);
11835 if (tmp == NULL)
11836 return -ENOMEM;
11837
11838 while (len) {
11839 int j;
e6af301b 11840 u32 phy_addr, page_off, size;
1da177e4
LT		 11841
11842 phy_addr = offset & ~pagemask;
6aa20a22 11843
1da177e4 11844 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11845 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11846 (__be32 *) (tmp + j));
11847 if (ret)
1da177e4
LT		 11848 break;
11849 }
11850 if (ret)
11851 break;
11852
11853 page_off = offset & pagemask;
11854 size = pagesize;
11855 if (len < size)
11856 size = len;
11857
11858 len -= size;
11859
11860 memcpy(tmp + page_off, buf, size);
11861
11862 offset = offset + (pagesize - page_off);
11863
e6af301b 11864 tg3_enable_nvram_access(tp);
1da177e4
LT		 11865
11866 /*
11867 * Before we can erase the flash page, we need
11868 * to issue a special "write enable" command.
11869 */
11870 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11871
11872 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11873 break;
11874
11875 /* Erase the target page */
11876 tw32(NVRAM_ADDR, phy_addr);
11877
11878 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11879 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11880
11881 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11882 break;
11883
11884 /* Issue another write enable to start the write. */
11885 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11886
11887 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11888 break;
11889
11890 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11891 __be32 data;
1da177e4 11892
b9fc7dc5 11893 data = *((__be32 *) (tmp + j));
a9dc529d 11894
b9fc7dc5 11895 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11896
11897 tw32(NVRAM_ADDR, phy_addr + j);
11898
11899 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11900 NVRAM_CMD_WR;
11901
11902 if (j == 0)
11903 nvram_cmd |= NVRAM_CMD_FIRST;
11904 else if (j == (pagesize - 4))
11905 nvram_cmd |= NVRAM_CMD_LAST;
11906
11907 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11908 break;
11909 }
11910 if (ret)
11911 break;
11912 }
11913
11914 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11915 tg3_nvram_exec_cmd(tp, nvram_cmd);
11916
11917 kfree(tmp);
11918
11919 return ret;
11920}
11921
11922/* offset and length are dword aligned */
11923static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11924 u8 *buf)
11925{
11926 int i, ret = 0;
11927
11928 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11929 u32 page_off, phy_addr, nvram_cmd;
11930 __be32 data;
1da177e4
LT		 11931
11932 memcpy(&data, buf + i, 4);
b9fc7dc5 11933 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11934
11935 page_off = offset % tp->nvram_pagesize;
11936
1820180b 11937 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11938
11939 tw32(NVRAM_ADDR, phy_addr);
11940
11941 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11942
11943 if ((page_off == 0) || (i == 0))
11944 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11945 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11946 nvram_cmd |= NVRAM_CMD_LAST;
11947
11948 if (i == (len - 4))
11949 nvram_cmd |= NVRAM_CMD_LAST;
11950
321d32a0
MC		 11951 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11952 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11953 (tp->nvram_jedecnum == JEDEC_ST) &&
11954 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11955
11956 if ((ret = tg3_nvram_exec_cmd(tp,
11957 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11958 NVRAM_CMD_DONE)))
11959
11960 break;
11961 }
11962 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11963 /* We always do complete word writes to eeprom. */
11964 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11965 }
11966
11967 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11968 break;
11969 }
11970 return ret;
11971}
11972
11973/* offset and length are dword aligned */
11974static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11975{
11976 int ret;
11977
1da177e4 11978 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11979 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11980 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11981 udelay(40);
11982 }
11983
11984 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11985 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11986 }
11987 else {
11988 u32 grc_mode;
11989
ec41c7df
MC		 11990 ret = tg3_nvram_lock(tp);
11991 if (ret)
11992 return ret;
1da177e4 11993
e6af301b
MC		 11994 tg3_enable_nvram_access(tp);
11995 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11996 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11997 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11998
11999 grc_mode = tr32(GRC_MODE);
12000 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12001
12002 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12003 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12004
12005 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12006 buf);
12007 }
12008 else {
12009 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12010 buf);
12011 }
12012
12013 grc_mode = tr32(GRC_MODE);
12014 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12015
e6af301b 12016 tg3_disable_nvram_access(tp);
1da177e4
LT		 12017 tg3_nvram_unlock(tp);
12018 }
12019
12020 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 12021 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 12022 udelay(40);
12023 }
12024
12025 return ret;
12026}
12027
12028struct subsys_tbl_ent {
12029 u16 subsys_vendor, subsys_devid;
12030 u32 phy_id;
12031};
12032
12033static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12034 /* Broadcom boards. */
12035 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12036 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12037 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12038 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12039 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12040 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12041 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12042 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12043 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12044 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12045 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12046
12047 /* 3com boards. */
12048 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12049 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12050 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12051 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12052 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12053
12054 /* DELL boards. */
12055 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12056 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12057 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12058 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12059
12060 /* Compaq boards. */
12061 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12062 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12063 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12064 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12065 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12066
12067 /* IBM boards. */
12068 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12069};
12070
12071static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12072{
12073 int i;
12074
12075 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12076 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12077 tp->pdev->subsystem_vendor) &&
12078 (subsys_id_to_phy_id[i].subsys_devid ==
12079 tp->pdev->subsystem_device))
12080 return &subsys_id_to_phy_id[i];
12081 }
12082 return NULL;
12083}
12084
7d0c41ef 12085static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12086{
1da177e4 12087 u32 val;
caf636c7
MC		 12088 u16 pmcsr;
12089
12090 /* On some early chips the SRAM cannot be accessed in D3hot state,
12091 * so need make sure we're in D0.
12092 */
12093 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12094 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12095 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12096 msleep(1);
7d0c41ef
MC		 12097
12098 /* Make sure register accesses (indirect or otherwise)
12099 * will function correctly.
12100 */
12101 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12102 tp->misc_host_ctrl);
1da177e4 12103
f49639e6
DM		 12104 /* The memory arbiter has to be enabled in order for SRAM accesses
12105 * to succeed. Normally on powerup the tg3 chip firmware will make
12106 * sure it is enabled, but other entities such as system netboot
12107 * code might disable it.
12108 */
12109 val = tr32(MEMARB_MODE);
12110 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12111
1da177e4 12112 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 12113 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12114
a85feb8c
GZ		 12115 /* Assume an onboard device and WOL capable by default. */
12116 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12117
b5d3772c 12118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12119 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12120 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12121 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12122 }
0527ba35
MC		 12123 val = tr32(VCPU_CFGSHDW);
12124 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12125 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12126 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12127 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12128 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12129 goto done;
b5d3772c
MC		 12130 }
12131
1da177e4
LT		 12132 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12133 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12134 u32 nic_cfg, led_cfg;
a9daf367 12135 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12136 int eeprom_phy_serdes = 0;
1da177e4
LT		 12137
12138 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12139 tp->nic_sram_data_cfg = nic_cfg;
12140
12141 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12142 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12143 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12144 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12145 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12146 (ver > 0) && (ver < 0x100))
12147 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12148
a9daf367
MC		 12149 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12150 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12151
1da177e4
LT		 12152 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12153 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12154 eeprom_phy_serdes = 1;
12155
12156 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12157 if (nic_phy_id != 0) {
12158 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12159 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12160
12161 eeprom_phy_id = (id1 >> 16) << 10;
12162 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12163 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12164 } else
12165 eeprom_phy_id = 0;
12166
7d0c41ef 12167 tp->phy_id = eeprom_phy_id;
747e8f8b 12168 if (eeprom_phy_serdes) {
a4e2b347 12169 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 12170 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12171 else
12172 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12173 }
7d0c41ef 12174
cbf46853 12175 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12176 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12177 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12178 else
1da177e4
LT		 12179 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12180
12181 switch (led_cfg) {
12182 default:
12183 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12184 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12185 break;
12186
12187 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12188 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12189 break;
12190
12191 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12192 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12193
12194 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12195 * read on some older 5700/5701 bootcode.
12196 */
12197 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12198 ASIC_REV_5700 ||
12199 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12200 ASIC_REV_5701)
12201 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12202
1da177e4
LT		 12203 break;
12204
12205 case SHASTA_EXT_LED_SHARED:
12206 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12207 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12208 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12209 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12210 LED_CTRL_MODE_PHY_2);
12211 break;
12212
12213 case SHASTA_EXT_LED_MAC:
12214 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12215 break;
12216
12217 case SHASTA_EXT_LED_COMBO:
12218 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12219 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12220 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12221 LED_CTRL_MODE_PHY_2);
12222 break;
12223
855e1111 12224 }
1da177e4
LT		 12225
12226 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12228 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12229 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12230
b2a5c19c
MC		 12231 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12232 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12233
9d26e213 12234 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12235 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12236 if ((tp->pdev->subsystem_vendor ==
12237 PCI_VENDOR_ID_ARIMA) &&
12238 (tp->pdev->subsystem_device == 0x205a ||
12239 tp->pdev->subsystem_device == 0x2063))
12240 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12241 } else {
f49639e6 12242 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12243 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12244 }
1da177e4
LT		 12245
12246 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12247 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12248 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12249 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12250 }
b2b98d4a
MC		 12251
12252 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12253 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12254 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12255
a85feb8c
GZ		 12256 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12257 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12258 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12259
12dac075 12260 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12261 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12262 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12263
1da177e4
LT		 12264 if (cfg2 & (1 << 17))
12265 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12266
12267 /* serdes signal pre-emphasis in register 0x590 set by */
12268 /* bootcode if bit 18 is set */
12269 if (cfg2 & (1 << 18))
12270 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12271
321d32a0
MC		 12272 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12273 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12274 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12275 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12276
8ed5d97e
MC		 12277 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12278 u32 cfg3;
12279
12280 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12281 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12282 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12283 }
a9daf367
MC		 12284
12285 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12286 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12287 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12288 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12289 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12290 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12291 }
05ac4cb7
MC		 12292done:
12293 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12294 device_set_wakeup_enable(&tp->pdev->dev,
12295 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12296}
12297
b2a5c19c
MC		 12298static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12299{
12300 int i;
12301 u32 val;
12302
12303 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12304 tw32(OTP_CTRL, cmd);
12305
12306 /* Wait for up to 1 ms for command to execute. */
12307 for (i = 0; i < 100; i++) {
12308 val = tr32(OTP_STATUS);
12309 if (val & OTP_STATUS_CMD_DONE)
12310 break;
12311 udelay(10);
12312 }
12313
12314 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12315}
12316
12317/* Read the gphy configuration from the OTP region of the chip. The gphy
12318 * configuration is a 32-bit value that straddles the alignment boundary.
12319 * We do two 32-bit reads and then shift and merge the results.
12320 */
12321static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12322{
12323 u32 bhalf_otp, thalf_otp;
12324
12325 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12326
12327 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12328 return 0;
12329
12330 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12331
12332 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12333 return 0;
12334
12335 thalf_otp = tr32(OTP_READ_DATA);
12336
12337 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12338
12339 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12340 return 0;
12341
12342 bhalf_otp = tr32(OTP_READ_DATA);
12343
12344 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12345}
12346
7d0c41ef
MC		 12347static int __devinit tg3_phy_probe(struct tg3 *tp)
12348{
12349 u32 hw_phy_id_1, hw_phy_id_2;
12350 u32 hw_phy_id, hw_phy_id_masked;
12351 int err;
1da177e4 12352
b02fd9e3
MC		 12353 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12354 return tg3_phy_init(tp);
12355
1da177e4 12356 /* Reading the PHY ID register can conflict with ASF
877d0310 12357 * firmware access to the PHY hardware.
1da177e4
LT		 12358 */
12359 err = 0;
0d3031d9
MC		 12360 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12361 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12362 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12363 } else {
12364 /* Now read the physical PHY_ID from the chip and verify
12365 * that it is sane. If it doesn't look good, we fall back
12366 * to either the hard-coded table based PHY_ID and failing
12367 * that the value found in the eeprom area.
12368 */
12369 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12370 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12371
12372 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12373 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12374 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12375
12376 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12377 }
12378
12379 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12380 tp->phy_id = hw_phy_id;
12381 if (hw_phy_id_masked == PHY_ID_BCM8002)
12382 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12383 else
12384 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12385 } else {
7d0c41ef
MC		 12386 if (tp->phy_id != PHY_ID_INVALID) {
12387 /* Do nothing, phy ID already set up in
12388 * tg3_get_eeprom_hw_cfg().
12389 */
1da177e4
LT		 12390 } else {
12391 struct subsys_tbl_ent *p;
12392
12393 /* No eeprom signature? Try the hardcoded
12394 * subsys device table.
12395 */
12396 p = lookup_by_subsys(tp);
12397 if (!p)
12398 return -ENODEV;
12399
12400 tp->phy_id = p->phy_id;
12401 if (!tp->phy_id ||
12402 tp->phy_id == PHY_ID_BCM8002)
12403 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12404 }
12405 }
12406
747e8f8b 12407 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12408 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12409 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12410 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12411
12412 tg3_readphy(tp, MII_BMSR, &bmsr);
12413 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12414 (bmsr & BMSR_LSTATUS))
12415 goto skip_phy_reset;
6aa20a22 12416
1da177e4
LT		 12417 err = tg3_phy_reset(tp);
12418 if (err)
12419 return err;
12420
12421 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12422 ADVERTISE_100HALF | ADVERTISE_100FULL |
12423 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12424 tg3_ctrl = 0;
12425 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12426 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12427 MII_TG3_CTRL_ADV_1000_FULL);
12428 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12429 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12430 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12431 MII_TG3_CTRL_ENABLE_AS_MASTER);
12432 }
12433
3600d918
MC		 12434 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12435 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12436 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12437 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12438 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12439
12440 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12441 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12442
12443 tg3_writephy(tp, MII_BMCR,
12444 BMCR_ANENABLE | BMCR_ANRESTART);
12445 }
12446 tg3_phy_set_wirespeed(tp);
12447
12448 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12449 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12450 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12451 }
12452
12453skip_phy_reset:
12454 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12455 err = tg3_init_5401phy_dsp(tp);
12456 if (err)
12457 return err;
12458 }
12459
12460 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12461 err = tg3_init_5401phy_dsp(tp);
12462 }
12463
747e8f8b 12464 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12465 tp->link_config.advertising =
12466 (ADVERTISED_1000baseT_Half |
12467 ADVERTISED_1000baseT_Full |
12468 ADVERTISED_Autoneg |
12469 ADVERTISED_FIBRE);
12470 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12471 tp->link_config.advertising &=
12472 ~(ADVERTISED_1000baseT_Half |
12473 ADVERTISED_1000baseT_Full);
12474
12475 return err;
12476}
12477
12478static void __devinit tg3_read_partno(struct tg3 *tp)
12479{
141518c9 12480 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
af2c6a4a 12481 unsigned int i;
1b27777a 12482 u32 magic;
1da177e4 12483
df259d8c
MC		 12484 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12485 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12486 goto out_not_found;
1da177e4 12487
1820180b 12488 if (magic == TG3_EEPROM_MAGIC) {
141518c9 12489 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
1b27777a 12490 u32 tmp;
1da177e4 12491
6d348f2c
MC		 12492 /* The data is in little-endian format in NVRAM.
12493 * Use the big-endian read routines to preserve
12494 * the byte order as it exists in NVRAM.
12495 */
141518c9 12496 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
1b27777a
MC		 12497 goto out_not_found;
12498
6d348f2c 12499 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12500 }
12501 } else {
94c982bd
MC		 12502 ssize_t cnt;
12503 unsigned int pos = 0, i = 0;
12504
12505 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12506 cnt = pci_read_vpd(tp->pdev, pos,
12507 TG3_NVM_VPD_LEN - pos,
12508 &vpd_data[pos]);
12509 if (cnt == -ETIMEDOUT || -EINTR)
12510 cnt = 0;
12511 else if (cnt < 0)
f49639e6 12512 goto out_not_found;
1b27777a 12513 }
94c982bd
MC		 12514 if (pos != TG3_NVM_VPD_LEN)
12515 goto out_not_found;
1da177e4
LT		 12516 }
12517
12518 /* Now parse and find the part number. */
141518c9 12519 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
1da177e4 12520 unsigned char val = vpd_data[i];
af2c6a4a 12521 unsigned int block_end;
1da177e4
LT		 12522
12523 if (val == 0x82 || val == 0x91) {
12524 i = (i + 3 +
12525 (vpd_data[i + 1] +
12526 (vpd_data[i + 2] << 8)));
12527 continue;
12528 }
12529
12530 if (val != 0x90)
12531 goto out_not_found;
12532
12533 block_end = (i + 3 +
12534 (vpd_data[i + 1] +
12535 (vpd_data[i + 2] << 8)));
12536 i += 3;
af2c6a4a 12537
141518c9 12538 if (block_end > TG3_NVM_VPD_LEN)
af2c6a4a
MC		 12539 goto out_not_found;
12540
12541 while (i < (block_end - 2)) {
1da177e4
LT		 12542 if (vpd_data[i + 0] == 'P' &&
12543 vpd_data[i + 1] == 'N') {
12544 int partno_len = vpd_data[i + 2];
12545
af2c6a4a 12546 i += 3;
141518c9
MC		 12547 if (partno_len > TG3_BPN_SIZE ||
12548 (partno_len + i) > TG3_NVM_VPD_LEN)
1da177e4
LT		 12549 goto out_not_found;
12550
12551 memcpy(tp->board_part_number,
af2c6a4a 12552 &vpd_data[i], partno_len);
1da177e4
LT		 12553
12554 /* Success. */
12555 return;
12556 }
af2c6a4a 12557 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12558 }
12559
12560 /* Part number not found. */
12561 goto out_not_found;
12562 }
12563
12564out_not_found:
b5d3772c
MC		 12565 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12566 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12567 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12568 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12569 strcpy(tp->board_part_number, "BCM57780");
12570 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12571 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12572 strcpy(tp->board_part_number, "BCM57760");
12573 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12574 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12575 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12576 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12577 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12578 strcpy(tp->board_part_number, "BCM57788");
b703df6f
MC		 12579 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12580 strcpy(tp->board_part_number, "BCM57765");
b5d3772c
MC		 12581 else
12582 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12583}
12584
9c8a620e
MC		 12585static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12586{
12587 u32 val;
12588
e4f34110 12589 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12590 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12591 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12592 val != 0)
12593 return 0;
12594
12595 return 1;
12596}
12597
acd9c119
MC		 12598static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12599{
ff3a7cb2 12600 u32 val, offset, start, ver_offset;
acd9c119 12601 int i;
ff3a7cb2 12602 bool newver = false;
acd9c119
MC		 12603
12604 if (tg3_nvram_read(tp, 0xc, &offset) ||
12605 tg3_nvram_read(tp, 0x4, &start))
12606 return;
12607
12608 offset = tg3_nvram_logical_addr(tp, offset);
12609
ff3a7cb2 12610 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12611 return;
12612
ff3a7cb2
MC		 12613 if ((val & 0xfc000000) == 0x0c000000) {
12614 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12615 return;
12616
ff3a7cb2
MC		 12617 if (val == 0)
12618 newver = true;
12619 }
12620
12621 if (newver) {
12622 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12623 return;
12624
12625 offset = offset + ver_offset - start;
12626 for (i = 0; i < 16; i += 4) {
12627 __be32 v;
12628 if (tg3_nvram_read_be32(tp, offset + i, &v))
12629 return;
12630
12631 memcpy(tp->fw_ver + i, &v, sizeof(v));
12632 }
12633 } else {
12634 u32 major, minor;
12635
12636 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12637 return;
12638
12639 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12640 TG3_NVM_BCVER_MAJSFT;
12641 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12642 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12643 }
12644}
12645
a6f6cb1c
MC		 12646static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12647{
12648 u32 val, major, minor;
12649
12650 /* Use native endian representation */
12651 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12652 return;
12653
12654 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12655 TG3_NVM_HWSB_CFG1_MAJSFT;
12656 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12657 TG3_NVM_HWSB_CFG1_MINSFT;
12658
12659 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12660}
12661
dfe00d7d
MC		 12662static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12663{
12664 u32 offset, major, minor, build;
12665
12666 tp->fw_ver[0] = 's';
12667 tp->fw_ver[1] = 'b';
12668 tp->fw_ver[2] = '\0';
12669
12670 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12671 return;
12672
12673 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12674 case TG3_EEPROM_SB_REVISION_0:
12675 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12676 break;
12677 case TG3_EEPROM_SB_REVISION_2:
12678 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12679 break;
12680 case TG3_EEPROM_SB_REVISION_3:
12681 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12682 break;
12683 default:
12684 return;
12685 }
12686
e4f34110 12687 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12688 return;
12689
12690 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12691 TG3_EEPROM_SB_EDH_BLD_SHFT;
12692 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12693 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12694 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12695
12696 if (minor > 99 || build > 26)
12697 return;
12698
12699 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12700
12701 if (build > 0) {
12702 tp->fw_ver[8] = 'a' + build - 1;
12703 tp->fw_ver[9] = '\0';
12704 }
12705}
12706
acd9c119 12707static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12708{
12709 u32 val, offset, start;
acd9c119 12710 int i, vlen;
9c8a620e
MC		 12711
12712 for (offset = TG3_NVM_DIR_START;
12713 offset < TG3_NVM_DIR_END;
12714 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12715 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12716 return;
12717
9c8a620e
MC		 12718 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12719 break;
12720 }
12721
12722 if (offset == TG3_NVM_DIR_END)
12723 return;
12724
12725 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12726 start = 0x08000000;
e4f34110 12727 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12728 return;
12729
e4f34110 12730 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12731 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12732 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12733 return;
12734
12735 offset += val - start;
12736
acd9c119 12737 vlen = strlen(tp->fw_ver);
9c8a620e 12738
acd9c119
MC		 12739 tp->fw_ver[vlen++] = ',';
12740 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12741
12742 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12743 __be32 v;
12744 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12745 return;
12746
b9fc7dc5 12747 offset += sizeof(v);
c4e6575c 12748
acd9c119
MC		 12749 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12750 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12751 break;
c4e6575c 12752 }
9c8a620e 12753
acd9c119
MC		 12754 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12755 vlen += sizeof(v);
c4e6575c 12756 }
acd9c119
MC		 12757}
12758
7fd76445
MC		 12759static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12760{
12761 int vlen;
12762 u32 apedata;
12763
12764 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12765 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12766 return;
12767
12768 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12769 if (apedata != APE_SEG_SIG_MAGIC)
12770 return;
12771
12772 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12773 if (!(apedata & APE_FW_STATUS_READY))
12774 return;
12775
12776 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12777
12778 vlen = strlen(tp->fw_ver);
12779
12780 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12781 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12782 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12783 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12784 (apedata & APE_FW_VERSION_BLDMSK));
12785}
12786
acd9c119
MC		 12787static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12788{
12789 u32 val;
12790
df259d8c
MC		 12791 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12792 tp->fw_ver[0] = 's';
12793 tp->fw_ver[1] = 'b';
12794 tp->fw_ver[2] = '\0';
12795
12796 return;
12797 }
12798
acd9c119
MC		 12799 if (tg3_nvram_read(tp, 0, &val))
12800 return;
12801
12802 if (val == TG3_EEPROM_MAGIC)
12803 tg3_read_bc_ver(tp);
12804 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12805 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12806 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12807 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12808 else
12809 return;
12810
12811 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12812 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12813 return;
12814
12815 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12816
12817 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12818}
12819
7544b097
MC		 12820static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12821
1da177e4
LT		 12822static int __devinit tg3_get_invariants(struct tg3 *tp)
12823{
12824 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12825 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12826 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12827 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12828 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12829 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12830 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12831 { },
12832 };
12833 u32 misc_ctrl_reg;
1da177e4
LT		 12834 u32 pci_state_reg, grc_misc_cfg;
12835 u32 val;
12836 u16 pci_cmd;
5e7dfd0f 12837 int err;
1da177e4 12838
1da177e4
LT		 12839 /* Force memory write invalidate off. If we leave it on,
12840 * then on 5700_BX chips we have to enable a workaround.
12841 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12842 * to match the cacheline size. The Broadcom driver have this
12843 * workaround but turns MWI off all the times so never uses
12844 * it. This seems to suggest that the workaround is insufficient.
12845 */
12846 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12847 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12848 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12849
12850 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12851 * has the register indirect write enable bit set before
12852 * we try to access any of the MMIO registers. It is also
12853 * critical that the PCI-X hw workaround situation is decided
12854 * before that as well.
12855 */
12856 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12857 &misc_ctrl_reg);
12858
12859 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12860 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12862 u32 prod_id_asic_rev;
12863
5001e2f6
MC		 12864 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12865 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12866 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12867 pci_read_config_dword(tp->pdev,
12868 TG3PCI_GEN2_PRODID_ASICREV,
12869 &prod_id_asic_rev);
b703df6f
MC		 12870 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12871 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12872 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12873 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12874 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12875 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12876 pci_read_config_dword(tp->pdev,
12877 TG3PCI_GEN15_PRODID_ASICREV,
12878 &prod_id_asic_rev);
f6eb9b1f
MC		 12879 else
12880 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12881 &prod_id_asic_rev);
12882
321d32a0 12883 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12884 }
1da177e4 12885
ff645bec
MC		 12886 /* Wrong chip ID in 5752 A0. This code can be removed later
12887 * as A0 is not in production.
12888 */
12889 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12890 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12891
6892914f
MC		 12892 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12893 * we need to disable memory and use config. cycles
12894 * only to access all registers. The 5702/03 chips
12895 * can mistakenly decode the special cycles from the
12896 * ICH chipsets as memory write cycles, causing corruption
12897 * of register and memory space. Only certain ICH bridges
12898 * will drive special cycles with non-zero data during the
12899 * address phase which can fall within the 5703's address
12900 * range. This is not an ICH bug as the PCI spec allows
12901 * non-zero address during special cycles. However, only
12902 * these ICH bridges are known to drive non-zero addresses
12903 * during special cycles.
12904 *
12905 * Since special cycles do not cross PCI bridges, we only
12906 * enable this workaround if the 5703 is on the secondary
12907 * bus of these ICH bridges.
12908 */
12909 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12910 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12911 static struct tg3_dev_id {
12912 u32 vendor;
12913 u32 device;
12914 u32 rev;
12915 } ich_chipsets[] = {
12916 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12917 PCI_ANY_ID },
12918 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12919 PCI_ANY_ID },
12920 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12921 0xa },
12922 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12923 PCI_ANY_ID },
12924 { },
12925 };
12926 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12927 struct pci_dev *bridge = NULL;
12928
12929 while (pci_id->vendor != 0) {
12930 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12931 bridge);
12932 if (!bridge) {
12933 pci_id++;
12934 continue;
12935 }
12936 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12937 if (bridge->revision > pci_id->rev)
6892914f
MC		 12938 continue;
12939 }
12940 if (bridge->subordinate &&
12941 (bridge->subordinate->number ==
12942 tp->pdev->bus->number)) {
12943
12944 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12945 pci_dev_put(bridge);
12946 break;
12947 }
12948 }
12949 }
12950
41588ba1
MC		 12951 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12952 static struct tg3_dev_id {
12953 u32 vendor;
12954 u32 device;
12955 } bridge_chipsets[] = {
12956 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12957 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12958 { },
12959 };
12960 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12961 struct pci_dev *bridge = NULL;
12962
12963 while (pci_id->vendor != 0) {
12964 bridge = pci_get_device(pci_id->vendor,
12965 pci_id->device,
12966 bridge);
12967 if (!bridge) {
12968 pci_id++;
12969 continue;
12970 }
12971 if (bridge->subordinate &&
12972 (bridge->subordinate->number <=
12973 tp->pdev->bus->number) &&
12974 (bridge->subordinate->subordinate >=
12975 tp->pdev->bus->number)) {
12976 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12977 pci_dev_put(bridge);
12978 break;
12979 }
12980 }
12981 }
12982
4a29cc2e
MC		 12983 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12984 * DMA addresses > 40-bit. This bridge may have other additional
12985 * 57xx devices behind it in some 4-port NIC designs for example.
12986 * Any tg3 device found behind the bridge will also need the 40-bit
12987 * DMA workaround.
12988 */
a4e2b347
MC		 12989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12991 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12992 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12993 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12994 }
4a29cc2e
MC		 12995 else {
12996 struct pci_dev *bridge = NULL;
12997
12998 do {
12999 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13000 PCI_DEVICE_ID_SERVERWORKS_EPB,
13001 bridge);
13002 if (bridge && bridge->subordinate &&
13003 (bridge->subordinate->number <=
13004 tp->pdev->bus->number) &&
13005 (bridge->subordinate->subordinate >=
13006 tp->pdev->bus->number)) {
13007 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13008 pci_dev_put(bridge);
13009 break;
13010 }
13011 } while (bridge);
13012 }
4cf78e4f 13013
1da177e4
LT		 13014 /* Initialize misc host control in PCI block. */
13015 tp->misc_host_ctrl |= (misc_ctrl_reg &
13016 MISC_HOST_CTRL_CHIPREV);
13017 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13018 tp->misc_host_ctrl);
13019
f6eb9b1f
MC		 13020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13021 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 13023 tp->pdev_peer = tg3_find_peer(tp);
13024
321d32a0
MC		 13025 /* Intentionally exclude ASIC_REV_5906 */
13026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 13027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 13028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 13029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 13030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13032 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
321d32a0
MC		 13034 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13035
13036 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 13038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 13039 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 13040 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 13041 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13042
1b440c56
JL		 13043 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13044 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13045 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13046
027455ad
MC		 13047 /* 5700 B0 chips do not support checksumming correctly due
13048 * to hardware bugs.
13049 */
13050 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13051 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13052 else {
13053 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13054 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13055 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13056 tp->dev->features |= NETIF_F_IPV6_CSUM;
13057 }
13058
507399f1 13059 /* Determine TSO capabilities */
b703df6f
MC		 13060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13061 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
e849cdc3
MC		 13062 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13063 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13064 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 13065 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13066 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13067 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13069 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13070 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13071 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13072 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13073 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13074 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13076 tp->fw_needed = FIRMWARE_TG3TSO5;
13077 else
13078 tp->fw_needed = FIRMWARE_TG3TSO;
13079 }
13080
13081 tp->irq_max = 1;
13082
5a6f3074 13083 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13084 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13085 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13086 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13087 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13088 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13089 tp->pdev_peer == tp->pdev))
13090 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13091
321d32a0 13092 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13094 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13095 }
4f125f42 13096
b703df6f
MC		 13097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13098 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
507399f1
MC		 13099 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13100 tp->irq_max = TG3_IRQ_MAX_VECS;
13101 }
f6eb9b1f 13102 }
0e1406dd 13103
615774fe
MC		 13104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13106 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13107 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13108 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13109 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13110 }
f6eb9b1f 13111
b703df6f
MC		 13112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13113 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13114 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13115
f51f3562 13116 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f 13117 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
b703df6f 13118 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
8f666b07 13119 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13120
52f4490c
MC		 13121 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13122 &pci_state_reg);
13123
5e7dfd0f
MC		 13124 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13125 if (tp->pcie_cap != 0) {
13126 u16 lnkctl;
13127
1da177e4 13128 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13129
13130 pcie_set_readrq(tp->pdev, 4096);
13131
5e7dfd0f
MC		 13132 pci_read_config_word(tp->pdev,
13133 tp->pcie_cap + PCI_EXP_LNKCTL,
13134 &lnkctl);
13135 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13137 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13138 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13139 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13140 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13141 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13142 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
614b0590
MC		 13143 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13144 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
c7835a77 13145 }
52f4490c 13146 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13147 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13148 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13149 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13150 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13151 if (!tp->pcix_cap) {
13152 printk(KERN_ERR PFX "Cannot find PCI-X "
13153 "capability, aborting.\n");
13154 return -EIO;
13155 }
13156
13157 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13158 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13159 }
1da177e4 13160
399de50b
MC		 13161 /* If we have an AMD 762 or VIA K8T800 chipset, write
13162 * reordering to the mailbox registers done by the host
13163 * controller can cause major troubles. We read back from
13164 * every mailbox register write to force the writes to be
13165 * posted to the chip in order.
13166 */
13167 if (pci_dev_present(write_reorder_chipsets) &&
13168 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13169 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13170
69fc4053
MC		 13171 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13172 &tp->pci_cacheline_sz);
13173 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13174 &tp->pci_lat_timer);
1da177e4
LT		 13175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13176 tp->pci_lat_timer < 64) {
13177 tp->pci_lat_timer = 64;
69fc4053
MC		 13178 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13179 tp->pci_lat_timer);
1da177e4
LT		 13180 }
13181
52f4490c
MC		 13182 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13183 /* 5700 BX chips need to have their TX producer index
13184 * mailboxes written twice to workaround a bug.
13185 */
13186 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13187
52f4490c 13188 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13189 *
13190 * The workaround is to use indirect register accesses
13191 * for all chip writes not to mailbox registers.
13192 */
52f4490c 13193 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13194 u32 pm_reg;
1da177e4
LT		 13195
13196 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13197
13198 /* The chip can have it's power management PCI config
13199 * space registers clobbered due to this bug.
13200 * So explicitly force the chip into D0 here.
13201 */
9974a356
MC		 13202 pci_read_config_dword(tp->pdev,
13203 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13204 &pm_reg);
13205 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13206 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13207 pci_write_config_dword(tp->pdev,
13208 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13209 pm_reg);
13210
13211 /* Also, force SERR#/PERR# in PCI command. */
13212 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13213 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13214 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13215 }
13216 }
13217
1da177e4
LT		 13218 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13219 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13220 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13221 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13222
13223 /* Chip-specific fixup from Broadcom driver */
13224 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13225 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13226 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13227 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13228 }
13229
1ee582d8 13230 /* Default fast path register access methods */
20094930 13231 tp->read32 = tg3_read32;
1ee582d8 13232 tp->write32 = tg3_write32;
09ee929c 13233 tp->read32_mbox = tg3_read32;
20094930 13234 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13235 tp->write32_tx_mbox = tg3_write32;
13236 tp->write32_rx_mbox = tg3_write32;
13237
13238 /* Various workaround register access methods */
13239 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13240 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13241 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13242 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13243 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13244 /*
13245 * Back to back register writes can cause problems on these
13246 * chips, the workaround is to read back all reg writes
13247 * except those to mailbox regs.
13248 *
13249 * See tg3_write_indirect_reg32().
13250 */
1ee582d8 13251 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13252 }
13253
1ee582d8
MC		 13254 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13255 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13256 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13257 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13258 tp->write32_rx_mbox = tg3_write_flush_reg32;
13259 }
20094930 13260
6892914f
MC		 13261 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13262 tp->read32 = tg3_read_indirect_reg32;
13263 tp->write32 = tg3_write_indirect_reg32;
13264 tp->read32_mbox = tg3_read_indirect_mbox;
13265 tp->write32_mbox = tg3_write_indirect_mbox;
13266 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13267 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13268
13269 iounmap(tp->regs);
22abe310 13270 tp->regs = NULL;
6892914f
MC		 13271
13272 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13273 pci_cmd &= ~PCI_COMMAND_MEMORY;
13274 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13275 }
b5d3772c
MC		 13276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13277 tp->read32_mbox = tg3_read32_mbox_5906;
13278 tp->write32_mbox = tg3_write32_mbox_5906;
13279 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13280 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13281 }
6892914f 13282
bbadf503
MC		 13283 if (tp->write32 == tg3_write_indirect_reg32 ||
13284 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13285 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13286 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13287 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13288
7d0c41ef 13289 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13290 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13291 * determined before calling tg3_set_power_state() so that
13292 * we know whether or not to switch out of Vaux power.
13293 * When the flag is set, it means that GPIO1 is used for eeprom
13294 * write protect and also implies that it is a LOM where GPIOs
13295 * are not used to switch power.
6aa20a22 13296 */
7d0c41ef
MC		 13297 tg3_get_eeprom_hw_cfg(tp);
13298
0d3031d9
MC		 13299 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13300 /* Allow reads and writes to the
13301 * APE register and memory space.
13302 */
13303 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13304 PCISTATE_ALLOW_APE_SHMEM_WR;
13305 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13306 pci_state_reg);
13307 }
13308
9936bcf6 13309 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f 13312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
b703df6f
MC		 13313 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13314 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
d30cdd28
MC		 13315 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13316
314fba34
MC		 13317 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13318 * GPIO1 driven high will bring 5700's external PHY out of reset.
13319 * It is also used as eeprom write protect on LOMs.
13320 */
13321 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13322 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13323 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13324 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13325 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13326 /* Unused GPIO3 must be driven as output on 5752 because there
13327 * are no pull-up resistors on unused GPIO pins.
13328 */
13329 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13330 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13331
321d32a0 13332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
cb4ed1fd
MC		 13333 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13334 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
af36e6b6
MC		 13335 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13336
8d519ab2
MC		 13337 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13338 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13339 /* Turn off the debug UART. */
13340 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13341 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13342 /* Keep VMain power. */
13343 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13344 GRC_LCLCTRL_GPIO_OUTPUT0;
13345 }
13346
1da177e4 13347 /* Force the chip into D0. */
bc1c7567 13348 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13349 if (err) {
13350 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13351 pci_name(tp->pdev));
13352 return err;
13353 }
13354
1da177e4
LT		 13355 /* Derive initial jumbo mode from MTU assigned in
13356 * ether_setup() via the alloc_etherdev() call
13357 */
0f893dc6 13358 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13359 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13360 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13361
13362 /* Determine WakeOnLan speed to use. */
13363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13364 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13365 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13366 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13367 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13368 } else {
13369 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13370 }
13371
7f97a4bd
MC		 13372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13373 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13374
1da177e4
LT		 13375 /* A few boards don't want Ethernet@WireSpeed phy feature */
13376 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13377 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13378 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13379 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13380 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13381 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13382 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13383
13384 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13385 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13386 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13387 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13388 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13389
321d32a0 13390 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13391 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13392 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f 13393 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
b703df6f
MC		 13394 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13395 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
c424cb24 13396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13397 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13400 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13401 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13402 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13403 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13404 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13405 } else
c424cb24
MC		 13406 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13407 }
1da177e4 13408
b2a5c19c
MC		 13409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13410 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13411 tp->phy_otp = tg3_read_otp_phycfg(tp);
13412 if (tp->phy_otp == 0)
13413 tp->phy_otp = TG3_OTP_DEFAULT;
13414 }
13415
f51f3562 13416 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13417 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13418 else
13419 tp->mi_mode = MAC_MI_MODE_BASE;
13420
1da177e4 13421 tp->coalesce_mode = 0;
1da177e4
LT		 13422 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13423 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13424 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13425
321d32a0
MC		 13426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13428 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13429
158d7abd
MC		 13430 err = tg3_mdio_init(tp);
13431 if (err)
13432 return err;
1da177e4
LT		 13433
13434 /* Initialize data/descriptor byte/word swapping. */
13435 val = tr32(GRC_MODE);
13436 val &= GRC_MODE_HOST_STACKUP;
13437 tw32(GRC_MODE, val | tp->grc_mode);
13438
13439 tg3_switch_clocks(tp);
13440
13441 /* Clear this out for sanity. */
13442 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13443
13444 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13445 &pci_state_reg);
13446 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13447 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13448 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13449
13450 if (chiprevid == CHIPREV_ID_5701_A0 ||
13451 chiprevid == CHIPREV_ID_5701_B0 ||
13452 chiprevid == CHIPREV_ID_5701_B2 ||
13453 chiprevid == CHIPREV_ID_5701_B5) {
13454 void __iomem *sram_base;
13455
13456 /* Write some dummy words into the SRAM status block
13457 * area, see if it reads back correctly. If the return
13458 * value is bad, force enable the PCIX workaround.
13459 */
13460 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13461
13462 writel(0x00000000, sram_base);
13463 writel(0x00000000, sram_base + 4);
13464 writel(0xffffffff, sram_base + 4);
13465 if (readl(sram_base) != 0x00000000)
13466 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13467 }
13468 }
13469
13470 udelay(50);
13471 tg3_nvram_init(tp);
13472
13473 grc_misc_cfg = tr32(GRC_MISC_CFG);
13474 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13475
1da177e4
LT		 13476 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13477 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13478 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13479 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13480
fac9b83e
DM		 13481 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13482 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13483 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13484 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13485 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13486 HOSTCC_MODE_CLRTICK_TXBD);
13487
13488 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13490 tp->misc_host_ctrl);
13491 }
13492
3bda1258
MC		 13493 /* Preserve the APE MAC_MODE bits */
13494 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13495 tp->mac_mode = tr32(MAC_MODE) |
13496 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13497 else
13498 tp->mac_mode = TG3_DEF_MAC_MODE;
13499
1da177e4
LT		 13500 /* these are limited to 10/100 only */
13501 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13502 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13503 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13504 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13505 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13506 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13507 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13508 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13509 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13510 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13511 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13512 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13513 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13514 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13515
13516 err = tg3_phy_probe(tp);
13517 if (err) {
13518 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13519 pci_name(tp->pdev), err);
13520 /* ... but do not return immediately ... */
b02fd9e3 13521 tg3_mdio_fini(tp);
1da177e4
LT		 13522 }
13523
13524 tg3_read_partno(tp);
c4e6575c 13525 tg3_read_fw_ver(tp);
1da177e4
LT		 13526
13527 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13528 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13529 } else {
13530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13531 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13532 else
13533 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13534 }
13535
13536 /* 5700 {AX,BX} chips have a broken status block link
13537 * change bit implementation, so we must use the
13538 * status register in those cases.
13539 */
13540 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13541 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13542 else
13543 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13544
13545 /* The led_ctrl is set during tg3_phy_probe, here we might
13546 * have to force the link status polling mechanism based
13547 * upon subsystem IDs.
13548 */
13549 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13550 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13551 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13552 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13553 TG3_FLAG_USE_LINKCHG_REG);
13554 }
13555
13556 /* For all SERDES we poll the MAC status register. */
13557 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13558 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13559 else
13560 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13561
ad829268 13562 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13563 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13564 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13565 tp->rx_offset = 0;
13566
f92905de
MC		 13567 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13568
13569 /* Increment the rx prod index on the rx std ring by at most
13570 * 8 for these chips to workaround hw errata.
13571 */
13572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13575 tp->rx_std_max_post = 8;
13576
8ed5d97e
MC		 13577 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13578 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13579 PCIE_PWR_MGMT_L1_THRESH_MSK;
13580
1da177e4
LT		 13581 return err;
13582}
13583
49b6e95f 13584#ifdef CONFIG_SPARC
1da177e4
LT		 13585static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13586{
13587 struct net_device *dev = tp->dev;
13588 struct pci_dev *pdev = tp->pdev;
49b6e95f 13589 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13590 const unsigned char *addr;
49b6e95f
DM		 13591 int len;
13592
13593 addr = of_get_property(dp, "local-mac-address", &len);
13594 if (addr && len == 6) {
13595 memcpy(dev->dev_addr, addr, 6);
13596 memcpy(dev->perm_addr, dev->dev_addr, 6);
13597 return 0;
1da177e4
LT		 13598 }
13599 return -ENODEV;
13600}
13601
13602static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13603{
13604 struct net_device *dev = tp->dev;
13605
13606 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13607 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13608 return 0;
13609}
13610#endif
13611
13612static int __devinit tg3_get_device_address(struct tg3 *tp)
13613{
13614 struct net_device *dev = tp->dev;
13615 u32 hi, lo, mac_offset;
008652b3 13616 int addr_ok = 0;
1da177e4 13617
49b6e95f 13618#ifdef CONFIG_SPARC
1da177e4
LT		 13619 if (!tg3_get_macaddr_sparc(tp))
13620 return 0;
13621#endif
13622
13623 mac_offset = 0x7c;
f49639e6 13624 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13625 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13626 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13627 mac_offset = 0xcc;
13628 if (tg3_nvram_lock(tp))
13629 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13630 else
13631 tg3_nvram_unlock(tp);
a1b950d5
MC		 13632 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13633 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13634 mac_offset = 0xcc;
13635 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13636 mac_offset = 0x10;
1da177e4
LT		 13637
13638 /* First try to get it from MAC address mailbox. */
13639 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13640 if ((hi >> 16) == 0x484b) {
13641 dev->dev_addr[0] = (hi >> 8) & 0xff;
13642 dev->dev_addr[1] = (hi >> 0) & 0xff;
13643
13644 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13645 dev->dev_addr[2] = (lo >> 24) & 0xff;
13646 dev->dev_addr[3] = (lo >> 16) & 0xff;
13647 dev->dev_addr[4] = (lo >> 8) & 0xff;
13648 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13649
008652b3
MC		 13650 /* Some old bootcode may report a 0 MAC address in SRAM */
13651 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13652 }
13653 if (!addr_ok) {
13654 /* Next, try NVRAM. */
df259d8c
MC		 13655 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13656 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13657 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13658 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13659 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13660 }
13661 /* Finally just fetch it out of the MAC control regs. */
13662 else {
13663 hi = tr32(MAC_ADDR_0_HIGH);
13664 lo = tr32(MAC_ADDR_0_LOW);
13665
13666 dev->dev_addr[5] = lo & 0xff;
13667 dev->dev_addr[4] = (lo >> 8) & 0xff;
13668 dev->dev_addr[3] = (lo >> 16) & 0xff;
13669 dev->dev_addr[2] = (lo >> 24) & 0xff;
13670 dev->dev_addr[1] = hi & 0xff;
13671 dev->dev_addr[0] = (hi >> 8) & 0xff;
13672 }
1da177e4
LT		 13673 }
13674
13675 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13676#ifdef CONFIG_SPARC
1da177e4
LT		 13677 if (!tg3_get_default_macaddr_sparc(tp))
13678 return 0;
13679#endif
13680 return -EINVAL;
13681 }
2ff43697 13682 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13683 return 0;
13684}
13685
59e6b434
DM		 13686#define BOUNDARY_SINGLE_CACHELINE 1
13687#define BOUNDARY_MULTI_CACHELINE 2
13688
13689static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13690{
13691 int cacheline_size;
13692 u8 byte;
13693 int goal;
13694
13695 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13696 if (byte == 0)
13697 cacheline_size = 1024;
13698 else
13699 cacheline_size = (int) byte * 4;
13700
13701 /* On 5703 and later chips, the boundary bits have no
13702 * effect.
13703 */
13704 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13705 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13706 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13707 goto out;
13708
13709#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13710 goal = BOUNDARY_MULTI_CACHELINE;
13711#else
13712#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13713 goal = BOUNDARY_SINGLE_CACHELINE;
13714#else
13715 goal = 0;
13716#endif
13717#endif
13718
b703df6f
MC		 13719 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13720 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
cbf9ca6c
MC		 13721 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13722 goto out;
13723 }
13724
59e6b434
DM		 13725 if (!goal)
13726 goto out;
13727
13728 /* PCI controllers on most RISC systems tend to disconnect
13729 * when a device tries to burst across a cache-line boundary.
13730 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13731 *
13732 * Unfortunately, for PCI-E there are only limited
13733 * write-side controls for this, and thus for reads
13734 * we will still get the disconnects. We'll also waste
13735 * these PCI cycles for both read and write for chips
13736 * other than 5700 and 5701 which do not implement the
13737 * boundary bits.
13738 */
13739 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13740 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13741 switch (cacheline_size) {
13742 case 16:
13743 case 32:
13744 case 64:
13745 case 128:
13746 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13747 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13748 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13749 } else {
13750 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13751 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13752 }
13753 break;
13754
13755 case 256:
13756 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13757 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13758 break;
13759
13760 default:
13761 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13762 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13763 break;
855e1111 13764 }
59e6b434
DM		 13765 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13766 switch (cacheline_size) {
13767 case 16:
13768 case 32:
13769 case 64:
13770 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13771 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13772 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13773 break;
13774 }
13775 /* fallthrough */
13776 case 128:
13777 default:
13778 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13779 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13780 break;
855e1111 13781 }
59e6b434
DM		 13782 } else {
13783 switch (cacheline_size) {
13784 case 16:
13785 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13786 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13787 DMA_RWCTRL_WRITE_BNDRY_16);
13788 break;
13789 }
13790 /* fallthrough */
13791 case 32:
13792 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13793 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13794 DMA_RWCTRL_WRITE_BNDRY_32);
13795 break;
13796 }
13797 /* fallthrough */
13798 case 64:
13799 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13800 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13801 DMA_RWCTRL_WRITE_BNDRY_64);
13802 break;
13803 }
13804 /* fallthrough */
13805 case 128:
13806 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13807 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13808 DMA_RWCTRL_WRITE_BNDRY_128);
13809 break;
13810 }
13811 /* fallthrough */
13812 case 256:
13813 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13814 DMA_RWCTRL_WRITE_BNDRY_256);
13815 break;
13816 case 512:
13817 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13818 DMA_RWCTRL_WRITE_BNDRY_512);
13819 break;
13820 case 1024:
13821 default:
13822 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13823 DMA_RWCTRL_WRITE_BNDRY_1024);
13824 break;
855e1111 13825 }
59e6b434
DM		 13826 }
13827
13828out:
13829 return val;
13830}
13831
1da177e4
LT		 13832static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13833{
13834 struct tg3_internal_buffer_desc test_desc;
13835 u32 sram_dma_descs;
13836 int i, ret;
13837
13838 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13839
13840 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13841 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13842 tw32(RDMAC_STATUS, 0);
13843 tw32(WDMAC_STATUS, 0);
13844
13845 tw32(BUFMGR_MODE, 0);
13846 tw32(FTQ_RESET, 0);
13847
13848 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13849 test_desc.addr_lo = buf_dma & 0xffffffff;
13850 test_desc.nic_mbuf = 0x00002100;
13851 test_desc.len = size;
13852
13853 /*
13854 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13855 * the *second* time the tg3 driver was getting loaded after an
13856 * initial scan.
13857 *
13858 * Broadcom tells me:
13859 * ...the DMA engine is connected to the GRC block and a DMA
13860 * reset may affect the GRC block in some unpredictable way...
13861 * The behavior of resets to individual blocks has not been tested.
13862 *
13863 * Broadcom noted the GRC reset will also reset all sub-components.
13864 */
13865 if (to_device) {
13866 test_desc.cqid_sqid = (13 << 8) | 2;
13867
13868 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13869 udelay(40);
13870 } else {
13871 test_desc.cqid_sqid = (16 << 8) | 7;
13872
13873 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13874 udelay(40);
13875 }
13876 test_desc.flags = 0x00000005;
13877
13878 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13879 u32 val;
13880
13881 val = *(((u32 *)&test_desc) + i);
13882 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13883 sram_dma_descs + (i * sizeof(u32)));
13884 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13885 }
13886 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13887
13888 if (to_device) {
13889 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13890 } else {
13891 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13892 }
13893
13894 ret = -ENODEV;
13895 for (i = 0; i < 40; i++) {
13896 u32 val;
13897
13898 if (to_device)
13899 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13900 else
13901 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13902 if ((val & 0xffff) == sram_dma_descs) {
13903 ret = 0;
13904 break;
13905 }
13906
13907 udelay(100);
13908 }
13909
13910 return ret;
13911}
13912
ded7340d 13913#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13914
13915static int __devinit tg3_test_dma(struct tg3 *tp)
13916{
13917 dma_addr_t buf_dma;
59e6b434 13918 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13919 int ret = 0;
1da177e4
LT		 13920
13921 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13922 if (!buf) {
13923 ret = -ENOMEM;
13924 goto out_nofree;
13925 }
13926
13927 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13928 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13929
59e6b434 13930 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13931
b703df6f
MC		 13932 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
cbf9ca6c
MC		 13934 goto out;
13935
1da177e4
LT		 13936 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13937 /* DMA read watermark not used on PCIE */
13938 tp->dma_rwctrl |= 0x00180000;
13939 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13942 tp->dma_rwctrl |= 0x003f0000;
13943 else
13944 tp->dma_rwctrl |= 0x003f000f;
13945 } else {
13946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13948 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13949 u32 read_water = 0x7;
1da177e4 13950
4a29cc2e
MC		 13951 /* If the 5704 is behind the EPB bridge, we can
13952 * do the less restrictive ONE_DMA workaround for
13953 * better performance.
13954 */
13955 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13957 tp->dma_rwctrl |= 0x8000;
13958 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13959 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13960
49afdeb6
MC		 13961 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13962 read_water = 4;
59e6b434 13963 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13964 tp->dma_rwctrl |=
13965 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13966 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13967 (1 << 23);
4cf78e4f
MC		 13968 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13969 /* 5780 always in PCIX mode */
13970 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13971 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13972 /* 5714 always in PCIX mode */
13973 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13974 } else {
13975 tp->dma_rwctrl |= 0x001b000f;
13976 }
13977 }
13978
13979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13981 tp->dma_rwctrl &= 0xfffffff0;
13982
13983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13985 /* Remove this if it causes problems for some boards. */
13986 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13987
13988 /* On 5700/5701 chips, we need to set this bit.
13989 * Otherwise the chip will issue cacheline transactions
13990 * to streamable DMA memory with not all the byte
13991 * enables turned on. This is an error on several
13992 * RISC PCI controllers, in particular sparc64.
13993 *
13994 * On 5703/5704 chips, this bit has been reassigned
13995 * a different meaning. In particular, it is used
13996 * on those chips to enable a PCI-X workaround.
13997 */
13998 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13999 }
14000
14001 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14002
14003#if 0
14004 /* Unneeded, already done by tg3_get_invariants. */
14005 tg3_switch_clocks(tp);
14006#endif
14007
1da177e4
LT		 14008 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14009 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14010 goto out;
14011
59e6b434
DM		 14012 /* It is best to perform DMA test with maximum write burst size
14013 * to expose the 5700/5701 write DMA bug.
14014 */
14015 saved_dma_rwctrl = tp->dma_rwctrl;
14016 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14017 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14018
1da177e4
LT		 14019 while (1) {
14020 u32 *p = buf, i;
14021
14022 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14023 p[i] = i;
14024
14025 /* Send the buffer to the chip. */
14026 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14027 if (ret) {
14028 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14029 break;
14030 }
14031
14032#if 0
14033 /* validate data reached card RAM correctly. */
14034 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14035 u32 val;
14036 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14037 if (le32_to_cpu(val) != p[i]) {
14038 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14039 /* ret = -ENODEV here? */
14040 }
14041 p[i] = 0;
14042 }
14043#endif
14044 /* Now read it back. */
14045 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14046 if (ret) {
14047 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14048
14049 break;
14050 }
14051
14052 /* Verify it. */
14053 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14054 if (p[i] == i)
14055 continue;
14056
59e6b434
DM		 14057 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14058 DMA_RWCTRL_WRITE_BNDRY_16) {
14059 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 14060 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14061 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14062 break;
14063 } else {
14064 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14065 ret = -ENODEV;
14066 goto out;
14067 }
14068 }
14069
14070 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14071 /* Success. */
14072 ret = 0;
14073 break;
14074 }
14075 }
59e6b434
DM		 14076 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14077 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 14078 static struct pci_device_id dma_wait_state_chipsets[] = {
14079 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14080 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14081 { },
14082 };
14083
59e6b434 14084 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 14085 * now look for chipsets that are known to expose the
14086 * DMA bug without failing the test.
59e6b434 14087 */
6d1cfbab
MC		 14088 if (pci_dev_present(dma_wait_state_chipsets)) {
14089 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14090 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14091 }
14092 else
14093 /* Safe to use the calculated DMA boundary. */
14094 tp->dma_rwctrl = saved_dma_rwctrl;
14095
59e6b434
DM		 14096 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14097 }
1da177e4
LT		 14098
14099out:
14100 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14101out_nofree:
14102 return ret;
14103}
14104
14105static void __devinit tg3_init_link_config(struct tg3 *tp)
14106{
14107 tp->link_config.advertising =
14108 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14109 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14110 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14111 ADVERTISED_Autoneg | ADVERTISED_MII);
14112 tp->link_config.speed = SPEED_INVALID;
14113 tp->link_config.duplex = DUPLEX_INVALID;
14114 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14115 tp->link_config.active_speed = SPEED_INVALID;
14116 tp->link_config.active_duplex = DUPLEX_INVALID;
14117 tp->link_config.phy_is_low_power = 0;
14118 tp->link_config.orig_speed = SPEED_INVALID;
14119 tp->link_config.orig_duplex = DUPLEX_INVALID;
14120 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14121}
14122
14123static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14124{
666bc831
MC		 14125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14127 tp->bufmgr_config.mbuf_read_dma_low_water =
14128 DEFAULT_MB_RDMA_LOW_WATER_5705;
14129 tp->bufmgr_config.mbuf_mac_rx_low_water =
14130 DEFAULT_MB_MACRX_LOW_WATER_57765;
14131 tp->bufmgr_config.mbuf_high_water =
14132 DEFAULT_MB_HIGH_WATER_57765;
14133
14134 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14135 DEFAULT_MB_RDMA_LOW_WATER_5705;
14136 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14137 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14138 tp->bufmgr_config.mbuf_high_water_jumbo =
14139 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14140 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
fdfec172
MC		 14141 tp->bufmgr_config.mbuf_read_dma_low_water =
14142 DEFAULT_MB_RDMA_LOW_WATER_5705;
14143 tp->bufmgr_config.mbuf_mac_rx_low_water =
14144 DEFAULT_MB_MACRX_LOW_WATER_5705;
14145 tp->bufmgr_config.mbuf_high_water =
14146 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14148 tp->bufmgr_config.mbuf_mac_rx_low_water =
14149 DEFAULT_MB_MACRX_LOW_WATER_5906;
14150 tp->bufmgr_config.mbuf_high_water =
14151 DEFAULT_MB_HIGH_WATER_5906;
14152 }
fdfec172
MC		 14153
14154 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14155 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14156 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14157 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14158 tp->bufmgr_config.mbuf_high_water_jumbo =
14159 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14160 } else {
14161 tp->bufmgr_config.mbuf_read_dma_low_water =
14162 DEFAULT_MB_RDMA_LOW_WATER;
14163 tp->bufmgr_config.mbuf_mac_rx_low_water =
14164 DEFAULT_MB_MACRX_LOW_WATER;
14165 tp->bufmgr_config.mbuf_high_water =
14166 DEFAULT_MB_HIGH_WATER;
14167
14168 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14169 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14170 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14171 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14172 tp->bufmgr_config.mbuf_high_water_jumbo =
14173 DEFAULT_MB_HIGH_WATER_JUMBO;
14174 }
1da177e4
LT		 14175
14176 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14177 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14178}
14179
14180static char * __devinit tg3_phy_string(struct tg3 *tp)
14181{
14182 switch (tp->phy_id & PHY_ID_MASK) {
14183 case PHY_ID_BCM5400: return "5400";
14184 case PHY_ID_BCM5401: return "5401";
14185 case PHY_ID_BCM5411: return "5411";
14186 case PHY_ID_BCM5701: return "5701";
14187 case PHY_ID_BCM5703: return "5703";
14188 case PHY_ID_BCM5704: return "5704";
14189 case PHY_ID_BCM5705: return "5705";
14190 case PHY_ID_BCM5750: return "5750";
85e94ced 14191 case PHY_ID_BCM5752: return "5752";
a4e2b347 14192 case PHY_ID_BCM5714: return "5714";
4cf78e4f 14193 case PHY_ID_BCM5780: return "5780";
af36e6b6 14194 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 14195 case PHY_ID_BCM5787: return "5787";
d30cdd28 14196 case PHY_ID_BCM5784: return "5784";
126a3368 14197 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 14198 case PHY_ID_BCM5906: return "5906";
9936bcf6 14199 case PHY_ID_BCM5761: return "5761";
9b952f51
MC		 14200 case PHY_ID_BCM5718C: return "5718C";
14201 case PHY_ID_BCM5718S: return "5718S";
1da177e4
LT		 14202 case PHY_ID_BCM8002: return "8002/serdes";
14203 case 0: return "serdes";
14204 default: return "unknown";
855e1111 14205 }
1da177e4
LT		 14206}
14207
f9804ddb
MC		 14208static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14209{
14210 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14211 strcpy(str, "PCI Express");
14212 return str;
14213 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14214 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14215
14216 strcpy(str, "PCIX:");
14217
14218 if ((clock_ctrl == 7) ||
14219 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14220 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14221 strcat(str, "133MHz");
14222 else if (clock_ctrl == 0)
14223 strcat(str, "33MHz");
14224 else if (clock_ctrl == 2)
14225 strcat(str, "50MHz");
14226 else if (clock_ctrl == 4)
14227 strcat(str, "66MHz");
14228 else if (clock_ctrl == 6)
14229 strcat(str, "100MHz");
f9804ddb
MC		 14230 } else {
14231 strcpy(str, "PCI:");
14232 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14233 strcat(str, "66MHz");
14234 else
14235 strcat(str, "33MHz");
14236 }
14237 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14238 strcat(str, ":32-bit");
14239 else
14240 strcat(str, ":64-bit");
14241 return str;
14242}
14243
8c2dc7e1 14244static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14245{
14246 struct pci_dev *peer;
14247 unsigned int func, devnr = tp->pdev->devfn & ~7;
14248
14249 for (func = 0; func < 8; func++) {
14250 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14251 if (peer && peer != tp->pdev)
14252 break;
14253 pci_dev_put(peer);
14254 }
16fe9d74
MC		 14255 /* 5704 can be configured in single-port mode, set peer to
14256 * tp->pdev in that case.
14257 */
14258 if (!peer) {
14259 peer = tp->pdev;
14260 return peer;
14261 }
1da177e4
LT		 14262
14263 /*
14264 * We don't need to keep the refcount elevated; there's no way
14265 * to remove one half of this device without removing the other
14266 */
14267 pci_dev_put(peer);
14268
14269 return peer;
14270}
14271
15f9850d
DM		 14272static void __devinit tg3_init_coal(struct tg3 *tp)
14273{
14274 struct ethtool_coalesce *ec = &tp->coal;
14275
14276 memset(ec, 0, sizeof(*ec));
14277 ec->cmd = ETHTOOL_GCOALESCE;
14278 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14279 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14280 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14281 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14282 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14283 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14284 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14285 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14286 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14287
14288 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14289 HOSTCC_MODE_CLRTICK_TXBD)) {
14290 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14291 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14292 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14293 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14294 }
d244c892
MC		 14295
14296 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14297 ec->rx_coalesce_usecs_irq = 0;
14298 ec->tx_coalesce_usecs_irq = 0;
14299 ec->stats_block_coalesce_usecs = 0;
14300 }
15f9850d
DM		 14301}
14302
7c7d64b8
SH		 14303static const struct net_device_ops tg3_netdev_ops = {
14304 .ndo_open = tg3_open,
14305 .ndo_stop = tg3_close,
00829823
SH		 14306 .ndo_start_xmit = tg3_start_xmit,
14307 .ndo_get_stats = tg3_get_stats,
14308 .ndo_validate_addr = eth_validate_addr,
14309 .ndo_set_multicast_list = tg3_set_rx_mode,
14310 .ndo_set_mac_address = tg3_set_mac_addr,
14311 .ndo_do_ioctl = tg3_ioctl,
14312 .ndo_tx_timeout = tg3_tx_timeout,
14313 .ndo_change_mtu = tg3_change_mtu,
14314#if TG3_VLAN_TAG_USED
14315 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14316#endif
14317#ifdef CONFIG_NET_POLL_CONTROLLER
14318 .ndo_poll_controller = tg3_poll_controller,
14319#endif
14320};
14321
14322static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14323 .ndo_open = tg3_open,
14324 .ndo_stop = tg3_close,
14325 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14326 .ndo_get_stats = tg3_get_stats,
14327 .ndo_validate_addr = eth_validate_addr,
14328 .ndo_set_multicast_list = tg3_set_rx_mode,
14329 .ndo_set_mac_address = tg3_set_mac_addr,
14330 .ndo_do_ioctl = tg3_ioctl,
14331 .ndo_tx_timeout = tg3_tx_timeout,
14332 .ndo_change_mtu = tg3_change_mtu,
14333#if TG3_VLAN_TAG_USED
14334 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14335#endif
14336#ifdef CONFIG_NET_POLL_CONTROLLER
14337 .ndo_poll_controller = tg3_poll_controller,
14338#endif
14339};
14340
1da177e4
LT		 14341static int __devinit tg3_init_one(struct pci_dev *pdev,
14342 const struct pci_device_id *ent)
14343{
14344 static int tg3_version_printed = 0;
1da177e4
LT		 14345 struct net_device *dev;
14346 struct tg3 *tp;
646c9edd
MC		 14347 int i, err, pm_cap;
14348 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14349 char str[40];
72f2afb8 14350 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14351
14352 if (tg3_version_printed++ == 0)
14353 printk(KERN_INFO "%s", version);
14354
14355 err = pci_enable_device(pdev);
14356 if (err) {
14357 printk(KERN_ERR PFX "Cannot enable PCI device, "
14358 "aborting.\n");
14359 return err;
14360 }
14361
1da177e4
LT		 14362 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14363 if (err) {
14364 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14365 "aborting.\n");
14366 goto err_out_disable_pdev;
14367 }
14368
14369 pci_set_master(pdev);
14370
14371 /* Find power-management capability. */
14372 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14373 if (pm_cap == 0) {
14374 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14375 "aborting.\n");
14376 err = -EIO;
14377 goto err_out_free_res;
14378 }
14379
fe5f5787 14380 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14381 if (!dev) {
14382 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14383 err = -ENOMEM;
14384 goto err_out_free_res;
14385 }
14386
1da177e4
LT		 14387 SET_NETDEV_DEV(dev, &pdev->dev);
14388
1da177e4
LT		 14389#if TG3_VLAN_TAG_USED
14390 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14391#endif
14392
14393 tp = netdev_priv(dev);
14394 tp->pdev = pdev;
14395 tp->dev = dev;
14396 tp->pm_cap = pm_cap;
1da177e4
LT		 14397 tp->rx_mode = TG3_DEF_RX_MODE;
14398 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14399
1da177e4
LT		 14400 if (tg3_debug > 0)
14401 tp->msg_enable = tg3_debug;
14402 else
14403 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14404
14405 /* The word/byte swap controls here control register access byte
14406 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14407 * setting below.
14408 */
14409 tp->misc_host_ctrl =
14410 MISC_HOST_CTRL_MASK_PCI_INT |
14411 MISC_HOST_CTRL_WORD_SWAP |
14412 MISC_HOST_CTRL_INDIR_ACCESS |
14413 MISC_HOST_CTRL_PCISTATE_RW;
14414
14415 /* The NONFRM (non-frame) byte/word swap controls take effect
14416 * on descriptor entries, anything which isn't packet data.
14417 *
14418 * The StrongARM chips on the board (one for tx, one for rx)
14419 * are running in big-endian mode.
14420 */
14421 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14422 GRC_MODE_WSWAP_NONFRM_DATA);
14423#ifdef __BIG_ENDIAN
14424 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14425#endif
14426 spin_lock_init(&tp->lock);
1da177e4 14427 spin_lock_init(&tp->indirect_lock);
c4028958 14428 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14429
d5fe488a 14430 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14431 if (!tp->regs) {
1da177e4
LT		 14432 printk(KERN_ERR PFX "Cannot map device registers, "
14433 "aborting.\n");
14434 err = -ENOMEM;
14435 goto err_out_free_dev;
14436 }
14437
14438 tg3_init_link_config(tp);
14439
1da177e4
LT		 14440 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14441 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14442
1da177e4 14443 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14444 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14445 dev->irq = pdev->irq;
1da177e4
LT		 14446
14447 err = tg3_get_invariants(tp);
14448 if (err) {
14449 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14450 "aborting.\n");
14451 goto err_out_iounmap;
14452 }
14453
615774fe
MC		 14454 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14455 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14456 dev->netdev_ops = &tg3_netdev_ops;
14457 else
14458 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14459
14460
4a29cc2e
MC		 14461 /* The EPB bridge inside 5714, 5715, and 5780 and any
14462 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14463 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14464 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14465 * do DMA address check in tg3_start_xmit().
14466 */
4a29cc2e 14467 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14468 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14469 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14470 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14471#ifdef CONFIG_HIGHMEM
6a35528a 14472 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14473#endif
4a29cc2e 14474 } else
6a35528a 14475 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14476
14477 /* Configure DMA attributes. */
284901a9 14478 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14479 err = pci_set_dma_mask(pdev, dma_mask);
14480 if (!err) {
14481 dev->features |= NETIF_F_HIGHDMA;
14482 err = pci_set_consistent_dma_mask(pdev,
14483 persist_dma_mask);
14484 if (err < 0) {
14485 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14486 "DMA for consistent allocations\n");
14487 goto err_out_iounmap;
14488 }
14489 }
14490 }
284901a9
YH		 14491 if (err || dma_mask == DMA_BIT_MASK(32)) {
14492 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14493 if (err) {
14494 printk(KERN_ERR PFX "No usable DMA configuration, "
14495 "aborting.\n");
14496 goto err_out_iounmap;
14497 }
14498 }
14499
fdfec172 14500 tg3_init_bufmgr_config(tp);
1da177e4 14501
507399f1
MC		 14502 /* Selectively allow TSO based on operating conditions */
14503 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14504 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14505 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14506 else {
14507 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14508 tp->fw_needed = NULL;
1da177e4 14509 }
507399f1
MC		 14510
14511 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14512 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14513
4e3a7aaa
MC		 14514 /* TSO is on by default on chips that support hardware TSO.
14515 * Firmware TSO on older chips gives lower performance, so it
14516 * is off by default, but can be enabled using ethtool.
14517 */
e849cdc3
MC		 14518 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14519 (dev->features & NETIF_F_IP_CSUM))
14520 dev->features |= NETIF_F_TSO;
14521
14522 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14523 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14524 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14525 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14526 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14527 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14528 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14529 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14532 dev->features |= NETIF_F_TSO_ECN;
b0026624 14533 }
1da177e4 14534
1da177e4
LT		 14535 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14536 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14537 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14538 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14539 tp->rx_pending = 63;
14540 }
14541
1da177e4
LT		 14542 err = tg3_get_device_address(tp);
14543 if (err) {
14544 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14545 "aborting.\n");
026a6c21 14546 goto err_out_iounmap;
1da177e4
LT		 14547 }
14548
c88864df 14549 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14550 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14551 if (!tp->aperegs) {
c88864df
MC		 14552 printk(KERN_ERR PFX "Cannot map APE registers, "
14553 "aborting.\n");
14554 err = -ENOMEM;
026a6c21 14555 goto err_out_iounmap;
c88864df
MC		 14556 }
14557
14558 tg3_ape_lock_init(tp);
7fd76445
MC		 14559
14560 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14561 tg3_read_dash_ver(tp);
c88864df
MC		 14562 }
14563
1da177e4
LT		 14564 /*
14565 * Reset chip in case UNDI or EFI driver did not shutdown
14566 * DMA self test will enable WDMAC and we'll see (spurious)
14567 * pending DMA on the PCI bus at that point.
14568 */
14569 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14570 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14571 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14572 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14573 }
14574
14575 err = tg3_test_dma(tp);
14576 if (err) {
14577 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14578 goto err_out_apeunmap;
1da177e4
LT		 14579 }
14580
1da177e4
LT		 14581 /* flow control autonegotiation is default behavior */
14582 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14583 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14584
78f90dcf
MC		 14585 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14586 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14587 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14588 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14589 struct tg3_napi *tnapi = &tp->napi[i];
14590
14591 tnapi->tp = tp;
14592 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14593
14594 tnapi->int_mbox = intmbx;
14595 if (i < 4)
14596 intmbx += 0x8;
14597 else
14598 intmbx += 0x4;
14599
14600 tnapi->consmbox = rcvmbx;
14601 tnapi->prodmbox = sndmbx;
14602
14603 if (i) {
14604 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14605 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14606 } else {
14607 tnapi->coal_now = HOSTCC_MODE_NOW;
14608 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14609 }
14610
14611 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14612 break;
14613
14614 /*
14615 * If we support MSIX, we'll be using RSS. If we're using
14616 * RSS, the first vector only handles link interrupts and the
14617 * remaining vectors handle rx and tx interrupts. Reuse the
14618 * mailbox values for the next iteration. The values we setup
14619 * above are still useful for the single vectored mode.
14620 */
14621 if (!i)
14622 continue;
14623
14624 rcvmbx += 0x8;
14625
14626 if (sndmbx & 0x4)
14627 sndmbx -= 0x4;
14628 else
14629 sndmbx += 0xc;
14630 }
14631
15f9850d
DM		 14632 tg3_init_coal(tp);
14633
c49a1561
MC		 14634 pci_set_drvdata(pdev, dev);
14635
1da177e4
LT		 14636 err = register_netdev(dev);
14637 if (err) {
14638 printk(KERN_ERR PFX "Cannot register net device, "
14639 "aborting.\n");
0d3031d9 14640 goto err_out_apeunmap;
1da177e4
LT		 14641 }
14642
df59c940 14643 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14644 dev->name,
14645 tp->board_part_number,
14646 tp->pci_chip_rev_id,
f9804ddb 14647 tg3_bus_string(tp, str),
e174961c 14648 dev->dev_addr);
1da177e4 14649
3f0e3ad7
MC		 14650 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14651 struct phy_device *phydev;
14652 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14653 printk(KERN_INFO
14654 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14655 tp->dev->name, phydev->drv->name,
14656 dev_name(&phydev->dev));
14657 } else
df59c940
MC		 14658 printk(KERN_INFO
14659 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14660 tp->dev->name, tg3_phy_string(tp),
14661 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14662 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14663 "10/100/1000Base-T")),
14664 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14665
14666 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14667 dev->name,
14668 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14669 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14670 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14671 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14672 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14673 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14674 dev->name, tp->dma_rwctrl,
284901a9 14675 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14676 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14677
14678 return 0;
14679
0d3031d9
MC		 14680err_out_apeunmap:
14681 if (tp->aperegs) {
14682 iounmap(tp->aperegs);
14683 tp->aperegs = NULL;
14684 }
14685
1da177e4 14686err_out_iounmap:
6892914f
MC		 14687 if (tp->regs) {
14688 iounmap(tp->regs);
22abe310 14689 tp->regs = NULL;
6892914f 14690 }
1da177e4
LT		 14691
14692err_out_free_dev:
14693 free_netdev(dev);
14694
14695err_out_free_res:
14696 pci_release_regions(pdev);
14697
14698err_out_disable_pdev:
14699 pci_disable_device(pdev);
14700 pci_set_drvdata(pdev, NULL);
14701 return err;
14702}
14703
14704static void __devexit tg3_remove_one(struct pci_dev *pdev)
14705{
14706 struct net_device *dev = pci_get_drvdata(pdev);
14707
14708 if (dev) {
14709 struct tg3 *tp = netdev_priv(dev);
14710
077f849d
JSR		 14711 if (tp->fw)
14712 release_firmware(tp->fw);
14713
7faa006f 14714 flush_scheduled_work();
158d7abd 14715
b02fd9e3
MC		 14716 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14717 tg3_phy_fini(tp);
158d7abd 14718 tg3_mdio_fini(tp);
b02fd9e3 14719 }
158d7abd 14720
1da177e4 14721 unregister_netdev(dev);
0d3031d9
MC		 14722 if (tp->aperegs) {
14723 iounmap(tp->aperegs);
14724 tp->aperegs = NULL;
14725 }
6892914f
MC		 14726 if (tp->regs) {
14727 iounmap(tp->regs);
22abe310 14728 tp->regs = NULL;
6892914f 14729 }
1da177e4
LT		 14730 free_netdev(dev);
14731 pci_release_regions(pdev);
14732 pci_disable_device(pdev);
14733 pci_set_drvdata(pdev, NULL);
14734 }
14735}
14736
14737static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14738{
14739 struct net_device *dev = pci_get_drvdata(pdev);
14740 struct tg3 *tp = netdev_priv(dev);
12dac075 14741 pci_power_t target_state;
1da177e4
LT		 14742 int err;
14743
3e0c95fd
MC		 14744 /* PCI register 4 needs to be saved whether netif_running() or not.
14745 * MSI address and data need to be saved if using MSI and
14746 * netif_running().
14747 */
14748 pci_save_state(pdev);
14749
1da177e4
LT		 14750 if (!netif_running(dev))
14751 return 0;
14752
7faa006f 14753 flush_scheduled_work();
b02fd9e3 14754 tg3_phy_stop(tp);
1da177e4
LT		 14755 tg3_netif_stop(tp);
14756
14757 del_timer_sync(&tp->timer);
14758
f47c11ee 14759 tg3_full_lock(tp, 1);
1da177e4 14760 tg3_disable_ints(tp);
f47c11ee 14761 tg3_full_unlock(tp);
1da177e4
LT		 14762
14763 netif_device_detach(dev);
14764
f47c11ee 14765 tg3_full_lock(tp, 0);
944d980e 14766 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14767 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14768 tg3_full_unlock(tp);
1da177e4 14769
12dac075
RW		 14770 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14771
14772 err = tg3_set_power_state(tp, target_state);
1da177e4 14773 if (err) {
b02fd9e3
MC		 14774 int err2;
14775
f47c11ee 14776 tg3_full_lock(tp, 0);
1da177e4 14777
6a9eba15 14778 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14779 err2 = tg3_restart_hw(tp, 1);
14780 if (err2)
b9ec6c1b 14781 goto out;
1da177e4
LT		 14782
14783 tp->timer.expires = jiffies + tp->timer_offset;
14784 add_timer(&tp->timer);
14785
14786 netif_device_attach(dev);
14787 tg3_netif_start(tp);
14788
b9ec6c1b 14789out:
f47c11ee 14790 tg3_full_unlock(tp);
b02fd9e3
MC		 14791
14792 if (!err2)
14793 tg3_phy_start(tp);
1da177e4
LT		 14794 }
14795
14796 return err;
14797}
14798
14799static int tg3_resume(struct pci_dev *pdev)
14800{
14801 struct net_device *dev = pci_get_drvdata(pdev);
14802 struct tg3 *tp = netdev_priv(dev);
14803 int err;
14804
3e0c95fd
MC		 14805 pci_restore_state(tp->pdev);
14806
1da177e4
LT		 14807 if (!netif_running(dev))
14808 return 0;
14809
bc1c7567 14810 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14811 if (err)
14812 return err;
14813
14814 netif_device_attach(dev);
14815
f47c11ee 14816 tg3_full_lock(tp, 0);
1da177e4 14817
6a9eba15 14818 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14819 err = tg3_restart_hw(tp, 1);
14820 if (err)
14821 goto out;
1da177e4
LT		 14822
14823 tp->timer.expires = jiffies + tp->timer_offset;
14824 add_timer(&tp->timer);
14825
1da177e4
LT		 14826 tg3_netif_start(tp);
14827
b9ec6c1b 14828out:
f47c11ee 14829 tg3_full_unlock(tp);
1da177e4 14830
b02fd9e3
MC		 14831 if (!err)
14832 tg3_phy_start(tp);
14833
b9ec6c1b 14834 return err;
1da177e4
LT		 14835}
14836
14837static struct pci_driver tg3_driver = {
14838 .name = DRV_MODULE_NAME,
14839 .id_table = tg3_pci_tbl,
14840 .probe = tg3_init_one,
14841 .remove = __devexit_p(tg3_remove_one),
14842 .suspend = tg3_suspend,
14843 .resume = tg3_resume
14844};
14845
14846static int __init tg3_init(void)
14847{
29917620 14848 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14849}
14850
14851static void __exit tg3_cleanup(void)
14852{
14853 pci_unregister_driver(&tg3_driver);
14854}
14855
14856module_init(tg3_init);
14857module_exit(tg3_cleanup);
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