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be2net: Bump up the driver version number
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
c5d5d172
MC		 71#define DRV_MODULE_VERSION "3.104"
72#define DRV_MODULE_RELDATE "November 13, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
177static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6
MC		 244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
13185217
HK		 247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
254 {}
1da177e4
LT		 255};
256
257MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
258
50da859d 259static const struct {
1da177e4
LT		 260 const char string[ETH_GSTRING_LEN];
261} ethtool_stats_keys[TG3_NUM_STATS] = {
262 { "rx_octets" },
263 { "rx_fragments" },
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
267 { "rx_fcs_errors" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
274 { "rx_jabbers" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
288
289 { "tx_octets" },
290 { "tx_collisions" },
291
292 { "tx_xon_sent" },
293 { "tx_xoff_sent" },
294 { "tx_flow_control" },
295 { "tx_mac_errors" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
298 { "tx_deferred" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
319 { "tx_discards" },
320 { "tx_errors" },
321
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
324 { "rxbds_empty" },
325 { "rx_discards" },
326 { "rx_errors" },
327 { "rx_threshold_hit" },
328
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
332
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
335 { "nic_irqs" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
338};
339
50da859d 340static const struct {
4cafd3f5
MC		 341 const char string[ETH_GSTRING_LEN];
342} ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
349};
350
b401e9e2
MC		 351static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
352{
353 writel(val, tp->regs + off);
354}
355
356static u32 tg3_read32(struct tg3 *tp, u32 off)
357{
6aa20a22 358 return (readl(tp->regs + off));
b401e9e2
MC		 359}
360
0d3031d9
MC		 361static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
362{
363 writel(val, tp->aperegs + off);
364}
365
366static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
367{
368 return (readl(tp->aperegs + off));
369}
370
1da177e4
LT		 371static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
372{
6892914f
MC		 373 unsigned long flags;
374
375 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 379}
380
381static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
382{
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
1da177e4
LT		 385}
386
6892914f 387static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 388{
6892914f
MC		 389 unsigned long flags;
390 u32 val;
391
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
396 return val;
397}
398
399static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
400{
401 unsigned long flags;
402
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
406 return;
407 }
66711e66 408 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
1da177e4 412 }
6892914f
MC		 413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
421 */
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
423 (val == 0x1)) {
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
426 }
427}
428
429static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
430{
431 unsigned long flags;
432 u32 val;
433
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
438 return val;
439}
440
b401e9e2
MC		 441/* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
445 */
446static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 447{
b401e9e2
MC		 448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
452 else {
453 /* Posted method */
454 tg3_write32(tp, off, val);
455 if (usec_wait)
456 udelay(usec_wait);
457 tp->read32(tp, off);
458 }
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
461 */
462 if (usec_wait)
463 udelay(usec_wait);
1da177e4
LT		 464}
465
09ee929c
MC		 466static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
467{
468 tp->write32_mbox(tp, off, val);
6892914f
MC		 469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
09ee929c
MC		 472}
473
20094930 474static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 475{
476 void __iomem *mbox = tp->regs + off;
477 writel(val, mbox);
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
479 writel(val, mbox);
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
481 readl(mbox);
482}
483
b5d3772c
MC		 484static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
485{
486 return (readl(tp->regs + off + GRCMBOX_BASE));
487}
488
489static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
490{
491 writel(val, tp->regs + off + GRCMBOX_BASE);
492}
493
20094930 494#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 495#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 496#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 498#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 499
500#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 501#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 503#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 504
505static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
506{
6892914f
MC		 507 unsigned long flags;
508
b5d3772c
MC		 509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
511 return;
512
6892914f 513 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 517
bbadf503
MC		 518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
520 } else {
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 523
bbadf503
MC		 524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
526 }
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 528}
529
1da177e4
LT		 530static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
531{
6892914f
MC		 532 unsigned long flags;
533
b5d3772c
MC		 534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
536 *val = 0;
537 return;
538 }
539
6892914f 540 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 544
bbadf503
MC		 545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
547 } else {
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
550
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
553 }
6892914f 554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 555}
556
0d3031d9
MC		 557static void tg3_ape_lock_init(struct tg3 *tp)
558{
559 int i;
560
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
565}
566
567static int tg3_ape_lock(struct tg3 *tp, int locknum)
568{
569 int i, off;
570 int ret = 0;
571 u32 status;
572
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
574 return 0;
575
576 switch (locknum) {
77b483f1 577 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 578 case TG3_APE_LOCK_MEM:
579 break;
580 default:
581 return -EINVAL;
582 }
583
584 off = 4 * locknum;
585
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
587
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
592 break;
593 udelay(10);
594 }
595
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
600
601 ret = -EBUSY;
602 }
603
604 return ret;
605}
606
607static void tg3_ape_unlock(struct tg3 *tp, int locknum)
608{
609 int off;
610
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
612 return;
613
614 switch (locknum) {
77b483f1 615 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 616 case TG3_APE_LOCK_MEM:
617 break;
618 default:
619 return;
620 }
621
622 off = 4 * locknum;
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
624}
625
1da177e4
LT		 626static void tg3_disable_ints(struct tg3 *tp)
627{
89aeb3bc
MC		 628 int i;
629
1da177e4
LT		 630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 634}
635
1da177e4
LT		 636static void tg3_enable_ints(struct tg3 *tp)
637{
89aeb3bc
MC		 638 int i;
639 u32 coal_now = 0;
640
bbe832c0
MC		 641 tp->irq_sync = 0;
642 wmb();
643
1da177e4
LT		 644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 646
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 652
89aeb3bc
MC		 653 coal_now |= tnapi->coal_now;
654 }
f19af9c2
MC		 655
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
660 else
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 663}
664
17375d25 665static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 666{
17375d25 667 struct tg3 *tp = tnapi->tp;
898a56f8 668 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 669 unsigned int work_exists = 0;
670
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
676 work_exists = 1;
677 }
678 /* check for RX/TX work to do */
f3f3f27e 679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 681 work_exists = 1;
682
683 return work_exists;
684}
685
17375d25 686/* tg3_int_reenable
04237ddd
MC		 687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
6aa20a22 689 * which reenables interrupts
1da177e4 690 */
17375d25 691static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 692{
17375d25
MC		 693 struct tg3 *tp = tnapi->tp;
694
898a56f8 695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 696 mmiowb();
697
fac9b83e
DM		 698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
701 */
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 703 tg3_has_work(tnapi))
04237ddd 704 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 706}
707
fed97810
MC		 708static void tg3_napi_disable(struct tg3 *tp)
709{
710 int i;
711
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
714}
715
716static void tg3_napi_enable(struct tg3 *tp)
717{
718 int i;
719
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
722}
723
1da177e4
LT		 724static inline void tg3_netif_stop(struct tg3 *tp)
725{
bbe832c0 726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 727 tg3_napi_disable(tp);
1da177e4
LT		 728 netif_tx_disable(tp->dev);
729}
730
731static inline void tg3_netif_start(struct tg3 *tp)
732{
fe5f5787
MC		 733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
1da177e4 736 */
fe5f5787
MC		 737 netif_tx_wake_all_queues(tp->dev);
738
fed97810
MC		 739 tg3_napi_enable(tp);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 741 tg3_enable_ints(tp);
1da177e4
LT		 742}
743
744static void tg3_switch_clocks(struct tg3 *tp)
745{
f6eb9b1f 746 u32 clock_ctrl;
1da177e4
LT		 747 u32 orig_clock_ctrl;
748
795d01c5
MC		 749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 751 return;
752
f6eb9b1f
MC		 753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
754
1da177e4
LT		 755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
758 0x1f);
759 tp->pci_clock_ctrl = clock_ctrl;
760
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 765 }
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
768 clock_ctrl |
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
770 40);
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
773 40);
1da177e4 774 }
b401e9e2 775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 776}
777
778#define PHY_BUSY_LOOPS 5000
779
780static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
781{
782 u32 frame_val;
783 unsigned int loops;
784 int ret;
785
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
787 tw32_f(MAC_MI_MODE,
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
789 udelay(80);
790 }
791
792 *val = 0x0;
793
882e9793 794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 799
1da177e4
LT		 800 tw32_f(MAC_MI_COM, frame_val);
801
802 loops = PHY_BUSY_LOOPS;
803 while (loops != 0) {
804 udelay(10);
805 frame_val = tr32(MAC_MI_COM);
806
807 if ((frame_val & MI_COM_BUSY) == 0) {
808 udelay(5);
809 frame_val = tr32(MAC_MI_COM);
810 break;
811 }
812 loops -= 1;
813 }
814
815 ret = -EBUSY;
816 if (loops != 0) {
817 *val = frame_val & MI_COM_DATA_MASK;
818 ret = 0;
819 }
820
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
823 udelay(80);
824 }
825
826 return ret;
827}
828
829static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
830{
831 u32 frame_val;
832 unsigned int loops;
833 int ret;
834
7f97a4bd 835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
837 return 0;
838
1da177e4
LT		 839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
840 tw32_f(MAC_MI_MODE,
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
842 udelay(80);
843 }
844
882e9793 845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 851
1da177e4
LT		 852 tw32_f(MAC_MI_COM, frame_val);
853
854 loops = PHY_BUSY_LOOPS;
855 while (loops != 0) {
856 udelay(10);
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
859 udelay(5);
860 frame_val = tr32(MAC_MI_COM);
861 break;
862 }
863 loops -= 1;
864 }
865
866 ret = -EBUSY;
867 if (loops != 0)
868 ret = 0;
869
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
872 udelay(80);
873 }
874
875 return ret;
876}
877
95e2869a
MC		 878static int tg3_bmcr_reset(struct tg3 *tp)
879{
880 u32 phy_control;
881 int limit, err;
882
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
885 */
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
888 if (err != 0)
889 return -EBUSY;
890
891 limit = 5000;
892 while (limit--) {
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 if ((phy_control & BMCR_RESET) == 0) {
898 udelay(40);
899 break;
900 }
901 udelay(10);
902 }
d4675b52 903 if (limit < 0)
95e2869a
MC		 904 return -EBUSY;
905
906 return 0;
907}
908
158d7abd
MC		 909static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
910{
3d16543d 911 struct tg3 *tp = bp->priv;
158d7abd
MC		 912 u32 val;
913
24bb4fb6 914 spin_lock_bh(&tp->lock);
158d7abd
MC		 915
916 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 917 val = -EIO;
918
919 spin_unlock_bh(&tp->lock);
158d7abd
MC		 920
921 return val;
922}
923
924static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
925{
3d16543d 926 struct tg3 *tp = bp->priv;
24bb4fb6 927 u32 ret = 0;
158d7abd 928
24bb4fb6 929 spin_lock_bh(&tp->lock);
158d7abd
MC		 930
931 if (tg3_writephy(tp, reg, val))
24bb4fb6 932 ret = -EIO;
158d7abd 933
24bb4fb6
MC		 934 spin_unlock_bh(&tp->lock);
935
936 return ret;
158d7abd
MC		 937}
938
939static int tg3_mdio_reset(struct mii_bus *bp)
940{
941 return 0;
942}
943
9c61d6bc 944static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 945{
946 u32 val;
fcb389df 947 struct phy_device *phydev;
a9daf367 948
3f0e3ad7 949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
c73430d0 952 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 953 val = MAC_PHYCFG2_50610_LED_MODES;
954 break;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
957 break;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
960 break;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
963 break;
964 default:
a9daf367 965 return;
fcb389df
MC		 966 }
967
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
970
971 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 975 tw32(MAC_PHYCFG1, val);
976
977 return;
978 }
979
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
987
988 tw32(MAC_PHYCFG2, val);
a9daf367 989
bb85fbb6
MC		 990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
998 }
bb85fbb6
MC		 999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
a9daf367 1002
a9daf367
MC		 1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
fcb389df 1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1021 }
1022 tw32(MAC_EXT_RGMII_MODE, val);
1023}
1024
158d7abd
MC		 1025static void tg3_mdio_start(struct tg3 *tp)
1026{
158d7abd
MC		 1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1029 udelay(80);
a9daf367 1030
882e9793
MC		 1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1033
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035 if (funcnum)
1036 tp->phy_addr = 2;
1037 else
1038 tp->phy_addr = 1;
1039
1040 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041 if (is_serdes)
1042 tp->phy_addr += 7;
1043 } else
3f0e3ad7 1044 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1045
9c61d6bc
MC		 1046 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048 tg3_mdio_config_5785(tp);
158d7abd
MC		 1049}
1050
158d7abd
MC		 1051static int tg3_mdio_init(struct tg3 *tp)
1052{
1053 int i;
1054 u32 reg;
a9daf367 1055 struct phy_device *phydev;
158d7abd
MC		 1056
1057 tg3_mdio_start(tp);
1058
1059 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061 return 0;
1062
298cf9be
LB		 1063 tp->mdio_bus = mdiobus_alloc();
1064 if (tp->mdio_bus == NULL)
1065 return -ENOMEM;
158d7abd 1066
298cf9be
LB		 1067 tp->mdio_bus->name = "tg3 mdio bus";
1068 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1069 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1070 tp->mdio_bus->priv = tp;
1071 tp->mdio_bus->parent = &tp->pdev->dev;
1072 tp->mdio_bus->read = &tg3_mdio_read;
1073 tp->mdio_bus->write = &tg3_mdio_write;
1074 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1075 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1076 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1077
1078 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1079 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1080
1081 /* The bus registration will look for all the PHYs on the mdio bus.
1082 * Unfortunately, it does not ensure the PHY is powered up before
1083 * accessing the PHY ID registers. A chip reset is the
1084 * quickest way to bring the device back to an operational state..
1085 */
1086 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087 tg3_bmcr_reset(tp);
1088
298cf9be 1089 i = mdiobus_register(tp->mdio_bus);
a9daf367 1090 if (i) {
158d7abd
MC		 1091 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092 tp->dev->name, i);
9c61d6bc 1093 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1094 return i;
1095 }
158d7abd 1096
3f0e3ad7 1097 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1098
9c61d6bc
MC		 1099 if (!phydev || !phydev->drv) {
1100 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101 mdiobus_unregister(tp->mdio_bus);
1102 mdiobus_free(tp->mdio_bus);
1103 return -ENODEV;
1104 }
1105
1106 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1107 case TG3_PHY_ID_BCM57780:
1108 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1109 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1110 break;
a9daf367 1111 case TG3_PHY_ID_BCM50610:
c73430d0 1112 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1113 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1114 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1115 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1116 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1117 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1123 /* fallthru */
1124 case TG3_PHY_ID_RTL8211C:
1125 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1126 break;
fcb389df 1127 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1128 case TG3_PHY_ID_BCMAC131:
1129 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1130 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1131 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1132 break;
1133 }
1134
9c61d6bc
MC		 1135 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138 tg3_mdio_config_5785(tp);
a9daf367
MC		 1139
1140 return 0;
158d7abd
MC		 1141}
1142
1143static void tg3_mdio_fini(struct tg3 *tp)
1144{
1145 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1147 mdiobus_unregister(tp->mdio_bus);
1148 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1149 }
1150}
1151
4ba526ce
MC		 1152/* tp->lock is held. */
1153static inline void tg3_generate_fw_event(struct tg3 *tp)
1154{
1155 u32 val;
1156
1157 val = tr32(GRC_RX_CPU_EVENT);
1158 val |= GRC_RX_CPU_DRIVER_EVENT;
1159 tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161 tp->last_event_jiffies = jiffies;
1162}
1163
1164#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
95e2869a
MC		 1166/* tp->lock is held. */
1167static void tg3_wait_for_event_ack(struct tg3 *tp)
1168{
1169 int i;
4ba526ce
MC		 1170 unsigned int delay_cnt;
1171 long time_remain;
1172
1173 /* If enough time has passed, no wait is necessary. */
1174 time_remain = (long)(tp->last_event_jiffies + 1 +
1175 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176 (long)jiffies;
1177 if (time_remain < 0)
1178 return;
1179
1180 /* Check if we can shorten the wait time. */
1181 delay_cnt = jiffies_to_usecs(time_remain);
1182 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1185
4ba526ce 1186 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1187 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188 break;
4ba526ce 1189 udelay(8);
95e2869a
MC		 1190 }
1191}
1192
1193/* tp->lock is held. */
1194static void tg3_ump_link_report(struct tg3 *tp)
1195{
1196 u32 reg;
1197 u32 val;
1198
1199 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1201 return;
1202
1203 tg3_wait_for_event_ack(tp);
1204
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209 val = 0;
1210 if (!tg3_readphy(tp, MII_BMCR, &reg))
1211 val = reg << 16;
1212 if (!tg3_readphy(tp, MII_BMSR, &reg))
1213 val |= (reg & 0xffff);
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216 val = 0;
1217 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218 val = reg << 16;
1219 if (!tg3_readphy(tp, MII_LPA, &reg))
1220 val |= (reg & 0xffff);
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223 val = 0;
1224 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226 val = reg << 16;
1227 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228 val |= (reg & 0xffff);
1229 }
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233 val = reg << 16;
1234 else
1235 val = 0;
1236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
4ba526ce 1238 tg3_generate_fw_event(tp);
95e2869a
MC		 1239}
1240
1241static void tg3_link_report(struct tg3 *tp)
1242{
1243 if (!netif_carrier_ok(tp->dev)) {
1244 if (netif_msg_link(tp))
1245 printk(KERN_INFO PFX "%s: Link is down.\n",
1246 tp->dev->name);
1247 tg3_ump_link_report(tp);
1248 } else if (netif_msg_link(tp)) {
1249 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250 tp->dev->name,
1251 (tp->link_config.active_speed == SPEED_1000 ?
1252 1000 :
1253 (tp->link_config.active_speed == SPEED_100 ?
1254 100 : 10)),
1255 (tp->link_config.active_duplex == DUPLEX_FULL ?
1256 "full" : "half"));
1257
1258 printk(KERN_INFO PFX
1259 "%s: Flow control is %s for TX and %s for RX.\n",
1260 tp->dev->name,
e18ce346 1261 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1262 "on" : "off",
e18ce346 1263 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1264 "on" : "off");
1265 tg3_ump_link_report(tp);
1266 }
1267}
1268
1269static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270{
1271 u16 miireg;
1272
e18ce346 1273 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1274 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1275 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1276 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1277 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1278 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279 else
1280 miireg = 0;
1281
1282 return miireg;
1283}
1284
1285static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286{
1287 u16 miireg;
1288
e18ce346 1289 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1290 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1291 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1292 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1293 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1294 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295 else
1296 miireg = 0;
1297
1298 return miireg;
1299}
1300
95e2869a
MC		 1301static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302{
1303 u8 cap = 0;
1304
1305 if (lcladv & ADVERTISE_1000XPAUSE) {
1306 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1308 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1309 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1310 cap = FLOW_CTRL_RX;
95e2869a
MC		 1311 } else {
1312 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1314 }
1315 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1317 cap = FLOW_CTRL_TX;
95e2869a
MC		 1318 }
1319
1320 return cap;
1321}
1322
f51f3562 1323static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1324{
b02fd9e3 1325 u8 autoneg;
f51f3562 1326 u8 flowctrl = 0;
95e2869a
MC		 1327 u32 old_rx_mode = tp->rx_mode;
1328 u32 old_tx_mode = tp->tx_mode;
1329
b02fd9e3 1330 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1331 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1332 else
1333 autoneg = tp->link_config.autoneg;
1334
1335 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1336 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1338 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1339 else
bc02ff95 1340 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1341 } else
1342 flowctrl = tp->link_config.flowctrl;
95e2869a 1343
f51f3562 1344 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1345
e18ce346 1346 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1347 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348 else
1349 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
f51f3562 1351 if (old_rx_mode != tp->rx_mode)
95e2869a 1352 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1353
e18ce346 1354 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1355 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356 else
1357 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
f51f3562 1359 if (old_tx_mode != tp->tx_mode)
95e2869a 1360 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1361}
1362
b02fd9e3
MC		 1363static void tg3_adjust_link(struct net_device *dev)
1364{
1365 u8 oldflowctrl, linkmesg = 0;
1366 u32 mac_mode, lcl_adv, rmt_adv;
1367 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1368 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1369
24bb4fb6 1370 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1371
1372 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373 MAC_MODE_HALF_DUPLEX);
1374
1375 oldflowctrl = tp->link_config.active_flowctrl;
1376
1377 if (phydev->link) {
1378 lcl_adv = 0;
1379 rmt_adv = 0;
1380
1381 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1383 else if (phydev->speed == SPEED_1000 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1385 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1386 else
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1388
1389 if (phydev->duplex == DUPLEX_HALF)
1390 mac_mode |= MAC_MODE_HALF_DUPLEX;
1391 else {
1392 lcl_adv = tg3_advert_flowctrl_1000T(
1393 tp->link_config.flowctrl);
1394
1395 if (phydev->pause)
1396 rmt_adv = LPA_PAUSE_CAP;
1397 if (phydev->asym_pause)
1398 rmt_adv |= LPA_PAUSE_ASYM;
1399 }
1400
1401 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402 } else
1403 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405 if (mac_mode != tp->mac_mode) {
1406 tp->mac_mode = mac_mode;
1407 tw32_f(MAC_MODE, tp->mac_mode);
1408 udelay(40);
1409 }
1410
fcb389df
MC		 1411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412 if (phydev->speed == SPEED_10)
1413 tw32(MAC_MI_STAT,
1414 MAC_MI_STAT_10MBPS_MODE |
1415 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416 else
1417 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418 }
1419
b02fd9e3
MC		 1420 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421 tw32(MAC_TX_LENGTHS,
1422 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423 (6 << TX_LENGTHS_IPG_SHIFT) |
1424 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425 else
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433 phydev->speed != tp->link_config.active_speed ||
1434 phydev->duplex != tp->link_config.active_duplex ||
1435 oldflowctrl != tp->link_config.active_flowctrl)
1436 linkmesg = 1;
1437
1438 tp->link_config.active_speed = phydev->speed;
1439 tp->link_config.active_duplex = phydev->duplex;
1440
24bb4fb6 1441 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1442
1443 if (linkmesg)
1444 tg3_link_report(tp);
1445}
1446
1447static int tg3_phy_init(struct tg3 *tp)
1448{
1449 struct phy_device *phydev;
1450
1451 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452 return 0;
1453
1454 /* Bring the PHY back to a known state. */
1455 tg3_bmcr_reset(tp);
1456
3f0e3ad7 1457 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1458
1459 /* Attach the MAC to the PHY. */
fb28ad35 1460 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1461 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1462 if (IS_ERR(phydev)) {
1463 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464 return PTR_ERR(phydev);
1465 }
1466
b02fd9e3 1467 /* Mask with MAC supported features. */
9c61d6bc
MC		 1468 switch (phydev->interface) {
1469 case PHY_INTERFACE_MODE_GMII:
1470 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472 phydev->supported &= (PHY_GBIT_FEATURES |
1473 SUPPORTED_Pause |
1474 SUPPORTED_Asym_Pause);
1475 break;
1476 }
1477 /* fallthru */
9c61d6bc
MC		 1478 case PHY_INTERFACE_MODE_MII:
1479 phydev->supported &= (PHY_BASIC_FEATURES |
1480 SUPPORTED_Pause |
1481 SUPPORTED_Asym_Pause);
1482 break;
1483 default:
3f0e3ad7 1484 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1485 return -EINVAL;
1486 }
1487
1488 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1489
1490 phydev->advertising = phydev->supported;
1491
b02fd9e3
MC		 1492 return 0;
1493}
1494
1495static void tg3_phy_start(struct tg3 *tp)
1496{
1497 struct phy_device *phydev;
1498
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
3f0e3ad7 1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1503
1504 if (tp->link_config.phy_is_low_power) {
1505 tp->link_config.phy_is_low_power = 0;
1506 phydev->speed = tp->link_config.orig_speed;
1507 phydev->duplex = tp->link_config.orig_duplex;
1508 phydev->autoneg = tp->link_config.orig_autoneg;
1509 phydev->advertising = tp->link_config.orig_advertising;
1510 }
1511
1512 phy_start(phydev);
1513
1514 phy_start_aneg(phydev);
1515}
1516
1517static void tg3_phy_stop(struct tg3 *tp)
1518{
1519 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520 return;
1521
3f0e3ad7 1522 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1523}
1524
1525static void tg3_phy_fini(struct tg3 *tp)
1526{
1527 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1529 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530 }
1531}
1532
b2a5c19c
MC		 1533static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534{
1535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537}
1538
7f97a4bd
MC		 1539static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540{
1541 u32 phytest;
1542
1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544 u32 phy;
1545
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 phytest | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549 if (enable)
1550 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551 else
1552 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554 }
1555 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556 }
1557}
1558
6833c043
MC		 1559static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560{
1561 u32 reg;
1562
7f97a4bd 1563 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1564 return;
1565
7f97a4bd
MC		 1566 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1567 tg3_phy_fet_toggle_apd(tp, enable);
1568 return;
1569 }
1570
6833c043
MC		 1571 reg = MII_TG3_MISC_SHDW_WREN |
1572 MII_TG3_MISC_SHDW_SCR5_SEL |
1573 MII_TG3_MISC_SHDW_SCR5_LPED |
1574 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1575 MII_TG3_MISC_SHDW_SCR5_SDTL |
1576 MII_TG3_MISC_SHDW_SCR5_C125OE;
1577 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1578 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1579
1580 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581
1582
1583 reg = MII_TG3_MISC_SHDW_WREN |
1584 MII_TG3_MISC_SHDW_APD_SEL |
1585 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1586 if (enable)
1587 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1588
1589 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1590}
1591
9ef8ca99
MC		 1592static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1593{
1594 u32 phy;
1595
1596 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1597 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1598 return;
1599
7f97a4bd 1600 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1601 u32 ephy;
1602
535ef6e1
MC		 1603 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1604 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1605
1606 tg3_writephy(tp, MII_TG3_FET_TEST,
1607 ephy | MII_TG3_FET_SHADOW_EN);
1608 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1609 if (enable)
535ef6e1 1610 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1611 else
535ef6e1
MC		 1612 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613 tg3_writephy(tp, reg, phy);
9ef8ca99 1614 }
535ef6e1 1615 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1616 }
1617 } else {
1618 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1619 MII_TG3_AUXCTL_SHDWSEL_MISC;
1620 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1621 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1622 if (enable)
1623 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1624 else
1625 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626 phy |= MII_TG3_AUXCTL_MISC_WREN;
1627 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1628 }
1629 }
1630}
1631
1da177e4
LT		 1632static void tg3_phy_set_wirespeed(struct tg3 *tp)
1633{
1634 u32 val;
1635
1636 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1637 return;
1638
1639 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1640 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1641 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1642 (val | (1 << 15) | (1 << 4)));
1643}
1644
b2a5c19c
MC		 1645static void tg3_phy_apply_otp(struct tg3 *tp)
1646{
1647 u32 otp, phy;
1648
1649 if (!tp->phy_otp)
1650 return;
1651
1652 otp = tp->phy_otp;
1653
1654 /* Enable SM_DSP clock and tx 6dB coding. */
1655 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1656 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1657 MII_TG3_AUXCTL_ACTL_TX_6DB;
1658 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1659
1660 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1661 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1662 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1663
1664 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1665 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1666 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1667
1668 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1669 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1670 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1671
1672 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1673 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1674
1675 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1677
1678 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1679 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1680 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1681
1682 /* Turn off SM_DSP clock. */
1683 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1684 MII_TG3_AUXCTL_ACTL_TX_6DB;
1685 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1686}
1687
1da177e4
LT		 1688static int tg3_wait_macro_done(struct tg3 *tp)
1689{
1690 int limit = 100;
1691
1692 while (limit--) {
1693 u32 tmp32;
1694
1695 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1696 if ((tmp32 & 0x1000) == 0)
1697 break;
1698 }
1699 }
d4675b52 1700 if (limit < 0)
1da177e4
LT		 1701 return -EBUSY;
1702
1703 return 0;
1704}
1705
1706static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1707{
1708 static const u32 test_pat[4][6] = {
1709 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1710 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1711 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1712 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1713 };
1714 int chan;
1715
1716 for (chan = 0; chan < 4; chan++) {
1717 int i;
1718
1719 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720 (chan * 0x2000) | 0x0200);
1721 tg3_writephy(tp, 0x16, 0x0002);
1722
1723 for (i = 0; i < 6; i++)
1724 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1725 test_pat[chan][i]);
1726
1727 tg3_writephy(tp, 0x16, 0x0202);
1728 if (tg3_wait_macro_done(tp)) {
1729 *resetp = 1;
1730 return -EBUSY;
1731 }
1732
1733 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734 (chan * 0x2000) | 0x0200);
1735 tg3_writephy(tp, 0x16, 0x0082);
1736 if (tg3_wait_macro_done(tp)) {
1737 *resetp = 1;
1738 return -EBUSY;
1739 }
1740
1741 tg3_writephy(tp, 0x16, 0x0802);
1742 if (tg3_wait_macro_done(tp)) {
1743 *resetp = 1;
1744 return -EBUSY;
1745 }
1746
1747 for (i = 0; i < 6; i += 2) {
1748 u32 low, high;
1749
1750 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1751 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1752 tg3_wait_macro_done(tp)) {
1753 *resetp = 1;
1754 return -EBUSY;
1755 }
1756 low &= 0x7fff;
1757 high &= 0x000f;
1758 if (low != test_pat[chan][i] ||
1759 high != test_pat[chan][i+1]) {
1760 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1761 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1762 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1763
1764 return -EBUSY;
1765 }
1766 }
1767 }
1768
1769 return 0;
1770}
1771
1772static int tg3_phy_reset_chanpat(struct tg3 *tp)
1773{
1774 int chan;
1775
1776 for (chan = 0; chan < 4; chan++) {
1777 int i;
1778
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1780 (chan * 0x2000) | 0x0200);
1781 tg3_writephy(tp, 0x16, 0x0002);
1782 for (i = 0; i < 6; i++)
1783 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1784 tg3_writephy(tp, 0x16, 0x0202);
1785 if (tg3_wait_macro_done(tp))
1786 return -EBUSY;
1787 }
1788
1789 return 0;
1790}
1791
1792static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1793{
1794 u32 reg32, phy9_orig;
1795 int retries, do_phy_reset, err;
1796
1797 retries = 10;
1798 do_phy_reset = 1;
1799 do {
1800 if (do_phy_reset) {
1801 err = tg3_bmcr_reset(tp);
1802 if (err)
1803 return err;
1804 do_phy_reset = 0;
1805 }
1806
1807 /* Disable transmitter and interrupt. */
1808 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1809 continue;
1810
1811 reg32 |= 0x3000;
1812 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1813
1814 /* Set full-duplex, 1000 mbps. */
1815 tg3_writephy(tp, MII_BMCR,
1816 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1817
1818 /* Set to master mode. */
1819 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1820 continue;
1821
1822 tg3_writephy(tp, MII_TG3_CTRL,
1823 (MII_TG3_CTRL_AS_MASTER |
1824 MII_TG3_CTRL_ENABLE_AS_MASTER));
1825
1826 /* Enable SM_DSP_CLOCK and 6dB. */
1827 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1828
1829 /* Block the PHY control access. */
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1832
1833 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1834 if (!err)
1835 break;
1836 } while (--retries);
1837
1838 err = tg3_phy_reset_chanpat(tp);
1839 if (err)
1840 return err;
1841
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1844
1845 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1846 tg3_writephy(tp, 0x16, 0x0000);
1847
1848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1850 /* Set Extended packet length bit for jumbo frames */
1851 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1852 }
1853 else {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1855 }
1856
1857 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1858
1859 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1860 reg32 &= ~0x3000;
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1862 } else if (!err)
1863 err = -EBUSY;
1864
1865 return err;
1866}
1867
1868/* This will reset the tigon3 PHY if there is no valid
1869 * link unless the FORCE argument is non-zero.
1870 */
1871static int tg3_phy_reset(struct tg3 *tp)
1872{
b2a5c19c 1873 u32 cpmuctrl;
1da177e4
LT		 1874 u32 phy_status;
1875 int err;
1876
60189ddf
MC		 1877 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1878 u32 val;
1879
1880 val = tr32(GRC_MISC_CFG);
1881 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1882 udelay(40);
1883 }
1da177e4
LT		 1884 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1885 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1886 if (err != 0)
1887 return -EBUSY;
1888
c8e1e82b
MC		 1889 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1890 netif_carrier_off(tp->dev);
1891 tg3_link_report(tp);
1892 }
1893
1da177e4
LT		 1894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1897 err = tg3_phy_reset_5703_4_5(tp);
1898 if (err)
1899 return err;
1900 goto out;
1901 }
1902
b2a5c19c
MC		 1903 cpmuctrl = 0;
1904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1905 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1906 cpmuctrl = tr32(TG3_CPMU_CTRL);
1907 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1908 tw32(TG3_CPMU_CTRL,
1909 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1910 }
1911
1da177e4
LT		 1912 err = tg3_bmcr_reset(tp);
1913 if (err)
1914 return err;
1915
b2a5c19c
MC		 1916 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1917 u32 phy;
1918
1919 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1920 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1921
1922 tw32(TG3_CPMU_CTRL, cpmuctrl);
1923 }
1924
bcb37f6c
MC		 1925 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1926 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1927 u32 val;
1928
1929 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1930 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1931 CPMU_LSPD_1000MB_MACCLK_12_5) {
1932 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1933 udelay(40);
1934 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1935 }
1936 }
1937
b2a5c19c
MC		 1938 tg3_phy_apply_otp(tp);
1939
6833c043
MC		 1940 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1941 tg3_phy_toggle_apd(tp, true);
1942 else
1943 tg3_phy_toggle_apd(tp, false);
1944
1da177e4
LT		 1945out:
1946 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1947 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1952 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953 }
1954 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1955 tg3_writephy(tp, 0x1c, 0x8d68);
1956 tg3_writephy(tp, 0x1c, 0x8d68);
1957 }
1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1959 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1964 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1965 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1966 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1967 }
c424cb24
MC		 1968 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1972 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1973 tg3_writephy(tp, MII_TG3_TEST1,
1974 MII_TG3_TEST1_TRIM_EN | 0x4);
1975 } else
1976 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1978 }
1da177e4
LT		 1979 /* Set Extended packet length bit (bit 14) on all chips that */
1980 /* support jumbo frames */
1981 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1982 /* Cannot do read-modify-write on 5401 */
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1984 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1985 u32 phy_reg;
1986
1987 /* Set bit 14 with read-modify-write to preserve other bits */
1988 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1990 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1991 }
1992
1993 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994 * jumbo frames transmission.
1995 */
8f666b07 1996 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1997 u32 phy_reg;
1998
1999 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2000 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2001 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2002 }
2003
715116a1 2004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2005 /* adjust output voltage */
535ef6e1 2006 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2007 }
2008
9ef8ca99 2009 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2010 tg3_phy_set_wirespeed(tp);
2011 return 0;
2012}
2013
2014static void tg3_frob_aux_power(struct tg3 *tp)
2015{
2016 struct tg3 *tp_peer = tp;
2017
9d26e213 2018 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2019 return;
2020
f6eb9b1f
MC		 2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2024 struct net_device *dev_peer;
2025
2026 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2027 /* remove_one() may have been run on the peer. */
8c2dc7e1 2028 if (!dev_peer)
bc1c7567
MC		 2029 tp_peer = tp;
2030 else
2031 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2032 }
2033
1da177e4 2034 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2035 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2036 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 (GRC_LCLCTRL_GPIO_OE0 |
2042 GRC_LCLCTRL_GPIO_OE1 |
2043 GRC_LCLCTRL_GPIO_OE2 |
2044 GRC_LCLCTRL_GPIO_OUTPUT0 |
2045 GRC_LCLCTRL_GPIO_OUTPUT1),
2046 100);
8d519ab2
MC		 2047 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2049 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2050 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2051 GRC_LCLCTRL_GPIO_OE1 |
2052 GRC_LCLCTRL_GPIO_OE2 |
2053 GRC_LCLCTRL_GPIO_OUTPUT0 |
2054 GRC_LCLCTRL_GPIO_OUTPUT1 |
2055 tp->grc_local_ctrl;
2056 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2057
2058 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2059 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2060
2061 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2062 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2063 } else {
2064 u32 no_gpio2;
dc56b7d4 2065 u32 grc_local_ctrl = 0;
1da177e4
LT		 2066
2067 if (tp_peer != tp &&
2068 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2069 return;
2070
dc56b7d4
MC		 2071 /* Workaround to prevent overdrawing Amps. */
2072 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2073 ASIC_REV_5714) {
2074 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2075 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076 grc_local_ctrl, 100);
dc56b7d4
MC		 2077 }
2078
1da177e4
LT		 2079 /* On 5753 and variants, GPIO2 cannot be used. */
2080 no_gpio2 = tp->nic_sram_data_cfg &
2081 NIC_SRAM_DATA_CFG_NO_GPIO2;
2082
dc56b7d4 2083 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2084 GRC_LCLCTRL_GPIO_OE1 |
2085 GRC_LCLCTRL_GPIO_OE2 |
2086 GRC_LCLCTRL_GPIO_OUTPUT1 |
2087 GRC_LCLCTRL_GPIO_OUTPUT2;
2088 if (no_gpio2) {
2089 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2090 GRC_LCLCTRL_GPIO_OUTPUT2);
2091 }
b401e9e2
MC		 2092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093 grc_local_ctrl, 100);
1da177e4
LT		 2094
2095 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2096
b401e9e2
MC		 2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 grc_local_ctrl, 100);
1da177e4
LT		 2099
2100 if (!no_gpio2) {
2101 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2102 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103 grc_local_ctrl, 100);
1da177e4
LT		 2104 }
2105 }
2106 } else {
2107 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2108 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2109 if (tp_peer != tp &&
2110 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2111 return;
2112
b401e9e2
MC		 2113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114 (GRC_LCLCTRL_GPIO_OE1 |
2115 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2116
b401e9e2
MC		 2117 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2119
b401e9e2
MC		 2120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121 (GRC_LCLCTRL_GPIO_OE1 |
2122 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2123 }
2124 }
2125}
2126
e8f3f6ca
MC		 2127static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2128{
2129 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2130 return 1;
2131 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2132 if (speed != SPEED_10)
2133 return 1;
2134 } else if (speed == SPEED_10)
2135 return 1;
2136
2137 return 0;
2138}
2139
1da177e4
LT		 2140static int tg3_setup_phy(struct tg3 *, int);
2141
2142#define RESET_KIND_SHUTDOWN 0
2143#define RESET_KIND_INIT 1
2144#define RESET_KIND_SUSPEND 2
2145
2146static void tg3_write_sig_post_reset(struct tg3 *, int);
2147static int tg3_halt_cpu(struct tg3 *, u32);
2148
0a459aac 2149static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2150{
ce057f01
MC		 2151 u32 val;
2152
5129724a
MC		 2153 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2155 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2156 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2157
2158 sg_dig_ctrl |=
2159 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2160 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2161 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2162 }
3f7045c1 2163 return;
5129724a 2164 }
3f7045c1 2165
60189ddf 2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2167 tg3_bmcr_reset(tp);
2168 val = tr32(GRC_MISC_CFG);
2169 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2170 udelay(40);
2171 return;
0e5f784c
MC		 2172 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2173 u32 phytest;
2174 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2175 u32 phy;
2176
2177 tg3_writephy(tp, MII_ADVERTISE, 0);
2178 tg3_writephy(tp, MII_BMCR,
2179 BMCR_ANENABLE | BMCR_ANRESTART);
2180
2181 tg3_writephy(tp, MII_TG3_FET_TEST,
2182 phytest | MII_TG3_FET_SHADOW_EN);
2183 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2184 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2185 tg3_writephy(tp,
2186 MII_TG3_FET_SHDW_AUXMODE4,
2187 phy);
2188 }
2189 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2190 }
2191 return;
0a459aac 2192 } else if (do_low_power) {
715116a1
MC		 2193 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2194 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2195
2196 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2197 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2198 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2199 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2200 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2201 }
3f7045c1 2202
15c3b696
MC		 2203 /* The PHY should not be powered down on some chips because
2204 * of bugs.
2205 */
2206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2208 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2209 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2210 return;
ce057f01 2211
bcb37f6c
MC		 2212 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2213 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2214 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2215 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2216 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2217 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2218 }
2219
15c3b696
MC		 2220 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2221}
2222
ffbcfed4
MC		 2223/* tp->lock is held. */
2224static int tg3_nvram_lock(struct tg3 *tp)
2225{
2226 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2227 int i;
2228
2229 if (tp->nvram_lock_cnt == 0) {
2230 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2231 for (i = 0; i < 8000; i++) {
2232 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2233 break;
2234 udelay(20);
2235 }
2236 if (i == 8000) {
2237 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2238 return -ENODEV;
2239 }
2240 }
2241 tp->nvram_lock_cnt++;
2242 }
2243 return 0;
2244}
2245
2246/* tp->lock is held. */
2247static void tg3_nvram_unlock(struct tg3 *tp)
2248{
2249 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2250 if (tp->nvram_lock_cnt > 0)
2251 tp->nvram_lock_cnt--;
2252 if (tp->nvram_lock_cnt == 0)
2253 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2254 }
2255}
2256
2257/* tp->lock is held. */
2258static void tg3_enable_nvram_access(struct tg3 *tp)
2259{
2260 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2261 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2262 u32 nvaccess = tr32(NVRAM_ACCESS);
2263
2264 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2265 }
2266}
2267
2268/* tp->lock is held. */
2269static void tg3_disable_nvram_access(struct tg3 *tp)
2270{
2271 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2272 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2273 u32 nvaccess = tr32(NVRAM_ACCESS);
2274
2275 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2276 }
2277}
2278
2279static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2280 u32 offset, u32 *val)
2281{
2282 u32 tmp;
2283 int i;
2284
2285 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2286 return -EINVAL;
2287
2288 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2289 EEPROM_ADDR_DEVID_MASK |
2290 EEPROM_ADDR_READ);
2291 tw32(GRC_EEPROM_ADDR,
2292 tmp |
2293 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2294 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2295 EEPROM_ADDR_ADDR_MASK) |
2296 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2297
2298 for (i = 0; i < 1000; i++) {
2299 tmp = tr32(GRC_EEPROM_ADDR);
2300
2301 if (tmp & EEPROM_ADDR_COMPLETE)
2302 break;
2303 msleep(1);
2304 }
2305 if (!(tmp & EEPROM_ADDR_COMPLETE))
2306 return -EBUSY;
2307
62cedd11
MC		 2308 tmp = tr32(GRC_EEPROM_DATA);
2309
2310 /*
2311 * The data will always be opposite the native endian
2312 * format. Perform a blind byteswap to compensate.
2313 */
2314 *val = swab32(tmp);
2315
ffbcfed4
MC		 2316 return 0;
2317}
2318
2319#define NVRAM_CMD_TIMEOUT 10000
2320
2321static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2322{
2323 int i;
2324
2325 tw32(NVRAM_CMD, nvram_cmd);
2326 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2327 udelay(10);
2328 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2329 udelay(10);
2330 break;
2331 }
2332 }
2333
2334 if (i == NVRAM_CMD_TIMEOUT)
2335 return -EBUSY;
2336
2337 return 0;
2338}
2339
2340static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2341{
2342 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346 (tp->nvram_jedecnum == JEDEC_ATMEL))
2347
2348 addr = ((addr / tp->nvram_pagesize) <<
2349 ATMEL_AT45DB0X1B_PAGE_POS) +
2350 (addr % tp->nvram_pagesize);
2351
2352 return addr;
2353}
2354
2355static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2356{
2357 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361 (tp->nvram_jedecnum == JEDEC_ATMEL))
2362
2363 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2364 tp->nvram_pagesize) +
2365 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2366
2367 return addr;
2368}
2369
e4f34110
MC		 2370/* NOTE: Data read in from NVRAM is byteswapped according to
2371 * the byteswapping settings for all other register accesses.
2372 * tg3 devices are BE devices, so on a BE machine, the data
2373 * returned will be exactly as it is seen in NVRAM. On a LE
2374 * machine, the 32-bit value will be byteswapped.
2375 */
ffbcfed4
MC		 2376static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2377{
2378 int ret;
2379
2380 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2381 return tg3_nvram_read_using_eeprom(tp, offset, val);
2382
2383 offset = tg3_nvram_phys_addr(tp, offset);
2384
2385 if (offset > NVRAM_ADDR_MSK)
2386 return -EINVAL;
2387
2388 ret = tg3_nvram_lock(tp);
2389 if (ret)
2390 return ret;
2391
2392 tg3_enable_nvram_access(tp);
2393
2394 tw32(NVRAM_ADDR, offset);
2395 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2396 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2397
2398 if (ret == 0)
e4f34110 2399 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2400
2401 tg3_disable_nvram_access(tp);
2402
2403 tg3_nvram_unlock(tp);
2404
2405 return ret;
2406}
2407
a9dc529d
MC		 2408/* Ensures NVRAM data is in bytestream format. */
2409static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2410{
2411 u32 v;
a9dc529d 2412 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2413 if (!res)
a9dc529d 2414 *val = cpu_to_be32(v);
ffbcfed4
MC		 2415 return res;
2416}
2417
3f007891
MC		 2418/* tp->lock is held. */
2419static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2420{
2421 u32 addr_high, addr_low;
2422 int i;
2423
2424 addr_high = ((tp->dev->dev_addr[0] << 8) |
2425 tp->dev->dev_addr[1]);
2426 addr_low = ((tp->dev->dev_addr[2] << 24) |
2427 (tp->dev->dev_addr[3] << 16) |
2428 (tp->dev->dev_addr[4] << 8) |
2429 (tp->dev->dev_addr[5] << 0));
2430 for (i = 0; i < 4; i++) {
2431 if (i == 1 && skip_mac_1)
2432 continue;
2433 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2434 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2435 }
2436
2437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2439 for (i = 0; i < 12; i++) {
2440 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2441 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2442 }
2443 }
2444
2445 addr_high = (tp->dev->dev_addr[0] +
2446 tp->dev->dev_addr[1] +
2447 tp->dev->dev_addr[2] +
2448 tp->dev->dev_addr[3] +
2449 tp->dev->dev_addr[4] +
2450 tp->dev->dev_addr[5]) &
2451 TX_BACKOFF_SEED_MASK;
2452 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2453}
2454
bc1c7567 2455static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2456{
2457 u32 misc_host_ctrl;
0a459aac 2458 bool device_should_wake, do_low_power;
1da177e4
LT		 2459
2460 /* Make sure register accesses (indirect or otherwise)
2461 * will function correctly.
2462 */
2463 pci_write_config_dword(tp->pdev,
2464 TG3PCI_MISC_HOST_CTRL,
2465 tp->misc_host_ctrl);
2466
1da177e4 2467 switch (state) {
bc1c7567 2468 case PCI_D0:
12dac075
RW		 2469 pci_enable_wake(tp->pdev, state, false);
2470 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2471
9d26e213
MC		 2472 /* Switch out of Vaux if it is a NIC */
2473 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2474 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2475
2476 return 0;
2477
bc1c7567 2478 case PCI_D1:
bc1c7567 2479 case PCI_D2:
bc1c7567 2480 case PCI_D3hot:
1da177e4
LT		 2481 break;
2482
2483 default:
12dac075
RW		 2484 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2485 tp->dev->name, state);
1da177e4 2486 return -EINVAL;
855e1111 2487 }
5e7dfd0f
MC		 2488
2489 /* Restore the CLKREQ setting. */
2490 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2491 u16 lnkctl;
2492
2493 pci_read_config_word(tp->pdev,
2494 tp->pcie_cap + PCI_EXP_LNKCTL,
2495 &lnkctl);
2496 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2497 pci_write_config_word(tp->pdev,
2498 tp->pcie_cap + PCI_EXP_LNKCTL,
2499 lnkctl);
2500 }
2501
1da177e4
LT		 2502 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2503 tw32(TG3PCI_MISC_HOST_CTRL,
2504 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2505
05ac4cb7
MC		 2506 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2507 device_may_wakeup(&tp->pdev->dev) &&
2508 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2509
dd477003 2510 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2511 do_low_power = false;
b02fd9e3
MC		 2512 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2513 !tp->link_config.phy_is_low_power) {
2514 struct phy_device *phydev;
0a459aac 2515 u32 phyid, advertising;
b02fd9e3 2516
3f0e3ad7 2517 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2518
2519 tp->link_config.phy_is_low_power = 1;
2520
2521 tp->link_config.orig_speed = phydev->speed;
2522 tp->link_config.orig_duplex = phydev->duplex;
2523 tp->link_config.orig_autoneg = phydev->autoneg;
2524 tp->link_config.orig_advertising = phydev->advertising;
2525
2526 advertising = ADVERTISED_TP |
2527 ADVERTISED_Pause |
2528 ADVERTISED_Autoneg |
2529 ADVERTISED_10baseT_Half;
2530
2531 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2532 device_should_wake) {
b02fd9e3
MC		 2533 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2534 advertising |=
2535 ADVERTISED_100baseT_Half |
2536 ADVERTISED_100baseT_Full |
2537 ADVERTISED_10baseT_Full;
2538 else
2539 advertising |= ADVERTISED_10baseT_Full;
2540 }
2541
2542 phydev->advertising = advertising;
2543
2544 phy_start_aneg(phydev);
0a459aac
MC		 2545
2546 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2547 if (phyid != TG3_PHY_ID_BCMAC131) {
2548 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2549 if (phyid == TG3_PHY_OUI_1 ||
2550 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2551 phyid == TG3_PHY_OUI_3)
2552 do_low_power = true;
2553 }
b02fd9e3 2554 }
dd477003 2555 } else {
2023276e 2556 do_low_power = true;
0a459aac 2557
dd477003
MC		 2558 if (tp->link_config.phy_is_low_power == 0) {
2559 tp->link_config.phy_is_low_power = 1;
2560 tp->link_config.orig_speed = tp->link_config.speed;
2561 tp->link_config.orig_duplex = tp->link_config.duplex;
2562 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2563 }
1da177e4 2564
dd477003
MC		 2565 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2566 tp->link_config.speed = SPEED_10;
2567 tp->link_config.duplex = DUPLEX_HALF;
2568 tp->link_config.autoneg = AUTONEG_ENABLE;
2569 tg3_setup_phy(tp, 0);
2570 }
1da177e4
LT		 2571 }
2572
b5d3772c
MC		 2573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2574 u32 val;
2575
2576 val = tr32(GRC_VCPU_EXT_CTRL);
2577 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2578 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2579 int i;
2580 u32 val;
2581
2582 for (i = 0; i < 200; i++) {
2583 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2584 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2585 break;
2586 msleep(1);
2587 }
2588 }
a85feb8c
GZ		 2589 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2590 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2591 WOL_DRV_STATE_SHUTDOWN |
2592 WOL_DRV_WOL |
2593 WOL_SET_MAGIC_PKT);
6921d201 2594
05ac4cb7 2595 if (device_should_wake) {
1da177e4
LT		 2596 u32 mac_mode;
2597
2598 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2599 if (do_low_power) {
dd477003
MC		 2600 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2601 udelay(40);
2602 }
1da177e4 2603
3f7045c1
MC		 2604 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2605 mac_mode = MAC_MODE_PORT_MODE_GMII;
2606 else
2607 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2608
e8f3f6ca
MC		 2609 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2610 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2611 ASIC_REV_5700) {
2612 u32 speed = (tp->tg3_flags &
2613 TG3_FLAG_WOL_SPEED_100MB) ?
2614 SPEED_100 : SPEED_10;
2615 if (tg3_5700_link_polarity(tp, speed))
2616 mac_mode |= MAC_MODE_LINK_POLARITY;
2617 else
2618 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2619 }
1da177e4
LT		 2620 } else {
2621 mac_mode = MAC_MODE_PORT_MODE_TBI;
2622 }
2623
cbf46853 2624 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2625 tw32(MAC_LED_CTRL, tp->led_ctrl);
2626
05ac4cb7
MC		 2627 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2628 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2629 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2630 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2632 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2633
3bda1258
MC		 2634 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2635 mac_mode |= tp->mac_mode &
2636 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2637 if (mac_mode & MAC_MODE_APE_TX_EN)
2638 mac_mode |= MAC_MODE_TDE_ENABLE;
2639 }
2640
1da177e4
LT		 2641 tw32_f(MAC_MODE, mac_mode);
2642 udelay(100);
2643
2644 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2645 udelay(10);
2646 }
2647
2648 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2649 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2651 u32 base_val;
2652
2653 base_val = tp->pci_clock_ctrl;
2654 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2655 CLOCK_CTRL_TXCLK_DISABLE);
2656
b401e9e2
MC		 2657 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2658 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2659 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2660 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2662 /* do nothing */
85e94ced 2663 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2664 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2665 u32 newbits1, newbits2;
2666
2667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2669 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2670 CLOCK_CTRL_TXCLK_DISABLE |
2671 CLOCK_CTRL_ALTCLK);
2672 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2673 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2674 newbits1 = CLOCK_CTRL_625_CORE;
2675 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2676 } else {
2677 newbits1 = CLOCK_CTRL_ALTCLK;
2678 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679 }
2680
b401e9e2
MC		 2681 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2682 40);
1da177e4 2683
b401e9e2
MC		 2684 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2685 40);
1da177e4
LT		 2686
2687 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2688 u32 newbits3;
2689
2690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2692 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2693 CLOCK_CTRL_TXCLK_DISABLE |
2694 CLOCK_CTRL_44MHZ_CORE);
2695 } else {
2696 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2697 }
2698
b401e9e2
MC		 2699 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2700 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2701 }
2702 }
2703
05ac4cb7 2704 if (!(device_should_wake) &&
22435849 2705 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2706 tg3_power_down_phy(tp, do_low_power);
6921d201 2707
1da177e4
LT		 2708 tg3_frob_aux_power(tp);
2709
2710 /* Workaround for unstable PLL clock */
2711 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2712 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2713 u32 val = tr32(0x7d00);
2714
2715 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2716 tw32(0x7d00, val);
6921d201 2717 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2718 int err;
2719
2720 err = tg3_nvram_lock(tp);
1da177e4 2721 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2722 if (!err)
2723 tg3_nvram_unlock(tp);
6921d201 2724 }
1da177e4
LT		 2725 }
2726
bbadf503
MC		 2727 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2728
05ac4cb7 2729 if (device_should_wake)
12dac075
RW		 2730 pci_enable_wake(tp->pdev, state, true);
2731
1da177e4 2732 /* Finally, set the new power state. */
12dac075 2733 pci_set_power_state(tp->pdev, state);
1da177e4 2734
1da177e4
LT		 2735 return 0;
2736}
2737
1da177e4
LT		 2738static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2739{
2740 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2741 case MII_TG3_AUX_STAT_10HALF:
2742 *speed = SPEED_10;
2743 *duplex = DUPLEX_HALF;
2744 break;
2745
2746 case MII_TG3_AUX_STAT_10FULL:
2747 *speed = SPEED_10;
2748 *duplex = DUPLEX_FULL;
2749 break;
2750
2751 case MII_TG3_AUX_STAT_100HALF:
2752 *speed = SPEED_100;
2753 *duplex = DUPLEX_HALF;
2754 break;
2755
2756 case MII_TG3_AUX_STAT_100FULL:
2757 *speed = SPEED_100;
2758 *duplex = DUPLEX_FULL;
2759 break;
2760
2761 case MII_TG3_AUX_STAT_1000HALF:
2762 *speed = SPEED_1000;
2763 *duplex = DUPLEX_HALF;
2764 break;
2765
2766 case MII_TG3_AUX_STAT_1000FULL:
2767 *speed = SPEED_1000;
2768 *duplex = DUPLEX_FULL;
2769 break;
2770
2771 default:
7f97a4bd 2772 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2773 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2774 SPEED_10;
2775 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2776 DUPLEX_HALF;
2777 break;
2778 }
1da177e4
LT		 2779 *speed = SPEED_INVALID;
2780 *duplex = DUPLEX_INVALID;
2781 break;
855e1111 2782 }
1da177e4
LT		 2783}
2784
2785static void tg3_phy_copper_begin(struct tg3 *tp)
2786{
2787 u32 new_adv;
2788 int i;
2789
2790 if (tp->link_config.phy_is_low_power) {
2791 /* Entering low power mode. Disable gigabit and
2792 * 100baseT advertisements.
2793 */
2794 tg3_writephy(tp, MII_TG3_CTRL, 0);
2795
2796 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2797 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2798 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2799 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2800
2801 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2802 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2803 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2804 tp->link_config.advertising &=
2805 ~(ADVERTISED_1000baseT_Half |
2806 ADVERTISED_1000baseT_Full);
2807
ba4d07a8 2808 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2809 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2810 new_adv |= ADVERTISE_10HALF;
2811 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2812 new_adv |= ADVERTISE_10FULL;
2813 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2814 new_adv |= ADVERTISE_100HALF;
2815 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2816 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2817
2818 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2819
1da177e4
LT		 2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821
2822 if (tp->link_config.advertising &
2823 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2824 new_adv = 0;
2825 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2826 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2827 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2828 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2829 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2830 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2832 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833 MII_TG3_CTRL_ENABLE_AS_MASTER);
2834 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2835 } else {
2836 tg3_writephy(tp, MII_TG3_CTRL, 0);
2837 }
2838 } else {
ba4d07a8
MC		 2839 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2840 new_adv |= ADVERTISE_CSMA;
2841
1da177e4
LT		 2842 /* Asking for a specific link mode. */
2843 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2844 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2845
2846 if (tp->link_config.duplex == DUPLEX_FULL)
2847 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2848 else
2849 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2850 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2851 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2852 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2853 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2854 } else {
1da177e4
LT		 2855 if (tp->link_config.speed == SPEED_100) {
2856 if (tp->link_config.duplex == DUPLEX_FULL)
2857 new_adv |= ADVERTISE_100FULL;
2858 else
2859 new_adv |= ADVERTISE_100HALF;
2860 } else {
2861 if (tp->link_config.duplex == DUPLEX_FULL)
2862 new_adv |= ADVERTISE_10FULL;
2863 else
2864 new_adv |= ADVERTISE_10HALF;
2865 }
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2867
2868 new_adv = 0;
1da177e4 2869 }
ba4d07a8
MC		 2870
2871 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2872 }
2873
2874 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2875 tp->link_config.speed != SPEED_INVALID) {
2876 u32 bmcr, orig_bmcr;
2877
2878 tp->link_config.active_speed = tp->link_config.speed;
2879 tp->link_config.active_duplex = tp->link_config.duplex;
2880
2881 bmcr = 0;
2882 switch (tp->link_config.speed) {
2883 default:
2884 case SPEED_10:
2885 break;
2886
2887 case SPEED_100:
2888 bmcr |= BMCR_SPEED100;
2889 break;
2890
2891 case SPEED_1000:
2892 bmcr |= TG3_BMCR_SPEED1000;
2893 break;
855e1111 2894 }
1da177e4
LT		 2895
2896 if (tp->link_config.duplex == DUPLEX_FULL)
2897 bmcr |= BMCR_FULLDPLX;
2898
2899 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2900 (bmcr != orig_bmcr)) {
2901 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2902 for (i = 0; i < 1500; i++) {
2903 u32 tmp;
2904
2905 udelay(10);
2906 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2907 tg3_readphy(tp, MII_BMSR, &tmp))
2908 continue;
2909 if (!(tmp & BMSR_LSTATUS)) {
2910 udelay(40);
2911 break;
2912 }
2913 }
2914 tg3_writephy(tp, MII_BMCR, bmcr);
2915 udelay(40);
2916 }
2917 } else {
2918 tg3_writephy(tp, MII_BMCR,
2919 BMCR_ANENABLE | BMCR_ANRESTART);
2920 }
2921}
2922
2923static int tg3_init_5401phy_dsp(struct tg3 *tp)
2924{
2925 int err;
2926
2927 /* Turn off tap power management. */
2928 /* Set Extended packet length bit */
2929 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2930
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2933
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2936
2937 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2939
2940 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2941 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2942
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2945
2946 udelay(40);
2947
2948 return err;
2949}
2950
3600d918 2951static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2952{
3600d918
MC		 2953 u32 adv_reg, all_mask = 0;
2954
2955 if (mask & ADVERTISED_10baseT_Half)
2956 all_mask |= ADVERTISE_10HALF;
2957 if (mask & ADVERTISED_10baseT_Full)
2958 all_mask |= ADVERTISE_10FULL;
2959 if (mask & ADVERTISED_100baseT_Half)
2960 all_mask |= ADVERTISE_100HALF;
2961 if (mask & ADVERTISED_100baseT_Full)
2962 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2963
2964 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2965 return 0;
2966
1da177e4
LT		 2967 if ((adv_reg & all_mask) != all_mask)
2968 return 0;
2969 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2970 u32 tg3_ctrl;
2971
3600d918
MC		 2972 all_mask = 0;
2973 if (mask & ADVERTISED_1000baseT_Half)
2974 all_mask |= ADVERTISE_1000HALF;
2975 if (mask & ADVERTISED_1000baseT_Full)
2976 all_mask |= ADVERTISE_1000FULL;
2977
1da177e4
LT		 2978 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2979 return 0;
2980
1da177e4
LT		 2981 if ((tg3_ctrl & all_mask) != all_mask)
2982 return 0;
2983 }
2984 return 1;
2985}
2986
ef167e27
MC		 2987static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2988{
2989 u32 curadv, reqadv;
2990
2991 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2992 return 1;
2993
2994 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2995 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2996
2997 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2998 if (curadv != reqadv)
2999 return 0;
3000
3001 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3002 tg3_readphy(tp, MII_LPA, rmtadv);
3003 } else {
3004 /* Reprogram the advertisement register, even if it
3005 * does not affect the current link. If the link
3006 * gets renegotiated in the future, we can save an
3007 * additional renegotiation cycle by advertising
3008 * it correctly in the first place.
3009 */
3010 if (curadv != reqadv) {
3011 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3012 ADVERTISE_PAUSE_ASYM);
3013 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3014 }
3015 }
3016
3017 return 1;
3018}
3019
1da177e4
LT		 3020static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3021{
3022 int current_link_up;
3023 u32 bmsr, dummy;
ef167e27 3024 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3025 u16 current_speed;
3026 u8 current_duplex;
3027 int i, err;
3028
3029 tw32(MAC_EVENT, 0);
3030
3031 tw32_f(MAC_STATUS,
3032 (MAC_STATUS_SYNC_CHANGED |
3033 MAC_STATUS_CFG_CHANGED |
3034 MAC_STATUS_MI_COMPLETION |
3035 MAC_STATUS_LNKSTATE_CHANGED));
3036 udelay(40);
3037
8ef21428
MC		 3038 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3039 tw32_f(MAC_MI_MODE,
3040 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3041 udelay(80);
3042 }
1da177e4
LT		 3043
3044 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3045
3046 /* Some third-party PHYs need to be reset on link going
3047 * down.
3048 */
3049 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3052 netif_carrier_ok(tp->dev)) {
3053 tg3_readphy(tp, MII_BMSR, &bmsr);
3054 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3055 !(bmsr & BMSR_LSTATUS))
3056 force_reset = 1;
3057 }
3058 if (force_reset)
3059 tg3_phy_reset(tp);
3060
3061 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3062 tg3_readphy(tp, MII_BMSR, &bmsr);
3063 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3064 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3065 bmsr = 0;
3066
3067 if (!(bmsr & BMSR_LSTATUS)) {
3068 err = tg3_init_5401phy_dsp(tp);
3069 if (err)
3070 return err;
3071
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 for (i = 0; i < 1000; i++) {
3074 udelay(10);
3075 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3076 (bmsr & BMSR_LSTATUS)) {
3077 udelay(40);
3078 break;
3079 }
3080 }
3081
3082 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3083 !(bmsr & BMSR_LSTATUS) &&
3084 tp->link_config.active_speed == SPEED_1000) {
3085 err = tg3_phy_reset(tp);
3086 if (!err)
3087 err = tg3_init_5401phy_dsp(tp);
3088 if (err)
3089 return err;
3090 }
3091 }
3092 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3093 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3094 /* 5701 {A0,B0} CRC bug workaround */
3095 tg3_writephy(tp, 0x15, 0x0a75);
3096 tg3_writephy(tp, 0x1c, 0x8c68);
3097 tg3_writephy(tp, 0x1c, 0x8d68);
3098 tg3_writephy(tp, 0x1c, 0x8c68);
3099 }
3100
3101 /* Clear pending interrupts... */
3102 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3103 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3104
3105 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3106 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3107 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3108 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3109
3110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3112 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3115 else
3116 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3117 }
3118
3119 current_link_up = 0;
3120 current_speed = SPEED_INVALID;
3121 current_duplex = DUPLEX_INVALID;
3122
3123 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3124 u32 val;
3125
3126 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3127 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3128 if (!(val & (1 << 10))) {
3129 val |= (1 << 10);
3130 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3131 goto relink;
3132 }
3133 }
3134
3135 bmsr = 0;
3136 for (i = 0; i < 100; i++) {
3137 tg3_readphy(tp, MII_BMSR, &bmsr);
3138 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3139 (bmsr & BMSR_LSTATUS))
3140 break;
3141 udelay(40);
3142 }
3143
3144 if (bmsr & BMSR_LSTATUS) {
3145 u32 aux_stat, bmcr;
3146
3147 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3148 for (i = 0; i < 2000; i++) {
3149 udelay(10);
3150 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3151 aux_stat)
3152 break;
3153 }
3154
3155 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3156 &current_speed,
3157 &current_duplex);
3158
3159 bmcr = 0;
3160 for (i = 0; i < 200; i++) {
3161 tg3_readphy(tp, MII_BMCR, &bmcr);
3162 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3163 continue;
3164 if (bmcr && bmcr != 0x7fff)
3165 break;
3166 udelay(10);
3167 }
3168
ef167e27
MC		 3169 lcl_adv = 0;
3170 rmt_adv = 0;
1da177e4 3171
ef167e27
MC		 3172 tp->link_config.active_speed = current_speed;
3173 tp->link_config.active_duplex = current_duplex;
3174
3175 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176 if ((bmcr & BMCR_ANENABLE) &&
3177 tg3_copper_is_advertising_all(tp,
3178 tp->link_config.advertising)) {
3179 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3180 &rmt_adv))
3181 current_link_up = 1;
1da177e4
LT		 3182 }
3183 } else {
3184 if (!(bmcr & BMCR_ANENABLE) &&
3185 tp->link_config.speed == current_speed &&
ef167e27
MC		 3186 tp->link_config.duplex == current_duplex &&
3187 tp->link_config.flowctrl ==
3188 tp->link_config.active_flowctrl) {
1da177e4 3189 current_link_up = 1;
1da177e4
LT		 3190 }
3191 }
3192
ef167e27
MC		 3193 if (current_link_up == 1 &&
3194 tp->link_config.active_duplex == DUPLEX_FULL)
3195 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3196 }
3197
1da177e4 3198relink:
6921d201 3199 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3200 u32 tmp;
3201
3202 tg3_phy_copper_begin(tp);
3203
3204 tg3_readphy(tp, MII_BMSR, &tmp);
3205 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3206 (tmp & BMSR_LSTATUS))
3207 current_link_up = 1;
3208 }
3209
3210 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3211 if (current_link_up == 1) {
3212 if (tp->link_config.active_speed == SPEED_100 ||
3213 tp->link_config.active_speed == SPEED_10)
3214 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3215 else
3216 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3217 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3218 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3219 else
1da177e4
LT		 3220 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3221
3222 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3223 if (tp->link_config.active_duplex == DUPLEX_HALF)
3224 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3225
1da177e4 3226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3227 if (current_link_up == 1 &&
3228 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3229 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3230 else
3231 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3232 }
3233
3234 /* ??? Without this setting Netgear GA302T PHY does not
3235 * ??? send/receive packets...
3236 */
3237 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3238 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3239 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3240 tw32_f(MAC_MI_MODE, tp->mi_mode);
3241 udelay(80);
3242 }
3243
3244 tw32_f(MAC_MODE, tp->mac_mode);
3245 udelay(40);
3246
3247 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3248 /* Polled via timer. */
3249 tw32_f(MAC_EVENT, 0);
3250 } else {
3251 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3252 }
3253 udelay(40);
3254
3255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3256 current_link_up == 1 &&
3257 tp->link_config.active_speed == SPEED_1000 &&
3258 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3259 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3260 udelay(120);
3261 tw32_f(MAC_STATUS,
3262 (MAC_STATUS_SYNC_CHANGED |
3263 MAC_STATUS_CFG_CHANGED));
3264 udelay(40);
3265 tg3_write_mem(tp,
3266 NIC_SRAM_FIRMWARE_MBOX,
3267 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3268 }
3269
5e7dfd0f
MC		 3270 /* Prevent send BD corruption. */
3271 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3272 u16 oldlnkctl, newlnkctl;
3273
3274 pci_read_config_word(tp->pdev,
3275 tp->pcie_cap + PCI_EXP_LNKCTL,
3276 &oldlnkctl);
3277 if (tp->link_config.active_speed == SPEED_100 ||
3278 tp->link_config.active_speed == SPEED_10)
3279 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3280 else
3281 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3282 if (newlnkctl != oldlnkctl)
3283 pci_write_config_word(tp->pdev,
3284 tp->pcie_cap + PCI_EXP_LNKCTL,
3285 newlnkctl);
3286 }
3287
1da177e4
LT		 3288 if (current_link_up != netif_carrier_ok(tp->dev)) {
3289 if (current_link_up)
3290 netif_carrier_on(tp->dev);
3291 else
3292 netif_carrier_off(tp->dev);
3293 tg3_link_report(tp);
3294 }
3295
3296 return 0;
3297}
3298
3299struct tg3_fiber_aneginfo {
3300 int state;
3301#define ANEG_STATE_UNKNOWN 0
3302#define ANEG_STATE_AN_ENABLE 1
3303#define ANEG_STATE_RESTART_INIT 2
3304#define ANEG_STATE_RESTART 3
3305#define ANEG_STATE_DISABLE_LINK_OK 4
3306#define ANEG_STATE_ABILITY_DETECT_INIT 5
3307#define ANEG_STATE_ABILITY_DETECT 6
3308#define ANEG_STATE_ACK_DETECT_INIT 7
3309#define ANEG_STATE_ACK_DETECT 8
3310#define ANEG_STATE_COMPLETE_ACK_INIT 9
3311#define ANEG_STATE_COMPLETE_ACK 10
3312#define ANEG_STATE_IDLE_DETECT_INIT 11
3313#define ANEG_STATE_IDLE_DETECT 12
3314#define ANEG_STATE_LINK_OK 13
3315#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3316#define ANEG_STATE_NEXT_PAGE_WAIT 15
3317
3318 u32 flags;
3319#define MR_AN_ENABLE 0x00000001
3320#define MR_RESTART_AN 0x00000002
3321#define MR_AN_COMPLETE 0x00000004
3322#define MR_PAGE_RX 0x00000008
3323#define MR_NP_LOADED 0x00000010
3324#define MR_TOGGLE_TX 0x00000020
3325#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3326#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3327#define MR_LP_ADV_SYM_PAUSE 0x00000100
3328#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3329#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3330#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3331#define MR_LP_ADV_NEXT_PAGE 0x00001000
3332#define MR_TOGGLE_RX 0x00002000
3333#define MR_NP_RX 0x00004000
3334
3335#define MR_LINK_OK 0x80000000
3336
3337 unsigned long link_time, cur_time;
3338
3339 u32 ability_match_cfg;
3340 int ability_match_count;
3341
3342 char ability_match, idle_match, ack_match;
3343
3344 u32 txconfig, rxconfig;
3345#define ANEG_CFG_NP 0x00000080
3346#define ANEG_CFG_ACK 0x00000040
3347#define ANEG_CFG_RF2 0x00000020
3348#define ANEG_CFG_RF1 0x00000010
3349#define ANEG_CFG_PS2 0x00000001
3350#define ANEG_CFG_PS1 0x00008000
3351#define ANEG_CFG_HD 0x00004000
3352#define ANEG_CFG_FD 0x00002000
3353#define ANEG_CFG_INVAL 0x00001f06
3354
3355};
3356#define ANEG_OK 0
3357#define ANEG_DONE 1
3358#define ANEG_TIMER_ENAB 2
3359#define ANEG_FAILED -1
3360
3361#define ANEG_STATE_SETTLE_TIME 10000
3362
3363static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3364 struct tg3_fiber_aneginfo *ap)
3365{
5be73b47 3366 u16 flowctrl;
1da177e4
LT		 3367 unsigned long delta;
3368 u32 rx_cfg_reg;
3369 int ret;
3370
3371 if (ap->state == ANEG_STATE_UNKNOWN) {
3372 ap->rxconfig = 0;
3373 ap->link_time = 0;
3374 ap->cur_time = 0;
3375 ap->ability_match_cfg = 0;
3376 ap->ability_match_count = 0;
3377 ap->ability_match = 0;
3378 ap->idle_match = 0;
3379 ap->ack_match = 0;
3380 }
3381 ap->cur_time++;
3382
3383 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3384 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3385
3386 if (rx_cfg_reg != ap->ability_match_cfg) {
3387 ap->ability_match_cfg = rx_cfg_reg;
3388 ap->ability_match = 0;
3389 ap->ability_match_count = 0;
3390 } else {
3391 if (++ap->ability_match_count > 1) {
3392 ap->ability_match = 1;
3393 ap->ability_match_cfg = rx_cfg_reg;
3394 }
3395 }
3396 if (rx_cfg_reg & ANEG_CFG_ACK)
3397 ap->ack_match = 1;
3398 else
3399 ap->ack_match = 0;
3400
3401 ap->idle_match = 0;
3402 } else {
3403 ap->idle_match = 1;
3404 ap->ability_match_cfg = 0;
3405 ap->ability_match_count = 0;
3406 ap->ability_match = 0;
3407 ap->ack_match = 0;
3408
3409 rx_cfg_reg = 0;
3410 }
3411
3412 ap->rxconfig = rx_cfg_reg;
3413 ret = ANEG_OK;
3414
3415 switch(ap->state) {
3416 case ANEG_STATE_UNKNOWN:
3417 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3418 ap->state = ANEG_STATE_AN_ENABLE;
3419
3420 /* fallthru */
3421 case ANEG_STATE_AN_ENABLE:
3422 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3423 if (ap->flags & MR_AN_ENABLE) {
3424 ap->link_time = 0;
3425 ap->cur_time = 0;
3426 ap->ability_match_cfg = 0;
3427 ap->ability_match_count = 0;
3428 ap->ability_match = 0;
3429 ap->idle_match = 0;
3430 ap->ack_match = 0;
3431
3432 ap->state = ANEG_STATE_RESTART_INIT;
3433 } else {
3434 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3435 }
3436 break;
3437
3438 case ANEG_STATE_RESTART_INIT:
3439 ap->link_time = ap->cur_time;
3440 ap->flags &= ~(MR_NP_LOADED);
3441 ap->txconfig = 0;
3442 tw32(MAC_TX_AUTO_NEG, 0);
3443 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3444 tw32_f(MAC_MODE, tp->mac_mode);
3445 udelay(40);
3446
3447 ret = ANEG_TIMER_ENAB;
3448 ap->state = ANEG_STATE_RESTART;
3449
3450 /* fallthru */
3451 case ANEG_STATE_RESTART:
3452 delta = ap->cur_time - ap->link_time;
3453 if (delta > ANEG_STATE_SETTLE_TIME) {
3454 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3455 } else {
3456 ret = ANEG_TIMER_ENAB;
3457 }
3458 break;
3459
3460 case ANEG_STATE_DISABLE_LINK_OK:
3461 ret = ANEG_DONE;
3462 break;
3463
3464 case ANEG_STATE_ABILITY_DETECT_INIT:
3465 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3466 ap->txconfig = ANEG_CFG_FD;
3467 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3468 if (flowctrl & ADVERTISE_1000XPAUSE)
3469 ap->txconfig |= ANEG_CFG_PS1;
3470 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3471 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3472 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3473 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3474 tw32_f(MAC_MODE, tp->mac_mode);
3475 udelay(40);
3476
3477 ap->state = ANEG_STATE_ABILITY_DETECT;
3478 break;
3479
3480 case ANEG_STATE_ABILITY_DETECT:
3481 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3482 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3483 }
3484 break;
3485
3486 case ANEG_STATE_ACK_DETECT_INIT:
3487 ap->txconfig |= ANEG_CFG_ACK;
3488 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490 tw32_f(MAC_MODE, tp->mac_mode);
3491 udelay(40);
3492
3493 ap->state = ANEG_STATE_ACK_DETECT;
3494
3495 /* fallthru */
3496 case ANEG_STATE_ACK_DETECT:
3497 if (ap->ack_match != 0) {
3498 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3499 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3500 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3501 } else {
3502 ap->state = ANEG_STATE_AN_ENABLE;
3503 }
3504 } else if (ap->ability_match != 0 &&
3505 ap->rxconfig == 0) {
3506 ap->state = ANEG_STATE_AN_ENABLE;
3507 }
3508 break;
3509
3510 case ANEG_STATE_COMPLETE_ACK_INIT:
3511 if (ap->rxconfig & ANEG_CFG_INVAL) {
3512 ret = ANEG_FAILED;
3513 break;
3514 }
3515 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3516 MR_LP_ADV_HALF_DUPLEX |
3517 MR_LP_ADV_SYM_PAUSE |
3518 MR_LP_ADV_ASYM_PAUSE |
3519 MR_LP_ADV_REMOTE_FAULT1 |
3520 MR_LP_ADV_REMOTE_FAULT2 |
3521 MR_LP_ADV_NEXT_PAGE |
3522 MR_TOGGLE_RX |
3523 MR_NP_RX);
3524 if (ap->rxconfig & ANEG_CFG_FD)
3525 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3526 if (ap->rxconfig & ANEG_CFG_HD)
3527 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3528 if (ap->rxconfig & ANEG_CFG_PS1)
3529 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3530 if (ap->rxconfig & ANEG_CFG_PS2)
3531 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3532 if (ap->rxconfig & ANEG_CFG_RF1)
3533 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3534 if (ap->rxconfig & ANEG_CFG_RF2)
3535 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3536 if (ap->rxconfig & ANEG_CFG_NP)
3537 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3538
3539 ap->link_time = ap->cur_time;
3540
3541 ap->flags ^= (MR_TOGGLE_TX);
3542 if (ap->rxconfig & 0x0008)
3543 ap->flags |= MR_TOGGLE_RX;
3544 if (ap->rxconfig & ANEG_CFG_NP)
3545 ap->flags |= MR_NP_RX;
3546 ap->flags |= MR_PAGE_RX;
3547
3548 ap->state = ANEG_STATE_COMPLETE_ACK;
3549 ret = ANEG_TIMER_ENAB;
3550 break;
3551
3552 case ANEG_STATE_COMPLETE_ACK:
3553 if (ap->ability_match != 0 &&
3554 ap->rxconfig == 0) {
3555 ap->state = ANEG_STATE_AN_ENABLE;
3556 break;
3557 }
3558 delta = ap->cur_time - ap->link_time;
3559 if (delta > ANEG_STATE_SETTLE_TIME) {
3560 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3561 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3562 } else {
3563 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3564 !(ap->flags & MR_NP_RX)) {
3565 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3566 } else {
3567 ret = ANEG_FAILED;
3568 }
3569 }
3570 }
3571 break;
3572
3573 case ANEG_STATE_IDLE_DETECT_INIT:
3574 ap->link_time = ap->cur_time;
3575 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576 tw32_f(MAC_MODE, tp->mac_mode);
3577 udelay(40);
3578
3579 ap->state = ANEG_STATE_IDLE_DETECT;
3580 ret = ANEG_TIMER_ENAB;
3581 break;
3582
3583 case ANEG_STATE_IDLE_DETECT:
3584 if (ap->ability_match != 0 &&
3585 ap->rxconfig == 0) {
3586 ap->state = ANEG_STATE_AN_ENABLE;
3587 break;
3588 }
3589 delta = ap->cur_time - ap->link_time;
3590 if (delta > ANEG_STATE_SETTLE_TIME) {
3591 /* XXX another gem from the Broadcom driver :( */
3592 ap->state = ANEG_STATE_LINK_OK;
3593 }
3594 break;
3595
3596 case ANEG_STATE_LINK_OK:
3597 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3598 ret = ANEG_DONE;
3599 break;
3600
3601 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3602 /* ??? unimplemented */
3603 break;
3604
3605 case ANEG_STATE_NEXT_PAGE_WAIT:
3606 /* ??? unimplemented */
3607 break;
3608
3609 default:
3610 ret = ANEG_FAILED;
3611 break;
855e1111 3612 }
1da177e4
LT		 3613
3614 return ret;
3615}
3616
5be73b47 3617static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3618{
3619 int res = 0;
3620 struct tg3_fiber_aneginfo aninfo;
3621 int status = ANEG_FAILED;
3622 unsigned int tick;
3623 u32 tmp;
3624
3625 tw32_f(MAC_TX_AUTO_NEG, 0);
3626
3627 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3628 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3629 udelay(40);
3630
3631 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3632 udelay(40);
3633
3634 memset(&aninfo, 0, sizeof(aninfo));
3635 aninfo.flags |= MR_AN_ENABLE;
3636 aninfo.state = ANEG_STATE_UNKNOWN;
3637 aninfo.cur_time = 0;
3638 tick = 0;
3639 while (++tick < 195000) {
3640 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3641 if (status == ANEG_DONE || status == ANEG_FAILED)
3642 break;
3643
3644 udelay(1);
3645 }
3646
3647 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3648 tw32_f(MAC_MODE, tp->mac_mode);
3649 udelay(40);
3650
5be73b47
MC		 3651 *txflags = aninfo.txconfig;
3652 *rxflags = aninfo.flags;
1da177e4
LT		 3653
3654 if (status == ANEG_DONE &&
3655 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3656 MR_LP_ADV_FULL_DUPLEX)))
3657 res = 1;
3658
3659 return res;
3660}
3661
3662static void tg3_init_bcm8002(struct tg3 *tp)
3663{
3664 u32 mac_status = tr32(MAC_STATUS);
3665 int i;
3666
3667 /* Reset when initting first time or we have a link. */
3668 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3669 !(mac_status & MAC_STATUS_PCS_SYNCED))
3670 return;
3671
3672 /* Set PLL lock range. */
3673 tg3_writephy(tp, 0x16, 0x8007);
3674
3675 /* SW reset */
3676 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3677
3678 /* Wait for reset to complete. */
3679 /* XXX schedule_timeout() ... */
3680 for (i = 0; i < 500; i++)
3681 udelay(10);
3682
3683 /* Config mode; select PMA/Ch 1 regs. */
3684 tg3_writephy(tp, 0x10, 0x8411);
3685
3686 /* Enable auto-lock and comdet, select txclk for tx. */
3687 tg3_writephy(tp, 0x11, 0x0a10);
3688
3689 tg3_writephy(tp, 0x18, 0x00a0);
3690 tg3_writephy(tp, 0x16, 0x41ff);
3691
3692 /* Assert and deassert POR. */
3693 tg3_writephy(tp, 0x13, 0x0400);
3694 udelay(40);
3695 tg3_writephy(tp, 0x13, 0x0000);
3696
3697 tg3_writephy(tp, 0x11, 0x0a50);
3698 udelay(40);
3699 tg3_writephy(tp, 0x11, 0x0a10);
3700
3701 /* Wait for signal to stabilize */
3702 /* XXX schedule_timeout() ... */
3703 for (i = 0; i < 15000; i++)
3704 udelay(10);
3705
3706 /* Deselect the channel register so we can read the PHYID
3707 * later.
3708 */
3709 tg3_writephy(tp, 0x10, 0x8011);
3710}
3711
3712static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3713{
82cd3d11 3714 u16 flowctrl;
1da177e4
LT		 3715 u32 sg_dig_ctrl, sg_dig_status;
3716 u32 serdes_cfg, expected_sg_dig_ctrl;
3717 int workaround, port_a;
3718 int current_link_up;
3719
3720 serdes_cfg = 0;
3721 expected_sg_dig_ctrl = 0;
3722 workaround = 0;
3723 port_a = 1;
3724 current_link_up = 0;
3725
3726 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3727 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3728 workaround = 1;
3729 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3730 port_a = 0;
3731
3732 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3733 /* preserve bits 20-23 for voltage regulator */
3734 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3735 }
3736
3737 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3738
3739 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3740 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3741 if (workaround) {
3742 u32 val = serdes_cfg;
3743
3744 if (port_a)
3745 val |= 0xc010000;
3746 else
3747 val |= 0x4010000;
3748 tw32_f(MAC_SERDES_CFG, val);
3749 }
c98f6e3b
MC		 3750
3751 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3752 }
3753 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3754 tg3_setup_flow_control(tp, 0, 0);
3755 current_link_up = 1;
3756 }
3757 goto out;
3758 }
3759
3760 /* Want auto-negotiation. */
c98f6e3b 3761 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3762
82cd3d11
MC		 3763 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3764 if (flowctrl & ADVERTISE_1000XPAUSE)
3765 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3766 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3767 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3768
3769 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3770 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3771 tp->serdes_counter &&
3772 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3773 MAC_STATUS_RCVD_CFG)) ==
3774 MAC_STATUS_PCS_SYNCED)) {
3775 tp->serdes_counter--;
3776 current_link_up = 1;
3777 goto out;
3778 }
3779restart_autoneg:
1da177e4
LT		 3780 if (workaround)
3781 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3782 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3783 udelay(5);
3784 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3785
3d3ebe74
MC		 3786 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3787 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3788 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3789 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3790 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3791 mac_status = tr32(MAC_STATUS);
3792
c98f6e3b 3793 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3794 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3795 u32 local_adv = 0, remote_adv = 0;
3796
3797 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3798 local_adv |= ADVERTISE_1000XPAUSE;
3799 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3800 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3801
c98f6e3b 3802 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3803 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3804 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3805 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3806
3807 tg3_setup_flow_control(tp, local_adv, remote_adv);
3808 current_link_up = 1;
3d3ebe74
MC		 3809 tp->serdes_counter = 0;
3810 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3811 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3812 if (tp->serdes_counter)
3813 tp->serdes_counter--;
1da177e4
LT		 3814 else {
3815 if (workaround) {
3816 u32 val = serdes_cfg;
3817
3818 if (port_a)
3819 val |= 0xc010000;
3820 else
3821 val |= 0x4010000;
3822
3823 tw32_f(MAC_SERDES_CFG, val);
3824 }
3825
c98f6e3b 3826 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3827 udelay(40);
3828
3829 /* Link parallel detection - link is up */
3830 /* only if we have PCS_SYNC and not */
3831 /* receiving config code words */
3832 mac_status = tr32(MAC_STATUS);
3833 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3835 tg3_setup_flow_control(tp, 0, 0);
3836 current_link_up = 1;
3d3ebe74
MC		 3837 tp->tg3_flags2 |=
3838 TG3_FLG2_PARALLEL_DETECT;
3839 tp->serdes_counter =
3840 SERDES_PARALLEL_DET_TIMEOUT;
3841 } else
3842 goto restart_autoneg;
1da177e4
LT		 3843 }
3844 }
3d3ebe74
MC		 3845 } else {
3846 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3847 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3848 }
3849
3850out:
3851 return current_link_up;
3852}
3853
3854static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3855{
3856 int current_link_up = 0;
3857
5cf64b8a 3858 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3859 goto out;
1da177e4
LT		 3860
3861 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3862 u32 txflags, rxflags;
1da177e4 3863 int i;
6aa20a22 3864
5be73b47
MC		 3865 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3866 u32 local_adv = 0, remote_adv = 0;
1da177e4 3867
5be73b47
MC		 3868 if (txflags & ANEG_CFG_PS1)
3869 local_adv |= ADVERTISE_1000XPAUSE;
3870 if (txflags & ANEG_CFG_PS2)
3871 local_adv |= ADVERTISE_1000XPSE_ASYM;
3872
3873 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3874 remote_adv |= LPA_1000XPAUSE;
3875 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3876 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3877
3878 tg3_setup_flow_control(tp, local_adv, remote_adv);
3879
1da177e4
LT		 3880 current_link_up = 1;
3881 }
3882 for (i = 0; i < 30; i++) {
3883 udelay(20);
3884 tw32_f(MAC_STATUS,
3885 (MAC_STATUS_SYNC_CHANGED |
3886 MAC_STATUS_CFG_CHANGED));
3887 udelay(40);
3888 if ((tr32(MAC_STATUS) &
3889 (MAC_STATUS_SYNC_CHANGED |
3890 MAC_STATUS_CFG_CHANGED)) == 0)
3891 break;
3892 }
3893
3894 mac_status = tr32(MAC_STATUS);
3895 if (current_link_up == 0 &&
3896 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3897 !(mac_status & MAC_STATUS_RCVD_CFG))
3898 current_link_up = 1;
3899 } else {
5be73b47
MC		 3900 tg3_setup_flow_control(tp, 0, 0);
3901
1da177e4
LT		 3902 /* Forcing 1000FD link up. */
3903 current_link_up = 1;
1da177e4
LT		 3904
3905 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3906 udelay(40);
e8f3f6ca
MC		 3907
3908 tw32_f(MAC_MODE, tp->mac_mode);
3909 udelay(40);
1da177e4
LT		 3910 }
3911
3912out:
3913 return current_link_up;
3914}
3915
3916static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3917{
3918 u32 orig_pause_cfg;
3919 u16 orig_active_speed;
3920 u8 orig_active_duplex;
3921 u32 mac_status;
3922 int current_link_up;
3923 int i;
3924
8d018621 3925 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3926 orig_active_speed = tp->link_config.active_speed;
3927 orig_active_duplex = tp->link_config.active_duplex;
3928
3929 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3930 netif_carrier_ok(tp->dev) &&
3931 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3932 mac_status = tr32(MAC_STATUS);
3933 mac_status &= (MAC_STATUS_PCS_SYNCED |
3934 MAC_STATUS_SIGNAL_DET |
3935 MAC_STATUS_CFG_CHANGED |
3936 MAC_STATUS_RCVD_CFG);
3937 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3938 MAC_STATUS_SIGNAL_DET)) {
3939 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940 MAC_STATUS_CFG_CHANGED));
3941 return 0;
3942 }
3943 }
3944
3945 tw32_f(MAC_TX_AUTO_NEG, 0);
3946
3947 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3948 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3949 tw32_f(MAC_MODE, tp->mac_mode);
3950 udelay(40);
3951
3952 if (tp->phy_id == PHY_ID_BCM8002)
3953 tg3_init_bcm8002(tp);
3954
3955 /* Enable link change event even when serdes polling. */
3956 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3957 udelay(40);
3958
3959 current_link_up = 0;
3960 mac_status = tr32(MAC_STATUS);
3961
3962 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3963 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3964 else
3965 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3966
898a56f8 3967 tp->napi[0].hw_status->status =
1da177e4 3968 (SD_STATUS_UPDATED |
898a56f8 3969 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3970
3971 for (i = 0; i < 100; i++) {
3972 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3973 MAC_STATUS_CFG_CHANGED));
3974 udelay(5);
3975 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3976 MAC_STATUS_CFG_CHANGED |
3977 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3978 break;
3979 }
3980
3981 mac_status = tr32(MAC_STATUS);
3982 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3983 current_link_up = 0;
3d3ebe74
MC		 3984 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3985 tp->serdes_counter == 0) {
1da177e4
LT		 3986 tw32_f(MAC_MODE, (tp->mac_mode |
3987 MAC_MODE_SEND_CONFIGS));
3988 udelay(1);
3989 tw32_f(MAC_MODE, tp->mac_mode);
3990 }
3991 }
3992
3993 if (current_link_up == 1) {
3994 tp->link_config.active_speed = SPEED_1000;
3995 tp->link_config.active_duplex = DUPLEX_FULL;
3996 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3997 LED_CTRL_LNKLED_OVERRIDE |
3998 LED_CTRL_1000MBPS_ON));
3999 } else {
4000 tp->link_config.active_speed = SPEED_INVALID;
4001 tp->link_config.active_duplex = DUPLEX_INVALID;
4002 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003 LED_CTRL_LNKLED_OVERRIDE |
4004 LED_CTRL_TRAFFIC_OVERRIDE));
4005 }
4006
4007 if (current_link_up != netif_carrier_ok(tp->dev)) {
4008 if (current_link_up)
4009 netif_carrier_on(tp->dev);
4010 else
4011 netif_carrier_off(tp->dev);
4012 tg3_link_report(tp);
4013 } else {
8d018621 4014 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4015 if (orig_pause_cfg != now_pause_cfg ||
4016 orig_active_speed != tp->link_config.active_speed ||
4017 orig_active_duplex != tp->link_config.active_duplex)
4018 tg3_link_report(tp);
4019 }
4020
4021 return 0;
4022}
4023
747e8f8b
MC		 4024static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4025{
4026 int current_link_up, err = 0;
4027 u32 bmsr, bmcr;
4028 u16 current_speed;
4029 u8 current_duplex;
ef167e27 4030 u32 local_adv, remote_adv;
747e8f8b
MC		 4031
4032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4033 tw32_f(MAC_MODE, tp->mac_mode);
4034 udelay(40);
4035
4036 tw32(MAC_EVENT, 0);
4037
4038 tw32_f(MAC_STATUS,
4039 (MAC_STATUS_SYNC_CHANGED |
4040 MAC_STATUS_CFG_CHANGED |
4041 MAC_STATUS_MI_COMPLETION |
4042 MAC_STATUS_LNKSTATE_CHANGED));
4043 udelay(40);
4044
4045 if (force_reset)
4046 tg3_phy_reset(tp);
4047
4048 current_link_up = 0;
4049 current_speed = SPEED_INVALID;
4050 current_duplex = DUPLEX_INVALID;
4051
4052 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4055 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4056 bmsr |= BMSR_LSTATUS;
4057 else
4058 bmsr &= ~BMSR_LSTATUS;
4059 }
747e8f8b
MC		 4060
4061 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4062
4063 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4064 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4065 /* do nothing, just check for link up at the end */
4066 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4067 u32 adv, new_adv;
4068
4069 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4070 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4071 ADVERTISE_1000XPAUSE |
4072 ADVERTISE_1000XPSE_ASYM |
4073 ADVERTISE_SLCT);
4074
ba4d07a8 4075 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4076
4077 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4078 new_adv |= ADVERTISE_1000XHALF;
4079 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4080 new_adv |= ADVERTISE_1000XFULL;
4081
4082 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4083 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4084 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4085 tg3_writephy(tp, MII_BMCR, bmcr);
4086
4087 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4088 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4089 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4090
4091 return err;
4092 }
4093 } else {
4094 u32 new_bmcr;
4095
4096 bmcr &= ~BMCR_SPEED1000;
4097 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4098
4099 if (tp->link_config.duplex == DUPLEX_FULL)
4100 new_bmcr |= BMCR_FULLDPLX;
4101
4102 if (new_bmcr != bmcr) {
4103 /* BMCR_SPEED1000 is a reserved bit that needs
4104 * to be set on write.
4105 */
4106 new_bmcr |= BMCR_SPEED1000;
4107
4108 /* Force a linkdown */
4109 if (netif_carrier_ok(tp->dev)) {
4110 u32 adv;
4111
4112 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4113 adv &= ~(ADVERTISE_1000XFULL |
4114 ADVERTISE_1000XHALF |
4115 ADVERTISE_SLCT);
4116 tg3_writephy(tp, MII_ADVERTISE, adv);
4117 tg3_writephy(tp, MII_BMCR, bmcr |
4118 BMCR_ANRESTART |
4119 BMCR_ANENABLE);
4120 udelay(10);
4121 netif_carrier_off(tp->dev);
4122 }
4123 tg3_writephy(tp, MII_BMCR, new_bmcr);
4124 bmcr = new_bmcr;
4125 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4126 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4127 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4128 ASIC_REV_5714) {
4129 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4130 bmsr |= BMSR_LSTATUS;
4131 else
4132 bmsr &= ~BMSR_LSTATUS;
4133 }
747e8f8b
MC		 4134 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4135 }
4136 }
4137
4138 if (bmsr & BMSR_LSTATUS) {
4139 current_speed = SPEED_1000;
4140 current_link_up = 1;
4141 if (bmcr & BMCR_FULLDPLX)
4142 current_duplex = DUPLEX_FULL;
4143 else
4144 current_duplex = DUPLEX_HALF;
4145
ef167e27
MC		 4146 local_adv = 0;
4147 remote_adv = 0;
4148
747e8f8b 4149 if (bmcr & BMCR_ANENABLE) {
ef167e27 4150 u32 common;
747e8f8b
MC		 4151
4152 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4153 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4154 common = local_adv & remote_adv;
4155 if (common & (ADVERTISE_1000XHALF |
4156 ADVERTISE_1000XFULL)) {
4157 if (common & ADVERTISE_1000XFULL)
4158 current_duplex = DUPLEX_FULL;
4159 else
4160 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4161 }
4162 else
4163 current_link_up = 0;
4164 }
4165 }
4166
ef167e27
MC		 4167 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4168 tg3_setup_flow_control(tp, local_adv, remote_adv);
4169
747e8f8b
MC		 4170 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4171 if (tp->link_config.active_duplex == DUPLEX_HALF)
4172 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4173
4174 tw32_f(MAC_MODE, tp->mac_mode);
4175 udelay(40);
4176
4177 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4178
4179 tp->link_config.active_speed = current_speed;
4180 tp->link_config.active_duplex = current_duplex;
4181
4182 if (current_link_up != netif_carrier_ok(tp->dev)) {
4183 if (current_link_up)
4184 netif_carrier_on(tp->dev);
4185 else {
4186 netif_carrier_off(tp->dev);
4187 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4188 }
4189 tg3_link_report(tp);
4190 }
4191 return err;
4192}
4193
4194static void tg3_serdes_parallel_detect(struct tg3 *tp)
4195{
3d3ebe74 4196 if (tp->serdes_counter) {
747e8f8b 4197 /* Give autoneg time to complete. */
3d3ebe74 4198 tp->serdes_counter--;
747e8f8b
MC		 4199 return;
4200 }
4201 if (!netif_carrier_ok(tp->dev) &&
4202 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4203 u32 bmcr;
4204
4205 tg3_readphy(tp, MII_BMCR, &bmcr);
4206 if (bmcr & BMCR_ANENABLE) {
4207 u32 phy1, phy2;
4208
4209 /* Select shadow register 0x1f */
4210 tg3_writephy(tp, 0x1c, 0x7c00);
4211 tg3_readphy(tp, 0x1c, &phy1);
4212
4213 /* Select expansion interrupt status register */
4214 tg3_writephy(tp, 0x17, 0x0f01);
4215 tg3_readphy(tp, 0x15, &phy2);
4216 tg3_readphy(tp, 0x15, &phy2);
4217
4218 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4219 /* We have signal detect and not receiving
4220 * config code words, link is up by parallel
4221 * detection.
4222 */
4223
4224 bmcr &= ~BMCR_ANENABLE;
4225 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4226 tg3_writephy(tp, MII_BMCR, bmcr);
4227 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4228 }
4229 }
4230 }
4231 else if (netif_carrier_ok(tp->dev) &&
4232 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4233 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4234 u32 phy2;
4235
4236 /* Select expansion interrupt status register */
4237 tg3_writephy(tp, 0x17, 0x0f01);
4238 tg3_readphy(tp, 0x15, &phy2);
4239 if (phy2 & 0x20) {
4240 u32 bmcr;
4241
4242 /* Config code words received, turn on autoneg. */
4243 tg3_readphy(tp, MII_BMCR, &bmcr);
4244 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4245
4246 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4247
4248 }
4249 }
4250}
4251
1da177e4
LT		 4252static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4253{
4254 int err;
4255
4256 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4257 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4258 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4259 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4260 } else {
4261 err = tg3_setup_copper_phy(tp, force_reset);
4262 }
4263
bcb37f6c 4264 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4265 u32 val, scale;
4266
4267 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4268 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4269 scale = 65;
4270 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4271 scale = 6;
4272 else
4273 scale = 12;
4274
4275 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4276 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4277 tw32(GRC_MISC_CFG, val);
4278 }
4279
1da177e4
LT		 4280 if (tp->link_config.active_speed == SPEED_1000 &&
4281 tp->link_config.active_duplex == DUPLEX_HALF)
4282 tw32(MAC_TX_LENGTHS,
4283 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4284 (6 << TX_LENGTHS_IPG_SHIFT) |
4285 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4286 else
4287 tw32(MAC_TX_LENGTHS,
4288 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4289 (6 << TX_LENGTHS_IPG_SHIFT) |
4290 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4291
4292 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4293 if (netif_carrier_ok(tp->dev)) {
4294 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4295 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4296 } else {
4297 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4298 }
4299 }
4300
8ed5d97e
MC		 4301 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4302 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4303 if (!netif_carrier_ok(tp->dev))
4304 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4305 tp->pwrmgmt_thresh;
4306 else
4307 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4308 tw32(PCIE_PWR_MGMT_THRESH, val);
4309 }
4310
1da177e4
LT		 4311 return err;
4312}
4313
df3e6548
MC		 4314/* This is called whenever we suspect that the system chipset is re-
4315 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4316 * is bogus tx completions. We try to recover by setting the
4317 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4318 * in the workqueue.
4319 */
4320static void tg3_tx_recover(struct tg3 *tp)
4321{
4322 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4323 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4324
4325 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4326 "mapped I/O cycles to the network device, attempting to "
4327 "recover. Please report the problem to the driver maintainer "
4328 "and include system chipset information.\n", tp->dev->name);
4329
4330 spin_lock(&tp->lock);
df3e6548 4331 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4332 spin_unlock(&tp->lock);
4333}
4334
f3f3f27e 4335static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4336{
4337 smp_mb();
f3f3f27e
MC		 4338 return tnapi->tx_pending -
4339 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4340}
4341
1da177e4
LT		 4342/* Tigon3 never reports partial packet sends. So we do not
4343 * need special logic to handle SKBs that have not had all
4344 * of their frags sent yet, like SunGEM does.
4345 */
17375d25 4346static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4347{
17375d25 4348 struct tg3 *tp = tnapi->tp;
898a56f8 4349 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4350 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4351 struct netdev_queue *txq;
4352 int index = tnapi - tp->napi;
4353
4354 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4355 index--;
4356
4357 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4358
4359 while (sw_idx != hw_idx) {
f4188d8a 4360 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4361 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4362 int i, tx_bug = 0;
4363
4364 if (unlikely(skb == NULL)) {
4365 tg3_tx_recover(tp);
4366 return;
4367 }
1da177e4 4368
f4188d8a
AD		 4369 pci_unmap_single(tp->pdev,
4370 pci_unmap_addr(ri, mapping),
4371 skb_headlen(skb),
4372 PCI_DMA_TODEVICE);
1da177e4
LT		 4373
4374 ri->skb = NULL;
4375
4376 sw_idx = NEXT_TX(sw_idx);
4377
4378 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4379 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4380 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4381 tx_bug = 1;
f4188d8a
AD		 4382
4383 pci_unmap_page(tp->pdev,
4384 pci_unmap_addr(ri, mapping),
4385 skb_shinfo(skb)->frags[i].size,
4386 PCI_DMA_TODEVICE);
1da177e4
LT		 4387 sw_idx = NEXT_TX(sw_idx);
4388 }
4389
f47c11ee 4390 dev_kfree_skb(skb);
df3e6548
MC		 4391
4392 if (unlikely(tx_bug)) {
4393 tg3_tx_recover(tp);
4394 return;
4395 }
1da177e4
LT		 4396 }
4397
f3f3f27e 4398 tnapi->tx_cons = sw_idx;
1da177e4 4399
1b2a7205
MC		 4400 /* Need to make the tx_cons update visible to tg3_start_xmit()
4401 * before checking for netif_queue_stopped(). Without the
4402 * memory barrier, there is a small possibility that tg3_start_xmit()
4403 * will miss it and cause the queue to be stopped forever.
4404 */
4405 smp_mb();
4406
fe5f5787 4407 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4408 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4409 __netif_tx_lock(txq, smp_processor_id());
4410 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4411 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4412 netif_tx_wake_queue(txq);
4413 __netif_tx_unlock(txq);
51b91468 4414 }
1da177e4
LT		 4415}
4416
2b2cdb65
MC		 4417static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4418{
4419 if (!ri->skb)
4420 return;
4421
4422 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4423 map_sz, PCI_DMA_FROMDEVICE);
4424 dev_kfree_skb_any(ri->skb);
4425 ri->skb = NULL;
4426}
4427
1da177e4
LT		 4428/* Returns size of skb allocated or < 0 on error.
4429 *
4430 * We only need to fill in the address because the other members
4431 * of the RX descriptor are invariant, see tg3_init_rings.
4432 *
4433 * Note the purposeful assymetry of cpu vs. chip accesses. For
4434 * posting buffers we only dirty the first cache line of the RX
4435 * descriptor (containing the address). Whereas for the RX status
4436 * buffers the cpu only reads the last cacheline of the RX descriptor
4437 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4438 */
86b21e59 4439static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4440 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4441{
4442 struct tg3_rx_buffer_desc *desc;
4443 struct ring_info *map, *src_map;
4444 struct sk_buff *skb;
4445 dma_addr_t mapping;
4446 int skb_size, dest_idx;
4447
4448 src_map = NULL;
4449 switch (opaque_key) {
4450 case RXD_OPAQUE_RING_STD:
4451 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4452 desc = &tpr->rx_std[dest_idx];
4453 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4454 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4455 break;
4456
4457 case RXD_OPAQUE_RING_JUMBO:
4458 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4459 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4460 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4461 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4462 break;
4463
4464 default:
4465 return -EINVAL;
855e1111 4466 }
1da177e4
LT		 4467
4468 /* Do not overwrite any of the map or rp information
4469 * until we are sure we can commit to a new buffer.
4470 *
4471 * Callers depend upon this behavior and assume that
4472 * we leave everything unchanged if we fail.
4473 */
287be12e 4474 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4475 if (skb == NULL)
4476 return -ENOMEM;
4477
1da177e4
LT		 4478 skb_reserve(skb, tp->rx_offset);
4479
287be12e 4480 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4481 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4482 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4483 dev_kfree_skb(skb);
4484 return -EIO;
4485 }
1da177e4
LT		 4486
4487 map->skb = skb;
4488 pci_unmap_addr_set(map, mapping, mapping);
4489
1da177e4
LT		 4490 desc->addr_hi = ((u64)mapping >> 32);
4491 desc->addr_lo = ((u64)mapping & 0xffffffff);
4492
4493 return skb_size;
4494}
4495
4496/* We only need to move over in the address because the other
4497 * members of the RX descriptor are invariant. See notes above
4498 * tg3_alloc_rx_skb for full details.
4499 */
a3896167
MC		 4500static void tg3_recycle_rx(struct tg3_napi *tnapi,
4501 struct tg3_rx_prodring_set *dpr,
4502 u32 opaque_key, int src_idx,
4503 u32 dest_idx_unmasked)
1da177e4 4504{
17375d25 4505 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4506 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4507 struct ring_info *src_map, *dest_map;
4508 int dest_idx;
a3896167 4509 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4510
4511 switch (opaque_key) {
4512 case RXD_OPAQUE_RING_STD:
4513 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4514 dest_desc = &dpr->rx_std[dest_idx];
4515 dest_map = &dpr->rx_std_buffers[dest_idx];
4516 src_desc = &spr->rx_std[src_idx];
4517 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4518 break;
4519
4520 case RXD_OPAQUE_RING_JUMBO:
4521 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4522 dest_desc = &dpr->rx_jmb[dest_idx].std;
4523 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4524 src_desc = &spr->rx_jmb[src_idx].std;
4525 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4526 break;
4527
4528 default:
4529 return;
855e1111 4530 }
1da177e4
LT		 4531
4532 dest_map->skb = src_map->skb;
4533 pci_unmap_addr_set(dest_map, mapping,
4534 pci_unmap_addr(src_map, mapping));
4535 dest_desc->addr_hi = src_desc->addr_hi;
4536 dest_desc->addr_lo = src_desc->addr_lo;
1da177e4
LT		 4537 src_map->skb = NULL;
4538}
4539
1da177e4
LT		 4540/* The RX ring scheme is composed of multiple rings which post fresh
4541 * buffers to the chip, and one special ring the chip uses to report
4542 * status back to the host.
4543 *
4544 * The special ring reports the status of received packets to the
4545 * host. The chip does not write into the original descriptor the
4546 * RX buffer was obtained from. The chip simply takes the original
4547 * descriptor as provided by the host, updates the status and length
4548 * field, then writes this into the next status ring entry.
4549 *
4550 * Each ring the host uses to post buffers to the chip is described
4551 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4552 * it is first placed into the on-chip ram. When the packet's length
4553 * is known, it walks down the TG3_BDINFO entries to select the ring.
4554 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4555 * which is within the range of the new packet's length is chosen.
4556 *
4557 * The "separate ring for rx status" scheme may sound queer, but it makes
4558 * sense from a cache coherency perspective. If only the host writes
4559 * to the buffer post rings, and only the chip writes to the rx status
4560 * rings, then cache lines never move beyond shared-modified state.
4561 * If both the host and chip were to write into the same ring, cache line
4562 * eviction could occur since both entities want it in an exclusive state.
4563 */
17375d25 4564static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4565{
17375d25 4566 struct tg3 *tp = tnapi->tp;
f92905de 4567 u32 work_mask, rx_std_posted = 0;
4361935a 4568 u32 std_prod_idx, jmb_prod_idx;
72334482 4569 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4570 u16 hw_idx;
1da177e4 4571 int received;
b196c7e4 4572 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
1da177e4 4573
8d9d7cfc 4574 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4575 /*
4576 * We need to order the read of hw_idx and the read of
4577 * the opaque cookie.
4578 */
4579 rmb();
1da177e4
LT		 4580 work_mask = 0;
4581 received = 0;
4361935a
MC		 4582 std_prod_idx = tpr->rx_std_prod_idx;
4583 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4584 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4585 struct ring_info *ri;
72334482 4586 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4587 unsigned int len;
4588 struct sk_buff *skb;
4589 dma_addr_t dma_addr;
4590 u32 opaque_key, desc_idx, *post_ptr;
4591
4592 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4593 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4594 if (opaque_key == RXD_OPAQUE_RING_STD) {
b196c7e4 4595 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
21f581a5
MC		 4596 dma_addr = pci_unmap_addr(ri, mapping);
4597 skb = ri->skb;
4361935a 4598 post_ptr = &std_prod_idx;
f92905de 4599 rx_std_posted++;
1da177e4 4600 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
b196c7e4 4601 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
21f581a5
MC		 4602 dma_addr = pci_unmap_addr(ri, mapping);
4603 skb = ri->skb;
4361935a 4604 post_ptr = &jmb_prod_idx;
21f581a5 4605 } else
1da177e4 4606 goto next_pkt_nopost;
1da177e4
LT		 4607
4608 work_mask |= opaque_key;
4609
4610 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4611 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4612 drop_it:
a3896167 4613 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4614 desc_idx, *post_ptr);
4615 drop_it_no_recycle:
4616 /* Other statistics kept track of by card. */
4617 tp->net_stats.rx_dropped++;
4618 goto next_pkt;
4619 }
4620
ad829268
MC		 4621 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4622 ETH_FCS_LEN;
1da177e4 4623
6aa20a22 4624 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4625 && tp->rx_offset == NET_IP_ALIGN
4626 /* rx_offset will likely not equal NET_IP_ALIGN
4627 * if this is a 5701 card running in PCI-X mode
4628 * [see tg3_get_invariants()]
4629 */
1da177e4
LT		 4630 ) {
4631 int skb_size;
4632
86b21e59 4633 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4634 *post_ptr);
1da177e4
LT		 4635 if (skb_size < 0)
4636 goto drop_it;
4637
afc081f8
MC		 4638 ri->skb = NULL;
4639
287be12e 4640 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4641 PCI_DMA_FROMDEVICE);
4642
4643 skb_put(skb, len);
4644 } else {
4645 struct sk_buff *copy_skb;
4646
a3896167 4647 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4648 desc_idx, *post_ptr);
4649
ad829268
MC		 4650 copy_skb = netdev_alloc_skb(tp->dev,
4651 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4652 if (copy_skb == NULL)
4653 goto drop_it_no_recycle;
4654
ad829268 4655 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4656 skb_put(copy_skb, len);
4657 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4658 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4659 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4660
4661 /* We'll reuse the original ring buffer. */
4662 skb = copy_skb;
4663 }
4664
4665 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4666 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4667 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4668 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4669 skb->ip_summed = CHECKSUM_UNNECESSARY;
4670 else
4671 skb->ip_summed = CHECKSUM_NONE;
4672
4673 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4674
4675 if (len > (tp->dev->mtu + ETH_HLEN) &&
4676 skb->protocol != htons(ETH_P_8021Q)) {
4677 dev_kfree_skb(skb);
4678 goto next_pkt;
4679 }
4680
1da177e4
LT		 4681#if TG3_VLAN_TAG_USED
4682 if (tp->vlgrp != NULL &&
4683 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4684 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4685 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4686 } else
4687#endif
17375d25 4688 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4689
1da177e4
LT		 4690 received++;
4691 budget--;
4692
4693next_pkt:
4694 (*post_ptr)++;
f92905de
MC		 4695
4696 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4697 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
66711e66 4698 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
f92905de
MC		 4699 work_mask &= ~RXD_OPAQUE_RING_STD;
4700 rx_std_posted = 0;
4701 }
1da177e4 4702next_pkt_nopost:
483ba50b 4703 sw_idx++;
6b31a515 4704 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4705
4706 /* Refresh hw_idx to see if there is new work */
4707 if (sw_idx == hw_idx) {
8d9d7cfc 4708 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4709 rmb();
4710 }
1da177e4
LT		 4711 }
4712
4713 /* ACK the status ring. */
72334482
MC		 4714 tnapi->rx_rcb_ptr = sw_idx;
4715 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4716
4717 /* Refill RX ring(s). */
b196c7e4
MC		 4718 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4719 if (work_mask & RXD_OPAQUE_RING_STD) {
4720 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4721 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4722 tpr->rx_std_prod_idx);
4723 }
4724 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4725 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4726 TG3_RX_JUMBO_RING_SIZE;
4727 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4728 tpr->rx_jmb_prod_idx);
4729 }
4730 mmiowb();
4731 } else if (work_mask) {
4732 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4733 * updated before the producer indices can be updated.
4734 */
4735 smp_wmb();
4736
4361935a 4737 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4361935a 4738 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
b196c7e4
MC		 4739
4740 napi_schedule(&tp->napi[1].napi);
1da177e4 4741 }
1da177e4
LT		 4742
4743 return received;
4744}
4745
35f2d7d0 4746static void tg3_poll_link(struct tg3 *tp)
1da177e4 4747{
1da177e4
LT		 4748 /* handle link change and other phy events */
4749 if (!(tp->tg3_flags &
4750 (TG3_FLAG_USE_LINKCHG_REG |
4751 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4752 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4753
1da177e4
LT		 4754 if (sblk->status & SD_STATUS_LINK_CHG) {
4755 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4756 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4757 spin_lock(&tp->lock);
dd477003
MC		 4758 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4759 tw32_f(MAC_STATUS,
4760 (MAC_STATUS_SYNC_CHANGED |
4761 MAC_STATUS_CFG_CHANGED |
4762 MAC_STATUS_MI_COMPLETION |
4763 MAC_STATUS_LNKSTATE_CHANGED));
4764 udelay(40);
4765 } else
4766 tg3_setup_phy(tp, 0);
f47c11ee 4767 spin_unlock(&tp->lock);
1da177e4
LT		 4768 }
4769 }
35f2d7d0
MC		 4770}
4771
b196c7e4
MC		 4772static void tg3_rx_prodring_xfer(struct tg3 *tp,
4773 struct tg3_rx_prodring_set *dpr,
4774 struct tg3_rx_prodring_set *spr)
4775{
4776 u32 si, di, cpycnt, src_prod_idx;
4777 int i;
4778
4779 while (1) {
4780 src_prod_idx = spr->rx_std_prod_idx;
4781
4782 /* Make sure updates to the rx_std_buffers[] entries and the
4783 * standard producer index are seen in the correct order.
4784 */
4785 smp_rmb();
4786
4787 if (spr->rx_std_cons_idx == src_prod_idx)
4788 break;
4789
4790 if (spr->rx_std_cons_idx < src_prod_idx)
4791 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4792 else
4793 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4794
4795 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4796
4797 si = spr->rx_std_cons_idx;
4798 di = dpr->rx_std_prod_idx;
4799
4800 memcpy(&dpr->rx_std_buffers[di],
4801 &spr->rx_std_buffers[si],
4802 cpycnt * sizeof(struct ring_info));
4803
4804 for (i = 0; i < cpycnt; i++, di++, si++) {
4805 struct tg3_rx_buffer_desc *sbd, *dbd;
4806 sbd = &spr->rx_std[si];
4807 dbd = &dpr->rx_std[di];
4808 dbd->addr_hi = sbd->addr_hi;
4809 dbd->addr_lo = sbd->addr_lo;
4810 }
4811
4812 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4813 TG3_RX_RING_SIZE;
4814 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4815 TG3_RX_RING_SIZE;
4816 }
4817
4818 while (1) {
4819 src_prod_idx = spr->rx_jmb_prod_idx;
4820
4821 /* Make sure updates to the rx_jmb_buffers[] entries and
4822 * the jumbo producer index are seen in the correct order.
4823 */
4824 smp_rmb();
4825
4826 if (spr->rx_jmb_cons_idx == src_prod_idx)
4827 break;
4828
4829 if (spr->rx_jmb_cons_idx < src_prod_idx)
4830 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4831 else
4832 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4833
4834 cpycnt = min(cpycnt,
4835 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4836
4837 si = spr->rx_jmb_cons_idx;
4838 di = dpr->rx_jmb_prod_idx;
4839
4840 memcpy(&dpr->rx_jmb_buffers[di],
4841 &spr->rx_jmb_buffers[si],
4842 cpycnt * sizeof(struct ring_info));
4843
4844 for (i = 0; i < cpycnt; i++, di++, si++) {
4845 struct tg3_rx_buffer_desc *sbd, *dbd;
4846 sbd = &spr->rx_jmb[si].std;
4847 dbd = &dpr->rx_jmb[di].std;
4848 dbd->addr_hi = sbd->addr_hi;
4849 dbd->addr_lo = sbd->addr_lo;
4850 }
4851
4852 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4853 TG3_RX_JUMBO_RING_SIZE;
4854 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4855 TG3_RX_JUMBO_RING_SIZE;
4856 }
4857}
4858
35f2d7d0
MC		 4859static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4860{
4861 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4862
4863 /* run TX completion thread */
f3f3f27e 4864 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4865 tg3_tx(tnapi);
6f535763 4866 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4867 return work_done;
1da177e4
LT		 4868 }
4869
1da177e4
LT		 4870 /* run RX thread, within the bounds set by NAPI.
4871 * All RX "locking" is done by ensuring outside
bea3348e 4872 * code synchronizes with tg3->napi.poll()
1da177e4 4873 */
8d9d7cfc 4874 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4875 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4876
b196c7e4
MC		 4877 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4878 int i;
4879 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4880 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4881
4882 for (i = 2; i < tp->irq_cnt; i++)
4883 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4884 tp->napi[i].prodring);
4885
4886 wmb();
4887
4888 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4889 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4890 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4891 }
4892
4893 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4894 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4895 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4896 }
4897
4898 mmiowb();
4899 }
4900
6f535763
DM		 4901 return work_done;
4902}
4903
35f2d7d0
MC		 4904static int tg3_poll_msix(struct napi_struct *napi, int budget)
4905{
4906 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4907 struct tg3 *tp = tnapi->tp;
4908 int work_done = 0;
4909 struct tg3_hw_status *sblk = tnapi->hw_status;
4910
4911 while (1) {
4912 work_done = tg3_poll_work(tnapi, work_done, budget);
4913
4914 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4915 goto tx_recovery;
4916
4917 if (unlikely(work_done >= budget))
4918 break;
4919
4920 /* tp->last_tag is used in tg3_restart_ints() below
4921 * to tell the hw how much work has been processed,
4922 * so we must read it before checking for more work.
4923 */
4924 tnapi->last_tag = sblk->status_tag;
4925 tnapi->last_irq_tag = tnapi->last_tag;
4926 rmb();
4927
4928 /* check for RX/TX work to do */
4929 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4930 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4931 napi_complete(napi);
4932 /* Reenable interrupts. */
4933 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4934 mmiowb();
4935 break;
4936 }
4937 }
4938
4939 return work_done;
4940
4941tx_recovery:
4942 /* work_done is guaranteed to be less than budget. */
4943 napi_complete(napi);
4944 schedule_work(&tp->reset_task);
4945 return work_done;
4946}
4947
6f535763
DM		 4948static int tg3_poll(struct napi_struct *napi, int budget)
4949{
8ef0442f
MC		 4950 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4951 struct tg3 *tp = tnapi->tp;
6f535763 4952 int work_done = 0;
898a56f8 4953 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4954
4955 while (1) {
35f2d7d0
MC		 4956 tg3_poll_link(tp);
4957
17375d25 4958 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4959
4960 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4961 goto tx_recovery;
4962
4963 if (unlikely(work_done >= budget))
4964 break;
4965
4fd7ab59 4966 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4967 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4968 * to tell the hw how much work has been processed,
4969 * so we must read it before checking for more work.
4970 */
898a56f8
MC		 4971 tnapi->last_tag = sblk->status_tag;
4972 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4973 rmb();
4974 } else
4975 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4976
17375d25 4977 if (likely(!tg3_has_work(tnapi))) {
288379f0 4978 napi_complete(napi);
17375d25 4979 tg3_int_reenable(tnapi);
6f535763
DM		 4980 break;
4981 }
1da177e4
LT		 4982 }
4983
bea3348e 4984 return work_done;
6f535763
DM		 4985
4986tx_recovery:
4fd7ab59 4987 /* work_done is guaranteed to be less than budget. */
288379f0 4988 napi_complete(napi);
6f535763 4989 schedule_work(&tp->reset_task);
4fd7ab59 4990 return work_done;
1da177e4
LT		 4991}
4992
f47c11ee
DM		 4993static void tg3_irq_quiesce(struct tg3 *tp)
4994{
4f125f42
MC		 4995 int i;
4996
f47c11ee
DM		 4997 BUG_ON(tp->irq_sync);
4998
4999 tp->irq_sync = 1;
5000 smp_mb();
5001
4f125f42
MC		 5002 for (i = 0; i < tp->irq_cnt; i++)
5003 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 5004}
5005
5006static inline int tg3_irq_sync(struct tg3 *tp)
5007{
5008 return tp->irq_sync;
5009}
5010
5011/* Fully shutdown all tg3 driver activity elsewhere in the system.
5012 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5013 * with as well. Most of the time, this is not necessary except when
5014 * shutting down the device.
5015 */
5016static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5017{
46966545 5018 spin_lock_bh(&tp->lock);
f47c11ee
DM		 5019 if (irq_sync)
5020 tg3_irq_quiesce(tp);
f47c11ee
DM		 5021}
5022
5023static inline void tg3_full_unlock(struct tg3 *tp)
5024{
f47c11ee
DM		 5025 spin_unlock_bh(&tp->lock);
5026}
5027
fcfa0a32
MC		 5028/* One-shot MSI handler - Chip automatically disables interrupt
5029 * after sending MSI so driver doesn't have to do it.
5030 */
7d12e780 5031static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 5032{
09943a18
MC		 5033 struct tg3_napi *tnapi = dev_id;
5034 struct tg3 *tp = tnapi->tp;
fcfa0a32 5035
898a56f8 5036 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5037 if (tnapi->rx_rcb)
5038 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 5039
5040 if (likely(!tg3_irq_sync(tp)))
09943a18 5041 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 5042
5043 return IRQ_HANDLED;
5044}
5045
88b06bc2
MC		 5046/* MSI ISR - No need to check for interrupt sharing and no need to
5047 * flush status block and interrupt mailbox. PCI ordering rules
5048 * guarantee that MSI will arrive after the status block.
5049 */
7d12e780 5050static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 5051{
09943a18
MC		 5052 struct tg3_napi *tnapi = dev_id;
5053 struct tg3 *tp = tnapi->tp;
88b06bc2 5054
898a56f8 5055 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 5056 if (tnapi->rx_rcb)
5057 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 5058 /*
fac9b83e 5059 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 5060 * chip-internal interrupt pending events.
fac9b83e 5061 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 5062 * NIC to stop sending us irqs, engaging "in-intr-handler"
5063 * event coalescing.
5064 */
5065 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 5066 if (likely(!tg3_irq_sync(tp)))
09943a18 5067 napi_schedule(&tnapi->napi);
61487480 5068
88b06bc2
MC		 5069 return IRQ_RETVAL(1);
5070}
5071
7d12e780 5072static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 5073{
09943a18
MC		 5074 struct tg3_napi *tnapi = dev_id;
5075 struct tg3 *tp = tnapi->tp;
898a56f8 5076 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 5077 unsigned int handled = 1;
5078
1da177e4
LT		 5079 /* In INTx mode, it is possible for the interrupt to arrive at
5080 * the CPU before the status block posted prior to the interrupt.
5081 * Reading the PCI State register will confirm whether the
5082 * interrupt is ours and will flush the status block.
5083 */
d18edcb2
MC		 5084 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5085 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5086 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5087 handled = 0;
f47c11ee 5088 goto out;
fac9b83e 5089 }
d18edcb2
MC		 5090 }
5091
5092 /*
5093 * Writing any value to intr-mbox-0 clears PCI INTA# and
5094 * chip-internal interrupt pending events.
5095 * Writing non-zero to intr-mbox-0 additional tells the
5096 * NIC to stop sending us irqs, engaging "in-intr-handler"
5097 * event coalescing.
c04cb347
MC		 5098 *
5099 * Flush the mailbox to de-assert the IRQ immediately to prevent
5100 * spurious interrupts. The flush impacts performance but
5101 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5102 */
c04cb347 5103 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 5104 if (tg3_irq_sync(tp))
5105 goto out;
5106 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 5107 if (likely(tg3_has_work(tnapi))) {
72334482 5108 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 5109 napi_schedule(&tnapi->napi);
d18edcb2
MC		 5110 } else {
5111 /* No work, shared interrupt perhaps? re-enable
5112 * interrupts, and flush that PCI write
5113 */
5114 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5115 0x00000000);
fac9b83e 5116 }
f47c11ee 5117out:
fac9b83e
DM		 5118 return IRQ_RETVAL(handled);
5119}
5120
7d12e780 5121static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 5122{
09943a18
MC		 5123 struct tg3_napi *tnapi = dev_id;
5124 struct tg3 *tp = tnapi->tp;
898a56f8 5125 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 5126 unsigned int handled = 1;
5127
fac9b83e
DM		 5128 /* In INTx mode, it is possible for the interrupt to arrive at
5129 * the CPU before the status block posted prior to the interrupt.
5130 * Reading the PCI State register will confirm whether the
5131 * interrupt is ours and will flush the status block.
5132 */
898a56f8 5133 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5134 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5135 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5136 handled = 0;
f47c11ee 5137 goto out;
1da177e4 5138 }
d18edcb2
MC		 5139 }
5140
5141 /*
5142 * writing any value to intr-mbox-0 clears PCI INTA# and
5143 * chip-internal interrupt pending events.
5144 * writing non-zero to intr-mbox-0 additional tells the
5145 * NIC to stop sending us irqs, engaging "in-intr-handler"
5146 * event coalescing.
c04cb347
MC		 5147 *
5148 * Flush the mailbox to de-assert the IRQ immediately to prevent
5149 * spurious interrupts. The flush impacts performance but
5150 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5151 */
c04cb347 5152 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5153
5154 /*
5155 * In a shared interrupt configuration, sometimes other devices'
5156 * interrupts will scream. We record the current status tag here
5157 * so that the above check can report that the screaming interrupts
5158 * are unhandled. Eventually they will be silenced.
5159 */
898a56f8 5160 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5161
d18edcb2
MC		 5162 if (tg3_irq_sync(tp))
5163 goto out;
624f8e50 5164
72334482 5165 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5166
09943a18 5167 napi_schedule(&tnapi->napi);
624f8e50 5168
f47c11ee 5169out:
1da177e4
LT		 5170 return IRQ_RETVAL(handled);
5171}
5172
7938109f 5173/* ISR for interrupt test */
7d12e780 5174static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5175{
09943a18
MC		 5176 struct tg3_napi *tnapi = dev_id;
5177 struct tg3 *tp = tnapi->tp;
898a56f8 5178 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5179
f9804ddb
MC		 5180 if ((sblk->status & SD_STATUS_UPDATED) ||
5181 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5182 tg3_disable_ints(tp);
7938109f
MC		 5183 return IRQ_RETVAL(1);
5184 }
5185 return IRQ_RETVAL(0);
5186}
5187
8e7a22e3 5188static int tg3_init_hw(struct tg3 *, int);
944d980e 5189static int tg3_halt(struct tg3 *, int, int);
1da177e4 5190
b9ec6c1b
MC		 5191/* Restart hardware after configuration changes, self-test, etc.
5192 * Invoked with tp->lock held.
5193 */
5194static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5195 __releases(tp->lock)
5196 __acquires(tp->lock)
b9ec6c1b
MC		 5197{
5198 int err;
5199
5200 err = tg3_init_hw(tp, reset_phy);
5201 if (err) {
5202 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5203 "aborting.\n", tp->dev->name);
5204 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5205 tg3_full_unlock(tp);
5206 del_timer_sync(&tp->timer);
5207 tp->irq_sync = 0;
fed97810 5208 tg3_napi_enable(tp);
b9ec6c1b
MC		 5209 dev_close(tp->dev);
5210 tg3_full_lock(tp, 0);
5211 }
5212 return err;
5213}
5214
1da177e4
LT		 5215#ifdef CONFIG_NET_POLL_CONTROLLER
5216static void tg3_poll_controller(struct net_device *dev)
5217{
4f125f42 5218 int i;
88b06bc2
MC		 5219 struct tg3 *tp = netdev_priv(dev);
5220
4f125f42
MC		 5221 for (i = 0; i < tp->irq_cnt; i++)
5222 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5223}
5224#endif
5225
c4028958 5226static void tg3_reset_task(struct work_struct *work)
1da177e4 5227{
c4028958 5228 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5229 int err;
1da177e4
LT		 5230 unsigned int restart_timer;
5231
7faa006f 5232 tg3_full_lock(tp, 0);
7faa006f
MC		 5233
5234 if (!netif_running(tp->dev)) {
7faa006f
MC		 5235 tg3_full_unlock(tp);
5236 return;
5237 }
5238
5239 tg3_full_unlock(tp);
5240
b02fd9e3
MC		 5241 tg3_phy_stop(tp);
5242
1da177e4
LT		 5243 tg3_netif_stop(tp);
5244
f47c11ee 5245 tg3_full_lock(tp, 1);
1da177e4
LT		 5246
5247 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5248 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5249
df3e6548
MC		 5250 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5251 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5252 tp->write32_rx_mbox = tg3_write_flush_reg32;
5253 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5254 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5255 }
5256
944d980e 5257 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5258 err = tg3_init_hw(tp, 1);
5259 if (err)
b9ec6c1b 5260 goto out;
1da177e4
LT		 5261
5262 tg3_netif_start(tp);
5263
1da177e4
LT		 5264 if (restart_timer)
5265 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5266
b9ec6c1b 5267out:
7faa006f 5268 tg3_full_unlock(tp);
b02fd9e3
MC		 5269
5270 if (!err)
5271 tg3_phy_start(tp);
1da177e4
LT		 5272}
5273
b0408751
MC		 5274static void tg3_dump_short_state(struct tg3 *tp)
5275{
5276 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5277 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5278 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5279 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5280}
5281
1da177e4
LT		 5282static void tg3_tx_timeout(struct net_device *dev)
5283{
5284 struct tg3 *tp = netdev_priv(dev);
5285
b0408751 5286 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5287 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5288 dev->name);
b0408751
MC		 5289 tg3_dump_short_state(tp);
5290 }
1da177e4
LT		 5291
5292 schedule_work(&tp->reset_task);
5293}
5294
c58ec932
MC		 5295/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5296static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5297{
5298 u32 base = (u32) mapping & 0xffffffff;
5299
5300 return ((base > 0xffffdcc0) &&
5301 (base + len + 8 < base));
5302}
5303
72f2afb8
MC		 5304/* Test for DMA addresses > 40-bit */
5305static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5306 int len)
5307{
5308#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5309 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5310 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5311 return 0;
5312#else
5313 return 0;
5314#endif
5315}
5316
f3f3f27e 5317static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5318
72f2afb8 5319/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5320static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5321 struct sk_buff *skb, u32 last_plus_one,
5322 u32 *start, u32 base_flags, u32 mss)
1da177e4 5323{
24f4efd4 5324 struct tg3 *tp = tnapi->tp;
41588ba1 5325 struct sk_buff *new_skb;
c58ec932 5326 dma_addr_t new_addr = 0;
1da177e4 5327 u32 entry = *start;
c58ec932 5328 int i, ret = 0;
1da177e4 5329
41588ba1
MC		 5330 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5331 new_skb = skb_copy(skb, GFP_ATOMIC);
5332 else {
5333 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5334
5335 new_skb = skb_copy_expand(skb,
5336 skb_headroom(skb) + more_headroom,
5337 skb_tailroom(skb), GFP_ATOMIC);
5338 }
5339
1da177e4 5340 if (!new_skb) {
c58ec932
MC		 5341 ret = -1;
5342 } else {
5343 /* New SKB is guaranteed to be linear. */
5344 entry = *start;
f4188d8a
AD		 5345 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5346 PCI_DMA_TODEVICE);
5347 /* Make sure the mapping succeeded */
5348 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5349 ret = -1;
5350 dev_kfree_skb(new_skb);
5351 new_skb = NULL;
90079ce8 5352
c58ec932
MC		 5353 /* Make sure new skb does not cross any 4G boundaries.
5354 * Drop the packet if it does.
5355 */
f4188d8a
AD		 5356 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5357 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5358 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5359 PCI_DMA_TODEVICE);
c58ec932
MC		 5360 ret = -1;
5361 dev_kfree_skb(new_skb);
5362 new_skb = NULL;
5363 } else {
f3f3f27e 5364 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5365 base_flags, 1 | (mss << 1));
5366 *start = NEXT_TX(entry);
5367 }
1da177e4
LT		 5368 }
5369
1da177e4
LT		 5370 /* Now clean up the sw ring entries. */
5371 i = 0;
5372 while (entry != last_plus_one) {
f4188d8a
AD		 5373 int len;
5374
f3f3f27e 5375 if (i == 0)
f4188d8a 5376 len = skb_headlen(skb);
f3f3f27e 5377 else
f4188d8a
AD		 5378 len = skb_shinfo(skb)->frags[i-1].size;
5379
5380 pci_unmap_single(tp->pdev,
5381 pci_unmap_addr(&tnapi->tx_buffers[entry],
5382 mapping),
5383 len, PCI_DMA_TODEVICE);
5384 if (i == 0) {
5385 tnapi->tx_buffers[entry].skb = new_skb;
5386 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5387 new_addr);
5388 } else {
f3f3f27e 5389 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a 5390 }
1da177e4
LT		 5391 entry = NEXT_TX(entry);
5392 i++;
5393 }
5394
5395 dev_kfree_skb(skb);
5396
c58ec932 5397 return ret;
1da177e4
LT		 5398}
5399
f3f3f27e 5400static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5401 dma_addr_t mapping, int len, u32 flags,
5402 u32 mss_and_is_end)
5403{
f3f3f27e 5404 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5405 int is_end = (mss_and_is_end & 0x1);
5406 u32 mss = (mss_and_is_end >> 1);
5407 u32 vlan_tag = 0;
5408
5409 if (is_end)
5410 flags |= TXD_FLAG_END;
5411 if (flags & TXD_FLAG_VLAN) {
5412 vlan_tag = flags >> 16;
5413 flags &= 0xffff;
5414 }
5415 vlan_tag |= (mss << TXD_MSS_SHIFT);
5416
5417 txd->addr_hi = ((u64) mapping >> 32);
5418 txd->addr_lo = ((u64) mapping & 0xffffffff);
5419 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5420 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5421}
5422
5a6f3074 5423/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5424 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5425 */
61357325
SH		 5426static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5427 struct net_device *dev)
5a6f3074
MC		 5428{
5429 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5430 u32 len, entry, base_flags, mss;
90079ce8 5431 dma_addr_t mapping;
fe5f5787
MC		 5432 struct tg3_napi *tnapi;
5433 struct netdev_queue *txq;
f4188d8a
AD		 5434 unsigned int i, last;
5435
5a6f3074 5436
fe5f5787
MC		 5437 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5438 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5439 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5440 tnapi++;
5a6f3074 5441
00b70504 5442 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5443 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5444 * interrupt. Furthermore, IRQ processing runs lockless so we have
5445 * no IRQ context deadlocks to worry about either. Rejoice!
5446 */
f3f3f27e 5447 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5448 if (!netif_tx_queue_stopped(txq)) {
5449 netif_tx_stop_queue(txq);
5a6f3074
MC		 5450
5451 /* This is a hard error, log it. */
5452 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5453 "queue awake!\n", dev->name);
5454 }
5a6f3074
MC		 5455 return NETDEV_TX_BUSY;
5456 }
5457
f3f3f27e 5458 entry = tnapi->tx_prod;
5a6f3074 5459 base_flags = 0;
5a6f3074 5460 mss = 0;
c13e3713 5461 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5462 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5463 u32 hdrlen;
5a6f3074
MC		 5464
5465 if (skb_header_cloned(skb) &&
5466 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5467 dev_kfree_skb(skb);
5468 goto out_unlock;
5469 }
5470
b0026624 5471 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5472 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5473 else {
eddc9ec5
ACM		 5474 struct iphdr *iph = ip_hdr(skb);
5475
ab6a5bb6 5476 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5477 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5478
eddc9ec5
ACM		 5479 iph->check = 0;
5480 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5481 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5482 }
5a6f3074 5483
e849cdc3 5484 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5485 mss |= (hdrlen & 0xc) << 12;
5486 if (hdrlen & 0x10)
5487 base_flags |= 0x00000010;
5488 base_flags |= (hdrlen & 0x3e0) << 5;
5489 } else
5490 mss |= hdrlen << 9;
5491
5a6f3074
MC		 5492 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5493 TXD_FLAG_CPU_POST_DMA);
5494
aa8223c7 5495 tcp_hdr(skb)->check = 0;
5a6f3074 5496
5a6f3074 5497 }
84fa7933 5498 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5499 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5500#if TG3_VLAN_TAG_USED
5501 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5502 base_flags |= (TXD_FLAG_VLAN |
5503 (vlan_tx_tag_get(skb) << 16));
5504#endif
5505
f4188d8a
AD		 5506 len = skb_headlen(skb);
5507
5508 /* Queue skb data, a.k.a. the main skb fragment. */
5509 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5510 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5511 dev_kfree_skb(skb);
5512 goto out_unlock;
5513 }
5514
f3f3f27e 5515 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5516 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
fe5f5787 5517
f6eb9b1f
MC		 5518 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5519 !mss && skb->len > ETH_DATA_LEN)
5520 base_flags |= TXD_FLAG_JMB_PKT;
5521
f3f3f27e 5522 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5523 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5524
5525 entry = NEXT_TX(entry);
5526
5527 /* Now loop through additional data fragments, and queue them. */
5528 if (skb_shinfo(skb)->nr_frags > 0) {
5a6f3074
MC		 5529 last = skb_shinfo(skb)->nr_frags - 1;
5530 for (i = 0; i <= last; i++) {
5531 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5532
5533 len = frag->size;
f4188d8a
AD		 5534 mapping = pci_map_page(tp->pdev,
5535 frag->page,
5536 frag->page_offset,
5537 len, PCI_DMA_TODEVICE);
5538 if (pci_dma_mapping_error(tp->pdev, mapping))
5539 goto dma_error;
5540
f3f3f27e 5541 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5542 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5543 mapping);
5a6f3074 5544
f3f3f27e 5545 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5546 base_flags, (i == last) | (mss << 1));
5547
5548 entry = NEXT_TX(entry);
5549 }
5550 }
5551
5552 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5553 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5554
f3f3f27e
MC		 5555 tnapi->tx_prod = entry;
5556 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5557 netif_tx_stop_queue(txq);
f3f3f27e 5558 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5559 netif_tx_wake_queue(txq);
5a6f3074
MC		 5560 }
5561
5562out_unlock:
cdd0db05 5563 mmiowb();
5a6f3074
MC		 5564
5565 return NETDEV_TX_OK;
f4188d8a
AD		 5566
5567dma_error:
5568 last = i;
5569 entry = tnapi->tx_prod;
5570 tnapi->tx_buffers[entry].skb = NULL;
5571 pci_unmap_single(tp->pdev,
5572 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5573 skb_headlen(skb),
5574 PCI_DMA_TODEVICE);
5575 for (i = 0; i <= last; i++) {
5576 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5577 entry = NEXT_TX(entry);
5578
5579 pci_unmap_page(tp->pdev,
5580 pci_unmap_addr(&tnapi->tx_buffers[entry],
5581 mapping),
5582 frag->size, PCI_DMA_TODEVICE);
5583 }
5584
5585 dev_kfree_skb(skb);
5586 return NETDEV_TX_OK;
5a6f3074
MC		 5587}
5588
61357325
SH		 5589static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5590 struct net_device *);
52c0fd83
MC		 5591
5592/* Use GSO to workaround a rare TSO bug that may be triggered when the
5593 * TSO header is greater than 80 bytes.
5594 */
5595static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5596{
5597 struct sk_buff *segs, *nskb;
f3f3f27e 5598 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5599
5600 /* Estimate the number of fragments in the worst case */
f3f3f27e 5601 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5602 netif_stop_queue(tp->dev);
f3f3f27e 5603 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5604 return NETDEV_TX_BUSY;
5605
5606 netif_wake_queue(tp->dev);
52c0fd83
MC		 5607 }
5608
5609 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5610 if (IS_ERR(segs))
52c0fd83
MC		 5611 goto tg3_tso_bug_end;
5612
5613 do {
5614 nskb = segs;
5615 segs = segs->next;
5616 nskb->next = NULL;
5617 tg3_start_xmit_dma_bug(nskb, tp->dev);
5618 } while (segs);
5619
5620tg3_tso_bug_end:
5621 dev_kfree_skb(skb);
5622
5623 return NETDEV_TX_OK;
5624}
52c0fd83 5625
5a6f3074
MC		 5626/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5627 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5628 */
61357325
SH		 5629static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5630 struct net_device *dev)
1da177e4
LT		 5631{
5632 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 5633 u32 len, entry, base_flags, mss;
5634 int would_hit_hwbug;
90079ce8 5635 dma_addr_t mapping;
24f4efd4
MC		 5636 struct tg3_napi *tnapi;
5637 struct netdev_queue *txq;
f4188d8a
AD		 5638 unsigned int i, last;
5639
1da177e4 5640
24f4efd4
MC		 5641 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5642 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5643 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5644 tnapi++;
1da177e4 5645
00b70504 5646 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5647 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5648 * interrupt. Furthermore, IRQ processing runs lockless so we have
5649 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5650 */
f3f3f27e 5651 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5652 if (!netif_tx_queue_stopped(txq)) {
5653 netif_tx_stop_queue(txq);
1f064a87
SH		 5654
5655 /* This is a hard error, log it. */
5656 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5657 "queue awake!\n", dev->name);
5658 }
1da177e4
LT		 5659 return NETDEV_TX_BUSY;
5660 }
5661
f3f3f27e 5662 entry = tnapi->tx_prod;
1da177e4 5663 base_flags = 0;
84fa7933 5664 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5665 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5666
c13e3713 5667 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5668 struct iphdr *iph;
92c6b8d1 5669 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5670
5671 if (skb_header_cloned(skb) &&
5672 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5673 dev_kfree_skb(skb);
5674 goto out_unlock;
5675 }
5676
ab6a5bb6 5677 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5678 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5679
52c0fd83
MC		 5680 hdr_len = ip_tcp_len + tcp_opt_len;
5681 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5682 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5683 return (tg3_tso_bug(tp, skb));
5684
1da177e4
LT		 5685 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5686 TXD_FLAG_CPU_POST_DMA);
5687
eddc9ec5
ACM		 5688 iph = ip_hdr(skb);
5689 iph->check = 0;
5690 iph->tot_len = htons(mss + hdr_len);
1da177e4 5691 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5692 tcp_hdr(skb)->check = 0;
1da177e4 5693 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5694 } else
5695 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5696 iph->daddr, 0,
5697 IPPROTO_TCP,
5698 0);
1da177e4 5699
615774fe
MC		 5700 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5701 mss |= (hdr_len & 0xc) << 12;
5702 if (hdr_len & 0x10)
5703 base_flags |= 0x00000010;
5704 base_flags |= (hdr_len & 0x3e0) << 5;
5705 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5706 mss |= hdr_len << 9;
5707 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5709 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5710 int tsflags;
5711
eddc9ec5 5712 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5713 mss |= (tsflags << 11);
5714 }
5715 } else {
eddc9ec5 5716 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5717 int tsflags;
5718
eddc9ec5 5719 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5720 base_flags |= tsflags << 12;
5721 }
5722 }
5723 }
1da177e4
LT		 5724#if TG3_VLAN_TAG_USED
5725 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5726 base_flags |= (TXD_FLAG_VLAN |
5727 (vlan_tx_tag_get(skb) << 16));
5728#endif
5729
615774fe
MC		 5730 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5731 !mss && skb->len > ETH_DATA_LEN)
5732 base_flags |= TXD_FLAG_JMB_PKT;
5733
f4188d8a
AD		 5734 len = skb_headlen(skb);
5735
5736 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5737 if (pci_dma_mapping_error(tp->pdev, mapping)) {
90079ce8
DM		 5738 dev_kfree_skb(skb);
5739 goto out_unlock;
5740 }
5741
f3f3f27e 5742 tnapi->tx_buffers[entry].skb = skb;
f4188d8a 5743 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 5744
5745 would_hit_hwbug = 0;
5746
92c6b8d1
MC		 5747 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5748 would_hit_hwbug = 1;
5749
0e1406dd
MC		 5750 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5751 tg3_4g_overflow_test(mapping, len))
5752 would_hit_hwbug = 1;
5753
5754 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5755 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5756 would_hit_hwbug = 1;
0e1406dd
MC		 5757
5758 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5759 would_hit_hwbug = 1;
1da177e4 5760
f3f3f27e 5761 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5762 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5763
5764 entry = NEXT_TX(entry);
5765
5766 /* Now loop through additional data fragments, and queue them. */
5767 if (skb_shinfo(skb)->nr_frags > 0) {
1da177e4
LT		 5768 last = skb_shinfo(skb)->nr_frags - 1;
5769 for (i = 0; i <= last; i++) {
5770 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5771
5772 len = frag->size;
f4188d8a
AD		 5773 mapping = pci_map_page(tp->pdev,
5774 frag->page,
5775 frag->page_offset,
5776 len, PCI_DMA_TODEVICE);
1da177e4 5777
f3f3f27e 5778 tnapi->tx_buffers[entry].skb = NULL;
f4188d8a
AD		 5779 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5780 mapping);
5781 if (pci_dma_mapping_error(tp->pdev, mapping))
5782 goto dma_error;
1da177e4 5783
92c6b8d1
MC		 5784 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5785 len <= 8)
5786 would_hit_hwbug = 1;
5787
0e1406dd
MC		 5788 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5789 tg3_4g_overflow_test(mapping, len))
c58ec932 5790 would_hit_hwbug = 1;
1da177e4 5791
0e1406dd
MC		 5792 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5793 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5794 would_hit_hwbug = 1;
5795
1da177e4 5796 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5797 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5798 base_flags, (i == last)|(mss << 1));
5799 else
f3f3f27e 5800 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5801 base_flags, (i == last));
5802
5803 entry = NEXT_TX(entry);
5804 }
5805 }
5806
5807 if (would_hit_hwbug) {
5808 u32 last_plus_one = entry;
5809 u32 start;
1da177e4 5810
c58ec932
MC		 5811 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5812 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5813
5814 /* If the workaround fails due to memory/mapping
5815 * failure, silently drop this packet.
5816 */
24f4efd4 5817 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5818 &start, base_flags, mss))
1da177e4
LT		 5819 goto out_unlock;
5820
5821 entry = start;
5822 }
5823
5824 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5825 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5826
f3f3f27e
MC		 5827 tnapi->tx_prod = entry;
5828 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5829 netif_tx_stop_queue(txq);
f3f3f27e 5830 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5831 netif_tx_wake_queue(txq);
51b91468 5832 }
1da177e4
LT		 5833
5834out_unlock:
cdd0db05 5835 mmiowb();
1da177e4
LT		 5836
5837 return NETDEV_TX_OK;
f4188d8a
AD		 5838
5839dma_error:
5840 last = i;
5841 entry = tnapi->tx_prod;
5842 tnapi->tx_buffers[entry].skb = NULL;
5843 pci_unmap_single(tp->pdev,
5844 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5845 skb_headlen(skb),
5846 PCI_DMA_TODEVICE);
5847 for (i = 0; i <= last; i++) {
5848 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5849 entry = NEXT_TX(entry);
5850
5851 pci_unmap_page(tp->pdev,
5852 pci_unmap_addr(&tnapi->tx_buffers[entry],
5853 mapping),
5854 frag->size, PCI_DMA_TODEVICE);
5855 }
5856
5857 dev_kfree_skb(skb);
5858 return NETDEV_TX_OK;
1da177e4
LT		 5859}
5860
5861static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5862 int new_mtu)
5863{
5864 dev->mtu = new_mtu;
5865
ef7f5ec0 5866 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5867 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5868 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5869 ethtool_op_set_tso(dev, 0);
5870 }
5871 else
5872 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5873 } else {
a4e2b347 5874 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5875 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5876 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5877 }
1da177e4
LT		 5878}
5879
5880static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5881{
5882 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5883 int err;
1da177e4
LT		 5884
5885 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5886 return -EINVAL;
5887
5888 if (!netif_running(dev)) {
5889 /* We'll just catch it later when the
5890 * device is up'd.
5891 */
5892 tg3_set_mtu(dev, tp, new_mtu);
5893 return 0;
5894 }
5895
b02fd9e3
MC		 5896 tg3_phy_stop(tp);
5897
1da177e4 5898 tg3_netif_stop(tp);
f47c11ee
DM		 5899
5900 tg3_full_lock(tp, 1);
1da177e4 5901
944d980e 5902 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5903
5904 tg3_set_mtu(dev, tp, new_mtu);
5905
b9ec6c1b 5906 err = tg3_restart_hw(tp, 0);
1da177e4 5907
b9ec6c1b
MC		 5908 if (!err)
5909 tg3_netif_start(tp);
1da177e4 5910
f47c11ee 5911 tg3_full_unlock(tp);
1da177e4 5912
b02fd9e3
MC		 5913 if (!err)
5914 tg3_phy_start(tp);
5915
b9ec6c1b 5916 return err;
1da177e4
LT		 5917}
5918
21f581a5
MC		 5919static void tg3_rx_prodring_free(struct tg3 *tp,
5920 struct tg3_rx_prodring_set *tpr)
1da177e4 5921{
1da177e4
LT		 5922 int i;
5923
b196c7e4
MC		 5924 if (tpr != &tp->prodring[0]) {
5925 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5926 i = (i + 1) % TG3_RX_RING_SIZE)
5927 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5928 tp->rx_pkt_map_sz);
5929
5930 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5931 for (i = tpr->rx_jmb_cons_idx;
5932 i != tpr->rx_jmb_prod_idx;
5933 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5934 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5935 TG3_RX_JMB_MAP_SZ);
5936 }
5937 }
5938
2b2cdb65 5939 return;
b196c7e4 5940 }
1da177e4 5941
2b2cdb65
MC		 5942 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5943 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5944 tp->rx_pkt_map_sz);
1da177e4 5945
cf7a7298 5946 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 5947 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5948 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5949 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 5950 }
5951}
5952
5953/* Initialize tx/rx rings for packet processing.
5954 *
5955 * The chip has been shut down and the driver detached from
5956 * the networking, so no interrupts or new tx packets will
5957 * end up in the driver. tp->{tx,}lock are held and thus
5958 * we may not sleep.
5959 */
21f581a5
MC		 5960static int tg3_rx_prodring_alloc(struct tg3 *tp,
5961 struct tg3_rx_prodring_set *tpr)
1da177e4 5962{
287be12e 5963 u32 i, rx_pkt_dma_sz;
1da177e4 5964
b196c7e4
MC		 5965 tpr->rx_std_cons_idx = 0;
5966 tpr->rx_std_prod_idx = 0;
5967 tpr->rx_jmb_cons_idx = 0;
5968 tpr->rx_jmb_prod_idx = 0;
5969
2b2cdb65
MC		 5970 if (tpr != &tp->prodring[0]) {
5971 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5972 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5973 memset(&tpr->rx_jmb_buffers[0], 0,
5974 TG3_RX_JMB_BUFF_RING_SIZE);
5975 goto done;
5976 }
5977
1da177e4 5978 /* Zero out all descriptors. */
21f581a5 5979 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5980
287be12e 5981 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5982 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5983 tp->dev->mtu > ETH_DATA_LEN)
5984 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5985 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5986
1da177e4
LT		 5987 /* Initialize invariants of the rings, we only set this
5988 * stuff once. This works because the card does not
5989 * write into the rx buffer posting rings.
5990 */
5991 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5992 struct tg3_rx_buffer_desc *rxd;
5993
21f581a5 5994 rxd = &tpr->rx_std[i];
287be12e 5995 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5996 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5997 rxd->opaque = (RXD_OPAQUE_RING_STD |
5998 (i << RXD_OPAQUE_INDEX_SHIFT));
5999 }
6000
1da177e4
LT		 6001 /* Now allocate fresh SKBs for each rx ring. */
6002 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 6003 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 6004 printk(KERN_WARNING PFX
6005 "%s: Using a smaller RX standard ring, "
6006 "only %d out of %d buffers were allocated "
6007 "successfully.\n",
6008 tp->dev->name, i, tp->rx_pending);
6009 if (i == 0)
cf7a7298 6010 goto initfail;
32d8c572 6011 tp->rx_pending = i;
1da177e4 6012 break;
32d8c572 6013 }
1da177e4
LT		 6014 }
6015
cf7a7298
MC		 6016 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6017 goto done;
6018
21f581a5 6019 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 6020
0f893dc6 6021 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 6022 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6023 struct tg3_rx_buffer_desc *rxd;
6024
79ed5ac7 6025 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 6026 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6027 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6028 RXD_FLAG_JUMBO;
6029 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6030 (i << RXD_OPAQUE_INDEX_SHIFT));
6031 }
6032
1da177e4 6033 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 6034 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 6035 i) < 0) {
32d8c572
MC		 6036 printk(KERN_WARNING PFX
6037 "%s: Using a smaller RX jumbo ring, "
6038 "only %d out of %d buffers were "
6039 "allocated successfully.\n",
6040 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 6041 if (i == 0)
6042 goto initfail;
32d8c572 6043 tp->rx_jumbo_pending = i;
1da177e4 6044 break;
32d8c572 6045 }
1da177e4
LT		 6046 }
6047 }
cf7a7298
MC		 6048
6049done:
32d8c572 6050 return 0;
cf7a7298
MC		 6051
6052initfail:
21f581a5 6053 tg3_rx_prodring_free(tp, tpr);
cf7a7298 6054 return -ENOMEM;
1da177e4
LT		 6055}
6056
21f581a5
MC		 6057static void tg3_rx_prodring_fini(struct tg3 *tp,
6058 struct tg3_rx_prodring_set *tpr)
1da177e4 6059{
21f581a5
MC		 6060 kfree(tpr->rx_std_buffers);
6061 tpr->rx_std_buffers = NULL;
6062 kfree(tpr->rx_jmb_buffers);
6063 tpr->rx_jmb_buffers = NULL;
6064 if (tpr->rx_std) {
1da177e4 6065 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 6066 tpr->rx_std, tpr->rx_std_mapping);
6067 tpr->rx_std = NULL;
1da177e4 6068 }
21f581a5 6069 if (tpr->rx_jmb) {
1da177e4 6070 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 6071 tpr->rx_jmb, tpr->rx_jmb_mapping);
6072 tpr->rx_jmb = NULL;
1da177e4 6073 }
cf7a7298
MC		 6074}
6075
21f581a5
MC		 6076static int tg3_rx_prodring_init(struct tg3 *tp,
6077 struct tg3_rx_prodring_set *tpr)
cf7a7298 6078{
2b2cdb65 6079 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 6080 if (!tpr->rx_std_buffers)
cf7a7298
MC		 6081 return -ENOMEM;
6082
21f581a5
MC		 6083 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6084 &tpr->rx_std_mapping);
6085 if (!tpr->rx_std)
cf7a7298
MC		 6086 goto err_out;
6087
6088 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 6089 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 6090 GFP_KERNEL);
6091 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 6092 goto err_out;
6093
21f581a5
MC		 6094 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6095 TG3_RX_JUMBO_RING_BYTES,
6096 &tpr->rx_jmb_mapping);
6097 if (!tpr->rx_jmb)
cf7a7298
MC		 6098 goto err_out;
6099 }
6100
6101 return 0;
6102
6103err_out:
21f581a5 6104 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 6105 return -ENOMEM;
6106}
6107
6108/* Free up pending packets in all rx/tx rings.
6109 *
6110 * The chip has been shut down and the driver detached from
6111 * the networking, so no interrupts or new tx packets will
6112 * end up in the driver. tp->{tx,}lock is not held and we are not
6113 * in an interrupt context and thus may sleep.
6114 */
6115static void tg3_free_rings(struct tg3 *tp)
6116{
f77a6a8e 6117 int i, j;
cf7a7298 6118
f77a6a8e
MC		 6119 for (j = 0; j < tp->irq_cnt; j++) {
6120 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 6121
0c1d0e2b
MC		 6122 if (!tnapi->tx_buffers)
6123 continue;
6124
f77a6a8e 6125 for (i = 0; i < TG3_TX_RING_SIZE; ) {
f4188d8a 6126 struct ring_info *txp;
f77a6a8e 6127 struct sk_buff *skb;
f4188d8a 6128 unsigned int k;
cf7a7298 6129
f77a6a8e
MC		 6130 txp = &tnapi->tx_buffers[i];
6131 skb = txp->skb;
cf7a7298 6132
f77a6a8e
MC		 6133 if (skb == NULL) {
6134 i++;
6135 continue;
6136 }
cf7a7298 6137
f4188d8a
AD		 6138 pci_unmap_single(tp->pdev,
6139 pci_unmap_addr(txp, mapping),
6140 skb_headlen(skb),
6141 PCI_DMA_TODEVICE);
f77a6a8e 6142 txp->skb = NULL;
cf7a7298 6143
f4188d8a
AD		 6144 i++;
6145
6146 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6147 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6148 pci_unmap_page(tp->pdev,
6149 pci_unmap_addr(txp, mapping),
6150 skb_shinfo(skb)->frags[k].size,
6151 PCI_DMA_TODEVICE);
6152 i++;
6153 }
f77a6a8e
MC		 6154
6155 dev_kfree_skb_any(skb);
6156 }
cf7a7298 6157
2b2cdb65
MC		 6158 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6159 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6160 }
cf7a7298
MC		 6161}
6162
6163/* Initialize tx/rx rings for packet processing.
6164 *
6165 * The chip has been shut down and the driver detached from
6166 * the networking, so no interrupts or new tx packets will
6167 * end up in the driver. tp->{tx,}lock are held and thus
6168 * we may not sleep.
6169 */
6170static int tg3_init_rings(struct tg3 *tp)
6171{
f77a6a8e 6172 int i;
72334482 6173
cf7a7298
MC		 6174 /* Free up all the SKBs. */
6175 tg3_free_rings(tp);
6176
f77a6a8e
MC		 6177 for (i = 0; i < tp->irq_cnt; i++) {
6178 struct tg3_napi *tnapi = &tp->napi[i];
6179
6180 tnapi->last_tag = 0;
6181 tnapi->last_irq_tag = 0;
6182 tnapi->hw_status->status = 0;
6183 tnapi->hw_status->status_tag = 0;
6184 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 6185
f77a6a8e
MC		 6186 tnapi->tx_prod = 0;
6187 tnapi->tx_cons = 0;
0c1d0e2b
MC		 6188 if (tnapi->tx_ring)
6189 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 6190
6191 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 6192 if (tnapi->rx_rcb)
6193 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65
MC		 6194
6195 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6196 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6197 return -ENOMEM;
f77a6a8e 6198 }
72334482 6199
2b2cdb65 6200 return 0;
cf7a7298
MC		 6201}
6202
6203/*
6204 * Must not be invoked with interrupt sources disabled and
6205 * the hardware shutdown down.
6206 */
6207static void tg3_free_consistent(struct tg3 *tp)
6208{
f77a6a8e 6209 int i;
898a56f8 6210
f77a6a8e
MC		 6211 for (i = 0; i < tp->irq_cnt; i++) {
6212 struct tg3_napi *tnapi = &tp->napi[i];
6213
6214 if (tnapi->tx_ring) {
6215 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6216 tnapi->tx_ring, tnapi->tx_desc_mapping);
6217 tnapi->tx_ring = NULL;
6218 }
6219
6220 kfree(tnapi->tx_buffers);
6221 tnapi->tx_buffers = NULL;
6222
6223 if (tnapi->rx_rcb) {
6224 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6225 tnapi->rx_rcb,
6226 tnapi->rx_rcb_mapping);
6227 tnapi->rx_rcb = NULL;
6228 }
6229
6230 if (tnapi->hw_status) {
6231 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6232 tnapi->hw_status,
6233 tnapi->status_mapping);
6234 tnapi->hw_status = NULL;
6235 }
1da177e4 6236 }
f77a6a8e 6237
1da177e4
LT		 6238 if (tp->hw_stats) {
6239 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6240 tp->hw_stats, tp->stats_mapping);
6241 tp->hw_stats = NULL;
6242 }
f77a6a8e 6243
2b2cdb65
MC		 6244 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6245 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6246}
6247
6248/*
6249 * Must not be invoked with interrupt sources disabled and
6250 * the hardware shutdown down. Can sleep.
6251 */
6252static int tg3_alloc_consistent(struct tg3 *tp)
6253{
f77a6a8e 6254 int i;
898a56f8 6255
2b2cdb65
MC		 6256 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6257 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6258 goto err_out;
6259 }
1da177e4 6260
f77a6a8e
MC		 6261 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6262 sizeof(struct tg3_hw_stats),
6263 &tp->stats_mapping);
6264 if (!tp->hw_stats)
1da177e4
LT		 6265 goto err_out;
6266
f77a6a8e 6267 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6268
f77a6a8e
MC		 6269 for (i = 0; i < tp->irq_cnt; i++) {
6270 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6271 struct tg3_hw_status *sblk;
1da177e4 6272
f77a6a8e
MC		 6273 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6274 TG3_HW_STATUS_SIZE,
6275 &tnapi->status_mapping);
6276 if (!tnapi->hw_status)
6277 goto err_out;
898a56f8 6278
f77a6a8e 6279 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6280 sblk = tnapi->hw_status;
6281
6282 /*
6283 * When RSS is enabled, the status block format changes
6284 * slightly. The "rx_jumbo_consumer", "reserved",
6285 * and "rx_mini_consumer" members get mapped to the
6286 * other three rx return ring producer indexes.
6287 */
6288 switch (i) {
6289 default:
6290 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6291 break;
6292 case 2:
6293 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6294 break;
6295 case 3:
6296 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6297 break;
6298 case 4:
6299 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6300 break;
6301 }
72334482 6302
b196c7e4
MC		 6303 if (tp->irq_cnt == 1)
6304 tnapi->prodring = &tp->prodring[0];
6305 else if (i)
6306 tnapi->prodring = &tp->prodring[i - 1];
6307
0c1d0e2b
MC		 6308 /*
6309 * If multivector RSS is enabled, vector 0 does not handle
6310 * rx or tx interrupts. Don't allocate any resources for it.
6311 */
6312 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6313 continue;
6314
f77a6a8e
MC		 6315 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6316 TG3_RX_RCB_RING_BYTES(tp),
6317 &tnapi->rx_rcb_mapping);
6318 if (!tnapi->rx_rcb)
6319 goto err_out;
72334482 6320
f77a6a8e 6321 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 6322
f4188d8a 6323 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
f77a6a8e
MC		 6324 TG3_TX_RING_SIZE, GFP_KERNEL);
6325 if (!tnapi->tx_buffers)
6326 goto err_out;
6327
6328 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6329 TG3_TX_RING_BYTES,
6330 &tnapi->tx_desc_mapping);
6331 if (!tnapi->tx_ring)
6332 goto err_out;
6333 }
1da177e4
LT		 6334
6335 return 0;
6336
6337err_out:
6338 tg3_free_consistent(tp);
6339 return -ENOMEM;
6340}
6341
6342#define MAX_WAIT_CNT 1000
6343
6344/* To stop a block, clear the enable bit and poll till it
6345 * clears. tp->lock is held.
6346 */
b3b7d6be 6347static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6348{
6349 unsigned int i;
6350 u32 val;
6351
6352 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6353 switch (ofs) {
6354 case RCVLSC_MODE:
6355 case DMAC_MODE:
6356 case MBFREE_MODE:
6357 case BUFMGR_MODE:
6358 case MEMARB_MODE:
6359 /* We can't enable/disable these bits of the
6360 * 5705/5750, just say success.
6361 */
6362 return 0;
6363
6364 default:
6365 break;
855e1111 6366 }
1da177e4
LT		 6367 }
6368
6369 val = tr32(ofs);
6370 val &= ~enable_bit;
6371 tw32_f(ofs, val);
6372
6373 for (i = 0; i < MAX_WAIT_CNT; i++) {
6374 udelay(100);
6375 val = tr32(ofs);
6376 if ((val & enable_bit) == 0)
6377 break;
6378 }
6379
b3b7d6be 6380 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6381 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6382 "ofs=%lx enable_bit=%x\n",
6383 ofs, enable_bit);
6384 return -ENODEV;
6385 }
6386
6387 return 0;
6388}
6389
6390/* tp->lock is held. */
b3b7d6be 6391static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6392{
6393 int i, err;
6394
6395 tg3_disable_ints(tp);
6396
6397 tp->rx_mode &= ~RX_MODE_ENABLE;
6398 tw32_f(MAC_RX_MODE, tp->rx_mode);
6399 udelay(10);
6400
b3b7d6be
DM		 6401 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6402 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6403 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6404 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6405 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6406 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6407
6408 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6409 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6410 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6411 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6412 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6413 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6414 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6415
6416 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6417 tw32_f(MAC_MODE, tp->mac_mode);
6418 udelay(40);
6419
6420 tp->tx_mode &= ~TX_MODE_ENABLE;
6421 tw32_f(MAC_TX_MODE, tp->tx_mode);
6422
6423 for (i = 0; i < MAX_WAIT_CNT; i++) {
6424 udelay(100);
6425 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6426 break;
6427 }
6428 if (i >= MAX_WAIT_CNT) {
6429 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6430 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6431 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6432 err |= -ENODEV;
1da177e4
LT		 6433 }
6434
e6de8ad1 6435 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6436 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6437 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6438
6439 tw32(FTQ_RESET, 0xffffffff);
6440 tw32(FTQ_RESET, 0x00000000);
6441
b3b7d6be
DM		 6442 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6443 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6444
f77a6a8e
MC		 6445 for (i = 0; i < tp->irq_cnt; i++) {
6446 struct tg3_napi *tnapi = &tp->napi[i];
6447 if (tnapi->hw_status)
6448 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6449 }
1da177e4
LT		 6450 if (tp->hw_stats)
6451 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6452
1da177e4
LT		 6453 return err;
6454}
6455
0d3031d9
MC		 6456static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6457{
6458 int i;
6459 u32 apedata;
6460
6461 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6462 if (apedata != APE_SEG_SIG_MAGIC)
6463 return;
6464
6465 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6466 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6467 return;
6468
6469 /* Wait for up to 1 millisecond for APE to service previous event. */
6470 for (i = 0; i < 10; i++) {
6471 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6472 return;
6473
6474 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6475
6476 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6477 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6478 event | APE_EVENT_STATUS_EVENT_PENDING);
6479
6480 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6481
6482 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6483 break;
6484
6485 udelay(100);
6486 }
6487
6488 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6489 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6490}
6491
6492static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6493{
6494 u32 event;
6495 u32 apedata;
6496
6497 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6498 return;
6499
6500 switch (kind) {
6501 case RESET_KIND_INIT:
6502 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6503 APE_HOST_SEG_SIG_MAGIC);
6504 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6505 APE_HOST_SEG_LEN_MAGIC);
6506 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6507 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6508 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6509 APE_HOST_DRIVER_ID_MAGIC);
6510 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6511 APE_HOST_BEHAV_NO_PHYLOCK);
6512
6513 event = APE_EVENT_STATUS_STATE_START;
6514 break;
6515 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6516 /* With the interface we are currently using,
6517 * APE does not track driver state. Wiping
6518 * out the HOST SEGMENT SIGNATURE forces
6519 * the APE to assume OS absent status.
6520 */
6521 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6522
0d3031d9
MC		 6523 event = APE_EVENT_STATUS_STATE_UNLOAD;
6524 break;
6525 case RESET_KIND_SUSPEND:
6526 event = APE_EVENT_STATUS_STATE_SUSPEND;
6527 break;
6528 default:
6529 return;
6530 }
6531
6532 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6533
6534 tg3_ape_send_event(tp, event);
6535}
6536
1da177e4
LT		 6537/* tp->lock is held. */
6538static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6539{
f49639e6
DM		 6540 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6541 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6542
6543 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6544 switch (kind) {
6545 case RESET_KIND_INIT:
6546 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6547 DRV_STATE_START);
6548 break;
6549
6550 case RESET_KIND_SHUTDOWN:
6551 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6552 DRV_STATE_UNLOAD);
6553 break;
6554
6555 case RESET_KIND_SUSPEND:
6556 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6557 DRV_STATE_SUSPEND);
6558 break;
6559
6560 default:
6561 break;
855e1111 6562 }
1da177e4 6563 }
0d3031d9
MC		 6564
6565 if (kind == RESET_KIND_INIT ||
6566 kind == RESET_KIND_SUSPEND)
6567 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6568}
6569
6570/* tp->lock is held. */
6571static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6572{
6573 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6574 switch (kind) {
6575 case RESET_KIND_INIT:
6576 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6577 DRV_STATE_START_DONE);
6578 break;
6579
6580 case RESET_KIND_SHUTDOWN:
6581 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6582 DRV_STATE_UNLOAD_DONE);
6583 break;
6584
6585 default:
6586 break;
855e1111 6587 }
1da177e4 6588 }
0d3031d9
MC		 6589
6590 if (kind == RESET_KIND_SHUTDOWN)
6591 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6592}
6593
6594/* tp->lock is held. */
6595static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6596{
6597 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6598 switch (kind) {
6599 case RESET_KIND_INIT:
6600 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6601 DRV_STATE_START);
6602 break;
6603
6604 case RESET_KIND_SHUTDOWN:
6605 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6606 DRV_STATE_UNLOAD);
6607 break;
6608
6609 case RESET_KIND_SUSPEND:
6610 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6611 DRV_STATE_SUSPEND);
6612 break;
6613
6614 default:
6615 break;
855e1111 6616 }
1da177e4
LT		 6617 }
6618}
6619
7a6f4369
MC		 6620static int tg3_poll_fw(struct tg3 *tp)
6621{
6622 int i;
6623 u32 val;
6624
b5d3772c 6625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6626 /* Wait up to 20ms for init done. */
6627 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6628 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6629 return 0;
0ccead18 6630 udelay(100);
b5d3772c
MC		 6631 }
6632 return -ENODEV;
6633 }
6634
7a6f4369
MC		 6635 /* Wait for firmware initialization to complete. */
6636 for (i = 0; i < 100000; i++) {
6637 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6638 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6639 break;
6640 udelay(10);
6641 }
6642
6643 /* Chip might not be fitted with firmware. Some Sun onboard
6644 * parts are configured like that. So don't signal the timeout
6645 * of the above loop as an error, but do report the lack of
6646 * running firmware once.
6647 */
6648 if (i >= 100000 &&
6649 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6650 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6651
6652 printk(KERN_INFO PFX "%s: No firmware running.\n",
6653 tp->dev->name);
6654 }
6655
6656 return 0;
6657}
6658
ee6a99b5
MC		 6659/* Save PCI command register before chip reset */
6660static void tg3_save_pci_state(struct tg3 *tp)
6661{
8a6eac90 6662 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6663}
6664
6665/* Restore PCI state after chip reset */
6666static void tg3_restore_pci_state(struct tg3 *tp)
6667{
6668 u32 val;
6669
6670 /* Re-enable indirect register accesses. */
6671 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6672 tp->misc_host_ctrl);
6673
6674 /* Set MAX PCI retry to zero. */
6675 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6676 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6677 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6678 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6679 /* Allow reads and writes to the APE register and memory space. */
6680 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6681 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6682 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6683 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6684
8a6eac90 6685 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6686
fcb389df
MC		 6687 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6688 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6689 pcie_set_readrq(tp->pdev, 4096);
6690 else {
6691 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6692 tp->pci_cacheline_sz);
6693 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6694 tp->pci_lat_timer);
6695 }
114342f2 6696 }
5f5c51e3 6697
ee6a99b5 6698 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6699 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6700 u16 pcix_cmd;
6701
6702 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6703 &pcix_cmd);
6704 pcix_cmd &= ~PCI_X_CMD_ERO;
6705 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6706 pcix_cmd);
6707 }
ee6a99b5
MC		 6708
6709 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6710
6711 /* Chip reset on 5780 will reset MSI enable bit,
6712 * so need to restore it.
6713 */
6714 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6715 u16 ctrl;
6716
6717 pci_read_config_word(tp->pdev,
6718 tp->msi_cap + PCI_MSI_FLAGS,
6719 &ctrl);
6720 pci_write_config_word(tp->pdev,
6721 tp->msi_cap + PCI_MSI_FLAGS,
6722 ctrl | PCI_MSI_FLAGS_ENABLE);
6723 val = tr32(MSGINT_MODE);
6724 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6725 }
6726 }
6727}
6728
1da177e4
LT		 6729static void tg3_stop_fw(struct tg3 *);
6730
6731/* tp->lock is held. */
6732static int tg3_chip_reset(struct tg3 *tp)
6733{
6734 u32 val;
1ee582d8 6735 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6736 int i, err;
1da177e4 6737
f49639e6
DM		 6738 tg3_nvram_lock(tp);
6739
77b483f1
MC		 6740 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6741
f49639e6
DM		 6742 /* No matching tg3_nvram_unlock() after this because
6743 * chip reset below will undo the nvram lock.
6744 */
6745 tp->nvram_lock_cnt = 0;
1da177e4 6746
ee6a99b5
MC		 6747 /* GRC_MISC_CFG core clock reset will clear the memory
6748 * enable bit in PCI register 4 and the MSI enable bit
6749 * on some chips, so we save relevant registers here.
6750 */
6751 tg3_save_pci_state(tp);
6752
d9ab5ad1 6753 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6754 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6755 tw32(GRC_FASTBOOT_PC, 0);
6756
1da177e4
LT		 6757 /*
6758 * We must avoid the readl() that normally takes place.
6759 * It locks machines, causes machine checks, and other
6760 * fun things. So, temporarily disable the 5701
6761 * hardware workaround, while we do the reset.
6762 */
1ee582d8
MC		 6763 write_op = tp->write32;
6764 if (write_op == tg3_write_flush_reg32)
6765 tp->write32 = tg3_write32;
1da177e4 6766
d18edcb2
MC		 6767 /* Prevent the irq handler from reading or writing PCI registers
6768 * during chip reset when the memory enable bit in the PCI command
6769 * register may be cleared. The chip does not generate interrupt
6770 * at this time, but the irq handler may still be called due to irq
6771 * sharing or irqpoll.
6772 */
6773 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6774 for (i = 0; i < tp->irq_cnt; i++) {
6775 struct tg3_napi *tnapi = &tp->napi[i];
6776 if (tnapi->hw_status) {
6777 tnapi->hw_status->status = 0;
6778 tnapi->hw_status->status_tag = 0;
6779 }
6780 tnapi->last_tag = 0;
6781 tnapi->last_irq_tag = 0;
b8fa2f3a 6782 }
d18edcb2 6783 smp_mb();
4f125f42
MC		 6784
6785 for (i = 0; i < tp->irq_cnt; i++)
6786 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6787
255ca311
MC		 6788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6789 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6790 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6791 }
6792
1da177e4
LT		 6793 /* do the reset */
6794 val = GRC_MISC_CFG_CORECLK_RESET;
6795
6796 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6797 if (tr32(0x7e2c) == 0x60) {
6798 tw32(0x7e2c, 0x20);
6799 }
6800 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6801 tw32(GRC_MISC_CFG, (1 << 29));
6802 val |= (1 << 29);
6803 }
6804 }
6805
b5d3772c
MC		 6806 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6807 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6808 tw32(GRC_VCPU_EXT_CTRL,
6809 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6810 }
6811
1da177e4
LT		 6812 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6813 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6814 tw32(GRC_MISC_CFG, val);
6815
1ee582d8
MC		 6816 /* restore 5701 hardware bug workaround write method */
6817 tp->write32 = write_op;
1da177e4
LT		 6818
6819 /* Unfortunately, we have to delay before the PCI read back.
6820 * Some 575X chips even will not respond to a PCI cfg access
6821 * when the reset command is given to the chip.
6822 *
6823 * How do these hardware designers expect things to work
6824 * properly if the PCI write is posted for a long period
6825 * of time? It is always necessary to have some method by
6826 * which a register read back can occur to push the write
6827 * out which does the reset.
6828 *
6829 * For most tg3 variants the trick below was working.
6830 * Ho hum...
6831 */
6832 udelay(120);
6833
6834 /* Flush PCI posted writes. The normal MMIO registers
6835 * are inaccessible at this time so this is the only
6836 * way to make this reliably (actually, this is no longer
6837 * the case, see above). I tried to use indirect
6838 * register read/write but this upset some 5701 variants.
6839 */
6840 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6841
6842 udelay(120);
6843
5e7dfd0f 6844 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6845 u16 val16;
6846
1da177e4
LT		 6847 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6848 int i;
6849 u32 cfg_val;
6850
6851 /* Wait for link training to complete. */
6852 for (i = 0; i < 5000; i++)
6853 udelay(100);
6854
6855 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6856 pci_write_config_dword(tp->pdev, 0xc4,
6857 cfg_val | (1 << 15));
6858 }
5e7dfd0f 6859
e7126997
MC		 6860 /* Clear the "no snoop" and "relaxed ordering" bits. */
6861 pci_read_config_word(tp->pdev,
6862 tp->pcie_cap + PCI_EXP_DEVCTL,
6863 &val16);
6864 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6865 PCI_EXP_DEVCTL_NOSNOOP_EN);
6866 /*
6867 * Older PCIe devices only support the 128 byte
6868 * MPS setting. Enforce the restriction.
5e7dfd0f 6869 */
e7126997
MC		 6870 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6871 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6872 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6873 pci_write_config_word(tp->pdev,
6874 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6875 val16);
5e7dfd0f
MC		 6876
6877 pcie_set_readrq(tp->pdev, 4096);
6878
6879 /* Clear error status */
6880 pci_write_config_word(tp->pdev,
6881 tp->pcie_cap + PCI_EXP_DEVSTA,
6882 PCI_EXP_DEVSTA_CED |
6883 PCI_EXP_DEVSTA_NFED |
6884 PCI_EXP_DEVSTA_FED |
6885 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6886 }
6887
ee6a99b5 6888 tg3_restore_pci_state(tp);
1da177e4 6889
d18edcb2
MC		 6890 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6891
ee6a99b5
MC		 6892 val = 0;
6893 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6894 val = tr32(MEMARB_MODE);
ee6a99b5 6895 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6896
6897 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6898 tg3_stop_fw(tp);
6899 tw32(0x5000, 0x400);
6900 }
6901
6902 tw32(GRC_MODE, tp->grc_mode);
6903
6904 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6905 val = tr32(0xc4);
1da177e4
LT		 6906
6907 tw32(0xc4, val | (1 << 15));
6908 }
6909
6910 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6911 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6912 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6913 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6914 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6915 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6916 }
6917
6918 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6919 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6920 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6921 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6922 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6923 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6924 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6925 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6926 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6927 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6928 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6929 } else
6930 tw32_f(MAC_MODE, 0);
6931 udelay(40);
6932
77b483f1
MC		 6933 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6934
7a6f4369
MC		 6935 err = tg3_poll_fw(tp);
6936 if (err)
6937 return err;
1da177e4 6938
0a9140cf
MC		 6939 tg3_mdio_start(tp);
6940
52cdf852
MC		 6941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6942 u8 phy_addr;
6943
6944 phy_addr = tp->phy_addr;
6945 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6946
6947 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6948 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6949 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6950 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6951 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6952 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6953 udelay(10);
6954
6955 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6956 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6957 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6958 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6959 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6960 udelay(10);
6961
6962 tp->phy_addr = phy_addr;
6963 }
6964
1da177e4 6965 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6966 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6967 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6968 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6969 val = tr32(0x7c00);
1da177e4
LT		 6970
6971 tw32(0x7c00, val | (1 << 25));
6972 }
6973
6974 /* Reprobe ASF enable state. */
6975 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6976 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6977 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6978 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6979 u32 nic_cfg;
6980
6981 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6982 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6983 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6984 tp->last_event_jiffies = jiffies;
cbf46853 6985 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6986 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6987 }
6988 }
6989
6990 return 0;
6991}
6992
6993/* tp->lock is held. */
6994static void tg3_stop_fw(struct tg3 *tp)
6995{
0d3031d9
MC		 6996 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6997 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6998 /* Wait for RX cpu to ACK the previous event. */
6999 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7000
7001 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 7002
7003 tg3_generate_fw_event(tp);
1da177e4 7004
7c5026aa
MC		 7005 /* Wait for RX cpu to ACK this event. */
7006 tg3_wait_for_event_ack(tp);
1da177e4
LT		 7007 }
7008}
7009
7010/* tp->lock is held. */
944d980e 7011static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 7012{
7013 int err;
7014
7015 tg3_stop_fw(tp);
7016
944d980e 7017 tg3_write_sig_pre_reset(tp, kind);
1da177e4 7018
b3b7d6be 7019 tg3_abort_hw(tp, silent);
1da177e4
LT		 7020 err = tg3_chip_reset(tp);
7021
daba2a63
MC		 7022 __tg3_set_mac_addr(tp, 0);
7023
944d980e
MC		 7024 tg3_write_sig_legacy(tp, kind);
7025 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 7026
7027 if (err)
7028 return err;
7029
7030 return 0;
7031}
7032
1da177e4
LT		 7033#define RX_CPU_SCRATCH_BASE 0x30000
7034#define RX_CPU_SCRATCH_SIZE 0x04000
7035#define TX_CPU_SCRATCH_BASE 0x34000
7036#define TX_CPU_SCRATCH_SIZE 0x04000
7037
7038/* tp->lock is held. */
7039static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7040{
7041 int i;
7042
5d9428de
ES		 7043 BUG_ON(offset == TX_CPU_BASE &&
7044 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 7045
b5d3772c
MC		 7046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7047 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7048
7049 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7050 return 0;
7051 }
1da177e4
LT		 7052 if (offset == RX_CPU_BASE) {
7053 for (i = 0; i < 10000; i++) {
7054 tw32(offset + CPU_STATE, 0xffffffff);
7055 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7056 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7057 break;
7058 }
7059
7060 tw32(offset + CPU_STATE, 0xffffffff);
7061 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7062 udelay(10);
7063 } else {
7064 for (i = 0; i < 10000; i++) {
7065 tw32(offset + CPU_STATE, 0xffffffff);
7066 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7067 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7068 break;
7069 }
7070 }
7071
7072 if (i >= 10000) {
7073 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7074 "and %s CPU\n",
7075 tp->dev->name,
7076 (offset == RX_CPU_BASE ? "RX" : "TX"));
7077 return -ENODEV;
7078 }
ec41c7df
MC		 7079
7080 /* Clear firmware's nvram arbitration. */
7081 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7082 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 7083 return 0;
7084}
7085
7086struct fw_info {
077f849d
JSR		 7087 unsigned int fw_base;
7088 unsigned int fw_len;
7089 const __be32 *fw_data;
1da177e4
LT		 7090};
7091
7092/* tp->lock is held. */
7093static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7094 int cpu_scratch_size, struct fw_info *info)
7095{
ec41c7df 7096 int err, lock_err, i;
1da177e4
LT		 7097 void (*write_op)(struct tg3 *, u32, u32);
7098
7099 if (cpu_base == TX_CPU_BASE &&
7100 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7101 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7102 "TX cpu firmware on %s which is 5705.\n",
7103 tp->dev->name);
7104 return -EINVAL;
7105 }
7106
7107 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7108 write_op = tg3_write_mem;
7109 else
7110 write_op = tg3_write_indirect_reg32;
7111
1b628151
MC		 7112 /* It is possible that bootcode is still loading at this point.
7113 * Get the nvram lock first before halting the cpu.
7114 */
ec41c7df 7115 lock_err = tg3_nvram_lock(tp);
1da177e4 7116 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 7117 if (!lock_err)
7118 tg3_nvram_unlock(tp);
1da177e4
LT		 7119 if (err)
7120 goto out;
7121
7122 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7123 write_op(tp, cpu_scratch_base + i, 0);
7124 tw32(cpu_base + CPU_STATE, 0xffffffff);
7125 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 7126 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 7127 write_op(tp, (cpu_scratch_base +
077f849d 7128 (info->fw_base & 0xffff) +
1da177e4 7129 (i * sizeof(u32))),
077f849d 7130 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 7131
7132 err = 0;
7133
7134out:
1da177e4
LT		 7135 return err;
7136}
7137
7138/* tp->lock is held. */
7139static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7140{
7141 struct fw_info info;
077f849d 7142 const __be32 *fw_data;
1da177e4
LT		 7143 int err, i;
7144
077f849d
JSR		 7145 fw_data = (void *)tp->fw->data;
7146
7147 /* Firmware blob starts with version numbers, followed by
7148 start address and length. We are setting complete length.
7149 length = end_address_of_bss - start_address_of_text.
7150 Remainder is the blob to be loaded contiguously
7151 from start address. */
7152
7153 info.fw_base = be32_to_cpu(fw_data[1]);
7154 info.fw_len = tp->fw->size - 12;
7155 info.fw_data = &fw_data[3];
1da177e4
LT		 7156
7157 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7158 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7159 &info);
7160 if (err)
7161 return err;
7162
7163 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7164 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7165 &info);
7166 if (err)
7167 return err;
7168
7169 /* Now startup only the RX cpu. */
7170 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 7171 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7172
7173 for (i = 0; i < 5; i++) {
077f849d 7174 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 7175 break;
7176 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7177 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 7178 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 7179 udelay(1000);
7180 }
7181 if (i >= 5) {
7182 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7183 "to set RX CPU PC, is %08x should be %08x\n",
7184 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 7185 info.fw_base);
1da177e4
LT		 7186 return -ENODEV;
7187 }
7188 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7189 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7190
7191 return 0;
7192}
7193
1da177e4 7194/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 7195
7196/* tp->lock is held. */
7197static int tg3_load_tso_firmware(struct tg3 *tp)
7198{
7199 struct fw_info info;
077f849d 7200 const __be32 *fw_data;
1da177e4
LT		 7201 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7202 int err, i;
7203
7204 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7205 return 0;
7206
077f849d
JSR		 7207 fw_data = (void *)tp->fw->data;
7208
7209 /* Firmware blob starts with version numbers, followed by
7210 start address and length. We are setting complete length.
7211 length = end_address_of_bss - start_address_of_text.
7212 Remainder is the blob to be loaded contiguously
7213 from start address. */
7214
7215 info.fw_base = be32_to_cpu(fw_data[1]);
7216 cpu_scratch_size = tp->fw_len;
7217 info.fw_len = tp->fw->size - 12;
7218 info.fw_data = &fw_data[3];
7219
1da177e4 7220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7221 cpu_base = RX_CPU_BASE;
7222 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 7223 } else {
1da177e4
LT		 7224 cpu_base = TX_CPU_BASE;
7225 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7226 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7227 }
7228
7229 err = tg3_load_firmware_cpu(tp, cpu_base,
7230 cpu_scratch_base, cpu_scratch_size,
7231 &info);
7232 if (err)
7233 return err;
7234
7235 /* Now startup the cpu. */
7236 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 7237 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7238
7239 for (i = 0; i < 5; i++) {
077f849d 7240 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7241 break;
7242 tw32(cpu_base + CPU_STATE, 0xffffffff);
7243 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7244 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7245 udelay(1000);
7246 }
7247 if (i >= 5) {
7248 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7249 "to set CPU PC, is %08x should be %08x\n",
7250 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7251 info.fw_base);
1da177e4
LT		 7252 return -ENODEV;
7253 }
7254 tw32(cpu_base + CPU_STATE, 0xffffffff);
7255 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7256 return 0;
7257}
7258
1da177e4 7259
1da177e4
LT		 7260static int tg3_set_mac_addr(struct net_device *dev, void *p)
7261{
7262 struct tg3 *tp = netdev_priv(dev);
7263 struct sockaddr *addr = p;
986e0aeb 7264 int err = 0, skip_mac_1 = 0;
1da177e4 7265
f9804ddb
MC		 7266 if (!is_valid_ether_addr(addr->sa_data))
7267 return -EINVAL;
7268
1da177e4
LT		 7269 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7270
e75f7c90
MC		 7271 if (!netif_running(dev))
7272 return 0;
7273
58712ef9 7274 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7275 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7276
986e0aeb
MC		 7277 addr0_high = tr32(MAC_ADDR_0_HIGH);
7278 addr0_low = tr32(MAC_ADDR_0_LOW);
7279 addr1_high = tr32(MAC_ADDR_1_HIGH);
7280 addr1_low = tr32(MAC_ADDR_1_LOW);
7281
7282 /* Skip MAC addr 1 if ASF is using it. */
7283 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7284 !(addr1_high == 0 && addr1_low == 0))
7285 skip_mac_1 = 1;
58712ef9 7286 }
986e0aeb
MC		 7287 spin_lock_bh(&tp->lock);
7288 __tg3_set_mac_addr(tp, skip_mac_1);
7289 spin_unlock_bh(&tp->lock);
1da177e4 7290
b9ec6c1b 7291 return err;
1da177e4
LT		 7292}
7293
7294/* tp->lock is held. */
7295static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7296 dma_addr_t mapping, u32 maxlen_flags,
7297 u32 nic_addr)
7298{
7299 tg3_write_mem(tp,
7300 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7301 ((u64) mapping >> 32));
7302 tg3_write_mem(tp,
7303 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7304 ((u64) mapping & 0xffffffff));
7305 tg3_write_mem(tp,
7306 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7307 maxlen_flags);
7308
7309 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7310 tg3_write_mem(tp,
7311 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7312 nic_addr);
7313}
7314
7315static void __tg3_set_rx_mode(struct net_device *);
d244c892 7316static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7317{
b6080e12
MC		 7318 int i;
7319
7320 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7321 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7322 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7323 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7324
7325 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7326 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7327 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7328 } else {
7329 tw32(HOSTCC_TXCOL_TICKS, 0);
7330 tw32(HOSTCC_TXMAX_FRAMES, 0);
7331 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7332
7333 tw32(HOSTCC_RXCOL_TICKS, 0);
7334 tw32(HOSTCC_RXMAX_FRAMES, 0);
7335 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7336 }
b6080e12 7337
15f9850d
DM		 7338 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7339 u32 val = ec->stats_block_coalesce_usecs;
7340
b6080e12
MC		 7341 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7342 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7343
15f9850d
DM		 7344 if (!netif_carrier_ok(tp->dev))
7345 val = 0;
7346
7347 tw32(HOSTCC_STAT_COAL_TICKS, val);
7348 }
b6080e12
MC		 7349
7350 for (i = 0; i < tp->irq_cnt - 1; i++) {
7351 u32 reg;
7352
7353 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7354 tw32(reg, ec->rx_coalesce_usecs);
7355 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7356 tw32(reg, ec->tx_coalesce_usecs);
7357 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7358 tw32(reg, ec->rx_max_coalesced_frames);
7359 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7360 tw32(reg, ec->tx_max_coalesced_frames);
7361 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7362 tw32(reg, ec->rx_max_coalesced_frames_irq);
7363 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7364 tw32(reg, ec->tx_max_coalesced_frames_irq);
7365 }
7366
7367 for (; i < tp->irq_max - 1; i++) {
7368 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7369 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7370 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7371 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7372 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7373 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7374 }
15f9850d 7375}
1da177e4 7376
2d31ecaf
MC		 7377/* tp->lock is held. */
7378static void tg3_rings_reset(struct tg3 *tp)
7379{
7380 int i;
f77a6a8e 7381 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7382 struct tg3_napi *tnapi = &tp->napi[0];
7383
7384 /* Disable all transmit rings but the first. */
7385 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7386 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7387 else
7388 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7389
7390 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7391 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7392 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7393 BDINFO_FLAGS_DISABLED);
7394
7395
7396 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7398 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7399 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7400 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7401 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7402 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7403 else
7404 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7405
7406 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7407 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7408 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7409 BDINFO_FLAGS_DISABLED);
7410
7411 /* Disable interrupts */
7412 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7413
7414 /* Zero mailbox registers. */
f77a6a8e
MC		 7415 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7416 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7417 tp->napi[i].tx_prod = 0;
7418 tp->napi[i].tx_cons = 0;
7419 tw32_mailbox(tp->napi[i].prodmbox, 0);
7420 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7421 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7422 }
7423 } else {
7424 tp->napi[0].tx_prod = 0;
7425 tp->napi[0].tx_cons = 0;
7426 tw32_mailbox(tp->napi[0].prodmbox, 0);
7427 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7428 }
2d31ecaf
MC		 7429
7430 /* Make sure the NIC-based send BD rings are disabled. */
7431 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7432 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7433 for (i = 0; i < 16; i++)
7434 tw32_tx_mbox(mbox + i * 8, 0);
7435 }
7436
7437 txrcb = NIC_SRAM_SEND_RCB;
7438 rxrcb = NIC_SRAM_RCV_RET_RCB;
7439
7440 /* Clear status block in ram. */
7441 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7442
7443 /* Set status block DMA address */
7444 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7445 ((u64) tnapi->status_mapping >> 32));
7446 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7447 ((u64) tnapi->status_mapping & 0xffffffff));
7448
f77a6a8e
MC		 7449 if (tnapi->tx_ring) {
7450 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7451 (TG3_TX_RING_SIZE <<
7452 BDINFO_FLAGS_MAXLEN_SHIFT),
7453 NIC_SRAM_TX_BUFFER_DESC);
7454 txrcb += TG3_BDINFO_SIZE;
7455 }
7456
7457 if (tnapi->rx_rcb) {
7458 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7459 (TG3_RX_RCB_RING_SIZE(tp) <<
7460 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7461 rxrcb += TG3_BDINFO_SIZE;
7462 }
7463
7464 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7465
f77a6a8e
MC		 7466 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7467 u64 mapping = (u64)tnapi->status_mapping;
7468 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7469 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7470
7471 /* Clear status block in ram. */
7472 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7473
7474 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7475 (TG3_TX_RING_SIZE <<
7476 BDINFO_FLAGS_MAXLEN_SHIFT),
7477 NIC_SRAM_TX_BUFFER_DESC);
7478
7479 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7480 (TG3_RX_RCB_RING_SIZE(tp) <<
7481 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7482
7483 stblk += 8;
7484 txrcb += TG3_BDINFO_SIZE;
7485 rxrcb += TG3_BDINFO_SIZE;
7486 }
2d31ecaf
MC		 7487}
7488
1da177e4 7489/* tp->lock is held. */
8e7a22e3 7490static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7491{
7492 u32 val, rdmac_mode;
7493 int i, err, limit;
21f581a5 7494 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7495
7496 tg3_disable_ints(tp);
7497
7498 tg3_stop_fw(tp);
7499
7500 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7501
7502 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7503 tg3_abort_hw(tp, 1);
1da177e4
LT		 7504 }
7505
dd477003
MC		 7506 if (reset_phy &&
7507 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7508 tg3_phy_reset(tp);
7509
1da177e4
LT		 7510 err = tg3_chip_reset(tp);
7511 if (err)
7512 return err;
7513
7514 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7515
bcb37f6c 7516 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7517 val = tr32(TG3_CPMU_CTRL);
7518 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7519 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7520
7521 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7522 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7523 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7524 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7525
7526 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7527 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7528 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7529 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7530
7531 val = tr32(TG3_CPMU_HST_ACC);
7532 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7533 val |= CPMU_HST_ACC_MACCLK_6_25;
7534 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7535 }
7536
33466d93
MC		 7537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7538 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7539 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7540 PCIE_PWR_MGMT_L1_THRESH_4MS;
7541 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7542
7543 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7544 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7545
7546 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7547
f40386c8
MC		 7548 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7549 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7550 }
7551
1da177e4
LT		 7552 /* This works around an issue with Athlon chipsets on
7553 * B3 tigon3 silicon. This bit has no effect on any
7554 * other revision. But do not set this on PCI Express
795d01c5 7555 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7556 */
795d01c5
MC		 7557 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7558 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7559 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7560 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7561 }
1da177e4
LT		 7562
7563 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7564 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7565 val = tr32(TG3PCI_PCISTATE);
7566 val |= PCISTATE_RETRY_SAME_DMA;
7567 tw32(TG3PCI_PCISTATE, val);
7568 }
7569
0d3031d9
MC		 7570 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7571 /* Allow reads and writes to the
7572 * APE register and memory space.
7573 */
7574 val = tr32(TG3PCI_PCISTATE);
7575 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7576 PCISTATE_ALLOW_APE_SHMEM_WR;
7577 tw32(TG3PCI_PCISTATE, val);
7578 }
7579
1da177e4
LT		 7580 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7581 /* Enable some hw fixes. */
7582 val = tr32(TG3PCI_MSI_DATA);
7583 val |= (1 << 26) | (1 << 28) | (1 << 29);
7584 tw32(TG3PCI_MSI_DATA, val);
7585 }
7586
7587 /* Descriptor ring init may make accesses to the
7588 * NIC SRAM area to setup the TX descriptors, so we
7589 * can only do this after the hardware has been
7590 * successfully reset.
7591 */
32d8c572
MC		 7592 err = tg3_init_rings(tp);
7593 if (err)
7594 return err;
1da177e4 7595
cbf9ca6c
MC		 7596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7597 val = tr32(TG3PCI_DMA_RW_CTRL) &
7598 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7599 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7600 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7601 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7602 /* This value is determined during the probe time DMA
7603 * engine test, tg3_test_dma.
7604 */
7605 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7606 }
1da177e4
LT		 7607
7608 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7609 GRC_MODE_4X_NIC_SEND_RINGS |
7610 GRC_MODE_NO_TX_PHDR_CSUM |
7611 GRC_MODE_NO_RX_PHDR_CSUM);
7612 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7613
7614 /* Pseudo-header checksum is done by hardware logic and not
7615 * the offload processers, so make the chip do the pseudo-
7616 * header checksums on receive. For transmit it is more
7617 * convenient to do the pseudo-header checksum in software
7618 * as Linux does that on transmit for us in all cases.
7619 */
7620 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7621
7622 tw32(GRC_MODE,
7623 tp->grc_mode |
7624 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7625
7626 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7627 val = tr32(GRC_MISC_CFG);
7628 val &= ~0xff;
7629 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7630 tw32(GRC_MISC_CFG, val);
7631
7632 /* Initialize MBUF/DESC pool. */
cbf46853 7633 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7634 /* Do nothing. */
7635 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7636 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7638 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7639 else
7640 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7641 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7642 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7643 }
1da177e4
LT		 7644 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7645 int fw_len;
7646
077f849d 7647 fw_len = tp->fw_len;
1da177e4
LT		 7648 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7649 tw32(BUFMGR_MB_POOL_ADDR,
7650 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7651 tw32(BUFMGR_MB_POOL_SIZE,
7652 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7653 }
1da177e4 7654
0f893dc6 7655 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7656 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7657 tp->bufmgr_config.mbuf_read_dma_low_water);
7658 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7659 tp->bufmgr_config.mbuf_mac_rx_low_water);
7660 tw32(BUFMGR_MB_HIGH_WATER,
7661 tp->bufmgr_config.mbuf_high_water);
7662 } else {
7663 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7664 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7665 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7666 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7667 tw32(BUFMGR_MB_HIGH_WATER,
7668 tp->bufmgr_config.mbuf_high_water_jumbo);
7669 }
7670 tw32(BUFMGR_DMA_LOW_WATER,
7671 tp->bufmgr_config.dma_low_water);
7672 tw32(BUFMGR_DMA_HIGH_WATER,
7673 tp->bufmgr_config.dma_high_water);
7674
7675 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7676 for (i = 0; i < 2000; i++) {
7677 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7678 break;
7679 udelay(10);
7680 }
7681 if (i >= 2000) {
7682 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7683 tp->dev->name);
7684 return -ENODEV;
7685 }
7686
7687 /* Setup replenish threshold. */
f92905de
MC		 7688 val = tp->rx_pending / 8;
7689 if (val == 0)
7690 val = 1;
7691 else if (val > tp->rx_std_max_post)
7692 val = tp->rx_std_max_post;
b5d3772c
MC		 7693 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7694 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7695 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7696
7697 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7698 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7699 }
f92905de
MC		 7700
7701 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7702
7703 /* Initialize TG3_BDINFO's at:
7704 * RCVDBDI_STD_BD: standard eth size rx ring
7705 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7706 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7707 *
7708 * like so:
7709 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7710 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7711 * ring attribute flags
7712 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7713 *
7714 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7715 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7716 *
7717 * The size of each ring is fixed in the firmware, but the location is
7718 * configurable.
7719 */
7720 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7721 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7722 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7723 ((u64) tpr->rx_std_mapping & 0xffffffff));
87668d35
MC		 7724 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7725 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7726 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7727
fdb72b38
MC		 7728 /* Disable the mini ring */
7729 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7730 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7731 BDINFO_FLAGS_DISABLED);
7732
fdb72b38
MC		 7733 /* Program the jumbo buffer descriptor ring control
7734 * blocks on those devices that have them.
7735 */
8f666b07 7736 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7737 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7738 /* Setup replenish threshold. */
7739 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7740
0f893dc6 7741 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7742 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7743 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7744 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7745 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7746 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7747 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7748 BDINFO_FLAGS_USE_EXT_RECV);
87668d35
MC		 7749 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7750 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7751 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7752 } else {
7753 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7754 BDINFO_FLAGS_DISABLED);
7755 }
7756
f6eb9b1f
MC		 7757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7758 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7759 (RX_STD_MAX_SIZE << 2);
7760 else
7761 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7762 } else
7763 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7764
7765 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7766
411da640 7767 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 7768 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 7769
411da640 7770 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7771 tp->rx_jumbo_pending : 0;
66711e66 7772 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 7773
f6eb9b1f
MC		 7774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7775 tw32(STD_REPLENISH_LWM, 32);
7776 tw32(JMB_REPLENISH_LWM, 16);
7777 }
7778
2d31ecaf
MC		 7779 tg3_rings_reset(tp);
7780
1da177e4 7781 /* Initialize MAC address and backoff seed. */
986e0aeb 7782 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7783
7784 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7785 tw32(MAC_RX_MTU_SIZE,
7786 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7787
7788 /* The slot time is changed by tg3_setup_phy if we
7789 * run at gigabit with half duplex.
7790 */
7791 tw32(MAC_TX_LENGTHS,
7792 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7793 (6 << TX_LENGTHS_IPG_SHIFT) |
7794 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7795
7796 /* Receive rules. */
7797 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7798 tw32(RCVLPC_CONFIG, 0x0181);
7799
7800 /* Calculate RDMAC_MODE setting early, we need it to determine
7801 * the RCVLPC_STATE_ENABLE mask.
7802 */
7803 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7804 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7805 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7806 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7807 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7808
57e6983c 7809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7810 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7811 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7812 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7813 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7814 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7815
85e94ced
MC		 7816 /* If statement applies to 5705 and 5750 PCI devices only */
7817 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7818 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7819 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7820 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7822 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7823 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7824 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7825 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7826 }
7827 }
7828
85e94ced
MC		 7829 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7830 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7831
1da177e4 7832 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7833 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7834
e849cdc3
MC		 7835 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7838 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7839
7840 /* Receive/send statistics. */
1661394e
MC		 7841 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7842 val = tr32(RCVLPC_STATS_ENABLE);
7843 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7844 tw32(RCVLPC_STATS_ENABLE, val);
7845 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7846 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7847 val = tr32(RCVLPC_STATS_ENABLE);
7848 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7849 tw32(RCVLPC_STATS_ENABLE, val);
7850 } else {
7851 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7852 }
7853 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7854 tw32(SNDDATAI_STATSENAB, 0xffffff);
7855 tw32(SNDDATAI_STATSCTRL,
7856 (SNDDATAI_SCTRL_ENABLE |
7857 SNDDATAI_SCTRL_FASTUPD));
7858
7859 /* Setup host coalescing engine. */
7860 tw32(HOSTCC_MODE, 0);
7861 for (i = 0; i < 2000; i++) {
7862 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7863 break;
7864 udelay(10);
7865 }
7866
d244c892 7867 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7868
1da177e4
LT		 7869 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7870 /* Status/statistics block address. See tg3_timer,
7871 * the tg3_periodic_fetch_stats call there, and
7872 * tg3_get_stats to see how this works for 5705/5750 chips.
7873 */
1da177e4
LT		 7874 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7875 ((u64) tp->stats_mapping >> 32));
7876 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7877 ((u64) tp->stats_mapping & 0xffffffff));
7878 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7879
1da177e4 7880 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7881
7882 /* Clear statistics and status block memory areas */
7883 for (i = NIC_SRAM_STATS_BLK;
7884 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7885 i += sizeof(u32)) {
7886 tg3_write_mem(tp, i, 0);
7887 udelay(40);
7888 }
1da177e4
LT		 7889 }
7890
7891 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7892
7893 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7894 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7895 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7896 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7897
c94e3941
MC		 7898 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7899 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7900 /* reset to prevent losing 1st rx packet intermittently */
7901 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7902 udelay(10);
7903 }
7904
3bda1258
MC		 7905 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7906 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7907 else
7908 tp->mac_mode = 0;
7909 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7910 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7911 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7912 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7913 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7914 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7915 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7916 udelay(40);
7917
314fba34 7918 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7919 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7920 * register to preserve the GPIO settings for LOMs. The GPIOs,
7921 * whether used as inputs or outputs, are set by boot code after
7922 * reset.
7923 */
9d26e213 7924 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7925 u32 gpio_mask;
7926
9d26e213
MC		 7927 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7928 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7929 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7930
7931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7932 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7933 GRC_LCLCTRL_GPIO_OUTPUT3;
7934
af36e6b6
MC		 7935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7936 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7937
aaf84465 7938 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7939 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7940
7941 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7942 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7943 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7944 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7945 }
1da177e4
LT		 7946 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7947 udelay(100);
7948
baf8a94a
MC		 7949 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7950 val = tr32(MSGINT_MODE);
7951 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7952 tw32(MSGINT_MODE, val);
7953 }
7954
1da177e4
LT		 7955 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7956 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7957 udelay(40);
7958 }
7959
7960 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7961 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7962 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7963 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7964 WDMAC_MODE_LNGREAD_ENAB);
7965
85e94ced
MC		 7966 /* If statement applies to 5705 and 5750 PCI devices only */
7967 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7968 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7970 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7971 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7972 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7973 /* nothing */
7974 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7975 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7976 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7977 val |= WDMAC_MODE_RX_ACCEL;
7978 }
7979 }
7980
d9ab5ad1 7981 /* Enable host coalescing bug fix */
321d32a0 7982 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7983 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7984
788a035e
MC		 7985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7986 val |= WDMAC_MODE_BURST_ALL_DATA;
7987
1da177e4
LT		 7988 tw32_f(WDMAC_MODE, val);
7989 udelay(40);
7990
9974a356
MC		 7991 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7992 u16 pcix_cmd;
7993
7994 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7995 &pcix_cmd);
1da177e4 7996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7997 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7998 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7999 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 8000 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8001 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 8002 }
9974a356
MC		 8003 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8004 pcix_cmd);
1da177e4
LT		 8005 }
8006
8007 tw32_f(RDMAC_MODE, rdmac_mode);
8008 udelay(40);
8009
8010 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8011 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8012 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 8013
8014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8015 tw32(SNDDATAC_MODE,
8016 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8017 else
8018 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8019
1da177e4
LT		 8020 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8021 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8022 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8023 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 8024 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8025 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 8026 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8027 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8028 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8029 tw32(SNDBDI_MODE, val);
1da177e4
LT		 8030 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8031
8032 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8033 err = tg3_load_5701_a0_firmware_fix(tp);
8034 if (err)
8035 return err;
8036 }
8037
1da177e4
LT		 8038 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8039 err = tg3_load_tso_firmware(tp);
8040 if (err)
8041 return err;
8042 }
1da177e4
LT		 8043
8044 tp->tx_mode = TX_MODE_ENABLE;
8045 tw32_f(MAC_TX_MODE, tp->tx_mode);
8046 udelay(100);
8047
baf8a94a
MC		 8048 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8049 u32 reg = MAC_RSS_INDIR_TBL_0;
8050 u8 *ent = (u8 *)&val;
8051
8052 /* Setup the indirection table */
8053 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8054 int idx = i % sizeof(val);
8055
8056 ent[idx] = i % (tp->irq_cnt - 1);
8057 if (idx == sizeof(val) - 1) {
8058 tw32(reg, val);
8059 reg += 4;
8060 }
8061 }
8062
8063 /* Setup the "secret" hash key. */
8064 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8065 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8066 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8067 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8068 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8069 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8070 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8071 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8072 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8073 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8074 }
8075
1da177e4 8076 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 8077 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 8078 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8079
baf8a94a
MC		 8080 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8081 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8082 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8083 RX_MODE_RSS_IPV6_HASH_EN |
8084 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8085 RX_MODE_RSS_IPV4_HASH_EN |
8086 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8087
1da177e4
LT		 8088 tw32_f(MAC_RX_MODE, tp->rx_mode);
8089 udelay(10);
8090
1da177e4
LT		 8091 tw32(MAC_LED_CTRL, tp->led_ctrl);
8092
8093 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 8094 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 8095 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8096 udelay(10);
8097 }
8098 tw32_f(MAC_RX_MODE, tp->rx_mode);
8099 udelay(10);
8100
8101 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8103 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8104 /* Set drive transmission level to 1.2V */
8105 /* only if the signal pre-emphasis bit is not set */
8106 val = tr32(MAC_SERDES_CFG);
8107 val &= 0xfffff000;
8108 val |= 0x880;
8109 tw32(MAC_SERDES_CFG, val);
8110 }
8111 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8112 tw32(MAC_SERDES_CFG, 0x616000);
8113 }
8114
8115 /* Prevent chip from dropping frames when flow control
8116 * is enabled.
8117 */
8118 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
8119
8120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8121 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8122 /* Use hardware link auto-negotiation */
8123 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8124 }
8125
d4d2c558
MC		 8126 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8127 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8128 u32 tmp;
8129
8130 tmp = tr32(SERDES_RX_CTRL);
8131 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8132 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8133 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8134 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8135 }
8136
dd477003
MC		 8137 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8138 if (tp->link_config.phy_is_low_power) {
8139 tp->link_config.phy_is_low_power = 0;
8140 tp->link_config.speed = tp->link_config.orig_speed;
8141 tp->link_config.duplex = tp->link_config.orig_duplex;
8142 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8143 }
1da177e4 8144
dd477003
MC		 8145 err = tg3_setup_phy(tp, 0);
8146 if (err)
8147 return err;
1da177e4 8148
dd477003 8149 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 8150 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 8151 u32 tmp;
8152
8153 /* Clear CRC stats. */
8154 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8155 tg3_writephy(tp, MII_TG3_TEST1,
8156 tmp | MII_TG3_TEST1_CRC_EN);
8157 tg3_readphy(tp, 0x14, &tmp);
8158 }
1da177e4
LT		 8159 }
8160 }
8161
8162 __tg3_set_rx_mode(tp->dev);
8163
8164 /* Initialize receive rules. */
8165 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8166 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8167 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8168 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8169
4cf78e4f 8170 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 8171 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 8172 limit = 8;
8173 else
8174 limit = 16;
8175 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8176 limit -= 4;
8177 switch (limit) {
8178 case 16:
8179 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8180 case 15:
8181 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8182 case 14:
8183 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8184 case 13:
8185 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8186 case 12:
8187 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8188 case 11:
8189 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8190 case 10:
8191 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8192 case 9:
8193 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8194 case 8:
8195 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8196 case 7:
8197 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8198 case 6:
8199 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8200 case 5:
8201 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8202 case 4:
8203 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8204 case 3:
8205 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8206 case 2:
8207 case 1:
8208
8209 default:
8210 break;
855e1111 8211 }
1da177e4 8212
9ce768ea
MC		 8213 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8214 /* Write our heartbeat update interval to APE. */
8215 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8216 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 8217
1da177e4
LT		 8218 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8219
1da177e4
LT		 8220 return 0;
8221}
8222
8223/* Called at device open time to get the chip ready for
8224 * packet processing. Invoked with tp->lock held.
8225 */
8e7a22e3 8226static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 8227{
1da177e4
LT		 8228 tg3_switch_clocks(tp);
8229
8230 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8231
2f751b67 8232 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 8233}
8234
8235#define TG3_STAT_ADD32(PSTAT, REG) \
8236do { u32 __val = tr32(REG); \
8237 (PSTAT)->low += __val; \
8238 if ((PSTAT)->low < __val) \
8239 (PSTAT)->high += 1; \
8240} while (0)
8241
8242static void tg3_periodic_fetch_stats(struct tg3 *tp)
8243{
8244 struct tg3_hw_stats *sp = tp->hw_stats;
8245
8246 if (!netif_carrier_ok(tp->dev))
8247 return;
8248
8249 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8250 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8251 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8252 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8253 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8254 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8255 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8256 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8257 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8258 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8259 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8260 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8261 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8262
8263 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8264 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8265 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8266 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8267 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8268 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8269 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8270 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8271 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8272 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8273 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8274 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8275 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8276 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8277
8278 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8279 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8280 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8281}
8282
8283static void tg3_timer(unsigned long __opaque)
8284{
8285 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8286
f475f163
MC		 8287 if (tp->irq_sync)
8288 goto restart_timer;
8289
f47c11ee 8290 spin_lock(&tp->lock);
1da177e4 8291
fac9b83e
DM		 8292 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8293 /* All of this garbage is because when using non-tagged
8294 * IRQ status the mailbox/status_block protocol the chip
8295 * uses with the cpu is race prone.
8296 */
898a56f8 8297 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8298 tw32(GRC_LOCAL_CTRL,
8299 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8300 } else {
8301 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8302 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8303 }
1da177e4 8304
fac9b83e
DM		 8305 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8306 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8307 spin_unlock(&tp->lock);
fac9b83e
DM		 8308 schedule_work(&tp->reset_task);
8309 return;
8310 }
1da177e4
LT		 8311 }
8312
1da177e4
LT		 8313 /* This part only runs once per second. */
8314 if (!--tp->timer_counter) {
fac9b83e
DM		 8315 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8316 tg3_periodic_fetch_stats(tp);
8317
1da177e4
LT		 8318 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8319 u32 mac_stat;
8320 int phy_event;
8321
8322 mac_stat = tr32(MAC_STATUS);
8323
8324 phy_event = 0;
8325 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8326 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8327 phy_event = 1;
8328 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8329 phy_event = 1;
8330
8331 if (phy_event)
8332 tg3_setup_phy(tp, 0);
8333 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8334 u32 mac_stat = tr32(MAC_STATUS);
8335 int need_setup = 0;
8336
8337 if (netif_carrier_ok(tp->dev) &&
8338 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8339 need_setup = 1;
8340 }
8341 if (! netif_carrier_ok(tp->dev) &&
8342 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8343 MAC_STATUS_SIGNAL_DET))) {
8344 need_setup = 1;
8345 }
8346 if (need_setup) {
3d3ebe74
MC		 8347 if (!tp->serdes_counter) {
8348 tw32_f(MAC_MODE,
8349 (tp->mac_mode &
8350 ~MAC_MODE_PORT_MODE_MASK));
8351 udelay(40);
8352 tw32_f(MAC_MODE, tp->mac_mode);
8353 udelay(40);
8354 }
1da177e4
LT		 8355 tg3_setup_phy(tp, 0);
8356 }
747e8f8b
MC		 8357 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8358 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8359
8360 tp->timer_counter = tp->timer_multiplier;
8361 }
8362
130b8e4d
MC		 8363 /* Heartbeat is only sent once every 2 seconds.
8364 *
8365 * The heartbeat is to tell the ASF firmware that the host
8366 * driver is still alive. In the event that the OS crashes,
8367 * ASF needs to reset the hardware to free up the FIFO space
8368 * that may be filled with rx packets destined for the host.
8369 * If the FIFO is full, ASF will no longer function properly.
8370 *
8371 * Unintended resets have been reported on real time kernels
8372 * where the timer doesn't run on time. Netpoll will also have
8373 * same problem.
8374 *
8375 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8376 * to check the ring condition when the heartbeat is expiring
8377 * before doing the reset. This will prevent most unintended
8378 * resets.
8379 */
1da177e4 8380 if (!--tp->asf_counter) {
bc7959b2
MC		 8381 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8382 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8383 tg3_wait_for_event_ack(tp);
8384
bbadf503 8385 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8386 FWCMD_NICDRV_ALIVE3);
bbadf503 8387 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8388 /* 5 seconds timeout */
bbadf503 8389 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8390
8391 tg3_generate_fw_event(tp);
1da177e4
LT		 8392 }
8393 tp->asf_counter = tp->asf_multiplier;
8394 }
8395
f47c11ee 8396 spin_unlock(&tp->lock);
1da177e4 8397
f475f163 8398restart_timer:
1da177e4
LT		 8399 tp->timer.expires = jiffies + tp->timer_offset;
8400 add_timer(&tp->timer);
8401}
8402
4f125f42 8403static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8404{
7d12e780 8405 irq_handler_t fn;
fcfa0a32 8406 unsigned long flags;
4f125f42
MC		 8407 char *name;
8408 struct tg3_napi *tnapi = &tp->napi[irq_num];
8409
8410 if (tp->irq_cnt == 1)
8411 name = tp->dev->name;
8412 else {
8413 name = &tnapi->irq_lbl[0];
8414 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8415 name[IFNAMSIZ-1] = 0;
8416 }
fcfa0a32 8417
679563f4 8418 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8419 fn = tg3_msi;
8420 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8421 fn = tg3_msi_1shot;
1fb9df5d 8422 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8423 } else {
8424 fn = tg3_interrupt;
8425 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8426 fn = tg3_interrupt_tagged;
1fb9df5d 8427 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8428 }
4f125f42
MC		 8429
8430 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8431}
8432
7938109f
MC		 8433static int tg3_test_interrupt(struct tg3 *tp)
8434{
09943a18 8435 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8436 struct net_device *dev = tp->dev;
b16250e3 8437 int err, i, intr_ok = 0;
f6eb9b1f 8438 u32 val;
7938109f 8439
d4bc3927
MC		 8440 if (!netif_running(dev))
8441 return -ENODEV;
8442
7938109f
MC		 8443 tg3_disable_ints(tp);
8444
4f125f42 8445 free_irq(tnapi->irq_vec, tnapi);
7938109f 8446
f6eb9b1f
MC		 8447 /*
8448 * Turn off MSI one shot mode. Otherwise this test has no
8449 * observable way to know whether the interrupt was delivered.
8450 */
8451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8452 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8453 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8454 tw32(MSGINT_MODE, val);
8455 }
8456
4f125f42 8457 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8458 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8459 if (err)
8460 return err;
8461
898a56f8 8462 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8463 tg3_enable_ints(tp);
8464
8465 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8466 tnapi->coal_now);
7938109f
MC		 8467
8468 for (i = 0; i < 5; i++) {
b16250e3
MC		 8469 u32 int_mbox, misc_host_ctrl;
8470
898a56f8 8471 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8472 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8473
8474 if ((int_mbox != 0) ||
8475 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8476 intr_ok = 1;
7938109f 8477 break;
b16250e3
MC		 8478 }
8479
7938109f
MC		 8480 msleep(10);
8481 }
8482
8483 tg3_disable_ints(tp);
8484
4f125f42 8485 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8486
4f125f42 8487 err = tg3_request_irq(tp, 0);
7938109f
MC		 8488
8489 if (err)
8490 return err;
8491
f6eb9b1f
MC		 8492 if (intr_ok) {
8493 /* Reenable MSI one shot mode. */
8494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8495 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8496 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8497 tw32(MSGINT_MODE, val);
8498 }
7938109f 8499 return 0;
f6eb9b1f 8500 }
7938109f
MC		 8501
8502 return -EIO;
8503}
8504
8505/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8506 * successfully restored
8507 */
8508static int tg3_test_msi(struct tg3 *tp)
8509{
7938109f
MC		 8510 int err;
8511 u16 pci_cmd;
8512
8513 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8514 return 0;
8515
8516 /* Turn off SERR reporting in case MSI terminates with Master
8517 * Abort.
8518 */
8519 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8520 pci_write_config_word(tp->pdev, PCI_COMMAND,
8521 pci_cmd & ~PCI_COMMAND_SERR);
8522
8523 err = tg3_test_interrupt(tp);
8524
8525 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8526
8527 if (!err)
8528 return 0;
8529
8530 /* other failures */
8531 if (err != -EIO)
8532 return err;
8533
8534 /* MSI test failed, go back to INTx mode */
8535 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8536 "switching to INTx mode. Please report this failure to "
8537 "the PCI maintainer and include system chipset information.\n",
8538 tp->dev->name);
8539
4f125f42 8540 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8541
7938109f
MC		 8542 pci_disable_msi(tp->pdev);
8543
8544 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8545
4f125f42 8546 err = tg3_request_irq(tp, 0);
7938109f
MC		 8547 if (err)
8548 return err;
8549
8550 /* Need to reset the chip because the MSI cycle may have terminated
8551 * with Master Abort.
8552 */
f47c11ee 8553 tg3_full_lock(tp, 1);
7938109f 8554
944d980e 8555 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8556 err = tg3_init_hw(tp, 1);
7938109f 8557
f47c11ee 8558 tg3_full_unlock(tp);
7938109f
MC		 8559
8560 if (err)
4f125f42 8561 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8562
8563 return err;
8564}
8565
9e9fd12d
MC		 8566static int tg3_request_firmware(struct tg3 *tp)
8567{
8568 const __be32 *fw_data;
8569
8570 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8571 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8572 tp->dev->name, tp->fw_needed);
8573 return -ENOENT;
8574 }
8575
8576 fw_data = (void *)tp->fw->data;
8577
8578 /* Firmware blob starts with version numbers, followed by
8579 * start address and _full_ length including BSS sections
8580 * (which must be longer than the actual data, of course
8581 */
8582
8583 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8584 if (tp->fw_len < (tp->fw->size - 12)) {
8585 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8586 tp->dev->name, tp->fw_len, tp->fw_needed);
8587 release_firmware(tp->fw);
8588 tp->fw = NULL;
8589 return -EINVAL;
8590 }
8591
8592 /* We no longer need firmware; we have it. */
8593 tp->fw_needed = NULL;
8594 return 0;
8595}
8596
679563f4
MC		 8597static bool tg3_enable_msix(struct tg3 *tp)
8598{
8599 int i, rc, cpus = num_online_cpus();
8600 struct msix_entry msix_ent[tp->irq_max];
8601
8602 if (cpus == 1)
8603 /* Just fallback to the simpler MSI mode. */
8604 return false;
8605
8606 /*
8607 * We want as many rx rings enabled as there are cpus.
8608 * The first MSIX vector only deals with link interrupts, etc,
8609 * so we add one to the number of vectors we are requesting.
8610 */
8611 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8612
8613 for (i = 0; i < tp->irq_max; i++) {
8614 msix_ent[i].entry = i;
8615 msix_ent[i].vector = 0;
8616 }
8617
8618 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8619 if (rc != 0) {
8620 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8621 return false;
8622 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8623 return false;
8624 printk(KERN_NOTICE
8625 "%s: Requested %d MSI-X vectors, received %d\n",
8626 tp->dev->name, tp->irq_cnt, rc);
8627 tp->irq_cnt = rc;
8628 }
8629
baf8a94a
MC		 8630 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8631
679563f4
MC		 8632 for (i = 0; i < tp->irq_max; i++)
8633 tp->napi[i].irq_vec = msix_ent[i].vector;
8634
fe5f5787
MC		 8635 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8636
679563f4
MC		 8637 return true;
8638}
8639
07b0173c
MC		 8640static void tg3_ints_init(struct tg3 *tp)
8641{
679563f4
MC		 8642 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8643 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8644 /* All MSI supporting chips should support tagged
8645 * status. Assert that this is the case.
8646 */
679563f4
MC		 8647 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8648 "Not using MSI.\n", tp->dev->name);
8649 goto defcfg;
07b0173c 8650 }
4f125f42 8651
679563f4
MC		 8652 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8653 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8654 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8655 pci_enable_msi(tp->pdev) == 0)
8656 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8657
8658 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8659 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8660 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8661 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8662 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8663 }
8664defcfg:
8665 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8666 tp->irq_cnt = 1;
8667 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8668 tp->dev->real_num_tx_queues = 1;
679563f4 8669 }
07b0173c
MC		 8670}
8671
8672static void tg3_ints_fini(struct tg3 *tp)
8673{
679563f4
MC		 8674 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8675 pci_disable_msix(tp->pdev);
8676 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8677 pci_disable_msi(tp->pdev);
8678 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8679 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8680}
8681
1da177e4
LT		 8682static int tg3_open(struct net_device *dev)
8683{
8684 struct tg3 *tp = netdev_priv(dev);
4f125f42 8685 int i, err;
1da177e4 8686
9e9fd12d
MC		 8687 if (tp->fw_needed) {
8688 err = tg3_request_firmware(tp);
8689 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8690 if (err)
8691 return err;
8692 } else if (err) {
8693 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8694 tp->dev->name);
8695 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8696 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8697 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8698 tp->dev->name);
8699 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8700 }
8701 }
8702
c49a1561
MC		 8703 netif_carrier_off(tp->dev);
8704
bc1c7567 8705 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8706 if (err)
bc1c7567 8707 return err;
2f751b67
MC		 8708
8709 tg3_full_lock(tp, 0);
bc1c7567 8710
1da177e4
LT		 8711 tg3_disable_ints(tp);
8712 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8713
f47c11ee 8714 tg3_full_unlock(tp);
1da177e4 8715
679563f4
MC		 8716 /*
8717 * Setup interrupts first so we know how
8718 * many NAPI resources to allocate
8719 */
8720 tg3_ints_init(tp);
8721
1da177e4
LT		 8722 /* The placement of this call is tied
8723 * to the setup and use of Host TX descriptors.
8724 */
8725 err = tg3_alloc_consistent(tp);
8726 if (err)
679563f4 8727 goto err_out1;
88b06bc2 8728
fed97810 8729 tg3_napi_enable(tp);
1da177e4 8730
4f125f42
MC		 8731 for (i = 0; i < tp->irq_cnt; i++) {
8732 struct tg3_napi *tnapi = &tp->napi[i];
8733 err = tg3_request_irq(tp, i);
8734 if (err) {
8735 for (i--; i >= 0; i--)
8736 free_irq(tnapi->irq_vec, tnapi);
8737 break;
8738 }
8739 }
1da177e4 8740
07b0173c 8741 if (err)
679563f4 8742 goto err_out2;
bea3348e 8743
f47c11ee 8744 tg3_full_lock(tp, 0);
1da177e4 8745
8e7a22e3 8746 err = tg3_init_hw(tp, 1);
1da177e4 8747 if (err) {
944d980e 8748 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8749 tg3_free_rings(tp);
8750 } else {
fac9b83e
DM		 8751 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8752 tp->timer_offset = HZ;
8753 else
8754 tp->timer_offset = HZ / 10;
8755
8756 BUG_ON(tp->timer_offset > HZ);
8757 tp->timer_counter = tp->timer_multiplier =
8758 (HZ / tp->timer_offset);
8759 tp->asf_counter = tp->asf_multiplier =
28fbef78 8760 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8761
8762 init_timer(&tp->timer);
8763 tp->timer.expires = jiffies + tp->timer_offset;
8764 tp->timer.data = (unsigned long) tp;
8765 tp->timer.function = tg3_timer;
1da177e4
LT		 8766 }
8767
f47c11ee 8768 tg3_full_unlock(tp);
1da177e4 8769
07b0173c 8770 if (err)
679563f4 8771 goto err_out3;
1da177e4 8772
7938109f
MC		 8773 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8774 err = tg3_test_msi(tp);
fac9b83e 8775
7938109f 8776 if (err) {
f47c11ee 8777 tg3_full_lock(tp, 0);
944d980e 8778 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8779 tg3_free_rings(tp);
f47c11ee 8780 tg3_full_unlock(tp);
7938109f 8781
679563f4 8782 goto err_out2;
7938109f 8783 }
fcfa0a32 8784
f6eb9b1f
MC		 8785 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8786 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8787 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8788 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8789
f6eb9b1f
MC		 8790 tw32(PCIE_TRANSACTION_CFG,
8791 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8792 }
7938109f
MC		 8793 }
8794
b02fd9e3
MC		 8795 tg3_phy_start(tp);
8796
f47c11ee 8797 tg3_full_lock(tp, 0);
1da177e4 8798
7938109f
MC		 8799 add_timer(&tp->timer);
8800 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8801 tg3_enable_ints(tp);
8802
f47c11ee 8803 tg3_full_unlock(tp);
1da177e4 8804
fe5f5787 8805 netif_tx_start_all_queues(dev);
1da177e4
LT		 8806
8807 return 0;
07b0173c 8808
679563f4 8809err_out3:
4f125f42
MC		 8810 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8811 struct tg3_napi *tnapi = &tp->napi[i];
8812 free_irq(tnapi->irq_vec, tnapi);
8813 }
07b0173c 8814
679563f4 8815err_out2:
fed97810 8816 tg3_napi_disable(tp);
07b0173c 8817 tg3_free_consistent(tp);
679563f4
MC		 8818
8819err_out1:
8820 tg3_ints_fini(tp);
07b0173c 8821 return err;
1da177e4
LT		 8822}
8823
8824#if 0
8825/*static*/ void tg3_dump_state(struct tg3 *tp)
8826{
8827 u32 val32, val32_2, val32_3, val32_4, val32_5;
8828 u16 val16;
8829 int i;
898a56f8 8830 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8831
8832 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8833 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8834 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8835 val16, val32);
8836
8837 /* MAC block */
8838 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8839 tr32(MAC_MODE), tr32(MAC_STATUS));
8840 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8841 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8842 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8843 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8844 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8845 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8846
8847 /* Send data initiator control block */
8848 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8849 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8850 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8851 tr32(SNDDATAI_STATSCTRL));
8852
8853 /* Send data completion control block */
8854 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8855
8856 /* Send BD ring selector block */
8857 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8858 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8859
8860 /* Send BD initiator control block */
8861 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8862 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8863
8864 /* Send BD completion control block */
8865 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8866
8867 /* Receive list placement control block */
8868 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8869 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8870 printk(" RCVLPC_STATSCTRL[%08x]\n",
8871 tr32(RCVLPC_STATSCTRL));
8872
8873 /* Receive data and receive BD initiator control block */
8874 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8875 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8876
8877 /* Receive data completion control block */
8878 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8879 tr32(RCVDCC_MODE));
8880
8881 /* Receive BD initiator control block */
8882 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8883 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8884
8885 /* Receive BD completion control block */
8886 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8887 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8888
8889 /* Receive list selector control block */
8890 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8891 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8892
8893 /* Mbuf cluster free block */
8894 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8895 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8896
8897 /* Host coalescing control block */
8898 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8899 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8900 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8901 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8902 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8903 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8904 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8905 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8906 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8907 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8908 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8909 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8910
8911 /* Memory arbiter control block */
8912 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8913 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8914
8915 /* Buffer manager control block */
8916 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8917 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8918 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8919 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8920 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8921 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8922 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8923 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8924
8925 /* Read DMA control block */
8926 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8927 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8928
8929 /* Write DMA control block */
8930 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8931 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8932
8933 /* DMA completion block */
8934 printk("DEBUG: DMAC_MODE[%08x]\n",
8935 tr32(DMAC_MODE));
8936
8937 /* GRC block */
8938 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8939 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8940 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8941 tr32(GRC_LOCAL_CTRL));
8942
8943 /* TG3_BDINFOs */
8944 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8945 tr32(RCVDBDI_JUMBO_BD + 0x0),
8946 tr32(RCVDBDI_JUMBO_BD + 0x4),
8947 tr32(RCVDBDI_JUMBO_BD + 0x8),
8948 tr32(RCVDBDI_JUMBO_BD + 0xc));
8949 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8950 tr32(RCVDBDI_STD_BD + 0x0),
8951 tr32(RCVDBDI_STD_BD + 0x4),
8952 tr32(RCVDBDI_STD_BD + 0x8),
8953 tr32(RCVDBDI_STD_BD + 0xc));
8954 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8955 tr32(RCVDBDI_MINI_BD + 0x0),
8956 tr32(RCVDBDI_MINI_BD + 0x4),
8957 tr32(RCVDBDI_MINI_BD + 0x8),
8958 tr32(RCVDBDI_MINI_BD + 0xc));
8959
8960 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8961 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8962 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8963 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8964 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8965 val32, val32_2, val32_3, val32_4);
8966
8967 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8968 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8969 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8970 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8971 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8972 val32, val32_2, val32_3, val32_4);
8973
8974 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8975 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8976 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8977 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8978 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8979 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8980 val32, val32_2, val32_3, val32_4, val32_5);
8981
8982 /* SW status block */
898a56f8
MC		 8983 printk(KERN_DEBUG
8984 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8985 sblk->status,
8986 sblk->status_tag,
8987 sblk->rx_jumbo_consumer,
8988 sblk->rx_consumer,
8989 sblk->rx_mini_consumer,
8990 sblk->idx[0].rx_producer,
8991 sblk->idx[0].tx_consumer);
1da177e4
LT		 8992
8993 /* SW statistics block */
8994 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8995 ((u32 *)tp->hw_stats)[0],
8996 ((u32 *)tp->hw_stats)[1],
8997 ((u32 *)tp->hw_stats)[2],
8998 ((u32 *)tp->hw_stats)[3]);
8999
9000 /* Mailboxes */
9001 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 9002 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9003 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9004 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9005 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 9006
9007 /* NIC side send descriptors. */
9008 for (i = 0; i < 6; i++) {
9009 unsigned long txd;
9010
9011 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9012 + (i * sizeof(struct tg3_tx_buffer_desc));
9013 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9014 i,
9015 readl(txd + 0x0), readl(txd + 0x4),
9016 readl(txd + 0x8), readl(txd + 0xc));
9017 }
9018
9019 /* NIC side RX descriptors. */
9020 for (i = 0; i < 6; i++) {
9021 unsigned long rxd;
9022
9023 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9024 + (i * sizeof(struct tg3_rx_buffer_desc));
9025 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9026 i,
9027 readl(rxd + 0x0), readl(rxd + 0x4),
9028 readl(rxd + 0x8), readl(rxd + 0xc));
9029 rxd += (4 * sizeof(u32));
9030 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9031 i,
9032 readl(rxd + 0x0), readl(rxd + 0x4),
9033 readl(rxd + 0x8), readl(rxd + 0xc));
9034 }
9035
9036 for (i = 0; i < 6; i++) {
9037 unsigned long rxd;
9038
9039 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9040 + (i * sizeof(struct tg3_rx_buffer_desc));
9041 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9042 i,
9043 readl(rxd + 0x0), readl(rxd + 0x4),
9044 readl(rxd + 0x8), readl(rxd + 0xc));
9045 rxd += (4 * sizeof(u32));
9046 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9047 i,
9048 readl(rxd + 0x0), readl(rxd + 0x4),
9049 readl(rxd + 0x8), readl(rxd + 0xc));
9050 }
9051}
9052#endif
9053
9054static struct net_device_stats *tg3_get_stats(struct net_device *);
9055static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9056
9057static int tg3_close(struct net_device *dev)
9058{
4f125f42 9059 int i;
1da177e4
LT		 9060 struct tg3 *tp = netdev_priv(dev);
9061
fed97810 9062 tg3_napi_disable(tp);
28e53bdd 9063 cancel_work_sync(&tp->reset_task);
7faa006f 9064
fe5f5787 9065 netif_tx_stop_all_queues(dev);
1da177e4
LT		 9066
9067 del_timer_sync(&tp->timer);
9068
24bb4fb6
MC		 9069 tg3_phy_stop(tp);
9070
f47c11ee 9071 tg3_full_lock(tp, 1);
1da177e4
LT		 9072#if 0
9073 tg3_dump_state(tp);
9074#endif
9075
9076 tg3_disable_ints(tp);
9077
944d980e 9078 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 9079 tg3_free_rings(tp);
5cf64b8a 9080 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 9081
f47c11ee 9082 tg3_full_unlock(tp);
1da177e4 9083
4f125f42
MC		 9084 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9085 struct tg3_napi *tnapi = &tp->napi[i];
9086 free_irq(tnapi->irq_vec, tnapi);
9087 }
07b0173c
MC		 9088
9089 tg3_ints_fini(tp);
1da177e4
LT		 9090
9091 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9092 sizeof(tp->net_stats_prev));
9093 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9094 sizeof(tp->estats_prev));
9095
9096 tg3_free_consistent(tp);
9097
bc1c7567
MC		 9098 tg3_set_power_state(tp, PCI_D3hot);
9099
9100 netif_carrier_off(tp->dev);
9101
1da177e4
LT		 9102 return 0;
9103}
9104
9105static inline unsigned long get_stat64(tg3_stat64_t *val)
9106{
9107 unsigned long ret;
9108
9109#if (BITS_PER_LONG == 32)
9110 ret = val->low;
9111#else
9112 ret = ((u64)val->high << 32) | ((u64)val->low);
9113#endif
9114 return ret;
9115}
9116
816f8b86
SB		 9117static inline u64 get_estat64(tg3_stat64_t *val)
9118{
9119 return ((u64)val->high << 32) | ((u64)val->low);
9120}
9121
1da177e4
LT		 9122static unsigned long calc_crc_errors(struct tg3 *tp)
9123{
9124 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9125
9126 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9127 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 9129 u32 val;
9130
f47c11ee 9131 spin_lock_bh(&tp->lock);
569a5df8
MC		 9132 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9133 tg3_writephy(tp, MII_TG3_TEST1,
9134 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 9135 tg3_readphy(tp, 0x14, &val);
9136 } else
9137 val = 0;
f47c11ee 9138 spin_unlock_bh(&tp->lock);
1da177e4
LT		 9139
9140 tp->phy_crc_errors += val;
9141
9142 return tp->phy_crc_errors;
9143 }
9144
9145 return get_stat64(&hw_stats->rx_fcs_errors);
9146}
9147
9148#define ESTAT_ADD(member) \
9149 estats->member = old_estats->member + \
816f8b86 9150 get_estat64(&hw_stats->member)
1da177e4
LT		 9151
9152static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9153{
9154 struct tg3_ethtool_stats *estats = &tp->estats;
9155 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9156 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9157
9158 if (!hw_stats)
9159 return old_estats;
9160
9161 ESTAT_ADD(rx_octets);
9162 ESTAT_ADD(rx_fragments);
9163 ESTAT_ADD(rx_ucast_packets);
9164 ESTAT_ADD(rx_mcast_packets);
9165 ESTAT_ADD(rx_bcast_packets);
9166 ESTAT_ADD(rx_fcs_errors);
9167 ESTAT_ADD(rx_align_errors);
9168 ESTAT_ADD(rx_xon_pause_rcvd);
9169 ESTAT_ADD(rx_xoff_pause_rcvd);
9170 ESTAT_ADD(rx_mac_ctrl_rcvd);
9171 ESTAT_ADD(rx_xoff_entered);
9172 ESTAT_ADD(rx_frame_too_long_errors);
9173 ESTAT_ADD(rx_jabbers);
9174 ESTAT_ADD(rx_undersize_packets);
9175 ESTAT_ADD(rx_in_length_errors);
9176 ESTAT_ADD(rx_out_length_errors);
9177 ESTAT_ADD(rx_64_or_less_octet_packets);
9178 ESTAT_ADD(rx_65_to_127_octet_packets);
9179 ESTAT_ADD(rx_128_to_255_octet_packets);
9180 ESTAT_ADD(rx_256_to_511_octet_packets);
9181 ESTAT_ADD(rx_512_to_1023_octet_packets);
9182 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9183 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9184 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9185 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9186 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9187
9188 ESTAT_ADD(tx_octets);
9189 ESTAT_ADD(tx_collisions);
9190 ESTAT_ADD(tx_xon_sent);
9191 ESTAT_ADD(tx_xoff_sent);
9192 ESTAT_ADD(tx_flow_control);
9193 ESTAT_ADD(tx_mac_errors);
9194 ESTAT_ADD(tx_single_collisions);
9195 ESTAT_ADD(tx_mult_collisions);
9196 ESTAT_ADD(tx_deferred);
9197 ESTAT_ADD(tx_excessive_collisions);
9198 ESTAT_ADD(tx_late_collisions);
9199 ESTAT_ADD(tx_collide_2times);
9200 ESTAT_ADD(tx_collide_3times);
9201 ESTAT_ADD(tx_collide_4times);
9202 ESTAT_ADD(tx_collide_5times);
9203 ESTAT_ADD(tx_collide_6times);
9204 ESTAT_ADD(tx_collide_7times);
9205 ESTAT_ADD(tx_collide_8times);
9206 ESTAT_ADD(tx_collide_9times);
9207 ESTAT_ADD(tx_collide_10times);
9208 ESTAT_ADD(tx_collide_11times);
9209 ESTAT_ADD(tx_collide_12times);
9210 ESTAT_ADD(tx_collide_13times);
9211 ESTAT_ADD(tx_collide_14times);
9212 ESTAT_ADD(tx_collide_15times);
9213 ESTAT_ADD(tx_ucast_packets);
9214 ESTAT_ADD(tx_mcast_packets);
9215 ESTAT_ADD(tx_bcast_packets);
9216 ESTAT_ADD(tx_carrier_sense_errors);
9217 ESTAT_ADD(tx_discards);
9218 ESTAT_ADD(tx_errors);
9219
9220 ESTAT_ADD(dma_writeq_full);
9221 ESTAT_ADD(dma_write_prioq_full);
9222 ESTAT_ADD(rxbds_empty);
9223 ESTAT_ADD(rx_discards);
9224 ESTAT_ADD(rx_errors);
9225 ESTAT_ADD(rx_threshold_hit);
9226
9227 ESTAT_ADD(dma_readq_full);
9228 ESTAT_ADD(dma_read_prioq_full);
9229 ESTAT_ADD(tx_comp_queue_full);
9230
9231 ESTAT_ADD(ring_set_send_prod_index);
9232 ESTAT_ADD(ring_status_update);
9233 ESTAT_ADD(nic_irqs);
9234 ESTAT_ADD(nic_avoided_irqs);
9235 ESTAT_ADD(nic_tx_threshold_hit);
9236
9237 return estats;
9238}
9239
9240static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9241{
9242 struct tg3 *tp = netdev_priv(dev);
9243 struct net_device_stats *stats = &tp->net_stats;
9244 struct net_device_stats *old_stats = &tp->net_stats_prev;
9245 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9246
9247 if (!hw_stats)
9248 return old_stats;
9249
9250 stats->rx_packets = old_stats->rx_packets +
9251 get_stat64(&hw_stats->rx_ucast_packets) +
9252 get_stat64(&hw_stats->rx_mcast_packets) +
9253 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9254
1da177e4
LT		 9255 stats->tx_packets = old_stats->tx_packets +
9256 get_stat64(&hw_stats->tx_ucast_packets) +
9257 get_stat64(&hw_stats->tx_mcast_packets) +
9258 get_stat64(&hw_stats->tx_bcast_packets);
9259
9260 stats->rx_bytes = old_stats->rx_bytes +
9261 get_stat64(&hw_stats->rx_octets);
9262 stats->tx_bytes = old_stats->tx_bytes +
9263 get_stat64(&hw_stats->tx_octets);
9264
9265 stats->rx_errors = old_stats->rx_errors +
4f63b877 9266 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9267 stats->tx_errors = old_stats->tx_errors +
9268 get_stat64(&hw_stats->tx_errors) +
9269 get_stat64(&hw_stats->tx_mac_errors) +
9270 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9271 get_stat64(&hw_stats->tx_discards);
9272
9273 stats->multicast = old_stats->multicast +
9274 get_stat64(&hw_stats->rx_mcast_packets);
9275 stats->collisions = old_stats->collisions +
9276 get_stat64(&hw_stats->tx_collisions);
9277
9278 stats->rx_length_errors = old_stats->rx_length_errors +
9279 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9280 get_stat64(&hw_stats->rx_undersize_packets);
9281
9282 stats->rx_over_errors = old_stats->rx_over_errors +
9283 get_stat64(&hw_stats->rxbds_empty);
9284 stats->rx_frame_errors = old_stats->rx_frame_errors +
9285 get_stat64(&hw_stats->rx_align_errors);
9286 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9287 get_stat64(&hw_stats->tx_discards);
9288 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9289 get_stat64(&hw_stats->tx_carrier_sense_errors);
9290
9291 stats->rx_crc_errors = old_stats->rx_crc_errors +
9292 calc_crc_errors(tp);
9293
4f63b877
JL		 9294 stats->rx_missed_errors = old_stats->rx_missed_errors +
9295 get_stat64(&hw_stats->rx_discards);
9296
1da177e4
LT		 9297 return stats;
9298}
9299
9300static inline u32 calc_crc(unsigned char *buf, int len)
9301{
9302 u32 reg;
9303 u32 tmp;
9304 int j, k;
9305
9306 reg = 0xffffffff;
9307
9308 for (j = 0; j < len; j++) {
9309 reg ^= buf[j];
9310
9311 for (k = 0; k < 8; k++) {
9312 tmp = reg & 0x01;
9313
9314 reg >>= 1;
9315
9316 if (tmp) {
9317 reg ^= 0xedb88320;
9318 }
9319 }
9320 }
9321
9322 return ~reg;
9323}
9324
9325static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9326{
9327 /* accept or reject all multicast frames */
9328 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9329 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9330 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9331 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9332}
9333
9334static void __tg3_set_rx_mode(struct net_device *dev)
9335{
9336 struct tg3 *tp = netdev_priv(dev);
9337 u32 rx_mode;
9338
9339 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9340 RX_MODE_KEEP_VLAN_TAG);
9341
9342 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9343 * flag clear.
9344 */
9345#if TG3_VLAN_TAG_USED
9346 if (!tp->vlgrp &&
9347 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9348 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9349#else
9350 /* By definition, VLAN is disabled always in this
9351 * case.
9352 */
9353 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9354 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9355#endif
9356
9357 if (dev->flags & IFF_PROMISC) {
9358 /* Promiscuous mode. */
9359 rx_mode |= RX_MODE_PROMISC;
9360 } else if (dev->flags & IFF_ALLMULTI) {
9361 /* Accept all multicast. */
9362 tg3_set_multi (tp, 1);
9363 } else if (dev->mc_count < 1) {
9364 /* Reject all multicast. */
9365 tg3_set_multi (tp, 0);
9366 } else {
9367 /* Accept one or more multicast(s). */
9368 struct dev_mc_list *mclist;
9369 unsigned int i;
9370 u32 mc_filter[4] = { 0, };
9371 u32 regidx;
9372 u32 bit;
9373 u32 crc;
9374
9375 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9376 i++, mclist = mclist->next) {
9377
9378 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9379 bit = ~crc & 0x7f;
9380 regidx = (bit & 0x60) >> 5;
9381 bit &= 0x1f;
9382 mc_filter[regidx] |= (1 << bit);
9383 }
9384
9385 tw32(MAC_HASH_REG_0, mc_filter[0]);
9386 tw32(MAC_HASH_REG_1, mc_filter[1]);
9387 tw32(MAC_HASH_REG_2, mc_filter[2]);
9388 tw32(MAC_HASH_REG_3, mc_filter[3]);
9389 }
9390
9391 if (rx_mode != tp->rx_mode) {
9392 tp->rx_mode = rx_mode;
9393 tw32_f(MAC_RX_MODE, rx_mode);
9394 udelay(10);
9395 }
9396}
9397
9398static void tg3_set_rx_mode(struct net_device *dev)
9399{
9400 struct tg3 *tp = netdev_priv(dev);
9401
e75f7c90
MC		 9402 if (!netif_running(dev))
9403 return;
9404
f47c11ee 9405 tg3_full_lock(tp, 0);
1da177e4 9406 __tg3_set_rx_mode(dev);
f47c11ee 9407 tg3_full_unlock(tp);
1da177e4
LT		 9408}
9409
9410#define TG3_REGDUMP_LEN (32 * 1024)
9411
9412static int tg3_get_regs_len(struct net_device *dev)
9413{
9414 return TG3_REGDUMP_LEN;
9415}
9416
9417static void tg3_get_regs(struct net_device *dev,
9418 struct ethtool_regs *regs, void *_p)
9419{
9420 u32 *p = _p;
9421 struct tg3 *tp = netdev_priv(dev);
9422 u8 *orig_p = _p;
9423 int i;
9424
9425 regs->version = 0;
9426
9427 memset(p, 0, TG3_REGDUMP_LEN);
9428
bc1c7567
MC		 9429 if (tp->link_config.phy_is_low_power)
9430 return;
9431
f47c11ee 9432 tg3_full_lock(tp, 0);
1da177e4
LT		 9433
9434#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9435#define GET_REG32_LOOP(base,len) \
9436do { p = (u32 *)(orig_p + (base)); \
9437 for (i = 0; i < len; i += 4) \
9438 __GET_REG32((base) + i); \
9439} while (0)
9440#define GET_REG32_1(reg) \
9441do { p = (u32 *)(orig_p + (reg)); \
9442 __GET_REG32((reg)); \
9443} while (0)
9444
9445 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9446 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9447 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9448 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9449 GET_REG32_1(SNDDATAC_MODE);
9450 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9451 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9452 GET_REG32_1(SNDBDC_MODE);
9453 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9454 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9455 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9456 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9457 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9458 GET_REG32_1(RCVDCC_MODE);
9459 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9460 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9461 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9462 GET_REG32_1(MBFREE_MODE);
9463 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9464 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9465 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9466 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9467 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9468 GET_REG32_1(RX_CPU_MODE);
9469 GET_REG32_1(RX_CPU_STATE);
9470 GET_REG32_1(RX_CPU_PGMCTR);
9471 GET_REG32_1(RX_CPU_HWBKPT);
9472 GET_REG32_1(TX_CPU_MODE);
9473 GET_REG32_1(TX_CPU_STATE);
9474 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9475 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9476 GET_REG32_LOOP(FTQ_RESET, 0x120);
9477 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9478 GET_REG32_1(DMAC_MODE);
9479 GET_REG32_LOOP(GRC_MODE, 0x4c);
9480 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9481 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9482
9483#undef __GET_REG32
9484#undef GET_REG32_LOOP
9485#undef GET_REG32_1
9486
f47c11ee 9487 tg3_full_unlock(tp);
1da177e4
LT		 9488}
9489
9490static int tg3_get_eeprom_len(struct net_device *dev)
9491{
9492 struct tg3 *tp = netdev_priv(dev);
9493
9494 return tp->nvram_size;
9495}
9496
1da177e4
LT		 9497static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9498{
9499 struct tg3 *tp = netdev_priv(dev);
9500 int ret;
9501 u8 *pd;
b9fc7dc5 9502 u32 i, offset, len, b_offset, b_count;
a9dc529d 9503 __be32 val;
1da177e4 9504
df259d8c
MC		 9505 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9506 return -EINVAL;
9507
bc1c7567
MC		 9508 if (tp->link_config.phy_is_low_power)
9509 return -EAGAIN;
9510
1da177e4
LT		 9511 offset = eeprom->offset;
9512 len = eeprom->len;
9513 eeprom->len = 0;
9514
9515 eeprom->magic = TG3_EEPROM_MAGIC;
9516
9517 if (offset & 3) {
9518 /* adjustments to start on required 4 byte boundary */
9519 b_offset = offset & 3;
9520 b_count = 4 - b_offset;
9521 if (b_count > len) {
9522 /* i.e. offset=1 len=2 */
9523 b_count = len;
9524 }
a9dc529d 9525 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9526 if (ret)
9527 return ret;
1da177e4
LT		 9528 memcpy(data, ((char*)&val) + b_offset, b_count);
9529 len -= b_count;
9530 offset += b_count;
9531 eeprom->len += b_count;
9532 }
9533
9534 /* read bytes upto the last 4 byte boundary */
9535 pd = &data[eeprom->len];
9536 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9537 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9538 if (ret) {
9539 eeprom->len += i;
9540 return ret;
9541 }
1da177e4
LT		 9542 memcpy(pd + i, &val, 4);
9543 }
9544 eeprom->len += i;
9545
9546 if (len & 3) {
9547 /* read last bytes not ending on 4 byte boundary */
9548 pd = &data[eeprom->len];
9549 b_count = len & 3;
9550 b_offset = offset + len - b_count;
a9dc529d 9551 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9552 if (ret)
9553 return ret;
b9fc7dc5 9554 memcpy(pd, &val, b_count);
1da177e4
LT		 9555 eeprom->len += b_count;
9556 }
9557 return 0;
9558}
9559
6aa20a22 9560static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9561
9562static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9563{
9564 struct tg3 *tp = netdev_priv(dev);
9565 int ret;
b9fc7dc5 9566 u32 offset, len, b_offset, odd_len;
1da177e4 9567 u8 *buf;
a9dc529d 9568 __be32 start, end;
1da177e4 9569
bc1c7567
MC		 9570 if (tp->link_config.phy_is_low_power)
9571 return -EAGAIN;
9572
df259d8c
MC		 9573 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9574 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9575 return -EINVAL;
9576
9577 offset = eeprom->offset;
9578 len = eeprom->len;
9579
9580 if ((b_offset = (offset & 3))) {
9581 /* adjustments to start on required 4 byte boundary */
a9dc529d 9582 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9583 if (ret)
9584 return ret;
1da177e4
LT		 9585 len += b_offset;
9586 offset &= ~3;
1c8594b4
MC		 9587 if (len < 4)
9588 len = 4;
1da177e4
LT		 9589 }
9590
9591 odd_len = 0;
1c8594b4 9592 if (len & 3) {
1da177e4
LT		 9593 /* adjustments to end on required 4 byte boundary */
9594 odd_len = 1;
9595 len = (len + 3) & ~3;
a9dc529d 9596 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9597 if (ret)
9598 return ret;
1da177e4
LT		 9599 }
9600
9601 buf = data;
9602 if (b_offset || odd_len) {
9603 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9604 if (!buf)
1da177e4
LT		 9605 return -ENOMEM;
9606 if (b_offset)
9607 memcpy(buf, &start, 4);
9608 if (odd_len)
9609 memcpy(buf+len-4, &end, 4);
9610 memcpy(buf + b_offset, data, eeprom->len);
9611 }
9612
9613 ret = tg3_nvram_write_block(tp, offset, len, buf);
9614
9615 if (buf != data)
9616 kfree(buf);
9617
9618 return ret;
9619}
9620
9621static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9622{
b02fd9e3
MC		 9623 struct tg3 *tp = netdev_priv(dev);
9624
9625 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9626 struct phy_device *phydev;
b02fd9e3
MC		 9627 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9628 return -EAGAIN;
3f0e3ad7
MC		 9629 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9630 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9631 }
6aa20a22 9632
1da177e4
LT		 9633 cmd->supported = (SUPPORTED_Autoneg);
9634
9635 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9636 cmd->supported |= (SUPPORTED_1000baseT_Half |
9637 SUPPORTED_1000baseT_Full);
9638
ef348144 9639 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9640 cmd->supported |= (SUPPORTED_100baseT_Half |
9641 SUPPORTED_100baseT_Full |
9642 SUPPORTED_10baseT_Half |
9643 SUPPORTED_10baseT_Full |
3bebab59 9644 SUPPORTED_TP);
ef348144
KK		 9645 cmd->port = PORT_TP;
9646 } else {
1da177e4 9647 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9648 cmd->port = PORT_FIBRE;
9649 }
6aa20a22 9650
1da177e4
LT		 9651 cmd->advertising = tp->link_config.advertising;
9652 if (netif_running(dev)) {
9653 cmd->speed = tp->link_config.active_speed;
9654 cmd->duplex = tp->link_config.active_duplex;
9655 }
882e9793 9656 cmd->phy_address = tp->phy_addr;
7e5856bd 9657 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9658 cmd->autoneg = tp->link_config.autoneg;
9659 cmd->maxtxpkt = 0;
9660 cmd->maxrxpkt = 0;
9661 return 0;
9662}
6aa20a22 9663
1da177e4
LT		 9664static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9665{
9666 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9667
b02fd9e3 9668 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9669 struct phy_device *phydev;
b02fd9e3
MC		 9670 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9671 return -EAGAIN;
3f0e3ad7
MC		 9672 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9673 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9674 }
9675
7e5856bd
MC		 9676 if (cmd->autoneg != AUTONEG_ENABLE &&
9677 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9678 return -EINVAL;
7e5856bd
MC		 9679
9680 if (cmd->autoneg == AUTONEG_DISABLE &&
9681 cmd->duplex != DUPLEX_FULL &&
9682 cmd->duplex != DUPLEX_HALF)
37ff238d 9683 return -EINVAL;
1da177e4 9684
7e5856bd
MC		 9685 if (cmd->autoneg == AUTONEG_ENABLE) {
9686 u32 mask = ADVERTISED_Autoneg |
9687 ADVERTISED_Pause |
9688 ADVERTISED_Asym_Pause;
9689
9690 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9691 mask |= ADVERTISED_1000baseT_Half |
9692 ADVERTISED_1000baseT_Full;
9693
9694 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9695 mask |= ADVERTISED_100baseT_Half |
9696 ADVERTISED_100baseT_Full |
9697 ADVERTISED_10baseT_Half |
9698 ADVERTISED_10baseT_Full |
9699 ADVERTISED_TP;
9700 else
9701 mask |= ADVERTISED_FIBRE;
9702
9703 if (cmd->advertising & ~mask)
9704 return -EINVAL;
9705
9706 mask &= (ADVERTISED_1000baseT_Half |
9707 ADVERTISED_1000baseT_Full |
9708 ADVERTISED_100baseT_Half |
9709 ADVERTISED_100baseT_Full |
9710 ADVERTISED_10baseT_Half |
9711 ADVERTISED_10baseT_Full);
9712
9713 cmd->advertising &= mask;
9714 } else {
9715 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9716 if (cmd->speed != SPEED_1000)
9717 return -EINVAL;
9718
9719 if (cmd->duplex != DUPLEX_FULL)
9720 return -EINVAL;
9721 } else {
9722 if (cmd->speed != SPEED_100 &&
9723 cmd->speed != SPEED_10)
9724 return -EINVAL;
9725 }
9726 }
9727
f47c11ee 9728 tg3_full_lock(tp, 0);
1da177e4
LT		 9729
9730 tp->link_config.autoneg = cmd->autoneg;
9731 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9732 tp->link_config.advertising = (cmd->advertising |
9733 ADVERTISED_Autoneg);
1da177e4
LT		 9734 tp->link_config.speed = SPEED_INVALID;
9735 tp->link_config.duplex = DUPLEX_INVALID;
9736 } else {
9737 tp->link_config.advertising = 0;
9738 tp->link_config.speed = cmd->speed;
9739 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9740 }
6aa20a22 9741
24fcad6b
MC		 9742 tp->link_config.orig_speed = tp->link_config.speed;
9743 tp->link_config.orig_duplex = tp->link_config.duplex;
9744 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9745
1da177e4
LT		 9746 if (netif_running(dev))
9747 tg3_setup_phy(tp, 1);
9748
f47c11ee 9749 tg3_full_unlock(tp);
6aa20a22 9750
1da177e4
LT		 9751 return 0;
9752}
6aa20a22 9753
1da177e4
LT		 9754static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9755{
9756 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9757
1da177e4
LT		 9758 strcpy(info->driver, DRV_MODULE_NAME);
9759 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9760 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9761 strcpy(info->bus_info, pci_name(tp->pdev));
9762}
6aa20a22 9763
1da177e4
LT		 9764static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9765{
9766 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9767
12dac075
RW		 9768 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9769 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9770 wol->supported = WAKE_MAGIC;
9771 else
9772 wol->supported = 0;
1da177e4 9773 wol->wolopts = 0;
05ac4cb7
MC		 9774 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9775 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9776 wol->wolopts = WAKE_MAGIC;
9777 memset(&wol->sopass, 0, sizeof(wol->sopass));
9778}
6aa20a22 9779
1da177e4
LT		 9780static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9781{
9782 struct tg3 *tp = netdev_priv(dev);
12dac075 9783 struct device *dp = &tp->pdev->dev;
6aa20a22 9784
1da177e4
LT		 9785 if (wol->wolopts & ~WAKE_MAGIC)
9786 return -EINVAL;
9787 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9788 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9789 return -EINVAL;
6aa20a22 9790
f47c11ee 9791 spin_lock_bh(&tp->lock);
12dac075 9792 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9793 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9794 device_set_wakeup_enable(dp, true);
9795 } else {
1da177e4 9796 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9797 device_set_wakeup_enable(dp, false);
9798 }
f47c11ee 9799 spin_unlock_bh(&tp->lock);
6aa20a22 9800
1da177e4
LT		 9801 return 0;
9802}
6aa20a22 9803
1da177e4
LT		 9804static u32 tg3_get_msglevel(struct net_device *dev)
9805{
9806 struct tg3 *tp = netdev_priv(dev);
9807 return tp->msg_enable;
9808}
6aa20a22 9809
1da177e4
LT		 9810static void tg3_set_msglevel(struct net_device *dev, u32 value)
9811{
9812 struct tg3 *tp = netdev_priv(dev);
9813 tp->msg_enable = value;
9814}
6aa20a22 9815
1da177e4
LT		 9816static int tg3_set_tso(struct net_device *dev, u32 value)
9817{
9818 struct tg3 *tp = netdev_priv(dev);
9819
9820 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9821 if (value)
9822 return -EINVAL;
9823 return 0;
9824 }
027455ad 9825 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9826 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9827 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9828 if (value) {
b0026624 9829 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9830 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9831 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9832 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9833 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9836 dev->features |= NETIF_F_TSO_ECN;
9837 } else
9838 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9839 }
1da177e4
LT		 9840 return ethtool_op_set_tso(dev, value);
9841}
6aa20a22 9842
1da177e4
LT		 9843static int tg3_nway_reset(struct net_device *dev)
9844{
9845 struct tg3 *tp = netdev_priv(dev);
1da177e4 9846 int r;
6aa20a22 9847
1da177e4
LT		 9848 if (!netif_running(dev))
9849 return -EAGAIN;
9850
c94e3941
MC		 9851 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9852 return -EINVAL;
9853
b02fd9e3
MC		 9854 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9855 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9856 return -EAGAIN;
3f0e3ad7 9857 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9858 } else {
9859 u32 bmcr;
9860
9861 spin_lock_bh(&tp->lock);
9862 r = -EINVAL;
9863 tg3_readphy(tp, MII_BMCR, &bmcr);
9864 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9865 ((bmcr & BMCR_ANENABLE) ||
9866 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9867 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9868 BMCR_ANENABLE);
9869 r = 0;
9870 }
9871 spin_unlock_bh(&tp->lock);
1da177e4 9872 }
6aa20a22 9873
1da177e4
LT		 9874 return r;
9875}
6aa20a22 9876
1da177e4
LT		 9877static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9878{
9879 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9880
1da177e4
LT		 9881 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9882 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9883 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9884 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9885 else
9886 ering->rx_jumbo_max_pending = 0;
9887
9888 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9889
9890 ering->rx_pending = tp->rx_pending;
9891 ering->rx_mini_pending = 0;
4f81c32b
MC		 9892 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9893 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9894 else
9895 ering->rx_jumbo_pending = 0;
9896
f3f3f27e 9897 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9898}
6aa20a22 9899
1da177e4
LT		 9900static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9901{
9902 struct tg3 *tp = netdev_priv(dev);
646c9edd 9903 int i, irq_sync = 0, err = 0;
6aa20a22 9904
1da177e4
LT		 9905 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9906 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9907 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9908 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9909 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9910 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9911 return -EINVAL;
6aa20a22 9912
bbe832c0 9913 if (netif_running(dev)) {
b02fd9e3 9914 tg3_phy_stop(tp);
1da177e4 9915 tg3_netif_stop(tp);
bbe832c0
MC		 9916 irq_sync = 1;
9917 }
1da177e4 9918
bbe832c0 9919 tg3_full_lock(tp, irq_sync);
6aa20a22 9920
1da177e4
LT		 9921 tp->rx_pending = ering->rx_pending;
9922
9923 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9924 tp->rx_pending > 63)
9925 tp->rx_pending = 63;
9926 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9927
9928 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9929 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9930
9931 if (netif_running(dev)) {
944d980e 9932 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9933 err = tg3_restart_hw(tp, 1);
9934 if (!err)
9935 tg3_netif_start(tp);
1da177e4
LT		 9936 }
9937
f47c11ee 9938 tg3_full_unlock(tp);
6aa20a22 9939
b02fd9e3
MC		 9940 if (irq_sync && !err)
9941 tg3_phy_start(tp);
9942
b9ec6c1b 9943 return err;
1da177e4 9944}
6aa20a22 9945
1da177e4
LT		 9946static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9947{
9948 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9949
1da177e4 9950 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9951
e18ce346 9952 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9953 epause->rx_pause = 1;
9954 else
9955 epause->rx_pause = 0;
9956
e18ce346 9957 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9958 epause->tx_pause = 1;
9959 else
9960 epause->tx_pause = 0;
1da177e4 9961}
6aa20a22 9962
1da177e4
LT		 9963static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9964{
9965 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9966 int err = 0;
6aa20a22 9967
b02fd9e3
MC		 9968 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9969 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9970 return -EAGAIN;
1da177e4 9971
b02fd9e3
MC		 9972 if (epause->autoneg) {
9973 u32 newadv;
9974 struct phy_device *phydev;
f47c11ee 9975
3f0e3ad7 9976 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9977
b02fd9e3
MC		 9978 if (epause->rx_pause) {
9979 if (epause->tx_pause)
9980 newadv = ADVERTISED_Pause;
9981 else
9982 newadv = ADVERTISED_Pause |
9983 ADVERTISED_Asym_Pause;
9984 } else if (epause->tx_pause) {
9985 newadv = ADVERTISED_Asym_Pause;
9986 } else
9987 newadv = 0;
9988
9989 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9990 u32 oldadv = phydev->advertising &
9991 (ADVERTISED_Pause |
9992 ADVERTISED_Asym_Pause);
9993 if (oldadv != newadv) {
9994 phydev->advertising &=
9995 ~(ADVERTISED_Pause |
9996 ADVERTISED_Asym_Pause);
9997 phydev->advertising |= newadv;
9998 err = phy_start_aneg(phydev);
9999 }
10000 } else {
10001 tp->link_config.advertising &=
10002 ~(ADVERTISED_Pause |
10003 ADVERTISED_Asym_Pause);
10004 tp->link_config.advertising |= newadv;
10005 }
10006 } else {
10007 if (epause->rx_pause)
e18ce346 10008 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10009 else
e18ce346 10010 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 10011
b02fd9e3 10012 if (epause->tx_pause)
e18ce346 10013 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10014 else
e18ce346 10015 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10016
10017 if (netif_running(dev))
10018 tg3_setup_flow_control(tp, 0, 0);
10019 }
10020 } else {
10021 int irq_sync = 0;
10022
10023 if (netif_running(dev)) {
10024 tg3_netif_stop(tp);
10025 irq_sync = 1;
10026 }
10027
10028 tg3_full_lock(tp, irq_sync);
10029
10030 if (epause->autoneg)
10031 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10032 else
10033 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10034 if (epause->rx_pause)
e18ce346 10035 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 10036 else
e18ce346 10037 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 10038 if (epause->tx_pause)
e18ce346 10039 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 10040 else
e18ce346 10041 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 10042
10043 if (netif_running(dev)) {
10044 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10045 err = tg3_restart_hw(tp, 1);
10046 if (!err)
10047 tg3_netif_start(tp);
10048 }
10049
10050 tg3_full_unlock(tp);
10051 }
6aa20a22 10052
b9ec6c1b 10053 return err;
1da177e4 10054}
6aa20a22 10055
1da177e4
LT		 10056static u32 tg3_get_rx_csum(struct net_device *dev)
10057{
10058 struct tg3 *tp = netdev_priv(dev);
10059 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10060}
6aa20a22 10061
1da177e4
LT		 10062static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10063{
10064 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10065
1da177e4
LT		 10066 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10067 if (data != 0)
10068 return -EINVAL;
10069 return 0;
10070 }
6aa20a22 10071
f47c11ee 10072 spin_lock_bh(&tp->lock);
1da177e4
LT		 10073 if (data)
10074 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10075 else
10076 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 10077 spin_unlock_bh(&tp->lock);
6aa20a22 10078
1da177e4
LT		 10079 return 0;
10080}
6aa20a22 10081
1da177e4
LT		 10082static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10083{
10084 struct tg3 *tp = netdev_priv(dev);
6aa20a22 10085
1da177e4
LT		 10086 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10087 if (data != 0)
10088 return -EINVAL;
10089 return 0;
10090 }
6aa20a22 10091
321d32a0 10092 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 10093 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 10094 else
9c27dbdf 10095 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 10096
10097 return 0;
10098}
10099
b9f2c044 10100static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 10101{
b9f2c044
JG		 10102 switch (sset) {
10103 case ETH_SS_TEST:
10104 return TG3_NUM_TEST;
10105 case ETH_SS_STATS:
10106 return TG3_NUM_STATS;
10107 default:
10108 return -EOPNOTSUPP;
10109 }
4cafd3f5
MC		 10110}
10111
1da177e4
LT		 10112static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10113{
10114 switch (stringset) {
10115 case ETH_SS_STATS:
10116 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10117 break;
4cafd3f5
MC		 10118 case ETH_SS_TEST:
10119 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10120 break;
1da177e4
LT		 10121 default:
10122 WARN_ON(1); /* we need a WARN() */
10123 break;
10124 }
10125}
10126
4009a93d
MC		 10127static int tg3_phys_id(struct net_device *dev, u32 data)
10128{
10129 struct tg3 *tp = netdev_priv(dev);
10130 int i;
10131
10132 if (!netif_running(tp->dev))
10133 return -EAGAIN;
10134
10135 if (data == 0)
759afc31 10136 data = UINT_MAX / 2;
4009a93d
MC		 10137
10138 for (i = 0; i < (data * 2); i++) {
10139 if ((i % 2) == 0)
10140 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10141 LED_CTRL_1000MBPS_ON |
10142 LED_CTRL_100MBPS_ON |
10143 LED_CTRL_10MBPS_ON |
10144 LED_CTRL_TRAFFIC_OVERRIDE |
10145 LED_CTRL_TRAFFIC_BLINK |
10146 LED_CTRL_TRAFFIC_LED);
6aa20a22 10147
4009a93d
MC		 10148 else
10149 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10150 LED_CTRL_TRAFFIC_OVERRIDE);
10151
10152 if (msleep_interruptible(500))
10153 break;
10154 }
10155 tw32(MAC_LED_CTRL, tp->led_ctrl);
10156 return 0;
10157}
10158
1da177e4
LT		 10159static void tg3_get_ethtool_stats (struct net_device *dev,
10160 struct ethtool_stats *estats, u64 *tmp_stats)
10161{
10162 struct tg3 *tp = netdev_priv(dev);
10163 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10164}
10165
566f86ad 10166#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 10167#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10168#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10169#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 10170#define NVRAM_SELFBOOT_HW_SIZE 0x20
10171#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 10172
10173static int tg3_test_nvram(struct tg3 *tp)
10174{
b9fc7dc5 10175 u32 csum, magic;
a9dc529d 10176 __be32 *buf;
ab0049b4 10177 int i, j, k, err = 0, size;
566f86ad 10178
df259d8c
MC		 10179 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10180 return 0;
10181
e4f34110 10182 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 10183 return -EIO;
10184
1b27777a
MC		 10185 if (magic == TG3_EEPROM_MAGIC)
10186 size = NVRAM_TEST_SIZE;
b16250e3 10187 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 10188 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10189 TG3_EEPROM_SB_FORMAT_1) {
10190 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10191 case TG3_EEPROM_SB_REVISION_0:
10192 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10193 break;
10194 case TG3_EEPROM_SB_REVISION_2:
10195 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10196 break;
10197 case TG3_EEPROM_SB_REVISION_3:
10198 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10199 break;
10200 default:
10201 return 0;
10202 }
10203 } else
1b27777a 10204 return 0;
b16250e3
MC		 10205 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10206 size = NVRAM_SELFBOOT_HW_SIZE;
10207 else
1b27777a
MC		 10208 return -EIO;
10209
10210 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 10211 if (buf == NULL)
10212 return -ENOMEM;
10213
1b27777a
MC		 10214 err = -EIO;
10215 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 10216 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10217 if (err)
566f86ad 10218 break;
566f86ad 10219 }
1b27777a 10220 if (i < size)
566f86ad
MC		 10221 goto out;
10222
1b27777a 10223 /* Selfboot format */
a9dc529d 10224 magic = be32_to_cpu(buf[0]);
b9fc7dc5 10225 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 10226 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 10227 u8 *buf8 = (u8 *) buf, csum8 = 0;
10228
b9fc7dc5 10229 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 10230 TG3_EEPROM_SB_REVISION_2) {
10231 /* For rev 2, the csum doesn't include the MBA. */
10232 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10233 csum8 += buf8[i];
10234 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10235 csum8 += buf8[i];
10236 } else {
10237 for (i = 0; i < size; i++)
10238 csum8 += buf8[i];
10239 }
1b27777a 10240
ad96b485
AB		 10241 if (csum8 == 0) {
10242 err = 0;
10243 goto out;
10244 }
10245
10246 err = -EIO;
10247 goto out;
1b27777a 10248 }
566f86ad 10249
b9fc7dc5 10250 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10251 TG3_EEPROM_MAGIC_HW) {
10252 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10253 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10254 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10255
10256 /* Separate the parity bits and the data bytes. */
10257 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10258 if ((i == 0) || (i == 8)) {
10259 int l;
10260 u8 msk;
10261
10262 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10263 parity[k++] = buf8[i] & msk;
10264 i++;
10265 }
10266 else if (i == 16) {
10267 int l;
10268 u8 msk;
10269
10270 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10271 parity[k++] = buf8[i] & msk;
10272 i++;
10273
10274 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10275 parity[k++] = buf8[i] & msk;
10276 i++;
10277 }
10278 data[j++] = buf8[i];
10279 }
10280
10281 err = -EIO;
10282 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10283 u8 hw8 = hweight8(data[i]);
10284
10285 if ((hw8 & 0x1) && parity[i])
10286 goto out;
10287 else if (!(hw8 & 0x1) && !parity[i])
10288 goto out;
10289 }
10290 err = 0;
10291 goto out;
10292 }
10293
566f86ad
MC		 10294 /* Bootstrap checksum at offset 0x10 */
10295 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10296 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10297 goto out;
10298
10299 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10300 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10301 if (csum != be32_to_cpu(buf[0xfc/4]))
10302 goto out;
566f86ad
MC		 10303
10304 err = 0;
10305
10306out:
10307 kfree(buf);
10308 return err;
10309}
10310
ca43007a
MC		 10311#define TG3_SERDES_TIMEOUT_SEC 2
10312#define TG3_COPPER_TIMEOUT_SEC 6
10313
10314static int tg3_test_link(struct tg3 *tp)
10315{
10316 int i, max;
10317
10318 if (!netif_running(tp->dev))
10319 return -ENODEV;
10320
4c987487 10321 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10322 max = TG3_SERDES_TIMEOUT_SEC;
10323 else
10324 max = TG3_COPPER_TIMEOUT_SEC;
10325
10326 for (i = 0; i < max; i++) {
10327 if (netif_carrier_ok(tp->dev))
10328 return 0;
10329
10330 if (msleep_interruptible(1000))
10331 break;
10332 }
10333
10334 return -EIO;
10335}
10336
a71116d1 10337/* Only test the commonly used registers */
30ca3e37 10338static int tg3_test_registers(struct tg3 *tp)
a71116d1 10339{
b16250e3 10340 int i, is_5705, is_5750;
a71116d1
MC		 10341 u32 offset, read_mask, write_mask, val, save_val, read_val;
10342 static struct {
10343 u16 offset;
10344 u16 flags;
10345#define TG3_FL_5705 0x1
10346#define TG3_FL_NOT_5705 0x2
10347#define TG3_FL_NOT_5788 0x4
b16250e3 10348#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10349 u32 read_mask;
10350 u32 write_mask;
10351 } reg_tbl[] = {
10352 /* MAC Control Registers */
10353 { MAC_MODE, TG3_FL_NOT_5705,
10354 0x00000000, 0x00ef6f8c },
10355 { MAC_MODE, TG3_FL_5705,
10356 0x00000000, 0x01ef6b8c },
10357 { MAC_STATUS, TG3_FL_NOT_5705,
10358 0x03800107, 0x00000000 },
10359 { MAC_STATUS, TG3_FL_5705,
10360 0x03800100, 0x00000000 },
10361 { MAC_ADDR_0_HIGH, 0x0000,
10362 0x00000000, 0x0000ffff },
10363 { MAC_ADDR_0_LOW, 0x0000,
10364 0x00000000, 0xffffffff },
10365 { MAC_RX_MTU_SIZE, 0x0000,
10366 0x00000000, 0x0000ffff },
10367 { MAC_TX_MODE, 0x0000,
10368 0x00000000, 0x00000070 },
10369 { MAC_TX_LENGTHS, 0x0000,
10370 0x00000000, 0x00003fff },
10371 { MAC_RX_MODE, TG3_FL_NOT_5705,
10372 0x00000000, 0x000007fc },
10373 { MAC_RX_MODE, TG3_FL_5705,
10374 0x00000000, 0x000007dc },
10375 { MAC_HASH_REG_0, 0x0000,
10376 0x00000000, 0xffffffff },
10377 { MAC_HASH_REG_1, 0x0000,
10378 0x00000000, 0xffffffff },
10379 { MAC_HASH_REG_2, 0x0000,
10380 0x00000000, 0xffffffff },
10381 { MAC_HASH_REG_3, 0x0000,
10382 0x00000000, 0xffffffff },
10383
10384 /* Receive Data and Receive BD Initiator Control Registers. */
10385 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10386 0x00000000, 0xffffffff },
10387 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10388 0x00000000, 0xffffffff },
10389 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10390 0x00000000, 0x00000003 },
10391 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10392 0x00000000, 0xffffffff },
10393 { RCVDBDI_STD_BD+0, 0x0000,
10394 0x00000000, 0xffffffff },
10395 { RCVDBDI_STD_BD+4, 0x0000,
10396 0x00000000, 0xffffffff },
10397 { RCVDBDI_STD_BD+8, 0x0000,
10398 0x00000000, 0xffff0002 },
10399 { RCVDBDI_STD_BD+0xc, 0x0000,
10400 0x00000000, 0xffffffff },
6aa20a22 10401
a71116d1
MC		 10402 /* Receive BD Initiator Control Registers. */
10403 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10404 0x00000000, 0xffffffff },
10405 { RCVBDI_STD_THRESH, TG3_FL_5705,
10406 0x00000000, 0x000003ff },
10407 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10408 0x00000000, 0xffffffff },
6aa20a22 10409
a71116d1
MC		 10410 /* Host Coalescing Control Registers. */
10411 { HOSTCC_MODE, TG3_FL_NOT_5705,
10412 0x00000000, 0x00000004 },
10413 { HOSTCC_MODE, TG3_FL_5705,
10414 0x00000000, 0x000000f6 },
10415 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10416 0x00000000, 0xffffffff },
10417 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10418 0x00000000, 0x000003ff },
10419 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10420 0x00000000, 0xffffffff },
10421 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10422 0x00000000, 0x000003ff },
10423 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10424 0x00000000, 0xffffffff },
10425 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10426 0x00000000, 0x000000ff },
10427 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10428 0x00000000, 0xffffffff },
10429 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10430 0x00000000, 0x000000ff },
10431 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10432 0x00000000, 0xffffffff },
10433 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10434 0x00000000, 0xffffffff },
10435 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10436 0x00000000, 0xffffffff },
10437 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10438 0x00000000, 0x000000ff },
10439 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10440 0x00000000, 0xffffffff },
10441 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10442 0x00000000, 0x000000ff },
10443 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10444 0x00000000, 0xffffffff },
10445 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10446 0x00000000, 0xffffffff },
10447 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10448 0x00000000, 0xffffffff },
10449 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10450 0x00000000, 0xffffffff },
10451 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10452 0x00000000, 0xffffffff },
10453 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10454 0xffffffff, 0x00000000 },
10455 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10456 0xffffffff, 0x00000000 },
10457
10458 /* Buffer Manager Control Registers. */
b16250e3 10459 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10460 0x00000000, 0x007fff80 },
b16250e3 10461 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10462 0x00000000, 0x007fffff },
10463 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10464 0x00000000, 0x0000003f },
10465 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10466 0x00000000, 0x000001ff },
10467 { BUFMGR_MB_HIGH_WATER, 0x0000,
10468 0x00000000, 0x000001ff },
10469 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10470 0xffffffff, 0x00000000 },
10471 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10472 0xffffffff, 0x00000000 },
6aa20a22 10473
a71116d1
MC		 10474 /* Mailbox Registers */
10475 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10476 0x00000000, 0x000001ff },
10477 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10478 0x00000000, 0x000001ff },
10479 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10480 0x00000000, 0x000007ff },
10481 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10482 0x00000000, 0x000001ff },
10483
10484 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10485 };
10486
b16250e3
MC		 10487 is_5705 = is_5750 = 0;
10488 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10489 is_5705 = 1;
b16250e3
MC		 10490 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10491 is_5750 = 1;
10492 }
a71116d1
MC		 10493
10494 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10495 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10496 continue;
10497
10498 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10499 continue;
10500
10501 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10502 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10503 continue;
10504
b16250e3
MC		 10505 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10506 continue;
10507
a71116d1
MC		 10508 offset = (u32) reg_tbl[i].offset;
10509 read_mask = reg_tbl[i].read_mask;
10510 write_mask = reg_tbl[i].write_mask;
10511
10512 /* Save the original register content */
10513 save_val = tr32(offset);
10514
10515 /* Determine the read-only value. */
10516 read_val = save_val & read_mask;
10517
10518 /* Write zero to the register, then make sure the read-only bits
10519 * are not changed and the read/write bits are all zeros.
10520 */
10521 tw32(offset, 0);
10522
10523 val = tr32(offset);
10524
10525 /* Test the read-only and read/write bits. */
10526 if (((val & read_mask) != read_val) || (val & write_mask))
10527 goto out;
10528
10529 /* Write ones to all the bits defined by RdMask and WrMask, then
10530 * make sure the read-only bits are not changed and the
10531 * read/write bits are all ones.
10532 */
10533 tw32(offset, read_mask | write_mask);
10534
10535 val = tr32(offset);
10536
10537 /* Test the read-only bits. */
10538 if ((val & read_mask) != read_val)
10539 goto out;
10540
10541 /* Test the read/write bits. */
10542 if ((val & write_mask) != write_mask)
10543 goto out;
10544
10545 tw32(offset, save_val);
10546 }
10547
10548 return 0;
10549
10550out:
9f88f29f
MC		 10551 if (netif_msg_hw(tp))
10552 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10553 offset);
a71116d1
MC		 10554 tw32(offset, save_val);
10555 return -EIO;
10556}
10557
7942e1db
MC		 10558static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10559{
f71e1309 10560 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10561 int i;
10562 u32 j;
10563
e9edda69 10564 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10565 for (j = 0; j < len; j += 4) {
10566 u32 val;
10567
10568 tg3_write_mem(tp, offset + j, test_pattern[i]);
10569 tg3_read_mem(tp, offset + j, &val);
10570 if (val != test_pattern[i])
10571 return -EIO;
10572 }
10573 }
10574 return 0;
10575}
10576
10577static int tg3_test_memory(struct tg3 *tp)
10578{
10579 static struct mem_entry {
10580 u32 offset;
10581 u32 len;
10582 } mem_tbl_570x[] = {
38690194 10583 { 0x00000000, 0x00b50},
7942e1db
MC		 10584 { 0x00002000, 0x1c000},
10585 { 0xffffffff, 0x00000}
10586 }, mem_tbl_5705[] = {
10587 { 0x00000100, 0x0000c},
10588 { 0x00000200, 0x00008},
7942e1db
MC		 10589 { 0x00004000, 0x00800},
10590 { 0x00006000, 0x01000},
10591 { 0x00008000, 0x02000},
10592 { 0x00010000, 0x0e000},
10593 { 0xffffffff, 0x00000}
79f4d13a
MC		 10594 }, mem_tbl_5755[] = {
10595 { 0x00000200, 0x00008},
10596 { 0x00004000, 0x00800},
10597 { 0x00006000, 0x00800},
10598 { 0x00008000, 0x02000},
10599 { 0x00010000, 0x0c000},
10600 { 0xffffffff, 0x00000}
b16250e3
MC		 10601 }, mem_tbl_5906[] = {
10602 { 0x00000200, 0x00008},
10603 { 0x00004000, 0x00400},
10604 { 0x00006000, 0x00400},
10605 { 0x00008000, 0x01000},
10606 { 0x00010000, 0x01000},
10607 { 0xffffffff, 0x00000}
7942e1db
MC		 10608 };
10609 struct mem_entry *mem_tbl;
10610 int err = 0;
10611 int i;
10612
321d32a0
MC		 10613 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10614 mem_tbl = mem_tbl_5755;
10615 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10616 mem_tbl = mem_tbl_5906;
10617 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10618 mem_tbl = mem_tbl_5705;
10619 else
7942e1db
MC		 10620 mem_tbl = mem_tbl_570x;
10621
10622 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10623 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10624 mem_tbl[i].len)) != 0)
10625 break;
10626 }
6aa20a22 10627
7942e1db
MC		 10628 return err;
10629}
10630
9f40dead
MC		 10631#define TG3_MAC_LOOPBACK 0
10632#define TG3_PHY_LOOPBACK 1
10633
10634static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10635{
9f40dead 10636 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10637 u32 desc_idx, coal_now;
c76949a6
MC		 10638 struct sk_buff *skb, *rx_skb;
10639 u8 *tx_data;
10640 dma_addr_t map;
10641 int num_pkts, tx_len, rx_len, i, err;
10642 struct tg3_rx_buffer_desc *desc;
898a56f8 10643 struct tg3_napi *tnapi, *rnapi;
21f581a5 10644 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10645
0c1d0e2b
MC		 10646 if (tp->irq_cnt > 1) {
10647 tnapi = &tp->napi[1];
10648 rnapi = &tp->napi[1];
10649 } else {
10650 tnapi = &tp->napi[0];
10651 rnapi = &tp->napi[0];
10652 }
fd2ce37f 10653 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10654
9f40dead 10655 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10656 /* HW errata - mac loopback fails in some cases on 5780.
10657 * Normal traffic and PHY loopback are not affected by
10658 * errata.
10659 */
10660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10661 return 0;
10662
9f40dead 10663 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10664 MAC_MODE_PORT_INT_LPBACK;
10665 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10666 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10667 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10668 mac_mode |= MAC_MODE_PORT_MODE_MII;
10669 else
10670 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10671 tw32(MAC_MODE, mac_mode);
10672 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10673 u32 val;
10674
7f97a4bd
MC		 10675 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10676 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10677 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10678 } else
10679 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10680
9ef8ca99
MC		 10681 tg3_phy_toggle_automdix(tp, 0);
10682
3f7045c1 10683 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10684 udelay(40);
5d64ad34 10685
e8f3f6ca 10686 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10687 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10689 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10690 mac_mode |= MAC_MODE_PORT_MODE_MII;
10691 } else
10692 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10693
c94e3941
MC		 10694 /* reset to prevent losing 1st rx packet intermittently */
10695 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10696 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10697 udelay(10);
10698 tw32_f(MAC_RX_MODE, tp->rx_mode);
10699 }
e8f3f6ca
MC		 10700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10701 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10702 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10703 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10704 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10705 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10706 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10707 }
9f40dead 10708 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10709 }
10710 else
10711 return -EINVAL;
c76949a6
MC		 10712
10713 err = -EIO;
10714
c76949a6 10715 tx_len = 1514;
a20e9c62 10716 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10717 if (!skb)
10718 return -ENOMEM;
10719
c76949a6
MC		 10720 tx_data = skb_put(skb, tx_len);
10721 memcpy(tx_data, tp->dev->dev_addr, 6);
10722 memset(tx_data + 6, 0x0, 8);
10723
10724 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10725
10726 for (i = 14; i < tx_len; i++)
10727 tx_data[i] = (u8) (i & 0xff);
10728
f4188d8a
AD		 10729 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10730 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 10731 dev_kfree_skb(skb);
10732 return -EIO;
10733 }
c76949a6
MC		 10734
10735 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10736 rnapi->coal_now);
c76949a6
MC		 10737
10738 udelay(10);
10739
898a56f8 10740 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10741
c76949a6
MC		 10742 num_pkts = 0;
10743
f4188d8a 10744 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
c76949a6 10745
f3f3f27e 10746 tnapi->tx_prod++;
c76949a6
MC		 10747 num_pkts++;
10748
f3f3f27e
MC		 10749 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10750 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10751
10752 udelay(10);
10753
303fc921
MC		 10754 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10755 for (i = 0; i < 35; i++) {
c76949a6 10756 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10757 coal_now);
c76949a6
MC		 10758
10759 udelay(10);
10760
898a56f8
MC		 10761 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10762 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10763 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10764 (rx_idx == (rx_start_idx + num_pkts)))
10765 break;
10766 }
10767
f4188d8a 10768 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
c76949a6
MC		 10769 dev_kfree_skb(skb);
10770
f3f3f27e 10771 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10772 goto out;
10773
10774 if (rx_idx != rx_start_idx + num_pkts)
10775 goto out;
10776
72334482 10777 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10778 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10779 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10780 if (opaque_key != RXD_OPAQUE_RING_STD)
10781 goto out;
10782
10783 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10784 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10785 goto out;
10786
10787 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10788 if (rx_len != tx_len)
10789 goto out;
10790
21f581a5 10791 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10792
21f581a5 10793 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10794 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10795
10796 for (i = 14; i < tx_len; i++) {
10797 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10798 goto out;
10799 }
10800 err = 0;
6aa20a22 10801
c76949a6
MC		 10802 /* tg3_free_rings will unmap and free the rx_skb */
10803out:
10804 return err;
10805}
10806
9f40dead
MC		 10807#define TG3_MAC_LOOPBACK_FAILED 1
10808#define TG3_PHY_LOOPBACK_FAILED 2
10809#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10810 TG3_PHY_LOOPBACK_FAILED)
10811
10812static int tg3_test_loopback(struct tg3 *tp)
10813{
10814 int err = 0;
9936bcf6 10815 u32 cpmuctrl = 0;
9f40dead
MC		 10816
10817 if (!netif_running(tp->dev))
10818 return TG3_LOOPBACK_FAILED;
10819
b9ec6c1b
MC		 10820 err = tg3_reset_hw(tp, 1);
10821 if (err)
10822 return TG3_LOOPBACK_FAILED;
9f40dead 10823
6833c043
MC		 10824 /* Turn off gphy autopowerdown. */
10825 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10826 tg3_phy_toggle_apd(tp, false);
10827
321d32a0 10828 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10829 int i;
10830 u32 status;
10831
10832 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10833
10834 /* Wait for up to 40 microseconds to acquire lock. */
10835 for (i = 0; i < 4; i++) {
10836 status = tr32(TG3_CPMU_MUTEX_GNT);
10837 if (status == CPMU_MUTEX_GNT_DRIVER)
10838 break;
10839 udelay(10);
10840 }
10841
10842 if (status != CPMU_MUTEX_GNT_DRIVER)
10843 return TG3_LOOPBACK_FAILED;
10844
b2a5c19c 10845 /* Turn off link-based power management. */
e875093c 10846 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10847 tw32(TG3_CPMU_CTRL,
10848 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10849 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10850 }
10851
9f40dead
MC		 10852 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10853 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10854
321d32a0 10855 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10856 tw32(TG3_CPMU_CTRL, cpmuctrl);
10857
10858 /* Release the mutex */
10859 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10860 }
10861
dd477003
MC		 10862 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10863 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10864 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10865 err |= TG3_PHY_LOOPBACK_FAILED;
10866 }
10867
6833c043
MC		 10868 /* Re-enable gphy autopowerdown. */
10869 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10870 tg3_phy_toggle_apd(tp, true);
10871
9f40dead
MC		 10872 return err;
10873}
10874
4cafd3f5
MC		 10875static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10876 u64 *data)
10877{
566f86ad
MC		 10878 struct tg3 *tp = netdev_priv(dev);
10879
bc1c7567
MC		 10880 if (tp->link_config.phy_is_low_power)
10881 tg3_set_power_state(tp, PCI_D0);
10882
566f86ad
MC		 10883 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10884
10885 if (tg3_test_nvram(tp) != 0) {
10886 etest->flags |= ETH_TEST_FL_FAILED;
10887 data[0] = 1;
10888 }
ca43007a
MC		 10889 if (tg3_test_link(tp) != 0) {
10890 etest->flags |= ETH_TEST_FL_FAILED;
10891 data[1] = 1;
10892 }
a71116d1 10893 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10894 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10895
10896 if (netif_running(dev)) {
b02fd9e3 10897 tg3_phy_stop(tp);
a71116d1 10898 tg3_netif_stop(tp);
bbe832c0
MC		 10899 irq_sync = 1;
10900 }
a71116d1 10901
bbe832c0 10902 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10903
10904 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10905 err = tg3_nvram_lock(tp);
a71116d1
MC		 10906 tg3_halt_cpu(tp, RX_CPU_BASE);
10907 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10908 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10909 if (!err)
10910 tg3_nvram_unlock(tp);
a71116d1 10911
d9ab5ad1
MC		 10912 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10913 tg3_phy_reset(tp);
10914
a71116d1
MC		 10915 if (tg3_test_registers(tp) != 0) {
10916 etest->flags |= ETH_TEST_FL_FAILED;
10917 data[2] = 1;
10918 }
7942e1db
MC		 10919 if (tg3_test_memory(tp) != 0) {
10920 etest->flags |= ETH_TEST_FL_FAILED;
10921 data[3] = 1;
10922 }
9f40dead 10923 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10924 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10925
f47c11ee
DM		 10926 tg3_full_unlock(tp);
10927
d4bc3927
MC		 10928 if (tg3_test_interrupt(tp) != 0) {
10929 etest->flags |= ETH_TEST_FL_FAILED;
10930 data[5] = 1;
10931 }
f47c11ee
DM		 10932
10933 tg3_full_lock(tp, 0);
d4bc3927 10934
a71116d1
MC		 10935 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10936 if (netif_running(dev)) {
10937 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10938 err2 = tg3_restart_hw(tp, 1);
10939 if (!err2)
b9ec6c1b 10940 tg3_netif_start(tp);
a71116d1 10941 }
f47c11ee
DM		 10942
10943 tg3_full_unlock(tp);
b02fd9e3
MC		 10944
10945 if (irq_sync && !err2)
10946 tg3_phy_start(tp);
a71116d1 10947 }
bc1c7567
MC		 10948 if (tp->link_config.phy_is_low_power)
10949 tg3_set_power_state(tp, PCI_D3hot);
10950
4cafd3f5
MC		 10951}
10952
1da177e4
LT		 10953static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10954{
10955 struct mii_ioctl_data *data = if_mii(ifr);
10956 struct tg3 *tp = netdev_priv(dev);
10957 int err;
10958
b02fd9e3 10959 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10960 struct phy_device *phydev;
b02fd9e3
MC		 10961 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10962 return -EAGAIN;
3f0e3ad7
MC		 10963 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10964 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10965 }
10966
1da177e4
LT		 10967 switch(cmd) {
10968 case SIOCGMIIPHY:
882e9793 10969 data->phy_id = tp->phy_addr;
1da177e4
LT		 10970
10971 /* fallthru */
10972 case SIOCGMIIREG: {
10973 u32 mii_regval;
10974
10975 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10976 break; /* We have no PHY */
10977
bc1c7567
MC		 10978 if (tp->link_config.phy_is_low_power)
10979 return -EAGAIN;
10980
f47c11ee 10981 spin_lock_bh(&tp->lock);
1da177e4 10982 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10983 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10984
10985 data->val_out = mii_regval;
10986
10987 return err;
10988 }
10989
10990 case SIOCSMIIREG:
10991 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10992 break; /* We have no PHY */
10993
bc1c7567
MC		 10994 if (tp->link_config.phy_is_low_power)
10995 return -EAGAIN;
10996
f47c11ee 10997 spin_lock_bh(&tp->lock);
1da177e4 10998 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10999 spin_unlock_bh(&tp->lock);
1da177e4
LT		 11000
11001 return err;
11002
11003 default:
11004 /* do nothing */
11005 break;
11006 }
11007 return -EOPNOTSUPP;
11008}
11009
11010#if TG3_VLAN_TAG_USED
11011static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11012{
11013 struct tg3 *tp = netdev_priv(dev);
11014
844b3eed
MC		 11015 if (!netif_running(dev)) {
11016 tp->vlgrp = grp;
11017 return;
11018 }
11019
11020 tg3_netif_stop(tp);
29315e87 11021
f47c11ee 11022 tg3_full_lock(tp, 0);
1da177e4
LT		 11023
11024 tp->vlgrp = grp;
11025
11026 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11027 __tg3_set_rx_mode(dev);
11028
844b3eed 11029 tg3_netif_start(tp);
46966545
MC		 11030
11031 tg3_full_unlock(tp);
1da177e4 11032}
1da177e4
LT		 11033#endif
11034
15f9850d
DM		 11035static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11036{
11037 struct tg3 *tp = netdev_priv(dev);
11038
11039 memcpy(ec, &tp->coal, sizeof(*ec));
11040 return 0;
11041}
11042
d244c892
MC		 11043static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11044{
11045 struct tg3 *tp = netdev_priv(dev);
11046 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11047 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11048
11049 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11050 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11051 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11052 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11053 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11054 }
11055
11056 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11057 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11058 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11059 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11060 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11061 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11062 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11063 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11064 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11065 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11066 return -EINVAL;
11067
11068 /* No rx interrupts will be generated if both are zero */
11069 if ((ec->rx_coalesce_usecs == 0) &&
11070 (ec->rx_max_coalesced_frames == 0))
11071 return -EINVAL;
11072
11073 /* No tx interrupts will be generated if both are zero */
11074 if ((ec->tx_coalesce_usecs == 0) &&
11075 (ec->tx_max_coalesced_frames == 0))
11076 return -EINVAL;
11077
11078 /* Only copy relevant parameters, ignore all others. */
11079 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11080 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11081 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11082 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11083 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11084 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11085 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11086 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11087 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11088
11089 if (netif_running(dev)) {
11090 tg3_full_lock(tp, 0);
11091 __tg3_set_coalesce(tp, &tp->coal);
11092 tg3_full_unlock(tp);
11093 }
11094 return 0;
11095}
11096
7282d491 11097static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 11098 .get_settings = tg3_get_settings,
11099 .set_settings = tg3_set_settings,
11100 .get_drvinfo = tg3_get_drvinfo,
11101 .get_regs_len = tg3_get_regs_len,
11102 .get_regs = tg3_get_regs,
11103 .get_wol = tg3_get_wol,
11104 .set_wol = tg3_set_wol,
11105 .get_msglevel = tg3_get_msglevel,
11106 .set_msglevel = tg3_set_msglevel,
11107 .nway_reset = tg3_nway_reset,
11108 .get_link = ethtool_op_get_link,
11109 .get_eeprom_len = tg3_get_eeprom_len,
11110 .get_eeprom = tg3_get_eeprom,
11111 .set_eeprom = tg3_set_eeprom,
11112 .get_ringparam = tg3_get_ringparam,
11113 .set_ringparam = tg3_set_ringparam,
11114 .get_pauseparam = tg3_get_pauseparam,
11115 .set_pauseparam = tg3_set_pauseparam,
11116 .get_rx_csum = tg3_get_rx_csum,
11117 .set_rx_csum = tg3_set_rx_csum,
1da177e4 11118 .set_tx_csum = tg3_set_tx_csum,
1da177e4 11119 .set_sg = ethtool_op_set_sg,
1da177e4 11120 .set_tso = tg3_set_tso,
4cafd3f5 11121 .self_test = tg3_self_test,
1da177e4 11122 .get_strings = tg3_get_strings,
4009a93d 11123 .phys_id = tg3_phys_id,
1da177e4 11124 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 11125 .get_coalesce = tg3_get_coalesce,
d244c892 11126 .set_coalesce = tg3_set_coalesce,
b9f2c044 11127 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 11128};
11129
11130static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11131{
1b27777a 11132 u32 cursize, val, magic;
1da177e4
LT		 11133
11134 tp->nvram_size = EEPROM_CHIP_SIZE;
11135
e4f34110 11136 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 11137 return;
11138
b16250e3
MC		 11139 if ((magic != TG3_EEPROM_MAGIC) &&
11140 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11141 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 11142 return;
11143
11144 /*
11145 * Size the chip by reading offsets at increasing powers of two.
11146 * When we encounter our validation signature, we know the addressing
11147 * has wrapped around, and thus have our chip size.
11148 */
1b27777a 11149 cursize = 0x10;
1da177e4
LT		 11150
11151 while (cursize < tp->nvram_size) {
e4f34110 11152 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 11153 return;
11154
1820180b 11155 if (val == magic)
1da177e4
LT		 11156 break;
11157
11158 cursize <<= 1;
11159 }
11160
11161 tp->nvram_size = cursize;
11162}
6aa20a22 11163
1da177e4
LT		 11164static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11165{
11166 u32 val;
11167
df259d8c
MC		 11168 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11169 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 11170 return;
11171
11172 /* Selfboot format */
1820180b 11173 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 11174 tg3_get_eeprom_size(tp);
11175 return;
11176 }
11177
6d348f2c 11178 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 11179 if (val != 0) {
6d348f2c
MC		 11180 /* This is confusing. We want to operate on the
11181 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11182 * call will read from NVRAM and byteswap the data
11183 * according to the byteswapping settings for all
11184 * other register accesses. This ensures the data we
11185 * want will always reside in the lower 16-bits.
11186 * However, the data in NVRAM is in LE format, which
11187 * means the data from the NVRAM read will always be
11188 * opposite the endianness of the CPU. The 16-bit
11189 * byteswap then brings the data to CPU endianness.
11190 */
11191 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 11192 return;
11193 }
11194 }
fd1122a2 11195 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 11196}
11197
11198static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11199{
11200 u32 nvcfg1;
11201
11202 nvcfg1 = tr32(NVRAM_CFG1);
11203 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11204 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 11205 } else {
1da177e4
LT		 11206 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11207 tw32(NVRAM_CFG1, nvcfg1);
11208 }
11209
4c987487 11210 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 11211 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 11212 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 11213 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11214 tp->nvram_jedecnum = JEDEC_ATMEL;
11215 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11216 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11217 break;
11218 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11219 tp->nvram_jedecnum = JEDEC_ATMEL;
11220 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11221 break;
11222 case FLASH_VENDOR_ATMEL_EEPROM:
11223 tp->nvram_jedecnum = JEDEC_ATMEL;
11224 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11225 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11226 break;
11227 case FLASH_VENDOR_ST:
11228 tp->nvram_jedecnum = JEDEC_ST;
11229 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11230 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11231 break;
11232 case FLASH_VENDOR_SAIFUN:
11233 tp->nvram_jedecnum = JEDEC_SAIFUN;
11234 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11235 break;
11236 case FLASH_VENDOR_SST_SMALL:
11237 case FLASH_VENDOR_SST_LARGE:
11238 tp->nvram_jedecnum = JEDEC_SST;
11239 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11240 break;
1da177e4 11241 }
8590a603 11242 } else {
1da177e4
LT		 11243 tp->nvram_jedecnum = JEDEC_ATMEL;
11244 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11245 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11246 }
11247}
11248
a1b950d5
MC		 11249static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11250{
11251 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11252 case FLASH_5752PAGE_SIZE_256:
11253 tp->nvram_pagesize = 256;
11254 break;
11255 case FLASH_5752PAGE_SIZE_512:
11256 tp->nvram_pagesize = 512;
11257 break;
11258 case FLASH_5752PAGE_SIZE_1K:
11259 tp->nvram_pagesize = 1024;
11260 break;
11261 case FLASH_5752PAGE_SIZE_2K:
11262 tp->nvram_pagesize = 2048;
11263 break;
11264 case FLASH_5752PAGE_SIZE_4K:
11265 tp->nvram_pagesize = 4096;
11266 break;
11267 case FLASH_5752PAGE_SIZE_264:
11268 tp->nvram_pagesize = 264;
11269 break;
11270 case FLASH_5752PAGE_SIZE_528:
11271 tp->nvram_pagesize = 528;
11272 break;
11273 }
11274}
11275
361b4ac2
MC		 11276static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11277{
11278 u32 nvcfg1;
11279
11280 nvcfg1 = tr32(NVRAM_CFG1);
11281
e6af301b
MC		 11282 /* NVRAM protection for TPM */
11283 if (nvcfg1 & (1 << 27))
f66a29b0 11284 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11285
361b4ac2 11286 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11287 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11288 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11289 tp->nvram_jedecnum = JEDEC_ATMEL;
11290 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11291 break;
11292 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11293 tp->nvram_jedecnum = JEDEC_ATMEL;
11294 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11295 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11296 break;
11297 case FLASH_5752VENDOR_ST_M45PE10:
11298 case FLASH_5752VENDOR_ST_M45PE20:
11299 case FLASH_5752VENDOR_ST_M45PE40:
11300 tp->nvram_jedecnum = JEDEC_ST;
11301 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11302 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11303 break;
361b4ac2
MC		 11304 }
11305
11306 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11307 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11308 } else {
361b4ac2
MC		 11309 /* For eeprom, set pagesize to maximum eeprom size */
11310 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11311
11312 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11313 tw32(NVRAM_CFG1, nvcfg1);
11314 }
11315}
11316
d3c7b886
MC		 11317static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11318{
989a9d23 11319 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11320
11321 nvcfg1 = tr32(NVRAM_CFG1);
11322
11323 /* NVRAM protection for TPM */
989a9d23 11324 if (nvcfg1 & (1 << 27)) {
f66a29b0 11325 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11326 protect = 1;
11327 }
d3c7b886 11328
989a9d23
MC		 11329 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11330 switch (nvcfg1) {
8590a603
MC		 11331 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11332 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11333 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11334 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11335 tp->nvram_jedecnum = JEDEC_ATMEL;
11336 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11337 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11338 tp->nvram_pagesize = 264;
11339 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11340 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11341 tp->nvram_size = (protect ? 0x3e200 :
11342 TG3_NVRAM_SIZE_512KB);
11343 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11344 tp->nvram_size = (protect ? 0x1f200 :
11345 TG3_NVRAM_SIZE_256KB);
11346 else
11347 tp->nvram_size = (protect ? 0x1f200 :
11348 TG3_NVRAM_SIZE_128KB);
11349 break;
11350 case FLASH_5752VENDOR_ST_M45PE10:
11351 case FLASH_5752VENDOR_ST_M45PE20:
11352 case FLASH_5752VENDOR_ST_M45PE40:
11353 tp->nvram_jedecnum = JEDEC_ST;
11354 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11355 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11356 tp->nvram_pagesize = 256;
11357 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11358 tp->nvram_size = (protect ?
11359 TG3_NVRAM_SIZE_64KB :
11360 TG3_NVRAM_SIZE_128KB);
11361 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11362 tp->nvram_size = (protect ?
11363 TG3_NVRAM_SIZE_64KB :
11364 TG3_NVRAM_SIZE_256KB);
11365 else
11366 tp->nvram_size = (protect ?
11367 TG3_NVRAM_SIZE_128KB :
11368 TG3_NVRAM_SIZE_512KB);
11369 break;
d3c7b886
MC		 11370 }
11371}
11372
1b27777a
MC		 11373static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11374{
11375 u32 nvcfg1;
11376
11377 nvcfg1 = tr32(NVRAM_CFG1);
11378
11379 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11380 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11381 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11382 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11383 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11384 tp->nvram_jedecnum = JEDEC_ATMEL;
11385 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11386 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11387
8590a603
MC		 11388 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11389 tw32(NVRAM_CFG1, nvcfg1);
11390 break;
11391 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11392 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11393 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11394 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11395 tp->nvram_jedecnum = JEDEC_ATMEL;
11396 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11397 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11398 tp->nvram_pagesize = 264;
11399 break;
11400 case FLASH_5752VENDOR_ST_M45PE10:
11401 case FLASH_5752VENDOR_ST_M45PE20:
11402 case FLASH_5752VENDOR_ST_M45PE40:
11403 tp->nvram_jedecnum = JEDEC_ST;
11404 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11405 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11406 tp->nvram_pagesize = 256;
11407 break;
1b27777a
MC		 11408 }
11409}
11410
6b91fa02
MC		 11411static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11412{
11413 u32 nvcfg1, protect = 0;
11414
11415 nvcfg1 = tr32(NVRAM_CFG1);
11416
11417 /* NVRAM protection for TPM */
11418 if (nvcfg1 & (1 << 27)) {
f66a29b0 11419 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11420 protect = 1;
11421 }
11422
11423 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11424 switch (nvcfg1) {
8590a603
MC		 11425 case FLASH_5761VENDOR_ATMEL_ADB021D:
11426 case FLASH_5761VENDOR_ATMEL_ADB041D:
11427 case FLASH_5761VENDOR_ATMEL_ADB081D:
11428 case FLASH_5761VENDOR_ATMEL_ADB161D:
11429 case FLASH_5761VENDOR_ATMEL_MDB021D:
11430 case FLASH_5761VENDOR_ATMEL_MDB041D:
11431 case FLASH_5761VENDOR_ATMEL_MDB081D:
11432 case FLASH_5761VENDOR_ATMEL_MDB161D:
11433 tp->nvram_jedecnum = JEDEC_ATMEL;
11434 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11435 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11436 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11437 tp->nvram_pagesize = 256;
11438 break;
11439 case FLASH_5761VENDOR_ST_A_M45PE20:
11440 case FLASH_5761VENDOR_ST_A_M45PE40:
11441 case FLASH_5761VENDOR_ST_A_M45PE80:
11442 case FLASH_5761VENDOR_ST_A_M45PE16:
11443 case FLASH_5761VENDOR_ST_M_M45PE20:
11444 case FLASH_5761VENDOR_ST_M_M45PE40:
11445 case FLASH_5761VENDOR_ST_M_M45PE80:
11446 case FLASH_5761VENDOR_ST_M_M45PE16:
11447 tp->nvram_jedecnum = JEDEC_ST;
11448 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11449 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11450 tp->nvram_pagesize = 256;
11451 break;
6b91fa02
MC		 11452 }
11453
11454 if (protect) {
11455 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11456 } else {
11457 switch (nvcfg1) {
8590a603
MC		 11458 case FLASH_5761VENDOR_ATMEL_ADB161D:
11459 case FLASH_5761VENDOR_ATMEL_MDB161D:
11460 case FLASH_5761VENDOR_ST_A_M45PE16:
11461 case FLASH_5761VENDOR_ST_M_M45PE16:
11462 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11463 break;
11464 case FLASH_5761VENDOR_ATMEL_ADB081D:
11465 case FLASH_5761VENDOR_ATMEL_MDB081D:
11466 case FLASH_5761VENDOR_ST_A_M45PE80:
11467 case FLASH_5761VENDOR_ST_M_M45PE80:
11468 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11469 break;
11470 case FLASH_5761VENDOR_ATMEL_ADB041D:
11471 case FLASH_5761VENDOR_ATMEL_MDB041D:
11472 case FLASH_5761VENDOR_ST_A_M45PE40:
11473 case FLASH_5761VENDOR_ST_M_M45PE40:
11474 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11475 break;
11476 case FLASH_5761VENDOR_ATMEL_ADB021D:
11477 case FLASH_5761VENDOR_ATMEL_MDB021D:
11478 case FLASH_5761VENDOR_ST_A_M45PE20:
11479 case FLASH_5761VENDOR_ST_M_M45PE20:
11480 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11481 break;
6b91fa02
MC		 11482 }
11483 }
11484}
11485
b5d3772c
MC		 11486static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11487{
11488 tp->nvram_jedecnum = JEDEC_ATMEL;
11489 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11490 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11491}
11492
321d32a0
MC		 11493static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11494{
11495 u32 nvcfg1;
11496
11497 nvcfg1 = tr32(NVRAM_CFG1);
11498
11499 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11500 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11501 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11502 tp->nvram_jedecnum = JEDEC_ATMEL;
11503 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11504 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11505
11506 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11507 tw32(NVRAM_CFG1, nvcfg1);
11508 return;
11509 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11510 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11511 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11512 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11513 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11514 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11515 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11516 tp->nvram_jedecnum = JEDEC_ATMEL;
11517 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11518 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11519
11520 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11521 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11522 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11523 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11524 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11525 break;
11526 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11527 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11528 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11529 break;
11530 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11531 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11532 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11533 break;
11534 }
11535 break;
11536 case FLASH_5752VENDOR_ST_M45PE10:
11537 case FLASH_5752VENDOR_ST_M45PE20:
11538 case FLASH_5752VENDOR_ST_M45PE40:
11539 tp->nvram_jedecnum = JEDEC_ST;
11540 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11541 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11542
11543 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11544 case FLASH_5752VENDOR_ST_M45PE10:
11545 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11546 break;
11547 case FLASH_5752VENDOR_ST_M45PE20:
11548 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11549 break;
11550 case FLASH_5752VENDOR_ST_M45PE40:
11551 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11552 break;
11553 }
11554 break;
11555 default:
df259d8c 11556 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11557 return;
11558 }
11559
a1b950d5
MC		 11560 tg3_nvram_get_pagesize(tp, nvcfg1);
11561 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11562 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11563}
11564
11565
11566static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11567{
11568 u32 nvcfg1;
11569
11570 nvcfg1 = tr32(NVRAM_CFG1);
11571
11572 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11573 case FLASH_5717VENDOR_ATMEL_EEPROM:
11574 case FLASH_5717VENDOR_MICRO_EEPROM:
11575 tp->nvram_jedecnum = JEDEC_ATMEL;
11576 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11577 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11578
11579 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11580 tw32(NVRAM_CFG1, nvcfg1);
11581 return;
11582 case FLASH_5717VENDOR_ATMEL_MDB011D:
11583 case FLASH_5717VENDOR_ATMEL_ADB011B:
11584 case FLASH_5717VENDOR_ATMEL_ADB011D:
11585 case FLASH_5717VENDOR_ATMEL_MDB021D:
11586 case FLASH_5717VENDOR_ATMEL_ADB021B:
11587 case FLASH_5717VENDOR_ATMEL_ADB021D:
11588 case FLASH_5717VENDOR_ATMEL_45USPT:
11589 tp->nvram_jedecnum = JEDEC_ATMEL;
11590 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11591 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11592
11593 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11594 case FLASH_5717VENDOR_ATMEL_MDB021D:
11595 case FLASH_5717VENDOR_ATMEL_ADB021B:
11596 case FLASH_5717VENDOR_ATMEL_ADB021D:
11597 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11598 break;
11599 default:
11600 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11601 break;
11602 }
321d32a0 11603 break;
a1b950d5
MC		 11604 case FLASH_5717VENDOR_ST_M_M25PE10:
11605 case FLASH_5717VENDOR_ST_A_M25PE10:
11606 case FLASH_5717VENDOR_ST_M_M45PE10:
11607 case FLASH_5717VENDOR_ST_A_M45PE10:
11608 case FLASH_5717VENDOR_ST_M_M25PE20:
11609 case FLASH_5717VENDOR_ST_A_M25PE20:
11610 case FLASH_5717VENDOR_ST_M_M45PE20:
11611 case FLASH_5717VENDOR_ST_A_M45PE20:
11612 case FLASH_5717VENDOR_ST_25USPT:
11613 case FLASH_5717VENDOR_ST_45USPT:
11614 tp->nvram_jedecnum = JEDEC_ST;
11615 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11616 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11617
11618 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11619 case FLASH_5717VENDOR_ST_M_M25PE20:
11620 case FLASH_5717VENDOR_ST_A_M25PE20:
11621 case FLASH_5717VENDOR_ST_M_M45PE20:
11622 case FLASH_5717VENDOR_ST_A_M45PE20:
11623 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11624 break;
11625 default:
11626 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11627 break;
11628 }
321d32a0 11629 break;
a1b950d5
MC		 11630 default:
11631 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11632 return;
321d32a0 11633 }
a1b950d5
MC		 11634
11635 tg3_nvram_get_pagesize(tp, nvcfg1);
11636 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11637 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11638}
11639
1da177e4
LT		 11640/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11641static void __devinit tg3_nvram_init(struct tg3 *tp)
11642{
1da177e4
LT		 11643 tw32_f(GRC_EEPROM_ADDR,
11644 (EEPROM_ADDR_FSM_RESET |
11645 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11646 EEPROM_ADDR_CLKPERD_SHIFT)));
11647
9d57f01c 11648 msleep(1);
1da177e4
LT		 11649
11650 /* Enable seeprom accesses. */
11651 tw32_f(GRC_LOCAL_CTRL,
11652 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11653 udelay(100);
11654
11655 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11656 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11657 tp->tg3_flags |= TG3_FLAG_NVRAM;
11658
ec41c7df
MC		 11659 if (tg3_nvram_lock(tp)) {
11660 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11661 "tg3_nvram_init failed.\n", tp->dev->name);
11662 return;
11663 }
e6af301b 11664 tg3_enable_nvram_access(tp);
1da177e4 11665
989a9d23
MC		 11666 tp->nvram_size = 0;
11667
361b4ac2
MC		 11668 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11669 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11670 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11671 tg3_get_5755_nvram_info(tp);
d30cdd28 11672 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11673 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11674 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11675 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11676 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11677 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11678 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11679 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11680 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11681 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11682 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11683 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11684 else
11685 tg3_get_nvram_info(tp);
11686
989a9d23
MC		 11687 if (tp->nvram_size == 0)
11688 tg3_get_nvram_size(tp);
1da177e4 11689
e6af301b 11690 tg3_disable_nvram_access(tp);
381291b7 11691 tg3_nvram_unlock(tp);
1da177e4
LT		 11692
11693 } else {
11694 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11695
11696 tg3_get_eeprom_size(tp);
11697 }
11698}
11699
1da177e4
LT		 11700static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11701 u32 offset, u32 len, u8 *buf)
11702{
11703 int i, j, rc = 0;
11704 u32 val;
11705
11706 for (i = 0; i < len; i += 4) {
b9fc7dc5 11707 u32 addr;
a9dc529d 11708 __be32 data;
1da177e4
LT		 11709
11710 addr = offset + i;
11711
11712 memcpy(&data, buf + i, 4);
11713
62cedd11
MC		 11714 /*
11715 * The SEEPROM interface expects the data to always be opposite
11716 * the native endian format. We accomplish this by reversing
11717 * all the operations that would have been performed on the
11718 * data from a call to tg3_nvram_read_be32().
11719 */
11720 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11721
11722 val = tr32(GRC_EEPROM_ADDR);
11723 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11724
11725 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11726 EEPROM_ADDR_READ);
11727 tw32(GRC_EEPROM_ADDR, val |
11728 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11729 (addr & EEPROM_ADDR_ADDR_MASK) |
11730 EEPROM_ADDR_START |
11731 EEPROM_ADDR_WRITE);
6aa20a22 11732
9d57f01c 11733 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11734 val = tr32(GRC_EEPROM_ADDR);
11735
11736 if (val & EEPROM_ADDR_COMPLETE)
11737 break;
9d57f01c 11738 msleep(1);
1da177e4
LT		 11739 }
11740 if (!(val & EEPROM_ADDR_COMPLETE)) {
11741 rc = -EBUSY;
11742 break;
11743 }
11744 }
11745
11746 return rc;
11747}
11748
11749/* offset and length are dword aligned */
11750static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11751 u8 *buf)
11752{
11753 int ret = 0;
11754 u32 pagesize = tp->nvram_pagesize;
11755 u32 pagemask = pagesize - 1;
11756 u32 nvram_cmd;
11757 u8 *tmp;
11758
11759 tmp = kmalloc(pagesize, GFP_KERNEL);
11760 if (tmp == NULL)
11761 return -ENOMEM;
11762
11763 while (len) {
11764 int j;
e6af301b 11765 u32 phy_addr, page_off, size;
1da177e4
LT		 11766
11767 phy_addr = offset & ~pagemask;
6aa20a22 11768
1da177e4 11769 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11770 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11771 (__be32 *) (tmp + j));
11772 if (ret)
1da177e4
LT		 11773 break;
11774 }
11775 if (ret)
11776 break;
11777
11778 page_off = offset & pagemask;
11779 size = pagesize;
11780 if (len < size)
11781 size = len;
11782
11783 len -= size;
11784
11785 memcpy(tmp + page_off, buf, size);
11786
11787 offset = offset + (pagesize - page_off);
11788
e6af301b 11789 tg3_enable_nvram_access(tp);
1da177e4
LT		 11790
11791 /*
11792 * Before we can erase the flash page, we need
11793 * to issue a special "write enable" command.
11794 */
11795 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11796
11797 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11798 break;
11799
11800 /* Erase the target page */
11801 tw32(NVRAM_ADDR, phy_addr);
11802
11803 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11804 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11805
11806 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11807 break;
11808
11809 /* Issue another write enable to start the write. */
11810 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11811
11812 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11813 break;
11814
11815 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11816 __be32 data;
1da177e4 11817
b9fc7dc5 11818 data = *((__be32 *) (tmp + j));
a9dc529d 11819
b9fc7dc5 11820 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11821
11822 tw32(NVRAM_ADDR, phy_addr + j);
11823
11824 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11825 NVRAM_CMD_WR;
11826
11827 if (j == 0)
11828 nvram_cmd |= NVRAM_CMD_FIRST;
11829 else if (j == (pagesize - 4))
11830 nvram_cmd |= NVRAM_CMD_LAST;
11831
11832 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11833 break;
11834 }
11835 if (ret)
11836 break;
11837 }
11838
11839 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11840 tg3_nvram_exec_cmd(tp, nvram_cmd);
11841
11842 kfree(tmp);
11843
11844 return ret;
11845}
11846
11847/* offset and length are dword aligned */
11848static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11849 u8 *buf)
11850{
11851 int i, ret = 0;
11852
11853 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11854 u32 page_off, phy_addr, nvram_cmd;
11855 __be32 data;
1da177e4
LT		 11856
11857 memcpy(&data, buf + i, 4);
b9fc7dc5 11858 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11859
11860 page_off = offset % tp->nvram_pagesize;
11861
1820180b 11862 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11863
11864 tw32(NVRAM_ADDR, phy_addr);
11865
11866 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11867
11868 if ((page_off == 0) || (i == 0))
11869 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11870 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11871 nvram_cmd |= NVRAM_CMD_LAST;
11872
11873 if (i == (len - 4))
11874 nvram_cmd |= NVRAM_CMD_LAST;
11875
321d32a0
MC		 11876 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11877 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11878 (tp->nvram_jedecnum == JEDEC_ST) &&
11879 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11880
11881 if ((ret = tg3_nvram_exec_cmd(tp,
11882 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11883 NVRAM_CMD_DONE)))
11884
11885 break;
11886 }
11887 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11888 /* We always do complete word writes to eeprom. */
11889 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11890 }
11891
11892 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11893 break;
11894 }
11895 return ret;
11896}
11897
11898/* offset and length are dword aligned */
11899static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11900{
11901 int ret;
11902
1da177e4 11903 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11904 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11905 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11906 udelay(40);
11907 }
11908
11909 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11910 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11911 }
11912 else {
11913 u32 grc_mode;
11914
ec41c7df
MC		 11915 ret = tg3_nvram_lock(tp);
11916 if (ret)
11917 return ret;
1da177e4 11918
e6af301b
MC		 11919 tg3_enable_nvram_access(tp);
11920 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11921 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11922 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11923
11924 grc_mode = tr32(GRC_MODE);
11925 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11926
11927 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11928 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11929
11930 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11931 buf);
11932 }
11933 else {
11934 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11935 buf);
11936 }
11937
11938 grc_mode = tr32(GRC_MODE);
11939 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11940
e6af301b 11941 tg3_disable_nvram_access(tp);
1da177e4
LT		 11942 tg3_nvram_unlock(tp);
11943 }
11944
11945 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11946 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11947 udelay(40);
11948 }
11949
11950 return ret;
11951}
11952
11953struct subsys_tbl_ent {
11954 u16 subsys_vendor, subsys_devid;
11955 u32 phy_id;
11956};
11957
11958static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11959 /* Broadcom boards. */
11960 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11961 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11962 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11963 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11964 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11965 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11966 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11967 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11968 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11969 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11970 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11971
11972 /* 3com boards. */
11973 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11974 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11975 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11976 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11977 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11978
11979 /* DELL boards. */
11980 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11981 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11982 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11983 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11984
11985 /* Compaq boards. */
11986 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11987 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11988 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11989 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11990 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11991
11992 /* IBM boards. */
11993 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11994};
11995
11996static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11997{
11998 int i;
11999
12000 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12001 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12002 tp->pdev->subsystem_vendor) &&
12003 (subsys_id_to_phy_id[i].subsys_devid ==
12004 tp->pdev->subsystem_device))
12005 return &subsys_id_to_phy_id[i];
12006 }
12007 return NULL;
12008}
12009
7d0c41ef 12010static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 12011{
1da177e4 12012 u32 val;
caf636c7
MC		 12013 u16 pmcsr;
12014
12015 /* On some early chips the SRAM cannot be accessed in D3hot state,
12016 * so need make sure we're in D0.
12017 */
12018 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12019 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12020 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12021 msleep(1);
7d0c41ef
MC		 12022
12023 /* Make sure register accesses (indirect or otherwise)
12024 * will function correctly.
12025 */
12026 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12027 tp->misc_host_ctrl);
1da177e4 12028
f49639e6
DM		 12029 /* The memory arbiter has to be enabled in order for SRAM accesses
12030 * to succeed. Normally on powerup the tg3 chip firmware will make
12031 * sure it is enabled, but other entities such as system netboot
12032 * code might disable it.
12033 */
12034 val = tr32(MEMARB_MODE);
12035 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12036
1da177e4 12037 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 12038 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12039
a85feb8c
GZ		 12040 /* Assume an onboard device and WOL capable by default. */
12041 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 12042
b5d3772c 12043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 12044 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 12045 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12046 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12047 }
0527ba35
MC		 12048 val = tr32(VCPU_CFGSHDW);
12049 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 12050 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 12051 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 12052 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 12053 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 12054 goto done;
b5d3772c
MC		 12055 }
12056
1da177e4
LT		 12057 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12058 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12059 u32 nic_cfg, led_cfg;
a9daf367 12060 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 12061 int eeprom_phy_serdes = 0;
1da177e4
LT		 12062
12063 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12064 tp->nic_sram_data_cfg = nic_cfg;
12065
12066 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12067 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12069 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12070 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12071 (ver > 0) && (ver < 0x100))
12072 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12073
a9daf367
MC		 12074 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12075 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12076
1da177e4
LT		 12077 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12078 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12079 eeprom_phy_serdes = 1;
12080
12081 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12082 if (nic_phy_id != 0) {
12083 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12084 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12085
12086 eeprom_phy_id = (id1 >> 16) << 10;
12087 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12088 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12089 } else
12090 eeprom_phy_id = 0;
12091
7d0c41ef 12092 tp->phy_id = eeprom_phy_id;
747e8f8b 12093 if (eeprom_phy_serdes) {
a4e2b347 12094 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 12095 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12096 else
12097 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12098 }
7d0c41ef 12099
cbf46853 12100 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12101 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12102 SHASTA_EXT_LED_MODE_MASK);
cbf46853 12103 else
1da177e4
LT		 12104 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12105
12106 switch (led_cfg) {
12107 default:
12108 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12109 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12110 break;
12111
12112 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12113 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12114 break;
12115
12116 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12117 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 12118
12119 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12120 * read on some older 5700/5701 bootcode.
12121 */
12122 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12123 ASIC_REV_5700 ||
12124 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12125 ASIC_REV_5701)
12126 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12127
1da177e4
LT		 12128 break;
12129
12130 case SHASTA_EXT_LED_SHARED:
12131 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12132 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12133 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12134 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12135 LED_CTRL_MODE_PHY_2);
12136 break;
12137
12138 case SHASTA_EXT_LED_MAC:
12139 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12140 break;
12141
12142 case SHASTA_EXT_LED_COMBO:
12143 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12144 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12145 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12146 LED_CTRL_MODE_PHY_2);
12147 break;
12148
855e1111 12149 }
1da177e4
LT		 12150
12151 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12153 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12154 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12155
b2a5c19c
MC		 12156 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12157 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 12158
9d26e213 12159 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 12160 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12161 if ((tp->pdev->subsystem_vendor ==
12162 PCI_VENDOR_ID_ARIMA) &&
12163 (tp->pdev->subsystem_device == 0x205a ||
12164 tp->pdev->subsystem_device == 0x2063))
12165 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12166 } else {
f49639e6 12167 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 12168 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12169 }
1da177e4
LT		 12170
12171 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12172 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 12173 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 12174 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12175 }
b2b98d4a
MC		 12176
12177 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12178 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 12179 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 12180
a85feb8c
GZ		 12181 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12182 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12183 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 12184
12dac075 12185 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 12186 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 12187 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12188
1da177e4
LT		 12189 if (cfg2 & (1 << 17))
12190 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12191
12192 /* serdes signal pre-emphasis in register 0x590 set by */
12193 /* bootcode if bit 18 is set */
12194 if (cfg2 & (1 << 18))
12195 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 12196
321d32a0
MC		 12197 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12198 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 12199 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12200 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12201
8ed5d97e
MC		 12202 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12203 u32 cfg3;
12204
12205 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12206 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12207 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12208 }
a9daf367
MC		 12209
12210 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12211 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12212 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12213 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12214 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12215 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 12216 }
05ac4cb7
MC		 12217done:
12218 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12219 device_set_wakeup_enable(&tp->pdev->dev,
12220 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 12221}
12222
b2a5c19c
MC		 12223static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12224{
12225 int i;
12226 u32 val;
12227
12228 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12229 tw32(OTP_CTRL, cmd);
12230
12231 /* Wait for up to 1 ms for command to execute. */
12232 for (i = 0; i < 100; i++) {
12233 val = tr32(OTP_STATUS);
12234 if (val & OTP_STATUS_CMD_DONE)
12235 break;
12236 udelay(10);
12237 }
12238
12239 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12240}
12241
12242/* Read the gphy configuration from the OTP region of the chip. The gphy
12243 * configuration is a 32-bit value that straddles the alignment boundary.
12244 * We do two 32-bit reads and then shift and merge the results.
12245 */
12246static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12247{
12248 u32 bhalf_otp, thalf_otp;
12249
12250 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12251
12252 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12253 return 0;
12254
12255 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12256
12257 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12258 return 0;
12259
12260 thalf_otp = tr32(OTP_READ_DATA);
12261
12262 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12263
12264 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12265 return 0;
12266
12267 bhalf_otp = tr32(OTP_READ_DATA);
12268
12269 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12270}
12271
7d0c41ef
MC		 12272static int __devinit tg3_phy_probe(struct tg3 *tp)
12273{
12274 u32 hw_phy_id_1, hw_phy_id_2;
12275 u32 hw_phy_id, hw_phy_id_masked;
12276 int err;
1da177e4 12277
b02fd9e3
MC		 12278 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12279 return tg3_phy_init(tp);
12280
1da177e4 12281 /* Reading the PHY ID register can conflict with ASF
877d0310 12282 * firmware access to the PHY hardware.
1da177e4
LT		 12283 */
12284 err = 0;
0d3031d9
MC		 12285 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12286 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12287 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12288 } else {
12289 /* Now read the physical PHY_ID from the chip and verify
12290 * that it is sane. If it doesn't look good, we fall back
12291 * to either the hard-coded table based PHY_ID and failing
12292 * that the value found in the eeprom area.
12293 */
12294 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12295 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12296
12297 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12298 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12299 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12300
12301 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12302 }
12303
12304 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12305 tp->phy_id = hw_phy_id;
12306 if (hw_phy_id_masked == PHY_ID_BCM8002)
12307 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12308 else
12309 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12310 } else {
7d0c41ef
MC		 12311 if (tp->phy_id != PHY_ID_INVALID) {
12312 /* Do nothing, phy ID already set up in
12313 * tg3_get_eeprom_hw_cfg().
12314 */
1da177e4
LT		 12315 } else {
12316 struct subsys_tbl_ent *p;
12317
12318 /* No eeprom signature? Try the hardcoded
12319 * subsys device table.
12320 */
12321 p = lookup_by_subsys(tp);
12322 if (!p)
12323 return -ENODEV;
12324
12325 tp->phy_id = p->phy_id;
12326 if (!tp->phy_id ||
12327 tp->phy_id == PHY_ID_BCM8002)
12328 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12329 }
12330 }
12331
747e8f8b 12332 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12333 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12334 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12335 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12336
12337 tg3_readphy(tp, MII_BMSR, &bmsr);
12338 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12339 (bmsr & BMSR_LSTATUS))
12340 goto skip_phy_reset;
6aa20a22 12341
1da177e4
LT		 12342 err = tg3_phy_reset(tp);
12343 if (err)
12344 return err;
12345
12346 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12347 ADVERTISE_100HALF | ADVERTISE_100FULL |
12348 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12349 tg3_ctrl = 0;
12350 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12351 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12352 MII_TG3_CTRL_ADV_1000_FULL);
12353 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12354 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12355 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12356 MII_TG3_CTRL_ENABLE_AS_MASTER);
12357 }
12358
3600d918
MC		 12359 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12360 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12361 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12362 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12363 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12364
12365 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12366 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12367
12368 tg3_writephy(tp, MII_BMCR,
12369 BMCR_ANENABLE | BMCR_ANRESTART);
12370 }
12371 tg3_phy_set_wirespeed(tp);
12372
12373 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12374 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12375 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12376 }
12377
12378skip_phy_reset:
12379 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12380 err = tg3_init_5401phy_dsp(tp);
12381 if (err)
12382 return err;
12383 }
12384
12385 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12386 err = tg3_init_5401phy_dsp(tp);
12387 }
12388
747e8f8b 12389 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12390 tp->link_config.advertising =
12391 (ADVERTISED_1000baseT_Half |
12392 ADVERTISED_1000baseT_Full |
12393 ADVERTISED_Autoneg |
12394 ADVERTISED_FIBRE);
12395 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12396 tp->link_config.advertising &=
12397 ~(ADVERTISED_1000baseT_Half |
12398 ADVERTISED_1000baseT_Full);
12399
12400 return err;
12401}
12402
12403static void __devinit tg3_read_partno(struct tg3 *tp)
12404{
6d348f2c 12405 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12406 unsigned int i;
1b27777a 12407 u32 magic;
1da177e4 12408
df259d8c
MC		 12409 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12410 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12411 goto out_not_found;
1da177e4 12412
1820180b 12413 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12414 for (i = 0; i < 256; i += 4) {
12415 u32 tmp;
1da177e4 12416
6d348f2c
MC		 12417 /* The data is in little-endian format in NVRAM.
12418 * Use the big-endian read routines to preserve
12419 * the byte order as it exists in NVRAM.
12420 */
12421 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12422 goto out_not_found;
12423
6d348f2c 12424 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12425 }
12426 } else {
12427 int vpd_cap;
12428
12429 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12430 for (i = 0; i < 256; i += 4) {
12431 u32 tmp, j = 0;
b9fc7dc5 12432 __le32 v;
1b27777a
MC		 12433 u16 tmp16;
12434
12435 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12436 i);
12437 while (j++ < 100) {
12438 pci_read_config_word(tp->pdev, vpd_cap +
12439 PCI_VPD_ADDR, &tmp16);
12440 if (tmp16 & 0x8000)
12441 break;
12442 msleep(1);
12443 }
f49639e6
DM		 12444 if (!(tmp16 & 0x8000))
12445 goto out_not_found;
12446
1b27777a
MC		 12447 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12448 &tmp);
b9fc7dc5 12449 v = cpu_to_le32(tmp);
6d348f2c 12450 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12451 }
1da177e4
LT		 12452 }
12453
12454 /* Now parse and find the part number. */
af2c6a4a 12455 for (i = 0; i < 254; ) {
1da177e4 12456 unsigned char val = vpd_data[i];
af2c6a4a 12457 unsigned int block_end;
1da177e4
LT		 12458
12459 if (val == 0x82 || val == 0x91) {
12460 i = (i + 3 +
12461 (vpd_data[i + 1] +
12462 (vpd_data[i + 2] << 8)));
12463 continue;
12464 }
12465
12466 if (val != 0x90)
12467 goto out_not_found;
12468
12469 block_end = (i + 3 +
12470 (vpd_data[i + 1] +
12471 (vpd_data[i + 2] << 8)));
12472 i += 3;
af2c6a4a
MC		 12473
12474 if (block_end > 256)
12475 goto out_not_found;
12476
12477 while (i < (block_end - 2)) {
1da177e4
LT		 12478 if (vpd_data[i + 0] == 'P' &&
12479 vpd_data[i + 1] == 'N') {
12480 int partno_len = vpd_data[i + 2];
12481
af2c6a4a
MC		 12482 i += 3;
12483 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12484 goto out_not_found;
12485
12486 memcpy(tp->board_part_number,
af2c6a4a 12487 &vpd_data[i], partno_len);
1da177e4
LT		 12488
12489 /* Success. */
12490 return;
12491 }
af2c6a4a 12492 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12493 }
12494
12495 /* Part number not found. */
12496 goto out_not_found;
12497 }
12498
12499out_not_found:
b5d3772c
MC		 12500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12501 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12502 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12503 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12504 strcpy(tp->board_part_number, "BCM57780");
12505 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12506 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12507 strcpy(tp->board_part_number, "BCM57760");
12508 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12509 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12510 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12511 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12512 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12513 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12514 else
12515 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12516}
12517
9c8a620e
MC		 12518static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12519{
12520 u32 val;
12521
e4f34110 12522 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12523 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12524 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12525 val != 0)
12526 return 0;
12527
12528 return 1;
12529}
12530
acd9c119
MC		 12531static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12532{
ff3a7cb2 12533 u32 val, offset, start, ver_offset;
acd9c119 12534 int i;
ff3a7cb2 12535 bool newver = false;
acd9c119
MC		 12536
12537 if (tg3_nvram_read(tp, 0xc, &offset) ||
12538 tg3_nvram_read(tp, 0x4, &start))
12539 return;
12540
12541 offset = tg3_nvram_logical_addr(tp, offset);
12542
ff3a7cb2 12543 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12544 return;
12545
ff3a7cb2
MC		 12546 if ((val & 0xfc000000) == 0x0c000000) {
12547 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12548 return;
12549
ff3a7cb2
MC		 12550 if (val == 0)
12551 newver = true;
12552 }
12553
12554 if (newver) {
12555 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12556 return;
12557
12558 offset = offset + ver_offset - start;
12559 for (i = 0; i < 16; i += 4) {
12560 __be32 v;
12561 if (tg3_nvram_read_be32(tp, offset + i, &v))
12562 return;
12563
12564 memcpy(tp->fw_ver + i, &v, sizeof(v));
12565 }
12566 } else {
12567 u32 major, minor;
12568
12569 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12570 return;
12571
12572 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12573 TG3_NVM_BCVER_MAJSFT;
12574 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12575 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12576 }
12577}
12578
a6f6cb1c
MC		 12579static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12580{
12581 u32 val, major, minor;
12582
12583 /* Use native endian representation */
12584 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12585 return;
12586
12587 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12588 TG3_NVM_HWSB_CFG1_MAJSFT;
12589 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12590 TG3_NVM_HWSB_CFG1_MINSFT;
12591
12592 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12593}
12594
dfe00d7d
MC		 12595static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12596{
12597 u32 offset, major, minor, build;
12598
12599 tp->fw_ver[0] = 's';
12600 tp->fw_ver[1] = 'b';
12601 tp->fw_ver[2] = '\0';
12602
12603 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12604 return;
12605
12606 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12607 case TG3_EEPROM_SB_REVISION_0:
12608 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12609 break;
12610 case TG3_EEPROM_SB_REVISION_2:
12611 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12612 break;
12613 case TG3_EEPROM_SB_REVISION_3:
12614 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12615 break;
12616 default:
12617 return;
12618 }
12619
e4f34110 12620 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12621 return;
12622
12623 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12624 TG3_EEPROM_SB_EDH_BLD_SHFT;
12625 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12626 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12627 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12628
12629 if (minor > 99 || build > 26)
12630 return;
12631
12632 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12633
12634 if (build > 0) {
12635 tp->fw_ver[8] = 'a' + build - 1;
12636 tp->fw_ver[9] = '\0';
12637 }
12638}
12639
acd9c119 12640static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12641{
12642 u32 val, offset, start;
acd9c119 12643 int i, vlen;
9c8a620e
MC		 12644
12645 for (offset = TG3_NVM_DIR_START;
12646 offset < TG3_NVM_DIR_END;
12647 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12648 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12649 return;
12650
9c8a620e
MC		 12651 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12652 break;
12653 }
12654
12655 if (offset == TG3_NVM_DIR_END)
12656 return;
12657
12658 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12659 start = 0x08000000;
e4f34110 12660 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12661 return;
12662
e4f34110 12663 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12664 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12665 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12666 return;
12667
12668 offset += val - start;
12669
acd9c119 12670 vlen = strlen(tp->fw_ver);
9c8a620e 12671
acd9c119
MC		 12672 tp->fw_ver[vlen++] = ',';
12673 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12674
12675 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12676 __be32 v;
12677 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12678 return;
12679
b9fc7dc5 12680 offset += sizeof(v);
c4e6575c 12681
acd9c119
MC		 12682 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12683 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12684 break;
c4e6575c 12685 }
9c8a620e 12686
acd9c119
MC		 12687 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12688 vlen += sizeof(v);
c4e6575c 12689 }
acd9c119
MC		 12690}
12691
7fd76445
MC		 12692static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12693{
12694 int vlen;
12695 u32 apedata;
12696
12697 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12698 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12699 return;
12700
12701 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12702 if (apedata != APE_SEG_SIG_MAGIC)
12703 return;
12704
12705 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12706 if (!(apedata & APE_FW_STATUS_READY))
12707 return;
12708
12709 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12710
12711 vlen = strlen(tp->fw_ver);
12712
12713 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12714 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12715 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12716 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12717 (apedata & APE_FW_VERSION_BLDMSK));
12718}
12719
acd9c119
MC		 12720static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12721{
12722 u32 val;
12723
df259d8c
MC		 12724 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12725 tp->fw_ver[0] = 's';
12726 tp->fw_ver[1] = 'b';
12727 tp->fw_ver[2] = '\0';
12728
12729 return;
12730 }
12731
acd9c119
MC		 12732 if (tg3_nvram_read(tp, 0, &val))
12733 return;
12734
12735 if (val == TG3_EEPROM_MAGIC)
12736 tg3_read_bc_ver(tp);
12737 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12738 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12739 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12740 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12741 else
12742 return;
12743
12744 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12745 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12746 return;
12747
12748 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12749
12750 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12751}
12752
7544b097
MC		 12753static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12754
1da177e4
LT		 12755static int __devinit tg3_get_invariants(struct tg3 *tp)
12756{
12757 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12758 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12759 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12760 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12761 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12762 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12763 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12764 { },
12765 };
12766 u32 misc_ctrl_reg;
1da177e4
LT		 12767 u32 pci_state_reg, grc_misc_cfg;
12768 u32 val;
12769 u16 pci_cmd;
5e7dfd0f 12770 int err;
1da177e4 12771
1da177e4
LT		 12772 /* Force memory write invalidate off. If we leave it on,
12773 * then on 5700_BX chips we have to enable a workaround.
12774 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12775 * to match the cacheline size. The Broadcom driver have this
12776 * workaround but turns MWI off all the times so never uses
12777 * it. This seems to suggest that the workaround is insufficient.
12778 */
12779 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12780 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12781 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12782
12783 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12784 * has the register indirect write enable bit set before
12785 * we try to access any of the MMIO registers. It is also
12786 * critical that the PCI-X hw workaround situation is decided
12787 * before that as well.
12788 */
12789 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12790 &misc_ctrl_reg);
12791
12792 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12793 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12795 u32 prod_id_asic_rev;
12796
5001e2f6
MC		 12797 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12798 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12799 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
f6eb9b1f
MC		 12800 pci_read_config_dword(tp->pdev,
12801 TG3PCI_GEN2_PRODID_ASICREV,
12802 &prod_id_asic_rev);
12803 else
12804 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12805 &prod_id_asic_rev);
12806
321d32a0 12807 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12808 }
1da177e4 12809
ff645bec
MC		 12810 /* Wrong chip ID in 5752 A0. This code can be removed later
12811 * as A0 is not in production.
12812 */
12813 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12814 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12815
6892914f
MC		 12816 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12817 * we need to disable memory and use config. cycles
12818 * only to access all registers. The 5702/03 chips
12819 * can mistakenly decode the special cycles from the
12820 * ICH chipsets as memory write cycles, causing corruption
12821 * of register and memory space. Only certain ICH bridges
12822 * will drive special cycles with non-zero data during the
12823 * address phase which can fall within the 5703's address
12824 * range. This is not an ICH bug as the PCI spec allows
12825 * non-zero address during special cycles. However, only
12826 * these ICH bridges are known to drive non-zero addresses
12827 * during special cycles.
12828 *
12829 * Since special cycles do not cross PCI bridges, we only
12830 * enable this workaround if the 5703 is on the secondary
12831 * bus of these ICH bridges.
12832 */
12833 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12834 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12835 static struct tg3_dev_id {
12836 u32 vendor;
12837 u32 device;
12838 u32 rev;
12839 } ich_chipsets[] = {
12840 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12841 PCI_ANY_ID },
12842 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12843 PCI_ANY_ID },
12844 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12845 0xa },
12846 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12847 PCI_ANY_ID },
12848 { },
12849 };
12850 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12851 struct pci_dev *bridge = NULL;
12852
12853 while (pci_id->vendor != 0) {
12854 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12855 bridge);
12856 if (!bridge) {
12857 pci_id++;
12858 continue;
12859 }
12860 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12861 if (bridge->revision > pci_id->rev)
6892914f
MC		 12862 continue;
12863 }
12864 if (bridge->subordinate &&
12865 (bridge->subordinate->number ==
12866 tp->pdev->bus->number)) {
12867
12868 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12869 pci_dev_put(bridge);
12870 break;
12871 }
12872 }
12873 }
12874
41588ba1
MC		 12875 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12876 static struct tg3_dev_id {
12877 u32 vendor;
12878 u32 device;
12879 } bridge_chipsets[] = {
12880 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12881 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12882 { },
12883 };
12884 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12885 struct pci_dev *bridge = NULL;
12886
12887 while (pci_id->vendor != 0) {
12888 bridge = pci_get_device(pci_id->vendor,
12889 pci_id->device,
12890 bridge);
12891 if (!bridge) {
12892 pci_id++;
12893 continue;
12894 }
12895 if (bridge->subordinate &&
12896 (bridge->subordinate->number <=
12897 tp->pdev->bus->number) &&
12898 (bridge->subordinate->subordinate >=
12899 tp->pdev->bus->number)) {
12900 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12901 pci_dev_put(bridge);
12902 break;
12903 }
12904 }
12905 }
12906
4a29cc2e
MC		 12907 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12908 * DMA addresses > 40-bit. This bridge may have other additional
12909 * 57xx devices behind it in some 4-port NIC designs for example.
12910 * Any tg3 device found behind the bridge will also need the 40-bit
12911 * DMA workaround.
12912 */
a4e2b347
MC		 12913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12915 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12916 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12917 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12918 }
4a29cc2e
MC		 12919 else {
12920 struct pci_dev *bridge = NULL;
12921
12922 do {
12923 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12924 PCI_DEVICE_ID_SERVERWORKS_EPB,
12925 bridge);
12926 if (bridge && bridge->subordinate &&
12927 (bridge->subordinate->number <=
12928 tp->pdev->bus->number) &&
12929 (bridge->subordinate->subordinate >=
12930 tp->pdev->bus->number)) {
12931 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12932 pci_dev_put(bridge);
12933 break;
12934 }
12935 } while (bridge);
12936 }
4cf78e4f 12937
1da177e4
LT		 12938 /* Initialize misc host control in PCI block. */
12939 tp->misc_host_ctrl |= (misc_ctrl_reg &
12940 MISC_HOST_CTRL_CHIPREV);
12941 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12942 tp->misc_host_ctrl);
12943
f6eb9b1f
MC		 12944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12947 tp->pdev_peer = tg3_find_peer(tp);
12948
321d32a0
MC		 12949 /* Intentionally exclude ASIC_REV_5906 */
12950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12957 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12958
12959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12960 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12961 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12962 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12963 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12964 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12965
1b440c56
JL		 12966 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12967 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12968 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12969
027455ad
MC		 12970 /* 5700 B0 chips do not support checksumming correctly due
12971 * to hardware bugs.
12972 */
12973 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12974 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12975 else {
12976 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12977 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12978 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12979 tp->dev->features |= NETIF_F_IPV6_CSUM;
12980 }
12981
507399f1 12982 /* Determine TSO capabilities */
e849cdc3
MC		 12983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12984 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12985 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 12987 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12988 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12989 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12991 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12992 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12993 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12994 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12995 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12996 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12998 tp->fw_needed = FIRMWARE_TG3TSO5;
12999 else
13000 tp->fw_needed = FIRMWARE_TG3TSO;
13001 }
13002
13003 tp->irq_max = 1;
13004
5a6f3074 13005 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 13006 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13007 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13008 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13009 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13010 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13011 tp->pdev_peer == tp->pdev))
13012 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13013
321d32a0 13014 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 13015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 13016 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 13017 }
4f125f42 13018
507399f1
MC		 13019 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13020 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13021 tp->irq_max = TG3_IRQ_MAX_VECS;
13022 }
f6eb9b1f 13023 }
0e1406dd 13024
615774fe
MC		 13025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13027 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13028 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13029 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13030 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 13031 }
f6eb9b1f 13032
f51f3562 13033 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 13034 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 13036 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 13037
52f4490c
MC		 13038 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13039 &pci_state_reg);
13040
5e7dfd0f
MC		 13041 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13042 if (tp->pcie_cap != 0) {
13043 u16 lnkctl;
13044
1da177e4 13045 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 13046
13047 pcie_set_readrq(tp->pdev, 4096);
13048
5e7dfd0f
MC		 13049 pci_read_config_word(tp->pdev,
13050 tp->pcie_cap + PCI_EXP_LNKCTL,
13051 &lnkctl);
13052 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 13054 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 13055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 13056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 13057 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13058 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 13059 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 13060 }
52f4490c 13061 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 13062 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 13063 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13064 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13065 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13066 if (!tp->pcix_cap) {
13067 printk(KERN_ERR PFX "Cannot find PCI-X "
13068 "capability, aborting.\n");
13069 return -EIO;
13070 }
13071
13072 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13073 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13074 }
1da177e4 13075
399de50b
MC		 13076 /* If we have an AMD 762 or VIA K8T800 chipset, write
13077 * reordering to the mailbox registers done by the host
13078 * controller can cause major troubles. We read back from
13079 * every mailbox register write to force the writes to be
13080 * posted to the chip in order.
13081 */
13082 if (pci_dev_present(write_reorder_chipsets) &&
13083 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13084 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13085
69fc4053
MC		 13086 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13087 &tp->pci_cacheline_sz);
13088 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13089 &tp->pci_lat_timer);
1da177e4
LT		 13090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13091 tp->pci_lat_timer < 64) {
13092 tp->pci_lat_timer = 64;
69fc4053
MC		 13093 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13094 tp->pci_lat_timer);
1da177e4
LT		 13095 }
13096
52f4490c
MC		 13097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13098 /* 5700 BX chips need to have their TX producer index
13099 * mailboxes written twice to workaround a bug.
13100 */
13101 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 13102
52f4490c 13103 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 13104 *
13105 * The workaround is to use indirect register accesses
13106 * for all chip writes not to mailbox registers.
13107 */
52f4490c 13108 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 13109 u32 pm_reg;
1da177e4
LT		 13110
13111 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13112
13113 /* The chip can have it's power management PCI config
13114 * space registers clobbered due to this bug.
13115 * So explicitly force the chip into D0 here.
13116 */
9974a356
MC		 13117 pci_read_config_dword(tp->pdev,
13118 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13119 &pm_reg);
13120 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13121 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 13122 pci_write_config_dword(tp->pdev,
13123 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 13124 pm_reg);
13125
13126 /* Also, force SERR#/PERR# in PCI command. */
13127 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13128 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13129 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13130 }
13131 }
13132
1da177e4
LT		 13133 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13134 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13135 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13136 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13137
13138 /* Chip-specific fixup from Broadcom driver */
13139 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13140 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13141 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13142 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13143 }
13144
1ee582d8 13145 /* Default fast path register access methods */
20094930 13146 tp->read32 = tg3_read32;
1ee582d8 13147 tp->write32 = tg3_write32;
09ee929c 13148 tp->read32_mbox = tg3_read32;
20094930 13149 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 13150 tp->write32_tx_mbox = tg3_write32;
13151 tp->write32_rx_mbox = tg3_write32;
13152
13153 /* Various workaround register access methods */
13154 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13155 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 13156 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13157 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13158 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13159 /*
13160 * Back to back register writes can cause problems on these
13161 * chips, the workaround is to read back all reg writes
13162 * except those to mailbox regs.
13163 *
13164 * See tg3_write_indirect_reg32().
13165 */
1ee582d8 13166 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 13167 }
13168
1ee582d8
MC		 13169 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13170 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13171 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13172 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13173 tp->write32_rx_mbox = tg3_write_flush_reg32;
13174 }
20094930 13175
6892914f
MC		 13176 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13177 tp->read32 = tg3_read_indirect_reg32;
13178 tp->write32 = tg3_write_indirect_reg32;
13179 tp->read32_mbox = tg3_read_indirect_mbox;
13180 tp->write32_mbox = tg3_write_indirect_mbox;
13181 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13182 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13183
13184 iounmap(tp->regs);
22abe310 13185 tp->regs = NULL;
6892914f
MC		 13186
13187 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13188 pci_cmd &= ~PCI_COMMAND_MEMORY;
13189 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13190 }
b5d3772c
MC		 13191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13192 tp->read32_mbox = tg3_read32_mbox_5906;
13193 tp->write32_mbox = tg3_write32_mbox_5906;
13194 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13195 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13196 }
6892914f 13197
bbadf503
MC		 13198 if (tp->write32 == tg3_write_indirect_reg32 ||
13199 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13200 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 13201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 13202 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13203
7d0c41ef 13204 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 13205 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 13206 * determined before calling tg3_set_power_state() so that
13207 * we know whether or not to switch out of Vaux power.
13208 * When the flag is set, it means that GPIO1 is used for eeprom
13209 * write protect and also implies that it is a LOM where GPIOs
13210 * are not used to switch power.
6aa20a22 13211 */
7d0c41ef
MC		 13212 tg3_get_eeprom_hw_cfg(tp);
13213
0d3031d9
MC		 13214 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13215 /* Allow reads and writes to the
13216 * APE register and memory space.
13217 */
13218 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13219 PCISTATE_ALLOW_APE_SHMEM_WR;
13220 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13221 pci_state_reg);
13222 }
13223
9936bcf6 13224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 13225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 13226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 13227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 13229 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13230
314fba34
MC		 13231 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13232 * GPIO1 driven high will bring 5700's external PHY out of reset.
13233 * It is also used as eeprom write protect on LOMs.
13234 */
13235 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13236 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13237 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13238 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13239 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13240 /* Unused GPIO3 must be driven as output on 5752 because there
13241 * are no pull-up resistors on unused GPIO pins.
13242 */
13243 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13244 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13245
321d32a0
MC		 13246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13247 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 13248 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13249
8d519ab2
MC		 13250 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13251 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13252 /* Turn off the debug UART. */
13253 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13254 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13255 /* Keep VMain power. */
13256 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13257 GRC_LCLCTRL_GPIO_OUTPUT0;
13258 }
13259
1da177e4 13260 /* Force the chip into D0. */
bc1c7567 13261 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13262 if (err) {
13263 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13264 pci_name(tp->pdev));
13265 return err;
13266 }
13267
1da177e4
LT		 13268 /* Derive initial jumbo mode from MTU assigned in
13269 * ether_setup() via the alloc_etherdev() call
13270 */
0f893dc6 13271 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13272 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13273 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13274
13275 /* Determine WakeOnLan speed to use. */
13276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13277 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13278 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13279 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13280 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13281 } else {
13282 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13283 }
13284
7f97a4bd
MC		 13285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13286 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13287
1da177e4
LT		 13288 /* A few boards don't want Ethernet@WireSpeed phy feature */
13289 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13290 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13291 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13292 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13293 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13294 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13295 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13296
13297 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13298 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13299 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13300 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13301 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13302
321d32a0 13303 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13304 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13305 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 13306 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13307 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 13308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13312 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13313 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13314 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13315 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13316 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13317 } else
c424cb24
MC		 13318 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13319 }
1da177e4 13320
b2a5c19c
MC		 13321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13322 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13323 tp->phy_otp = tg3_read_otp_phycfg(tp);
13324 if (tp->phy_otp == 0)
13325 tp->phy_otp = TG3_OTP_DEFAULT;
13326 }
13327
f51f3562 13328 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13329 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13330 else
13331 tp->mi_mode = MAC_MI_MODE_BASE;
13332
1da177e4 13333 tp->coalesce_mode = 0;
1da177e4
LT		 13334 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13335 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13336 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13337
321d32a0
MC		 13338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13339 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13340 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13341
158d7abd
MC		 13342 err = tg3_mdio_init(tp);
13343 if (err)
13344 return err;
1da177e4
LT		 13345
13346 /* Initialize data/descriptor byte/word swapping. */
13347 val = tr32(GRC_MODE);
13348 val &= GRC_MODE_HOST_STACKUP;
13349 tw32(GRC_MODE, val | tp->grc_mode);
13350
13351 tg3_switch_clocks(tp);
13352
13353 /* Clear this out for sanity. */
13354 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13355
13356 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13357 &pci_state_reg);
13358 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13359 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13360 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13361
13362 if (chiprevid == CHIPREV_ID_5701_A0 ||
13363 chiprevid == CHIPREV_ID_5701_B0 ||
13364 chiprevid == CHIPREV_ID_5701_B2 ||
13365 chiprevid == CHIPREV_ID_5701_B5) {
13366 void __iomem *sram_base;
13367
13368 /* Write some dummy words into the SRAM status block
13369 * area, see if it reads back correctly. If the return
13370 * value is bad, force enable the PCIX workaround.
13371 */
13372 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13373
13374 writel(0x00000000, sram_base);
13375 writel(0x00000000, sram_base + 4);
13376 writel(0xffffffff, sram_base + 4);
13377 if (readl(sram_base) != 0x00000000)
13378 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13379 }
13380 }
13381
13382 udelay(50);
13383 tg3_nvram_init(tp);
13384
13385 grc_misc_cfg = tr32(GRC_MISC_CFG);
13386 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13387
1da177e4
LT		 13388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13389 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13390 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13391 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13392
fac9b83e
DM		 13393 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13394 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13395 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13396 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13397 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13398 HOSTCC_MODE_CLRTICK_TXBD);
13399
13400 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13401 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13402 tp->misc_host_ctrl);
13403 }
13404
3bda1258
MC		 13405 /* Preserve the APE MAC_MODE bits */
13406 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13407 tp->mac_mode = tr32(MAC_MODE) |
13408 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13409 else
13410 tp->mac_mode = TG3_DEF_MAC_MODE;
13411
1da177e4
LT		 13412 /* these are limited to 10/100 only */
13413 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13414 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13415 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13416 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13417 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13418 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13419 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13420 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13421 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13422 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13423 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13424 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13425 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13426 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13427
13428 err = tg3_phy_probe(tp);
13429 if (err) {
13430 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13431 pci_name(tp->pdev), err);
13432 /* ... but do not return immediately ... */
b02fd9e3 13433 tg3_mdio_fini(tp);
1da177e4
LT		 13434 }
13435
13436 tg3_read_partno(tp);
c4e6575c 13437 tg3_read_fw_ver(tp);
1da177e4
LT		 13438
13439 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13440 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13441 } else {
13442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13443 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13444 else
13445 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13446 }
13447
13448 /* 5700 {AX,BX} chips have a broken status block link
13449 * change bit implementation, so we must use the
13450 * status register in those cases.
13451 */
13452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13453 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13454 else
13455 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13456
13457 /* The led_ctrl is set during tg3_phy_probe, here we might
13458 * have to force the link status polling mechanism based
13459 * upon subsystem IDs.
13460 */
13461 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13462 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13463 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13464 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13465 TG3_FLAG_USE_LINKCHG_REG);
13466 }
13467
13468 /* For all SERDES we poll the MAC status register. */
13469 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13470 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13471 else
13472 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13473
ad829268 13474 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13475 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13476 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13477 tp->rx_offset = 0;
13478
f92905de
MC		 13479 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13480
13481 /* Increment the rx prod index on the rx std ring by at most
13482 * 8 for these chips to workaround hw errata.
13483 */
13484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13486 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13487 tp->rx_std_max_post = 8;
13488
8ed5d97e
MC		 13489 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13490 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13491 PCIE_PWR_MGMT_L1_THRESH_MSK;
13492
1da177e4
LT		 13493 return err;
13494}
13495
49b6e95f 13496#ifdef CONFIG_SPARC
1da177e4
LT		 13497static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13498{
13499 struct net_device *dev = tp->dev;
13500 struct pci_dev *pdev = tp->pdev;
49b6e95f 13501 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13502 const unsigned char *addr;
49b6e95f
DM		 13503 int len;
13504
13505 addr = of_get_property(dp, "local-mac-address", &len);
13506 if (addr && len == 6) {
13507 memcpy(dev->dev_addr, addr, 6);
13508 memcpy(dev->perm_addr, dev->dev_addr, 6);
13509 return 0;
1da177e4
LT		 13510 }
13511 return -ENODEV;
13512}
13513
13514static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13515{
13516 struct net_device *dev = tp->dev;
13517
13518 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13519 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13520 return 0;
13521}
13522#endif
13523
13524static int __devinit tg3_get_device_address(struct tg3 *tp)
13525{
13526 struct net_device *dev = tp->dev;
13527 u32 hi, lo, mac_offset;
008652b3 13528 int addr_ok = 0;
1da177e4 13529
49b6e95f 13530#ifdef CONFIG_SPARC
1da177e4
LT		 13531 if (!tg3_get_macaddr_sparc(tp))
13532 return 0;
13533#endif
13534
13535 mac_offset = 0x7c;
f49639e6 13536 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13537 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13538 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13539 mac_offset = 0xcc;
13540 if (tg3_nvram_lock(tp))
13541 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13542 else
13543 tg3_nvram_unlock(tp);
a1b950d5
MC		 13544 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13545 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13546 mac_offset = 0xcc;
13547 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13548 mac_offset = 0x10;
1da177e4
LT		 13549
13550 /* First try to get it from MAC address mailbox. */
13551 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13552 if ((hi >> 16) == 0x484b) {
13553 dev->dev_addr[0] = (hi >> 8) & 0xff;
13554 dev->dev_addr[1] = (hi >> 0) & 0xff;
13555
13556 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13557 dev->dev_addr[2] = (lo >> 24) & 0xff;
13558 dev->dev_addr[3] = (lo >> 16) & 0xff;
13559 dev->dev_addr[4] = (lo >> 8) & 0xff;
13560 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13561
008652b3
MC		 13562 /* Some old bootcode may report a 0 MAC address in SRAM */
13563 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13564 }
13565 if (!addr_ok) {
13566 /* Next, try NVRAM. */
df259d8c
MC		 13567 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13568 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13569 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13570 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13571 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13572 }
13573 /* Finally just fetch it out of the MAC control regs. */
13574 else {
13575 hi = tr32(MAC_ADDR_0_HIGH);
13576 lo = tr32(MAC_ADDR_0_LOW);
13577
13578 dev->dev_addr[5] = lo & 0xff;
13579 dev->dev_addr[4] = (lo >> 8) & 0xff;
13580 dev->dev_addr[3] = (lo >> 16) & 0xff;
13581 dev->dev_addr[2] = (lo >> 24) & 0xff;
13582 dev->dev_addr[1] = hi & 0xff;
13583 dev->dev_addr[0] = (hi >> 8) & 0xff;
13584 }
1da177e4
LT		 13585 }
13586
13587 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13588#ifdef CONFIG_SPARC
1da177e4
LT		 13589 if (!tg3_get_default_macaddr_sparc(tp))
13590 return 0;
13591#endif
13592 return -EINVAL;
13593 }
2ff43697 13594 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13595 return 0;
13596}
13597
59e6b434
DM		 13598#define BOUNDARY_SINGLE_CACHELINE 1
13599#define BOUNDARY_MULTI_CACHELINE 2
13600
13601static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13602{
13603 int cacheline_size;
13604 u8 byte;
13605 int goal;
13606
13607 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13608 if (byte == 0)
13609 cacheline_size = 1024;
13610 else
13611 cacheline_size = (int) byte * 4;
13612
13613 /* On 5703 and later chips, the boundary bits have no
13614 * effect.
13615 */
13616 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13617 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13618 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13619 goto out;
13620
13621#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13622 goal = BOUNDARY_MULTI_CACHELINE;
13623#else
13624#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13625 goal = BOUNDARY_SINGLE_CACHELINE;
13626#else
13627 goal = 0;
13628#endif
13629#endif
13630
cbf9ca6c
MC		 13631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13632 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13633 goto out;
13634 }
13635
59e6b434
DM		 13636 if (!goal)
13637 goto out;
13638
13639 /* PCI controllers on most RISC systems tend to disconnect
13640 * when a device tries to burst across a cache-line boundary.
13641 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13642 *
13643 * Unfortunately, for PCI-E there are only limited
13644 * write-side controls for this, and thus for reads
13645 * we will still get the disconnects. We'll also waste
13646 * these PCI cycles for both read and write for chips
13647 * other than 5700 and 5701 which do not implement the
13648 * boundary bits.
13649 */
13650 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13651 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13652 switch (cacheline_size) {
13653 case 16:
13654 case 32:
13655 case 64:
13656 case 128:
13657 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13658 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13659 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13660 } else {
13661 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13662 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13663 }
13664 break;
13665
13666 case 256:
13667 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13668 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13669 break;
13670
13671 default:
13672 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13673 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13674 break;
855e1111 13675 }
59e6b434
DM		 13676 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13677 switch (cacheline_size) {
13678 case 16:
13679 case 32:
13680 case 64:
13681 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13682 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13683 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13684 break;
13685 }
13686 /* fallthrough */
13687 case 128:
13688 default:
13689 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13690 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13691 break;
855e1111 13692 }
59e6b434
DM		 13693 } else {
13694 switch (cacheline_size) {
13695 case 16:
13696 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13697 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13698 DMA_RWCTRL_WRITE_BNDRY_16);
13699 break;
13700 }
13701 /* fallthrough */
13702 case 32:
13703 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13704 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13705 DMA_RWCTRL_WRITE_BNDRY_32);
13706 break;
13707 }
13708 /* fallthrough */
13709 case 64:
13710 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13711 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13712 DMA_RWCTRL_WRITE_BNDRY_64);
13713 break;
13714 }
13715 /* fallthrough */
13716 case 128:
13717 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13718 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13719 DMA_RWCTRL_WRITE_BNDRY_128);
13720 break;
13721 }
13722 /* fallthrough */
13723 case 256:
13724 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13725 DMA_RWCTRL_WRITE_BNDRY_256);
13726 break;
13727 case 512:
13728 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13729 DMA_RWCTRL_WRITE_BNDRY_512);
13730 break;
13731 case 1024:
13732 default:
13733 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13734 DMA_RWCTRL_WRITE_BNDRY_1024);
13735 break;
855e1111 13736 }
59e6b434
DM		 13737 }
13738
13739out:
13740 return val;
13741}
13742
1da177e4
LT		 13743static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13744{
13745 struct tg3_internal_buffer_desc test_desc;
13746 u32 sram_dma_descs;
13747 int i, ret;
13748
13749 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13750
13751 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13752 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13753 tw32(RDMAC_STATUS, 0);
13754 tw32(WDMAC_STATUS, 0);
13755
13756 tw32(BUFMGR_MODE, 0);
13757 tw32(FTQ_RESET, 0);
13758
13759 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13760 test_desc.addr_lo = buf_dma & 0xffffffff;
13761 test_desc.nic_mbuf = 0x00002100;
13762 test_desc.len = size;
13763
13764 /*
13765 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13766 * the *second* time the tg3 driver was getting loaded after an
13767 * initial scan.
13768 *
13769 * Broadcom tells me:
13770 * ...the DMA engine is connected to the GRC block and a DMA
13771 * reset may affect the GRC block in some unpredictable way...
13772 * The behavior of resets to individual blocks has not been tested.
13773 *
13774 * Broadcom noted the GRC reset will also reset all sub-components.
13775 */
13776 if (to_device) {
13777 test_desc.cqid_sqid = (13 << 8) | 2;
13778
13779 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13780 udelay(40);
13781 } else {
13782 test_desc.cqid_sqid = (16 << 8) | 7;
13783
13784 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13785 udelay(40);
13786 }
13787 test_desc.flags = 0x00000005;
13788
13789 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13790 u32 val;
13791
13792 val = *(((u32 *)&test_desc) + i);
13793 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13794 sram_dma_descs + (i * sizeof(u32)));
13795 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13796 }
13797 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13798
13799 if (to_device) {
13800 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13801 } else {
13802 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13803 }
13804
13805 ret = -ENODEV;
13806 for (i = 0; i < 40; i++) {
13807 u32 val;
13808
13809 if (to_device)
13810 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13811 else
13812 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13813 if ((val & 0xffff) == sram_dma_descs) {
13814 ret = 0;
13815 break;
13816 }
13817
13818 udelay(100);
13819 }
13820
13821 return ret;
13822}
13823
ded7340d 13824#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13825
13826static int __devinit tg3_test_dma(struct tg3 *tp)
13827{
13828 dma_addr_t buf_dma;
59e6b434 13829 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13830 int ret = 0;
1da177e4
LT		 13831
13832 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13833 if (!buf) {
13834 ret = -ENOMEM;
13835 goto out_nofree;
13836 }
13837
13838 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13839 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13840
59e6b434 13841 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13842
cbf9ca6c
MC		 13843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13844 goto out;
13845
1da177e4
LT		 13846 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13847 /* DMA read watermark not used on PCIE */
13848 tp->dma_rwctrl |= 0x00180000;
13849 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13852 tp->dma_rwctrl |= 0x003f0000;
13853 else
13854 tp->dma_rwctrl |= 0x003f000f;
13855 } else {
13856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13858 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13859 u32 read_water = 0x7;
1da177e4 13860
4a29cc2e
MC		 13861 /* If the 5704 is behind the EPB bridge, we can
13862 * do the less restrictive ONE_DMA workaround for
13863 * better performance.
13864 */
13865 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13867 tp->dma_rwctrl |= 0x8000;
13868 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13869 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13870
49afdeb6
MC		 13871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13872 read_water = 4;
59e6b434 13873 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13874 tp->dma_rwctrl |=
13875 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13876 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13877 (1 << 23);
4cf78e4f
MC		 13878 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13879 /* 5780 always in PCIX mode */
13880 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13881 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13882 /* 5714 always in PCIX mode */
13883 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13884 } else {
13885 tp->dma_rwctrl |= 0x001b000f;
13886 }
13887 }
13888
13889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13891 tp->dma_rwctrl &= 0xfffffff0;
13892
13893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13894 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13895 /* Remove this if it causes problems for some boards. */
13896 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13897
13898 /* On 5700/5701 chips, we need to set this bit.
13899 * Otherwise the chip will issue cacheline transactions
13900 * to streamable DMA memory with not all the byte
13901 * enables turned on. This is an error on several
13902 * RISC PCI controllers, in particular sparc64.
13903 *
13904 * On 5703/5704 chips, this bit has been reassigned
13905 * a different meaning. In particular, it is used
13906 * on those chips to enable a PCI-X workaround.
13907 */
13908 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13909 }
13910
13911 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13912
13913#if 0
13914 /* Unneeded, already done by tg3_get_invariants. */
13915 tg3_switch_clocks(tp);
13916#endif
13917
1da177e4
LT		 13918 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13919 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13920 goto out;
13921
59e6b434
DM		 13922 /* It is best to perform DMA test with maximum write burst size
13923 * to expose the 5700/5701 write DMA bug.
13924 */
13925 saved_dma_rwctrl = tp->dma_rwctrl;
13926 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13927 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13928
1da177e4
LT		 13929 while (1) {
13930 u32 *p = buf, i;
13931
13932 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13933 p[i] = i;
13934
13935 /* Send the buffer to the chip. */
13936 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13937 if (ret) {
13938 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13939 break;
13940 }
13941
13942#if 0
13943 /* validate data reached card RAM correctly. */
13944 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13945 u32 val;
13946 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13947 if (le32_to_cpu(val) != p[i]) {
13948 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13949 /* ret = -ENODEV here? */
13950 }
13951 p[i] = 0;
13952 }
13953#endif
13954 /* Now read it back. */
13955 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13956 if (ret) {
13957 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13958
13959 break;
13960 }
13961
13962 /* Verify it. */
13963 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13964 if (p[i] == i)
13965 continue;
13966
59e6b434
DM		 13967 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13968 DMA_RWCTRL_WRITE_BNDRY_16) {
13969 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13970 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13971 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13972 break;
13973 } else {
13974 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13975 ret = -ENODEV;
13976 goto out;
13977 }
13978 }
13979
13980 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13981 /* Success. */
13982 ret = 0;
13983 break;
13984 }
13985 }
59e6b434
DM		 13986 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13987 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13988 static struct pci_device_id dma_wait_state_chipsets[] = {
13989 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13990 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13991 { },
13992 };
13993
59e6b434 13994 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13995 * now look for chipsets that are known to expose the
13996 * DMA bug without failing the test.
59e6b434 13997 */
6d1cfbab
MC		 13998 if (pci_dev_present(dma_wait_state_chipsets)) {
13999 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14000 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14001 }
14002 else
14003 /* Safe to use the calculated DMA boundary. */
14004 tp->dma_rwctrl = saved_dma_rwctrl;
14005
59e6b434
DM		 14006 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14007 }
1da177e4
LT		 14008
14009out:
14010 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14011out_nofree:
14012 return ret;
14013}
14014
14015static void __devinit tg3_init_link_config(struct tg3 *tp)
14016{
14017 tp->link_config.advertising =
14018 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14019 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14020 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14021 ADVERTISED_Autoneg | ADVERTISED_MII);
14022 tp->link_config.speed = SPEED_INVALID;
14023 tp->link_config.duplex = DUPLEX_INVALID;
14024 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 14025 tp->link_config.active_speed = SPEED_INVALID;
14026 tp->link_config.active_duplex = DUPLEX_INVALID;
14027 tp->link_config.phy_is_low_power = 0;
14028 tp->link_config.orig_speed = SPEED_INVALID;
14029 tp->link_config.orig_duplex = DUPLEX_INVALID;
14030 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14031}
14032
14033static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14034{
f6eb9b1f
MC		 14035 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
14036 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 14037 tp->bufmgr_config.mbuf_read_dma_low_water =
14038 DEFAULT_MB_RDMA_LOW_WATER_5705;
14039 tp->bufmgr_config.mbuf_mac_rx_low_water =
14040 DEFAULT_MB_MACRX_LOW_WATER_5705;
14041 tp->bufmgr_config.mbuf_high_water =
14042 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 14043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14044 tp->bufmgr_config.mbuf_mac_rx_low_water =
14045 DEFAULT_MB_MACRX_LOW_WATER_5906;
14046 tp->bufmgr_config.mbuf_high_water =
14047 DEFAULT_MB_HIGH_WATER_5906;
14048 }
fdfec172
MC		 14049
14050 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14051 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14052 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14053 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14054 tp->bufmgr_config.mbuf_high_water_jumbo =
14055 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14056 } else {
14057 tp->bufmgr_config.mbuf_read_dma_low_water =
14058 DEFAULT_MB_RDMA_LOW_WATER;
14059 tp->bufmgr_config.mbuf_mac_rx_low_water =
14060 DEFAULT_MB_MACRX_LOW_WATER;
14061 tp->bufmgr_config.mbuf_high_water =
14062 DEFAULT_MB_HIGH_WATER;
14063
14064 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14065 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14066 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14067 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14068 tp->bufmgr_config.mbuf_high_water_jumbo =
14069 DEFAULT_MB_HIGH_WATER_JUMBO;
14070 }
1da177e4
LT		 14071
14072 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14073 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14074}
14075
14076static char * __devinit tg3_phy_string(struct tg3 *tp)
14077{
14078 switch (tp->phy_id & PHY_ID_MASK) {
14079 case PHY_ID_BCM5400: return "5400";
14080 case PHY_ID_BCM5401: return "5401";
14081 case PHY_ID_BCM5411: return "5411";
14082 case PHY_ID_BCM5701: return "5701";
14083 case PHY_ID_BCM5703: return "5703";
14084 case PHY_ID_BCM5704: return "5704";
14085 case PHY_ID_BCM5705: return "5705";
14086 case PHY_ID_BCM5750: return "5750";
85e94ced 14087 case PHY_ID_BCM5752: return "5752";
a4e2b347 14088 case PHY_ID_BCM5714: return "5714";
4cf78e4f 14089 case PHY_ID_BCM5780: return "5780";
af36e6b6 14090 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 14091 case PHY_ID_BCM5787: return "5787";
d30cdd28 14092 case PHY_ID_BCM5784: return "5784";
126a3368 14093 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 14094 case PHY_ID_BCM5906: return "5906";
9936bcf6 14095 case PHY_ID_BCM5761: return "5761";
c2060fe1 14096 case PHY_ID_BCM5717: return "5717";
1da177e4
LT		 14097 case PHY_ID_BCM8002: return "8002/serdes";
14098 case 0: return "serdes";
14099 default: return "unknown";
855e1111 14100 }
1da177e4
LT		 14101}
14102
f9804ddb
MC		 14103static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14104{
14105 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14106 strcpy(str, "PCI Express");
14107 return str;
14108 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14109 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14110
14111 strcpy(str, "PCIX:");
14112
14113 if ((clock_ctrl == 7) ||
14114 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14115 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14116 strcat(str, "133MHz");
14117 else if (clock_ctrl == 0)
14118 strcat(str, "33MHz");
14119 else if (clock_ctrl == 2)
14120 strcat(str, "50MHz");
14121 else if (clock_ctrl == 4)
14122 strcat(str, "66MHz");
14123 else if (clock_ctrl == 6)
14124 strcat(str, "100MHz");
f9804ddb
MC		 14125 } else {
14126 strcpy(str, "PCI:");
14127 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14128 strcat(str, "66MHz");
14129 else
14130 strcat(str, "33MHz");
14131 }
14132 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14133 strcat(str, ":32-bit");
14134 else
14135 strcat(str, ":64-bit");
14136 return str;
14137}
14138
8c2dc7e1 14139static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 14140{
14141 struct pci_dev *peer;
14142 unsigned int func, devnr = tp->pdev->devfn & ~7;
14143
14144 for (func = 0; func < 8; func++) {
14145 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14146 if (peer && peer != tp->pdev)
14147 break;
14148 pci_dev_put(peer);
14149 }
16fe9d74
MC		 14150 /* 5704 can be configured in single-port mode, set peer to
14151 * tp->pdev in that case.
14152 */
14153 if (!peer) {
14154 peer = tp->pdev;
14155 return peer;
14156 }
1da177e4
LT		 14157
14158 /*
14159 * We don't need to keep the refcount elevated; there's no way
14160 * to remove one half of this device without removing the other
14161 */
14162 pci_dev_put(peer);
14163
14164 return peer;
14165}
14166
15f9850d
DM		 14167static void __devinit tg3_init_coal(struct tg3 *tp)
14168{
14169 struct ethtool_coalesce *ec = &tp->coal;
14170
14171 memset(ec, 0, sizeof(*ec));
14172 ec->cmd = ETHTOOL_GCOALESCE;
14173 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14174 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14175 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14176 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14177 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14178 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14179 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14180 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14181 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14182
14183 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14184 HOSTCC_MODE_CLRTICK_TXBD)) {
14185 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14186 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14187 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14188 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14189 }
d244c892
MC		 14190
14191 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14192 ec->rx_coalesce_usecs_irq = 0;
14193 ec->tx_coalesce_usecs_irq = 0;
14194 ec->stats_block_coalesce_usecs = 0;
14195 }
15f9850d
DM		 14196}
14197
7c7d64b8
SH		 14198static const struct net_device_ops tg3_netdev_ops = {
14199 .ndo_open = tg3_open,
14200 .ndo_stop = tg3_close,
00829823
SH		 14201 .ndo_start_xmit = tg3_start_xmit,
14202 .ndo_get_stats = tg3_get_stats,
14203 .ndo_validate_addr = eth_validate_addr,
14204 .ndo_set_multicast_list = tg3_set_rx_mode,
14205 .ndo_set_mac_address = tg3_set_mac_addr,
14206 .ndo_do_ioctl = tg3_ioctl,
14207 .ndo_tx_timeout = tg3_tx_timeout,
14208 .ndo_change_mtu = tg3_change_mtu,
14209#if TG3_VLAN_TAG_USED
14210 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14211#endif
14212#ifdef CONFIG_NET_POLL_CONTROLLER
14213 .ndo_poll_controller = tg3_poll_controller,
14214#endif
14215};
14216
14217static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14218 .ndo_open = tg3_open,
14219 .ndo_stop = tg3_close,
14220 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 14221 .ndo_get_stats = tg3_get_stats,
14222 .ndo_validate_addr = eth_validate_addr,
14223 .ndo_set_multicast_list = tg3_set_rx_mode,
14224 .ndo_set_mac_address = tg3_set_mac_addr,
14225 .ndo_do_ioctl = tg3_ioctl,
14226 .ndo_tx_timeout = tg3_tx_timeout,
14227 .ndo_change_mtu = tg3_change_mtu,
14228#if TG3_VLAN_TAG_USED
14229 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14230#endif
14231#ifdef CONFIG_NET_POLL_CONTROLLER
14232 .ndo_poll_controller = tg3_poll_controller,
14233#endif
14234};
14235
1da177e4
LT		 14236static int __devinit tg3_init_one(struct pci_dev *pdev,
14237 const struct pci_device_id *ent)
14238{
14239 static int tg3_version_printed = 0;
1da177e4
LT		 14240 struct net_device *dev;
14241 struct tg3 *tp;
646c9edd
MC		 14242 int i, err, pm_cap;
14243 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14244 char str[40];
72f2afb8 14245 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14246
14247 if (tg3_version_printed++ == 0)
14248 printk(KERN_INFO "%s", version);
14249
14250 err = pci_enable_device(pdev);
14251 if (err) {
14252 printk(KERN_ERR PFX "Cannot enable PCI device, "
14253 "aborting.\n");
14254 return err;
14255 }
14256
1da177e4
LT		 14257 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14258 if (err) {
14259 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14260 "aborting.\n");
14261 goto err_out_disable_pdev;
14262 }
14263
14264 pci_set_master(pdev);
14265
14266 /* Find power-management capability. */
14267 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14268 if (pm_cap == 0) {
14269 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14270 "aborting.\n");
14271 err = -EIO;
14272 goto err_out_free_res;
14273 }
14274
fe5f5787 14275 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14276 if (!dev) {
14277 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14278 err = -ENOMEM;
14279 goto err_out_free_res;
14280 }
14281
1da177e4
LT		 14282 SET_NETDEV_DEV(dev, &pdev->dev);
14283
1da177e4
LT		 14284#if TG3_VLAN_TAG_USED
14285 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14286#endif
14287
14288 tp = netdev_priv(dev);
14289 tp->pdev = pdev;
14290 tp->dev = dev;
14291 tp->pm_cap = pm_cap;
1da177e4
LT		 14292 tp->rx_mode = TG3_DEF_RX_MODE;
14293 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14294
1da177e4
LT		 14295 if (tg3_debug > 0)
14296 tp->msg_enable = tg3_debug;
14297 else
14298 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14299
14300 /* The word/byte swap controls here control register access byte
14301 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14302 * setting below.
14303 */
14304 tp->misc_host_ctrl =
14305 MISC_HOST_CTRL_MASK_PCI_INT |
14306 MISC_HOST_CTRL_WORD_SWAP |
14307 MISC_HOST_CTRL_INDIR_ACCESS |
14308 MISC_HOST_CTRL_PCISTATE_RW;
14309
14310 /* The NONFRM (non-frame) byte/word swap controls take effect
14311 * on descriptor entries, anything which isn't packet data.
14312 *
14313 * The StrongARM chips on the board (one for tx, one for rx)
14314 * are running in big-endian mode.
14315 */
14316 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14317 GRC_MODE_WSWAP_NONFRM_DATA);
14318#ifdef __BIG_ENDIAN
14319 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14320#endif
14321 spin_lock_init(&tp->lock);
1da177e4 14322 spin_lock_init(&tp->indirect_lock);
c4028958 14323 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14324
d5fe488a 14325 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14326 if (!tp->regs) {
1da177e4
LT		 14327 printk(KERN_ERR PFX "Cannot map device registers, "
14328 "aborting.\n");
14329 err = -ENOMEM;
14330 goto err_out_free_dev;
14331 }
14332
14333 tg3_init_link_config(tp);
14334
1da177e4
LT		 14335 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14336 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14337
1da177e4 14338 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14339 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14340 dev->irq = pdev->irq;
1da177e4
LT		 14341
14342 err = tg3_get_invariants(tp);
14343 if (err) {
14344 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14345 "aborting.\n");
14346 goto err_out_iounmap;
14347 }
14348
615774fe
MC		 14349 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14350 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14351 dev->netdev_ops = &tg3_netdev_ops;
14352 else
14353 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14354
14355
4a29cc2e
MC		 14356 /* The EPB bridge inside 5714, 5715, and 5780 and any
14357 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14358 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14359 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14360 * do DMA address check in tg3_start_xmit().
14361 */
4a29cc2e 14362 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14363 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14364 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14365 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14366#ifdef CONFIG_HIGHMEM
6a35528a 14367 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14368#endif
4a29cc2e 14369 } else
6a35528a 14370 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14371
14372 /* Configure DMA attributes. */
284901a9 14373 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14374 err = pci_set_dma_mask(pdev, dma_mask);
14375 if (!err) {
14376 dev->features |= NETIF_F_HIGHDMA;
14377 err = pci_set_consistent_dma_mask(pdev,
14378 persist_dma_mask);
14379 if (err < 0) {
14380 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14381 "DMA for consistent allocations\n");
14382 goto err_out_iounmap;
14383 }
14384 }
14385 }
284901a9
YH		 14386 if (err || dma_mask == DMA_BIT_MASK(32)) {
14387 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14388 if (err) {
14389 printk(KERN_ERR PFX "No usable DMA configuration, "
14390 "aborting.\n");
14391 goto err_out_iounmap;
14392 }
14393 }
14394
fdfec172 14395 tg3_init_bufmgr_config(tp);
1da177e4 14396
507399f1
MC		 14397 /* Selectively allow TSO based on operating conditions */
14398 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14399 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14400 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14401 else {
14402 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14403 tp->fw_needed = NULL;
1da177e4 14404 }
507399f1
MC		 14405
14406 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14407 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14408
4e3a7aaa
MC		 14409 /* TSO is on by default on chips that support hardware TSO.
14410 * Firmware TSO on older chips gives lower performance, so it
14411 * is off by default, but can be enabled using ethtool.
14412 */
e849cdc3
MC		 14413 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14414 (dev->features & NETIF_F_IP_CSUM))
14415 dev->features |= NETIF_F_TSO;
14416
14417 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14418 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14419 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14420 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14421 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14422 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14423 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14424 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14427 dev->features |= NETIF_F_TSO_ECN;
b0026624 14428 }
1da177e4 14429
1da177e4
LT		 14430 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14431 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14432 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14433 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14434 tp->rx_pending = 63;
14435 }
14436
1da177e4
LT		 14437 err = tg3_get_device_address(tp);
14438 if (err) {
14439 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14440 "aborting.\n");
077f849d 14441 goto err_out_fw;
1da177e4
LT		 14442 }
14443
c88864df 14444 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14445 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14446 if (!tp->aperegs) {
c88864df
MC		 14447 printk(KERN_ERR PFX "Cannot map APE registers, "
14448 "aborting.\n");
14449 err = -ENOMEM;
077f849d 14450 goto err_out_fw;
c88864df
MC		 14451 }
14452
14453 tg3_ape_lock_init(tp);
7fd76445
MC		 14454
14455 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14456 tg3_read_dash_ver(tp);
c88864df
MC		 14457 }
14458
1da177e4
LT		 14459 /*
14460 * Reset chip in case UNDI or EFI driver did not shutdown
14461 * DMA self test will enable WDMAC and we'll see (spurious)
14462 * pending DMA on the PCI bus at that point.
14463 */
14464 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14465 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14466 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14467 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14468 }
14469
14470 err = tg3_test_dma(tp);
14471 if (err) {
14472 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14473 goto err_out_apeunmap;
1da177e4
LT		 14474 }
14475
1da177e4
LT		 14476 /* flow control autonegotiation is default behavior */
14477 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14478 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14479
78f90dcf
MC		 14480 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14481 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14482 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14483 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14484 struct tg3_napi *tnapi = &tp->napi[i];
14485
14486 tnapi->tp = tp;
14487 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14488
14489 tnapi->int_mbox = intmbx;
14490 if (i < 4)
14491 intmbx += 0x8;
14492 else
14493 intmbx += 0x4;
14494
14495 tnapi->consmbox = rcvmbx;
14496 tnapi->prodmbox = sndmbx;
14497
14498 if (i) {
14499 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14500 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14501 } else {
14502 tnapi->coal_now = HOSTCC_MODE_NOW;
14503 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14504 }
14505
14506 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14507 break;
14508
14509 /*
14510 * If we support MSIX, we'll be using RSS. If we're using
14511 * RSS, the first vector only handles link interrupts and the
14512 * remaining vectors handle rx and tx interrupts. Reuse the
14513 * mailbox values for the next iteration. The values we setup
14514 * above are still useful for the single vectored mode.
14515 */
14516 if (!i)
14517 continue;
14518
14519 rcvmbx += 0x8;
14520
14521 if (sndmbx & 0x4)
14522 sndmbx -= 0x4;
14523 else
14524 sndmbx += 0xc;
14525 }
14526
15f9850d
DM		 14527 tg3_init_coal(tp);
14528
c49a1561
MC		 14529 pci_set_drvdata(pdev, dev);
14530
1da177e4
LT		 14531 err = register_netdev(dev);
14532 if (err) {
14533 printk(KERN_ERR PFX "Cannot register net device, "
14534 "aborting.\n");
0d3031d9 14535 goto err_out_apeunmap;
1da177e4
LT		 14536 }
14537
df59c940 14538 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14539 dev->name,
14540 tp->board_part_number,
14541 tp->pci_chip_rev_id,
f9804ddb 14542 tg3_bus_string(tp, str),
e174961c 14543 dev->dev_addr);
1da177e4 14544
3f0e3ad7
MC		 14545 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14546 struct phy_device *phydev;
14547 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14548 printk(KERN_INFO
14549 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14550 tp->dev->name, phydev->drv->name,
14551 dev_name(&phydev->dev));
14552 } else
df59c940
MC		 14553 printk(KERN_INFO
14554 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14555 tp->dev->name, tg3_phy_string(tp),
14556 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14557 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14558 "10/100/1000Base-T")),
14559 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14560
14561 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14562 dev->name,
14563 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14564 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14565 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14566 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14567 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14568 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14569 dev->name, tp->dma_rwctrl,
284901a9 14570 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14571 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14572
14573 return 0;
14574
0d3031d9
MC		 14575err_out_apeunmap:
14576 if (tp->aperegs) {
14577 iounmap(tp->aperegs);
14578 tp->aperegs = NULL;
14579 }
14580
077f849d
JSR		 14581err_out_fw:
14582 if (tp->fw)
14583 release_firmware(tp->fw);
14584
1da177e4 14585err_out_iounmap:
6892914f
MC		 14586 if (tp->regs) {
14587 iounmap(tp->regs);
22abe310 14588 tp->regs = NULL;
6892914f 14589 }
1da177e4
LT		 14590
14591err_out_free_dev:
14592 free_netdev(dev);
14593
14594err_out_free_res:
14595 pci_release_regions(pdev);
14596
14597err_out_disable_pdev:
14598 pci_disable_device(pdev);
14599 pci_set_drvdata(pdev, NULL);
14600 return err;
14601}
14602
14603static void __devexit tg3_remove_one(struct pci_dev *pdev)
14604{
14605 struct net_device *dev = pci_get_drvdata(pdev);
14606
14607 if (dev) {
14608 struct tg3 *tp = netdev_priv(dev);
14609
077f849d
JSR		 14610 if (tp->fw)
14611 release_firmware(tp->fw);
14612
7faa006f 14613 flush_scheduled_work();
158d7abd 14614
b02fd9e3
MC		 14615 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14616 tg3_phy_fini(tp);
158d7abd 14617 tg3_mdio_fini(tp);
b02fd9e3 14618 }
158d7abd 14619
1da177e4 14620 unregister_netdev(dev);
0d3031d9
MC		 14621 if (tp->aperegs) {
14622 iounmap(tp->aperegs);
14623 tp->aperegs = NULL;
14624 }
6892914f
MC		 14625 if (tp->regs) {
14626 iounmap(tp->regs);
22abe310 14627 tp->regs = NULL;
6892914f 14628 }
1da177e4
LT		 14629 free_netdev(dev);
14630 pci_release_regions(pdev);
14631 pci_disable_device(pdev);
14632 pci_set_drvdata(pdev, NULL);
14633 }
14634}
14635
14636static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14637{
14638 struct net_device *dev = pci_get_drvdata(pdev);
14639 struct tg3 *tp = netdev_priv(dev);
12dac075 14640 pci_power_t target_state;
1da177e4
LT		 14641 int err;
14642
3e0c95fd
MC		 14643 /* PCI register 4 needs to be saved whether netif_running() or not.
14644 * MSI address and data need to be saved if using MSI and
14645 * netif_running().
14646 */
14647 pci_save_state(pdev);
14648
1da177e4
LT		 14649 if (!netif_running(dev))
14650 return 0;
14651
7faa006f 14652 flush_scheduled_work();
b02fd9e3 14653 tg3_phy_stop(tp);
1da177e4
LT		 14654 tg3_netif_stop(tp);
14655
14656 del_timer_sync(&tp->timer);
14657
f47c11ee 14658 tg3_full_lock(tp, 1);
1da177e4 14659 tg3_disable_ints(tp);
f47c11ee 14660 tg3_full_unlock(tp);
1da177e4
LT		 14661
14662 netif_device_detach(dev);
14663
f47c11ee 14664 tg3_full_lock(tp, 0);
944d980e 14665 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14666 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14667 tg3_full_unlock(tp);
1da177e4 14668
12dac075
RW		 14669 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14670
14671 err = tg3_set_power_state(tp, target_state);
1da177e4 14672 if (err) {
b02fd9e3
MC		 14673 int err2;
14674
f47c11ee 14675 tg3_full_lock(tp, 0);
1da177e4 14676
6a9eba15 14677 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14678 err2 = tg3_restart_hw(tp, 1);
14679 if (err2)
b9ec6c1b 14680 goto out;
1da177e4
LT		 14681
14682 tp->timer.expires = jiffies + tp->timer_offset;
14683 add_timer(&tp->timer);
14684
14685 netif_device_attach(dev);
14686 tg3_netif_start(tp);
14687
b9ec6c1b 14688out:
f47c11ee 14689 tg3_full_unlock(tp);
b02fd9e3
MC		 14690
14691 if (!err2)
14692 tg3_phy_start(tp);
1da177e4
LT		 14693 }
14694
14695 return err;
14696}
14697
14698static int tg3_resume(struct pci_dev *pdev)
14699{
14700 struct net_device *dev = pci_get_drvdata(pdev);
14701 struct tg3 *tp = netdev_priv(dev);
14702 int err;
14703
3e0c95fd
MC		 14704 pci_restore_state(tp->pdev);
14705
1da177e4
LT		 14706 if (!netif_running(dev))
14707 return 0;
14708
bc1c7567 14709 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14710 if (err)
14711 return err;
14712
14713 netif_device_attach(dev);
14714
f47c11ee 14715 tg3_full_lock(tp, 0);
1da177e4 14716
6a9eba15 14717 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14718 err = tg3_restart_hw(tp, 1);
14719 if (err)
14720 goto out;
1da177e4
LT		 14721
14722 tp->timer.expires = jiffies + tp->timer_offset;
14723 add_timer(&tp->timer);
14724
1da177e4
LT		 14725 tg3_netif_start(tp);
14726
b9ec6c1b 14727out:
f47c11ee 14728 tg3_full_unlock(tp);
1da177e4 14729
b02fd9e3
MC		 14730 if (!err)
14731 tg3_phy_start(tp);
14732
b9ec6c1b 14733 return err;
1da177e4
LT		 14734}
14735
14736static struct pci_driver tg3_driver = {
14737 .name = DRV_MODULE_NAME,
14738 .id_table = tg3_pci_tbl,
14739 .probe = tg3_init_one,
14740 .remove = __devexit_p(tg3_remove_one),
14741 .suspend = tg3_suspend,
14742 .resume = tg3_resume
14743};
14744
14745static int __init tg3_init(void)
14746{
29917620 14747 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14748}
14749
14750static void __exit tg3_cleanup(void)
14751{
14752 pci_unregister_driver(&tg3_driver);
14753}
14754
14755module_init(tg3_init);
14756module_exit(tg3_cleanup);
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