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tg3: Lay proucer ring handling groundwork
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
123b43e9
MC		 71#define DRV_MODULE_VERSION "3.103"
72#define DRV_MODULE_RELDATE "November 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 139
2b2cdb65
MC		 140#define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142
143#define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145
1da177e4 146/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 147#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 148
ad829268
MC		 149#define TG3_RAW_IP_ALIGN 2
150
1da177e4
LT		 151/* number of ETHTOOL_GSTATS u64's */
152#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
153
4cafd3f5
MC		 154#define TG3_NUM_TEST 6
155
077f849d
JSR		 156#define FIRMWARE_TG3 "tigon/tg3.bin"
157#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
159
1da177e4
LT		 160static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
162
163MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165MODULE_LICENSE("GPL");
166MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 167MODULE_FIRMWARE(FIRMWARE_TG3);
168MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
170
679563f4 171#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 172
173static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174module_param(tg3_debug, int, 0);
175MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
176
177static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 244 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
245 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
246 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
247 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
248 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
250 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
251 {}
1da177e4
LT		 252};
253
254MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
255
50da859d 256static const struct {
1da177e4
LT		 257 const char string[ETH_GSTRING_LEN];
258} ethtool_stats_keys[TG3_NUM_STATS] = {
259 { "rx_octets" },
260 { "rx_fragments" },
261 { "rx_ucast_packets" },
262 { "rx_mcast_packets" },
263 { "rx_bcast_packets" },
264 { "rx_fcs_errors" },
265 { "rx_align_errors" },
266 { "rx_xon_pause_rcvd" },
267 { "rx_xoff_pause_rcvd" },
268 { "rx_mac_ctrl_rcvd" },
269 { "rx_xoff_entered" },
270 { "rx_frame_too_long_errors" },
271 { "rx_jabbers" },
272 { "rx_undersize_packets" },
273 { "rx_in_length_errors" },
274 { "rx_out_length_errors" },
275 { "rx_64_or_less_octet_packets" },
276 { "rx_65_to_127_octet_packets" },
277 { "rx_128_to_255_octet_packets" },
278 { "rx_256_to_511_octet_packets" },
279 { "rx_512_to_1023_octet_packets" },
280 { "rx_1024_to_1522_octet_packets" },
281 { "rx_1523_to_2047_octet_packets" },
282 { "rx_2048_to_4095_octet_packets" },
283 { "rx_4096_to_8191_octet_packets" },
284 { "rx_8192_to_9022_octet_packets" },
285
286 { "tx_octets" },
287 { "tx_collisions" },
288
289 { "tx_xon_sent" },
290 { "tx_xoff_sent" },
291 { "tx_flow_control" },
292 { "tx_mac_errors" },
293 { "tx_single_collisions" },
294 { "tx_mult_collisions" },
295 { "tx_deferred" },
296 { "tx_excessive_collisions" },
297 { "tx_late_collisions" },
298 { "tx_collide_2times" },
299 { "tx_collide_3times" },
300 { "tx_collide_4times" },
301 { "tx_collide_5times" },
302 { "tx_collide_6times" },
303 { "tx_collide_7times" },
304 { "tx_collide_8times" },
305 { "tx_collide_9times" },
306 { "tx_collide_10times" },
307 { "tx_collide_11times" },
308 { "tx_collide_12times" },
309 { "tx_collide_13times" },
310 { "tx_collide_14times" },
311 { "tx_collide_15times" },
312 { "tx_ucast_packets" },
313 { "tx_mcast_packets" },
314 { "tx_bcast_packets" },
315 { "tx_carrier_sense_errors" },
316 { "tx_discards" },
317 { "tx_errors" },
318
319 { "dma_writeq_full" },
320 { "dma_write_prioq_full" },
321 { "rxbds_empty" },
322 { "rx_discards" },
323 { "rx_errors" },
324 { "rx_threshold_hit" },
325
326 { "dma_readq_full" },
327 { "dma_read_prioq_full" },
328 { "tx_comp_queue_full" },
329
330 { "ring_set_send_prod_index" },
331 { "ring_status_update" },
332 { "nic_irqs" },
333 { "nic_avoided_irqs" },
334 { "nic_tx_threshold_hit" }
335};
336
50da859d 337static const struct {
4cafd3f5
MC		 338 const char string[ETH_GSTRING_LEN];
339} ethtool_test_keys[TG3_NUM_TEST] = {
340 { "nvram test (online) " },
341 { "link test (online) " },
342 { "register test (offline)" },
343 { "memory test (offline)" },
344 { "loopback test (offline)" },
345 { "interrupt test (offline)" },
346};
347
b401e9e2
MC		 348static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
349{
350 writel(val, tp->regs + off);
351}
352
353static u32 tg3_read32(struct tg3 *tp, u32 off)
354{
6aa20a22 355 return (readl(tp->regs + off));
b401e9e2
MC		 356}
357
0d3031d9
MC		 358static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
359{
360 writel(val, tp->aperegs + off);
361}
362
363static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
364{
365 return (readl(tp->aperegs + off));
366}
367
1da177e4
LT		 368static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
369{
6892914f
MC		 370 unsigned long flags;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 376}
377
378static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
379{
380 writel(val, tp->regs + off);
381 readl(tp->regs + off);
1da177e4
LT		 382}
383
6892914f 384static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 385{
6892914f
MC		 386 unsigned long flags;
387 u32 val;
388
389 spin_lock_irqsave(&tp->indirect_lock, flags);
390 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
391 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
392 spin_unlock_irqrestore(&tp->indirect_lock, flags);
393 return val;
394}
395
396static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
397{
398 unsigned long flags;
399
400 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
401 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
402 TG3_64BIT_REG_LOW, val);
403 return;
404 }
405 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
406 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
407 TG3_64BIT_REG_LOW, val);
408 return;
1da177e4 409 }
6892914f
MC		 410
411 spin_lock_irqsave(&tp->indirect_lock, flags);
412 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
413 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
414 spin_unlock_irqrestore(&tp->indirect_lock, flags);
415
416 /* In indirect mode when disabling interrupts, we also need
417 * to clear the interrupt bit in the GRC local ctrl register.
418 */
419 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
420 (val == 0x1)) {
421 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
422 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
423 }
424}
425
426static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
427{
428 unsigned long flags;
429 u32 val;
430
431 spin_lock_irqsave(&tp->indirect_lock, flags);
432 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
433 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
434 spin_unlock_irqrestore(&tp->indirect_lock, flags);
435 return val;
436}
437
b401e9e2
MC		 438/* usec_wait specifies the wait time in usec when writing to certain registers
439 * where it is unsafe to read back the register without some delay.
440 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
441 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
442 */
443static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 444{
b401e9e2
MC		 445 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
446 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
447 /* Non-posted methods */
448 tp->write32(tp, off, val);
449 else {
450 /* Posted method */
451 tg3_write32(tp, off, val);
452 if (usec_wait)
453 udelay(usec_wait);
454 tp->read32(tp, off);
455 }
456 /* Wait again after the read for the posted method to guarantee that
457 * the wait time is met.
458 */
459 if (usec_wait)
460 udelay(usec_wait);
1da177e4
LT		 461}
462
09ee929c
MC		 463static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
464{
465 tp->write32_mbox(tp, off, val);
6892914f
MC		 466 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
467 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
468 tp->read32_mbox(tp, off);
09ee929c
MC		 469}
470
20094930 471static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 472{
473 void __iomem *mbox = tp->regs + off;
474 writel(val, mbox);
475 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
476 writel(val, mbox);
477 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
478 readl(mbox);
479}
480
b5d3772c
MC		 481static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
482{
483 return (readl(tp->regs + off + GRCMBOX_BASE));
484}
485
486static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
487{
488 writel(val, tp->regs + off + GRCMBOX_BASE);
489}
490
20094930 491#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 492#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 493#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
494#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 495#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 496
497#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 498#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
499#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 500#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 501
502static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
503{
6892914f
MC		 504 unsigned long flags;
505
b5d3772c
MC		 506 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
507 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
508 return;
509
6892914f 510 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 511 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
512 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
513 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 } else {
518 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
519 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 520
bbadf503
MC		 521 /* Always leave this as zero. */
522 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
523 }
524 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 525}
526
1da177e4
LT		 527static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
528{
6892914f
MC		 529 unsigned long flags;
530
b5d3772c
MC		 531 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
532 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
533 *val = 0;
534 return;
535 }
536
6892914f 537 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 538 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
539 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
540 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 541
bbadf503
MC		 542 /* Always leave this as zero. */
543 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 } else {
545 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
546 *val = tr32(TG3PCI_MEM_WIN_DATA);
547
548 /* Always leave this as zero. */
549 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
550 }
6892914f 551 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 552}
553
0d3031d9
MC		 554static void tg3_ape_lock_init(struct tg3 *tp)
555{
556 int i;
557
558 /* Make sure the driver hasn't any stale locks. */
559 for (i = 0; i < 8; i++)
560 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
561 APE_LOCK_GRANT_DRIVER);
562}
563
564static int tg3_ape_lock(struct tg3 *tp, int locknum)
565{
566 int i, off;
567 int ret = 0;
568 u32 status;
569
570 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
571 return 0;
572
573 switch (locknum) {
77b483f1 574 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 575 case TG3_APE_LOCK_MEM:
576 break;
577 default:
578 return -EINVAL;
579 }
580
581 off = 4 * locknum;
582
583 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
584
585 /* Wait for up to 1 millisecond to acquire lock. */
586 for (i = 0; i < 100; i++) {
587 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
588 if (status == APE_LOCK_GRANT_DRIVER)
589 break;
590 udelay(10);
591 }
592
593 if (status != APE_LOCK_GRANT_DRIVER) {
594 /* Revoke the lock request. */
595 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
596 APE_LOCK_GRANT_DRIVER);
597
598 ret = -EBUSY;
599 }
600
601 return ret;
602}
603
604static void tg3_ape_unlock(struct tg3 *tp, int locknum)
605{
606 int off;
607
608 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
609 return;
610
611 switch (locknum) {
77b483f1 612 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 613 case TG3_APE_LOCK_MEM:
614 break;
615 default:
616 return;
617 }
618
619 off = 4 * locknum;
620 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
621}
622
1da177e4
LT		 623static void tg3_disable_ints(struct tg3 *tp)
624{
89aeb3bc
MC		 625 int i;
626
1da177e4
LT		 627 tw32(TG3PCI_MISC_HOST_CTRL,
628 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 629 for (i = 0; i < tp->irq_max; i++)
630 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 631}
632
1da177e4
LT		 633static void tg3_enable_ints(struct tg3 *tp)
634{
89aeb3bc
MC		 635 int i;
636 u32 coal_now = 0;
637
bbe832c0
MC		 638 tp->irq_sync = 0;
639 wmb();
640
1da177e4
LT		 641 tw32(TG3PCI_MISC_HOST_CTRL,
642 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 643
644 for (i = 0; i < tp->irq_cnt; i++) {
645 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 646 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 647 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
648 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 649
89aeb3bc
MC		 650 coal_now |= tnapi->coal_now;
651 }
f19af9c2
MC		 652
653 /* Force an initial interrupt */
654 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
655 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
656 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
657 else
658 tw32(HOSTCC_MODE, tp->coalesce_mode |
659 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 660}
661
17375d25 662static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 663{
17375d25 664 struct tg3 *tp = tnapi->tp;
898a56f8 665 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 666 unsigned int work_exists = 0;
667
668 /* check for phy events */
669 if (!(tp->tg3_flags &
670 (TG3_FLAG_USE_LINKCHG_REG |
671 TG3_FLAG_POLL_SERDES))) {
672 if (sblk->status & SD_STATUS_LINK_CHG)
673 work_exists = 1;
674 }
675 /* check for RX/TX work to do */
f3f3f27e 676 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 677 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 678 work_exists = 1;
679
680 return work_exists;
681}
682
17375d25 683/* tg3_int_reenable
04237ddd
MC		 684 * similar to tg3_enable_ints, but it accurately determines whether there
685 * is new work pending and can return without flushing the PIO write
6aa20a22 686 * which reenables interrupts
1da177e4 687 */
17375d25 688static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 689{
17375d25
MC		 690 struct tg3 *tp = tnapi->tp;
691
898a56f8 692 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 693 mmiowb();
694
fac9b83e
DM		 695 /* When doing tagged status, this work check is unnecessary.
696 * The last_tag we write above tells the chip which piece of
697 * work we've completed.
698 */
699 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 700 tg3_has_work(tnapi))
04237ddd 701 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 702 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 703}
704
fed97810
MC		 705static void tg3_napi_disable(struct tg3 *tp)
706{
707 int i;
708
709 for (i = tp->irq_cnt - 1; i >= 0; i--)
710 napi_disable(&tp->napi[i].napi);
711}
712
713static void tg3_napi_enable(struct tg3 *tp)
714{
715 int i;
716
717 for (i = 0; i < tp->irq_cnt; i++)
718 napi_enable(&tp->napi[i].napi);
719}
720
1da177e4
LT		 721static inline void tg3_netif_stop(struct tg3 *tp)
722{
bbe832c0 723 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 724 tg3_napi_disable(tp);
1da177e4
LT		 725 netif_tx_disable(tp->dev);
726}
727
728static inline void tg3_netif_start(struct tg3 *tp)
729{
fe5f5787
MC		 730 /* NOTE: unconditional netif_tx_wake_all_queues is only
731 * appropriate so long as all callers are assured to
732 * have free tx slots (such as after tg3_init_hw)
1da177e4 733 */
fe5f5787
MC		 734 netif_tx_wake_all_queues(tp->dev);
735
fed97810
MC		 736 tg3_napi_enable(tp);
737 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 738 tg3_enable_ints(tp);
1da177e4
LT		 739}
740
741static void tg3_switch_clocks(struct tg3 *tp)
742{
f6eb9b1f 743 u32 clock_ctrl;
1da177e4
LT		 744 u32 orig_clock_ctrl;
745
795d01c5
MC		 746 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
747 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 748 return;
749
f6eb9b1f
MC		 750 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
751
1da177e4
LT		 752 orig_clock_ctrl = clock_ctrl;
753 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
754 CLOCK_CTRL_CLKRUN_OENABLE |
755 0x1f);
756 tp->pci_clock_ctrl = clock_ctrl;
757
758 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
759 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 760 tw32_wait_f(TG3PCI_CLOCK_CTRL,
761 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 762 }
763 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 764 tw32_wait_f(TG3PCI_CLOCK_CTRL,
765 clock_ctrl |
766 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
767 40);
768 tw32_wait_f(TG3PCI_CLOCK_CTRL,
769 clock_ctrl | (CLOCK_CTRL_ALTCLK),
770 40);
1da177e4 771 }
b401e9e2 772 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 773}
774
775#define PHY_BUSY_LOOPS 5000
776
777static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
778{
779 u32 frame_val;
780 unsigned int loops;
781 int ret;
782
783 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
784 tw32_f(MAC_MI_MODE,
785 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
786 udelay(80);
787 }
788
789 *val = 0x0;
790
882e9793 791 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 792 MI_COM_PHY_ADDR_MASK);
793 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
794 MI_COM_REG_ADDR_MASK);
795 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 796
1da177e4
LT		 797 tw32_f(MAC_MI_COM, frame_val);
798
799 loops = PHY_BUSY_LOOPS;
800 while (loops != 0) {
801 udelay(10);
802 frame_val = tr32(MAC_MI_COM);
803
804 if ((frame_val & MI_COM_BUSY) == 0) {
805 udelay(5);
806 frame_val = tr32(MAC_MI_COM);
807 break;
808 }
809 loops -= 1;
810 }
811
812 ret = -EBUSY;
813 if (loops != 0) {
814 *val = frame_val & MI_COM_DATA_MASK;
815 ret = 0;
816 }
817
818 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
819 tw32_f(MAC_MI_MODE, tp->mi_mode);
820 udelay(80);
821 }
822
823 return ret;
824}
825
826static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
827{
828 u32 frame_val;
829 unsigned int loops;
830 int ret;
831
7f97a4bd 832 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 833 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
834 return 0;
835
1da177e4
LT		 836 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
837 tw32_f(MAC_MI_MODE,
838 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
839 udelay(80);
840 }
841
882e9793 842 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 843 MI_COM_PHY_ADDR_MASK);
844 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
845 MI_COM_REG_ADDR_MASK);
846 frame_val |= (val & MI_COM_DATA_MASK);
847 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 848
1da177e4
LT		 849 tw32_f(MAC_MI_COM, frame_val);
850
851 loops = PHY_BUSY_LOOPS;
852 while (loops != 0) {
853 udelay(10);
854 frame_val = tr32(MAC_MI_COM);
855 if ((frame_val & MI_COM_BUSY) == 0) {
856 udelay(5);
857 frame_val = tr32(MAC_MI_COM);
858 break;
859 }
860 loops -= 1;
861 }
862
863 ret = -EBUSY;
864 if (loops != 0)
865 ret = 0;
866
867 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
868 tw32_f(MAC_MI_MODE, tp->mi_mode);
869 udelay(80);
870 }
871
872 return ret;
873}
874
95e2869a
MC		 875static int tg3_bmcr_reset(struct tg3 *tp)
876{
877 u32 phy_control;
878 int limit, err;
879
880 /* OK, reset it, and poll the BMCR_RESET bit until it
881 * clears or we time out.
882 */
883 phy_control = BMCR_RESET;
884 err = tg3_writephy(tp, MII_BMCR, phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 limit = 5000;
889 while (limit--) {
890 err = tg3_readphy(tp, MII_BMCR, &phy_control);
891 if (err != 0)
892 return -EBUSY;
893
894 if ((phy_control & BMCR_RESET) == 0) {
895 udelay(40);
896 break;
897 }
898 udelay(10);
899 }
d4675b52 900 if (limit < 0)
95e2869a
MC		 901 return -EBUSY;
902
903 return 0;
904}
905
158d7abd
MC		 906static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
907{
3d16543d 908 struct tg3 *tp = bp->priv;
158d7abd
MC		 909 u32 val;
910
24bb4fb6 911 spin_lock_bh(&tp->lock);
158d7abd
MC		 912
913 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 914 val = -EIO;
915
916 spin_unlock_bh(&tp->lock);
158d7abd
MC		 917
918 return val;
919}
920
921static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
922{
3d16543d 923 struct tg3 *tp = bp->priv;
24bb4fb6 924 u32 ret = 0;
158d7abd 925
24bb4fb6 926 spin_lock_bh(&tp->lock);
158d7abd
MC		 927
928 if (tg3_writephy(tp, reg, val))
24bb4fb6 929 ret = -EIO;
158d7abd 930
24bb4fb6
MC		 931 spin_unlock_bh(&tp->lock);
932
933 return ret;
158d7abd
MC		 934}
935
936static int tg3_mdio_reset(struct mii_bus *bp)
937{
938 return 0;
939}
940
9c61d6bc 941static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 942{
943 u32 val;
fcb389df 944 struct phy_device *phydev;
a9daf367 945
3f0e3ad7 946 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 947 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
948 case TG3_PHY_ID_BCM50610:
c73430d0 949 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 950 val = MAC_PHYCFG2_50610_LED_MODES;
951 break;
952 case TG3_PHY_ID_BCMAC131:
953 val = MAC_PHYCFG2_AC131_LED_MODES;
954 break;
955 case TG3_PHY_ID_RTL8211C:
956 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
957 break;
958 case TG3_PHY_ID_RTL8201E:
959 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
960 break;
961 default:
a9daf367 962 return;
fcb389df
MC		 963 }
964
965 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
966 tw32(MAC_PHYCFG2, val);
967
968 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 969 val &= ~(MAC_PHYCFG1_RGMII_INT |
970 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
971 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 972 tw32(MAC_PHYCFG1, val);
973
974 return;
975 }
976
977 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
978 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
979 MAC_PHYCFG2_FMODE_MASK_MASK |
980 MAC_PHYCFG2_GMODE_MASK_MASK |
981 MAC_PHYCFG2_ACT_MASK_MASK |
982 MAC_PHYCFG2_QUAL_MASK_MASK |
983 MAC_PHYCFG2_INBAND_ENABLE;
984
985 tw32(MAC_PHYCFG2, val);
a9daf367 986
bb85fbb6
MC		 987 val = tr32(MAC_PHYCFG1);
988 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
989 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
990 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 991 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
992 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
993 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
994 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
995 }
bb85fbb6
MC		 996 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
997 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
998 tw32(MAC_PHYCFG1, val);
a9daf367 999
a9daf367
MC		 1000 val = tr32(MAC_EXT_RGMII_MODE);
1001 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1002 MAC_RGMII_MODE_RX_QUALITY |
1003 MAC_RGMII_MODE_RX_ACTIVITY |
1004 MAC_RGMII_MODE_RX_ENG_DET |
1005 MAC_RGMII_MODE_TX_ENABLE |
1006 MAC_RGMII_MODE_TX_LOWPWR |
1007 MAC_RGMII_MODE_TX_RESET);
fcb389df 1008 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1009 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1010 val |= MAC_RGMII_MODE_RX_INT_B |
1011 MAC_RGMII_MODE_RX_QUALITY |
1012 MAC_RGMII_MODE_RX_ACTIVITY |
1013 MAC_RGMII_MODE_RX_ENG_DET;
1014 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1015 val |= MAC_RGMII_MODE_TX_ENABLE |
1016 MAC_RGMII_MODE_TX_LOWPWR |
1017 MAC_RGMII_MODE_TX_RESET;
1018 }
1019 tw32(MAC_EXT_RGMII_MODE, val);
1020}
1021
158d7abd
MC		 1022static void tg3_mdio_start(struct tg3 *tp)
1023{
158d7abd
MC		 1024 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1025 tw32_f(MAC_MI_MODE, tp->mi_mode);
1026 udelay(80);
a9daf367 1027
882e9793
MC		 1028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1029 u32 funcnum, is_serdes;
1030
1031 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1032 if (funcnum)
1033 tp->phy_addr = 2;
1034 else
1035 tp->phy_addr = 1;
1036
1037 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1038 if (is_serdes)
1039 tp->phy_addr += 7;
1040 } else
3f0e3ad7 1041 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1042
9c61d6bc
MC		 1043 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1045 tg3_mdio_config_5785(tp);
158d7abd
MC		 1046}
1047
158d7abd
MC		 1048static int tg3_mdio_init(struct tg3 *tp)
1049{
1050 int i;
1051 u32 reg;
a9daf367 1052 struct phy_device *phydev;
158d7abd
MC		 1053
1054 tg3_mdio_start(tp);
1055
1056 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1057 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1058 return 0;
1059
298cf9be
LB		 1060 tp->mdio_bus = mdiobus_alloc();
1061 if (tp->mdio_bus == NULL)
1062 return -ENOMEM;
158d7abd 1063
298cf9be
LB		 1064 tp->mdio_bus->name = "tg3 mdio bus";
1065 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1066 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1067 tp->mdio_bus->priv = tp;
1068 tp->mdio_bus->parent = &tp->pdev->dev;
1069 tp->mdio_bus->read = &tg3_mdio_read;
1070 tp->mdio_bus->write = &tg3_mdio_write;
1071 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1072 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1073 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1074
1075 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1076 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1077
1078 /* The bus registration will look for all the PHYs on the mdio bus.
1079 * Unfortunately, it does not ensure the PHY is powered up before
1080 * accessing the PHY ID registers. A chip reset is the
1081 * quickest way to bring the device back to an operational state..
1082 */
1083 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1084 tg3_bmcr_reset(tp);
1085
298cf9be 1086 i = mdiobus_register(tp->mdio_bus);
a9daf367 1087 if (i) {
158d7abd
MC		 1088 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1089 tp->dev->name, i);
9c61d6bc 1090 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1091 return i;
1092 }
158d7abd 1093
3f0e3ad7 1094 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1095
9c61d6bc
MC		 1096 if (!phydev || !phydev->drv) {
1097 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1098 mdiobus_unregister(tp->mdio_bus);
1099 mdiobus_free(tp->mdio_bus);
1100 return -ENODEV;
1101 }
1102
1103 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1104 case TG3_PHY_ID_BCM57780:
1105 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1106 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1107 break;
a9daf367 1108 case TG3_PHY_ID_BCM50610:
c73430d0 1109 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1110 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1111 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1112 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1113 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1114 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1115 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1116 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1117 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1118 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1119 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1120 /* fallthru */
1121 case TG3_PHY_ID_RTL8211C:
1122 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1123 break;
fcb389df 1124 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1125 case TG3_PHY_ID_BCMAC131:
1126 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1127 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1128 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1129 break;
1130 }
1131
9c61d6bc
MC		 1132 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1133
1134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1135 tg3_mdio_config_5785(tp);
a9daf367
MC		 1136
1137 return 0;
158d7abd
MC		 1138}
1139
1140static void tg3_mdio_fini(struct tg3 *tp)
1141{
1142 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1143 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1144 mdiobus_unregister(tp->mdio_bus);
1145 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1146 }
1147}
1148
4ba526ce
MC		 1149/* tp->lock is held. */
1150static inline void tg3_generate_fw_event(struct tg3 *tp)
1151{
1152 u32 val;
1153
1154 val = tr32(GRC_RX_CPU_EVENT);
1155 val |= GRC_RX_CPU_DRIVER_EVENT;
1156 tw32_f(GRC_RX_CPU_EVENT, val);
1157
1158 tp->last_event_jiffies = jiffies;
1159}
1160
1161#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1162
95e2869a
MC		 1163/* tp->lock is held. */
1164static void tg3_wait_for_event_ack(struct tg3 *tp)
1165{
1166 int i;
4ba526ce
MC		 1167 unsigned int delay_cnt;
1168 long time_remain;
1169
1170 /* If enough time has passed, no wait is necessary. */
1171 time_remain = (long)(tp->last_event_jiffies + 1 +
1172 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1173 (long)jiffies;
1174 if (time_remain < 0)
1175 return;
1176
1177 /* Check if we can shorten the wait time. */
1178 delay_cnt = jiffies_to_usecs(time_remain);
1179 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1180 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1181 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1182
4ba526ce 1183 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1184 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1185 break;
4ba526ce 1186 udelay(8);
95e2869a
MC		 1187 }
1188}
1189
1190/* tp->lock is held. */
1191static void tg3_ump_link_report(struct tg3 *tp)
1192{
1193 u32 reg;
1194 u32 val;
1195
1196 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1197 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1198 return;
1199
1200 tg3_wait_for_event_ack(tp);
1201
1202 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1203
1204 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1205
1206 val = 0;
1207 if (!tg3_readphy(tp, MII_BMCR, &reg))
1208 val = reg << 16;
1209 if (!tg3_readphy(tp, MII_BMSR, &reg))
1210 val |= (reg & 0xffff);
1211 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1212
1213 val = 0;
1214 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1215 val = reg << 16;
1216 if (!tg3_readphy(tp, MII_LPA, &reg))
1217 val |= (reg & 0xffff);
1218 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1219
1220 val = 0;
1221 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1222 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1223 val = reg << 16;
1224 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1225 val |= (reg & 0xffff);
1226 }
1227 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1228
1229 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1230 val = reg << 16;
1231 else
1232 val = 0;
1233 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1234
4ba526ce 1235 tg3_generate_fw_event(tp);
95e2869a
MC		 1236}
1237
1238static void tg3_link_report(struct tg3 *tp)
1239{
1240 if (!netif_carrier_ok(tp->dev)) {
1241 if (netif_msg_link(tp))
1242 printk(KERN_INFO PFX "%s: Link is down.\n",
1243 tp->dev->name);
1244 tg3_ump_link_report(tp);
1245 } else if (netif_msg_link(tp)) {
1246 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1247 tp->dev->name,
1248 (tp->link_config.active_speed == SPEED_1000 ?
1249 1000 :
1250 (tp->link_config.active_speed == SPEED_100 ?
1251 100 : 10)),
1252 (tp->link_config.active_duplex == DUPLEX_FULL ?
1253 "full" : "half"));
1254
1255 printk(KERN_INFO PFX
1256 "%s: Flow control is %s for TX and %s for RX.\n",
1257 tp->dev->name,
e18ce346 1258 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1259 "on" : "off",
e18ce346 1260 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1261 "on" : "off");
1262 tg3_ump_link_report(tp);
1263 }
1264}
1265
1266static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1267{
1268 u16 miireg;
1269
e18ce346 1270 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1271 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1272 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1273 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1274 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1275 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1276 else
1277 miireg = 0;
1278
1279 return miireg;
1280}
1281
1282static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1283{
1284 u16 miireg;
1285
e18ce346 1286 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1287 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1288 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1289 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1290 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1291 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1292 else
1293 miireg = 0;
1294
1295 return miireg;
1296}
1297
95e2869a
MC		 1298static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1299{
1300 u8 cap = 0;
1301
1302 if (lcladv & ADVERTISE_1000XPAUSE) {
1303 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1304 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1305 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1306 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1307 cap = FLOW_CTRL_RX;
95e2869a
MC		 1308 } else {
1309 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1310 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1311 }
1312 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1313 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1314 cap = FLOW_CTRL_TX;
95e2869a
MC		 1315 }
1316
1317 return cap;
1318}
1319
f51f3562 1320static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1321{
b02fd9e3 1322 u8 autoneg;
f51f3562 1323 u8 flowctrl = 0;
95e2869a
MC		 1324 u32 old_rx_mode = tp->rx_mode;
1325 u32 old_tx_mode = tp->tx_mode;
1326
b02fd9e3 1327 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1328 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1329 else
1330 autoneg = tp->link_config.autoneg;
1331
1332 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1333 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1334 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1335 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1336 else
bc02ff95 1337 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1338 } else
1339 flowctrl = tp->link_config.flowctrl;
95e2869a 1340
f51f3562 1341 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1342
e18ce346 1343 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1344 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1345 else
1346 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1347
f51f3562 1348 if (old_rx_mode != tp->rx_mode)
95e2869a 1349 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1350
e18ce346 1351 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1352 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1353 else
1354 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1355
f51f3562 1356 if (old_tx_mode != tp->tx_mode)
95e2869a 1357 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1358}
1359
b02fd9e3
MC		 1360static void tg3_adjust_link(struct net_device *dev)
1361{
1362 u8 oldflowctrl, linkmesg = 0;
1363 u32 mac_mode, lcl_adv, rmt_adv;
1364 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1365 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1366
24bb4fb6 1367 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1368
1369 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1370 MAC_MODE_HALF_DUPLEX);
1371
1372 oldflowctrl = tp->link_config.active_flowctrl;
1373
1374 if (phydev->link) {
1375 lcl_adv = 0;
1376 rmt_adv = 0;
1377
1378 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1379 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1380 else if (phydev->speed == SPEED_1000 ||
1381 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1382 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1383 else
1384 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1385
1386 if (phydev->duplex == DUPLEX_HALF)
1387 mac_mode |= MAC_MODE_HALF_DUPLEX;
1388 else {
1389 lcl_adv = tg3_advert_flowctrl_1000T(
1390 tp->link_config.flowctrl);
1391
1392 if (phydev->pause)
1393 rmt_adv = LPA_PAUSE_CAP;
1394 if (phydev->asym_pause)
1395 rmt_adv |= LPA_PAUSE_ASYM;
1396 }
1397
1398 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1399 } else
1400 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1401
1402 if (mac_mode != tp->mac_mode) {
1403 tp->mac_mode = mac_mode;
1404 tw32_f(MAC_MODE, tp->mac_mode);
1405 udelay(40);
1406 }
1407
fcb389df
MC		 1408 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1409 if (phydev->speed == SPEED_10)
1410 tw32(MAC_MI_STAT,
1411 MAC_MI_STAT_10MBPS_MODE |
1412 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1413 else
1414 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1415 }
1416
b02fd9e3
MC		 1417 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1418 tw32(MAC_TX_LENGTHS,
1419 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1420 (6 << TX_LENGTHS_IPG_SHIFT) |
1421 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1422 else
1423 tw32(MAC_TX_LENGTHS,
1424 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1425 (6 << TX_LENGTHS_IPG_SHIFT) |
1426 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1427
1428 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1429 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1430 phydev->speed != tp->link_config.active_speed ||
1431 phydev->duplex != tp->link_config.active_duplex ||
1432 oldflowctrl != tp->link_config.active_flowctrl)
1433 linkmesg = 1;
1434
1435 tp->link_config.active_speed = phydev->speed;
1436 tp->link_config.active_duplex = phydev->duplex;
1437
24bb4fb6 1438 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1439
1440 if (linkmesg)
1441 tg3_link_report(tp);
1442}
1443
1444static int tg3_phy_init(struct tg3 *tp)
1445{
1446 struct phy_device *phydev;
1447
1448 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1449 return 0;
1450
1451 /* Bring the PHY back to a known state. */
1452 tg3_bmcr_reset(tp);
1453
3f0e3ad7 1454 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1455
1456 /* Attach the MAC to the PHY. */
fb28ad35 1457 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1458 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1459 if (IS_ERR(phydev)) {
1460 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1461 return PTR_ERR(phydev);
1462 }
1463
b02fd9e3 1464 /* Mask with MAC supported features. */
9c61d6bc
MC		 1465 switch (phydev->interface) {
1466 case PHY_INTERFACE_MODE_GMII:
1467 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1468 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1469 phydev->supported &= (PHY_GBIT_FEATURES |
1470 SUPPORTED_Pause |
1471 SUPPORTED_Asym_Pause);
1472 break;
1473 }
1474 /* fallthru */
9c61d6bc
MC		 1475 case PHY_INTERFACE_MODE_MII:
1476 phydev->supported &= (PHY_BASIC_FEATURES |
1477 SUPPORTED_Pause |
1478 SUPPORTED_Asym_Pause);
1479 break;
1480 default:
3f0e3ad7 1481 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1482 return -EINVAL;
1483 }
1484
1485 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1486
1487 phydev->advertising = phydev->supported;
1488
b02fd9e3
MC		 1489 return 0;
1490}
1491
1492static void tg3_phy_start(struct tg3 *tp)
1493{
1494 struct phy_device *phydev;
1495
1496 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1497 return;
1498
3f0e3ad7 1499 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1500
1501 if (tp->link_config.phy_is_low_power) {
1502 tp->link_config.phy_is_low_power = 0;
1503 phydev->speed = tp->link_config.orig_speed;
1504 phydev->duplex = tp->link_config.orig_duplex;
1505 phydev->autoneg = tp->link_config.orig_autoneg;
1506 phydev->advertising = tp->link_config.orig_advertising;
1507 }
1508
1509 phy_start(phydev);
1510
1511 phy_start_aneg(phydev);
1512}
1513
1514static void tg3_phy_stop(struct tg3 *tp)
1515{
1516 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1517 return;
1518
3f0e3ad7 1519 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1520}
1521
1522static void tg3_phy_fini(struct tg3 *tp)
1523{
1524 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1525 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1526 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1527 }
1528}
1529
b2a5c19c
MC		 1530static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1531{
1532 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1533 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1534}
1535
7f97a4bd
MC		 1536static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1537{
1538 u32 phytest;
1539
1540 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1541 u32 phy;
1542
1543 tg3_writephy(tp, MII_TG3_FET_TEST,
1544 phytest | MII_TG3_FET_SHADOW_EN);
1545 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1546 if (enable)
1547 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1548 else
1549 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1550 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1551 }
1552 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1553 }
1554}
1555
6833c043
MC		 1556static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1557{
1558 u32 reg;
1559
7f97a4bd 1560 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1561 return;
1562
7f97a4bd
MC		 1563 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1564 tg3_phy_fet_toggle_apd(tp, enable);
1565 return;
1566 }
1567
6833c043
MC		 1568 reg = MII_TG3_MISC_SHDW_WREN |
1569 MII_TG3_MISC_SHDW_SCR5_SEL |
1570 MII_TG3_MISC_SHDW_SCR5_LPED |
1571 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1572 MII_TG3_MISC_SHDW_SCR5_SDTL |
1573 MII_TG3_MISC_SHDW_SCR5_C125OE;
1574 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1575 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1576
1577 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1578
1579
1580 reg = MII_TG3_MISC_SHDW_WREN |
1581 MII_TG3_MISC_SHDW_APD_SEL |
1582 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1583 if (enable)
1584 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1585
1586 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1587}
1588
9ef8ca99
MC		 1589static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1590{
1591 u32 phy;
1592
1593 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1594 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1595 return;
1596
7f97a4bd 1597 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1598 u32 ephy;
1599
535ef6e1
MC		 1600 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1601 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1602
1603 tg3_writephy(tp, MII_TG3_FET_TEST,
1604 ephy | MII_TG3_FET_SHADOW_EN);
1605 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1606 if (enable)
535ef6e1 1607 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1608 else
535ef6e1
MC		 1609 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1610 tg3_writephy(tp, reg, phy);
9ef8ca99 1611 }
535ef6e1 1612 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1613 }
1614 } else {
1615 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1616 MII_TG3_AUXCTL_SHDWSEL_MISC;
1617 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1618 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1619 if (enable)
1620 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1621 else
1622 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1623 phy |= MII_TG3_AUXCTL_MISC_WREN;
1624 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1625 }
1626 }
1627}
1628
1da177e4
LT		 1629static void tg3_phy_set_wirespeed(struct tg3 *tp)
1630{
1631 u32 val;
1632
1633 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1634 return;
1635
1636 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1637 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1638 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1639 (val | (1 << 15) | (1 << 4)));
1640}
1641
b2a5c19c
MC		 1642static void tg3_phy_apply_otp(struct tg3 *tp)
1643{
1644 u32 otp, phy;
1645
1646 if (!tp->phy_otp)
1647 return;
1648
1649 otp = tp->phy_otp;
1650
1651 /* Enable SM_DSP clock and tx 6dB coding. */
1652 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1653 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1654 MII_TG3_AUXCTL_ACTL_TX_6DB;
1655 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1656
1657 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1658 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1659 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1660
1661 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1662 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1663 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1664
1665 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1666 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1667 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1668
1669 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1670 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1671
1672 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1673 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1674
1675 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1676 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1677 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1678
1679 /* Turn off SM_DSP clock. */
1680 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1681 MII_TG3_AUXCTL_ACTL_TX_6DB;
1682 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1683}
1684
1da177e4
LT		 1685static int tg3_wait_macro_done(struct tg3 *tp)
1686{
1687 int limit = 100;
1688
1689 while (limit--) {
1690 u32 tmp32;
1691
1692 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1693 if ((tmp32 & 0x1000) == 0)
1694 break;
1695 }
1696 }
d4675b52 1697 if (limit < 0)
1da177e4
LT		 1698 return -EBUSY;
1699
1700 return 0;
1701}
1702
1703static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1704{
1705 static const u32 test_pat[4][6] = {
1706 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1707 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1708 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1709 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1710 };
1711 int chan;
1712
1713 for (chan = 0; chan < 4; chan++) {
1714 int i;
1715
1716 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1717 (chan * 0x2000) | 0x0200);
1718 tg3_writephy(tp, 0x16, 0x0002);
1719
1720 for (i = 0; i < 6; i++)
1721 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1722 test_pat[chan][i]);
1723
1724 tg3_writephy(tp, 0x16, 0x0202);
1725 if (tg3_wait_macro_done(tp)) {
1726 *resetp = 1;
1727 return -EBUSY;
1728 }
1729
1730 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1731 (chan * 0x2000) | 0x0200);
1732 tg3_writephy(tp, 0x16, 0x0082);
1733 if (tg3_wait_macro_done(tp)) {
1734 *resetp = 1;
1735 return -EBUSY;
1736 }
1737
1738 tg3_writephy(tp, 0x16, 0x0802);
1739 if (tg3_wait_macro_done(tp)) {
1740 *resetp = 1;
1741 return -EBUSY;
1742 }
1743
1744 for (i = 0; i < 6; i += 2) {
1745 u32 low, high;
1746
1747 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1748 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1749 tg3_wait_macro_done(tp)) {
1750 *resetp = 1;
1751 return -EBUSY;
1752 }
1753 low &= 0x7fff;
1754 high &= 0x000f;
1755 if (low != test_pat[chan][i] ||
1756 high != test_pat[chan][i+1]) {
1757 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1758 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1759 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1760
1761 return -EBUSY;
1762 }
1763 }
1764 }
1765
1766 return 0;
1767}
1768
1769static int tg3_phy_reset_chanpat(struct tg3 *tp)
1770{
1771 int chan;
1772
1773 for (chan = 0; chan < 4; chan++) {
1774 int i;
1775
1776 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1777 (chan * 0x2000) | 0x0200);
1778 tg3_writephy(tp, 0x16, 0x0002);
1779 for (i = 0; i < 6; i++)
1780 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1781 tg3_writephy(tp, 0x16, 0x0202);
1782 if (tg3_wait_macro_done(tp))
1783 return -EBUSY;
1784 }
1785
1786 return 0;
1787}
1788
1789static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1790{
1791 u32 reg32, phy9_orig;
1792 int retries, do_phy_reset, err;
1793
1794 retries = 10;
1795 do_phy_reset = 1;
1796 do {
1797 if (do_phy_reset) {
1798 err = tg3_bmcr_reset(tp);
1799 if (err)
1800 return err;
1801 do_phy_reset = 0;
1802 }
1803
1804 /* Disable transmitter and interrupt. */
1805 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1806 continue;
1807
1808 reg32 |= 0x3000;
1809 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1810
1811 /* Set full-duplex, 1000 mbps. */
1812 tg3_writephy(tp, MII_BMCR,
1813 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1814
1815 /* Set to master mode. */
1816 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1817 continue;
1818
1819 tg3_writephy(tp, MII_TG3_CTRL,
1820 (MII_TG3_CTRL_AS_MASTER |
1821 MII_TG3_CTRL_ENABLE_AS_MASTER));
1822
1823 /* Enable SM_DSP_CLOCK and 6dB. */
1824 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1825
1826 /* Block the PHY control access. */
1827 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1828 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1829
1830 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1831 if (!err)
1832 break;
1833 } while (--retries);
1834
1835 err = tg3_phy_reset_chanpat(tp);
1836 if (err)
1837 return err;
1838
1839 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1840 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1841
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1843 tg3_writephy(tp, 0x16, 0x0000);
1844
1845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1847 /* Set Extended packet length bit for jumbo frames */
1848 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1849 }
1850 else {
1851 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1852 }
1853
1854 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1855
1856 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1857 reg32 &= ~0x3000;
1858 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1859 } else if (!err)
1860 err = -EBUSY;
1861
1862 return err;
1863}
1864
1865/* This will reset the tigon3 PHY if there is no valid
1866 * link unless the FORCE argument is non-zero.
1867 */
1868static int tg3_phy_reset(struct tg3 *tp)
1869{
b2a5c19c 1870 u32 cpmuctrl;
1da177e4
LT		 1871 u32 phy_status;
1872 int err;
1873
60189ddf
MC		 1874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1875 u32 val;
1876
1877 val = tr32(GRC_MISC_CFG);
1878 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1879 udelay(40);
1880 }
1da177e4
LT		 1881 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1882 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1883 if (err != 0)
1884 return -EBUSY;
1885
c8e1e82b
MC		 1886 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1887 netif_carrier_off(tp->dev);
1888 tg3_link_report(tp);
1889 }
1890
1da177e4
LT		 1891 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1894 err = tg3_phy_reset_5703_4_5(tp);
1895 if (err)
1896 return err;
1897 goto out;
1898 }
1899
b2a5c19c
MC		 1900 cpmuctrl = 0;
1901 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1902 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1903 cpmuctrl = tr32(TG3_CPMU_CTRL);
1904 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1905 tw32(TG3_CPMU_CTRL,
1906 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1907 }
1908
1da177e4
LT		 1909 err = tg3_bmcr_reset(tp);
1910 if (err)
1911 return err;
1912
b2a5c19c
MC		 1913 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1914 u32 phy;
1915
1916 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1917 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1918
1919 tw32(TG3_CPMU_CTRL, cpmuctrl);
1920 }
1921
bcb37f6c
MC		 1922 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1923 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1924 u32 val;
1925
1926 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1927 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1928 CPMU_LSPD_1000MB_MACCLK_12_5) {
1929 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1930 udelay(40);
1931 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1932 }
1933 }
1934
b2a5c19c
MC		 1935 tg3_phy_apply_otp(tp);
1936
6833c043
MC		 1937 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1938 tg3_phy_toggle_apd(tp, true);
1939 else
1940 tg3_phy_toggle_apd(tp, false);
1941
1da177e4
LT		 1942out:
1943 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1944 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1945 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1946 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1947 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1948 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1949 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1950 }
1951 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1952 tg3_writephy(tp, 0x1c, 0x8d68);
1953 tg3_writephy(tp, 0x1c, 0x8d68);
1954 }
1955 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1956 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1957 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1958 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1959 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1960 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1961 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1962 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1964 }
c424cb24
MC		 1965 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1966 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1967 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1968 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1969 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1970 tg3_writephy(tp, MII_TG3_TEST1,
1971 MII_TG3_TEST1_TRIM_EN | 0x4);
1972 } else
1973 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1974 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1975 }
1da177e4
LT		 1976 /* Set Extended packet length bit (bit 14) on all chips that */
1977 /* support jumbo frames */
1978 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1979 /* Cannot do read-modify-write on 5401 */
1980 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1981 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1982 u32 phy_reg;
1983
1984 /* Set bit 14 with read-modify-write to preserve other bits */
1985 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1986 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1987 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1988 }
1989
1990 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1991 * jumbo frames transmission.
1992 */
8f666b07 1993 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1994 u32 phy_reg;
1995
1996 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1997 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1998 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1999 }
2000
715116a1 2001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 2002 /* adjust output voltage */
535ef6e1 2003 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2004 }
2005
9ef8ca99 2006 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2007 tg3_phy_set_wirespeed(tp);
2008 return 0;
2009}
2010
2011static void tg3_frob_aux_power(struct tg3 *tp)
2012{
2013 struct tg3 *tp_peer = tp;
2014
9d26e213 2015 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2016 return;
2017
f6eb9b1f
MC		 2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2020 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2021 struct net_device *dev_peer;
2022
2023 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2024 /* remove_one() may have been run on the peer. */
8c2dc7e1 2025 if (!dev_peer)
bc1c7567
MC		 2026 tp_peer = tp;
2027 else
2028 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2029 }
2030
1da177e4 2031 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2032 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2033 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2034 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2037 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2038 (GRC_LCLCTRL_GPIO_OE0 |
2039 GRC_LCLCTRL_GPIO_OE1 |
2040 GRC_LCLCTRL_GPIO_OE2 |
2041 GRC_LCLCTRL_GPIO_OUTPUT0 |
2042 GRC_LCLCTRL_GPIO_OUTPUT1),
2043 100);
8d519ab2
MC		 2044 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2045 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2046 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2047 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2048 GRC_LCLCTRL_GPIO_OE1 |
2049 GRC_LCLCTRL_GPIO_OE2 |
2050 GRC_LCLCTRL_GPIO_OUTPUT0 |
2051 GRC_LCLCTRL_GPIO_OUTPUT1 |
2052 tp->grc_local_ctrl;
2053 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2054
2055 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2056 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2057
2058 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2059 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2060 } else {
2061 u32 no_gpio2;
dc56b7d4 2062 u32 grc_local_ctrl = 0;
1da177e4
LT		 2063
2064 if (tp_peer != tp &&
2065 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2066 return;
2067
dc56b7d4
MC		 2068 /* Workaround to prevent overdrawing Amps. */
2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2070 ASIC_REV_5714) {
2071 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2072 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2073 grc_local_ctrl, 100);
dc56b7d4
MC		 2074 }
2075
1da177e4
LT		 2076 /* On 5753 and variants, GPIO2 cannot be used. */
2077 no_gpio2 = tp->nic_sram_data_cfg &
2078 NIC_SRAM_DATA_CFG_NO_GPIO2;
2079
dc56b7d4 2080 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2081 GRC_LCLCTRL_GPIO_OE1 |
2082 GRC_LCLCTRL_GPIO_OE2 |
2083 GRC_LCLCTRL_GPIO_OUTPUT1 |
2084 GRC_LCLCTRL_GPIO_OUTPUT2;
2085 if (no_gpio2) {
2086 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2087 GRC_LCLCTRL_GPIO_OUTPUT2);
2088 }
b401e9e2
MC		 2089 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090 grc_local_ctrl, 100);
1da177e4
LT		 2091
2092 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2093
b401e9e2
MC		 2094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095 grc_local_ctrl, 100);
1da177e4
LT		 2096
2097 if (!no_gpio2) {
2098 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2099 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2100 grc_local_ctrl, 100);
1da177e4
LT		 2101 }
2102 }
2103 } else {
2104 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2105 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2106 if (tp_peer != tp &&
2107 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2108 return;
2109
b401e9e2
MC		 2110 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111 (GRC_LCLCTRL_GPIO_OE1 |
2112 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2113
b401e9e2
MC		 2114 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2116
b401e9e2
MC		 2117 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118 (GRC_LCLCTRL_GPIO_OE1 |
2119 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2120 }
2121 }
2122}
2123
e8f3f6ca
MC		 2124static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2125{
2126 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2127 return 1;
2128 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2129 if (speed != SPEED_10)
2130 return 1;
2131 } else if (speed == SPEED_10)
2132 return 1;
2133
2134 return 0;
2135}
2136
1da177e4
LT		 2137static int tg3_setup_phy(struct tg3 *, int);
2138
2139#define RESET_KIND_SHUTDOWN 0
2140#define RESET_KIND_INIT 1
2141#define RESET_KIND_SUSPEND 2
2142
2143static void tg3_write_sig_post_reset(struct tg3 *, int);
2144static int tg3_halt_cpu(struct tg3 *, u32);
2145
0a459aac 2146static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2147{
ce057f01
MC		 2148 u32 val;
2149
5129724a
MC		 2150 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2152 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2153 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2154
2155 sg_dig_ctrl |=
2156 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2157 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2158 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2159 }
3f7045c1 2160 return;
5129724a 2161 }
3f7045c1 2162
60189ddf 2163 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2164 tg3_bmcr_reset(tp);
2165 val = tr32(GRC_MISC_CFG);
2166 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2167 udelay(40);
2168 return;
0e5f784c
MC		 2169 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2170 u32 phytest;
2171 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2172 u32 phy;
2173
2174 tg3_writephy(tp, MII_ADVERTISE, 0);
2175 tg3_writephy(tp, MII_BMCR,
2176 BMCR_ANENABLE | BMCR_ANRESTART);
2177
2178 tg3_writephy(tp, MII_TG3_FET_TEST,
2179 phytest | MII_TG3_FET_SHADOW_EN);
2180 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2181 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2182 tg3_writephy(tp,
2183 MII_TG3_FET_SHDW_AUXMODE4,
2184 phy);
2185 }
2186 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2187 }
2188 return;
0a459aac 2189 } else if (do_low_power) {
715116a1
MC		 2190 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2191 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2192
2193 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2194 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2195 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2196 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2197 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2198 }
3f7045c1 2199
15c3b696
MC		 2200 /* The PHY should not be powered down on some chips because
2201 * of bugs.
2202 */
2203 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2204 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2205 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2206 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2207 return;
ce057f01 2208
bcb37f6c
MC		 2209 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2210 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2211 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2212 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2213 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2214 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2215 }
2216
15c3b696
MC		 2217 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2218}
2219
ffbcfed4
MC		 2220/* tp->lock is held. */
2221static int tg3_nvram_lock(struct tg3 *tp)
2222{
2223 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2224 int i;
2225
2226 if (tp->nvram_lock_cnt == 0) {
2227 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2228 for (i = 0; i < 8000; i++) {
2229 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2230 break;
2231 udelay(20);
2232 }
2233 if (i == 8000) {
2234 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2235 return -ENODEV;
2236 }
2237 }
2238 tp->nvram_lock_cnt++;
2239 }
2240 return 0;
2241}
2242
2243/* tp->lock is held. */
2244static void tg3_nvram_unlock(struct tg3 *tp)
2245{
2246 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2247 if (tp->nvram_lock_cnt > 0)
2248 tp->nvram_lock_cnt--;
2249 if (tp->nvram_lock_cnt == 0)
2250 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2251 }
2252}
2253
2254/* tp->lock is held. */
2255static void tg3_enable_nvram_access(struct tg3 *tp)
2256{
2257 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2258 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2259 u32 nvaccess = tr32(NVRAM_ACCESS);
2260
2261 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2262 }
2263}
2264
2265/* tp->lock is held. */
2266static void tg3_disable_nvram_access(struct tg3 *tp)
2267{
2268 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 2269 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
ffbcfed4
MC		 2270 u32 nvaccess = tr32(NVRAM_ACCESS);
2271
2272 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2273 }
2274}
2275
2276static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2277 u32 offset, u32 *val)
2278{
2279 u32 tmp;
2280 int i;
2281
2282 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2283 return -EINVAL;
2284
2285 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2286 EEPROM_ADDR_DEVID_MASK |
2287 EEPROM_ADDR_READ);
2288 tw32(GRC_EEPROM_ADDR,
2289 tmp |
2290 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2291 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2292 EEPROM_ADDR_ADDR_MASK) |
2293 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2294
2295 for (i = 0; i < 1000; i++) {
2296 tmp = tr32(GRC_EEPROM_ADDR);
2297
2298 if (tmp & EEPROM_ADDR_COMPLETE)
2299 break;
2300 msleep(1);
2301 }
2302 if (!(tmp & EEPROM_ADDR_COMPLETE))
2303 return -EBUSY;
2304
62cedd11
MC		 2305 tmp = tr32(GRC_EEPROM_DATA);
2306
2307 /*
2308 * The data will always be opposite the native endian
2309 * format. Perform a blind byteswap to compensate.
2310 */
2311 *val = swab32(tmp);
2312
ffbcfed4
MC		 2313 return 0;
2314}
2315
2316#define NVRAM_CMD_TIMEOUT 10000
2317
2318static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2319{
2320 int i;
2321
2322 tw32(NVRAM_CMD, nvram_cmd);
2323 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2324 udelay(10);
2325 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2326 udelay(10);
2327 break;
2328 }
2329 }
2330
2331 if (i == NVRAM_CMD_TIMEOUT)
2332 return -EBUSY;
2333
2334 return 0;
2335}
2336
2337static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2338{
2339 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2340 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2341 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2342 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2343 (tp->nvram_jedecnum == JEDEC_ATMEL))
2344
2345 addr = ((addr / tp->nvram_pagesize) <<
2346 ATMEL_AT45DB0X1B_PAGE_POS) +
2347 (addr % tp->nvram_pagesize);
2348
2349 return addr;
2350}
2351
2352static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2353{
2354 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2355 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2356 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2357 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2358 (tp->nvram_jedecnum == JEDEC_ATMEL))
2359
2360 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2361 tp->nvram_pagesize) +
2362 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2363
2364 return addr;
2365}
2366
e4f34110
MC		 2367/* NOTE: Data read in from NVRAM is byteswapped according to
2368 * the byteswapping settings for all other register accesses.
2369 * tg3 devices are BE devices, so on a BE machine, the data
2370 * returned will be exactly as it is seen in NVRAM. On a LE
2371 * machine, the 32-bit value will be byteswapped.
2372 */
ffbcfed4
MC		 2373static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2374{
2375 int ret;
2376
2377 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2378 return tg3_nvram_read_using_eeprom(tp, offset, val);
2379
2380 offset = tg3_nvram_phys_addr(tp, offset);
2381
2382 if (offset > NVRAM_ADDR_MSK)
2383 return -EINVAL;
2384
2385 ret = tg3_nvram_lock(tp);
2386 if (ret)
2387 return ret;
2388
2389 tg3_enable_nvram_access(tp);
2390
2391 tw32(NVRAM_ADDR, offset);
2392 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2393 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2394
2395 if (ret == 0)
e4f34110 2396 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2397
2398 tg3_disable_nvram_access(tp);
2399
2400 tg3_nvram_unlock(tp);
2401
2402 return ret;
2403}
2404
a9dc529d
MC		 2405/* Ensures NVRAM data is in bytestream format. */
2406static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2407{
2408 u32 v;
a9dc529d 2409 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2410 if (!res)
a9dc529d 2411 *val = cpu_to_be32(v);
ffbcfed4
MC		 2412 return res;
2413}
2414
3f007891
MC		 2415/* tp->lock is held. */
2416static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2417{
2418 u32 addr_high, addr_low;
2419 int i;
2420
2421 addr_high = ((tp->dev->dev_addr[0] << 8) |
2422 tp->dev->dev_addr[1]);
2423 addr_low = ((tp->dev->dev_addr[2] << 24) |
2424 (tp->dev->dev_addr[3] << 16) |
2425 (tp->dev->dev_addr[4] << 8) |
2426 (tp->dev->dev_addr[5] << 0));
2427 for (i = 0; i < 4; i++) {
2428 if (i == 1 && skip_mac_1)
2429 continue;
2430 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2431 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2432 }
2433
2434 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2435 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2436 for (i = 0; i < 12; i++) {
2437 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2438 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2439 }
2440 }
2441
2442 addr_high = (tp->dev->dev_addr[0] +
2443 tp->dev->dev_addr[1] +
2444 tp->dev->dev_addr[2] +
2445 tp->dev->dev_addr[3] +
2446 tp->dev->dev_addr[4] +
2447 tp->dev->dev_addr[5]) &
2448 TX_BACKOFF_SEED_MASK;
2449 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2450}
2451
bc1c7567 2452static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2453{
2454 u32 misc_host_ctrl;
0a459aac 2455 bool device_should_wake, do_low_power;
1da177e4
LT		 2456
2457 /* Make sure register accesses (indirect or otherwise)
2458 * will function correctly.
2459 */
2460 pci_write_config_dword(tp->pdev,
2461 TG3PCI_MISC_HOST_CTRL,
2462 tp->misc_host_ctrl);
2463
1da177e4 2464 switch (state) {
bc1c7567 2465 case PCI_D0:
12dac075
RW		 2466 pci_enable_wake(tp->pdev, state, false);
2467 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2468
9d26e213
MC		 2469 /* Switch out of Vaux if it is a NIC */
2470 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2471 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2472
2473 return 0;
2474
bc1c7567 2475 case PCI_D1:
bc1c7567 2476 case PCI_D2:
bc1c7567 2477 case PCI_D3hot:
1da177e4
LT		 2478 break;
2479
2480 default:
12dac075
RW		 2481 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2482 tp->dev->name, state);
1da177e4 2483 return -EINVAL;
855e1111 2484 }
5e7dfd0f
MC		 2485
2486 /* Restore the CLKREQ setting. */
2487 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2488 u16 lnkctl;
2489
2490 pci_read_config_word(tp->pdev,
2491 tp->pcie_cap + PCI_EXP_LNKCTL,
2492 &lnkctl);
2493 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2494 pci_write_config_word(tp->pdev,
2495 tp->pcie_cap + PCI_EXP_LNKCTL,
2496 lnkctl);
2497 }
2498
1da177e4
LT		 2499 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2500 tw32(TG3PCI_MISC_HOST_CTRL,
2501 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2502
05ac4cb7
MC		 2503 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2504 device_may_wakeup(&tp->pdev->dev) &&
2505 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2506
dd477003 2507 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2508 do_low_power = false;
b02fd9e3
MC		 2509 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2510 !tp->link_config.phy_is_low_power) {
2511 struct phy_device *phydev;
0a459aac 2512 u32 phyid, advertising;
b02fd9e3 2513
3f0e3ad7 2514 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2515
2516 tp->link_config.phy_is_low_power = 1;
2517
2518 tp->link_config.orig_speed = phydev->speed;
2519 tp->link_config.orig_duplex = phydev->duplex;
2520 tp->link_config.orig_autoneg = phydev->autoneg;
2521 tp->link_config.orig_advertising = phydev->advertising;
2522
2523 advertising = ADVERTISED_TP |
2524 ADVERTISED_Pause |
2525 ADVERTISED_Autoneg |
2526 ADVERTISED_10baseT_Half;
2527
2528 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2529 device_should_wake) {
b02fd9e3
MC		 2530 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2531 advertising |=
2532 ADVERTISED_100baseT_Half |
2533 ADVERTISED_100baseT_Full |
2534 ADVERTISED_10baseT_Full;
2535 else
2536 advertising |= ADVERTISED_10baseT_Full;
2537 }
2538
2539 phydev->advertising = advertising;
2540
2541 phy_start_aneg(phydev);
0a459aac
MC		 2542
2543 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2544 if (phyid != TG3_PHY_ID_BCMAC131) {
2545 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2546 if (phyid == TG3_PHY_OUI_1 ||
2547 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2548 phyid == TG3_PHY_OUI_3)
2549 do_low_power = true;
2550 }
b02fd9e3 2551 }
dd477003 2552 } else {
2023276e 2553 do_low_power = true;
0a459aac 2554
dd477003
MC		 2555 if (tp->link_config.phy_is_low_power == 0) {
2556 tp->link_config.phy_is_low_power = 1;
2557 tp->link_config.orig_speed = tp->link_config.speed;
2558 tp->link_config.orig_duplex = tp->link_config.duplex;
2559 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2560 }
1da177e4 2561
dd477003
MC		 2562 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2563 tp->link_config.speed = SPEED_10;
2564 tp->link_config.duplex = DUPLEX_HALF;
2565 tp->link_config.autoneg = AUTONEG_ENABLE;
2566 tg3_setup_phy(tp, 0);
2567 }
1da177e4
LT		 2568 }
2569
b5d3772c
MC		 2570 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2571 u32 val;
2572
2573 val = tr32(GRC_VCPU_EXT_CTRL);
2574 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2575 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2576 int i;
2577 u32 val;
2578
2579 for (i = 0; i < 200; i++) {
2580 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2581 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2582 break;
2583 msleep(1);
2584 }
2585 }
a85feb8c
GZ		 2586 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2587 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2588 WOL_DRV_STATE_SHUTDOWN |
2589 WOL_DRV_WOL |
2590 WOL_SET_MAGIC_PKT);
6921d201 2591
05ac4cb7 2592 if (device_should_wake) {
1da177e4
LT		 2593 u32 mac_mode;
2594
2595 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2596 if (do_low_power) {
dd477003
MC		 2597 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2598 udelay(40);
2599 }
1da177e4 2600
3f7045c1
MC		 2601 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2602 mac_mode = MAC_MODE_PORT_MODE_GMII;
2603 else
2604 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2605
e8f3f6ca
MC		 2606 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2607 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2608 ASIC_REV_5700) {
2609 u32 speed = (tp->tg3_flags &
2610 TG3_FLAG_WOL_SPEED_100MB) ?
2611 SPEED_100 : SPEED_10;
2612 if (tg3_5700_link_polarity(tp, speed))
2613 mac_mode |= MAC_MODE_LINK_POLARITY;
2614 else
2615 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2616 }
1da177e4
LT		 2617 } else {
2618 mac_mode = MAC_MODE_PORT_MODE_TBI;
2619 }
2620
cbf46853 2621 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2622 tw32(MAC_LED_CTRL, tp->led_ctrl);
2623
05ac4cb7
MC		 2624 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2625 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2626 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2627 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2628 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2629 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2630
3bda1258
MC		 2631 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2632 mac_mode |= tp->mac_mode &
2633 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2634 if (mac_mode & MAC_MODE_APE_TX_EN)
2635 mac_mode |= MAC_MODE_TDE_ENABLE;
2636 }
2637
1da177e4
LT		 2638 tw32_f(MAC_MODE, mac_mode);
2639 udelay(100);
2640
2641 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2642 udelay(10);
2643 }
2644
2645 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2646 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2648 u32 base_val;
2649
2650 base_val = tp->pci_clock_ctrl;
2651 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2652 CLOCK_CTRL_TXCLK_DISABLE);
2653
b401e9e2
MC		 2654 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2655 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2656 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2657 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2658 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2659 /* do nothing */
85e94ced 2660 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2661 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2662 u32 newbits1, newbits2;
2663
2664 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2665 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2666 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2667 CLOCK_CTRL_TXCLK_DISABLE |
2668 CLOCK_CTRL_ALTCLK);
2669 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2671 newbits1 = CLOCK_CTRL_625_CORE;
2672 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2673 } else {
2674 newbits1 = CLOCK_CTRL_ALTCLK;
2675 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2676 }
2677
b401e9e2
MC		 2678 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2679 40);
1da177e4 2680
b401e9e2
MC		 2681 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2682 40);
1da177e4
LT		 2683
2684 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2685 u32 newbits3;
2686
2687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2688 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2689 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2690 CLOCK_CTRL_TXCLK_DISABLE |
2691 CLOCK_CTRL_44MHZ_CORE);
2692 } else {
2693 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2694 }
2695
b401e9e2
MC		 2696 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2697 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2698 }
2699 }
2700
05ac4cb7 2701 if (!(device_should_wake) &&
22435849 2702 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2703 tg3_power_down_phy(tp, do_low_power);
6921d201 2704
1da177e4
LT		 2705 tg3_frob_aux_power(tp);
2706
2707 /* Workaround for unstable PLL clock */
2708 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2709 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2710 u32 val = tr32(0x7d00);
2711
2712 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2713 tw32(0x7d00, val);
6921d201 2714 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2715 int err;
2716
2717 err = tg3_nvram_lock(tp);
1da177e4 2718 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2719 if (!err)
2720 tg3_nvram_unlock(tp);
6921d201 2721 }
1da177e4
LT		 2722 }
2723
bbadf503
MC		 2724 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2725
05ac4cb7 2726 if (device_should_wake)
12dac075
RW		 2727 pci_enable_wake(tp->pdev, state, true);
2728
1da177e4 2729 /* Finally, set the new power state. */
12dac075 2730 pci_set_power_state(tp->pdev, state);
1da177e4 2731
1da177e4
LT		 2732 return 0;
2733}
2734
1da177e4
LT		 2735static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2736{
2737 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2738 case MII_TG3_AUX_STAT_10HALF:
2739 *speed = SPEED_10;
2740 *duplex = DUPLEX_HALF;
2741 break;
2742
2743 case MII_TG3_AUX_STAT_10FULL:
2744 *speed = SPEED_10;
2745 *duplex = DUPLEX_FULL;
2746 break;
2747
2748 case MII_TG3_AUX_STAT_100HALF:
2749 *speed = SPEED_100;
2750 *duplex = DUPLEX_HALF;
2751 break;
2752
2753 case MII_TG3_AUX_STAT_100FULL:
2754 *speed = SPEED_100;
2755 *duplex = DUPLEX_FULL;
2756 break;
2757
2758 case MII_TG3_AUX_STAT_1000HALF:
2759 *speed = SPEED_1000;
2760 *duplex = DUPLEX_HALF;
2761 break;
2762
2763 case MII_TG3_AUX_STAT_1000FULL:
2764 *speed = SPEED_1000;
2765 *duplex = DUPLEX_FULL;
2766 break;
2767
2768 default:
7f97a4bd 2769 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2770 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2771 SPEED_10;
2772 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2773 DUPLEX_HALF;
2774 break;
2775 }
1da177e4
LT		 2776 *speed = SPEED_INVALID;
2777 *duplex = DUPLEX_INVALID;
2778 break;
855e1111 2779 }
1da177e4
LT		 2780}
2781
2782static void tg3_phy_copper_begin(struct tg3 *tp)
2783{
2784 u32 new_adv;
2785 int i;
2786
2787 if (tp->link_config.phy_is_low_power) {
2788 /* Entering low power mode. Disable gigabit and
2789 * 100baseT advertisements.
2790 */
2791 tg3_writephy(tp, MII_TG3_CTRL, 0);
2792
2793 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2794 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2795 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2796 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2797
2798 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2799 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2800 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2801 tp->link_config.advertising &=
2802 ~(ADVERTISED_1000baseT_Half |
2803 ADVERTISED_1000baseT_Full);
2804
ba4d07a8 2805 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2806 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2807 new_adv |= ADVERTISE_10HALF;
2808 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2809 new_adv |= ADVERTISE_10FULL;
2810 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2811 new_adv |= ADVERTISE_100HALF;
2812 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2813 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2814
2815 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2816
1da177e4
LT		 2817 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2818
2819 if (tp->link_config.advertising &
2820 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2821 new_adv = 0;
2822 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2823 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2824 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2825 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2826 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2827 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2828 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2829 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2830 MII_TG3_CTRL_ENABLE_AS_MASTER);
2831 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2832 } else {
2833 tg3_writephy(tp, MII_TG3_CTRL, 0);
2834 }
2835 } else {
ba4d07a8
MC		 2836 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2837 new_adv |= ADVERTISE_CSMA;
2838
1da177e4
LT		 2839 /* Asking for a specific link mode. */
2840 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2841 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2842
2843 if (tp->link_config.duplex == DUPLEX_FULL)
2844 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2845 else
2846 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2847 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2848 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2849 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2850 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2851 } else {
1da177e4
LT		 2852 if (tp->link_config.speed == SPEED_100) {
2853 if (tp->link_config.duplex == DUPLEX_FULL)
2854 new_adv |= ADVERTISE_100FULL;
2855 else
2856 new_adv |= ADVERTISE_100HALF;
2857 } else {
2858 if (tp->link_config.duplex == DUPLEX_FULL)
2859 new_adv |= ADVERTISE_10FULL;
2860 else
2861 new_adv |= ADVERTISE_10HALF;
2862 }
2863 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2864
2865 new_adv = 0;
1da177e4 2866 }
ba4d07a8
MC		 2867
2868 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2869 }
2870
2871 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2872 tp->link_config.speed != SPEED_INVALID) {
2873 u32 bmcr, orig_bmcr;
2874
2875 tp->link_config.active_speed = tp->link_config.speed;
2876 tp->link_config.active_duplex = tp->link_config.duplex;
2877
2878 bmcr = 0;
2879 switch (tp->link_config.speed) {
2880 default:
2881 case SPEED_10:
2882 break;
2883
2884 case SPEED_100:
2885 bmcr |= BMCR_SPEED100;
2886 break;
2887
2888 case SPEED_1000:
2889 bmcr |= TG3_BMCR_SPEED1000;
2890 break;
855e1111 2891 }
1da177e4
LT		 2892
2893 if (tp->link_config.duplex == DUPLEX_FULL)
2894 bmcr |= BMCR_FULLDPLX;
2895
2896 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2897 (bmcr != orig_bmcr)) {
2898 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2899 for (i = 0; i < 1500; i++) {
2900 u32 tmp;
2901
2902 udelay(10);
2903 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2904 tg3_readphy(tp, MII_BMSR, &tmp))
2905 continue;
2906 if (!(tmp & BMSR_LSTATUS)) {
2907 udelay(40);
2908 break;
2909 }
2910 }
2911 tg3_writephy(tp, MII_BMCR, bmcr);
2912 udelay(40);
2913 }
2914 } else {
2915 tg3_writephy(tp, MII_BMCR,
2916 BMCR_ANENABLE | BMCR_ANRESTART);
2917 }
2918}
2919
2920static int tg3_init_5401phy_dsp(struct tg3 *tp)
2921{
2922 int err;
2923
2924 /* Turn off tap power management. */
2925 /* Set Extended packet length bit */
2926 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2927
2928 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2929 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2930
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2933
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2936
2937 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2939
2940 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2941 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2942
2943 udelay(40);
2944
2945 return err;
2946}
2947
3600d918 2948static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2949{
3600d918
MC		 2950 u32 adv_reg, all_mask = 0;
2951
2952 if (mask & ADVERTISED_10baseT_Half)
2953 all_mask |= ADVERTISE_10HALF;
2954 if (mask & ADVERTISED_10baseT_Full)
2955 all_mask |= ADVERTISE_10FULL;
2956 if (mask & ADVERTISED_100baseT_Half)
2957 all_mask |= ADVERTISE_100HALF;
2958 if (mask & ADVERTISED_100baseT_Full)
2959 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2960
2961 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2962 return 0;
2963
1da177e4
LT		 2964 if ((adv_reg & all_mask) != all_mask)
2965 return 0;
2966 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2967 u32 tg3_ctrl;
2968
3600d918
MC		 2969 all_mask = 0;
2970 if (mask & ADVERTISED_1000baseT_Half)
2971 all_mask |= ADVERTISE_1000HALF;
2972 if (mask & ADVERTISED_1000baseT_Full)
2973 all_mask |= ADVERTISE_1000FULL;
2974
1da177e4
LT		 2975 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2976 return 0;
2977
1da177e4
LT		 2978 if ((tg3_ctrl & all_mask) != all_mask)
2979 return 0;
2980 }
2981 return 1;
2982}
2983
ef167e27
MC		 2984static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2985{
2986 u32 curadv, reqadv;
2987
2988 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2989 return 1;
2990
2991 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2992 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2993
2994 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2995 if (curadv != reqadv)
2996 return 0;
2997
2998 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2999 tg3_readphy(tp, MII_LPA, rmtadv);
3000 } else {
3001 /* Reprogram the advertisement register, even if it
3002 * does not affect the current link. If the link
3003 * gets renegotiated in the future, we can save an
3004 * additional renegotiation cycle by advertising
3005 * it correctly in the first place.
3006 */
3007 if (curadv != reqadv) {
3008 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3009 ADVERTISE_PAUSE_ASYM);
3010 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3011 }
3012 }
3013
3014 return 1;
3015}
3016
1da177e4
LT		 3017static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3018{
3019 int current_link_up;
3020 u32 bmsr, dummy;
ef167e27 3021 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3022 u16 current_speed;
3023 u8 current_duplex;
3024 int i, err;
3025
3026 tw32(MAC_EVENT, 0);
3027
3028 tw32_f(MAC_STATUS,
3029 (MAC_STATUS_SYNC_CHANGED |
3030 MAC_STATUS_CFG_CHANGED |
3031 MAC_STATUS_MI_COMPLETION |
3032 MAC_STATUS_LNKSTATE_CHANGED));
3033 udelay(40);
3034
8ef21428
MC		 3035 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3036 tw32_f(MAC_MI_MODE,
3037 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3038 udelay(80);
3039 }
1da177e4
LT		 3040
3041 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3042
3043 /* Some third-party PHYs need to be reset on link going
3044 * down.
3045 */
3046 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3048 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3049 netif_carrier_ok(tp->dev)) {
3050 tg3_readphy(tp, MII_BMSR, &bmsr);
3051 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3052 !(bmsr & BMSR_LSTATUS))
3053 force_reset = 1;
3054 }
3055 if (force_reset)
3056 tg3_phy_reset(tp);
3057
3058 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3059 tg3_readphy(tp, MII_BMSR, &bmsr);
3060 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3061 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3062 bmsr = 0;
3063
3064 if (!(bmsr & BMSR_LSTATUS)) {
3065 err = tg3_init_5401phy_dsp(tp);
3066 if (err)
3067 return err;
3068
3069 tg3_readphy(tp, MII_BMSR, &bmsr);
3070 for (i = 0; i < 1000; i++) {
3071 udelay(10);
3072 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3073 (bmsr & BMSR_LSTATUS)) {
3074 udelay(40);
3075 break;
3076 }
3077 }
3078
3079 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3080 !(bmsr & BMSR_LSTATUS) &&
3081 tp->link_config.active_speed == SPEED_1000) {
3082 err = tg3_phy_reset(tp);
3083 if (!err)
3084 err = tg3_init_5401phy_dsp(tp);
3085 if (err)
3086 return err;
3087 }
3088 }
3089 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3090 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3091 /* 5701 {A0,B0} CRC bug workaround */
3092 tg3_writephy(tp, 0x15, 0x0a75);
3093 tg3_writephy(tp, 0x1c, 0x8c68);
3094 tg3_writephy(tp, 0x1c, 0x8d68);
3095 tg3_writephy(tp, 0x1c, 0x8c68);
3096 }
3097
3098 /* Clear pending interrupts... */
3099 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3100 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3101
3102 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3103 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3104 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3105 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3106
3107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3109 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3110 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3111 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3112 else
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3114 }
3115
3116 current_link_up = 0;
3117 current_speed = SPEED_INVALID;
3118 current_duplex = DUPLEX_INVALID;
3119
3120 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3121 u32 val;
3122
3123 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3124 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3125 if (!(val & (1 << 10))) {
3126 val |= (1 << 10);
3127 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3128 goto relink;
3129 }
3130 }
3131
3132 bmsr = 0;
3133 for (i = 0; i < 100; i++) {
3134 tg3_readphy(tp, MII_BMSR, &bmsr);
3135 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3136 (bmsr & BMSR_LSTATUS))
3137 break;
3138 udelay(40);
3139 }
3140
3141 if (bmsr & BMSR_LSTATUS) {
3142 u32 aux_stat, bmcr;
3143
3144 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3145 for (i = 0; i < 2000; i++) {
3146 udelay(10);
3147 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3148 aux_stat)
3149 break;
3150 }
3151
3152 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3153 &current_speed,
3154 &current_duplex);
3155
3156 bmcr = 0;
3157 for (i = 0; i < 200; i++) {
3158 tg3_readphy(tp, MII_BMCR, &bmcr);
3159 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3160 continue;
3161 if (bmcr && bmcr != 0x7fff)
3162 break;
3163 udelay(10);
3164 }
3165
ef167e27
MC		 3166 lcl_adv = 0;
3167 rmt_adv = 0;
1da177e4 3168
ef167e27
MC		 3169 tp->link_config.active_speed = current_speed;
3170 tp->link_config.active_duplex = current_duplex;
3171
3172 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3173 if ((bmcr & BMCR_ANENABLE) &&
3174 tg3_copper_is_advertising_all(tp,
3175 tp->link_config.advertising)) {
3176 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3177 &rmt_adv))
3178 current_link_up = 1;
1da177e4
LT		 3179 }
3180 } else {
3181 if (!(bmcr & BMCR_ANENABLE) &&
3182 tp->link_config.speed == current_speed &&
ef167e27
MC		 3183 tp->link_config.duplex == current_duplex &&
3184 tp->link_config.flowctrl ==
3185 tp->link_config.active_flowctrl) {
1da177e4 3186 current_link_up = 1;
1da177e4
LT		 3187 }
3188 }
3189
ef167e27
MC		 3190 if (current_link_up == 1 &&
3191 tp->link_config.active_duplex == DUPLEX_FULL)
3192 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3193 }
3194
1da177e4 3195relink:
6921d201 3196 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3197 u32 tmp;
3198
3199 tg3_phy_copper_begin(tp);
3200
3201 tg3_readphy(tp, MII_BMSR, &tmp);
3202 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3203 (tmp & BMSR_LSTATUS))
3204 current_link_up = 1;
3205 }
3206
3207 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3208 if (current_link_up == 1) {
3209 if (tp->link_config.active_speed == SPEED_100 ||
3210 tp->link_config.active_speed == SPEED_10)
3211 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3212 else
3213 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3214 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3215 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3216 else
1da177e4
LT		 3217 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3218
3219 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3220 if (tp->link_config.active_duplex == DUPLEX_HALF)
3221 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3222
1da177e4 3223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3224 if (current_link_up == 1 &&
3225 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3226 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3227 else
3228 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3229 }
3230
3231 /* ??? Without this setting Netgear GA302T PHY does not
3232 * ??? send/receive packets...
3233 */
3234 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3235 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3236 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3237 tw32_f(MAC_MI_MODE, tp->mi_mode);
3238 udelay(80);
3239 }
3240
3241 tw32_f(MAC_MODE, tp->mac_mode);
3242 udelay(40);
3243
3244 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3245 /* Polled via timer. */
3246 tw32_f(MAC_EVENT, 0);
3247 } else {
3248 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3249 }
3250 udelay(40);
3251
3252 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3253 current_link_up == 1 &&
3254 tp->link_config.active_speed == SPEED_1000 &&
3255 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3256 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3257 udelay(120);
3258 tw32_f(MAC_STATUS,
3259 (MAC_STATUS_SYNC_CHANGED |
3260 MAC_STATUS_CFG_CHANGED));
3261 udelay(40);
3262 tg3_write_mem(tp,
3263 NIC_SRAM_FIRMWARE_MBOX,
3264 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3265 }
3266
5e7dfd0f
MC		 3267 /* Prevent send BD corruption. */
3268 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3269 u16 oldlnkctl, newlnkctl;
3270
3271 pci_read_config_word(tp->pdev,
3272 tp->pcie_cap + PCI_EXP_LNKCTL,
3273 &oldlnkctl);
3274 if (tp->link_config.active_speed == SPEED_100 ||
3275 tp->link_config.active_speed == SPEED_10)
3276 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3277 else
3278 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3279 if (newlnkctl != oldlnkctl)
3280 pci_write_config_word(tp->pdev,
3281 tp->pcie_cap + PCI_EXP_LNKCTL,
3282 newlnkctl);
3283 }
3284
1da177e4
LT		 3285 if (current_link_up != netif_carrier_ok(tp->dev)) {
3286 if (current_link_up)
3287 netif_carrier_on(tp->dev);
3288 else
3289 netif_carrier_off(tp->dev);
3290 tg3_link_report(tp);
3291 }
3292
3293 return 0;
3294}
3295
3296struct tg3_fiber_aneginfo {
3297 int state;
3298#define ANEG_STATE_UNKNOWN 0
3299#define ANEG_STATE_AN_ENABLE 1
3300#define ANEG_STATE_RESTART_INIT 2
3301#define ANEG_STATE_RESTART 3
3302#define ANEG_STATE_DISABLE_LINK_OK 4
3303#define ANEG_STATE_ABILITY_DETECT_INIT 5
3304#define ANEG_STATE_ABILITY_DETECT 6
3305#define ANEG_STATE_ACK_DETECT_INIT 7
3306#define ANEG_STATE_ACK_DETECT 8
3307#define ANEG_STATE_COMPLETE_ACK_INIT 9
3308#define ANEG_STATE_COMPLETE_ACK 10
3309#define ANEG_STATE_IDLE_DETECT_INIT 11
3310#define ANEG_STATE_IDLE_DETECT 12
3311#define ANEG_STATE_LINK_OK 13
3312#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3313#define ANEG_STATE_NEXT_PAGE_WAIT 15
3314
3315 u32 flags;
3316#define MR_AN_ENABLE 0x00000001
3317#define MR_RESTART_AN 0x00000002
3318#define MR_AN_COMPLETE 0x00000004
3319#define MR_PAGE_RX 0x00000008
3320#define MR_NP_LOADED 0x00000010
3321#define MR_TOGGLE_TX 0x00000020
3322#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3323#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3324#define MR_LP_ADV_SYM_PAUSE 0x00000100
3325#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3326#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3327#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3328#define MR_LP_ADV_NEXT_PAGE 0x00001000
3329#define MR_TOGGLE_RX 0x00002000
3330#define MR_NP_RX 0x00004000
3331
3332#define MR_LINK_OK 0x80000000
3333
3334 unsigned long link_time, cur_time;
3335
3336 u32 ability_match_cfg;
3337 int ability_match_count;
3338
3339 char ability_match, idle_match, ack_match;
3340
3341 u32 txconfig, rxconfig;
3342#define ANEG_CFG_NP 0x00000080
3343#define ANEG_CFG_ACK 0x00000040
3344#define ANEG_CFG_RF2 0x00000020
3345#define ANEG_CFG_RF1 0x00000010
3346#define ANEG_CFG_PS2 0x00000001
3347#define ANEG_CFG_PS1 0x00008000
3348#define ANEG_CFG_HD 0x00004000
3349#define ANEG_CFG_FD 0x00002000
3350#define ANEG_CFG_INVAL 0x00001f06
3351
3352};
3353#define ANEG_OK 0
3354#define ANEG_DONE 1
3355#define ANEG_TIMER_ENAB 2
3356#define ANEG_FAILED -1
3357
3358#define ANEG_STATE_SETTLE_TIME 10000
3359
3360static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3361 struct tg3_fiber_aneginfo *ap)
3362{
5be73b47 3363 u16 flowctrl;
1da177e4
LT		 3364 unsigned long delta;
3365 u32 rx_cfg_reg;
3366 int ret;
3367
3368 if (ap->state == ANEG_STATE_UNKNOWN) {
3369 ap->rxconfig = 0;
3370 ap->link_time = 0;
3371 ap->cur_time = 0;
3372 ap->ability_match_cfg = 0;
3373 ap->ability_match_count = 0;
3374 ap->ability_match = 0;
3375 ap->idle_match = 0;
3376 ap->ack_match = 0;
3377 }
3378 ap->cur_time++;
3379
3380 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3381 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3382
3383 if (rx_cfg_reg != ap->ability_match_cfg) {
3384 ap->ability_match_cfg = rx_cfg_reg;
3385 ap->ability_match = 0;
3386 ap->ability_match_count = 0;
3387 } else {
3388 if (++ap->ability_match_count > 1) {
3389 ap->ability_match = 1;
3390 ap->ability_match_cfg = rx_cfg_reg;
3391 }
3392 }
3393 if (rx_cfg_reg & ANEG_CFG_ACK)
3394 ap->ack_match = 1;
3395 else
3396 ap->ack_match = 0;
3397
3398 ap->idle_match = 0;
3399 } else {
3400 ap->idle_match = 1;
3401 ap->ability_match_cfg = 0;
3402 ap->ability_match_count = 0;
3403 ap->ability_match = 0;
3404 ap->ack_match = 0;
3405
3406 rx_cfg_reg = 0;
3407 }
3408
3409 ap->rxconfig = rx_cfg_reg;
3410 ret = ANEG_OK;
3411
3412 switch(ap->state) {
3413 case ANEG_STATE_UNKNOWN:
3414 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3415 ap->state = ANEG_STATE_AN_ENABLE;
3416
3417 /* fallthru */
3418 case ANEG_STATE_AN_ENABLE:
3419 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3420 if (ap->flags & MR_AN_ENABLE) {
3421 ap->link_time = 0;
3422 ap->cur_time = 0;
3423 ap->ability_match_cfg = 0;
3424 ap->ability_match_count = 0;
3425 ap->ability_match = 0;
3426 ap->idle_match = 0;
3427 ap->ack_match = 0;
3428
3429 ap->state = ANEG_STATE_RESTART_INIT;
3430 } else {
3431 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3432 }
3433 break;
3434
3435 case ANEG_STATE_RESTART_INIT:
3436 ap->link_time = ap->cur_time;
3437 ap->flags &= ~(MR_NP_LOADED);
3438 ap->txconfig = 0;
3439 tw32(MAC_TX_AUTO_NEG, 0);
3440 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3441 tw32_f(MAC_MODE, tp->mac_mode);
3442 udelay(40);
3443
3444 ret = ANEG_TIMER_ENAB;
3445 ap->state = ANEG_STATE_RESTART;
3446
3447 /* fallthru */
3448 case ANEG_STATE_RESTART:
3449 delta = ap->cur_time - ap->link_time;
3450 if (delta > ANEG_STATE_SETTLE_TIME) {
3451 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3452 } else {
3453 ret = ANEG_TIMER_ENAB;
3454 }
3455 break;
3456
3457 case ANEG_STATE_DISABLE_LINK_OK:
3458 ret = ANEG_DONE;
3459 break;
3460
3461 case ANEG_STATE_ABILITY_DETECT_INIT:
3462 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3463 ap->txconfig = ANEG_CFG_FD;
3464 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3465 if (flowctrl & ADVERTISE_1000XPAUSE)
3466 ap->txconfig |= ANEG_CFG_PS1;
3467 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3468 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3469 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3470 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3471 tw32_f(MAC_MODE, tp->mac_mode);
3472 udelay(40);
3473
3474 ap->state = ANEG_STATE_ABILITY_DETECT;
3475 break;
3476
3477 case ANEG_STATE_ABILITY_DETECT:
3478 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3479 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3480 }
3481 break;
3482
3483 case ANEG_STATE_ACK_DETECT_INIT:
3484 ap->txconfig |= ANEG_CFG_ACK;
3485 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3486 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3487 tw32_f(MAC_MODE, tp->mac_mode);
3488 udelay(40);
3489
3490 ap->state = ANEG_STATE_ACK_DETECT;
3491
3492 /* fallthru */
3493 case ANEG_STATE_ACK_DETECT:
3494 if (ap->ack_match != 0) {
3495 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3496 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3497 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3498 } else {
3499 ap->state = ANEG_STATE_AN_ENABLE;
3500 }
3501 } else if (ap->ability_match != 0 &&
3502 ap->rxconfig == 0) {
3503 ap->state = ANEG_STATE_AN_ENABLE;
3504 }
3505 break;
3506
3507 case ANEG_STATE_COMPLETE_ACK_INIT:
3508 if (ap->rxconfig & ANEG_CFG_INVAL) {
3509 ret = ANEG_FAILED;
3510 break;
3511 }
3512 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3513 MR_LP_ADV_HALF_DUPLEX |
3514 MR_LP_ADV_SYM_PAUSE |
3515 MR_LP_ADV_ASYM_PAUSE |
3516 MR_LP_ADV_REMOTE_FAULT1 |
3517 MR_LP_ADV_REMOTE_FAULT2 |
3518 MR_LP_ADV_NEXT_PAGE |
3519 MR_TOGGLE_RX |
3520 MR_NP_RX);
3521 if (ap->rxconfig & ANEG_CFG_FD)
3522 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3523 if (ap->rxconfig & ANEG_CFG_HD)
3524 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3525 if (ap->rxconfig & ANEG_CFG_PS1)
3526 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3527 if (ap->rxconfig & ANEG_CFG_PS2)
3528 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3529 if (ap->rxconfig & ANEG_CFG_RF1)
3530 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3531 if (ap->rxconfig & ANEG_CFG_RF2)
3532 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3533 if (ap->rxconfig & ANEG_CFG_NP)
3534 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3535
3536 ap->link_time = ap->cur_time;
3537
3538 ap->flags ^= (MR_TOGGLE_TX);
3539 if (ap->rxconfig & 0x0008)
3540 ap->flags |= MR_TOGGLE_RX;
3541 if (ap->rxconfig & ANEG_CFG_NP)
3542 ap->flags |= MR_NP_RX;
3543 ap->flags |= MR_PAGE_RX;
3544
3545 ap->state = ANEG_STATE_COMPLETE_ACK;
3546 ret = ANEG_TIMER_ENAB;
3547 break;
3548
3549 case ANEG_STATE_COMPLETE_ACK:
3550 if (ap->ability_match != 0 &&
3551 ap->rxconfig == 0) {
3552 ap->state = ANEG_STATE_AN_ENABLE;
3553 break;
3554 }
3555 delta = ap->cur_time - ap->link_time;
3556 if (delta > ANEG_STATE_SETTLE_TIME) {
3557 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3558 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3559 } else {
3560 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3561 !(ap->flags & MR_NP_RX)) {
3562 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3563 } else {
3564 ret = ANEG_FAILED;
3565 }
3566 }
3567 }
3568 break;
3569
3570 case ANEG_STATE_IDLE_DETECT_INIT:
3571 ap->link_time = ap->cur_time;
3572 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3573 tw32_f(MAC_MODE, tp->mac_mode);
3574 udelay(40);
3575
3576 ap->state = ANEG_STATE_IDLE_DETECT;
3577 ret = ANEG_TIMER_ENAB;
3578 break;
3579
3580 case ANEG_STATE_IDLE_DETECT:
3581 if (ap->ability_match != 0 &&
3582 ap->rxconfig == 0) {
3583 ap->state = ANEG_STATE_AN_ENABLE;
3584 break;
3585 }
3586 delta = ap->cur_time - ap->link_time;
3587 if (delta > ANEG_STATE_SETTLE_TIME) {
3588 /* XXX another gem from the Broadcom driver :( */
3589 ap->state = ANEG_STATE_LINK_OK;
3590 }
3591 break;
3592
3593 case ANEG_STATE_LINK_OK:
3594 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3595 ret = ANEG_DONE;
3596 break;
3597
3598 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3599 /* ??? unimplemented */
3600 break;
3601
3602 case ANEG_STATE_NEXT_PAGE_WAIT:
3603 /* ??? unimplemented */
3604 break;
3605
3606 default:
3607 ret = ANEG_FAILED;
3608 break;
855e1111 3609 }
1da177e4
LT		 3610
3611 return ret;
3612}
3613
5be73b47 3614static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3615{
3616 int res = 0;
3617 struct tg3_fiber_aneginfo aninfo;
3618 int status = ANEG_FAILED;
3619 unsigned int tick;
3620 u32 tmp;
3621
3622 tw32_f(MAC_TX_AUTO_NEG, 0);
3623
3624 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3625 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3626 udelay(40);
3627
3628 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3629 udelay(40);
3630
3631 memset(&aninfo, 0, sizeof(aninfo));
3632 aninfo.flags |= MR_AN_ENABLE;
3633 aninfo.state = ANEG_STATE_UNKNOWN;
3634 aninfo.cur_time = 0;
3635 tick = 0;
3636 while (++tick < 195000) {
3637 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3638 if (status == ANEG_DONE || status == ANEG_FAILED)
3639 break;
3640
3641 udelay(1);
3642 }
3643
3644 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3645 tw32_f(MAC_MODE, tp->mac_mode);
3646 udelay(40);
3647
5be73b47
MC		 3648 *txflags = aninfo.txconfig;
3649 *rxflags = aninfo.flags;
1da177e4
LT		 3650
3651 if (status == ANEG_DONE &&
3652 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3653 MR_LP_ADV_FULL_DUPLEX)))
3654 res = 1;
3655
3656 return res;
3657}
3658
3659static void tg3_init_bcm8002(struct tg3 *tp)
3660{
3661 u32 mac_status = tr32(MAC_STATUS);
3662 int i;
3663
3664 /* Reset when initting first time or we have a link. */
3665 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3666 !(mac_status & MAC_STATUS_PCS_SYNCED))
3667 return;
3668
3669 /* Set PLL lock range. */
3670 tg3_writephy(tp, 0x16, 0x8007);
3671
3672 /* SW reset */
3673 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3674
3675 /* Wait for reset to complete. */
3676 /* XXX schedule_timeout() ... */
3677 for (i = 0; i < 500; i++)
3678 udelay(10);
3679
3680 /* Config mode; select PMA/Ch 1 regs. */
3681 tg3_writephy(tp, 0x10, 0x8411);
3682
3683 /* Enable auto-lock and comdet, select txclk for tx. */
3684 tg3_writephy(tp, 0x11, 0x0a10);
3685
3686 tg3_writephy(tp, 0x18, 0x00a0);
3687 tg3_writephy(tp, 0x16, 0x41ff);
3688
3689 /* Assert and deassert POR. */
3690 tg3_writephy(tp, 0x13, 0x0400);
3691 udelay(40);
3692 tg3_writephy(tp, 0x13, 0x0000);
3693
3694 tg3_writephy(tp, 0x11, 0x0a50);
3695 udelay(40);
3696 tg3_writephy(tp, 0x11, 0x0a10);
3697
3698 /* Wait for signal to stabilize */
3699 /* XXX schedule_timeout() ... */
3700 for (i = 0; i < 15000; i++)
3701 udelay(10);
3702
3703 /* Deselect the channel register so we can read the PHYID
3704 * later.
3705 */
3706 tg3_writephy(tp, 0x10, 0x8011);
3707}
3708
3709static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3710{
82cd3d11 3711 u16 flowctrl;
1da177e4
LT		 3712 u32 sg_dig_ctrl, sg_dig_status;
3713 u32 serdes_cfg, expected_sg_dig_ctrl;
3714 int workaround, port_a;
3715 int current_link_up;
3716
3717 serdes_cfg = 0;
3718 expected_sg_dig_ctrl = 0;
3719 workaround = 0;
3720 port_a = 1;
3721 current_link_up = 0;
3722
3723 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3724 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3725 workaround = 1;
3726 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3727 port_a = 0;
3728
3729 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3730 /* preserve bits 20-23 for voltage regulator */
3731 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3732 }
3733
3734 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3735
3736 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3737 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3738 if (workaround) {
3739 u32 val = serdes_cfg;
3740
3741 if (port_a)
3742 val |= 0xc010000;
3743 else
3744 val |= 0x4010000;
3745 tw32_f(MAC_SERDES_CFG, val);
3746 }
c98f6e3b
MC		 3747
3748 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3749 }
3750 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3751 tg3_setup_flow_control(tp, 0, 0);
3752 current_link_up = 1;
3753 }
3754 goto out;
3755 }
3756
3757 /* Want auto-negotiation. */
c98f6e3b 3758 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3759
82cd3d11
MC		 3760 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3761 if (flowctrl & ADVERTISE_1000XPAUSE)
3762 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3763 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3764 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3765
3766 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3767 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3768 tp->serdes_counter &&
3769 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3770 MAC_STATUS_RCVD_CFG)) ==
3771 MAC_STATUS_PCS_SYNCED)) {
3772 tp->serdes_counter--;
3773 current_link_up = 1;
3774 goto out;
3775 }
3776restart_autoneg:
1da177e4
LT		 3777 if (workaround)
3778 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3779 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3780 udelay(5);
3781 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3782
3d3ebe74
MC		 3783 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3784 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3785 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3786 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3787 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3788 mac_status = tr32(MAC_STATUS);
3789
c98f6e3b 3790 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3791 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3792 u32 local_adv = 0, remote_adv = 0;
3793
3794 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3795 local_adv |= ADVERTISE_1000XPAUSE;
3796 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3797 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3798
c98f6e3b 3799 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3800 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3801 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3802 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3803
3804 tg3_setup_flow_control(tp, local_adv, remote_adv);
3805 current_link_up = 1;
3d3ebe74
MC		 3806 tp->serdes_counter = 0;
3807 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3808 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3809 if (tp->serdes_counter)
3810 tp->serdes_counter--;
1da177e4
LT		 3811 else {
3812 if (workaround) {
3813 u32 val = serdes_cfg;
3814
3815 if (port_a)
3816 val |= 0xc010000;
3817 else
3818 val |= 0x4010000;
3819
3820 tw32_f(MAC_SERDES_CFG, val);
3821 }
3822
c98f6e3b 3823 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3824 udelay(40);
3825
3826 /* Link parallel detection - link is up */
3827 /* only if we have PCS_SYNC and not */
3828 /* receiving config code words */
3829 mac_status = tr32(MAC_STATUS);
3830 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3831 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3832 tg3_setup_flow_control(tp, 0, 0);
3833 current_link_up = 1;
3d3ebe74
MC		 3834 tp->tg3_flags2 |=
3835 TG3_FLG2_PARALLEL_DETECT;
3836 tp->serdes_counter =
3837 SERDES_PARALLEL_DET_TIMEOUT;
3838 } else
3839 goto restart_autoneg;
1da177e4
LT		 3840 }
3841 }
3d3ebe74
MC		 3842 } else {
3843 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3844 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3845 }
3846
3847out:
3848 return current_link_up;
3849}
3850
3851static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3852{
3853 int current_link_up = 0;
3854
5cf64b8a 3855 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3856 goto out;
1da177e4
LT		 3857
3858 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3859 u32 txflags, rxflags;
1da177e4 3860 int i;
6aa20a22 3861
5be73b47
MC		 3862 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3863 u32 local_adv = 0, remote_adv = 0;
1da177e4 3864
5be73b47
MC		 3865 if (txflags & ANEG_CFG_PS1)
3866 local_adv |= ADVERTISE_1000XPAUSE;
3867 if (txflags & ANEG_CFG_PS2)
3868 local_adv |= ADVERTISE_1000XPSE_ASYM;
3869
3870 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3871 remote_adv |= LPA_1000XPAUSE;
3872 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3873 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3874
3875 tg3_setup_flow_control(tp, local_adv, remote_adv);
3876
1da177e4
LT		 3877 current_link_up = 1;
3878 }
3879 for (i = 0; i < 30; i++) {
3880 udelay(20);
3881 tw32_f(MAC_STATUS,
3882 (MAC_STATUS_SYNC_CHANGED |
3883 MAC_STATUS_CFG_CHANGED));
3884 udelay(40);
3885 if ((tr32(MAC_STATUS) &
3886 (MAC_STATUS_SYNC_CHANGED |
3887 MAC_STATUS_CFG_CHANGED)) == 0)
3888 break;
3889 }
3890
3891 mac_status = tr32(MAC_STATUS);
3892 if (current_link_up == 0 &&
3893 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3894 !(mac_status & MAC_STATUS_RCVD_CFG))
3895 current_link_up = 1;
3896 } else {
5be73b47
MC		 3897 tg3_setup_flow_control(tp, 0, 0);
3898
1da177e4
LT		 3899 /* Forcing 1000FD link up. */
3900 current_link_up = 1;
1da177e4
LT		 3901
3902 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3903 udelay(40);
e8f3f6ca
MC		 3904
3905 tw32_f(MAC_MODE, tp->mac_mode);
3906 udelay(40);
1da177e4
LT		 3907 }
3908
3909out:
3910 return current_link_up;
3911}
3912
3913static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3914{
3915 u32 orig_pause_cfg;
3916 u16 orig_active_speed;
3917 u8 orig_active_duplex;
3918 u32 mac_status;
3919 int current_link_up;
3920 int i;
3921
8d018621 3922 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3923 orig_active_speed = tp->link_config.active_speed;
3924 orig_active_duplex = tp->link_config.active_duplex;
3925
3926 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3927 netif_carrier_ok(tp->dev) &&
3928 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3929 mac_status = tr32(MAC_STATUS);
3930 mac_status &= (MAC_STATUS_PCS_SYNCED |
3931 MAC_STATUS_SIGNAL_DET |
3932 MAC_STATUS_CFG_CHANGED |
3933 MAC_STATUS_RCVD_CFG);
3934 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3935 MAC_STATUS_SIGNAL_DET)) {
3936 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3937 MAC_STATUS_CFG_CHANGED));
3938 return 0;
3939 }
3940 }
3941
3942 tw32_f(MAC_TX_AUTO_NEG, 0);
3943
3944 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3945 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3946 tw32_f(MAC_MODE, tp->mac_mode);
3947 udelay(40);
3948
3949 if (tp->phy_id == PHY_ID_BCM8002)
3950 tg3_init_bcm8002(tp);
3951
3952 /* Enable link change event even when serdes polling. */
3953 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3954 udelay(40);
3955
3956 current_link_up = 0;
3957 mac_status = tr32(MAC_STATUS);
3958
3959 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3960 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3961 else
3962 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3963
898a56f8 3964 tp->napi[0].hw_status->status =
1da177e4 3965 (SD_STATUS_UPDATED |
898a56f8 3966 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3967
3968 for (i = 0; i < 100; i++) {
3969 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3970 MAC_STATUS_CFG_CHANGED));
3971 udelay(5);
3972 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3973 MAC_STATUS_CFG_CHANGED |
3974 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3975 break;
3976 }
3977
3978 mac_status = tr32(MAC_STATUS);
3979 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3980 current_link_up = 0;
3d3ebe74
MC		 3981 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3982 tp->serdes_counter == 0) {
1da177e4
LT		 3983 tw32_f(MAC_MODE, (tp->mac_mode |
3984 MAC_MODE_SEND_CONFIGS));
3985 udelay(1);
3986 tw32_f(MAC_MODE, tp->mac_mode);
3987 }
3988 }
3989
3990 if (current_link_up == 1) {
3991 tp->link_config.active_speed = SPEED_1000;
3992 tp->link_config.active_duplex = DUPLEX_FULL;
3993 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994 LED_CTRL_LNKLED_OVERRIDE |
3995 LED_CTRL_1000MBPS_ON));
3996 } else {
3997 tp->link_config.active_speed = SPEED_INVALID;
3998 tp->link_config.active_duplex = DUPLEX_INVALID;
3999 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4000 LED_CTRL_LNKLED_OVERRIDE |
4001 LED_CTRL_TRAFFIC_OVERRIDE));
4002 }
4003
4004 if (current_link_up != netif_carrier_ok(tp->dev)) {
4005 if (current_link_up)
4006 netif_carrier_on(tp->dev);
4007 else
4008 netif_carrier_off(tp->dev);
4009 tg3_link_report(tp);
4010 } else {
8d018621 4011 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4012 if (orig_pause_cfg != now_pause_cfg ||
4013 orig_active_speed != tp->link_config.active_speed ||
4014 orig_active_duplex != tp->link_config.active_duplex)
4015 tg3_link_report(tp);
4016 }
4017
4018 return 0;
4019}
4020
747e8f8b
MC		 4021static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4022{
4023 int current_link_up, err = 0;
4024 u32 bmsr, bmcr;
4025 u16 current_speed;
4026 u8 current_duplex;
ef167e27 4027 u32 local_adv, remote_adv;
747e8f8b
MC		 4028
4029 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4030 tw32_f(MAC_MODE, tp->mac_mode);
4031 udelay(40);
4032
4033 tw32(MAC_EVENT, 0);
4034
4035 tw32_f(MAC_STATUS,
4036 (MAC_STATUS_SYNC_CHANGED |
4037 MAC_STATUS_CFG_CHANGED |
4038 MAC_STATUS_MI_COMPLETION |
4039 MAC_STATUS_LNKSTATE_CHANGED));
4040 udelay(40);
4041
4042 if (force_reset)
4043 tg3_phy_reset(tp);
4044
4045 current_link_up = 0;
4046 current_speed = SPEED_INVALID;
4047 current_duplex = DUPLEX_INVALID;
4048
4049 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4050 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4052 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4053 bmsr |= BMSR_LSTATUS;
4054 else
4055 bmsr &= ~BMSR_LSTATUS;
4056 }
747e8f8b
MC		 4057
4058 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4059
4060 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4061 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4062 /* do nothing, just check for link up at the end */
4063 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4064 u32 adv, new_adv;
4065
4066 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4067 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4068 ADVERTISE_1000XPAUSE |
4069 ADVERTISE_1000XPSE_ASYM |
4070 ADVERTISE_SLCT);
4071
ba4d07a8 4072 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4073
4074 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4075 new_adv |= ADVERTISE_1000XHALF;
4076 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4077 new_adv |= ADVERTISE_1000XFULL;
4078
4079 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4080 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4081 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4082 tg3_writephy(tp, MII_BMCR, bmcr);
4083
4084 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4085 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4086 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4087
4088 return err;
4089 }
4090 } else {
4091 u32 new_bmcr;
4092
4093 bmcr &= ~BMCR_SPEED1000;
4094 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4095
4096 if (tp->link_config.duplex == DUPLEX_FULL)
4097 new_bmcr |= BMCR_FULLDPLX;
4098
4099 if (new_bmcr != bmcr) {
4100 /* BMCR_SPEED1000 is a reserved bit that needs
4101 * to be set on write.
4102 */
4103 new_bmcr |= BMCR_SPEED1000;
4104
4105 /* Force a linkdown */
4106 if (netif_carrier_ok(tp->dev)) {
4107 u32 adv;
4108
4109 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4110 adv &= ~(ADVERTISE_1000XFULL |
4111 ADVERTISE_1000XHALF |
4112 ADVERTISE_SLCT);
4113 tg3_writephy(tp, MII_ADVERTISE, adv);
4114 tg3_writephy(tp, MII_BMCR, bmcr |
4115 BMCR_ANRESTART |
4116 BMCR_ANENABLE);
4117 udelay(10);
4118 netif_carrier_off(tp->dev);
4119 }
4120 tg3_writephy(tp, MII_BMCR, new_bmcr);
4121 bmcr = new_bmcr;
4122 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4123 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4124 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4125 ASIC_REV_5714) {
4126 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4127 bmsr |= BMSR_LSTATUS;
4128 else
4129 bmsr &= ~BMSR_LSTATUS;
4130 }
747e8f8b
MC		 4131 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4132 }
4133 }
4134
4135 if (bmsr & BMSR_LSTATUS) {
4136 current_speed = SPEED_1000;
4137 current_link_up = 1;
4138 if (bmcr & BMCR_FULLDPLX)
4139 current_duplex = DUPLEX_FULL;
4140 else
4141 current_duplex = DUPLEX_HALF;
4142
ef167e27
MC		 4143 local_adv = 0;
4144 remote_adv = 0;
4145
747e8f8b 4146 if (bmcr & BMCR_ANENABLE) {
ef167e27 4147 u32 common;
747e8f8b
MC		 4148
4149 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4150 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4151 common = local_adv & remote_adv;
4152 if (common & (ADVERTISE_1000XHALF |
4153 ADVERTISE_1000XFULL)) {
4154 if (common & ADVERTISE_1000XFULL)
4155 current_duplex = DUPLEX_FULL;
4156 else
4157 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4158 }
4159 else
4160 current_link_up = 0;
4161 }
4162 }
4163
ef167e27
MC		 4164 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4165 tg3_setup_flow_control(tp, local_adv, remote_adv);
4166
747e8f8b
MC		 4167 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4168 if (tp->link_config.active_duplex == DUPLEX_HALF)
4169 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4170
4171 tw32_f(MAC_MODE, tp->mac_mode);
4172 udelay(40);
4173
4174 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4175
4176 tp->link_config.active_speed = current_speed;
4177 tp->link_config.active_duplex = current_duplex;
4178
4179 if (current_link_up != netif_carrier_ok(tp->dev)) {
4180 if (current_link_up)
4181 netif_carrier_on(tp->dev);
4182 else {
4183 netif_carrier_off(tp->dev);
4184 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4185 }
4186 tg3_link_report(tp);
4187 }
4188 return err;
4189}
4190
4191static void tg3_serdes_parallel_detect(struct tg3 *tp)
4192{
3d3ebe74 4193 if (tp->serdes_counter) {
747e8f8b 4194 /* Give autoneg time to complete. */
3d3ebe74 4195 tp->serdes_counter--;
747e8f8b
MC		 4196 return;
4197 }
4198 if (!netif_carrier_ok(tp->dev) &&
4199 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4200 u32 bmcr;
4201
4202 tg3_readphy(tp, MII_BMCR, &bmcr);
4203 if (bmcr & BMCR_ANENABLE) {
4204 u32 phy1, phy2;
4205
4206 /* Select shadow register 0x1f */
4207 tg3_writephy(tp, 0x1c, 0x7c00);
4208 tg3_readphy(tp, 0x1c, &phy1);
4209
4210 /* Select expansion interrupt status register */
4211 tg3_writephy(tp, 0x17, 0x0f01);
4212 tg3_readphy(tp, 0x15, &phy2);
4213 tg3_readphy(tp, 0x15, &phy2);
4214
4215 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4216 /* We have signal detect and not receiving
4217 * config code words, link is up by parallel
4218 * detection.
4219 */
4220
4221 bmcr &= ~BMCR_ANENABLE;
4222 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4223 tg3_writephy(tp, MII_BMCR, bmcr);
4224 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4225 }
4226 }
4227 }
4228 else if (netif_carrier_ok(tp->dev) &&
4229 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4230 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4231 u32 phy2;
4232
4233 /* Select expansion interrupt status register */
4234 tg3_writephy(tp, 0x17, 0x0f01);
4235 tg3_readphy(tp, 0x15, &phy2);
4236 if (phy2 & 0x20) {
4237 u32 bmcr;
4238
4239 /* Config code words received, turn on autoneg. */
4240 tg3_readphy(tp, MII_BMCR, &bmcr);
4241 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4242
4243 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4244
4245 }
4246 }
4247}
4248
1da177e4
LT		 4249static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4250{
4251 int err;
4252
4253 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4254 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4255 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4256 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4257 } else {
4258 err = tg3_setup_copper_phy(tp, force_reset);
4259 }
4260
bcb37f6c 4261 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4262 u32 val, scale;
4263
4264 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4265 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4266 scale = 65;
4267 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4268 scale = 6;
4269 else
4270 scale = 12;
4271
4272 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4273 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4274 tw32(GRC_MISC_CFG, val);
4275 }
4276
1da177e4
LT		 4277 if (tp->link_config.active_speed == SPEED_1000 &&
4278 tp->link_config.active_duplex == DUPLEX_HALF)
4279 tw32(MAC_TX_LENGTHS,
4280 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4281 (6 << TX_LENGTHS_IPG_SHIFT) |
4282 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4283 else
4284 tw32(MAC_TX_LENGTHS,
4285 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4286 (6 << TX_LENGTHS_IPG_SHIFT) |
4287 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4288
4289 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4290 if (netif_carrier_ok(tp->dev)) {
4291 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4292 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4293 } else {
4294 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4295 }
4296 }
4297
8ed5d97e
MC		 4298 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4299 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4300 if (!netif_carrier_ok(tp->dev))
4301 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4302 tp->pwrmgmt_thresh;
4303 else
4304 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4305 tw32(PCIE_PWR_MGMT_THRESH, val);
4306 }
4307
1da177e4
LT		 4308 return err;
4309}
4310
df3e6548
MC		 4311/* This is called whenever we suspect that the system chipset is re-
4312 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4313 * is bogus tx completions. We try to recover by setting the
4314 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4315 * in the workqueue.
4316 */
4317static void tg3_tx_recover(struct tg3 *tp)
4318{
4319 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4320 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4321
4322 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4323 "mapped I/O cycles to the network device, attempting to "
4324 "recover. Please report the problem to the driver maintainer "
4325 "and include system chipset information.\n", tp->dev->name);
4326
4327 spin_lock(&tp->lock);
df3e6548 4328 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4329 spin_unlock(&tp->lock);
4330}
4331
f3f3f27e 4332static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4333{
4334 smp_mb();
f3f3f27e
MC		 4335 return tnapi->tx_pending -
4336 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4337}
4338
1da177e4
LT		 4339/* Tigon3 never reports partial packet sends. So we do not
4340 * need special logic to handle SKBs that have not had all
4341 * of their frags sent yet, like SunGEM does.
4342 */
17375d25 4343static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4344{
17375d25 4345 struct tg3 *tp = tnapi->tp;
898a56f8 4346 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4347 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4348 struct netdev_queue *txq;
4349 int index = tnapi - tp->napi;
4350
4351 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4352 index--;
4353
4354 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4355
4356 while (sw_idx != hw_idx) {
f3f3f27e 4357 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4358 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4359 int i, tx_bug = 0;
4360
4361 if (unlikely(skb == NULL)) {
4362 tg3_tx_recover(tp);
4363 return;
4364 }
1da177e4 4365
90079ce8 4366 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4367
4368 ri->skb = NULL;
4369
4370 sw_idx = NEXT_TX(sw_idx);
4371
4372 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4373 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4374 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4375 tx_bug = 1;
1da177e4
LT		 4376 sw_idx = NEXT_TX(sw_idx);
4377 }
4378
f47c11ee 4379 dev_kfree_skb(skb);
df3e6548
MC		 4380
4381 if (unlikely(tx_bug)) {
4382 tg3_tx_recover(tp);
4383 return;
4384 }
1da177e4
LT		 4385 }
4386
f3f3f27e 4387 tnapi->tx_cons = sw_idx;
1da177e4 4388
1b2a7205
MC		 4389 /* Need to make the tx_cons update visible to tg3_start_xmit()
4390 * before checking for netif_queue_stopped(). Without the
4391 * memory barrier, there is a small possibility that tg3_start_xmit()
4392 * will miss it and cause the queue to be stopped forever.
4393 */
4394 smp_mb();
4395
fe5f5787 4396 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4397 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4398 __netif_tx_lock(txq, smp_processor_id());
4399 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4400 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4401 netif_tx_wake_queue(txq);
4402 __netif_tx_unlock(txq);
51b91468 4403 }
1da177e4
LT		 4404}
4405
2b2cdb65
MC		 4406static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4407{
4408 if (!ri->skb)
4409 return;
4410
4411 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4412 map_sz, PCI_DMA_FROMDEVICE);
4413 dev_kfree_skb_any(ri->skb);
4414 ri->skb = NULL;
4415}
4416
1da177e4
LT		 4417/* Returns size of skb allocated or < 0 on error.
4418 *
4419 * We only need to fill in the address because the other members
4420 * of the RX descriptor are invariant, see tg3_init_rings.
4421 *
4422 * Note the purposeful assymetry of cpu vs. chip accesses. For
4423 * posting buffers we only dirty the first cache line of the RX
4424 * descriptor (containing the address). Whereas for the RX status
4425 * buffers the cpu only reads the last cacheline of the RX descriptor
4426 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4427 */
86b21e59 4428static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
a3896167 4429 u32 opaque_key, u32 dest_idx_unmasked)
1da177e4
LT		 4430{
4431 struct tg3_rx_buffer_desc *desc;
4432 struct ring_info *map, *src_map;
4433 struct sk_buff *skb;
4434 dma_addr_t mapping;
4435 int skb_size, dest_idx;
4436
4437 src_map = NULL;
4438 switch (opaque_key) {
4439 case RXD_OPAQUE_RING_STD:
4440 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4441 desc = &tpr->rx_std[dest_idx];
4442 map = &tpr->rx_std_buffers[dest_idx];
287be12e 4443 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4444 break;
4445
4446 case RXD_OPAQUE_RING_JUMBO:
4447 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4448 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4449 map = &tpr->rx_jmb_buffers[dest_idx];
287be12e 4450 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4451 break;
4452
4453 default:
4454 return -EINVAL;
855e1111 4455 }
1da177e4
LT		 4456
4457 /* Do not overwrite any of the map or rp information
4458 * until we are sure we can commit to a new buffer.
4459 *
4460 * Callers depend upon this behavior and assume that
4461 * we leave everything unchanged if we fail.
4462 */
287be12e 4463 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4464 if (skb == NULL)
4465 return -ENOMEM;
4466
1da177e4
LT		 4467 skb_reserve(skb, tp->rx_offset);
4468
287be12e 4469 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4470 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4471 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4472 dev_kfree_skb(skb);
4473 return -EIO;
4474 }
1da177e4
LT		 4475
4476 map->skb = skb;
4477 pci_unmap_addr_set(map, mapping, mapping);
4478
1da177e4
LT		 4479 desc->addr_hi = ((u64)mapping >> 32);
4480 desc->addr_lo = ((u64)mapping & 0xffffffff);
4481
4482 return skb_size;
4483}
4484
4485/* We only need to move over in the address because the other
4486 * members of the RX descriptor are invariant. See notes above
4487 * tg3_alloc_rx_skb for full details.
4488 */
a3896167
MC		 4489static void tg3_recycle_rx(struct tg3_napi *tnapi,
4490 struct tg3_rx_prodring_set *dpr,
4491 u32 opaque_key, int src_idx,
4492 u32 dest_idx_unmasked)
1da177e4 4493{
17375d25 4494 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4495 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4496 struct ring_info *src_map, *dest_map;
4497 int dest_idx;
a3896167 4498 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
1da177e4
LT		 4499
4500 switch (opaque_key) {
4501 case RXD_OPAQUE_RING_STD:
4502 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
a3896167
MC		 4503 dest_desc = &dpr->rx_std[dest_idx];
4504 dest_map = &dpr->rx_std_buffers[dest_idx];
4505 src_desc = &spr->rx_std[src_idx];
4506 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 4507 break;
4508
4509 case RXD_OPAQUE_RING_JUMBO:
4510 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
a3896167
MC		 4511 dest_desc = &dpr->rx_jmb[dest_idx].std;
4512 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4513 src_desc = &spr->rx_jmb[src_idx].std;
4514 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4515 break;
4516
4517 default:
4518 return;
855e1111 4519 }
1da177e4
LT		 4520
4521 dest_map->skb = src_map->skb;
4522 pci_unmap_addr_set(dest_map, mapping,
4523 pci_unmap_addr(src_map, mapping));
4524 dest_desc->addr_hi = src_desc->addr_hi;
4525 dest_desc->addr_lo = src_desc->addr_lo;
1da177e4
LT		 4526 src_map->skb = NULL;
4527}
4528
1da177e4
LT		 4529/* The RX ring scheme is composed of multiple rings which post fresh
4530 * buffers to the chip, and one special ring the chip uses to report
4531 * status back to the host.
4532 *
4533 * The special ring reports the status of received packets to the
4534 * host. The chip does not write into the original descriptor the
4535 * RX buffer was obtained from. The chip simply takes the original
4536 * descriptor as provided by the host, updates the status and length
4537 * field, then writes this into the next status ring entry.
4538 *
4539 * Each ring the host uses to post buffers to the chip is described
4540 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4541 * it is first placed into the on-chip ram. When the packet's length
4542 * is known, it walks down the TG3_BDINFO entries to select the ring.
4543 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4544 * which is within the range of the new packet's length is chosen.
4545 *
4546 * The "separate ring for rx status" scheme may sound queer, but it makes
4547 * sense from a cache coherency perspective. If only the host writes
4548 * to the buffer post rings, and only the chip writes to the rx status
4549 * rings, then cache lines never move beyond shared-modified state.
4550 * If both the host and chip were to write into the same ring, cache line
4551 * eviction could occur since both entities want it in an exclusive state.
4552 */
17375d25 4553static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4554{
17375d25 4555 struct tg3 *tp = tnapi->tp;
f92905de 4556 u32 work_mask, rx_std_posted = 0;
4361935a 4557 u32 std_prod_idx, jmb_prod_idx;
72334482 4558 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4559 u16 hw_idx;
1da177e4 4560 int received;
21f581a5 4561 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4562
8d9d7cfc 4563 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4564 /*
4565 * We need to order the read of hw_idx and the read of
4566 * the opaque cookie.
4567 */
4568 rmb();
1da177e4
LT		 4569 work_mask = 0;
4570 received = 0;
4361935a
MC		 4571 std_prod_idx = tpr->rx_std_prod_idx;
4572 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 4573 while (sw_idx != hw_idx && budget > 0) {
afc081f8 4574 struct ring_info *ri;
72334482 4575 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4576 unsigned int len;
4577 struct sk_buff *skb;
4578 dma_addr_t dma_addr;
4579 u32 opaque_key, desc_idx, *post_ptr;
4580
4581 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4582 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4583 if (opaque_key == RXD_OPAQUE_RING_STD) {
afc081f8 4584 ri = &tpr->rx_std_buffers[desc_idx];
21f581a5
MC		 4585 dma_addr = pci_unmap_addr(ri, mapping);
4586 skb = ri->skb;
4361935a 4587 post_ptr = &std_prod_idx;
f92905de 4588 rx_std_posted++;
1da177e4 4589 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
afc081f8 4590 ri = &tpr->rx_jmb_buffers[desc_idx];
21f581a5
MC		 4591 dma_addr = pci_unmap_addr(ri, mapping);
4592 skb = ri->skb;
4361935a 4593 post_ptr = &jmb_prod_idx;
21f581a5 4594 } else
1da177e4 4595 goto next_pkt_nopost;
1da177e4
LT		 4596
4597 work_mask |= opaque_key;
4598
4599 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4600 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4601 drop_it:
a3896167 4602 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4603 desc_idx, *post_ptr);
4604 drop_it_no_recycle:
4605 /* Other statistics kept track of by card. */
4606 tp->net_stats.rx_dropped++;
4607 goto next_pkt;
4608 }
4609
ad829268
MC		 4610 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4611 ETH_FCS_LEN;
1da177e4 4612
6aa20a22 4613 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4614 && tp->rx_offset == NET_IP_ALIGN
4615 /* rx_offset will likely not equal NET_IP_ALIGN
4616 * if this is a 5701 card running in PCI-X mode
4617 * [see tg3_get_invariants()]
4618 */
1da177e4
LT		 4619 ) {
4620 int skb_size;
4621
86b21e59 4622 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
afc081f8 4623 *post_ptr);
1da177e4
LT		 4624 if (skb_size < 0)
4625 goto drop_it;
4626
afc081f8
MC		 4627 ri->skb = NULL;
4628
287be12e 4629 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4630 PCI_DMA_FROMDEVICE);
4631
4632 skb_put(skb, len);
4633 } else {
4634 struct sk_buff *copy_skb;
4635
a3896167 4636 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 4637 desc_idx, *post_ptr);
4638
ad829268
MC		 4639 copy_skb = netdev_alloc_skb(tp->dev,
4640 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4641 if (copy_skb == NULL)
4642 goto drop_it_no_recycle;
4643
ad829268 4644 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4645 skb_put(copy_skb, len);
4646 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4647 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4648 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4649
4650 /* We'll reuse the original ring buffer. */
4651 skb = copy_skb;
4652 }
4653
4654 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4655 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4656 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4657 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4658 skb->ip_summed = CHECKSUM_UNNECESSARY;
4659 else
4660 skb->ip_summed = CHECKSUM_NONE;
4661
4662 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4663
4664 if (len > (tp->dev->mtu + ETH_HLEN) &&
4665 skb->protocol != htons(ETH_P_8021Q)) {
4666 dev_kfree_skb(skb);
4667 goto next_pkt;
4668 }
4669
1da177e4
LT		 4670#if TG3_VLAN_TAG_USED
4671 if (tp->vlgrp != NULL &&
4672 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4673 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4674 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4675 } else
4676#endif
17375d25 4677 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4678
1da177e4
LT		 4679 received++;
4680 budget--;
4681
4682next_pkt:
4683 (*post_ptr)++;
f92905de
MC		 4684
4685 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4686 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4687
4688 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4689 TG3_64BIT_REG_LOW, idx);
4690 work_mask &= ~RXD_OPAQUE_RING_STD;
4691 rx_std_posted = 0;
4692 }
1da177e4 4693next_pkt_nopost:
483ba50b 4694 sw_idx++;
6b31a515 4695 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4696
4697 /* Refresh hw_idx to see if there is new work */
4698 if (sw_idx == hw_idx) {
8d9d7cfc 4699 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4700 rmb();
4701 }
1da177e4
LT		 4702 }
4703
4704 /* ACK the status ring. */
72334482
MC		 4705 tnapi->rx_rcb_ptr = sw_idx;
4706 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4707
4708 /* Refill RX ring(s). */
4709 if (work_mask & RXD_OPAQUE_RING_STD) {
4361935a 4710 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
1da177e4 4711 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4361935a 4712 tpr->rx_std_prod_idx);
1da177e4
LT		 4713 }
4714 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4361935a 4715 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
1da177e4 4716 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4361935a 4717 tpr->rx_jmb_prod_idx);
1da177e4
LT		 4718 }
4719 mmiowb();
4720
4721 return received;
4722}
4723
35f2d7d0 4724static void tg3_poll_link(struct tg3 *tp)
1da177e4 4725{
1da177e4
LT		 4726 /* handle link change and other phy events */
4727 if (!(tp->tg3_flags &
4728 (TG3_FLAG_USE_LINKCHG_REG |
4729 TG3_FLAG_POLL_SERDES))) {
35f2d7d0
MC		 4730 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4731
1da177e4
LT		 4732 if (sblk->status & SD_STATUS_LINK_CHG) {
4733 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 4734 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4735 spin_lock(&tp->lock);
dd477003
MC		 4736 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4737 tw32_f(MAC_STATUS,
4738 (MAC_STATUS_SYNC_CHANGED |
4739 MAC_STATUS_CFG_CHANGED |
4740 MAC_STATUS_MI_COMPLETION |
4741 MAC_STATUS_LNKSTATE_CHANGED));
4742 udelay(40);
4743 } else
4744 tg3_setup_phy(tp, 0);
f47c11ee 4745 spin_unlock(&tp->lock);
1da177e4
LT		 4746 }
4747 }
35f2d7d0
MC		 4748}
4749
4750static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4751{
4752 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4753
4754 /* run TX completion thread */
f3f3f27e 4755 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4756 tg3_tx(tnapi);
6f535763 4757 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4758 return work_done;
1da177e4
LT		 4759 }
4760
1da177e4
LT		 4761 /* run RX thread, within the bounds set by NAPI.
4762 * All RX "locking" is done by ensuring outside
bea3348e 4763 * code synchronizes with tg3->napi.poll()
1da177e4 4764 */
8d9d7cfc 4765 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4766 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4767
6f535763
DM		 4768 return work_done;
4769}
4770
35f2d7d0
MC		 4771static int tg3_poll_msix(struct napi_struct *napi, int budget)
4772{
4773 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4774 struct tg3 *tp = tnapi->tp;
4775 int work_done = 0;
4776 struct tg3_hw_status *sblk = tnapi->hw_status;
4777
4778 while (1) {
4779 work_done = tg3_poll_work(tnapi, work_done, budget);
4780
4781 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4782 goto tx_recovery;
4783
4784 if (unlikely(work_done >= budget))
4785 break;
4786
4787 /* tp->last_tag is used in tg3_restart_ints() below
4788 * to tell the hw how much work has been processed,
4789 * so we must read it before checking for more work.
4790 */
4791 tnapi->last_tag = sblk->status_tag;
4792 tnapi->last_irq_tag = tnapi->last_tag;
4793 rmb();
4794
4795 /* check for RX/TX work to do */
4796 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4797 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4798 napi_complete(napi);
4799 /* Reenable interrupts. */
4800 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4801 mmiowb();
4802 break;
4803 }
4804 }
4805
4806 return work_done;
4807
4808tx_recovery:
4809 /* work_done is guaranteed to be less than budget. */
4810 napi_complete(napi);
4811 schedule_work(&tp->reset_task);
4812 return work_done;
4813}
4814
6f535763
DM		 4815static int tg3_poll(struct napi_struct *napi, int budget)
4816{
8ef0442f
MC		 4817 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4818 struct tg3 *tp = tnapi->tp;
6f535763 4819 int work_done = 0;
898a56f8 4820 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4821
4822 while (1) {
35f2d7d0
MC		 4823 tg3_poll_link(tp);
4824
17375d25 4825 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4826
4827 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4828 goto tx_recovery;
4829
4830 if (unlikely(work_done >= budget))
4831 break;
4832
4fd7ab59 4833 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4834 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4835 * to tell the hw how much work has been processed,
4836 * so we must read it before checking for more work.
4837 */
898a56f8
MC		 4838 tnapi->last_tag = sblk->status_tag;
4839 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4840 rmb();
4841 } else
4842 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4843
17375d25 4844 if (likely(!tg3_has_work(tnapi))) {
288379f0 4845 napi_complete(napi);
17375d25 4846 tg3_int_reenable(tnapi);
6f535763
DM		 4847 break;
4848 }
1da177e4
LT		 4849 }
4850
bea3348e 4851 return work_done;
6f535763
DM		 4852
4853tx_recovery:
4fd7ab59 4854 /* work_done is guaranteed to be less than budget. */
288379f0 4855 napi_complete(napi);
6f535763 4856 schedule_work(&tp->reset_task);
4fd7ab59 4857 return work_done;
1da177e4
LT		 4858}
4859
f47c11ee
DM		 4860static void tg3_irq_quiesce(struct tg3 *tp)
4861{
4f125f42
MC		 4862 int i;
4863
f47c11ee
DM		 4864 BUG_ON(tp->irq_sync);
4865
4866 tp->irq_sync = 1;
4867 smp_mb();
4868
4f125f42
MC		 4869 for (i = 0; i < tp->irq_cnt; i++)
4870 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4871}
4872
4873static inline int tg3_irq_sync(struct tg3 *tp)
4874{
4875 return tp->irq_sync;
4876}
4877
4878/* Fully shutdown all tg3 driver activity elsewhere in the system.
4879 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4880 * with as well. Most of the time, this is not necessary except when
4881 * shutting down the device.
4882 */
4883static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4884{
46966545 4885 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4886 if (irq_sync)
4887 tg3_irq_quiesce(tp);
f47c11ee
DM		 4888}
4889
4890static inline void tg3_full_unlock(struct tg3 *tp)
4891{
f47c11ee
DM		 4892 spin_unlock_bh(&tp->lock);
4893}
4894
fcfa0a32
MC		 4895/* One-shot MSI handler - Chip automatically disables interrupt
4896 * after sending MSI so driver doesn't have to do it.
4897 */
7d12e780 4898static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4899{
09943a18
MC		 4900 struct tg3_napi *tnapi = dev_id;
4901 struct tg3 *tp = tnapi->tp;
fcfa0a32 4902
898a56f8 4903 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4904 if (tnapi->rx_rcb)
4905 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4906
4907 if (likely(!tg3_irq_sync(tp)))
09943a18 4908 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4909
4910 return IRQ_HANDLED;
4911}
4912
88b06bc2
MC		 4913/* MSI ISR - No need to check for interrupt sharing and no need to
4914 * flush status block and interrupt mailbox. PCI ordering rules
4915 * guarantee that MSI will arrive after the status block.
4916 */
7d12e780 4917static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4918{
09943a18
MC		 4919 struct tg3_napi *tnapi = dev_id;
4920 struct tg3 *tp = tnapi->tp;
88b06bc2 4921
898a56f8 4922 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4923 if (tnapi->rx_rcb)
4924 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4925 /*
fac9b83e 4926 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4927 * chip-internal interrupt pending events.
fac9b83e 4928 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4929 * NIC to stop sending us irqs, engaging "in-intr-handler"
4930 * event coalescing.
4931 */
4932 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4933 if (likely(!tg3_irq_sync(tp)))
09943a18 4934 napi_schedule(&tnapi->napi);
61487480 4935
88b06bc2
MC		 4936 return IRQ_RETVAL(1);
4937}
4938
7d12e780 4939static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4940{
09943a18
MC		 4941 struct tg3_napi *tnapi = dev_id;
4942 struct tg3 *tp = tnapi->tp;
898a56f8 4943 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4944 unsigned int handled = 1;
4945
1da177e4
LT		 4946 /* In INTx mode, it is possible for the interrupt to arrive at
4947 * the CPU before the status block posted prior to the interrupt.
4948 * Reading the PCI State register will confirm whether the
4949 * interrupt is ours and will flush the status block.
4950 */
d18edcb2
MC		 4951 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4952 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4953 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4954 handled = 0;
f47c11ee 4955 goto out;
fac9b83e 4956 }
d18edcb2
MC		 4957 }
4958
4959 /*
4960 * Writing any value to intr-mbox-0 clears PCI INTA# and
4961 * chip-internal interrupt pending events.
4962 * Writing non-zero to intr-mbox-0 additional tells the
4963 * NIC to stop sending us irqs, engaging "in-intr-handler"
4964 * event coalescing.
c04cb347
MC		 4965 *
4966 * Flush the mailbox to de-assert the IRQ immediately to prevent
4967 * spurious interrupts. The flush impacts performance but
4968 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4969 */
c04cb347 4970 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4971 if (tg3_irq_sync(tp))
4972 goto out;
4973 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4974 if (likely(tg3_has_work(tnapi))) {
72334482 4975 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4976 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4977 } else {
4978 /* No work, shared interrupt perhaps? re-enable
4979 * interrupts, and flush that PCI write
4980 */
4981 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4982 0x00000000);
fac9b83e 4983 }
f47c11ee 4984out:
fac9b83e
DM		 4985 return IRQ_RETVAL(handled);
4986}
4987
7d12e780 4988static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4989{
09943a18
MC		 4990 struct tg3_napi *tnapi = dev_id;
4991 struct tg3 *tp = tnapi->tp;
898a56f8 4992 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4993 unsigned int handled = 1;
4994
fac9b83e
DM		 4995 /* In INTx mode, it is possible for the interrupt to arrive at
4996 * the CPU before the status block posted prior to the interrupt.
4997 * Reading the PCI State register will confirm whether the
4998 * interrupt is ours and will flush the status block.
4999 */
898a56f8 5000 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 5001 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5002 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5003 handled = 0;
f47c11ee 5004 goto out;
1da177e4 5005 }
d18edcb2
MC		 5006 }
5007
5008 /*
5009 * writing any value to intr-mbox-0 clears PCI INTA# and
5010 * chip-internal interrupt pending events.
5011 * writing non-zero to intr-mbox-0 additional tells the
5012 * NIC to stop sending us irqs, engaging "in-intr-handler"
5013 * event coalescing.
c04cb347
MC		 5014 *
5015 * Flush the mailbox to de-assert the IRQ immediately to prevent
5016 * spurious interrupts. The flush impacts performance but
5017 * excessive spurious interrupts can be worse in some cases.
d18edcb2 5018 */
c04cb347 5019 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 5020
5021 /*
5022 * In a shared interrupt configuration, sometimes other devices'
5023 * interrupts will scream. We record the current status tag here
5024 * so that the above check can report that the screaming interrupts
5025 * are unhandled. Eventually they will be silenced.
5026 */
898a56f8 5027 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 5028
d18edcb2
MC		 5029 if (tg3_irq_sync(tp))
5030 goto out;
624f8e50 5031
72334482 5032 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 5033
09943a18 5034 napi_schedule(&tnapi->napi);
624f8e50 5035
f47c11ee 5036out:
1da177e4
LT		 5037 return IRQ_RETVAL(handled);
5038}
5039
7938109f 5040/* ISR for interrupt test */
7d12e780 5041static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 5042{
09943a18
MC		 5043 struct tg3_napi *tnapi = dev_id;
5044 struct tg3 *tp = tnapi->tp;
898a56f8 5045 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 5046
f9804ddb
MC		 5047 if ((sblk->status & SD_STATUS_UPDATED) ||
5048 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 5049 tg3_disable_ints(tp);
7938109f
MC		 5050 return IRQ_RETVAL(1);
5051 }
5052 return IRQ_RETVAL(0);
5053}
5054
8e7a22e3 5055static int tg3_init_hw(struct tg3 *, int);
944d980e 5056static int tg3_halt(struct tg3 *, int, int);
1da177e4 5057
b9ec6c1b
MC		 5058/* Restart hardware after configuration changes, self-test, etc.
5059 * Invoked with tp->lock held.
5060 */
5061static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 5062 __releases(tp->lock)
5063 __acquires(tp->lock)
b9ec6c1b
MC		 5064{
5065 int err;
5066
5067 err = tg3_init_hw(tp, reset_phy);
5068 if (err) {
5069 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5070 "aborting.\n", tp->dev->name);
5071 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5072 tg3_full_unlock(tp);
5073 del_timer_sync(&tp->timer);
5074 tp->irq_sync = 0;
fed97810 5075 tg3_napi_enable(tp);
b9ec6c1b
MC		 5076 dev_close(tp->dev);
5077 tg3_full_lock(tp, 0);
5078 }
5079 return err;
5080}
5081
1da177e4
LT		 5082#ifdef CONFIG_NET_POLL_CONTROLLER
5083static void tg3_poll_controller(struct net_device *dev)
5084{
4f125f42 5085 int i;
88b06bc2
MC		 5086 struct tg3 *tp = netdev_priv(dev);
5087
4f125f42
MC		 5088 for (i = 0; i < tp->irq_cnt; i++)
5089 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5090}
5091#endif
5092
c4028958 5093static void tg3_reset_task(struct work_struct *work)
1da177e4 5094{
c4028958 5095 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5096 int err;
1da177e4
LT		 5097 unsigned int restart_timer;
5098
7faa006f 5099 tg3_full_lock(tp, 0);
7faa006f
MC		 5100
5101 if (!netif_running(tp->dev)) {
7faa006f
MC		 5102 tg3_full_unlock(tp);
5103 return;
5104 }
5105
5106 tg3_full_unlock(tp);
5107
b02fd9e3
MC		 5108 tg3_phy_stop(tp);
5109
1da177e4
LT		 5110 tg3_netif_stop(tp);
5111
f47c11ee 5112 tg3_full_lock(tp, 1);
1da177e4
LT		 5113
5114 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5115 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5116
df3e6548
MC		 5117 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5118 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5119 tp->write32_rx_mbox = tg3_write_flush_reg32;
5120 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5121 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5122 }
5123
944d980e 5124 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5125 err = tg3_init_hw(tp, 1);
5126 if (err)
b9ec6c1b 5127 goto out;
1da177e4
LT		 5128
5129 tg3_netif_start(tp);
5130
1da177e4
LT		 5131 if (restart_timer)
5132 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5133
b9ec6c1b 5134out:
7faa006f 5135 tg3_full_unlock(tp);
b02fd9e3
MC		 5136
5137 if (!err)
5138 tg3_phy_start(tp);
1da177e4
LT		 5139}
5140
b0408751
MC		 5141static void tg3_dump_short_state(struct tg3 *tp)
5142{
5143 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5144 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5145 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5146 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5147}
5148
1da177e4
LT		 5149static void tg3_tx_timeout(struct net_device *dev)
5150{
5151 struct tg3 *tp = netdev_priv(dev);
5152
b0408751 5153 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5154 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5155 dev->name);
b0408751
MC		 5156 tg3_dump_short_state(tp);
5157 }
1da177e4
LT		 5158
5159 schedule_work(&tp->reset_task);
5160}
5161
c58ec932
MC		 5162/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5163static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5164{
5165 u32 base = (u32) mapping & 0xffffffff;
5166
5167 return ((base > 0xffffdcc0) &&
5168 (base + len + 8 < base));
5169}
5170
72f2afb8
MC		 5171/* Test for DMA addresses > 40-bit */
5172static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5173 int len)
5174{
5175#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5176 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5177 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5178 return 0;
5179#else
5180 return 0;
5181#endif
5182}
5183
f3f3f27e 5184static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5185
72f2afb8 5186/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4
MC		 5187static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5188 struct sk_buff *skb, u32 last_plus_one,
5189 u32 *start, u32 base_flags, u32 mss)
1da177e4 5190{
24f4efd4 5191 struct tg3 *tp = tnapi->tp;
41588ba1 5192 struct sk_buff *new_skb;
c58ec932 5193 dma_addr_t new_addr = 0;
1da177e4 5194 u32 entry = *start;
c58ec932 5195 int i, ret = 0;
1da177e4 5196
41588ba1
MC		 5197 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5198 new_skb = skb_copy(skb, GFP_ATOMIC);
5199 else {
5200 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5201
5202 new_skb = skb_copy_expand(skb,
5203 skb_headroom(skb) + more_headroom,
5204 skb_tailroom(skb), GFP_ATOMIC);
5205 }
5206
1da177e4 5207 if (!new_skb) {
c58ec932
MC		 5208 ret = -1;
5209 } else {
5210 /* New SKB is guaranteed to be linear. */
5211 entry = *start;
90079ce8 5212 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5213 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5214
c58ec932
MC		 5215 /* Make sure new skb does not cross any 4G boundaries.
5216 * Drop the packet if it does.
5217 */
0e1406dd
MC		 5218 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5219 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5220 if (!ret)
5221 skb_dma_unmap(&tp->pdev->dev, new_skb,
5222 DMA_TO_DEVICE);
c58ec932
MC		 5223 ret = -1;
5224 dev_kfree_skb(new_skb);
5225 new_skb = NULL;
5226 } else {
f3f3f27e 5227 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5228 base_flags, 1 | (mss << 1));
5229 *start = NEXT_TX(entry);
5230 }
1da177e4
LT		 5231 }
5232
1da177e4
LT		 5233 /* Now clean up the sw ring entries. */
5234 i = 0;
5235 while (entry != last_plus_one) {
f3f3f27e
MC		 5236 if (i == 0)
5237 tnapi->tx_buffers[entry].skb = new_skb;
5238 else
5239 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5240 entry = NEXT_TX(entry);
5241 i++;
5242 }
5243
90079ce8 5244 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5245 dev_kfree_skb(skb);
5246
c58ec932 5247 return ret;
1da177e4
LT		 5248}
5249
f3f3f27e 5250static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5251 dma_addr_t mapping, int len, u32 flags,
5252 u32 mss_and_is_end)
5253{
f3f3f27e 5254 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5255 int is_end = (mss_and_is_end & 0x1);
5256 u32 mss = (mss_and_is_end >> 1);
5257 u32 vlan_tag = 0;
5258
5259 if (is_end)
5260 flags |= TXD_FLAG_END;
5261 if (flags & TXD_FLAG_VLAN) {
5262 vlan_tag = flags >> 16;
5263 flags &= 0xffff;
5264 }
5265 vlan_tag |= (mss << TXD_MSS_SHIFT);
5266
5267 txd->addr_hi = ((u64) mapping >> 32);
5268 txd->addr_lo = ((u64) mapping & 0xffffffff);
5269 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5270 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5271}
5272
5a6f3074 5273/* hard_start_xmit for devices that don't have any bugs and
e849cdc3 5274 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5a6f3074 5275 */
61357325
SH		 5276static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5277 struct net_device *dev)
5a6f3074
MC		 5278{
5279 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5280 u32 len, entry, base_flags, mss;
90079ce8
DM		 5281 struct skb_shared_info *sp;
5282 dma_addr_t mapping;
fe5f5787
MC		 5283 struct tg3_napi *tnapi;
5284 struct netdev_queue *txq;
5a6f3074 5285
fe5f5787
MC		 5286 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5287 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5288 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5289 tnapi++;
5a6f3074 5290
00b70504 5291 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5292 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5293 * interrupt. Furthermore, IRQ processing runs lockless so we have
5294 * no IRQ context deadlocks to worry about either. Rejoice!
5295 */
f3f3f27e 5296 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5297 if (!netif_tx_queue_stopped(txq)) {
5298 netif_tx_stop_queue(txq);
5a6f3074
MC		 5299
5300 /* This is a hard error, log it. */
5301 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5302 "queue awake!\n", dev->name);
5303 }
5a6f3074
MC		 5304 return NETDEV_TX_BUSY;
5305 }
5306
f3f3f27e 5307 entry = tnapi->tx_prod;
5a6f3074 5308 base_flags = 0;
5a6f3074 5309 mss = 0;
c13e3713 5310 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5311 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5312 u32 hdrlen;
5a6f3074
MC		 5313
5314 if (skb_header_cloned(skb) &&
5315 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5316 dev_kfree_skb(skb);
5317 goto out_unlock;
5318 }
5319
b0026624 5320 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5321 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5322 else {
eddc9ec5
ACM		 5323 struct iphdr *iph = ip_hdr(skb);
5324
ab6a5bb6 5325 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5326 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5327
eddc9ec5
ACM		 5328 iph->check = 0;
5329 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5330 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5331 }
5a6f3074 5332
e849cdc3 5333 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
f6eb9b1f
MC		 5334 mss |= (hdrlen & 0xc) << 12;
5335 if (hdrlen & 0x10)
5336 base_flags |= 0x00000010;
5337 base_flags |= (hdrlen & 0x3e0) << 5;
5338 } else
5339 mss |= hdrlen << 9;
5340
5a6f3074
MC		 5341 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5342 TXD_FLAG_CPU_POST_DMA);
5343
aa8223c7 5344 tcp_hdr(skb)->check = 0;
5a6f3074 5345
5a6f3074 5346 }
84fa7933 5347 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5348 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5349#if TG3_VLAN_TAG_USED
5350 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5351 base_flags |= (TXD_FLAG_VLAN |
5352 (vlan_tx_tag_get(skb) << 16));
5353#endif
5354
90079ce8
DM		 5355 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5356 dev_kfree_skb(skb);
5357 goto out_unlock;
5358 }
5359
5360 sp = skb_shinfo(skb);
5361
042a53a9 5362 mapping = sp->dma_head;
5a6f3074 5363
f3f3f27e 5364 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5365
fe5f5787
MC		 5366 len = skb_headlen(skb);
5367
f6eb9b1f
MC		 5368 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5369 !mss && skb->len > ETH_DATA_LEN)
5370 base_flags |= TXD_FLAG_JMB_PKT;
5371
f3f3f27e 5372 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5373 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5374
5375 entry = NEXT_TX(entry);
5376
5377 /* Now loop through additional data fragments, and queue them. */
5378 if (skb_shinfo(skb)->nr_frags > 0) {
5379 unsigned int i, last;
5380
5381 last = skb_shinfo(skb)->nr_frags - 1;
5382 for (i = 0; i <= last; i++) {
5383 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5384
5385 len = frag->size;
042a53a9 5386 mapping = sp->dma_maps[i];
f3f3f27e 5387 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5388
f3f3f27e 5389 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5390 base_flags, (i == last) | (mss << 1));
5391
5392 entry = NEXT_TX(entry);
5393 }
5394 }
5395
5396 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5397 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5398
f3f3f27e
MC		 5399 tnapi->tx_prod = entry;
5400 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5401 netif_tx_stop_queue(txq);
f3f3f27e 5402 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5403 netif_tx_wake_queue(txq);
5a6f3074
MC		 5404 }
5405
5406out_unlock:
cdd0db05 5407 mmiowb();
5a6f3074
MC		 5408
5409 return NETDEV_TX_OK;
5410}
5411
61357325
SH		 5412static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5413 struct net_device *);
52c0fd83
MC		 5414
5415/* Use GSO to workaround a rare TSO bug that may be triggered when the
5416 * TSO header is greater than 80 bytes.
5417 */
5418static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5419{
5420 struct sk_buff *segs, *nskb;
f3f3f27e 5421 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5422
5423 /* Estimate the number of fragments in the worst case */
f3f3f27e 5424 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5425 netif_stop_queue(tp->dev);
f3f3f27e 5426 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5427 return NETDEV_TX_BUSY;
5428
5429 netif_wake_queue(tp->dev);
52c0fd83
MC		 5430 }
5431
5432 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5433 if (IS_ERR(segs))
52c0fd83
MC		 5434 goto tg3_tso_bug_end;
5435
5436 do {
5437 nskb = segs;
5438 segs = segs->next;
5439 nskb->next = NULL;
5440 tg3_start_xmit_dma_bug(nskb, tp->dev);
5441 } while (segs);
5442
5443tg3_tso_bug_end:
5444 dev_kfree_skb(skb);
5445
5446 return NETDEV_TX_OK;
5447}
52c0fd83 5448
5a6f3074
MC		 5449/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5450 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5451 */
61357325
SH		 5452static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5453 struct net_device *dev)
1da177e4
LT		 5454{
5455 struct tg3 *tp = netdev_priv(dev);
1da177e4 5456 u32 len, entry, base_flags, mss;
90079ce8 5457 struct skb_shared_info *sp;
1da177e4 5458 int would_hit_hwbug;
90079ce8 5459 dma_addr_t mapping;
24f4efd4
MC		 5460 struct tg3_napi *tnapi;
5461 struct netdev_queue *txq;
1da177e4 5462
24f4efd4
MC		 5463 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5464 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5465 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5466 tnapi++;
1da177e4 5467
00b70504 5468 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5469 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5470 * interrupt. Furthermore, IRQ processing runs lockless so we have
5471 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5472 */
f3f3f27e 5473 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 5474 if (!netif_tx_queue_stopped(txq)) {
5475 netif_tx_stop_queue(txq);
1f064a87
SH		 5476
5477 /* This is a hard error, log it. */
5478 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5479 "queue awake!\n", dev->name);
5480 }
1da177e4
LT		 5481 return NETDEV_TX_BUSY;
5482 }
5483
f3f3f27e 5484 entry = tnapi->tx_prod;
1da177e4 5485 base_flags = 0;
84fa7933 5486 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5487 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 5488
c13e3713 5489 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5490 struct iphdr *iph;
92c6b8d1 5491 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5492
5493 if (skb_header_cloned(skb) &&
5494 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5495 dev_kfree_skb(skb);
5496 goto out_unlock;
5497 }
5498
ab6a5bb6 5499 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5500 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5501
52c0fd83
MC		 5502 hdr_len = ip_tcp_len + tcp_opt_len;
5503 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5504 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5505 return (tg3_tso_bug(tp, skb));
5506
1da177e4
LT		 5507 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5508 TXD_FLAG_CPU_POST_DMA);
5509
eddc9ec5
ACM		 5510 iph = ip_hdr(skb);
5511 iph->check = 0;
5512 iph->tot_len = htons(mss + hdr_len);
1da177e4 5513 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5514 tcp_hdr(skb)->check = 0;
1da177e4 5515 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5516 } else
5517 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5518 iph->daddr, 0,
5519 IPPROTO_TCP,
5520 0);
1da177e4 5521
615774fe
MC		 5522 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5523 mss |= (hdr_len & 0xc) << 12;
5524 if (hdr_len & 0x10)
5525 base_flags |= 0x00000010;
5526 base_flags |= (hdr_len & 0x3e0) << 5;
5527 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
92c6b8d1
MC		 5528 mss |= hdr_len << 9;
5529 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5531 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5532 int tsflags;
5533
eddc9ec5 5534 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5535 mss |= (tsflags << 11);
5536 }
5537 } else {
eddc9ec5 5538 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5539 int tsflags;
5540
eddc9ec5 5541 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5542 base_flags |= tsflags << 12;
5543 }
5544 }
5545 }
1da177e4
LT		 5546#if TG3_VLAN_TAG_USED
5547 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5548 base_flags |= (TXD_FLAG_VLAN |
5549 (vlan_tx_tag_get(skb) << 16));
5550#endif
5551
615774fe
MC		 5552 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5553 !mss && skb->len > ETH_DATA_LEN)
5554 base_flags |= TXD_FLAG_JMB_PKT;
5555
90079ce8
DM		 5556 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5557 dev_kfree_skb(skb);
5558 goto out_unlock;
5559 }
5560
5561 sp = skb_shinfo(skb);
5562
042a53a9 5563 mapping = sp->dma_head;
1da177e4 5564
f3f3f27e 5565 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5566
5567 would_hit_hwbug = 0;
5568
24f4efd4
MC		 5569 len = skb_headlen(skb);
5570
92c6b8d1
MC		 5571 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5572 would_hit_hwbug = 1;
5573
0e1406dd
MC		 5574 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5575 tg3_4g_overflow_test(mapping, len))
5576 would_hit_hwbug = 1;
5577
5578 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5579 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5580 would_hit_hwbug = 1;
0e1406dd
MC		 5581
5582 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5583 would_hit_hwbug = 1;
1da177e4 5584
f3f3f27e 5585 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5586 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5587
5588 entry = NEXT_TX(entry);
5589
5590 /* Now loop through additional data fragments, and queue them. */
5591 if (skb_shinfo(skb)->nr_frags > 0) {
5592 unsigned int i, last;
5593
5594 last = skb_shinfo(skb)->nr_frags - 1;
5595 for (i = 0; i <= last; i++) {
5596 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5597
5598 len = frag->size;
042a53a9 5599 mapping = sp->dma_maps[i];
1da177e4 5600
f3f3f27e 5601 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5602
92c6b8d1
MC		 5603 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5604 len <= 8)
5605 would_hit_hwbug = 1;
5606
0e1406dd
MC		 5607 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5608 tg3_4g_overflow_test(mapping, len))
c58ec932 5609 would_hit_hwbug = 1;
1da177e4 5610
0e1406dd
MC		 5611 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5612 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5613 would_hit_hwbug = 1;
5614
1da177e4 5615 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5616 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5617 base_flags, (i == last)|(mss << 1));
5618 else
f3f3f27e 5619 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5620 base_flags, (i == last));
5621
5622 entry = NEXT_TX(entry);
5623 }
5624 }
5625
5626 if (would_hit_hwbug) {
5627 u32 last_plus_one = entry;
5628 u32 start;
1da177e4 5629
c58ec932
MC		 5630 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5631 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5632
5633 /* If the workaround fails due to memory/mapping
5634 * failure, silently drop this packet.
5635 */
24f4efd4 5636 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
c58ec932 5637 &start, base_flags, mss))
1da177e4
LT		 5638 goto out_unlock;
5639
5640 entry = start;
5641 }
5642
5643 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 5644 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 5645
f3f3f27e
MC		 5646 tnapi->tx_prod = entry;
5647 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 5648 netif_tx_stop_queue(txq);
f3f3f27e 5649 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 5650 netif_tx_wake_queue(txq);
51b91468 5651 }
1da177e4
LT		 5652
5653out_unlock:
cdd0db05 5654 mmiowb();
1da177e4
LT		 5655
5656 return NETDEV_TX_OK;
5657}
5658
5659static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5660 int new_mtu)
5661{
5662 dev->mtu = new_mtu;
5663
ef7f5ec0 5664 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5665 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5666 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5667 ethtool_op_set_tso(dev, 0);
5668 }
5669 else
5670 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5671 } else {
a4e2b347 5672 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5673 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5674 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5675 }
1da177e4
LT		 5676}
5677
5678static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5679{
5680 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5681 int err;
1da177e4
LT		 5682
5683 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5684 return -EINVAL;
5685
5686 if (!netif_running(dev)) {
5687 /* We'll just catch it later when the
5688 * device is up'd.
5689 */
5690 tg3_set_mtu(dev, tp, new_mtu);
5691 return 0;
5692 }
5693
b02fd9e3
MC		 5694 tg3_phy_stop(tp);
5695
1da177e4 5696 tg3_netif_stop(tp);
f47c11ee
DM		 5697
5698 tg3_full_lock(tp, 1);
1da177e4 5699
944d980e 5700 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5701
5702 tg3_set_mtu(dev, tp, new_mtu);
5703
b9ec6c1b 5704 err = tg3_restart_hw(tp, 0);
1da177e4 5705
b9ec6c1b
MC		 5706 if (!err)
5707 tg3_netif_start(tp);
1da177e4 5708
f47c11ee 5709 tg3_full_unlock(tp);
1da177e4 5710
b02fd9e3
MC		 5711 if (!err)
5712 tg3_phy_start(tp);
5713
b9ec6c1b 5714 return err;
1da177e4
LT		 5715}
5716
21f581a5
MC		 5717static void tg3_rx_prodring_free(struct tg3 *tp,
5718 struct tg3_rx_prodring_set *tpr)
1da177e4 5719{
1da177e4
LT		 5720 int i;
5721
2b2cdb65
MC		 5722 if (tpr != &tp->prodring[0])
5723 return;
1da177e4 5724
2b2cdb65
MC		 5725 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5726 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5727 tp->rx_pkt_map_sz);
1da177e4 5728
cf7a7298 5729 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65
MC		 5730 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5731 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5732 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 5733 }
5734}
5735
5736/* Initialize tx/rx rings for packet processing.
5737 *
5738 * The chip has been shut down and the driver detached from
5739 * the networking, so no interrupts or new tx packets will
5740 * end up in the driver. tp->{tx,}lock are held and thus
5741 * we may not sleep.
5742 */
21f581a5
MC		 5743static int tg3_rx_prodring_alloc(struct tg3 *tp,
5744 struct tg3_rx_prodring_set *tpr)
1da177e4 5745{
287be12e 5746 u32 i, rx_pkt_dma_sz;
1da177e4 5747
2b2cdb65
MC		 5748 if (tpr != &tp->prodring[0]) {
5749 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5750 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5751 memset(&tpr->rx_jmb_buffers[0], 0,
5752 TG3_RX_JMB_BUFF_RING_SIZE);
5753 goto done;
5754 }
5755
1da177e4 5756 /* Zero out all descriptors. */
21f581a5 5757 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5758
287be12e 5759 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5760 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5761 tp->dev->mtu > ETH_DATA_LEN)
5762 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5763 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5764
1da177e4
LT		 5765 /* Initialize invariants of the rings, we only set this
5766 * stuff once. This works because the card does not
5767 * write into the rx buffer posting rings.
5768 */
5769 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5770 struct tg3_rx_buffer_desc *rxd;
5771
21f581a5 5772 rxd = &tpr->rx_std[i];
287be12e 5773 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5774 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5775 rxd->opaque = (RXD_OPAQUE_RING_STD |
5776 (i << RXD_OPAQUE_INDEX_SHIFT));
5777 }
5778
1da177e4
LT		 5779 /* Now allocate fresh SKBs for each rx ring. */
5780 for (i = 0; i < tp->rx_pending; i++) {
86b21e59 5781 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
32d8c572
MC		 5782 printk(KERN_WARNING PFX
5783 "%s: Using a smaller RX standard ring, "
5784 "only %d out of %d buffers were allocated "
5785 "successfully.\n",
5786 tp->dev->name, i, tp->rx_pending);
5787 if (i == 0)
cf7a7298 5788 goto initfail;
32d8c572 5789 tp->rx_pending = i;
1da177e4 5790 break;
32d8c572 5791 }
1da177e4
LT		 5792 }
5793
cf7a7298
MC		 5794 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5795 goto done;
5796
21f581a5 5797 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5798
0f893dc6 5799 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5800 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5801 struct tg3_rx_buffer_desc *rxd;
5802
79ed5ac7 5803 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5804 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5805 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5806 RXD_FLAG_JUMBO;
5807 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5808 (i << RXD_OPAQUE_INDEX_SHIFT));
5809 }
5810
1da177e4 5811 for (i = 0; i < tp->rx_jumbo_pending; i++) {
86b21e59 5812 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
afc081f8 5813 i) < 0) {
32d8c572
MC		 5814 printk(KERN_WARNING PFX
5815 "%s: Using a smaller RX jumbo ring, "
5816 "only %d out of %d buffers were "
5817 "allocated successfully.\n",
5818 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5819 if (i == 0)
5820 goto initfail;
32d8c572 5821 tp->rx_jumbo_pending = i;
1da177e4 5822 break;
32d8c572 5823 }
1da177e4
LT		 5824 }
5825 }
cf7a7298
MC		 5826
5827done:
32d8c572 5828 return 0;
cf7a7298
MC		 5829
5830initfail:
21f581a5 5831 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5832 return -ENOMEM;
1da177e4
LT		 5833}
5834
21f581a5
MC		 5835static void tg3_rx_prodring_fini(struct tg3 *tp,
5836 struct tg3_rx_prodring_set *tpr)
1da177e4 5837{
21f581a5
MC		 5838 kfree(tpr->rx_std_buffers);
5839 tpr->rx_std_buffers = NULL;
5840 kfree(tpr->rx_jmb_buffers);
5841 tpr->rx_jmb_buffers = NULL;
5842 if (tpr->rx_std) {
1da177e4 5843 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5844 tpr->rx_std, tpr->rx_std_mapping);
5845 tpr->rx_std = NULL;
1da177e4 5846 }
21f581a5 5847 if (tpr->rx_jmb) {
1da177e4 5848 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5849 tpr->rx_jmb, tpr->rx_jmb_mapping);
5850 tpr->rx_jmb = NULL;
1da177e4 5851 }
cf7a7298
MC		 5852}
5853
21f581a5
MC		 5854static int tg3_rx_prodring_init(struct tg3 *tp,
5855 struct tg3_rx_prodring_set *tpr)
cf7a7298 5856{
2b2cdb65 5857 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
21f581a5 5858 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5859 return -ENOMEM;
5860
21f581a5
MC		 5861 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5862 &tpr->rx_std_mapping);
5863 if (!tpr->rx_std)
cf7a7298
MC		 5864 goto err_out;
5865
5866 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2b2cdb65 5867 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
21f581a5
MC		 5868 GFP_KERNEL);
5869 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5870 goto err_out;
5871
21f581a5
MC		 5872 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5873 TG3_RX_JUMBO_RING_BYTES,
5874 &tpr->rx_jmb_mapping);
5875 if (!tpr->rx_jmb)
cf7a7298
MC		 5876 goto err_out;
5877 }
5878
5879 return 0;
5880
5881err_out:
21f581a5 5882 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5883 return -ENOMEM;
5884}
5885
5886/* Free up pending packets in all rx/tx rings.
5887 *
5888 * The chip has been shut down and the driver detached from
5889 * the networking, so no interrupts or new tx packets will
5890 * end up in the driver. tp->{tx,}lock is not held and we are not
5891 * in an interrupt context and thus may sleep.
5892 */
5893static void tg3_free_rings(struct tg3 *tp)
5894{
f77a6a8e 5895 int i, j;
cf7a7298 5896
f77a6a8e
MC		 5897 for (j = 0; j < tp->irq_cnt; j++) {
5898 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5899
0c1d0e2b
MC		 5900 if (!tnapi->tx_buffers)
5901 continue;
5902
f77a6a8e
MC		 5903 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5904 struct tx_ring_info *txp;
5905 struct sk_buff *skb;
cf7a7298 5906
f77a6a8e
MC		 5907 txp = &tnapi->tx_buffers[i];
5908 skb = txp->skb;
cf7a7298 5909
f77a6a8e
MC		 5910 if (skb == NULL) {
5911 i++;
5912 continue;
5913 }
cf7a7298 5914
f77a6a8e 5915 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5916
f77a6a8e 5917 txp->skb = NULL;
cf7a7298 5918
f77a6a8e
MC		 5919 i += skb_shinfo(skb)->nr_frags + 1;
5920
5921 dev_kfree_skb_any(skb);
5922 }
cf7a7298 5923
2b2cdb65
MC		 5924 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
5925 tg3_rx_prodring_free(tp, &tp->prodring[j]);
5926 }
cf7a7298
MC		 5927}
5928
5929/* Initialize tx/rx rings for packet processing.
5930 *
5931 * The chip has been shut down and the driver detached from
5932 * the networking, so no interrupts or new tx packets will
5933 * end up in the driver. tp->{tx,}lock are held and thus
5934 * we may not sleep.
5935 */
5936static int tg3_init_rings(struct tg3 *tp)
5937{
f77a6a8e 5938 int i;
72334482 5939
cf7a7298
MC		 5940 /* Free up all the SKBs. */
5941 tg3_free_rings(tp);
5942
f77a6a8e
MC		 5943 for (i = 0; i < tp->irq_cnt; i++) {
5944 struct tg3_napi *tnapi = &tp->napi[i];
5945
5946 tnapi->last_tag = 0;
5947 tnapi->last_irq_tag = 0;
5948 tnapi->hw_status->status = 0;
5949 tnapi->hw_status->status_tag = 0;
5950 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5951
f77a6a8e
MC		 5952 tnapi->tx_prod = 0;
5953 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5954 if (tnapi->tx_ring)
5955 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5956
5957 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5958 if (tnapi->rx_rcb)
5959 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65
MC		 5960
5961 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
5962 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
5963 return -ENOMEM;
f77a6a8e 5964 }
72334482 5965
2b2cdb65 5966 return 0;
cf7a7298
MC		 5967}
5968
5969/*
5970 * Must not be invoked with interrupt sources disabled and
5971 * the hardware shutdown down.
5972 */
5973static void tg3_free_consistent(struct tg3 *tp)
5974{
f77a6a8e 5975 int i;
898a56f8 5976
f77a6a8e
MC		 5977 for (i = 0; i < tp->irq_cnt; i++) {
5978 struct tg3_napi *tnapi = &tp->napi[i];
5979
5980 if (tnapi->tx_ring) {
5981 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5982 tnapi->tx_ring, tnapi->tx_desc_mapping);
5983 tnapi->tx_ring = NULL;
5984 }
5985
5986 kfree(tnapi->tx_buffers);
5987 tnapi->tx_buffers = NULL;
5988
5989 if (tnapi->rx_rcb) {
5990 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5991 tnapi->rx_rcb,
5992 tnapi->rx_rcb_mapping);
5993 tnapi->rx_rcb = NULL;
5994 }
5995
5996 if (tnapi->hw_status) {
5997 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5998 tnapi->hw_status,
5999 tnapi->status_mapping);
6000 tnapi->hw_status = NULL;
6001 }
1da177e4 6002 }
f77a6a8e 6003
1da177e4
LT		 6004 if (tp->hw_stats) {
6005 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6006 tp->hw_stats, tp->stats_mapping);
6007 tp->hw_stats = NULL;
6008 }
f77a6a8e 6009
2b2cdb65
MC		 6010 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6011 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
1da177e4
LT		 6012}
6013
6014/*
6015 * Must not be invoked with interrupt sources disabled and
6016 * the hardware shutdown down. Can sleep.
6017 */
6018static int tg3_alloc_consistent(struct tg3 *tp)
6019{
f77a6a8e 6020 int i;
898a56f8 6021
2b2cdb65
MC		 6022 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6023 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6024 goto err_out;
6025 }
1da177e4 6026
f77a6a8e
MC		 6027 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6028 sizeof(struct tg3_hw_stats),
6029 &tp->stats_mapping);
6030 if (!tp->hw_stats)
1da177e4
LT		 6031 goto err_out;
6032
f77a6a8e 6033 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 6034
f77a6a8e
MC		 6035 for (i = 0; i < tp->irq_cnt; i++) {
6036 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 6037 struct tg3_hw_status *sblk;
1da177e4 6038
f77a6a8e
MC		 6039 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6040 TG3_HW_STATUS_SIZE,
6041 &tnapi->status_mapping);
6042 if (!tnapi->hw_status)
6043 goto err_out;
898a56f8 6044
f77a6a8e 6045 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 6046 sblk = tnapi->hw_status;
6047
6048 /*
6049 * When RSS is enabled, the status block format changes
6050 * slightly. The "rx_jumbo_consumer", "reserved",
6051 * and "rx_mini_consumer" members get mapped to the
6052 * other three rx return ring producer indexes.
6053 */
6054 switch (i) {
6055 default:
6056 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6057 break;
6058 case 2:
6059 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6060 break;
6061 case 3:
6062 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6063 break;
6064 case 4:
6065 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6066 break;
6067 }
72334482 6068
0c1d0e2b
MC		 6069 /*
6070 * If multivector RSS is enabled, vector 0 does not handle
6071 * rx or tx interrupts. Don't allocate any resources for it.
6072 */
6073 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6074 continue;
6075
f77a6a8e
MC		 6076 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6077 TG3_RX_RCB_RING_BYTES(tp),
6078 &tnapi->rx_rcb_mapping);
6079 if (!tnapi->rx_rcb)
6080 goto err_out;
72334482 6081
f77a6a8e 6082 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 6083
f77a6a8e
MC		 6084 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6085 TG3_TX_RING_SIZE, GFP_KERNEL);
6086 if (!tnapi->tx_buffers)
6087 goto err_out;
6088
6089 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6090 TG3_TX_RING_BYTES,
6091 &tnapi->tx_desc_mapping);
6092 if (!tnapi->tx_ring)
6093 goto err_out;
6094 }
1da177e4
LT		 6095
6096 return 0;
6097
6098err_out:
6099 tg3_free_consistent(tp);
6100 return -ENOMEM;
6101}
6102
6103#define MAX_WAIT_CNT 1000
6104
6105/* To stop a block, clear the enable bit and poll till it
6106 * clears. tp->lock is held.
6107 */
b3b7d6be 6108static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6109{
6110 unsigned int i;
6111 u32 val;
6112
6113 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6114 switch (ofs) {
6115 case RCVLSC_MODE:
6116 case DMAC_MODE:
6117 case MBFREE_MODE:
6118 case BUFMGR_MODE:
6119 case MEMARB_MODE:
6120 /* We can't enable/disable these bits of the
6121 * 5705/5750, just say success.
6122 */
6123 return 0;
6124
6125 default:
6126 break;
855e1111 6127 }
1da177e4
LT		 6128 }
6129
6130 val = tr32(ofs);
6131 val &= ~enable_bit;
6132 tw32_f(ofs, val);
6133
6134 for (i = 0; i < MAX_WAIT_CNT; i++) {
6135 udelay(100);
6136 val = tr32(ofs);
6137 if ((val & enable_bit) == 0)
6138 break;
6139 }
6140
b3b7d6be 6141 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6142 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6143 "ofs=%lx enable_bit=%x\n",
6144 ofs, enable_bit);
6145 return -ENODEV;
6146 }
6147
6148 return 0;
6149}
6150
6151/* tp->lock is held. */
b3b7d6be 6152static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6153{
6154 int i, err;
6155
6156 tg3_disable_ints(tp);
6157
6158 tp->rx_mode &= ~RX_MODE_ENABLE;
6159 tw32_f(MAC_RX_MODE, tp->rx_mode);
6160 udelay(10);
6161
b3b7d6be
DM		 6162 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6163 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6164 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6165 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6166 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6167 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6168
6169 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6170 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6171 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6172 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6173 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6174 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6175 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6176
6177 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6178 tw32_f(MAC_MODE, tp->mac_mode);
6179 udelay(40);
6180
6181 tp->tx_mode &= ~TX_MODE_ENABLE;
6182 tw32_f(MAC_TX_MODE, tp->tx_mode);
6183
6184 for (i = 0; i < MAX_WAIT_CNT; i++) {
6185 udelay(100);
6186 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6187 break;
6188 }
6189 if (i >= MAX_WAIT_CNT) {
6190 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6191 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6192 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6193 err |= -ENODEV;
1da177e4
LT		 6194 }
6195
e6de8ad1 6196 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6197 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6198 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6199
6200 tw32(FTQ_RESET, 0xffffffff);
6201 tw32(FTQ_RESET, 0x00000000);
6202
b3b7d6be
DM		 6203 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6204 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6205
f77a6a8e
MC		 6206 for (i = 0; i < tp->irq_cnt; i++) {
6207 struct tg3_napi *tnapi = &tp->napi[i];
6208 if (tnapi->hw_status)
6209 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6210 }
1da177e4
LT		 6211 if (tp->hw_stats)
6212 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6213
1da177e4
LT		 6214 return err;
6215}
6216
0d3031d9
MC		 6217static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6218{
6219 int i;
6220 u32 apedata;
6221
6222 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6223 if (apedata != APE_SEG_SIG_MAGIC)
6224 return;
6225
6226 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6227 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6228 return;
6229
6230 /* Wait for up to 1 millisecond for APE to service previous event. */
6231 for (i = 0; i < 10; i++) {
6232 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6233 return;
6234
6235 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6236
6237 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6238 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6239 event | APE_EVENT_STATUS_EVENT_PENDING);
6240
6241 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6242
6243 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6244 break;
6245
6246 udelay(100);
6247 }
6248
6249 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6250 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6251}
6252
6253static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6254{
6255 u32 event;
6256 u32 apedata;
6257
6258 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6259 return;
6260
6261 switch (kind) {
6262 case RESET_KIND_INIT:
6263 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6264 APE_HOST_SEG_SIG_MAGIC);
6265 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6266 APE_HOST_SEG_LEN_MAGIC);
6267 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6268 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6269 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6270 APE_HOST_DRIVER_ID_MAGIC);
6271 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6272 APE_HOST_BEHAV_NO_PHYLOCK);
6273
6274 event = APE_EVENT_STATUS_STATE_START;
6275 break;
6276 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6277 /* With the interface we are currently using,
6278 * APE does not track driver state. Wiping
6279 * out the HOST SEGMENT SIGNATURE forces
6280 * the APE to assume OS absent status.
6281 */
6282 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6283
0d3031d9
MC		 6284 event = APE_EVENT_STATUS_STATE_UNLOAD;
6285 break;
6286 case RESET_KIND_SUSPEND:
6287 event = APE_EVENT_STATUS_STATE_SUSPEND;
6288 break;
6289 default:
6290 return;
6291 }
6292
6293 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6294
6295 tg3_ape_send_event(tp, event);
6296}
6297
1da177e4
LT		 6298/* tp->lock is held. */
6299static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6300{
f49639e6
DM		 6301 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6302 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6303
6304 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6305 switch (kind) {
6306 case RESET_KIND_INIT:
6307 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6308 DRV_STATE_START);
6309 break;
6310
6311 case RESET_KIND_SHUTDOWN:
6312 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6313 DRV_STATE_UNLOAD);
6314 break;
6315
6316 case RESET_KIND_SUSPEND:
6317 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6318 DRV_STATE_SUSPEND);
6319 break;
6320
6321 default:
6322 break;
855e1111 6323 }
1da177e4 6324 }
0d3031d9
MC		 6325
6326 if (kind == RESET_KIND_INIT ||
6327 kind == RESET_KIND_SUSPEND)
6328 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6329}
6330
6331/* tp->lock is held. */
6332static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6333{
6334 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6335 switch (kind) {
6336 case RESET_KIND_INIT:
6337 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6338 DRV_STATE_START_DONE);
6339 break;
6340
6341 case RESET_KIND_SHUTDOWN:
6342 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6343 DRV_STATE_UNLOAD_DONE);
6344 break;
6345
6346 default:
6347 break;
855e1111 6348 }
1da177e4 6349 }
0d3031d9
MC		 6350
6351 if (kind == RESET_KIND_SHUTDOWN)
6352 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6353}
6354
6355/* tp->lock is held. */
6356static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6357{
6358 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6359 switch (kind) {
6360 case RESET_KIND_INIT:
6361 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6362 DRV_STATE_START);
6363 break;
6364
6365 case RESET_KIND_SHUTDOWN:
6366 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6367 DRV_STATE_UNLOAD);
6368 break;
6369
6370 case RESET_KIND_SUSPEND:
6371 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6372 DRV_STATE_SUSPEND);
6373 break;
6374
6375 default:
6376 break;
855e1111 6377 }
1da177e4
LT		 6378 }
6379}
6380
7a6f4369
MC		 6381static int tg3_poll_fw(struct tg3 *tp)
6382{
6383 int i;
6384 u32 val;
6385
b5d3772c 6386 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6387 /* Wait up to 20ms for init done. */
6388 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6389 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6390 return 0;
0ccead18 6391 udelay(100);
b5d3772c
MC		 6392 }
6393 return -ENODEV;
6394 }
6395
7a6f4369
MC		 6396 /* Wait for firmware initialization to complete. */
6397 for (i = 0; i < 100000; i++) {
6398 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6399 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6400 break;
6401 udelay(10);
6402 }
6403
6404 /* Chip might not be fitted with firmware. Some Sun onboard
6405 * parts are configured like that. So don't signal the timeout
6406 * of the above loop as an error, but do report the lack of
6407 * running firmware once.
6408 */
6409 if (i >= 100000 &&
6410 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6411 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6412
6413 printk(KERN_INFO PFX "%s: No firmware running.\n",
6414 tp->dev->name);
6415 }
6416
6417 return 0;
6418}
6419
ee6a99b5
MC		 6420/* Save PCI command register before chip reset */
6421static void tg3_save_pci_state(struct tg3 *tp)
6422{
8a6eac90 6423 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6424}
6425
6426/* Restore PCI state after chip reset */
6427static void tg3_restore_pci_state(struct tg3 *tp)
6428{
6429 u32 val;
6430
6431 /* Re-enable indirect register accesses. */
6432 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6433 tp->misc_host_ctrl);
6434
6435 /* Set MAX PCI retry to zero. */
6436 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6437 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6438 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6439 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6440 /* Allow reads and writes to the APE register and memory space. */
6441 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6442 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6443 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6444 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6445
8a6eac90 6446 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6447
fcb389df
MC		 6448 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6449 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6450 pcie_set_readrq(tp->pdev, 4096);
6451 else {
6452 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6453 tp->pci_cacheline_sz);
6454 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6455 tp->pci_lat_timer);
6456 }
114342f2 6457 }
5f5c51e3 6458
ee6a99b5 6459 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6460 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6461 u16 pcix_cmd;
6462
6463 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6464 &pcix_cmd);
6465 pcix_cmd &= ~PCI_X_CMD_ERO;
6466 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6467 pcix_cmd);
6468 }
ee6a99b5
MC		 6469
6470 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6471
6472 /* Chip reset on 5780 will reset MSI enable bit,
6473 * so need to restore it.
6474 */
6475 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6476 u16 ctrl;
6477
6478 pci_read_config_word(tp->pdev,
6479 tp->msi_cap + PCI_MSI_FLAGS,
6480 &ctrl);
6481 pci_write_config_word(tp->pdev,
6482 tp->msi_cap + PCI_MSI_FLAGS,
6483 ctrl | PCI_MSI_FLAGS_ENABLE);
6484 val = tr32(MSGINT_MODE);
6485 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6486 }
6487 }
6488}
6489
1da177e4
LT		 6490static void tg3_stop_fw(struct tg3 *);
6491
6492/* tp->lock is held. */
6493static int tg3_chip_reset(struct tg3 *tp)
6494{
6495 u32 val;
1ee582d8 6496 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6497 int i, err;
1da177e4 6498
f49639e6
DM		 6499 tg3_nvram_lock(tp);
6500
77b483f1
MC		 6501 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6502
f49639e6
DM		 6503 /* No matching tg3_nvram_unlock() after this because
6504 * chip reset below will undo the nvram lock.
6505 */
6506 tp->nvram_lock_cnt = 0;
1da177e4 6507
ee6a99b5
MC		 6508 /* GRC_MISC_CFG core clock reset will clear the memory
6509 * enable bit in PCI register 4 and the MSI enable bit
6510 * on some chips, so we save relevant registers here.
6511 */
6512 tg3_save_pci_state(tp);
6513
d9ab5ad1 6514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6515 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6516 tw32(GRC_FASTBOOT_PC, 0);
6517
1da177e4
LT		 6518 /*
6519 * We must avoid the readl() that normally takes place.
6520 * It locks machines, causes machine checks, and other
6521 * fun things. So, temporarily disable the 5701
6522 * hardware workaround, while we do the reset.
6523 */
1ee582d8
MC		 6524 write_op = tp->write32;
6525 if (write_op == tg3_write_flush_reg32)
6526 tp->write32 = tg3_write32;
1da177e4 6527
d18edcb2
MC		 6528 /* Prevent the irq handler from reading or writing PCI registers
6529 * during chip reset when the memory enable bit in the PCI command
6530 * register may be cleared. The chip does not generate interrupt
6531 * at this time, but the irq handler may still be called due to irq
6532 * sharing or irqpoll.
6533 */
6534 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6535 for (i = 0; i < tp->irq_cnt; i++) {
6536 struct tg3_napi *tnapi = &tp->napi[i];
6537 if (tnapi->hw_status) {
6538 tnapi->hw_status->status = 0;
6539 tnapi->hw_status->status_tag = 0;
6540 }
6541 tnapi->last_tag = 0;
6542 tnapi->last_irq_tag = 0;
b8fa2f3a 6543 }
d18edcb2 6544 smp_mb();
4f125f42
MC		 6545
6546 for (i = 0; i < tp->irq_cnt; i++)
6547 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6548
255ca311
MC		 6549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6550 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6551 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6552 }
6553
1da177e4
LT		 6554 /* do the reset */
6555 val = GRC_MISC_CFG_CORECLK_RESET;
6556
6557 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6558 if (tr32(0x7e2c) == 0x60) {
6559 tw32(0x7e2c, 0x20);
6560 }
6561 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6562 tw32(GRC_MISC_CFG, (1 << 29));
6563 val |= (1 << 29);
6564 }
6565 }
6566
b5d3772c
MC		 6567 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6568 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6569 tw32(GRC_VCPU_EXT_CTRL,
6570 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6571 }
6572
1da177e4
LT		 6573 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6574 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6575 tw32(GRC_MISC_CFG, val);
6576
1ee582d8
MC		 6577 /* restore 5701 hardware bug workaround write method */
6578 tp->write32 = write_op;
1da177e4
LT		 6579
6580 /* Unfortunately, we have to delay before the PCI read back.
6581 * Some 575X chips even will not respond to a PCI cfg access
6582 * when the reset command is given to the chip.
6583 *
6584 * How do these hardware designers expect things to work
6585 * properly if the PCI write is posted for a long period
6586 * of time? It is always necessary to have some method by
6587 * which a register read back can occur to push the write
6588 * out which does the reset.
6589 *
6590 * For most tg3 variants the trick below was working.
6591 * Ho hum...
6592 */
6593 udelay(120);
6594
6595 /* Flush PCI posted writes. The normal MMIO registers
6596 * are inaccessible at this time so this is the only
6597 * way to make this reliably (actually, this is no longer
6598 * the case, see above). I tried to use indirect
6599 * register read/write but this upset some 5701 variants.
6600 */
6601 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6602
6603 udelay(120);
6604
5e7dfd0f 6605 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6606 u16 val16;
6607
1da177e4
LT		 6608 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6609 int i;
6610 u32 cfg_val;
6611
6612 /* Wait for link training to complete. */
6613 for (i = 0; i < 5000; i++)
6614 udelay(100);
6615
6616 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6617 pci_write_config_dword(tp->pdev, 0xc4,
6618 cfg_val | (1 << 15));
6619 }
5e7dfd0f 6620
e7126997
MC		 6621 /* Clear the "no snoop" and "relaxed ordering" bits. */
6622 pci_read_config_word(tp->pdev,
6623 tp->pcie_cap + PCI_EXP_DEVCTL,
6624 &val16);
6625 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6626 PCI_EXP_DEVCTL_NOSNOOP_EN);
6627 /*
6628 * Older PCIe devices only support the 128 byte
6629 * MPS setting. Enforce the restriction.
5e7dfd0f 6630 */
e7126997
MC		 6631 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6632 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6633 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6634 pci_write_config_word(tp->pdev,
6635 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6636 val16);
5e7dfd0f
MC		 6637
6638 pcie_set_readrq(tp->pdev, 4096);
6639
6640 /* Clear error status */
6641 pci_write_config_word(tp->pdev,
6642 tp->pcie_cap + PCI_EXP_DEVSTA,
6643 PCI_EXP_DEVSTA_CED |
6644 PCI_EXP_DEVSTA_NFED |
6645 PCI_EXP_DEVSTA_FED |
6646 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6647 }
6648
ee6a99b5 6649 tg3_restore_pci_state(tp);
1da177e4 6650
d18edcb2
MC		 6651 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6652
ee6a99b5
MC		 6653 val = 0;
6654 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6655 val = tr32(MEMARB_MODE);
ee6a99b5 6656 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6657
6658 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6659 tg3_stop_fw(tp);
6660 tw32(0x5000, 0x400);
6661 }
6662
6663 tw32(GRC_MODE, tp->grc_mode);
6664
6665 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6666 val = tr32(0xc4);
1da177e4
LT		 6667
6668 tw32(0xc4, val | (1 << 15));
6669 }
6670
6671 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6672 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6673 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6674 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6675 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6676 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6677 }
6678
6679 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6680 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6681 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6682 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6683 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6684 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6685 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6686 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6687 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6688 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6689 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6690 } else
6691 tw32_f(MAC_MODE, 0);
6692 udelay(40);
6693
77b483f1
MC		 6694 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6695
7a6f4369
MC		 6696 err = tg3_poll_fw(tp);
6697 if (err)
6698 return err;
1da177e4 6699
0a9140cf
MC		 6700 tg3_mdio_start(tp);
6701
52cdf852
MC		 6702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6703 u8 phy_addr;
6704
6705 phy_addr = tp->phy_addr;
6706 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6707
6708 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6709 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6710 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6711 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6712 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6713 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6714 udelay(10);
6715
6716 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6717 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6718 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6719 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6720 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6721 udelay(10);
6722
6723 tp->phy_addr = phy_addr;
6724 }
6725
1da177e4 6726 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6727 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6728 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6729 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6730 val = tr32(0x7c00);
1da177e4
LT		 6731
6732 tw32(0x7c00, val | (1 << 25));
6733 }
6734
6735 /* Reprobe ASF enable state. */
6736 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6737 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6738 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6739 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6740 u32 nic_cfg;
6741
6742 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6743 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6744 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6745 tp->last_event_jiffies = jiffies;
cbf46853 6746 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6747 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6748 }
6749 }
6750
6751 return 0;
6752}
6753
6754/* tp->lock is held. */
6755static void tg3_stop_fw(struct tg3 *tp)
6756{
0d3031d9
MC		 6757 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6758 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6759 /* Wait for RX cpu to ACK the previous event. */
6760 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6761
6762 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6763
6764 tg3_generate_fw_event(tp);
1da177e4 6765
7c5026aa
MC		 6766 /* Wait for RX cpu to ACK this event. */
6767 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6768 }
6769}
6770
6771/* tp->lock is held. */
944d980e 6772static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6773{
6774 int err;
6775
6776 tg3_stop_fw(tp);
6777
944d980e 6778 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6779
b3b7d6be 6780 tg3_abort_hw(tp, silent);
1da177e4
LT		 6781 err = tg3_chip_reset(tp);
6782
daba2a63
MC		 6783 __tg3_set_mac_addr(tp, 0);
6784
944d980e
MC		 6785 tg3_write_sig_legacy(tp, kind);
6786 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6787
6788 if (err)
6789 return err;
6790
6791 return 0;
6792}
6793
1da177e4
LT		 6794#define RX_CPU_SCRATCH_BASE 0x30000
6795#define RX_CPU_SCRATCH_SIZE 0x04000
6796#define TX_CPU_SCRATCH_BASE 0x34000
6797#define TX_CPU_SCRATCH_SIZE 0x04000
6798
6799/* tp->lock is held. */
6800static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6801{
6802 int i;
6803
5d9428de
ES		 6804 BUG_ON(offset == TX_CPU_BASE &&
6805 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6806
b5d3772c
MC		 6807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6808 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6809
6810 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6811 return 0;
6812 }
1da177e4
LT		 6813 if (offset == RX_CPU_BASE) {
6814 for (i = 0; i < 10000; i++) {
6815 tw32(offset + CPU_STATE, 0xffffffff);
6816 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6817 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6818 break;
6819 }
6820
6821 tw32(offset + CPU_STATE, 0xffffffff);
6822 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6823 udelay(10);
6824 } else {
6825 for (i = 0; i < 10000; i++) {
6826 tw32(offset + CPU_STATE, 0xffffffff);
6827 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6828 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6829 break;
6830 }
6831 }
6832
6833 if (i >= 10000) {
6834 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6835 "and %s CPU\n",
6836 tp->dev->name,
6837 (offset == RX_CPU_BASE ? "RX" : "TX"));
6838 return -ENODEV;
6839 }
ec41c7df
MC		 6840
6841 /* Clear firmware's nvram arbitration. */
6842 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6843 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6844 return 0;
6845}
6846
6847struct fw_info {
077f849d
JSR		 6848 unsigned int fw_base;
6849 unsigned int fw_len;
6850 const __be32 *fw_data;
1da177e4
LT		 6851};
6852
6853/* tp->lock is held. */
6854static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6855 int cpu_scratch_size, struct fw_info *info)
6856{
ec41c7df 6857 int err, lock_err, i;
1da177e4
LT		 6858 void (*write_op)(struct tg3 *, u32, u32);
6859
6860 if (cpu_base == TX_CPU_BASE &&
6861 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6862 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6863 "TX cpu firmware on %s which is 5705.\n",
6864 tp->dev->name);
6865 return -EINVAL;
6866 }
6867
6868 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6869 write_op = tg3_write_mem;
6870 else
6871 write_op = tg3_write_indirect_reg32;
6872
1b628151
MC		 6873 /* It is possible that bootcode is still loading at this point.
6874 * Get the nvram lock first before halting the cpu.
6875 */
ec41c7df 6876 lock_err = tg3_nvram_lock(tp);
1da177e4 6877 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6878 if (!lock_err)
6879 tg3_nvram_unlock(tp);
1da177e4
LT		 6880 if (err)
6881 goto out;
6882
6883 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6884 write_op(tp, cpu_scratch_base + i, 0);
6885 tw32(cpu_base + CPU_STATE, 0xffffffff);
6886 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6887 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6888 write_op(tp, (cpu_scratch_base +
077f849d 6889 (info->fw_base & 0xffff) +
1da177e4 6890 (i * sizeof(u32))),
077f849d 6891 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6892
6893 err = 0;
6894
6895out:
1da177e4
LT		 6896 return err;
6897}
6898
6899/* tp->lock is held. */
6900static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6901{
6902 struct fw_info info;
077f849d 6903 const __be32 *fw_data;
1da177e4
LT		 6904 int err, i;
6905
077f849d
JSR		 6906 fw_data = (void *)tp->fw->data;
6907
6908 /* Firmware blob starts with version numbers, followed by
6909 start address and length. We are setting complete length.
6910 length = end_address_of_bss - start_address_of_text.
6911 Remainder is the blob to be loaded contiguously
6912 from start address. */
6913
6914 info.fw_base = be32_to_cpu(fw_data[1]);
6915 info.fw_len = tp->fw->size - 12;
6916 info.fw_data = &fw_data[3];
1da177e4
LT		 6917
6918 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6919 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6920 &info);
6921 if (err)
6922 return err;
6923
6924 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6925 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6926 &info);
6927 if (err)
6928 return err;
6929
6930 /* Now startup only the RX cpu. */
6931 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6932 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6933
6934 for (i = 0; i < 5; i++) {
077f849d 6935 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6936 break;
6937 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6938 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6939 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6940 udelay(1000);
6941 }
6942 if (i >= 5) {
6943 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6944 "to set RX CPU PC, is %08x should be %08x\n",
6945 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6946 info.fw_base);
1da177e4
LT		 6947 return -ENODEV;
6948 }
6949 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6950 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6951
6952 return 0;
6953}
6954
1da177e4 6955/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6956
6957/* tp->lock is held. */
6958static int tg3_load_tso_firmware(struct tg3 *tp)
6959{
6960 struct fw_info info;
077f849d 6961 const __be32 *fw_data;
1da177e4
LT		 6962 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6963 int err, i;
6964
6965 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6966 return 0;
6967
077f849d
JSR		 6968 fw_data = (void *)tp->fw->data;
6969
6970 /* Firmware blob starts with version numbers, followed by
6971 start address and length. We are setting complete length.
6972 length = end_address_of_bss - start_address_of_text.
6973 Remainder is the blob to be loaded contiguously
6974 from start address. */
6975
6976 info.fw_base = be32_to_cpu(fw_data[1]);
6977 cpu_scratch_size = tp->fw_len;
6978 info.fw_len = tp->fw->size - 12;
6979 info.fw_data = &fw_data[3];
6980
1da177e4 6981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6982 cpu_base = RX_CPU_BASE;
6983 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6984 } else {
1da177e4
LT		 6985 cpu_base = TX_CPU_BASE;
6986 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6987 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6988 }
6989
6990 err = tg3_load_firmware_cpu(tp, cpu_base,
6991 cpu_scratch_base, cpu_scratch_size,
6992 &info);
6993 if (err)
6994 return err;
6995
6996 /* Now startup the cpu. */
6997 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6998 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6999
7000 for (i = 0; i < 5; i++) {
077f849d 7001 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 7002 break;
7003 tw32(cpu_base + CPU_STATE, 0xffffffff);
7004 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 7005 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 7006 udelay(1000);
7007 }
7008 if (i >= 5) {
7009 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7010 "to set CPU PC, is %08x should be %08x\n",
7011 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 7012 info.fw_base);
1da177e4
LT		 7013 return -ENODEV;
7014 }
7015 tw32(cpu_base + CPU_STATE, 0xffffffff);
7016 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7017 return 0;
7018}
7019
1da177e4 7020
1da177e4
LT		 7021static int tg3_set_mac_addr(struct net_device *dev, void *p)
7022{
7023 struct tg3 *tp = netdev_priv(dev);
7024 struct sockaddr *addr = p;
986e0aeb 7025 int err = 0, skip_mac_1 = 0;
1da177e4 7026
f9804ddb
MC		 7027 if (!is_valid_ether_addr(addr->sa_data))
7028 return -EINVAL;
7029
1da177e4
LT		 7030 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7031
e75f7c90
MC		 7032 if (!netif_running(dev))
7033 return 0;
7034
58712ef9 7035 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 7036 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 7037
986e0aeb
MC		 7038 addr0_high = tr32(MAC_ADDR_0_HIGH);
7039 addr0_low = tr32(MAC_ADDR_0_LOW);
7040 addr1_high = tr32(MAC_ADDR_1_HIGH);
7041 addr1_low = tr32(MAC_ADDR_1_LOW);
7042
7043 /* Skip MAC addr 1 if ASF is using it. */
7044 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7045 !(addr1_high == 0 && addr1_low == 0))
7046 skip_mac_1 = 1;
58712ef9 7047 }
986e0aeb
MC		 7048 spin_lock_bh(&tp->lock);
7049 __tg3_set_mac_addr(tp, skip_mac_1);
7050 spin_unlock_bh(&tp->lock);
1da177e4 7051
b9ec6c1b 7052 return err;
1da177e4
LT		 7053}
7054
7055/* tp->lock is held. */
7056static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7057 dma_addr_t mapping, u32 maxlen_flags,
7058 u32 nic_addr)
7059{
7060 tg3_write_mem(tp,
7061 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7062 ((u64) mapping >> 32));
7063 tg3_write_mem(tp,
7064 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7065 ((u64) mapping & 0xffffffff));
7066 tg3_write_mem(tp,
7067 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7068 maxlen_flags);
7069
7070 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7071 tg3_write_mem(tp,
7072 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7073 nic_addr);
7074}
7075
7076static void __tg3_set_rx_mode(struct net_device *);
d244c892 7077static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7078{
b6080e12
MC		 7079 int i;
7080
7081 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7082 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7083 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7084 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7085
7086 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7087 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7088 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7089 } else {
7090 tw32(HOSTCC_TXCOL_TICKS, 0);
7091 tw32(HOSTCC_TXMAX_FRAMES, 0);
7092 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7093
7094 tw32(HOSTCC_RXCOL_TICKS, 0);
7095 tw32(HOSTCC_RXMAX_FRAMES, 0);
7096 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7097 }
b6080e12 7098
15f9850d
DM		 7099 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7100 u32 val = ec->stats_block_coalesce_usecs;
7101
b6080e12
MC		 7102 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7103 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7104
15f9850d
DM		 7105 if (!netif_carrier_ok(tp->dev))
7106 val = 0;
7107
7108 tw32(HOSTCC_STAT_COAL_TICKS, val);
7109 }
b6080e12
MC		 7110
7111 for (i = 0; i < tp->irq_cnt - 1; i++) {
7112 u32 reg;
7113
7114 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7115 tw32(reg, ec->rx_coalesce_usecs);
7116 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7117 tw32(reg, ec->tx_coalesce_usecs);
7118 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7119 tw32(reg, ec->rx_max_coalesced_frames);
7120 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7121 tw32(reg, ec->tx_max_coalesced_frames);
7122 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7123 tw32(reg, ec->rx_max_coalesced_frames_irq);
7124 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7125 tw32(reg, ec->tx_max_coalesced_frames_irq);
7126 }
7127
7128 for (; i < tp->irq_max - 1; i++) {
7129 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7130 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7131 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7132 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7133 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7134 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7135 }
15f9850d 7136}
1da177e4 7137
2d31ecaf
MC		 7138/* tp->lock is held. */
7139static void tg3_rings_reset(struct tg3 *tp)
7140{
7141 int i;
f77a6a8e 7142 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7143 struct tg3_napi *tnapi = &tp->napi[0];
7144
7145 /* Disable all transmit rings but the first. */
7146 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7147 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7148 else
7149 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7150
7151 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7152 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7153 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7154 BDINFO_FLAGS_DISABLED);
7155
7156
7157 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7159 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7160 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7161 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7162 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7163 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7164 else
7165 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7166
7167 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7168 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7169 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7170 BDINFO_FLAGS_DISABLED);
7171
7172 /* Disable interrupts */
7173 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7174
7175 /* Zero mailbox registers. */
f77a6a8e
MC		 7176 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7177 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7178 tp->napi[i].tx_prod = 0;
7179 tp->napi[i].tx_cons = 0;
7180 tw32_mailbox(tp->napi[i].prodmbox, 0);
7181 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7182 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7183 }
7184 } else {
7185 tp->napi[0].tx_prod = 0;
7186 tp->napi[0].tx_cons = 0;
7187 tw32_mailbox(tp->napi[0].prodmbox, 0);
7188 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7189 }
2d31ecaf
MC		 7190
7191 /* Make sure the NIC-based send BD rings are disabled. */
7192 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7193 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7194 for (i = 0; i < 16; i++)
7195 tw32_tx_mbox(mbox + i * 8, 0);
7196 }
7197
7198 txrcb = NIC_SRAM_SEND_RCB;
7199 rxrcb = NIC_SRAM_RCV_RET_RCB;
7200
7201 /* Clear status block in ram. */
7202 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7203
7204 /* Set status block DMA address */
7205 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7206 ((u64) tnapi->status_mapping >> 32));
7207 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7208 ((u64) tnapi->status_mapping & 0xffffffff));
7209
f77a6a8e
MC		 7210 if (tnapi->tx_ring) {
7211 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7212 (TG3_TX_RING_SIZE <<
7213 BDINFO_FLAGS_MAXLEN_SHIFT),
7214 NIC_SRAM_TX_BUFFER_DESC);
7215 txrcb += TG3_BDINFO_SIZE;
7216 }
7217
7218 if (tnapi->rx_rcb) {
7219 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7220 (TG3_RX_RCB_RING_SIZE(tp) <<
7221 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7222 rxrcb += TG3_BDINFO_SIZE;
7223 }
7224
7225 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7226
f77a6a8e
MC		 7227 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7228 u64 mapping = (u64)tnapi->status_mapping;
7229 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7230 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7231
7232 /* Clear status block in ram. */
7233 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7234
7235 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7236 (TG3_TX_RING_SIZE <<
7237 BDINFO_FLAGS_MAXLEN_SHIFT),
7238 NIC_SRAM_TX_BUFFER_DESC);
7239
7240 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7241 (TG3_RX_RCB_RING_SIZE(tp) <<
7242 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7243
7244 stblk += 8;
7245 txrcb += TG3_BDINFO_SIZE;
7246 rxrcb += TG3_BDINFO_SIZE;
7247 }
2d31ecaf
MC		 7248}
7249
1da177e4 7250/* tp->lock is held. */
8e7a22e3 7251static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7252{
7253 u32 val, rdmac_mode;
7254 int i, err, limit;
21f581a5 7255 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7256
7257 tg3_disable_ints(tp);
7258
7259 tg3_stop_fw(tp);
7260
7261 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7262
7263 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7264 tg3_abort_hw(tp, 1);
1da177e4
LT		 7265 }
7266
dd477003
MC		 7267 if (reset_phy &&
7268 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7269 tg3_phy_reset(tp);
7270
1da177e4
LT		 7271 err = tg3_chip_reset(tp);
7272 if (err)
7273 return err;
7274
7275 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7276
bcb37f6c 7277 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7278 val = tr32(TG3_CPMU_CTRL);
7279 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7280 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7281
7282 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7283 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7284 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7285 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7286
7287 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7288 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7289 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7290 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7291
7292 val = tr32(TG3_CPMU_HST_ACC);
7293 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7294 val |= CPMU_HST_ACC_MACCLK_6_25;
7295 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7296 }
7297
33466d93
MC		 7298 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7299 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7300 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7301 PCIE_PWR_MGMT_L1_THRESH_4MS;
7302 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7303
7304 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7305 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7306
7307 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7308
f40386c8
MC		 7309 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7310 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7311 }
7312
1da177e4
LT		 7313 /* This works around an issue with Athlon chipsets on
7314 * B3 tigon3 silicon. This bit has no effect on any
7315 * other revision. But do not set this on PCI Express
795d01c5 7316 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7317 */
795d01c5
MC		 7318 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7319 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7320 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7321 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7322 }
1da177e4
LT		 7323
7324 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7325 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7326 val = tr32(TG3PCI_PCISTATE);
7327 val |= PCISTATE_RETRY_SAME_DMA;
7328 tw32(TG3PCI_PCISTATE, val);
7329 }
7330
0d3031d9
MC		 7331 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7332 /* Allow reads and writes to the
7333 * APE register and memory space.
7334 */
7335 val = tr32(TG3PCI_PCISTATE);
7336 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7337 PCISTATE_ALLOW_APE_SHMEM_WR;
7338 tw32(TG3PCI_PCISTATE, val);
7339 }
7340
1da177e4
LT		 7341 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7342 /* Enable some hw fixes. */
7343 val = tr32(TG3PCI_MSI_DATA);
7344 val |= (1 << 26) | (1 << 28) | (1 << 29);
7345 tw32(TG3PCI_MSI_DATA, val);
7346 }
7347
7348 /* Descriptor ring init may make accesses to the
7349 * NIC SRAM area to setup the TX descriptors, so we
7350 * can only do this after the hardware has been
7351 * successfully reset.
7352 */
32d8c572
MC		 7353 err = tg3_init_rings(tp);
7354 if (err)
7355 return err;
1da177e4 7356
cbf9ca6c
MC		 7357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7358 val = tr32(TG3PCI_DMA_RW_CTRL) &
7359 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7360 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7361 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7362 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
d30cdd28
MC		 7363 /* This value is determined during the probe time DMA
7364 * engine test, tg3_test_dma.
7365 */
7366 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7367 }
1da177e4
LT		 7368
7369 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7370 GRC_MODE_4X_NIC_SEND_RINGS |
7371 GRC_MODE_NO_TX_PHDR_CSUM |
7372 GRC_MODE_NO_RX_PHDR_CSUM);
7373 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7374
7375 /* Pseudo-header checksum is done by hardware logic and not
7376 * the offload processers, so make the chip do the pseudo-
7377 * header checksums on receive. For transmit it is more
7378 * convenient to do the pseudo-header checksum in software
7379 * as Linux does that on transmit for us in all cases.
7380 */
7381 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7382
7383 tw32(GRC_MODE,
7384 tp->grc_mode |
7385 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7386
7387 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7388 val = tr32(GRC_MISC_CFG);
7389 val &= ~0xff;
7390 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7391 tw32(GRC_MISC_CFG, val);
7392
7393 /* Initialize MBUF/DESC pool. */
cbf46853 7394 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7395 /* Do nothing. */
7396 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7397 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7398 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7399 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7400 else
7401 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7402 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7403 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7404 }
1da177e4
LT		 7405 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7406 int fw_len;
7407
077f849d 7408 fw_len = tp->fw_len;
1da177e4
LT		 7409 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7410 tw32(BUFMGR_MB_POOL_ADDR,
7411 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7412 tw32(BUFMGR_MB_POOL_SIZE,
7413 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7414 }
1da177e4 7415
0f893dc6 7416 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7417 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7418 tp->bufmgr_config.mbuf_read_dma_low_water);
7419 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7420 tp->bufmgr_config.mbuf_mac_rx_low_water);
7421 tw32(BUFMGR_MB_HIGH_WATER,
7422 tp->bufmgr_config.mbuf_high_water);
7423 } else {
7424 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7425 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7426 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7427 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7428 tw32(BUFMGR_MB_HIGH_WATER,
7429 tp->bufmgr_config.mbuf_high_water_jumbo);
7430 }
7431 tw32(BUFMGR_DMA_LOW_WATER,
7432 tp->bufmgr_config.dma_low_water);
7433 tw32(BUFMGR_DMA_HIGH_WATER,
7434 tp->bufmgr_config.dma_high_water);
7435
7436 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7437 for (i = 0; i < 2000; i++) {
7438 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7439 break;
7440 udelay(10);
7441 }
7442 if (i >= 2000) {
7443 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7444 tp->dev->name);
7445 return -ENODEV;
7446 }
7447
7448 /* Setup replenish threshold. */
f92905de
MC		 7449 val = tp->rx_pending / 8;
7450 if (val == 0)
7451 val = 1;
7452 else if (val > tp->rx_std_max_post)
7453 val = tp->rx_std_max_post;
b5d3772c
MC		 7454 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7455 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7456 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7457
7458 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7459 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7460 }
f92905de
MC		 7461
7462 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7463
7464 /* Initialize TG3_BDINFO's at:
7465 * RCVDBDI_STD_BD: standard eth size rx ring
7466 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7467 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7468 *
7469 * like so:
7470 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7471 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7472 * ring attribute flags
7473 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7474 *
7475 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7476 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7477 *
7478 * The size of each ring is fixed in the firmware, but the location is
7479 * configurable.
7480 */
7481 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7482 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7483 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7484 ((u64) tpr->rx_std_mapping & 0xffffffff));
87668d35
MC		 7485 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7486 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7487 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7488
fdb72b38
MC		 7489 /* Disable the mini ring */
7490 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7491 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7492 BDINFO_FLAGS_DISABLED);
7493
fdb72b38
MC		 7494 /* Program the jumbo buffer descriptor ring control
7495 * blocks on those devices that have them.
7496 */
8f666b07 7497 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7498 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7499 /* Setup replenish threshold. */
7500 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7501
0f893dc6 7502 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7503 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7504 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7505 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7506 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7507 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7508 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7509 BDINFO_FLAGS_USE_EXT_RECV);
87668d35
MC		 7510 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7511 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7512 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7513 } else {
7514 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7515 BDINFO_FLAGS_DISABLED);
7516 }
7517
f6eb9b1f
MC		 7518 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7519 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7520 (RX_STD_MAX_SIZE << 2);
7521 else
7522 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7523 } else
7524 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7525
7526 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7527
411da640 7528 tpr->rx_std_prod_idx = tp->rx_pending;
1da177e4 7529 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
411da640 7530 tpr->rx_std_prod_idx);
1da177e4 7531
411da640 7532 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
21f581a5 7533 tp->rx_jumbo_pending : 0;
1da177e4 7534 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
411da640 7535 tpr->rx_jmb_prod_idx);
1da177e4 7536
f6eb9b1f
MC		 7537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7538 tw32(STD_REPLENISH_LWM, 32);
7539 tw32(JMB_REPLENISH_LWM, 16);
7540 }
7541
2d31ecaf
MC		 7542 tg3_rings_reset(tp);
7543
1da177e4 7544 /* Initialize MAC address and backoff seed. */
986e0aeb 7545 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7546
7547 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7548 tw32(MAC_RX_MTU_SIZE,
7549 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7550
7551 /* The slot time is changed by tg3_setup_phy if we
7552 * run at gigabit with half duplex.
7553 */
7554 tw32(MAC_TX_LENGTHS,
7555 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7556 (6 << TX_LENGTHS_IPG_SHIFT) |
7557 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7558
7559 /* Receive rules. */
7560 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7561 tw32(RCVLPC_CONFIG, 0x0181);
7562
7563 /* Calculate RDMAC_MODE setting early, we need it to determine
7564 * the RCVLPC_STATE_ENABLE mask.
7565 */
7566 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7567 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7568 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7569 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7570 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7571
57e6983c 7572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7575 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7576 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7577 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7578
85e94ced
MC		 7579 /* If statement applies to 5705 and 5750 PCI devices only */
7580 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7581 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7582 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7583 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7584 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7585 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7586 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7587 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7588 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7589 }
7590 }
7591
85e94ced
MC		 7592 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7593 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7594
1da177e4 7595 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7596 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7597
e849cdc3
MC		 7598 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7599 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
027455ad
MC		 7600 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7601 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7602
7603 /* Receive/send statistics. */
1661394e
MC		 7604 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7605 val = tr32(RCVLPC_STATS_ENABLE);
7606 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7607 tw32(RCVLPC_STATS_ENABLE, val);
7608 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7609 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7610 val = tr32(RCVLPC_STATS_ENABLE);
7611 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7612 tw32(RCVLPC_STATS_ENABLE, val);
7613 } else {
7614 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7615 }
7616 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7617 tw32(SNDDATAI_STATSENAB, 0xffffff);
7618 tw32(SNDDATAI_STATSCTRL,
7619 (SNDDATAI_SCTRL_ENABLE |
7620 SNDDATAI_SCTRL_FASTUPD));
7621
7622 /* Setup host coalescing engine. */
7623 tw32(HOSTCC_MODE, 0);
7624 for (i = 0; i < 2000; i++) {
7625 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7626 break;
7627 udelay(10);
7628 }
7629
d244c892 7630 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7631
1da177e4
LT		 7632 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7633 /* Status/statistics block address. See tg3_timer,
7634 * the tg3_periodic_fetch_stats call there, and
7635 * tg3_get_stats to see how this works for 5705/5750 chips.
7636 */
1da177e4
LT		 7637 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7638 ((u64) tp->stats_mapping >> 32));
7639 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7640 ((u64) tp->stats_mapping & 0xffffffff));
7641 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7642
1da177e4 7643 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7644
7645 /* Clear statistics and status block memory areas */
7646 for (i = NIC_SRAM_STATS_BLK;
7647 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7648 i += sizeof(u32)) {
7649 tg3_write_mem(tp, i, 0);
7650 udelay(40);
7651 }
1da177e4
LT		 7652 }
7653
7654 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7655
7656 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7657 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7658 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7659 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7660
c94e3941
MC		 7661 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7662 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7663 /* reset to prevent losing 1st rx packet intermittently */
7664 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7665 udelay(10);
7666 }
7667
3bda1258
MC		 7668 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7669 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7670 else
7671 tp->mac_mode = 0;
7672 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7673 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7674 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7675 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7676 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7677 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7678 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7679 udelay(40);
7680
314fba34 7681 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7682 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7683 * register to preserve the GPIO settings for LOMs. The GPIOs,
7684 * whether used as inputs or outputs, are set by boot code after
7685 * reset.
7686 */
9d26e213 7687 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7688 u32 gpio_mask;
7689
9d26e213
MC		 7690 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7691 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7692 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7693
7694 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7695 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7696 GRC_LCLCTRL_GPIO_OUTPUT3;
7697
af36e6b6
MC		 7698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7699 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7700
aaf84465 7701 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7702 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7703
7704 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7705 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7706 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7707 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7708 }
1da177e4
LT		 7709 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7710 udelay(100);
7711
baf8a94a
MC		 7712 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7713 val = tr32(MSGINT_MODE);
7714 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7715 tw32(MSGINT_MODE, val);
7716 }
7717
1da177e4
LT		 7718 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7719 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7720 udelay(40);
7721 }
7722
7723 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7724 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7725 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7726 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7727 WDMAC_MODE_LNGREAD_ENAB);
7728
85e94ced
MC		 7729 /* If statement applies to 5705 and 5750 PCI devices only */
7730 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7731 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7732 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7733 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7734 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7735 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7736 /* nothing */
7737 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7738 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7739 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7740 val |= WDMAC_MODE_RX_ACCEL;
7741 }
7742 }
7743
d9ab5ad1 7744 /* Enable host coalescing bug fix */
321d32a0 7745 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7746 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7747
788a035e
MC		 7748 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7749 val |= WDMAC_MODE_BURST_ALL_DATA;
7750
1da177e4
LT		 7751 tw32_f(WDMAC_MODE, val);
7752 udelay(40);
7753
9974a356
MC		 7754 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7755 u16 pcix_cmd;
7756
7757 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7758 &pcix_cmd);
1da177e4 7759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7760 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7761 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7762 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7763 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7764 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7765 }
9974a356
MC		 7766 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7767 pcix_cmd);
1da177e4
LT		 7768 }
7769
7770 tw32_f(RDMAC_MODE, rdmac_mode);
7771 udelay(40);
7772
7773 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7774 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7775 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7776
7777 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7778 tw32(SNDDATAC_MODE,
7779 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7780 else
7781 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7782
1da177e4
LT		 7783 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7784 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7785 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7786 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7787 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7788 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7789 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7790 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7791 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7792 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7793 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7794
7795 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7796 err = tg3_load_5701_a0_firmware_fix(tp);
7797 if (err)
7798 return err;
7799 }
7800
1da177e4
LT		 7801 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7802 err = tg3_load_tso_firmware(tp);
7803 if (err)
7804 return err;
7805 }
1da177e4
LT		 7806
7807 tp->tx_mode = TX_MODE_ENABLE;
7808 tw32_f(MAC_TX_MODE, tp->tx_mode);
7809 udelay(100);
7810
baf8a94a
MC		 7811 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7812 u32 reg = MAC_RSS_INDIR_TBL_0;
7813 u8 *ent = (u8 *)&val;
7814
7815 /* Setup the indirection table */
7816 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7817 int idx = i % sizeof(val);
7818
7819 ent[idx] = i % (tp->irq_cnt - 1);
7820 if (idx == sizeof(val) - 1) {
7821 tw32(reg, val);
7822 reg += 4;
7823 }
7824 }
7825
7826 /* Setup the "secret" hash key. */
7827 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7828 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7829 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7830 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7831 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7832 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7833 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7834 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7835 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7836 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7837 }
7838
1da177e4 7839 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7840 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7841 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7842
baf8a94a
MC		 7843 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7844 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7845 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7846 RX_MODE_RSS_IPV6_HASH_EN |
7847 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7848 RX_MODE_RSS_IPV4_HASH_EN |
7849 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7850
1da177e4
LT		 7851 tw32_f(MAC_RX_MODE, tp->rx_mode);
7852 udelay(10);
7853
1da177e4
LT		 7854 tw32(MAC_LED_CTRL, tp->led_ctrl);
7855
7856 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7857 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7858 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7859 udelay(10);
7860 }
7861 tw32_f(MAC_RX_MODE, tp->rx_mode);
7862 udelay(10);
7863
7864 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7865 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7866 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7867 /* Set drive transmission level to 1.2V */
7868 /* only if the signal pre-emphasis bit is not set */
7869 val = tr32(MAC_SERDES_CFG);
7870 val &= 0xfffff000;
7871 val |= 0x880;
7872 tw32(MAC_SERDES_CFG, val);
7873 }
7874 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7875 tw32(MAC_SERDES_CFG, 0x616000);
7876 }
7877
7878 /* Prevent chip from dropping frames when flow control
7879 * is enabled.
7880 */
7881 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7882
7883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7884 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7885 /* Use hardware link auto-negotiation */
7886 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7887 }
7888
d4d2c558
MC		 7889 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7890 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7891 u32 tmp;
7892
7893 tmp = tr32(SERDES_RX_CTRL);
7894 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7895 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7896 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7897 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7898 }
7899
dd477003
MC		 7900 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7901 if (tp->link_config.phy_is_low_power) {
7902 tp->link_config.phy_is_low_power = 0;
7903 tp->link_config.speed = tp->link_config.orig_speed;
7904 tp->link_config.duplex = tp->link_config.orig_duplex;
7905 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7906 }
1da177e4 7907
dd477003
MC		 7908 err = tg3_setup_phy(tp, 0);
7909 if (err)
7910 return err;
1da177e4 7911
dd477003 7912 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7913 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7914 u32 tmp;
7915
7916 /* Clear CRC stats. */
7917 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7918 tg3_writephy(tp, MII_TG3_TEST1,
7919 tmp | MII_TG3_TEST1_CRC_EN);
7920 tg3_readphy(tp, 0x14, &tmp);
7921 }
1da177e4
LT		 7922 }
7923 }
7924
7925 __tg3_set_rx_mode(tp->dev);
7926
7927 /* Initialize receive rules. */
7928 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7929 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7930 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7931 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7932
4cf78e4f 7933 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7934 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7935 limit = 8;
7936 else
7937 limit = 16;
7938 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7939 limit -= 4;
7940 switch (limit) {
7941 case 16:
7942 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7943 case 15:
7944 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7945 case 14:
7946 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7947 case 13:
7948 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7949 case 12:
7950 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7951 case 11:
7952 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7953 case 10:
7954 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7955 case 9:
7956 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7957 case 8:
7958 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7959 case 7:
7960 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7961 case 6:
7962 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7963 case 5:
7964 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7965 case 4:
7966 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7967 case 3:
7968 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7969 case 2:
7970 case 1:
7971
7972 default:
7973 break;
855e1111 7974 }
1da177e4 7975
9ce768ea
MC		 7976 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7977 /* Write our heartbeat update interval to APE. */
7978 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7979 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7980
1da177e4
LT		 7981 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7982
1da177e4
LT		 7983 return 0;
7984}
7985
7986/* Called at device open time to get the chip ready for
7987 * packet processing. Invoked with tp->lock held.
7988 */
8e7a22e3 7989static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7990{
1da177e4
LT		 7991 tg3_switch_clocks(tp);
7992
7993 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7994
2f751b67 7995 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7996}
7997
7998#define TG3_STAT_ADD32(PSTAT, REG) \
7999do { u32 __val = tr32(REG); \
8000 (PSTAT)->low += __val; \
8001 if ((PSTAT)->low < __val) \
8002 (PSTAT)->high += 1; \
8003} while (0)
8004
8005static void tg3_periodic_fetch_stats(struct tg3 *tp)
8006{
8007 struct tg3_hw_stats *sp = tp->hw_stats;
8008
8009 if (!netif_carrier_ok(tp->dev))
8010 return;
8011
8012 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8013 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8014 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8015 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8016 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8017 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8018 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8019 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8020 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8021 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8022 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8023 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8024 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8025
8026 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8027 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8028 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8029 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8030 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8031 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8032 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8033 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8034 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8035 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8036 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8037 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8038 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8039 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 8040
8041 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8042 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8043 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 8044}
8045
8046static void tg3_timer(unsigned long __opaque)
8047{
8048 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 8049
f475f163
MC		 8050 if (tp->irq_sync)
8051 goto restart_timer;
8052
f47c11ee 8053 spin_lock(&tp->lock);
1da177e4 8054
fac9b83e
DM		 8055 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8056 /* All of this garbage is because when using non-tagged
8057 * IRQ status the mailbox/status_block protocol the chip
8058 * uses with the cpu is race prone.
8059 */
898a56f8 8060 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 8061 tw32(GRC_LOCAL_CTRL,
8062 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8063 } else {
8064 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 8065 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 8066 }
1da177e4 8067
fac9b83e
DM		 8068 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8069 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 8070 spin_unlock(&tp->lock);
fac9b83e
DM		 8071 schedule_work(&tp->reset_task);
8072 return;
8073 }
1da177e4
LT		 8074 }
8075
1da177e4
LT		 8076 /* This part only runs once per second. */
8077 if (!--tp->timer_counter) {
fac9b83e
DM		 8078 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8079 tg3_periodic_fetch_stats(tp);
8080
1da177e4
LT		 8081 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8082 u32 mac_stat;
8083 int phy_event;
8084
8085 mac_stat = tr32(MAC_STATUS);
8086
8087 phy_event = 0;
8088 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8089 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8090 phy_event = 1;
8091 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8092 phy_event = 1;
8093
8094 if (phy_event)
8095 tg3_setup_phy(tp, 0);
8096 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8097 u32 mac_stat = tr32(MAC_STATUS);
8098 int need_setup = 0;
8099
8100 if (netif_carrier_ok(tp->dev) &&
8101 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8102 need_setup = 1;
8103 }
8104 if (! netif_carrier_ok(tp->dev) &&
8105 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8106 MAC_STATUS_SIGNAL_DET))) {
8107 need_setup = 1;
8108 }
8109 if (need_setup) {
3d3ebe74
MC		 8110 if (!tp->serdes_counter) {
8111 tw32_f(MAC_MODE,
8112 (tp->mac_mode &
8113 ~MAC_MODE_PORT_MODE_MASK));
8114 udelay(40);
8115 tw32_f(MAC_MODE, tp->mac_mode);
8116 udelay(40);
8117 }
1da177e4
LT		 8118 tg3_setup_phy(tp, 0);
8119 }
747e8f8b
MC		 8120 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8121 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8122
8123 tp->timer_counter = tp->timer_multiplier;
8124 }
8125
130b8e4d
MC		 8126 /* Heartbeat is only sent once every 2 seconds.
8127 *
8128 * The heartbeat is to tell the ASF firmware that the host
8129 * driver is still alive. In the event that the OS crashes,
8130 * ASF needs to reset the hardware to free up the FIFO space
8131 * that may be filled with rx packets destined for the host.
8132 * If the FIFO is full, ASF will no longer function properly.
8133 *
8134 * Unintended resets have been reported on real time kernels
8135 * where the timer doesn't run on time. Netpoll will also have
8136 * same problem.
8137 *
8138 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8139 * to check the ring condition when the heartbeat is expiring
8140 * before doing the reset. This will prevent most unintended
8141 * resets.
8142 */
1da177e4 8143 if (!--tp->asf_counter) {
bc7959b2
MC		 8144 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8145 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8146 tg3_wait_for_event_ack(tp);
8147
bbadf503 8148 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8149 FWCMD_NICDRV_ALIVE3);
bbadf503 8150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8151 /* 5 seconds timeout */
bbadf503 8152 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8153
8154 tg3_generate_fw_event(tp);
1da177e4
LT		 8155 }
8156 tp->asf_counter = tp->asf_multiplier;
8157 }
8158
f47c11ee 8159 spin_unlock(&tp->lock);
1da177e4 8160
f475f163 8161restart_timer:
1da177e4
LT		 8162 tp->timer.expires = jiffies + tp->timer_offset;
8163 add_timer(&tp->timer);
8164}
8165
4f125f42 8166static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8167{
7d12e780 8168 irq_handler_t fn;
fcfa0a32 8169 unsigned long flags;
4f125f42
MC		 8170 char *name;
8171 struct tg3_napi *tnapi = &tp->napi[irq_num];
8172
8173 if (tp->irq_cnt == 1)
8174 name = tp->dev->name;
8175 else {
8176 name = &tnapi->irq_lbl[0];
8177 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8178 name[IFNAMSIZ-1] = 0;
8179 }
fcfa0a32 8180
679563f4 8181 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8182 fn = tg3_msi;
8183 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8184 fn = tg3_msi_1shot;
1fb9df5d 8185 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8186 } else {
8187 fn = tg3_interrupt;
8188 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8189 fn = tg3_interrupt_tagged;
1fb9df5d 8190 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8191 }
4f125f42
MC		 8192
8193 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8194}
8195
7938109f
MC		 8196static int tg3_test_interrupt(struct tg3 *tp)
8197{
09943a18 8198 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8199 struct net_device *dev = tp->dev;
b16250e3 8200 int err, i, intr_ok = 0;
f6eb9b1f 8201 u32 val;
7938109f 8202
d4bc3927
MC		 8203 if (!netif_running(dev))
8204 return -ENODEV;
8205
7938109f
MC		 8206 tg3_disable_ints(tp);
8207
4f125f42 8208 free_irq(tnapi->irq_vec, tnapi);
7938109f 8209
f6eb9b1f
MC		 8210 /*
8211 * Turn off MSI one shot mode. Otherwise this test has no
8212 * observable way to know whether the interrupt was delivered.
8213 */
8214 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8215 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8216 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8217 tw32(MSGINT_MODE, val);
8218 }
8219
4f125f42 8220 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8221 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8222 if (err)
8223 return err;
8224
898a56f8 8225 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8226 tg3_enable_ints(tp);
8227
8228 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8229 tnapi->coal_now);
7938109f
MC		 8230
8231 for (i = 0; i < 5; i++) {
b16250e3
MC		 8232 u32 int_mbox, misc_host_ctrl;
8233
898a56f8 8234 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8235 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8236
8237 if ((int_mbox != 0) ||
8238 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8239 intr_ok = 1;
7938109f 8240 break;
b16250e3
MC		 8241 }
8242
7938109f
MC		 8243 msleep(10);
8244 }
8245
8246 tg3_disable_ints(tp);
8247
4f125f42 8248 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8249
4f125f42 8250 err = tg3_request_irq(tp, 0);
7938109f
MC		 8251
8252 if (err)
8253 return err;
8254
f6eb9b1f
MC		 8255 if (intr_ok) {
8256 /* Reenable MSI one shot mode. */
8257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8258 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8259 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8260 tw32(MSGINT_MODE, val);
8261 }
7938109f 8262 return 0;
f6eb9b1f 8263 }
7938109f
MC		 8264
8265 return -EIO;
8266}
8267
8268/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8269 * successfully restored
8270 */
8271static int tg3_test_msi(struct tg3 *tp)
8272{
7938109f
MC		 8273 int err;
8274 u16 pci_cmd;
8275
8276 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8277 return 0;
8278
8279 /* Turn off SERR reporting in case MSI terminates with Master
8280 * Abort.
8281 */
8282 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8283 pci_write_config_word(tp->pdev, PCI_COMMAND,
8284 pci_cmd & ~PCI_COMMAND_SERR);
8285
8286 err = tg3_test_interrupt(tp);
8287
8288 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8289
8290 if (!err)
8291 return 0;
8292
8293 /* other failures */
8294 if (err != -EIO)
8295 return err;
8296
8297 /* MSI test failed, go back to INTx mode */
8298 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8299 "switching to INTx mode. Please report this failure to "
8300 "the PCI maintainer and include system chipset information.\n",
8301 tp->dev->name);
8302
4f125f42 8303 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8304
7938109f
MC		 8305 pci_disable_msi(tp->pdev);
8306
8307 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8308
4f125f42 8309 err = tg3_request_irq(tp, 0);
7938109f
MC		 8310 if (err)
8311 return err;
8312
8313 /* Need to reset the chip because the MSI cycle may have terminated
8314 * with Master Abort.
8315 */
f47c11ee 8316 tg3_full_lock(tp, 1);
7938109f 8317
944d980e 8318 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8319 err = tg3_init_hw(tp, 1);
7938109f 8320
f47c11ee 8321 tg3_full_unlock(tp);
7938109f
MC		 8322
8323 if (err)
4f125f42 8324 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8325
8326 return err;
8327}
8328
9e9fd12d
MC		 8329static int tg3_request_firmware(struct tg3 *tp)
8330{
8331 const __be32 *fw_data;
8332
8333 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8334 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8335 tp->dev->name, tp->fw_needed);
8336 return -ENOENT;
8337 }
8338
8339 fw_data = (void *)tp->fw->data;
8340
8341 /* Firmware blob starts with version numbers, followed by
8342 * start address and _full_ length including BSS sections
8343 * (which must be longer than the actual data, of course
8344 */
8345
8346 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8347 if (tp->fw_len < (tp->fw->size - 12)) {
8348 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8349 tp->dev->name, tp->fw_len, tp->fw_needed);
8350 release_firmware(tp->fw);
8351 tp->fw = NULL;
8352 return -EINVAL;
8353 }
8354
8355 /* We no longer need firmware; we have it. */
8356 tp->fw_needed = NULL;
8357 return 0;
8358}
8359
679563f4
MC		 8360static bool tg3_enable_msix(struct tg3 *tp)
8361{
8362 int i, rc, cpus = num_online_cpus();
8363 struct msix_entry msix_ent[tp->irq_max];
8364
8365 if (cpus == 1)
8366 /* Just fallback to the simpler MSI mode. */
8367 return false;
8368
8369 /*
8370 * We want as many rx rings enabled as there are cpus.
8371 * The first MSIX vector only deals with link interrupts, etc,
8372 * so we add one to the number of vectors we are requesting.
8373 */
8374 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8375
8376 for (i = 0; i < tp->irq_max; i++) {
8377 msix_ent[i].entry = i;
8378 msix_ent[i].vector = 0;
8379 }
8380
8381 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8382 if (rc != 0) {
8383 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8384 return false;
8385 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8386 return false;
8387 printk(KERN_NOTICE
8388 "%s: Requested %d MSI-X vectors, received %d\n",
8389 tp->dev->name, tp->irq_cnt, rc);
8390 tp->irq_cnt = rc;
8391 }
8392
baf8a94a
MC		 8393 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8394
679563f4
MC		 8395 for (i = 0; i < tp->irq_max; i++)
8396 tp->napi[i].irq_vec = msix_ent[i].vector;
8397
fe5f5787
MC		 8398 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8399
679563f4
MC		 8400 return true;
8401}
8402
07b0173c
MC		 8403static void tg3_ints_init(struct tg3 *tp)
8404{
679563f4
MC		 8405 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8406 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8407 /* All MSI supporting chips should support tagged
8408 * status. Assert that this is the case.
8409 */
679563f4
MC		 8410 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8411 "Not using MSI.\n", tp->dev->name);
8412 goto defcfg;
07b0173c 8413 }
4f125f42 8414
679563f4
MC		 8415 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8416 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8417 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8418 pci_enable_msi(tp->pdev) == 0)
8419 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8420
8421 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8422 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8423 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8424 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8425 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8426 }
8427defcfg:
8428 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8429 tp->irq_cnt = 1;
8430 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8431 tp->dev->real_num_tx_queues = 1;
679563f4 8432 }
07b0173c
MC		 8433}
8434
8435static void tg3_ints_fini(struct tg3 *tp)
8436{
679563f4
MC		 8437 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8438 pci_disable_msix(tp->pdev);
8439 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8440 pci_disable_msi(tp->pdev);
8441 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8442 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8443}
8444
1da177e4
LT		 8445static int tg3_open(struct net_device *dev)
8446{
8447 struct tg3 *tp = netdev_priv(dev);
4f125f42 8448 int i, err;
1da177e4 8449
9e9fd12d
MC		 8450 if (tp->fw_needed) {
8451 err = tg3_request_firmware(tp);
8452 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8453 if (err)
8454 return err;
8455 } else if (err) {
8456 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8457 tp->dev->name);
8458 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8459 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8460 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8461 tp->dev->name);
8462 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8463 }
8464 }
8465
c49a1561
MC		 8466 netif_carrier_off(tp->dev);
8467
bc1c7567 8468 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8469 if (err)
bc1c7567 8470 return err;
2f751b67
MC		 8471
8472 tg3_full_lock(tp, 0);
bc1c7567 8473
1da177e4
LT		 8474 tg3_disable_ints(tp);
8475 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8476
f47c11ee 8477 tg3_full_unlock(tp);
1da177e4 8478
679563f4
MC		 8479 /*
8480 * Setup interrupts first so we know how
8481 * many NAPI resources to allocate
8482 */
8483 tg3_ints_init(tp);
8484
1da177e4
LT		 8485 /* The placement of this call is tied
8486 * to the setup and use of Host TX descriptors.
8487 */
8488 err = tg3_alloc_consistent(tp);
8489 if (err)
679563f4 8490 goto err_out1;
88b06bc2 8491
fed97810 8492 tg3_napi_enable(tp);
1da177e4 8493
4f125f42
MC		 8494 for (i = 0; i < tp->irq_cnt; i++) {
8495 struct tg3_napi *tnapi = &tp->napi[i];
8496 err = tg3_request_irq(tp, i);
8497 if (err) {
8498 for (i--; i >= 0; i--)
8499 free_irq(tnapi->irq_vec, tnapi);
8500 break;
8501 }
8502 }
1da177e4 8503
07b0173c 8504 if (err)
679563f4 8505 goto err_out2;
bea3348e 8506
f47c11ee 8507 tg3_full_lock(tp, 0);
1da177e4 8508
8e7a22e3 8509 err = tg3_init_hw(tp, 1);
1da177e4 8510 if (err) {
944d980e 8511 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8512 tg3_free_rings(tp);
8513 } else {
fac9b83e
DM		 8514 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8515 tp->timer_offset = HZ;
8516 else
8517 tp->timer_offset = HZ / 10;
8518
8519 BUG_ON(tp->timer_offset > HZ);
8520 tp->timer_counter = tp->timer_multiplier =
8521 (HZ / tp->timer_offset);
8522 tp->asf_counter = tp->asf_multiplier =
28fbef78 8523 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8524
8525 init_timer(&tp->timer);
8526 tp->timer.expires = jiffies + tp->timer_offset;
8527 tp->timer.data = (unsigned long) tp;
8528 tp->timer.function = tg3_timer;
1da177e4
LT		 8529 }
8530
f47c11ee 8531 tg3_full_unlock(tp);
1da177e4 8532
07b0173c 8533 if (err)
679563f4 8534 goto err_out3;
1da177e4 8535
7938109f
MC		 8536 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8537 err = tg3_test_msi(tp);
fac9b83e 8538
7938109f 8539 if (err) {
f47c11ee 8540 tg3_full_lock(tp, 0);
944d980e 8541 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8542 tg3_free_rings(tp);
f47c11ee 8543 tg3_full_unlock(tp);
7938109f 8544
679563f4 8545 goto err_out2;
7938109f 8546 }
fcfa0a32 8547
f6eb9b1f
MC		 8548 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8549 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8550 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8551 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8552
f6eb9b1f
MC		 8553 tw32(PCIE_TRANSACTION_CFG,
8554 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8555 }
7938109f
MC		 8556 }
8557
b02fd9e3
MC		 8558 tg3_phy_start(tp);
8559
f47c11ee 8560 tg3_full_lock(tp, 0);
1da177e4 8561
7938109f
MC		 8562 add_timer(&tp->timer);
8563 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8564 tg3_enable_ints(tp);
8565
f47c11ee 8566 tg3_full_unlock(tp);
1da177e4 8567
fe5f5787 8568 netif_tx_start_all_queues(dev);
1da177e4
LT		 8569
8570 return 0;
07b0173c 8571
679563f4 8572err_out3:
4f125f42
MC		 8573 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8574 struct tg3_napi *tnapi = &tp->napi[i];
8575 free_irq(tnapi->irq_vec, tnapi);
8576 }
07b0173c 8577
679563f4 8578err_out2:
fed97810 8579 tg3_napi_disable(tp);
07b0173c 8580 tg3_free_consistent(tp);
679563f4
MC		 8581
8582err_out1:
8583 tg3_ints_fini(tp);
07b0173c 8584 return err;
1da177e4
LT		 8585}
8586
8587#if 0
8588/*static*/ void tg3_dump_state(struct tg3 *tp)
8589{
8590 u32 val32, val32_2, val32_3, val32_4, val32_5;
8591 u16 val16;
8592 int i;
898a56f8 8593 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8594
8595 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8596 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8597 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8598 val16, val32);
8599
8600 /* MAC block */
8601 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8602 tr32(MAC_MODE), tr32(MAC_STATUS));
8603 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8604 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8605 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8606 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8607 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8608 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8609
8610 /* Send data initiator control block */
8611 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8612 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8613 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8614 tr32(SNDDATAI_STATSCTRL));
8615
8616 /* Send data completion control block */
8617 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8618
8619 /* Send BD ring selector block */
8620 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8621 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8622
8623 /* Send BD initiator control block */
8624 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8625 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8626
8627 /* Send BD completion control block */
8628 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8629
8630 /* Receive list placement control block */
8631 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8632 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8633 printk(" RCVLPC_STATSCTRL[%08x]\n",
8634 tr32(RCVLPC_STATSCTRL));
8635
8636 /* Receive data and receive BD initiator control block */
8637 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8638 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8639
8640 /* Receive data completion control block */
8641 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8642 tr32(RCVDCC_MODE));
8643
8644 /* Receive BD initiator control block */
8645 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8646 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8647
8648 /* Receive BD completion control block */
8649 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8650 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8651
8652 /* Receive list selector control block */
8653 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8654 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8655
8656 /* Mbuf cluster free block */
8657 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8658 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8659
8660 /* Host coalescing control block */
8661 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8662 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8663 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8664 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8665 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8666 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8667 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8668 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8669 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8670 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8671 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8672 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8673
8674 /* Memory arbiter control block */
8675 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8676 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8677
8678 /* Buffer manager control block */
8679 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8680 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8681 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8682 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8683 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8684 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8685 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8686 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8687
8688 /* Read DMA control block */
8689 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8690 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8691
8692 /* Write DMA control block */
8693 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8694 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8695
8696 /* DMA completion block */
8697 printk("DEBUG: DMAC_MODE[%08x]\n",
8698 tr32(DMAC_MODE));
8699
8700 /* GRC block */
8701 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8702 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8703 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8704 tr32(GRC_LOCAL_CTRL));
8705
8706 /* TG3_BDINFOs */
8707 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8708 tr32(RCVDBDI_JUMBO_BD + 0x0),
8709 tr32(RCVDBDI_JUMBO_BD + 0x4),
8710 tr32(RCVDBDI_JUMBO_BD + 0x8),
8711 tr32(RCVDBDI_JUMBO_BD + 0xc));
8712 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8713 tr32(RCVDBDI_STD_BD + 0x0),
8714 tr32(RCVDBDI_STD_BD + 0x4),
8715 tr32(RCVDBDI_STD_BD + 0x8),
8716 tr32(RCVDBDI_STD_BD + 0xc));
8717 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8718 tr32(RCVDBDI_MINI_BD + 0x0),
8719 tr32(RCVDBDI_MINI_BD + 0x4),
8720 tr32(RCVDBDI_MINI_BD + 0x8),
8721 tr32(RCVDBDI_MINI_BD + 0xc));
8722
8723 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8724 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8725 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8726 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8727 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8728 val32, val32_2, val32_3, val32_4);
8729
8730 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8731 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8732 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8733 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8734 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8735 val32, val32_2, val32_3, val32_4);
8736
8737 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8738 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8739 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8740 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8741 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8742 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8743 val32, val32_2, val32_3, val32_4, val32_5);
8744
8745 /* SW status block */
898a56f8
MC		 8746 printk(KERN_DEBUG
8747 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8748 sblk->status,
8749 sblk->status_tag,
8750 sblk->rx_jumbo_consumer,
8751 sblk->rx_consumer,
8752 sblk->rx_mini_consumer,
8753 sblk->idx[0].rx_producer,
8754 sblk->idx[0].tx_consumer);
1da177e4
LT		 8755
8756 /* SW statistics block */
8757 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8758 ((u32 *)tp->hw_stats)[0],
8759 ((u32 *)tp->hw_stats)[1],
8760 ((u32 *)tp->hw_stats)[2],
8761 ((u32 *)tp->hw_stats)[3]);
8762
8763 /* Mailboxes */
8764 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8765 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8766 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8767 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8768 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8769
8770 /* NIC side send descriptors. */
8771 for (i = 0; i < 6; i++) {
8772 unsigned long txd;
8773
8774 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8775 + (i * sizeof(struct tg3_tx_buffer_desc));
8776 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8777 i,
8778 readl(txd + 0x0), readl(txd + 0x4),
8779 readl(txd + 0x8), readl(txd + 0xc));
8780 }
8781
8782 /* NIC side RX descriptors. */
8783 for (i = 0; i < 6; i++) {
8784 unsigned long rxd;
8785
8786 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8787 + (i * sizeof(struct tg3_rx_buffer_desc));
8788 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8789 i,
8790 readl(rxd + 0x0), readl(rxd + 0x4),
8791 readl(rxd + 0x8), readl(rxd + 0xc));
8792 rxd += (4 * sizeof(u32));
8793 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8794 i,
8795 readl(rxd + 0x0), readl(rxd + 0x4),
8796 readl(rxd + 0x8), readl(rxd + 0xc));
8797 }
8798
8799 for (i = 0; i < 6; i++) {
8800 unsigned long rxd;
8801
8802 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8803 + (i * sizeof(struct tg3_rx_buffer_desc));
8804 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8805 i,
8806 readl(rxd + 0x0), readl(rxd + 0x4),
8807 readl(rxd + 0x8), readl(rxd + 0xc));
8808 rxd += (4 * sizeof(u32));
8809 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8810 i,
8811 readl(rxd + 0x0), readl(rxd + 0x4),
8812 readl(rxd + 0x8), readl(rxd + 0xc));
8813 }
8814}
8815#endif
8816
8817static struct net_device_stats *tg3_get_stats(struct net_device *);
8818static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8819
8820static int tg3_close(struct net_device *dev)
8821{
4f125f42 8822 int i;
1da177e4
LT		 8823 struct tg3 *tp = netdev_priv(dev);
8824
fed97810 8825 tg3_napi_disable(tp);
28e53bdd 8826 cancel_work_sync(&tp->reset_task);
7faa006f 8827
fe5f5787 8828 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8829
8830 del_timer_sync(&tp->timer);
8831
24bb4fb6
MC		 8832 tg3_phy_stop(tp);
8833
f47c11ee 8834 tg3_full_lock(tp, 1);
1da177e4
LT		 8835#if 0
8836 tg3_dump_state(tp);
8837#endif
8838
8839 tg3_disable_ints(tp);
8840
944d980e 8841 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8842 tg3_free_rings(tp);
5cf64b8a 8843 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8844
f47c11ee 8845 tg3_full_unlock(tp);
1da177e4 8846
4f125f42
MC		 8847 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8848 struct tg3_napi *tnapi = &tp->napi[i];
8849 free_irq(tnapi->irq_vec, tnapi);
8850 }
07b0173c
MC		 8851
8852 tg3_ints_fini(tp);
1da177e4
LT		 8853
8854 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8855 sizeof(tp->net_stats_prev));
8856 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8857 sizeof(tp->estats_prev));
8858
8859 tg3_free_consistent(tp);
8860
bc1c7567
MC		 8861 tg3_set_power_state(tp, PCI_D3hot);
8862
8863 netif_carrier_off(tp->dev);
8864
1da177e4
LT		 8865 return 0;
8866}
8867
8868static inline unsigned long get_stat64(tg3_stat64_t *val)
8869{
8870 unsigned long ret;
8871
8872#if (BITS_PER_LONG == 32)
8873 ret = val->low;
8874#else
8875 ret = ((u64)val->high << 32) | ((u64)val->low);
8876#endif
8877 return ret;
8878}
8879
816f8b86
SB		 8880static inline u64 get_estat64(tg3_stat64_t *val)
8881{
8882 return ((u64)val->high << 32) | ((u64)val->low);
8883}
8884
1da177e4
LT		 8885static unsigned long calc_crc_errors(struct tg3 *tp)
8886{
8887 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8888
8889 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8890 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8892 u32 val;
8893
f47c11ee 8894 spin_lock_bh(&tp->lock);
569a5df8
MC		 8895 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8896 tg3_writephy(tp, MII_TG3_TEST1,
8897 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8898 tg3_readphy(tp, 0x14, &val);
8899 } else
8900 val = 0;
f47c11ee 8901 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8902
8903 tp->phy_crc_errors += val;
8904
8905 return tp->phy_crc_errors;
8906 }
8907
8908 return get_stat64(&hw_stats->rx_fcs_errors);
8909}
8910
8911#define ESTAT_ADD(member) \
8912 estats->member = old_estats->member + \
816f8b86 8913 get_estat64(&hw_stats->member)
1da177e4
LT		 8914
8915static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8916{
8917 struct tg3_ethtool_stats *estats = &tp->estats;
8918 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8919 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8920
8921 if (!hw_stats)
8922 return old_estats;
8923
8924 ESTAT_ADD(rx_octets);
8925 ESTAT_ADD(rx_fragments);
8926 ESTAT_ADD(rx_ucast_packets);
8927 ESTAT_ADD(rx_mcast_packets);
8928 ESTAT_ADD(rx_bcast_packets);
8929 ESTAT_ADD(rx_fcs_errors);
8930 ESTAT_ADD(rx_align_errors);
8931 ESTAT_ADD(rx_xon_pause_rcvd);
8932 ESTAT_ADD(rx_xoff_pause_rcvd);
8933 ESTAT_ADD(rx_mac_ctrl_rcvd);
8934 ESTAT_ADD(rx_xoff_entered);
8935 ESTAT_ADD(rx_frame_too_long_errors);
8936 ESTAT_ADD(rx_jabbers);
8937 ESTAT_ADD(rx_undersize_packets);
8938 ESTAT_ADD(rx_in_length_errors);
8939 ESTAT_ADD(rx_out_length_errors);
8940 ESTAT_ADD(rx_64_or_less_octet_packets);
8941 ESTAT_ADD(rx_65_to_127_octet_packets);
8942 ESTAT_ADD(rx_128_to_255_octet_packets);
8943 ESTAT_ADD(rx_256_to_511_octet_packets);
8944 ESTAT_ADD(rx_512_to_1023_octet_packets);
8945 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8946 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8947 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8948 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8949 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8950
8951 ESTAT_ADD(tx_octets);
8952 ESTAT_ADD(tx_collisions);
8953 ESTAT_ADD(tx_xon_sent);
8954 ESTAT_ADD(tx_xoff_sent);
8955 ESTAT_ADD(tx_flow_control);
8956 ESTAT_ADD(tx_mac_errors);
8957 ESTAT_ADD(tx_single_collisions);
8958 ESTAT_ADD(tx_mult_collisions);
8959 ESTAT_ADD(tx_deferred);
8960 ESTAT_ADD(tx_excessive_collisions);
8961 ESTAT_ADD(tx_late_collisions);
8962 ESTAT_ADD(tx_collide_2times);
8963 ESTAT_ADD(tx_collide_3times);
8964 ESTAT_ADD(tx_collide_4times);
8965 ESTAT_ADD(tx_collide_5times);
8966 ESTAT_ADD(tx_collide_6times);
8967 ESTAT_ADD(tx_collide_7times);
8968 ESTAT_ADD(tx_collide_8times);
8969 ESTAT_ADD(tx_collide_9times);
8970 ESTAT_ADD(tx_collide_10times);
8971 ESTAT_ADD(tx_collide_11times);
8972 ESTAT_ADD(tx_collide_12times);
8973 ESTAT_ADD(tx_collide_13times);
8974 ESTAT_ADD(tx_collide_14times);
8975 ESTAT_ADD(tx_collide_15times);
8976 ESTAT_ADD(tx_ucast_packets);
8977 ESTAT_ADD(tx_mcast_packets);
8978 ESTAT_ADD(tx_bcast_packets);
8979 ESTAT_ADD(tx_carrier_sense_errors);
8980 ESTAT_ADD(tx_discards);
8981 ESTAT_ADD(tx_errors);
8982
8983 ESTAT_ADD(dma_writeq_full);
8984 ESTAT_ADD(dma_write_prioq_full);
8985 ESTAT_ADD(rxbds_empty);
8986 ESTAT_ADD(rx_discards);
8987 ESTAT_ADD(rx_errors);
8988 ESTAT_ADD(rx_threshold_hit);
8989
8990 ESTAT_ADD(dma_readq_full);
8991 ESTAT_ADD(dma_read_prioq_full);
8992 ESTAT_ADD(tx_comp_queue_full);
8993
8994 ESTAT_ADD(ring_set_send_prod_index);
8995 ESTAT_ADD(ring_status_update);
8996 ESTAT_ADD(nic_irqs);
8997 ESTAT_ADD(nic_avoided_irqs);
8998 ESTAT_ADD(nic_tx_threshold_hit);
8999
9000 return estats;
9001}
9002
9003static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9004{
9005 struct tg3 *tp = netdev_priv(dev);
9006 struct net_device_stats *stats = &tp->net_stats;
9007 struct net_device_stats *old_stats = &tp->net_stats_prev;
9008 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9009
9010 if (!hw_stats)
9011 return old_stats;
9012
9013 stats->rx_packets = old_stats->rx_packets +
9014 get_stat64(&hw_stats->rx_ucast_packets) +
9015 get_stat64(&hw_stats->rx_mcast_packets) +
9016 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 9017
1da177e4
LT		 9018 stats->tx_packets = old_stats->tx_packets +
9019 get_stat64(&hw_stats->tx_ucast_packets) +
9020 get_stat64(&hw_stats->tx_mcast_packets) +
9021 get_stat64(&hw_stats->tx_bcast_packets);
9022
9023 stats->rx_bytes = old_stats->rx_bytes +
9024 get_stat64(&hw_stats->rx_octets);
9025 stats->tx_bytes = old_stats->tx_bytes +
9026 get_stat64(&hw_stats->tx_octets);
9027
9028 stats->rx_errors = old_stats->rx_errors +
4f63b877 9029 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 9030 stats->tx_errors = old_stats->tx_errors +
9031 get_stat64(&hw_stats->tx_errors) +
9032 get_stat64(&hw_stats->tx_mac_errors) +
9033 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9034 get_stat64(&hw_stats->tx_discards);
9035
9036 stats->multicast = old_stats->multicast +
9037 get_stat64(&hw_stats->rx_mcast_packets);
9038 stats->collisions = old_stats->collisions +
9039 get_stat64(&hw_stats->tx_collisions);
9040
9041 stats->rx_length_errors = old_stats->rx_length_errors +
9042 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9043 get_stat64(&hw_stats->rx_undersize_packets);
9044
9045 stats->rx_over_errors = old_stats->rx_over_errors +
9046 get_stat64(&hw_stats->rxbds_empty);
9047 stats->rx_frame_errors = old_stats->rx_frame_errors +
9048 get_stat64(&hw_stats->rx_align_errors);
9049 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9050 get_stat64(&hw_stats->tx_discards);
9051 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9052 get_stat64(&hw_stats->tx_carrier_sense_errors);
9053
9054 stats->rx_crc_errors = old_stats->rx_crc_errors +
9055 calc_crc_errors(tp);
9056
4f63b877
JL		 9057 stats->rx_missed_errors = old_stats->rx_missed_errors +
9058 get_stat64(&hw_stats->rx_discards);
9059
1da177e4
LT		 9060 return stats;
9061}
9062
9063static inline u32 calc_crc(unsigned char *buf, int len)
9064{
9065 u32 reg;
9066 u32 tmp;
9067 int j, k;
9068
9069 reg = 0xffffffff;
9070
9071 for (j = 0; j < len; j++) {
9072 reg ^= buf[j];
9073
9074 for (k = 0; k < 8; k++) {
9075 tmp = reg & 0x01;
9076
9077 reg >>= 1;
9078
9079 if (tmp) {
9080 reg ^= 0xedb88320;
9081 }
9082 }
9083 }
9084
9085 return ~reg;
9086}
9087
9088static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9089{
9090 /* accept or reject all multicast frames */
9091 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9092 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9093 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9094 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9095}
9096
9097static void __tg3_set_rx_mode(struct net_device *dev)
9098{
9099 struct tg3 *tp = netdev_priv(dev);
9100 u32 rx_mode;
9101
9102 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9103 RX_MODE_KEEP_VLAN_TAG);
9104
9105 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9106 * flag clear.
9107 */
9108#if TG3_VLAN_TAG_USED
9109 if (!tp->vlgrp &&
9110 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9111 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9112#else
9113 /* By definition, VLAN is disabled always in this
9114 * case.
9115 */
9116 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9117 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9118#endif
9119
9120 if (dev->flags & IFF_PROMISC) {
9121 /* Promiscuous mode. */
9122 rx_mode |= RX_MODE_PROMISC;
9123 } else if (dev->flags & IFF_ALLMULTI) {
9124 /* Accept all multicast. */
9125 tg3_set_multi (tp, 1);
9126 } else if (dev->mc_count < 1) {
9127 /* Reject all multicast. */
9128 tg3_set_multi (tp, 0);
9129 } else {
9130 /* Accept one or more multicast(s). */
9131 struct dev_mc_list *mclist;
9132 unsigned int i;
9133 u32 mc_filter[4] = { 0, };
9134 u32 regidx;
9135 u32 bit;
9136 u32 crc;
9137
9138 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9139 i++, mclist = mclist->next) {
9140
9141 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9142 bit = ~crc & 0x7f;
9143 regidx = (bit & 0x60) >> 5;
9144 bit &= 0x1f;
9145 mc_filter[regidx] |= (1 << bit);
9146 }
9147
9148 tw32(MAC_HASH_REG_0, mc_filter[0]);
9149 tw32(MAC_HASH_REG_1, mc_filter[1]);
9150 tw32(MAC_HASH_REG_2, mc_filter[2]);
9151 tw32(MAC_HASH_REG_3, mc_filter[3]);
9152 }
9153
9154 if (rx_mode != tp->rx_mode) {
9155 tp->rx_mode = rx_mode;
9156 tw32_f(MAC_RX_MODE, rx_mode);
9157 udelay(10);
9158 }
9159}
9160
9161static void tg3_set_rx_mode(struct net_device *dev)
9162{
9163 struct tg3 *tp = netdev_priv(dev);
9164
e75f7c90
MC		 9165 if (!netif_running(dev))
9166 return;
9167
f47c11ee 9168 tg3_full_lock(tp, 0);
1da177e4 9169 __tg3_set_rx_mode(dev);
f47c11ee 9170 tg3_full_unlock(tp);
1da177e4
LT		 9171}
9172
9173#define TG3_REGDUMP_LEN (32 * 1024)
9174
9175static int tg3_get_regs_len(struct net_device *dev)
9176{
9177 return TG3_REGDUMP_LEN;
9178}
9179
9180static void tg3_get_regs(struct net_device *dev,
9181 struct ethtool_regs *regs, void *_p)
9182{
9183 u32 *p = _p;
9184 struct tg3 *tp = netdev_priv(dev);
9185 u8 *orig_p = _p;
9186 int i;
9187
9188 regs->version = 0;
9189
9190 memset(p, 0, TG3_REGDUMP_LEN);
9191
bc1c7567
MC		 9192 if (tp->link_config.phy_is_low_power)
9193 return;
9194
f47c11ee 9195 tg3_full_lock(tp, 0);
1da177e4
LT		 9196
9197#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9198#define GET_REG32_LOOP(base,len) \
9199do { p = (u32 *)(orig_p + (base)); \
9200 for (i = 0; i < len; i += 4) \
9201 __GET_REG32((base) + i); \
9202} while (0)
9203#define GET_REG32_1(reg) \
9204do { p = (u32 *)(orig_p + (reg)); \
9205 __GET_REG32((reg)); \
9206} while (0)
9207
9208 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9209 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9210 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9211 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9212 GET_REG32_1(SNDDATAC_MODE);
9213 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9214 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9215 GET_REG32_1(SNDBDC_MODE);
9216 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9217 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9218 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9219 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9220 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9221 GET_REG32_1(RCVDCC_MODE);
9222 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9223 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9224 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9225 GET_REG32_1(MBFREE_MODE);
9226 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9227 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9228 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9229 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9230 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9231 GET_REG32_1(RX_CPU_MODE);
9232 GET_REG32_1(RX_CPU_STATE);
9233 GET_REG32_1(RX_CPU_PGMCTR);
9234 GET_REG32_1(RX_CPU_HWBKPT);
9235 GET_REG32_1(TX_CPU_MODE);
9236 GET_REG32_1(TX_CPU_STATE);
9237 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9238 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9239 GET_REG32_LOOP(FTQ_RESET, 0x120);
9240 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9241 GET_REG32_1(DMAC_MODE);
9242 GET_REG32_LOOP(GRC_MODE, 0x4c);
9243 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9244 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9245
9246#undef __GET_REG32
9247#undef GET_REG32_LOOP
9248#undef GET_REG32_1
9249
f47c11ee 9250 tg3_full_unlock(tp);
1da177e4
LT		 9251}
9252
9253static int tg3_get_eeprom_len(struct net_device *dev)
9254{
9255 struct tg3 *tp = netdev_priv(dev);
9256
9257 return tp->nvram_size;
9258}
9259
1da177e4
LT		 9260static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9261{
9262 struct tg3 *tp = netdev_priv(dev);
9263 int ret;
9264 u8 *pd;
b9fc7dc5 9265 u32 i, offset, len, b_offset, b_count;
a9dc529d 9266 __be32 val;
1da177e4 9267
df259d8c
MC		 9268 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9269 return -EINVAL;
9270
bc1c7567
MC		 9271 if (tp->link_config.phy_is_low_power)
9272 return -EAGAIN;
9273
1da177e4
LT		 9274 offset = eeprom->offset;
9275 len = eeprom->len;
9276 eeprom->len = 0;
9277
9278 eeprom->magic = TG3_EEPROM_MAGIC;
9279
9280 if (offset & 3) {
9281 /* adjustments to start on required 4 byte boundary */
9282 b_offset = offset & 3;
9283 b_count = 4 - b_offset;
9284 if (b_count > len) {
9285 /* i.e. offset=1 len=2 */
9286 b_count = len;
9287 }
a9dc529d 9288 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9289 if (ret)
9290 return ret;
1da177e4
LT		 9291 memcpy(data, ((char*)&val) + b_offset, b_count);
9292 len -= b_count;
9293 offset += b_count;
9294 eeprom->len += b_count;
9295 }
9296
9297 /* read bytes upto the last 4 byte boundary */
9298 pd = &data[eeprom->len];
9299 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9300 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9301 if (ret) {
9302 eeprom->len += i;
9303 return ret;
9304 }
1da177e4
LT		 9305 memcpy(pd + i, &val, 4);
9306 }
9307 eeprom->len += i;
9308
9309 if (len & 3) {
9310 /* read last bytes not ending on 4 byte boundary */
9311 pd = &data[eeprom->len];
9312 b_count = len & 3;
9313 b_offset = offset + len - b_count;
a9dc529d 9314 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9315 if (ret)
9316 return ret;
b9fc7dc5 9317 memcpy(pd, &val, b_count);
1da177e4
LT		 9318 eeprom->len += b_count;
9319 }
9320 return 0;
9321}
9322
6aa20a22 9323static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9324
9325static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9326{
9327 struct tg3 *tp = netdev_priv(dev);
9328 int ret;
b9fc7dc5 9329 u32 offset, len, b_offset, odd_len;
1da177e4 9330 u8 *buf;
a9dc529d 9331 __be32 start, end;
1da177e4 9332
bc1c7567
MC		 9333 if (tp->link_config.phy_is_low_power)
9334 return -EAGAIN;
9335
df259d8c
MC		 9336 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9337 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9338 return -EINVAL;
9339
9340 offset = eeprom->offset;
9341 len = eeprom->len;
9342
9343 if ((b_offset = (offset & 3))) {
9344 /* adjustments to start on required 4 byte boundary */
a9dc529d 9345 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9346 if (ret)
9347 return ret;
1da177e4
LT		 9348 len += b_offset;
9349 offset &= ~3;
1c8594b4
MC		 9350 if (len < 4)
9351 len = 4;
1da177e4
LT		 9352 }
9353
9354 odd_len = 0;
1c8594b4 9355 if (len & 3) {
1da177e4
LT		 9356 /* adjustments to end on required 4 byte boundary */
9357 odd_len = 1;
9358 len = (len + 3) & ~3;
a9dc529d 9359 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9360 if (ret)
9361 return ret;
1da177e4
LT		 9362 }
9363
9364 buf = data;
9365 if (b_offset || odd_len) {
9366 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9367 if (!buf)
1da177e4
LT		 9368 return -ENOMEM;
9369 if (b_offset)
9370 memcpy(buf, &start, 4);
9371 if (odd_len)
9372 memcpy(buf+len-4, &end, 4);
9373 memcpy(buf + b_offset, data, eeprom->len);
9374 }
9375
9376 ret = tg3_nvram_write_block(tp, offset, len, buf);
9377
9378 if (buf != data)
9379 kfree(buf);
9380
9381 return ret;
9382}
9383
9384static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9385{
b02fd9e3
MC		 9386 struct tg3 *tp = netdev_priv(dev);
9387
9388 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9389 struct phy_device *phydev;
b02fd9e3
MC		 9390 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9391 return -EAGAIN;
3f0e3ad7
MC		 9392 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9393 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9394 }
6aa20a22 9395
1da177e4
LT		 9396 cmd->supported = (SUPPORTED_Autoneg);
9397
9398 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9399 cmd->supported |= (SUPPORTED_1000baseT_Half |
9400 SUPPORTED_1000baseT_Full);
9401
ef348144 9402 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9403 cmd->supported |= (SUPPORTED_100baseT_Half |
9404 SUPPORTED_100baseT_Full |
9405 SUPPORTED_10baseT_Half |
9406 SUPPORTED_10baseT_Full |
3bebab59 9407 SUPPORTED_TP);
ef348144
KK		 9408 cmd->port = PORT_TP;
9409 } else {
1da177e4 9410 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9411 cmd->port = PORT_FIBRE;
9412 }
6aa20a22 9413
1da177e4
LT		 9414 cmd->advertising = tp->link_config.advertising;
9415 if (netif_running(dev)) {
9416 cmd->speed = tp->link_config.active_speed;
9417 cmd->duplex = tp->link_config.active_duplex;
9418 }
882e9793 9419 cmd->phy_address = tp->phy_addr;
7e5856bd 9420 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9421 cmd->autoneg = tp->link_config.autoneg;
9422 cmd->maxtxpkt = 0;
9423 cmd->maxrxpkt = 0;
9424 return 0;
9425}
6aa20a22 9426
1da177e4
LT		 9427static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9428{
9429 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9430
b02fd9e3 9431 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9432 struct phy_device *phydev;
b02fd9e3
MC		 9433 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9434 return -EAGAIN;
3f0e3ad7
MC		 9435 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9436 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9437 }
9438
7e5856bd
MC		 9439 if (cmd->autoneg != AUTONEG_ENABLE &&
9440 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9441 return -EINVAL;
7e5856bd
MC		 9442
9443 if (cmd->autoneg == AUTONEG_DISABLE &&
9444 cmd->duplex != DUPLEX_FULL &&
9445 cmd->duplex != DUPLEX_HALF)
37ff238d 9446 return -EINVAL;
1da177e4 9447
7e5856bd
MC		 9448 if (cmd->autoneg == AUTONEG_ENABLE) {
9449 u32 mask = ADVERTISED_Autoneg |
9450 ADVERTISED_Pause |
9451 ADVERTISED_Asym_Pause;
9452
9453 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9454 mask |= ADVERTISED_1000baseT_Half |
9455 ADVERTISED_1000baseT_Full;
9456
9457 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9458 mask |= ADVERTISED_100baseT_Half |
9459 ADVERTISED_100baseT_Full |
9460 ADVERTISED_10baseT_Half |
9461 ADVERTISED_10baseT_Full |
9462 ADVERTISED_TP;
9463 else
9464 mask |= ADVERTISED_FIBRE;
9465
9466 if (cmd->advertising & ~mask)
9467 return -EINVAL;
9468
9469 mask &= (ADVERTISED_1000baseT_Half |
9470 ADVERTISED_1000baseT_Full |
9471 ADVERTISED_100baseT_Half |
9472 ADVERTISED_100baseT_Full |
9473 ADVERTISED_10baseT_Half |
9474 ADVERTISED_10baseT_Full);
9475
9476 cmd->advertising &= mask;
9477 } else {
9478 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9479 if (cmd->speed != SPEED_1000)
9480 return -EINVAL;
9481
9482 if (cmd->duplex != DUPLEX_FULL)
9483 return -EINVAL;
9484 } else {
9485 if (cmd->speed != SPEED_100 &&
9486 cmd->speed != SPEED_10)
9487 return -EINVAL;
9488 }
9489 }
9490
f47c11ee 9491 tg3_full_lock(tp, 0);
1da177e4
LT		 9492
9493 tp->link_config.autoneg = cmd->autoneg;
9494 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9495 tp->link_config.advertising = (cmd->advertising |
9496 ADVERTISED_Autoneg);
1da177e4
LT		 9497 tp->link_config.speed = SPEED_INVALID;
9498 tp->link_config.duplex = DUPLEX_INVALID;
9499 } else {
9500 tp->link_config.advertising = 0;
9501 tp->link_config.speed = cmd->speed;
9502 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9503 }
6aa20a22 9504
24fcad6b
MC		 9505 tp->link_config.orig_speed = tp->link_config.speed;
9506 tp->link_config.orig_duplex = tp->link_config.duplex;
9507 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9508
1da177e4
LT		 9509 if (netif_running(dev))
9510 tg3_setup_phy(tp, 1);
9511
f47c11ee 9512 tg3_full_unlock(tp);
6aa20a22 9513
1da177e4
LT		 9514 return 0;
9515}
6aa20a22 9516
1da177e4
LT		 9517static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9518{
9519 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9520
1da177e4
LT		 9521 strcpy(info->driver, DRV_MODULE_NAME);
9522 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9523 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9524 strcpy(info->bus_info, pci_name(tp->pdev));
9525}
6aa20a22 9526
1da177e4
LT		 9527static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9528{
9529 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9530
12dac075
RW		 9531 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9532 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9533 wol->supported = WAKE_MAGIC;
9534 else
9535 wol->supported = 0;
1da177e4 9536 wol->wolopts = 0;
05ac4cb7
MC		 9537 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9538 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9539 wol->wolopts = WAKE_MAGIC;
9540 memset(&wol->sopass, 0, sizeof(wol->sopass));
9541}
6aa20a22 9542
1da177e4
LT		 9543static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9544{
9545 struct tg3 *tp = netdev_priv(dev);
12dac075 9546 struct device *dp = &tp->pdev->dev;
6aa20a22 9547
1da177e4
LT		 9548 if (wol->wolopts & ~WAKE_MAGIC)
9549 return -EINVAL;
9550 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9551 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9552 return -EINVAL;
6aa20a22 9553
f47c11ee 9554 spin_lock_bh(&tp->lock);
12dac075 9555 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9556 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9557 device_set_wakeup_enable(dp, true);
9558 } else {
1da177e4 9559 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9560 device_set_wakeup_enable(dp, false);
9561 }
f47c11ee 9562 spin_unlock_bh(&tp->lock);
6aa20a22 9563
1da177e4
LT		 9564 return 0;
9565}
6aa20a22 9566
1da177e4
LT		 9567static u32 tg3_get_msglevel(struct net_device *dev)
9568{
9569 struct tg3 *tp = netdev_priv(dev);
9570 return tp->msg_enable;
9571}
6aa20a22 9572
1da177e4
LT		 9573static void tg3_set_msglevel(struct net_device *dev, u32 value)
9574{
9575 struct tg3 *tp = netdev_priv(dev);
9576 tp->msg_enable = value;
9577}
6aa20a22 9578
1da177e4
LT		 9579static int tg3_set_tso(struct net_device *dev, u32 value)
9580{
9581 struct tg3 *tp = netdev_priv(dev);
9582
9583 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9584 if (value)
9585 return -EINVAL;
9586 return 0;
9587 }
027455ad 9588 if ((dev->features & NETIF_F_IPV6_CSUM) &&
e849cdc3
MC		 9589 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9590 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9936bcf6 9591 if (value) {
b0026624 9592 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 9593 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9594 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 9595 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9596 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9597 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 9598 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6
MC		 9599 dev->features |= NETIF_F_TSO_ECN;
9600 } else
9601 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9602 }
1da177e4
LT		 9603 return ethtool_op_set_tso(dev, value);
9604}
6aa20a22 9605
1da177e4
LT		 9606static int tg3_nway_reset(struct net_device *dev)
9607{
9608 struct tg3 *tp = netdev_priv(dev);
1da177e4 9609 int r;
6aa20a22 9610
1da177e4
LT		 9611 if (!netif_running(dev))
9612 return -EAGAIN;
9613
c94e3941
MC		 9614 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9615 return -EINVAL;
9616
b02fd9e3
MC		 9617 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9618 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9619 return -EAGAIN;
3f0e3ad7 9620 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9621 } else {
9622 u32 bmcr;
9623
9624 spin_lock_bh(&tp->lock);
9625 r = -EINVAL;
9626 tg3_readphy(tp, MII_BMCR, &bmcr);
9627 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9628 ((bmcr & BMCR_ANENABLE) ||
9629 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9630 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9631 BMCR_ANENABLE);
9632 r = 0;
9633 }
9634 spin_unlock_bh(&tp->lock);
1da177e4 9635 }
6aa20a22 9636
1da177e4
LT		 9637 return r;
9638}
6aa20a22 9639
1da177e4
LT		 9640static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9641{
9642 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9643
1da177e4
LT		 9644 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9645 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9646 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9647 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9648 else
9649 ering->rx_jumbo_max_pending = 0;
9650
9651 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9652
9653 ering->rx_pending = tp->rx_pending;
9654 ering->rx_mini_pending = 0;
4f81c32b
MC		 9655 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9656 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9657 else
9658 ering->rx_jumbo_pending = 0;
9659
f3f3f27e 9660 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9661}
6aa20a22 9662
1da177e4
LT		 9663static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9664{
9665 struct tg3 *tp = netdev_priv(dev);
646c9edd 9666 int i, irq_sync = 0, err = 0;
6aa20a22 9667
1da177e4
LT		 9668 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9669 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9670 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9671 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9672 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9673 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9674 return -EINVAL;
6aa20a22 9675
bbe832c0 9676 if (netif_running(dev)) {
b02fd9e3 9677 tg3_phy_stop(tp);
1da177e4 9678 tg3_netif_stop(tp);
bbe832c0
MC		 9679 irq_sync = 1;
9680 }
1da177e4 9681
bbe832c0 9682 tg3_full_lock(tp, irq_sync);
6aa20a22 9683
1da177e4
LT		 9684 tp->rx_pending = ering->rx_pending;
9685
9686 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9687 tp->rx_pending > 63)
9688 tp->rx_pending = 63;
9689 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9690
9691 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9692 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9693
9694 if (netif_running(dev)) {
944d980e 9695 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9696 err = tg3_restart_hw(tp, 1);
9697 if (!err)
9698 tg3_netif_start(tp);
1da177e4
LT		 9699 }
9700
f47c11ee 9701 tg3_full_unlock(tp);
6aa20a22 9702
b02fd9e3
MC		 9703 if (irq_sync && !err)
9704 tg3_phy_start(tp);
9705
b9ec6c1b 9706 return err;
1da177e4 9707}
6aa20a22 9708
1da177e4
LT		 9709static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9710{
9711 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9712
1da177e4 9713 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9714
e18ce346 9715 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9716 epause->rx_pause = 1;
9717 else
9718 epause->rx_pause = 0;
9719
e18ce346 9720 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9721 epause->tx_pause = 1;
9722 else
9723 epause->tx_pause = 0;
1da177e4 9724}
6aa20a22 9725
1da177e4
LT		 9726static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9727{
9728 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9729 int err = 0;
6aa20a22 9730
b02fd9e3
MC		 9731 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9732 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9733 return -EAGAIN;
1da177e4 9734
b02fd9e3
MC		 9735 if (epause->autoneg) {
9736 u32 newadv;
9737 struct phy_device *phydev;
f47c11ee 9738
3f0e3ad7 9739 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9740
b02fd9e3
MC		 9741 if (epause->rx_pause) {
9742 if (epause->tx_pause)
9743 newadv = ADVERTISED_Pause;
9744 else
9745 newadv = ADVERTISED_Pause |
9746 ADVERTISED_Asym_Pause;
9747 } else if (epause->tx_pause) {
9748 newadv = ADVERTISED_Asym_Pause;
9749 } else
9750 newadv = 0;
9751
9752 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9753 u32 oldadv = phydev->advertising &
9754 (ADVERTISED_Pause |
9755 ADVERTISED_Asym_Pause);
9756 if (oldadv != newadv) {
9757 phydev->advertising &=
9758 ~(ADVERTISED_Pause |
9759 ADVERTISED_Asym_Pause);
9760 phydev->advertising |= newadv;
9761 err = phy_start_aneg(phydev);
9762 }
9763 } else {
9764 tp->link_config.advertising &=
9765 ~(ADVERTISED_Pause |
9766 ADVERTISED_Asym_Pause);
9767 tp->link_config.advertising |= newadv;
9768 }
9769 } else {
9770 if (epause->rx_pause)
e18ce346 9771 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9772 else
e18ce346 9773 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9774
b02fd9e3 9775 if (epause->tx_pause)
e18ce346 9776 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9777 else
e18ce346 9778 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9779
9780 if (netif_running(dev))
9781 tg3_setup_flow_control(tp, 0, 0);
9782 }
9783 } else {
9784 int irq_sync = 0;
9785
9786 if (netif_running(dev)) {
9787 tg3_netif_stop(tp);
9788 irq_sync = 1;
9789 }
9790
9791 tg3_full_lock(tp, irq_sync);
9792
9793 if (epause->autoneg)
9794 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9795 else
9796 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9797 if (epause->rx_pause)
e18ce346 9798 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9799 else
e18ce346 9800 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9801 if (epause->tx_pause)
e18ce346 9802 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9803 else
e18ce346 9804 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9805
9806 if (netif_running(dev)) {
9807 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9808 err = tg3_restart_hw(tp, 1);
9809 if (!err)
9810 tg3_netif_start(tp);
9811 }
9812
9813 tg3_full_unlock(tp);
9814 }
6aa20a22 9815
b9ec6c1b 9816 return err;
1da177e4 9817}
6aa20a22 9818
1da177e4
LT		 9819static u32 tg3_get_rx_csum(struct net_device *dev)
9820{
9821 struct tg3 *tp = netdev_priv(dev);
9822 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9823}
6aa20a22 9824
1da177e4
LT		 9825static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9826{
9827 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9828
1da177e4
LT		 9829 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9830 if (data != 0)
9831 return -EINVAL;
9832 return 0;
9833 }
6aa20a22 9834
f47c11ee 9835 spin_lock_bh(&tp->lock);
1da177e4
LT		 9836 if (data)
9837 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9838 else
9839 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9840 spin_unlock_bh(&tp->lock);
6aa20a22 9841
1da177e4
LT		 9842 return 0;
9843}
6aa20a22 9844
1da177e4
LT		 9845static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9846{
9847 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9848
1da177e4
LT		 9849 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9850 if (data != 0)
9851 return -EINVAL;
9852 return 0;
9853 }
6aa20a22 9854
321d32a0 9855 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9856 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9857 else
9c27dbdf 9858 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9859
9860 return 0;
9861}
9862
b9f2c044 9863static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9864{
b9f2c044
JG		 9865 switch (sset) {
9866 case ETH_SS_TEST:
9867 return TG3_NUM_TEST;
9868 case ETH_SS_STATS:
9869 return TG3_NUM_STATS;
9870 default:
9871 return -EOPNOTSUPP;
9872 }
4cafd3f5
MC		 9873}
9874
1da177e4
LT		 9875static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9876{
9877 switch (stringset) {
9878 case ETH_SS_STATS:
9879 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9880 break;
4cafd3f5
MC		 9881 case ETH_SS_TEST:
9882 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9883 break;
1da177e4
LT		 9884 default:
9885 WARN_ON(1); /* we need a WARN() */
9886 break;
9887 }
9888}
9889
4009a93d
MC		 9890static int tg3_phys_id(struct net_device *dev, u32 data)
9891{
9892 struct tg3 *tp = netdev_priv(dev);
9893 int i;
9894
9895 if (!netif_running(tp->dev))
9896 return -EAGAIN;
9897
9898 if (data == 0)
759afc31 9899 data = UINT_MAX / 2;
4009a93d
MC		 9900
9901 for (i = 0; i < (data * 2); i++) {
9902 if ((i % 2) == 0)
9903 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9904 LED_CTRL_1000MBPS_ON |
9905 LED_CTRL_100MBPS_ON |
9906 LED_CTRL_10MBPS_ON |
9907 LED_CTRL_TRAFFIC_OVERRIDE |
9908 LED_CTRL_TRAFFIC_BLINK |
9909 LED_CTRL_TRAFFIC_LED);
6aa20a22 9910
4009a93d
MC		 9911 else
9912 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9913 LED_CTRL_TRAFFIC_OVERRIDE);
9914
9915 if (msleep_interruptible(500))
9916 break;
9917 }
9918 tw32(MAC_LED_CTRL, tp->led_ctrl);
9919 return 0;
9920}
9921
1da177e4
LT		 9922static void tg3_get_ethtool_stats (struct net_device *dev,
9923 struct ethtool_stats *estats, u64 *tmp_stats)
9924{
9925 struct tg3 *tp = netdev_priv(dev);
9926 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9927}
9928
566f86ad 9929#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9930#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9931#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9932#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9933#define NVRAM_SELFBOOT_HW_SIZE 0x20
9934#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9935
9936static int tg3_test_nvram(struct tg3 *tp)
9937{
b9fc7dc5 9938 u32 csum, magic;
a9dc529d 9939 __be32 *buf;
ab0049b4 9940 int i, j, k, err = 0, size;
566f86ad 9941
df259d8c
MC		 9942 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9943 return 0;
9944
e4f34110 9945 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9946 return -EIO;
9947
1b27777a
MC		 9948 if (magic == TG3_EEPROM_MAGIC)
9949 size = NVRAM_TEST_SIZE;
b16250e3 9950 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9951 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9952 TG3_EEPROM_SB_FORMAT_1) {
9953 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9954 case TG3_EEPROM_SB_REVISION_0:
9955 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9956 break;
9957 case TG3_EEPROM_SB_REVISION_2:
9958 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9959 break;
9960 case TG3_EEPROM_SB_REVISION_3:
9961 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9962 break;
9963 default:
9964 return 0;
9965 }
9966 } else
1b27777a 9967 return 0;
b16250e3
MC		 9968 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9969 size = NVRAM_SELFBOOT_HW_SIZE;
9970 else
1b27777a
MC		 9971 return -EIO;
9972
9973 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9974 if (buf == NULL)
9975 return -ENOMEM;
9976
1b27777a
MC		 9977 err = -EIO;
9978 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9979 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9980 if (err)
566f86ad 9981 break;
566f86ad 9982 }
1b27777a 9983 if (i < size)
566f86ad
MC		 9984 goto out;
9985
1b27777a 9986 /* Selfboot format */
a9dc529d 9987 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9988 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9989 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9990 u8 *buf8 = (u8 *) buf, csum8 = 0;
9991
b9fc7dc5 9992 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9993 TG3_EEPROM_SB_REVISION_2) {
9994 /* For rev 2, the csum doesn't include the MBA. */
9995 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9996 csum8 += buf8[i];
9997 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9998 csum8 += buf8[i];
9999 } else {
10000 for (i = 0; i < size; i++)
10001 csum8 += buf8[i];
10002 }
1b27777a 10003
ad96b485
AB		 10004 if (csum8 == 0) {
10005 err = 0;
10006 goto out;
10007 }
10008
10009 err = -EIO;
10010 goto out;
1b27777a 10011 }
566f86ad 10012
b9fc7dc5 10013 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 10014 TG3_EEPROM_MAGIC_HW) {
10015 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 10016 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 10017 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 10018
10019 /* Separate the parity bits and the data bytes. */
10020 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10021 if ((i == 0) || (i == 8)) {
10022 int l;
10023 u8 msk;
10024
10025 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10026 parity[k++] = buf8[i] & msk;
10027 i++;
10028 }
10029 else if (i == 16) {
10030 int l;
10031 u8 msk;
10032
10033 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10034 parity[k++] = buf8[i] & msk;
10035 i++;
10036
10037 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10038 parity[k++] = buf8[i] & msk;
10039 i++;
10040 }
10041 data[j++] = buf8[i];
10042 }
10043
10044 err = -EIO;
10045 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10046 u8 hw8 = hweight8(data[i]);
10047
10048 if ((hw8 & 0x1) && parity[i])
10049 goto out;
10050 else if (!(hw8 & 0x1) && !parity[i])
10051 goto out;
10052 }
10053 err = 0;
10054 goto out;
10055 }
10056
566f86ad
MC		 10057 /* Bootstrap checksum at offset 0x10 */
10058 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 10059 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 10060 goto out;
10061
10062 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10063 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 10064 if (csum != be32_to_cpu(buf[0xfc/4]))
10065 goto out;
566f86ad
MC		 10066
10067 err = 0;
10068
10069out:
10070 kfree(buf);
10071 return err;
10072}
10073
ca43007a
MC		 10074#define TG3_SERDES_TIMEOUT_SEC 2
10075#define TG3_COPPER_TIMEOUT_SEC 6
10076
10077static int tg3_test_link(struct tg3 *tp)
10078{
10079 int i, max;
10080
10081 if (!netif_running(tp->dev))
10082 return -ENODEV;
10083
4c987487 10084 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10085 max = TG3_SERDES_TIMEOUT_SEC;
10086 else
10087 max = TG3_COPPER_TIMEOUT_SEC;
10088
10089 for (i = 0; i < max; i++) {
10090 if (netif_carrier_ok(tp->dev))
10091 return 0;
10092
10093 if (msleep_interruptible(1000))
10094 break;
10095 }
10096
10097 return -EIO;
10098}
10099
a71116d1 10100/* Only test the commonly used registers */
30ca3e37 10101static int tg3_test_registers(struct tg3 *tp)
a71116d1 10102{
b16250e3 10103 int i, is_5705, is_5750;
a71116d1
MC		 10104 u32 offset, read_mask, write_mask, val, save_val, read_val;
10105 static struct {
10106 u16 offset;
10107 u16 flags;
10108#define TG3_FL_5705 0x1
10109#define TG3_FL_NOT_5705 0x2
10110#define TG3_FL_NOT_5788 0x4
b16250e3 10111#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10112 u32 read_mask;
10113 u32 write_mask;
10114 } reg_tbl[] = {
10115 /* MAC Control Registers */
10116 { MAC_MODE, TG3_FL_NOT_5705,
10117 0x00000000, 0x00ef6f8c },
10118 { MAC_MODE, TG3_FL_5705,
10119 0x00000000, 0x01ef6b8c },
10120 { MAC_STATUS, TG3_FL_NOT_5705,
10121 0x03800107, 0x00000000 },
10122 { MAC_STATUS, TG3_FL_5705,
10123 0x03800100, 0x00000000 },
10124 { MAC_ADDR_0_HIGH, 0x0000,
10125 0x00000000, 0x0000ffff },
10126 { MAC_ADDR_0_LOW, 0x0000,
10127 0x00000000, 0xffffffff },
10128 { MAC_RX_MTU_SIZE, 0x0000,
10129 0x00000000, 0x0000ffff },
10130 { MAC_TX_MODE, 0x0000,
10131 0x00000000, 0x00000070 },
10132 { MAC_TX_LENGTHS, 0x0000,
10133 0x00000000, 0x00003fff },
10134 { MAC_RX_MODE, TG3_FL_NOT_5705,
10135 0x00000000, 0x000007fc },
10136 { MAC_RX_MODE, TG3_FL_5705,
10137 0x00000000, 0x000007dc },
10138 { MAC_HASH_REG_0, 0x0000,
10139 0x00000000, 0xffffffff },
10140 { MAC_HASH_REG_1, 0x0000,
10141 0x00000000, 0xffffffff },
10142 { MAC_HASH_REG_2, 0x0000,
10143 0x00000000, 0xffffffff },
10144 { MAC_HASH_REG_3, 0x0000,
10145 0x00000000, 0xffffffff },
10146
10147 /* Receive Data and Receive BD Initiator Control Registers. */
10148 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10149 0x00000000, 0xffffffff },
10150 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10151 0x00000000, 0xffffffff },
10152 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10153 0x00000000, 0x00000003 },
10154 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10155 0x00000000, 0xffffffff },
10156 { RCVDBDI_STD_BD+0, 0x0000,
10157 0x00000000, 0xffffffff },
10158 { RCVDBDI_STD_BD+4, 0x0000,
10159 0x00000000, 0xffffffff },
10160 { RCVDBDI_STD_BD+8, 0x0000,
10161 0x00000000, 0xffff0002 },
10162 { RCVDBDI_STD_BD+0xc, 0x0000,
10163 0x00000000, 0xffffffff },
6aa20a22 10164
a71116d1
MC		 10165 /* Receive BD Initiator Control Registers. */
10166 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10167 0x00000000, 0xffffffff },
10168 { RCVBDI_STD_THRESH, TG3_FL_5705,
10169 0x00000000, 0x000003ff },
10170 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10171 0x00000000, 0xffffffff },
6aa20a22 10172
a71116d1
MC		 10173 /* Host Coalescing Control Registers. */
10174 { HOSTCC_MODE, TG3_FL_NOT_5705,
10175 0x00000000, 0x00000004 },
10176 { HOSTCC_MODE, TG3_FL_5705,
10177 0x00000000, 0x000000f6 },
10178 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10179 0x00000000, 0xffffffff },
10180 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10181 0x00000000, 0x000003ff },
10182 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10183 0x00000000, 0xffffffff },
10184 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10185 0x00000000, 0x000003ff },
10186 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10187 0x00000000, 0xffffffff },
10188 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10189 0x00000000, 0x000000ff },
10190 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10191 0x00000000, 0xffffffff },
10192 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10193 0x00000000, 0x000000ff },
10194 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10195 0x00000000, 0xffffffff },
10196 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10197 0x00000000, 0xffffffff },
10198 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10199 0x00000000, 0xffffffff },
10200 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10201 0x00000000, 0x000000ff },
10202 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10203 0x00000000, 0xffffffff },
10204 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10205 0x00000000, 0x000000ff },
10206 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10207 0x00000000, 0xffffffff },
10208 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10209 0x00000000, 0xffffffff },
10210 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10211 0x00000000, 0xffffffff },
10212 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10213 0x00000000, 0xffffffff },
10214 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10215 0x00000000, 0xffffffff },
10216 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10217 0xffffffff, 0x00000000 },
10218 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10219 0xffffffff, 0x00000000 },
10220
10221 /* Buffer Manager Control Registers. */
b16250e3 10222 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10223 0x00000000, 0x007fff80 },
b16250e3 10224 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10225 0x00000000, 0x007fffff },
10226 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10227 0x00000000, 0x0000003f },
10228 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10229 0x00000000, 0x000001ff },
10230 { BUFMGR_MB_HIGH_WATER, 0x0000,
10231 0x00000000, 0x000001ff },
10232 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10233 0xffffffff, 0x00000000 },
10234 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10235 0xffffffff, 0x00000000 },
6aa20a22 10236
a71116d1
MC		 10237 /* Mailbox Registers */
10238 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10239 0x00000000, 0x000001ff },
10240 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10241 0x00000000, 0x000001ff },
10242 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10243 0x00000000, 0x000007ff },
10244 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10245 0x00000000, 0x000001ff },
10246
10247 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10248 };
10249
b16250e3
MC		 10250 is_5705 = is_5750 = 0;
10251 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10252 is_5705 = 1;
b16250e3
MC		 10253 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10254 is_5750 = 1;
10255 }
a71116d1
MC		 10256
10257 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10258 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10259 continue;
10260
10261 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10262 continue;
10263
10264 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10265 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10266 continue;
10267
b16250e3
MC		 10268 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10269 continue;
10270
a71116d1
MC		 10271 offset = (u32) reg_tbl[i].offset;
10272 read_mask = reg_tbl[i].read_mask;
10273 write_mask = reg_tbl[i].write_mask;
10274
10275 /* Save the original register content */
10276 save_val = tr32(offset);
10277
10278 /* Determine the read-only value. */
10279 read_val = save_val & read_mask;
10280
10281 /* Write zero to the register, then make sure the read-only bits
10282 * are not changed and the read/write bits are all zeros.
10283 */
10284 tw32(offset, 0);
10285
10286 val = tr32(offset);
10287
10288 /* Test the read-only and read/write bits. */
10289 if (((val & read_mask) != read_val) || (val & write_mask))
10290 goto out;
10291
10292 /* Write ones to all the bits defined by RdMask and WrMask, then
10293 * make sure the read-only bits are not changed and the
10294 * read/write bits are all ones.
10295 */
10296 tw32(offset, read_mask | write_mask);
10297
10298 val = tr32(offset);
10299
10300 /* Test the read-only bits. */
10301 if ((val & read_mask) != read_val)
10302 goto out;
10303
10304 /* Test the read/write bits. */
10305 if ((val & write_mask) != write_mask)
10306 goto out;
10307
10308 tw32(offset, save_val);
10309 }
10310
10311 return 0;
10312
10313out:
9f88f29f
MC		 10314 if (netif_msg_hw(tp))
10315 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10316 offset);
a71116d1
MC		 10317 tw32(offset, save_val);
10318 return -EIO;
10319}
10320
7942e1db
MC		 10321static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10322{
f71e1309 10323 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10324 int i;
10325 u32 j;
10326
e9edda69 10327 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10328 for (j = 0; j < len; j += 4) {
10329 u32 val;
10330
10331 tg3_write_mem(tp, offset + j, test_pattern[i]);
10332 tg3_read_mem(tp, offset + j, &val);
10333 if (val != test_pattern[i])
10334 return -EIO;
10335 }
10336 }
10337 return 0;
10338}
10339
10340static int tg3_test_memory(struct tg3 *tp)
10341{
10342 static struct mem_entry {
10343 u32 offset;
10344 u32 len;
10345 } mem_tbl_570x[] = {
38690194 10346 { 0x00000000, 0x00b50},
7942e1db
MC		 10347 { 0x00002000, 0x1c000},
10348 { 0xffffffff, 0x00000}
10349 }, mem_tbl_5705[] = {
10350 { 0x00000100, 0x0000c},
10351 { 0x00000200, 0x00008},
7942e1db
MC		 10352 { 0x00004000, 0x00800},
10353 { 0x00006000, 0x01000},
10354 { 0x00008000, 0x02000},
10355 { 0x00010000, 0x0e000},
10356 { 0xffffffff, 0x00000}
79f4d13a
MC		 10357 }, mem_tbl_5755[] = {
10358 { 0x00000200, 0x00008},
10359 { 0x00004000, 0x00800},
10360 { 0x00006000, 0x00800},
10361 { 0x00008000, 0x02000},
10362 { 0x00010000, 0x0c000},
10363 { 0xffffffff, 0x00000}
b16250e3
MC		 10364 }, mem_tbl_5906[] = {
10365 { 0x00000200, 0x00008},
10366 { 0x00004000, 0x00400},
10367 { 0x00006000, 0x00400},
10368 { 0x00008000, 0x01000},
10369 { 0x00010000, 0x01000},
10370 { 0xffffffff, 0x00000}
7942e1db
MC		 10371 };
10372 struct mem_entry *mem_tbl;
10373 int err = 0;
10374 int i;
10375
321d32a0
MC		 10376 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10377 mem_tbl = mem_tbl_5755;
10378 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10379 mem_tbl = mem_tbl_5906;
10380 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10381 mem_tbl = mem_tbl_5705;
10382 else
7942e1db
MC		 10383 mem_tbl = mem_tbl_570x;
10384
10385 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10386 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10387 mem_tbl[i].len)) != 0)
10388 break;
10389 }
6aa20a22 10390
7942e1db
MC		 10391 return err;
10392}
10393
9f40dead
MC		 10394#define TG3_MAC_LOOPBACK 0
10395#define TG3_PHY_LOOPBACK 1
10396
10397static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10398{
9f40dead 10399 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10400 u32 desc_idx, coal_now;
c76949a6
MC		 10401 struct sk_buff *skb, *rx_skb;
10402 u8 *tx_data;
10403 dma_addr_t map;
10404 int num_pkts, tx_len, rx_len, i, err;
10405 struct tg3_rx_buffer_desc *desc;
898a56f8 10406 struct tg3_napi *tnapi, *rnapi;
21f581a5 10407 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10408
0c1d0e2b
MC		 10409 if (tp->irq_cnt > 1) {
10410 tnapi = &tp->napi[1];
10411 rnapi = &tp->napi[1];
10412 } else {
10413 tnapi = &tp->napi[0];
10414 rnapi = &tp->napi[0];
10415 }
fd2ce37f 10416 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10417
9f40dead 10418 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10419 /* HW errata - mac loopback fails in some cases on 5780.
10420 * Normal traffic and PHY loopback are not affected by
10421 * errata.
10422 */
10423 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10424 return 0;
10425
9f40dead 10426 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10427 MAC_MODE_PORT_INT_LPBACK;
10428 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10429 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10430 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10431 mac_mode |= MAC_MODE_PORT_MODE_MII;
10432 else
10433 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10434 tw32(MAC_MODE, mac_mode);
10435 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10436 u32 val;
10437
7f97a4bd
MC		 10438 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10439 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10440 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10441 } else
10442 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10443
9ef8ca99
MC		 10444 tg3_phy_toggle_automdix(tp, 0);
10445
3f7045c1 10446 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10447 udelay(40);
5d64ad34 10448
e8f3f6ca 10449 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10450 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10452 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10453 mac_mode |= MAC_MODE_PORT_MODE_MII;
10454 } else
10455 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10456
c94e3941
MC		 10457 /* reset to prevent losing 1st rx packet intermittently */
10458 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10459 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10460 udelay(10);
10461 tw32_f(MAC_RX_MODE, tp->rx_mode);
10462 }
e8f3f6ca
MC		 10463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10464 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10465 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10466 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10467 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10468 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10469 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10470 }
9f40dead 10471 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10472 }
10473 else
10474 return -EINVAL;
c76949a6
MC		 10475
10476 err = -EIO;
10477
c76949a6 10478 tx_len = 1514;
a20e9c62 10479 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10480 if (!skb)
10481 return -ENOMEM;
10482
c76949a6
MC		 10483 tx_data = skb_put(skb, tx_len);
10484 memcpy(tx_data, tp->dev->dev_addr, 6);
10485 memset(tx_data + 6, 0x0, 8);
10486
10487 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10488
10489 for (i = 14; i < tx_len; i++)
10490 tx_data[i] = (u8) (i & 0xff);
10491
a21771dd
MC		 10492 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10493 dev_kfree_skb(skb);
10494 return -EIO;
10495 }
c76949a6
MC		 10496
10497 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10498 rnapi->coal_now);
c76949a6
MC		 10499
10500 udelay(10);
10501
898a56f8 10502 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10503
c76949a6
MC		 10504 num_pkts = 0;
10505
a21771dd
MC		 10506 tg3_set_txd(tnapi, tnapi->tx_prod,
10507 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
c76949a6 10508
f3f3f27e 10509 tnapi->tx_prod++;
c76949a6
MC		 10510 num_pkts++;
10511
f3f3f27e
MC		 10512 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10513 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10514
10515 udelay(10);
10516
303fc921
MC		 10517 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10518 for (i = 0; i < 35; i++) {
c76949a6 10519 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10520 coal_now);
c76949a6
MC		 10521
10522 udelay(10);
10523
898a56f8
MC		 10524 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10525 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10526 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10527 (rx_idx == (rx_start_idx + num_pkts)))
10528 break;
10529 }
10530
a21771dd 10531 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
c76949a6
MC		 10532 dev_kfree_skb(skb);
10533
f3f3f27e 10534 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10535 goto out;
10536
10537 if (rx_idx != rx_start_idx + num_pkts)
10538 goto out;
10539
72334482 10540 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10541 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10542 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10543 if (opaque_key != RXD_OPAQUE_RING_STD)
10544 goto out;
10545
10546 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10547 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10548 goto out;
10549
10550 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10551 if (rx_len != tx_len)
10552 goto out;
10553
21f581a5 10554 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10555
21f581a5 10556 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10557 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10558
10559 for (i = 14; i < tx_len; i++) {
10560 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10561 goto out;
10562 }
10563 err = 0;
6aa20a22 10564
c76949a6
MC		 10565 /* tg3_free_rings will unmap and free the rx_skb */
10566out:
10567 return err;
10568}
10569
9f40dead
MC		 10570#define TG3_MAC_LOOPBACK_FAILED 1
10571#define TG3_PHY_LOOPBACK_FAILED 2
10572#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10573 TG3_PHY_LOOPBACK_FAILED)
10574
10575static int tg3_test_loopback(struct tg3 *tp)
10576{
10577 int err = 0;
9936bcf6 10578 u32 cpmuctrl = 0;
9f40dead
MC		 10579
10580 if (!netif_running(tp->dev))
10581 return TG3_LOOPBACK_FAILED;
10582
b9ec6c1b
MC		 10583 err = tg3_reset_hw(tp, 1);
10584 if (err)
10585 return TG3_LOOPBACK_FAILED;
9f40dead 10586
6833c043
MC		 10587 /* Turn off gphy autopowerdown. */
10588 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10589 tg3_phy_toggle_apd(tp, false);
10590
321d32a0 10591 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10592 int i;
10593 u32 status;
10594
10595 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10596
10597 /* Wait for up to 40 microseconds to acquire lock. */
10598 for (i = 0; i < 4; i++) {
10599 status = tr32(TG3_CPMU_MUTEX_GNT);
10600 if (status == CPMU_MUTEX_GNT_DRIVER)
10601 break;
10602 udelay(10);
10603 }
10604
10605 if (status != CPMU_MUTEX_GNT_DRIVER)
10606 return TG3_LOOPBACK_FAILED;
10607
b2a5c19c 10608 /* Turn off link-based power management. */
e875093c 10609 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10610 tw32(TG3_CPMU_CTRL,
10611 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10612 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10613 }
10614
9f40dead
MC		 10615 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10616 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10617
321d32a0 10618 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10619 tw32(TG3_CPMU_CTRL, cpmuctrl);
10620
10621 /* Release the mutex */
10622 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10623 }
10624
dd477003
MC		 10625 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10626 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10627 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10628 err |= TG3_PHY_LOOPBACK_FAILED;
10629 }
10630
6833c043
MC		 10631 /* Re-enable gphy autopowerdown. */
10632 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10633 tg3_phy_toggle_apd(tp, true);
10634
9f40dead
MC		 10635 return err;
10636}
10637
4cafd3f5
MC		 10638static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10639 u64 *data)
10640{
566f86ad
MC		 10641 struct tg3 *tp = netdev_priv(dev);
10642
bc1c7567
MC		 10643 if (tp->link_config.phy_is_low_power)
10644 tg3_set_power_state(tp, PCI_D0);
10645
566f86ad
MC		 10646 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10647
10648 if (tg3_test_nvram(tp) != 0) {
10649 etest->flags |= ETH_TEST_FL_FAILED;
10650 data[0] = 1;
10651 }
ca43007a
MC		 10652 if (tg3_test_link(tp) != 0) {
10653 etest->flags |= ETH_TEST_FL_FAILED;
10654 data[1] = 1;
10655 }
a71116d1 10656 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10657 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10658
10659 if (netif_running(dev)) {
b02fd9e3 10660 tg3_phy_stop(tp);
a71116d1 10661 tg3_netif_stop(tp);
bbe832c0
MC		 10662 irq_sync = 1;
10663 }
a71116d1 10664
bbe832c0 10665 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10666
10667 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10668 err = tg3_nvram_lock(tp);
a71116d1
MC		 10669 tg3_halt_cpu(tp, RX_CPU_BASE);
10670 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10671 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10672 if (!err)
10673 tg3_nvram_unlock(tp);
a71116d1 10674
d9ab5ad1
MC		 10675 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10676 tg3_phy_reset(tp);
10677
a71116d1
MC		 10678 if (tg3_test_registers(tp) != 0) {
10679 etest->flags |= ETH_TEST_FL_FAILED;
10680 data[2] = 1;
10681 }
7942e1db
MC		 10682 if (tg3_test_memory(tp) != 0) {
10683 etest->flags |= ETH_TEST_FL_FAILED;
10684 data[3] = 1;
10685 }
9f40dead 10686 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10687 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10688
f47c11ee
DM		 10689 tg3_full_unlock(tp);
10690
d4bc3927
MC		 10691 if (tg3_test_interrupt(tp) != 0) {
10692 etest->flags |= ETH_TEST_FL_FAILED;
10693 data[5] = 1;
10694 }
f47c11ee
DM		 10695
10696 tg3_full_lock(tp, 0);
d4bc3927 10697
a71116d1
MC		 10698 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10699 if (netif_running(dev)) {
10700 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10701 err2 = tg3_restart_hw(tp, 1);
10702 if (!err2)
b9ec6c1b 10703 tg3_netif_start(tp);
a71116d1 10704 }
f47c11ee
DM		 10705
10706 tg3_full_unlock(tp);
b02fd9e3
MC		 10707
10708 if (irq_sync && !err2)
10709 tg3_phy_start(tp);
a71116d1 10710 }
bc1c7567
MC		 10711 if (tp->link_config.phy_is_low_power)
10712 tg3_set_power_state(tp, PCI_D3hot);
10713
4cafd3f5
MC		 10714}
10715
1da177e4
LT		 10716static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10717{
10718 struct mii_ioctl_data *data = if_mii(ifr);
10719 struct tg3 *tp = netdev_priv(dev);
10720 int err;
10721
b02fd9e3 10722 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10723 struct phy_device *phydev;
b02fd9e3
MC		 10724 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10725 return -EAGAIN;
3f0e3ad7
MC		 10726 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10727 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10728 }
10729
1da177e4
LT		 10730 switch(cmd) {
10731 case SIOCGMIIPHY:
882e9793 10732 data->phy_id = tp->phy_addr;
1da177e4
LT		 10733
10734 /* fallthru */
10735 case SIOCGMIIREG: {
10736 u32 mii_regval;
10737
10738 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10739 break; /* We have no PHY */
10740
bc1c7567
MC		 10741 if (tp->link_config.phy_is_low_power)
10742 return -EAGAIN;
10743
f47c11ee 10744 spin_lock_bh(&tp->lock);
1da177e4 10745 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10746 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10747
10748 data->val_out = mii_regval;
10749
10750 return err;
10751 }
10752
10753 case SIOCSMIIREG:
10754 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10755 break; /* We have no PHY */
10756
bc1c7567
MC		 10757 if (tp->link_config.phy_is_low_power)
10758 return -EAGAIN;
10759
f47c11ee 10760 spin_lock_bh(&tp->lock);
1da177e4 10761 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10762 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10763
10764 return err;
10765
10766 default:
10767 /* do nothing */
10768 break;
10769 }
10770 return -EOPNOTSUPP;
10771}
10772
10773#if TG3_VLAN_TAG_USED
10774static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10775{
10776 struct tg3 *tp = netdev_priv(dev);
10777
844b3eed
MC		 10778 if (!netif_running(dev)) {
10779 tp->vlgrp = grp;
10780 return;
10781 }
10782
10783 tg3_netif_stop(tp);
29315e87 10784
f47c11ee 10785 tg3_full_lock(tp, 0);
1da177e4
LT		 10786
10787 tp->vlgrp = grp;
10788
10789 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10790 __tg3_set_rx_mode(dev);
10791
844b3eed 10792 tg3_netif_start(tp);
46966545
MC		 10793
10794 tg3_full_unlock(tp);
1da177e4 10795}
1da177e4
LT		 10796#endif
10797
15f9850d
DM		 10798static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10799{
10800 struct tg3 *tp = netdev_priv(dev);
10801
10802 memcpy(ec, &tp->coal, sizeof(*ec));
10803 return 0;
10804}
10805
d244c892
MC		 10806static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10807{
10808 struct tg3 *tp = netdev_priv(dev);
10809 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10810 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10811
10812 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10813 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10814 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10815 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10816 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10817 }
10818
10819 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10820 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10821 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10822 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10823 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10824 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10825 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10826 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10827 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10828 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10829 return -EINVAL;
10830
10831 /* No rx interrupts will be generated if both are zero */
10832 if ((ec->rx_coalesce_usecs == 0) &&
10833 (ec->rx_max_coalesced_frames == 0))
10834 return -EINVAL;
10835
10836 /* No tx interrupts will be generated if both are zero */
10837 if ((ec->tx_coalesce_usecs == 0) &&
10838 (ec->tx_max_coalesced_frames == 0))
10839 return -EINVAL;
10840
10841 /* Only copy relevant parameters, ignore all others. */
10842 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10843 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10844 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10845 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10846 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10847 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10848 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10849 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10850 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10851
10852 if (netif_running(dev)) {
10853 tg3_full_lock(tp, 0);
10854 __tg3_set_coalesce(tp, &tp->coal);
10855 tg3_full_unlock(tp);
10856 }
10857 return 0;
10858}
10859
7282d491 10860static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10861 .get_settings = tg3_get_settings,
10862 .set_settings = tg3_set_settings,
10863 .get_drvinfo = tg3_get_drvinfo,
10864 .get_regs_len = tg3_get_regs_len,
10865 .get_regs = tg3_get_regs,
10866 .get_wol = tg3_get_wol,
10867 .set_wol = tg3_set_wol,
10868 .get_msglevel = tg3_get_msglevel,
10869 .set_msglevel = tg3_set_msglevel,
10870 .nway_reset = tg3_nway_reset,
10871 .get_link = ethtool_op_get_link,
10872 .get_eeprom_len = tg3_get_eeprom_len,
10873 .get_eeprom = tg3_get_eeprom,
10874 .set_eeprom = tg3_set_eeprom,
10875 .get_ringparam = tg3_get_ringparam,
10876 .set_ringparam = tg3_set_ringparam,
10877 .get_pauseparam = tg3_get_pauseparam,
10878 .set_pauseparam = tg3_set_pauseparam,
10879 .get_rx_csum = tg3_get_rx_csum,
10880 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10881 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10882 .set_sg = ethtool_op_set_sg,
1da177e4 10883 .set_tso = tg3_set_tso,
4cafd3f5 10884 .self_test = tg3_self_test,
1da177e4 10885 .get_strings = tg3_get_strings,
4009a93d 10886 .phys_id = tg3_phys_id,
1da177e4 10887 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10888 .get_coalesce = tg3_get_coalesce,
d244c892 10889 .set_coalesce = tg3_set_coalesce,
b9f2c044 10890 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10891};
10892
10893static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10894{
1b27777a 10895 u32 cursize, val, magic;
1da177e4
LT		 10896
10897 tp->nvram_size = EEPROM_CHIP_SIZE;
10898
e4f34110 10899 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10900 return;
10901
b16250e3
MC		 10902 if ((magic != TG3_EEPROM_MAGIC) &&
10903 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10904 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10905 return;
10906
10907 /*
10908 * Size the chip by reading offsets at increasing powers of two.
10909 * When we encounter our validation signature, we know the addressing
10910 * has wrapped around, and thus have our chip size.
10911 */
1b27777a 10912 cursize = 0x10;
1da177e4
LT		 10913
10914 while (cursize < tp->nvram_size) {
e4f34110 10915 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10916 return;
10917
1820180b 10918 if (val == magic)
1da177e4
LT		 10919 break;
10920
10921 cursize <<= 1;
10922 }
10923
10924 tp->nvram_size = cursize;
10925}
6aa20a22 10926
1da177e4
LT		 10927static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10928{
10929 u32 val;
10930
df259d8c
MC		 10931 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10932 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10933 return;
10934
10935 /* Selfboot format */
1820180b 10936 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10937 tg3_get_eeprom_size(tp);
10938 return;
10939 }
10940
6d348f2c 10941 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10942 if (val != 0) {
6d348f2c
MC		 10943 /* This is confusing. We want to operate on the
10944 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10945 * call will read from NVRAM and byteswap the data
10946 * according to the byteswapping settings for all
10947 * other register accesses. This ensures the data we
10948 * want will always reside in the lower 16-bits.
10949 * However, the data in NVRAM is in LE format, which
10950 * means the data from the NVRAM read will always be
10951 * opposite the endianness of the CPU. The 16-bit
10952 * byteswap then brings the data to CPU endianness.
10953 */
10954 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10955 return;
10956 }
10957 }
fd1122a2 10958 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10959}
10960
10961static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10962{
10963 u32 nvcfg1;
10964
10965 nvcfg1 = tr32(NVRAM_CFG1);
10966 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10967 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10968 } else {
1da177e4
LT		 10969 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10970 tw32(NVRAM_CFG1, nvcfg1);
10971 }
10972
4c987487 10973 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10974 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10975 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10976 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10977 tp->nvram_jedecnum = JEDEC_ATMEL;
10978 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10979 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10980 break;
10981 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10982 tp->nvram_jedecnum = JEDEC_ATMEL;
10983 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10984 break;
10985 case FLASH_VENDOR_ATMEL_EEPROM:
10986 tp->nvram_jedecnum = JEDEC_ATMEL;
10987 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10988 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10989 break;
10990 case FLASH_VENDOR_ST:
10991 tp->nvram_jedecnum = JEDEC_ST;
10992 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10993 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10994 break;
10995 case FLASH_VENDOR_SAIFUN:
10996 tp->nvram_jedecnum = JEDEC_SAIFUN;
10997 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10998 break;
10999 case FLASH_VENDOR_SST_SMALL:
11000 case FLASH_VENDOR_SST_LARGE:
11001 tp->nvram_jedecnum = JEDEC_SST;
11002 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11003 break;
1da177e4 11004 }
8590a603 11005 } else {
1da177e4
LT		 11006 tp->nvram_jedecnum = JEDEC_ATMEL;
11007 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11008 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11009 }
11010}
11011
a1b950d5
MC		 11012static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11013{
11014 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11015 case FLASH_5752PAGE_SIZE_256:
11016 tp->nvram_pagesize = 256;
11017 break;
11018 case FLASH_5752PAGE_SIZE_512:
11019 tp->nvram_pagesize = 512;
11020 break;
11021 case FLASH_5752PAGE_SIZE_1K:
11022 tp->nvram_pagesize = 1024;
11023 break;
11024 case FLASH_5752PAGE_SIZE_2K:
11025 tp->nvram_pagesize = 2048;
11026 break;
11027 case FLASH_5752PAGE_SIZE_4K:
11028 tp->nvram_pagesize = 4096;
11029 break;
11030 case FLASH_5752PAGE_SIZE_264:
11031 tp->nvram_pagesize = 264;
11032 break;
11033 case FLASH_5752PAGE_SIZE_528:
11034 tp->nvram_pagesize = 528;
11035 break;
11036 }
11037}
11038
361b4ac2
MC		 11039static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11040{
11041 u32 nvcfg1;
11042
11043 nvcfg1 = tr32(NVRAM_CFG1);
11044
e6af301b
MC		 11045 /* NVRAM protection for TPM */
11046 if (nvcfg1 & (1 << 27))
f66a29b0 11047 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
e6af301b 11048
361b4ac2 11049 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11050 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11051 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11052 tp->nvram_jedecnum = JEDEC_ATMEL;
11053 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11054 break;
11055 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11056 tp->nvram_jedecnum = JEDEC_ATMEL;
11057 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11058 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11059 break;
11060 case FLASH_5752VENDOR_ST_M45PE10:
11061 case FLASH_5752VENDOR_ST_M45PE20:
11062 case FLASH_5752VENDOR_ST_M45PE40:
11063 tp->nvram_jedecnum = JEDEC_ST;
11064 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11065 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11066 break;
361b4ac2
MC		 11067 }
11068
11069 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 11070 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 11071 } else {
361b4ac2
MC		 11072 /* For eeprom, set pagesize to maximum eeprom size */
11073 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11074
11075 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11076 tw32(NVRAM_CFG1, nvcfg1);
11077 }
11078}
11079
d3c7b886
MC		 11080static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11081{
989a9d23 11082 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11083
11084 nvcfg1 = tr32(NVRAM_CFG1);
11085
11086 /* NVRAM protection for TPM */
989a9d23 11087 if (nvcfg1 & (1 << 27)) {
f66a29b0 11088 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
989a9d23
MC		 11089 protect = 1;
11090 }
d3c7b886 11091
989a9d23
MC		 11092 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11093 switch (nvcfg1) {
8590a603
MC		 11094 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11095 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11096 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11097 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11098 tp->nvram_jedecnum = JEDEC_ATMEL;
11099 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11100 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11101 tp->nvram_pagesize = 264;
11102 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11103 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11104 tp->nvram_size = (protect ? 0x3e200 :
11105 TG3_NVRAM_SIZE_512KB);
11106 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11107 tp->nvram_size = (protect ? 0x1f200 :
11108 TG3_NVRAM_SIZE_256KB);
11109 else
11110 tp->nvram_size = (protect ? 0x1f200 :
11111 TG3_NVRAM_SIZE_128KB);
11112 break;
11113 case FLASH_5752VENDOR_ST_M45PE10:
11114 case FLASH_5752VENDOR_ST_M45PE20:
11115 case FLASH_5752VENDOR_ST_M45PE40:
11116 tp->nvram_jedecnum = JEDEC_ST;
11117 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11118 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11119 tp->nvram_pagesize = 256;
11120 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11121 tp->nvram_size = (protect ?
11122 TG3_NVRAM_SIZE_64KB :
11123 TG3_NVRAM_SIZE_128KB);
11124 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11125 tp->nvram_size = (protect ?
11126 TG3_NVRAM_SIZE_64KB :
11127 TG3_NVRAM_SIZE_256KB);
11128 else
11129 tp->nvram_size = (protect ?
11130 TG3_NVRAM_SIZE_128KB :
11131 TG3_NVRAM_SIZE_512KB);
11132 break;
d3c7b886
MC		 11133 }
11134}
11135
1b27777a
MC		 11136static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11137{
11138 u32 nvcfg1;
11139
11140 nvcfg1 = tr32(NVRAM_CFG1);
11141
11142 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11143 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11144 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11145 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11146 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11147 tp->nvram_jedecnum = JEDEC_ATMEL;
11148 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11149 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11150
8590a603
MC		 11151 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11152 tw32(NVRAM_CFG1, nvcfg1);
11153 break;
11154 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11155 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11156 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11157 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11158 tp->nvram_jedecnum = JEDEC_ATMEL;
11159 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11160 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11161 tp->nvram_pagesize = 264;
11162 break;
11163 case FLASH_5752VENDOR_ST_M45PE10:
11164 case FLASH_5752VENDOR_ST_M45PE20:
11165 case FLASH_5752VENDOR_ST_M45PE40:
11166 tp->nvram_jedecnum = JEDEC_ST;
11167 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11168 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11169 tp->nvram_pagesize = 256;
11170 break;
1b27777a
MC		 11171 }
11172}
11173
6b91fa02
MC		 11174static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11175{
11176 u32 nvcfg1, protect = 0;
11177
11178 nvcfg1 = tr32(NVRAM_CFG1);
11179
11180 /* NVRAM protection for TPM */
11181 if (nvcfg1 & (1 << 27)) {
f66a29b0 11182 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
6b91fa02
MC		 11183 protect = 1;
11184 }
11185
11186 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11187 switch (nvcfg1) {
8590a603
MC		 11188 case FLASH_5761VENDOR_ATMEL_ADB021D:
11189 case FLASH_5761VENDOR_ATMEL_ADB041D:
11190 case FLASH_5761VENDOR_ATMEL_ADB081D:
11191 case FLASH_5761VENDOR_ATMEL_ADB161D:
11192 case FLASH_5761VENDOR_ATMEL_MDB021D:
11193 case FLASH_5761VENDOR_ATMEL_MDB041D:
11194 case FLASH_5761VENDOR_ATMEL_MDB081D:
11195 case FLASH_5761VENDOR_ATMEL_MDB161D:
11196 tp->nvram_jedecnum = JEDEC_ATMEL;
11197 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11198 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11199 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11200 tp->nvram_pagesize = 256;
11201 break;
11202 case FLASH_5761VENDOR_ST_A_M45PE20:
11203 case FLASH_5761VENDOR_ST_A_M45PE40:
11204 case FLASH_5761VENDOR_ST_A_M45PE80:
11205 case FLASH_5761VENDOR_ST_A_M45PE16:
11206 case FLASH_5761VENDOR_ST_M_M45PE20:
11207 case FLASH_5761VENDOR_ST_M_M45PE40:
11208 case FLASH_5761VENDOR_ST_M_M45PE80:
11209 case FLASH_5761VENDOR_ST_M_M45PE16:
11210 tp->nvram_jedecnum = JEDEC_ST;
11211 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11212 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11213 tp->nvram_pagesize = 256;
11214 break;
6b91fa02
MC		 11215 }
11216
11217 if (protect) {
11218 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11219 } else {
11220 switch (nvcfg1) {
8590a603
MC		 11221 case FLASH_5761VENDOR_ATMEL_ADB161D:
11222 case FLASH_5761VENDOR_ATMEL_MDB161D:
11223 case FLASH_5761VENDOR_ST_A_M45PE16:
11224 case FLASH_5761VENDOR_ST_M_M45PE16:
11225 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11226 break;
11227 case FLASH_5761VENDOR_ATMEL_ADB081D:
11228 case FLASH_5761VENDOR_ATMEL_MDB081D:
11229 case FLASH_5761VENDOR_ST_A_M45PE80:
11230 case FLASH_5761VENDOR_ST_M_M45PE80:
11231 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11232 break;
11233 case FLASH_5761VENDOR_ATMEL_ADB041D:
11234 case FLASH_5761VENDOR_ATMEL_MDB041D:
11235 case FLASH_5761VENDOR_ST_A_M45PE40:
11236 case FLASH_5761VENDOR_ST_M_M45PE40:
11237 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11238 break;
11239 case FLASH_5761VENDOR_ATMEL_ADB021D:
11240 case FLASH_5761VENDOR_ATMEL_MDB021D:
11241 case FLASH_5761VENDOR_ST_A_M45PE20:
11242 case FLASH_5761VENDOR_ST_M_M45PE20:
11243 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11244 break;
6b91fa02
MC		 11245 }
11246 }
11247}
11248
b5d3772c
MC		 11249static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11250{
11251 tp->nvram_jedecnum = JEDEC_ATMEL;
11252 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11253 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11254}
11255
321d32a0
MC		 11256static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11257{
11258 u32 nvcfg1;
11259
11260 nvcfg1 = tr32(NVRAM_CFG1);
11261
11262 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11263 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11264 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11265 tp->nvram_jedecnum = JEDEC_ATMEL;
11266 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11267 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11268
11269 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11270 tw32(NVRAM_CFG1, nvcfg1);
11271 return;
11272 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11273 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11274 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11275 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11276 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11277 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11278 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11279 tp->nvram_jedecnum = JEDEC_ATMEL;
11280 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11281 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11282
11283 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11284 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11285 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11286 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11287 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11288 break;
11289 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11290 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11291 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11292 break;
11293 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11294 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11295 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11296 break;
11297 }
11298 break;
11299 case FLASH_5752VENDOR_ST_M45PE10:
11300 case FLASH_5752VENDOR_ST_M45PE20:
11301 case FLASH_5752VENDOR_ST_M45PE40:
11302 tp->nvram_jedecnum = JEDEC_ST;
11303 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11304 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11305
11306 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11307 case FLASH_5752VENDOR_ST_M45PE10:
11308 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11309 break;
11310 case FLASH_5752VENDOR_ST_M45PE20:
11311 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11312 break;
11313 case FLASH_5752VENDOR_ST_M45PE40:
11314 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11315 break;
11316 }
11317 break;
11318 default:
df259d8c 11319 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11320 return;
11321 }
11322
a1b950d5
MC		 11323 tg3_nvram_get_pagesize(tp, nvcfg1);
11324 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11325 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11326}
11327
11328
11329static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11330{
11331 u32 nvcfg1;
11332
11333 nvcfg1 = tr32(NVRAM_CFG1);
11334
11335 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11336 case FLASH_5717VENDOR_ATMEL_EEPROM:
11337 case FLASH_5717VENDOR_MICRO_EEPROM:
11338 tp->nvram_jedecnum = JEDEC_ATMEL;
11339 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11340 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11341
11342 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11343 tw32(NVRAM_CFG1, nvcfg1);
11344 return;
11345 case FLASH_5717VENDOR_ATMEL_MDB011D:
11346 case FLASH_5717VENDOR_ATMEL_ADB011B:
11347 case FLASH_5717VENDOR_ATMEL_ADB011D:
11348 case FLASH_5717VENDOR_ATMEL_MDB021D:
11349 case FLASH_5717VENDOR_ATMEL_ADB021B:
11350 case FLASH_5717VENDOR_ATMEL_ADB021D:
11351 case FLASH_5717VENDOR_ATMEL_45USPT:
11352 tp->nvram_jedecnum = JEDEC_ATMEL;
11353 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11354 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11355
11356 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11357 case FLASH_5717VENDOR_ATMEL_MDB021D:
11358 case FLASH_5717VENDOR_ATMEL_ADB021B:
11359 case FLASH_5717VENDOR_ATMEL_ADB021D:
11360 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11361 break;
11362 default:
11363 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11364 break;
11365 }
321d32a0 11366 break;
a1b950d5
MC		 11367 case FLASH_5717VENDOR_ST_M_M25PE10:
11368 case FLASH_5717VENDOR_ST_A_M25PE10:
11369 case FLASH_5717VENDOR_ST_M_M45PE10:
11370 case FLASH_5717VENDOR_ST_A_M45PE10:
11371 case FLASH_5717VENDOR_ST_M_M25PE20:
11372 case FLASH_5717VENDOR_ST_A_M25PE20:
11373 case FLASH_5717VENDOR_ST_M_M45PE20:
11374 case FLASH_5717VENDOR_ST_A_M45PE20:
11375 case FLASH_5717VENDOR_ST_25USPT:
11376 case FLASH_5717VENDOR_ST_45USPT:
11377 tp->nvram_jedecnum = JEDEC_ST;
11378 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11379 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11380
11381 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11382 case FLASH_5717VENDOR_ST_M_M25PE20:
11383 case FLASH_5717VENDOR_ST_A_M25PE20:
11384 case FLASH_5717VENDOR_ST_M_M45PE20:
11385 case FLASH_5717VENDOR_ST_A_M45PE20:
11386 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11387 break;
11388 default:
11389 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11390 break;
11391 }
321d32a0 11392 break;
a1b950d5
MC		 11393 default:
11394 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11395 return;
321d32a0 11396 }
a1b950d5
MC		 11397
11398 tg3_nvram_get_pagesize(tp, nvcfg1);
11399 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11400 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11401}
11402
1da177e4
LT		 11403/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11404static void __devinit tg3_nvram_init(struct tg3 *tp)
11405{
1da177e4
LT		 11406 tw32_f(GRC_EEPROM_ADDR,
11407 (EEPROM_ADDR_FSM_RESET |
11408 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11409 EEPROM_ADDR_CLKPERD_SHIFT)));
11410
9d57f01c 11411 msleep(1);
1da177e4
LT		 11412
11413 /* Enable seeprom accesses. */
11414 tw32_f(GRC_LOCAL_CTRL,
11415 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11416 udelay(100);
11417
11418 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11419 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11420 tp->tg3_flags |= TG3_FLAG_NVRAM;
11421
ec41c7df
MC		 11422 if (tg3_nvram_lock(tp)) {
11423 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11424 "tg3_nvram_init failed.\n", tp->dev->name);
11425 return;
11426 }
e6af301b 11427 tg3_enable_nvram_access(tp);
1da177e4 11428
989a9d23
MC		 11429 tp->nvram_size = 0;
11430
361b4ac2
MC		 11431 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11432 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11433 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11434 tg3_get_5755_nvram_info(tp);
d30cdd28 11435 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11436 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11437 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11438 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11439 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11440 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11441 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11442 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11443 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11444 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11445 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11446 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11447 else
11448 tg3_get_nvram_info(tp);
11449
989a9d23
MC		 11450 if (tp->nvram_size == 0)
11451 tg3_get_nvram_size(tp);
1da177e4 11452
e6af301b 11453 tg3_disable_nvram_access(tp);
381291b7 11454 tg3_nvram_unlock(tp);
1da177e4
LT		 11455
11456 } else {
11457 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11458
11459 tg3_get_eeprom_size(tp);
11460 }
11461}
11462
1da177e4
LT		 11463static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11464 u32 offset, u32 len, u8 *buf)
11465{
11466 int i, j, rc = 0;
11467 u32 val;
11468
11469 for (i = 0; i < len; i += 4) {
b9fc7dc5 11470 u32 addr;
a9dc529d 11471 __be32 data;
1da177e4
LT		 11472
11473 addr = offset + i;
11474
11475 memcpy(&data, buf + i, 4);
11476
62cedd11
MC		 11477 /*
11478 * The SEEPROM interface expects the data to always be opposite
11479 * the native endian format. We accomplish this by reversing
11480 * all the operations that would have been performed on the
11481 * data from a call to tg3_nvram_read_be32().
11482 */
11483 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11484
11485 val = tr32(GRC_EEPROM_ADDR);
11486 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11487
11488 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11489 EEPROM_ADDR_READ);
11490 tw32(GRC_EEPROM_ADDR, val |
11491 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11492 (addr & EEPROM_ADDR_ADDR_MASK) |
11493 EEPROM_ADDR_START |
11494 EEPROM_ADDR_WRITE);
6aa20a22 11495
9d57f01c 11496 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11497 val = tr32(GRC_EEPROM_ADDR);
11498
11499 if (val & EEPROM_ADDR_COMPLETE)
11500 break;
9d57f01c 11501 msleep(1);
1da177e4
LT		 11502 }
11503 if (!(val & EEPROM_ADDR_COMPLETE)) {
11504 rc = -EBUSY;
11505 break;
11506 }
11507 }
11508
11509 return rc;
11510}
11511
11512/* offset and length are dword aligned */
11513static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11514 u8 *buf)
11515{
11516 int ret = 0;
11517 u32 pagesize = tp->nvram_pagesize;
11518 u32 pagemask = pagesize - 1;
11519 u32 nvram_cmd;
11520 u8 *tmp;
11521
11522 tmp = kmalloc(pagesize, GFP_KERNEL);
11523 if (tmp == NULL)
11524 return -ENOMEM;
11525
11526 while (len) {
11527 int j;
e6af301b 11528 u32 phy_addr, page_off, size;
1da177e4
LT		 11529
11530 phy_addr = offset & ~pagemask;
6aa20a22 11531
1da177e4 11532 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11533 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11534 (__be32 *) (tmp + j));
11535 if (ret)
1da177e4
LT		 11536 break;
11537 }
11538 if (ret)
11539 break;
11540
11541 page_off = offset & pagemask;
11542 size = pagesize;
11543 if (len < size)
11544 size = len;
11545
11546 len -= size;
11547
11548 memcpy(tmp + page_off, buf, size);
11549
11550 offset = offset + (pagesize - page_off);
11551
e6af301b 11552 tg3_enable_nvram_access(tp);
1da177e4
LT		 11553
11554 /*
11555 * Before we can erase the flash page, we need
11556 * to issue a special "write enable" command.
11557 */
11558 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11559
11560 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11561 break;
11562
11563 /* Erase the target page */
11564 tw32(NVRAM_ADDR, phy_addr);
11565
11566 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11567 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11568
11569 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11570 break;
11571
11572 /* Issue another write enable to start the write. */
11573 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11574
11575 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11576 break;
11577
11578 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11579 __be32 data;
1da177e4 11580
b9fc7dc5 11581 data = *((__be32 *) (tmp + j));
a9dc529d 11582
b9fc7dc5 11583 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11584
11585 tw32(NVRAM_ADDR, phy_addr + j);
11586
11587 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11588 NVRAM_CMD_WR;
11589
11590 if (j == 0)
11591 nvram_cmd |= NVRAM_CMD_FIRST;
11592 else if (j == (pagesize - 4))
11593 nvram_cmd |= NVRAM_CMD_LAST;
11594
11595 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11596 break;
11597 }
11598 if (ret)
11599 break;
11600 }
11601
11602 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11603 tg3_nvram_exec_cmd(tp, nvram_cmd);
11604
11605 kfree(tmp);
11606
11607 return ret;
11608}
11609
11610/* offset and length are dword aligned */
11611static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11612 u8 *buf)
11613{
11614 int i, ret = 0;
11615
11616 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11617 u32 page_off, phy_addr, nvram_cmd;
11618 __be32 data;
1da177e4
LT		 11619
11620 memcpy(&data, buf + i, 4);
b9fc7dc5 11621 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11622
11623 page_off = offset % tp->nvram_pagesize;
11624
1820180b 11625 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11626
11627 tw32(NVRAM_ADDR, phy_addr);
11628
11629 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11630
11631 if ((page_off == 0) || (i == 0))
11632 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11633 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11634 nvram_cmd |= NVRAM_CMD_LAST;
11635
11636 if (i == (len - 4))
11637 nvram_cmd |= NVRAM_CMD_LAST;
11638
321d32a0
MC		 11639 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11640 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11641 (tp->nvram_jedecnum == JEDEC_ST) &&
11642 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11643
11644 if ((ret = tg3_nvram_exec_cmd(tp,
11645 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11646 NVRAM_CMD_DONE)))
11647
11648 break;
11649 }
11650 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11651 /* We always do complete word writes to eeprom. */
11652 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11653 }
11654
11655 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11656 break;
11657 }
11658 return ret;
11659}
11660
11661/* offset and length are dword aligned */
11662static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11663{
11664 int ret;
11665
1da177e4 11666 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11667 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11668 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11669 udelay(40);
11670 }
11671
11672 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11673 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11674 }
11675 else {
11676 u32 grc_mode;
11677
ec41c7df
MC		 11678 ret = tg3_nvram_lock(tp);
11679 if (ret)
11680 return ret;
1da177e4 11681
e6af301b
MC		 11682 tg3_enable_nvram_access(tp);
11683 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
f66a29b0 11684 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
1da177e4 11685 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11686
11687 grc_mode = tr32(GRC_MODE);
11688 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11689
11690 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11691 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11692
11693 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11694 buf);
11695 }
11696 else {
11697 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11698 buf);
11699 }
11700
11701 grc_mode = tr32(GRC_MODE);
11702 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11703
e6af301b 11704 tg3_disable_nvram_access(tp);
1da177e4
LT		 11705 tg3_nvram_unlock(tp);
11706 }
11707
11708 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11709 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11710 udelay(40);
11711 }
11712
11713 return ret;
11714}
11715
11716struct subsys_tbl_ent {
11717 u16 subsys_vendor, subsys_devid;
11718 u32 phy_id;
11719};
11720
11721static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11722 /* Broadcom boards. */
11723 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11724 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11725 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11726 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11727 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11728 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11729 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11730 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11731 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11732 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11733 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11734
11735 /* 3com boards. */
11736 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11737 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11738 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11739 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11740 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11741
11742 /* DELL boards. */
11743 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11744 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11745 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11746 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11747
11748 /* Compaq boards. */
11749 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11750 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11751 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11752 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11753 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11754
11755 /* IBM boards. */
11756 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11757};
11758
11759static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11760{
11761 int i;
11762
11763 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11764 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11765 tp->pdev->subsystem_vendor) &&
11766 (subsys_id_to_phy_id[i].subsys_devid ==
11767 tp->pdev->subsystem_device))
11768 return &subsys_id_to_phy_id[i];
11769 }
11770 return NULL;
11771}
11772
7d0c41ef 11773static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11774{
1da177e4 11775 u32 val;
caf636c7
MC		 11776 u16 pmcsr;
11777
11778 /* On some early chips the SRAM cannot be accessed in D3hot state,
11779 * so need make sure we're in D0.
11780 */
11781 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11782 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11783 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11784 msleep(1);
7d0c41ef
MC		 11785
11786 /* Make sure register accesses (indirect or otherwise)
11787 * will function correctly.
11788 */
11789 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11790 tp->misc_host_ctrl);
1da177e4 11791
f49639e6
DM		 11792 /* The memory arbiter has to be enabled in order for SRAM accesses
11793 * to succeed. Normally on powerup the tg3 chip firmware will make
11794 * sure it is enabled, but other entities such as system netboot
11795 * code might disable it.
11796 */
11797 val = tr32(MEMARB_MODE);
11798 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11799
1da177e4 11800 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11801 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11802
a85feb8c
GZ		 11803 /* Assume an onboard device and WOL capable by default. */
11804 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11805
b5d3772c 11806 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11807 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11808 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11809 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11810 }
0527ba35
MC		 11811 val = tr32(VCPU_CFGSHDW);
11812 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11813 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11814 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11815 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11816 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11817 goto done;
b5d3772c
MC		 11818 }
11819
1da177e4
LT		 11820 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11821 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11822 u32 nic_cfg, led_cfg;
a9daf367 11823 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11824 int eeprom_phy_serdes = 0;
1da177e4
LT		 11825
11826 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11827 tp->nic_sram_data_cfg = nic_cfg;
11828
11829 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11830 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11831 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11832 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11833 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11834 (ver > 0) && (ver < 0x100))
11835 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11836
a9daf367
MC		 11837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11838 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11839
1da177e4
LT		 11840 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11841 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11842 eeprom_phy_serdes = 1;
11843
11844 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11845 if (nic_phy_id != 0) {
11846 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11847 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11848
11849 eeprom_phy_id = (id1 >> 16) << 10;
11850 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11851 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11852 } else
11853 eeprom_phy_id = 0;
11854
7d0c41ef 11855 tp->phy_id = eeprom_phy_id;
747e8f8b 11856 if (eeprom_phy_serdes) {
a4e2b347 11857 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11858 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11859 else
11860 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11861 }
7d0c41ef 11862
cbf46853 11863 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11864 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11865 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11866 else
1da177e4
LT		 11867 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11868
11869 switch (led_cfg) {
11870 default:
11871 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11872 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11873 break;
11874
11875 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11876 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11877 break;
11878
11879 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11880 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11881
11882 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11883 * read on some older 5700/5701 bootcode.
11884 */
11885 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11886 ASIC_REV_5700 ||
11887 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11888 ASIC_REV_5701)
11889 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11890
1da177e4
LT		 11891 break;
11892
11893 case SHASTA_EXT_LED_SHARED:
11894 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11895 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11896 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11897 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11898 LED_CTRL_MODE_PHY_2);
11899 break;
11900
11901 case SHASTA_EXT_LED_MAC:
11902 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11903 break;
11904
11905 case SHASTA_EXT_LED_COMBO:
11906 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11907 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11908 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11909 LED_CTRL_MODE_PHY_2);
11910 break;
11911
855e1111 11912 }
1da177e4
LT		 11913
11914 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11916 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11917 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11918
b2a5c19c
MC		 11919 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11920 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11921
9d26e213 11922 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11923 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11924 if ((tp->pdev->subsystem_vendor ==
11925 PCI_VENDOR_ID_ARIMA) &&
11926 (tp->pdev->subsystem_device == 0x205a ||
11927 tp->pdev->subsystem_device == 0x2063))
11928 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11929 } else {
f49639e6 11930 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11931 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11932 }
1da177e4
LT		 11933
11934 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11935 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11936 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11937 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11938 }
b2b98d4a
MC		 11939
11940 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11941 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11942 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11943
a85feb8c
GZ		 11944 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11945 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11946 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11947
12dac075 11948 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11949 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11950 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11951
1da177e4
LT		 11952 if (cfg2 & (1 << 17))
11953 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11954
11955 /* serdes signal pre-emphasis in register 0x590 set by */
11956 /* bootcode if bit 18 is set */
11957 if (cfg2 & (1 << 18))
11958 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11959
321d32a0
MC		 11960 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11961 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11962 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11963 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11964
8ed5d97e
MC		 11965 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11966 u32 cfg3;
11967
11968 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11969 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11970 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11971 }
a9daf367
MC		 11972
11973 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11974 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11975 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11976 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11977 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11978 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11979 }
05ac4cb7
MC		 11980done:
11981 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11982 device_set_wakeup_enable(&tp->pdev->dev,
11983 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11984}
11985
b2a5c19c
MC		 11986static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11987{
11988 int i;
11989 u32 val;
11990
11991 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11992 tw32(OTP_CTRL, cmd);
11993
11994 /* Wait for up to 1 ms for command to execute. */
11995 for (i = 0; i < 100; i++) {
11996 val = tr32(OTP_STATUS);
11997 if (val & OTP_STATUS_CMD_DONE)
11998 break;
11999 udelay(10);
12000 }
12001
12002 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12003}
12004
12005/* Read the gphy configuration from the OTP region of the chip. The gphy
12006 * configuration is a 32-bit value that straddles the alignment boundary.
12007 * We do two 32-bit reads and then shift and merge the results.
12008 */
12009static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12010{
12011 u32 bhalf_otp, thalf_otp;
12012
12013 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12014
12015 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12016 return 0;
12017
12018 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12019
12020 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12021 return 0;
12022
12023 thalf_otp = tr32(OTP_READ_DATA);
12024
12025 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12026
12027 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12028 return 0;
12029
12030 bhalf_otp = tr32(OTP_READ_DATA);
12031
12032 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12033}
12034
7d0c41ef
MC		 12035static int __devinit tg3_phy_probe(struct tg3 *tp)
12036{
12037 u32 hw_phy_id_1, hw_phy_id_2;
12038 u32 hw_phy_id, hw_phy_id_masked;
12039 int err;
1da177e4 12040
b02fd9e3
MC		 12041 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12042 return tg3_phy_init(tp);
12043
1da177e4 12044 /* Reading the PHY ID register can conflict with ASF
877d0310 12045 * firmware access to the PHY hardware.
1da177e4
LT		 12046 */
12047 err = 0;
0d3031d9
MC		 12048 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12049 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 12050 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12051 } else {
12052 /* Now read the physical PHY_ID from the chip and verify
12053 * that it is sane. If it doesn't look good, we fall back
12054 * to either the hard-coded table based PHY_ID and failing
12055 * that the value found in the eeprom area.
12056 */
12057 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12058 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12059
12060 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12061 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12062 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12063
12064 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12065 }
12066
12067 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12068 tp->phy_id = hw_phy_id;
12069 if (hw_phy_id_masked == PHY_ID_BCM8002)
12070 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 12071 else
12072 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 12073 } else {
7d0c41ef
MC		 12074 if (tp->phy_id != PHY_ID_INVALID) {
12075 /* Do nothing, phy ID already set up in
12076 * tg3_get_eeprom_hw_cfg().
12077 */
1da177e4
LT		 12078 } else {
12079 struct subsys_tbl_ent *p;
12080
12081 /* No eeprom signature? Try the hardcoded
12082 * subsys device table.
12083 */
12084 p = lookup_by_subsys(tp);
12085 if (!p)
12086 return -ENODEV;
12087
12088 tp->phy_id = p->phy_id;
12089 if (!tp->phy_id ||
12090 tp->phy_id == PHY_ID_BCM8002)
12091 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12092 }
12093 }
12094
747e8f8b 12095 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12096 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12097 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12098 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12099
12100 tg3_readphy(tp, MII_BMSR, &bmsr);
12101 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12102 (bmsr & BMSR_LSTATUS))
12103 goto skip_phy_reset;
6aa20a22 12104
1da177e4
LT		 12105 err = tg3_phy_reset(tp);
12106 if (err)
12107 return err;
12108
12109 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12110 ADVERTISE_100HALF | ADVERTISE_100FULL |
12111 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12112 tg3_ctrl = 0;
12113 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12114 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12115 MII_TG3_CTRL_ADV_1000_FULL);
12116 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12117 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12118 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12119 MII_TG3_CTRL_ENABLE_AS_MASTER);
12120 }
12121
3600d918
MC		 12122 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12123 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12124 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12125 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12126 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12127
12128 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12129 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12130
12131 tg3_writephy(tp, MII_BMCR,
12132 BMCR_ANENABLE | BMCR_ANRESTART);
12133 }
12134 tg3_phy_set_wirespeed(tp);
12135
12136 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12137 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12138 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12139 }
12140
12141skip_phy_reset:
12142 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12143 err = tg3_init_5401phy_dsp(tp);
12144 if (err)
12145 return err;
12146 }
12147
12148 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12149 err = tg3_init_5401phy_dsp(tp);
12150 }
12151
747e8f8b 12152 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12153 tp->link_config.advertising =
12154 (ADVERTISED_1000baseT_Half |
12155 ADVERTISED_1000baseT_Full |
12156 ADVERTISED_Autoneg |
12157 ADVERTISED_FIBRE);
12158 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12159 tp->link_config.advertising &=
12160 ~(ADVERTISED_1000baseT_Half |
12161 ADVERTISED_1000baseT_Full);
12162
12163 return err;
12164}
12165
12166static void __devinit tg3_read_partno(struct tg3 *tp)
12167{
6d348f2c 12168 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12169 unsigned int i;
1b27777a 12170 u32 magic;
1da177e4 12171
df259d8c
MC		 12172 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12173 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12174 goto out_not_found;
1da177e4 12175
1820180b 12176 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12177 for (i = 0; i < 256; i += 4) {
12178 u32 tmp;
1da177e4 12179
6d348f2c
MC		 12180 /* The data is in little-endian format in NVRAM.
12181 * Use the big-endian read routines to preserve
12182 * the byte order as it exists in NVRAM.
12183 */
12184 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12185 goto out_not_found;
12186
6d348f2c 12187 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12188 }
12189 } else {
12190 int vpd_cap;
12191
12192 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12193 for (i = 0; i < 256; i += 4) {
12194 u32 tmp, j = 0;
b9fc7dc5 12195 __le32 v;
1b27777a
MC		 12196 u16 tmp16;
12197
12198 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12199 i);
12200 while (j++ < 100) {
12201 pci_read_config_word(tp->pdev, vpd_cap +
12202 PCI_VPD_ADDR, &tmp16);
12203 if (tmp16 & 0x8000)
12204 break;
12205 msleep(1);
12206 }
f49639e6
DM		 12207 if (!(tmp16 & 0x8000))
12208 goto out_not_found;
12209
1b27777a
MC		 12210 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12211 &tmp);
b9fc7dc5 12212 v = cpu_to_le32(tmp);
6d348f2c 12213 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12214 }
1da177e4
LT		 12215 }
12216
12217 /* Now parse and find the part number. */
af2c6a4a 12218 for (i = 0; i < 254; ) {
1da177e4 12219 unsigned char val = vpd_data[i];
af2c6a4a 12220 unsigned int block_end;
1da177e4
LT		 12221
12222 if (val == 0x82 || val == 0x91) {
12223 i = (i + 3 +
12224 (vpd_data[i + 1] +
12225 (vpd_data[i + 2] << 8)));
12226 continue;
12227 }
12228
12229 if (val != 0x90)
12230 goto out_not_found;
12231
12232 block_end = (i + 3 +
12233 (vpd_data[i + 1] +
12234 (vpd_data[i + 2] << 8)));
12235 i += 3;
af2c6a4a
MC		 12236
12237 if (block_end > 256)
12238 goto out_not_found;
12239
12240 while (i < (block_end - 2)) {
1da177e4
LT		 12241 if (vpd_data[i + 0] == 'P' &&
12242 vpd_data[i + 1] == 'N') {
12243 int partno_len = vpd_data[i + 2];
12244
af2c6a4a
MC		 12245 i += 3;
12246 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12247 goto out_not_found;
12248
12249 memcpy(tp->board_part_number,
af2c6a4a 12250 &vpd_data[i], partno_len);
1da177e4
LT		 12251
12252 /* Success. */
12253 return;
12254 }
af2c6a4a 12255 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12256 }
12257
12258 /* Part number not found. */
12259 goto out_not_found;
12260 }
12261
12262out_not_found:
b5d3772c
MC		 12263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12264 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12265 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12266 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12267 strcpy(tp->board_part_number, "BCM57780");
12268 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12269 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12270 strcpy(tp->board_part_number, "BCM57760");
12271 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12272 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12273 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12274 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12275 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12276 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12277 else
12278 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12279}
12280
9c8a620e
MC		 12281static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12282{
12283 u32 val;
12284
e4f34110 12285 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12286 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12287 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12288 val != 0)
12289 return 0;
12290
12291 return 1;
12292}
12293
acd9c119
MC		 12294static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12295{
ff3a7cb2 12296 u32 val, offset, start, ver_offset;
acd9c119 12297 int i;
ff3a7cb2 12298 bool newver = false;
acd9c119
MC		 12299
12300 if (tg3_nvram_read(tp, 0xc, &offset) ||
12301 tg3_nvram_read(tp, 0x4, &start))
12302 return;
12303
12304 offset = tg3_nvram_logical_addr(tp, offset);
12305
ff3a7cb2 12306 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12307 return;
12308
ff3a7cb2
MC		 12309 if ((val & 0xfc000000) == 0x0c000000) {
12310 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12311 return;
12312
ff3a7cb2
MC		 12313 if (val == 0)
12314 newver = true;
12315 }
12316
12317 if (newver) {
12318 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12319 return;
12320
12321 offset = offset + ver_offset - start;
12322 for (i = 0; i < 16; i += 4) {
12323 __be32 v;
12324 if (tg3_nvram_read_be32(tp, offset + i, &v))
12325 return;
12326
12327 memcpy(tp->fw_ver + i, &v, sizeof(v));
12328 }
12329 } else {
12330 u32 major, minor;
12331
12332 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12333 return;
12334
12335 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12336 TG3_NVM_BCVER_MAJSFT;
12337 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12338 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12339 }
12340}
12341
a6f6cb1c
MC		 12342static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12343{
12344 u32 val, major, minor;
12345
12346 /* Use native endian representation */
12347 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12348 return;
12349
12350 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12351 TG3_NVM_HWSB_CFG1_MAJSFT;
12352 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12353 TG3_NVM_HWSB_CFG1_MINSFT;
12354
12355 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12356}
12357
dfe00d7d
MC		 12358static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12359{
12360 u32 offset, major, minor, build;
12361
12362 tp->fw_ver[0] = 's';
12363 tp->fw_ver[1] = 'b';
12364 tp->fw_ver[2] = '\0';
12365
12366 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12367 return;
12368
12369 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12370 case TG3_EEPROM_SB_REVISION_0:
12371 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12372 break;
12373 case TG3_EEPROM_SB_REVISION_2:
12374 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12375 break;
12376 case TG3_EEPROM_SB_REVISION_3:
12377 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12378 break;
12379 default:
12380 return;
12381 }
12382
e4f34110 12383 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12384 return;
12385
12386 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12387 TG3_EEPROM_SB_EDH_BLD_SHFT;
12388 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12389 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12390 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12391
12392 if (minor > 99 || build > 26)
12393 return;
12394
12395 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12396
12397 if (build > 0) {
12398 tp->fw_ver[8] = 'a' + build - 1;
12399 tp->fw_ver[9] = '\0';
12400 }
12401}
12402
acd9c119 12403static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12404{
12405 u32 val, offset, start;
acd9c119 12406 int i, vlen;
9c8a620e
MC		 12407
12408 for (offset = TG3_NVM_DIR_START;
12409 offset < TG3_NVM_DIR_END;
12410 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12411 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12412 return;
12413
9c8a620e
MC		 12414 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12415 break;
12416 }
12417
12418 if (offset == TG3_NVM_DIR_END)
12419 return;
12420
12421 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12422 start = 0x08000000;
e4f34110 12423 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12424 return;
12425
e4f34110 12426 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12427 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12428 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12429 return;
12430
12431 offset += val - start;
12432
acd9c119 12433 vlen = strlen(tp->fw_ver);
9c8a620e 12434
acd9c119
MC		 12435 tp->fw_ver[vlen++] = ',';
12436 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12437
12438 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12439 __be32 v;
12440 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12441 return;
12442
b9fc7dc5 12443 offset += sizeof(v);
c4e6575c 12444
acd9c119
MC		 12445 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12446 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12447 break;
c4e6575c 12448 }
9c8a620e 12449
acd9c119
MC		 12450 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12451 vlen += sizeof(v);
c4e6575c 12452 }
acd9c119
MC		 12453}
12454
7fd76445
MC		 12455static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12456{
12457 int vlen;
12458 u32 apedata;
12459
12460 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12461 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12462 return;
12463
12464 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12465 if (apedata != APE_SEG_SIG_MAGIC)
12466 return;
12467
12468 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12469 if (!(apedata & APE_FW_STATUS_READY))
12470 return;
12471
12472 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12473
12474 vlen = strlen(tp->fw_ver);
12475
12476 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12477 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12478 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12479 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12480 (apedata & APE_FW_VERSION_BLDMSK));
12481}
12482
acd9c119
MC		 12483static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12484{
12485 u32 val;
12486
df259d8c
MC		 12487 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12488 tp->fw_ver[0] = 's';
12489 tp->fw_ver[1] = 'b';
12490 tp->fw_ver[2] = '\0';
12491
12492 return;
12493 }
12494
acd9c119
MC		 12495 if (tg3_nvram_read(tp, 0, &val))
12496 return;
12497
12498 if (val == TG3_EEPROM_MAGIC)
12499 tg3_read_bc_ver(tp);
12500 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12501 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12502 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12503 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12504 else
12505 return;
12506
12507 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12508 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12509 return;
12510
12511 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12512
12513 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12514}
12515
7544b097
MC		 12516static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12517
1da177e4
LT		 12518static int __devinit tg3_get_invariants(struct tg3 *tp)
12519{
12520 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12521 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12522 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12523 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12524 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12525 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12526 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12527 { },
12528 };
12529 u32 misc_ctrl_reg;
1da177e4
LT		 12530 u32 pci_state_reg, grc_misc_cfg;
12531 u32 val;
12532 u16 pci_cmd;
5e7dfd0f 12533 int err;
1da177e4 12534
1da177e4
LT		 12535 /* Force memory write invalidate off. If we leave it on,
12536 * then on 5700_BX chips we have to enable a workaround.
12537 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12538 * to match the cacheline size. The Broadcom driver have this
12539 * workaround but turns MWI off all the times so never uses
12540 * it. This seems to suggest that the workaround is insufficient.
12541 */
12542 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12543 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12544 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12545
12546 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12547 * has the register indirect write enable bit set before
12548 * we try to access any of the MMIO registers. It is also
12549 * critical that the PCI-X hw workaround situation is decided
12550 * before that as well.
12551 */
12552 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12553 &misc_ctrl_reg);
12554
12555 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12556 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12557 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12558 u32 prod_id_asic_rev;
12559
f6eb9b1f
MC		 12560 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12561 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12562 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12563 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12564 pci_read_config_dword(tp->pdev,
12565 TG3PCI_GEN2_PRODID_ASICREV,
12566 &prod_id_asic_rev);
12567 else
12568 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12569 &prod_id_asic_rev);
12570
321d32a0 12571 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12572 }
1da177e4 12573
ff645bec
MC		 12574 /* Wrong chip ID in 5752 A0. This code can be removed later
12575 * as A0 is not in production.
12576 */
12577 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12578 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12579
6892914f
MC		 12580 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12581 * we need to disable memory and use config. cycles
12582 * only to access all registers. The 5702/03 chips
12583 * can mistakenly decode the special cycles from the
12584 * ICH chipsets as memory write cycles, causing corruption
12585 * of register and memory space. Only certain ICH bridges
12586 * will drive special cycles with non-zero data during the
12587 * address phase which can fall within the 5703's address
12588 * range. This is not an ICH bug as the PCI spec allows
12589 * non-zero address during special cycles. However, only
12590 * these ICH bridges are known to drive non-zero addresses
12591 * during special cycles.
12592 *
12593 * Since special cycles do not cross PCI bridges, we only
12594 * enable this workaround if the 5703 is on the secondary
12595 * bus of these ICH bridges.
12596 */
12597 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12598 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12599 static struct tg3_dev_id {
12600 u32 vendor;
12601 u32 device;
12602 u32 rev;
12603 } ich_chipsets[] = {
12604 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12605 PCI_ANY_ID },
12606 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12607 PCI_ANY_ID },
12608 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12609 0xa },
12610 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12611 PCI_ANY_ID },
12612 { },
12613 };
12614 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12615 struct pci_dev *bridge = NULL;
12616
12617 while (pci_id->vendor != 0) {
12618 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12619 bridge);
12620 if (!bridge) {
12621 pci_id++;
12622 continue;
12623 }
12624 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12625 if (bridge->revision > pci_id->rev)
6892914f
MC		 12626 continue;
12627 }
12628 if (bridge->subordinate &&
12629 (bridge->subordinate->number ==
12630 tp->pdev->bus->number)) {
12631
12632 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12633 pci_dev_put(bridge);
12634 break;
12635 }
12636 }
12637 }
12638
41588ba1
MC		 12639 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12640 static struct tg3_dev_id {
12641 u32 vendor;
12642 u32 device;
12643 } bridge_chipsets[] = {
12644 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12645 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12646 { },
12647 };
12648 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12649 struct pci_dev *bridge = NULL;
12650
12651 while (pci_id->vendor != 0) {
12652 bridge = pci_get_device(pci_id->vendor,
12653 pci_id->device,
12654 bridge);
12655 if (!bridge) {
12656 pci_id++;
12657 continue;
12658 }
12659 if (bridge->subordinate &&
12660 (bridge->subordinate->number <=
12661 tp->pdev->bus->number) &&
12662 (bridge->subordinate->subordinate >=
12663 tp->pdev->bus->number)) {
12664 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12665 pci_dev_put(bridge);
12666 break;
12667 }
12668 }
12669 }
12670
4a29cc2e
MC		 12671 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12672 * DMA addresses > 40-bit. This bridge may have other additional
12673 * 57xx devices behind it in some 4-port NIC designs for example.
12674 * Any tg3 device found behind the bridge will also need the 40-bit
12675 * DMA workaround.
12676 */
a4e2b347
MC		 12677 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12678 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12679 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12680 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12681 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12682 }
4a29cc2e
MC		 12683 else {
12684 struct pci_dev *bridge = NULL;
12685
12686 do {
12687 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12688 PCI_DEVICE_ID_SERVERWORKS_EPB,
12689 bridge);
12690 if (bridge && bridge->subordinate &&
12691 (bridge->subordinate->number <=
12692 tp->pdev->bus->number) &&
12693 (bridge->subordinate->subordinate >=
12694 tp->pdev->bus->number)) {
12695 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12696 pci_dev_put(bridge);
12697 break;
12698 }
12699 } while (bridge);
12700 }
4cf78e4f 12701
1da177e4
LT		 12702 /* Initialize misc host control in PCI block. */
12703 tp->misc_host_ctrl |= (misc_ctrl_reg &
12704 MISC_HOST_CTRL_CHIPREV);
12705 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12706 tp->misc_host_ctrl);
12707
f6eb9b1f
MC		 12708 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12710 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12711 tp->pdev_peer = tg3_find_peer(tp);
12712
321d32a0
MC		 12713 /* Intentionally exclude ASIC_REV_5906 */
12714 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12716 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12719 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12720 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12721 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12722
12723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12724 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12725 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12726 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12727 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12728 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12729
1b440c56
JL		 12730 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12731 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12732 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12733
027455ad
MC		 12734 /* 5700 B0 chips do not support checksumming correctly due
12735 * to hardware bugs.
12736 */
12737 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12738 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12739 else {
12740 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12741 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12742 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12743 tp->dev->features |= NETIF_F_IPV6_CSUM;
12744 }
12745
507399f1 12746 /* Determine TSO capabilities */
e849cdc3
MC		 12747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12748 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12749 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12750 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
507399f1
MC		 12751 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12752 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12753 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12754 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12755 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12756 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12757 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12758 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12759 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12760 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12762 tp->fw_needed = FIRMWARE_TG3TSO5;
12763 else
12764 tp->fw_needed = FIRMWARE_TG3TSO;
12765 }
12766
12767 tp->irq_max = 1;
12768
5a6f3074 12769 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12770 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12771 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12772 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12773 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12774 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12775 tp->pdev_peer == tp->pdev))
12776 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12777
321d32a0 12778 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12779 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
fcfa0a32 12780 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12781 }
4f125f42 12782
507399f1
MC		 12783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12784 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12785 tp->irq_max = TG3_IRQ_MAX_VECS;
12786 }
f6eb9b1f 12787 }
0e1406dd 12788
615774fe
MC		 12789 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12790 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12791 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12792 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12793 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12794 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
0e1406dd 12795 }
f6eb9b1f 12796
f51f3562 12797 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12798 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12800 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12801
52f4490c
MC		 12802 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12803 &pci_state_reg);
12804
5e7dfd0f
MC		 12805 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12806 if (tp->pcie_cap != 0) {
12807 u16 lnkctl;
12808
1da177e4 12809 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12810
12811 pcie_set_readrq(tp->pdev, 4096);
12812
5e7dfd0f
MC		 12813 pci_read_config_word(tp->pdev,
12814 tp->pcie_cap + PCI_EXP_LNKCTL,
12815 &lnkctl);
12816 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12817 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12818 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12819 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12821 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12822 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12823 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12824 }
52f4490c 12825 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12826 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12827 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12828 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12829 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12830 if (!tp->pcix_cap) {
12831 printk(KERN_ERR PFX "Cannot find PCI-X "
12832 "capability, aborting.\n");
12833 return -EIO;
12834 }
12835
12836 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12837 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12838 }
1da177e4 12839
399de50b
MC		 12840 /* If we have an AMD 762 or VIA K8T800 chipset, write
12841 * reordering to the mailbox registers done by the host
12842 * controller can cause major troubles. We read back from
12843 * every mailbox register write to force the writes to be
12844 * posted to the chip in order.
12845 */
12846 if (pci_dev_present(write_reorder_chipsets) &&
12847 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12848 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12849
69fc4053
MC		 12850 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12851 &tp->pci_cacheline_sz);
12852 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12853 &tp->pci_lat_timer);
1da177e4
LT		 12854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12855 tp->pci_lat_timer < 64) {
12856 tp->pci_lat_timer = 64;
69fc4053
MC		 12857 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12858 tp->pci_lat_timer);
1da177e4
LT		 12859 }
12860
52f4490c
MC		 12861 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12862 /* 5700 BX chips need to have their TX producer index
12863 * mailboxes written twice to workaround a bug.
12864 */
12865 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12866
52f4490c 12867 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12868 *
12869 * The workaround is to use indirect register accesses
12870 * for all chip writes not to mailbox registers.
12871 */
52f4490c 12872 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12873 u32 pm_reg;
1da177e4
LT		 12874
12875 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12876
12877 /* The chip can have it's power management PCI config
12878 * space registers clobbered due to this bug.
12879 * So explicitly force the chip into D0 here.
12880 */
9974a356
MC		 12881 pci_read_config_dword(tp->pdev,
12882 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12883 &pm_reg);
12884 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12885 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12886 pci_write_config_dword(tp->pdev,
12887 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12888 pm_reg);
12889
12890 /* Also, force SERR#/PERR# in PCI command. */
12891 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12892 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12893 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12894 }
12895 }
12896
1da177e4
LT		 12897 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12898 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12899 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12900 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12901
12902 /* Chip-specific fixup from Broadcom driver */
12903 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12904 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12905 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12906 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12907 }
12908
1ee582d8 12909 /* Default fast path register access methods */
20094930 12910 tp->read32 = tg3_read32;
1ee582d8 12911 tp->write32 = tg3_write32;
09ee929c 12912 tp->read32_mbox = tg3_read32;
20094930 12913 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12914 tp->write32_tx_mbox = tg3_write32;
12915 tp->write32_rx_mbox = tg3_write32;
12916
12917 /* Various workaround register access methods */
12918 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12919 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12920 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12921 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12922 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12923 /*
12924 * Back to back register writes can cause problems on these
12925 * chips, the workaround is to read back all reg writes
12926 * except those to mailbox regs.
12927 *
12928 * See tg3_write_indirect_reg32().
12929 */
1ee582d8 12930 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12931 }
12932
1ee582d8
MC		 12933 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12934 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12935 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12936 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12937 tp->write32_rx_mbox = tg3_write_flush_reg32;
12938 }
20094930 12939
6892914f
MC		 12940 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12941 tp->read32 = tg3_read_indirect_reg32;
12942 tp->write32 = tg3_write_indirect_reg32;
12943 tp->read32_mbox = tg3_read_indirect_mbox;
12944 tp->write32_mbox = tg3_write_indirect_mbox;
12945 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12946 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12947
12948 iounmap(tp->regs);
22abe310 12949 tp->regs = NULL;
6892914f
MC		 12950
12951 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12952 pci_cmd &= ~PCI_COMMAND_MEMORY;
12953 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12954 }
b5d3772c
MC		 12955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12956 tp->read32_mbox = tg3_read32_mbox_5906;
12957 tp->write32_mbox = tg3_write32_mbox_5906;
12958 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12959 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12960 }
6892914f 12961
bbadf503
MC		 12962 if (tp->write32 == tg3_write_indirect_reg32 ||
12963 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12964 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12966 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12967
7d0c41ef 12968 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12969 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12970 * determined before calling tg3_set_power_state() so that
12971 * we know whether or not to switch out of Vaux power.
12972 * When the flag is set, it means that GPIO1 is used for eeprom
12973 * write protect and also implies that it is a LOM where GPIOs
12974 * are not used to switch power.
6aa20a22 12975 */
7d0c41ef
MC		 12976 tg3_get_eeprom_hw_cfg(tp);
12977
0d3031d9
MC		 12978 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12979 /* Allow reads and writes to the
12980 * APE register and memory space.
12981 */
12982 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12983 PCISTATE_ALLOW_APE_SHMEM_WR;
12984 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12985 pci_state_reg);
12986 }
12987
9936bcf6 12988 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12993 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12994
314fba34
MC		 12995 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12996 * GPIO1 driven high will bring 5700's external PHY out of reset.
12997 * It is also used as eeprom write protect on LOMs.
12998 */
12999 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13000 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13001 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13002 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13003 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 13004 /* Unused GPIO3 must be driven as output on 5752 because there
13005 * are no pull-up resistors on unused GPIO pins.
13006 */
13007 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13008 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 13009
321d32a0
MC		 13010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 13012 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13013
8d519ab2
MC		 13014 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13015 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 13016 /* Turn off the debug UART. */
13017 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13018 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13019 /* Keep VMain power. */
13020 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13021 GRC_LCLCTRL_GPIO_OUTPUT0;
13022 }
13023
1da177e4 13024 /* Force the chip into D0. */
bc1c7567 13025 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 13026 if (err) {
13027 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13028 pci_name(tp->pdev));
13029 return err;
13030 }
13031
1da177e4
LT		 13032 /* Derive initial jumbo mode from MTU assigned in
13033 * ether_setup() via the alloc_etherdev() call
13034 */
0f893dc6 13035 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 13036 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 13037 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 13038
13039 /* Determine WakeOnLan speed to use. */
13040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13041 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13042 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13043 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13044 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13045 } else {
13046 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13047 }
13048
7f97a4bd
MC		 13049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13050 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13051
1da177e4
LT		 13052 /* A few boards don't want Ethernet@WireSpeed phy feature */
13053 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13054 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13055 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 13056 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 13057 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 13058 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 13059 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13060
13061 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13062 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13063 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13064 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13065 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13066
321d32a0 13067 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 13068 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 13069 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 13070 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13071 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 13072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 13073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 13074 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 13076 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13077 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13078 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 13079 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13080 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 13081 } else
c424cb24
MC		 13082 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13083 }
1da177e4 13084
b2a5c19c
MC		 13085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13086 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13087 tp->phy_otp = tg3_read_otp_phycfg(tp);
13088 if (tp->phy_otp == 0)
13089 tp->phy_otp = TG3_OTP_DEFAULT;
13090 }
13091
f51f3562 13092 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13093 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13094 else
13095 tp->mi_mode = MAC_MI_MODE_BASE;
13096
1da177e4 13097 tp->coalesce_mode = 0;
1da177e4
LT		 13098 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13099 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13100 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13101
321d32a0
MC		 13102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13104 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13105
158d7abd
MC		 13106 err = tg3_mdio_init(tp);
13107 if (err)
13108 return err;
1da177e4
LT		 13109
13110 /* Initialize data/descriptor byte/word swapping. */
13111 val = tr32(GRC_MODE);
13112 val &= GRC_MODE_HOST_STACKUP;
13113 tw32(GRC_MODE, val | tp->grc_mode);
13114
13115 tg3_switch_clocks(tp);
13116
13117 /* Clear this out for sanity. */
13118 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13119
13120 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13121 &pci_state_reg);
13122 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13123 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13124 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13125
13126 if (chiprevid == CHIPREV_ID_5701_A0 ||
13127 chiprevid == CHIPREV_ID_5701_B0 ||
13128 chiprevid == CHIPREV_ID_5701_B2 ||
13129 chiprevid == CHIPREV_ID_5701_B5) {
13130 void __iomem *sram_base;
13131
13132 /* Write some dummy words into the SRAM status block
13133 * area, see if it reads back correctly. If the return
13134 * value is bad, force enable the PCIX workaround.
13135 */
13136 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13137
13138 writel(0x00000000, sram_base);
13139 writel(0x00000000, sram_base + 4);
13140 writel(0xffffffff, sram_base + 4);
13141 if (readl(sram_base) != 0x00000000)
13142 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13143 }
13144 }
13145
13146 udelay(50);
13147 tg3_nvram_init(tp);
13148
13149 grc_misc_cfg = tr32(GRC_MISC_CFG);
13150 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13151
1da177e4
LT		 13152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13153 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13154 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13155 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13156
fac9b83e
DM		 13157 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13158 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13159 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13160 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13161 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13162 HOSTCC_MODE_CLRTICK_TXBD);
13163
13164 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13165 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13166 tp->misc_host_ctrl);
13167 }
13168
3bda1258
MC		 13169 /* Preserve the APE MAC_MODE bits */
13170 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13171 tp->mac_mode = tr32(MAC_MODE) |
13172 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13173 else
13174 tp->mac_mode = TG3_DEF_MAC_MODE;
13175
1da177e4
LT		 13176 /* these are limited to 10/100 only */
13177 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13178 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13179 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13180 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13181 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13182 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13183 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13184 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13185 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13186 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13187 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13188 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13189 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13190 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13191
13192 err = tg3_phy_probe(tp);
13193 if (err) {
13194 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13195 pci_name(tp->pdev), err);
13196 /* ... but do not return immediately ... */
b02fd9e3 13197 tg3_mdio_fini(tp);
1da177e4
LT		 13198 }
13199
13200 tg3_read_partno(tp);
c4e6575c 13201 tg3_read_fw_ver(tp);
1da177e4
LT		 13202
13203 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13204 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13205 } else {
13206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13207 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13208 else
13209 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13210 }
13211
13212 /* 5700 {AX,BX} chips have a broken status block link
13213 * change bit implementation, so we must use the
13214 * status register in those cases.
13215 */
13216 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13217 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13218 else
13219 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13220
13221 /* The led_ctrl is set during tg3_phy_probe, here we might
13222 * have to force the link status polling mechanism based
13223 * upon subsystem IDs.
13224 */
13225 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13227 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13228 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13229 TG3_FLAG_USE_LINKCHG_REG);
13230 }
13231
13232 /* For all SERDES we poll the MAC status register. */
13233 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13234 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13235 else
13236 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13237
ad829268 13238 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13239 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13240 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13241 tp->rx_offset = 0;
13242
f92905de
MC		 13243 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13244
13245 /* Increment the rx prod index on the rx std ring by at most
13246 * 8 for these chips to workaround hw errata.
13247 */
13248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13251 tp->rx_std_max_post = 8;
13252
8ed5d97e
MC		 13253 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13254 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13255 PCIE_PWR_MGMT_L1_THRESH_MSK;
13256
1da177e4
LT		 13257 return err;
13258}
13259
49b6e95f 13260#ifdef CONFIG_SPARC
1da177e4
LT		 13261static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13262{
13263 struct net_device *dev = tp->dev;
13264 struct pci_dev *pdev = tp->pdev;
49b6e95f 13265 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13266 const unsigned char *addr;
49b6e95f
DM		 13267 int len;
13268
13269 addr = of_get_property(dp, "local-mac-address", &len);
13270 if (addr && len == 6) {
13271 memcpy(dev->dev_addr, addr, 6);
13272 memcpy(dev->perm_addr, dev->dev_addr, 6);
13273 return 0;
1da177e4
LT		 13274 }
13275 return -ENODEV;
13276}
13277
13278static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13279{
13280 struct net_device *dev = tp->dev;
13281
13282 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13283 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13284 return 0;
13285}
13286#endif
13287
13288static int __devinit tg3_get_device_address(struct tg3 *tp)
13289{
13290 struct net_device *dev = tp->dev;
13291 u32 hi, lo, mac_offset;
008652b3 13292 int addr_ok = 0;
1da177e4 13293
49b6e95f 13294#ifdef CONFIG_SPARC
1da177e4
LT		 13295 if (!tg3_get_macaddr_sparc(tp))
13296 return 0;
13297#endif
13298
13299 mac_offset = 0x7c;
f49639e6 13300 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13301 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13302 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13303 mac_offset = 0xcc;
13304 if (tg3_nvram_lock(tp))
13305 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13306 else
13307 tg3_nvram_unlock(tp);
a1b950d5
MC		 13308 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13309 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13310 mac_offset = 0xcc;
13311 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13312 mac_offset = 0x10;
1da177e4
LT		 13313
13314 /* First try to get it from MAC address mailbox. */
13315 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13316 if ((hi >> 16) == 0x484b) {
13317 dev->dev_addr[0] = (hi >> 8) & 0xff;
13318 dev->dev_addr[1] = (hi >> 0) & 0xff;
13319
13320 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13321 dev->dev_addr[2] = (lo >> 24) & 0xff;
13322 dev->dev_addr[3] = (lo >> 16) & 0xff;
13323 dev->dev_addr[4] = (lo >> 8) & 0xff;
13324 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13325
008652b3
MC		 13326 /* Some old bootcode may report a 0 MAC address in SRAM */
13327 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13328 }
13329 if (!addr_ok) {
13330 /* Next, try NVRAM. */
df259d8c
MC		 13331 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13332 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13333 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13334 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13335 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13336 }
13337 /* Finally just fetch it out of the MAC control regs. */
13338 else {
13339 hi = tr32(MAC_ADDR_0_HIGH);
13340 lo = tr32(MAC_ADDR_0_LOW);
13341
13342 dev->dev_addr[5] = lo & 0xff;
13343 dev->dev_addr[4] = (lo >> 8) & 0xff;
13344 dev->dev_addr[3] = (lo >> 16) & 0xff;
13345 dev->dev_addr[2] = (lo >> 24) & 0xff;
13346 dev->dev_addr[1] = hi & 0xff;
13347 dev->dev_addr[0] = (hi >> 8) & 0xff;
13348 }
1da177e4
LT		 13349 }
13350
13351 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13352#ifdef CONFIG_SPARC
1da177e4
LT		 13353 if (!tg3_get_default_macaddr_sparc(tp))
13354 return 0;
13355#endif
13356 return -EINVAL;
13357 }
2ff43697 13358 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13359 return 0;
13360}
13361
59e6b434
DM		 13362#define BOUNDARY_SINGLE_CACHELINE 1
13363#define BOUNDARY_MULTI_CACHELINE 2
13364
13365static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13366{
13367 int cacheline_size;
13368 u8 byte;
13369 int goal;
13370
13371 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13372 if (byte == 0)
13373 cacheline_size = 1024;
13374 else
13375 cacheline_size = (int) byte * 4;
13376
13377 /* On 5703 and later chips, the boundary bits have no
13378 * effect.
13379 */
13380 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13381 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13382 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13383 goto out;
13384
13385#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13386 goal = BOUNDARY_MULTI_CACHELINE;
13387#else
13388#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13389 goal = BOUNDARY_SINGLE_CACHELINE;
13390#else
13391 goal = 0;
13392#endif
13393#endif
13394
cbf9ca6c
MC		 13395 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13396 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13397 goto out;
13398 }
13399
59e6b434
DM		 13400 if (!goal)
13401 goto out;
13402
13403 /* PCI controllers on most RISC systems tend to disconnect
13404 * when a device tries to burst across a cache-line boundary.
13405 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13406 *
13407 * Unfortunately, for PCI-E there are only limited
13408 * write-side controls for this, and thus for reads
13409 * we will still get the disconnects. We'll also waste
13410 * these PCI cycles for both read and write for chips
13411 * other than 5700 and 5701 which do not implement the
13412 * boundary bits.
13413 */
13414 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13415 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13416 switch (cacheline_size) {
13417 case 16:
13418 case 32:
13419 case 64:
13420 case 128:
13421 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13422 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13423 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13424 } else {
13425 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13426 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13427 }
13428 break;
13429
13430 case 256:
13431 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13432 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13433 break;
13434
13435 default:
13436 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13437 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13438 break;
855e1111 13439 }
59e6b434
DM		 13440 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13441 switch (cacheline_size) {
13442 case 16:
13443 case 32:
13444 case 64:
13445 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13446 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13447 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13448 break;
13449 }
13450 /* fallthrough */
13451 case 128:
13452 default:
13453 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13454 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13455 break;
855e1111 13456 }
59e6b434
DM		 13457 } else {
13458 switch (cacheline_size) {
13459 case 16:
13460 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13461 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13462 DMA_RWCTRL_WRITE_BNDRY_16);
13463 break;
13464 }
13465 /* fallthrough */
13466 case 32:
13467 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13468 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13469 DMA_RWCTRL_WRITE_BNDRY_32);
13470 break;
13471 }
13472 /* fallthrough */
13473 case 64:
13474 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13475 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13476 DMA_RWCTRL_WRITE_BNDRY_64);
13477 break;
13478 }
13479 /* fallthrough */
13480 case 128:
13481 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13482 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13483 DMA_RWCTRL_WRITE_BNDRY_128);
13484 break;
13485 }
13486 /* fallthrough */
13487 case 256:
13488 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13489 DMA_RWCTRL_WRITE_BNDRY_256);
13490 break;
13491 case 512:
13492 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13493 DMA_RWCTRL_WRITE_BNDRY_512);
13494 break;
13495 case 1024:
13496 default:
13497 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13498 DMA_RWCTRL_WRITE_BNDRY_1024);
13499 break;
855e1111 13500 }
59e6b434
DM		 13501 }
13502
13503out:
13504 return val;
13505}
13506
1da177e4
LT		 13507static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13508{
13509 struct tg3_internal_buffer_desc test_desc;
13510 u32 sram_dma_descs;
13511 int i, ret;
13512
13513 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13514
13515 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13516 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13517 tw32(RDMAC_STATUS, 0);
13518 tw32(WDMAC_STATUS, 0);
13519
13520 tw32(BUFMGR_MODE, 0);
13521 tw32(FTQ_RESET, 0);
13522
13523 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13524 test_desc.addr_lo = buf_dma & 0xffffffff;
13525 test_desc.nic_mbuf = 0x00002100;
13526 test_desc.len = size;
13527
13528 /*
13529 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13530 * the *second* time the tg3 driver was getting loaded after an
13531 * initial scan.
13532 *
13533 * Broadcom tells me:
13534 * ...the DMA engine is connected to the GRC block and a DMA
13535 * reset may affect the GRC block in some unpredictable way...
13536 * The behavior of resets to individual blocks has not been tested.
13537 *
13538 * Broadcom noted the GRC reset will also reset all sub-components.
13539 */
13540 if (to_device) {
13541 test_desc.cqid_sqid = (13 << 8) | 2;
13542
13543 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13544 udelay(40);
13545 } else {
13546 test_desc.cqid_sqid = (16 << 8) | 7;
13547
13548 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13549 udelay(40);
13550 }
13551 test_desc.flags = 0x00000005;
13552
13553 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13554 u32 val;
13555
13556 val = *(((u32 *)&test_desc) + i);
13557 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13558 sram_dma_descs + (i * sizeof(u32)));
13559 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13560 }
13561 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13562
13563 if (to_device) {
13564 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13565 } else {
13566 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13567 }
13568
13569 ret = -ENODEV;
13570 for (i = 0; i < 40; i++) {
13571 u32 val;
13572
13573 if (to_device)
13574 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13575 else
13576 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13577 if ((val & 0xffff) == sram_dma_descs) {
13578 ret = 0;
13579 break;
13580 }
13581
13582 udelay(100);
13583 }
13584
13585 return ret;
13586}
13587
ded7340d 13588#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13589
13590static int __devinit tg3_test_dma(struct tg3 *tp)
13591{
13592 dma_addr_t buf_dma;
59e6b434 13593 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 13594 int ret = 0;
1da177e4
LT		 13595
13596 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13597 if (!buf) {
13598 ret = -ENOMEM;
13599 goto out_nofree;
13600 }
13601
13602 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13603 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13604
59e6b434 13605 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 13606
cbf9ca6c
MC		 13607 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13608 goto out;
13609
1da177e4
LT		 13610 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13611 /* DMA read watermark not used on PCIE */
13612 tp->dma_rwctrl |= 0x00180000;
13613 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13614 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13615 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13616 tp->dma_rwctrl |= 0x003f0000;
13617 else
13618 tp->dma_rwctrl |= 0x003f000f;
13619 } else {
13620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13621 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13622 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13623 u32 read_water = 0x7;
1da177e4 13624
4a29cc2e
MC		 13625 /* If the 5704 is behind the EPB bridge, we can
13626 * do the less restrictive ONE_DMA workaround for
13627 * better performance.
13628 */
13629 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13631 tp->dma_rwctrl |= 0x8000;
13632 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13633 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13634
49afdeb6
MC		 13635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13636 read_water = 4;
59e6b434 13637 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13638 tp->dma_rwctrl |=
13639 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13640 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13641 (1 << 23);
4cf78e4f
MC		 13642 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13643 /* 5780 always in PCIX mode */
13644 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13645 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13646 /* 5714 always in PCIX mode */
13647 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13648 } else {
13649 tp->dma_rwctrl |= 0x001b000f;
13650 }
13651 }
13652
13653 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13654 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13655 tp->dma_rwctrl &= 0xfffffff0;
13656
13657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13658 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13659 /* Remove this if it causes problems for some boards. */
13660 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13661
13662 /* On 5700/5701 chips, we need to set this bit.
13663 * Otherwise the chip will issue cacheline transactions
13664 * to streamable DMA memory with not all the byte
13665 * enables turned on. This is an error on several
13666 * RISC PCI controllers, in particular sparc64.
13667 *
13668 * On 5703/5704 chips, this bit has been reassigned
13669 * a different meaning. In particular, it is used
13670 * on those chips to enable a PCI-X workaround.
13671 */
13672 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13673 }
13674
13675 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13676
13677#if 0
13678 /* Unneeded, already done by tg3_get_invariants. */
13679 tg3_switch_clocks(tp);
13680#endif
13681
1da177e4
LT		 13682 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13683 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13684 goto out;
13685
59e6b434
DM		 13686 /* It is best to perform DMA test with maximum write burst size
13687 * to expose the 5700/5701 write DMA bug.
13688 */
13689 saved_dma_rwctrl = tp->dma_rwctrl;
13690 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13691 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13692
1da177e4
LT		 13693 while (1) {
13694 u32 *p = buf, i;
13695
13696 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13697 p[i] = i;
13698
13699 /* Send the buffer to the chip. */
13700 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13701 if (ret) {
13702 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13703 break;
13704 }
13705
13706#if 0
13707 /* validate data reached card RAM correctly. */
13708 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13709 u32 val;
13710 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13711 if (le32_to_cpu(val) != p[i]) {
13712 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13713 /* ret = -ENODEV here? */
13714 }
13715 p[i] = 0;
13716 }
13717#endif
13718 /* Now read it back. */
13719 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13720 if (ret) {
13721 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13722
13723 break;
13724 }
13725
13726 /* Verify it. */
13727 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13728 if (p[i] == i)
13729 continue;
13730
59e6b434
DM		 13731 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13732 DMA_RWCTRL_WRITE_BNDRY_16) {
13733 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13734 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13735 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13736 break;
13737 } else {
13738 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13739 ret = -ENODEV;
13740 goto out;
13741 }
13742 }
13743
13744 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13745 /* Success. */
13746 ret = 0;
13747 break;
13748 }
13749 }
59e6b434
DM		 13750 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13751 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13752 static struct pci_device_id dma_wait_state_chipsets[] = {
13753 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13754 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13755 { },
13756 };
13757
59e6b434 13758 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13759 * now look for chipsets that are known to expose the
13760 * DMA bug without failing the test.
59e6b434 13761 */
6d1cfbab
MC		 13762 if (pci_dev_present(dma_wait_state_chipsets)) {
13763 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13764 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13765 }
13766 else
13767 /* Safe to use the calculated DMA boundary. */
13768 tp->dma_rwctrl = saved_dma_rwctrl;
13769
59e6b434
DM		 13770 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13771 }
1da177e4
LT		 13772
13773out:
13774 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13775out_nofree:
13776 return ret;
13777}
13778
13779static void __devinit tg3_init_link_config(struct tg3 *tp)
13780{
13781 tp->link_config.advertising =
13782 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13783 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13784 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13785 ADVERTISED_Autoneg | ADVERTISED_MII);
13786 tp->link_config.speed = SPEED_INVALID;
13787 tp->link_config.duplex = DUPLEX_INVALID;
13788 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13789 tp->link_config.active_speed = SPEED_INVALID;
13790 tp->link_config.active_duplex = DUPLEX_INVALID;
13791 tp->link_config.phy_is_low_power = 0;
13792 tp->link_config.orig_speed = SPEED_INVALID;
13793 tp->link_config.orig_duplex = DUPLEX_INVALID;
13794 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13795}
13796
13797static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13798{
f6eb9b1f
MC		 13799 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13800 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13801 tp->bufmgr_config.mbuf_read_dma_low_water =
13802 DEFAULT_MB_RDMA_LOW_WATER_5705;
13803 tp->bufmgr_config.mbuf_mac_rx_low_water =
13804 DEFAULT_MB_MACRX_LOW_WATER_5705;
13805 tp->bufmgr_config.mbuf_high_water =
13806 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13808 tp->bufmgr_config.mbuf_mac_rx_low_water =
13809 DEFAULT_MB_MACRX_LOW_WATER_5906;
13810 tp->bufmgr_config.mbuf_high_water =
13811 DEFAULT_MB_HIGH_WATER_5906;
13812 }
fdfec172
MC		 13813
13814 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13815 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13816 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13817 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13818 tp->bufmgr_config.mbuf_high_water_jumbo =
13819 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13820 } else {
13821 tp->bufmgr_config.mbuf_read_dma_low_water =
13822 DEFAULT_MB_RDMA_LOW_WATER;
13823 tp->bufmgr_config.mbuf_mac_rx_low_water =
13824 DEFAULT_MB_MACRX_LOW_WATER;
13825 tp->bufmgr_config.mbuf_high_water =
13826 DEFAULT_MB_HIGH_WATER;
13827
13828 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13829 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13830 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13831 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13832 tp->bufmgr_config.mbuf_high_water_jumbo =
13833 DEFAULT_MB_HIGH_WATER_JUMBO;
13834 }
1da177e4
LT		 13835
13836 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13837 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13838}
13839
13840static char * __devinit tg3_phy_string(struct tg3 *tp)
13841{
13842 switch (tp->phy_id & PHY_ID_MASK) {
13843 case PHY_ID_BCM5400: return "5400";
13844 case PHY_ID_BCM5401: return "5401";
13845 case PHY_ID_BCM5411: return "5411";
13846 case PHY_ID_BCM5701: return "5701";
13847 case PHY_ID_BCM5703: return "5703";
13848 case PHY_ID_BCM5704: return "5704";
13849 case PHY_ID_BCM5705: return "5705";
13850 case PHY_ID_BCM5750: return "5750";
85e94ced 13851 case PHY_ID_BCM5752: return "5752";
a4e2b347 13852 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13853 case PHY_ID_BCM5780: return "5780";
af36e6b6 13854 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13855 case PHY_ID_BCM5787: return "5787";
d30cdd28 13856 case PHY_ID_BCM5784: return "5784";
126a3368 13857 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13858 case PHY_ID_BCM5906: return "5906";
9936bcf6 13859 case PHY_ID_BCM5761: return "5761";
c2060fe1 13860 case PHY_ID_BCM5717: return "5717";
1da177e4
LT		 13861 case PHY_ID_BCM8002: return "8002/serdes";
13862 case 0: return "serdes";
13863 default: return "unknown";
855e1111 13864 }
1da177e4
LT		 13865}
13866
f9804ddb
MC		 13867static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13868{
13869 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13870 strcpy(str, "PCI Express");
13871 return str;
13872 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13873 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13874
13875 strcpy(str, "PCIX:");
13876
13877 if ((clock_ctrl == 7) ||
13878 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13879 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13880 strcat(str, "133MHz");
13881 else if (clock_ctrl == 0)
13882 strcat(str, "33MHz");
13883 else if (clock_ctrl == 2)
13884 strcat(str, "50MHz");
13885 else if (clock_ctrl == 4)
13886 strcat(str, "66MHz");
13887 else if (clock_ctrl == 6)
13888 strcat(str, "100MHz");
f9804ddb
MC		 13889 } else {
13890 strcpy(str, "PCI:");
13891 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13892 strcat(str, "66MHz");
13893 else
13894 strcat(str, "33MHz");
13895 }
13896 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13897 strcat(str, ":32-bit");
13898 else
13899 strcat(str, ":64-bit");
13900 return str;
13901}
13902
8c2dc7e1 13903static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13904{
13905 struct pci_dev *peer;
13906 unsigned int func, devnr = tp->pdev->devfn & ~7;
13907
13908 for (func = 0; func < 8; func++) {
13909 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13910 if (peer && peer != tp->pdev)
13911 break;
13912 pci_dev_put(peer);
13913 }
16fe9d74
MC		 13914 /* 5704 can be configured in single-port mode, set peer to
13915 * tp->pdev in that case.
13916 */
13917 if (!peer) {
13918 peer = tp->pdev;
13919 return peer;
13920 }
1da177e4
LT		 13921
13922 /*
13923 * We don't need to keep the refcount elevated; there's no way
13924 * to remove one half of this device without removing the other
13925 */
13926 pci_dev_put(peer);
13927
13928 return peer;
13929}
13930
15f9850d
DM		 13931static void __devinit tg3_init_coal(struct tg3 *tp)
13932{
13933 struct ethtool_coalesce *ec = &tp->coal;
13934
13935 memset(ec, 0, sizeof(*ec));
13936 ec->cmd = ETHTOOL_GCOALESCE;
13937 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13938 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13939 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13940 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13941 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13942 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13943 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13944 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13945 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13946
13947 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13948 HOSTCC_MODE_CLRTICK_TXBD)) {
13949 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13950 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13951 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13952 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13953 }
d244c892
MC		 13954
13955 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13956 ec->rx_coalesce_usecs_irq = 0;
13957 ec->tx_coalesce_usecs_irq = 0;
13958 ec->stats_block_coalesce_usecs = 0;
13959 }
15f9850d
DM		 13960}
13961
7c7d64b8
SH		 13962static const struct net_device_ops tg3_netdev_ops = {
13963 .ndo_open = tg3_open,
13964 .ndo_stop = tg3_close,
00829823
SH		 13965 .ndo_start_xmit = tg3_start_xmit,
13966 .ndo_get_stats = tg3_get_stats,
13967 .ndo_validate_addr = eth_validate_addr,
13968 .ndo_set_multicast_list = tg3_set_rx_mode,
13969 .ndo_set_mac_address = tg3_set_mac_addr,
13970 .ndo_do_ioctl = tg3_ioctl,
13971 .ndo_tx_timeout = tg3_tx_timeout,
13972 .ndo_change_mtu = tg3_change_mtu,
13973#if TG3_VLAN_TAG_USED
13974 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13975#endif
13976#ifdef CONFIG_NET_POLL_CONTROLLER
13977 .ndo_poll_controller = tg3_poll_controller,
13978#endif
13979};
13980
13981static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13982 .ndo_open = tg3_open,
13983 .ndo_stop = tg3_close,
13984 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13985 .ndo_get_stats = tg3_get_stats,
13986 .ndo_validate_addr = eth_validate_addr,
13987 .ndo_set_multicast_list = tg3_set_rx_mode,
13988 .ndo_set_mac_address = tg3_set_mac_addr,
13989 .ndo_do_ioctl = tg3_ioctl,
13990 .ndo_tx_timeout = tg3_tx_timeout,
13991 .ndo_change_mtu = tg3_change_mtu,
13992#if TG3_VLAN_TAG_USED
13993 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13994#endif
13995#ifdef CONFIG_NET_POLL_CONTROLLER
13996 .ndo_poll_controller = tg3_poll_controller,
13997#endif
13998};
13999
1da177e4
LT		 14000static int __devinit tg3_init_one(struct pci_dev *pdev,
14001 const struct pci_device_id *ent)
14002{
14003 static int tg3_version_printed = 0;
1da177e4
LT		 14004 struct net_device *dev;
14005 struct tg3 *tp;
646c9edd
MC		 14006 int i, err, pm_cap;
14007 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 14008 char str[40];
72f2afb8 14009 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 14010
14011 if (tg3_version_printed++ == 0)
14012 printk(KERN_INFO "%s", version);
14013
14014 err = pci_enable_device(pdev);
14015 if (err) {
14016 printk(KERN_ERR PFX "Cannot enable PCI device, "
14017 "aborting.\n");
14018 return err;
14019 }
14020
1da177e4
LT		 14021 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14022 if (err) {
14023 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14024 "aborting.\n");
14025 goto err_out_disable_pdev;
14026 }
14027
14028 pci_set_master(pdev);
14029
14030 /* Find power-management capability. */
14031 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14032 if (pm_cap == 0) {
14033 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14034 "aborting.\n");
14035 err = -EIO;
14036 goto err_out_free_res;
14037 }
14038
fe5f5787 14039 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 14040 if (!dev) {
14041 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14042 err = -ENOMEM;
14043 goto err_out_free_res;
14044 }
14045
1da177e4
LT		 14046 SET_NETDEV_DEV(dev, &pdev->dev);
14047
1da177e4
LT		 14048#if TG3_VLAN_TAG_USED
14049 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 14050#endif
14051
14052 tp = netdev_priv(dev);
14053 tp->pdev = pdev;
14054 tp->dev = dev;
14055 tp->pm_cap = pm_cap;
1da177e4
LT		 14056 tp->rx_mode = TG3_DEF_RX_MODE;
14057 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 14058
1da177e4
LT		 14059 if (tg3_debug > 0)
14060 tp->msg_enable = tg3_debug;
14061 else
14062 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14063
14064 /* The word/byte swap controls here control register access byte
14065 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14066 * setting below.
14067 */
14068 tp->misc_host_ctrl =
14069 MISC_HOST_CTRL_MASK_PCI_INT |
14070 MISC_HOST_CTRL_WORD_SWAP |
14071 MISC_HOST_CTRL_INDIR_ACCESS |
14072 MISC_HOST_CTRL_PCISTATE_RW;
14073
14074 /* The NONFRM (non-frame) byte/word swap controls take effect
14075 * on descriptor entries, anything which isn't packet data.
14076 *
14077 * The StrongARM chips on the board (one for tx, one for rx)
14078 * are running in big-endian mode.
14079 */
14080 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14081 GRC_MODE_WSWAP_NONFRM_DATA);
14082#ifdef __BIG_ENDIAN
14083 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14084#endif
14085 spin_lock_init(&tp->lock);
1da177e4 14086 spin_lock_init(&tp->indirect_lock);
c4028958 14087 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 14088
d5fe488a 14089 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 14090 if (!tp->regs) {
1da177e4
LT		 14091 printk(KERN_ERR PFX "Cannot map device registers, "
14092 "aborting.\n");
14093 err = -ENOMEM;
14094 goto err_out_free_dev;
14095 }
14096
14097 tg3_init_link_config(tp);
14098
1da177e4
LT		 14099 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14100 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14101
1da177e4 14102 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14103 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14104 dev->irq = pdev->irq;
1da177e4
LT		 14105
14106 err = tg3_get_invariants(tp);
14107 if (err) {
14108 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14109 "aborting.\n");
14110 goto err_out_iounmap;
14111 }
14112
615774fe
MC		 14113 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14114 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00829823
SH		 14115 dev->netdev_ops = &tg3_netdev_ops;
14116 else
14117 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14118
14119
4a29cc2e
MC		 14120 /* The EPB bridge inside 5714, 5715, and 5780 and any
14121 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14122 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14123 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14124 * do DMA address check in tg3_start_xmit().
14125 */
4a29cc2e 14126 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14127 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14128 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14129 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14130#ifdef CONFIG_HIGHMEM
6a35528a 14131 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14132#endif
4a29cc2e 14133 } else
6a35528a 14134 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14135
14136 /* Configure DMA attributes. */
284901a9 14137 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14138 err = pci_set_dma_mask(pdev, dma_mask);
14139 if (!err) {
14140 dev->features |= NETIF_F_HIGHDMA;
14141 err = pci_set_consistent_dma_mask(pdev,
14142 persist_dma_mask);
14143 if (err < 0) {
14144 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14145 "DMA for consistent allocations\n");
14146 goto err_out_iounmap;
14147 }
14148 }
14149 }
284901a9
YH		 14150 if (err || dma_mask == DMA_BIT_MASK(32)) {
14151 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14152 if (err) {
14153 printk(KERN_ERR PFX "No usable DMA configuration, "
14154 "aborting.\n");
14155 goto err_out_iounmap;
14156 }
14157 }
14158
fdfec172 14159 tg3_init_bufmgr_config(tp);
1da177e4 14160
507399f1
MC		 14161 /* Selectively allow TSO based on operating conditions */
14162 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14163 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
1da177e4 14164 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
507399f1
MC		 14165 else {
14166 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14167 tp->fw_needed = NULL;
1da177e4 14168 }
507399f1
MC		 14169
14170 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14171 tp->fw_needed = FIRMWARE_TG3;
1da177e4 14172
4e3a7aaa
MC		 14173 /* TSO is on by default on chips that support hardware TSO.
14174 * Firmware TSO on older chips gives lower performance, so it
14175 * is off by default, but can be enabled using ethtool.
14176 */
e849cdc3
MC		 14177 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14178 (dev->features & NETIF_F_IP_CSUM))
14179 dev->features |= NETIF_F_TSO;
14180
14181 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14182 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14183 if (dev->features & NETIF_F_IPV6_CSUM)
b0026624 14184 dev->features |= NETIF_F_TSO6;
e849cdc3
MC		 14185 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14186 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c
MC		 14187 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14188 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
e849cdc3 14190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936bcf6 14191 dev->features |= NETIF_F_TSO_ECN;
b0026624 14192 }
1da177e4 14193
1da177e4
LT		 14194 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14195 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14196 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14197 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14198 tp->rx_pending = 63;
14199 }
14200
1da177e4
LT		 14201 err = tg3_get_device_address(tp);
14202 if (err) {
14203 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14204 "aborting.\n");
077f849d 14205 goto err_out_fw;
1da177e4
LT		 14206 }
14207
c88864df 14208 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14209 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14210 if (!tp->aperegs) {
c88864df
MC		 14211 printk(KERN_ERR PFX "Cannot map APE registers, "
14212 "aborting.\n");
14213 err = -ENOMEM;
077f849d 14214 goto err_out_fw;
c88864df
MC		 14215 }
14216
14217 tg3_ape_lock_init(tp);
7fd76445
MC		 14218
14219 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14220 tg3_read_dash_ver(tp);
c88864df
MC		 14221 }
14222
1da177e4
LT		 14223 /*
14224 * Reset chip in case UNDI or EFI driver did not shutdown
14225 * DMA self test will enable WDMAC and we'll see (spurious)
14226 * pending DMA on the PCI bus at that point.
14227 */
14228 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14229 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14230 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14231 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14232 }
14233
14234 err = tg3_test_dma(tp);
14235 if (err) {
14236 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14237 goto err_out_apeunmap;
1da177e4
LT		 14238 }
14239
1da177e4
LT		 14240 /* flow control autonegotiation is default behavior */
14241 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14242 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14243
78f90dcf
MC		 14244 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14245 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14246 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14247 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14248 struct tg3_napi *tnapi = &tp->napi[i];
14249
14250 tnapi->tp = tp;
14251 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14252
14253 tnapi->int_mbox = intmbx;
14254 if (i < 4)
14255 intmbx += 0x8;
14256 else
14257 intmbx += 0x4;
14258
14259 tnapi->consmbox = rcvmbx;
14260 tnapi->prodmbox = sndmbx;
14261
14262 if (i) {
14263 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14264 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14265 } else {
14266 tnapi->coal_now = HOSTCC_MODE_NOW;
14267 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14268 }
14269
14270 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14271 break;
14272
14273 /*
14274 * If we support MSIX, we'll be using RSS. If we're using
14275 * RSS, the first vector only handles link interrupts and the
14276 * remaining vectors handle rx and tx interrupts. Reuse the
14277 * mailbox values for the next iteration. The values we setup
14278 * above are still useful for the single vectored mode.
14279 */
14280 if (!i)
14281 continue;
14282
14283 rcvmbx += 0x8;
14284
14285 if (sndmbx & 0x4)
14286 sndmbx -= 0x4;
14287 else
14288 sndmbx += 0xc;
14289 }
14290
15f9850d
DM		 14291 tg3_init_coal(tp);
14292
c49a1561
MC		 14293 pci_set_drvdata(pdev, dev);
14294
1da177e4
LT		 14295 err = register_netdev(dev);
14296 if (err) {
14297 printk(KERN_ERR PFX "Cannot register net device, "
14298 "aborting.\n");
0d3031d9 14299 goto err_out_apeunmap;
1da177e4
LT		 14300 }
14301
df59c940 14302 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14303 dev->name,
14304 tp->board_part_number,
14305 tp->pci_chip_rev_id,
f9804ddb 14306 tg3_bus_string(tp, str),
e174961c 14307 dev->dev_addr);
1da177e4 14308
3f0e3ad7
MC		 14309 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14310 struct phy_device *phydev;
14311 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14312 printk(KERN_INFO
14313 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14314 tp->dev->name, phydev->drv->name,
14315 dev_name(&phydev->dev));
14316 } else
df59c940
MC		 14317 printk(KERN_INFO
14318 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14319 tp->dev->name, tg3_phy_string(tp),
14320 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14321 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14322 "10/100/1000Base-T")),
14323 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14324
14325 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14326 dev->name,
14327 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14328 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14329 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14330 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14331 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14332 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14333 dev->name, tp->dma_rwctrl,
284901a9 14334 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14335 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14336
14337 return 0;
14338
0d3031d9
MC		 14339err_out_apeunmap:
14340 if (tp->aperegs) {
14341 iounmap(tp->aperegs);
14342 tp->aperegs = NULL;
14343 }
14344
077f849d
JSR		 14345err_out_fw:
14346 if (tp->fw)
14347 release_firmware(tp->fw);
14348
1da177e4 14349err_out_iounmap:
6892914f
MC		 14350 if (tp->regs) {
14351 iounmap(tp->regs);
22abe310 14352 tp->regs = NULL;
6892914f 14353 }
1da177e4
LT		 14354
14355err_out_free_dev:
14356 free_netdev(dev);
14357
14358err_out_free_res:
14359 pci_release_regions(pdev);
14360
14361err_out_disable_pdev:
14362 pci_disable_device(pdev);
14363 pci_set_drvdata(pdev, NULL);
14364 return err;
14365}
14366
14367static void __devexit tg3_remove_one(struct pci_dev *pdev)
14368{
14369 struct net_device *dev = pci_get_drvdata(pdev);
14370
14371 if (dev) {
14372 struct tg3 *tp = netdev_priv(dev);
14373
077f849d
JSR		 14374 if (tp->fw)
14375 release_firmware(tp->fw);
14376
7faa006f 14377 flush_scheduled_work();
158d7abd 14378
b02fd9e3
MC		 14379 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14380 tg3_phy_fini(tp);
158d7abd 14381 tg3_mdio_fini(tp);
b02fd9e3 14382 }
158d7abd 14383
1da177e4 14384 unregister_netdev(dev);
0d3031d9
MC		 14385 if (tp->aperegs) {
14386 iounmap(tp->aperegs);
14387 tp->aperegs = NULL;
14388 }
6892914f
MC		 14389 if (tp->regs) {
14390 iounmap(tp->regs);
22abe310 14391 tp->regs = NULL;
6892914f 14392 }
1da177e4
LT		 14393 free_netdev(dev);
14394 pci_release_regions(pdev);
14395 pci_disable_device(pdev);
14396 pci_set_drvdata(pdev, NULL);
14397 }
14398}
14399
14400static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14401{
14402 struct net_device *dev = pci_get_drvdata(pdev);
14403 struct tg3 *tp = netdev_priv(dev);
12dac075 14404 pci_power_t target_state;
1da177e4
LT		 14405 int err;
14406
3e0c95fd
MC		 14407 /* PCI register 4 needs to be saved whether netif_running() or not.
14408 * MSI address and data need to be saved if using MSI and
14409 * netif_running().
14410 */
14411 pci_save_state(pdev);
14412
1da177e4
LT		 14413 if (!netif_running(dev))
14414 return 0;
14415
7faa006f 14416 flush_scheduled_work();
b02fd9e3 14417 tg3_phy_stop(tp);
1da177e4
LT		 14418 tg3_netif_stop(tp);
14419
14420 del_timer_sync(&tp->timer);
14421
f47c11ee 14422 tg3_full_lock(tp, 1);
1da177e4 14423 tg3_disable_ints(tp);
f47c11ee 14424 tg3_full_unlock(tp);
1da177e4
LT		 14425
14426 netif_device_detach(dev);
14427
f47c11ee 14428 tg3_full_lock(tp, 0);
944d980e 14429 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14430 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14431 tg3_full_unlock(tp);
1da177e4 14432
12dac075
RW		 14433 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14434
14435 err = tg3_set_power_state(tp, target_state);
1da177e4 14436 if (err) {
b02fd9e3
MC		 14437 int err2;
14438
f47c11ee 14439 tg3_full_lock(tp, 0);
1da177e4 14440
6a9eba15 14441 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14442 err2 = tg3_restart_hw(tp, 1);
14443 if (err2)
b9ec6c1b 14444 goto out;
1da177e4
LT		 14445
14446 tp->timer.expires = jiffies + tp->timer_offset;
14447 add_timer(&tp->timer);
14448
14449 netif_device_attach(dev);
14450 tg3_netif_start(tp);
14451
b9ec6c1b 14452out:
f47c11ee 14453 tg3_full_unlock(tp);
b02fd9e3
MC		 14454
14455 if (!err2)
14456 tg3_phy_start(tp);
1da177e4
LT		 14457 }
14458
14459 return err;
14460}
14461
14462static int tg3_resume(struct pci_dev *pdev)
14463{
14464 struct net_device *dev = pci_get_drvdata(pdev);
14465 struct tg3 *tp = netdev_priv(dev);
14466 int err;
14467
3e0c95fd
MC		 14468 pci_restore_state(tp->pdev);
14469
1da177e4
LT		 14470 if (!netif_running(dev))
14471 return 0;
14472
bc1c7567 14473 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14474 if (err)
14475 return err;
14476
14477 netif_device_attach(dev);
14478
f47c11ee 14479 tg3_full_lock(tp, 0);
1da177e4 14480
6a9eba15 14481 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14482 err = tg3_restart_hw(tp, 1);
14483 if (err)
14484 goto out;
1da177e4
LT		 14485
14486 tp->timer.expires = jiffies + tp->timer_offset;
14487 add_timer(&tp->timer);
14488
1da177e4
LT		 14489 tg3_netif_start(tp);
14490
b9ec6c1b 14491out:
f47c11ee 14492 tg3_full_unlock(tp);
1da177e4 14493
b02fd9e3
MC		 14494 if (!err)
14495 tg3_phy_start(tp);
14496
b9ec6c1b 14497 return err;
1da177e4
LT		 14498}
14499
14500static struct pci_driver tg3_driver = {
14501 .name = DRV_MODULE_NAME,
14502 .id_table = tg3_pci_tbl,
14503 .probe = tg3_init_one,
14504 .remove = __devexit_p(tg3_remove_one),
14505 .suspend = tg3_suspend,
14506 .resume = tg3_resume
14507};
14508
14509static int __init tg3_init(void)
14510{
29917620 14511 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14512}
14513
14514static void __exit tg3_cleanup(void)
14515{
14516 pci_unregister_driver(&tg3_driver);
14517}
14518
14519module_init(tg3_init);
14520module_exit(tg3_cleanup);
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