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tg3: Don't touch RCB nic addresses
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
0d2a5068 7 * Copyright (C) 2005-2009 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/compiler.h>
24#include <linux/slab.h>
25#include <linux/delay.h>
14c85021 26#include <linux/in.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
158d7abd 35#include <linux/phy.h>
a9daf367 36#include <linux/brcmphy.h>
1da177e4
LT		 37#include <linux/if_vlan.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/workqueue.h>
61487480 41#include <linux/prefetch.h>
f9a5f7d3 42#include <linux/dma-mapping.h>
077f849d 43#include <linux/firmware.h>
1da177e4
LT		 44
45#include <net/checksum.h>
c9bdd4b5 46#include <net/ip.h>
1da177e4
LT		 47
48#include <asm/system.h>
49#include <asm/io.h>
50#include <asm/byteorder.h>
51#include <asm/uaccess.h>
52
49b6e95f 53#ifdef CONFIG_SPARC
1da177e4 54#include <asm/idprom.h>
49b6e95f 55#include <asm/prom.h>
1da177e4
LT		 56#endif
57
63532394
MC		 58#define BAR_0 0
59#define BAR_2 2
60
1da177e4
LT		 61#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62#define TG3_VLAN_TAG_USED 1
63#else
64#define TG3_VLAN_TAG_USED 0
65#endif
66
1da177e4
LT		 67#include "tg3.h"
68
69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": "
123b43e9
MC		 71#define DRV_MODULE_VERSION "3.103"
72#define DRV_MODULE_RELDATE "November 2, 2009"
1da177e4
LT		 73
74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0
76#define TG3_DEF_TX_MODE 0
77#define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87/* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90#define TG3_TX_TIMEOUT (5 * HZ)
91
92/* hardware minimum and maximum for a single frame's data payload */
93#define TG3_MIN_MTU 60
94#define TG3_MAX_MTU(tp) \
8f666b07 95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 96
97/* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101#define TG3_RX_RING_SIZE 512
102#define TG3_DEF_RX_RING_PENDING 200
103#define TG3_RX_JUMBO_RING_SIZE 256
104#define TG3_DEF_RX_JUMBO_RING_PENDING 100
baf8a94a 105#define TG3_RSS_INDIR_TBL_SIZE 128
1da177e4
LT		 106
107/* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113#define TG3_RX_RCB_RING_SIZE(tp) \
f6eb9b1f 114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
5ea1c506 115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
1da177e4
LT		 116
117#define TG3_TX_RING_SIZE 512
118#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
79ed5ac7
MC		 122#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
1da177e4 124#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
79ed5ac7 125 TG3_RX_RCB_RING_SIZE(tp))
1da177e4
LT		 126#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
1da177e4
LT		 128#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
287be12e
MC		 130#define TG3_DMA_BYTE_ENAB 64
131
132#define TG3_RX_STD_DMA_SZ 1536
133#define TG3_RX_JMB_DMA_SZ 9046
134
135#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4
LT		 139
140/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 141#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
1da177e4 142
ad829268
MC		 143#define TG3_RAW_IP_ALIGN 2
144
1da177e4
LT		 145/* number of ETHTOOL_GSTATS u64's */
146#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
4cafd3f5
MC		 148#define TG3_NUM_TEST 6
149
077f849d
JSR		 150#define FIRMWARE_TG3 "tigon/tg3.bin"
151#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
1da177e4
LT		 154static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 161MODULE_FIRMWARE(FIRMWARE_TG3);
162MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
679563f4 165#define TG3_RSS_MIN_NUM_MSIX_VECS 2
1da177e4
LT		 166
167static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168module_param(tg3_debug, int, 0);
169MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171static struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
13185217
HK		 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
676917d4 215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
13185217
HK		 216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321d32a0
MC		 234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
5e7ccf20 237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
1da177e4
LT		 246};
247
248MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
50da859d 250static const struct {
1da177e4
LT		 251 const char string[ETH_GSTRING_LEN];
252} ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329};
330
50da859d 331static const struct {
4cafd3f5
MC		 332 const char string[ETH_GSTRING_LEN];
333} ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340};
341
b401e9e2
MC		 342static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343{
344 writel(val, tp->regs + off);
345}
346
347static u32 tg3_read32(struct tg3 *tp, u32 off)
348{
6aa20a22 349 return (readl(tp->regs + off));
b401e9e2
MC		 350}
351
0d3031d9
MC		 352static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353{
354 writel(val, tp->aperegs + off);
355}
356
357static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358{
359 return (readl(tp->aperegs + off));
360}
361
1da177e4
LT		 362static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363{
6892914f
MC		 364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 370}
371
372static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373{
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
1da177e4
LT		 376}
377
6892914f 378static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 379{
6892914f
MC		 380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388}
389
390static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391{
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
1da177e4 403 }
6892914f
MC		 404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418}
419
420static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421{
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430}
431
b401e9e2
MC		 432/* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 438{
b401e9e2
MC		 439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
1da177e4
LT		 455}
456
09ee929c
MC		 457static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458{
459 tp->write32_mbox(tp, off, val);
6892914f
MC		 460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
09ee929c
MC		 463}
464
20094930 465static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 466{
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473}
474
b5d3772c
MC		 475static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476{
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478}
479
480static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481{
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483}
484
20094930 485#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 486#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 487#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 489#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 490
491#define tw32(reg,val) tp->write32(tp, reg, val)
b401e9e2
MC		 492#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
20094930 494#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 495
496static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497{
6892914f
MC		 498 unsigned long flags;
499
b5d3772c
MC		 500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
6892914f 504 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 508
bbadf503
MC		 509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 514
bbadf503
MC		 515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 519}
520
1da177e4
LT		 521static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522{
6892914f
MC		 523 unsigned long flags;
524
b5d3772c
MC		 525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
6892914f 531 spin_lock_irqsave(&tp->indirect_lock, flags);
bbadf503
MC		 532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 535
bbadf503
MC		 536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
6892914f 545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 546}
547
0d3031d9
MC		 548static void tg3_ape_lock_init(struct tg3 *tp)
549{
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556}
557
558static int tg3_ape_lock(struct tg3 *tp, int locknum)
559{
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
77b483f1 568 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596}
597
598static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599{
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
77b483f1 606 case TG3_APE_LOCK_GRC:
0d3031d9
MC		 607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615}
616
1da177e4
LT		 617static void tg3_disable_ints(struct tg3 *tp)
618{
89aeb3bc
MC		 619 int i;
620
1da177e4
LT		 621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 625}
626
1da177e4
LT		 627static void tg3_enable_ints(struct tg3 *tp)
628{
89aeb3bc
MC		 629 int i;
630 u32 coal_now = 0;
631
bbe832c0
MC		 632 tp->irq_sync = 0;
633 wmb();
634
1da177e4
LT		 635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
898a56f8 640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
89aeb3bc
MC		 641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 643
89aeb3bc
MC		 644 coal_now |= tnapi->coal_now;
645 }
f19af9c2
MC		 646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
1da177e4
LT		 654}
655
17375d25 656static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 657{
17375d25 658 struct tg3 *tp = tnapi->tp;
898a56f8 659 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
f3f3f27e 670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
8d9d7cfc 671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 672 work_exists = 1;
673
674 return work_exists;
675}
676
17375d25 677/* tg3_int_reenable
04237ddd
MC		 678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
6aa20a22 680 * which reenables interrupts
1da177e4 681 */
17375d25 682static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 683{
17375d25
MC		 684 struct tg3 *tp = tnapi->tp;
685
898a56f8 686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 687 mmiowb();
688
fac9b83e
DM		 689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
17375d25 694 tg3_has_work(tnapi))
04237ddd 695 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 697}
698
fed97810
MC		 699static void tg3_napi_disable(struct tg3 *tp)
700{
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705}
706
707static void tg3_napi_enable(struct tg3 *tp)
708{
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713}
714
1da177e4
LT		 715static inline void tg3_netif_stop(struct tg3 *tp)
716{
bbe832c0 717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
fed97810 718 tg3_napi_disable(tp);
1da177e4
LT		 719 netif_tx_disable(tp->dev);
720}
721
722static inline void tg3_netif_start(struct tg3 *tp)
723{
fe5f5787
MC		 724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
1da177e4 727 */
fe5f5787
MC		 728 netif_tx_wake_all_queues(tp->dev);
729
fed97810
MC		 730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
f47c11ee 732 tg3_enable_ints(tp);
1da177e4
LT		 733}
734
735static void tg3_switch_clocks(struct tg3 *tp)
736{
f6eb9b1f 737 u32 clock_ctrl;
1da177e4
LT		 738 u32 orig_clock_ctrl;
739
795d01c5
MC		 740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
4cf78e4f
MC		 742 return;
743
f6eb9b1f
MC		 744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
1da177e4
LT		 746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
1da177e4 765 }
b401e9e2 766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 767}
768
769#define PHY_BUSY_LOOPS 5000
770
771static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772{
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
882e9793 785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 790
1da177e4
LT		 791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818}
819
820static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821{
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
7f97a4bd 826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
b5d3772c
MC		 827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
1da177e4
LT		 830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
882e9793 836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 842
1da177e4
LT		 843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867}
868
95e2869a
MC		 869static int tg3_bmcr_reset(struct tg3 *tp)
870{
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
d4675b52 894 if (limit < 0)
95e2869a
MC		 895 return -EBUSY;
896
897 return 0;
898}
899
158d7abd
MC		 900static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901{
3d16543d 902 struct tg3 *tp = bp->priv;
158d7abd
MC		 903 u32 val;
904
24bb4fb6 905 spin_lock_bh(&tp->lock);
158d7abd
MC		 906
907 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
158d7abd
MC		 911
912 return val;
913}
914
915static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916{
3d16543d 917 struct tg3 *tp = bp->priv;
24bb4fb6 918 u32 ret = 0;
158d7abd 919
24bb4fb6 920 spin_lock_bh(&tp->lock);
158d7abd
MC		 921
922 if (tg3_writephy(tp, reg, val))
24bb4fb6 923 ret = -EIO;
158d7abd 924
24bb4fb6
MC		 925 spin_unlock_bh(&tp->lock);
926
927 return ret;
158d7abd
MC		 928}
929
930static int tg3_mdio_reset(struct mii_bus *bp)
931{
932 return 0;
933}
934
9c61d6bc 935static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 936{
937 u32 val;
fcb389df 938 struct phy_device *phydev;
a9daf367 939
3f0e3ad7 940 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df
MC		 941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
c73430d0 943 case TG3_PHY_ID_BCM50610M:
fcb389df
MC		 944 val = MAC_PHYCFG2_50610_LED_MODES;
945 break;
946 case TG3_PHY_ID_BCMAC131:
947 val = MAC_PHYCFG2_AC131_LED_MODES;
948 break;
949 case TG3_PHY_ID_RTL8211C:
950 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
951 break;
952 case TG3_PHY_ID_RTL8201E:
953 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
954 break;
955 default:
a9daf367 956 return;
fcb389df
MC		 957 }
958
959 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
960 tw32(MAC_PHYCFG2, val);
961
962 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 963 val &= ~(MAC_PHYCFG1_RGMII_INT |
964 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
965 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 966 tw32(MAC_PHYCFG1, val);
967
968 return;
969 }
970
971 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
972 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
973 MAC_PHYCFG2_FMODE_MASK_MASK |
974 MAC_PHYCFG2_GMODE_MASK_MASK |
975 MAC_PHYCFG2_ACT_MASK_MASK |
976 MAC_PHYCFG2_QUAL_MASK_MASK |
977 MAC_PHYCFG2_INBAND_ENABLE;
978
979 tw32(MAC_PHYCFG2, val);
a9daf367 980
bb85fbb6
MC		 981 val = tr32(MAC_PHYCFG1);
982 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
983 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
984 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 985 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
986 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
987 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
988 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
989 }
bb85fbb6
MC		 990 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
991 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
992 tw32(MAC_PHYCFG1, val);
a9daf367 993
a9daf367
MC		 994 val = tr32(MAC_EXT_RGMII_MODE);
995 val &= ~(MAC_RGMII_MODE_RX_INT_B |
996 MAC_RGMII_MODE_RX_QUALITY |
997 MAC_RGMII_MODE_RX_ACTIVITY |
998 MAC_RGMII_MODE_RX_ENG_DET |
999 MAC_RGMII_MODE_TX_ENABLE |
1000 MAC_RGMII_MODE_TX_LOWPWR |
1001 MAC_RGMII_MODE_TX_RESET);
fcb389df 1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
a9daf367
MC		 1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET;
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009 val |= MAC_RGMII_MODE_TX_ENABLE |
1010 MAC_RGMII_MODE_TX_LOWPWR |
1011 MAC_RGMII_MODE_TX_RESET;
1012 }
1013 tw32(MAC_EXT_RGMII_MODE, val);
1014}
1015
158d7abd
MC		 1016static void tg3_mdio_start(struct tg3 *tp)
1017{
158d7abd
MC		 1018 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019 tw32_f(MAC_MI_MODE, tp->mi_mode);
1020 udelay(80);
a9daf367 1021
882e9793
MC		 1022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023 u32 funcnum, is_serdes;
1024
1025 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026 if (funcnum)
1027 tp->phy_addr = 2;
1028 else
1029 tp->phy_addr = 1;
1030
1031 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032 if (is_serdes)
1033 tp->phy_addr += 7;
1034 } else
3f0e3ad7 1035 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1036
9c61d6bc
MC		 1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
158d7abd
MC		 1040}
1041
158d7abd
MC		 1042static int tg3_mdio_init(struct tg3 *tp)
1043{
1044 int i;
1045 u32 reg;
a9daf367 1046 struct phy_device *phydev;
158d7abd
MC		 1047
1048 tg3_mdio_start(tp);
1049
1050 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052 return 0;
1053
298cf9be
LB		 1054 tp->mdio_bus = mdiobus_alloc();
1055 if (tp->mdio_bus == NULL)
1056 return -ENOMEM;
158d7abd 1057
298cf9be
LB		 1058 tp->mdio_bus->name = "tg3 mdio bus";
1059 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1060 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1061 tp->mdio_bus->priv = tp;
1062 tp->mdio_bus->parent = &tp->pdev->dev;
1063 tp->mdio_bus->read = &tg3_mdio_read;
1064 tp->mdio_bus->write = &tg3_mdio_write;
1065 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1066 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1067 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1068
1069 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1070 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1071
1072 /* The bus registration will look for all the PHYs on the mdio bus.
1073 * Unfortunately, it does not ensure the PHY is powered up before
1074 * accessing the PHY ID registers. A chip reset is the
1075 * quickest way to bring the device back to an operational state..
1076 */
1077 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078 tg3_bmcr_reset(tp);
1079
298cf9be 1080 i = mdiobus_register(tp->mdio_bus);
a9daf367 1081 if (i) {
158d7abd
MC		 1082 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083 tp->dev->name, i);
9c61d6bc 1084 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1085 return i;
1086 }
158d7abd 1087
3f0e3ad7 1088 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1089
9c61d6bc
MC		 1090 if (!phydev || !phydev->drv) {
1091 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092 mdiobus_unregister(tp->mdio_bus);
1093 mdiobus_free(tp->mdio_bus);
1094 return -ENODEV;
1095 }
1096
1097 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
321d32a0
MC		 1098 case TG3_PHY_ID_BCM57780:
1099 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1100 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1101 break;
a9daf367 1102 case TG3_PHY_ID_BCM50610:
c73430d0 1103 case TG3_PHY_ID_BCM50610M:
32e5a8d6 1104 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1105 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1106 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1107 PHY_BRCM_AUTO_PWRDWN_ENABLE;
a9daf367
MC		 1108 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1109 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1110 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1111 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1112 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df
MC		 1114 /* fallthru */
1115 case TG3_PHY_ID_RTL8211C:
1116 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1117 break;
fcb389df 1118 case TG3_PHY_ID_RTL8201E:
a9daf367
MC		 1119 case TG3_PHY_ID_BCMAC131:
1120 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1121 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
7f97a4bd 1122 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
a9daf367
MC		 1123 break;
1124 }
1125
9c61d6bc
MC		 1126 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1127
1128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1129 tg3_mdio_config_5785(tp);
a9daf367
MC		 1130
1131 return 0;
158d7abd
MC		 1132}
1133
1134static void tg3_mdio_fini(struct tg3 *tp)
1135{
1136 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1137 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
298cf9be
LB		 1138 mdiobus_unregister(tp->mdio_bus);
1139 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1140 }
1141}
1142
4ba526ce
MC		 1143/* tp->lock is held. */
1144static inline void tg3_generate_fw_event(struct tg3 *tp)
1145{
1146 u32 val;
1147
1148 val = tr32(GRC_RX_CPU_EVENT);
1149 val |= GRC_RX_CPU_DRIVER_EVENT;
1150 tw32_f(GRC_RX_CPU_EVENT, val);
1151
1152 tp->last_event_jiffies = jiffies;
1153}
1154
1155#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1156
95e2869a
MC		 1157/* tp->lock is held. */
1158static void tg3_wait_for_event_ack(struct tg3 *tp)
1159{
1160 int i;
4ba526ce
MC		 1161 unsigned int delay_cnt;
1162 long time_remain;
1163
1164 /* If enough time has passed, no wait is necessary. */
1165 time_remain = (long)(tp->last_event_jiffies + 1 +
1166 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1167 (long)jiffies;
1168 if (time_remain < 0)
1169 return;
1170
1171 /* Check if we can shorten the wait time. */
1172 delay_cnt = jiffies_to_usecs(time_remain);
1173 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1174 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1175 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1176
4ba526ce 1177 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1178 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1179 break;
4ba526ce 1180 udelay(8);
95e2869a
MC		 1181 }
1182}
1183
1184/* tp->lock is held. */
1185static void tg3_ump_link_report(struct tg3 *tp)
1186{
1187 u32 reg;
1188 u32 val;
1189
1190 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1191 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1192 return;
1193
1194 tg3_wait_for_event_ack(tp);
1195
1196 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1197
1198 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1199
1200 val = 0;
1201 if (!tg3_readphy(tp, MII_BMCR, &reg))
1202 val = reg << 16;
1203 if (!tg3_readphy(tp, MII_BMSR, &reg))
1204 val |= (reg & 0xffff);
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1206
1207 val = 0;
1208 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1209 val = reg << 16;
1210 if (!tg3_readphy(tp, MII_LPA, &reg))
1211 val |= (reg & 0xffff);
1212 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1213
1214 val = 0;
1215 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1216 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1217 val = reg << 16;
1218 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1219 val |= (reg & 0xffff);
1220 }
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1222
1223 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1224 val = reg << 16;
1225 else
1226 val = 0;
1227 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1228
4ba526ce 1229 tg3_generate_fw_event(tp);
95e2869a
MC		 1230}
1231
1232static void tg3_link_report(struct tg3 *tp)
1233{
1234 if (!netif_carrier_ok(tp->dev)) {
1235 if (netif_msg_link(tp))
1236 printk(KERN_INFO PFX "%s: Link is down.\n",
1237 tp->dev->name);
1238 tg3_ump_link_report(tp);
1239 } else if (netif_msg_link(tp)) {
1240 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1241 tp->dev->name,
1242 (tp->link_config.active_speed == SPEED_1000 ?
1243 1000 :
1244 (tp->link_config.active_speed == SPEED_100 ?
1245 100 : 10)),
1246 (tp->link_config.active_duplex == DUPLEX_FULL ?
1247 "full" : "half"));
1248
1249 printk(KERN_INFO PFX
1250 "%s: Flow control is %s for TX and %s for RX.\n",
1251 tp->dev->name,
e18ce346 1252 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
95e2869a 1253 "on" : "off",
e18ce346 1254 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
95e2869a
MC		 1255 "on" : "off");
1256 tg3_ump_link_report(tp);
1257 }
1258}
1259
1260static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1261{
1262 u16 miireg;
1263
e18ce346 1264 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1265 miireg = ADVERTISE_PAUSE_CAP;
e18ce346 1266 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1267 miireg = ADVERTISE_PAUSE_ASYM;
e18ce346 1268 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1269 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1270 else
1271 miireg = 0;
1272
1273 return miireg;
1274}
1275
1276static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1277{
1278 u16 miireg;
1279
e18ce346 1280 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1281 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1282 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1283 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1284 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1285 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1286 else
1287 miireg = 0;
1288
1289 return miireg;
1290}
1291
95e2869a
MC		 1292static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1293{
1294 u8 cap = 0;
1295
1296 if (lcladv & ADVERTISE_1000XPAUSE) {
1297 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1298 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1299 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a 1300 else if (rmtadv & LPA_1000XPAUSE_ASYM)
e18ce346 1301 cap = FLOW_CTRL_RX;
95e2869a
MC		 1302 } else {
1303 if (rmtadv & LPA_1000XPAUSE)
e18ce346 1304 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
95e2869a
MC		 1305 }
1306 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
e18ce346 1308 cap = FLOW_CTRL_TX;
95e2869a
MC		 1309 }
1310
1311 return cap;
1312}
1313
f51f3562 1314static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1315{
b02fd9e3 1316 u8 autoneg;
f51f3562 1317 u8 flowctrl = 0;
95e2869a
MC		 1318 u32 old_rx_mode = tp->rx_mode;
1319 u32 old_tx_mode = tp->tx_mode;
1320
b02fd9e3 1321 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
3f0e3ad7 1322 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1323 else
1324 autoneg = tp->link_config.autoneg;
1325
1326 if (autoneg == AUTONEG_ENABLE &&
95e2869a
MC		 1327 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1328 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
f51f3562 1329 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1330 else
bc02ff95 1331 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1332 } else
1333 flowctrl = tp->link_config.flowctrl;
95e2869a 1334
f51f3562 1335 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1336
e18ce346 1337 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1338 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1339 else
1340 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1341
f51f3562 1342 if (old_rx_mode != tp->rx_mode)
95e2869a 1343 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1344
e18ce346 1345 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1346 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1347 else
1348 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1349
f51f3562 1350 if (old_tx_mode != tp->tx_mode)
95e2869a 1351 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1352}
1353
b02fd9e3
MC		 1354static void tg3_adjust_link(struct net_device *dev)
1355{
1356 u8 oldflowctrl, linkmesg = 0;
1357 u32 mac_mode, lcl_adv, rmt_adv;
1358 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1359 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1360
24bb4fb6 1361 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1362
1363 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1364 MAC_MODE_HALF_DUPLEX);
1365
1366 oldflowctrl = tp->link_config.active_flowctrl;
1367
1368 if (phydev->link) {
1369 lcl_adv = 0;
1370 rmt_adv = 0;
1371
1372 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1373 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748
MC		 1374 else if (phydev->speed == SPEED_1000 ||
1375 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
b02fd9e3 1376 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 1377 else
1378 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 1379
1380 if (phydev->duplex == DUPLEX_HALF)
1381 mac_mode |= MAC_MODE_HALF_DUPLEX;
1382 else {
1383 lcl_adv = tg3_advert_flowctrl_1000T(
1384 tp->link_config.flowctrl);
1385
1386 if (phydev->pause)
1387 rmt_adv = LPA_PAUSE_CAP;
1388 if (phydev->asym_pause)
1389 rmt_adv |= LPA_PAUSE_ASYM;
1390 }
1391
1392 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1393 } else
1394 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1395
1396 if (mac_mode != tp->mac_mode) {
1397 tp->mac_mode = mac_mode;
1398 tw32_f(MAC_MODE, tp->mac_mode);
1399 udelay(40);
1400 }
1401
fcb389df
MC		 1402 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1403 if (phydev->speed == SPEED_10)
1404 tw32(MAC_MI_STAT,
1405 MAC_MI_STAT_10MBPS_MODE |
1406 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1407 else
1408 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1409 }
1410
b02fd9e3
MC		 1411 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1412 tw32(MAC_TX_LENGTHS,
1413 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414 (6 << TX_LENGTHS_IPG_SHIFT) |
1415 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416 else
1417 tw32(MAC_TX_LENGTHS,
1418 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419 (6 << TX_LENGTHS_IPG_SHIFT) |
1420 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421
1422 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1423 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1424 phydev->speed != tp->link_config.active_speed ||
1425 phydev->duplex != tp->link_config.active_duplex ||
1426 oldflowctrl != tp->link_config.active_flowctrl)
1427 linkmesg = 1;
1428
1429 tp->link_config.active_speed = phydev->speed;
1430 tp->link_config.active_duplex = phydev->duplex;
1431
24bb4fb6 1432 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 1433
1434 if (linkmesg)
1435 tg3_link_report(tp);
1436}
1437
1438static int tg3_phy_init(struct tg3 *tp)
1439{
1440 struct phy_device *phydev;
1441
1442 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1443 return 0;
1444
1445 /* Bring the PHY back to a known state. */
1446 tg3_bmcr_reset(tp);
1447
3f0e3ad7 1448 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1449
1450 /* Attach the MAC to the PHY. */
fb28ad35 1451 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
a9daf367 1452 phydev->dev_flags, phydev->interface);
b02fd9e3
MC		 1453 if (IS_ERR(phydev)) {
1454 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1455 return PTR_ERR(phydev);
1456 }
1457
b02fd9e3 1458 /* Mask with MAC supported features. */
9c61d6bc
MC		 1459 switch (phydev->interface) {
1460 case PHY_INTERFACE_MODE_GMII:
1461 case PHY_INTERFACE_MODE_RGMII:
321d32a0
MC		 1462 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1463 phydev->supported &= (PHY_GBIT_FEATURES |
1464 SUPPORTED_Pause |
1465 SUPPORTED_Asym_Pause);
1466 break;
1467 }
1468 /* fallthru */
9c61d6bc
MC		 1469 case PHY_INTERFACE_MODE_MII:
1470 phydev->supported &= (PHY_BASIC_FEATURES |
1471 SUPPORTED_Pause |
1472 SUPPORTED_Asym_Pause);
1473 break;
1474 default:
3f0e3ad7 1475 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 1476 return -EINVAL;
1477 }
1478
1479 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
b02fd9e3
MC		 1480
1481 phydev->advertising = phydev->supported;
1482
b02fd9e3
MC		 1483 return 0;
1484}
1485
1486static void tg3_phy_start(struct tg3 *tp)
1487{
1488 struct phy_device *phydev;
1489
1490 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1491 return;
1492
3f0e3ad7 1493 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 1494
1495 if (tp->link_config.phy_is_low_power) {
1496 tp->link_config.phy_is_low_power = 0;
1497 phydev->speed = tp->link_config.orig_speed;
1498 phydev->duplex = tp->link_config.orig_duplex;
1499 phydev->autoneg = tp->link_config.orig_autoneg;
1500 phydev->advertising = tp->link_config.orig_advertising;
1501 }
1502
1503 phy_start(phydev);
1504
1505 phy_start_aneg(phydev);
1506}
1507
1508static void tg3_phy_stop(struct tg3 *tp)
1509{
1510 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511 return;
1512
3f0e3ad7 1513 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1514}
1515
1516static void tg3_phy_fini(struct tg3 *tp)
1517{
1518 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
3f0e3ad7 1519 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 1520 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1521 }
1522}
1523
b2a5c19c
MC		 1524static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1525{
1526 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1527 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1528}
1529
7f97a4bd
MC		 1530static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1531{
1532 u32 phytest;
1533
1534 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1535 u32 phy;
1536
1537 tg3_writephy(tp, MII_TG3_FET_TEST,
1538 phytest | MII_TG3_FET_SHADOW_EN);
1539 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1540 if (enable)
1541 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1542 else
1543 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1544 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1545 }
1546 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1547 }
1548}
1549
6833c043
MC		 1550static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1551{
1552 u32 reg;
1553
7f97a4bd 1554 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6833c043
MC		 1555 return;
1556
7f97a4bd
MC		 1557 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1558 tg3_phy_fet_toggle_apd(tp, enable);
1559 return;
1560 }
1561
6833c043
MC		 1562 reg = MII_TG3_MISC_SHDW_WREN |
1563 MII_TG3_MISC_SHDW_SCR5_SEL |
1564 MII_TG3_MISC_SHDW_SCR5_LPED |
1565 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1566 MII_TG3_MISC_SHDW_SCR5_SDTL |
1567 MII_TG3_MISC_SHDW_SCR5_C125OE;
1568 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1569 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1570
1571 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1572
1573
1574 reg = MII_TG3_MISC_SHDW_WREN |
1575 MII_TG3_MISC_SHDW_APD_SEL |
1576 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1577 if (enable)
1578 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1579
1580 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581}
1582
9ef8ca99
MC		 1583static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1584{
1585 u32 phy;
1586
1587 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1588 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1589 return;
1590
7f97a4bd 1591 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9ef8ca99
MC		 1592 u32 ephy;
1593
535ef6e1
MC		 1594 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1595 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1596
1597 tg3_writephy(tp, MII_TG3_FET_TEST,
1598 ephy | MII_TG3_FET_SHADOW_EN);
1599 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 1600 if (enable)
535ef6e1 1601 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 1602 else
535ef6e1
MC		 1603 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1604 tg3_writephy(tp, reg, phy);
9ef8ca99 1605 }
535ef6e1 1606 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 1607 }
1608 } else {
1609 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1610 MII_TG3_AUXCTL_SHDWSEL_MISC;
1611 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1612 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1613 if (enable)
1614 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1615 else
1616 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1617 phy |= MII_TG3_AUXCTL_MISC_WREN;
1618 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619 }
1620 }
1621}
1622
1da177e4
LT		 1623static void tg3_phy_set_wirespeed(struct tg3 *tp)
1624{
1625 u32 val;
1626
1627 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1628 return;
1629
1630 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1631 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1632 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1633 (val | (1 << 15) | (1 << 4)));
1634}
1635
b2a5c19c
MC		 1636static void tg3_phy_apply_otp(struct tg3 *tp)
1637{
1638 u32 otp, phy;
1639
1640 if (!tp->phy_otp)
1641 return;
1642
1643 otp = tp->phy_otp;
1644
1645 /* Enable SM_DSP clock and tx 6dB coding. */
1646 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1647 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1648 MII_TG3_AUXCTL_ACTL_TX_6DB;
1649 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1650
1651 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1652 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1653 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1654
1655 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1656 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1657 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1658
1659 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1660 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1661 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1662
1663 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1664 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1665
1666 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1667 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1668
1669 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1670 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1671 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1672
1673 /* Turn off SM_DSP clock. */
1674 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1675 MII_TG3_AUXCTL_ACTL_TX_6DB;
1676 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1677}
1678
1da177e4
LT		 1679static int tg3_wait_macro_done(struct tg3 *tp)
1680{
1681 int limit = 100;
1682
1683 while (limit--) {
1684 u32 tmp32;
1685
1686 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1687 if ((tmp32 & 0x1000) == 0)
1688 break;
1689 }
1690 }
d4675b52 1691 if (limit < 0)
1da177e4
LT		 1692 return -EBUSY;
1693
1694 return 0;
1695}
1696
1697static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1698{
1699 static const u32 test_pat[4][6] = {
1700 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1704 };
1705 int chan;
1706
1707 for (chan = 0; chan < 4; chan++) {
1708 int i;
1709
1710 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1711 (chan * 0x2000) | 0x0200);
1712 tg3_writephy(tp, 0x16, 0x0002);
1713
1714 for (i = 0; i < 6; i++)
1715 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1716 test_pat[chan][i]);
1717
1718 tg3_writephy(tp, 0x16, 0x0202);
1719 if (tg3_wait_macro_done(tp)) {
1720 *resetp = 1;
1721 return -EBUSY;
1722 }
1723
1724 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1725 (chan * 0x2000) | 0x0200);
1726 tg3_writephy(tp, 0x16, 0x0082);
1727 if (tg3_wait_macro_done(tp)) {
1728 *resetp = 1;
1729 return -EBUSY;
1730 }
1731
1732 tg3_writephy(tp, 0x16, 0x0802);
1733 if (tg3_wait_macro_done(tp)) {
1734 *resetp = 1;
1735 return -EBUSY;
1736 }
1737
1738 for (i = 0; i < 6; i += 2) {
1739 u32 low, high;
1740
1741 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1742 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1743 tg3_wait_macro_done(tp)) {
1744 *resetp = 1;
1745 return -EBUSY;
1746 }
1747 low &= 0x7fff;
1748 high &= 0x000f;
1749 if (low != test_pat[chan][i] ||
1750 high != test_pat[chan][i+1]) {
1751 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1752 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1753 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1754
1755 return -EBUSY;
1756 }
1757 }
1758 }
1759
1760 return 0;
1761}
1762
1763static int tg3_phy_reset_chanpat(struct tg3 *tp)
1764{
1765 int chan;
1766
1767 for (chan = 0; chan < 4; chan++) {
1768 int i;
1769
1770 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1771 (chan * 0x2000) | 0x0200);
1772 tg3_writephy(tp, 0x16, 0x0002);
1773 for (i = 0; i < 6; i++)
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1775 tg3_writephy(tp, 0x16, 0x0202);
1776 if (tg3_wait_macro_done(tp))
1777 return -EBUSY;
1778 }
1779
1780 return 0;
1781}
1782
1783static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1784{
1785 u32 reg32, phy9_orig;
1786 int retries, do_phy_reset, err;
1787
1788 retries = 10;
1789 do_phy_reset = 1;
1790 do {
1791 if (do_phy_reset) {
1792 err = tg3_bmcr_reset(tp);
1793 if (err)
1794 return err;
1795 do_phy_reset = 0;
1796 }
1797
1798 /* Disable transmitter and interrupt. */
1799 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1800 continue;
1801
1802 reg32 |= 0x3000;
1803 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1804
1805 /* Set full-duplex, 1000 mbps. */
1806 tg3_writephy(tp, MII_BMCR,
1807 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1808
1809 /* Set to master mode. */
1810 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1811 continue;
1812
1813 tg3_writephy(tp, MII_TG3_CTRL,
1814 (MII_TG3_CTRL_AS_MASTER |
1815 MII_TG3_CTRL_ENABLE_AS_MASTER));
1816
1817 /* Enable SM_DSP_CLOCK and 6dB. */
1818 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1819
1820 /* Block the PHY control access. */
1821 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1822 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1823
1824 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1825 if (!err)
1826 break;
1827 } while (--retries);
1828
1829 err = tg3_phy_reset_chanpat(tp);
1830 if (err)
1831 return err;
1832
1833 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1834 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1835
1836 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1837 tg3_writephy(tp, 0x16, 0x0000);
1838
1839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1841 /* Set Extended packet length bit for jumbo frames */
1842 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1843 }
1844 else {
1845 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1846 }
1847
1848 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1849
1850 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1851 reg32 &= ~0x3000;
1852 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1853 } else if (!err)
1854 err = -EBUSY;
1855
1856 return err;
1857}
1858
1859/* This will reset the tigon3 PHY if there is no valid
1860 * link unless the FORCE argument is non-zero.
1861 */
1862static int tg3_phy_reset(struct tg3 *tp)
1863{
b2a5c19c 1864 u32 cpmuctrl;
1da177e4
LT		 1865 u32 phy_status;
1866 int err;
1867
60189ddf
MC		 1868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1869 u32 val;
1870
1871 val = tr32(GRC_MISC_CFG);
1872 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1873 udelay(40);
1874 }
1da177e4
LT		 1875 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1876 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1877 if (err != 0)
1878 return -EBUSY;
1879
c8e1e82b
MC		 1880 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1881 netif_carrier_off(tp->dev);
1882 tg3_link_report(tp);
1883 }
1884
1da177e4
LT		 1885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1888 err = tg3_phy_reset_5703_4_5(tp);
1889 if (err)
1890 return err;
1891 goto out;
1892 }
1893
b2a5c19c
MC		 1894 cpmuctrl = 0;
1895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1896 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1897 cpmuctrl = tr32(TG3_CPMU_CTRL);
1898 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1899 tw32(TG3_CPMU_CTRL,
1900 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1901 }
1902
1da177e4
LT		 1903 err = tg3_bmcr_reset(tp);
1904 if (err)
1905 return err;
1906
b2a5c19c
MC		 1907 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1908 u32 phy;
1909
1910 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1911 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1912
1913 tw32(TG3_CPMU_CTRL, cpmuctrl);
1914 }
1915
bcb37f6c
MC		 1916 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1917 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 1918 u32 val;
1919
1920 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1921 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1922 CPMU_LSPD_1000MB_MACCLK_12_5) {
1923 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1924 udelay(40);
1925 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1926 }
1927 }
1928
b2a5c19c
MC		 1929 tg3_phy_apply_otp(tp);
1930
6833c043
MC		 1931 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1932 tg3_phy_toggle_apd(tp, true);
1933 else
1934 tg3_phy_toggle_apd(tp, false);
1935
1da177e4
LT		 1936out:
1937 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1938 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1940 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1941 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1942 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1943 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1944 }
1945 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1946 tg3_writephy(tp, 0x1c, 0x8d68);
1947 tg3_writephy(tp, 0x1c, 0x8d68);
1948 }
1949 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1950 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1951 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1953 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1954 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1955 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958 }
c424cb24
MC		 1959 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
c1d2a196
MC		 1962 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1964 tg3_writephy(tp, MII_TG3_TEST1,
1965 MII_TG3_TEST1_TRIM_EN | 0x4);
1966 } else
1967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
c424cb24
MC		 1968 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969 }
1da177e4
LT		 1970 /* Set Extended packet length bit (bit 14) on all chips that */
1971 /* support jumbo frames */
1972 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1973 /* Cannot do read-modify-write on 5401 */
1974 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
8f666b07 1975 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1976 u32 phy_reg;
1977
1978 /* Set bit 14 with read-modify-write to preserve other bits */
1979 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1980 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1981 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1982 }
1983
1984 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985 * jumbo frames transmission.
1986 */
8f666b07 1987 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1da177e4
LT		 1988 u32 phy_reg;
1989
1990 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1991 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1992 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1993 }
1994
715116a1 1995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
715116a1 1996 /* adjust output voltage */
535ef6e1 1997 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 1998 }
1999
9ef8ca99 2000 tg3_phy_toggle_automdix(tp, 1);
1da177e4
LT		 2001 tg3_phy_set_wirespeed(tp);
2002 return 0;
2003}
2004
2005static void tg3_frob_aux_power(struct tg3 *tp)
2006{
2007 struct tg3 *tp_peer = tp;
2008
9d26e213 2009 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1da177e4
LT		 2010 return;
2011
f6eb9b1f
MC		 2012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8c2dc7e1
MC		 2015 struct net_device *dev_peer;
2016
2017 dev_peer = pci_get_drvdata(tp->pdev_peer);
bc1c7567 2018 /* remove_one() may have been run on the peer. */
8c2dc7e1 2019 if (!dev_peer)
bc1c7567
MC		 2020 tp_peer = tp;
2021 else
2022 tp_peer = netdev_priv(dev_peer);
1da177e4
LT		 2023 }
2024
1da177e4 2025 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
6921d201
MC		 2026 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2027 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2028 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1da177e4
LT		 2029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
b401e9e2
MC		 2031 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032 (GRC_LCLCTRL_GPIO_OE0 |
2033 GRC_LCLCTRL_GPIO_OE1 |
2034 GRC_LCLCTRL_GPIO_OE2 |
2035 GRC_LCLCTRL_GPIO_OUTPUT0 |
2036 GRC_LCLCTRL_GPIO_OUTPUT1),
2037 100);
8d519ab2
MC		 2038 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 2040 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2042 GRC_LCLCTRL_GPIO_OE1 |
2043 GRC_LCLCTRL_GPIO_OE2 |
2044 GRC_LCLCTRL_GPIO_OUTPUT0 |
2045 GRC_LCLCTRL_GPIO_OUTPUT1 |
2046 tp->grc_local_ctrl;
2047 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2050 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051
2052 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2053 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1da177e4
LT		 2054 } else {
2055 u32 no_gpio2;
dc56b7d4 2056 u32 grc_local_ctrl = 0;
1da177e4
LT		 2057
2058 if (tp_peer != tp &&
2059 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060 return;
2061
dc56b7d4
MC		 2062 /* Workaround to prevent overdrawing Amps. */
2063 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2064 ASIC_REV_5714) {
2065 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
b401e9e2
MC		 2066 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067 grc_local_ctrl, 100);
dc56b7d4
MC		 2068 }
2069
1da177e4
LT		 2070 /* On 5753 and variants, GPIO2 cannot be used. */
2071 no_gpio2 = tp->nic_sram_data_cfg &
2072 NIC_SRAM_DATA_CFG_NO_GPIO2;
2073
dc56b7d4 2074 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1da177e4
LT		 2075 GRC_LCLCTRL_GPIO_OE1 |
2076 GRC_LCLCTRL_GPIO_OE2 |
2077 GRC_LCLCTRL_GPIO_OUTPUT1 |
2078 GRC_LCLCTRL_GPIO_OUTPUT2;
2079 if (no_gpio2) {
2080 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2081 GRC_LCLCTRL_GPIO_OUTPUT2);
2082 }
b401e9e2
MC		 2083 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084 grc_local_ctrl, 100);
1da177e4
LT		 2085
2086 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2087
b401e9e2
MC		 2088 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089 grc_local_ctrl, 100);
1da177e4
LT		 2090
2091 if (!no_gpio2) {
2092 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
b401e9e2
MC		 2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 grc_local_ctrl, 100);
1da177e4
LT		 2095 }
2096 }
2097 } else {
2098 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2099 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2100 if (tp_peer != tp &&
2101 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102 return;
2103
b401e9e2
MC		 2104 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105 (GRC_LCLCTRL_GPIO_OE1 |
2106 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4 2107
b401e9e2
MC		 2108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109 GRC_LCLCTRL_GPIO_OE1, 100);
1da177e4 2110
b401e9e2
MC		 2111 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112 (GRC_LCLCTRL_GPIO_OE1 |
2113 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1da177e4
LT		 2114 }
2115 }
2116}
2117
e8f3f6ca
MC		 2118static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2119{
2120 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2121 return 1;
2122 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2123 if (speed != SPEED_10)
2124 return 1;
2125 } else if (speed == SPEED_10)
2126 return 1;
2127
2128 return 0;
2129}
2130
1da177e4
LT		 2131static int tg3_setup_phy(struct tg3 *, int);
2132
2133#define RESET_KIND_SHUTDOWN 0
2134#define RESET_KIND_INIT 1
2135#define RESET_KIND_SUSPEND 2
2136
2137static void tg3_write_sig_post_reset(struct tg3 *, int);
2138static int tg3_halt_cpu(struct tg3 *, u32);
2139
0a459aac 2140static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 2141{
ce057f01
MC		 2142 u32 val;
2143
5129724a
MC		 2144 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2146 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2147 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2148
2149 sg_dig_ctrl |=
2150 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2151 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2152 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2153 }
3f7045c1 2154 return;
5129724a 2155 }
3f7045c1 2156
60189ddf 2157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
60189ddf
MC		 2158 tg3_bmcr_reset(tp);
2159 val = tr32(GRC_MISC_CFG);
2160 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2161 udelay(40);
2162 return;
0e5f784c
MC		 2163 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2164 u32 phytest;
2165 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2166 u32 phy;
2167
2168 tg3_writephy(tp, MII_ADVERTISE, 0);
2169 tg3_writephy(tp, MII_BMCR,
2170 BMCR_ANENABLE | BMCR_ANRESTART);
2171
2172 tg3_writephy(tp, MII_TG3_FET_TEST,
2173 phytest | MII_TG3_FET_SHADOW_EN);
2174 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2175 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2176 tg3_writephy(tp,
2177 MII_TG3_FET_SHDW_AUXMODE4,
2178 phy);
2179 }
2180 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2181 }
2182 return;
0a459aac 2183 } else if (do_low_power) {
715116a1
MC		 2184 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2185 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac
MC		 2186
2187 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2188 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2189 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2190 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2191 MII_TG3_AUXCTL_PCTL_VREG_11V);
715116a1 2192 }
3f7045c1 2193
15c3b696
MC		 2194 /* The PHY should not be powered down on some chips because
2195 * of bugs.
2196 */
2197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2198 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2199 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2200 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2201 return;
ce057f01 2202
bcb37f6c
MC		 2203 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2204 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
ce057f01
MC		 2205 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2206 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2207 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2208 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2209 }
2210
15c3b696
MC		 2211 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2212}
2213
ffbcfed4
MC		 2214/* tp->lock is held. */
2215static int tg3_nvram_lock(struct tg3 *tp)
2216{
2217 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2218 int i;
2219
2220 if (tp->nvram_lock_cnt == 0) {
2221 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2222 for (i = 0; i < 8000; i++) {
2223 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2224 break;
2225 udelay(20);
2226 }
2227 if (i == 8000) {
2228 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2229 return -ENODEV;
2230 }
2231 }
2232 tp->nvram_lock_cnt++;
2233 }
2234 return 0;
2235}
2236
2237/* tp->lock is held. */
2238static void tg3_nvram_unlock(struct tg3 *tp)
2239{
2240 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241 if (tp->nvram_lock_cnt > 0)
2242 tp->nvram_lock_cnt--;
2243 if (tp->nvram_lock_cnt == 0)
2244 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2245 }
2246}
2247
2248/* tp->lock is held. */
2249static void tg3_enable_nvram_access(struct tg3 *tp)
2250{
2251 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2252 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2253 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2256 }
2257}
2258
2259/* tp->lock is held. */
2260static void tg3_disable_nvram_access(struct tg3 *tp)
2261{
2262 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2263 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2264 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2267 }
2268}
2269
2270static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2271 u32 offset, u32 *val)
2272{
2273 u32 tmp;
2274 int i;
2275
2276 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2277 return -EINVAL;
2278
2279 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2280 EEPROM_ADDR_DEVID_MASK |
2281 EEPROM_ADDR_READ);
2282 tw32(GRC_EEPROM_ADDR,
2283 tmp |
2284 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2285 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2286 EEPROM_ADDR_ADDR_MASK) |
2287 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2288
2289 for (i = 0; i < 1000; i++) {
2290 tmp = tr32(GRC_EEPROM_ADDR);
2291
2292 if (tmp & EEPROM_ADDR_COMPLETE)
2293 break;
2294 msleep(1);
2295 }
2296 if (!(tmp & EEPROM_ADDR_COMPLETE))
2297 return -EBUSY;
2298
62cedd11
MC		 2299 tmp = tr32(GRC_EEPROM_DATA);
2300
2301 /*
2302 * The data will always be opposite the native endian
2303 * format. Perform a blind byteswap to compensate.
2304 */
2305 *val = swab32(tmp);
2306
ffbcfed4
MC		 2307 return 0;
2308}
2309
2310#define NVRAM_CMD_TIMEOUT 10000
2311
2312static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2313{
2314 int i;
2315
2316 tw32(NVRAM_CMD, nvram_cmd);
2317 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2318 udelay(10);
2319 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2320 udelay(10);
2321 break;
2322 }
2323 }
2324
2325 if (i == NVRAM_CMD_TIMEOUT)
2326 return -EBUSY;
2327
2328 return 0;
2329}
2330
2331static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2332{
2333 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2334 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2335 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2336 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2337 (tp->nvram_jedecnum == JEDEC_ATMEL))
2338
2339 addr = ((addr / tp->nvram_pagesize) <<
2340 ATMEL_AT45DB0X1B_PAGE_POS) +
2341 (addr % tp->nvram_pagesize);
2342
2343 return addr;
2344}
2345
2346static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2347{
2348 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352 (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2355 tp->nvram_pagesize) +
2356 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2357
2358 return addr;
2359}
2360
e4f34110
MC		 2361/* NOTE: Data read in from NVRAM is byteswapped according to
2362 * the byteswapping settings for all other register accesses.
2363 * tg3 devices are BE devices, so on a BE machine, the data
2364 * returned will be exactly as it is seen in NVRAM. On a LE
2365 * machine, the 32-bit value will be byteswapped.
2366 */
ffbcfed4
MC		 2367static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2368{
2369 int ret;
2370
2371 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2372 return tg3_nvram_read_using_eeprom(tp, offset, val);
2373
2374 offset = tg3_nvram_phys_addr(tp, offset);
2375
2376 if (offset > NVRAM_ADDR_MSK)
2377 return -EINVAL;
2378
2379 ret = tg3_nvram_lock(tp);
2380 if (ret)
2381 return ret;
2382
2383 tg3_enable_nvram_access(tp);
2384
2385 tw32(NVRAM_ADDR, offset);
2386 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2387 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2388
2389 if (ret == 0)
e4f34110 2390 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 2391
2392 tg3_disable_nvram_access(tp);
2393
2394 tg3_nvram_unlock(tp);
2395
2396 return ret;
2397}
2398
a9dc529d
MC		 2399/* Ensures NVRAM data is in bytestream format. */
2400static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 2401{
2402 u32 v;
a9dc529d 2403 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 2404 if (!res)
a9dc529d 2405 *val = cpu_to_be32(v);
ffbcfed4
MC		 2406 return res;
2407}
2408
3f007891
MC		 2409/* tp->lock is held. */
2410static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2411{
2412 u32 addr_high, addr_low;
2413 int i;
2414
2415 addr_high = ((tp->dev->dev_addr[0] << 8) |
2416 tp->dev->dev_addr[1]);
2417 addr_low = ((tp->dev->dev_addr[2] << 24) |
2418 (tp->dev->dev_addr[3] << 16) |
2419 (tp->dev->dev_addr[4] << 8) |
2420 (tp->dev->dev_addr[5] << 0));
2421 for (i = 0; i < 4; i++) {
2422 if (i == 1 && skip_mac_1)
2423 continue;
2424 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2425 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2426 }
2427
2428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2430 for (i = 0; i < 12; i++) {
2431 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2432 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2433 }
2434 }
2435
2436 addr_high = (tp->dev->dev_addr[0] +
2437 tp->dev->dev_addr[1] +
2438 tp->dev->dev_addr[2] +
2439 tp->dev->dev_addr[3] +
2440 tp->dev->dev_addr[4] +
2441 tp->dev->dev_addr[5]) &
2442 TX_BACKOFF_SEED_MASK;
2443 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2444}
2445
bc1c7567 2446static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1da177e4
LT		 2447{
2448 u32 misc_host_ctrl;
0a459aac 2449 bool device_should_wake, do_low_power;
1da177e4
LT		 2450
2451 /* Make sure register accesses (indirect or otherwise)
2452 * will function correctly.
2453 */
2454 pci_write_config_dword(tp->pdev,
2455 TG3PCI_MISC_HOST_CTRL,
2456 tp->misc_host_ctrl);
2457
1da177e4 2458 switch (state) {
bc1c7567 2459 case PCI_D0:
12dac075
RW		 2460 pci_enable_wake(tp->pdev, state, false);
2461 pci_set_power_state(tp->pdev, PCI_D0);
8c6bda1a 2462
9d26e213
MC		 2463 /* Switch out of Vaux if it is a NIC */
2464 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
b401e9e2 2465 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1da177e4
LT		 2466
2467 return 0;
2468
bc1c7567 2469 case PCI_D1:
bc1c7567 2470 case PCI_D2:
bc1c7567 2471 case PCI_D3hot:
1da177e4
LT		 2472 break;
2473
2474 default:
12dac075
RW		 2475 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2476 tp->dev->name, state);
1da177e4 2477 return -EINVAL;
855e1111 2478 }
5e7dfd0f
MC		 2479
2480 /* Restore the CLKREQ setting. */
2481 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2482 u16 lnkctl;
2483
2484 pci_read_config_word(tp->pdev,
2485 tp->pcie_cap + PCI_EXP_LNKCTL,
2486 &lnkctl);
2487 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2488 pci_write_config_word(tp->pdev,
2489 tp->pcie_cap + PCI_EXP_LNKCTL,
2490 lnkctl);
2491 }
2492
1da177e4
LT		 2493 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2494 tw32(TG3PCI_MISC_HOST_CTRL,
2495 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2496
05ac4cb7
MC		 2497 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2498 device_may_wakeup(&tp->pdev->dev) &&
2499 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2500
dd477003 2501 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
0a459aac 2502 do_low_power = false;
b02fd9e3
MC		 2503 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2504 !tp->link_config.phy_is_low_power) {
2505 struct phy_device *phydev;
0a459aac 2506 u32 phyid, advertising;
b02fd9e3 2507
3f0e3ad7 2508 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2509
2510 tp->link_config.phy_is_low_power = 1;
2511
2512 tp->link_config.orig_speed = phydev->speed;
2513 tp->link_config.orig_duplex = phydev->duplex;
2514 tp->link_config.orig_autoneg = phydev->autoneg;
2515 tp->link_config.orig_advertising = phydev->advertising;
2516
2517 advertising = ADVERTISED_TP |
2518 ADVERTISED_Pause |
2519 ADVERTISED_Autoneg |
2520 ADVERTISED_10baseT_Half;
2521
2522 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
05ac4cb7 2523 device_should_wake) {
b02fd9e3
MC		 2524 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2525 advertising |=
2526 ADVERTISED_100baseT_Half |
2527 ADVERTISED_100baseT_Full |
2528 ADVERTISED_10baseT_Full;
2529 else
2530 advertising |= ADVERTISED_10baseT_Full;
2531 }
2532
2533 phydev->advertising = advertising;
2534
2535 phy_start_aneg(phydev);
0a459aac
MC		 2536
2537 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2538 if (phyid != TG3_PHY_ID_BCMAC131) {
2539 phyid &= TG3_PHY_OUI_MASK;
f72b5349
RK		 2540 if (phyid == TG3_PHY_OUI_1 ||
2541 phyid == TG3_PHY_OUI_2 ||
0a459aac
MC		 2542 phyid == TG3_PHY_OUI_3)
2543 do_low_power = true;
2544 }
b02fd9e3 2545 }
dd477003 2546 } else {
2023276e 2547 do_low_power = true;
0a459aac 2548
dd477003
MC		 2549 if (tp->link_config.phy_is_low_power == 0) {
2550 tp->link_config.phy_is_low_power = 1;
2551 tp->link_config.orig_speed = tp->link_config.speed;
2552 tp->link_config.orig_duplex = tp->link_config.duplex;
2553 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2554 }
1da177e4 2555
dd477003
MC		 2556 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2557 tp->link_config.speed = SPEED_10;
2558 tp->link_config.duplex = DUPLEX_HALF;
2559 tp->link_config.autoneg = AUTONEG_ENABLE;
2560 tg3_setup_phy(tp, 0);
2561 }
1da177e4
LT		 2562 }
2563
b5d3772c
MC		 2564 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2565 u32 val;
2566
2567 val = tr32(GRC_VCPU_EXT_CTRL);
2568 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2569 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
6921d201
MC		 2570 int i;
2571 u32 val;
2572
2573 for (i = 0; i < 200; i++) {
2574 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2575 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2576 break;
2577 msleep(1);
2578 }
2579 }
a85feb8c
GZ		 2580 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2581 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2582 WOL_DRV_STATE_SHUTDOWN |
2583 WOL_DRV_WOL |
2584 WOL_SET_MAGIC_PKT);
6921d201 2585
05ac4cb7 2586 if (device_should_wake) {
1da177e4
LT		 2587 u32 mac_mode;
2588
2589 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
0a459aac 2590 if (do_low_power) {
dd477003
MC		 2591 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2592 udelay(40);
2593 }
1da177e4 2594
3f7045c1
MC		 2595 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2596 mac_mode = MAC_MODE_PORT_MODE_GMII;
2597 else
2598 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 2599
e8f3f6ca
MC		 2600 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2601 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2602 ASIC_REV_5700) {
2603 u32 speed = (tp->tg3_flags &
2604 TG3_FLAG_WOL_SPEED_100MB) ?
2605 SPEED_100 : SPEED_10;
2606 if (tg3_5700_link_polarity(tp, speed))
2607 mac_mode |= MAC_MODE_LINK_POLARITY;
2608 else
2609 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2610 }
1da177e4
LT		 2611 } else {
2612 mac_mode = MAC_MODE_PORT_MODE_TBI;
2613 }
2614
cbf46853 2615 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 2616 tw32(MAC_LED_CTRL, tp->led_ctrl);
2617
05ac4cb7
MC		 2618 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2619 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2620 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2621 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2622 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2623 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 2624
3bda1258
MC		 2625 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2626 mac_mode |= tp->mac_mode &
2627 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2628 if (mac_mode & MAC_MODE_APE_TX_EN)
2629 mac_mode |= MAC_MODE_TDE_ENABLE;
2630 }
2631
1da177e4
LT		 2632 tw32_f(MAC_MODE, mac_mode);
2633 udelay(100);
2634
2635 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2636 udelay(10);
2637 }
2638
2639 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2640 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2641 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2642 u32 base_val;
2643
2644 base_val = tp->pci_clock_ctrl;
2645 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2646 CLOCK_CTRL_TXCLK_DISABLE);
2647
b401e9e2
MC		 2648 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2649 CLOCK_CTRL_PWRDOWN_PLL133, 40);
d7b0a857 2650 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
795d01c5 2651 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
d7b0a857 2652 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
4cf78e4f 2653 /* do nothing */
85e94ced 2654 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 2655 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2656 u32 newbits1, newbits2;
2657
2658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2660 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2661 CLOCK_CTRL_TXCLK_DISABLE |
2662 CLOCK_CTRL_ALTCLK);
2663 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2665 newbits1 = CLOCK_CTRL_625_CORE;
2666 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2667 } else {
2668 newbits1 = CLOCK_CTRL_ALTCLK;
2669 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670 }
2671
b401e9e2
MC		 2672 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2673 40);
1da177e4 2674
b401e9e2
MC		 2675 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2676 40);
1da177e4
LT		 2677
2678 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2679 u32 newbits3;
2680
2681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2684 CLOCK_CTRL_TXCLK_DISABLE |
2685 CLOCK_CTRL_44MHZ_CORE);
2686 } else {
2687 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2688 }
2689
b401e9e2
MC		 2690 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2691 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 2692 }
2693 }
2694
05ac4cb7 2695 if (!(device_should_wake) &&
22435849 2696 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
0a459aac 2697 tg3_power_down_phy(tp, do_low_power);
6921d201 2698
1da177e4
LT		 2699 tg3_frob_aux_power(tp);
2700
2701 /* Workaround for unstable PLL clock */
2702 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2703 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2704 u32 val = tr32(0x7d00);
2705
2706 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2707 tw32(0x7d00, val);
6921d201 2708 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
ec41c7df
MC		 2709 int err;
2710
2711 err = tg3_nvram_lock(tp);
1da177e4 2712 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 2713 if (!err)
2714 tg3_nvram_unlock(tp);
6921d201 2715 }
1da177e4
LT		 2716 }
2717
bbadf503
MC		 2718 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2719
05ac4cb7 2720 if (device_should_wake)
12dac075
RW		 2721 pci_enable_wake(tp->pdev, state, true);
2722
1da177e4 2723 /* Finally, set the new power state. */
12dac075 2724 pci_set_power_state(tp->pdev, state);
1da177e4 2725
1da177e4
LT		 2726 return 0;
2727}
2728
1da177e4
LT		 2729static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2730{
2731 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2732 case MII_TG3_AUX_STAT_10HALF:
2733 *speed = SPEED_10;
2734 *duplex = DUPLEX_HALF;
2735 break;
2736
2737 case MII_TG3_AUX_STAT_10FULL:
2738 *speed = SPEED_10;
2739 *duplex = DUPLEX_FULL;
2740 break;
2741
2742 case MII_TG3_AUX_STAT_100HALF:
2743 *speed = SPEED_100;
2744 *duplex = DUPLEX_HALF;
2745 break;
2746
2747 case MII_TG3_AUX_STAT_100FULL:
2748 *speed = SPEED_100;
2749 *duplex = DUPLEX_FULL;
2750 break;
2751
2752 case MII_TG3_AUX_STAT_1000HALF:
2753 *speed = SPEED_1000;
2754 *duplex = DUPLEX_HALF;
2755 break;
2756
2757 case MII_TG3_AUX_STAT_1000FULL:
2758 *speed = SPEED_1000;
2759 *duplex = DUPLEX_FULL;
2760 break;
2761
2762 default:
7f97a4bd 2763 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
715116a1
MC		 2764 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2765 SPEED_10;
2766 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2767 DUPLEX_HALF;
2768 break;
2769 }
1da177e4
LT		 2770 *speed = SPEED_INVALID;
2771 *duplex = DUPLEX_INVALID;
2772 break;
855e1111 2773 }
1da177e4
LT		 2774}
2775
2776static void tg3_phy_copper_begin(struct tg3 *tp)
2777{
2778 u32 new_adv;
2779 int i;
2780
2781 if (tp->link_config.phy_is_low_power) {
2782 /* Entering low power mode. Disable gigabit and
2783 * 100baseT advertisements.
2784 */
2785 tg3_writephy(tp, MII_TG3_CTRL, 0);
2786
2787 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2788 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2789 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2790 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2791
2792 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793 } else if (tp->link_config.speed == SPEED_INVALID) {
1da177e4
LT		 2794 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2795 tp->link_config.advertising &=
2796 ~(ADVERTISED_1000baseT_Half |
2797 ADVERTISED_1000baseT_Full);
2798
ba4d07a8 2799 new_adv = ADVERTISE_CSMA;
1da177e4
LT		 2800 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2801 new_adv |= ADVERTISE_10HALF;
2802 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2803 new_adv |= ADVERTISE_10FULL;
2804 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2805 new_adv |= ADVERTISE_100HALF;
2806 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2807 new_adv |= ADVERTISE_100FULL;
ba4d07a8
MC		 2808
2809 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2810
1da177e4
LT		 2811 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2812
2813 if (tp->link_config.advertising &
2814 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2815 new_adv = 0;
2816 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2817 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2818 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2819 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2820 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2821 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2822 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2823 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2824 MII_TG3_CTRL_ENABLE_AS_MASTER);
2825 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826 } else {
2827 tg3_writephy(tp, MII_TG3_CTRL, 0);
2828 }
2829 } else {
ba4d07a8
MC		 2830 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831 new_adv |= ADVERTISE_CSMA;
2832
1da177e4
LT		 2833 /* Asking for a specific link mode. */
2834 if (tp->link_config.speed == SPEED_1000) {
1da177e4
LT		 2835 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837 if (tp->link_config.duplex == DUPLEX_FULL)
2838 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2839 else
2840 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2841 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2842 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2843 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2844 MII_TG3_CTRL_ENABLE_AS_MASTER);
1da177e4 2845 } else {
1da177e4
LT		 2846 if (tp->link_config.speed == SPEED_100) {
2847 if (tp->link_config.duplex == DUPLEX_FULL)
2848 new_adv |= ADVERTISE_100FULL;
2849 else
2850 new_adv |= ADVERTISE_100HALF;
2851 } else {
2852 if (tp->link_config.duplex == DUPLEX_FULL)
2853 new_adv |= ADVERTISE_10FULL;
2854 else
2855 new_adv |= ADVERTISE_10HALF;
2856 }
2857 tg3_writephy(tp, MII_ADVERTISE, new_adv);
ba4d07a8
MC		 2858
2859 new_adv = 0;
1da177e4 2860 }
ba4d07a8
MC		 2861
2862 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1da177e4
LT		 2863 }
2864
2865 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2866 tp->link_config.speed != SPEED_INVALID) {
2867 u32 bmcr, orig_bmcr;
2868
2869 tp->link_config.active_speed = tp->link_config.speed;
2870 tp->link_config.active_duplex = tp->link_config.duplex;
2871
2872 bmcr = 0;
2873 switch (tp->link_config.speed) {
2874 default:
2875 case SPEED_10:
2876 break;
2877
2878 case SPEED_100:
2879 bmcr |= BMCR_SPEED100;
2880 break;
2881
2882 case SPEED_1000:
2883 bmcr |= TG3_BMCR_SPEED1000;
2884 break;
855e1111 2885 }
1da177e4
LT		 2886
2887 if (tp->link_config.duplex == DUPLEX_FULL)
2888 bmcr |= BMCR_FULLDPLX;
2889
2890 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2891 (bmcr != orig_bmcr)) {
2892 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2893 for (i = 0; i < 1500; i++) {
2894 u32 tmp;
2895
2896 udelay(10);
2897 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2898 tg3_readphy(tp, MII_BMSR, &tmp))
2899 continue;
2900 if (!(tmp & BMSR_LSTATUS)) {
2901 udelay(40);
2902 break;
2903 }
2904 }
2905 tg3_writephy(tp, MII_BMCR, bmcr);
2906 udelay(40);
2907 }
2908 } else {
2909 tg3_writephy(tp, MII_BMCR,
2910 BMCR_ANENABLE | BMCR_ANRESTART);
2911 }
2912}
2913
2914static int tg3_init_5401phy_dsp(struct tg3 *tp)
2915{
2916 int err;
2917
2918 /* Turn off tap power management. */
2919 /* Set Extended packet length bit */
2920 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2921
2922 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2923 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2924
2925 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2926 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2927
2928 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2930
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2933
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2936
2937 udelay(40);
2938
2939 return err;
2940}
2941
3600d918 2942static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1da177e4 2943{
3600d918
MC		 2944 u32 adv_reg, all_mask = 0;
2945
2946 if (mask & ADVERTISED_10baseT_Half)
2947 all_mask |= ADVERTISE_10HALF;
2948 if (mask & ADVERTISED_10baseT_Full)
2949 all_mask |= ADVERTISE_10FULL;
2950 if (mask & ADVERTISED_100baseT_Half)
2951 all_mask |= ADVERTISE_100HALF;
2952 if (mask & ADVERTISED_100baseT_Full)
2953 all_mask |= ADVERTISE_100FULL;
1da177e4
LT		 2954
2955 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2956 return 0;
2957
1da177e4
LT		 2958 if ((adv_reg & all_mask) != all_mask)
2959 return 0;
2960 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2961 u32 tg3_ctrl;
2962
3600d918
MC		 2963 all_mask = 0;
2964 if (mask & ADVERTISED_1000baseT_Half)
2965 all_mask |= ADVERTISE_1000HALF;
2966 if (mask & ADVERTISED_1000baseT_Full)
2967 all_mask |= ADVERTISE_1000FULL;
2968
1da177e4
LT		 2969 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2970 return 0;
2971
1da177e4
LT		 2972 if ((tg3_ctrl & all_mask) != all_mask)
2973 return 0;
2974 }
2975 return 1;
2976}
2977
ef167e27
MC		 2978static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2979{
2980 u32 curadv, reqadv;
2981
2982 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2983 return 1;
2984
2985 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2986 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2987
2988 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2989 if (curadv != reqadv)
2990 return 0;
2991
2992 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2993 tg3_readphy(tp, MII_LPA, rmtadv);
2994 } else {
2995 /* Reprogram the advertisement register, even if it
2996 * does not affect the current link. If the link
2997 * gets renegotiated in the future, we can save an
2998 * additional renegotiation cycle by advertising
2999 * it correctly in the first place.
3000 */
3001 if (curadv != reqadv) {
3002 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3003 ADVERTISE_PAUSE_ASYM);
3004 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3005 }
3006 }
3007
3008 return 1;
3009}
3010
1da177e4
LT		 3011static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3012{
3013 int current_link_up;
3014 u32 bmsr, dummy;
ef167e27 3015 u32 lcl_adv, rmt_adv;
1da177e4
LT		 3016 u16 current_speed;
3017 u8 current_duplex;
3018 int i, err;
3019
3020 tw32(MAC_EVENT, 0);
3021
3022 tw32_f(MAC_STATUS,
3023 (MAC_STATUS_SYNC_CHANGED |
3024 MAC_STATUS_CFG_CHANGED |
3025 MAC_STATUS_MI_COMPLETION |
3026 MAC_STATUS_LNKSTATE_CHANGED));
3027 udelay(40);
3028
8ef21428
MC		 3029 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3030 tw32_f(MAC_MI_MODE,
3031 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3032 udelay(80);
3033 }
1da177e4
LT		 3034
3035 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3036
3037 /* Some third-party PHYs need to be reset on link going
3038 * down.
3039 */
3040 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3043 netif_carrier_ok(tp->dev)) {
3044 tg3_readphy(tp, MII_BMSR, &bmsr);
3045 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3046 !(bmsr & BMSR_LSTATUS))
3047 force_reset = 1;
3048 }
3049 if (force_reset)
3050 tg3_phy_reset(tp);
3051
3052 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3053 tg3_readphy(tp, MII_BMSR, &bmsr);
3054 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3055 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3056 bmsr = 0;
3057
3058 if (!(bmsr & BMSR_LSTATUS)) {
3059 err = tg3_init_5401phy_dsp(tp);
3060 if (err)
3061 return err;
3062
3063 tg3_readphy(tp, MII_BMSR, &bmsr);
3064 for (i = 0; i < 1000; i++) {
3065 udelay(10);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 (bmsr & BMSR_LSTATUS)) {
3068 udelay(40);
3069 break;
3070 }
3071 }
3072
3073 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3074 !(bmsr & BMSR_LSTATUS) &&
3075 tp->link_config.active_speed == SPEED_1000) {
3076 err = tg3_phy_reset(tp);
3077 if (!err)
3078 err = tg3_init_5401phy_dsp(tp);
3079 if (err)
3080 return err;
3081 }
3082 }
3083 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3084 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3085 /* 5701 {A0,B0} CRC bug workaround */
3086 tg3_writephy(tp, 0x15, 0x0a75);
3087 tg3_writephy(tp, 0x1c, 0x8c68);
3088 tg3_writephy(tp, 0x1c, 0x8d68);
3089 tg3_writephy(tp, 0x1c, 0x8c68);
3090 }
3091
3092 /* Clear pending interrupts... */
3093 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3095
3096 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3097 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
7f97a4bd 3098 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 3099 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3100
3101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3103 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3104 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3106 else
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3108 }
3109
3110 current_link_up = 0;
3111 current_speed = SPEED_INVALID;
3112 current_duplex = DUPLEX_INVALID;
3113
3114 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3115 u32 val;
3116
3117 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119 if (!(val & (1 << 10))) {
3120 val |= (1 << 10);
3121 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122 goto relink;
3123 }
3124 }
3125
3126 bmsr = 0;
3127 for (i = 0; i < 100; i++) {
3128 tg3_readphy(tp, MII_BMSR, &bmsr);
3129 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130 (bmsr & BMSR_LSTATUS))
3131 break;
3132 udelay(40);
3133 }
3134
3135 if (bmsr & BMSR_LSTATUS) {
3136 u32 aux_stat, bmcr;
3137
3138 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139 for (i = 0; i < 2000; i++) {
3140 udelay(10);
3141 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142 aux_stat)
3143 break;
3144 }
3145
3146 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147 &current_speed,
3148 &current_duplex);
3149
3150 bmcr = 0;
3151 for (i = 0; i < 200; i++) {
3152 tg3_readphy(tp, MII_BMCR, &bmcr);
3153 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154 continue;
3155 if (bmcr && bmcr != 0x7fff)
3156 break;
3157 udelay(10);
3158 }
3159
ef167e27
MC		 3160 lcl_adv = 0;
3161 rmt_adv = 0;
1da177e4 3162
ef167e27
MC		 3163 tp->link_config.active_speed = current_speed;
3164 tp->link_config.active_duplex = current_duplex;
3165
3166 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167 if ((bmcr & BMCR_ANENABLE) &&
3168 tg3_copper_is_advertising_all(tp,
3169 tp->link_config.advertising)) {
3170 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171 &rmt_adv))
3172 current_link_up = 1;
1da177e4
LT		 3173 }
3174 } else {
3175 if (!(bmcr & BMCR_ANENABLE) &&
3176 tp->link_config.speed == current_speed &&
ef167e27
MC		 3177 tp->link_config.duplex == current_duplex &&
3178 tp->link_config.flowctrl ==
3179 tp->link_config.active_flowctrl) {
1da177e4 3180 current_link_up = 1;
1da177e4
LT		 3181 }
3182 }
3183
ef167e27
MC		 3184 if (current_link_up == 1 &&
3185 tp->link_config.active_duplex == DUPLEX_FULL)
3186 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1da177e4
LT		 3187 }
3188
1da177e4 3189relink:
6921d201 3190 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1da177e4
LT		 3191 u32 tmp;
3192
3193 tg3_phy_copper_begin(tp);
3194
3195 tg3_readphy(tp, MII_BMSR, &tmp);
3196 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3197 (tmp & BMSR_LSTATUS))
3198 current_link_up = 1;
3199 }
3200
3201 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3202 if (current_link_up == 1) {
3203 if (tp->link_config.active_speed == SPEED_100 ||
3204 tp->link_config.active_speed == SPEED_10)
3205 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206 else
3207 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7f97a4bd
MC		 3208 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3209 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3210 else
1da177e4
LT		 3211 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3212
3213 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3214 if (tp->link_config.active_duplex == DUPLEX_HALF)
3215 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3216
1da177e4 3217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
e8f3f6ca
MC		 3218 if (current_link_up == 1 &&
3219 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 3220 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 3221 else
3222 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 3223 }
3224
3225 /* ??? Without this setting Netgear GA302T PHY does not
3226 * ??? send/receive packets...
3227 */
3228 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3229 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3230 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3231 tw32_f(MAC_MI_MODE, tp->mi_mode);
3232 udelay(80);
3233 }
3234
3235 tw32_f(MAC_MODE, tp->mac_mode);
3236 udelay(40);
3237
3238 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3239 /* Polled via timer. */
3240 tw32_f(MAC_EVENT, 0);
3241 } else {
3242 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3243 }
3244 udelay(40);
3245
3246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3247 current_link_up == 1 &&
3248 tp->link_config.active_speed == SPEED_1000 &&
3249 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3250 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251 udelay(120);
3252 tw32_f(MAC_STATUS,
3253 (MAC_STATUS_SYNC_CHANGED |
3254 MAC_STATUS_CFG_CHANGED));
3255 udelay(40);
3256 tg3_write_mem(tp,
3257 NIC_SRAM_FIRMWARE_MBOX,
3258 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259 }
3260
5e7dfd0f
MC		 3261 /* Prevent send BD corruption. */
3262 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3263 u16 oldlnkctl, newlnkctl;
3264
3265 pci_read_config_word(tp->pdev,
3266 tp->pcie_cap + PCI_EXP_LNKCTL,
3267 &oldlnkctl);
3268 if (tp->link_config.active_speed == SPEED_100 ||
3269 tp->link_config.active_speed == SPEED_10)
3270 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3271 else
3272 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3273 if (newlnkctl != oldlnkctl)
3274 pci_write_config_word(tp->pdev,
3275 tp->pcie_cap + PCI_EXP_LNKCTL,
3276 newlnkctl);
3277 }
3278
1da177e4
LT		 3279 if (current_link_up != netif_carrier_ok(tp->dev)) {
3280 if (current_link_up)
3281 netif_carrier_on(tp->dev);
3282 else
3283 netif_carrier_off(tp->dev);
3284 tg3_link_report(tp);
3285 }
3286
3287 return 0;
3288}
3289
3290struct tg3_fiber_aneginfo {
3291 int state;
3292#define ANEG_STATE_UNKNOWN 0
3293#define ANEG_STATE_AN_ENABLE 1
3294#define ANEG_STATE_RESTART_INIT 2
3295#define ANEG_STATE_RESTART 3
3296#define ANEG_STATE_DISABLE_LINK_OK 4
3297#define ANEG_STATE_ABILITY_DETECT_INIT 5
3298#define ANEG_STATE_ABILITY_DETECT 6
3299#define ANEG_STATE_ACK_DETECT_INIT 7
3300#define ANEG_STATE_ACK_DETECT 8
3301#define ANEG_STATE_COMPLETE_ACK_INIT 9
3302#define ANEG_STATE_COMPLETE_ACK 10
3303#define ANEG_STATE_IDLE_DETECT_INIT 11
3304#define ANEG_STATE_IDLE_DETECT 12
3305#define ANEG_STATE_LINK_OK 13
3306#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3307#define ANEG_STATE_NEXT_PAGE_WAIT 15
3308
3309 u32 flags;
3310#define MR_AN_ENABLE 0x00000001
3311#define MR_RESTART_AN 0x00000002
3312#define MR_AN_COMPLETE 0x00000004
3313#define MR_PAGE_RX 0x00000008
3314#define MR_NP_LOADED 0x00000010
3315#define MR_TOGGLE_TX 0x00000020
3316#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3317#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3318#define MR_LP_ADV_SYM_PAUSE 0x00000100
3319#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3320#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322#define MR_LP_ADV_NEXT_PAGE 0x00001000
3323#define MR_TOGGLE_RX 0x00002000
3324#define MR_NP_RX 0x00004000
3325
3326#define MR_LINK_OK 0x80000000
3327
3328 unsigned long link_time, cur_time;
3329
3330 u32 ability_match_cfg;
3331 int ability_match_count;
3332
3333 char ability_match, idle_match, ack_match;
3334
3335 u32 txconfig, rxconfig;
3336#define ANEG_CFG_NP 0x00000080
3337#define ANEG_CFG_ACK 0x00000040
3338#define ANEG_CFG_RF2 0x00000020
3339#define ANEG_CFG_RF1 0x00000010
3340#define ANEG_CFG_PS2 0x00000001
3341#define ANEG_CFG_PS1 0x00008000
3342#define ANEG_CFG_HD 0x00004000
3343#define ANEG_CFG_FD 0x00002000
3344#define ANEG_CFG_INVAL 0x00001f06
3345
3346};
3347#define ANEG_OK 0
3348#define ANEG_DONE 1
3349#define ANEG_TIMER_ENAB 2
3350#define ANEG_FAILED -1
3351
3352#define ANEG_STATE_SETTLE_TIME 10000
3353
3354static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3355 struct tg3_fiber_aneginfo *ap)
3356{
5be73b47 3357 u16 flowctrl;
1da177e4
LT		 3358 unsigned long delta;
3359 u32 rx_cfg_reg;
3360 int ret;
3361
3362 if (ap->state == ANEG_STATE_UNKNOWN) {
3363 ap->rxconfig = 0;
3364 ap->link_time = 0;
3365 ap->cur_time = 0;
3366 ap->ability_match_cfg = 0;
3367 ap->ability_match_count = 0;
3368 ap->ability_match = 0;
3369 ap->idle_match = 0;
3370 ap->ack_match = 0;
3371 }
3372 ap->cur_time++;
3373
3374 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3375 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3376
3377 if (rx_cfg_reg != ap->ability_match_cfg) {
3378 ap->ability_match_cfg = rx_cfg_reg;
3379 ap->ability_match = 0;
3380 ap->ability_match_count = 0;
3381 } else {
3382 if (++ap->ability_match_count > 1) {
3383 ap->ability_match = 1;
3384 ap->ability_match_cfg = rx_cfg_reg;
3385 }
3386 }
3387 if (rx_cfg_reg & ANEG_CFG_ACK)
3388 ap->ack_match = 1;
3389 else
3390 ap->ack_match = 0;
3391
3392 ap->idle_match = 0;
3393 } else {
3394 ap->idle_match = 1;
3395 ap->ability_match_cfg = 0;
3396 ap->ability_match_count = 0;
3397 ap->ability_match = 0;
3398 ap->ack_match = 0;
3399
3400 rx_cfg_reg = 0;
3401 }
3402
3403 ap->rxconfig = rx_cfg_reg;
3404 ret = ANEG_OK;
3405
3406 switch(ap->state) {
3407 case ANEG_STATE_UNKNOWN:
3408 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3409 ap->state = ANEG_STATE_AN_ENABLE;
3410
3411 /* fallthru */
3412 case ANEG_STATE_AN_ENABLE:
3413 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3414 if (ap->flags & MR_AN_ENABLE) {
3415 ap->link_time = 0;
3416 ap->cur_time = 0;
3417 ap->ability_match_cfg = 0;
3418 ap->ability_match_count = 0;
3419 ap->ability_match = 0;
3420 ap->idle_match = 0;
3421 ap->ack_match = 0;
3422
3423 ap->state = ANEG_STATE_RESTART_INIT;
3424 } else {
3425 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3426 }
3427 break;
3428
3429 case ANEG_STATE_RESTART_INIT:
3430 ap->link_time = ap->cur_time;
3431 ap->flags &= ~(MR_NP_LOADED);
3432 ap->txconfig = 0;
3433 tw32(MAC_TX_AUTO_NEG, 0);
3434 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3435 tw32_f(MAC_MODE, tp->mac_mode);
3436 udelay(40);
3437
3438 ret = ANEG_TIMER_ENAB;
3439 ap->state = ANEG_STATE_RESTART;
3440
3441 /* fallthru */
3442 case ANEG_STATE_RESTART:
3443 delta = ap->cur_time - ap->link_time;
3444 if (delta > ANEG_STATE_SETTLE_TIME) {
3445 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3446 } else {
3447 ret = ANEG_TIMER_ENAB;
3448 }
3449 break;
3450
3451 case ANEG_STATE_DISABLE_LINK_OK:
3452 ret = ANEG_DONE;
3453 break;
3454
3455 case ANEG_STATE_ABILITY_DETECT_INIT:
3456 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 3457 ap->txconfig = ANEG_CFG_FD;
3458 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459 if (flowctrl & ADVERTISE_1000XPAUSE)
3460 ap->txconfig |= ANEG_CFG_PS1;
3461 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 3463 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465 tw32_f(MAC_MODE, tp->mac_mode);
3466 udelay(40);
3467
3468 ap->state = ANEG_STATE_ABILITY_DETECT;
3469 break;
3470
3471 case ANEG_STATE_ABILITY_DETECT:
3472 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3473 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474 }
3475 break;
3476
3477 case ANEG_STATE_ACK_DETECT_INIT:
3478 ap->txconfig |= ANEG_CFG_ACK;
3479 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3480 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3481 tw32_f(MAC_MODE, tp->mac_mode);
3482 udelay(40);
3483
3484 ap->state = ANEG_STATE_ACK_DETECT;
3485
3486 /* fallthru */
3487 case ANEG_STATE_ACK_DETECT:
3488 if (ap->ack_match != 0) {
3489 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3490 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3491 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3492 } else {
3493 ap->state = ANEG_STATE_AN_ENABLE;
3494 }
3495 } else if (ap->ability_match != 0 &&
3496 ap->rxconfig == 0) {
3497 ap->state = ANEG_STATE_AN_ENABLE;
3498 }
3499 break;
3500
3501 case ANEG_STATE_COMPLETE_ACK_INIT:
3502 if (ap->rxconfig & ANEG_CFG_INVAL) {
3503 ret = ANEG_FAILED;
3504 break;
3505 }
3506 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3507 MR_LP_ADV_HALF_DUPLEX |
3508 MR_LP_ADV_SYM_PAUSE |
3509 MR_LP_ADV_ASYM_PAUSE |
3510 MR_LP_ADV_REMOTE_FAULT1 |
3511 MR_LP_ADV_REMOTE_FAULT2 |
3512 MR_LP_ADV_NEXT_PAGE |
3513 MR_TOGGLE_RX |
3514 MR_NP_RX);
3515 if (ap->rxconfig & ANEG_CFG_FD)
3516 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3517 if (ap->rxconfig & ANEG_CFG_HD)
3518 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3519 if (ap->rxconfig & ANEG_CFG_PS1)
3520 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3521 if (ap->rxconfig & ANEG_CFG_PS2)
3522 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3523 if (ap->rxconfig & ANEG_CFG_RF1)
3524 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3525 if (ap->rxconfig & ANEG_CFG_RF2)
3526 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3527 if (ap->rxconfig & ANEG_CFG_NP)
3528 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3529
3530 ap->link_time = ap->cur_time;
3531
3532 ap->flags ^= (MR_TOGGLE_TX);
3533 if (ap->rxconfig & 0x0008)
3534 ap->flags |= MR_TOGGLE_RX;
3535 if (ap->rxconfig & ANEG_CFG_NP)
3536 ap->flags |= MR_NP_RX;
3537 ap->flags |= MR_PAGE_RX;
3538
3539 ap->state = ANEG_STATE_COMPLETE_ACK;
3540 ret = ANEG_TIMER_ENAB;
3541 break;
3542
3543 case ANEG_STATE_COMPLETE_ACK:
3544 if (ap->ability_match != 0 &&
3545 ap->rxconfig == 0) {
3546 ap->state = ANEG_STATE_AN_ENABLE;
3547 break;
3548 }
3549 delta = ap->cur_time - ap->link_time;
3550 if (delta > ANEG_STATE_SETTLE_TIME) {
3551 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3552 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553 } else {
3554 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3555 !(ap->flags & MR_NP_RX)) {
3556 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3557 } else {
3558 ret = ANEG_FAILED;
3559 }
3560 }
3561 }
3562 break;
3563
3564 case ANEG_STATE_IDLE_DETECT_INIT:
3565 ap->link_time = ap->cur_time;
3566 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3567 tw32_f(MAC_MODE, tp->mac_mode);
3568 udelay(40);
3569
3570 ap->state = ANEG_STATE_IDLE_DETECT;
3571 ret = ANEG_TIMER_ENAB;
3572 break;
3573
3574 case ANEG_STATE_IDLE_DETECT:
3575 if (ap->ability_match != 0 &&
3576 ap->rxconfig == 0) {
3577 ap->state = ANEG_STATE_AN_ENABLE;
3578 break;
3579 }
3580 delta = ap->cur_time - ap->link_time;
3581 if (delta > ANEG_STATE_SETTLE_TIME) {
3582 /* XXX another gem from the Broadcom driver :( */
3583 ap->state = ANEG_STATE_LINK_OK;
3584 }
3585 break;
3586
3587 case ANEG_STATE_LINK_OK:
3588 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3589 ret = ANEG_DONE;
3590 break;
3591
3592 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3593 /* ??? unimplemented */
3594 break;
3595
3596 case ANEG_STATE_NEXT_PAGE_WAIT:
3597 /* ??? unimplemented */
3598 break;
3599
3600 default:
3601 ret = ANEG_FAILED;
3602 break;
855e1111 3603 }
1da177e4
LT		 3604
3605 return ret;
3606}
3607
5be73b47 3608static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 3609{
3610 int res = 0;
3611 struct tg3_fiber_aneginfo aninfo;
3612 int status = ANEG_FAILED;
3613 unsigned int tick;
3614 u32 tmp;
3615
3616 tw32_f(MAC_TX_AUTO_NEG, 0);
3617
3618 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3619 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3620 udelay(40);
3621
3622 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3623 udelay(40);
3624
3625 memset(&aninfo, 0, sizeof(aninfo));
3626 aninfo.flags |= MR_AN_ENABLE;
3627 aninfo.state = ANEG_STATE_UNKNOWN;
3628 aninfo.cur_time = 0;
3629 tick = 0;
3630 while (++tick < 195000) {
3631 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3632 if (status == ANEG_DONE || status == ANEG_FAILED)
3633 break;
3634
3635 udelay(1);
3636 }
3637
3638 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3639 tw32_f(MAC_MODE, tp->mac_mode);
3640 udelay(40);
3641
5be73b47
MC		 3642 *txflags = aninfo.txconfig;
3643 *rxflags = aninfo.flags;
1da177e4
LT		 3644
3645 if (status == ANEG_DONE &&
3646 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3647 MR_LP_ADV_FULL_DUPLEX)))
3648 res = 1;
3649
3650 return res;
3651}
3652
3653static void tg3_init_bcm8002(struct tg3 *tp)
3654{
3655 u32 mac_status = tr32(MAC_STATUS);
3656 int i;
3657
3658 /* Reset when initting first time or we have a link. */
3659 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3660 !(mac_status & MAC_STATUS_PCS_SYNCED))
3661 return;
3662
3663 /* Set PLL lock range. */
3664 tg3_writephy(tp, 0x16, 0x8007);
3665
3666 /* SW reset */
3667 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3668
3669 /* Wait for reset to complete. */
3670 /* XXX schedule_timeout() ... */
3671 for (i = 0; i < 500; i++)
3672 udelay(10);
3673
3674 /* Config mode; select PMA/Ch 1 regs. */
3675 tg3_writephy(tp, 0x10, 0x8411);
3676
3677 /* Enable auto-lock and comdet, select txclk for tx. */
3678 tg3_writephy(tp, 0x11, 0x0a10);
3679
3680 tg3_writephy(tp, 0x18, 0x00a0);
3681 tg3_writephy(tp, 0x16, 0x41ff);
3682
3683 /* Assert and deassert POR. */
3684 tg3_writephy(tp, 0x13, 0x0400);
3685 udelay(40);
3686 tg3_writephy(tp, 0x13, 0x0000);
3687
3688 tg3_writephy(tp, 0x11, 0x0a50);
3689 udelay(40);
3690 tg3_writephy(tp, 0x11, 0x0a10);
3691
3692 /* Wait for signal to stabilize */
3693 /* XXX schedule_timeout() ... */
3694 for (i = 0; i < 15000; i++)
3695 udelay(10);
3696
3697 /* Deselect the channel register so we can read the PHYID
3698 * later.
3699 */
3700 tg3_writephy(tp, 0x10, 0x8011);
3701}
3702
3703static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3704{
82cd3d11 3705 u16 flowctrl;
1da177e4
LT		 3706 u32 sg_dig_ctrl, sg_dig_status;
3707 u32 serdes_cfg, expected_sg_dig_ctrl;
3708 int workaround, port_a;
3709 int current_link_up;
3710
3711 serdes_cfg = 0;
3712 expected_sg_dig_ctrl = 0;
3713 workaround = 0;
3714 port_a = 1;
3715 current_link_up = 0;
3716
3717 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3718 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3719 workaround = 1;
3720 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3721 port_a = 0;
3722
3723 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724 /* preserve bits 20-23 for voltage regulator */
3725 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3726 }
3727
3728 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3729
3730 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 3731 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 3732 if (workaround) {
3733 u32 val = serdes_cfg;
3734
3735 if (port_a)
3736 val |= 0xc010000;
3737 else
3738 val |= 0x4010000;
3739 tw32_f(MAC_SERDES_CFG, val);
3740 }
c98f6e3b
MC		 3741
3742 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3743 }
3744 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3745 tg3_setup_flow_control(tp, 0, 0);
3746 current_link_up = 1;
3747 }
3748 goto out;
3749 }
3750
3751 /* Want auto-negotiation. */
c98f6e3b 3752 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 3753
82cd3d11
MC		 3754 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3755 if (flowctrl & ADVERTISE_1000XPAUSE)
3756 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3757 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3758 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 3759
3760 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3d3ebe74
MC		 3761 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3762 tp->serdes_counter &&
3763 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3764 MAC_STATUS_RCVD_CFG)) ==
3765 MAC_STATUS_PCS_SYNCED)) {
3766 tp->serdes_counter--;
3767 current_link_up = 1;
3768 goto out;
3769 }
3770restart_autoneg:
1da177e4
LT		 3771 if (workaround)
3772 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 3773 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 3774 udelay(5);
3775 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3776
3d3ebe74
MC		 3777 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3778 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3779 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3780 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 3781 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 3782 mac_status = tr32(MAC_STATUS);
3783
c98f6e3b 3784 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 3785 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 3786 u32 local_adv = 0, remote_adv = 0;
3787
3788 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3789 local_adv |= ADVERTISE_1000XPAUSE;
3790 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3791 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 3792
c98f6e3b 3793 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 3794 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 3795 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 3796 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3797
3798 tg3_setup_flow_control(tp, local_adv, remote_adv);
3799 current_link_up = 1;
3d3ebe74
MC		 3800 tp->serdes_counter = 0;
3801 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
c98f6e3b 3802 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 3803 if (tp->serdes_counter)
3804 tp->serdes_counter--;
1da177e4
LT		 3805 else {
3806 if (workaround) {
3807 u32 val = serdes_cfg;
3808
3809 if (port_a)
3810 val |= 0xc010000;
3811 else
3812 val |= 0x4010000;
3813
3814 tw32_f(MAC_SERDES_CFG, val);
3815 }
3816
c98f6e3b 3817 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 3818 udelay(40);
3819
3820 /* Link parallel detection - link is up */
3821 /* only if we have PCS_SYNC and not */
3822 /* receiving config code words */
3823 mac_status = tr32(MAC_STATUS);
3824 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3825 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3826 tg3_setup_flow_control(tp, 0, 0);
3827 current_link_up = 1;
3d3ebe74
MC		 3828 tp->tg3_flags2 |=
3829 TG3_FLG2_PARALLEL_DETECT;
3830 tp->serdes_counter =
3831 SERDES_PARALLEL_DET_TIMEOUT;
3832 } else
3833 goto restart_autoneg;
1da177e4
LT		 3834 }
3835 }
3d3ebe74
MC		 3836 } else {
3837 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3838 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
1da177e4
LT		 3839 }
3840
3841out:
3842 return current_link_up;
3843}
3844
3845static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3846{
3847 int current_link_up = 0;
3848
5cf64b8a 3849 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 3850 goto out;
1da177e4
LT		 3851
3852 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 3853 u32 txflags, rxflags;
1da177e4 3854 int i;
6aa20a22 3855
5be73b47
MC		 3856 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3857 u32 local_adv = 0, remote_adv = 0;
1da177e4 3858
5be73b47
MC		 3859 if (txflags & ANEG_CFG_PS1)
3860 local_adv |= ADVERTISE_1000XPAUSE;
3861 if (txflags & ANEG_CFG_PS2)
3862 local_adv |= ADVERTISE_1000XPSE_ASYM;
3863
3864 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3865 remote_adv |= LPA_1000XPAUSE;
3866 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3867 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4
LT		 3868
3869 tg3_setup_flow_control(tp, local_adv, remote_adv);
3870
1da177e4
LT		 3871 current_link_up = 1;
3872 }
3873 for (i = 0; i < 30; i++) {
3874 udelay(20);
3875 tw32_f(MAC_STATUS,
3876 (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED));
3878 udelay(40);
3879 if ((tr32(MAC_STATUS) &
3880 (MAC_STATUS_SYNC_CHANGED |
3881 MAC_STATUS_CFG_CHANGED)) == 0)
3882 break;
3883 }
3884
3885 mac_status = tr32(MAC_STATUS);
3886 if (current_link_up == 0 &&
3887 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3888 !(mac_status & MAC_STATUS_RCVD_CFG))
3889 current_link_up = 1;
3890 } else {
5be73b47
MC		 3891 tg3_setup_flow_control(tp, 0, 0);
3892
1da177e4
LT		 3893 /* Forcing 1000FD link up. */
3894 current_link_up = 1;
1da177e4
LT		 3895
3896 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3897 udelay(40);
e8f3f6ca
MC		 3898
3899 tw32_f(MAC_MODE, tp->mac_mode);
3900 udelay(40);
1da177e4
LT		 3901 }
3902
3903out:
3904 return current_link_up;
3905}
3906
3907static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3908{
3909 u32 orig_pause_cfg;
3910 u16 orig_active_speed;
3911 u8 orig_active_duplex;
3912 u32 mac_status;
3913 int current_link_up;
3914 int i;
3915
8d018621 3916 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 3917 orig_active_speed = tp->link_config.active_speed;
3918 orig_active_duplex = tp->link_config.active_duplex;
3919
3920 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3921 netif_carrier_ok(tp->dev) &&
3922 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3923 mac_status = tr32(MAC_STATUS);
3924 mac_status &= (MAC_STATUS_PCS_SYNCED |
3925 MAC_STATUS_SIGNAL_DET |
3926 MAC_STATUS_CFG_CHANGED |
3927 MAC_STATUS_RCVD_CFG);
3928 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3929 MAC_STATUS_SIGNAL_DET)) {
3930 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3931 MAC_STATUS_CFG_CHANGED));
3932 return 0;
3933 }
3934 }
3935
3936 tw32_f(MAC_TX_AUTO_NEG, 0);
3937
3938 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3939 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3940 tw32_f(MAC_MODE, tp->mac_mode);
3941 udelay(40);
3942
3943 if (tp->phy_id == PHY_ID_BCM8002)
3944 tg3_init_bcm8002(tp);
3945
3946 /* Enable link change event even when serdes polling. */
3947 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3948 udelay(40);
3949
3950 current_link_up = 0;
3951 mac_status = tr32(MAC_STATUS);
3952
3953 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3954 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3955 else
3956 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3957
898a56f8 3958 tp->napi[0].hw_status->status =
1da177e4 3959 (SD_STATUS_UPDATED |
898a56f8 3960 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 3961
3962 for (i = 0; i < 100; i++) {
3963 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964 MAC_STATUS_CFG_CHANGED));
3965 udelay(5);
3966 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 3967 MAC_STATUS_CFG_CHANGED |
3968 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 3969 break;
3970 }
3971
3972 mac_status = tr32(MAC_STATUS);
3973 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3974 current_link_up = 0;
3d3ebe74
MC		 3975 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3976 tp->serdes_counter == 0) {
1da177e4
LT		 3977 tw32_f(MAC_MODE, (tp->mac_mode |
3978 MAC_MODE_SEND_CONFIGS));
3979 udelay(1);
3980 tw32_f(MAC_MODE, tp->mac_mode);
3981 }
3982 }
3983
3984 if (current_link_up == 1) {
3985 tp->link_config.active_speed = SPEED_1000;
3986 tp->link_config.active_duplex = DUPLEX_FULL;
3987 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988 LED_CTRL_LNKLED_OVERRIDE |
3989 LED_CTRL_1000MBPS_ON));
3990 } else {
3991 tp->link_config.active_speed = SPEED_INVALID;
3992 tp->link_config.active_duplex = DUPLEX_INVALID;
3993 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994 LED_CTRL_LNKLED_OVERRIDE |
3995 LED_CTRL_TRAFFIC_OVERRIDE));
3996 }
3997
3998 if (current_link_up != netif_carrier_ok(tp->dev)) {
3999 if (current_link_up)
4000 netif_carrier_on(tp->dev);
4001 else
4002 netif_carrier_off(tp->dev);
4003 tg3_link_report(tp);
4004 } else {
8d018621 4005 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 4006 if (orig_pause_cfg != now_pause_cfg ||
4007 orig_active_speed != tp->link_config.active_speed ||
4008 orig_active_duplex != tp->link_config.active_duplex)
4009 tg3_link_report(tp);
4010 }
4011
4012 return 0;
4013}
4014
747e8f8b
MC		 4015static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4016{
4017 int current_link_up, err = 0;
4018 u32 bmsr, bmcr;
4019 u16 current_speed;
4020 u8 current_duplex;
ef167e27 4021 u32 local_adv, remote_adv;
747e8f8b
MC		 4022
4023 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4024 tw32_f(MAC_MODE, tp->mac_mode);
4025 udelay(40);
4026
4027 tw32(MAC_EVENT, 0);
4028
4029 tw32_f(MAC_STATUS,
4030 (MAC_STATUS_SYNC_CHANGED |
4031 MAC_STATUS_CFG_CHANGED |
4032 MAC_STATUS_MI_COMPLETION |
4033 MAC_STATUS_LNKSTATE_CHANGED));
4034 udelay(40);
4035
4036 if (force_reset)
4037 tg3_phy_reset(tp);
4038
4039 current_link_up = 0;
4040 current_speed = SPEED_INVALID;
4041 current_duplex = DUPLEX_INVALID;
4042
4043 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4046 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4047 bmsr |= BMSR_LSTATUS;
4048 else
4049 bmsr &= ~BMSR_LSTATUS;
4050 }
747e8f8b
MC		 4051
4052 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4053
4054 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2bd3ed04 4055 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
747e8f8b
MC		 4056 /* do nothing, just check for link up at the end */
4057 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4058 u32 adv, new_adv;
4059
4060 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4062 ADVERTISE_1000XPAUSE |
4063 ADVERTISE_1000XPSE_ASYM |
4064 ADVERTISE_SLCT);
4065
ba4d07a8 4066 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
747e8f8b
MC		 4067
4068 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4069 new_adv |= ADVERTISE_1000XHALF;
4070 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4071 new_adv |= ADVERTISE_1000XFULL;
4072
4073 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4074 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4075 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4076 tg3_writephy(tp, MII_BMCR, bmcr);
4077
4078 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 4079 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
747e8f8b
MC		 4080 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081
4082 return err;
4083 }
4084 } else {
4085 u32 new_bmcr;
4086
4087 bmcr &= ~BMCR_SPEED1000;
4088 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4089
4090 if (tp->link_config.duplex == DUPLEX_FULL)
4091 new_bmcr |= BMCR_FULLDPLX;
4092
4093 if (new_bmcr != bmcr) {
4094 /* BMCR_SPEED1000 is a reserved bit that needs
4095 * to be set on write.
4096 */
4097 new_bmcr |= BMCR_SPEED1000;
4098
4099 /* Force a linkdown */
4100 if (netif_carrier_ok(tp->dev)) {
4101 u32 adv;
4102
4103 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4104 adv &= ~(ADVERTISE_1000XFULL |
4105 ADVERTISE_1000XHALF |
4106 ADVERTISE_SLCT);
4107 tg3_writephy(tp, MII_ADVERTISE, adv);
4108 tg3_writephy(tp, MII_BMCR, bmcr |
4109 BMCR_ANRESTART |
4110 BMCR_ANENABLE);
4111 udelay(10);
4112 netif_carrier_off(tp->dev);
4113 }
4114 tg3_writephy(tp, MII_BMCR, new_bmcr);
4115 bmcr = new_bmcr;
4116 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
d4d2c558
MC		 4118 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4119 ASIC_REV_5714) {
4120 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4121 bmsr |= BMSR_LSTATUS;
4122 else
4123 bmsr &= ~BMSR_LSTATUS;
4124 }
747e8f8b
MC		 4125 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126 }
4127 }
4128
4129 if (bmsr & BMSR_LSTATUS) {
4130 current_speed = SPEED_1000;
4131 current_link_up = 1;
4132 if (bmcr & BMCR_FULLDPLX)
4133 current_duplex = DUPLEX_FULL;
4134 else
4135 current_duplex = DUPLEX_HALF;
4136
ef167e27
MC		 4137 local_adv = 0;
4138 remote_adv = 0;
4139
747e8f8b 4140 if (bmcr & BMCR_ANENABLE) {
ef167e27 4141 u32 common;
747e8f8b
MC		 4142
4143 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4144 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4145 common = local_adv & remote_adv;
4146 if (common & (ADVERTISE_1000XHALF |
4147 ADVERTISE_1000XFULL)) {
4148 if (common & ADVERTISE_1000XFULL)
4149 current_duplex = DUPLEX_FULL;
4150 else
4151 current_duplex = DUPLEX_HALF;
747e8f8b
MC		 4152 }
4153 else
4154 current_link_up = 0;
4155 }
4156 }
4157
ef167e27
MC		 4158 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4159 tg3_setup_flow_control(tp, local_adv, remote_adv);
4160
747e8f8b
MC		 4161 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4162 if (tp->link_config.active_duplex == DUPLEX_HALF)
4163 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4164
4165 tw32_f(MAC_MODE, tp->mac_mode);
4166 udelay(40);
4167
4168 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4169
4170 tp->link_config.active_speed = current_speed;
4171 tp->link_config.active_duplex = current_duplex;
4172
4173 if (current_link_up != netif_carrier_ok(tp->dev)) {
4174 if (current_link_up)
4175 netif_carrier_on(tp->dev);
4176 else {
4177 netif_carrier_off(tp->dev);
4178 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179 }
4180 tg3_link_report(tp);
4181 }
4182 return err;
4183}
4184
4185static void tg3_serdes_parallel_detect(struct tg3 *tp)
4186{
3d3ebe74 4187 if (tp->serdes_counter) {
747e8f8b 4188 /* Give autoneg time to complete. */
3d3ebe74 4189 tp->serdes_counter--;
747e8f8b
MC		 4190 return;
4191 }
4192 if (!netif_carrier_ok(tp->dev) &&
4193 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194 u32 bmcr;
4195
4196 tg3_readphy(tp, MII_BMCR, &bmcr);
4197 if (bmcr & BMCR_ANENABLE) {
4198 u32 phy1, phy2;
4199
4200 /* Select shadow register 0x1f */
4201 tg3_writephy(tp, 0x1c, 0x7c00);
4202 tg3_readphy(tp, 0x1c, &phy1);
4203
4204 /* Select expansion interrupt status register */
4205 tg3_writephy(tp, 0x17, 0x0f01);
4206 tg3_readphy(tp, 0x15, &phy2);
4207 tg3_readphy(tp, 0x15, &phy2);
4208
4209 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210 /* We have signal detect and not receiving
4211 * config code words, link is up by parallel
4212 * detection.
4213 */
4214
4215 bmcr &= ~BMCR_ANENABLE;
4216 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217 tg3_writephy(tp, MII_BMCR, bmcr);
4218 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4219 }
4220 }
4221 }
4222 else if (netif_carrier_ok(tp->dev) &&
4223 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4225 u32 phy2;
4226
4227 /* Select expansion interrupt status register */
4228 tg3_writephy(tp, 0x17, 0x0f01);
4229 tg3_readphy(tp, 0x15, &phy2);
4230 if (phy2 & 0x20) {
4231 u32 bmcr;
4232
4233 /* Config code words received, turn on autoneg. */
4234 tg3_readphy(tp, MII_BMCR, &bmcr);
4235 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238
4239 }
4240 }
4241}
4242
1da177e4
LT		 4243static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244{
4245 int err;
4246
4247 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4248 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 4249 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4250 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 4251 } else {
4252 err = tg3_setup_copper_phy(tp, force_reset);
4253 }
4254
bcb37f6c 4255 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
aa6c91fe
MC		 4256 u32 val, scale;
4257
4258 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260 scale = 65;
4261 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262 scale = 6;
4263 else
4264 scale = 12;
4265
4266 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268 tw32(GRC_MISC_CFG, val);
4269 }
4270
1da177e4
LT		 4271 if (tp->link_config.active_speed == SPEED_1000 &&
4272 tp->link_config.active_duplex == DUPLEX_HALF)
4273 tw32(MAC_TX_LENGTHS,
4274 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275 (6 << TX_LENGTHS_IPG_SHIFT) |
4276 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277 else
4278 tw32(MAC_TX_LENGTHS,
4279 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280 (6 << TX_LENGTHS_IPG_SHIFT) |
4281 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284 if (netif_carrier_ok(tp->dev)) {
4285 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 4286 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 4287 } else {
4288 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289 }
4290 }
4291
8ed5d97e
MC		 4292 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294 if (!netif_carrier_ok(tp->dev))
4295 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296 tp->pwrmgmt_thresh;
4297 else
4298 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299 tw32(PCIE_PWR_MGMT_THRESH, val);
4300 }
4301
1da177e4
LT		 4302 return err;
4303}
4304
df3e6548
MC		 4305/* This is called whenever we suspect that the system chipset is re-
4306 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307 * is bogus tx completions. We try to recover by setting the
4308 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4309 * in the workqueue.
4310 */
4311static void tg3_tx_recover(struct tg3 *tp)
4312{
4313 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4314 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4315
4316 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4317 "mapped I/O cycles to the network device, attempting to "
4318 "recover. Please report the problem to the driver maintainer "
4319 "and include system chipset information.\n", tp->dev->name);
4320
4321 spin_lock(&tp->lock);
df3e6548 4322 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
df3e6548
MC		 4323 spin_unlock(&tp->lock);
4324}
4325
f3f3f27e 4326static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205
MC		 4327{
4328 smp_mb();
f3f3f27e
MC		 4329 return tnapi->tx_pending -
4330 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 4331}
4332
1da177e4
LT		 4333/* Tigon3 never reports partial packet sends. So we do not
4334 * need special logic to handle SKBs that have not had all
4335 * of their frags sent yet, like SunGEM does.
4336 */
17375d25 4337static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 4338{
17375d25 4339 struct tg3 *tp = tnapi->tp;
898a56f8 4340 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 4341 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 4342 struct netdev_queue *txq;
4343 int index = tnapi - tp->napi;
4344
4345 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4346 index--;
4347
4348 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 4349
4350 while (sw_idx != hw_idx) {
f3f3f27e 4351 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 4352 struct sk_buff *skb = ri->skb;
df3e6548
MC		 4353 int i, tx_bug = 0;
4354
4355 if (unlikely(skb == NULL)) {
4356 tg3_tx_recover(tp);
4357 return;
4358 }
1da177e4 4359
90079ce8 4360 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 4361
4362 ri->skb = NULL;
4363
4364 sw_idx = NEXT_TX(sw_idx);
4365
4366 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 4367 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 4368 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4369 tx_bug = 1;
1da177e4
LT		 4370 sw_idx = NEXT_TX(sw_idx);
4371 }
4372
f47c11ee 4373 dev_kfree_skb(skb);
df3e6548
MC		 4374
4375 if (unlikely(tx_bug)) {
4376 tg3_tx_recover(tp);
4377 return;
4378 }
1da177e4
LT		 4379 }
4380
f3f3f27e 4381 tnapi->tx_cons = sw_idx;
1da177e4 4382
1b2a7205
MC		 4383 /* Need to make the tx_cons update visible to tg3_start_xmit()
4384 * before checking for netif_queue_stopped(). Without the
4385 * memory barrier, there is a small possibility that tg3_start_xmit()
4386 * will miss it and cause the queue to be stopped forever.
4387 */
4388 smp_mb();
4389
fe5f5787 4390 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 4391 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 4392 __netif_tx_lock(txq, smp_processor_id());
4393 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 4394 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 4395 netif_tx_wake_queue(txq);
4396 __netif_tx_unlock(txq);
51b91468 4397 }
1da177e4
LT		 4398}
4399
4400/* Returns size of skb allocated or < 0 on error.
4401 *
4402 * We only need to fill in the address because the other members
4403 * of the RX descriptor are invariant, see tg3_init_rings.
4404 *
4405 * Note the purposeful assymetry of cpu vs. chip accesses. For
4406 * posting buffers we only dirty the first cache line of the RX
4407 * descriptor (containing the address). Whereas for the RX status
4408 * buffers the cpu only reads the last cacheline of the RX descriptor
4409 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4410 */
17375d25 4411static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4412 int src_idx, u32 dest_idx_unmasked)
4413{
17375d25 4414 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4415 struct tg3_rx_buffer_desc *desc;
4416 struct ring_info *map, *src_map;
4417 struct sk_buff *skb;
4418 dma_addr_t mapping;
4419 int skb_size, dest_idx;
21f581a5 4420 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4421
4422 src_map = NULL;
4423 switch (opaque_key) {
4424 case RXD_OPAQUE_RING_STD:
4425 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4426 desc = &tpr->rx_std[dest_idx];
4427 map = &tpr->rx_std_buffers[dest_idx];
1da177e4 4428 if (src_idx >= 0)
21f581a5 4429 src_map = &tpr->rx_std_buffers[src_idx];
287be12e 4430 skb_size = tp->rx_pkt_map_sz;
1da177e4
LT		 4431 break;
4432
4433 case RXD_OPAQUE_RING_JUMBO:
4434 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4435 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4436 map = &tpr->rx_jmb_buffers[dest_idx];
1da177e4 4437 if (src_idx >= 0)
21f581a5 4438 src_map = &tpr->rx_jmb_buffers[src_idx];
287be12e 4439 skb_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 4440 break;
4441
4442 default:
4443 return -EINVAL;
855e1111 4444 }
1da177e4
LT		 4445
4446 /* Do not overwrite any of the map or rp information
4447 * until we are sure we can commit to a new buffer.
4448 *
4449 * Callers depend upon this behavior and assume that
4450 * we leave everything unchanged if we fail.
4451 */
287be12e 4452 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
1da177e4
LT		 4453 if (skb == NULL)
4454 return -ENOMEM;
4455
1da177e4
LT		 4456 skb_reserve(skb, tp->rx_offset);
4457
287be12e 4458 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
1da177e4 4459 PCI_DMA_FROMDEVICE);
a21771dd
MC		 4460 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4461 dev_kfree_skb(skb);
4462 return -EIO;
4463 }
1da177e4
LT		 4464
4465 map->skb = skb;
4466 pci_unmap_addr_set(map, mapping, mapping);
4467
4468 if (src_map != NULL)
4469 src_map->skb = NULL;
4470
4471 desc->addr_hi = ((u64)mapping >> 32);
4472 desc->addr_lo = ((u64)mapping & 0xffffffff);
4473
4474 return skb_size;
4475}
4476
4477/* We only need to move over in the address because the other
4478 * members of the RX descriptor are invariant. See notes above
4479 * tg3_alloc_rx_skb for full details.
4480 */
17375d25 4481static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
1da177e4
LT		 4482 int src_idx, u32 dest_idx_unmasked)
4483{
17375d25 4484 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 4485 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4486 struct ring_info *src_map, *dest_map;
4487 int dest_idx;
21f581a5 4488 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 4489
4490 switch (opaque_key) {
4491 case RXD_OPAQUE_RING_STD:
4492 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
21f581a5
MC		 4493 dest_desc = &tpr->rx_std[dest_idx];
4494 dest_map = &tpr->rx_std_buffers[dest_idx];
4495 src_desc = &tpr->rx_std[src_idx];
4496 src_map = &tpr->rx_std_buffers[src_idx];
1da177e4
LT		 4497 break;
4498
4499 case RXD_OPAQUE_RING_JUMBO:
4500 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
79ed5ac7 4501 dest_desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 4502 dest_map = &tpr->rx_jmb_buffers[dest_idx];
79ed5ac7 4503 src_desc = &tpr->rx_jmb[src_idx].std;
21f581a5 4504 src_map = &tpr->rx_jmb_buffers[src_idx];
1da177e4
LT		 4505 break;
4506
4507 default:
4508 return;
855e1111 4509 }
1da177e4
LT		 4510
4511 dest_map->skb = src_map->skb;
4512 pci_unmap_addr_set(dest_map, mapping,
4513 pci_unmap_addr(src_map, mapping));
4514 dest_desc->addr_hi = src_desc->addr_hi;
4515 dest_desc->addr_lo = src_desc->addr_lo;
4516
4517 src_map->skb = NULL;
4518}
4519
1da177e4
LT		 4520/* The RX ring scheme is composed of multiple rings which post fresh
4521 * buffers to the chip, and one special ring the chip uses to report
4522 * status back to the host.
4523 *
4524 * The special ring reports the status of received packets to the
4525 * host. The chip does not write into the original descriptor the
4526 * RX buffer was obtained from. The chip simply takes the original
4527 * descriptor as provided by the host, updates the status and length
4528 * field, then writes this into the next status ring entry.
4529 *
4530 * Each ring the host uses to post buffers to the chip is described
4531 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4532 * it is first placed into the on-chip ram. When the packet's length
4533 * is known, it walks down the TG3_BDINFO entries to select the ring.
4534 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4535 * which is within the range of the new packet's length is chosen.
4536 *
4537 * The "separate ring for rx status" scheme may sound queer, but it makes
4538 * sense from a cache coherency perspective. If only the host writes
4539 * to the buffer post rings, and only the chip writes to the rx status
4540 * rings, then cache lines never move beyond shared-modified state.
4541 * If both the host and chip were to write into the same ring, cache line
4542 * eviction could occur since both entities want it in an exclusive state.
4543 */
17375d25 4544static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 4545{
17375d25 4546 struct tg3 *tp = tnapi->tp;
f92905de 4547 u32 work_mask, rx_std_posted = 0;
72334482 4548 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 4549 u16 hw_idx;
1da177e4 4550 int received;
21f581a5 4551 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4 4552
8d9d7cfc 4553 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 4554 /*
4555 * We need to order the read of hw_idx and the read of
4556 * the opaque cookie.
4557 */
4558 rmb();
1da177e4
LT		 4559 work_mask = 0;
4560 received = 0;
4561 while (sw_idx != hw_idx && budget > 0) {
72334482 4562 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 4563 unsigned int len;
4564 struct sk_buff *skb;
4565 dma_addr_t dma_addr;
4566 u32 opaque_key, desc_idx, *post_ptr;
4567
4568 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4569 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4570 if (opaque_key == RXD_OPAQUE_RING_STD) {
21f581a5
MC		 4571 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4572 dma_addr = pci_unmap_addr(ri, mapping);
4573 skb = ri->skb;
4574 post_ptr = &tpr->rx_std_ptr;
f92905de 4575 rx_std_posted++;
1da177e4 4576 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
21f581a5
MC		 4577 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4578 dma_addr = pci_unmap_addr(ri, mapping);
4579 skb = ri->skb;
4580 post_ptr = &tpr->rx_jmb_ptr;
4581 } else
1da177e4 4582 goto next_pkt_nopost;
1da177e4
LT		 4583
4584 work_mask |= opaque_key;
4585
4586 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4587 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4588 drop_it:
17375d25 4589 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4590 desc_idx, *post_ptr);
4591 drop_it_no_recycle:
4592 /* Other statistics kept track of by card. */
4593 tp->net_stats.rx_dropped++;
4594 goto next_pkt;
4595 }
4596
ad829268
MC		 4597 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4598 ETH_FCS_LEN;
1da177e4 4599
6aa20a22 4600 if (len > RX_COPY_THRESHOLD
ad829268
MC		 4601 && tp->rx_offset == NET_IP_ALIGN
4602 /* rx_offset will likely not equal NET_IP_ALIGN
4603 * if this is a 5701 card running in PCI-X mode
4604 * [see tg3_get_invariants()]
4605 */
1da177e4
LT		 4606 ) {
4607 int skb_size;
4608
17375d25 4609 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
1da177e4
LT		 4610 desc_idx, *post_ptr);
4611 if (skb_size < 0)
4612 goto drop_it;
4613
287be12e 4614 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 4615 PCI_DMA_FROMDEVICE);
4616
4617 skb_put(skb, len);
4618 } else {
4619 struct sk_buff *copy_skb;
4620
17375d25 4621 tg3_recycle_rx(tnapi, opaque_key,
1da177e4
LT		 4622 desc_idx, *post_ptr);
4623
ad829268
MC		 4624 copy_skb = netdev_alloc_skb(tp->dev,
4625 len + TG3_RAW_IP_ALIGN);
1da177e4
LT		 4626 if (copy_skb == NULL)
4627 goto drop_it_no_recycle;
4628
ad829268 4629 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
1da177e4
LT		 4630 skb_put(copy_skb, len);
4631 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 4632 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 4633 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4634
4635 /* We'll reuse the original ring buffer. */
4636 skb = copy_skb;
4637 }
4638
4639 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4640 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4641 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4642 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4643 skb->ip_summed = CHECKSUM_UNNECESSARY;
4644 else
4645 skb->ip_summed = CHECKSUM_NONE;
4646
4647 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 4648
4649 if (len > (tp->dev->mtu + ETH_HLEN) &&
4650 skb->protocol != htons(ETH_P_8021Q)) {
4651 dev_kfree_skb(skb);
4652 goto next_pkt;
4653 }
4654
1da177e4
LT		 4655#if TG3_VLAN_TAG_USED
4656 if (tp->vlgrp != NULL &&
4657 desc->type_flags & RXD_FLAG_VLAN) {
17375d25 4658 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
8ef0442f 4659 desc->err_vlan & RXD_VLAN_MASK, skb);
1da177e4
LT		 4660 } else
4661#endif
17375d25 4662 napi_gro_receive(&tnapi->napi, skb);
1da177e4 4663
1da177e4
LT		 4664 received++;
4665 budget--;
4666
4667next_pkt:
4668 (*post_ptr)++;
f92905de
MC		 4669
4670 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4671 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4672
4673 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4674 TG3_64BIT_REG_LOW, idx);
4675 work_mask &= ~RXD_OPAQUE_RING_STD;
4676 rx_std_posted = 0;
4677 }
1da177e4 4678next_pkt_nopost:
483ba50b 4679 sw_idx++;
6b31a515 4680 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
52f6d697
MC		 4681
4682 /* Refresh hw_idx to see if there is new work */
4683 if (sw_idx == hw_idx) {
8d9d7cfc 4684 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 4685 rmb();
4686 }
1da177e4
LT		 4687 }
4688
4689 /* ACK the status ring. */
72334482
MC		 4690 tnapi->rx_rcb_ptr = sw_idx;
4691 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 4692
4693 /* Refill RX ring(s). */
4694 if (work_mask & RXD_OPAQUE_RING_STD) {
21f581a5 4695 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
1da177e4
LT		 4696 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4697 sw_idx);
4698 }
4699 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
21f581a5 4700 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
1da177e4
LT		 4701 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4702 sw_idx);
4703 }
4704 mmiowb();
4705
4706 return received;
4707}
4708
17375d25 4709static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
1da177e4 4710{
17375d25 4711 struct tg3 *tp = tnapi->tp;
898a56f8 4712 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4 4713
1da177e4
LT		 4714 /* handle link change and other phy events */
4715 if (!(tp->tg3_flags &
4716 (TG3_FLAG_USE_LINKCHG_REG |
4717 TG3_FLAG_POLL_SERDES))) {
4718 if (sblk->status & SD_STATUS_LINK_CHG) {
4719 sblk->status = SD_STATUS_UPDATED |
4720 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 4721 spin_lock(&tp->lock);
dd477003
MC		 4722 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4723 tw32_f(MAC_STATUS,
4724 (MAC_STATUS_SYNC_CHANGED |
4725 MAC_STATUS_CFG_CHANGED |
4726 MAC_STATUS_MI_COMPLETION |
4727 MAC_STATUS_LNKSTATE_CHANGED));
4728 udelay(40);
4729 } else
4730 tg3_setup_phy(tp, 0);
f47c11ee 4731 spin_unlock(&tp->lock);
1da177e4
LT		 4732 }
4733 }
4734
4735 /* run TX completion thread */
f3f3f27e 4736 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 4737 tg3_tx(tnapi);
6f535763 4738 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4fd7ab59 4739 return work_done;
1da177e4
LT		 4740 }
4741
1da177e4
LT		 4742 /* run RX thread, within the bounds set by NAPI.
4743 * All RX "locking" is done by ensuring outside
bea3348e 4744 * code synchronizes with tg3->napi.poll()
1da177e4 4745 */
8d9d7cfc 4746 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 4747 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 4748
6f535763
DM		 4749 return work_done;
4750}
4751
4752static int tg3_poll(struct napi_struct *napi, int budget)
4753{
8ef0442f
MC		 4754 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4755 struct tg3 *tp = tnapi->tp;
6f535763 4756 int work_done = 0;
898a56f8 4757 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 4758
4759 while (1) {
17375d25 4760 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763
DM		 4761
4762 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4763 goto tx_recovery;
4764
4765 if (unlikely(work_done >= budget))
4766 break;
4767
4fd7ab59 4768 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
17375d25 4769 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 4770 * to tell the hw how much work has been processed,
4771 * so we must read it before checking for more work.
4772 */
898a56f8
MC		 4773 tnapi->last_tag = sblk->status_tag;
4774 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 4775 rmb();
4776 } else
4777 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 4778
17375d25 4779 if (likely(!tg3_has_work(tnapi))) {
288379f0 4780 napi_complete(napi);
17375d25 4781 tg3_int_reenable(tnapi);
6f535763
DM		 4782 break;
4783 }
1da177e4
LT		 4784 }
4785
bea3348e 4786 return work_done;
6f535763
DM		 4787
4788tx_recovery:
4fd7ab59 4789 /* work_done is guaranteed to be less than budget. */
288379f0 4790 napi_complete(napi);
6f535763 4791 schedule_work(&tp->reset_task);
4fd7ab59 4792 return work_done;
1da177e4
LT		 4793}
4794
f47c11ee
DM		 4795static void tg3_irq_quiesce(struct tg3 *tp)
4796{
4f125f42
MC		 4797 int i;
4798
f47c11ee
DM		 4799 BUG_ON(tp->irq_sync);
4800
4801 tp->irq_sync = 1;
4802 smp_mb();
4803
4f125f42
MC		 4804 for (i = 0; i < tp->irq_cnt; i++)
4805 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 4806}
4807
4808static inline int tg3_irq_sync(struct tg3 *tp)
4809{
4810 return tp->irq_sync;
4811}
4812
4813/* Fully shutdown all tg3 driver activity elsewhere in the system.
4814 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4815 * with as well. Most of the time, this is not necessary except when
4816 * shutting down the device.
4817 */
4818static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4819{
46966545 4820 spin_lock_bh(&tp->lock);
f47c11ee
DM		 4821 if (irq_sync)
4822 tg3_irq_quiesce(tp);
f47c11ee
DM		 4823}
4824
4825static inline void tg3_full_unlock(struct tg3 *tp)
4826{
f47c11ee
DM		 4827 spin_unlock_bh(&tp->lock);
4828}
4829
fcfa0a32
MC		 4830/* One-shot MSI handler - Chip automatically disables interrupt
4831 * after sending MSI so driver doesn't have to do it.
4832 */
7d12e780 4833static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 4834{
09943a18
MC		 4835 struct tg3_napi *tnapi = dev_id;
4836 struct tg3 *tp = tnapi->tp;
fcfa0a32 4837
898a56f8 4838 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4839 if (tnapi->rx_rcb)
4840 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 4841
4842 if (likely(!tg3_irq_sync(tp)))
09943a18 4843 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 4844
4845 return IRQ_HANDLED;
4846}
4847
88b06bc2
MC		 4848/* MSI ISR - No need to check for interrupt sharing and no need to
4849 * flush status block and interrupt mailbox. PCI ordering rules
4850 * guarantee that MSI will arrive after the status block.
4851 */
7d12e780 4852static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 4853{
09943a18
MC		 4854 struct tg3_napi *tnapi = dev_id;
4855 struct tg3 *tp = tnapi->tp;
88b06bc2 4856
898a56f8 4857 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 4858 if (tnapi->rx_rcb)
4859 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 4860 /*
fac9b83e 4861 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 4862 * chip-internal interrupt pending events.
fac9b83e 4863 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 4864 * NIC to stop sending us irqs, engaging "in-intr-handler"
4865 * event coalescing.
4866 */
4867 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
61487480 4868 if (likely(!tg3_irq_sync(tp)))
09943a18 4869 napi_schedule(&tnapi->napi);
61487480 4870
88b06bc2
MC		 4871 return IRQ_RETVAL(1);
4872}
4873
7d12e780 4874static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 4875{
09943a18
MC		 4876 struct tg3_napi *tnapi = dev_id;
4877 struct tg3 *tp = tnapi->tp;
898a56f8 4878 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 4879 unsigned int handled = 1;
4880
1da177e4
LT		 4881 /* In INTx mode, it is possible for the interrupt to arrive at
4882 * the CPU before the status block posted prior to the interrupt.
4883 * Reading the PCI State register will confirm whether the
4884 * interrupt is ours and will flush the status block.
4885 */
d18edcb2
MC		 4886 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4887 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4888 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4889 handled = 0;
f47c11ee 4890 goto out;
fac9b83e 4891 }
d18edcb2
MC		 4892 }
4893
4894 /*
4895 * Writing any value to intr-mbox-0 clears PCI INTA# and
4896 * chip-internal interrupt pending events.
4897 * Writing non-zero to intr-mbox-0 additional tells the
4898 * NIC to stop sending us irqs, engaging "in-intr-handler"
4899 * event coalescing.
c04cb347
MC		 4900 *
4901 * Flush the mailbox to de-assert the IRQ immediately to prevent
4902 * spurious interrupts. The flush impacts performance but
4903 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4904 */
c04cb347 4905 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 4906 if (tg3_irq_sync(tp))
4907 goto out;
4908 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 4909 if (likely(tg3_has_work(tnapi))) {
72334482 4910 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 4911 napi_schedule(&tnapi->napi);
d18edcb2
MC		 4912 } else {
4913 /* No work, shared interrupt perhaps? re-enable
4914 * interrupts, and flush that PCI write
4915 */
4916 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4917 0x00000000);
fac9b83e 4918 }
f47c11ee 4919out:
fac9b83e
DM		 4920 return IRQ_RETVAL(handled);
4921}
4922
7d12e780 4923static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 4924{
09943a18
MC		 4925 struct tg3_napi *tnapi = dev_id;
4926 struct tg3 *tp = tnapi->tp;
898a56f8 4927 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 4928 unsigned int handled = 1;
4929
fac9b83e
DM		 4930 /* In INTx mode, it is possible for the interrupt to arrive at
4931 * the CPU before the status block posted prior to the interrupt.
4932 * Reading the PCI State register will confirm whether the
4933 * interrupt is ours and will flush the status block.
4934 */
898a56f8 4935 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
d18edcb2
MC		 4936 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4937 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4938 handled = 0;
f47c11ee 4939 goto out;
1da177e4 4940 }
d18edcb2
MC		 4941 }
4942
4943 /*
4944 * writing any value to intr-mbox-0 clears PCI INTA# and
4945 * chip-internal interrupt pending events.
4946 * writing non-zero to intr-mbox-0 additional tells the
4947 * NIC to stop sending us irqs, engaging "in-intr-handler"
4948 * event coalescing.
c04cb347
MC		 4949 *
4950 * Flush the mailbox to de-assert the IRQ immediately to prevent
4951 * spurious interrupts. The flush impacts performance but
4952 * excessive spurious interrupts can be worse in some cases.
d18edcb2 4953 */
c04cb347 4954 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 4955
4956 /*
4957 * In a shared interrupt configuration, sometimes other devices'
4958 * interrupts will scream. We record the current status tag here
4959 * so that the above check can report that the screaming interrupts
4960 * are unhandled. Eventually they will be silenced.
4961 */
898a56f8 4962 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 4963
d18edcb2
MC		 4964 if (tg3_irq_sync(tp))
4965 goto out;
624f8e50 4966
72334482 4967 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 4968
09943a18 4969 napi_schedule(&tnapi->napi);
624f8e50 4970
f47c11ee 4971out:
1da177e4
LT		 4972 return IRQ_RETVAL(handled);
4973}
4974
7938109f 4975/* ISR for interrupt test */
7d12e780 4976static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 4977{
09943a18
MC		 4978 struct tg3_napi *tnapi = dev_id;
4979 struct tg3 *tp = tnapi->tp;
898a56f8 4980 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 4981
f9804ddb
MC		 4982 if ((sblk->status & SD_STATUS_UPDATED) ||
4983 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 4984 tg3_disable_ints(tp);
7938109f
MC		 4985 return IRQ_RETVAL(1);
4986 }
4987 return IRQ_RETVAL(0);
4988}
4989
8e7a22e3 4990static int tg3_init_hw(struct tg3 *, int);
944d980e 4991static int tg3_halt(struct tg3 *, int, int);
1da177e4 4992
b9ec6c1b
MC		 4993/* Restart hardware after configuration changes, self-test, etc.
4994 * Invoked with tp->lock held.
4995 */
4996static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
78c6146f
ED		 4997 __releases(tp->lock)
4998 __acquires(tp->lock)
b9ec6c1b
MC		 4999{
5000 int err;
5001
5002 err = tg3_init_hw(tp, reset_phy);
5003 if (err) {
5004 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5005 "aborting.\n", tp->dev->name);
5006 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5007 tg3_full_unlock(tp);
5008 del_timer_sync(&tp->timer);
5009 tp->irq_sync = 0;
fed97810 5010 tg3_napi_enable(tp);
b9ec6c1b
MC		 5011 dev_close(tp->dev);
5012 tg3_full_lock(tp, 0);
5013 }
5014 return err;
5015}
5016
1da177e4
LT		 5017#ifdef CONFIG_NET_POLL_CONTROLLER
5018static void tg3_poll_controller(struct net_device *dev)
5019{
4f125f42 5020 int i;
88b06bc2
MC		 5021 struct tg3 *tp = netdev_priv(dev);
5022
4f125f42
MC		 5023 for (i = 0; i < tp->irq_cnt; i++)
5024 tg3_interrupt(tp->napi[i].irq_vec, dev);
1da177e4
LT		 5025}
5026#endif
5027
c4028958 5028static void tg3_reset_task(struct work_struct *work)
1da177e4 5029{
c4028958 5030 struct tg3 *tp = container_of(work, struct tg3, reset_task);
b02fd9e3 5031 int err;
1da177e4
LT		 5032 unsigned int restart_timer;
5033
7faa006f 5034 tg3_full_lock(tp, 0);
7faa006f
MC		 5035
5036 if (!netif_running(tp->dev)) {
7faa006f
MC		 5037 tg3_full_unlock(tp);
5038 return;
5039 }
5040
5041 tg3_full_unlock(tp);
5042
b02fd9e3
MC		 5043 tg3_phy_stop(tp);
5044
1da177e4
LT		 5045 tg3_netif_stop(tp);
5046
f47c11ee 5047 tg3_full_lock(tp, 1);
1da177e4
LT		 5048
5049 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5050 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5051
df3e6548
MC		 5052 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5053 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5054 tp->write32_rx_mbox = tg3_write_flush_reg32;
5055 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5056 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5057 }
5058
944d980e 5059 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
b02fd9e3
MC		 5060 err = tg3_init_hw(tp, 1);
5061 if (err)
b9ec6c1b 5062 goto out;
1da177e4
LT		 5063
5064 tg3_netif_start(tp);
5065
1da177e4
LT		 5066 if (restart_timer)
5067 mod_timer(&tp->timer, jiffies + 1);
7faa006f 5068
b9ec6c1b 5069out:
7faa006f 5070 tg3_full_unlock(tp);
b02fd9e3
MC		 5071
5072 if (!err)
5073 tg3_phy_start(tp);
1da177e4
LT		 5074}
5075
b0408751
MC		 5076static void tg3_dump_short_state(struct tg3 *tp)
5077{
5078 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5079 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5080 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5081 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5082}
5083
1da177e4
LT		 5084static void tg3_tx_timeout(struct net_device *dev)
5085{
5086 struct tg3 *tp = netdev_priv(dev);
5087
b0408751 5088 if (netif_msg_tx_err(tp)) {
9f88f29f
MC		 5089 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5090 dev->name);
b0408751
MC		 5091 tg3_dump_short_state(tp);
5092 }
1da177e4
LT		 5093
5094 schedule_work(&tp->reset_task);
5095}
5096
c58ec932
MC		 5097/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5098static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5099{
5100 u32 base = (u32) mapping & 0xffffffff;
5101
5102 return ((base > 0xffffdcc0) &&
5103 (base + len + 8 < base));
5104}
5105
72f2afb8
MC		 5106/* Test for DMA addresses > 40-bit */
5107static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5108 int len)
5109{
5110#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6728a8e2 5111 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
50cf156a 5112 return (((u64) mapping + len) > DMA_BIT_MASK(40));
72f2afb8
MC		 5113 return 0;
5114#else
5115 return 0;
5116#endif
5117}
5118
f3f3f27e 5119static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
1da177e4 5120
72f2afb8
MC		 5121/* Workaround 4GB and 40-bit hardware DMA bugs. */
5122static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
c58ec932
MC		 5123 u32 last_plus_one, u32 *start,
5124 u32 base_flags, u32 mss)
1da177e4 5125{
f3f3f27e 5126 struct tg3_napi *tnapi = &tp->napi[0];
41588ba1 5127 struct sk_buff *new_skb;
c58ec932 5128 dma_addr_t new_addr = 0;
1da177e4 5129 u32 entry = *start;
c58ec932 5130 int i, ret = 0;
1da177e4 5131
41588ba1
MC		 5132 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5133 new_skb = skb_copy(skb, GFP_ATOMIC);
5134 else {
5135 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5136
5137 new_skb = skb_copy_expand(skb,
5138 skb_headroom(skb) + more_headroom,
5139 skb_tailroom(skb), GFP_ATOMIC);
5140 }
5141
1da177e4 5142 if (!new_skb) {
c58ec932
MC		 5143 ret = -1;
5144 } else {
5145 /* New SKB is guaranteed to be linear. */
5146 entry = *start;
90079ce8 5147 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
042a53a9 5148 new_addr = skb_shinfo(new_skb)->dma_head;
90079ce8 5149
c58ec932
MC		 5150 /* Make sure new skb does not cross any 4G boundaries.
5151 * Drop the packet if it does.
5152 */
0e1406dd
MC		 5153 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5154 tg3_4g_overflow_test(new_addr, new_skb->len))) {
638266f7
DM		 5155 if (!ret)
5156 skb_dma_unmap(&tp->pdev->dev, new_skb,
5157 DMA_TO_DEVICE);
c58ec932
MC		 5158 ret = -1;
5159 dev_kfree_skb(new_skb);
5160 new_skb = NULL;
5161 } else {
f3f3f27e 5162 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
c58ec932
MC		 5163 base_flags, 1 | (mss << 1));
5164 *start = NEXT_TX(entry);
5165 }
1da177e4
LT		 5166 }
5167
1da177e4
LT		 5168 /* Now clean up the sw ring entries. */
5169 i = 0;
5170 while (entry != last_plus_one) {
f3f3f27e
MC		 5171 if (i == 0)
5172 tnapi->tx_buffers[entry].skb = new_skb;
5173 else
5174 tnapi->tx_buffers[entry].skb = NULL;
1da177e4
LT		 5175 entry = NEXT_TX(entry);
5176 i++;
5177 }
5178
90079ce8 5179 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
1da177e4
LT		 5180 dev_kfree_skb(skb);
5181
c58ec932 5182 return ret;
1da177e4
LT		 5183}
5184
f3f3f27e 5185static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
1da177e4
LT		 5186 dma_addr_t mapping, int len, u32 flags,
5187 u32 mss_and_is_end)
5188{
f3f3f27e 5189 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
1da177e4
LT		 5190 int is_end = (mss_and_is_end & 0x1);
5191 u32 mss = (mss_and_is_end >> 1);
5192 u32 vlan_tag = 0;
5193
5194 if (is_end)
5195 flags |= TXD_FLAG_END;
5196 if (flags & TXD_FLAG_VLAN) {
5197 vlan_tag = flags >> 16;
5198 flags &= 0xffff;
5199 }
5200 vlan_tag |= (mss << TXD_MSS_SHIFT);
5201
5202 txd->addr_hi = ((u64) mapping >> 32);
5203 txd->addr_lo = ((u64) mapping & 0xffffffff);
5204 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5205 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5206}
5207
5a6f3074
MC		 5208/* hard_start_xmit for devices that don't have any bugs and
5209 * support TG3_FLG2_HW_TSO_2 only.
5210 */
61357325
SH		 5211static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5212 struct net_device *dev)
5a6f3074
MC		 5213{
5214 struct tg3 *tp = netdev_priv(dev);
5a6f3074 5215 u32 len, entry, base_flags, mss;
90079ce8
DM		 5216 struct skb_shared_info *sp;
5217 dma_addr_t mapping;
fe5f5787
MC		 5218 struct tg3_napi *tnapi;
5219 struct netdev_queue *txq;
5a6f3074 5220
fe5f5787
MC		 5221 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5222 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5223 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5224 tnapi++;
5a6f3074 5225
00b70504 5226 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5227 * and TX reclaim runs via tp->napi.poll inside of a software
5a6f3074
MC		 5228 * interrupt. Furthermore, IRQ processing runs lockless so we have
5229 * no IRQ context deadlocks to worry about either. Rejoice!
5230 */
f3f3f27e 5231 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
fe5f5787
MC		 5232 if (!netif_tx_queue_stopped(txq)) {
5233 netif_tx_stop_queue(txq);
5a6f3074
MC		 5234
5235 /* This is a hard error, log it. */
5236 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5237 "queue awake!\n", dev->name);
5238 }
5a6f3074
MC		 5239 return NETDEV_TX_BUSY;
5240 }
5241
f3f3f27e 5242 entry = tnapi->tx_prod;
5a6f3074 5243 base_flags = 0;
5a6f3074 5244 mss = 0;
c13e3713 5245 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5a6f3074 5246 int tcp_opt_len, ip_tcp_len;
f6eb9b1f 5247 u32 hdrlen;
5a6f3074
MC		 5248
5249 if (skb_header_cloned(skb) &&
5250 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5251 dev_kfree_skb(skb);
5252 goto out_unlock;
5253 }
5254
b0026624 5255 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
f6eb9b1f 5256 hdrlen = skb_headlen(skb) - ETH_HLEN;
b0026624 5257 else {
eddc9ec5
ACM		 5258 struct iphdr *iph = ip_hdr(skb);
5259
ab6a5bb6 5260 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5261 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
b0026624 5262
eddc9ec5
ACM		 5263 iph->check = 0;
5264 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
f6eb9b1f 5265 hdrlen = ip_tcp_len + tcp_opt_len;
b0026624 5266 }
5a6f3074 5267
f6eb9b1f
MC		 5268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5269 mss |= (hdrlen & 0xc) << 12;
5270 if (hdrlen & 0x10)
5271 base_flags |= 0x00000010;
5272 base_flags |= (hdrlen & 0x3e0) << 5;
5273 } else
5274 mss |= hdrlen << 9;
5275
5a6f3074
MC		 5276 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5277 TXD_FLAG_CPU_POST_DMA);
5278
aa8223c7 5279 tcp_hdr(skb)->check = 0;
5a6f3074 5280
5a6f3074 5281 }
84fa7933 5282 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5a6f3074 5283 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5a6f3074
MC		 5284#if TG3_VLAN_TAG_USED
5285 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5286 base_flags |= (TXD_FLAG_VLAN |
5287 (vlan_tx_tag_get(skb) << 16));
5288#endif
5289
90079ce8
DM		 5290 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5291 dev_kfree_skb(skb);
5292 goto out_unlock;
5293 }
5294
5295 sp = skb_shinfo(skb);
5296
042a53a9 5297 mapping = sp->dma_head;
5a6f3074 5298
f3f3f27e 5299 tnapi->tx_buffers[entry].skb = skb;
5a6f3074 5300
fe5f5787
MC		 5301 len = skb_headlen(skb);
5302
f6eb9b1f
MC		 5303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5304 !mss && skb->len > ETH_DATA_LEN)
5305 base_flags |= TXD_FLAG_JMB_PKT;
5306
f3f3f27e 5307 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5a6f3074
MC		 5308 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5309
5310 entry = NEXT_TX(entry);
5311
5312 /* Now loop through additional data fragments, and queue them. */
5313 if (skb_shinfo(skb)->nr_frags > 0) {
5314 unsigned int i, last;
5315
5316 last = skb_shinfo(skb)->nr_frags - 1;
5317 for (i = 0; i <= last; i++) {
5318 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5319
5320 len = frag->size;
042a53a9 5321 mapping = sp->dma_maps[i];
f3f3f27e 5322 tnapi->tx_buffers[entry].skb = NULL;
5a6f3074 5323
f3f3f27e 5324 tg3_set_txd(tnapi, entry, mapping, len,
5a6f3074
MC		 5325 base_flags, (i == last) | (mss << 1));
5326
5327 entry = NEXT_TX(entry);
5328 }
5329 }
5330
5331 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5332 tw32_tx_mbox(tnapi->prodmbox, entry);
5a6f3074 5333
f3f3f27e
MC		 5334 tnapi->tx_prod = entry;
5335 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
fe5f5787 5336 netif_tx_stop_queue(txq);
f3f3f27e 5337 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
fe5f5787 5338 netif_tx_wake_queue(txq);
5a6f3074
MC		 5339 }
5340
5341out_unlock:
cdd0db05 5342 mmiowb();
5a6f3074
MC		 5343
5344 return NETDEV_TX_OK;
5345}
5346
61357325
SH		 5347static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5348 struct net_device *);
52c0fd83
MC		 5349
5350/* Use GSO to workaround a rare TSO bug that may be triggered when the
5351 * TSO header is greater than 80 bytes.
5352 */
5353static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5354{
5355 struct sk_buff *segs, *nskb;
f3f3f27e 5356 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 5357
5358 /* Estimate the number of fragments in the worst case */
f3f3f27e 5359 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 5360 netif_stop_queue(tp->dev);
f3f3f27e 5361 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 5362 return NETDEV_TX_BUSY;
5363
5364 netif_wake_queue(tp->dev);
52c0fd83
MC		 5365 }
5366
5367 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 5368 if (IS_ERR(segs))
52c0fd83
MC		 5369 goto tg3_tso_bug_end;
5370
5371 do {
5372 nskb = segs;
5373 segs = segs->next;
5374 nskb->next = NULL;
5375 tg3_start_xmit_dma_bug(nskb, tp->dev);
5376 } while (segs);
5377
5378tg3_tso_bug_end:
5379 dev_kfree_skb(skb);
5380
5381 return NETDEV_TX_OK;
5382}
52c0fd83 5383
5a6f3074
MC		 5384/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5385 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5386 */
61357325
SH		 5387static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5388 struct net_device *dev)
1da177e4
LT		 5389{
5390 struct tg3 *tp = netdev_priv(dev);
1da177e4 5391 u32 len, entry, base_flags, mss;
90079ce8 5392 struct skb_shared_info *sp;
1da177e4 5393 int would_hit_hwbug;
90079ce8 5394 dma_addr_t mapping;
f3f3f27e 5395 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4
LT		 5396
5397 len = skb_headlen(skb);
5398
00b70504 5399 /* We are running in BH disabled context with netif_tx_lock
bea3348e 5400 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 5401 * interrupt. Furthermore, IRQ processing runs lockless so we have
5402 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 5403 */
f3f3f27e 5404 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
1f064a87
SH		 5405 if (!netif_queue_stopped(dev)) {
5406 netif_stop_queue(dev);
5407
5408 /* This is a hard error, log it. */
5409 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5410 "queue awake!\n", dev->name);
5411 }
1da177e4
LT		 5412 return NETDEV_TX_BUSY;
5413 }
5414
f3f3f27e 5415 entry = tnapi->tx_prod;
1da177e4 5416 base_flags = 0;
84fa7933 5417 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 5418 base_flags |= TXD_FLAG_TCPUDP_CSUM;
1da177e4 5419 mss = 0;
c13e3713 5420 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
eddc9ec5 5421 struct iphdr *iph;
92c6b8d1 5422 u32 tcp_opt_len, ip_tcp_len, hdr_len;
1da177e4
LT		 5423
5424 if (skb_header_cloned(skb) &&
5425 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5426 dev_kfree_skb(skb);
5427 goto out_unlock;
5428 }
5429
ab6a5bb6 5430 tcp_opt_len = tcp_optlen(skb);
c9bdd4b5 5431 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
1da177e4 5432
52c0fd83
MC		 5433 hdr_len = ip_tcp_len + tcp_opt_len;
5434 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7f62ad5d 5435 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
52c0fd83
MC		 5436 return (tg3_tso_bug(tp, skb));
5437
1da177e4
LT		 5438 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5439 TXD_FLAG_CPU_POST_DMA);
5440
eddc9ec5
ACM		 5441 iph = ip_hdr(skb);
5442 iph->check = 0;
5443 iph->tot_len = htons(mss + hdr_len);
1da177e4 5444 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
aa8223c7 5445 tcp_hdr(skb)->check = 0;
1da177e4 5446 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 5447 } else
5448 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5449 iph->daddr, 0,
5450 IPPROTO_TCP,
5451 0);
1da177e4 5452
92c6b8d1
MC		 5453 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5454 mss |= hdr_len << 9;
5455 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
eddc9ec5 5457 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5458 int tsflags;
5459
eddc9ec5 5460 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5461 mss |= (tsflags << 11);
5462 }
5463 } else {
eddc9ec5 5464 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 5465 int tsflags;
5466
eddc9ec5 5467 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 5468 base_flags |= tsflags << 12;
5469 }
5470 }
5471 }
1da177e4
LT		 5472#if TG3_VLAN_TAG_USED
5473 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5474 base_flags |= (TXD_FLAG_VLAN |
5475 (vlan_tx_tag_get(skb) << 16));
5476#endif
5477
90079ce8
DM		 5478 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5479 dev_kfree_skb(skb);
5480 goto out_unlock;
5481 }
5482
5483 sp = skb_shinfo(skb);
5484
042a53a9 5485 mapping = sp->dma_head;
1da177e4 5486
f3f3f27e 5487 tnapi->tx_buffers[entry].skb = skb;
1da177e4
LT		 5488
5489 would_hit_hwbug = 0;
5490
92c6b8d1
MC		 5491 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5492 would_hit_hwbug = 1;
5493
0e1406dd
MC		 5494 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5495 tg3_4g_overflow_test(mapping, len))
5496 would_hit_hwbug = 1;
5497
5498 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5499 tg3_40bit_overflow_test(tp, mapping, len))
41588ba1 5500 would_hit_hwbug = 1;
0e1406dd
MC		 5501
5502 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
c58ec932 5503 would_hit_hwbug = 1;
1da177e4 5504
f3f3f27e 5505 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
1da177e4
LT		 5506 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5507
5508 entry = NEXT_TX(entry);
5509
5510 /* Now loop through additional data fragments, and queue them. */
5511 if (skb_shinfo(skb)->nr_frags > 0) {
5512 unsigned int i, last;
5513
5514 last = skb_shinfo(skb)->nr_frags - 1;
5515 for (i = 0; i <= last; i++) {
5516 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5517
5518 len = frag->size;
042a53a9 5519 mapping = sp->dma_maps[i];
1da177e4 5520
f3f3f27e 5521 tnapi->tx_buffers[entry].skb = NULL;
1da177e4 5522
92c6b8d1
MC		 5523 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5524 len <= 8)
5525 would_hit_hwbug = 1;
5526
0e1406dd
MC		 5527 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5528 tg3_4g_overflow_test(mapping, len))
c58ec932 5529 would_hit_hwbug = 1;
1da177e4 5530
0e1406dd
MC		 5531 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5532 tg3_40bit_overflow_test(tp, mapping, len))
72f2afb8
MC		 5533 would_hit_hwbug = 1;
5534
1da177e4 5535 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
f3f3f27e 5536 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5537 base_flags, (i == last)|(mss << 1));
5538 else
f3f3f27e 5539 tg3_set_txd(tnapi, entry, mapping, len,
1da177e4
LT		 5540 base_flags, (i == last));
5541
5542 entry = NEXT_TX(entry);
5543 }
5544 }
5545
5546 if (would_hit_hwbug) {
5547 u32 last_plus_one = entry;
5548 u32 start;
1da177e4 5549
c58ec932
MC		 5550 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5551 start &= (TG3_TX_RING_SIZE - 1);
1da177e4
LT		 5552
5553 /* If the workaround fails due to memory/mapping
5554 * failure, silently drop this packet.
5555 */
72f2afb8 5556 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
c58ec932 5557 &start, base_flags, mss))
1da177e4
LT		 5558 goto out_unlock;
5559
5560 entry = start;
5561 }
5562
5563 /* Packets are ready, update Tx producer idx local and on card. */
f3f3f27e 5564 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
1da177e4 5565
f3f3f27e
MC		 5566 tnapi->tx_prod = entry;
5567 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
1da177e4 5568 netif_stop_queue(dev);
f3f3f27e 5569 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
51b91468
MC		 5570 netif_wake_queue(tp->dev);
5571 }
1da177e4
LT		 5572
5573out_unlock:
cdd0db05 5574 mmiowb();
1da177e4
LT		 5575
5576 return NETDEV_TX_OK;
5577}
5578
5579static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5580 int new_mtu)
5581{
5582 dev->mtu = new_mtu;
5583
ef7f5ec0 5584 if (new_mtu > ETH_DATA_LEN) {
a4e2b347 5585 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ef7f5ec0
MC		 5586 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5587 ethtool_op_set_tso(dev, 0);
5588 }
5589 else
5590 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5591 } else {
a4e2b347 5592 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
ef7f5ec0 5593 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 5594 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 5595 }
1da177e4
LT		 5596}
5597
5598static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5599{
5600 struct tg3 *tp = netdev_priv(dev);
b9ec6c1b 5601 int err;
1da177e4
LT		 5602
5603 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5604 return -EINVAL;
5605
5606 if (!netif_running(dev)) {
5607 /* We'll just catch it later when the
5608 * device is up'd.
5609 */
5610 tg3_set_mtu(dev, tp, new_mtu);
5611 return 0;
5612 }
5613
b02fd9e3
MC		 5614 tg3_phy_stop(tp);
5615
1da177e4 5616 tg3_netif_stop(tp);
f47c11ee
DM		 5617
5618 tg3_full_lock(tp, 1);
1da177e4 5619
944d980e 5620 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 5621
5622 tg3_set_mtu(dev, tp, new_mtu);
5623
b9ec6c1b 5624 err = tg3_restart_hw(tp, 0);
1da177e4 5625
b9ec6c1b
MC		 5626 if (!err)
5627 tg3_netif_start(tp);
1da177e4 5628
f47c11ee 5629 tg3_full_unlock(tp);
1da177e4 5630
b02fd9e3
MC		 5631 if (!err)
5632 tg3_phy_start(tp);
5633
b9ec6c1b 5634 return err;
1da177e4
LT		 5635}
5636
21f581a5
MC		 5637static void tg3_rx_prodring_free(struct tg3 *tp,
5638 struct tg3_rx_prodring_set *tpr)
1da177e4 5639{
1da177e4 5640 int i;
f3f3f27e 5641 struct ring_info *rxp;
1da177e4
LT		 5642
5643 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
21f581a5 5644 rxp = &tpr->rx_std_buffers[i];
1da177e4
LT		 5645
5646 if (rxp->skb == NULL)
5647 continue;
1da177e4 5648
1da177e4
LT		 5649 pci_unmap_single(tp->pdev,
5650 pci_unmap_addr(rxp, mapping),
cf7a7298 5651 tp->rx_pkt_map_sz,
1da177e4
LT		 5652 PCI_DMA_FROMDEVICE);
5653 dev_kfree_skb_any(rxp->skb);
5654 rxp->skb = NULL;
5655 }
5656
cf7a7298
MC		 5657 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5658 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
21f581a5 5659 rxp = &tpr->rx_jmb_buffers[i];
1da177e4 5660
cf7a7298
MC		 5661 if (rxp->skb == NULL)
5662 continue;
1da177e4 5663
cf7a7298
MC		 5664 pci_unmap_single(tp->pdev,
5665 pci_unmap_addr(rxp, mapping),
5666 TG3_RX_JMB_MAP_SZ,
5667 PCI_DMA_FROMDEVICE);
5668 dev_kfree_skb_any(rxp->skb);
5669 rxp->skb = NULL;
1da177e4 5670 }
1da177e4
LT		 5671 }
5672}
5673
5674/* Initialize tx/rx rings for packet processing.
5675 *
5676 * The chip has been shut down and the driver detached from
5677 * the networking, so no interrupts or new tx packets will
5678 * end up in the driver. tp->{tx,}lock are held and thus
5679 * we may not sleep.
5680 */
21f581a5
MC		 5681static int tg3_rx_prodring_alloc(struct tg3 *tp,
5682 struct tg3_rx_prodring_set *tpr)
1da177e4 5683{
287be12e 5684 u32 i, rx_pkt_dma_sz;
17375d25 5685 struct tg3_napi *tnapi = &tp->napi[0];
1da177e4 5686
1da177e4 5687 /* Zero out all descriptors. */
21f581a5 5688 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
1da177e4 5689
287be12e 5690 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
a4e2b347 5691 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
287be12e
MC		 5692 tp->dev->mtu > ETH_DATA_LEN)
5693 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5694 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 5695
1da177e4
LT		 5696 /* Initialize invariants of the rings, we only set this
5697 * stuff once. This works because the card does not
5698 * write into the rx buffer posting rings.
5699 */
5700 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5701 struct tg3_rx_buffer_desc *rxd;
5702
21f581a5 5703 rxd = &tpr->rx_std[i];
287be12e 5704 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 5705 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5706 rxd->opaque = (RXD_OPAQUE_RING_STD |
5707 (i << RXD_OPAQUE_INDEX_SHIFT));
5708 }
5709
1da177e4
LT		 5710 /* Now allocate fresh SKBs for each rx ring. */
5711 for (i = 0; i < tp->rx_pending; i++) {
17375d25 5712 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
32d8c572
MC		 5713 printk(KERN_WARNING PFX
5714 "%s: Using a smaller RX standard ring, "
5715 "only %d out of %d buffers were allocated "
5716 "successfully.\n",
5717 tp->dev->name, i, tp->rx_pending);
5718 if (i == 0)
cf7a7298 5719 goto initfail;
32d8c572 5720 tp->rx_pending = i;
1da177e4 5721 break;
32d8c572 5722 }
1da177e4
LT		 5723 }
5724
cf7a7298
MC		 5725 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5726 goto done;
5727
21f581a5 5728 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
cf7a7298 5729
0f893dc6 5730 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
cf7a7298
MC		 5731 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5732 struct tg3_rx_buffer_desc *rxd;
5733
79ed5ac7 5734 rxd = &tpr->rx_jmb[i].std;
cf7a7298
MC		 5735 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5736 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5737 RXD_FLAG_JUMBO;
5738 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5739 (i << RXD_OPAQUE_INDEX_SHIFT));
5740 }
5741
1da177e4 5742 for (i = 0; i < tp->rx_jumbo_pending; i++) {
17375d25 5743 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
32d8c572
MC		 5744 -1, i) < 0) {
5745 printk(KERN_WARNING PFX
5746 "%s: Using a smaller RX jumbo ring, "
5747 "only %d out of %d buffers were "
5748 "allocated successfully.\n",
5749 tp->dev->name, i, tp->rx_jumbo_pending);
cf7a7298
MC		 5750 if (i == 0)
5751 goto initfail;
32d8c572 5752 tp->rx_jumbo_pending = i;
1da177e4 5753 break;
32d8c572 5754 }
1da177e4
LT		 5755 }
5756 }
cf7a7298
MC		 5757
5758done:
32d8c572 5759 return 0;
cf7a7298
MC		 5760
5761initfail:
21f581a5 5762 tg3_rx_prodring_free(tp, tpr);
cf7a7298 5763 return -ENOMEM;
1da177e4
LT		 5764}
5765
21f581a5
MC		 5766static void tg3_rx_prodring_fini(struct tg3 *tp,
5767 struct tg3_rx_prodring_set *tpr)
1da177e4 5768{
21f581a5
MC		 5769 kfree(tpr->rx_std_buffers);
5770 tpr->rx_std_buffers = NULL;
5771 kfree(tpr->rx_jmb_buffers);
5772 tpr->rx_jmb_buffers = NULL;
5773 if (tpr->rx_std) {
1da177e4 5774 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
21f581a5
MC		 5775 tpr->rx_std, tpr->rx_std_mapping);
5776 tpr->rx_std = NULL;
1da177e4 5777 }
21f581a5 5778 if (tpr->rx_jmb) {
1da177e4 5779 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
21f581a5
MC		 5780 tpr->rx_jmb, tpr->rx_jmb_mapping);
5781 tpr->rx_jmb = NULL;
1da177e4 5782 }
cf7a7298
MC		 5783}
5784
21f581a5
MC		 5785static int tg3_rx_prodring_init(struct tg3 *tp,
5786 struct tg3_rx_prodring_set *tpr)
cf7a7298 5787{
21f581a5
MC		 5788 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5789 TG3_RX_RING_SIZE, GFP_KERNEL);
5790 if (!tpr->rx_std_buffers)
cf7a7298
MC		 5791 return -ENOMEM;
5792
21f581a5
MC		 5793 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5794 &tpr->rx_std_mapping);
5795 if (!tpr->rx_std)
cf7a7298
MC		 5796 goto err_out;
5797
5798 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
21f581a5
MC		 5799 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5800 TG3_RX_JUMBO_RING_SIZE,
5801 GFP_KERNEL);
5802 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 5803 goto err_out;
5804
21f581a5
MC		 5805 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5806 TG3_RX_JUMBO_RING_BYTES,
5807 &tpr->rx_jmb_mapping);
5808 if (!tpr->rx_jmb)
cf7a7298
MC		 5809 goto err_out;
5810 }
5811
5812 return 0;
5813
5814err_out:
21f581a5 5815 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 5816 return -ENOMEM;
5817}
5818
5819/* Free up pending packets in all rx/tx rings.
5820 *
5821 * The chip has been shut down and the driver detached from
5822 * the networking, so no interrupts or new tx packets will
5823 * end up in the driver. tp->{tx,}lock is not held and we are not
5824 * in an interrupt context and thus may sleep.
5825 */
5826static void tg3_free_rings(struct tg3 *tp)
5827{
f77a6a8e 5828 int i, j;
cf7a7298 5829
f77a6a8e
MC		 5830 for (j = 0; j < tp->irq_cnt; j++) {
5831 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 5832
0c1d0e2b
MC		 5833 if (!tnapi->tx_buffers)
5834 continue;
5835
f77a6a8e
MC		 5836 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5837 struct tx_ring_info *txp;
5838 struct sk_buff *skb;
cf7a7298 5839
f77a6a8e
MC		 5840 txp = &tnapi->tx_buffers[i];
5841 skb = txp->skb;
cf7a7298 5842
f77a6a8e
MC		 5843 if (skb == NULL) {
5844 i++;
5845 continue;
5846 }
cf7a7298 5847
f77a6a8e 5848 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
cf7a7298 5849
f77a6a8e 5850 txp->skb = NULL;
cf7a7298 5851
f77a6a8e
MC		 5852 i += skb_shinfo(skb)->nr_frags + 1;
5853
5854 dev_kfree_skb_any(skb);
5855 }
cf7a7298
MC		 5856 }
5857
21f581a5 5858 tg3_rx_prodring_free(tp, &tp->prodring[0]);
cf7a7298
MC		 5859}
5860
5861/* Initialize tx/rx rings for packet processing.
5862 *
5863 * The chip has been shut down and the driver detached from
5864 * the networking, so no interrupts or new tx packets will
5865 * end up in the driver. tp->{tx,}lock are held and thus
5866 * we may not sleep.
5867 */
5868static int tg3_init_rings(struct tg3 *tp)
5869{
f77a6a8e 5870 int i;
72334482 5871
cf7a7298
MC		 5872 /* Free up all the SKBs. */
5873 tg3_free_rings(tp);
5874
f77a6a8e
MC		 5875 for (i = 0; i < tp->irq_cnt; i++) {
5876 struct tg3_napi *tnapi = &tp->napi[i];
5877
5878 tnapi->last_tag = 0;
5879 tnapi->last_irq_tag = 0;
5880 tnapi->hw_status->status = 0;
5881 tnapi->hw_status->status_tag = 0;
5882 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 5883
f77a6a8e
MC		 5884 tnapi->tx_prod = 0;
5885 tnapi->tx_cons = 0;
0c1d0e2b
MC		 5886 if (tnapi->tx_ring)
5887 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 5888
5889 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 5890 if (tnapi->rx_rcb)
5891 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
f77a6a8e 5892 }
72334482 5893
21f581a5 5894 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
cf7a7298
MC		 5895}
5896
5897/*
5898 * Must not be invoked with interrupt sources disabled and
5899 * the hardware shutdown down.
5900 */
5901static void tg3_free_consistent(struct tg3 *tp)
5902{
f77a6a8e 5903 int i;
898a56f8 5904
f77a6a8e
MC		 5905 for (i = 0; i < tp->irq_cnt; i++) {
5906 struct tg3_napi *tnapi = &tp->napi[i];
5907
5908 if (tnapi->tx_ring) {
5909 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5910 tnapi->tx_ring, tnapi->tx_desc_mapping);
5911 tnapi->tx_ring = NULL;
5912 }
5913
5914 kfree(tnapi->tx_buffers);
5915 tnapi->tx_buffers = NULL;
5916
5917 if (tnapi->rx_rcb) {
5918 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5919 tnapi->rx_rcb,
5920 tnapi->rx_rcb_mapping);
5921 tnapi->rx_rcb = NULL;
5922 }
5923
5924 if (tnapi->hw_status) {
5925 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5926 tnapi->hw_status,
5927 tnapi->status_mapping);
5928 tnapi->hw_status = NULL;
5929 }
1da177e4 5930 }
f77a6a8e 5931
1da177e4
LT		 5932 if (tp->hw_stats) {
5933 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5934 tp->hw_stats, tp->stats_mapping);
5935 tp->hw_stats = NULL;
5936 }
f77a6a8e 5937
21f581a5 5938 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
1da177e4
LT		 5939}
5940
5941/*
5942 * Must not be invoked with interrupt sources disabled and
5943 * the hardware shutdown down. Can sleep.
5944 */
5945static int tg3_alloc_consistent(struct tg3 *tp)
5946{
f77a6a8e 5947 int i;
898a56f8 5948
21f581a5 5949 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
1da177e4
LT		 5950 return -ENOMEM;
5951
f77a6a8e
MC		 5952 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5953 sizeof(struct tg3_hw_stats),
5954 &tp->stats_mapping);
5955 if (!tp->hw_stats)
1da177e4
LT		 5956 goto err_out;
5957
f77a6a8e 5958 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
1da177e4 5959
f77a6a8e
MC		 5960 for (i = 0; i < tp->irq_cnt; i++) {
5961 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 5962 struct tg3_hw_status *sblk;
1da177e4 5963
f77a6a8e
MC		 5964 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5965 TG3_HW_STATUS_SIZE,
5966 &tnapi->status_mapping);
5967 if (!tnapi->hw_status)
5968 goto err_out;
898a56f8 5969
f77a6a8e 5970 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8d9d7cfc
MC		 5971 sblk = tnapi->hw_status;
5972
5973 /*
5974 * When RSS is enabled, the status block format changes
5975 * slightly. The "rx_jumbo_consumer", "reserved",
5976 * and "rx_mini_consumer" members get mapped to the
5977 * other three rx return ring producer indexes.
5978 */
5979 switch (i) {
5980 default:
5981 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5982 break;
5983 case 2:
5984 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5985 break;
5986 case 3:
5987 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5988 break;
5989 case 4:
5990 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5991 break;
5992 }
72334482 5993
0c1d0e2b
MC		 5994 /*
5995 * If multivector RSS is enabled, vector 0 does not handle
5996 * rx or tx interrupts. Don't allocate any resources for it.
5997 */
5998 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5999 continue;
6000
f77a6a8e
MC		 6001 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6002 TG3_RX_RCB_RING_BYTES(tp),
6003 &tnapi->rx_rcb_mapping);
6004 if (!tnapi->rx_rcb)
6005 goto err_out;
72334482 6006
f77a6a8e 6007 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
1da177e4 6008
f77a6a8e
MC		 6009 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6010 TG3_TX_RING_SIZE, GFP_KERNEL);
6011 if (!tnapi->tx_buffers)
6012 goto err_out;
6013
6014 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6015 TG3_TX_RING_BYTES,
6016 &tnapi->tx_desc_mapping);
6017 if (!tnapi->tx_ring)
6018 goto err_out;
6019 }
1da177e4
LT		 6020
6021 return 0;
6022
6023err_out:
6024 tg3_free_consistent(tp);
6025 return -ENOMEM;
6026}
6027
6028#define MAX_WAIT_CNT 1000
6029
6030/* To stop a block, clear the enable bit and poll till it
6031 * clears. tp->lock is held.
6032 */
b3b7d6be 6033static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 6034{
6035 unsigned int i;
6036 u32 val;
6037
6038 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6039 switch (ofs) {
6040 case RCVLSC_MODE:
6041 case DMAC_MODE:
6042 case MBFREE_MODE:
6043 case BUFMGR_MODE:
6044 case MEMARB_MODE:
6045 /* We can't enable/disable these bits of the
6046 * 5705/5750, just say success.
6047 */
6048 return 0;
6049
6050 default:
6051 break;
855e1111 6052 }
1da177e4
LT		 6053 }
6054
6055 val = tr32(ofs);
6056 val &= ~enable_bit;
6057 tw32_f(ofs, val);
6058
6059 for (i = 0; i < MAX_WAIT_CNT; i++) {
6060 udelay(100);
6061 val = tr32(ofs);
6062 if ((val & enable_bit) == 0)
6063 break;
6064 }
6065
b3b7d6be 6066 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 6067 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6068 "ofs=%lx enable_bit=%x\n",
6069 ofs, enable_bit);
6070 return -ENODEV;
6071 }
6072
6073 return 0;
6074}
6075
6076/* tp->lock is held. */
b3b7d6be 6077static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 6078{
6079 int i, err;
6080
6081 tg3_disable_ints(tp);
6082
6083 tp->rx_mode &= ~RX_MODE_ENABLE;
6084 tw32_f(MAC_RX_MODE, tp->rx_mode);
6085 udelay(10);
6086
b3b7d6be
DM		 6087 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6088 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6089 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6090 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6091 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6092 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6093
6094 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6095 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6096 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6097 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6098 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6099 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6100 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 6101
6102 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6103 tw32_f(MAC_MODE, tp->mac_mode);
6104 udelay(40);
6105
6106 tp->tx_mode &= ~TX_MODE_ENABLE;
6107 tw32_f(MAC_TX_MODE, tp->tx_mode);
6108
6109 for (i = 0; i < MAX_WAIT_CNT; i++) {
6110 udelay(100);
6111 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6112 break;
6113 }
6114 if (i >= MAX_WAIT_CNT) {
6115 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6116 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6117 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 6118 err |= -ENODEV;
1da177e4
LT		 6119 }
6120
e6de8ad1 6121 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 6122 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6123 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 6124
6125 tw32(FTQ_RESET, 0xffffffff);
6126 tw32(FTQ_RESET, 0x00000000);
6127
b3b7d6be
DM		 6128 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6129 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 6130
f77a6a8e
MC		 6131 for (i = 0; i < tp->irq_cnt; i++) {
6132 struct tg3_napi *tnapi = &tp->napi[i];
6133 if (tnapi->hw_status)
6134 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6135 }
1da177e4
LT		 6136 if (tp->hw_stats)
6137 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6138
1da177e4
LT		 6139 return err;
6140}
6141
0d3031d9
MC		 6142static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6143{
6144 int i;
6145 u32 apedata;
6146
6147 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6148 if (apedata != APE_SEG_SIG_MAGIC)
6149 return;
6150
6151 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
731fd79c 6152 if (!(apedata & APE_FW_STATUS_READY))
0d3031d9
MC		 6153 return;
6154
6155 /* Wait for up to 1 millisecond for APE to service previous event. */
6156 for (i = 0; i < 10; i++) {
6157 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6158 return;
6159
6160 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6161
6162 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6163 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6164 event | APE_EVENT_STATUS_EVENT_PENDING);
6165
6166 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6167
6168 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6169 break;
6170
6171 udelay(100);
6172 }
6173
6174 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6175 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6176}
6177
6178static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6179{
6180 u32 event;
6181 u32 apedata;
6182
6183 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6184 return;
6185
6186 switch (kind) {
6187 case RESET_KIND_INIT:
6188 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6189 APE_HOST_SEG_SIG_MAGIC);
6190 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6191 APE_HOST_SEG_LEN_MAGIC);
6192 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6193 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6194 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6195 APE_HOST_DRIVER_ID_MAGIC);
6196 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6197 APE_HOST_BEHAV_NO_PHYLOCK);
6198
6199 event = APE_EVENT_STATUS_STATE_START;
6200 break;
6201 case RESET_KIND_SHUTDOWN:
b2aee154
MC		 6202 /* With the interface we are currently using,
6203 * APE does not track driver state. Wiping
6204 * out the HOST SEGMENT SIGNATURE forces
6205 * the APE to assume OS absent status.
6206 */
6207 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6208
0d3031d9
MC		 6209 event = APE_EVENT_STATUS_STATE_UNLOAD;
6210 break;
6211 case RESET_KIND_SUSPEND:
6212 event = APE_EVENT_STATUS_STATE_SUSPEND;
6213 break;
6214 default:
6215 return;
6216 }
6217
6218 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6219
6220 tg3_ape_send_event(tp, event);
6221}
6222
1da177e4
LT		 6223/* tp->lock is held. */
6224static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6225{
f49639e6
DM		 6226 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6227 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1da177e4
LT		 6228
6229 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6230 switch (kind) {
6231 case RESET_KIND_INIT:
6232 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6233 DRV_STATE_START);
6234 break;
6235
6236 case RESET_KIND_SHUTDOWN:
6237 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6238 DRV_STATE_UNLOAD);
6239 break;
6240
6241 case RESET_KIND_SUSPEND:
6242 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6243 DRV_STATE_SUSPEND);
6244 break;
6245
6246 default:
6247 break;
855e1111 6248 }
1da177e4 6249 }
0d3031d9
MC		 6250
6251 if (kind == RESET_KIND_INIT ||
6252 kind == RESET_KIND_SUSPEND)
6253 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6254}
6255
6256/* tp->lock is held. */
6257static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6258{
6259 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6260 switch (kind) {
6261 case RESET_KIND_INIT:
6262 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6263 DRV_STATE_START_DONE);
6264 break;
6265
6266 case RESET_KIND_SHUTDOWN:
6267 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6268 DRV_STATE_UNLOAD_DONE);
6269 break;
6270
6271 default:
6272 break;
855e1111 6273 }
1da177e4 6274 }
0d3031d9
MC		 6275
6276 if (kind == RESET_KIND_SHUTDOWN)
6277 tg3_ape_driver_state_change(tp, kind);
1da177e4
LT		 6278}
6279
6280/* tp->lock is held. */
6281static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6282{
6283 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6284 switch (kind) {
6285 case RESET_KIND_INIT:
6286 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6287 DRV_STATE_START);
6288 break;
6289
6290 case RESET_KIND_SHUTDOWN:
6291 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6292 DRV_STATE_UNLOAD);
6293 break;
6294
6295 case RESET_KIND_SUSPEND:
6296 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6297 DRV_STATE_SUSPEND);
6298 break;
6299
6300 default:
6301 break;
855e1111 6302 }
1da177e4
LT		 6303 }
6304}
6305
7a6f4369
MC		 6306static int tg3_poll_fw(struct tg3 *tp)
6307{
6308 int i;
6309 u32 val;
6310
b5d3772c 6311 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
0ccead18
GZ		 6312 /* Wait up to 20ms for init done. */
6313 for (i = 0; i < 200; i++) {
b5d3772c
MC		 6314 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6315 return 0;
0ccead18 6316 udelay(100);
b5d3772c
MC		 6317 }
6318 return -ENODEV;
6319 }
6320
7a6f4369
MC		 6321 /* Wait for firmware initialization to complete. */
6322 for (i = 0; i < 100000; i++) {
6323 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6324 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6325 break;
6326 udelay(10);
6327 }
6328
6329 /* Chip might not be fitted with firmware. Some Sun onboard
6330 * parts are configured like that. So don't signal the timeout
6331 * of the above loop as an error, but do report the lack of
6332 * running firmware once.
6333 */
6334 if (i >= 100000 &&
6335 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6336 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6337
6338 printk(KERN_INFO PFX "%s: No firmware running.\n",
6339 tp->dev->name);
6340 }
6341
6342 return 0;
6343}
6344
ee6a99b5
MC		 6345/* Save PCI command register before chip reset */
6346static void tg3_save_pci_state(struct tg3 *tp)
6347{
8a6eac90 6348 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 6349}
6350
6351/* Restore PCI state after chip reset */
6352static void tg3_restore_pci_state(struct tg3 *tp)
6353{
6354 u32 val;
6355
6356 /* Re-enable indirect register accesses. */
6357 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6358 tp->misc_host_ctrl);
6359
6360 /* Set MAX PCI retry to zero. */
6361 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6362 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6363 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6364 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9
MC		 6365 /* Allow reads and writes to the APE register and memory space. */
6366 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6367 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6368 PCISTATE_ALLOW_APE_SHMEM_WR;
ee6a99b5
MC		 6369 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6370
8a6eac90 6371 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 6372
fcb389df
MC		 6373 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6374 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6375 pcie_set_readrq(tp->pdev, 4096);
6376 else {
6377 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6378 tp->pci_cacheline_sz);
6379 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6380 tp->pci_lat_timer);
6381 }
114342f2 6382 }
5f5c51e3 6383
ee6a99b5 6384 /* Make sure PCI-X relaxed ordering bit is clear. */
52f4490c 6385 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
9974a356
MC		 6386 u16 pcix_cmd;
6387
6388 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6389 &pcix_cmd);
6390 pcix_cmd &= ~PCI_X_CMD_ERO;
6391 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6392 pcix_cmd);
6393 }
ee6a99b5
MC		 6394
6395 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
ee6a99b5
MC		 6396
6397 /* Chip reset on 5780 will reset MSI enable bit,
6398 * so need to restore it.
6399 */
6400 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6401 u16 ctrl;
6402
6403 pci_read_config_word(tp->pdev,
6404 tp->msi_cap + PCI_MSI_FLAGS,
6405 &ctrl);
6406 pci_write_config_word(tp->pdev,
6407 tp->msi_cap + PCI_MSI_FLAGS,
6408 ctrl | PCI_MSI_FLAGS_ENABLE);
6409 val = tr32(MSGINT_MODE);
6410 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6411 }
6412 }
6413}
6414
1da177e4
LT		 6415static void tg3_stop_fw(struct tg3 *);
6416
6417/* tp->lock is held. */
6418static int tg3_chip_reset(struct tg3 *tp)
6419{
6420 u32 val;
1ee582d8 6421 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 6422 int i, err;
1da177e4 6423
f49639e6
DM		 6424 tg3_nvram_lock(tp);
6425
77b483f1
MC		 6426 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6427
f49639e6
DM		 6428 /* No matching tg3_nvram_unlock() after this because
6429 * chip reset below will undo the nvram lock.
6430 */
6431 tp->nvram_lock_cnt = 0;
1da177e4 6432
ee6a99b5
MC		 6433 /* GRC_MISC_CFG core clock reset will clear the memory
6434 * enable bit in PCI register 4 and the MSI enable bit
6435 * on some chips, so we save relevant registers here.
6436 */
6437 tg3_save_pci_state(tp);
6438
d9ab5ad1 6439 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
321d32a0 6440 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
d9ab5ad1
MC		 6441 tw32(GRC_FASTBOOT_PC, 0);
6442
1da177e4
LT		 6443 /*
6444 * We must avoid the readl() that normally takes place.
6445 * It locks machines, causes machine checks, and other
6446 * fun things. So, temporarily disable the 5701
6447 * hardware workaround, while we do the reset.
6448 */
1ee582d8
MC		 6449 write_op = tp->write32;
6450 if (write_op == tg3_write_flush_reg32)
6451 tp->write32 = tg3_write32;
1da177e4 6452
d18edcb2
MC		 6453 /* Prevent the irq handler from reading or writing PCI registers
6454 * during chip reset when the memory enable bit in the PCI command
6455 * register may be cleared. The chip does not generate interrupt
6456 * at this time, but the irq handler may still be called due to irq
6457 * sharing or irqpoll.
6458 */
6459 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
f77a6a8e
MC		 6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6462 if (tnapi->hw_status) {
6463 tnapi->hw_status->status = 0;
6464 tnapi->hw_status->status_tag = 0;
6465 }
6466 tnapi->last_tag = 0;
6467 tnapi->last_irq_tag = 0;
b8fa2f3a 6468 }
d18edcb2 6469 smp_mb();
4f125f42
MC		 6470
6471 for (i = 0; i < tp->irq_cnt; i++)
6472 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 6473
255ca311
MC		 6474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6475 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6476 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6477 }
6478
1da177e4
LT		 6479 /* do the reset */
6480 val = GRC_MISC_CFG_CORECLK_RESET;
6481
6482 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6483 if (tr32(0x7e2c) == 0x60) {
6484 tw32(0x7e2c, 0x20);
6485 }
6486 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6487 tw32(GRC_MISC_CFG, (1 << 29));
6488 val |= (1 << 29);
6489 }
6490 }
6491
b5d3772c
MC		 6492 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6493 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6494 tw32(GRC_VCPU_EXT_CTRL,
6495 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6496 }
6497
1da177e4
LT		 6498 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6499 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6500 tw32(GRC_MISC_CFG, val);
6501
1ee582d8
MC		 6502 /* restore 5701 hardware bug workaround write method */
6503 tp->write32 = write_op;
1da177e4
LT		 6504
6505 /* Unfortunately, we have to delay before the PCI read back.
6506 * Some 575X chips even will not respond to a PCI cfg access
6507 * when the reset command is given to the chip.
6508 *
6509 * How do these hardware designers expect things to work
6510 * properly if the PCI write is posted for a long period
6511 * of time? It is always necessary to have some method by
6512 * which a register read back can occur to push the write
6513 * out which does the reset.
6514 *
6515 * For most tg3 variants the trick below was working.
6516 * Ho hum...
6517 */
6518 udelay(120);
6519
6520 /* Flush PCI posted writes. The normal MMIO registers
6521 * are inaccessible at this time so this is the only
6522 * way to make this reliably (actually, this is no longer
6523 * the case, see above). I tried to use indirect
6524 * register read/write but this upset some 5701 variants.
6525 */
6526 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6527
6528 udelay(120);
6529
5e7dfd0f 6530 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
e7126997
MC		 6531 u16 val16;
6532
1da177e4
LT		 6533 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6534 int i;
6535 u32 cfg_val;
6536
6537 /* Wait for link training to complete. */
6538 for (i = 0; i < 5000; i++)
6539 udelay(100);
6540
6541 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6542 pci_write_config_dword(tp->pdev, 0xc4,
6543 cfg_val | (1 << 15));
6544 }
5e7dfd0f 6545
e7126997
MC		 6546 /* Clear the "no snoop" and "relaxed ordering" bits. */
6547 pci_read_config_word(tp->pdev,
6548 tp->pcie_cap + PCI_EXP_DEVCTL,
6549 &val16);
6550 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6551 PCI_EXP_DEVCTL_NOSNOOP_EN);
6552 /*
6553 * Older PCIe devices only support the 128 byte
6554 * MPS setting. Enforce the restriction.
5e7dfd0f 6555 */
e7126997
MC		 6556 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6557 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6558 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
5e7dfd0f
MC		 6559 pci_write_config_word(tp->pdev,
6560 tp->pcie_cap + PCI_EXP_DEVCTL,
e7126997 6561 val16);
5e7dfd0f
MC		 6562
6563 pcie_set_readrq(tp->pdev, 4096);
6564
6565 /* Clear error status */
6566 pci_write_config_word(tp->pdev,
6567 tp->pcie_cap + PCI_EXP_DEVSTA,
6568 PCI_EXP_DEVSTA_CED |
6569 PCI_EXP_DEVSTA_NFED |
6570 PCI_EXP_DEVSTA_FED |
6571 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 6572 }
6573
ee6a99b5 6574 tg3_restore_pci_state(tp);
1da177e4 6575
d18edcb2
MC		 6576 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6577
ee6a99b5
MC		 6578 val = 0;
6579 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4cf78e4f 6580 val = tr32(MEMARB_MODE);
ee6a99b5 6581 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4
LT		 6582
6583 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6584 tg3_stop_fw(tp);
6585 tw32(0x5000, 0x400);
6586 }
6587
6588 tw32(GRC_MODE, tp->grc_mode);
6589
6590 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
ab0049b4 6591 val = tr32(0xc4);
1da177e4
LT		 6592
6593 tw32(0xc4, val | (1 << 15));
6594 }
6595
6596 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6597 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6598 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6599 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6600 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6601 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6602 }
6603
6604 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6605 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6606 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 6607 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6608 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6609 tw32_f(MAC_MODE, tp->mac_mode);
3bda1258
MC		 6610 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6611 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6612 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6613 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6614 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 6615 } else
6616 tw32_f(MAC_MODE, 0);
6617 udelay(40);
6618
77b483f1
MC		 6619 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6620
7a6f4369
MC		 6621 err = tg3_poll_fw(tp);
6622 if (err)
6623 return err;
1da177e4 6624
0a9140cf
MC		 6625 tg3_mdio_start(tp);
6626
52cdf852
MC		 6627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6628 u8 phy_addr;
6629
6630 phy_addr = tp->phy_addr;
6631 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6632
6633 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6634 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6635 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6636 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6637 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6638 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6639 udelay(10);
6640
6641 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6642 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6643 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6644 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6645 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6646 udelay(10);
6647
6648 tp->phy_addr = phy_addr;
6649 }
6650
1da177e4 6651 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
f6eb9b1f
MC		 6652 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6653 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6654 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
ab0049b4 6655 val = tr32(0x7c00);
1da177e4
LT		 6656
6657 tw32(0x7c00, val | (1 << 25));
6658 }
6659
6660 /* Reprobe ASF enable state. */
6661 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6662 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6663 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6664 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6665 u32 nic_cfg;
6666
6667 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6668 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6669 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4ba526ce 6670 tp->last_event_jiffies = jiffies;
cbf46853 6671 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 6672 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6673 }
6674 }
6675
6676 return 0;
6677}
6678
6679/* tp->lock is held. */
6680static void tg3_stop_fw(struct tg3 *tp)
6681{
0d3031d9
MC		 6682 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6683 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 6684 /* Wait for RX cpu to ACK the previous event. */
6685 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6686
6687 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4ba526ce
MC		 6688
6689 tg3_generate_fw_event(tp);
1da177e4 6690
7c5026aa
MC		 6691 /* Wait for RX cpu to ACK this event. */
6692 tg3_wait_for_event_ack(tp);
1da177e4
LT		 6693 }
6694}
6695
6696/* tp->lock is held. */
944d980e 6697static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 6698{
6699 int err;
6700
6701 tg3_stop_fw(tp);
6702
944d980e 6703 tg3_write_sig_pre_reset(tp, kind);
1da177e4 6704
b3b7d6be 6705 tg3_abort_hw(tp, silent);
1da177e4
LT		 6706 err = tg3_chip_reset(tp);
6707
daba2a63
MC		 6708 __tg3_set_mac_addr(tp, 0);
6709
944d980e
MC		 6710 tg3_write_sig_legacy(tp, kind);
6711 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 6712
6713 if (err)
6714 return err;
6715
6716 return 0;
6717}
6718
1da177e4
LT		 6719#define RX_CPU_SCRATCH_BASE 0x30000
6720#define RX_CPU_SCRATCH_SIZE 0x04000
6721#define TX_CPU_SCRATCH_BASE 0x34000
6722#define TX_CPU_SCRATCH_SIZE 0x04000
6723
6724/* tp->lock is held. */
6725static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6726{
6727 int i;
6728
5d9428de
ES		 6729 BUG_ON(offset == TX_CPU_BASE &&
6730 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
1da177e4 6731
b5d3772c
MC		 6732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6733 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6734
6735 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6736 return 0;
6737 }
1da177e4
LT		 6738 if (offset == RX_CPU_BASE) {
6739 for (i = 0; i < 10000; i++) {
6740 tw32(offset + CPU_STATE, 0xffffffff);
6741 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6742 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6743 break;
6744 }
6745
6746 tw32(offset + CPU_STATE, 0xffffffff);
6747 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6748 udelay(10);
6749 } else {
6750 for (i = 0; i < 10000; i++) {
6751 tw32(offset + CPU_STATE, 0xffffffff);
6752 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6753 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6754 break;
6755 }
6756 }
6757
6758 if (i >= 10000) {
6759 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6760 "and %s CPU\n",
6761 tp->dev->name,
6762 (offset == RX_CPU_BASE ? "RX" : "TX"));
6763 return -ENODEV;
6764 }
ec41c7df
MC		 6765
6766 /* Clear firmware's nvram arbitration. */
6767 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6768 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1da177e4
LT		 6769 return 0;
6770}
6771
6772struct fw_info {
077f849d
JSR		 6773 unsigned int fw_base;
6774 unsigned int fw_len;
6775 const __be32 *fw_data;
1da177e4
LT		 6776};
6777
6778/* tp->lock is held. */
6779static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6780 int cpu_scratch_size, struct fw_info *info)
6781{
ec41c7df 6782 int err, lock_err, i;
1da177e4
LT		 6783 void (*write_op)(struct tg3 *, u32, u32);
6784
6785 if (cpu_base == TX_CPU_BASE &&
6786 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6787 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6788 "TX cpu firmware on %s which is 5705.\n",
6789 tp->dev->name);
6790 return -EINVAL;
6791 }
6792
6793 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6794 write_op = tg3_write_mem;
6795 else
6796 write_op = tg3_write_indirect_reg32;
6797
1b628151
MC		 6798 /* It is possible that bootcode is still loading at this point.
6799 * Get the nvram lock first before halting the cpu.
6800 */
ec41c7df 6801 lock_err = tg3_nvram_lock(tp);
1da177e4 6802 err = tg3_halt_cpu(tp, cpu_base);
ec41c7df
MC		 6803 if (!lock_err)
6804 tg3_nvram_unlock(tp);
1da177e4
LT		 6805 if (err)
6806 goto out;
6807
6808 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6809 write_op(tp, cpu_scratch_base + i, 0);
6810 tw32(cpu_base + CPU_STATE, 0xffffffff);
6811 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
077f849d 6812 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
1da177e4 6813 write_op(tp, (cpu_scratch_base +
077f849d 6814 (info->fw_base & 0xffff) +
1da177e4 6815 (i * sizeof(u32))),
077f849d 6816 be32_to_cpu(info->fw_data[i]));
1da177e4
LT		 6817
6818 err = 0;
6819
6820out:
1da177e4
LT		 6821 return err;
6822}
6823
6824/* tp->lock is held. */
6825static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6826{
6827 struct fw_info info;
077f849d 6828 const __be32 *fw_data;
1da177e4
LT		 6829 int err, i;
6830
077f849d
JSR		 6831 fw_data = (void *)tp->fw->data;
6832
6833 /* Firmware blob starts with version numbers, followed by
6834 start address and length. We are setting complete length.
6835 length = end_address_of_bss - start_address_of_text.
6836 Remainder is the blob to be loaded contiguously
6837 from start address. */
6838
6839 info.fw_base = be32_to_cpu(fw_data[1]);
6840 info.fw_len = tp->fw->size - 12;
6841 info.fw_data = &fw_data[3];
1da177e4
LT		 6842
6843 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6844 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6845 &info);
6846 if (err)
6847 return err;
6848
6849 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6850 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6851 &info);
6852 if (err)
6853 return err;
6854
6855 /* Now startup only the RX cpu. */
6856 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
077f849d 6857 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6858
6859 for (i = 0; i < 5; i++) {
077f849d 6860 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
1da177e4
LT		 6861 break;
6862 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6863 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
077f849d 6864 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
1da177e4
LT		 6865 udelay(1000);
6866 }
6867 if (i >= 5) {
6868 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6869 "to set RX CPU PC, is %08x should be %08x\n",
6870 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
077f849d 6871 info.fw_base);
1da177e4
LT		 6872 return -ENODEV;
6873 }
6874 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6875 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6876
6877 return 0;
6878}
6879
1da177e4 6880/* 5705 needs a special version of the TSO firmware. */
1da177e4
LT		 6881
6882/* tp->lock is held. */
6883static int tg3_load_tso_firmware(struct tg3 *tp)
6884{
6885 struct fw_info info;
077f849d 6886 const __be32 *fw_data;
1da177e4
LT		 6887 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6888 int err, i;
6889
6890 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6891 return 0;
6892
077f849d
JSR		 6893 fw_data = (void *)tp->fw->data;
6894
6895 /* Firmware blob starts with version numbers, followed by
6896 start address and length. We are setting complete length.
6897 length = end_address_of_bss - start_address_of_text.
6898 Remainder is the blob to be loaded contiguously
6899 from start address. */
6900
6901 info.fw_base = be32_to_cpu(fw_data[1]);
6902 cpu_scratch_size = tp->fw_len;
6903 info.fw_len = tp->fw->size - 12;
6904 info.fw_data = &fw_data[3];
6905
1da177e4 6906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 6907 cpu_base = RX_CPU_BASE;
6908 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
1da177e4 6909 } else {
1da177e4
LT		 6910 cpu_base = TX_CPU_BASE;
6911 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6912 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6913 }
6914
6915 err = tg3_load_firmware_cpu(tp, cpu_base,
6916 cpu_scratch_base, cpu_scratch_size,
6917 &info);
6918 if (err)
6919 return err;
6920
6921 /* Now startup the cpu. */
6922 tw32(cpu_base + CPU_STATE, 0xffffffff);
077f849d 6923 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6924
6925 for (i = 0; i < 5; i++) {
077f849d 6926 if (tr32(cpu_base + CPU_PC) == info.fw_base)
1da177e4
LT		 6927 break;
6928 tw32(cpu_base + CPU_STATE, 0xffffffff);
6929 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
077f849d 6930 tw32_f(cpu_base + CPU_PC, info.fw_base);
1da177e4
LT		 6931 udelay(1000);
6932 }
6933 if (i >= 5) {
6934 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6935 "to set CPU PC, is %08x should be %08x\n",
6936 tp->dev->name, tr32(cpu_base + CPU_PC),
077f849d 6937 info.fw_base);
1da177e4
LT		 6938 return -ENODEV;
6939 }
6940 tw32(cpu_base + CPU_STATE, 0xffffffff);
6941 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6942 return 0;
6943}
6944
1da177e4 6945
1da177e4
LT		 6946static int tg3_set_mac_addr(struct net_device *dev, void *p)
6947{
6948 struct tg3 *tp = netdev_priv(dev);
6949 struct sockaddr *addr = p;
986e0aeb 6950 int err = 0, skip_mac_1 = 0;
1da177e4 6951
f9804ddb
MC		 6952 if (!is_valid_ether_addr(addr->sa_data))
6953 return -EINVAL;
6954
1da177e4
LT		 6955 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6956
e75f7c90
MC		 6957 if (!netif_running(dev))
6958 return 0;
6959
58712ef9 6960 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
986e0aeb 6961 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 6962
986e0aeb
MC		 6963 addr0_high = tr32(MAC_ADDR_0_HIGH);
6964 addr0_low = tr32(MAC_ADDR_0_LOW);
6965 addr1_high = tr32(MAC_ADDR_1_HIGH);
6966 addr1_low = tr32(MAC_ADDR_1_LOW);
6967
6968 /* Skip MAC addr 1 if ASF is using it. */
6969 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6970 !(addr1_high == 0 && addr1_low == 0))
6971 skip_mac_1 = 1;
58712ef9 6972 }
986e0aeb
MC		 6973 spin_lock_bh(&tp->lock);
6974 __tg3_set_mac_addr(tp, skip_mac_1);
6975 spin_unlock_bh(&tp->lock);
1da177e4 6976
b9ec6c1b 6977 return err;
1da177e4
LT		 6978}
6979
6980/* tp->lock is held. */
6981static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6982 dma_addr_t mapping, u32 maxlen_flags,
6983 u32 nic_addr)
6984{
6985 tg3_write_mem(tp,
6986 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6987 ((u64) mapping >> 32));
6988 tg3_write_mem(tp,
6989 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6990 ((u64) mapping & 0xffffffff));
6991 tg3_write_mem(tp,
6992 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6993 maxlen_flags);
6994
6995 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6996 tg3_write_mem(tp,
6997 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6998 nic_addr);
6999}
7000
7001static void __tg3_set_rx_mode(struct net_device *);
d244c892 7002static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 7003{
b6080e12
MC		 7004 int i;
7005
7006 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7007 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7008 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7009 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7010
7011 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7012 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7013 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7014 } else {
7015 tw32(HOSTCC_TXCOL_TICKS, 0);
7016 tw32(HOSTCC_TXMAX_FRAMES, 0);
7017 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7018
7019 tw32(HOSTCC_RXCOL_TICKS, 0);
7020 tw32(HOSTCC_RXMAX_FRAMES, 0);
7021 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 7022 }
b6080e12 7023
15f9850d
DM		 7024 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7025 u32 val = ec->stats_block_coalesce_usecs;
7026
b6080e12
MC		 7027 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7028 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7029
15f9850d
DM		 7030 if (!netif_carrier_ok(tp->dev))
7031 val = 0;
7032
7033 tw32(HOSTCC_STAT_COAL_TICKS, val);
7034 }
b6080e12
MC		 7035
7036 for (i = 0; i < tp->irq_cnt - 1; i++) {
7037 u32 reg;
7038
7039 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7040 tw32(reg, ec->rx_coalesce_usecs);
7041 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7042 tw32(reg, ec->tx_coalesce_usecs);
7043 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7044 tw32(reg, ec->rx_max_coalesced_frames);
7045 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7046 tw32(reg, ec->tx_max_coalesced_frames);
7047 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7048 tw32(reg, ec->rx_max_coalesced_frames_irq);
7049 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7050 tw32(reg, ec->tx_max_coalesced_frames_irq);
7051 }
7052
7053 for (; i < tp->irq_max - 1; i++) {
7054 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7055 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7056 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7057 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7058 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7059 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7060 }
15f9850d 7061}
1da177e4 7062
2d31ecaf
MC		 7063/* tp->lock is held. */
7064static void tg3_rings_reset(struct tg3 *tp)
7065{
7066 int i;
f77a6a8e 7067 u32 stblk, txrcb, rxrcb, limit;
2d31ecaf
MC		 7068 struct tg3_napi *tnapi = &tp->napi[0];
7069
7070 /* Disable all transmit rings but the first. */
7071 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7072 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7073 else
7074 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7075
7076 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7077 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7078 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7079 BDINFO_FLAGS_DISABLED);
7080
7081
7082 /* Disable all receive return rings but the first. */
f6eb9b1f
MC		 7083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7084 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7085 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
2d31ecaf
MC		 7086 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7087 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7088 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7089 else
7090 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7091
7092 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7093 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7094 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7095 BDINFO_FLAGS_DISABLED);
7096
7097 /* Disable interrupts */
7098 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7099
7100 /* Zero mailbox registers. */
f77a6a8e
MC		 7101 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7102 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7103 tp->napi[i].tx_prod = 0;
7104 tp->napi[i].tx_cons = 0;
7105 tw32_mailbox(tp->napi[i].prodmbox, 0);
7106 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7107 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7108 }
7109 } else {
7110 tp->napi[0].tx_prod = 0;
7111 tp->napi[0].tx_cons = 0;
7112 tw32_mailbox(tp->napi[0].prodmbox, 0);
7113 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7114 }
2d31ecaf
MC		 7115
7116 /* Make sure the NIC-based send BD rings are disabled. */
7117 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7118 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7119 for (i = 0; i < 16; i++)
7120 tw32_tx_mbox(mbox + i * 8, 0);
7121 }
7122
7123 txrcb = NIC_SRAM_SEND_RCB;
7124 rxrcb = NIC_SRAM_RCV_RET_RCB;
7125
7126 /* Clear status block in ram. */
7127 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7128
7129 /* Set status block DMA address */
7130 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7131 ((u64) tnapi->status_mapping >> 32));
7132 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7133 ((u64) tnapi->status_mapping & 0xffffffff));
7134
f77a6a8e
MC		 7135 if (tnapi->tx_ring) {
7136 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7137 (TG3_TX_RING_SIZE <<
7138 BDINFO_FLAGS_MAXLEN_SHIFT),
7139 NIC_SRAM_TX_BUFFER_DESC);
7140 txrcb += TG3_BDINFO_SIZE;
7141 }
7142
7143 if (tnapi->rx_rcb) {
7144 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7145 (TG3_RX_RCB_RING_SIZE(tp) <<
7146 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7147 rxrcb += TG3_BDINFO_SIZE;
7148 }
7149
7150 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 7151
f77a6a8e
MC		 7152 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7153 u64 mapping = (u64)tnapi->status_mapping;
7154 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7155 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7156
7157 /* Clear status block in ram. */
7158 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7159
7160 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7161 (TG3_TX_RING_SIZE <<
7162 BDINFO_FLAGS_MAXLEN_SHIFT),
7163 NIC_SRAM_TX_BUFFER_DESC);
7164
7165 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7166 (TG3_RX_RCB_RING_SIZE(tp) <<
7167 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7168
7169 stblk += 8;
7170 txrcb += TG3_BDINFO_SIZE;
7171 rxrcb += TG3_BDINFO_SIZE;
7172 }
2d31ecaf
MC		 7173}
7174
1da177e4 7175/* tp->lock is held. */
8e7a22e3 7176static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
1da177e4
LT		 7177{
7178 u32 val, rdmac_mode;
7179 int i, err, limit;
21f581a5 7180 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
1da177e4
LT		 7181
7182 tg3_disable_ints(tp);
7183
7184 tg3_stop_fw(tp);
7185
7186 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7187
7188 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 7189 tg3_abort_hw(tp, 1);
1da177e4
LT		 7190 }
7191
dd477003
MC		 7192 if (reset_phy &&
7193 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
d4d2c558
MC		 7194 tg3_phy_reset(tp);
7195
1da177e4
LT		 7196 err = tg3_chip_reset(tp);
7197 if (err)
7198 return err;
7199
7200 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7201
bcb37f6c 7202 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
d30cdd28
MC		 7203 val = tr32(TG3_CPMU_CTRL);
7204 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7205 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 7206
7207 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7208 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7209 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7210 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7211
7212 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7213 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7214 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7215 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7216
7217 val = tr32(TG3_CPMU_HST_ACC);
7218 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7219 val |= CPMU_HST_ACC_MACCLK_6_25;
7220 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 7221 }
7222
33466d93
MC		 7223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7224 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7225 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7226 PCIE_PWR_MGMT_L1_THRESH_4MS;
7227 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 7228
7229 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7230 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7231
7232 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 7233
f40386c8
MC		 7234 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7235 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 7236 }
7237
1da177e4
LT		 7238 /* This works around an issue with Athlon chipsets on
7239 * B3 tigon3 silicon. This bit has no effect on any
7240 * other revision. But do not set this on PCI Express
795d01c5 7241 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 7242 */
795d01c5
MC		 7243 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7244 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7245 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7246 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7247 }
1da177e4
LT		 7248
7249 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7250 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7251 val = tr32(TG3PCI_PCISTATE);
7252 val |= PCISTATE_RETRY_SAME_DMA;
7253 tw32(TG3PCI_PCISTATE, val);
7254 }
7255
0d3031d9
MC		 7256 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7257 /* Allow reads and writes to the
7258 * APE register and memory space.
7259 */
7260 val = tr32(TG3PCI_PCISTATE);
7261 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7262 PCISTATE_ALLOW_APE_SHMEM_WR;
7263 tw32(TG3PCI_PCISTATE, val);
7264 }
7265
1da177e4
LT		 7266 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7267 /* Enable some hw fixes. */
7268 val = tr32(TG3PCI_MSI_DATA);
7269 val |= (1 << 26) | (1 << 28) | (1 << 29);
7270 tw32(TG3PCI_MSI_DATA, val);
7271 }
7272
7273 /* Descriptor ring init may make accesses to the
7274 * NIC SRAM area to setup the TX descriptors, so we
7275 * can only do this after the hardware has been
7276 * successfully reset.
7277 */
32d8c572
MC		 7278 err = tg3_init_rings(tp);
7279 if (err)
7280 return err;
1da177e4 7281
9936bcf6 7282 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
f6eb9b1f
MC		 7283 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7284 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
d30cdd28
MC		 7285 /* This value is determined during the probe time DMA
7286 * engine test, tg3_test_dma.
7287 */
7288 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7289 }
1da177e4
LT		 7290
7291 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7292 GRC_MODE_4X_NIC_SEND_RINGS |
7293 GRC_MODE_NO_TX_PHDR_CSUM |
7294 GRC_MODE_NO_RX_PHDR_CSUM);
7295 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 7296
7297 /* Pseudo-header checksum is done by hardware logic and not
7298 * the offload processers, so make the chip do the pseudo-
7299 * header checksums on receive. For transmit it is more
7300 * convenient to do the pseudo-header checksum in software
7301 * as Linux does that on transmit for us in all cases.
7302 */
7303 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4
LT		 7304
7305 tw32(GRC_MODE,
7306 tp->grc_mode |
7307 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7308
7309 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7310 val = tr32(GRC_MISC_CFG);
7311 val &= ~0xff;
7312 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7313 tw32(GRC_MISC_CFG, val);
7314
7315 /* Initialize MBUF/DESC pool. */
cbf46853 7316 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 7317 /* Do nothing. */
7318 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7319 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7320 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7321 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7322 else
7323 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7324 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7325 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7326 }
1da177e4
LT		 7327 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7328 int fw_len;
7329
077f849d 7330 fw_len = tp->fw_len;
1da177e4
LT		 7331 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7332 tw32(BUFMGR_MB_POOL_ADDR,
7333 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7334 tw32(BUFMGR_MB_POOL_SIZE,
7335 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7336 }
1da177e4 7337
0f893dc6 7338 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 7339 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7340 tp->bufmgr_config.mbuf_read_dma_low_water);
7341 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7342 tp->bufmgr_config.mbuf_mac_rx_low_water);
7343 tw32(BUFMGR_MB_HIGH_WATER,
7344 tp->bufmgr_config.mbuf_high_water);
7345 } else {
7346 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7347 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7348 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7349 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7350 tw32(BUFMGR_MB_HIGH_WATER,
7351 tp->bufmgr_config.mbuf_high_water_jumbo);
7352 }
7353 tw32(BUFMGR_DMA_LOW_WATER,
7354 tp->bufmgr_config.dma_low_water);
7355 tw32(BUFMGR_DMA_HIGH_WATER,
7356 tp->bufmgr_config.dma_high_water);
7357
7358 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7359 for (i = 0; i < 2000; i++) {
7360 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7361 break;
7362 udelay(10);
7363 }
7364 if (i >= 2000) {
7365 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7366 tp->dev->name);
7367 return -ENODEV;
7368 }
7369
7370 /* Setup replenish threshold. */
f92905de
MC		 7371 val = tp->rx_pending / 8;
7372 if (val == 0)
7373 val = 1;
7374 else if (val > tp->rx_std_max_post)
7375 val = tp->rx_std_max_post;
b5d3772c
MC		 7376 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7377 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7378 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7379
7380 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7381 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7382 }
f92905de
MC		 7383
7384 tw32(RCVBDI_STD_THRESH, val);
1da177e4
LT		 7385
7386 /* Initialize TG3_BDINFO's at:
7387 * RCVDBDI_STD_BD: standard eth size rx ring
7388 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7389 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7390 *
7391 * like so:
7392 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7393 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7394 * ring attribute flags
7395 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7396 *
7397 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7398 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7399 *
7400 * The size of each ring is fixed in the firmware, but the location is
7401 * configurable.
7402 */
7403 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7404 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 7405 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7406 ((u64) tpr->rx_std_mapping & 0xffffffff));
87668d35
MC		 7407 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7408 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7409 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 7410
fdb72b38
MC		 7411 /* Disable the mini ring */
7412 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1da177e4
LT		 7413 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7414 BDINFO_FLAGS_DISABLED);
7415
fdb72b38
MC		 7416 /* Program the jumbo buffer descriptor ring control
7417 * blocks on those devices that have them.
7418 */
8f666b07 7419 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
fdb72b38 7420 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 7421 /* Setup replenish threshold. */
7422 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7423
0f893dc6 7424 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4 7425 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 7426 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 7427 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 7428 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
1da177e4 7429 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
79ed5ac7
MC		 7430 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7431 BDINFO_FLAGS_USE_EXT_RECV);
87668d35
MC		 7432 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7433 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7434 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 7435 } else {
7436 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7437 BDINFO_FLAGS_DISABLED);
7438 }
7439
f6eb9b1f
MC		 7440 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7441 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7442 (RX_STD_MAX_SIZE << 2);
7443 else
7444 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 7445 } else
7446 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7447
7448 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 7449
21f581a5 7450 tpr->rx_std_ptr = tp->rx_pending;
1da177e4 7451 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7452 tpr->rx_std_ptr);
1da177e4 7453
21f581a5
MC		 7454 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7455 tp->rx_jumbo_pending : 0;
1da177e4 7456 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
21f581a5 7457 tpr->rx_jmb_ptr);
1da177e4 7458
f6eb9b1f
MC		 7459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7460 tw32(STD_REPLENISH_LWM, 32);
7461 tw32(JMB_REPLENISH_LWM, 16);
7462 }
7463
2d31ecaf
MC		 7464 tg3_rings_reset(tp);
7465
1da177e4 7466 /* Initialize MAC address and backoff seed. */
986e0aeb 7467 __tg3_set_mac_addr(tp, 0);
1da177e4
LT		 7468
7469 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 7470 tw32(MAC_RX_MTU_SIZE,
7471 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 7472
7473 /* The slot time is changed by tg3_setup_phy if we
7474 * run at gigabit with half duplex.
7475 */
7476 tw32(MAC_TX_LENGTHS,
7477 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7478 (6 << TX_LENGTHS_IPG_SHIFT) |
7479 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7480
7481 /* Receive rules. */
7482 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7483 tw32(RCVLPC_CONFIG, 0x0181);
7484
7485 /* Calculate RDMAC_MODE setting early, we need it to determine
7486 * the RCVLPC_STATE_ENABLE mask.
7487 */
7488 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7489 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7490 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7491 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7492 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 7493
57e6983c 7494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0
MC		 7495 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
d30cdd28
MC		 7497 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7498 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7499 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7500
85e94ced
MC		 7501 /* If statement applies to 5705 and 5750 PCI devices only */
7502 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7503 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7504 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4 7505 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
c13e3713 7506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1da177e4
LT		 7507 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7508 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7509 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7510 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7511 }
7512 }
7513
85e94ced
MC		 7514 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7515 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7516
1da177e4 7517 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
027455ad
MC		 7518 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7519
7520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7522 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4
LT		 7523
7524 /* Receive/send statistics. */
1661394e
MC		 7525 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7526 val = tr32(RCVLPC_STATS_ENABLE);
7527 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7528 tw32(RCVLPC_STATS_ENABLE, val);
7529 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7530 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
1da177e4
LT		 7531 val = tr32(RCVLPC_STATS_ENABLE);
7532 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7533 tw32(RCVLPC_STATS_ENABLE, val);
7534 } else {
7535 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7536 }
7537 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7538 tw32(SNDDATAI_STATSENAB, 0xffffff);
7539 tw32(SNDDATAI_STATSCTRL,
7540 (SNDDATAI_SCTRL_ENABLE |
7541 SNDDATAI_SCTRL_FASTUPD));
7542
7543 /* Setup host coalescing engine. */
7544 tw32(HOSTCC_MODE, 0);
7545 for (i = 0; i < 2000; i++) {
7546 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7547 break;
7548 udelay(10);
7549 }
7550
d244c892 7551 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 7552
1da177e4
LT		 7553 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7554 /* Status/statistics block address. See tg3_timer,
7555 * the tg3_periodic_fetch_stats call there, and
7556 * tg3_get_stats to see how this works for 5705/5750 chips.
7557 */
1da177e4
LT		 7558 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7559 ((u64) tp->stats_mapping >> 32));
7560 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7561 ((u64) tp->stats_mapping & 0xffffffff));
7562 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 7563
1da177e4 7564 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 7565
7566 /* Clear statistics and status block memory areas */
7567 for (i = NIC_SRAM_STATS_BLK;
7568 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7569 i += sizeof(u32)) {
7570 tg3_write_mem(tp, i, 0);
7571 udelay(40);
7572 }
1da177e4
LT		 7573 }
7574
7575 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7576
7577 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7578 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7579 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7580 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7581
c94e3941
MC		 7582 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7583 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7584 /* reset to prevent losing 1st rx packet intermittently */
7585 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7586 udelay(10);
7587 }
7588
3bda1258
MC		 7589 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7590 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7591 else
7592 tp->mac_mode = 0;
7593 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
1da177e4 7594 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
e8f3f6ca
MC		 7595 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7596 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7597 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7598 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 7599 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7600 udelay(40);
7601
314fba34 7602 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9d26e213 7603 * If TG3_FLG2_IS_NIC is zero, we should read the
314fba34
MC		 7604 * register to preserve the GPIO settings for LOMs. The GPIOs,
7605 * whether used as inputs or outputs, are set by boot code after
7606 * reset.
7607 */
9d26e213 7608 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
314fba34
MC		 7609 u32 gpio_mask;
7610
9d26e213
MC		 7611 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7612 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7613 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 7614
7615 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7616 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7617 GRC_LCLCTRL_GPIO_OUTPUT3;
7618
af36e6b6
MC		 7619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7620 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7621
aaf84465 7622 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 7623 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7624
7625 /* GPIO1 must be driven high for eeprom write protect */
9d26e213
MC		 7626 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7627 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7628 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 7629 }
1da177e4
LT		 7630 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7631 udelay(100);
7632
baf8a94a
MC		 7633 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7634 val = tr32(MSGINT_MODE);
7635 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7636 tw32(MSGINT_MODE, val);
7637 }
7638
1da177e4
LT		 7639 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7640 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7641 udelay(40);
7642 }
7643
7644 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7645 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7646 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7647 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7648 WDMAC_MODE_LNGREAD_ENAB);
7649
85e94ced
MC		 7650 /* If statement applies to 5705 and 5750 PCI devices only */
7651 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7652 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7653 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
29ea095f 7654 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
1da177e4
LT		 7655 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7656 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7657 /* nothing */
7658 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7659 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7660 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7661 val |= WDMAC_MODE_RX_ACCEL;
7662 }
7663 }
7664
d9ab5ad1 7665 /* Enable host coalescing bug fix */
321d32a0 7666 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
f51f3562 7667 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 7668
788a035e
MC		 7669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7670 val |= WDMAC_MODE_BURST_ALL_DATA;
7671
1da177e4
LT		 7672 tw32_f(WDMAC_MODE, val);
7673 udelay(40);
7674
9974a356
MC		 7675 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7676 u16 pcix_cmd;
7677
7678 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7679 &pcix_cmd);
1da177e4 7680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9974a356
MC		 7681 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7682 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7683 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9974a356
MC		 7684 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7685 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 7686 }
9974a356
MC		 7687 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7688 pcix_cmd);
1da177e4
LT		 7689 }
7690
7691 tw32_f(RDMAC_MODE, rdmac_mode);
7692 udelay(40);
7693
7694 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7695 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7696 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6
MC		 7697
7698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7699 tw32(SNDDATAC_MODE,
7700 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7701 else
7702 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7703
1da177e4
LT		 7704 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7705 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7706 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7707 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1da177e4
LT		 7708 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7709 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a
MC		 7710 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7711 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7712 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7713 tw32(SNDBDI_MODE, val);
1da177e4
LT		 7714 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7715
7716 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7717 err = tg3_load_5701_a0_firmware_fix(tp);
7718 if (err)
7719 return err;
7720 }
7721
1da177e4
LT		 7722 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7723 err = tg3_load_tso_firmware(tp);
7724 if (err)
7725 return err;
7726 }
1da177e4
LT		 7727
7728 tp->tx_mode = TX_MODE_ENABLE;
7729 tw32_f(MAC_TX_MODE, tp->tx_mode);
7730 udelay(100);
7731
baf8a94a
MC		 7732 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7733 u32 reg = MAC_RSS_INDIR_TBL_0;
7734 u8 *ent = (u8 *)&val;
7735
7736 /* Setup the indirection table */
7737 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7738 int idx = i % sizeof(val);
7739
7740 ent[idx] = i % (tp->irq_cnt - 1);
7741 if (idx == sizeof(val) - 1) {
7742 tw32(reg, val);
7743 reg += 4;
7744 }
7745 }
7746
7747 /* Setup the "secret" hash key. */
7748 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7749 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7750 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7751 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7752 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7753 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7754 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7755 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7756 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7757 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7758 }
7759
1da177e4 7760 tp->rx_mode = RX_MODE_ENABLE;
321d32a0 7761 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
af36e6b6
MC		 7762 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7763
baf8a94a
MC		 7764 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7765 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7766 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7767 RX_MODE_RSS_IPV6_HASH_EN |
7768 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7769 RX_MODE_RSS_IPV4_HASH_EN |
7770 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7771
1da177e4
LT		 7772 tw32_f(MAC_RX_MODE, tp->rx_mode);
7773 udelay(10);
7774
1da177e4
LT		 7775 tw32(MAC_LED_CTRL, tp->led_ctrl);
7776
7777 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
c94e3941 7778 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1da177e4
LT		 7779 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7780 udelay(10);
7781 }
7782 tw32_f(MAC_RX_MODE, tp->rx_mode);
7783 udelay(10);
7784
7785 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7786 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7787 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7788 /* Set drive transmission level to 1.2V */
7789 /* only if the signal pre-emphasis bit is not set */
7790 val = tr32(MAC_SERDES_CFG);
7791 val &= 0xfffff000;
7792 val |= 0x880;
7793 tw32(MAC_SERDES_CFG, val);
7794 }
7795 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7796 tw32(MAC_SERDES_CFG, 0x616000);
7797 }
7798
7799 /* Prevent chip from dropping frames when flow control
7800 * is enabled.
7801 */
7802 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7803
7804 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7805 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7806 /* Use hardware link auto-negotiation */
7807 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7808 }
7809
d4d2c558
MC		 7810 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7811 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7812 u32 tmp;
7813
7814 tmp = tr32(SERDES_RX_CTRL);
7815 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7816 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7817 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7818 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7819 }
7820
dd477003
MC		 7821 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7822 if (tp->link_config.phy_is_low_power) {
7823 tp->link_config.phy_is_low_power = 0;
7824 tp->link_config.speed = tp->link_config.orig_speed;
7825 tp->link_config.duplex = tp->link_config.orig_duplex;
7826 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7827 }
1da177e4 7828
dd477003
MC		 7829 err = tg3_setup_phy(tp, 0);
7830 if (err)
7831 return err;
1da177e4 7832
dd477003 7833 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7f97a4bd 7834 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
dd477003
MC		 7835 u32 tmp;
7836
7837 /* Clear CRC stats. */
7838 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7839 tg3_writephy(tp, MII_TG3_TEST1,
7840 tmp | MII_TG3_TEST1_CRC_EN);
7841 tg3_readphy(tp, 0x14, &tmp);
7842 }
1da177e4
LT		 7843 }
7844 }
7845
7846 __tg3_set_rx_mode(tp->dev);
7847
7848 /* Initialize receive rules. */
7849 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7850 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7851 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7852 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7853
4cf78e4f 7854 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
a4e2b347 7855 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
1da177e4
LT		 7856 limit = 8;
7857 else
7858 limit = 16;
7859 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7860 limit -= 4;
7861 switch (limit) {
7862 case 16:
7863 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7864 case 15:
7865 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7866 case 14:
7867 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7868 case 13:
7869 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7870 case 12:
7871 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7872 case 11:
7873 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7874 case 10:
7875 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7876 case 9:
7877 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7878 case 8:
7879 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7880 case 7:
7881 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7882 case 6:
7883 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7884 case 5:
7885 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7886 case 4:
7887 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7888 case 3:
7889 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7890 case 2:
7891 case 1:
7892
7893 default:
7894 break;
855e1111 7895 }
1da177e4 7896
9ce768ea
MC		 7897 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7898 /* Write our heartbeat update interval to APE. */
7899 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7900 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 7901
1da177e4
LT		 7902 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7903
1da177e4
LT		 7904 return 0;
7905}
7906
7907/* Called at device open time to get the chip ready for
7908 * packet processing. Invoked with tp->lock held.
7909 */
8e7a22e3 7910static int tg3_init_hw(struct tg3 *tp, int reset_phy)
1da177e4 7911{
1da177e4
LT		 7912 tg3_switch_clocks(tp);
7913
7914 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7915
2f751b67 7916 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 7917}
7918
7919#define TG3_STAT_ADD32(PSTAT, REG) \
7920do { u32 __val = tr32(REG); \
7921 (PSTAT)->low += __val; \
7922 if ((PSTAT)->low < __val) \
7923 (PSTAT)->high += 1; \
7924} while (0)
7925
7926static void tg3_periodic_fetch_stats(struct tg3 *tp)
7927{
7928 struct tg3_hw_stats *sp = tp->hw_stats;
7929
7930 if (!netif_carrier_ok(tp->dev))
7931 return;
7932
7933 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7934 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7935 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7936 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7937 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7938 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7939 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7940 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7941 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7942 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7943 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7944 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7945 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7946
7947 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7948 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7949 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7950 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7951 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7952 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7953 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7954 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7955 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7956 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7957 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7958 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7959 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7960 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 7961
7962 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7963 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7964 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 7965}
7966
7967static void tg3_timer(unsigned long __opaque)
7968{
7969 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 7970
f475f163
MC		 7971 if (tp->irq_sync)
7972 goto restart_timer;
7973
f47c11ee 7974 spin_lock(&tp->lock);
1da177e4 7975
fac9b83e
DM		 7976 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7977 /* All of this garbage is because when using non-tagged
7978 * IRQ status the mailbox/status_block protocol the chip
7979 * uses with the cpu is race prone.
7980 */
898a56f8 7981 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 7982 tw32(GRC_LOCAL_CTRL,
7983 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7984 } else {
7985 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 7986 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 7987 }
1da177e4 7988
fac9b83e
DM		 7989 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7990 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 7991 spin_unlock(&tp->lock);
fac9b83e
DM		 7992 schedule_work(&tp->reset_task);
7993 return;
7994 }
1da177e4
LT		 7995 }
7996
1da177e4
LT		 7997 /* This part only runs once per second. */
7998 if (!--tp->timer_counter) {
fac9b83e
DM		 7999 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8000 tg3_periodic_fetch_stats(tp);
8001
1da177e4
LT		 8002 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8003 u32 mac_stat;
8004 int phy_event;
8005
8006 mac_stat = tr32(MAC_STATUS);
8007
8008 phy_event = 0;
8009 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8010 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8011 phy_event = 1;
8012 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8013 phy_event = 1;
8014
8015 if (phy_event)
8016 tg3_setup_phy(tp, 0);
8017 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8018 u32 mac_stat = tr32(MAC_STATUS);
8019 int need_setup = 0;
8020
8021 if (netif_carrier_ok(tp->dev) &&
8022 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8023 need_setup = 1;
8024 }
8025 if (! netif_carrier_ok(tp->dev) &&
8026 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8027 MAC_STATUS_SIGNAL_DET))) {
8028 need_setup = 1;
8029 }
8030 if (need_setup) {
3d3ebe74
MC		 8031 if (!tp->serdes_counter) {
8032 tw32_f(MAC_MODE,
8033 (tp->mac_mode &
8034 ~MAC_MODE_PORT_MODE_MASK));
8035 udelay(40);
8036 tw32_f(MAC_MODE, tp->mac_mode);
8037 udelay(40);
8038 }
1da177e4
LT		 8039 tg3_setup_phy(tp, 0);
8040 }
747e8f8b
MC		 8041 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8042 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 8043
8044 tp->timer_counter = tp->timer_multiplier;
8045 }
8046
130b8e4d
MC		 8047 /* Heartbeat is only sent once every 2 seconds.
8048 *
8049 * The heartbeat is to tell the ASF firmware that the host
8050 * driver is still alive. In the event that the OS crashes,
8051 * ASF needs to reset the hardware to free up the FIFO space
8052 * that may be filled with rx packets destined for the host.
8053 * If the FIFO is full, ASF will no longer function properly.
8054 *
8055 * Unintended resets have been reported on real time kernels
8056 * where the timer doesn't run on time. Netpoll will also have
8057 * same problem.
8058 *
8059 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8060 * to check the ring condition when the heartbeat is expiring
8061 * before doing the reset. This will prevent most unintended
8062 * resets.
8063 */
1da177e4 8064 if (!--tp->asf_counter) {
bc7959b2
MC		 8065 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8066 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7c5026aa
MC		 8067 tg3_wait_for_event_ack(tp);
8068
bbadf503 8069 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 8070 FWCMD_NICDRV_ALIVE3);
bbadf503 8071 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
28fbef78 8072 /* 5 seconds timeout */
bbadf503 8073 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
4ba526ce
MC		 8074
8075 tg3_generate_fw_event(tp);
1da177e4
LT		 8076 }
8077 tp->asf_counter = tp->asf_multiplier;
8078 }
8079
f47c11ee 8080 spin_unlock(&tp->lock);
1da177e4 8081
f475f163 8082restart_timer:
1da177e4
LT		 8083 tp->timer.expires = jiffies + tp->timer_offset;
8084 add_timer(&tp->timer);
8085}
8086
4f125f42 8087static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 8088{
7d12e780 8089 irq_handler_t fn;
fcfa0a32 8090 unsigned long flags;
4f125f42
MC		 8091 char *name;
8092 struct tg3_napi *tnapi = &tp->napi[irq_num];
8093
8094 if (tp->irq_cnt == 1)
8095 name = tp->dev->name;
8096 else {
8097 name = &tnapi->irq_lbl[0];
8098 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8099 name[IFNAMSIZ-1] = 0;
8100 }
fcfa0a32 8101
679563f4 8102 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
fcfa0a32
MC		 8103 fn = tg3_msi;
8104 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8105 fn = tg3_msi_1shot;
1fb9df5d 8106 flags = IRQF_SAMPLE_RANDOM;
fcfa0a32
MC		 8107 } else {
8108 fn = tg3_interrupt;
8109 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8110 fn = tg3_interrupt_tagged;
1fb9df5d 8111 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
fcfa0a32 8112 }
4f125f42
MC		 8113
8114 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 8115}
8116
7938109f
MC		 8117static int tg3_test_interrupt(struct tg3 *tp)
8118{
09943a18 8119 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 8120 struct net_device *dev = tp->dev;
b16250e3 8121 int err, i, intr_ok = 0;
f6eb9b1f 8122 u32 val;
7938109f 8123
d4bc3927
MC		 8124 if (!netif_running(dev))
8125 return -ENODEV;
8126
7938109f
MC		 8127 tg3_disable_ints(tp);
8128
4f125f42 8129 free_irq(tnapi->irq_vec, tnapi);
7938109f 8130
f6eb9b1f
MC		 8131 /*
8132 * Turn off MSI one shot mode. Otherwise this test has no
8133 * observable way to know whether the interrupt was delivered.
8134 */
8135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8136 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8137 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8138 tw32(MSGINT_MODE, val);
8139 }
8140
4f125f42 8141 err = request_irq(tnapi->irq_vec, tg3_test_isr,
09943a18 8142 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7938109f
MC		 8143 if (err)
8144 return err;
8145
898a56f8 8146 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 8147 tg3_enable_ints(tp);
8148
8149 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 8150 tnapi->coal_now);
7938109f
MC		 8151
8152 for (i = 0; i < 5; i++) {
b16250e3
MC		 8153 u32 int_mbox, misc_host_ctrl;
8154
898a56f8 8155 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 8156 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8157
8158 if ((int_mbox != 0) ||
8159 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8160 intr_ok = 1;
7938109f 8161 break;
b16250e3
MC		 8162 }
8163
7938109f
MC		 8164 msleep(10);
8165 }
8166
8167 tg3_disable_ints(tp);
8168
4f125f42 8169 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 8170
4f125f42 8171 err = tg3_request_irq(tp, 0);
7938109f
MC		 8172
8173 if (err)
8174 return err;
8175
f6eb9b1f
MC		 8176 if (intr_ok) {
8177 /* Reenable MSI one shot mode. */
8178 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8179 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8180 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8181 tw32(MSGINT_MODE, val);
8182 }
7938109f 8183 return 0;
f6eb9b1f 8184 }
7938109f
MC		 8185
8186 return -EIO;
8187}
8188
8189/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8190 * successfully restored
8191 */
8192static int tg3_test_msi(struct tg3 *tp)
8193{
7938109f
MC		 8194 int err;
8195 u16 pci_cmd;
8196
8197 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8198 return 0;
8199
8200 /* Turn off SERR reporting in case MSI terminates with Master
8201 * Abort.
8202 */
8203 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8204 pci_write_config_word(tp->pdev, PCI_COMMAND,
8205 pci_cmd & ~PCI_COMMAND_SERR);
8206
8207 err = tg3_test_interrupt(tp);
8208
8209 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8210
8211 if (!err)
8212 return 0;
8213
8214 /* other failures */
8215 if (err != -EIO)
8216 return err;
8217
8218 /* MSI test failed, go back to INTx mode */
8219 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8220 "switching to INTx mode. Please report this failure to "
8221 "the PCI maintainer and include system chipset information.\n",
8222 tp->dev->name);
8223
4f125f42 8224 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 8225
7938109f
MC		 8226 pci_disable_msi(tp->pdev);
8227
8228 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8229
4f125f42 8230 err = tg3_request_irq(tp, 0);
7938109f
MC		 8231 if (err)
8232 return err;
8233
8234 /* Need to reset the chip because the MSI cycle may have terminated
8235 * with Master Abort.
8236 */
f47c11ee 8237 tg3_full_lock(tp, 1);
7938109f 8238
944d980e 8239 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8e7a22e3 8240 err = tg3_init_hw(tp, 1);
7938109f 8241
f47c11ee 8242 tg3_full_unlock(tp);
7938109f
MC		 8243
8244 if (err)
4f125f42 8245 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 8246
8247 return err;
8248}
8249
9e9fd12d
MC		 8250static int tg3_request_firmware(struct tg3 *tp)
8251{
8252 const __be32 *fw_data;
8253
8254 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8255 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8256 tp->dev->name, tp->fw_needed);
8257 return -ENOENT;
8258 }
8259
8260 fw_data = (void *)tp->fw->data;
8261
8262 /* Firmware blob starts with version numbers, followed by
8263 * start address and _full_ length including BSS sections
8264 * (which must be longer than the actual data, of course
8265 */
8266
8267 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8268 if (tp->fw_len < (tp->fw->size - 12)) {
8269 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8270 tp->dev->name, tp->fw_len, tp->fw_needed);
8271 release_firmware(tp->fw);
8272 tp->fw = NULL;
8273 return -EINVAL;
8274 }
8275
8276 /* We no longer need firmware; we have it. */
8277 tp->fw_needed = NULL;
8278 return 0;
8279}
8280
679563f4
MC		 8281static bool tg3_enable_msix(struct tg3 *tp)
8282{
8283 int i, rc, cpus = num_online_cpus();
8284 struct msix_entry msix_ent[tp->irq_max];
8285
8286 if (cpus == 1)
8287 /* Just fallback to the simpler MSI mode. */
8288 return false;
8289
8290 /*
8291 * We want as many rx rings enabled as there are cpus.
8292 * The first MSIX vector only deals with link interrupts, etc,
8293 * so we add one to the number of vectors we are requesting.
8294 */
8295 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8296
8297 for (i = 0; i < tp->irq_max; i++) {
8298 msix_ent[i].entry = i;
8299 msix_ent[i].vector = 0;
8300 }
8301
8302 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8303 if (rc != 0) {
8304 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8305 return false;
8306 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8307 return false;
8308 printk(KERN_NOTICE
8309 "%s: Requested %d MSI-X vectors, received %d\n",
8310 tp->dev->name, tp->irq_cnt, rc);
8311 tp->irq_cnt = rc;
8312 }
8313
baf8a94a
MC		 8314 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8315
679563f4
MC		 8316 for (i = 0; i < tp->irq_max; i++)
8317 tp->napi[i].irq_vec = msix_ent[i].vector;
8318
fe5f5787
MC		 8319 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8320
679563f4
MC		 8321 return true;
8322}
8323
07b0173c
MC		 8324static void tg3_ints_init(struct tg3 *tp)
8325{
679563f4
MC		 8326 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8327 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
07b0173c
MC		 8328 /* All MSI supporting chips should support tagged
8329 * status. Assert that this is the case.
8330 */
679563f4
MC		 8331 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8332 "Not using MSI.\n", tp->dev->name);
8333 goto defcfg;
07b0173c 8334 }
4f125f42 8335
679563f4
MC		 8336 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8337 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8338 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8339 pci_enable_msi(tp->pdev) == 0)
8340 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8341
8342 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8343 u32 msi_mode = tr32(MSGINT_MODE);
baf8a94a
MC		 8344 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8345 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
679563f4
MC		 8346 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8347 }
8348defcfg:
8349 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8350 tp->irq_cnt = 1;
8351 tp->napi[0].irq_vec = tp->pdev->irq;
fe5f5787 8352 tp->dev->real_num_tx_queues = 1;
679563f4 8353 }
07b0173c
MC		 8354}
8355
8356static void tg3_ints_fini(struct tg3 *tp)
8357{
679563f4
MC		 8358 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8359 pci_disable_msix(tp->pdev);
8360 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8361 pci_disable_msi(tp->pdev);
8362 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
baf8a94a 8363 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
07b0173c
MC		 8364}
8365
1da177e4
LT		 8366static int tg3_open(struct net_device *dev)
8367{
8368 struct tg3 *tp = netdev_priv(dev);
4f125f42 8369 int i, err;
1da177e4 8370
9e9fd12d
MC		 8371 if (tp->fw_needed) {
8372 err = tg3_request_firmware(tp);
8373 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8374 if (err)
8375 return err;
8376 } else if (err) {
8377 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8378 tp->dev->name);
8379 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8380 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8381 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8382 tp->dev->name);
8383 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8384 }
8385 }
8386
c49a1561
MC		 8387 netif_carrier_off(tp->dev);
8388
bc1c7567 8389 err = tg3_set_power_state(tp, PCI_D0);
2f751b67 8390 if (err)
bc1c7567 8391 return err;
2f751b67
MC		 8392
8393 tg3_full_lock(tp, 0);
bc1c7567 8394
1da177e4
LT		 8395 tg3_disable_ints(tp);
8396 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8397
f47c11ee 8398 tg3_full_unlock(tp);
1da177e4 8399
679563f4
MC		 8400 /*
8401 * Setup interrupts first so we know how
8402 * many NAPI resources to allocate
8403 */
8404 tg3_ints_init(tp);
8405
1da177e4
LT		 8406 /* The placement of this call is tied
8407 * to the setup and use of Host TX descriptors.
8408 */
8409 err = tg3_alloc_consistent(tp);
8410 if (err)
679563f4 8411 goto err_out1;
88b06bc2 8412
fed97810 8413 tg3_napi_enable(tp);
1da177e4 8414
4f125f42
MC		 8415 for (i = 0; i < tp->irq_cnt; i++) {
8416 struct tg3_napi *tnapi = &tp->napi[i];
8417 err = tg3_request_irq(tp, i);
8418 if (err) {
8419 for (i--; i >= 0; i--)
8420 free_irq(tnapi->irq_vec, tnapi);
8421 break;
8422 }
8423 }
1da177e4 8424
07b0173c 8425 if (err)
679563f4 8426 goto err_out2;
bea3348e 8427
f47c11ee 8428 tg3_full_lock(tp, 0);
1da177e4 8429
8e7a22e3 8430 err = tg3_init_hw(tp, 1);
1da177e4 8431 if (err) {
944d980e 8432 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 8433 tg3_free_rings(tp);
8434 } else {
fac9b83e
DM		 8435 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8436 tp->timer_offset = HZ;
8437 else
8438 tp->timer_offset = HZ / 10;
8439
8440 BUG_ON(tp->timer_offset > HZ);
8441 tp->timer_counter = tp->timer_multiplier =
8442 (HZ / tp->timer_offset);
8443 tp->asf_counter = tp->asf_multiplier =
28fbef78 8444 ((HZ / tp->timer_offset) * 2);
1da177e4
LT		 8445
8446 init_timer(&tp->timer);
8447 tp->timer.expires = jiffies + tp->timer_offset;
8448 tp->timer.data = (unsigned long) tp;
8449 tp->timer.function = tg3_timer;
1da177e4
LT		 8450 }
8451
f47c11ee 8452 tg3_full_unlock(tp);
1da177e4 8453
07b0173c 8454 if (err)
679563f4 8455 goto err_out3;
1da177e4 8456
7938109f
MC		 8457 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8458 err = tg3_test_msi(tp);
fac9b83e 8459
7938109f 8460 if (err) {
f47c11ee 8461 tg3_full_lock(tp, 0);
944d980e 8462 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 8463 tg3_free_rings(tp);
f47c11ee 8464 tg3_full_unlock(tp);
7938109f 8465
679563f4 8466 goto err_out2;
7938109f 8467 }
fcfa0a32 8468
f6eb9b1f
MC		 8469 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8470 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8471 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8472 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 8473
f6eb9b1f
MC		 8474 tw32(PCIE_TRANSACTION_CFG,
8475 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 8476 }
7938109f
MC		 8477 }
8478
b02fd9e3
MC		 8479 tg3_phy_start(tp);
8480
f47c11ee 8481 tg3_full_lock(tp, 0);
1da177e4 8482
7938109f
MC		 8483 add_timer(&tp->timer);
8484 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 8485 tg3_enable_ints(tp);
8486
f47c11ee 8487 tg3_full_unlock(tp);
1da177e4 8488
fe5f5787 8489 netif_tx_start_all_queues(dev);
1da177e4
LT		 8490
8491 return 0;
07b0173c 8492
679563f4 8493err_out3:
4f125f42
MC		 8494 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8495 struct tg3_napi *tnapi = &tp->napi[i];
8496 free_irq(tnapi->irq_vec, tnapi);
8497 }
07b0173c 8498
679563f4 8499err_out2:
fed97810 8500 tg3_napi_disable(tp);
07b0173c 8501 tg3_free_consistent(tp);
679563f4
MC		 8502
8503err_out1:
8504 tg3_ints_fini(tp);
07b0173c 8505 return err;
1da177e4
LT		 8506}
8507
8508#if 0
8509/*static*/ void tg3_dump_state(struct tg3 *tp)
8510{
8511 u32 val32, val32_2, val32_3, val32_4, val32_5;
8512 u16 val16;
8513 int i;
898a56f8 8514 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
1da177e4
LT		 8515
8516 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8517 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8518 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8519 val16, val32);
8520
8521 /* MAC block */
8522 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8523 tr32(MAC_MODE), tr32(MAC_STATUS));
8524 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8525 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8526 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8527 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8528 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8529 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8530
8531 /* Send data initiator control block */
8532 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8533 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8534 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8535 tr32(SNDDATAI_STATSCTRL));
8536
8537 /* Send data completion control block */
8538 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8539
8540 /* Send BD ring selector block */
8541 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8542 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8543
8544 /* Send BD initiator control block */
8545 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8546 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8547
8548 /* Send BD completion control block */
8549 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8550
8551 /* Receive list placement control block */
8552 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8553 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8554 printk(" RCVLPC_STATSCTRL[%08x]\n",
8555 tr32(RCVLPC_STATSCTRL));
8556
8557 /* Receive data and receive BD initiator control block */
8558 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8559 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8560
8561 /* Receive data completion control block */
8562 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8563 tr32(RCVDCC_MODE));
8564
8565 /* Receive BD initiator control block */
8566 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8567 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8568
8569 /* Receive BD completion control block */
8570 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8571 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8572
8573 /* Receive list selector control block */
8574 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8575 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8576
8577 /* Mbuf cluster free block */
8578 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8579 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8580
8581 /* Host coalescing control block */
8582 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8583 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8584 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8585 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8586 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8587 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8588 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8589 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8590 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8591 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8592 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8593 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8594
8595 /* Memory arbiter control block */
8596 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8597 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8598
8599 /* Buffer manager control block */
8600 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8601 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8602 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8603 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8604 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8605 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8606 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8607 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8608
8609 /* Read DMA control block */
8610 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8611 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8612
8613 /* Write DMA control block */
8614 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8615 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8616
8617 /* DMA completion block */
8618 printk("DEBUG: DMAC_MODE[%08x]\n",
8619 tr32(DMAC_MODE));
8620
8621 /* GRC block */
8622 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8623 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8624 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8625 tr32(GRC_LOCAL_CTRL));
8626
8627 /* TG3_BDINFOs */
8628 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8629 tr32(RCVDBDI_JUMBO_BD + 0x0),
8630 tr32(RCVDBDI_JUMBO_BD + 0x4),
8631 tr32(RCVDBDI_JUMBO_BD + 0x8),
8632 tr32(RCVDBDI_JUMBO_BD + 0xc));
8633 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8634 tr32(RCVDBDI_STD_BD + 0x0),
8635 tr32(RCVDBDI_STD_BD + 0x4),
8636 tr32(RCVDBDI_STD_BD + 0x8),
8637 tr32(RCVDBDI_STD_BD + 0xc));
8638 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8639 tr32(RCVDBDI_MINI_BD + 0x0),
8640 tr32(RCVDBDI_MINI_BD + 0x4),
8641 tr32(RCVDBDI_MINI_BD + 0x8),
8642 tr32(RCVDBDI_MINI_BD + 0xc));
8643
8644 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8645 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8646 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8647 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8648 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8649 val32, val32_2, val32_3, val32_4);
8650
8651 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8652 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8653 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8654 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8655 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8656 val32, val32_2, val32_3, val32_4);
8657
8658 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8659 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8660 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8661 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8662 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8663 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8664 val32, val32_2, val32_3, val32_4, val32_5);
8665
8666 /* SW status block */
898a56f8
MC		 8667 printk(KERN_DEBUG
8668 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8669 sblk->status,
8670 sblk->status_tag,
8671 sblk->rx_jumbo_consumer,
8672 sblk->rx_consumer,
8673 sblk->rx_mini_consumer,
8674 sblk->idx[0].rx_producer,
8675 sblk->idx[0].tx_consumer);
1da177e4
LT		 8676
8677 /* SW statistics block */
8678 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8679 ((u32 *)tp->hw_stats)[0],
8680 ((u32 *)tp->hw_stats)[1],
8681 ((u32 *)tp->hw_stats)[2],
8682 ((u32 *)tp->hw_stats)[3]);
8683
8684 /* Mailboxes */
8685 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 8686 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8687 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8688 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8689 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 8690
8691 /* NIC side send descriptors. */
8692 for (i = 0; i < 6; i++) {
8693 unsigned long txd;
8694
8695 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8696 + (i * sizeof(struct tg3_tx_buffer_desc));
8697 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8698 i,
8699 readl(txd + 0x0), readl(txd + 0x4),
8700 readl(txd + 0x8), readl(txd + 0xc));
8701 }
8702
8703 /* NIC side RX descriptors. */
8704 for (i = 0; i < 6; i++) {
8705 unsigned long rxd;
8706
8707 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8708 + (i * sizeof(struct tg3_rx_buffer_desc));
8709 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8710 i,
8711 readl(rxd + 0x0), readl(rxd + 0x4),
8712 readl(rxd + 0x8), readl(rxd + 0xc));
8713 rxd += (4 * sizeof(u32));
8714 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8715 i,
8716 readl(rxd + 0x0), readl(rxd + 0x4),
8717 readl(rxd + 0x8), readl(rxd + 0xc));
8718 }
8719
8720 for (i = 0; i < 6; i++) {
8721 unsigned long rxd;
8722
8723 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8724 + (i * sizeof(struct tg3_rx_buffer_desc));
8725 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8726 i,
8727 readl(rxd + 0x0), readl(rxd + 0x4),
8728 readl(rxd + 0x8), readl(rxd + 0xc));
8729 rxd += (4 * sizeof(u32));
8730 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8731 i,
8732 readl(rxd + 0x0), readl(rxd + 0x4),
8733 readl(rxd + 0x8), readl(rxd + 0xc));
8734 }
8735}
8736#endif
8737
8738static struct net_device_stats *tg3_get_stats(struct net_device *);
8739static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8740
8741static int tg3_close(struct net_device *dev)
8742{
4f125f42 8743 int i;
1da177e4
LT		 8744 struct tg3 *tp = netdev_priv(dev);
8745
fed97810 8746 tg3_napi_disable(tp);
28e53bdd 8747 cancel_work_sync(&tp->reset_task);
7faa006f 8748
fe5f5787 8749 netif_tx_stop_all_queues(dev);
1da177e4
LT		 8750
8751 del_timer_sync(&tp->timer);
8752
24bb4fb6
MC		 8753 tg3_phy_stop(tp);
8754
f47c11ee 8755 tg3_full_lock(tp, 1);
1da177e4
LT		 8756#if 0
8757 tg3_dump_state(tp);
8758#endif
8759
8760 tg3_disable_ints(tp);
8761
944d980e 8762 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 8763 tg3_free_rings(tp);
5cf64b8a 8764 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
1da177e4 8765
f47c11ee 8766 tg3_full_unlock(tp);
1da177e4 8767
4f125f42
MC		 8768 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8769 struct tg3_napi *tnapi = &tp->napi[i];
8770 free_irq(tnapi->irq_vec, tnapi);
8771 }
07b0173c
MC		 8772
8773 tg3_ints_fini(tp);
1da177e4
LT		 8774
8775 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8776 sizeof(tp->net_stats_prev));
8777 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8778 sizeof(tp->estats_prev));
8779
8780 tg3_free_consistent(tp);
8781
bc1c7567
MC		 8782 tg3_set_power_state(tp, PCI_D3hot);
8783
8784 netif_carrier_off(tp->dev);
8785
1da177e4
LT		 8786 return 0;
8787}
8788
8789static inline unsigned long get_stat64(tg3_stat64_t *val)
8790{
8791 unsigned long ret;
8792
8793#if (BITS_PER_LONG == 32)
8794 ret = val->low;
8795#else
8796 ret = ((u64)val->high << 32) | ((u64)val->low);
8797#endif
8798 return ret;
8799}
8800
816f8b86
SB		 8801static inline u64 get_estat64(tg3_stat64_t *val)
8802{
8803 return ((u64)val->high << 32) | ((u64)val->low);
8804}
8805
1da177e4
LT		 8806static unsigned long calc_crc_errors(struct tg3 *tp)
8807{
8808 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8809
8810 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8811 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8812 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 8813 u32 val;
8814
f47c11ee 8815 spin_lock_bh(&tp->lock);
569a5df8
MC		 8816 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8817 tg3_writephy(tp, MII_TG3_TEST1,
8818 val | MII_TG3_TEST1_CRC_EN);
1da177e4
LT		 8819 tg3_readphy(tp, 0x14, &val);
8820 } else
8821 val = 0;
f47c11ee 8822 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8823
8824 tp->phy_crc_errors += val;
8825
8826 return tp->phy_crc_errors;
8827 }
8828
8829 return get_stat64(&hw_stats->rx_fcs_errors);
8830}
8831
8832#define ESTAT_ADD(member) \
8833 estats->member = old_estats->member + \
816f8b86 8834 get_estat64(&hw_stats->member)
1da177e4
LT		 8835
8836static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8837{
8838 struct tg3_ethtool_stats *estats = &tp->estats;
8839 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8840 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8841
8842 if (!hw_stats)
8843 return old_estats;
8844
8845 ESTAT_ADD(rx_octets);
8846 ESTAT_ADD(rx_fragments);
8847 ESTAT_ADD(rx_ucast_packets);
8848 ESTAT_ADD(rx_mcast_packets);
8849 ESTAT_ADD(rx_bcast_packets);
8850 ESTAT_ADD(rx_fcs_errors);
8851 ESTAT_ADD(rx_align_errors);
8852 ESTAT_ADD(rx_xon_pause_rcvd);
8853 ESTAT_ADD(rx_xoff_pause_rcvd);
8854 ESTAT_ADD(rx_mac_ctrl_rcvd);
8855 ESTAT_ADD(rx_xoff_entered);
8856 ESTAT_ADD(rx_frame_too_long_errors);
8857 ESTAT_ADD(rx_jabbers);
8858 ESTAT_ADD(rx_undersize_packets);
8859 ESTAT_ADD(rx_in_length_errors);
8860 ESTAT_ADD(rx_out_length_errors);
8861 ESTAT_ADD(rx_64_or_less_octet_packets);
8862 ESTAT_ADD(rx_65_to_127_octet_packets);
8863 ESTAT_ADD(rx_128_to_255_octet_packets);
8864 ESTAT_ADD(rx_256_to_511_octet_packets);
8865 ESTAT_ADD(rx_512_to_1023_octet_packets);
8866 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8867 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8868 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8869 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8870 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8871
8872 ESTAT_ADD(tx_octets);
8873 ESTAT_ADD(tx_collisions);
8874 ESTAT_ADD(tx_xon_sent);
8875 ESTAT_ADD(tx_xoff_sent);
8876 ESTAT_ADD(tx_flow_control);
8877 ESTAT_ADD(tx_mac_errors);
8878 ESTAT_ADD(tx_single_collisions);
8879 ESTAT_ADD(tx_mult_collisions);
8880 ESTAT_ADD(tx_deferred);
8881 ESTAT_ADD(tx_excessive_collisions);
8882 ESTAT_ADD(tx_late_collisions);
8883 ESTAT_ADD(tx_collide_2times);
8884 ESTAT_ADD(tx_collide_3times);
8885 ESTAT_ADD(tx_collide_4times);
8886 ESTAT_ADD(tx_collide_5times);
8887 ESTAT_ADD(tx_collide_6times);
8888 ESTAT_ADD(tx_collide_7times);
8889 ESTAT_ADD(tx_collide_8times);
8890 ESTAT_ADD(tx_collide_9times);
8891 ESTAT_ADD(tx_collide_10times);
8892 ESTAT_ADD(tx_collide_11times);
8893 ESTAT_ADD(tx_collide_12times);
8894 ESTAT_ADD(tx_collide_13times);
8895 ESTAT_ADD(tx_collide_14times);
8896 ESTAT_ADD(tx_collide_15times);
8897 ESTAT_ADD(tx_ucast_packets);
8898 ESTAT_ADD(tx_mcast_packets);
8899 ESTAT_ADD(tx_bcast_packets);
8900 ESTAT_ADD(tx_carrier_sense_errors);
8901 ESTAT_ADD(tx_discards);
8902 ESTAT_ADD(tx_errors);
8903
8904 ESTAT_ADD(dma_writeq_full);
8905 ESTAT_ADD(dma_write_prioq_full);
8906 ESTAT_ADD(rxbds_empty);
8907 ESTAT_ADD(rx_discards);
8908 ESTAT_ADD(rx_errors);
8909 ESTAT_ADD(rx_threshold_hit);
8910
8911 ESTAT_ADD(dma_readq_full);
8912 ESTAT_ADD(dma_read_prioq_full);
8913 ESTAT_ADD(tx_comp_queue_full);
8914
8915 ESTAT_ADD(ring_set_send_prod_index);
8916 ESTAT_ADD(ring_status_update);
8917 ESTAT_ADD(nic_irqs);
8918 ESTAT_ADD(nic_avoided_irqs);
8919 ESTAT_ADD(nic_tx_threshold_hit);
8920
8921 return estats;
8922}
8923
8924static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8925{
8926 struct tg3 *tp = netdev_priv(dev);
8927 struct net_device_stats *stats = &tp->net_stats;
8928 struct net_device_stats *old_stats = &tp->net_stats_prev;
8929 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8930
8931 if (!hw_stats)
8932 return old_stats;
8933
8934 stats->rx_packets = old_stats->rx_packets +
8935 get_stat64(&hw_stats->rx_ucast_packets) +
8936 get_stat64(&hw_stats->rx_mcast_packets) +
8937 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 8938
1da177e4
LT		 8939 stats->tx_packets = old_stats->tx_packets +
8940 get_stat64(&hw_stats->tx_ucast_packets) +
8941 get_stat64(&hw_stats->tx_mcast_packets) +
8942 get_stat64(&hw_stats->tx_bcast_packets);
8943
8944 stats->rx_bytes = old_stats->rx_bytes +
8945 get_stat64(&hw_stats->rx_octets);
8946 stats->tx_bytes = old_stats->tx_bytes +
8947 get_stat64(&hw_stats->tx_octets);
8948
8949 stats->rx_errors = old_stats->rx_errors +
4f63b877 8950 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 8951 stats->tx_errors = old_stats->tx_errors +
8952 get_stat64(&hw_stats->tx_errors) +
8953 get_stat64(&hw_stats->tx_mac_errors) +
8954 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8955 get_stat64(&hw_stats->tx_discards);
8956
8957 stats->multicast = old_stats->multicast +
8958 get_stat64(&hw_stats->rx_mcast_packets);
8959 stats->collisions = old_stats->collisions +
8960 get_stat64(&hw_stats->tx_collisions);
8961
8962 stats->rx_length_errors = old_stats->rx_length_errors +
8963 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8964 get_stat64(&hw_stats->rx_undersize_packets);
8965
8966 stats->rx_over_errors = old_stats->rx_over_errors +
8967 get_stat64(&hw_stats->rxbds_empty);
8968 stats->rx_frame_errors = old_stats->rx_frame_errors +
8969 get_stat64(&hw_stats->rx_align_errors);
8970 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8971 get_stat64(&hw_stats->tx_discards);
8972 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8973 get_stat64(&hw_stats->tx_carrier_sense_errors);
8974
8975 stats->rx_crc_errors = old_stats->rx_crc_errors +
8976 calc_crc_errors(tp);
8977
4f63b877
JL		 8978 stats->rx_missed_errors = old_stats->rx_missed_errors +
8979 get_stat64(&hw_stats->rx_discards);
8980
1da177e4
LT		 8981 return stats;
8982}
8983
8984static inline u32 calc_crc(unsigned char *buf, int len)
8985{
8986 u32 reg;
8987 u32 tmp;
8988 int j, k;
8989
8990 reg = 0xffffffff;
8991
8992 for (j = 0; j < len; j++) {
8993 reg ^= buf[j];
8994
8995 for (k = 0; k < 8; k++) {
8996 tmp = reg & 0x01;
8997
8998 reg >>= 1;
8999
9000 if (tmp) {
9001 reg ^= 0xedb88320;
9002 }
9003 }
9004 }
9005
9006 return ~reg;
9007}
9008
9009static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9010{
9011 /* accept or reject all multicast frames */
9012 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9013 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9014 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9015 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9016}
9017
9018static void __tg3_set_rx_mode(struct net_device *dev)
9019{
9020 struct tg3 *tp = netdev_priv(dev);
9021 u32 rx_mode;
9022
9023 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9024 RX_MODE_KEEP_VLAN_TAG);
9025
9026 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9027 * flag clear.
9028 */
9029#if TG3_VLAN_TAG_USED
9030 if (!tp->vlgrp &&
9031 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9032 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9033#else
9034 /* By definition, VLAN is disabled always in this
9035 * case.
9036 */
9037 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9038 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9039#endif
9040
9041 if (dev->flags & IFF_PROMISC) {
9042 /* Promiscuous mode. */
9043 rx_mode |= RX_MODE_PROMISC;
9044 } else if (dev->flags & IFF_ALLMULTI) {
9045 /* Accept all multicast. */
9046 tg3_set_multi (tp, 1);
9047 } else if (dev->mc_count < 1) {
9048 /* Reject all multicast. */
9049 tg3_set_multi (tp, 0);
9050 } else {
9051 /* Accept one or more multicast(s). */
9052 struct dev_mc_list *mclist;
9053 unsigned int i;
9054 u32 mc_filter[4] = { 0, };
9055 u32 regidx;
9056 u32 bit;
9057 u32 crc;
9058
9059 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9060 i++, mclist = mclist->next) {
9061
9062 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9063 bit = ~crc & 0x7f;
9064 regidx = (bit & 0x60) >> 5;
9065 bit &= 0x1f;
9066 mc_filter[regidx] |= (1 << bit);
9067 }
9068
9069 tw32(MAC_HASH_REG_0, mc_filter[0]);
9070 tw32(MAC_HASH_REG_1, mc_filter[1]);
9071 tw32(MAC_HASH_REG_2, mc_filter[2]);
9072 tw32(MAC_HASH_REG_3, mc_filter[3]);
9073 }
9074
9075 if (rx_mode != tp->rx_mode) {
9076 tp->rx_mode = rx_mode;
9077 tw32_f(MAC_RX_MODE, rx_mode);
9078 udelay(10);
9079 }
9080}
9081
9082static void tg3_set_rx_mode(struct net_device *dev)
9083{
9084 struct tg3 *tp = netdev_priv(dev);
9085
e75f7c90
MC		 9086 if (!netif_running(dev))
9087 return;
9088
f47c11ee 9089 tg3_full_lock(tp, 0);
1da177e4 9090 __tg3_set_rx_mode(dev);
f47c11ee 9091 tg3_full_unlock(tp);
1da177e4
LT		 9092}
9093
9094#define TG3_REGDUMP_LEN (32 * 1024)
9095
9096static int tg3_get_regs_len(struct net_device *dev)
9097{
9098 return TG3_REGDUMP_LEN;
9099}
9100
9101static void tg3_get_regs(struct net_device *dev,
9102 struct ethtool_regs *regs, void *_p)
9103{
9104 u32 *p = _p;
9105 struct tg3 *tp = netdev_priv(dev);
9106 u8 *orig_p = _p;
9107 int i;
9108
9109 regs->version = 0;
9110
9111 memset(p, 0, TG3_REGDUMP_LEN);
9112
bc1c7567
MC		 9113 if (tp->link_config.phy_is_low_power)
9114 return;
9115
f47c11ee 9116 tg3_full_lock(tp, 0);
1da177e4
LT		 9117
9118#define __GET_REG32(reg) (*(p)++ = tr32(reg))
9119#define GET_REG32_LOOP(base,len) \
9120do { p = (u32 *)(orig_p + (base)); \
9121 for (i = 0; i < len; i += 4) \
9122 __GET_REG32((base) + i); \
9123} while (0)
9124#define GET_REG32_1(reg) \
9125do { p = (u32 *)(orig_p + (reg)); \
9126 __GET_REG32((reg)); \
9127} while (0)
9128
9129 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9130 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9131 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9132 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9133 GET_REG32_1(SNDDATAC_MODE);
9134 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9135 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9136 GET_REG32_1(SNDBDC_MODE);
9137 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9138 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9139 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9140 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9141 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9142 GET_REG32_1(RCVDCC_MODE);
9143 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9144 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9145 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9146 GET_REG32_1(MBFREE_MODE);
9147 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9148 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9149 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9150 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9151 GET_REG32_LOOP(WDMAC_MODE, 0x08);
091465d7
CE		 9152 GET_REG32_1(RX_CPU_MODE);
9153 GET_REG32_1(RX_CPU_STATE);
9154 GET_REG32_1(RX_CPU_PGMCTR);
9155 GET_REG32_1(RX_CPU_HWBKPT);
9156 GET_REG32_1(TX_CPU_MODE);
9157 GET_REG32_1(TX_CPU_STATE);
9158 GET_REG32_1(TX_CPU_PGMCTR);
1da177e4
LT		 9159 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9160 GET_REG32_LOOP(FTQ_RESET, 0x120);
9161 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9162 GET_REG32_1(DMAC_MODE);
9163 GET_REG32_LOOP(GRC_MODE, 0x4c);
9164 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9165 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9166
9167#undef __GET_REG32
9168#undef GET_REG32_LOOP
9169#undef GET_REG32_1
9170
f47c11ee 9171 tg3_full_unlock(tp);
1da177e4
LT		 9172}
9173
9174static int tg3_get_eeprom_len(struct net_device *dev)
9175{
9176 struct tg3 *tp = netdev_priv(dev);
9177
9178 return tp->nvram_size;
9179}
9180
1da177e4
LT		 9181static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9182{
9183 struct tg3 *tp = netdev_priv(dev);
9184 int ret;
9185 u8 *pd;
b9fc7dc5 9186 u32 i, offset, len, b_offset, b_count;
a9dc529d 9187 __be32 val;
1da177e4 9188
df259d8c
MC		 9189 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9190 return -EINVAL;
9191
bc1c7567
MC		 9192 if (tp->link_config.phy_is_low_power)
9193 return -EAGAIN;
9194
1da177e4
LT		 9195 offset = eeprom->offset;
9196 len = eeprom->len;
9197 eeprom->len = 0;
9198
9199 eeprom->magic = TG3_EEPROM_MAGIC;
9200
9201 if (offset & 3) {
9202 /* adjustments to start on required 4 byte boundary */
9203 b_offset = offset & 3;
9204 b_count = 4 - b_offset;
9205 if (b_count > len) {
9206 /* i.e. offset=1 len=2 */
9207 b_count = len;
9208 }
a9dc529d 9209 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 9210 if (ret)
9211 return ret;
1da177e4
LT		 9212 memcpy(data, ((char*)&val) + b_offset, b_count);
9213 len -= b_count;
9214 offset += b_count;
9215 eeprom->len += b_count;
9216 }
9217
9218 /* read bytes upto the last 4 byte boundary */
9219 pd = &data[eeprom->len];
9220 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 9221 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 9222 if (ret) {
9223 eeprom->len += i;
9224 return ret;
9225 }
1da177e4
LT		 9226 memcpy(pd + i, &val, 4);
9227 }
9228 eeprom->len += i;
9229
9230 if (len & 3) {
9231 /* read last bytes not ending on 4 byte boundary */
9232 pd = &data[eeprom->len];
9233 b_count = len & 3;
9234 b_offset = offset + len - b_count;
a9dc529d 9235 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 9236 if (ret)
9237 return ret;
b9fc7dc5 9238 memcpy(pd, &val, b_count);
1da177e4
LT		 9239 eeprom->len += b_count;
9240 }
9241 return 0;
9242}
9243
6aa20a22 9244static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
1da177e4
LT		 9245
9246static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9247{
9248 struct tg3 *tp = netdev_priv(dev);
9249 int ret;
b9fc7dc5 9250 u32 offset, len, b_offset, odd_len;
1da177e4 9251 u8 *buf;
a9dc529d 9252 __be32 start, end;
1da177e4 9253
bc1c7567
MC		 9254 if (tp->link_config.phy_is_low_power)
9255 return -EAGAIN;
9256
df259d8c
MC		 9257 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9258 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 9259 return -EINVAL;
9260
9261 offset = eeprom->offset;
9262 len = eeprom->len;
9263
9264 if ((b_offset = (offset & 3))) {
9265 /* adjustments to start on required 4 byte boundary */
a9dc529d 9266 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 9267 if (ret)
9268 return ret;
1da177e4
LT		 9269 len += b_offset;
9270 offset &= ~3;
1c8594b4
MC		 9271 if (len < 4)
9272 len = 4;
1da177e4
LT		 9273 }
9274
9275 odd_len = 0;
1c8594b4 9276 if (len & 3) {
1da177e4
LT		 9277 /* adjustments to end on required 4 byte boundary */
9278 odd_len = 1;
9279 len = (len + 3) & ~3;
a9dc529d 9280 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 9281 if (ret)
9282 return ret;
1da177e4
LT		 9283 }
9284
9285 buf = data;
9286 if (b_offset || odd_len) {
9287 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 9288 if (!buf)
1da177e4
LT		 9289 return -ENOMEM;
9290 if (b_offset)
9291 memcpy(buf, &start, 4);
9292 if (odd_len)
9293 memcpy(buf+len-4, &end, 4);
9294 memcpy(buf + b_offset, data, eeprom->len);
9295 }
9296
9297 ret = tg3_nvram_write_block(tp, offset, len, buf);
9298
9299 if (buf != data)
9300 kfree(buf);
9301
9302 return ret;
9303}
9304
9305static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9306{
b02fd9e3
MC		 9307 struct tg3 *tp = netdev_priv(dev);
9308
9309 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9310 struct phy_device *phydev;
b02fd9e3
MC		 9311 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9312 return -EAGAIN;
3f0e3ad7
MC		 9313 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9314 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 9315 }
6aa20a22 9316
1da177e4
LT		 9317 cmd->supported = (SUPPORTED_Autoneg);
9318
9319 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9320 cmd->supported |= (SUPPORTED_1000baseT_Half |
9321 SUPPORTED_1000baseT_Full);
9322
ef348144 9323 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 9324 cmd->supported |= (SUPPORTED_100baseT_Half |
9325 SUPPORTED_100baseT_Full |
9326 SUPPORTED_10baseT_Half |
9327 SUPPORTED_10baseT_Full |
3bebab59 9328 SUPPORTED_TP);
ef348144
KK		 9329 cmd->port = PORT_TP;
9330 } else {
1da177e4 9331 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 9332 cmd->port = PORT_FIBRE;
9333 }
6aa20a22 9334
1da177e4
LT		 9335 cmd->advertising = tp->link_config.advertising;
9336 if (netif_running(dev)) {
9337 cmd->speed = tp->link_config.active_speed;
9338 cmd->duplex = tp->link_config.active_duplex;
9339 }
882e9793 9340 cmd->phy_address = tp->phy_addr;
7e5856bd 9341 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 9342 cmd->autoneg = tp->link_config.autoneg;
9343 cmd->maxtxpkt = 0;
9344 cmd->maxrxpkt = 0;
9345 return 0;
9346}
6aa20a22 9347
1da177e4
LT		 9348static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9349{
9350 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9351
b02fd9e3 9352 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 9353 struct phy_device *phydev;
b02fd9e3
MC		 9354 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9355 return -EAGAIN;
3f0e3ad7
MC		 9356 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9357 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 9358 }
9359
7e5856bd
MC		 9360 if (cmd->autoneg != AUTONEG_ENABLE &&
9361 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 9362 return -EINVAL;
7e5856bd
MC		 9363
9364 if (cmd->autoneg == AUTONEG_DISABLE &&
9365 cmd->duplex != DUPLEX_FULL &&
9366 cmd->duplex != DUPLEX_HALF)
37ff238d 9367 return -EINVAL;
1da177e4 9368
7e5856bd
MC		 9369 if (cmd->autoneg == AUTONEG_ENABLE) {
9370 u32 mask = ADVERTISED_Autoneg |
9371 ADVERTISED_Pause |
9372 ADVERTISED_Asym_Pause;
9373
9374 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9375 mask |= ADVERTISED_1000baseT_Half |
9376 ADVERTISED_1000baseT_Full;
9377
9378 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9379 mask |= ADVERTISED_100baseT_Half |
9380 ADVERTISED_100baseT_Full |
9381 ADVERTISED_10baseT_Half |
9382 ADVERTISED_10baseT_Full |
9383 ADVERTISED_TP;
9384 else
9385 mask |= ADVERTISED_FIBRE;
9386
9387 if (cmd->advertising & ~mask)
9388 return -EINVAL;
9389
9390 mask &= (ADVERTISED_1000baseT_Half |
9391 ADVERTISED_1000baseT_Full |
9392 ADVERTISED_100baseT_Half |
9393 ADVERTISED_100baseT_Full |
9394 ADVERTISED_10baseT_Half |
9395 ADVERTISED_10baseT_Full);
9396
9397 cmd->advertising &= mask;
9398 } else {
9399 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9400 if (cmd->speed != SPEED_1000)
9401 return -EINVAL;
9402
9403 if (cmd->duplex != DUPLEX_FULL)
9404 return -EINVAL;
9405 } else {
9406 if (cmd->speed != SPEED_100 &&
9407 cmd->speed != SPEED_10)
9408 return -EINVAL;
9409 }
9410 }
9411
f47c11ee 9412 tg3_full_lock(tp, 0);
1da177e4
LT		 9413
9414 tp->link_config.autoneg = cmd->autoneg;
9415 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 9416 tp->link_config.advertising = (cmd->advertising |
9417 ADVERTISED_Autoneg);
1da177e4
LT		 9418 tp->link_config.speed = SPEED_INVALID;
9419 tp->link_config.duplex = DUPLEX_INVALID;
9420 } else {
9421 tp->link_config.advertising = 0;
9422 tp->link_config.speed = cmd->speed;
9423 tp->link_config.duplex = cmd->duplex;
b02fd9e3 9424 }
6aa20a22 9425
24fcad6b
MC		 9426 tp->link_config.orig_speed = tp->link_config.speed;
9427 tp->link_config.orig_duplex = tp->link_config.duplex;
9428 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9429
1da177e4
LT		 9430 if (netif_running(dev))
9431 tg3_setup_phy(tp, 1);
9432
f47c11ee 9433 tg3_full_unlock(tp);
6aa20a22 9434
1da177e4
LT		 9435 return 0;
9436}
6aa20a22 9437
1da177e4
LT		 9438static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9439{
9440 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9441
1da177e4
LT		 9442 strcpy(info->driver, DRV_MODULE_NAME);
9443 strcpy(info->version, DRV_MODULE_VERSION);
c4e6575c 9444 strcpy(info->fw_version, tp->fw_ver);
1da177e4
LT		 9445 strcpy(info->bus_info, pci_name(tp->pdev));
9446}
6aa20a22 9447
1da177e4
LT		 9448static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9449{
9450 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9451
12dac075
RW		 9452 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9453 device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 9454 wol->supported = WAKE_MAGIC;
9455 else
9456 wol->supported = 0;
1da177e4 9457 wol->wolopts = 0;
05ac4cb7
MC		 9458 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9459 device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 9460 wol->wolopts = WAKE_MAGIC;
9461 memset(&wol->sopass, 0, sizeof(wol->sopass));
9462}
6aa20a22 9463
1da177e4
LT		 9464static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9465{
9466 struct tg3 *tp = netdev_priv(dev);
12dac075 9467 struct device *dp = &tp->pdev->dev;
6aa20a22 9468
1da177e4
LT		 9469 if (wol->wolopts & ~WAKE_MAGIC)
9470 return -EINVAL;
9471 if ((wol->wolopts & WAKE_MAGIC) &&
12dac075 9472 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
1da177e4 9473 return -EINVAL;
6aa20a22 9474
f47c11ee 9475 spin_lock_bh(&tp->lock);
12dac075 9476 if (wol->wolopts & WAKE_MAGIC) {
1da177e4 9477 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9478 device_set_wakeup_enable(dp, true);
9479 } else {
1da177e4 9480 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
12dac075
RW		 9481 device_set_wakeup_enable(dp, false);
9482 }
f47c11ee 9483 spin_unlock_bh(&tp->lock);
6aa20a22 9484
1da177e4
LT		 9485 return 0;
9486}
6aa20a22 9487
1da177e4
LT		 9488static u32 tg3_get_msglevel(struct net_device *dev)
9489{
9490 struct tg3 *tp = netdev_priv(dev);
9491 return tp->msg_enable;
9492}
6aa20a22 9493
1da177e4
LT		 9494static void tg3_set_msglevel(struct net_device *dev, u32 value)
9495{
9496 struct tg3 *tp = netdev_priv(dev);
9497 tp->msg_enable = value;
9498}
6aa20a22 9499
1da177e4
LT		 9500static int tg3_set_tso(struct net_device *dev, u32 value)
9501{
9502 struct tg3 *tp = netdev_priv(dev);
9503
9504 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9505 if (value)
9506 return -EINVAL;
9507 return 0;
9508 }
027455ad
MC		 9509 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9510 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9936bcf6 9511 if (value) {
b0026624 9512 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 9513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9514 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9515 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 9516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 9517 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9518 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6
MC		 9519 dev->features |= NETIF_F_TSO_ECN;
9520 } else
9521 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
b0026624 9522 }
1da177e4
LT		 9523 return ethtool_op_set_tso(dev, value);
9524}
6aa20a22 9525
1da177e4
LT		 9526static int tg3_nway_reset(struct net_device *dev)
9527{
9528 struct tg3 *tp = netdev_priv(dev);
1da177e4 9529 int r;
6aa20a22 9530
1da177e4
LT		 9531 if (!netif_running(dev))
9532 return -EAGAIN;
9533
c94e3941
MC		 9534 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9535 return -EINVAL;
9536
b02fd9e3
MC		 9537 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9538 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9539 return -EAGAIN;
3f0e3ad7 9540 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 9541 } else {
9542 u32 bmcr;
9543
9544 spin_lock_bh(&tp->lock);
9545 r = -EINVAL;
9546 tg3_readphy(tp, MII_BMCR, &bmcr);
9547 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9548 ((bmcr & BMCR_ANENABLE) ||
9549 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9550 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9551 BMCR_ANENABLE);
9552 r = 0;
9553 }
9554 spin_unlock_bh(&tp->lock);
1da177e4 9555 }
6aa20a22 9556
1da177e4
LT		 9557 return r;
9558}
6aa20a22 9559
1da177e4
LT		 9560static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9561{
9562 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9563
1da177e4
LT		 9564 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9565 ering->rx_mini_max_pending = 0;
4f81c32b
MC		 9566 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9567 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9568 else
9569 ering->rx_jumbo_max_pending = 0;
9570
9571 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 9572
9573 ering->rx_pending = tp->rx_pending;
9574 ering->rx_mini_pending = 0;
4f81c32b
MC		 9575 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9576 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9577 else
9578 ering->rx_jumbo_pending = 0;
9579
f3f3f27e 9580 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 9581}
6aa20a22 9582
1da177e4
LT		 9583static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9584{
9585 struct tg3 *tp = netdev_priv(dev);
646c9edd 9586 int i, irq_sync = 0, err = 0;
6aa20a22 9587
1da177e4
LT		 9588 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9589 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
bc3a9254
MC		 9590 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9591 (ering->tx_pending <= MAX_SKB_FRAGS) ||
7f62ad5d 9592 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
bc3a9254 9593 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 9594 return -EINVAL;
6aa20a22 9595
bbe832c0 9596 if (netif_running(dev)) {
b02fd9e3 9597 tg3_phy_stop(tp);
1da177e4 9598 tg3_netif_stop(tp);
bbe832c0
MC		 9599 irq_sync = 1;
9600 }
1da177e4 9601
bbe832c0 9602 tg3_full_lock(tp, irq_sync);
6aa20a22 9603
1da177e4
LT		 9604 tp->rx_pending = ering->rx_pending;
9605
9606 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9607 tp->rx_pending > 63)
9608 tp->rx_pending = 63;
9609 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd
MC		 9610
9611 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9612 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 9613
9614 if (netif_running(dev)) {
944d980e 9615 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
b9ec6c1b
MC		 9616 err = tg3_restart_hw(tp, 1);
9617 if (!err)
9618 tg3_netif_start(tp);
1da177e4
LT		 9619 }
9620
f47c11ee 9621 tg3_full_unlock(tp);
6aa20a22 9622
b02fd9e3
MC		 9623 if (irq_sync && !err)
9624 tg3_phy_start(tp);
9625
b9ec6c1b 9626 return err;
1da177e4 9627}
6aa20a22 9628
1da177e4
LT		 9629static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9630{
9631 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9632
1da177e4 9633 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8d018621 9634
e18ce346 9635 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8d018621
MC		 9636 epause->rx_pause = 1;
9637 else
9638 epause->rx_pause = 0;
9639
e18ce346 9640 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8d018621
MC		 9641 epause->tx_pause = 1;
9642 else
9643 epause->tx_pause = 0;
1da177e4 9644}
6aa20a22 9645
1da177e4
LT		 9646static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9647{
9648 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 9649 int err = 0;
6aa20a22 9650
b02fd9e3
MC		 9651 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9652 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9653 return -EAGAIN;
1da177e4 9654
b02fd9e3
MC		 9655 if (epause->autoneg) {
9656 u32 newadv;
9657 struct phy_device *phydev;
f47c11ee 9658
3f0e3ad7 9659 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1da177e4 9660
b02fd9e3
MC		 9661 if (epause->rx_pause) {
9662 if (epause->tx_pause)
9663 newadv = ADVERTISED_Pause;
9664 else
9665 newadv = ADVERTISED_Pause |
9666 ADVERTISED_Asym_Pause;
9667 } else if (epause->tx_pause) {
9668 newadv = ADVERTISED_Asym_Pause;
9669 } else
9670 newadv = 0;
9671
9672 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9673 u32 oldadv = phydev->advertising &
9674 (ADVERTISED_Pause |
9675 ADVERTISED_Asym_Pause);
9676 if (oldadv != newadv) {
9677 phydev->advertising &=
9678 ~(ADVERTISED_Pause |
9679 ADVERTISED_Asym_Pause);
9680 phydev->advertising |= newadv;
9681 err = phy_start_aneg(phydev);
9682 }
9683 } else {
9684 tp->link_config.advertising &=
9685 ~(ADVERTISED_Pause |
9686 ADVERTISED_Asym_Pause);
9687 tp->link_config.advertising |= newadv;
9688 }
9689 } else {
9690 if (epause->rx_pause)
e18ce346 9691 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9692 else
e18ce346 9693 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
f47c11ee 9694
b02fd9e3 9695 if (epause->tx_pause)
e18ce346 9696 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9697 else
e18ce346 9698 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9699
9700 if (netif_running(dev))
9701 tg3_setup_flow_control(tp, 0, 0);
9702 }
9703 } else {
9704 int irq_sync = 0;
9705
9706 if (netif_running(dev)) {
9707 tg3_netif_stop(tp);
9708 irq_sync = 1;
9709 }
9710
9711 tg3_full_lock(tp, irq_sync);
9712
9713 if (epause->autoneg)
9714 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9715 else
9716 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9717 if (epause->rx_pause)
e18ce346 9718 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 9719 else
e18ce346 9720 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 9721 if (epause->tx_pause)
e18ce346 9722 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 9723 else
e18ce346 9724 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 9725
9726 if (netif_running(dev)) {
9727 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9728 err = tg3_restart_hw(tp, 1);
9729 if (!err)
9730 tg3_netif_start(tp);
9731 }
9732
9733 tg3_full_unlock(tp);
9734 }
6aa20a22 9735
b9ec6c1b 9736 return err;
1da177e4 9737}
6aa20a22 9738
1da177e4
LT		 9739static u32 tg3_get_rx_csum(struct net_device *dev)
9740{
9741 struct tg3 *tp = netdev_priv(dev);
9742 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9743}
6aa20a22 9744
1da177e4
LT		 9745static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9746{
9747 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9748
1da177e4
LT		 9749 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9750 if (data != 0)
9751 return -EINVAL;
9752 return 0;
9753 }
6aa20a22 9754
f47c11ee 9755 spin_lock_bh(&tp->lock);
1da177e4
LT		 9756 if (data)
9757 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9758 else
9759 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 9760 spin_unlock_bh(&tp->lock);
6aa20a22 9761
1da177e4
LT		 9762 return 0;
9763}
6aa20a22 9764
1da177e4
LT		 9765static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9766{
9767 struct tg3 *tp = netdev_priv(dev);
6aa20a22 9768
1da177e4
LT		 9769 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9770 if (data != 0)
9771 return -EINVAL;
9772 return 0;
9773 }
6aa20a22 9774
321d32a0 9775 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
6460d948 9776 ethtool_op_set_tx_ipv6_csum(dev, data);
1da177e4 9777 else
9c27dbdf 9778 ethtool_op_set_tx_csum(dev, data);
1da177e4
LT		 9779
9780 return 0;
9781}
9782
b9f2c044 9783static int tg3_get_sset_count (struct net_device *dev, int sset)
1da177e4 9784{
b9f2c044
JG		 9785 switch (sset) {
9786 case ETH_SS_TEST:
9787 return TG3_NUM_TEST;
9788 case ETH_SS_STATS:
9789 return TG3_NUM_STATS;
9790 default:
9791 return -EOPNOTSUPP;
9792 }
4cafd3f5
MC		 9793}
9794
1da177e4
LT		 9795static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9796{
9797 switch (stringset) {
9798 case ETH_SS_STATS:
9799 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9800 break;
4cafd3f5
MC		 9801 case ETH_SS_TEST:
9802 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9803 break;
1da177e4
LT		 9804 default:
9805 WARN_ON(1); /* we need a WARN() */
9806 break;
9807 }
9808}
9809
4009a93d
MC		 9810static int tg3_phys_id(struct net_device *dev, u32 data)
9811{
9812 struct tg3 *tp = netdev_priv(dev);
9813 int i;
9814
9815 if (!netif_running(tp->dev))
9816 return -EAGAIN;
9817
9818 if (data == 0)
759afc31 9819 data = UINT_MAX / 2;
4009a93d
MC		 9820
9821 for (i = 0; i < (data * 2); i++) {
9822 if ((i % 2) == 0)
9823 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9824 LED_CTRL_1000MBPS_ON |
9825 LED_CTRL_100MBPS_ON |
9826 LED_CTRL_10MBPS_ON |
9827 LED_CTRL_TRAFFIC_OVERRIDE |
9828 LED_CTRL_TRAFFIC_BLINK |
9829 LED_CTRL_TRAFFIC_LED);
6aa20a22 9830
4009a93d
MC		 9831 else
9832 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9833 LED_CTRL_TRAFFIC_OVERRIDE);
9834
9835 if (msleep_interruptible(500))
9836 break;
9837 }
9838 tw32(MAC_LED_CTRL, tp->led_ctrl);
9839 return 0;
9840}
9841
1da177e4
LT		 9842static void tg3_get_ethtool_stats (struct net_device *dev,
9843 struct ethtool_stats *estats, u64 *tmp_stats)
9844{
9845 struct tg3 *tp = netdev_priv(dev);
9846 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9847}
9848
566f86ad 9849#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 9850#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9851#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9852#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
b16250e3
MC		 9853#define NVRAM_SELFBOOT_HW_SIZE 0x20
9854#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 9855
9856static int tg3_test_nvram(struct tg3 *tp)
9857{
b9fc7dc5 9858 u32 csum, magic;
a9dc529d 9859 __be32 *buf;
ab0049b4 9860 int i, j, k, err = 0, size;
566f86ad 9861
df259d8c
MC		 9862 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9863 return 0;
9864
e4f34110 9865 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 9866 return -EIO;
9867
1b27777a
MC		 9868 if (magic == TG3_EEPROM_MAGIC)
9869 size = NVRAM_TEST_SIZE;
b16250e3 9870 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 9871 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9872 TG3_EEPROM_SB_FORMAT_1) {
9873 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9874 case TG3_EEPROM_SB_REVISION_0:
9875 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9876 break;
9877 case TG3_EEPROM_SB_REVISION_2:
9878 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9879 break;
9880 case TG3_EEPROM_SB_REVISION_3:
9881 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9882 break;
9883 default:
9884 return 0;
9885 }
9886 } else
1b27777a 9887 return 0;
b16250e3
MC		 9888 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9889 size = NVRAM_SELFBOOT_HW_SIZE;
9890 else
1b27777a
MC		 9891 return -EIO;
9892
9893 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 9894 if (buf == NULL)
9895 return -ENOMEM;
9896
1b27777a
MC		 9897 err = -EIO;
9898 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 9899 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9900 if (err)
566f86ad 9901 break;
566f86ad 9902 }
1b27777a 9903 if (i < size)
566f86ad
MC		 9904 goto out;
9905
1b27777a 9906 /* Selfboot format */
a9dc529d 9907 magic = be32_to_cpu(buf[0]);
b9fc7dc5 9908 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 9909 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 9910 u8 *buf8 = (u8 *) buf, csum8 = 0;
9911
b9fc7dc5 9912 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 9913 TG3_EEPROM_SB_REVISION_2) {
9914 /* For rev 2, the csum doesn't include the MBA. */
9915 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9916 csum8 += buf8[i];
9917 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9918 csum8 += buf8[i];
9919 } else {
9920 for (i = 0; i < size; i++)
9921 csum8 += buf8[i];
9922 }
1b27777a 9923
ad96b485
AB		 9924 if (csum8 == 0) {
9925 err = 0;
9926 goto out;
9927 }
9928
9929 err = -EIO;
9930 goto out;
1b27777a 9931 }
566f86ad 9932
b9fc7dc5 9933 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 9934 TG3_EEPROM_MAGIC_HW) {
9935 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 9936 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 9937 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 9938
9939 /* Separate the parity bits and the data bytes. */
9940 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9941 if ((i == 0) || (i == 8)) {
9942 int l;
9943 u8 msk;
9944
9945 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9946 parity[k++] = buf8[i] & msk;
9947 i++;
9948 }
9949 else if (i == 16) {
9950 int l;
9951 u8 msk;
9952
9953 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9954 parity[k++] = buf8[i] & msk;
9955 i++;
9956
9957 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9958 parity[k++] = buf8[i] & msk;
9959 i++;
9960 }
9961 data[j++] = buf8[i];
9962 }
9963
9964 err = -EIO;
9965 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9966 u8 hw8 = hweight8(data[i]);
9967
9968 if ((hw8 & 0x1) && parity[i])
9969 goto out;
9970 else if (!(hw8 & 0x1) && !parity[i])
9971 goto out;
9972 }
9973 err = 0;
9974 goto out;
9975 }
9976
566f86ad
MC		 9977 /* Bootstrap checksum at offset 0x10 */
9978 csum = calc_crc((unsigned char *) buf, 0x10);
a9dc529d 9979 if (csum != be32_to_cpu(buf[0x10/4]))
566f86ad
MC		 9980 goto out;
9981
9982 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9983 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
a9dc529d
MC		 9984 if (csum != be32_to_cpu(buf[0xfc/4]))
9985 goto out;
566f86ad
MC		 9986
9987 err = 0;
9988
9989out:
9990 kfree(buf);
9991 return err;
9992}
9993
ca43007a
MC		 9994#define TG3_SERDES_TIMEOUT_SEC 2
9995#define TG3_COPPER_TIMEOUT_SEC 6
9996
9997static int tg3_test_link(struct tg3 *tp)
9998{
9999 int i, max;
10000
10001 if (!netif_running(tp->dev))
10002 return -ENODEV;
10003
4c987487 10004 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
ca43007a
MC		 10005 max = TG3_SERDES_TIMEOUT_SEC;
10006 else
10007 max = TG3_COPPER_TIMEOUT_SEC;
10008
10009 for (i = 0; i < max; i++) {
10010 if (netif_carrier_ok(tp->dev))
10011 return 0;
10012
10013 if (msleep_interruptible(1000))
10014 break;
10015 }
10016
10017 return -EIO;
10018}
10019
a71116d1 10020/* Only test the commonly used registers */
30ca3e37 10021static int tg3_test_registers(struct tg3 *tp)
a71116d1 10022{
b16250e3 10023 int i, is_5705, is_5750;
a71116d1
MC		 10024 u32 offset, read_mask, write_mask, val, save_val, read_val;
10025 static struct {
10026 u16 offset;
10027 u16 flags;
10028#define TG3_FL_5705 0x1
10029#define TG3_FL_NOT_5705 0x2
10030#define TG3_FL_NOT_5788 0x4
b16250e3 10031#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 10032 u32 read_mask;
10033 u32 write_mask;
10034 } reg_tbl[] = {
10035 /* MAC Control Registers */
10036 { MAC_MODE, TG3_FL_NOT_5705,
10037 0x00000000, 0x00ef6f8c },
10038 { MAC_MODE, TG3_FL_5705,
10039 0x00000000, 0x01ef6b8c },
10040 { MAC_STATUS, TG3_FL_NOT_5705,
10041 0x03800107, 0x00000000 },
10042 { MAC_STATUS, TG3_FL_5705,
10043 0x03800100, 0x00000000 },
10044 { MAC_ADDR_0_HIGH, 0x0000,
10045 0x00000000, 0x0000ffff },
10046 { MAC_ADDR_0_LOW, 0x0000,
10047 0x00000000, 0xffffffff },
10048 { MAC_RX_MTU_SIZE, 0x0000,
10049 0x00000000, 0x0000ffff },
10050 { MAC_TX_MODE, 0x0000,
10051 0x00000000, 0x00000070 },
10052 { MAC_TX_LENGTHS, 0x0000,
10053 0x00000000, 0x00003fff },
10054 { MAC_RX_MODE, TG3_FL_NOT_5705,
10055 0x00000000, 0x000007fc },
10056 { MAC_RX_MODE, TG3_FL_5705,
10057 0x00000000, 0x000007dc },
10058 { MAC_HASH_REG_0, 0x0000,
10059 0x00000000, 0xffffffff },
10060 { MAC_HASH_REG_1, 0x0000,
10061 0x00000000, 0xffffffff },
10062 { MAC_HASH_REG_2, 0x0000,
10063 0x00000000, 0xffffffff },
10064 { MAC_HASH_REG_3, 0x0000,
10065 0x00000000, 0xffffffff },
10066
10067 /* Receive Data and Receive BD Initiator Control Registers. */
10068 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10069 0x00000000, 0xffffffff },
10070 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10071 0x00000000, 0xffffffff },
10072 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10073 0x00000000, 0x00000003 },
10074 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10075 0x00000000, 0xffffffff },
10076 { RCVDBDI_STD_BD+0, 0x0000,
10077 0x00000000, 0xffffffff },
10078 { RCVDBDI_STD_BD+4, 0x0000,
10079 0x00000000, 0xffffffff },
10080 { RCVDBDI_STD_BD+8, 0x0000,
10081 0x00000000, 0xffff0002 },
10082 { RCVDBDI_STD_BD+0xc, 0x0000,
10083 0x00000000, 0xffffffff },
6aa20a22 10084
a71116d1
MC		 10085 /* Receive BD Initiator Control Registers. */
10086 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10087 0x00000000, 0xffffffff },
10088 { RCVBDI_STD_THRESH, TG3_FL_5705,
10089 0x00000000, 0x000003ff },
10090 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10091 0x00000000, 0xffffffff },
6aa20a22 10092
a71116d1
MC		 10093 /* Host Coalescing Control Registers. */
10094 { HOSTCC_MODE, TG3_FL_NOT_5705,
10095 0x00000000, 0x00000004 },
10096 { HOSTCC_MODE, TG3_FL_5705,
10097 0x00000000, 0x000000f6 },
10098 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10099 0x00000000, 0xffffffff },
10100 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10101 0x00000000, 0x000003ff },
10102 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10103 0x00000000, 0xffffffff },
10104 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10105 0x00000000, 0x000003ff },
10106 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10107 0x00000000, 0xffffffff },
10108 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10109 0x00000000, 0x000000ff },
10110 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10111 0x00000000, 0xffffffff },
10112 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10113 0x00000000, 0x000000ff },
10114 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10115 0x00000000, 0xffffffff },
10116 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10117 0x00000000, 0xffffffff },
10118 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10119 0x00000000, 0xffffffff },
10120 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10121 0x00000000, 0x000000ff },
10122 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10123 0x00000000, 0xffffffff },
10124 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10125 0x00000000, 0x000000ff },
10126 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10127 0x00000000, 0xffffffff },
10128 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10129 0x00000000, 0xffffffff },
10130 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10131 0x00000000, 0xffffffff },
10132 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10133 0x00000000, 0xffffffff },
10134 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10135 0x00000000, 0xffffffff },
10136 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10137 0xffffffff, 0x00000000 },
10138 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10139 0xffffffff, 0x00000000 },
10140
10141 /* Buffer Manager Control Registers. */
b16250e3 10142 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 10143 0x00000000, 0x007fff80 },
b16250e3 10144 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 10145 0x00000000, 0x007fffff },
10146 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10147 0x00000000, 0x0000003f },
10148 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10149 0x00000000, 0x000001ff },
10150 { BUFMGR_MB_HIGH_WATER, 0x0000,
10151 0x00000000, 0x000001ff },
10152 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10153 0xffffffff, 0x00000000 },
10154 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10155 0xffffffff, 0x00000000 },
6aa20a22 10156
a71116d1
MC		 10157 /* Mailbox Registers */
10158 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10159 0x00000000, 0x000001ff },
10160 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10161 0x00000000, 0x000001ff },
10162 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10163 0x00000000, 0x000007ff },
10164 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10165 0x00000000, 0x000001ff },
10166
10167 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10168 };
10169
b16250e3
MC		 10170 is_5705 = is_5750 = 0;
10171 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
a71116d1 10172 is_5705 = 1;
b16250e3
MC		 10173 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10174 is_5750 = 1;
10175 }
a71116d1
MC		 10176
10177 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10178 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10179 continue;
10180
10181 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10182 continue;
10183
10184 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10185 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10186 continue;
10187
b16250e3
MC		 10188 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10189 continue;
10190
a71116d1
MC		 10191 offset = (u32) reg_tbl[i].offset;
10192 read_mask = reg_tbl[i].read_mask;
10193 write_mask = reg_tbl[i].write_mask;
10194
10195 /* Save the original register content */
10196 save_val = tr32(offset);
10197
10198 /* Determine the read-only value. */
10199 read_val = save_val & read_mask;
10200
10201 /* Write zero to the register, then make sure the read-only bits
10202 * are not changed and the read/write bits are all zeros.
10203 */
10204 tw32(offset, 0);
10205
10206 val = tr32(offset);
10207
10208 /* Test the read-only and read/write bits. */
10209 if (((val & read_mask) != read_val) || (val & write_mask))
10210 goto out;
10211
10212 /* Write ones to all the bits defined by RdMask and WrMask, then
10213 * make sure the read-only bits are not changed and the
10214 * read/write bits are all ones.
10215 */
10216 tw32(offset, read_mask | write_mask);
10217
10218 val = tr32(offset);
10219
10220 /* Test the read-only bits. */
10221 if ((val & read_mask) != read_val)
10222 goto out;
10223
10224 /* Test the read/write bits. */
10225 if ((val & write_mask) != write_mask)
10226 goto out;
10227
10228 tw32(offset, save_val);
10229 }
10230
10231 return 0;
10232
10233out:
9f88f29f
MC		 10234 if (netif_msg_hw(tp))
10235 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10236 offset);
a71116d1
MC		 10237 tw32(offset, save_val);
10238 return -EIO;
10239}
10240
7942e1db
MC		 10241static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10242{
f71e1309 10243 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 10244 int i;
10245 u32 j;
10246
e9edda69 10247 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 10248 for (j = 0; j < len; j += 4) {
10249 u32 val;
10250
10251 tg3_write_mem(tp, offset + j, test_pattern[i]);
10252 tg3_read_mem(tp, offset + j, &val);
10253 if (val != test_pattern[i])
10254 return -EIO;
10255 }
10256 }
10257 return 0;
10258}
10259
10260static int tg3_test_memory(struct tg3 *tp)
10261{
10262 static struct mem_entry {
10263 u32 offset;
10264 u32 len;
10265 } mem_tbl_570x[] = {
38690194 10266 { 0x00000000, 0x00b50},
7942e1db
MC		 10267 { 0x00002000, 0x1c000},
10268 { 0xffffffff, 0x00000}
10269 }, mem_tbl_5705[] = {
10270 { 0x00000100, 0x0000c},
10271 { 0x00000200, 0x00008},
7942e1db
MC		 10272 { 0x00004000, 0x00800},
10273 { 0x00006000, 0x01000},
10274 { 0x00008000, 0x02000},
10275 { 0x00010000, 0x0e000},
10276 { 0xffffffff, 0x00000}
79f4d13a
MC		 10277 }, mem_tbl_5755[] = {
10278 { 0x00000200, 0x00008},
10279 { 0x00004000, 0x00800},
10280 { 0x00006000, 0x00800},
10281 { 0x00008000, 0x02000},
10282 { 0x00010000, 0x0c000},
10283 { 0xffffffff, 0x00000}
b16250e3
MC		 10284 }, mem_tbl_5906[] = {
10285 { 0x00000200, 0x00008},
10286 { 0x00004000, 0x00400},
10287 { 0x00006000, 0x00400},
10288 { 0x00008000, 0x01000},
10289 { 0x00010000, 0x01000},
10290 { 0xffffffff, 0x00000}
7942e1db
MC		 10291 };
10292 struct mem_entry *mem_tbl;
10293 int err = 0;
10294 int i;
10295
321d32a0
MC		 10296 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10297 mem_tbl = mem_tbl_5755;
10298 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10299 mem_tbl = mem_tbl_5906;
10300 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10301 mem_tbl = mem_tbl_5705;
10302 else
7942e1db
MC		 10303 mem_tbl = mem_tbl_570x;
10304
10305 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10306 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10307 mem_tbl[i].len)) != 0)
10308 break;
10309 }
6aa20a22 10310
7942e1db
MC		 10311 return err;
10312}
10313
9f40dead
MC		 10314#define TG3_MAC_LOOPBACK 0
10315#define TG3_PHY_LOOPBACK 1
10316
10317static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
c76949a6 10318{
9f40dead 10319 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
fd2ce37f 10320 u32 desc_idx, coal_now;
c76949a6
MC		 10321 struct sk_buff *skb, *rx_skb;
10322 u8 *tx_data;
10323 dma_addr_t map;
10324 int num_pkts, tx_len, rx_len, i, err;
10325 struct tg3_rx_buffer_desc *desc;
898a56f8 10326 struct tg3_napi *tnapi, *rnapi;
21f581a5 10327 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
c76949a6 10328
0c1d0e2b
MC		 10329 if (tp->irq_cnt > 1) {
10330 tnapi = &tp->napi[1];
10331 rnapi = &tp->napi[1];
10332 } else {
10333 tnapi = &tp->napi[0];
10334 rnapi = &tp->napi[0];
10335 }
fd2ce37f 10336 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 10337
9f40dead 10338 if (loopback_mode == TG3_MAC_LOOPBACK) {
c94e3941
MC		 10339 /* HW errata - mac loopback fails in some cases on 5780.
10340 * Normal traffic and PHY loopback are not affected by
10341 * errata.
10342 */
10343 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10344 return 0;
10345
9f40dead 10346 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
e8f3f6ca
MC		 10347 MAC_MODE_PORT_INT_LPBACK;
10348 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10349 mac_mode |= MAC_MODE_LINK_POLARITY;
3f7045c1
MC		 10350 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10351 mac_mode |= MAC_MODE_PORT_MODE_MII;
10352 else
10353 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9f40dead
MC		 10354 tw32(MAC_MODE, mac_mode);
10355 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
3f7045c1
MC		 10356 u32 val;
10357
7f97a4bd
MC		 10358 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10359 tg3_phy_fet_toggle_apd(tp, false);
5d64ad34
MC		 10360 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10361 } else
10362 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
3f7045c1 10363
9ef8ca99
MC		 10364 tg3_phy_toggle_automdix(tp, 0);
10365
3f7045c1 10366 tg3_writephy(tp, MII_BMCR, val);
c94e3941 10367 udelay(40);
5d64ad34 10368
e8f3f6ca 10369 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
7f97a4bd
MC		 10370 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10372 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
5d64ad34
MC		 10373 mac_mode |= MAC_MODE_PORT_MODE_MII;
10374 } else
10375 mac_mode |= MAC_MODE_PORT_MODE_GMII;
b16250e3 10376
c94e3941
MC		 10377 /* reset to prevent losing 1st rx packet intermittently */
10378 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10379 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10380 udelay(10);
10381 tw32_f(MAC_RX_MODE, tp->rx_mode);
10382 }
e8f3f6ca
MC		 10383 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10384 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10385 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10386 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10387 mac_mode |= MAC_MODE_LINK_POLARITY;
ff18ff02
MC		 10388 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10389 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10390 }
9f40dead 10391 tw32(MAC_MODE, mac_mode);
9f40dead
MC		 10392 }
10393 else
10394 return -EINVAL;
c76949a6
MC		 10395
10396 err = -EIO;
10397
c76949a6 10398 tx_len = 1514;
a20e9c62 10399 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 10400 if (!skb)
10401 return -ENOMEM;
10402
c76949a6
MC		 10403 tx_data = skb_put(skb, tx_len);
10404 memcpy(tx_data, tp->dev->dev_addr, 6);
10405 memset(tx_data + 6, 0x0, 8);
10406
10407 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10408
10409 for (i = 14; i < tx_len; i++)
10410 tx_data[i] = (u8) (i & 0xff);
10411
a21771dd
MC		 10412 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10413 dev_kfree_skb(skb);
10414 return -EIO;
10415 }
c76949a6
MC		 10416
10417 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10418 rnapi->coal_now);
c76949a6
MC		 10419
10420 udelay(10);
10421
898a56f8 10422 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 10423
c76949a6
MC		 10424 num_pkts = 0;
10425
a21771dd
MC		 10426 tg3_set_txd(tnapi, tnapi->tx_prod,
10427 skb_shinfo(skb)->dma_head, tx_len, 0, 1);
c76949a6 10428
f3f3f27e 10429 tnapi->tx_prod++;
c76949a6
MC		 10430 num_pkts++;
10431
f3f3f27e
MC		 10432 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10433 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 10434
10435 udelay(10);
10436
303fc921
MC		 10437 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10438 for (i = 0; i < 35; i++) {
c76949a6 10439 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 10440 coal_now);
c76949a6
MC		 10441
10442 udelay(10);
10443
898a56f8
MC		 10444 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10445 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 10446 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 10447 (rx_idx == (rx_start_idx + num_pkts)))
10448 break;
10449 }
10450
a21771dd 10451 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
c76949a6
MC		 10452 dev_kfree_skb(skb);
10453
f3f3f27e 10454 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 10455 goto out;
10456
10457 if (rx_idx != rx_start_idx + num_pkts)
10458 goto out;
10459
72334482 10460 desc = &rnapi->rx_rcb[rx_start_idx];
c76949a6
MC		 10461 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10462 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10463 if (opaque_key != RXD_OPAQUE_RING_STD)
10464 goto out;
10465
10466 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10467 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10468 goto out;
10469
10470 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10471 if (rx_len != tx_len)
10472 goto out;
10473
21f581a5 10474 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
c76949a6 10475
21f581a5 10476 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
c76949a6
MC		 10477 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10478
10479 for (i = 14; i < tx_len; i++) {
10480 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10481 goto out;
10482 }
10483 err = 0;
6aa20a22 10484
c76949a6
MC		 10485 /* tg3_free_rings will unmap and free the rx_skb */
10486out:
10487 return err;
10488}
10489
9f40dead
MC		 10490#define TG3_MAC_LOOPBACK_FAILED 1
10491#define TG3_PHY_LOOPBACK_FAILED 2
10492#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10493 TG3_PHY_LOOPBACK_FAILED)
10494
10495static int tg3_test_loopback(struct tg3 *tp)
10496{
10497 int err = 0;
9936bcf6 10498 u32 cpmuctrl = 0;
9f40dead
MC		 10499
10500 if (!netif_running(tp->dev))
10501 return TG3_LOOPBACK_FAILED;
10502
b9ec6c1b
MC		 10503 err = tg3_reset_hw(tp, 1);
10504 if (err)
10505 return TG3_LOOPBACK_FAILED;
9f40dead 10506
6833c043
MC		 10507 /* Turn off gphy autopowerdown. */
10508 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10509 tg3_phy_toggle_apd(tp, false);
10510
321d32a0 10511 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10512 int i;
10513 u32 status;
10514
10515 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10516
10517 /* Wait for up to 40 microseconds to acquire lock. */
10518 for (i = 0; i < 4; i++) {
10519 status = tr32(TG3_CPMU_MUTEX_GNT);
10520 if (status == CPMU_MUTEX_GNT_DRIVER)
10521 break;
10522 udelay(10);
10523 }
10524
10525 if (status != CPMU_MUTEX_GNT_DRIVER)
10526 return TG3_LOOPBACK_FAILED;
10527
b2a5c19c 10528 /* Turn off link-based power management. */
e875093c 10529 cpmuctrl = tr32(TG3_CPMU_CTRL);
109115e1
MC		 10530 tw32(TG3_CPMU_CTRL,
10531 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10532 CPMU_CTRL_LINK_AWARE_MODE));
9936bcf6
MC		 10533 }
10534
9f40dead
MC		 10535 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10536 err |= TG3_MAC_LOOPBACK_FAILED;
9936bcf6 10537
321d32a0 10538 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9936bcf6
MC		 10539 tw32(TG3_CPMU_CTRL, cpmuctrl);
10540
10541 /* Release the mutex */
10542 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10543 }
10544
dd477003
MC		 10545 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10546 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9f40dead
MC		 10547 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10548 err |= TG3_PHY_LOOPBACK_FAILED;
10549 }
10550
6833c043
MC		 10551 /* Re-enable gphy autopowerdown. */
10552 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10553 tg3_phy_toggle_apd(tp, true);
10554
9f40dead
MC		 10555 return err;
10556}
10557
4cafd3f5
MC		 10558static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10559 u64 *data)
10560{
566f86ad
MC		 10561 struct tg3 *tp = netdev_priv(dev);
10562
bc1c7567
MC		 10563 if (tp->link_config.phy_is_low_power)
10564 tg3_set_power_state(tp, PCI_D0);
10565
566f86ad
MC		 10566 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10567
10568 if (tg3_test_nvram(tp) != 0) {
10569 etest->flags |= ETH_TEST_FL_FAILED;
10570 data[0] = 1;
10571 }
ca43007a
MC		 10572 if (tg3_test_link(tp) != 0) {
10573 etest->flags |= ETH_TEST_FL_FAILED;
10574 data[1] = 1;
10575 }
a71116d1 10576 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 10577 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 10578
10579 if (netif_running(dev)) {
b02fd9e3 10580 tg3_phy_stop(tp);
a71116d1 10581 tg3_netif_stop(tp);
bbe832c0
MC		 10582 irq_sync = 1;
10583 }
a71116d1 10584
bbe832c0 10585 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 10586
10587 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 10588 err = tg3_nvram_lock(tp);
a71116d1
MC		 10589 tg3_halt_cpu(tp, RX_CPU_BASE);
10590 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10591 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 10592 if (!err)
10593 tg3_nvram_unlock(tp);
a71116d1 10594
d9ab5ad1
MC		 10595 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10596 tg3_phy_reset(tp);
10597
a71116d1
MC		 10598 if (tg3_test_registers(tp) != 0) {
10599 etest->flags |= ETH_TEST_FL_FAILED;
10600 data[2] = 1;
10601 }
7942e1db
MC		 10602 if (tg3_test_memory(tp) != 0) {
10603 etest->flags |= ETH_TEST_FL_FAILED;
10604 data[3] = 1;
10605 }
9f40dead 10606 if ((data[4] = tg3_test_loopback(tp)) != 0)
c76949a6 10607 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 10608
f47c11ee
DM		 10609 tg3_full_unlock(tp);
10610
d4bc3927
MC		 10611 if (tg3_test_interrupt(tp) != 0) {
10612 etest->flags |= ETH_TEST_FL_FAILED;
10613 data[5] = 1;
10614 }
f47c11ee
DM		 10615
10616 tg3_full_lock(tp, 0);
d4bc3927 10617
a71116d1
MC		 10618 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10619 if (netif_running(dev)) {
10620 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 10621 err2 = tg3_restart_hw(tp, 1);
10622 if (!err2)
b9ec6c1b 10623 tg3_netif_start(tp);
a71116d1 10624 }
f47c11ee
DM		 10625
10626 tg3_full_unlock(tp);
b02fd9e3
MC		 10627
10628 if (irq_sync && !err2)
10629 tg3_phy_start(tp);
a71116d1 10630 }
bc1c7567
MC		 10631 if (tp->link_config.phy_is_low_power)
10632 tg3_set_power_state(tp, PCI_D3hot);
10633
4cafd3f5
MC		 10634}
10635
1da177e4
LT		 10636static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10637{
10638 struct mii_ioctl_data *data = if_mii(ifr);
10639 struct tg3 *tp = netdev_priv(dev);
10640 int err;
10641
b02fd9e3 10642 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
3f0e3ad7 10643 struct phy_device *phydev;
b02fd9e3
MC		 10644 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10645 return -EAGAIN;
3f0e3ad7
MC		 10646 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10647 return phy_mii_ioctl(phydev, data, cmd);
b02fd9e3
MC		 10648 }
10649
1da177e4
LT		 10650 switch(cmd) {
10651 case SIOCGMIIPHY:
882e9793 10652 data->phy_id = tp->phy_addr;
1da177e4
LT		 10653
10654 /* fallthru */
10655 case SIOCGMIIREG: {
10656 u32 mii_regval;
10657
10658 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10659 break; /* We have no PHY */
10660
bc1c7567
MC		 10661 if (tp->link_config.phy_is_low_power)
10662 return -EAGAIN;
10663
f47c11ee 10664 spin_lock_bh(&tp->lock);
1da177e4 10665 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 10666 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10667
10668 data->val_out = mii_regval;
10669
10670 return err;
10671 }
10672
10673 case SIOCSMIIREG:
10674 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10675 break; /* We have no PHY */
10676
bc1c7567
MC		 10677 if (tp->link_config.phy_is_low_power)
10678 return -EAGAIN;
10679
f47c11ee 10680 spin_lock_bh(&tp->lock);
1da177e4 10681 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 10682 spin_unlock_bh(&tp->lock);
1da177e4
LT		 10683
10684 return err;
10685
10686 default:
10687 /* do nothing */
10688 break;
10689 }
10690 return -EOPNOTSUPP;
10691}
10692
10693#if TG3_VLAN_TAG_USED
10694static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10695{
10696 struct tg3 *tp = netdev_priv(dev);
10697
844b3eed
MC		 10698 if (!netif_running(dev)) {
10699 tp->vlgrp = grp;
10700 return;
10701 }
10702
10703 tg3_netif_stop(tp);
29315e87 10704
f47c11ee 10705 tg3_full_lock(tp, 0);
1da177e4
LT		 10706
10707 tp->vlgrp = grp;
10708
10709 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10710 __tg3_set_rx_mode(dev);
10711
844b3eed 10712 tg3_netif_start(tp);
46966545
MC		 10713
10714 tg3_full_unlock(tp);
1da177e4 10715}
1da177e4
LT		 10716#endif
10717
15f9850d
DM		 10718static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10719{
10720 struct tg3 *tp = netdev_priv(dev);
10721
10722 memcpy(ec, &tp->coal, sizeof(*ec));
10723 return 0;
10724}
10725
d244c892
MC		 10726static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10727{
10728 struct tg3 *tp = netdev_priv(dev);
10729 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10730 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10731
10732 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10733 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10734 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10735 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10736 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10737 }
10738
10739 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10740 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10741 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10742 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10743 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10744 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10745 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10746 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10747 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10748 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10749 return -EINVAL;
10750
10751 /* No rx interrupts will be generated if both are zero */
10752 if ((ec->rx_coalesce_usecs == 0) &&
10753 (ec->rx_max_coalesced_frames == 0))
10754 return -EINVAL;
10755
10756 /* No tx interrupts will be generated if both are zero */
10757 if ((ec->tx_coalesce_usecs == 0) &&
10758 (ec->tx_max_coalesced_frames == 0))
10759 return -EINVAL;
10760
10761 /* Only copy relevant parameters, ignore all others. */
10762 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10763 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10764 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10765 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10766 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10767 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10768 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10769 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10770 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10771
10772 if (netif_running(dev)) {
10773 tg3_full_lock(tp, 0);
10774 __tg3_set_coalesce(tp, &tp->coal);
10775 tg3_full_unlock(tp);
10776 }
10777 return 0;
10778}
10779
7282d491 10780static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 10781 .get_settings = tg3_get_settings,
10782 .set_settings = tg3_set_settings,
10783 .get_drvinfo = tg3_get_drvinfo,
10784 .get_regs_len = tg3_get_regs_len,
10785 .get_regs = tg3_get_regs,
10786 .get_wol = tg3_get_wol,
10787 .set_wol = tg3_set_wol,
10788 .get_msglevel = tg3_get_msglevel,
10789 .set_msglevel = tg3_set_msglevel,
10790 .nway_reset = tg3_nway_reset,
10791 .get_link = ethtool_op_get_link,
10792 .get_eeprom_len = tg3_get_eeprom_len,
10793 .get_eeprom = tg3_get_eeprom,
10794 .set_eeprom = tg3_set_eeprom,
10795 .get_ringparam = tg3_get_ringparam,
10796 .set_ringparam = tg3_set_ringparam,
10797 .get_pauseparam = tg3_get_pauseparam,
10798 .set_pauseparam = tg3_set_pauseparam,
10799 .get_rx_csum = tg3_get_rx_csum,
10800 .set_rx_csum = tg3_set_rx_csum,
1da177e4 10801 .set_tx_csum = tg3_set_tx_csum,
1da177e4 10802 .set_sg = ethtool_op_set_sg,
1da177e4 10803 .set_tso = tg3_set_tso,
4cafd3f5 10804 .self_test = tg3_self_test,
1da177e4 10805 .get_strings = tg3_get_strings,
4009a93d 10806 .phys_id = tg3_phys_id,
1da177e4 10807 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 10808 .get_coalesce = tg3_get_coalesce,
d244c892 10809 .set_coalesce = tg3_set_coalesce,
b9f2c044 10810 .get_sset_count = tg3_get_sset_count,
1da177e4
LT		 10811};
10812
10813static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10814{
1b27777a 10815 u32 cursize, val, magic;
1da177e4
LT		 10816
10817 tp->nvram_size = EEPROM_CHIP_SIZE;
10818
e4f34110 10819 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 10820 return;
10821
b16250e3
MC		 10822 if ((magic != TG3_EEPROM_MAGIC) &&
10823 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10824 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 10825 return;
10826
10827 /*
10828 * Size the chip by reading offsets at increasing powers of two.
10829 * When we encounter our validation signature, we know the addressing
10830 * has wrapped around, and thus have our chip size.
10831 */
1b27777a 10832 cursize = 0x10;
1da177e4
LT		 10833
10834 while (cursize < tp->nvram_size) {
e4f34110 10835 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 10836 return;
10837
1820180b 10838 if (val == magic)
1da177e4
LT		 10839 break;
10840
10841 cursize <<= 1;
10842 }
10843
10844 tp->nvram_size = cursize;
10845}
6aa20a22 10846
1da177e4
LT		 10847static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10848{
10849 u32 val;
10850
df259d8c
MC		 10851 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10852 tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 10853 return;
10854
10855 /* Selfboot format */
1820180b 10856 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 10857 tg3_get_eeprom_size(tp);
10858 return;
10859 }
10860
6d348f2c 10861 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 10862 if (val != 0) {
6d348f2c
MC		 10863 /* This is confusing. We want to operate on the
10864 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10865 * call will read from NVRAM and byteswap the data
10866 * according to the byteswapping settings for all
10867 * other register accesses. This ensures the data we
10868 * want will always reside in the lower 16-bits.
10869 * However, the data in NVRAM is in LE format, which
10870 * means the data from the NVRAM read will always be
10871 * opposite the endianness of the CPU. The 16-bit
10872 * byteswap then brings the data to CPU endianness.
10873 */
10874 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 10875 return;
10876 }
10877 }
fd1122a2 10878 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 10879}
10880
10881static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10882{
10883 u32 nvcfg1;
10884
10885 nvcfg1 = tr32(NVRAM_CFG1);
10886 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10887 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8590a603 10888 } else {
1da177e4
LT		 10889 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10890 tw32(NVRAM_CFG1, nvcfg1);
10891 }
10892
4c987487 10893 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
a4e2b347 10894 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4 10895 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 10896 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10897 tp->nvram_jedecnum = JEDEC_ATMEL;
10898 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10899 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10900 break;
10901 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10902 tp->nvram_jedecnum = JEDEC_ATMEL;
10903 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10904 break;
10905 case FLASH_VENDOR_ATMEL_EEPROM:
10906 tp->nvram_jedecnum = JEDEC_ATMEL;
10907 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10908 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10909 break;
10910 case FLASH_VENDOR_ST:
10911 tp->nvram_jedecnum = JEDEC_ST;
10912 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10913 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10914 break;
10915 case FLASH_VENDOR_SAIFUN:
10916 tp->nvram_jedecnum = JEDEC_SAIFUN;
10917 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10918 break;
10919 case FLASH_VENDOR_SST_SMALL:
10920 case FLASH_VENDOR_SST_LARGE:
10921 tp->nvram_jedecnum = JEDEC_SST;
10922 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10923 break;
1da177e4 10924 }
8590a603 10925 } else {
1da177e4
LT		 10926 tp->nvram_jedecnum = JEDEC_ATMEL;
10927 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10928 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10929 }
10930}
10931
a1b950d5
MC		 10932static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10933{
10934 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10935 case FLASH_5752PAGE_SIZE_256:
10936 tp->nvram_pagesize = 256;
10937 break;
10938 case FLASH_5752PAGE_SIZE_512:
10939 tp->nvram_pagesize = 512;
10940 break;
10941 case FLASH_5752PAGE_SIZE_1K:
10942 tp->nvram_pagesize = 1024;
10943 break;
10944 case FLASH_5752PAGE_SIZE_2K:
10945 tp->nvram_pagesize = 2048;
10946 break;
10947 case FLASH_5752PAGE_SIZE_4K:
10948 tp->nvram_pagesize = 4096;
10949 break;
10950 case FLASH_5752PAGE_SIZE_264:
10951 tp->nvram_pagesize = 264;
10952 break;
10953 case FLASH_5752PAGE_SIZE_528:
10954 tp->nvram_pagesize = 528;
10955 break;
10956 }
10957}
10958
361b4ac2
MC		 10959static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10960{
10961 u32 nvcfg1;
10962
10963 nvcfg1 = tr32(NVRAM_CFG1);
10964
e6af301b
MC		 10965 /* NVRAM protection for TPM */
10966 if (nvcfg1 & (1 << 27))
10967 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10968
361b4ac2 10969 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 10970 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10971 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10972 tp->nvram_jedecnum = JEDEC_ATMEL;
10973 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10974 break;
10975 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10976 tp->nvram_jedecnum = JEDEC_ATMEL;
10977 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10978 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10979 break;
10980 case FLASH_5752VENDOR_ST_M45PE10:
10981 case FLASH_5752VENDOR_ST_M45PE20:
10982 case FLASH_5752VENDOR_ST_M45PE40:
10983 tp->nvram_jedecnum = JEDEC_ST;
10984 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10985 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10986 break;
361b4ac2
MC		 10987 }
10988
10989 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
a1b950d5 10990 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 10991 } else {
361b4ac2
MC		 10992 /* For eeprom, set pagesize to maximum eeprom size */
10993 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10994
10995 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10996 tw32(NVRAM_CFG1, nvcfg1);
10997 }
10998}
10999
d3c7b886
MC		 11000static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11001{
989a9d23 11002 u32 nvcfg1, protect = 0;
d3c7b886
MC		 11003
11004 nvcfg1 = tr32(NVRAM_CFG1);
11005
11006 /* NVRAM protection for TPM */
989a9d23 11007 if (nvcfg1 & (1 << 27)) {
d3c7b886 11008 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
989a9d23
MC		 11009 protect = 1;
11010 }
d3c7b886 11011
989a9d23
MC		 11012 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11013 switch (nvcfg1) {
8590a603
MC		 11014 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11015 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11016 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11017 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11018 tp->nvram_jedecnum = JEDEC_ATMEL;
11019 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11020 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11021 tp->nvram_pagesize = 264;
11022 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11023 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11024 tp->nvram_size = (protect ? 0x3e200 :
11025 TG3_NVRAM_SIZE_512KB);
11026 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11027 tp->nvram_size = (protect ? 0x1f200 :
11028 TG3_NVRAM_SIZE_256KB);
11029 else
11030 tp->nvram_size = (protect ? 0x1f200 :
11031 TG3_NVRAM_SIZE_128KB);
11032 break;
11033 case FLASH_5752VENDOR_ST_M45PE10:
11034 case FLASH_5752VENDOR_ST_M45PE20:
11035 case FLASH_5752VENDOR_ST_M45PE40:
11036 tp->nvram_jedecnum = JEDEC_ST;
11037 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11038 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11039 tp->nvram_pagesize = 256;
11040 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11041 tp->nvram_size = (protect ?
11042 TG3_NVRAM_SIZE_64KB :
11043 TG3_NVRAM_SIZE_128KB);
11044 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11045 tp->nvram_size = (protect ?
11046 TG3_NVRAM_SIZE_64KB :
11047 TG3_NVRAM_SIZE_256KB);
11048 else
11049 tp->nvram_size = (protect ?
11050 TG3_NVRAM_SIZE_128KB :
11051 TG3_NVRAM_SIZE_512KB);
11052 break;
d3c7b886
MC		 11053 }
11054}
11055
1b27777a
MC		 11056static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11057{
11058 u32 nvcfg1;
11059
11060 nvcfg1 = tr32(NVRAM_CFG1);
11061
11062 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 11063 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11064 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11065 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11066 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11067 tp->nvram_jedecnum = JEDEC_ATMEL;
11068 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11069 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 11070
8590a603
MC		 11071 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11072 tw32(NVRAM_CFG1, nvcfg1);
11073 break;
11074 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11075 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11076 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11077 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11078 tp->nvram_jedecnum = JEDEC_ATMEL;
11079 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11080 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11081 tp->nvram_pagesize = 264;
11082 break;
11083 case FLASH_5752VENDOR_ST_M45PE10:
11084 case FLASH_5752VENDOR_ST_M45PE20:
11085 case FLASH_5752VENDOR_ST_M45PE40:
11086 tp->nvram_jedecnum = JEDEC_ST;
11087 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11088 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11089 tp->nvram_pagesize = 256;
11090 break;
1b27777a
MC		 11091 }
11092}
11093
6b91fa02
MC		 11094static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11095{
11096 u32 nvcfg1, protect = 0;
11097
11098 nvcfg1 = tr32(NVRAM_CFG1);
11099
11100 /* NVRAM protection for TPM */
11101 if (nvcfg1 & (1 << 27)) {
11102 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11103 protect = 1;
11104 }
11105
11106 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11107 switch (nvcfg1) {
8590a603
MC		 11108 case FLASH_5761VENDOR_ATMEL_ADB021D:
11109 case FLASH_5761VENDOR_ATMEL_ADB041D:
11110 case FLASH_5761VENDOR_ATMEL_ADB081D:
11111 case FLASH_5761VENDOR_ATMEL_ADB161D:
11112 case FLASH_5761VENDOR_ATMEL_MDB021D:
11113 case FLASH_5761VENDOR_ATMEL_MDB041D:
11114 case FLASH_5761VENDOR_ATMEL_MDB081D:
11115 case FLASH_5761VENDOR_ATMEL_MDB161D:
11116 tp->nvram_jedecnum = JEDEC_ATMEL;
11117 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11118 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11119 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11120 tp->nvram_pagesize = 256;
11121 break;
11122 case FLASH_5761VENDOR_ST_A_M45PE20:
11123 case FLASH_5761VENDOR_ST_A_M45PE40:
11124 case FLASH_5761VENDOR_ST_A_M45PE80:
11125 case FLASH_5761VENDOR_ST_A_M45PE16:
11126 case FLASH_5761VENDOR_ST_M_M45PE20:
11127 case FLASH_5761VENDOR_ST_M_M45PE40:
11128 case FLASH_5761VENDOR_ST_M_M45PE80:
11129 case FLASH_5761VENDOR_ST_M_M45PE16:
11130 tp->nvram_jedecnum = JEDEC_ST;
11131 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11132 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11133 tp->nvram_pagesize = 256;
11134 break;
6b91fa02
MC		 11135 }
11136
11137 if (protect) {
11138 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11139 } else {
11140 switch (nvcfg1) {
8590a603
MC		 11141 case FLASH_5761VENDOR_ATMEL_ADB161D:
11142 case FLASH_5761VENDOR_ATMEL_MDB161D:
11143 case FLASH_5761VENDOR_ST_A_M45PE16:
11144 case FLASH_5761VENDOR_ST_M_M45PE16:
11145 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11146 break;
11147 case FLASH_5761VENDOR_ATMEL_ADB081D:
11148 case FLASH_5761VENDOR_ATMEL_MDB081D:
11149 case FLASH_5761VENDOR_ST_A_M45PE80:
11150 case FLASH_5761VENDOR_ST_M_M45PE80:
11151 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11152 break;
11153 case FLASH_5761VENDOR_ATMEL_ADB041D:
11154 case FLASH_5761VENDOR_ATMEL_MDB041D:
11155 case FLASH_5761VENDOR_ST_A_M45PE40:
11156 case FLASH_5761VENDOR_ST_M_M45PE40:
11157 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11158 break;
11159 case FLASH_5761VENDOR_ATMEL_ADB021D:
11160 case FLASH_5761VENDOR_ATMEL_MDB021D:
11161 case FLASH_5761VENDOR_ST_A_M45PE20:
11162 case FLASH_5761VENDOR_ST_M_M45PE20:
11163 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11164 break;
6b91fa02
MC		 11165 }
11166 }
11167}
11168
b5d3772c
MC		 11169static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11170{
11171 tp->nvram_jedecnum = JEDEC_ATMEL;
11172 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11173 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11174}
11175
321d32a0
MC		 11176static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11177{
11178 u32 nvcfg1;
11179
11180 nvcfg1 = tr32(NVRAM_CFG1);
11181
11182 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11183 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11184 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11185 tp->nvram_jedecnum = JEDEC_ATMEL;
11186 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11187 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11188
11189 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11190 tw32(NVRAM_CFG1, nvcfg1);
11191 return;
11192 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11193 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11194 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11195 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11196 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11197 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11198 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11199 tp->nvram_jedecnum = JEDEC_ATMEL;
11200 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11201 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11202
11203 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11204 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11205 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11206 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11207 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11208 break;
11209 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11210 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11211 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11212 break;
11213 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11214 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11215 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11216 break;
11217 }
11218 break;
11219 case FLASH_5752VENDOR_ST_M45PE10:
11220 case FLASH_5752VENDOR_ST_M45PE20:
11221 case FLASH_5752VENDOR_ST_M45PE40:
11222 tp->nvram_jedecnum = JEDEC_ST;
11223 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11224 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11225
11226 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11227 case FLASH_5752VENDOR_ST_M45PE10:
11228 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11229 break;
11230 case FLASH_5752VENDOR_ST_M45PE20:
11231 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11232 break;
11233 case FLASH_5752VENDOR_ST_M45PE40:
11234 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11235 break;
11236 }
11237 break;
11238 default:
df259d8c 11239 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
321d32a0
MC		 11240 return;
11241 }
11242
a1b950d5
MC		 11243 tg3_nvram_get_pagesize(tp, nvcfg1);
11244 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
321d32a0 11245 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
a1b950d5
MC		 11246}
11247
11248
11249static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11250{
11251 u32 nvcfg1;
11252
11253 nvcfg1 = tr32(NVRAM_CFG1);
11254
11255 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11256 case FLASH_5717VENDOR_ATMEL_EEPROM:
11257 case FLASH_5717VENDOR_MICRO_EEPROM:
11258 tp->nvram_jedecnum = JEDEC_ATMEL;
11259 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11260 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11261
11262 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11263 tw32(NVRAM_CFG1, nvcfg1);
11264 return;
11265 case FLASH_5717VENDOR_ATMEL_MDB011D:
11266 case FLASH_5717VENDOR_ATMEL_ADB011B:
11267 case FLASH_5717VENDOR_ATMEL_ADB011D:
11268 case FLASH_5717VENDOR_ATMEL_MDB021D:
11269 case FLASH_5717VENDOR_ATMEL_ADB021B:
11270 case FLASH_5717VENDOR_ATMEL_ADB021D:
11271 case FLASH_5717VENDOR_ATMEL_45USPT:
11272 tp->nvram_jedecnum = JEDEC_ATMEL;
11273 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11274 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11275
11276 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11277 case FLASH_5717VENDOR_ATMEL_MDB021D:
11278 case FLASH_5717VENDOR_ATMEL_ADB021B:
11279 case FLASH_5717VENDOR_ATMEL_ADB021D:
11280 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11281 break;
11282 default:
11283 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11284 break;
11285 }
321d32a0 11286 break;
a1b950d5
MC		 11287 case FLASH_5717VENDOR_ST_M_M25PE10:
11288 case FLASH_5717VENDOR_ST_A_M25PE10:
11289 case FLASH_5717VENDOR_ST_M_M45PE10:
11290 case FLASH_5717VENDOR_ST_A_M45PE10:
11291 case FLASH_5717VENDOR_ST_M_M25PE20:
11292 case FLASH_5717VENDOR_ST_A_M25PE20:
11293 case FLASH_5717VENDOR_ST_M_M45PE20:
11294 case FLASH_5717VENDOR_ST_A_M45PE20:
11295 case FLASH_5717VENDOR_ST_25USPT:
11296 case FLASH_5717VENDOR_ST_45USPT:
11297 tp->nvram_jedecnum = JEDEC_ST;
11298 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11299 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11300
11301 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11302 case FLASH_5717VENDOR_ST_M_M25PE20:
11303 case FLASH_5717VENDOR_ST_A_M25PE20:
11304 case FLASH_5717VENDOR_ST_M_M45PE20:
11305 case FLASH_5717VENDOR_ST_A_M45PE20:
11306 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11307 break;
11308 default:
11309 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11310 break;
11311 }
321d32a0 11312 break;
a1b950d5
MC		 11313 default:
11314 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11315 return;
321d32a0 11316 }
a1b950d5
MC		 11317
11318 tg3_nvram_get_pagesize(tp, nvcfg1);
11319 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11320 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
321d32a0
MC		 11321}
11322
1da177e4
LT		 11323/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11324static void __devinit tg3_nvram_init(struct tg3 *tp)
11325{
1da177e4
LT		 11326 tw32_f(GRC_EEPROM_ADDR,
11327 (EEPROM_ADDR_FSM_RESET |
11328 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11329 EEPROM_ADDR_CLKPERD_SHIFT)));
11330
9d57f01c 11331 msleep(1);
1da177e4
LT		 11332
11333 /* Enable seeprom accesses. */
11334 tw32_f(GRC_LOCAL_CTRL,
11335 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11336 udelay(100);
11337
11338 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11339 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11340 tp->tg3_flags |= TG3_FLAG_NVRAM;
11341
ec41c7df
MC		 11342 if (tg3_nvram_lock(tp)) {
11343 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11344 "tg3_nvram_init failed.\n", tp->dev->name);
11345 return;
11346 }
e6af301b 11347 tg3_enable_nvram_access(tp);
1da177e4 11348
989a9d23
MC		 11349 tp->nvram_size = 0;
11350
361b4ac2
MC		 11351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11352 tg3_get_5752_nvram_info(tp);
d3c7b886
MC		 11353 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11354 tg3_get_5755_nvram_info(tp);
d30cdd28 11355 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
57e6983c
MC		 11356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11357 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1b27777a 11358 tg3_get_5787_nvram_info(tp);
6b91fa02
MC		 11359 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11360 tg3_get_5761_nvram_info(tp);
b5d3772c
MC		 11361 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11362 tg3_get_5906_nvram_info(tp);
321d32a0
MC		 11363 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11364 tg3_get_57780_nvram_info(tp);
a1b950d5
MC		 11365 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11366 tg3_get_5717_nvram_info(tp);
361b4ac2
MC		 11367 else
11368 tg3_get_nvram_info(tp);
11369
989a9d23
MC		 11370 if (tp->nvram_size == 0)
11371 tg3_get_nvram_size(tp);
1da177e4 11372
e6af301b 11373 tg3_disable_nvram_access(tp);
381291b7 11374 tg3_nvram_unlock(tp);
1da177e4
LT		 11375
11376 } else {
11377 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11378
11379 tg3_get_eeprom_size(tp);
11380 }
11381}
11382
1da177e4
LT		 11383static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11384 u32 offset, u32 len, u8 *buf)
11385{
11386 int i, j, rc = 0;
11387 u32 val;
11388
11389 for (i = 0; i < len; i += 4) {
b9fc7dc5 11390 u32 addr;
a9dc529d 11391 __be32 data;
1da177e4
LT		 11392
11393 addr = offset + i;
11394
11395 memcpy(&data, buf + i, 4);
11396
62cedd11
MC		 11397 /*
11398 * The SEEPROM interface expects the data to always be opposite
11399 * the native endian format. We accomplish this by reversing
11400 * all the operations that would have been performed on the
11401 * data from a call to tg3_nvram_read_be32().
11402 */
11403 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
1da177e4
LT		 11404
11405 val = tr32(GRC_EEPROM_ADDR);
11406 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11407
11408 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11409 EEPROM_ADDR_READ);
11410 tw32(GRC_EEPROM_ADDR, val |
11411 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11412 (addr & EEPROM_ADDR_ADDR_MASK) |
11413 EEPROM_ADDR_START |
11414 EEPROM_ADDR_WRITE);
6aa20a22 11415
9d57f01c 11416 for (j = 0; j < 1000; j++) {
1da177e4
LT		 11417 val = tr32(GRC_EEPROM_ADDR);
11418
11419 if (val & EEPROM_ADDR_COMPLETE)
11420 break;
9d57f01c 11421 msleep(1);
1da177e4
LT		 11422 }
11423 if (!(val & EEPROM_ADDR_COMPLETE)) {
11424 rc = -EBUSY;
11425 break;
11426 }
11427 }
11428
11429 return rc;
11430}
11431
11432/* offset and length are dword aligned */
11433static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11434 u8 *buf)
11435{
11436 int ret = 0;
11437 u32 pagesize = tp->nvram_pagesize;
11438 u32 pagemask = pagesize - 1;
11439 u32 nvram_cmd;
11440 u8 *tmp;
11441
11442 tmp = kmalloc(pagesize, GFP_KERNEL);
11443 if (tmp == NULL)
11444 return -ENOMEM;
11445
11446 while (len) {
11447 int j;
e6af301b 11448 u32 phy_addr, page_off, size;
1da177e4
LT		 11449
11450 phy_addr = offset & ~pagemask;
6aa20a22 11451
1da177e4 11452 for (j = 0; j < pagesize; j += 4) {
a9dc529d
MC		 11453 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11454 (__be32 *) (tmp + j));
11455 if (ret)
1da177e4
LT		 11456 break;
11457 }
11458 if (ret)
11459 break;
11460
11461 page_off = offset & pagemask;
11462 size = pagesize;
11463 if (len < size)
11464 size = len;
11465
11466 len -= size;
11467
11468 memcpy(tmp + page_off, buf, size);
11469
11470 offset = offset + (pagesize - page_off);
11471
e6af301b 11472 tg3_enable_nvram_access(tp);
1da177e4
LT		 11473
11474 /*
11475 * Before we can erase the flash page, we need
11476 * to issue a special "write enable" command.
11477 */
11478 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11479
11480 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11481 break;
11482
11483 /* Erase the target page */
11484 tw32(NVRAM_ADDR, phy_addr);
11485
11486 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11487 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11488
11489 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11490 break;
11491
11492 /* Issue another write enable to start the write. */
11493 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11494
11495 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11496 break;
11497
11498 for (j = 0; j < pagesize; j += 4) {
b9fc7dc5 11499 __be32 data;
1da177e4 11500
b9fc7dc5 11501 data = *((__be32 *) (tmp + j));
a9dc529d 11502
b9fc7dc5 11503 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11504
11505 tw32(NVRAM_ADDR, phy_addr + j);
11506
11507 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11508 NVRAM_CMD_WR;
11509
11510 if (j == 0)
11511 nvram_cmd |= NVRAM_CMD_FIRST;
11512 else if (j == (pagesize - 4))
11513 nvram_cmd |= NVRAM_CMD_LAST;
11514
11515 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11516 break;
11517 }
11518 if (ret)
11519 break;
11520 }
11521
11522 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11523 tg3_nvram_exec_cmd(tp, nvram_cmd);
11524
11525 kfree(tmp);
11526
11527 return ret;
11528}
11529
11530/* offset and length are dword aligned */
11531static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11532 u8 *buf)
11533{
11534 int i, ret = 0;
11535
11536 for (i = 0; i < len; i += 4, offset += 4) {
b9fc7dc5
AV		 11537 u32 page_off, phy_addr, nvram_cmd;
11538 __be32 data;
1da177e4
LT		 11539
11540 memcpy(&data, buf + i, 4);
b9fc7dc5 11541 tw32(NVRAM_WRDATA, be32_to_cpu(data));
1da177e4
LT		 11542
11543 page_off = offset % tp->nvram_pagesize;
11544
1820180b 11545 phy_addr = tg3_nvram_phys_addr(tp, offset);
1da177e4
LT		 11546
11547 tw32(NVRAM_ADDR, phy_addr);
11548
11549 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11550
11551 if ((page_off == 0) || (i == 0))
11552 nvram_cmd |= NVRAM_CMD_FIRST;
f6d9a256 11553 if (page_off == (tp->nvram_pagesize - 4))
1da177e4
LT		 11554 nvram_cmd |= NVRAM_CMD_LAST;
11555
11556 if (i == (len - 4))
11557 nvram_cmd |= NVRAM_CMD_LAST;
11558
321d32a0
MC		 11559 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11560 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
4c987487
MC		 11561 (tp->nvram_jedecnum == JEDEC_ST) &&
11562 (nvram_cmd & NVRAM_CMD_FIRST)) {
1da177e4
LT		 11563
11564 if ((ret = tg3_nvram_exec_cmd(tp,
11565 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11566 NVRAM_CMD_DONE)))
11567
11568 break;
11569 }
11570 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11571 /* We always do complete word writes to eeprom. */
11572 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11573 }
11574
11575 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11576 break;
11577 }
11578 return ret;
11579}
11580
11581/* offset and length are dword aligned */
11582static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11583{
11584 int ret;
11585
1da177e4 11586 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 11587 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11588 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 11589 udelay(40);
11590 }
11591
11592 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11593 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11594 }
11595 else {
11596 u32 grc_mode;
11597
ec41c7df
MC		 11598 ret = tg3_nvram_lock(tp);
11599 if (ret)
11600 return ret;
1da177e4 11601
e6af301b
MC		 11602 tg3_enable_nvram_access(tp);
11603 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11604 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 11605 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 11606
11607 grc_mode = tr32(GRC_MODE);
11608 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11609
11610 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11611 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11612
11613 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11614 buf);
11615 }
11616 else {
11617 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11618 buf);
11619 }
11620
11621 grc_mode = tr32(GRC_MODE);
11622 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11623
e6af301b 11624 tg3_disable_nvram_access(tp);
1da177e4
LT		 11625 tg3_nvram_unlock(tp);
11626 }
11627
11628 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 11629 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 11630 udelay(40);
11631 }
11632
11633 return ret;
11634}
11635
11636struct subsys_tbl_ent {
11637 u16 subsys_vendor, subsys_devid;
11638 u32 phy_id;
11639};
11640
11641static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11642 /* Broadcom boards. */
11643 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11644 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11645 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11646 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11647 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11648 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11649 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11650 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11651 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11652 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11653 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11654
11655 /* 3com boards. */
11656 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11657 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11658 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11659 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11660 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11661
11662 /* DELL boards. */
11663 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11664 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11665 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11666 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11667
11668 /* Compaq boards. */
11669 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11670 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11671 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11672 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11673 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11674
11675 /* IBM boards. */
11676 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11677};
11678
11679static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11680{
11681 int i;
11682
11683 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11684 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11685 tp->pdev->subsystem_vendor) &&
11686 (subsys_id_to_phy_id[i].subsys_devid ==
11687 tp->pdev->subsystem_device))
11688 return &subsys_id_to_phy_id[i];
11689 }
11690 return NULL;
11691}
11692
7d0c41ef 11693static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 11694{
1da177e4 11695 u32 val;
caf636c7
MC		 11696 u16 pmcsr;
11697
11698 /* On some early chips the SRAM cannot be accessed in D3hot state,
11699 * so need make sure we're in D0.
11700 */
11701 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11702 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11703 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11704 msleep(1);
7d0c41ef
MC		 11705
11706 /* Make sure register accesses (indirect or otherwise)
11707 * will function correctly.
11708 */
11709 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11710 tp->misc_host_ctrl);
1da177e4 11711
f49639e6
DM		 11712 /* The memory arbiter has to be enabled in order for SRAM accesses
11713 * to succeed. Normally on powerup the tg3 chip firmware will make
11714 * sure it is enabled, but other entities such as system netboot
11715 * code might disable it.
11716 */
11717 val = tr32(MEMARB_MODE);
11718 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11719
1da177e4 11720 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 11721 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11722
a85feb8c
GZ		 11723 /* Assume an onboard device and WOL capable by default. */
11724 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
72b845e0 11725
b5d3772c 11726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9d26e213 11727 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
b5d3772c 11728 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11729 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11730 }
0527ba35
MC		 11731 val = tr32(VCPU_CFGSHDW);
11732 if (val & VCPU_CFGSHDW_ASPM_DBNC)
8ed5d97e 11733 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
0527ba35 11734 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
2023276e 11735 (val & VCPU_CFGSHDW_WOL_MAGPKT))
0527ba35 11736 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
05ac4cb7 11737 goto done;
b5d3772c
MC		 11738 }
11739
1da177e4
LT		 11740 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11741 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11742 u32 nic_cfg, led_cfg;
a9daf367 11743 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 11744 int eeprom_phy_serdes = 0;
1da177e4
LT		 11745
11746 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11747 tp->nic_sram_data_cfg = nic_cfg;
11748
11749 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11750 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11751 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11752 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11753 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11754 (ver > 0) && (ver < 0x100))
11755 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11756
a9daf367
MC		 11757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11758 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11759
1da177e4
LT		 11760 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11761 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11762 eeprom_phy_serdes = 1;
11763
11764 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11765 if (nic_phy_id != 0) {
11766 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11767 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11768
11769 eeprom_phy_id = (id1 >> 16) << 10;
11770 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11771 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11772 } else
11773 eeprom_phy_id = 0;
11774
7d0c41ef 11775 tp->phy_id = eeprom_phy_id;
747e8f8b 11776 if (eeprom_phy_serdes) {
a4e2b347 11777 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
747e8f8b
MC		 11778 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11779 else
11780 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11781 }
7d0c41ef 11782
cbf46853 11783 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11784 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11785 SHASTA_EXT_LED_MODE_MASK);
cbf46853 11786 else
1da177e4
LT		 11787 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11788
11789 switch (led_cfg) {
11790 default:
11791 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11792 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11793 break;
11794
11795 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11796 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11797 break;
11798
11799 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11800 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 11801
11802 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11803 * read on some older 5700/5701 bootcode.
11804 */
11805 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11806 ASIC_REV_5700 ||
11807 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11808 ASIC_REV_5701)
11809 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11810
1da177e4
LT		 11811 break;
11812
11813 case SHASTA_EXT_LED_SHARED:
11814 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11815 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11816 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11817 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11818 LED_CTRL_MODE_PHY_2);
11819 break;
11820
11821 case SHASTA_EXT_LED_MAC:
11822 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11823 break;
11824
11825 case SHASTA_EXT_LED_COMBO:
11826 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11827 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11828 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11829 LED_CTRL_MODE_PHY_2);
11830 break;
11831
855e1111 11832 }
1da177e4
LT		 11833
11834 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11836 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11837 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11838
b2a5c19c
MC		 11839 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11840 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 11841
9d26e213 11842 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
1da177e4 11843 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11844 if ((tp->pdev->subsystem_vendor ==
11845 PCI_VENDOR_ID_ARIMA) &&
11846 (tp->pdev->subsystem_device == 0x205a ||
11847 tp->pdev->subsystem_device == 0x2063))
11848 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11849 } else {
f49639e6 11850 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9d26e213
MC		 11851 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11852 }
1da177e4
LT		 11853
11854 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11855 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 11856 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 11857 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11858 }
b2b98d4a
MC		 11859
11860 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11861 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
0d3031d9 11862 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
b2b98d4a 11863
a85feb8c
GZ		 11864 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11865 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11866 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
1da177e4 11867
12dac075 11868 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
05ac4cb7 11869 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
0527ba35
MC		 11870 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11871
1da177e4
LT		 11872 if (cfg2 & (1 << 17))
11873 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11874
11875 /* serdes signal pre-emphasis in register 0x590 set by */
11876 /* bootcode if bit 18 is set */
11877 if (cfg2 & (1 << 18))
11878 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8ed5d97e 11879
321d32a0
MC		 11880 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11881 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
6833c043
MC		 11882 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11883 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11884
8ed5d97e
MC		 11885 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11886 u32 cfg3;
11887
11888 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11889 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11890 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11891 }
a9daf367
MC		 11892
11893 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11894 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11895 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11896 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11897 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11898 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
1da177e4 11899 }
05ac4cb7
MC		 11900done:
11901 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11902 device_set_wakeup_enable(&tp->pdev->dev,
11903 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
7d0c41ef
MC		 11904}
11905
b2a5c19c
MC		 11906static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11907{
11908 int i;
11909 u32 val;
11910
11911 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11912 tw32(OTP_CTRL, cmd);
11913
11914 /* Wait for up to 1 ms for command to execute. */
11915 for (i = 0; i < 100; i++) {
11916 val = tr32(OTP_STATUS);
11917 if (val & OTP_STATUS_CMD_DONE)
11918 break;
11919 udelay(10);
11920 }
11921
11922 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11923}
11924
11925/* Read the gphy configuration from the OTP region of the chip. The gphy
11926 * configuration is a 32-bit value that straddles the alignment boundary.
11927 * We do two 32-bit reads and then shift and merge the results.
11928 */
11929static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11930{
11931 u32 bhalf_otp, thalf_otp;
11932
11933 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11934
11935 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11936 return 0;
11937
11938 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11939
11940 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11941 return 0;
11942
11943 thalf_otp = tr32(OTP_READ_DATA);
11944
11945 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11946
11947 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11948 return 0;
11949
11950 bhalf_otp = tr32(OTP_READ_DATA);
11951
11952 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11953}
11954
7d0c41ef
MC		 11955static int __devinit tg3_phy_probe(struct tg3 *tp)
11956{
11957 u32 hw_phy_id_1, hw_phy_id_2;
11958 u32 hw_phy_id, hw_phy_id_masked;
11959 int err;
1da177e4 11960
b02fd9e3
MC		 11961 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11962 return tg3_phy_init(tp);
11963
1da177e4 11964 /* Reading the PHY ID register can conflict with ASF
877d0310 11965 * firmware access to the PHY hardware.
1da177e4
LT		 11966 */
11967 err = 0;
0d3031d9
MC		 11968 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11969 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
1da177e4
LT		 11970 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11971 } else {
11972 /* Now read the physical PHY_ID from the chip and verify
11973 * that it is sane. If it doesn't look good, we fall back
11974 * to either the hard-coded table based PHY_ID and failing
11975 * that the value found in the eeprom area.
11976 */
11977 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11978 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11979
11980 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11981 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11982 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11983
11984 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11985 }
11986
11987 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11988 tp->phy_id = hw_phy_id;
11989 if (hw_phy_id_masked == PHY_ID_BCM8002)
11990 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 11991 else
11992 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 11993 } else {
7d0c41ef
MC		 11994 if (tp->phy_id != PHY_ID_INVALID) {
11995 /* Do nothing, phy ID already set up in
11996 * tg3_get_eeprom_hw_cfg().
11997 */
1da177e4
LT		 11998 } else {
11999 struct subsys_tbl_ent *p;
12000
12001 /* No eeprom signature? Try the hardcoded
12002 * subsys device table.
12003 */
12004 p = lookup_by_subsys(tp);
12005 if (!p)
12006 return -ENODEV;
12007
12008 tp->phy_id = p->phy_id;
12009 if (!tp->phy_id ||
12010 tp->phy_id == PHY_ID_BCM8002)
12011 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12012 }
12013 }
12014
747e8f8b 12015 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
0d3031d9 12016 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
1da177e4 12017 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
3600d918 12018 u32 bmsr, adv_reg, tg3_ctrl, mask;
1da177e4
LT		 12019
12020 tg3_readphy(tp, MII_BMSR, &bmsr);
12021 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12022 (bmsr & BMSR_LSTATUS))
12023 goto skip_phy_reset;
6aa20a22 12024
1da177e4
LT		 12025 err = tg3_phy_reset(tp);
12026 if (err)
12027 return err;
12028
12029 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12030 ADVERTISE_100HALF | ADVERTISE_100FULL |
12031 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12032 tg3_ctrl = 0;
12033 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12034 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12035 MII_TG3_CTRL_ADV_1000_FULL);
12036 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12037 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12038 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12039 MII_TG3_CTRL_ENABLE_AS_MASTER);
12040 }
12041
3600d918
MC		 12042 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12043 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12044 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12045 if (!tg3_copper_is_advertising_all(tp, mask)) {
1da177e4
LT		 12046 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12047
12048 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12049 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12050
12051 tg3_writephy(tp, MII_BMCR,
12052 BMCR_ANENABLE | BMCR_ANRESTART);
12053 }
12054 tg3_phy_set_wirespeed(tp);
12055
12056 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12057 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12058 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12059 }
12060
12061skip_phy_reset:
12062 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12063 err = tg3_init_5401phy_dsp(tp);
12064 if (err)
12065 return err;
12066 }
12067
12068 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12069 err = tg3_init_5401phy_dsp(tp);
12070 }
12071
747e8f8b 12072 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 12073 tp->link_config.advertising =
12074 (ADVERTISED_1000baseT_Half |
12075 ADVERTISED_1000baseT_Full |
12076 ADVERTISED_Autoneg |
12077 ADVERTISED_FIBRE);
12078 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12079 tp->link_config.advertising &=
12080 ~(ADVERTISED_1000baseT_Half |
12081 ADVERTISED_1000baseT_Full);
12082
12083 return err;
12084}
12085
12086static void __devinit tg3_read_partno(struct tg3 *tp)
12087{
6d348f2c 12088 unsigned char vpd_data[256]; /* in little-endian format */
af2c6a4a 12089 unsigned int i;
1b27777a 12090 u32 magic;
1da177e4 12091
df259d8c
MC		 12092 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12093 tg3_nvram_read(tp, 0x0, &magic))
f49639e6 12094 goto out_not_found;
1da177e4 12095
1820180b 12096 if (magic == TG3_EEPROM_MAGIC) {
1b27777a
MC		 12097 for (i = 0; i < 256; i += 4) {
12098 u32 tmp;
1da177e4 12099
6d348f2c
MC		 12100 /* The data is in little-endian format in NVRAM.
12101 * Use the big-endian read routines to preserve
12102 * the byte order as it exists in NVRAM.
12103 */
12104 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
1b27777a
MC		 12105 goto out_not_found;
12106
6d348f2c 12107 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
1b27777a
MC		 12108 }
12109 } else {
12110 int vpd_cap;
12111
12112 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12113 for (i = 0; i < 256; i += 4) {
12114 u32 tmp, j = 0;
b9fc7dc5 12115 __le32 v;
1b27777a
MC		 12116 u16 tmp16;
12117
12118 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12119 i);
12120 while (j++ < 100) {
12121 pci_read_config_word(tp->pdev, vpd_cap +
12122 PCI_VPD_ADDR, &tmp16);
12123 if (tmp16 & 0x8000)
12124 break;
12125 msleep(1);
12126 }
f49639e6
DM		 12127 if (!(tmp16 & 0x8000))
12128 goto out_not_found;
12129
1b27777a
MC		 12130 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12131 &tmp);
b9fc7dc5 12132 v = cpu_to_le32(tmp);
6d348f2c 12133 memcpy(&vpd_data[i], &v, sizeof(v));
1b27777a 12134 }
1da177e4
LT		 12135 }
12136
12137 /* Now parse and find the part number. */
af2c6a4a 12138 for (i = 0; i < 254; ) {
1da177e4 12139 unsigned char val = vpd_data[i];
af2c6a4a 12140 unsigned int block_end;
1da177e4
LT		 12141
12142 if (val == 0x82 || val == 0x91) {
12143 i = (i + 3 +
12144 (vpd_data[i + 1] +
12145 (vpd_data[i + 2] << 8)));
12146 continue;
12147 }
12148
12149 if (val != 0x90)
12150 goto out_not_found;
12151
12152 block_end = (i + 3 +
12153 (vpd_data[i + 1] +
12154 (vpd_data[i + 2] << 8)));
12155 i += 3;
af2c6a4a
MC		 12156
12157 if (block_end > 256)
12158 goto out_not_found;
12159
12160 while (i < (block_end - 2)) {
1da177e4
LT		 12161 if (vpd_data[i + 0] == 'P' &&
12162 vpd_data[i + 1] == 'N') {
12163 int partno_len = vpd_data[i + 2];
12164
af2c6a4a
MC		 12165 i += 3;
12166 if (partno_len > 24 || (partno_len + i) > 256)
1da177e4
LT		 12167 goto out_not_found;
12168
12169 memcpy(tp->board_part_number,
af2c6a4a 12170 &vpd_data[i], partno_len);
1da177e4
LT		 12171
12172 /* Success. */
12173 return;
12174 }
af2c6a4a 12175 i += 3 + vpd_data[i + 2];
1da177e4
LT		 12176 }
12177
12178 /* Part number not found. */
12179 goto out_not_found;
12180 }
12181
12182out_not_found:
b5d3772c
MC		 12183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12184 strcpy(tp->board_part_number, "BCM95906");
df259d8c
MC		 12185 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12186 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12187 strcpy(tp->board_part_number, "BCM57780");
12188 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12189 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12190 strcpy(tp->board_part_number, "BCM57760");
12191 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12192 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12193 strcpy(tp->board_part_number, "BCM57790");
5e7ccf20
MC		 12194 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12195 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12196 strcpy(tp->board_part_number, "BCM57788");
b5d3772c
MC		 12197 else
12198 strcpy(tp->board_part_number, "none");
1da177e4
LT		 12199}
12200
9c8a620e
MC		 12201static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12202{
12203 u32 val;
12204
e4f34110 12205 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 12206 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 12207 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 12208 val != 0)
12209 return 0;
12210
12211 return 1;
12212}
12213
acd9c119
MC		 12214static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12215{
ff3a7cb2 12216 u32 val, offset, start, ver_offset;
acd9c119 12217 int i;
ff3a7cb2 12218 bool newver = false;
acd9c119
MC		 12219
12220 if (tg3_nvram_read(tp, 0xc, &offset) ||
12221 tg3_nvram_read(tp, 0x4, &start))
12222 return;
12223
12224 offset = tg3_nvram_logical_addr(tp, offset);
12225
ff3a7cb2 12226 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 12227 return;
12228
ff3a7cb2
MC		 12229 if ((val & 0xfc000000) == 0x0c000000) {
12230 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 12231 return;
12232
ff3a7cb2
MC		 12233 if (val == 0)
12234 newver = true;
12235 }
12236
12237 if (newver) {
12238 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12239 return;
12240
12241 offset = offset + ver_offset - start;
12242 for (i = 0; i < 16; i += 4) {
12243 __be32 v;
12244 if (tg3_nvram_read_be32(tp, offset + i, &v))
12245 return;
12246
12247 memcpy(tp->fw_ver + i, &v, sizeof(v));
12248 }
12249 } else {
12250 u32 major, minor;
12251
12252 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12253 return;
12254
12255 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12256 TG3_NVM_BCVER_MAJSFT;
12257 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12258 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
acd9c119
MC		 12259 }
12260}
12261
a6f6cb1c
MC		 12262static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12263{
12264 u32 val, major, minor;
12265
12266 /* Use native endian representation */
12267 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12268 return;
12269
12270 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12271 TG3_NVM_HWSB_CFG1_MAJSFT;
12272 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12273 TG3_NVM_HWSB_CFG1_MINSFT;
12274
12275 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12276}
12277
dfe00d7d
MC		 12278static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12279{
12280 u32 offset, major, minor, build;
12281
12282 tp->fw_ver[0] = 's';
12283 tp->fw_ver[1] = 'b';
12284 tp->fw_ver[2] = '\0';
12285
12286 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12287 return;
12288
12289 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12290 case TG3_EEPROM_SB_REVISION_0:
12291 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12292 break;
12293 case TG3_EEPROM_SB_REVISION_2:
12294 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12295 break;
12296 case TG3_EEPROM_SB_REVISION_3:
12297 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12298 break;
12299 default:
12300 return;
12301 }
12302
e4f34110 12303 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 12304 return;
12305
12306 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12307 TG3_EEPROM_SB_EDH_BLD_SHFT;
12308 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12309 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12310 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12311
12312 if (minor > 99 || build > 26)
12313 return;
12314
12315 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12316
12317 if (build > 0) {
12318 tp->fw_ver[8] = 'a' + build - 1;
12319 tp->fw_ver[9] = '\0';
12320 }
12321}
12322
acd9c119 12323static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 12324{
12325 u32 val, offset, start;
acd9c119 12326 int i, vlen;
9c8a620e
MC		 12327
12328 for (offset = TG3_NVM_DIR_START;
12329 offset < TG3_NVM_DIR_END;
12330 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 12331 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 12332 return;
12333
9c8a620e
MC		 12334 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12335 break;
12336 }
12337
12338 if (offset == TG3_NVM_DIR_END)
12339 return;
12340
12341 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12342 start = 0x08000000;
e4f34110 12343 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 12344 return;
12345
e4f34110 12346 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 12347 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 12348 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 12349 return;
12350
12351 offset += val - start;
12352
acd9c119 12353 vlen = strlen(tp->fw_ver);
9c8a620e 12354
acd9c119
MC		 12355 tp->fw_ver[vlen++] = ',';
12356 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 12357
12358 for (i = 0; i < 4; i++) {
a9dc529d
MC		 12359 __be32 v;
12360 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 12361 return;
12362
b9fc7dc5 12363 offset += sizeof(v);
c4e6575c 12364
acd9c119
MC		 12365 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12366 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 12367 break;
c4e6575c 12368 }
9c8a620e 12369
acd9c119
MC		 12370 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12371 vlen += sizeof(v);
c4e6575c 12372 }
acd9c119
MC		 12373}
12374
7fd76445
MC		 12375static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12376{
12377 int vlen;
12378 u32 apedata;
12379
12380 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12381 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12382 return;
12383
12384 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12385 if (apedata != APE_SEG_SIG_MAGIC)
12386 return;
12387
12388 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12389 if (!(apedata & APE_FW_STATUS_READY))
12390 return;
12391
12392 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12393
12394 vlen = strlen(tp->fw_ver);
12395
12396 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12397 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12398 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12399 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12400 (apedata & APE_FW_VERSION_BLDMSK));
12401}
12402
acd9c119
MC		 12403static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12404{
12405 u32 val;
12406
df259d8c
MC		 12407 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12408 tp->fw_ver[0] = 's';
12409 tp->fw_ver[1] = 'b';
12410 tp->fw_ver[2] = '\0';
12411
12412 return;
12413 }
12414
acd9c119
MC		 12415 if (tg3_nvram_read(tp, 0, &val))
12416 return;
12417
12418 if (val == TG3_EEPROM_MAGIC)
12419 tg3_read_bc_ver(tp);
12420 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12421 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 12422 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12423 tg3_read_hwsb_ver(tp);
acd9c119
MC		 12424 else
12425 return;
12426
12427 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12428 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12429 return;
12430
12431 tg3_read_mgmtfw_ver(tp);
9c8a620e
MC		 12432
12433 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 12434}
12435
7544b097
MC		 12436static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12437
1da177e4
LT		 12438static int __devinit tg3_get_invariants(struct tg3 *tp)
12439{
12440 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 12441 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12442 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
c165b004
JL		 12443 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12444 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
399de50b
MC		 12445 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12446 PCI_DEVICE_ID_VIA_8385_0) },
1da177e4
LT		 12447 { },
12448 };
12449 u32 misc_ctrl_reg;
1da177e4
LT		 12450 u32 pci_state_reg, grc_misc_cfg;
12451 u32 val;
12452 u16 pci_cmd;
5e7dfd0f 12453 int err;
1da177e4 12454
1da177e4
LT		 12455 /* Force memory write invalidate off. If we leave it on,
12456 * then on 5700_BX chips we have to enable a workaround.
12457 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12458 * to match the cacheline size. The Broadcom driver have this
12459 * workaround but turns MWI off all the times so never uses
12460 * it. This seems to suggest that the workaround is insufficient.
12461 */
12462 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12463 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12464 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12465
12466 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12467 * has the register indirect write enable bit set before
12468 * we try to access any of the MMIO registers. It is also
12469 * critical that the PCI-X hw workaround situation is decided
12470 * before that as well.
12471 */
12472 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12473 &misc_ctrl_reg);
12474
12475 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12476 MISC_HOST_CTRL_CHIPREV_SHIFT);
795d01c5
MC		 12477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12478 u32 prod_id_asic_rev;
12479
f6eb9b1f
MC		 12480 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12481 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12482 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12483 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12484 pci_read_config_dword(tp->pdev,
12485 TG3PCI_GEN2_PRODID_ASICREV,
12486 &prod_id_asic_rev);
12487 else
12488 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12489 &prod_id_asic_rev);
12490
321d32a0 12491 tp->pci_chip_rev_id = prod_id_asic_rev;
795d01c5 12492 }
1da177e4 12493
ff645bec
MC		 12494 /* Wrong chip ID in 5752 A0. This code can be removed later
12495 * as A0 is not in production.
12496 */
12497 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12498 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12499
6892914f
MC		 12500 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12501 * we need to disable memory and use config. cycles
12502 * only to access all registers. The 5702/03 chips
12503 * can mistakenly decode the special cycles from the
12504 * ICH chipsets as memory write cycles, causing corruption
12505 * of register and memory space. Only certain ICH bridges
12506 * will drive special cycles with non-zero data during the
12507 * address phase which can fall within the 5703's address
12508 * range. This is not an ICH bug as the PCI spec allows
12509 * non-zero address during special cycles. However, only
12510 * these ICH bridges are known to drive non-zero addresses
12511 * during special cycles.
12512 *
12513 * Since special cycles do not cross PCI bridges, we only
12514 * enable this workaround if the 5703 is on the secondary
12515 * bus of these ICH bridges.
12516 */
12517 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12518 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12519 static struct tg3_dev_id {
12520 u32 vendor;
12521 u32 device;
12522 u32 rev;
12523 } ich_chipsets[] = {
12524 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12525 PCI_ANY_ID },
12526 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12527 PCI_ANY_ID },
12528 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12529 0xa },
12530 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12531 PCI_ANY_ID },
12532 { },
12533 };
12534 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12535 struct pci_dev *bridge = NULL;
12536
12537 while (pci_id->vendor != 0) {
12538 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12539 bridge);
12540 if (!bridge) {
12541 pci_id++;
12542 continue;
12543 }
12544 if (pci_id->rev != PCI_ANY_ID) {
44c10138 12545 if (bridge->revision > pci_id->rev)
6892914f
MC		 12546 continue;
12547 }
12548 if (bridge->subordinate &&
12549 (bridge->subordinate->number ==
12550 tp->pdev->bus->number)) {
12551
12552 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12553 pci_dev_put(bridge);
12554 break;
12555 }
12556 }
12557 }
12558
41588ba1
MC		 12559 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12560 static struct tg3_dev_id {
12561 u32 vendor;
12562 u32 device;
12563 } bridge_chipsets[] = {
12564 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12565 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12566 { },
12567 };
12568 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12569 struct pci_dev *bridge = NULL;
12570
12571 while (pci_id->vendor != 0) {
12572 bridge = pci_get_device(pci_id->vendor,
12573 pci_id->device,
12574 bridge);
12575 if (!bridge) {
12576 pci_id++;
12577 continue;
12578 }
12579 if (bridge->subordinate &&
12580 (bridge->subordinate->number <=
12581 tp->pdev->bus->number) &&
12582 (bridge->subordinate->subordinate >=
12583 tp->pdev->bus->number)) {
12584 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12585 pci_dev_put(bridge);
12586 break;
12587 }
12588 }
12589 }
12590
4a29cc2e
MC		 12591 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12592 * DMA addresses > 40-bit. This bridge may have other additional
12593 * 57xx devices behind it in some 4-port NIC designs for example.
12594 * Any tg3 device found behind the bridge will also need the 40-bit
12595 * DMA workaround.
12596 */
a4e2b347
MC		 12597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12598 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12599 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
4a29cc2e 12600 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
4cf78e4f 12601 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
a4e2b347 12602 }
4a29cc2e
MC		 12603 else {
12604 struct pci_dev *bridge = NULL;
12605
12606 do {
12607 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12608 PCI_DEVICE_ID_SERVERWORKS_EPB,
12609 bridge);
12610 if (bridge && bridge->subordinate &&
12611 (bridge->subordinate->number <=
12612 tp->pdev->bus->number) &&
12613 (bridge->subordinate->subordinate >=
12614 tp->pdev->bus->number)) {
12615 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12616 pci_dev_put(bridge);
12617 break;
12618 }
12619 } while (bridge);
12620 }
4cf78e4f 12621
1da177e4
LT		 12622 /* Initialize misc host control in PCI block. */
12623 tp->misc_host_ctrl |= (misc_ctrl_reg &
12624 MISC_HOST_CTRL_CHIPREV);
12625 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12626 tp->misc_host_ctrl);
12627
f6eb9b1f
MC		 12628 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12629 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7544b097
MC		 12631 tp->pdev_peer = tg3_find_peer(tp);
12632
321d32a0
MC		 12633 /* Intentionally exclude ASIC_REV_5906 */
12634 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d9ab5ad1 12635 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
d30cdd28 12636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9936bcf6 12637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
57e6983c 12638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12639 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
321d32a0
MC		 12641 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12642
12643 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12644 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
b5d3772c 12645 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
321d32a0 12646 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
a4e2b347 12647 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6708e5cc
JL		 12648 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12649
1b440c56
JL		 12650 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12651 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12652 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12653
027455ad
MC		 12654 /* 5700 B0 chips do not support checksumming correctly due
12655 * to hardware bugs.
12656 */
12657 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12658 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12659 else {
12660 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12661 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12662 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12663 tp->dev->features |= NETIF_F_IPV6_CSUM;
12664 }
12665
5a6f3074 12666 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7544b097
MC		 12667 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12668 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12669 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12670 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12671 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12672 tp->pdev_peer == tp->pdev))
12673 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12674
321d32a0 12675 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
b5d3772c 12676 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5a6f3074 12677 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
fcfa0a32 12678 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
52c0fd83 12679 } else {
7f62ad5d 12680 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
52c0fd83
MC		 12681 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12682 ASIC_REV_5750 &&
12683 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
7f62ad5d 12684 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
52c0fd83 12685 }
5a6f3074 12686 }
1da177e4 12687
4f125f42
MC		 12688 tp->irq_max = 1;
12689
f6eb9b1f
MC		 12690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12691 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12692 tp->irq_max = TG3_IRQ_MAX_VECS;
12693 }
0e1406dd
MC		 12694
12695 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
92c6b8d1
MC		 12696 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12697 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12698 else {
12699 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12700 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12701 }
0e1406dd 12702 }
f6eb9b1f 12703
f51f3562 12704 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
f6eb9b1f
MC		 12705 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12706 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8f666b07 12707 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
0f893dc6 12708
52f4490c
MC		 12709 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12710 &pci_state_reg);
12711
5e7dfd0f
MC		 12712 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12713 if (tp->pcie_cap != 0) {
12714 u16 lnkctl;
12715
1da177e4 12716 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
5f5c51e3
MC		 12717
12718 pcie_set_readrq(tp->pdev, 4096);
12719
5e7dfd0f
MC		 12720 pci_read_config_word(tp->pdev,
12721 tp->pcie_cap + PCI_EXP_LNKCTL,
12722 &lnkctl);
12723 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12724 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
c7835a77 12725 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
5e7dfd0f 12726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
321d32a0 12727 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9cf74ebb
MC		 12728 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12729 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
5e7dfd0f 12730 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
c7835a77 12731 }
52f4490c 12732 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
fcb389df 12733 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
52f4490c
MC		 12734 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12735 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12736 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12737 if (!tp->pcix_cap) {
12738 printk(KERN_ERR PFX "Cannot find PCI-X "
12739 "capability, aborting.\n");
12740 return -EIO;
12741 }
12742
12743 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12744 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12745 }
1da177e4 12746
399de50b
MC		 12747 /* If we have an AMD 762 or VIA K8T800 chipset, write
12748 * reordering to the mailbox registers done by the host
12749 * controller can cause major troubles. We read back from
12750 * every mailbox register write to force the writes to be
12751 * posted to the chip in order.
12752 */
12753 if (pci_dev_present(write_reorder_chipsets) &&
12754 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12755 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12756
69fc4053
MC		 12757 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12758 &tp->pci_cacheline_sz);
12759 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12760 &tp->pci_lat_timer);
1da177e4
LT		 12761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12762 tp->pci_lat_timer < 64) {
12763 tp->pci_lat_timer = 64;
69fc4053
MC		 12764 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12765 tp->pci_lat_timer);
1da177e4
LT		 12766 }
12767
52f4490c
MC		 12768 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12769 /* 5700 BX chips need to have their TX producer index
12770 * mailboxes written twice to workaround a bug.
12771 */
12772 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
1da177e4 12773
52f4490c 12774 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 12775 *
12776 * The workaround is to use indirect register accesses
12777 * for all chip writes not to mailbox registers.
12778 */
52f4490c 12779 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
1da177e4 12780 u32 pm_reg;
1da177e4
LT		 12781
12782 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12783
12784 /* The chip can have it's power management PCI config
12785 * space registers clobbered due to this bug.
12786 * So explicitly force the chip into D0 here.
12787 */
9974a356
MC		 12788 pci_read_config_dword(tp->pdev,
12789 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12790 &pm_reg);
12791 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12792 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 12793 pci_write_config_dword(tp->pdev,
12794 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 12795 pm_reg);
12796
12797 /* Also, force SERR#/PERR# in PCI command. */
12798 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12799 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12800 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12801 }
12802 }
12803
1da177e4
LT		 12804 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12805 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12806 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12807 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12808
12809 /* Chip-specific fixup from Broadcom driver */
12810 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12811 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12812 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12813 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12814 }
12815
1ee582d8 12816 /* Default fast path register access methods */
20094930 12817 tp->read32 = tg3_read32;
1ee582d8 12818 tp->write32 = tg3_write32;
09ee929c 12819 tp->read32_mbox = tg3_read32;
20094930 12820 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 12821 tp->write32_tx_mbox = tg3_write32;
12822 tp->write32_rx_mbox = tg3_write32;
12823
12824 /* Various workaround register access methods */
12825 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12826 tp->write32 = tg3_write_indirect_reg32;
98efd8a6
MC		 12827 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12828 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12829 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12830 /*
12831 * Back to back register writes can cause problems on these
12832 * chips, the workaround is to read back all reg writes
12833 * except those to mailbox regs.
12834 *
12835 * See tg3_write_indirect_reg32().
12836 */
1ee582d8 12837 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 12838 }
12839
1ee582d8
MC		 12840 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12841 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12842 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12843 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12844 tp->write32_rx_mbox = tg3_write_flush_reg32;
12845 }
20094930 12846
6892914f
MC		 12847 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12848 tp->read32 = tg3_read_indirect_reg32;
12849 tp->write32 = tg3_write_indirect_reg32;
12850 tp->read32_mbox = tg3_read_indirect_mbox;
12851 tp->write32_mbox = tg3_write_indirect_mbox;
12852 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12853 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12854
12855 iounmap(tp->regs);
22abe310 12856 tp->regs = NULL;
6892914f
MC		 12857
12858 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12859 pci_cmd &= ~PCI_COMMAND_MEMORY;
12860 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12861 }
b5d3772c
MC		 12862 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12863 tp->read32_mbox = tg3_read32_mbox_5906;
12864 tp->write32_mbox = tg3_write32_mbox_5906;
12865 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12866 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12867 }
6892914f 12868
bbadf503
MC		 12869 if (tp->write32 == tg3_write_indirect_reg32 ||
12870 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12871 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
f49639e6 12872 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
bbadf503
MC		 12873 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12874
7d0c41ef 12875 /* Get eeprom hw config before calling tg3_set_power_state().
9d26e213 12876 * In particular, the TG3_FLG2_IS_NIC flag must be
7d0c41ef
MC		 12877 * determined before calling tg3_set_power_state() so that
12878 * we know whether or not to switch out of Vaux power.
12879 * When the flag is set, it means that GPIO1 is used for eeprom
12880 * write protect and also implies that it is a LOM where GPIOs
12881 * are not used to switch power.
6aa20a22 12882 */
7d0c41ef
MC		 12883 tg3_get_eeprom_hw_cfg(tp);
12884
0d3031d9
MC		 12885 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12886 /* Allow reads and writes to the
12887 * APE register and memory space.
12888 */
12889 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12890 PCISTATE_ALLOW_APE_SHMEM_WR;
12891 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12892 pci_state_reg);
12893 }
12894
9936bcf6 12895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
57e6983c 12896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
321d32a0 12897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 12898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
d30cdd28
MC		 12900 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12901
314fba34
MC		 12902 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12903 * GPIO1 driven high will bring 5700's external PHY out of reset.
12904 * It is also used as eeprom write protect on LOMs.
12905 */
12906 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12907 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12908 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12909 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12910 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 12911 /* Unused GPIO3 must be driven as output on 5752 because there
12912 * are no pull-up resistors on unused GPIO pins.
12913 */
12914 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12915 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 12916
321d32a0
MC		 12917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12918 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
af36e6b6
MC		 12919 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12920
8d519ab2
MC		 12921 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12922 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 12923 /* Turn off the debug UART. */
12924 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12925 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12926 /* Keep VMain power. */
12927 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12928 GRC_LCLCTRL_GPIO_OUTPUT0;
12929 }
12930
1da177e4 12931 /* Force the chip into D0. */
bc1c7567 12932 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 12933 if (err) {
12934 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12935 pci_name(tp->pdev));
12936 return err;
12937 }
12938
1da177e4
LT		 12939 /* Derive initial jumbo mode from MTU assigned in
12940 * ether_setup() via the alloc_etherdev() call
12941 */
0f893dc6 12942 if (tp->dev->mtu > ETH_DATA_LEN &&
a4e2b347 12943 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
0f893dc6 12944 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 12945
12946 /* Determine WakeOnLan speed to use. */
12947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12948 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12949 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12950 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12951 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12952 } else {
12953 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12954 }
12955
7f97a4bd
MC		 12956 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12957 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12958
1da177e4
LT		 12959 /* A few boards don't want Ethernet@WireSpeed phy feature */
12960 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12961 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12962 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b 12963 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
7f97a4bd 12964 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
747e8f8b 12965 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 12966 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12967
12968 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12969 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12970 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12971 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12972 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12973
321d32a0 12974 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7f97a4bd 12975 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
321d32a0 12976 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
f6eb9b1f
MC		 12977 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12978 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
c424cb24 12979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
d30cdd28 12980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9936bcf6
MC		 12981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12982 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
d4011ada
MC		 12983 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12984 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12985 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
c1d2a196
MC		 12986 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12987 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
321d32a0 12988 } else
c424cb24
MC		 12989 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12990 }
1da177e4 12991
b2a5c19c
MC		 12992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12993 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12994 tp->phy_otp = tg3_read_otp_phycfg(tp);
12995 if (tp->phy_otp == 0)
12996 tp->phy_otp = TG3_OTP_DEFAULT;
12997 }
12998
f51f3562 12999 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
8ef21428
MC		 13000 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13001 else
13002 tp->mi_mode = MAC_MI_MODE_BASE;
13003
1da177e4 13004 tp->coalesce_mode = 0;
1da177e4
LT		 13005 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13006 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13007 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13008
321d32a0
MC		 13009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
57e6983c
MC		 13011 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13012
158d7abd
MC		 13013 err = tg3_mdio_init(tp);
13014 if (err)
13015 return err;
1da177e4
LT		 13016
13017 /* Initialize data/descriptor byte/word swapping. */
13018 val = tr32(GRC_MODE);
13019 val &= GRC_MODE_HOST_STACKUP;
13020 tw32(GRC_MODE, val | tp->grc_mode);
13021
13022 tg3_switch_clocks(tp);
13023
13024 /* Clear this out for sanity. */
13025 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13026
13027 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13028 &pci_state_reg);
13029 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13030 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13031 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13032
13033 if (chiprevid == CHIPREV_ID_5701_A0 ||
13034 chiprevid == CHIPREV_ID_5701_B0 ||
13035 chiprevid == CHIPREV_ID_5701_B2 ||
13036 chiprevid == CHIPREV_ID_5701_B5) {
13037 void __iomem *sram_base;
13038
13039 /* Write some dummy words into the SRAM status block
13040 * area, see if it reads back correctly. If the return
13041 * value is bad, force enable the PCIX workaround.
13042 */
13043 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13044
13045 writel(0x00000000, sram_base);
13046 writel(0x00000000, sram_base + 4);
13047 writel(0xffffffff, sram_base + 4);
13048 if (readl(sram_base) != 0x00000000)
13049 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13050 }
13051 }
13052
13053 udelay(50);
13054 tg3_nvram_init(tp);
13055
13056 grc_misc_cfg = tr32(GRC_MISC_CFG);
13057 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13058
1da177e4
LT		 13059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13060 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13061 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13062 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13063
fac9b83e
DM		 13064 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13065 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13066 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13067 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13068 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13069 HOSTCC_MODE_CLRTICK_TXBD);
13070
13071 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13072 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13073 tp->misc_host_ctrl);
13074 }
13075
3bda1258
MC		 13076 /* Preserve the APE MAC_MODE bits */
13077 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13078 tp->mac_mode = tr32(MAC_MODE) |
13079 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13080 else
13081 tp->mac_mode = TG3_DEF_MAC_MODE;
13082
1da177e4
LT		 13083 /* these are limited to 10/100 only */
13084 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13085 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13086 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13087 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13088 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13089 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13090 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13091 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13092 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
676917d4
MC		 13093 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13094 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
321d32a0 13095 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
7f97a4bd 13096 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
1da177e4
LT		 13097 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13098
13099 err = tg3_phy_probe(tp);
13100 if (err) {
13101 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13102 pci_name(tp->pdev), err);
13103 /* ... but do not return immediately ... */
b02fd9e3 13104 tg3_mdio_fini(tp);
1da177e4
LT		 13105 }
13106
13107 tg3_read_partno(tp);
c4e6575c 13108 tg3_read_fw_ver(tp);
1da177e4
LT		 13109
13110 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13111 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13112 } else {
13113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13114 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13115 else
13116 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13117 }
13118
13119 /* 5700 {AX,BX} chips have a broken status block link
13120 * change bit implementation, so we must use the
13121 * status register in those cases.
13122 */
13123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13124 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13125 else
13126 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13127
13128 /* The led_ctrl is set during tg3_phy_probe, here we might
13129 * have to force the link status polling mechanism based
13130 * upon subsystem IDs.
13131 */
13132 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
007a880d 13133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
1da177e4
LT		 13134 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13135 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13136 TG3_FLAG_USE_LINKCHG_REG);
13137 }
13138
13139 /* For all SERDES we poll the MAC status register. */
13140 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13141 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13142 else
13143 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13144
ad829268 13145 tp->rx_offset = NET_IP_ALIGN;
1da177e4
LT		 13146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13147 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13148 tp->rx_offset = 0;
13149
f92905de
MC		 13150 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13151
13152 /* Increment the rx prod index on the rx std ring by at most
13153 * 8 for these chips to workaround hw errata.
13154 */
13155 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13156 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13158 tp->rx_std_max_post = 8;
13159
8ed5d97e
MC		 13160 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13161 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13162 PCIE_PWR_MGMT_L1_THRESH_MSK;
13163
1da177e4
LT		 13164 return err;
13165}
13166
49b6e95f 13167#ifdef CONFIG_SPARC
1da177e4
LT		 13168static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13169{
13170 struct net_device *dev = tp->dev;
13171 struct pci_dev *pdev = tp->pdev;
49b6e95f 13172 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 13173 const unsigned char *addr;
49b6e95f
DM		 13174 int len;
13175
13176 addr = of_get_property(dp, "local-mac-address", &len);
13177 if (addr && len == 6) {
13178 memcpy(dev->dev_addr, addr, 6);
13179 memcpy(dev->perm_addr, dev->dev_addr, 6);
13180 return 0;
1da177e4
LT		 13181 }
13182 return -ENODEV;
13183}
13184
13185static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13186{
13187 struct net_device *dev = tp->dev;
13188
13189 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2ff43697 13190 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 13191 return 0;
13192}
13193#endif
13194
13195static int __devinit tg3_get_device_address(struct tg3 *tp)
13196{
13197 struct net_device *dev = tp->dev;
13198 u32 hi, lo, mac_offset;
008652b3 13199 int addr_ok = 0;
1da177e4 13200
49b6e95f 13201#ifdef CONFIG_SPARC
1da177e4
LT		 13202 if (!tg3_get_macaddr_sparc(tp))
13203 return 0;
13204#endif
13205
13206 mac_offset = 0x7c;
f49639e6 13207 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
a4e2b347 13208 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
1da177e4
LT		 13209 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13210 mac_offset = 0xcc;
13211 if (tg3_nvram_lock(tp))
13212 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13213 else
13214 tg3_nvram_unlock(tp);
a1b950d5
MC		 13215 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13216 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13217 mac_offset = 0xcc;
13218 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
b5d3772c 13219 mac_offset = 0x10;
1da177e4
LT		 13220
13221 /* First try to get it from MAC address mailbox. */
13222 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13223 if ((hi >> 16) == 0x484b) {
13224 dev->dev_addr[0] = (hi >> 8) & 0xff;
13225 dev->dev_addr[1] = (hi >> 0) & 0xff;
13226
13227 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13228 dev->dev_addr[2] = (lo >> 24) & 0xff;
13229 dev->dev_addr[3] = (lo >> 16) & 0xff;
13230 dev->dev_addr[4] = (lo >> 8) & 0xff;
13231 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 13232
008652b3
MC		 13233 /* Some old bootcode may report a 0 MAC address in SRAM */
13234 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13235 }
13236 if (!addr_ok) {
13237 /* Next, try NVRAM. */
df259d8c
MC		 13238 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13239 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 13240 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 13241 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13242 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 13243 }
13244 /* Finally just fetch it out of the MAC control regs. */
13245 else {
13246 hi = tr32(MAC_ADDR_0_HIGH);
13247 lo = tr32(MAC_ADDR_0_LOW);
13248
13249 dev->dev_addr[5] = lo & 0xff;
13250 dev->dev_addr[4] = (lo >> 8) & 0xff;
13251 dev->dev_addr[3] = (lo >> 16) & 0xff;
13252 dev->dev_addr[2] = (lo >> 24) & 0xff;
13253 dev->dev_addr[1] = hi & 0xff;
13254 dev->dev_addr[0] = (hi >> 8) & 0xff;
13255 }
1da177e4
LT		 13256 }
13257
13258 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 13259#ifdef CONFIG_SPARC
1da177e4
LT		 13260 if (!tg3_get_default_macaddr_sparc(tp))
13261 return 0;
13262#endif
13263 return -EINVAL;
13264 }
2ff43697 13265 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 13266 return 0;
13267}
13268
59e6b434
DM		 13269#define BOUNDARY_SINGLE_CACHELINE 1
13270#define BOUNDARY_MULTI_CACHELINE 2
13271
13272static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13273{
13274 int cacheline_size;
13275 u8 byte;
13276 int goal;
13277
13278 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13279 if (byte == 0)
13280 cacheline_size = 1024;
13281 else
13282 cacheline_size = (int) byte * 4;
13283
13284 /* On 5703 and later chips, the boundary bits have no
13285 * effect.
13286 */
13287 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13288 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13289 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13290 goto out;
13291
13292#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13293 goal = BOUNDARY_MULTI_CACHELINE;
13294#else
13295#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13296 goal = BOUNDARY_SINGLE_CACHELINE;
13297#else
13298 goal = 0;
13299#endif
13300#endif
13301
13302 if (!goal)
13303 goto out;
13304
13305 /* PCI controllers on most RISC systems tend to disconnect
13306 * when a device tries to burst across a cache-line boundary.
13307 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13308 *
13309 * Unfortunately, for PCI-E there are only limited
13310 * write-side controls for this, and thus for reads
13311 * we will still get the disconnects. We'll also waste
13312 * these PCI cycles for both read and write for chips
13313 * other than 5700 and 5701 which do not implement the
13314 * boundary bits.
13315 */
13316 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13317 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13318 switch (cacheline_size) {
13319 case 16:
13320 case 32:
13321 case 64:
13322 case 128:
13323 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13324 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13325 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13326 } else {
13327 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13328 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13329 }
13330 break;
13331
13332 case 256:
13333 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13334 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13335 break;
13336
13337 default:
13338 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13339 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13340 break;
855e1111 13341 }
59e6b434
DM		 13342 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13343 switch (cacheline_size) {
13344 case 16:
13345 case 32:
13346 case 64:
13347 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13348 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13349 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13350 break;
13351 }
13352 /* fallthrough */
13353 case 128:
13354 default:
13355 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13356 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13357 break;
855e1111 13358 }
59e6b434
DM		 13359 } else {
13360 switch (cacheline_size) {
13361 case 16:
13362 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13363 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13364 DMA_RWCTRL_WRITE_BNDRY_16);
13365 break;
13366 }
13367 /* fallthrough */
13368 case 32:
13369 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13370 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13371 DMA_RWCTRL_WRITE_BNDRY_32);
13372 break;
13373 }
13374 /* fallthrough */
13375 case 64:
13376 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13377 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13378 DMA_RWCTRL_WRITE_BNDRY_64);
13379 break;
13380 }
13381 /* fallthrough */
13382 case 128:
13383 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13384 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13385 DMA_RWCTRL_WRITE_BNDRY_128);
13386 break;
13387 }
13388 /* fallthrough */
13389 case 256:
13390 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13391 DMA_RWCTRL_WRITE_BNDRY_256);
13392 break;
13393 case 512:
13394 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13395 DMA_RWCTRL_WRITE_BNDRY_512);
13396 break;
13397 case 1024:
13398 default:
13399 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13400 DMA_RWCTRL_WRITE_BNDRY_1024);
13401 break;
855e1111 13402 }
59e6b434
DM		 13403 }
13404
13405out:
13406 return val;
13407}
13408
1da177e4
LT		 13409static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13410{
13411 struct tg3_internal_buffer_desc test_desc;
13412 u32 sram_dma_descs;
13413 int i, ret;
13414
13415 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13416
13417 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13418 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13419 tw32(RDMAC_STATUS, 0);
13420 tw32(WDMAC_STATUS, 0);
13421
13422 tw32(BUFMGR_MODE, 0);
13423 tw32(FTQ_RESET, 0);
13424
13425 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13426 test_desc.addr_lo = buf_dma & 0xffffffff;
13427 test_desc.nic_mbuf = 0x00002100;
13428 test_desc.len = size;
13429
13430 /*
13431 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13432 * the *second* time the tg3 driver was getting loaded after an
13433 * initial scan.
13434 *
13435 * Broadcom tells me:
13436 * ...the DMA engine is connected to the GRC block and a DMA
13437 * reset may affect the GRC block in some unpredictable way...
13438 * The behavior of resets to individual blocks has not been tested.
13439 *
13440 * Broadcom noted the GRC reset will also reset all sub-components.
13441 */
13442 if (to_device) {
13443 test_desc.cqid_sqid = (13 << 8) | 2;
13444
13445 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13446 udelay(40);
13447 } else {
13448 test_desc.cqid_sqid = (16 << 8) | 7;
13449
13450 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13451 udelay(40);
13452 }
13453 test_desc.flags = 0x00000005;
13454
13455 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13456 u32 val;
13457
13458 val = *(((u32 *)&test_desc) + i);
13459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13460 sram_dma_descs + (i * sizeof(u32)));
13461 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13462 }
13463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13464
13465 if (to_device) {
13466 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13467 } else {
13468 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13469 }
13470
13471 ret = -ENODEV;
13472 for (i = 0; i < 40; i++) {
13473 u32 val;
13474
13475 if (to_device)
13476 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13477 else
13478 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13479 if ((val & 0xffff) == sram_dma_descs) {
13480 ret = 0;
13481 break;
13482 }
13483
13484 udelay(100);
13485 }
13486
13487 return ret;
13488}
13489
ded7340d 13490#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 13491
13492static int __devinit tg3_test_dma(struct tg3 *tp)
13493{
13494 dma_addr_t buf_dma;
59e6b434 13495 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 13496 int ret;
13497
13498 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13499 if (!buf) {
13500 ret = -ENOMEM;
13501 goto out_nofree;
13502 }
13503
13504 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13505 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13506
59e6b434 13507 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 13508
13509 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13510 /* DMA read watermark not used on PCIE */
13511 tp->dma_rwctrl |= 0x00180000;
13512 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 13513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13514 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 13515 tp->dma_rwctrl |= 0x003f0000;
13516 else
13517 tp->dma_rwctrl |= 0x003f000f;
13518 } else {
13519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13521 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 13522 u32 read_water = 0x7;
1da177e4 13523
4a29cc2e
MC		 13524 /* If the 5704 is behind the EPB bridge, we can
13525 * do the less restrictive ONE_DMA workaround for
13526 * better performance.
13527 */
13528 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13529 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13530 tp->dma_rwctrl |= 0x8000;
13531 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 13532 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13533
49afdeb6
MC		 13534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13535 read_water = 4;
59e6b434 13536 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 13537 tp->dma_rwctrl |=
13538 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13539 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13540 (1 << 23);
4cf78e4f
MC		 13541 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13542 /* 5780 always in PCIX mode */
13543 tp->dma_rwctrl |= 0x00144000;
a4e2b347
MC		 13544 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13545 /* 5714 always in PCIX mode */
13546 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 13547 } else {
13548 tp->dma_rwctrl |= 0x001b000f;
13549 }
13550 }
13551
13552 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13553 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13554 tp->dma_rwctrl &= 0xfffffff0;
13555
13556 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13557 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13558 /* Remove this if it causes problems for some boards. */
13559 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13560
13561 /* On 5700/5701 chips, we need to set this bit.
13562 * Otherwise the chip will issue cacheline transactions
13563 * to streamable DMA memory with not all the byte
13564 * enables turned on. This is an error on several
13565 * RISC PCI controllers, in particular sparc64.
13566 *
13567 * On 5703/5704 chips, this bit has been reassigned
13568 * a different meaning. In particular, it is used
13569 * on those chips to enable a PCI-X workaround.
13570 */
13571 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13572 }
13573
13574 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13575
13576#if 0
13577 /* Unneeded, already done by tg3_get_invariants. */
13578 tg3_switch_clocks(tp);
13579#endif
13580
13581 ret = 0;
13582 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13583 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13584 goto out;
13585
59e6b434
DM		 13586 /* It is best to perform DMA test with maximum write burst size
13587 * to expose the 5700/5701 write DMA bug.
13588 */
13589 saved_dma_rwctrl = tp->dma_rwctrl;
13590 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13591 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13592
1da177e4
LT		 13593 while (1) {
13594 u32 *p = buf, i;
13595
13596 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13597 p[i] = i;
13598
13599 /* Send the buffer to the chip. */
13600 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13601 if (ret) {
13602 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13603 break;
13604 }
13605
13606#if 0
13607 /* validate data reached card RAM correctly. */
13608 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13609 u32 val;
13610 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13611 if (le32_to_cpu(val) != p[i]) {
13612 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13613 /* ret = -ENODEV here? */
13614 }
13615 p[i] = 0;
13616 }
13617#endif
13618 /* Now read it back. */
13619 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13620 if (ret) {
13621 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13622
13623 break;
13624 }
13625
13626 /* Verify it. */
13627 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13628 if (p[i] == i)
13629 continue;
13630
59e6b434
DM		 13631 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13632 DMA_RWCTRL_WRITE_BNDRY_16) {
13633 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 13634 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13635 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13636 break;
13637 } else {
13638 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13639 ret = -ENODEV;
13640 goto out;
13641 }
13642 }
13643
13644 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13645 /* Success. */
13646 ret = 0;
13647 break;
13648 }
13649 }
59e6b434
DM		 13650 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13651 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 13652 static struct pci_device_id dma_wait_state_chipsets[] = {
13653 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13654 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13655 { },
13656 };
13657
59e6b434 13658 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 13659 * now look for chipsets that are known to expose the
13660 * DMA bug without failing the test.
59e6b434 13661 */
6d1cfbab
MC		 13662 if (pci_dev_present(dma_wait_state_chipsets)) {
13663 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13664 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13665 }
13666 else
13667 /* Safe to use the calculated DMA boundary. */
13668 tp->dma_rwctrl = saved_dma_rwctrl;
13669
59e6b434
DM		 13670 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13671 }
1da177e4
LT		 13672
13673out:
13674 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13675out_nofree:
13676 return ret;
13677}
13678
13679static void __devinit tg3_init_link_config(struct tg3 *tp)
13680{
13681 tp->link_config.advertising =
13682 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13683 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13684 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13685 ADVERTISED_Autoneg | ADVERTISED_MII);
13686 tp->link_config.speed = SPEED_INVALID;
13687 tp->link_config.duplex = DUPLEX_INVALID;
13688 tp->link_config.autoneg = AUTONEG_ENABLE;
1da177e4
LT		 13689 tp->link_config.active_speed = SPEED_INVALID;
13690 tp->link_config.active_duplex = DUPLEX_INVALID;
13691 tp->link_config.phy_is_low_power = 0;
13692 tp->link_config.orig_speed = SPEED_INVALID;
13693 tp->link_config.orig_duplex = DUPLEX_INVALID;
13694 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13695}
13696
13697static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13698{
f6eb9b1f
MC		 13699 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13700 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
fdfec172
MC		 13701 tp->bufmgr_config.mbuf_read_dma_low_water =
13702 DEFAULT_MB_RDMA_LOW_WATER_5705;
13703 tp->bufmgr_config.mbuf_mac_rx_low_water =
13704 DEFAULT_MB_MACRX_LOW_WATER_5705;
13705 tp->bufmgr_config.mbuf_high_water =
13706 DEFAULT_MB_HIGH_WATER_5705;
b5d3772c
MC		 13707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13708 tp->bufmgr_config.mbuf_mac_rx_low_water =
13709 DEFAULT_MB_MACRX_LOW_WATER_5906;
13710 tp->bufmgr_config.mbuf_high_water =
13711 DEFAULT_MB_HIGH_WATER_5906;
13712 }
fdfec172
MC		 13713
13714 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13715 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13716 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13717 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13718 tp->bufmgr_config.mbuf_high_water_jumbo =
13719 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13720 } else {
13721 tp->bufmgr_config.mbuf_read_dma_low_water =
13722 DEFAULT_MB_RDMA_LOW_WATER;
13723 tp->bufmgr_config.mbuf_mac_rx_low_water =
13724 DEFAULT_MB_MACRX_LOW_WATER;
13725 tp->bufmgr_config.mbuf_high_water =
13726 DEFAULT_MB_HIGH_WATER;
13727
13728 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13729 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13730 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13731 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13732 tp->bufmgr_config.mbuf_high_water_jumbo =
13733 DEFAULT_MB_HIGH_WATER_JUMBO;
13734 }
1da177e4
LT		 13735
13736 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13737 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13738}
13739
13740static char * __devinit tg3_phy_string(struct tg3 *tp)
13741{
13742 switch (tp->phy_id & PHY_ID_MASK) {
13743 case PHY_ID_BCM5400: return "5400";
13744 case PHY_ID_BCM5401: return "5401";
13745 case PHY_ID_BCM5411: return "5411";
13746 case PHY_ID_BCM5701: return "5701";
13747 case PHY_ID_BCM5703: return "5703";
13748 case PHY_ID_BCM5704: return "5704";
13749 case PHY_ID_BCM5705: return "5705";
13750 case PHY_ID_BCM5750: return "5750";
85e94ced 13751 case PHY_ID_BCM5752: return "5752";
a4e2b347 13752 case PHY_ID_BCM5714: return "5714";
4cf78e4f 13753 case PHY_ID_BCM5780: return "5780";
af36e6b6 13754 case PHY_ID_BCM5755: return "5755";
d9ab5ad1 13755 case PHY_ID_BCM5787: return "5787";
d30cdd28 13756 case PHY_ID_BCM5784: return "5784";
126a3368 13757 case PHY_ID_BCM5756: return "5722/5756";
b5d3772c 13758 case PHY_ID_BCM5906: return "5906";
9936bcf6 13759 case PHY_ID_BCM5761: return "5761";
c2060fe1 13760 case PHY_ID_BCM5717: return "5717";
1da177e4
LT		 13761 case PHY_ID_BCM8002: return "8002/serdes";
13762 case 0: return "serdes";
13763 default: return "unknown";
855e1111 13764 }
1da177e4
LT		 13765}
13766
f9804ddb
MC		 13767static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13768{
13769 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13770 strcpy(str, "PCI Express");
13771 return str;
13772 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13773 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13774
13775 strcpy(str, "PCIX:");
13776
13777 if ((clock_ctrl == 7) ||
13778 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13779 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13780 strcat(str, "133MHz");
13781 else if (clock_ctrl == 0)
13782 strcat(str, "33MHz");
13783 else if (clock_ctrl == 2)
13784 strcat(str, "50MHz");
13785 else if (clock_ctrl == 4)
13786 strcat(str, "66MHz");
13787 else if (clock_ctrl == 6)
13788 strcat(str, "100MHz");
f9804ddb
MC		 13789 } else {
13790 strcpy(str, "PCI:");
13791 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13792 strcat(str, "66MHz");
13793 else
13794 strcat(str, "33MHz");
13795 }
13796 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13797 strcat(str, ":32-bit");
13798 else
13799 strcat(str, ":64-bit");
13800 return str;
13801}
13802
8c2dc7e1 13803static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
1da177e4
LT		 13804{
13805 struct pci_dev *peer;
13806 unsigned int func, devnr = tp->pdev->devfn & ~7;
13807
13808 for (func = 0; func < 8; func++) {
13809 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13810 if (peer && peer != tp->pdev)
13811 break;
13812 pci_dev_put(peer);
13813 }
16fe9d74
MC		 13814 /* 5704 can be configured in single-port mode, set peer to
13815 * tp->pdev in that case.
13816 */
13817 if (!peer) {
13818 peer = tp->pdev;
13819 return peer;
13820 }
1da177e4
LT		 13821
13822 /*
13823 * We don't need to keep the refcount elevated; there's no way
13824 * to remove one half of this device without removing the other
13825 */
13826 pci_dev_put(peer);
13827
13828 return peer;
13829}
13830
15f9850d
DM		 13831static void __devinit tg3_init_coal(struct tg3 *tp)
13832{
13833 struct ethtool_coalesce *ec = &tp->coal;
13834
13835 memset(ec, 0, sizeof(*ec));
13836 ec->cmd = ETHTOOL_GCOALESCE;
13837 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13838 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13839 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13840 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13841 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13842 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13843 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13844 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13845 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13846
13847 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13848 HOSTCC_MODE_CLRTICK_TXBD)) {
13849 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13850 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13851 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13852 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13853 }
d244c892
MC		 13854
13855 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13856 ec->rx_coalesce_usecs_irq = 0;
13857 ec->tx_coalesce_usecs_irq = 0;
13858 ec->stats_block_coalesce_usecs = 0;
13859 }
15f9850d
DM		 13860}
13861
7c7d64b8
SH		 13862static const struct net_device_ops tg3_netdev_ops = {
13863 .ndo_open = tg3_open,
13864 .ndo_stop = tg3_close,
00829823
SH		 13865 .ndo_start_xmit = tg3_start_xmit,
13866 .ndo_get_stats = tg3_get_stats,
13867 .ndo_validate_addr = eth_validate_addr,
13868 .ndo_set_multicast_list = tg3_set_rx_mode,
13869 .ndo_set_mac_address = tg3_set_mac_addr,
13870 .ndo_do_ioctl = tg3_ioctl,
13871 .ndo_tx_timeout = tg3_tx_timeout,
13872 .ndo_change_mtu = tg3_change_mtu,
13873#if TG3_VLAN_TAG_USED
13874 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13875#endif
13876#ifdef CONFIG_NET_POLL_CONTROLLER
13877 .ndo_poll_controller = tg3_poll_controller,
13878#endif
13879};
13880
13881static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13882 .ndo_open = tg3_open,
13883 .ndo_stop = tg3_close,
13884 .ndo_start_xmit = tg3_start_xmit_dma_bug,
7c7d64b8
SH		 13885 .ndo_get_stats = tg3_get_stats,
13886 .ndo_validate_addr = eth_validate_addr,
13887 .ndo_set_multicast_list = tg3_set_rx_mode,
13888 .ndo_set_mac_address = tg3_set_mac_addr,
13889 .ndo_do_ioctl = tg3_ioctl,
13890 .ndo_tx_timeout = tg3_tx_timeout,
13891 .ndo_change_mtu = tg3_change_mtu,
13892#if TG3_VLAN_TAG_USED
13893 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13894#endif
13895#ifdef CONFIG_NET_POLL_CONTROLLER
13896 .ndo_poll_controller = tg3_poll_controller,
13897#endif
13898};
13899
1da177e4
LT		 13900static int __devinit tg3_init_one(struct pci_dev *pdev,
13901 const struct pci_device_id *ent)
13902{
13903 static int tg3_version_printed = 0;
1da177e4
LT		 13904 struct net_device *dev;
13905 struct tg3 *tp;
646c9edd
MC		 13906 int i, err, pm_cap;
13907 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 13908 char str[40];
72f2afb8 13909 u64 dma_mask, persist_dma_mask;
1da177e4
LT		 13910
13911 if (tg3_version_printed++ == 0)
13912 printk(KERN_INFO "%s", version);
13913
13914 err = pci_enable_device(pdev);
13915 if (err) {
13916 printk(KERN_ERR PFX "Cannot enable PCI device, "
13917 "aborting.\n");
13918 return err;
13919 }
13920
1da177e4
LT		 13921 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13922 if (err) {
13923 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13924 "aborting.\n");
13925 goto err_out_disable_pdev;
13926 }
13927
13928 pci_set_master(pdev);
13929
13930 /* Find power-management capability. */
13931 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13932 if (pm_cap == 0) {
13933 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13934 "aborting.\n");
13935 err = -EIO;
13936 goto err_out_free_res;
13937 }
13938
fe5f5787 13939 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4
LT		 13940 if (!dev) {
13941 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13942 err = -ENOMEM;
13943 goto err_out_free_res;
13944 }
13945
1da177e4
LT		 13946 SET_NETDEV_DEV(dev, &pdev->dev);
13947
1da177e4
LT		 13948#if TG3_VLAN_TAG_USED
13949 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 13950#endif
13951
13952 tp = netdev_priv(dev);
13953 tp->pdev = pdev;
13954 tp->dev = dev;
13955 tp->pm_cap = pm_cap;
1da177e4
LT		 13956 tp->rx_mode = TG3_DEF_RX_MODE;
13957 tp->tx_mode = TG3_DEF_TX_MODE;
8ef21428 13958
1da177e4
LT		 13959 if (tg3_debug > 0)
13960 tp->msg_enable = tg3_debug;
13961 else
13962 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13963
13964 /* The word/byte swap controls here control register access byte
13965 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13966 * setting below.
13967 */
13968 tp->misc_host_ctrl =
13969 MISC_HOST_CTRL_MASK_PCI_INT |
13970 MISC_HOST_CTRL_WORD_SWAP |
13971 MISC_HOST_CTRL_INDIR_ACCESS |
13972 MISC_HOST_CTRL_PCISTATE_RW;
13973
13974 /* The NONFRM (non-frame) byte/word swap controls take effect
13975 * on descriptor entries, anything which isn't packet data.
13976 *
13977 * The StrongARM chips on the board (one for tx, one for rx)
13978 * are running in big-endian mode.
13979 */
13980 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13981 GRC_MODE_WSWAP_NONFRM_DATA);
13982#ifdef __BIG_ENDIAN
13983 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13984#endif
13985 spin_lock_init(&tp->lock);
1da177e4 13986 spin_lock_init(&tp->indirect_lock);
c4028958 13987 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 13988
d5fe488a 13989 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 13990 if (!tp->regs) {
1da177e4
LT		 13991 printk(KERN_ERR PFX "Cannot map device registers, "
13992 "aborting.\n");
13993 err = -ENOMEM;
13994 goto err_out_free_dev;
13995 }
13996
13997 tg3_init_link_config(tp);
13998
1da177e4
LT		 13999 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14000 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 14001
646c9edd
MC		 14002 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14003 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14004 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14005 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14006 struct tg3_napi *tnapi = &tp->napi[i];
14007
14008 tnapi->tp = tp;
14009 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14010
14011 tnapi->int_mbox = intmbx;
14012 if (i < 4)
14013 intmbx += 0x8;
14014 else
14015 intmbx += 0x4;
14016
14017 tnapi->consmbox = rcvmbx;
14018 tnapi->prodmbox = sndmbx;
14019
14020 if (i)
14021 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14022 else
14023 tnapi->coal_now = HOSTCC_MODE_NOW;
14024
14025 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14026 break;
14027
14028 /*
14029 * If we support MSIX, we'll be using RSS. If we're using
14030 * RSS, the first vector only handles link interrupts and the
14031 * remaining vectors handle rx and tx interrupts. Reuse the
14032 * mailbox values for the next iteration. The values we setup
14033 * above are still useful for the single vectored mode.
14034 */
14035 if (!i)
14036 continue;
14037
14038 rcvmbx += 0x8;
14039
14040 if (sndmbx & 0x4)
14041 sndmbx -= 0x4;
14042 else
14043 sndmbx += 0xc;
14044 }
14045
8ef0442f 14046 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
1da177e4 14047 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 14048 dev->watchdog_timeo = TG3_TX_TIMEOUT;
1da177e4 14049 dev->irq = pdev->irq;
1da177e4
LT		 14050
14051 err = tg3_get_invariants(tp);
14052 if (err) {
14053 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14054 "aborting.\n");
14055 goto err_out_iounmap;
14056 }
14057
92c6b8d1 14058 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
00829823
SH		 14059 dev->netdev_ops = &tg3_netdev_ops;
14060 else
14061 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14062
14063
4a29cc2e
MC		 14064 /* The EPB bridge inside 5714, 5715, and 5780 and any
14065 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 14066 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14067 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14068 * do DMA address check in tg3_start_xmit().
14069 */
4a29cc2e 14070 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
284901a9 14071 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
4a29cc2e 14072 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
50cf156a 14073 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 14074#ifdef CONFIG_HIGHMEM
6a35528a 14075 dma_mask = DMA_BIT_MASK(64);
72f2afb8 14076#endif
4a29cc2e 14077 } else
6a35528a 14078 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 14079
14080 /* Configure DMA attributes. */
284901a9 14081 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 14082 err = pci_set_dma_mask(pdev, dma_mask);
14083 if (!err) {
14084 dev->features |= NETIF_F_HIGHDMA;
14085 err = pci_set_consistent_dma_mask(pdev,
14086 persist_dma_mask);
14087 if (err < 0) {
14088 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14089 "DMA for consistent allocations\n");
14090 goto err_out_iounmap;
14091 }
14092 }
14093 }
284901a9
YH		 14094 if (err || dma_mask == DMA_BIT_MASK(32)) {
14095 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8
MC		 14096 if (err) {
14097 printk(KERN_ERR PFX "No usable DMA configuration, "
14098 "aborting.\n");
14099 goto err_out_iounmap;
14100 }
14101 }
14102
fdfec172 14103 tg3_init_bufmgr_config(tp);
1da177e4 14104
077f849d 14105 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
9e9fd12d 14106 tp->fw_needed = FIRMWARE_TG3;
077f849d 14107
1da177e4
LT		 14108 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14109 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14110 }
14111 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14113 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
c7835a77 14114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
1da177e4
LT		 14115 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14116 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14117 } else {
7f62ad5d 14118 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
077f849d 14119 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
9e9fd12d 14120 tp->fw_needed = FIRMWARE_TG3TSO5;
077f849d 14121 else
9e9fd12d 14122 tp->fw_needed = FIRMWARE_TG3TSO;
077f849d 14123 }
1da177e4 14124
4e3a7aaa
MC		 14125 /* TSO is on by default on chips that support hardware TSO.
14126 * Firmware TSO on older chips gives lower performance, so it
14127 * is off by default, but can be enabled using ethtool.
14128 */
b0026624 14129 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
027455ad
MC		 14130 if (dev->features & NETIF_F_IP_CSUM)
14131 dev->features |= NETIF_F_TSO;
14132 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14133 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
b0026624 14134 dev->features |= NETIF_F_TSO6;
57e6983c
MC		 14135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14137 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
321d32a0 14138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
f6eb9b1f
MC		 14139 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9936bcf6 14141 dev->features |= NETIF_F_TSO_ECN;
b0026624 14142 }
1da177e4 14143
1da177e4
LT		 14144
14145 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14146 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14147 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14148 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14149 tp->rx_pending = 63;
14150 }
14151
1da177e4
LT		 14152 err = tg3_get_device_address(tp);
14153 if (err) {
14154 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14155 "aborting.\n");
077f849d 14156 goto err_out_fw;
1da177e4
LT		 14157 }
14158
c88864df 14159 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
63532394 14160 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
79ea13ce 14161 if (!tp->aperegs) {
c88864df
MC		 14162 printk(KERN_ERR PFX "Cannot map APE registers, "
14163 "aborting.\n");
14164 err = -ENOMEM;
077f849d 14165 goto err_out_fw;
c88864df
MC		 14166 }
14167
14168 tg3_ape_lock_init(tp);
7fd76445
MC		 14169
14170 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14171 tg3_read_dash_ver(tp);
c88864df
MC		 14172 }
14173
1da177e4
LT		 14174 /*
14175 * Reset chip in case UNDI or EFI driver did not shutdown
14176 * DMA self test will enable WDMAC and we'll see (spurious)
14177 * pending DMA on the PCI bus at that point.
14178 */
14179 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14180 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 14181 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 14182 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 14183 }
14184
14185 err = tg3_test_dma(tp);
14186 if (err) {
14187 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
c88864df 14188 goto err_out_apeunmap;
1da177e4
LT		 14189 }
14190
1da177e4
LT		 14191 /* flow control autonegotiation is default behavior */
14192 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
e18ce346 14193 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1da177e4 14194
15f9850d
DM		 14195 tg3_init_coal(tp);
14196
c49a1561
MC		 14197 pci_set_drvdata(pdev, dev);
14198
1da177e4
LT		 14199 err = register_netdev(dev);
14200 if (err) {
14201 printk(KERN_ERR PFX "Cannot register net device, "
14202 "aborting.\n");
0d3031d9 14203 goto err_out_apeunmap;
1da177e4
LT		 14204 }
14205
df59c940 14206 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
1da177e4
LT		 14207 dev->name,
14208 tp->board_part_number,
14209 tp->pci_chip_rev_id,
f9804ddb 14210 tg3_bus_string(tp, str),
e174961c 14211 dev->dev_addr);
1da177e4 14212
3f0e3ad7
MC		 14213 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14214 struct phy_device *phydev;
14215 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
df59c940
MC		 14216 printk(KERN_INFO
14217 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3f0e3ad7
MC		 14218 tp->dev->name, phydev->drv->name,
14219 dev_name(&phydev->dev));
14220 } else
df59c940
MC		 14221 printk(KERN_INFO
14222 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14223 tp->dev->name, tg3_phy_string(tp),
14224 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14225 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14226 "10/100/1000Base-T")),
14227 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14228
14229 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
1da177e4
LT		 14230 dev->name,
14231 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14232 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14233 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14234 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
1da177e4 14235 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
4a29cc2e
MC		 14236 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14237 dev->name, tp->dma_rwctrl,
284901a9 14238 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
50cf156a 14239 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
1da177e4
LT		 14240
14241 return 0;
14242
0d3031d9
MC		 14243err_out_apeunmap:
14244 if (tp->aperegs) {
14245 iounmap(tp->aperegs);
14246 tp->aperegs = NULL;
14247 }
14248
077f849d
JSR		 14249err_out_fw:
14250 if (tp->fw)
14251 release_firmware(tp->fw);
14252
1da177e4 14253err_out_iounmap:
6892914f
MC		 14254 if (tp->regs) {
14255 iounmap(tp->regs);
22abe310 14256 tp->regs = NULL;
6892914f 14257 }
1da177e4
LT		 14258
14259err_out_free_dev:
14260 free_netdev(dev);
14261
14262err_out_free_res:
14263 pci_release_regions(pdev);
14264
14265err_out_disable_pdev:
14266 pci_disable_device(pdev);
14267 pci_set_drvdata(pdev, NULL);
14268 return err;
14269}
14270
14271static void __devexit tg3_remove_one(struct pci_dev *pdev)
14272{
14273 struct net_device *dev = pci_get_drvdata(pdev);
14274
14275 if (dev) {
14276 struct tg3 *tp = netdev_priv(dev);
14277
077f849d
JSR		 14278 if (tp->fw)
14279 release_firmware(tp->fw);
14280
7faa006f 14281 flush_scheduled_work();
158d7abd 14282
b02fd9e3
MC		 14283 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14284 tg3_phy_fini(tp);
158d7abd 14285 tg3_mdio_fini(tp);
b02fd9e3 14286 }
158d7abd 14287
1da177e4 14288 unregister_netdev(dev);
0d3031d9
MC		 14289 if (tp->aperegs) {
14290 iounmap(tp->aperegs);
14291 tp->aperegs = NULL;
14292 }
6892914f
MC		 14293 if (tp->regs) {
14294 iounmap(tp->regs);
22abe310 14295 tp->regs = NULL;
6892914f 14296 }
1da177e4
LT		 14297 free_netdev(dev);
14298 pci_release_regions(pdev);
14299 pci_disable_device(pdev);
14300 pci_set_drvdata(pdev, NULL);
14301 }
14302}
14303
14304static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14305{
14306 struct net_device *dev = pci_get_drvdata(pdev);
14307 struct tg3 *tp = netdev_priv(dev);
12dac075 14308 pci_power_t target_state;
1da177e4
LT		 14309 int err;
14310
3e0c95fd
MC		 14311 /* PCI register 4 needs to be saved whether netif_running() or not.
14312 * MSI address and data need to be saved if using MSI and
14313 * netif_running().
14314 */
14315 pci_save_state(pdev);
14316
1da177e4
LT		 14317 if (!netif_running(dev))
14318 return 0;
14319
7faa006f 14320 flush_scheduled_work();
b02fd9e3 14321 tg3_phy_stop(tp);
1da177e4
LT		 14322 tg3_netif_stop(tp);
14323
14324 del_timer_sync(&tp->timer);
14325
f47c11ee 14326 tg3_full_lock(tp, 1);
1da177e4 14327 tg3_disable_ints(tp);
f47c11ee 14328 tg3_full_unlock(tp);
1da177e4
LT		 14329
14330 netif_device_detach(dev);
14331
f47c11ee 14332 tg3_full_lock(tp, 0);
944d980e 14333 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6a9eba15 14334 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
f47c11ee 14335 tg3_full_unlock(tp);
1da177e4 14336
12dac075
RW		 14337 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14338
14339 err = tg3_set_power_state(tp, target_state);
1da177e4 14340 if (err) {
b02fd9e3
MC		 14341 int err2;
14342
f47c11ee 14343 tg3_full_lock(tp, 0);
1da177e4 14344
6a9eba15 14345 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b02fd9e3
MC		 14346 err2 = tg3_restart_hw(tp, 1);
14347 if (err2)
b9ec6c1b 14348 goto out;
1da177e4
LT		 14349
14350 tp->timer.expires = jiffies + tp->timer_offset;
14351 add_timer(&tp->timer);
14352
14353 netif_device_attach(dev);
14354 tg3_netif_start(tp);
14355
b9ec6c1b 14356out:
f47c11ee 14357 tg3_full_unlock(tp);
b02fd9e3
MC		 14358
14359 if (!err2)
14360 tg3_phy_start(tp);
1da177e4
LT		 14361 }
14362
14363 return err;
14364}
14365
14366static int tg3_resume(struct pci_dev *pdev)
14367{
14368 struct net_device *dev = pci_get_drvdata(pdev);
14369 struct tg3 *tp = netdev_priv(dev);
14370 int err;
14371
3e0c95fd
MC		 14372 pci_restore_state(tp->pdev);
14373
1da177e4
LT		 14374 if (!netif_running(dev))
14375 return 0;
14376
bc1c7567 14377 err = tg3_set_power_state(tp, PCI_D0);
1da177e4
LT		 14378 if (err)
14379 return err;
14380
14381 netif_device_attach(dev);
14382
f47c11ee 14383 tg3_full_lock(tp, 0);
1da177e4 14384
6a9eba15 14385 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
b9ec6c1b
MC		 14386 err = tg3_restart_hw(tp, 1);
14387 if (err)
14388 goto out;
1da177e4
LT		 14389
14390 tp->timer.expires = jiffies + tp->timer_offset;
14391 add_timer(&tp->timer);
14392
1da177e4
LT		 14393 tg3_netif_start(tp);
14394
b9ec6c1b 14395out:
f47c11ee 14396 tg3_full_unlock(tp);
1da177e4 14397
b02fd9e3
MC		 14398 if (!err)
14399 tg3_phy_start(tp);
14400
b9ec6c1b 14401 return err;
1da177e4
LT		 14402}
14403
14404static struct pci_driver tg3_driver = {
14405 .name = DRV_MODULE_NAME,
14406 .id_table = tg3_pci_tbl,
14407 .probe = tg3_init_one,
14408 .remove = __devexit_p(tg3_remove_one),
14409 .suspend = tg3_suspend,
14410 .resume = tg3_resume
14411};
14412
14413static int __init tg3_init(void)
14414{
29917620 14415 return pci_register_driver(&tg3_driver);
1da177e4
LT		 14416}
14417
14418static void __exit tg3_cleanup(void)
14419{
14420 pci_unregister_driver(&tg3_driver);
14421}
14422
14423module_init(tg3_init);
14424module_exit(tg3_cleanup);
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